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/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_vdiv(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output reg pipe_ack_o,
input signed [17:0] ax,
input signed [17:0] ay,
input signed [17:0] bx,
input signed [17:0] by,
input diff_cx_positive,
input [16:0] diff_cx,
input diff_cy_positive,
input [16:0] diff_cy,
input diff_dx_positive,
input [16:0] diff_dx,
input diff_dy_positive,
input [16:0] diff_dy,
input signed [11:0] drx,
input signed [11:0] dry,
input [10:0] dst_squareh,
output reg pipe_stb_o,
input pipe_ack_i,
output reg signed [17:0] ax_f,
output reg signed [17:0] ay_f,
output reg signed [17:0] bx_f,
output reg signed [17:0] by_f,
output reg diff_cx_positive_f,
output [16:0] diff_cx_q,
output [16:0] diff_cx_r,
output reg diff_cy_positive_f,
output [16:0] diff_cy_q,
output [16:0] diff_cy_r,
output reg diff_dx_positive_f,
output [16:0] diff_dx_q,
output [16:0] diff_dx_r,
output reg diff_dy_positive_f,
output [16:0] diff_dy_q,
output [16:0] diff_dy_r,
output reg signed [11:0] drx_f,
output reg signed [11:0] dry_f
);
/* Divider bank */
reg start;
wire ready;
tmu2_divider17 d_cx(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_cx),
.divisor({6'd0, dst_squareh}),
.ready(ready),
.quotient(diff_cx_q),
.remainder(diff_cx_r)
);
tmu2_divider17 d_cy(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_cy),
.divisor({6'd0, dst_squareh}),
.ready(),
.quotient(diff_cy_q),
.remainder(diff_cy_r)
);
tmu2_divider17 d_dx(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_dx),
.divisor({6'd0, dst_squareh}),
.ready(),
.quotient(diff_dx_q),
.remainder(diff_dx_r)
);
tmu2_divider17 d_dy(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_dy),
.divisor({6'd0, dst_squareh}),
.ready(),
.quotient(diff_dy_q),
.remainder(diff_dy_r)
);
/* Forward */
always @(posedge sys_clk) begin
if(start) begin
ax_f <= ax;
ay_f <= ay;
bx_f <= bx;
by_f <= by;
diff_cx_positive_f <= diff_cx_positive;
diff_cy_positive_f <= diff_cy_positive;
diff_dx_positive_f <= diff_dx_positive;
diff_dy_positive_f <= diff_dy_positive;
drx_f <= drx;
dry_f <= dry;
end
end
/* Glue logic */
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter WAIT = 1'b1;
always @(posedge sys_clk) begin
if(sys_rst)
state = IDLE;
else
state = next_state;
end
assign busy = state;
always @(*) begin
next_state = state;
start = 1'b0;
pipe_stb_o = 1'b0;
pipe_ack_o = 1'b0;
case(state)
IDLE: begin
pipe_ack_o = 1'b1;
if(pipe_stb_i) begin
start = 1'b1;
next_state = WAIT;
end
end
WAIT: begin
if(ready) begin
pipe_stb_o = 1'b1;
if(pipe_ack_i)
next_state = IDLE;
end
end
endcase
end
endmodule
|
/*
ENGINNER: Mateusz Okulanis
PROJECT: OM_FIREWALL
MODULE: eth_mac_l2_testbench
SCENARIO:
1. PREAMBLE
2. SFD
*/
module eth_mac_l2_testbench();
reg Clk;
reg Rst_n;
reg Enet0_Rx_Data;
reg Enet0_Rx_Dv;
reg Enet0_Rx_Er;
wire avalonST_1_valid_wire;
wire [7:0] avalonST_1_data_wire;
wire avalonST_1_channel_wire;
wire avalonST_1_error_wire;
reg avalonST_1_ready_reg;
eth_mac_l2 eth_mac_inst(
.Clk(), // 125 MHz clock for GMII signals
.Rst_n(), // active-high sync reset
.M_ETH0_avalonST_valid(avalonST_1_valid_wire),
.M_ETH0_avalonST_data(avalonST_1_data_wire),
.M_ETH0_avalonST_channel(avalonST_1_channel_wire),
.M_ETH0_avalonST_error(avalonST_1_error_wire),
.M_ETH0_avalonST_ready(avalonST_1_ready_reg),
.S_ETH0_avalonST_valid(),
.S_ETH0_avalonST_data(),
.S_ETH0_avalonST_channel(),
.S_ETH0_avalonST_error(),
.S_ETH0_avalonST_ready(),
.M_ETH1_avalonST_valid(),
.M_ETH1_avalonST_data(),
.M_ETH1_avalonST_channel(),
.M_ETH1_avalonST_error(),
.M_ETH1_avalonST_ready(),
.S_ETH1_avalonST_valid(),
.S_ETH1_avalonST_data(),
.S_ETH1_avalonST_channel(),
.S_ETH1_avalonST_error(),
.S_ETH1_avalonST_ready(),
.ENET0_RX_DATA(ENET0_RX_DATA),
.ENET0_RX_DV(ENET0_RX_DV),
.ENET0_RX_ER(ENET0_RX_ER),
.ENET0_TX_DATA(ENET0_TX_DATA),
.ENET0_TX_DV(ENET0_TX_DV),
.ENET0_TX_ER(ENET0_TX_ER),
.ENET1_RX_DATA(ENET1_RX_DATA),
.ENET1_RX_DV(ENET1_RX_DV),
.ENET1_RX_ER(ENET1_RX_ER),
.ENET1_TX_DATA(ENET1_TX_DATA),
.ENET1_TX_DV(ENET1_TX_DV),
.ENET1_TX_ER(ENET1_TX_ER)
);
endmodule |
`include "top.vh"
module top(
input ice_clk_i,
output [7:0] led_o,
output vs_o,
output hs_o,
output [3 : 0] red_o,
output [3 : 0] blue_o,
output [3 : 0] green_o
);
reg [31:0] ctr;
reg vs = 0, hs = 0;
reg [9 : 0] ctr_x = 0;
reg [8 : 0] ctr_y = 0;
wire clk_vga;
wire locked;
clks#(
.PLL_EN(1),
.GBUFF_EN(1),
.DIVR(4'b0000),
.DIVF(7'b1000010),
.DIVQ(3'b100)
) clks(
.clk_i(ice_clk_i),
.clk_o(clk_vga)
);
always @(posedge clk_vga)
begin
ctr <= ctr +1;
end
genvar i;
generate
for (i = 0; i<8; i = i + 1) begin
assign led_o[i] = ctr[i + 18];
end
endgenerate
// 640 x 480
wire pix_clk;
// pixel clock: 25Mhz = 40ns (clk/2)
reg pcount = 0; // used to generate pixel clock
wire en = (pcount == 0);
always @ (posedge clk_vga) pcount <= ~pcount;
assign pix_clk = en;
reg hsync = 0,vsync = 0,hblank = 0,vblank = 0;
reg [9:0] hcount = 0; // pixel number on current line
reg [9:0] vcount = 0; // line number
// horizontal: 794 pixels = 31.76us
// display 640 pixels per line
wire hsyncon,hsyncoff,hreset,hblankon;
assign hblankon = en & (hcount == 639);
assign hsyncon = en & (hcount == 652-4);
assign hsyncoff = en & (hcount == 746-4);
assign hreset = en & (hcount == 793-4);
wire blank = (vblank | (hblank & ~hreset)); // blanking => black
// vertical: 528 lines = 16.77us
// display 480 lines
wire vsyncon,vsyncoff,vreset,vblankon;
assign vblankon = hreset & (vcount == 479);
assign vsyncon = hreset & (vcount == 492-4);
assign vsyncoff = hreset & (vcount == 494-4);
assign vreset = hreset & (vcount == 527-4);
// sync and blanking
always @(posedge clk_vga) begin
hcount <= en ? (hreset ? 0 : hcount + 1) : hcount;
hblank <= hreset ? 0 : hblankon ? 1 : hblank;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // hsync is active low
vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= vreset ? 0 : vblankon ? 1 : vblank;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // vsync is active low
end
assign hs_o = hsync;
assign vs_o = vsync;
// assign red_o = hsync ? hcount[8 : 5] & vcount[4:1] : 0;
//assign blue_o = hsync ? hcount[8 : 5] & vcount[4:1]: 0;
//assign green_o = hsync ? 1 : 0;//hsync ? hcount[8: 5] & vcount[4:1] : 0;
reg [9 : 0] h_bx_ctr = 0;
reg [9 : 0] v_bx_ctr = 0;
wire draw;
wire h_bx, v_vx;
always @ (posedge pix_clk)
begin
if (draw)
begin
h_bx_ctr <= h_bx_ctr + 1;
end
else
begin
h_bx_ctr <= 0;
end
end // always @ (posedge clk)
always @ (posedge pix_clk)
begin
if (vblankon)
begin
v_bx_ctr <= v_bx_ctr + 1;
end
else if(v_bx_ctr == 479)
begin
v_bx_ctr <= 0;
end
end // always @ (posedge clk)
assign draw = (hsync & ~hblank) & (vsync & ~vblank);
assign h_bx = (h_bx_ctr > 310) & (h_bx_ctr < 330);
assign v_bx = 1;//(v_bx_ctr > 220) & (v_bx_ctr > 240);
assign red_o = draw & h_bx & v_bx ? 4'b1111 : 0;
assign blue_o = draw & h_bx & v_bx ? 4'b1111 : 0;
assign green_o = draw & h_bx & v_bx ? 4'b1111 : 0;
endmodule // top
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Detect_Change_To_One.v
// Created: 2014-09-08 14:12:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Detect_Change_To_One
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Detect Change To One
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Detect_Change_To_One
(
CLK_IN,
reset,
enb,
In1,
Out1
);
input CLK_IN;
input reset;
input enb;
input In1;
output Out1;
reg Unit_Delay_out1;
wire Unit_Delay_out1_1;
wire In1_1;
// <S6>/Unit Delay
always @(posedge CLK_IN)
begin : Unit_Delay_process
if (reset == 1'b1) begin
Unit_Delay_out1 <= 1'b0;
end
else if (enb) begin
Unit_Delay_out1 <= In1;
end
end
// <S6>/Logical Operator
assign Unit_Delay_out1_1 = ~ Unit_Delay_out1;
// <S6>/Logical Operator1
assign In1_1 = In1 & Unit_Delay_out1_1;
assign Out1 = In1_1;
endmodule // Detect_Change_To_One
|
// -----------------------------------------------------------------------------
//
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : motor_driver.v
// MODULE NAME :motor_driver
// AUTHOR : acozma
// AUTHOR'S EMAIL : [email protected]
//
// -----------------------------------------------------------------------------
`timescale 1ns / 1ps
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module motor_driver
//----------- Parameters Declarations -------------------------------------------
#(
parameter PWM_BITS = 11,
localparam PWMBW = PWM_BITS - 1
)
//----------- Ports Declarations -----------------------------------------------
(
input clk_i,
input pwm_clk_i,
input rst_n_i,
input run_i,
input star_delta_i, // 1 STAR, 0 DELTA
input dir_i, // 1 CW, 0 CCW
input [2:0] position_i,
input [PWMBW:0] pwm_duty_i,
output AH_o,
output BH_o,
output CH_o,
output AL_o,
output BL_o,
output CL_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg pwm_s;
reg [ 3:0] motor_state;
reg [15:0] align_counter;
reg [ 2:0] position_s;
reg [PWMBW:0] pwm_cnt;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
wire align_complete;
wire [PWMBW:0] pwm_duty_s;
wire [1:0] commutation_table[0:2];
wire pwm_al_s;
wire pwm_ah_s;
wire pwm_bl_s;
wire pwm_bh_s;
wire pwm_cl_s;
wire pwm_ch_s;
wire pwmd_al_s;
wire pwmd_ah_s;
wire pwmd_bl_s;
wire pwmd_bh_s;
wire pwmd_cl_s;
wire pwmd_ch_s;
//------------------------------------------------------------------------------
//----------- Local Parameters -------------------------------------------------
//------------------------------------------------------------------------------
localparam OFF = 3'b001;
localparam ALIGN = 3'b010;
localparam RUN = 3'b100;
localparam DT = 20;
localparam [PWMBW:0] ALIGN_PWM_DUTY = 2**(PWMBW) + 2**(PWMBW-3);
localparam [15:0] ALIGN_TIME = 16'h8000;
localparam [1:0] COMMUTATION_TABLE_DELTA_CW_0[0:5] = { 2'd1,-2'd1, 2'd1,-2'd1, 2'd1,-2'd1};
localparam [1:0] COMMUTATION_TABLE_DELTA_CW_1[0:5] = {-2'd1, 2'd1, 2'd1,-2'd1,-2'd1, 2'd1};
localparam [1:0] COMMUTATION_TABLE_DELTA_CW_2[0:5] = {-2'd1,-2'd1,-2'd1, 2'd1, 2'd1, 2'd1};
localparam [1:0] COMMUTATION_TABLE_DELTA_CCW_0[0:5] = {-2'd1, 2'd1,-2'd1, 2'd1,-2'd1, 2'd1};
localparam [1:0] COMMUTATION_TABLE_DELTA_CCW_1[0:5] = { 2'd1,-2'd1,-2'd1, 2'd1, 2'd1,-2'd1};
localparam [1:0] COMMUTATION_TABLE_DELTA_CCW_2[0:5] = { 2'd1, 2'd1, 2'd1,-2'd1,-2'd1,-2'd1};
localparam [1:0] COMMUTATION_TABLE_STAR_CW_0[0:5] = { 2'd1,-2'd1, 2'd0, 2'd0, 2'd1,-2'd1};
localparam [1:0] COMMUTATION_TABLE_STAR_CW_1[0:5] = { 2'd0, 2'd1, 2'd1,-2'd1,-2'd1, 2'd0};
localparam [1:0] COMMUTATION_TABLE_STAR_CW_2[0:5] = {-2'd1, 2'd0,-2'd1, 2'd1, 2'd0, 2'd1};
localparam [1:0] COMMUTATION_TABLE_STAR_CCW_0[0:5] = {-2'd1, 2'd1, 2'd0, 2'd0, -2'd1, 2'd1};
localparam [1:0] COMMUTATION_TABLE_STAR_CCW_1[0:5] = { 2'd0,-2'd1,-2'd1, 2'd1, 2'd1, 2'd0};
localparam [1:0] COMMUTATION_TABLE_STAR_CCW_2[0:5] = { 2'd1, 2'd0, 2'd1,-2'd1, 2'd0,-2'd1};
delay #(
.DELAY(DT))
delay_ah_i (
.clk_i (clk_i),
.rst_n_i (pwm_ah_s),
.sig_i (pwm_ah_s),
.sig_o (pwmd_ah_s));
delay #(
.DELAY(DT))
delay_al_i (
.clk_i (clk_i),
.rst_n_i (pwm_al_s),
.sig_i (pwm_al_s),
.sig_o (pwmd_al_s));
delay #(
.DELAY(DT))
delay_bh_i (
.clk_i (clk_i),
.rst_n_i (pwm_bh_s),
.sig_i (pwm_bh_s),
.sig_o (pwmd_bh_s));
delay #(
.DELAY(DT))
delay_bl_i (
.clk_i (clk_i),
.rst_n_i (pwm_bl_s),
.sig_i (pwm_bl_s),
.sig_o (pwmd_bl_s));
delay #(
.DELAY(DT))
delay_ch_i (
.clk_i (clk_i),
.rst_n_i (pwm_ch_s),
.sig_i (pwm_ch_s),
.sig_o (pwmd_ch_s));
delay #(
.DELAY(DT))
delay_cl_i (
.clk_i (clk_i),
.rst_n_i (pwm_cl_s),
.sig_i (pwm_cl_s),
.sig_o (pwmd_cl_s));
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign align_complete = align_counter < ALIGN_TIME ? 0 : 1;
assign pwm_duty_s = motor_state == OFF ? 0 :
motor_state == ALIGN ? ALIGN_PWM_DUTY : pwm_duty_i;
assign commutation_table[0] = star_delta_i ?
dir_i ? COMMUTATION_TABLE_STAR_CW_0[position_s] : COMMUTATION_TABLE_STAR_CCW_0[position_s] :
dir_i ? COMMUTATION_TABLE_DELTA_CW_0[position_s] : COMMUTATION_TABLE_DELTA_CCW_0[position_s];
assign commutation_table[1] = star_delta_i ?
dir_i ? COMMUTATION_TABLE_STAR_CW_1[position_s] : COMMUTATION_TABLE_STAR_CCW_1[position_s] :
dir_i ? COMMUTATION_TABLE_DELTA_CW_1[position_s] : COMMUTATION_TABLE_DELTA_CCW_1[position_s];
assign commutation_table[2] = star_delta_i ?
dir_i ? COMMUTATION_TABLE_STAR_CW_2[position_s] : COMMUTATION_TABLE_STAR_CCW_2[position_s] :
dir_i ? COMMUTATION_TABLE_DELTA_CW_2[position_s] : COMMUTATION_TABLE_DELTA_CCW_2[position_s];
//Motor Phases Control
assign pwm_ah_s = commutation_table[0] == 2'd1 ? ~pwm_s : commutation_table[0] == -2'd1 ? pwm_s : 0;
assign pwm_al_s = commutation_table[0] == 2'd1 ? pwm_s : commutation_table[0] == -2'd1 ? ~pwm_s : 0;
assign pwm_bh_s = commutation_table[1] == 2'd1 ? ~pwm_s : commutation_table[1] == -2'd1 ? pwm_s : 0;
assign pwm_bl_s = commutation_table[1] == 2'd1 ? pwm_s : commutation_table[1] == -2'd1 ? ~pwm_s : 0;
assign pwm_ch_s = commutation_table[2] == 2'd1 ? ~pwm_s : commutation_table[2] == -2'd1 ? pwm_s : 0;
assign pwm_cl_s = commutation_table[2] == 2'd1 ? pwm_s : commutation_table[2] == -2'd1 ? ~pwm_s : 0;
assign AL_o = pwmd_ah_s? 0 : pwmd_al_s;
assign AH_o = pwmd_ah_s;
assign BL_o = pwmd_bh_s ? 0 : pwmd_bl_s;
assign BH_o = pwmd_bh_s;
assign CL_o = pwmd_ch_s ? 0 : pwmd_cl_s;
assign CH_o = pwmd_ch_s;
//Control the current motor state
always @(posedge clk_i)
begin
if(rst_n_i == 1'b0)
begin
motor_state <= OFF;
align_counter <= 0;
end
else
begin
case(motor_state)
OFF:
begin
position_s <= 0;
motor_state <= (run_i == 1'b1 ? ALIGN : OFF);
end
ALIGN:
begin
position_s <= 0;
if(align_complete == 1'b1)
begin
motor_state <= (run_i == 1'b1 ? RUN : OFF);
end
else
begin
motor_state <= (run_i == 1'b1 ? ALIGN : OFF);
end
end
RUN:
begin
position_s <= position_i - 1;
motor_state <= (run_i == 1'b1 ? RUN : OFF);
end
default:
begin
motor_state <= OFF;
end
endcase
align_counter <= motor_state == ALIGN ? align_counter + 1 : 0;
end
end
//Generate the PWM signal
always @(posedge pwm_clk_i)
begin
if((rst_n_i == 1'b0))
begin
pwm_cnt <= 0;
end
else
begin
pwm_cnt <= pwm_cnt < (2**PWM_BITS - 1) ? pwm_cnt + 1 : 0;
end
pwm_s <= pwm_cnt < pwm_duty_s ? 1 : 0;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:49:38 10/13/2015
// Design Name:
// Module Name: LCD_dis
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LCD_dis(
input clk,
input[127:0] num,
input reset,
output reg lcd_rs,
output lcd_rw,
output reg lcd_e,
output reg[3:0] lcd_d,
output flash_ce
);
assign flash_ce = 1;
assign lcd_rw = 0;
reg [19:0] delay_count;
reg [19:0] num_count;
wire[7:0] ascii;
wire[3:0] hex;
reg[4:0] dis_count;
reg [5:0] state;
reg state_change;
/*
initial begin
dis_count<=5'h0;
num_count<=20'd750000;
state<=6'b1;
state_change <=0;
delay_count <= 1;
end
*/
assign ascii = (hex[3] & (hex[2] | hex[1]))? (8'h37 + {4'h0,hex}) : {4'h3 ,hex};
assign hex =
{4{(dis_count == 5'h1F)}} & num[3:0] |
{4{(dis_count == 5'h1E)}} & num[7:4] |
{4{(dis_count == 5'h1D)}} & num[11:8] |
{4{(dis_count == 5'h1C)}} & num[15:12] |
{4{(dis_count == 5'h1B)}} & num[19:16] |
{4{(dis_count == 5'h1A)}} & num[23:20] |
{4{(dis_count == 5'h19)}} & num[27:24] |
{4{(dis_count == 5'h18)}} & num[31:28] |
{4{(dis_count == 5'h17)}} & num[35:32] |
{4{(dis_count == 5'h16)}} & num[39:36] |
{4{(dis_count == 5'h15)}} & num[43:40] |
{4{(dis_count == 5'h14)}} & num[47:44] |
{4{(dis_count == 5'h13)}} & num[51:48] |
{4{(dis_count == 5'h12)}} & num[55:52] |
{4{(dis_count == 5'h11)}} & num[59:56] |
{4{(dis_count == 5'h10)}} & num[63:60] |
{4{(dis_count == 5'hF)}} & num[67:64] |
{4{(dis_count == 5'hE)}} & num[71:68] |
{4{(dis_count == 5'hD)}} & num[75:72] |
{4{(dis_count == 5'hC)}} & num[79:76] |
{4{(dis_count == 5'hB)}} & num[83:80] |
{4{(dis_count == 5'hA)}} & num[87:84] |
{4{(dis_count == 5'h9)}} & num[91:88] |
{4{(dis_count == 5'h8)}} & num[95:92] |
{4{(dis_count == 5'h7)}} & num[99:96] |
{4{(dis_count == 5'h6)}} & num[103:100] |
{4{(dis_count == 5'h5)}} & num[107:104] |
{4{(dis_count == 5'h4)}} & num[111:108] |
{4{(dis_count == 5'h3)}} & num[115:112] |
{4{(dis_count == 5'h2)}} & num[119:116] |
{4{(dis_count == 5'h1)}} & num[123:120] |
{4{(dis_count == 5'h0)}} & num[127:124] ;
parameter state1 = 6'b000001;
parameter state2 = 6'b000010;
parameter state3 = 6'b000011;
parameter state4 = 6'b000100;
parameter state5 = 6'b000101;
parameter state6 = 6'b000110;
parameter state7 = 6'b000111;
parameter state8 = 6'b001000;
parameter state9 = 6'b001001;
parameter state10 = 6'b001010;
parameter state11 = 6'b001011;
parameter state12 = 6'b001100;
parameter state13 = 6'b001101;
parameter state14 = 6'b001110;
parameter state15 = 6'b001111;
parameter state16 = 6'b010000;
parameter state17 = 6'b010001;
parameter state18 = 6'b010010;
parameter state19 = 6'b010011;
parameter state20 = 6'b010100;
parameter state21 = 6'b010101;
parameter state22 = 6'b010110;
parameter state23 = 6'b010111;
parameter state24 = 6'b011000;
parameter state25 = 6'b011001;
parameter state26 = 6'b011010;
parameter state27 = 6'b011011;
parameter state28 = 6'b011100;
parameter state29 = 6'b011101;
parameter state30 = 6'b011110;
parameter state31 = 6'b011111;
parameter state32 = 6'b100000;
parameter state33 = 6'b100001;
parameter state34 = 6'b100010;
parameter state35 = 6'b100011;
parameter state36 = 6'b100100;
parameter state37 = 6'b100101;
parameter state38 = 6'b100110;
parameter state39 = 6'b100111;
parameter state40 = 6'b101000;
parameter state41 = 6'b101001;
parameter state42 = 6'b101010;
parameter state43 = 6'b101011;
parameter state44 = 6'b101100;
parameter state45 = 6'b101101;
parameter state46 = 6'b101110;
parameter state47 = 6'b101111;
parameter state48 = 6'b110000;
parameter state49 = 6'b110001;
parameter state50 = 6'b110010;
parameter state51 = 6'b110011;
parameter state52 = 6'b110100;
parameter state53 = 6'b110101;
parameter state54 = 6'b110110;
parameter state55 = 6'b110111;
parameter state56 = 6'b111000;
parameter state57 = 6'b111001;
parameter state58 = 6'b111010;
parameter state59 = 6'b111011;
always @(posedge clk or posedge reset)
if(reset) begin
state_change <= 1'b0;
delay_count <= 1'b1;
end
else
if(delay_count == num_count - 1) begin
state_change <= 1'b1;
delay_count <= 1'b1;
end
else
begin
state_change <= 1'b0;
delay_count <= delay_count + 1'b1;
end
always @(posedge state_change or posedge reset)
if(reset) begin
state <= state1;
num_count <= 20'd750000;
end
else begin
case(state)
state1:begin
state <= state2;
num_count <= 20'd4;
lcd_rs <= 1'b0;
lcd_e <= 1'b0;
lcd_d <= 4'h3;
end
state2:begin
state <= state3;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state3:begin
state <= state4;
num_count <= 20'd205000;
lcd_e <= 1'b0;
end
state4:begin
state <= state5;
num_count <= 20'd4;
lcd_d <= 4'h3;
end
state5:begin
state <= state6;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state6:begin
state <= state7;
num_count <= 20'd5000;
lcd_e <= 1'b0;
end
state7:begin
state <= state8;
num_count <= 20'd4;
lcd_d <= 4'h2;
end
state8:begin
state <= state9;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state9:begin
state <= state10;
num_count <= 20'd4000;
lcd_e <= 1'b0;
end
//set funtion mode
state10:begin
state <= state11;
num_count <= 20'd4;
lcd_rs <= 0;
lcd_d <= 4'h2;
end
state11:begin
state <= state12;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state12:begin
state <= state13;
num_count <= 20'd80;
lcd_e <= 1'b0;
end
state13:begin
state <= state14;
num_count <= 20'd4;
lcd_d <= 4'h8;
end
state14:begin
state <= state15;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state15:begin
state <= state16;
num_count <= 20'd4000;
lcd_e <= 1'b0;
end
//set entry mode
state16:begin
state <= state17;
num_count <= 20'd4;
lcd_d <= 4'h0;
end
state17:begin
state <= state18;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state18:begin
state <= state19;
num_count <= 20'd80;
lcd_e <= 1'b0;
end
state19:begin
state <= state20;
num_count <= 20'd4;
lcd_d <= 4'h6;
end
state20:begin
state <= state21;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state21:begin
state <= state22;
num_count <= 20'd4000;
lcd_e <= 1'b0;
end
//set display on/off
state22:begin
state <= state23;
num_count <= 20'd4;
lcd_d <= 4'h0;
end
state23:begin
state <= state24;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state24:begin
state <= state25;
num_count <= 20'd80;
lcd_e <= 1'b0;
end
state25:begin
state <= state26;
num_count <= 20'd4;
lcd_d <= 4'hc;
end
state26:begin
state <= state27;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state27:begin
state <= state28;
num_count <= 20'd4000;
lcd_e <= 1'b0;
end
//clear display
state28:begin
state <= state29;
num_count <= 20'd4;
lcd_d <= 4'h0;
end
state29:begin
state <= state30;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state30:begin
state <= state31;
num_count <= 20'd80;
lcd_e <= 1'b0;
end
state31:begin
state <= state32;
num_count <= 20'd4;
lcd_d <= 4'h1;
end
state32:begin
state <= state33;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state33:begin
state <= state34;
num_count <= 20'd2000;
lcd_e <= 1'b0;
end
state34:begin
state <= state35;
num_count <= 20'd82000;
end
//set DD RAM address
state35:begin
state <= state36;
num_count <= 20'd4;
lcd_rs <= 1'b0;
lcd_e <= 1'b0;
if (dis_count[4]) begin
lcd_d <= 4'hC;
end
else begin
lcd_d <= 4'h8;
end
end
state36:begin
state <= state37;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state37:begin
state <= state38;
num_count <= 20'd80;
lcd_e <= 1'b0;
end
state38:begin
state <= state39;
num_count <= 20'd4;
lcd_d <= dis_count[3:0];
end
state39:begin
state <= state40;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state40:begin
state <= state41;
num_count <= 20'd4000;
lcd_e <= 1'b0;
end
// now starts writing data to DD RAM
state41:begin
state <= state42;
num_count <= 20'd4;
lcd_rs <= 1'b1;
lcd_d <= ascii[7:4];
end
state42:begin
state <= state43;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state43:begin
state <= state44;
num_count <= 20'd80;
lcd_e <= 1'b0;
end
state44:begin
state <= state45;
num_count <= 20'd4;
lcd_d <= ascii[3:0];
end
state45:begin
state <= state46;
num_count <= 20'd12;
lcd_e <= 1'b1;
end
state46:begin
state <= state35;
num_count <= 20'd2000;
lcd_e <= 1'b0;
dis_count <= dis_count+1;
end
default:begin
state <= state1;
num_count <= 20'd800;
end
endcase
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: playback_fifo.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module playback_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
wrempty,
wrfull,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [63:0] q;
output rdempty;
output rdfull;
output wrempty;
output wrfull;
output [4:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire [4:0] sub_wire5;
wire [63:0] q = sub_wire0[63:0];
wire rdempty = sub_wire1;
wire rdfull = sub_wire2;
wire wrempty = sub_wire3;
wire wrfull = sub_wire4;
wire [4:0] wrusedw = sub_wire5[4:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdfull (sub_wire2),
.wrempty (sub_wire3),
.wrfull (sub_wire4),
.wrusedw (sub_wire5),
.eccstatus (),
.rdusedw ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone V",
dcfifo_mixed_widths_component.lpm_numwords = 32,
dcfifo_mixed_widths_component.lpm_showahead = "ON",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 32,
dcfifo_mixed_widths_component.lpm_widthu = 5,
dcfifo_mixed_widths_component.lpm_widthu_r = 4,
dcfifo_mixed_widths_component.lpm_width_r = 64,
dcfifo_mixed_widths_component.overflow_checking = "OFF",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
dcfifo_mixed_widths_component.underflow_checking = "OFF",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "ON",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "64"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "64"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL "wrusedw[4..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo_bb.v TRUE
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
usb_system_jtag_uart_sim_scfifo_w the_usb_system_jtag_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
usb_system_jtag_uart_sim_scfifo_r the_usb_system_jtag_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_jtag_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
usb_system_jtag_uart_scfifo_w the_usb_system_jtag_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
usb_system_jtag_uart_scfifo_r the_usb_system_jtag_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic usb_system_jtag_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam usb_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// usb_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// usb_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// usb_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O2BB2A_PP_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_PP_BLACKBOX_V
|
`include "config.inc"
module video2ram(
input clock,
input nreset,
input [7:0] R,
input [7:0] G,
input [7:0] B,
input [11:0] counterX,
input [11:0] counterY,
input line_doubler,
input is_pal,
output [23:0] wrdata,
output [`RAM_WIDTH-1:0] wraddr,
output wren,
output starttrigger,
input DCVideoConfig dcVideoConfig,
input [7:0] color_config_data
);
reg [9:0] H_CAPTURE_START;
reg [9:0] H_CAPTURE_END;
reg [9:0] V_CAPTURE_START;
reg [9:0] V_CAPTURE_END;
reg wren_reg;
reg [23:0] wrdata_reg;
reg [14:0] wraddr_reg;
reg [14:0] ram_addrY_reg;
reg trigger;
reg [11:0] counterX_prev;
reg line_doubler_reg = 0;
reg is_pal_reg = 0;
wire wren_cv;
wire [14:0] wraddr_cv;
wire [23:0] wrdata_cv;
wire starttrigger_cv;
colorconv cv(
.clock(clock),
.color_config(color_config_data[2:0]),
.in_wren(wren_reg),
.in_wraddr(wraddr_reg),
.in_red(wrdata_reg[23:16]),
.in_green(wrdata_reg[15:8]),
.in_blue(wrdata_reg[7:0]),
.in_starttrigger(trigger),
.wren(wren_cv),
.wraddr(wraddr_cv),
.wrdata(wrdata_cv),
.starttrigger(starttrigger_cv)
);
gammaconv gv(
.clock(clock),
.gamma_config(color_config_data[7:3]),
.in_wren(wren_cv),
.in_wraddr(wraddr_cv),
.in_red(wrdata_cv[23:16]),
.in_green(wrdata_cv[15:8]),
.in_blue(wrdata_cv[7:0]),
.in_starttrigger(starttrigger_cv),
.wren(wren),
.wraddr(wraddr),
.wrdata(wrdata),
.starttrigger(starttrigger)
);
always @(*) begin
if (line_doubler_reg) begin
H_CAPTURE_START = dcVideoConfig.i_horizontal_capture_start;
H_CAPTURE_END = dcVideoConfig.i_horizontal_capture_end;
V_CAPTURE_START = dcVideoConfig.i_vertical_capture_start;
V_CAPTURE_END = dcVideoConfig.i_vertical_capture_end;
end else begin
H_CAPTURE_START = dcVideoConfig.p_horizontal_capture_start;
H_CAPTURE_END = dcVideoConfig.p_horizontal_capture_end;
V_CAPTURE_START = dcVideoConfig.p_vertical_capture_start;
V_CAPTURE_END = dcVideoConfig.p_vertical_capture_end;
end
end
`define GetWriteAddr(x) (ram_addrY_reg + (x - H_CAPTURE_START))
`define IsFirstBuffer(y) ((y - V_CAPTURE_START) < dcVideoConfig.buffer_size)
`define IsTriggerPoint(y) (`IsFirstBuffer(y) && wraddr_reg == (line_doubler_reg ? dcVideoConfig.trigger_address_i : dcVideoConfig.trigger_address_p))
`define IsVerticalCaptureTime(y) ( \
line_doubler_reg \
? (is_pal_reg \
? (y < 288 || (y > 312 && y < V_CAPTURE_END)) \
: (y < 240 || (y > 262 && y < V_CAPTURE_END))) \
: (y >= V_CAPTURE_START && y < V_CAPTURE_END) \
)
`define IsCaptureTime(x,y) ( \
`IsVerticalCaptureTime(y) && x >= H_CAPTURE_START && x < H_CAPTURE_END \
)
initial begin
wren_reg <= 0;
wrdata_reg <= 24'd0;
wraddr_reg <= 0;
ram_addrY_reg <= 0;
trigger <= 0;
end
always @ (posedge clock or negedge nreset) begin
if (~nreset) begin
wren_reg <= 0;
wrdata_reg <= 24'd0;
wraddr_reg <= 0;
ram_addrY_reg <= 0;
trigger <= 0;
line_doubler_reg <= 0;
is_pal_reg <= 0;
end else begin
line_doubler_reg <= line_doubler;
is_pal_reg <= is_pal;
counterX_prev <= counterX;
if (counterX_prev == H_CAPTURE_END && counterX == H_CAPTURE_END) begin // calculate ram_addrY_reg once per line
if (`IsVerticalCaptureTime(counterY)
&& ram_addrY_reg < dcVideoConfig.ram_numwords - dcVideoConfig.buffer_line_length) begin
ram_addrY_reg <= ram_addrY_reg + dcVideoConfig.buffer_line_length;
end else begin
ram_addrY_reg <= 0;
end
end
if (`IsCaptureTime(counterX, counterY)) begin
wren_reg <= 1;
wraddr_reg <= `GetWriteAddr(counterX);
wrdata_reg <= { R, G, B };
if (`IsTriggerPoint(counterY)) begin
trigger <= 1'b1;
end else begin
trigger <= 1'b0;
end
end else begin
wren_reg <= 0;
trigger <= 1'b0;
end
end
end
// assign wren = wren_reg;
// assign wraddr = wraddr_reg;
// assign wrdata = wrdata_reg;
// assign starttrigger = trigger;
endmodule |
module game_graph_simple
(
input wire clk, reset,
input wire video_on,
input wire [1:0] btn,
// control the bar
input wire [1:0] sw,
// control the gun
input wire [9:0] pix_x, pix_y,
output reg [2:0] graph_rgb
);
// constant and signal declaration
// x, y coordinates (0,0) to (639,479)
localparam MAX_X = 640;
localparam MAX_Y = 480;
wire refr_tick;
// refr_tick is the refreshment rate
//--------------------------------------------
// vertical stripe as a wall
//--------------------------------------------
// wall left, right boundary
localparam WALL_X_L = 20;
localparam WALL_X_R = 25;
// decrease it if you want more space
//--------------------------------------------
// Let us define the gunner
// just think about the death gun from Sword Art Online
//--------------------------------------------
localparam GUN_X_L = 50;
localparam GUN_X_R = 53;
wire [9:0] gun_y_t;
wire [9:0] gun_y_b;
// register to track the gun
reg [9:0] gun_y_reg;
reg [9:0] gun_y_next;
// gun should move slower than bar
localparam GUN_V = 2;
localparam GUN_Y_SIZE = 62;
//--------------------------------------------
// Now bullet (without silver, pity)
//--------------------------------------------
localparam BULLET_SIZE = 9;
localparam BULLET_V = 5;
// should be able to run in all directions
// however, one direction is locked with the gun (emitter)
wire [9:0] bullet_x_l, bullet_x_r;
wire [9:0] bullet_y_t, bullet_y_b;
// speed shall be registered
reg [9:0] bullet_x_reg;
reg [9:0] bullet_y_reg;
reg [9:0] bullet_x_next;
reg [9:0] bullet_y_next;
//--------------------------------------------
// right vertical bar
//--------------------------------------------
// bar left, right boundary
localparam BAR_X_L = 600;
localparam BAR_X_R = 603;
// bar top, bottom boundary
wire [9:0] bar_y_t, bar_y_b;
localparam BAR_Y_SIZE = 72;
// register to track top boundary (x position is fixed)
reg [9:0] bar_y_reg, bar_y_next;
// bar moving velocity when a button is pressed
localparam BAR_V = 4;
//--------------------------------------------
// square ball (this part can be deleted, test purpose only)
//--------------------------------------------
localparam BALL_SIZE = 8;
// ball left, right boundary
wire [9:0] ball_x_l, ball_x_r;
// ball top, bottom boundary
wire [9:0] ball_y_t, ball_y_b;
// reg to track left, top position
reg [9:0] ball_x_reg, ball_y_reg;
wire [9:0] ball_x_next, ball_y_next;
// reg to track ball speed
reg [9:0] x_delta_reg, x_delta_next;
reg [9:0] y_delta_reg, y_delta_next;
// ball velocity can be pos or neg)
localparam BALL_V_P = 2;
localparam BALL_V_N = -2;
//--------------------------------------------
// round ball (we use this ball actually)
//--------------------------------------------
wire [2:0] rom_addr, rom_col;
reg [7:0] rom_data;
wire rom_bit;
//--------------------------------------------
// object output signals
//--------------------------------------------
wire wall_on, bar_on, gun_on, bullet_on, sq_ball_on, rd_ball_on;
wire [2:0] wall_rgb, gun_rgb, bullet_rgb, bar_rgb, ball_rgb;
// body
//--------------------------------------------
// round ball image ROM
//--------------------------------------------
always @*
case (rom_addr)
// right side is the shape of the ball (at least we think it shall be)
3'h0: rom_data = 8'b00111100; // ****
3'h1: rom_data = 8'b01111110; // ******
3'h2: rom_data = 8'b11111111; // ********
3'h3: rom_data = 8'b11111111; // ********
3'h4: rom_data = 8'b11111111; // ********
3'h5: rom_data = 8'b11111111; // ********
3'h6: rom_data = 8'b01111110; // ******
3'h7: rom_data = 8'b00111100; // ****
endcase
// registers
always @(posedge clk, posedge reset)
if (reset)
begin
bar_y_reg <= 0;
// well, this line is added for visual effect
gun_y_reg <= 0;
// and so is that line
ball_x_reg <= 0;
ball_y_reg <= 0;
bullet_x_reg <= GUN_X_R;
bullet_y_reg <= 0+GUN_Y_SIZE/2;
// 0 should actually be gun_y_reg
// (which shall be zero after resetting op)
// different from the ball
// since at the beginning of the game, bullet should lie
// still on the gun (or gunner)
x_delta_reg <= 10'h004;
y_delta_reg <= 10'h004;
end
else
begin
bar_y_reg <= bar_y_next;
// updating with reg (one time pad loss, same with sync)
gun_y_reg <= gun_y_next;
ball_x_reg <= ball_x_next;
ball_y_reg <= ball_y_next;
x_delta_reg <= x_delta_next;
y_delta_reg <= y_delta_next;
bullet_x_reg <= bullet_x_next; // changed from y to x
bullet_y_reg <= bullet_y_next;
// a little easy than the ball
end
// refr_tick: 1-clock tick asserted at start of v-sync
assign refr_tick = (pix_y==481) && (pix_x==0);
//--------------------------------------------
// (wall) left vertical strip
//--------------------------------------------
// pixel within wall
assign wall_on = (WALL_X_L<=pix_x) && (pix_x<=WALL_X_R);
// wall rgb output
assign wall_rgb = 3'b001; // blue
//--------------------------------------------
// right vertical bar
//--------------------------------------------
// boundary
assign bar_y_t = bar_y_reg;
assign bar_y_b = bar_y_t + BAR_Y_SIZE - 1;
// pixel within bar
assign bar_on = (BAR_X_L<=pix_x) && (pix_x<=BAR_X_R) &&
(bar_y_t<=pix_y) && (pix_y<=bar_y_b);
// bar rgb output
assign bar_rgb = 3'b010; // green
// new bar y-position
always @*
begin
bar_y_next = bar_y_reg; // no move
if (refr_tick)
if (btn[1] & (bar_y_b < (MAX_Y-1-BAR_V)))
bar_y_next = bar_y_reg + BAR_V; // move down
else if (btn[0] & (bar_y_t > BAR_V))
bar_y_next = bar_y_reg - BAR_V; // move up
end
//--------------------------------------------
// gun (well ... interesting)
//--------------------------------------------
// gun in the left
assign gun_y_t = gun_y_reg;
assign gun_y_b = gun_y_t + GUN_Y_SIZE -1;
// pixels within gun
assign gun_on = (GUN_X_L<=pix_x) && (pix_x<=GUN_X_R) && (gun_y_t<=pix_y) && (pix_y<=gun_y_b);
// gun_y_t should change timely based.
assign gun_rgb = 3'b000;
// changed from white to black
// black gun, the name was taken after the famous boss in the SWORT ART ONLINE
always @*
begin
gun_y_next = gun_y_reg;
if (refr_tick)
if (sw[0] & (gun_y_b < (MAX_Y-1-GUN_V)))
gun_y_next = gun_y_reg + GUN_V; // move up (minor changed)
else if ( (~sw[0]) & (gun_y_t > GUN_V) )
gun_y_next = gun_y_reg - GUN_V; // move down
end
// gun is controlled by switch
//--------------------------------------------
// you can not use a gun without bullet
//--------------------------------------------
// Let us define the bullet
assign bullet_x_l = bullet_x_reg;
assign bullet_x_r = bullet_x_l + BULLET_SIZE -1;
assign bullet_y_t = bullet_y_reg;
// the word size b is a little larger I assume
// right?
assign bullet_y_b = bullet_y_t + BULLET_SIZE -1;
// pixel within bullet
assign bullet_on =
(bullet_x_l<=pix_x) && (pix_x<=bullet_x_r) &&
(bullet_y_t<=pix_y) && (pix_y<=bullet_y_b);
// Now pixels within the bullet are defined with color
assign bullet_rgb = 3'b000; //black bullet
// Well, silver bullet is prefered, but I don't know how to represent it with rgb values.
// the board should be blamed, not me (laugh)
always @*
begin
bullet_x_next = bullet_x_reg;
bullet_y_next = bullet_y_reg;
if (refr_tick)
if ((BAR_X_L<=bullet_x_r) && (bullet_x_r<=BAR_X_R) &&
(bar_y_t<=bullet_y_b) && (bullet_y_t<=bar_y_b))
// now you hit it
begin
bullet_x_next = GUN_X_R;
// bullet_x_next is the left side of the bullet (should be held at the right side of the gun)
bullet_y_next = gun_y_reg+GUN_Y_SIZE/2;
end
// emission of bullet is controlled by sw not button
// actually, this should be done with a de-bounced switch (written by cpp)
else if ( sw[1] || (bullet_x_l >= GUN_X_R+5) )
bullet_x_next = bullet_x_reg + BULLET_V;
// y doesn't change, fly along the trajectory (not very physical I assume)
else if ( (bullet_x_reg<=(GUN_X_L-1)) || (bullet_x_reg>=(MAX_X-BULLET_SIZE-1)) )
// correspond to initialization, over, less than
// to make it clearer, over the right boarder of the screen, or less than the left side of the gun
begin
bullet_x_next = GUN_X_R;
bullet_y_next = gun_y_reg+GUN_Y_SIZE/2;
end
else
begin
bullet_x_next = GUN_X_R;
bullet_y_next = gun_y_reg+GUN_Y_SIZE/2;
end
end
// please don't delete it
// may be used in some test case
//--------------------------------------------
// ball
//--------------------------------------------
// boundary
assign ball_x_l = ball_x_reg;
assign ball_y_t = ball_y_reg;
assign ball_x_r = ball_x_l + BALL_SIZE - 1;
assign ball_y_b = ball_y_t + BALL_SIZE - 1;
// pixel within ball
assign sq_ball_on =
(ball_x_l<=pix_x) && (pix_x<=ball_x_r) &&
(ball_y_t<=pix_y) && (pix_y<=ball_y_b);
// map current pixel location to ROM addr/col
assign rom_addr = pix_y[2:0] - ball_y_t[2:0];
assign rom_col = pix_x[2:0] - ball_x_l[2:0];
assign rom_bit = rom_data[rom_col];
// pixel within ball
assign rd_ball_on = sq_ball_on & rom_bit;
// ball rgb output
assign ball_rgb = 3'b100; // red
// new ball position
assign ball_x_next = (refr_tick) ? ball_x_reg+x_delta_reg :
ball_x_reg ;
assign ball_y_next = (refr_tick) ? ball_y_reg+y_delta_reg :
ball_y_reg ;
// new ball velocity
always @*
begin
x_delta_next = x_delta_reg;
y_delta_next = y_delta_reg;
if (ball_y_t < 1) // reach top
y_delta_next = BALL_V_P;
else if (ball_y_b > (MAX_Y-1)) // reach bottom
y_delta_next = BALL_V_N;
else if (ball_x_l <= WALL_X_R) // reach wall
x_delta_next = BALL_V_P; // bounce back
else if ((BAR_X_L<=ball_x_r) && (ball_x_r<=BAR_X_R) &&
(bar_y_t<=ball_y_b) && (ball_y_t<=bar_y_b))
// reach x of right bar and hit, ball bounce back
x_delta_next = BALL_V_N;
end
//--------------------------------------------
// rgb multiplexing circuit
//--------------------------------------------
always @*
if (~video_on)
graph_rgb = 3'b000; // blank
else
if (wall_on)
graph_rgb = wall_rgb;
else if (bullet_on)
graph_rgb = bullet_rgb;
// bullet is higher that bar (since it can get through it)
else if (bar_on)
graph_rgb = bar_rgb;
else if (gun_on)
graph_rgb = gun_rgb;
else if (rd_ball_on)
// this stands for the round ball (well...)
// you could also use the sqaure ball which is not yet deleted for the test purpose only
graph_rgb = ball_rgb;
else
graph_rgb = 3'b110; // yellow background
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
/**
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer, vpb/vnb
* taps, double-row-height cell.
*
* Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
* size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A),
.LOWLVPWR(LOWLVPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 19:45:27 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_zynq_snick_auto_pc_0_stub.v
// Design : gcd_zynq_snick_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:53:27 2016
/////////////////////////////////////////////////////////////
module GeAr_N16_R4_P8 ( in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
wire n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72,
n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86,
n87;
AOI21X2TS U2 ( .A0(n56), .A1(n54), .B0(n13), .Y(n72) );
AOI21X1TS U3 ( .A0(n10), .A1(n76), .B0(n9), .Y(n11) );
OAI21X2TS U4 ( .A0(n8), .A1(n7), .B0(n6), .Y(n10) );
OAI21X2TS U5 ( .A0(n31), .A1(n30), .B0(n29), .Y(n40) );
INVX2TS U6 ( .A(n78), .Y(n9) );
OAI21XLTS U7 ( .A0(n16), .A1(n20), .B0(n22), .Y(n19) );
OAI21X2TS U8 ( .A0(n65), .A1(n64), .B0(n63), .Y(n75) );
XOR2X1TS U9 ( .A(n80), .B(n77), .Y(res[10]) );
XOR2X1TS U10 ( .A(n72), .B(n71), .Y(res[15]) );
OAI21X1TS U11 ( .A0(n72), .A1(n68), .B0(n69), .Y(res[16]) );
OAI21X1TS U12 ( .A0(n80), .A1(n79), .B0(n78), .Y(n85) );
NOR2X1TS U13 ( .A(n20), .B(n23), .Y(n25) );
OR2X2TS U14 ( .A(in1[12]), .B(in2[12]), .Y(n34) );
OR2X2TS U15 ( .A(in1[9]), .B(in2[9]), .Y(n74) );
OR2X2TS U16 ( .A(in1[5]), .B(in2[5]), .Y(n39) );
OR2X2TS U17 ( .A(in1[14]), .B(in2[14]), .Y(n54) );
INVX2TS U18 ( .A(n37), .Y(n38) );
INVX2TS U19 ( .A(n46), .Y(n59) );
AOI21X2TS U20 ( .A0(n36), .A1(n34), .B0(n12), .Y(n52) );
INVX2TS U21 ( .A(n33), .Y(n12) );
NOR2X1TS U22 ( .A(in1[8]), .B(in2[8]), .Y(n64) );
INVX2TS U23 ( .A(n66), .Y(n73) );
INVX2TS U24 ( .A(n64), .Y(n61) );
INVX2TS U25 ( .A(n57), .Y(n58) );
INVX2TS U26 ( .A(n79), .Y(n76) );
INVX2TS U27 ( .A(n53), .Y(n13) );
OAI21XLTS U28 ( .A0(n46), .A1(n43), .B0(n57), .Y(n2) );
INVX2TS U29 ( .A(n63), .Y(n5) );
INVX2TS U30 ( .A(n26), .Y(n16) );
INVX2TS U31 ( .A(n30), .Y(n27) );
INVX2TS U32 ( .A(n44), .Y(n41) );
XOR2XLTS U33 ( .A(n65), .B(n62), .Y(res[8]) );
NAND2X1TS U34 ( .A(n74), .B(n66), .Y(n67) );
NAND2X1TS U35 ( .A(n83), .B(n82), .Y(n84) );
XOR2XLTS U36 ( .A(n52), .B(n51), .Y(res[13]) );
INVX2TS U37 ( .A(n48), .Y(n50) );
INVX2TS U38 ( .A(n20), .Y(n14) );
NOR2X2TS U39 ( .A(in1[2]), .B(in2[2]), .Y(n20) );
INVX2TS U40 ( .A(n68), .Y(n70) );
NOR2X1TS U41 ( .A(in1[15]), .B(in2[15]), .Y(n68) );
AOI21X1TS U42 ( .A0(n4), .A1(n3), .B0(n2), .Y(n8) );
NOR2X2TS U43 ( .A(in1[6]), .B(in2[6]), .Y(n44) );
NOR2X1TS U44 ( .A(in1[11]), .B(in2[11]), .Y(n81) );
NAND2X1TS U45 ( .A(in1[4]), .B(in2[4]), .Y(n29) );
AFHCINX2TS U46 ( .CIN(n29), .B(in1[5]), .A(in2[5]), .CO(n4) );
NOR2X2TS U47 ( .A(in1[7]), .B(in2[7]), .Y(n46) );
NOR2XLTS U48 ( .A(n44), .B(n46), .Y(n3) );
NAND2X1TS U49 ( .A(in1[6]), .B(in2[6]), .Y(n43) );
NAND2X1TS U50 ( .A(in1[7]), .B(in2[7]), .Y(n57) );
NAND2X1TS U51 ( .A(n61), .B(n74), .Y(n7) );
NAND2X1TS U52 ( .A(in1[8]), .B(in2[8]), .Y(n63) );
NAND2X1TS U53 ( .A(in1[9]), .B(in2[9]), .Y(n66) );
AOI21X1TS U54 ( .A0(n74), .A1(n5), .B0(n73), .Y(n6) );
NOR2X1TS U55 ( .A(in1[10]), .B(in2[10]), .Y(n79) );
NAND2X1TS U56 ( .A(in1[10]), .B(in2[10]), .Y(n78) );
NAND2X1TS U57 ( .A(in1[11]), .B(in2[11]), .Y(n82) );
OAI21X1TS U58 ( .A0(n11), .A1(n81), .B0(n82), .Y(n36) );
NAND2X1TS U59 ( .A(in1[12]), .B(in2[12]), .Y(n33) );
NOR2X1TS U60 ( .A(in1[13]), .B(in2[13]), .Y(n48) );
NAND2X1TS U61 ( .A(in1[13]), .B(in2[13]), .Y(n49) );
OAI21X4TS U62 ( .A0(n52), .A1(n48), .B0(n49), .Y(n56) );
NAND2X1TS U63 ( .A(in1[14]), .B(in2[14]), .Y(n53) );
NAND2X1TS U64 ( .A(in1[15]), .B(in2[15]), .Y(n69) );
NAND2X1TS U65 ( .A(in1[0]), .B(in2[0]), .Y(n87) );
NAND2X1TS U66 ( .A(in1[2]), .B(in2[2]), .Y(n22) );
NAND2X1TS U67 ( .A(n14), .B(n22), .Y(n15) );
XNOR2X1TS U68 ( .A(n26), .B(n15), .Y(res[2]) );
NOR2X2TS U69 ( .A(in1[3]), .B(in2[3]), .Y(n23) );
INVX2TS U70 ( .A(n23), .Y(n17) );
NAND2X1TS U71 ( .A(in1[3]), .B(in2[3]), .Y(n21) );
NAND2X1TS U72 ( .A(n17), .B(n21), .Y(n18) );
XNOR2X1TS U73 ( .A(n19), .B(n18), .Y(res[3]) );
OAI21X1TS U74 ( .A0(n23), .A1(n22), .B0(n21), .Y(n24) );
AOI21X2TS U75 ( .A0(n26), .A1(n25), .B0(n24), .Y(n31) );
NOR2X1TS U76 ( .A(in1[4]), .B(in2[4]), .Y(n30) );
NAND2X1TS U77 ( .A(n27), .B(n29), .Y(n28) );
XOR2XLTS U78 ( .A(n31), .B(n28), .Y(res[4]) );
NAND2X1TS U79 ( .A(in1[5]), .B(in2[5]), .Y(n37) );
NAND2X1TS U80 ( .A(n39), .B(n37), .Y(n32) );
XNOR2X1TS U81 ( .A(n40), .B(n32), .Y(res[5]) );
NAND2X1TS U82 ( .A(n34), .B(n33), .Y(n35) );
XNOR2X1TS U83 ( .A(n36), .B(n35), .Y(res[12]) );
AOI21X4TS U84 ( .A0(n40), .A1(n39), .B0(n38), .Y(n45) );
NAND2X1TS U85 ( .A(n41), .B(n43), .Y(n42) );
XOR2XLTS U86 ( .A(n45), .B(n42), .Y(res[6]) );
OAI21X4TS U87 ( .A0(n45), .A1(n44), .B0(n43), .Y(n60) );
NAND2X1TS U88 ( .A(n59), .B(n57), .Y(n47) );
XNOR2X1TS U89 ( .A(n60), .B(n47), .Y(res[7]) );
NAND2X1TS U90 ( .A(n50), .B(n49), .Y(n51) );
NAND2X1TS U91 ( .A(n54), .B(n53), .Y(n55) );
XNOR2X1TS U92 ( .A(n56), .B(n55), .Y(res[14]) );
AOI21X4TS U93 ( .A0(n60), .A1(n59), .B0(n58), .Y(n65) );
NAND2X1TS U94 ( .A(n61), .B(n63), .Y(n62) );
XNOR2X1TS U95 ( .A(n75), .B(n67), .Y(res[9]) );
NAND2X1TS U96 ( .A(n70), .B(n69), .Y(n71) );
AOI21X1TS U97 ( .A0(n75), .A1(n74), .B0(n73), .Y(n80) );
NAND2X1TS U98 ( .A(n76), .B(n78), .Y(n77) );
INVX2TS U99 ( .A(n81), .Y(n83) );
XNOR2X1TS U100 ( .A(n85), .B(n84), .Y(res[11]) );
OR2X1TS U101 ( .A(in1[0]), .B(in2[0]), .Y(n86) );
CLKAND2X2TS U102 ( .A(n86), .B(n87), .Y(res[0]) );
AFHCINX2TS U103 ( .CIN(n87), .B(in1[1]), .A(in2[1]), .S(res[1]), .CO(n26) );
initial $sdf_annotate("GeAr_N16_R4_P8_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__NOR2_FUNCTIONAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O41AI_BEHAVIORAL_PP_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41AI_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__FILL_PP_BLACKBOX_V
/**
* fill: Fill cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fill (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:32:16 03/03/2016
// Design Name: register
// Module Name: G:/ceshi/lab4/test_for_register.v
// Project Name: lab4
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: register
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_register;
// Inputs
reg clock_in;
reg [25:21] readReg1;
reg [20:16] readReg2;
reg [4:0] writeReg;
reg [31:0] writeData;
reg regWrite;
// Outputs
wire [31:0] readData1;
wire [31:0] readData2;
// Instantiate the Unit Under Test (UUT)
register uut (
.clock_in(clock_in),
.readReg1(readReg1),
.readReg2(readReg2),
.writeReg(writeReg),
.writeData(writeData),
.regWrite(regWrite),
.readData1(readData1),
.readData2(readData2)
);
//always #100 clock_in = ~clock_in;
initial begin
// Initialize Inputs
clock_in = 0;
readReg1 = 0;
readReg2 = 0;
writeReg = 0;
writeData = 0;
regWrite = 0;
clock_in = 0;
// Wait 100 ns for global reset to finish
#285;
regWrite = 1'b1;
writeReg = 5'b10101;
writeData = 32'b11111111111111110000000000000000;
#200;
writeReg = 5'b01010;
writeData = 32'b00000000000000001111111111111111;
#200;
regWrite = 1'b0;
writeReg = 5'b00000;
writeData = 32'b00000000000000000000000000000000;
#50;
readReg1 = 5'b10101;
readReg2 = 5'b01010;
// Add stimulus here
end
always #100 clock_in = ~clock_in;
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sample_iterator_get_offset (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
indices_stride_req_din,
indices_stride_req_full_n,
indices_stride_req_write,
indices_stride_rsp_empty_n,
indices_stride_rsp_read,
indices_stride_address,
indices_stride_datain,
indices_stride_dataout,
indices_stride_size,
indices_begin_req_din,
indices_begin_req_full_n,
indices_begin_req_write,
indices_begin_rsp_empty_n,
indices_begin_rsp_read,
indices_begin_address,
indices_begin_datain,
indices_begin_dataout,
indices_begin_size,
ap_ce,
i_index,
i_sample,
indices_samples_req_din,
indices_samples_req_full_n,
indices_samples_req_write,
indices_samples_rsp_empty_n,
indices_samples_rsp_read,
indices_samples_address,
indices_samples_datain,
indices_samples_dataout,
indices_samples_size,
sample_buffer_size,
sample_length,
ap_return
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output indices_stride_req_din;
input indices_stride_req_full_n;
output indices_stride_req_write;
input indices_stride_rsp_empty_n;
output indices_stride_rsp_read;
output [31:0] indices_stride_address;
input [7:0] indices_stride_datain;
output [7:0] indices_stride_dataout;
output [31:0] indices_stride_size;
output indices_begin_req_din;
input indices_begin_req_full_n;
output indices_begin_req_write;
input indices_begin_rsp_empty_n;
output indices_begin_rsp_read;
output [31:0] indices_begin_address;
input [31:0] indices_begin_datain;
output [31:0] indices_begin_dataout;
output [31:0] indices_begin_size;
input ap_ce;
input [15:0] i_index;
input [15:0] i_sample;
output indices_samples_req_din;
input indices_samples_req_full_n;
output indices_samples_req_write;
input indices_samples_rsp_empty_n;
output indices_samples_rsp_read;
output [31:0] indices_samples_address;
input [15:0] indices_samples_datain;
output [15:0] indices_samples_dataout;
output [31:0] indices_samples_size;
input [31:0] sample_buffer_size;
input [15:0] sample_length;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg indices_stride_req_write;
reg indices_stride_rsp_read;
reg indices_begin_req_write;
reg indices_begin_rsp_read;
reg [0:0] ap_CS_fsm = 1'b0;
wire ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
reg ap_reg_ppiten_pp0_it2 = 1'b0;
reg ap_reg_ppiten_pp0_it3 = 1'b0;
reg ap_reg_ppiten_pp0_it4 = 1'b0;
reg ap_reg_ppiten_pp0_it5 = 1'b0;
reg ap_reg_ppiten_pp0_it6 = 1'b0;
reg ap_reg_ppiten_pp0_it7 = 1'b0;
reg ap_reg_ppiten_pp0_it8 = 1'b0;
reg ap_reg_ppiten_pp0_it9 = 1'b0;
reg ap_reg_ppiten_pp0_it10 = 1'b0;
reg ap_reg_ppiten_pp0_it11 = 1'b0;
reg ap_reg_ppiten_pp0_it12 = 1'b0;
reg ap_reg_ppiten_pp0_it13 = 1'b0;
reg [15:0] i_sample_read_reg_130;
reg [15:0] ap_reg_ppstg_i_sample_read_reg_130_pp0_it1;
wire [31:0] tmp_fu_93_p1;
reg [31:0] tmp_reg_135;
reg [31:0] ap_reg_ppstg_tmp_reg_135_pp0_it1;
reg [31:0] ap_reg_ppstg_tmp_reg_135_pp0_it2;
reg [31:0] ap_reg_ppstg_tmp_reg_135_pp0_it3;
reg [7:0] indices_stride_addr_read_reg_145;
reg [31:0] indices_begin_addr_read_reg_165;
wire [23:0] grp_fu_110_p2;
reg [23:0] tmp_1_reg_170;
wire [15:0] grp_fu_110_p0;
wire [7:0] grp_fu_110_p1;
wire [31:0] grp_fu_125_p0;
wire [31:0] grp_fu_125_p1;
reg grp_fu_110_ce;
wire [31:0] grp_fu_125_p2;
reg grp_fu_125_ce;
reg [0:0] ap_NS_fsm;
reg ap_sig_pprstidle_pp0;
wire [23:0] grp_fu_110_p00;
wire [23:0] grp_fu_110_p10;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_pp0_stg0_fsm_0 = 1'b0;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv16_0 = 16'b0000000000000000;
parameter ap_true = 1'b1;
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 #(
.ID( 0 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 16 ),
.din1_WIDTH( 8 ),
.dout_WIDTH( 24 ))
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_110_p0 ),
.din1( grp_fu_110_p1 ),
.ce( grp_fu_110_ce ),
.dout( grp_fu_110_p2 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 #(
.ID( 1 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_125_p0 ),
.din1( grp_fu_125_p1 ),
.ce( grp_fu_125_ce ),
.dout( grp_fu_125_p2 )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end
end
end
/// ap_reg_ppiten_pp0_it10 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it10
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end
end
end
/// ap_reg_ppiten_pp0_it11 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it11
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end
end
end
/// ap_reg_ppiten_pp0_it12 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it12
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end
end
end
/// ap_reg_ppiten_pp0_it13 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it13
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end
end
end
/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end
end
end
/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end
end
end
/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130;
ap_reg_ppstg_tmp_reg_135_pp0_it1[0] <= tmp_reg_135[0];
ap_reg_ppstg_tmp_reg_135_pp0_it1[1] <= tmp_reg_135[1];
ap_reg_ppstg_tmp_reg_135_pp0_it1[2] <= tmp_reg_135[2];
ap_reg_ppstg_tmp_reg_135_pp0_it1[3] <= tmp_reg_135[3];
ap_reg_ppstg_tmp_reg_135_pp0_it1[4] <= tmp_reg_135[4];
ap_reg_ppstg_tmp_reg_135_pp0_it1[5] <= tmp_reg_135[5];
ap_reg_ppstg_tmp_reg_135_pp0_it1[6] <= tmp_reg_135[6];
ap_reg_ppstg_tmp_reg_135_pp0_it1[7] <= tmp_reg_135[7];
ap_reg_ppstg_tmp_reg_135_pp0_it1[8] <= tmp_reg_135[8];
ap_reg_ppstg_tmp_reg_135_pp0_it1[9] <= tmp_reg_135[9];
ap_reg_ppstg_tmp_reg_135_pp0_it1[10] <= tmp_reg_135[10];
ap_reg_ppstg_tmp_reg_135_pp0_it1[11] <= tmp_reg_135[11];
ap_reg_ppstg_tmp_reg_135_pp0_it1[12] <= tmp_reg_135[12];
ap_reg_ppstg_tmp_reg_135_pp0_it1[13] <= tmp_reg_135[13];
ap_reg_ppstg_tmp_reg_135_pp0_it1[14] <= tmp_reg_135[14];
ap_reg_ppstg_tmp_reg_135_pp0_it1[15] <= tmp_reg_135[15];
ap_reg_ppstg_tmp_reg_135_pp0_it2[0] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[0];
ap_reg_ppstg_tmp_reg_135_pp0_it2[1] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[1];
ap_reg_ppstg_tmp_reg_135_pp0_it2[2] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[2];
ap_reg_ppstg_tmp_reg_135_pp0_it2[3] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[3];
ap_reg_ppstg_tmp_reg_135_pp0_it2[4] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[4];
ap_reg_ppstg_tmp_reg_135_pp0_it2[5] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[5];
ap_reg_ppstg_tmp_reg_135_pp0_it2[6] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[6];
ap_reg_ppstg_tmp_reg_135_pp0_it2[7] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[7];
ap_reg_ppstg_tmp_reg_135_pp0_it2[8] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[8];
ap_reg_ppstg_tmp_reg_135_pp0_it2[9] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[9];
ap_reg_ppstg_tmp_reg_135_pp0_it2[10] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[10];
ap_reg_ppstg_tmp_reg_135_pp0_it2[11] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[11];
ap_reg_ppstg_tmp_reg_135_pp0_it2[12] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[12];
ap_reg_ppstg_tmp_reg_135_pp0_it2[13] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[13];
ap_reg_ppstg_tmp_reg_135_pp0_it2[14] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[14];
ap_reg_ppstg_tmp_reg_135_pp0_it2[15] <= ap_reg_ppstg_tmp_reg_135_pp0_it1[15];
ap_reg_ppstg_tmp_reg_135_pp0_it3[0] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[0];
ap_reg_ppstg_tmp_reg_135_pp0_it3[1] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[1];
ap_reg_ppstg_tmp_reg_135_pp0_it3[2] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[2];
ap_reg_ppstg_tmp_reg_135_pp0_it3[3] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[3];
ap_reg_ppstg_tmp_reg_135_pp0_it3[4] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[4];
ap_reg_ppstg_tmp_reg_135_pp0_it3[5] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[5];
ap_reg_ppstg_tmp_reg_135_pp0_it3[6] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[6];
ap_reg_ppstg_tmp_reg_135_pp0_it3[7] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[7];
ap_reg_ppstg_tmp_reg_135_pp0_it3[8] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[8];
ap_reg_ppstg_tmp_reg_135_pp0_it3[9] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[9];
ap_reg_ppstg_tmp_reg_135_pp0_it3[10] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[10];
ap_reg_ppstg_tmp_reg_135_pp0_it3[11] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[11];
ap_reg_ppstg_tmp_reg_135_pp0_it3[12] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[12];
ap_reg_ppstg_tmp_reg_135_pp0_it3[13] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[13];
ap_reg_ppstg_tmp_reg_135_pp0_it3[14] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[14];
ap_reg_ppstg_tmp_reg_135_pp0_it3[15] <= ap_reg_ppstg_tmp_reg_135_pp0_it2[15];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
i_sample_read_reg_130 <= i_sample;
tmp_reg_135[0] <= tmp_fu_93_p1[0];
tmp_reg_135[1] <= tmp_fu_93_p1[1];
tmp_reg_135[2] <= tmp_fu_93_p1[2];
tmp_reg_135[3] <= tmp_fu_93_p1[3];
tmp_reg_135[4] <= tmp_fu_93_p1[4];
tmp_reg_135[5] <= tmp_fu_93_p1[5];
tmp_reg_135[6] <= tmp_fu_93_p1[6];
tmp_reg_135[7] <= tmp_fu_93_p1[7];
tmp_reg_135[8] <= tmp_fu_93_p1[8];
tmp_reg_135[9] <= tmp_fu_93_p1[9];
tmp_reg_135[10] <= tmp_fu_93_p1[10];
tmp_reg_135[11] <= tmp_fu_93_p1[11];
tmp_reg_135[12] <= tmp_fu_93_p1[12];
tmp_reg_135[13] <= tmp_fu_93_p1[13];
tmp_reg_135[14] <= tmp_fu_93_p1[14];
tmp_reg_135[15] <= tmp_fu_93_p1[15];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_begin_addr_read_reg_165 <= indices_begin_datain;
tmp_1_reg_170 <= grp_fu_110_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_stride_addr_read_reg_145 <= indices_stride_datain;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it13 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) | ((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it13) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp0_it8 or ap_reg_ppiten_pp0_it9 or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp0_it12 or ap_reg_ppiten_pp0_it13)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it3) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it4) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it5) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it6) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it7) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it8) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it9) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it10) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it11) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it12) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it13))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_pprstidle_pp0 assign process. ///
always @ (ap_start or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp0_it5 or ap_reg_ppiten_pp0_it6 or ap_reg_ppiten_pp0_it7 or ap_reg_ppiten_pp0_it8 or ap_reg_ppiten_pp0_it9 or ap_reg_ppiten_pp0_it10 or ap_reg_ppiten_pp0_it11 or ap_reg_ppiten_pp0_it12)
begin
if (((ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it3) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it4) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it5) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it6) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it7) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it8) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it9) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it10) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it11) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it12) & (ap_const_logic_0 == ap_start))) begin
ap_sig_pprstidle_pp0 = ap_const_logic_1;
end else begin
ap_sig_pprstidle_pp0 = ap_const_logic_0;
end
end
/// grp_fu_110_ce assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
grp_fu_110_ce = ap_const_logic_1;
end else begin
grp_fu_110_ce = ap_const_logic_0;
end
end
/// grp_fu_125_ce assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
grp_fu_125_ce = ap_const_logic_1;
end else begin
grp_fu_125_ce = ap_const_logic_0;
end
end
/// indices_begin_req_write assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it4 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it4) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_begin_req_write = ap_const_logic_1;
end else begin
indices_begin_req_write = ap_const_logic_0;
end
end
/// indices_begin_rsp_read assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_begin_rsp_read = ap_const_logic_1;
end else begin
indices_begin_rsp_read = ap_const_logic_0;
end
end
/// indices_stride_req_write assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_stride_req_write = ap_const_logic_1;
end else begin
indices_stride_req_write = ap_const_logic_0;
end
end
/// indices_stride_rsp_read assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & (indices_stride_rsp_empty_n == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it5) & (indices_begin_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_stride_rsp_read = ap_const_logic_1;
end else begin
indices_stride_rsp_read = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it5 or indices_stride_rsp_empty_n or indices_begin_rsp_empty_n or ap_ce or ap_sig_pprstidle_pp0)
begin
case (ap_CS_fsm)
ap_ST_pp0_stg0_fsm_0 :
ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign ap_reg_ppiten_pp0_it0 = ap_start;
assign ap_return = grp_fu_125_p2;
assign grp_fu_110_p0 = grp_fu_110_p00;
assign grp_fu_110_p00 = $unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it1);
assign grp_fu_110_p1 = grp_fu_110_p10;
assign grp_fu_110_p10 = $unsigned(indices_stride_addr_read_reg_145);
assign grp_fu_125_p0 = $unsigned(tmp_1_reg_170);
assign grp_fu_125_p1 = indices_begin_addr_read_reg_165;
assign indices_begin_address = ap_reg_ppstg_tmp_reg_135_pp0_it3;
assign indices_begin_dataout = ap_const_lv32_0;
assign indices_begin_req_din = ap_const_logic_0;
assign indices_begin_size = ap_const_lv32_1;
assign indices_samples_address = ap_const_lv32_0;
assign indices_samples_dataout = ap_const_lv16_0;
assign indices_samples_req_din = ap_const_logic_0;
assign indices_samples_req_write = ap_const_logic_0;
assign indices_samples_rsp_read = ap_const_logic_0;
assign indices_samples_size = ap_const_lv32_0;
assign indices_stride_address = tmp_fu_93_p1;
assign indices_stride_dataout = ap_const_lv8_0;
assign indices_stride_req_din = ap_const_logic_0;
assign indices_stride_size = ap_const_lv32_1;
assign tmp_fu_93_p1 = $unsigned(i_index);
always @ (posedge ap_clk)
begin
tmp_reg_135[31:16] <= 16'b0000000000000000;
ap_reg_ppstg_tmp_reg_135_pp0_it1[31:16] <= 16'b0000000000000000;
ap_reg_ppstg_tmp_reg_135_pp0_it2[31:16] <= 16'b0000000000000000;
ap_reg_ppstg_tmp_reg_135_pp0_it3[31:16] <= 16'b0000000000000000;
end
endmodule //sample_iterator_get_offset
|
//====================================================================
// bsg_dff_chain.v
// 04/01/2018, [email protected]
//====================================================================
//
// Pass the input singal to a chainded DFF registers
`include "bsg_defines.v"
module bsg_dff_chain #(
//the width of the input signal
parameter `BSG_INV_PARAM( width_p )
//the stages of the chained DFF register
//can be 0
,parameter num_stages_p = 1
)
(
input clk_i
,input [width_p-1:0] data_i
,output[width_p-1:0] data_o
);
if( num_stages_p == 0) begin:pass_through
assign data_o = data_i;
end:pass_through
else begin:chained
// data_i -- delayed[0]
//
// data_o -- delayed[num_stages_p]
logic [num_stages_p:0][width_p-1:0] data_delayed;
assign data_delayed[0] = data_i ;
assign data_o = data_delayed[num_stages_p] ;
genvar i;
for(i=1; i<= num_stages_p; i++) begin
bsg_dff #( .width_p ( width_p ) )
ch_reg (
.clk_i ( clk_i )
,.data_i ( data_delayed[ i-1 ] )
,.data_o ( data_delayed[ i ] )
);
end
end:chained
endmodule
`BSG_ABSTRACT_MODULE(bsg_dff_chain)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/26 17:37:19
// Design Name:
// Module Name: add_two_values_task_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module add_two_values_task_tb(
);
reg [3:0] ain, bin;
wire [3:0] sum;
wire cout;
integer k;
add_two_values_task DUT (.x(ain), .y(bin), .cout(cout), .z(sum));
initial
begin
ain = 4'h6; bin = 4'ha;
$display("ain=%b, bin=%b, cout=%b, sum=%b at time=%t",ain, bin, cout, sum, $time);
for (k=0; k < 5; k=k+1)
begin
#5 ain = ain + k; bin = bin + k;
$display("ain=%b, bin=%b, cout=%b, sum=%b at time=%t",ain, bin, cout, sum, $time);
end
$display("Simulation Done");
end
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Intel FPGA technology mapping. User must first simulate the generated \
// > netlist before going to test it on board.
// Input buffer map
module \$__inpad (input I, output O);
cyclone10lp_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
cyclone10lp_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
cyclone10lp_lcell_comb #(.lut_mask({4{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(1'b1),
.datad(1'b1));
end else
if(WIDTH == 3) begin
cyclone10lp_lcell_comb #(.lut_mask({2{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(1'b1));
end else
if(WIDTH == 4) begin
cyclone10lp_lcell_comb #(.lut_mask(LUT),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_V
`define SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__ebufn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_BEHAVIORAL_V |
`default_nettype none
`timescale 1ns / 1ps
`include "ipl_config.vh"
// This core aims to implement a simple, reusable Wishbone B.4 compatible
// bus master. EMPHASIS ON SIMPLE -- pipelined mode can get pretty complex
// if you're not careful.
//
// Pipelined masters and slaves are really quite simple to implement overall.
// You just register the address, the bus command (read/write), and if writing,
// the data.
//
// Be careful about edge cases though. If you implement back-to-back cycles
// to two different peripherals, and your pipeline depth is different for each,
// you can get an out-of-order response which leads to read 1 getting read 2's
// data, or worse. Ultimately, since most masters are built to be generic,
// it's up to the intercon to prevent this from happening by forcing STALL_I
// on the master high until order can be preserved. But, this is getting into
// that complexity that I specifically wanted to avoid above. The simpler way
// of preventing this from happening is sticking to one, and only one, outstanding
// transaction per bus cycle: one strobe, one ack, in that order.
`include "asserts.vh"
module master_tb();
parameter ADDR_WIDTH = 16;
parameter AW = ADDR_WIDTH - 1;
reg [11:0] story_to;
reg clk_i, reset_i, fault_to;
wire [AW:0] adr_o;
wire cyc_o, stb_o, we_o;
reg ack_i;
reg dreq_i;
wire dack_o;
always begin
#5 clk_i <= ~clk_i;
end
master #(
.ADDR_WIDTH(ADDR_WIDTH)
) m(
.clk_i(clk_i),
.reset_i(reset_i),
.dreq_i(dreq_i),
.dack_o(dack_o),
.adr_o(adr_o),
.cyc_o(cyc_o),
.stb_o(stb_o),
.we_o(we_o),
.ack_i(ack_i)
);
`STANDARD_FAULT
`DEFASSERT(adr, AW, o)
`DEFASSERT0(cyc, o)
`DEFASSERT0(stb, o)
`DEFASSERT0(we, o)
`DEFASSERT0(dack, o)
initial begin
$dumpfile("master.vcd");
$dumpvars;
{ack_i, dreq_i, clk_i, reset_i, fault_to} <= 0;
wait(~clk_i); wait(clk_i);
reset_i <= 1;
wait(~clk_i); wait(clk_i);
reset_i <= 0;
story_to <= 12'h000;
wait(~clk_i); wait(clk_i); #1;
assert_adr(0);
assert_cyc(0);
assert_stb(0);
assert_we(0);
assert_dack(0);
// Given CYC_O is negated,
// When DREQ_I is asserted,
// I want CYC_O to assert
// and a valid SIA address presented
// and a read command offered.
dreq_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(0);
assert_adr(`IPL_READ_ADDR);
assert_dack(1);
// Given CYC_O is asserted,
// If DREQ_I is (still) asserted,
// I want the STB_O to negate to avoid re-reading the same address before we're ready.
dreq_i <= 0;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(0);
assert_we(0);
assert_adr(0);
assert_dack(0);
// Given CYC_O is asserted,
// and a read cycle is in progress,
// If ACK_I is asserted,
// I want the cycle to end, and the data latched for the subsequent write cycle.
ack_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(1);
assert_adr(`IPL_WRITE_ADDR);
assert_dack(0);
// Given CYC_O is asserted during a write cycle,
// If unacknowledged,
// I want the cycle to continue as-is.
ack_i <= 0;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(0);
assert_we(0);
assert_adr(0);
assert_dack(0);
// Given CYC_O is asserted during a write cycle,
// When acknowledged,
// I want the cycle to terminate.
ack_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_cyc(0);
assert_stb(0);
assert_we(0);
assert_adr(0);
assert_dack(0);
// ATTENTION: This works on my simulator (iverilog).
// UNSURE if this will work on yours or on real hardware.
//
// When we peg DREQ_I and ACK_I to an asserted state,
// I want back-to-back transactions to occur in as few cycles as possible.
// N.B.: This means 2 cycles (one read, one write).
ack_i <= 0;
wait(~clk_i); wait(clk_i);
dreq_i <= 1;
wait(~clk_i); wait(clk_i); #1;
ack_i <= 1;
assert_cyc(1);
assert_stb(1);
assert_we(0);
assert_adr(`IPL_READ_ADDR);
assert_dack(1);
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(1);
assert_adr(`IPL_WRITE_ADDR);
assert_dack(0);
wait(~clk_i); wait(clk_i); #1;
assert_cyc(1);
assert_stb(1);
assert_we(0);
assert_adr(`IPL_READ_ADDR);
assert_dack(1);
wait(~clk_i); wait(clk_i); #1;
dreq_i <= 0;
assert_cyc(1);
assert_stb(1);
assert_we(1);
assert_adr(`IPL_WRITE_ADDR);
assert_dack(0);
wait(~clk_i); wait(clk_i);
ack_i <= 0;
$display("@I Done.");
onFault;
end
endmodule
|
/**
* This module combines various status signals and outputs 3
* hex digits (for a total of 12 bits) to be displayed by the
* 7-segment display.
*
* @author Robert Fotino, 2016
*/
`include "definitions.vh"
module seg_status
(
input boot_done, // Done booting, processor can execute
input mem_calib_done, // LPDDR RAM calibration complete
input mem_error, // Bit error with LPDDR RAM
input clear_screen_done, // Done zeroing video memory
input sdcard_read_started, // Started reading from the SD card
input sdcard_read_done, // Done reading from the SD card
input sdcard_read_error, // Error reading from SD card
input [7:0] sdcard_progress, // SDC receiving progress from 0-255
input uart_load_started, // Started loading data from UART into RAM
input uart_load_done, // Done loading data from UART into RAM
input [7:0] uart_progress, // UART receiving progress from 0-255
input [11:0] processor_status, // Shown in normal operation after boot
output reg [11:0] seg_digits
);
always @ (*) begin
if (!mem_calib_done) begin
seg_digits = `STATE_MEM_UNCALIB;
end else if (mem_error) begin
seg_digits = `STATE_MEM_ERROR;
end else if (!clear_screen_done) begin
seg_digits = `STATE_CLEAR_SCREEN;
end else if (sdcard_read_error) begin
seg_digits = `STATE_SDCARD_ERROR;
end else if (sdcard_read_started && !sdcard_read_done) begin
seg_digits = `STATE_SDCARD_READ | sdcard_progress;
end else if (!boot_done) begin
seg_digits = `STATE_UART_LOAD | uart_progress;
end else begin
seg_digits = processor_status;
end
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_xlconcat_1_0 (
In0,
dout
);
input wire [0 : 0] In0;
output wire [0 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(1),
.NUM_PORTS(1)
) inst (
.In0(In0),
.In1(1'B0),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/20/2016 07:03:40 PM
// Design Name:
// Module Name: xbar
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "global.vh"
`ifdef BLESS
module xbar(
in_0,
in_1,
in_2,
in_3,
indir_rank0,
indir_rank1,
indir_rank2,
indir_rank3,
allocPV_0,
allocPV_1,
allocPV_2,
allocPV_3,
out_0,
out_1,
out_2,
out_3
);
input [`DATA_WIDTH_XBAR-1:0] in_0, in_1, in_2, in_3;
input [`PC_INDEX_WIDTH-2:0] indir_rank0, indir_rank1, indir_rank2, indir_rank3;
input [`NUM_PORT-2:0] allocPV_0, allocPV_1, allocPV_2, allocPV_3;
output [`DATA_WIDTH_XBAR-1:0] out_0, out_1, out_2, out_3;
wire [`PC_INDEX_WIDTH-2:0] sel_out [3:0]; // select an input channel to channel to an output port, based on the sorted channel index and sorted APV
assign sel_out[0] = allocPV_0 [0] ? indir_rank0 :
allocPV_1 [0] ? indir_rank1 :
allocPV_2 [0] ? indir_rank2 :
allocPV_3 [0] ? indir_rank3 :
`NULL_PC;
assign sel_out[1] = allocPV_0 [1] ? indir_rank0 :
allocPV_1 [1] ? indir_rank1 :
allocPV_2 [1] ? indir_rank2 :
allocPV_3 [1] ? indir_rank3 :
`NULL_PC;
assign sel_out[2] = allocPV_0 [2] ? indir_rank0 :
allocPV_1 [2] ? indir_rank1 :
allocPV_2 [2] ? indir_rank2 :
allocPV_3 [2] ? indir_rank3 :
`NULL_PC;
assign sel_out[3]= allocPV_0 [3] ? indir_rank0 :
allocPV_1 [3] ? indir_rank1 :
allocPV_2 [3] ? indir_rank2 :
allocPV_3 [3] ? indir_rank3 :
`NULL_PC;
genvar i;
generate
for (i=0; i<`DATA_WIDTH_XBAR; i=i+1) begin : selectOutput
mux4to1 mux_out_0 (in_0[i], in_1[i], in_2[i], in_3[i], sel_out[0], out_0[i] );
mux4to1 mux_out_1 (in_0[i], in_1[i], in_2[i], in_3[i], sel_out[1], out_1[i] );
mux4to1 mux_out_2 (in_0[i], in_1[i], in_2[i], in_3[i], sel_out[2], out_2[i] );
mux4to1 mux_out_3 (in_0[i], in_1[i], in_2[i], in_3[i], sel_out[3], out_3[i] );
end
endgenerate
endmodule
`endif // BLESS
`ifdef CARPOOL
module xbar(
in_0,
in_1,
in_2,
in_3,
indir_rank0,
indir_rank1,
indir_rank2,
indir_rank3,
allocPV_0,
allocPV_1,
allocPV_2,
allocPV_3,
out_0,
out_1,
out_2,
out_3,
apv_on_out0,
apv_on_out1,
apv_on_out2,
apv_on_out3
);
input [`DATA_WIDTH_XBAR-1:0] in_0, in_1, in_2, in_3;
input [`PC_INDEX_WIDTH-2:0] indir_rank0, indir_rank1, indir_rank2, indir_rank3;
input [`NUM_PORT-1:0] allocPV_0, allocPV_1, allocPV_2, allocPV_3;
output [`NUM_PORT-1:0] apv_on_out0, apv_on_out1, apv_on_out2, apv_on_out3;
output [`DATA_WIDTH_XBAR-1:0] out_0, out_1, out_2, out_3;
wire [`PC_INDEX_WIDTH-2:0] sel_out [3:0]; // select an input channel to channel to an output port, based on the sorted channel index and sorted APV
genvar i;
generate
assign sel_out[0] = allocPV_0 [0] ? indir_rank0 :
allocPV_1 [0] ? indir_rank1 :
allocPV_2 [0] ? indir_rank2 :
allocPV_3 [0] ? indir_rank3 :
`NULL_PC;
assign sel_out[1] = allocPV_0 [1] ? indir_rank0 :
allocPV_1 [1] ? indir_rank1 :
allocPV_2 [1] ? indir_rank2 :
allocPV_3 [1] ? indir_rank3 :
`NULL_PC;
assign sel_out[2] = allocPV_0 [2] ? indir_rank0 :
allocPV_1 [2] ? indir_rank1 :
allocPV_2 [2] ? indir_rank2 :
allocPV_3 [2] ? indir_rank3 :
`NULL_PC;
assign sel_out[3]= allocPV_0 [3] ? indir_rank0 :
allocPV_1 [3] ? indir_rank1 :
allocPV_2 [3] ? indir_rank2 :
allocPV_3 [3] ? indir_rank3 :
`NULL_PC;
endgenerate
assign apv_on_out0 = allocPV_0[0] ? allocPV_0 :
allocPV_1[0] ? allocPV_1 :
allocPV_2[0] ? allocPV_2 :
allocPV_3[0] ? allocPV_3 : 4'b0;
assign apv_on_out1 = allocPV_0[1] ? allocPV_0 :
allocPV_1[1] ? allocPV_1 :
allocPV_2[1] ? allocPV_2 :
allocPV_3[1] ? allocPV_3 : 4'b0;
assign apv_on_out2 = allocPV_0[2] ? allocPV_0 :
allocPV_1[2] ? allocPV_1 :
allocPV_2[2] ? allocPV_2 :
allocPV_3[2] ? allocPV_3 : 4'b0;
assign apv_on_out3 = allocPV_0[3] ? allocPV_0 :
allocPV_1[3] ? allocPV_1 :
allocPV_2[3] ? allocPV_2 :
allocPV_3[3] ? allocPV_3 : 4'b0;
generate
for (i=0; i<`DATA_WIDTH_XBAR; i=i+1) begin : selectOutput
mux4to1 mux_out_0 (in_0[i], in_1[i], in_2[i], in_3[i], sel_out[0], out_0[i] );
mux4to1 mux_out_1 (in_0[i], in_1[i], in_2[i], in_3[i], sel_out[1], out_1[i] );
mux4to1 mux_out_2 (in_0[i], in_1[i], in_2[i], in_3[i], sel_out[2], out_2[i] );
mux4to1 mux_out_3 (in_0[i], in_1[i], in_2[i], in_3[i], sel_out[3], out_3[i] );
end
endgenerate
endmodule
`endif //CARPOOL |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_4_V
`define SKY130_FD_SC_LP__CLKINV_4_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CONB_1_V
`define SKY130_FD_SC_HD__CONB_1_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog wrapper for conb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__conb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__conb_1 (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__conb base (
.HI(HI),
.LO(LO),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__conb_1 (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__conb base (
.HI(HI),
.LO(LO)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CONB_1_V
|
module ISpm(input clk,
input [11:0] io_core_r_addr,
input io_core_r_enable,
output[31:0] io_core_r_data_out,
input [11:0] io_core_rw_addr,
input io_core_rw_enable,
output[31:0] io_core_rw_data_out,
input io_core_rw_write,
input [31:0] io_core_rw_data_in,
input [11:0] io_bus_addr,
input io_bus_enable,
output [31:0] io_bus_data_out,
input io_bus_write,
input [31:0] io_bus_data_in,
output io_bus_ready
);
genvar i;
generate
for(i = 0; i < 8; i = i+1)
begin: BRAMS
reg [3:0] ispm [4095:0];
reg [3:0] r_data_out, rw_data_out;
always @(posedge clk) begin
if(io_core_r_enable) begin
r_data_out <= ispm[io_core_r_addr];
end
end
assign io_core_r_data_out[4*i+3:4*i] = r_data_out;
always @(posedge clk) begin
if(io_core_rw_enable) begin
if(io_core_rw_write) begin
ispm[io_core_rw_addr] <= io_core_rw_data_in[4*i+3:4*i];
end
rw_data_out <= ispm[io_core_rw_addr];
end
end
//assign io_core_rw_data_out[4*i+3:4*i] = rw_data_out;
end
endgenerate
//assign io_core_rw_data_out = 32'b0;
assign io_bus_ready = 1'b0;
//assign io_bus_data_out = 32'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NOR4_FUNCTIONAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_FUNCTIONAL_PP_V |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.28xd
// \ \ Application: netgen
// / / Filename: FFT.v
// /___/ /\ Timestamp: Fri Dec 09 21:29:31 2016
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog X:/Desktop/Project_stuff/music-fpga-master/ipcore_dir/tmp/_cg/FFT.ngc X:/Desktop/Project_stuff/music-fpga-master/ipcore_dir/tmp/_cg/FFT.v
// Device : 7z020clg484-3
// Input file : X:/Desktop/Project_stuff/music-fpga-master/ipcore_dir/tmp/_cg/FFT.ngc
// Output file : X:/Desktop/Project_stuff/music-fpga-master/ipcore_dir/tmp/_cg/FFT.v
// # of Modules : 1
// Design Name : FFT
// Xilinx : C:\Xilinx\14.2\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module FFT (
aclk, s_axis_config_tvalid, s_axis_data_tvalid, s_axis_data_tlast, s_axis_config_tready, s_axis_data_tready, m_axis_data_tvalid, m_axis_data_tlast,
event_frame_started, event_tlast_unexpected, event_tlast_missing, event_data_in_channel_halt, s_axis_config_tdata, s_axis_data_tdata,
m_axis_data_tdata, m_axis_data_tuser
)/* synthesis syn_black_box syn_noprune=1 */;
input aclk;
input s_axis_config_tvalid;
input s_axis_data_tvalid;
input s_axis_data_tlast;
output s_axis_config_tready;
output s_axis_data_tready;
output m_axis_data_tvalid;
output m_axis_data_tlast;
output event_frame_started;
output event_tlast_unexpected;
output event_tlast_missing;
output event_data_in_channel_halt;
input [7 : 0] s_axis_config_tdata;
input [31 : 0] s_axis_data_tdata;
output [31 : 0] m_axis_data_tdata;
output [7 : 0] m_axis_data_tuser;
// synthesis translate_off
wire \U0/i_synth/axi_wrapper/event_frame_started ;
wire \U0/i_synth/axi_wrapper/event_tlast_missing ;
wire \U0/i_synth/axi_wrapper/event_data_in_channel_halt_int ;
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire \NlwRenamedSig_OI_U0/i_synth/axi_wrapper/dv_resolved_prev ;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
wire sig00000101;
wire sig00000102;
wire sig00000103;
wire sig00000104;
wire sig00000105;
wire sig00000106;
wire sig00000107;
wire sig00000108;
wire sig00000109;
wire sig0000010a;
wire sig0000010b;
wire sig0000010c;
wire sig0000010d;
wire sig0000010e;
wire sig0000010f;
wire sig00000110;
wire sig00000111;
wire sig00000112;
wire sig00000113;
wire sig00000114;
wire sig00000115;
wire sig00000116;
wire sig00000117;
wire sig00000118;
wire sig00000119;
wire sig0000011a;
wire sig0000011b;
wire sig0000011c;
wire sig0000011d;
wire sig0000011e;
wire sig0000011f;
wire sig00000120;
wire sig00000121;
wire sig00000122;
wire sig00000123;
wire sig00000124;
wire sig00000125;
wire sig00000126;
wire sig00000127;
wire sig00000128;
wire sig00000129;
wire sig0000012a;
wire sig0000012b;
wire sig0000012c;
wire sig0000012d;
wire sig0000012e;
wire sig0000012f;
wire sig00000130;
wire sig00000131;
wire sig00000132;
wire sig00000133;
wire sig00000134;
wire sig00000135;
wire sig00000136;
wire sig00000137;
wire sig00000138;
wire sig00000139;
wire sig0000013a;
wire sig0000013b;
wire sig0000013c;
wire sig0000013d;
wire sig0000013e;
wire sig0000013f;
wire sig00000140;
wire sig00000141;
wire sig00000142;
wire sig00000143;
wire sig00000144;
wire sig00000145;
wire sig00000146;
wire sig00000147;
wire sig00000148;
wire sig00000149;
wire sig0000014a;
wire sig0000014b;
wire sig0000014c;
wire sig0000014d;
wire sig0000014e;
wire sig0000014f;
wire sig00000150;
wire sig00000151;
wire sig00000152;
wire sig00000153;
wire sig00000154;
wire sig00000155;
wire sig00000156;
wire sig00000157;
wire sig00000158;
wire sig00000159;
wire sig0000015a;
wire sig0000015b;
wire sig0000015c;
wire sig0000015d;
wire sig0000015e;
wire sig0000015f;
wire sig00000160;
wire sig00000161;
wire sig00000162;
wire sig00000163;
wire sig00000164;
wire sig00000165;
wire sig00000166;
wire sig00000167;
wire sig00000168;
wire sig00000169;
wire sig0000016a;
wire sig0000016b;
wire sig0000016c;
wire sig0000016d;
wire sig0000016e;
wire sig0000016f;
wire sig00000170;
wire sig00000171;
wire sig00000172;
wire sig00000173;
wire sig00000174;
wire sig00000175;
wire sig00000176;
wire sig00000177;
wire sig00000178;
wire sig00000179;
wire sig0000017a;
wire sig0000017b;
wire sig0000017c;
wire sig0000017d;
wire sig0000017e;
wire sig0000017f;
wire sig00000180;
wire sig00000181;
wire sig00000182;
wire sig00000183;
wire sig00000184;
wire sig00000185;
wire sig00000186;
wire sig00000187;
wire sig00000188;
wire sig00000189;
wire sig0000018a;
wire sig0000018b;
wire sig0000018c;
wire sig0000018d;
wire sig0000018e;
wire sig0000018f;
wire sig00000190;
wire sig00000191;
wire sig00000192;
wire sig00000193;
wire sig00000194;
wire sig00000198;
wire sig00000199;
wire sig0000019b;
wire sig0000019c;
wire sig0000019d;
wire sig000001a0;
wire sig000001ae;
wire sig000001af;
wire sig000001b0;
wire sig000001b1;
wire sig000001b2;
wire sig000001b3;
wire sig000001b4;
wire sig000001b5;
wire sig000001b6;
wire sig000001b7;
wire sig000001b8;
wire sig000001b9;
wire sig000001ba;
wire sig000001bb;
wire sig000001bc;
wire sig000001bd;
wire sig000001be;
wire sig000001bf;
wire sig000001c0;
wire sig000001c1;
wire sig000001c2;
wire sig000001c3;
wire sig000001c4;
wire sig000001c5;
wire sig000001c6;
wire sig000001c7;
wire sig000001c8;
wire sig000001c9;
wire sig000001ca;
wire sig000001cb;
wire sig000001cc;
wire sig000001cd;
wire sig000001ce;
wire sig000001cf;
wire sig000001d0;
wire sig000001d1;
wire sig000001d2;
wire sig000001d3;
wire sig000001d4;
wire sig000001d5;
wire sig000001d6;
wire sig000001d7;
wire sig000001d8;
wire sig000001d9;
wire sig000001da;
wire sig000001db;
wire sig000001dc;
wire sig000001dd;
wire sig000001de;
wire sig000001df;
wire sig000001e0;
wire sig000001e1;
wire sig000001e2;
wire sig000001e3;
wire sig000001e4;
wire sig000001e5;
wire sig000001e6;
wire sig000001e7;
wire sig000001e8;
wire sig000001e9;
wire sig000001ea;
wire sig000001eb;
wire sig000001ec;
wire sig000001ed;
wire sig000001ee;
wire sig000001ef;
wire sig000001f0;
wire sig000001f1;
wire sig000001f2;
wire sig000001f3;
wire sig000001f4;
wire sig000001f5;
wire sig000001f6;
wire sig000001f7;
wire sig000001f8;
wire sig000001f9;
wire sig000001fa;
wire sig000001fb;
wire sig000001fc;
wire sig000001fd;
wire sig000001fe;
wire sig000001ff;
wire sig00000200;
wire sig00000201;
wire sig00000202;
wire sig00000203;
wire sig00000204;
wire sig00000205;
wire sig00000206;
wire sig00000207;
wire sig00000208;
wire sig00000209;
wire sig0000020a;
wire sig0000020b;
wire sig0000020c;
wire sig0000020d;
wire sig0000020e;
wire sig0000020f;
wire sig00000210;
wire sig00000211;
wire sig00000212;
wire sig00000213;
wire sig00000214;
wire sig00000215;
wire sig00000216;
wire sig00000217;
wire sig00000218;
wire sig00000219;
wire sig0000021a;
wire sig0000021b;
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wire sig00000af9;
wire sig00000afa;
wire sig00000afb;
wire sig00000afc;
wire sig00000afd;
wire sig00000afe;
wire sig00000aff;
wire sig00000b00;
wire sig00000b01;
wire sig00000b02;
wire sig00000b03;
wire sig00000b04;
wire sig00000b05;
wire sig00000b06;
wire sig00000b07;
wire sig00000b08;
wire sig00000b09;
wire sig00000b0a;
wire sig00000b0b;
wire sig00000b0c;
wire sig00000b0d;
wire sig00000b0e;
wire sig00000b0f;
wire sig00000b10;
wire sig00000b11;
wire sig00000b12;
wire sig00000b13;
wire sig00000b14;
wire sig00000b15;
wire sig00000b16;
wire sig00000b17;
wire sig00000b18;
wire sig00000b19;
wire sig00000b1a;
wire sig00000b1b;
wire sig00000b1c;
wire sig00000b1d;
wire sig00000b1e;
wire sig00000b1f;
wire sig00000b20;
wire sig00000b21;
wire sig00000b22;
wire sig00000b23;
wire sig00000b24;
wire sig00000b25;
wire sig00000b26;
wire sig00000b27;
wire sig00000b28;
wire sig00000b29;
wire sig00000b2a;
wire sig00000b2b;
wire sig00000b2c;
wire sig00000b2d;
wire sig00000b2e;
wire sig00000b2f;
wire sig00000b30;
wire sig00000b31;
wire sig00000b32;
wire sig00000b33;
wire sig00000b34;
wire sig00000b35;
wire sig00000b36;
wire sig00000b37;
wire sig00000b38;
wire sig00000b39;
wire sig00000b3a;
wire sig00000b3b;
wire sig00000b3c;
wire sig00000b3d;
wire sig00000b3e;
wire sig00000b3f;
wire sig00000b40;
wire sig00000b41;
wire sig00000b42;
wire sig00000b43;
wire sig00000b44;
wire sig00000b45;
wire sig00000b46;
wire sig00000b47;
wire sig00000b48;
wire sig00000b49;
wire sig00000b4a;
wire sig00000b4b;
wire sig00000b4c;
wire sig00000b4d;
wire sig00000b4e;
wire sig00000b4f;
wire sig00000b50;
wire sig00000b51;
wire sig00000b52;
wire sig00000b53;
wire sig00000b54;
wire sig00000b55;
wire sig00000b56;
wire sig00000b57;
wire sig00000b58;
wire sig00000b59;
wire sig00000b5a;
wire sig00000b5b;
wire sig00000b5c;
wire sig00000b5d;
wire sig00000b5e;
wire sig00000b5f;
wire sig00000b60;
wire sig00000b61;
wire sig00000b62;
wire sig00000b63;
wire sig00000b64;
wire sig00000b65;
wire sig00000b66;
wire sig00000b67;
wire sig00000b68;
wire sig00000b69;
wire sig00000b6a;
wire sig00000b6b;
wire sig00000b6c;
wire sig00000b6d;
wire sig00000b6e;
wire sig00000b6f;
wire sig00000b70;
wire sig00000b71;
wire sig00000b72;
wire sig00000b73;
wire sig00000b74;
wire sig00000b75;
wire sig00000b76;
wire sig00000b77;
wire sig00000b78;
wire sig00000b79;
wire sig00000b7a;
wire sig00000b7b;
wire sig00000b7c;
wire sig00000b7d;
wire sig00000b7e;
wire sig00000b7f;
wire sig00000b80;
wire sig00000b81;
wire sig00000b82;
wire sig00000b83;
wire sig00000b84;
wire sig00000b85;
wire sig00000b86;
wire sig00000b87;
wire sig00000b88;
wire sig00000b89;
wire sig00000b8a;
wire sig00000b8b;
wire sig00000b8c;
wire sig00000b8d;
wire sig00000b8e;
wire sig00000b8f;
wire sig00000b90;
wire sig00000b91;
wire sig00000b92;
wire sig00000b93;
wire sig00000b94;
wire sig00000b95;
wire sig00000b96;
wire sig00000b97;
wire sig00000b98;
wire sig00000b99;
wire sig00000b9a;
wire sig00000b9b;
wire sig00000b9c;
wire sig00000b9d;
wire sig00000b9e;
wire sig00000b9f;
wire sig00000ba0;
wire sig00000ba1;
wire sig00000ba2;
wire sig00000ba3;
wire sig00000ba4;
wire sig00000ba5;
wire sig00000ba6;
wire sig00000ba7;
wire sig00000ba8;
wire sig00000ba9;
wire sig00000baa;
wire sig00000bab;
wire sig00000bac;
wire sig00000bad;
wire sig00000bae;
wire sig00000baf;
wire sig00000bb0;
wire sig00000bb1;
wire sig00000bb2;
wire sig00000bb3;
wire sig00000bb4;
wire sig00000bb5;
wire sig00000bb6;
wire sig00000bb7;
wire sig00000bb8;
wire sig00000bb9;
wire sig00000bba;
wire sig00000bbb;
wire sig00000bbc;
wire sig00000bbd;
wire sig00000bbe;
wire sig00000bbf;
wire sig00000bc0;
wire sig00000bc1;
wire sig00000bc2;
wire sig00000bc3;
wire sig00000bc4;
wire sig00000bc5;
wire sig00000bc6;
wire sig00000bc7;
wire sig00000bc8;
wire sig00000bc9;
wire sig00000bca;
wire sig00000bcb;
wire sig00000bcc;
wire sig00000bcd;
wire sig00000bce;
wire sig00000bcf;
wire sig00000bd0;
wire sig00000bd1;
wire sig00000bd2;
wire sig00000bd3;
wire sig00000bd4;
wire sig00000bd5;
wire sig00000bd6;
wire sig00000bd7;
wire sig00000bd8;
wire sig00000bd9;
wire sig00000bda;
wire sig00000bdb;
wire sig00000bdc;
wire sig00000bdd;
wire sig00000bde;
wire sig00000bdf;
wire sig00000be0;
wire sig00000be1;
wire sig00000be2;
wire sig00000be3;
wire sig00000be4;
wire sig00000be5;
wire sig00000be6;
wire sig00000be7;
wire sig00000be8;
wire sig00000be9;
wire sig00000bea;
wire sig00000beb;
wire sig00000bec;
wire sig00000bed;
wire sig00000bee;
wire sig00000bef;
wire sig00000bf0;
wire sig00000bf1;
wire sig00000bf2;
wire sig00000bf3;
wire sig00000bf4;
wire sig00000bf5;
wire sig00000bf6;
wire sig00000bf7;
wire sig00000bf8;
wire sig00000bf9;
wire sig00000bfa;
wire sig00000bfb;
wire sig00000bfc;
wire sig00000bfd;
wire sig00000bfe;
wire sig00000bff;
wire sig00000c00;
wire sig00000c01;
wire sig00000c02;
wire sig00000c03;
wire sig00000c04;
wire sig00000c05;
wire sig00000c06;
wire sig00000c07;
wire sig00000c08;
wire sig00000c09;
wire sig00000c0a;
wire sig00000c0b;
wire sig00000c0c;
wire sig00000c0d;
wire sig00000c0e;
wire sig00000c0f;
wire sig00000c10;
wire sig00000c11;
wire sig00000c12;
wire sig00000c13;
wire sig00000c14;
wire sig00000c15;
wire sig00000c16;
wire sig00000c17;
wire sig00000c18;
wire sig00000c19;
wire sig00000c1a;
wire sig00000c1b;
wire sig00000c1c;
wire sig00000c1d;
wire sig00000c1e;
wire sig00000c1f;
wire sig00000c20;
wire sig00000c21;
wire sig00000c22;
wire sig00000c23;
wire sig00000c24;
wire sig00000c25;
wire sig00000c26;
wire sig00000c27;
wire sig00000c28;
wire sig00000c29;
wire sig00000c2a;
wire sig00000c2b;
wire sig00000c2c;
wire sig00000c2d;
wire sig00000c2e;
wire sig00000c2f;
wire sig00000c30;
wire sig00000c31;
wire sig00000c32;
wire sig00000c33;
wire sig00000c34;
wire sig00000c35;
wire sig00000c36;
wire sig00000c37;
wire sig00000c38;
wire sig00000c39;
wire sig00000c3a;
wire sig00000c3b;
wire sig00000c3c;
wire sig00000c3d;
wire sig00000c3e;
wire sig00000c3f;
wire sig00000c40;
wire sig00000c41;
wire sig00000c42;
wire sig00000c43;
wire sig00000c44;
wire sig00000c45;
wire sig00000c46;
wire sig00000c47;
wire sig00000c48;
wire sig00000c49;
wire sig00000c4a;
wire sig00000c4b;
wire sig00000c4c;
wire sig00000c4d;
wire sig00000c4e;
wire sig00000c4f;
wire sig00000c50;
wire sig00000c51;
wire sig00000c52;
wire sig00000c53;
wire sig00000c54;
wire sig00000c55;
wire sig00000c56;
wire sig00000c57;
wire sig00000c58;
wire sig00000c59;
wire sig00000c5a;
wire sig00000c5b;
wire sig00000c5c;
wire sig00000c5d;
wire sig00000c5e;
wire sig00000c5f;
wire sig00000c60;
wire sig00000c61;
wire sig00000c62;
wire sig00000c63;
wire sig00000c64;
wire sig00000c65;
wire sig00000c66;
wire sig00000c67;
wire sig00000c68;
wire sig00000c69;
wire sig00000c6a;
wire sig00000c6b;
wire sig00000c6c;
wire sig00000c6d;
wire sig00000c6e;
wire sig00000c6f;
wire sig00000c70;
wire sig00000c71;
wire sig00000c72;
wire sig00000c73;
wire sig00000c74;
wire sig00000c75;
wire sig00000c76;
wire sig00000c77;
wire sig00000c78;
wire sig00000c79;
wire sig00000c7a;
wire sig00000c7b;
wire sig00000c7c;
wire sig00000c7d;
wire sig00000c7e;
wire sig00000c7f;
wire sig00000c80;
wire sig00000c81;
wire sig00000c82;
wire sig00000c83;
wire sig00000c84;
wire sig00000c85;
wire sig00000c86;
wire sig00000c87;
wire sig00000c88;
wire sig00000c89;
wire sig00000c8a;
wire sig00000c8b;
wire sig00000c8c;
wire sig00000c8d;
wire sig00000c8e;
wire sig00000c8f;
wire sig00000c90;
wire sig00000c91;
wire sig00000c92;
wire sig00000c93;
wire sig00000c94;
wire sig00000c95;
wire sig00000c96;
wire sig00000c97;
wire sig00000c98;
wire sig00000c99;
wire sig00000c9a;
wire sig00000c9b;
wire sig00000c9c;
wire sig00000c9d;
wire sig00000c9e;
wire sig00000c9f;
wire sig00000ca0;
wire sig00000ca1;
wire sig00000ca2;
wire sig00000ca3;
wire sig00000ca4;
wire sig00000ca5;
wire sig00000ca6;
wire sig00000ca7;
wire sig00000ca8;
wire sig00000ca9;
wire sig00000caa;
wire sig00000cab;
wire sig00000cac;
wire sig00000cad;
wire \blk000000dc/sig00000cb4 ;
wire \blk000000dc/sig00000cb3 ;
wire \blk000000dc/sig00000cb2 ;
wire \blk000001f6/sig00000cba ;
wire \blk000001f6/sig00000cb9 ;
wire \blk000001f6/sig00000cb8 ;
wire \blk000002a3/sig00000cc3 ;
wire \blk000002a3/sig00000cc2 ;
wire \blk000002a3/sig00000cc1 ;
wire \blk000002a3/sig00000cc0 ;
wire \blk000002aa/sig00000cc9 ;
wire \blk000002aa/sig00000cc8 ;
wire \blk000002aa/sig00000cc7 ;
wire \blk000002af/sig00000ccf ;
wire \blk000002af/sig00000cce ;
wire \blk000002af/sig00000ccd ;
wire \blk000002b4/sig00000cd5 ;
wire \blk000002b4/sig00000cd4 ;
wire \blk000002b4/sig00000cd3 ;
wire \blk000002b9/sig00000cde ;
wire \blk000002b9/sig00000cdd ;
wire \blk000002b9/sig00000cdc ;
wire \blk000002b9/sig00000cdb ;
wire \blk000002c0/sig00000ce7 ;
wire \blk000002c0/sig00000ce6 ;
wire \blk000002c0/sig00000ce5 ;
wire \blk000002c0/sig00000ce4 ;
wire \blk000003fc/sig00000ced ;
wire \blk000003fc/sig00000cec ;
wire \blk00000400/sig00000cf3 ;
wire \blk00000400/sig00000cf2 ;
wire \blk00000404/sig00000cf9 ;
wire \blk00000404/sig00000cf8 ;
wire \blk00000404/sig00000cf7 ;
wire \blk00000503/sig00000cff ;
wire \blk00000503/sig00000cfe ;
wire \blk00000503/sig00000cfd ;
wire \blk00000508/sig00000d05 ;
wire \blk00000508/sig00000d04 ;
wire \blk00000522/sig00000d2d ;
wire \blk00000522/sig00000d2c ;
wire \blk00000522/sig00000d2b ;
wire \blk00000522/sig00000d2a ;
wire \blk00000522/sig00000d29 ;
wire \blk00000522/sig00000d27 ;
wire \blk00000522/sig00000d26 ;
wire \blk00000522/sig00000d25 ;
wire \blk00000522/sig00000d24 ;
wire \blk00000522/sig00000d23 ;
wire \blk00000522/sig00000d21 ;
wire \blk00000522/sig00000d20 ;
wire \blk00000522/sig00000d1f ;
wire \blk00000522/sig00000d1e ;
wire \blk00000522/sig00000d1d ;
wire \blk00000522/sig00000d1c ;
wire \blk00000522/sig00000d1b ;
wire \blk00000522/sig00000d1a ;
wire \blk00000522/sig00000d19 ;
wire \blk00000522/sig00000d18 ;
wire \blk00000522/sig00000d17 ;
wire \blk00000522/sig00000d16 ;
wire \blk00000522/sig00000d0a ;
wire \blk00000522/sig00000d09 ;
wire \blk00000640/sig00000e36 ;
wire \blk00000640/sig00000e35 ;
wire \blk00000640/sig00000e34 ;
wire \blk00000659/sig00000e3c ;
wire \blk00000659/sig00000e3b ;
wire \blk000007cb/sig00000e42 ;
wire \blk000007cb/sig00000e41 ;
wire \blk000007cb/sig00000e40 ;
wire \blk0000083a/sig00000e48 ;
wire \blk0000083a/sig00000e47 ;
wire \blk0000083e/sig00000e4e ;
wire \blk0000083e/sig00000e4d ;
wire NLW_blk00000062_Q_UNCONNECTED;
wire NLW_blk000000e6_Q_UNCONNECTED;
wire NLW_blk000000e7_Q_UNCONNECTED;
wire NLW_blk000000e8_Q_UNCONNECTED;
wire NLW_blk000002cb_Q_UNCONNECTED;
wire NLW_blk000002cc_Q_UNCONNECTED;
wire NLW_blk000002cd_Q_UNCONNECTED;
wire NLW_blk000002ce_Q_UNCONNECTED;
wire NLW_blk000002d5_Q_UNCONNECTED;
wire NLW_blk000002d6_Q_UNCONNECTED;
wire NLW_blk00000341_O_UNCONNECTED;
wire NLW_blk00000366_O_UNCONNECTED;
wire NLW_blk00000510_O_UNCONNECTED;
wire NLW_blk00000546_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000546_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000546_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000546_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000546_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000546_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000546_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000546_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000546_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000546_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000546_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000546_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000546_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000546_P<47>_UNCONNECTED ;
wire \NLW_blk00000546_P<46>_UNCONNECTED ;
wire \NLW_blk00000546_P<45>_UNCONNECTED ;
wire \NLW_blk00000546_P<44>_UNCONNECTED ;
wire \NLW_blk00000546_P<43>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000546_PCOUT<0>_UNCONNECTED ;
wire NLW_blk00000547_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000547_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000547_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000547_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000547_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000547_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000547_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000547_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000547_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000547_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000547_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000547_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000547_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000547_P<47>_UNCONNECTED ;
wire \NLW_blk00000547_P<46>_UNCONNECTED ;
wire \NLW_blk00000547_P<45>_UNCONNECTED ;
wire \NLW_blk00000547_P<44>_UNCONNECTED ;
wire \NLW_blk00000547_P<43>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000547_PCOUT<0>_UNCONNECTED ;
wire NLW_blk00000548_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000548_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000548_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000548_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000548_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000548_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000548_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000548_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000548_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000548_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000548_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000548_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000548_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000548_P<47>_UNCONNECTED ;
wire \NLW_blk00000548_P<46>_UNCONNECTED ;
wire \NLW_blk00000548_P<45>_UNCONNECTED ;
wire \NLW_blk00000548_P<44>_UNCONNECTED ;
wire \NLW_blk00000548_P<43>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000548_PCOUT<0>_UNCONNECTED ;
wire NLW_blk000005ef_Q_UNCONNECTED;
wire NLW_blk000005f0_Q_UNCONNECTED;
wire NLW_blk000005f1_Q_UNCONNECTED;
wire NLW_blk000005f2_Q_UNCONNECTED;
wire NLW_blk000005f3_Q_UNCONNECTED;
wire NLW_blk000005f4_Q_UNCONNECTED;
wire NLW_blk000005f5_Q_UNCONNECTED;
wire NLW_blk000005f6_Q_UNCONNECTED;
wire NLW_blk00000607_Q_UNCONNECTED;
wire NLW_blk00000608_Q_UNCONNECTED;
wire NLW_blk00000609_Q_UNCONNECTED;
wire NLW_blk00000625_Q_UNCONNECTED;
wire NLW_blk00000626_Q_UNCONNECTED;
wire NLW_blk00000627_Q_UNCONNECTED;
wire NLW_blk00000628_Q_UNCONNECTED;
wire NLW_blk00000629_Q_UNCONNECTED;
wire NLW_blk0000062a_Q_UNCONNECTED;
wire NLW_blk0000062b_Q_UNCONNECTED;
wire NLW_blk0000062c_Q_UNCONNECTED;
wire NLW_blk0000063d_Q_UNCONNECTED;
wire NLW_blk0000063e_Q_UNCONNECTED;
wire NLW_blk0000063f_Q_UNCONNECTED;
wire NLW_blk0000064e_Q_UNCONNECTED;
wire NLW_blk0000064f_Q_UNCONNECTED;
wire NLW_blk00000652_R_UNCONNECTED;
wire NLW_blk000008ac_O_UNCONNECTED;
wire NLW_blk000008d1_O_UNCONNECTED;
wire NLW_blk000009c5_Q_UNCONNECTED;
wire NLW_blk000009c6_Q_UNCONNECTED;
wire NLW_blk000009c7_Q_UNCONNECTED;
wire NLW_blk000009d8_Q_UNCONNECTED;
wire NLW_blk000009d9_Q_UNCONNECTED;
wire NLW_blk000009ef_Q_UNCONNECTED;
wire NLW_blk000009f0_Q_UNCONNECTED;
wire NLW_blk000009f1_Q_UNCONNECTED;
wire NLW_blk00000a02_Q_UNCONNECTED;
wire NLW_blk00000a03_Q_UNCONNECTED;
wire NLW_blk00000a25_R_UNCONNECTED;
wire NLW_blk00000a26_Q_UNCONNECTED;
wire NLW_blk00000b84_Q15_UNCONNECTED;
wire NLW_blk00000b86_Q15_UNCONNECTED;
wire NLW_blk00000b88_Q15_UNCONNECTED;
wire NLW_blk00000b8a_Q15_UNCONNECTED;
wire NLW_blk00000b8c_Q15_UNCONNECTED;
wire NLW_blk00000b8e_Q15_UNCONNECTED;
wire NLW_blk00000b90_Q15_UNCONNECTED;
wire NLW_blk00000b92_Q15_UNCONNECTED;
wire NLW_blk00000b94_Q15_UNCONNECTED;
wire NLW_blk00000b96_Q15_UNCONNECTED;
wire NLW_blk00000b98_Q15_UNCONNECTED;
wire NLW_blk00000b9a_Q15_UNCONNECTED;
wire NLW_blk00000b9c_Q15_UNCONNECTED;
wire NLW_blk00000b9e_Q15_UNCONNECTED;
wire NLW_blk00000ba0_Q15_UNCONNECTED;
wire NLW_blk00000ba2_Q15_UNCONNECTED;
wire NLW_blk00000ba4_Q15_UNCONNECTED;
wire NLW_blk00000ba6_Q15_UNCONNECTED;
wire NLW_blk00000ba8_Q15_UNCONNECTED;
wire NLW_blk00000baa_Q15_UNCONNECTED;
wire NLW_blk00000bac_Q15_UNCONNECTED;
wire NLW_blk00000bae_Q15_UNCONNECTED;
wire NLW_blk00000bb0_Q15_UNCONNECTED;
wire NLW_blk00000bb2_Q15_UNCONNECTED;
wire NLW_blk00000bb4_Q15_UNCONNECTED;
wire NLW_blk00000bb6_Q15_UNCONNECTED;
wire NLW_blk00000bb8_Q15_UNCONNECTED;
wire NLW_blk00000bba_Q15_UNCONNECTED;
wire NLW_blk00000bbc_Q15_UNCONNECTED;
wire NLW_blk00000bbe_Q15_UNCONNECTED;
wire NLW_blk00000bc0_Q15_UNCONNECTED;
wire NLW_blk00000bc2_Q15_UNCONNECTED;
wire NLW_blk00000bc4_Q15_UNCONNECTED;
wire NLW_blk00000bc6_Q15_UNCONNECTED;
wire NLW_blk00000bc8_Q15_UNCONNECTED;
wire NLW_blk00000bca_Q15_UNCONNECTED;
wire NLW_blk00000bcc_Q15_UNCONNECTED;
wire NLW_blk00000bce_Q15_UNCONNECTED;
wire NLW_blk00000bd0_Q15_UNCONNECTED;
wire NLW_blk00000bd2_Q15_UNCONNECTED;
wire NLW_blk00000bd4_Q15_UNCONNECTED;
wire NLW_blk00000bd6_Q15_UNCONNECTED;
wire NLW_blk00000bd8_Q15_UNCONNECTED;
wire NLW_blk00000bda_Q15_UNCONNECTED;
wire NLW_blk00000bdc_Q15_UNCONNECTED;
wire NLW_blk00000bde_Q15_UNCONNECTED;
wire NLW_blk00000be0_Q15_UNCONNECTED;
wire NLW_blk00000be2_Q15_UNCONNECTED;
wire NLW_blk00000be4_Q15_UNCONNECTED;
wire NLW_blk00000be6_Q15_UNCONNECTED;
wire NLW_blk00000be8_Q15_UNCONNECTED;
wire NLW_blk00000bea_Q15_UNCONNECTED;
wire NLW_blk00000bec_Q15_UNCONNECTED;
wire NLW_blk00000bee_Q15_UNCONNECTED;
wire NLW_blk00000bf0_Q15_UNCONNECTED;
wire NLW_blk00000bf2_Q15_UNCONNECTED;
wire NLW_blk00000bf4_Q15_UNCONNECTED;
wire NLW_blk00000bf6_Q15_UNCONNECTED;
wire NLW_blk00000bf8_Q15_UNCONNECTED;
wire NLW_blk00000bfa_Q15_UNCONNECTED;
wire NLW_blk00000bfc_Q15_UNCONNECTED;
wire NLW_blk00000bfe_Q15_UNCONNECTED;
wire NLW_blk00000c00_Q15_UNCONNECTED;
wire NLW_blk00000c02_Q15_UNCONNECTED;
wire NLW_blk00000c04_Q15_UNCONNECTED;
wire NLW_blk00000c06_Q15_UNCONNECTED;
wire NLW_blk00000c08_Q15_UNCONNECTED;
wire NLW_blk00000c0a_Q15_UNCONNECTED;
wire NLW_blk00000c0c_Q15_UNCONNECTED;
wire \NLW_blk000000dc/blk000000df_Q15_UNCONNECTED ;
wire \NLW_blk000001f6/blk000001f9_Q15_UNCONNECTED ;
wire \NLW_blk000002a3/blk000002a8_Q31_UNCONNECTED ;
wire \NLW_blk000002a3/blk000002a6_Q31_UNCONNECTED ;
wire \NLW_blk000002aa/blk000002ad_Q31_UNCONNECTED ;
wire \NLW_blk000002af/blk000002b2_Q15_UNCONNECTED ;
wire \NLW_blk000002b4/blk000002b7_Q31_UNCONNECTED ;
wire \NLW_blk000002b9/blk000002be_Q31_UNCONNECTED ;
wire \NLW_blk000002b9/blk000002bc_Q31_UNCONNECTED ;
wire \NLW_blk000002c0/blk000002c5_Q31_UNCONNECTED ;
wire \NLW_blk000002c0/blk000002c3_Q31_UNCONNECTED ;
wire \NLW_blk000003fc/blk000003fe_Q15_UNCONNECTED ;
wire \NLW_blk00000400/blk00000402_Q15_UNCONNECTED ;
wire \NLW_blk00000404/blk00000407_Q15_UNCONNECTED ;
wire \NLW_blk00000503/blk00000506_Q15_UNCONNECTED ;
wire \NLW_blk00000508/blk0000050a_Q15_UNCONNECTED ;
wire \NLW_blk00000522/blk00000544_Q15_UNCONNECTED ;
wire \NLW_blk00000522/blk00000542_Q15_UNCONNECTED ;
wire \NLW_blk00000640/blk00000643_Q15_UNCONNECTED ;
wire \NLW_blk00000659/blk0000065b_Q15_UNCONNECTED ;
wire \NLW_blk000007cb/blk000007ce_Q15_UNCONNECTED ;
wire \NLW_blk0000083a/blk0000083c_Q15_UNCONNECTED ;
wire \NLW_blk0000083e/blk00000840_Q15_UNCONNECTED ;
wire [36 : 0] \U0/i_synth/axi_wrapper/data_out_channel/data_out ;
wire [0 : 0] \U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer ;
wire [1 : 1] \NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer ;
assign
m_axis_data_tdata[31] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [32],
m_axis_data_tdata[30] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [31],
m_axis_data_tdata[29] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [30],
m_axis_data_tdata[28] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [29],
m_axis_data_tdata[27] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [28],
m_axis_data_tdata[26] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [27],
m_axis_data_tdata[25] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [26],
m_axis_data_tdata[24] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [25],
m_axis_data_tdata[23] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [24],
m_axis_data_tdata[22] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [23],
m_axis_data_tdata[21] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [22],
m_axis_data_tdata[20] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [21],
m_axis_data_tdata[19] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [20],
m_axis_data_tdata[18] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [19],
m_axis_data_tdata[17] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [18],
m_axis_data_tdata[16] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [17],
m_axis_data_tdata[15] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [16],
m_axis_data_tdata[14] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [15],
m_axis_data_tdata[13] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [14],
m_axis_data_tdata[12] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [13],
m_axis_data_tdata[11] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [12],
m_axis_data_tdata[10] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [11],
m_axis_data_tdata[9] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [10],
m_axis_data_tdata[8] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [9],
m_axis_data_tdata[7] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [8],
m_axis_data_tdata[6] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [7],
m_axis_data_tdata[5] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [6],
m_axis_data_tdata[4] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [5],
m_axis_data_tdata[3] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [4],
m_axis_data_tdata[2] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [3],
m_axis_data_tdata[1] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [2],
m_axis_data_tdata[0] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [1],
m_axis_data_tuser[7] = \NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
m_axis_data_tuser[6] = \NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
m_axis_data_tuser[5] = \NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
m_axis_data_tuser[4] = \NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
m_axis_data_tuser[3] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [36],
m_axis_data_tuser[2] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [35],
m_axis_data_tuser[1] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [34],
m_axis_data_tuser[0] = \U0/i_synth/axi_wrapper/data_out_channel/data_out [33],
m_axis_data_tvalid = \NlwRenamedSig_OI_U0/i_synth/axi_wrapper/dv_resolved_prev ,
m_axis_data_tlast = \U0/i_synth/axi_wrapper/data_out_channel/data_out [0],
event_frame_started = \U0/i_synth/axi_wrapper/event_frame_started ,
event_tlast_unexpected = \U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [0],
event_tlast_missing = \U0/i_synth/axi_wrapper/event_tlast_missing ,
event_data_in_channel_halt = \U0/i_synth/axi_wrapper/event_data_in_channel_halt_int ;
VCC blk00000001 (
.P(sig00000344)
);
GND blk00000002 (
.G(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1])
);
FDR #(
.INIT ( 1'b0 ))
blk00000003 (
.C(aclk),
.D(sig00000054),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(\U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [0])
);
FDR blk00000004 (
.C(aclk),
.D(sig0000006d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000006a)
);
FDR blk00000005 (
.C(aclk),
.D(sig0000002c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000069)
);
FDE #(
.INIT ( 1'b0 ))
blk00000006 (
.C(aclk),
.CE(sig00000344),
.D(sig0000005e),
.Q(sig00000065)
);
FDR #(
.INIT ( 1'b0 ))
blk00000007 (
.C(aclk),
.D(sig00000061),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(\U0/i_synth/axi_wrapper/event_data_in_channel_halt_int )
);
FDR #(
.INIT ( 1'b0 ))
blk00000008 (
.C(aclk),
.D(sig0000005d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000066)
);
FDR #(
.INIT ( 1'b0 ))
blk00000009 (
.C(aclk),
.D(sig0000002d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000067)
);
FDS #(
.INIT ( 1'b1 ))
blk0000000a (
.C(aclk),
.D(sig0000005a),
.S(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000068)
);
FDR #(
.INIT ( 1'b0 ))
blk0000000b (
.C(aclk),
.D(sig0000005b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(\U0/i_synth/axi_wrapper/event_tlast_missing )
);
FDR #(
.INIT ( 1'b0 ))
blk0000000c (
.C(aclk),
.D(sig00000059),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(\U0/i_synth/axi_wrapper/event_frame_started )
);
FDR #(
.INIT ( 1'b0 ))
blk0000000d (
.C(aclk),
.D(sig00000001),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/dv_resolved_prev )
);
FDR #(
.INIT ( 1'b0 ))
blk0000000e (
.C(aclk),
.D(sig0000005f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000002c)
);
FDE blk0000000f (
.C(aclk),
.CE(sig0000006c),
.D(s_axis_config_tdata[4]),
.Q(sig00000031)
);
FDE blk00000010 (
.C(aclk),
.CE(sig0000006c),
.D(s_axis_config_tdata[3]),
.Q(sig00000030)
);
FDE blk00000011 (
.C(aclk),
.CE(sig0000006c),
.D(s_axis_config_tdata[2]),
.Q(sig0000002f)
);
FDE blk00000012 (
.C(aclk),
.CE(sig0000006c),
.D(s_axis_config_tdata[1]),
.Q(sig0000002e)
);
FDE blk00000013 (
.C(aclk),
.CE(sig0000006c),
.D(s_axis_config_tdata[0]),
.Q(sig0000002b)
);
FDE blk00000014 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[31]),
.Q(sig00000041)
);
FDE blk00000015 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[30]),
.Q(sig00000040)
);
FDE blk00000016 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[29]),
.Q(sig0000003f)
);
FDE blk00000017 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[28]),
.Q(sig0000003e)
);
FDE blk00000018 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[27]),
.Q(sig0000003d)
);
FDE blk00000019 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[26]),
.Q(sig0000003c)
);
FDE blk0000001a (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[25]),
.Q(sig0000003b)
);
FDE blk0000001b (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[24]),
.Q(sig0000003a)
);
FDE blk0000001c (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[23]),
.Q(sig00000039)
);
FDE blk0000001d (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[22]),
.Q(sig00000038)
);
FDE blk0000001e (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[21]),
.Q(sig00000037)
);
FDE blk0000001f (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[20]),
.Q(sig00000036)
);
FDE blk00000020 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[19]),
.Q(sig00000035)
);
FDE blk00000021 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[18]),
.Q(sig00000034)
);
FDE blk00000022 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[17]),
.Q(sig00000033)
);
FDE blk00000023 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[16]),
.Q(sig00000032)
);
FDE blk00000024 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[15]),
.Q(sig00000051)
);
FDE blk00000025 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[14]),
.Q(sig00000050)
);
FDE blk00000026 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[13]),
.Q(sig0000004f)
);
FDE blk00000027 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[12]),
.Q(sig0000004e)
);
FDE blk00000028 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[11]),
.Q(sig0000004d)
);
FDE blk00000029 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[10]),
.Q(sig0000004c)
);
FDE blk0000002a (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[9]),
.Q(sig0000004b)
);
FDE blk0000002b (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[8]),
.Q(sig0000004a)
);
FDE blk0000002c (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[7]),
.Q(sig00000049)
);
FDE blk0000002d (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[6]),
.Q(sig00000048)
);
FDE blk0000002e (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[5]),
.Q(sig00000047)
);
FDE blk0000002f (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[4]),
.Q(sig00000046)
);
FDE blk00000030 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[3]),
.Q(sig00000045)
);
FDE blk00000031 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[2]),
.Q(sig00000044)
);
FDE blk00000032 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[1]),
.Q(sig00000043)
);
FDE blk00000033 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tdata[0]),
.Q(sig00000042)
);
FDE blk00000034 (
.C(aclk),
.CE(sig0000006e),
.D(s_axis_data_tlast),
.Q(sig0000006b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000035 (
.C(aclk),
.CE(sig00000001),
.D(sig00000026),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [36])
);
FDE #(
.INIT ( 1'b0 ))
blk00000036 (
.C(aclk),
.CE(sig00000001),
.D(sig00000025),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [35])
);
FDE #(
.INIT ( 1'b0 ))
blk00000037 (
.C(aclk),
.CE(sig00000001),
.D(sig00000024),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [34])
);
FDE #(
.INIT ( 1'b0 ))
blk00000038 (
.C(aclk),
.CE(sig00000001),
.D(sig00000023),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [33])
);
FDE #(
.INIT ( 1'b0 ))
blk00000039 (
.C(aclk),
.CE(sig00000001),
.D(sig00000012),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [32])
);
FDE #(
.INIT ( 1'b0 ))
blk0000003a (
.C(aclk),
.CE(sig00000001),
.D(sig00000011),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [31])
);
FDE #(
.INIT ( 1'b0 ))
blk0000003b (
.C(aclk),
.CE(sig00000001),
.D(sig00000010),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [30])
);
FDE #(
.INIT ( 1'b0 ))
blk0000003c (
.C(aclk),
.CE(sig00000001),
.D(sig0000000f),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [29])
);
FDE #(
.INIT ( 1'b0 ))
blk0000003d (
.C(aclk),
.CE(sig00000001),
.D(sig0000000e),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [28])
);
FDE #(
.INIT ( 1'b0 ))
blk0000003e (
.C(aclk),
.CE(sig00000001),
.D(sig0000000d),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [27])
);
FDE #(
.INIT ( 1'b0 ))
blk0000003f (
.C(aclk),
.CE(sig00000001),
.D(sig0000000c),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [26])
);
FDE #(
.INIT ( 1'b0 ))
blk00000040 (
.C(aclk),
.CE(sig00000001),
.D(sig0000000b),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [25])
);
FDE #(
.INIT ( 1'b0 ))
blk00000041 (
.C(aclk),
.CE(sig00000001),
.D(sig0000000a),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [24])
);
FDE #(
.INIT ( 1'b0 ))
blk00000042 (
.C(aclk),
.CE(sig00000001),
.D(sig00000009),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [23])
);
FDE #(
.INIT ( 1'b0 ))
blk00000043 (
.C(aclk),
.CE(sig00000001),
.D(sig00000008),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [22])
);
FDE #(
.INIT ( 1'b0 ))
blk00000044 (
.C(aclk),
.CE(sig00000001),
.D(sig00000007),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [21])
);
FDE #(
.INIT ( 1'b0 ))
blk00000045 (
.C(aclk),
.CE(sig00000001),
.D(sig00000006),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [20])
);
FDE #(
.INIT ( 1'b0 ))
blk00000046 (
.C(aclk),
.CE(sig00000001),
.D(sig00000005),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [19])
);
FDE #(
.INIT ( 1'b0 ))
blk00000047 (
.C(aclk),
.CE(sig00000001),
.D(sig00000004),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [18])
);
FDE #(
.INIT ( 1'b0 ))
blk00000048 (
.C(aclk),
.CE(sig00000001),
.D(sig00000003),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [17])
);
FDE #(
.INIT ( 1'b0 ))
blk00000049 (
.C(aclk),
.CE(sig00000001),
.D(sig00000022),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [16])
);
FDE #(
.INIT ( 1'b0 ))
blk0000004a (
.C(aclk),
.CE(sig00000001),
.D(sig00000021),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [15])
);
FDE #(
.INIT ( 1'b0 ))
blk0000004b (
.C(aclk),
.CE(sig00000001),
.D(sig00000020),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [14])
);
FDE #(
.INIT ( 1'b0 ))
blk0000004c (
.C(aclk),
.CE(sig00000001),
.D(sig0000001f),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [13])
);
FDE #(
.INIT ( 1'b0 ))
blk0000004d (
.C(aclk),
.CE(sig00000001),
.D(sig0000001e),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [12])
);
FDE #(
.INIT ( 1'b0 ))
blk0000004e (
.C(aclk),
.CE(sig00000001),
.D(sig0000001d),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [11])
);
FDE #(
.INIT ( 1'b0 ))
blk0000004f (
.C(aclk),
.CE(sig00000001),
.D(sig0000001c),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [10])
);
FDE #(
.INIT ( 1'b0 ))
blk00000050 (
.C(aclk),
.CE(sig00000001),
.D(sig0000001b),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [9])
);
FDE #(
.INIT ( 1'b0 ))
blk00000051 (
.C(aclk),
.CE(sig00000001),
.D(sig0000001a),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [8])
);
FDE #(
.INIT ( 1'b0 ))
blk00000052 (
.C(aclk),
.CE(sig00000001),
.D(sig00000019),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [7])
);
FDE #(
.INIT ( 1'b0 ))
blk00000053 (
.C(aclk),
.CE(sig00000001),
.D(sig00000018),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [6])
);
FDE #(
.INIT ( 1'b0 ))
blk00000054 (
.C(aclk),
.CE(sig00000001),
.D(sig00000017),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [5])
);
FDE #(
.INIT ( 1'b0 ))
blk00000055 (
.C(aclk),
.CE(sig00000001),
.D(sig00000016),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [4])
);
FDE #(
.INIT ( 1'b0 ))
blk00000056 (
.C(aclk),
.CE(sig00000001),
.D(sig00000015),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [3])
);
FDE #(
.INIT ( 1'b0 ))
blk00000057 (
.C(aclk),
.CE(sig00000001),
.D(sig00000014),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [2])
);
FDE #(
.INIT ( 1'b0 ))
blk00000058 (
.C(aclk),
.CE(sig00000001),
.D(sig00000013),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [1])
);
FDE #(
.INIT ( 1'b0 ))
blk00000059 (
.C(aclk),
.CE(sig00000001),
.D(sig00000060),
.Q(\U0/i_synth/axi_wrapper/data_out_channel/data_out [0])
);
LUT3 #(
.INIT ( 8'hAE ))
blk0000005a (
.I0(sig00000070),
.I1(sig000000c4),
.I2(sig00000072),
.O(sig00000073)
);
MUXCY blk0000005b (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000075),
.O(sig00000074)
);
XORCY blk0000005c (
.CI(sig00000079),
.LI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig00000077)
);
MUXCY blk0000005d (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000007a),
.O(sig00000078)
);
MUXCY blk0000005e (
.CI(sig00000078),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000007b),
.O(sig00000079)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000005f (
.I0(sig000000c8),
.I1(sig00000344),
.I2(sig000000c7),
.I3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I4(sig000000c6),
.I5(sig00000344),
.O(sig0000007a)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000060 (
.I0(sig000000c5),
.I1(sig00000344),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I4(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I5(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig0000007b)
);
FDR #(
.INIT ( 1'b0 ))
blk00000061 (
.C(aclk),
.D(sig000000c4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000001)
);
FDR #(
.INIT ( 1'b0 ))
blk00000062 (
.C(aclk),
.D(sig00000070),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk00000062_Q_UNCONNECTED)
);
FD #(
.INIT ( 1'b0 ))
blk00000063 (
.C(aclk),
.D(sig000000ca),
.Q(sig00000071)
);
FDR #(
.INIT ( 1'b0 ))
blk00000064 (
.C(aclk),
.D(sig00000071),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000c2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000065 (
.C(aclk),
.CE(sig00000344),
.D(sig00000073),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000c4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000066 (
.C(aclk),
.CE(sig000000c4),
.D(sig00000077),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000076)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000067 (
.C(aclk),
.CE(sig000000c4),
.D(sig00000076),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000072)
);
FDR #(
.INIT ( 1'b0 ))
blk00000068 (
.C(aclk),
.D(sig000000c8),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000026)
);
FDR #(
.INIT ( 1'b0 ))
blk00000069 (
.C(aclk),
.D(sig000000c7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000025)
);
FDR #(
.INIT ( 1'b0 ))
blk0000006a (
.C(aclk),
.D(sig000000c6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000024)
);
FDR #(
.INIT ( 1'b0 ))
blk0000006b (
.C(aclk),
.D(sig000000c5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000023)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000006c (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000041),
.Q(sig000000ef)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000006d (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000040),
.Q(sig000000f0)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000006e (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000003f),
.Q(sig000000f1)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000006f (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000003e),
.Q(sig000000f2)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000070 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000003d),
.Q(sig000000f3)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000071 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000003c),
.Q(sig000000f4)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000072 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000003b),
.Q(sig000000f5)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000073 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000003a),
.Q(sig000000f6)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000074 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000039),
.Q(sig000000f7)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000075 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000038),
.Q(sig000000f8)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000076 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000037),
.Q(sig000000f9)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000077 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000036),
.Q(sig000000fa)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000078 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000035),
.Q(sig000000fb)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000079 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000034),
.Q(sig000000fc)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000007a (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000033),
.Q(sig000000fd)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000007b (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000032),
.Q(sig000000fe)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000007c (
.C(aclk),
.CE(sig00000344),
.D(sig000000ef),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000de)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000007d (
.C(aclk),
.CE(sig00000344),
.D(sig000000f0),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000dd)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000007e (
.C(aclk),
.CE(sig00000344),
.D(sig000000f1),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000dc)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000007f (
.C(aclk),
.CE(sig00000344),
.D(sig000000f2),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000db)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000080 (
.C(aclk),
.CE(sig00000344),
.D(sig000000f3),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000da)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000081 (
.C(aclk),
.CE(sig00000344),
.D(sig000000f4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000d9)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000082 (
.C(aclk),
.CE(sig00000344),
.D(sig000000f5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000d8)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000083 (
.C(aclk),
.CE(sig00000344),
.D(sig000000f6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000d7)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000084 (
.C(aclk),
.CE(sig00000344),
.D(sig000000f7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000d6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000085 (
.C(aclk),
.CE(sig00000344),
.D(sig000000f8),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000d5)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000086 (
.C(aclk),
.CE(sig00000344),
.D(sig000000f9),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000d4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000087 (
.C(aclk),
.CE(sig00000344),
.D(sig000000fa),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000d3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000088 (
.C(aclk),
.CE(sig00000344),
.D(sig000000fb),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000d2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000089 (
.C(aclk),
.CE(sig00000344),
.D(sig000000fc),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000d1)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000008a (
.C(aclk),
.CE(sig00000344),
.D(sig000000fd),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000d0)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000008b (
.C(aclk),
.CE(sig00000344),
.D(sig000000fe),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000cf)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000008c (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000051),
.Q(sig000000ff)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000008d (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000050),
.Q(sig00000100)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000008e (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000004f),
.Q(sig00000101)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000008f (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000004e),
.Q(sig00000102)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000090 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000004d),
.Q(sig00000103)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000091 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000004c),
.Q(sig00000104)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000092 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000004b),
.Q(sig00000105)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000093 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000004a),
.Q(sig00000106)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000094 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000049),
.Q(sig00000107)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000095 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000048),
.Q(sig00000108)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000096 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000047),
.Q(sig00000109)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000097 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000046),
.Q(sig0000010a)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000098 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000045),
.Q(sig0000010b)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000099 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000044),
.Q(sig0000010c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000009a (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000043),
.Q(sig0000010d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000009b (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000042),
.Q(sig0000010e)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000009c (
.C(aclk),
.CE(sig00000344),
.D(sig000000ff),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000ee)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000009d (
.C(aclk),
.CE(sig00000344),
.D(sig00000100),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000ed)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000009e (
.C(aclk),
.CE(sig00000344),
.D(sig00000101),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000ec)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000009f (
.C(aclk),
.CE(sig00000344),
.D(sig00000102),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000eb)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000a0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000103),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000ea)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000a1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000104),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000e9)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000a2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000105),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000e8)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000a3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000106),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000e7)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000a4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000107),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000e6)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000a5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000108),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000e5)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000a6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000109),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000e4)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000a7 (
.C(aclk),
.CE(sig00000344),
.D(sig0000010a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000e3)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000a8 (
.C(aclk),
.CE(sig00000344),
.D(sig0000010b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000e2)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000a9 (
.C(aclk),
.CE(sig00000344),
.D(sig0000010c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000e1)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000aa (
.C(aclk),
.CE(sig00000344),
.D(sig0000010d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000e0)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000ab (
.C(aclk),
.CE(sig00000344),
.D(sig0000010e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000df)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000000ac (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(sig0000002a),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I4(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I5(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig0000010f)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000000ad (
.I0(sig00000344),
.I1(sig00000027),
.I2(sig00000344),
.I3(sig00000028),
.I4(sig00000344),
.I5(sig00000029),
.O(sig00000110)
);
MUXCY blk000000ae (
.CI(sig00000112),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000010f),
.O(sig00000111)
);
MUXCY blk000000af (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000110),
.O(sig00000112)
);
XORCY blk000000b0 (
.CI(sig00000111),
.LI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig0000011b)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000000b1 (
.I0(sig0000002a),
.I1(sig00000344),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I4(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I5(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig00000113)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000000b2 (
.I0(sig00000027),
.I1(sig00000344),
.I2(sig00000028),
.I3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I4(sig00000029),
.I5(sig00000344),
.O(sig00000114)
);
MUXCY blk000000b3 (
.CI(sig00000116),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000113),
.O(sig00000115)
);
MUXCY blk000000b4 (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000114),
.O(sig00000116)
);
XORCY blk000000b5 (
.CI(sig00000115),
.LI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig00000117)
);
MUXCY blk000000b6 (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000119),
.O(sig0000011a)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000b7 (
.C(aclk),
.CE(sig00000002),
.D(sig00000118),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000121)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000b8 (
.C(aclk),
.CE(sig00000002),
.D(sig00000117),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000118)
);
FD #(
.INIT ( 1'b0 ))
blk000000b9 (
.C(aclk),
.D(sig0000011b),
.Q(sig000000ca)
);
FDE #(
.INIT ( 1'b1 ))
blk000000ba (
.C(aclk),
.CE(sig00000120),
.D(sig0000011e),
.Q(sig000000c9)
);
FDE #(
.INIT ( 1'b1 ))
blk000000bb (
.C(aclk),
.CE(sig00000120),
.D(sig00000125),
.Q(sig000000ce)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bc (
.C(aclk),
.CE(sig00000120),
.D(sig00000124),
.Q(sig000000cd)
);
FDE #(
.INIT ( 1'b1 ))
blk000000bd (
.C(aclk),
.CE(sig00000120),
.D(sig00000123),
.Q(sig000000cc)
);
FDE #(
.INIT ( 1'b0 ))
blk000000be (
.C(aclk),
.CE(sig00000120),
.D(sig00000122),
.Q(sig000000cb)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bf (
.C(aclk),
.CE(sig00000344),
.D(sig0000011c),
.Q(sig00000002)
);
FDE #(
.INIT ( 1'b1 ))
blk000000c0 (
.C(aclk),
.CE(sig0000002c),
.D(sig0000002b),
.Q(sig0000011e)
);
FD #(
.INIT ( 1'b0 ))
blk000000c1 (
.C(aclk),
.D(sig0000011d),
.Q(sig0000011f)
);
FDE #(
.INIT ( 1'b1 ))
blk000000c2 (
.C(aclk),
.CE(sig0000002c),
.D(sig00000031),
.Q(sig00000125)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c3 (
.C(aclk),
.CE(sig0000002c),
.D(sig00000030),
.Q(sig00000124)
);
FDE #(
.INIT ( 1'b1 ))
blk000000c4 (
.C(aclk),
.CE(sig0000002c),
.D(sig0000002f),
.Q(sig00000123)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c5 (
.C(aclk),
.CE(sig0000002c),
.D(sig0000002e),
.Q(sig00000122)
);
XORCY blk000000c6 (
.CI(sig0000012d),
.LI(sig0000012b),
.O(sig00000126)
);
XORCY blk000000c7 (
.CI(sig0000012e),
.LI(sig00000c4f),
.O(sig00000127)
);
XORCY blk000000c8 (
.CI(sig00000130),
.LI(sig00000c50),
.O(sig00000128)
);
MUXCY blk000000c9 (
.CI(sig0000012e),
.DI(sig00000129),
.S(sig00000c4f),
.O(sig0000012d)
);
MUXCY blk000000ca (
.CI(sig00000130),
.DI(sig0000012a),
.S(sig00000c50),
.O(sig0000012e)
);
XORCY blk000000cb (
.CI(sig0000011a),
.LI(sig00000c51),
.O(sig0000012f)
);
MUXCY blk000000cc (
.CI(sig0000011a),
.DI(sig0000012c),
.S(sig00000c51),
.O(sig00000130)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000cd (
.C(aclk),
.CE(sig00000002),
.D(sig0000012f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000027)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000ce (
.C(aclk),
.CE(sig00000002),
.D(sig00000128),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000028)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000cf (
.C(aclk),
.CE(sig00000002),
.D(sig00000127),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000029)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000d0 (
.C(aclk),
.CE(sig00000002),
.D(sig00000126),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000002a)
);
XORCY blk000000d1 (
.CI(sig00000138),
.LI(sig00000136),
.O(sig00000131)
);
XORCY blk000000d2 (
.CI(sig00000139),
.LI(sig00000c52),
.O(sig00000132)
);
XORCY blk000000d3 (
.CI(sig0000013b),
.LI(sig00000c53),
.O(sig00000133)
);
MUXCY blk000000d4 (
.CI(sig00000139),
.DI(sig00000134),
.S(sig00000c52),
.O(sig00000138)
);
MUXCY blk000000d5 (
.CI(sig0000013b),
.DI(sig00000135),
.S(sig00000c53),
.O(sig00000139)
);
XORCY blk000000d6 (
.CI(sig00000074),
.LI(sig00000c54),
.O(sig0000013a)
);
MUXCY blk000000d7 (
.CI(sig00000074),
.DI(sig00000137),
.S(sig00000c54),
.O(sig0000013b)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000d8 (
.C(aclk),
.CE(sig000000c4),
.D(sig0000013a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000c8)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000d9 (
.C(aclk),
.CE(sig000000c4),
.D(sig00000133),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000c7)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000da (
.C(aclk),
.CE(sig000000c4),
.D(sig00000132),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000c6)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000db (
.C(aclk),
.CE(sig000000c4),
.D(sig00000131),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000c5)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000000e1 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000002a),
.Q(sig0000013c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000000e2 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000029),
.Q(sig0000013d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000000e3 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000028),
.Q(sig0000013e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000000e4 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000027),
.Q(sig0000013f)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000e5 (
.C(aclk),
.CE(sig00000344),
.D(sig0000013c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000c3)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000e6 (
.C(aclk),
.CE(sig00000344),
.D(sig0000013d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000000e6_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000e7 (
.C(aclk),
.CE(sig00000344),
.D(sig0000013e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000000e7_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000e8 (
.C(aclk),
.CE(sig00000344),
.D(sig0000013f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000000e8_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000e9 (
.C(aclk),
.CE(sig00000151),
.D(sig0000014a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000208)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000ea (
.C(aclk),
.CE(sig00000151),
.D(sig00000149),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000207)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000eb (
.C(aclk),
.CE(sig00000151),
.D(sig00000148),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000206)
);
FDRE #(
.INIT ( 1'b0 ))
blk000000ec (
.C(aclk),
.CE(sig00000151),
.D(sig00000141),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000205)
);
MUXCY blk000000ed (
.CI(sig00000156),
.DI(sig00000144),
.S(sig00000c55),
.O(sig00000140)
);
XORCY blk000000ee (
.CI(sig00000156),
.LI(sig00000c55),
.O(sig00000141)
);
MUXCY blk000000ef (
.CI(sig00000140),
.DI(sig00000146),
.S(sig00000c56),
.O(sig00000142)
);
MUXCY blk000000f0 (
.CI(sig00000142),
.DI(sig00000147),
.S(sig00000c57),
.O(sig00000143)
);
XORCY blk000000f1 (
.CI(sig00000140),
.LI(sig00000c56),
.O(sig00000148)
);
XORCY blk000000f2 (
.CI(sig00000142),
.LI(sig00000c57),
.O(sig00000149)
);
XORCY blk000000f3 (
.CI(sig00000143),
.LI(sig00000145),
.O(sig0000014a)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000000f4 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000205),
.Q(sig0000014b)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000000f5 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000206),
.Q(sig0000014c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000000f6 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000207),
.Q(sig0000014d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000000f7 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000208),
.Q(sig0000014e)
);
LUT3 #(
.INIT ( 8'hAE ))
blk000000f8 (
.I0(sig00000209),
.I1(sig00000151),
.I2(sig00000150),
.O(sig00000152)
);
MUXCY blk000000f9 (
.CI(sig00000153),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000c58),
.O(sig00000154)
);
XORCY blk000000fa (
.CI(sig00000154),
.LI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig00000155)
);
MUXCY blk000000fb (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000157),
.O(sig00000156)
);
XORCY blk000000fc (
.CI(sig0000015b),
.LI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig00000159)
);
MUXCY blk000000fd (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000015c),
.O(sig0000015a)
);
MUXCY blk000000fe (
.CI(sig0000015a),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000015d),
.O(sig0000015b)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk000000ff (
.I0(sig00000205),
.I1(sig00000344),
.I2(sig00000206),
.I3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I4(sig00000207),
.I5(sig00000344),
.O(sig0000015c)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000100 (
.I0(sig00000208),
.I1(sig00000344),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I4(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I5(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig0000015d)
);
MUXCY blk00000101 (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000015f),
.O(sig0000015e)
);
MUXCY blk00000102 (
.CI(sig0000015e),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000160),
.O(sig00000153)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000103 (
.I0(sig00000205),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(sig00000206),
.I3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I4(sig00000207),
.I5(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig0000015f)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000104 (
.I0(sig00000208),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I4(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I5(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig00000160)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000105 (
.C(aclk),
.CE(sig00000344),
.D(sig0000014b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001b2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000106 (
.C(aclk),
.CE(sig00000344),
.D(sig0000014c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001b3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000107 (
.C(aclk),
.CE(sig00000344),
.D(sig0000014d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001b0)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000108 (
.C(aclk),
.CE(sig00000344),
.D(sig0000014e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001b1)
);
FDR #(
.INIT ( 1'b0 ))
blk00000109 (
.C(aclk),
.D(sig0000014f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000009d)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000010a (
.C(aclk),
.CE(sig00000344),
.D(sig00000152),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000151)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000010b (
.C(aclk),
.CE(sig00000344),
.D(sig00000155),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000204)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000010c (
.C(aclk),
.CE(sig00000151),
.D(sig00000159),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000158)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000010d (
.C(aclk),
.CE(sig00000151),
.D(sig00000158),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000150)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010e (
.C(aclk),
.CE(sig00000209),
.D(sig000000cb),
.Q(sig000001dc)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010f (
.C(aclk),
.CE(sig00000209),
.D(sig000000cc),
.Q(sig000001dd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000110 (
.C(aclk),
.CE(sig00000209),
.D(sig000000cd),
.Q(sig000001de)
);
FDE #(
.INIT ( 1'b0 ))
blk00000111 (
.C(aclk),
.CE(sig00000209),
.D(sig000000ce),
.Q(sig000001df)
);
FD #(
.INIT ( 1'b0 ))
blk00000112 (
.C(aclk),
.D(sig00000161),
.Q(sig000001e1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000113 (
.C(aclk),
.CE(sig00000209),
.D(sig000001e1),
.Q(sig00000162)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000114 (
.C(aclk),
.CE(sig00000228),
.D(sig00000218),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000020d)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000115 (
.C(aclk),
.CE(sig00000228),
.D(sig00000217),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000020c)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000116 (
.C(aclk),
.CE(sig00000228),
.D(sig00000216),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000020b)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000117 (
.C(aclk),
.CE(sig00000228),
.D(sig0000020f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000020a)
);
MUXCY blk00000118 (
.CI(sig00000223),
.DI(sig00000212),
.S(sig00000c59),
.O(sig0000020e)
);
XORCY blk00000119 (
.CI(sig00000223),
.LI(sig00000c59),
.O(sig0000020f)
);
MUXCY blk0000011a (
.CI(sig0000020e),
.DI(sig00000214),
.S(sig00000c5a),
.O(sig00000210)
);
MUXCY blk0000011b (
.CI(sig00000210),
.DI(sig00000215),
.S(sig00000c5b),
.O(sig00000211)
);
XORCY blk0000011c (
.CI(sig0000020e),
.LI(sig00000c5a),
.O(sig00000216)
);
XORCY blk0000011d (
.CI(sig00000210),
.LI(sig00000c5b),
.O(sig00000217)
);
XORCY blk0000011e (
.CI(sig00000211),
.LI(sig00000213),
.O(sig00000218)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000011f (
.I0(sig0000020d),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I4(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I5(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig00000219)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000120 (
.I0(sig0000020a),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(sig0000020b),
.I3(sig00000344),
.I4(sig0000020c),
.I5(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig0000021a)
);
MUXCY blk00000121 (
.CI(sig0000021b),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000219),
.O(sig00000226)
);
MUXCY blk00000122 (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000021a),
.O(sig0000021b)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000123 (
.I0(sig0000020d),
.I1(sig00000344),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I4(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I5(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig0000021c)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000124 (
.I0(sig0000020a),
.I1(sig00000344),
.I2(sig0000020b),
.I3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I4(sig0000020c),
.I5(sig00000344),
.O(sig0000021d)
);
MUXCY blk00000125 (
.CI(sig0000021f),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000021c),
.O(sig0000021e)
);
MUXCY blk00000126 (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000021d),
.O(sig0000021f)
);
XORCY blk00000127 (
.CI(sig0000021e),
.LI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig00000220)
);
MUXCY blk00000128 (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000222),
.O(sig00000223)
);
XORCY blk00000129 (
.CI(sig00000225),
.LI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig00000224)
);
MUXCY blk0000012a (
.CI(sig00000226),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000c5c),
.O(sig00000225)
);
LUT3 #(
.INIT ( 8'hAE ))
blk0000012b (
.I0(sig000000c2),
.I1(sig00000228),
.I2(sig00000229),
.O(sig00000227)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000012c (
.C(aclk),
.CE(sig00000228),
.D(sig00000221),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000229)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000012d (
.C(aclk),
.CE(sig00000228),
.D(sig00000220),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000221)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000012e (
.C(aclk),
.CE(sig00000344),
.D(sig00000224),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000209)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000012f (
.C(aclk),
.CE(sig00000344),
.D(sig00000227),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000228)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000130 (
.I0(sig0000029f),
.I1(sig0000027d),
.I2(sig000002c0),
.O(sig0000022a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000131 (
.I0(sig000002a0),
.I1(sig0000027e),
.I2(sig000002c0),
.O(sig0000022b)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000132 (
.I0(sig000002a1),
.I1(sig0000027f),
.I2(sig000002c0),
.O(sig0000022c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000133 (
.I0(sig000002a2),
.I1(sig00000280),
.I2(sig000002c0),
.O(sig0000022d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000134 (
.I0(sig000002a3),
.I1(sig00000281),
.I2(sig000002c0),
.O(sig0000022e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000135 (
.I0(sig000002a4),
.I1(sig00000282),
.I2(sig000002c0),
.O(sig0000022f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000136 (
.I0(sig000002a5),
.I1(sig00000283),
.I2(sig000002c0),
.O(sig00000230)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000137 (
.I0(sig000002a6),
.I1(sig00000284),
.I2(sig000002c0),
.O(sig00000231)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000138 (
.I0(sig000002a7),
.I1(sig00000285),
.I2(sig000002c0),
.O(sig00000232)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000139 (
.I0(sig000002a8),
.I1(sig00000286),
.I2(sig000002c0),
.O(sig00000233)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000013a (
.I0(sig000002a9),
.I1(sig00000287),
.I2(sig000002c0),
.O(sig00000234)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000013b (
.I0(sig000002aa),
.I1(sig00000288),
.I2(sig000002c0),
.O(sig00000235)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000013c (
.I0(sig000002ab),
.I1(sig00000289),
.I2(sig000002c0),
.O(sig00000236)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000013d (
.I0(sig000002ac),
.I1(sig0000028a),
.I2(sig000002c0),
.O(sig00000237)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000013e (
.I0(sig000002ad),
.I1(sig0000028b),
.I2(sig000002c0),
.O(sig00000238)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000013f (
.I0(sig000002ae),
.I1(sig0000028c),
.I2(sig000002c0),
.O(sig00000239)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000140 (
.I0(sig000002af),
.I1(sig0000028d),
.I2(sig000002c0),
.O(sig0000023a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000141 (
.I0(sig0000027d),
.I1(sig0000029f),
.I2(sig000002c0),
.O(sig0000023b)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000142 (
.I0(sig0000027e),
.I1(sig000002a0),
.I2(sig000002c0),
.O(sig0000023c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000143 (
.I0(sig0000027f),
.I1(sig000002a1),
.I2(sig000002c0),
.O(sig0000023d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000144 (
.I0(sig00000280),
.I1(sig000002a2),
.I2(sig000002c0),
.O(sig0000023e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000145 (
.I0(sig00000281),
.I1(sig000002a3),
.I2(sig000002c0),
.O(sig0000023f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000146 (
.I0(sig00000282),
.I1(sig000002a4),
.I2(sig000002c0),
.O(sig00000240)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000147 (
.I0(sig00000283),
.I1(sig000002a5),
.I2(sig000002c0),
.O(sig00000241)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000148 (
.I0(sig00000284),
.I1(sig000002a6),
.I2(sig000002c0),
.O(sig00000242)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000149 (
.I0(sig00000285),
.I1(sig000002a7),
.I2(sig000002c0),
.O(sig00000243)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000014a (
.I0(sig00000286),
.I1(sig000002a8),
.I2(sig000002c0),
.O(sig00000244)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000014b (
.I0(sig00000287),
.I1(sig000002a9),
.I2(sig000002c0),
.O(sig00000245)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000014c (
.I0(sig00000288),
.I1(sig000002aa),
.I2(sig000002c0),
.O(sig00000246)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000014d (
.I0(sig00000289),
.I1(sig000002ab),
.I2(sig000002c0),
.O(sig00000247)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000014e (
.I0(sig0000028a),
.I1(sig000002ac),
.I2(sig000002c0),
.O(sig00000248)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000014f (
.I0(sig0000028b),
.I1(sig000002ad),
.I2(sig000002c0),
.O(sig00000249)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000150 (
.I0(sig0000028c),
.I1(sig000002ae),
.I2(sig000002c0),
.O(sig0000024a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000151 (
.I0(sig0000028d),
.I1(sig000002af),
.I2(sig000002c0),
.O(sig0000024b)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000152 (
.I0(sig000000df),
.I1(sig000002c3),
.I2(sig000000c3),
.O(sig0000024c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000153 (
.I0(sig000000e0),
.I1(sig000002c4),
.I2(sig000000c3),
.O(sig0000024d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000154 (
.I0(sig000000e1),
.I1(sig000002c5),
.I2(sig000000c3),
.O(sig0000024e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000155 (
.I0(sig000000e2),
.I1(sig000002c6),
.I2(sig000000c3),
.O(sig0000024f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000156 (
.I0(sig000000e3),
.I1(sig000002c7),
.I2(sig000000c3),
.O(sig00000250)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000157 (
.I0(sig000000e4),
.I1(sig000002c8),
.I2(sig000000c3),
.O(sig00000251)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000158 (
.I0(sig000000e5),
.I1(sig000002c9),
.I2(sig000000c3),
.O(sig00000252)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000159 (
.I0(sig000000e6),
.I1(sig000002ca),
.I2(sig000000c3),
.O(sig00000253)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000015a (
.I0(sig000000e7),
.I1(sig000002cb),
.I2(sig000000c3),
.O(sig00000254)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000015b (
.I0(sig000000e8),
.I1(sig000002cc),
.I2(sig000000c3),
.O(sig00000255)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000015c (
.I0(sig000000e9),
.I1(sig000002cd),
.I2(sig000000c3),
.O(sig00000256)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000015d (
.I0(sig000000ea),
.I1(sig000002ce),
.I2(sig000000c3),
.O(sig00000257)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000015e (
.I0(sig000000eb),
.I1(sig000002cf),
.I2(sig000000c3),
.O(sig00000258)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000015f (
.I0(sig000000ec),
.I1(sig000002d0),
.I2(sig000000c3),
.O(sig00000259)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000160 (
.I0(sig000000ed),
.I1(sig000002d1),
.I2(sig000000c3),
.O(sig0000025a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000161 (
.I0(sig000000ee),
.I1(sig000002d2),
.I2(sig000000c3),
.O(sig0000025b)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000162 (
.I0(sig000002c3),
.I1(sig000000df),
.I2(sig000000c3),
.O(sig0000025c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000163 (
.I0(sig000002c4),
.I1(sig000000e0),
.I2(sig000000c3),
.O(sig0000025d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000164 (
.I0(sig000002c5),
.I1(sig000000e1),
.I2(sig000000c3),
.O(sig0000025e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000165 (
.I0(sig000002c6),
.I1(sig000000e2),
.I2(sig000000c3),
.O(sig0000025f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000166 (
.I0(sig000002c7),
.I1(sig000000e3),
.I2(sig000000c3),
.O(sig00000260)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000167 (
.I0(sig000002c8),
.I1(sig000000e4),
.I2(sig000000c3),
.O(sig00000261)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000168 (
.I0(sig000002c9),
.I1(sig000000e5),
.I2(sig000000c3),
.O(sig00000262)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000169 (
.I0(sig000002ca),
.I1(sig000000e6),
.I2(sig000000c3),
.O(sig00000263)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000016a (
.I0(sig000002cb),
.I1(sig000000e7),
.I2(sig000000c3),
.O(sig00000264)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000016b (
.I0(sig000002cc),
.I1(sig000000e8),
.I2(sig000000c3),
.O(sig00000265)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000016c (
.I0(sig000002cd),
.I1(sig000000e9),
.I2(sig000000c3),
.O(sig00000266)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000016d (
.I0(sig000002ce),
.I1(sig000000ea),
.I2(sig000000c3),
.O(sig00000267)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000016e (
.I0(sig000002cf),
.I1(sig000000eb),
.I2(sig000000c3),
.O(sig00000268)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000016f (
.I0(sig000002d0),
.I1(sig000000ec),
.I2(sig000000c3),
.O(sig00000269)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000170 (
.I0(sig000002d1),
.I1(sig000000ed),
.I2(sig000000c3),
.O(sig0000026a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000171 (
.I0(sig000002d2),
.I1(sig000000ee),
.I2(sig000000c3),
.O(sig0000026b)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000172 (
.C(aclk),
.CE(sig00000344),
.D(sig0000022a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000026c)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000173 (
.C(aclk),
.CE(sig00000344),
.D(sig0000022b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000026d)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000174 (
.C(aclk),
.CE(sig00000344),
.D(sig0000022c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000026e)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000175 (
.C(aclk),
.CE(sig00000344),
.D(sig0000022d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000026f)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000176 (
.C(aclk),
.CE(sig00000344),
.D(sig0000022e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000270)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000177 (
.C(aclk),
.CE(sig00000344),
.D(sig0000022f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000271)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000178 (
.C(aclk),
.CE(sig00000344),
.D(sig00000230),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000272)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000179 (
.C(aclk),
.CE(sig00000344),
.D(sig00000231),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000273)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000017a (
.C(aclk),
.CE(sig00000344),
.D(sig00000232),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000274)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000017b (
.C(aclk),
.CE(sig00000344),
.D(sig00000233),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000275)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000017c (
.C(aclk),
.CE(sig00000344),
.D(sig00000234),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000276)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000017d (
.C(aclk),
.CE(sig00000344),
.D(sig00000235),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000277)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000017e (
.C(aclk),
.CE(sig00000344),
.D(sig00000236),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000278)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000017f (
.C(aclk),
.CE(sig00000344),
.D(sig00000237),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000279)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000180 (
.C(aclk),
.CE(sig00000344),
.D(sig00000238),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000027a)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000181 (
.C(aclk),
.CE(sig00000344),
.D(sig00000239),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000027b)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000182 (
.C(aclk),
.CE(sig00000344),
.D(sig0000023a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000027c)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000183 (
.C(aclk),
.CE(sig00000344),
.D(sig0000023b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001e2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000184 (
.C(aclk),
.CE(sig00000344),
.D(sig0000023c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001e3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000185 (
.C(aclk),
.CE(sig00000344),
.D(sig0000023d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001e4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000186 (
.C(aclk),
.CE(sig00000344),
.D(sig0000023e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001e5)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000187 (
.C(aclk),
.CE(sig00000344),
.D(sig0000023f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001e6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000188 (
.C(aclk),
.CE(sig00000344),
.D(sig00000240),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001e7)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000189 (
.C(aclk),
.CE(sig00000344),
.D(sig00000241),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001e8)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000018a (
.C(aclk),
.CE(sig00000344),
.D(sig00000242),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001e9)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000018b (
.C(aclk),
.CE(sig00000344),
.D(sig00000243),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001ea)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000018c (
.C(aclk),
.CE(sig00000344),
.D(sig00000244),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001eb)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000018d (
.C(aclk),
.CE(sig00000344),
.D(sig00000245),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001ec)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000018e (
.C(aclk),
.CE(sig00000344),
.D(sig00000246),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001ed)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000018f (
.C(aclk),
.CE(sig00000344),
.D(sig00000247),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001ee)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000190 (
.C(aclk),
.CE(sig00000344),
.D(sig00000248),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001ef)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000191 (
.C(aclk),
.CE(sig00000344),
.D(sig00000249),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001f0)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000192 (
.C(aclk),
.CE(sig00000344),
.D(sig0000024a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001f1)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000193 (
.C(aclk),
.CE(sig00000344),
.D(sig0000024b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001f2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000194 (
.C(aclk),
.CE(sig00000344),
.D(sig000002c2),
.Q(sig000002c1)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000195 (
.C(aclk),
.CE(sig00000344),
.D(sig0000024c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002e3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000196 (
.C(aclk),
.CE(sig00000344),
.D(sig0000024d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002e4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000197 (
.C(aclk),
.CE(sig00000344),
.D(sig0000024e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002e5)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000198 (
.C(aclk),
.CE(sig00000344),
.D(sig0000024f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002e6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000199 (
.C(aclk),
.CE(sig00000344),
.D(sig00000250),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002e7)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000019a (
.C(aclk),
.CE(sig00000344),
.D(sig00000251),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002e8)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000019b (
.C(aclk),
.CE(sig00000344),
.D(sig00000252),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002e9)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000019c (
.C(aclk),
.CE(sig00000344),
.D(sig00000253),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002ea)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000019d (
.C(aclk),
.CE(sig00000344),
.D(sig00000254),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002eb)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000019e (
.C(aclk),
.CE(sig00000344),
.D(sig00000255),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002ec)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000019f (
.C(aclk),
.CE(sig00000344),
.D(sig00000256),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002ed)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001a0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000257),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002ee)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001a1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000258),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002ef)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001a2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000259),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002f0)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001a3 (
.C(aclk),
.CE(sig00000344),
.D(sig0000025a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002f1)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001a4 (
.C(aclk),
.CE(sig00000344),
.D(sig0000025b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002f2)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001a5 (
.C(aclk),
.CE(sig00000344),
.D(sig0000025c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002d3)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001a6 (
.C(aclk),
.CE(sig00000344),
.D(sig0000025d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002d4)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001a7 (
.C(aclk),
.CE(sig00000344),
.D(sig0000025e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002d5)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001a8 (
.C(aclk),
.CE(sig00000344),
.D(sig0000025f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002d6)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001a9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000260),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002d7)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001aa (
.C(aclk),
.CE(sig00000344),
.D(sig00000261),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002d8)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001ab (
.C(aclk),
.CE(sig00000344),
.D(sig00000262),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002d9)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001ac (
.C(aclk),
.CE(sig00000344),
.D(sig00000263),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002da)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001ad (
.C(aclk),
.CE(sig00000344),
.D(sig00000264),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002db)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001ae (
.C(aclk),
.CE(sig00000344),
.D(sig00000265),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002dc)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001af (
.C(aclk),
.CE(sig00000344),
.D(sig00000266),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002dd)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001b0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000267),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002de)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001b1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000268),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002df)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001b2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000269),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002e0)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001b3 (
.C(aclk),
.CE(sig00000344),
.D(sig0000026a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002e1)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001b4 (
.C(aclk),
.CE(sig00000344),
.D(sig0000026b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002e2)
);
FDE #(
.INIT ( 1'b0 ))
blk000001b5 (
.C(aclk),
.CE(sig00000344),
.D(sig000000c3),
.Q(sig000002c2)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001b6 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002f2),
.Q(sig000002f3)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001b7 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002f1),
.Q(sig000002f4)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001b8 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002f0),
.Q(sig000002f5)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001b9 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002ef),
.Q(sig000002f6)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001ba (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002ee),
.Q(sig000002f7)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001bb (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002ed),
.Q(sig000002f8)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001bc (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002ec),
.Q(sig000002f9)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001bd (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002eb),
.Q(sig000002fa)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001be (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002ea),
.Q(sig000002fb)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001bf (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002e9),
.Q(sig000002fc)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001c0 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002e8),
.Q(sig000002fd)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001c1 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002e7),
.Q(sig000002fe)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001c2 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002e6),
.Q(sig000002ff)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001c3 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002e5),
.Q(sig00000300)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001c4 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002e4),
.Q(sig00000301)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001c5 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000002e3),
.Q(sig00000302)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001c6 (
.C(aclk),
.CE(sig00000344),
.D(sig000002f3),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002bf)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001c7 (
.C(aclk),
.CE(sig00000344),
.D(sig000002f4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002be)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001c8 (
.C(aclk),
.CE(sig00000344),
.D(sig000002f5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002bd)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001c9 (
.C(aclk),
.CE(sig00000344),
.D(sig000002f6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002bc)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001ca (
.C(aclk),
.CE(sig00000344),
.D(sig000002f7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002bb)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001cb (
.C(aclk),
.CE(sig00000344),
.D(sig000002f8),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002ba)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001cc (
.C(aclk),
.CE(sig00000344),
.D(sig000002f9),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002b9)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001cd (
.C(aclk),
.CE(sig00000344),
.D(sig000002fa),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002b8)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001ce (
.C(aclk),
.CE(sig00000344),
.D(sig000002fb),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002b7)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001cf (
.C(aclk),
.CE(sig00000344),
.D(sig000002fc),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002b6)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001d0 (
.C(aclk),
.CE(sig00000344),
.D(sig000002fd),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002b5)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001d1 (
.C(aclk),
.CE(sig00000344),
.D(sig000002fe),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002b4)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001d2 (
.C(aclk),
.CE(sig00000344),
.D(sig000002ff),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002b3)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001d3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000300),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002b2)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001d4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000301),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002b1)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001d5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000302),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002b0)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001d6 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000de),
.Q(sig00000303)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001d7 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000dd),
.Q(sig00000304)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001d8 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000dc),
.Q(sig00000305)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001d9 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000db),
.Q(sig00000306)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001da (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000da),
.Q(sig00000307)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001db (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000d9),
.Q(sig00000308)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001dc (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000d8),
.Q(sig00000309)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001dd (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000d7),
.Q(sig0000030a)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001de (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000d6),
.Q(sig0000030b)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001df (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000d5),
.Q(sig0000030c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001e0 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000d4),
.Q(sig0000030d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001e1 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000d3),
.Q(sig0000030e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001e2 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000d2),
.Q(sig0000030f)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001e3 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000d1),
.Q(sig00000310)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001e4 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000d0),
.Q(sig00000311)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000001e5 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000cf),
.Q(sig00000312)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001e6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000303),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002d2)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001e7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000304),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002d1)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001e8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000305),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002d0)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001e9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000306),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002cf)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001ea (
.C(aclk),
.CE(sig00000344),
.D(sig00000307),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002ce)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001eb (
.C(aclk),
.CE(sig00000344),
.D(sig00000308),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002cd)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001ec (
.C(aclk),
.CE(sig00000344),
.D(sig00000309),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002cc)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001ed (
.C(aclk),
.CE(sig00000344),
.D(sig0000030a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002cb)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001ee (
.C(aclk),
.CE(sig00000344),
.D(sig0000030b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002ca)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001ef (
.C(aclk),
.CE(sig00000344),
.D(sig0000030c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002c9)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001f0 (
.C(aclk),
.CE(sig00000344),
.D(sig0000030d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002c8)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001f1 (
.C(aclk),
.CE(sig00000344),
.D(sig0000030e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002c7)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001f2 (
.C(aclk),
.CE(sig00000344),
.D(sig0000030f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002c6)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001f3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000310),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002c5)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001f4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000311),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002c4)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001f5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000312),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000002c3)
);
XORCY blk000001fb (
.CI(sig00000334),
.LI(sig00000324),
.O(sig00000313)
);
XORCY blk000001fc (
.CI(sig00000335),
.LI(sig00000c5d),
.O(sig00000314)
);
XORCY blk000001fd (
.CI(sig00000336),
.LI(sig00000325),
.O(sig00000315)
);
XORCY blk000001fe (
.CI(sig00000337),
.LI(sig00000326),
.O(sig00000316)
);
XORCY blk000001ff (
.CI(sig00000338),
.LI(sig00000327),
.O(sig00000317)
);
XORCY blk00000200 (
.CI(sig00000339),
.LI(sig00000328),
.O(sig00000318)
);
XORCY blk00000201 (
.CI(sig0000033a),
.LI(sig00000329),
.O(sig00000319)
);
XORCY blk00000202 (
.CI(sig0000033b),
.LI(sig0000032a),
.O(sig0000031a)
);
XORCY blk00000203 (
.CI(sig0000033c),
.LI(sig0000032b),
.O(sig0000031b)
);
XORCY blk00000204 (
.CI(sig0000033d),
.LI(sig0000032c),
.O(sig0000031c)
);
XORCY blk00000205 (
.CI(sig0000033e),
.LI(sig0000032d),
.O(sig0000031d)
);
XORCY blk00000206 (
.CI(sig0000033f),
.LI(sig0000032e),
.O(sig0000031e)
);
XORCY blk00000207 (
.CI(sig00000340),
.LI(sig0000032f),
.O(sig0000031f)
);
XORCY blk00000208 (
.CI(sig00000341),
.LI(sig00000330),
.O(sig00000320)
);
XORCY blk00000209 (
.CI(sig00000342),
.LI(sig00000331),
.O(sig00000321)
);
XORCY blk0000020a (
.CI(sig00000343),
.LI(sig00000332),
.O(sig00000322)
);
XORCY blk0000020b (
.CI(sig00000344),
.LI(sig00000333),
.O(sig00000323)
);
MUXCY blk0000020c (
.CI(sig00000335),
.DI(sig000002bf),
.S(sig00000c5d),
.O(sig00000334)
);
MUXCY blk0000020d (
.CI(sig00000336),
.DI(sig000002be),
.S(sig00000325),
.O(sig00000335)
);
MUXCY blk0000020e (
.CI(sig00000337),
.DI(sig000002bd),
.S(sig00000326),
.O(sig00000336)
);
MUXCY blk0000020f (
.CI(sig00000338),
.DI(sig000002bc),
.S(sig00000327),
.O(sig00000337)
);
MUXCY blk00000210 (
.CI(sig00000339),
.DI(sig000002bb),
.S(sig00000328),
.O(sig00000338)
);
MUXCY blk00000211 (
.CI(sig0000033a),
.DI(sig000002ba),
.S(sig00000329),
.O(sig00000339)
);
MUXCY blk00000212 (
.CI(sig0000033b),
.DI(sig000002b9),
.S(sig0000032a),
.O(sig0000033a)
);
MUXCY blk00000213 (
.CI(sig0000033c),
.DI(sig000002b8),
.S(sig0000032b),
.O(sig0000033b)
);
MUXCY blk00000214 (
.CI(sig0000033d),
.DI(sig000002b7),
.S(sig0000032c),
.O(sig0000033c)
);
MUXCY blk00000215 (
.CI(sig0000033e),
.DI(sig000002b6),
.S(sig0000032d),
.O(sig0000033d)
);
MUXCY blk00000216 (
.CI(sig0000033f),
.DI(sig000002b5),
.S(sig0000032e),
.O(sig0000033e)
);
MUXCY blk00000217 (
.CI(sig00000340),
.DI(sig000002b4),
.S(sig0000032f),
.O(sig0000033f)
);
MUXCY blk00000218 (
.CI(sig00000341),
.DI(sig000002b3),
.S(sig00000330),
.O(sig00000340)
);
MUXCY blk00000219 (
.CI(sig00000342),
.DI(sig000002b2),
.S(sig00000331),
.O(sig00000341)
);
MUXCY blk0000021a (
.CI(sig00000343),
.DI(sig000002b1),
.S(sig00000332),
.O(sig00000342)
);
MUXCY blk0000021b (
.CI(sig00000344),
.DI(sig000002b0),
.S(sig00000333),
.O(sig00000343)
);
XORCY blk0000021c (
.CI(sig00000366),
.LI(sig00000356),
.O(sig00000345)
);
XORCY blk0000021d (
.CI(sig00000367),
.LI(sig00000c5e),
.O(sig00000346)
);
XORCY blk0000021e (
.CI(sig00000368),
.LI(sig00000357),
.O(sig00000347)
);
XORCY blk0000021f (
.CI(sig00000369),
.LI(sig00000358),
.O(sig00000348)
);
XORCY blk00000220 (
.CI(sig0000036a),
.LI(sig00000359),
.O(sig00000349)
);
XORCY blk00000221 (
.CI(sig0000036b),
.LI(sig0000035a),
.O(sig0000034a)
);
XORCY blk00000222 (
.CI(sig0000036c),
.LI(sig0000035b),
.O(sig0000034b)
);
XORCY blk00000223 (
.CI(sig0000036d),
.LI(sig0000035c),
.O(sig0000034c)
);
XORCY blk00000224 (
.CI(sig0000036e),
.LI(sig0000035d),
.O(sig0000034d)
);
XORCY blk00000225 (
.CI(sig0000036f),
.LI(sig0000035e),
.O(sig0000034e)
);
XORCY blk00000226 (
.CI(sig00000370),
.LI(sig0000035f),
.O(sig0000034f)
);
XORCY blk00000227 (
.CI(sig00000371),
.LI(sig00000360),
.O(sig00000350)
);
XORCY blk00000228 (
.CI(sig00000372),
.LI(sig00000361),
.O(sig00000351)
);
XORCY blk00000229 (
.CI(sig00000373),
.LI(sig00000362),
.O(sig00000352)
);
XORCY blk0000022a (
.CI(sig00000374),
.LI(sig00000363),
.O(sig00000353)
);
XORCY blk0000022b (
.CI(sig00000375),
.LI(sig00000364),
.O(sig00000354)
);
XORCY blk0000022c (
.CI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.LI(sig00000365),
.O(sig00000355)
);
MUXCY blk0000022d (
.CI(sig00000367),
.DI(sig000002bf),
.S(sig00000c5e),
.O(sig00000366)
);
MUXCY blk0000022e (
.CI(sig00000368),
.DI(sig000002be),
.S(sig00000357),
.O(sig00000367)
);
MUXCY blk0000022f (
.CI(sig00000369),
.DI(sig000002bd),
.S(sig00000358),
.O(sig00000368)
);
MUXCY blk00000230 (
.CI(sig0000036a),
.DI(sig000002bc),
.S(sig00000359),
.O(sig00000369)
);
MUXCY blk00000231 (
.CI(sig0000036b),
.DI(sig000002bb),
.S(sig0000035a),
.O(sig0000036a)
);
MUXCY blk00000232 (
.CI(sig0000036c),
.DI(sig000002ba),
.S(sig0000035b),
.O(sig0000036b)
);
MUXCY blk00000233 (
.CI(sig0000036d),
.DI(sig000002b9),
.S(sig0000035c),
.O(sig0000036c)
);
MUXCY blk00000234 (
.CI(sig0000036e),
.DI(sig000002b8),
.S(sig0000035d),
.O(sig0000036d)
);
MUXCY blk00000235 (
.CI(sig0000036f),
.DI(sig000002b7),
.S(sig0000035e),
.O(sig0000036e)
);
MUXCY blk00000236 (
.CI(sig00000370),
.DI(sig000002b6),
.S(sig0000035f),
.O(sig0000036f)
);
MUXCY blk00000237 (
.CI(sig00000371),
.DI(sig000002b5),
.S(sig00000360),
.O(sig00000370)
);
MUXCY blk00000238 (
.CI(sig00000372),
.DI(sig000002b4),
.S(sig00000361),
.O(sig00000371)
);
MUXCY blk00000239 (
.CI(sig00000373),
.DI(sig000002b3),
.S(sig00000362),
.O(sig00000372)
);
MUXCY blk0000023a (
.CI(sig00000374),
.DI(sig000002b2),
.S(sig00000363),
.O(sig00000373)
);
MUXCY blk0000023b (
.CI(sig00000375),
.DI(sig000002b1),
.S(sig00000364),
.O(sig00000374)
);
MUXCY blk0000023c (
.CI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.DI(sig000002b0),
.S(sig00000365),
.O(sig00000375)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023d (
.C(aclk),
.CE(sig00000344),
.D(sig00000345),
.Q(sig000002af)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023e (
.C(aclk),
.CE(sig00000344),
.D(sig00000346),
.Q(sig000002ae)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023f (
.C(aclk),
.CE(sig00000344),
.D(sig00000347),
.Q(sig000002ad)
);
FDE #(
.INIT ( 1'b0 ))
blk00000240 (
.C(aclk),
.CE(sig00000344),
.D(sig00000348),
.Q(sig000002ac)
);
FDE #(
.INIT ( 1'b0 ))
blk00000241 (
.C(aclk),
.CE(sig00000344),
.D(sig00000349),
.Q(sig000002ab)
);
FDE #(
.INIT ( 1'b0 ))
blk00000242 (
.C(aclk),
.CE(sig00000344),
.D(sig0000034a),
.Q(sig000002aa)
);
FDE #(
.INIT ( 1'b0 ))
blk00000243 (
.C(aclk),
.CE(sig00000344),
.D(sig0000034b),
.Q(sig000002a9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000244 (
.C(aclk),
.CE(sig00000344),
.D(sig0000034c),
.Q(sig000002a8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000245 (
.C(aclk),
.CE(sig00000344),
.D(sig0000034d),
.Q(sig000002a7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000246 (
.C(aclk),
.CE(sig00000344),
.D(sig0000034e),
.Q(sig000002a6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000247 (
.C(aclk),
.CE(sig00000344),
.D(sig0000034f),
.Q(sig000002a5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000248 (
.C(aclk),
.CE(sig00000344),
.D(sig00000350),
.Q(sig000002a4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000249 (
.C(aclk),
.CE(sig00000344),
.D(sig00000351),
.Q(sig000002a3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024a (
.C(aclk),
.CE(sig00000344),
.D(sig00000352),
.Q(sig000002a2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024b (
.C(aclk),
.CE(sig00000344),
.D(sig00000353),
.Q(sig000002a1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024c (
.C(aclk),
.CE(sig00000344),
.D(sig00000354),
.Q(sig000002a0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024d (
.C(aclk),
.CE(sig00000344),
.D(sig00000355),
.Q(sig0000029f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024e (
.C(aclk),
.CE(sig00000344),
.D(sig00000313),
.Q(sig0000029e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024f (
.C(aclk),
.CE(sig00000344),
.D(sig00000314),
.Q(sig0000029d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000250 (
.C(aclk),
.CE(sig00000344),
.D(sig00000315),
.Q(sig0000029c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000251 (
.C(aclk),
.CE(sig00000344),
.D(sig00000316),
.Q(sig0000029b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000252 (
.C(aclk),
.CE(sig00000344),
.D(sig00000317),
.Q(sig0000029a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000253 (
.C(aclk),
.CE(sig00000344),
.D(sig00000318),
.Q(sig00000299)
);
FDE #(
.INIT ( 1'b0 ))
blk00000254 (
.C(aclk),
.CE(sig00000344),
.D(sig00000319),
.Q(sig00000298)
);
FDE #(
.INIT ( 1'b0 ))
blk00000255 (
.C(aclk),
.CE(sig00000344),
.D(sig0000031a),
.Q(sig00000297)
);
FDE #(
.INIT ( 1'b0 ))
blk00000256 (
.C(aclk),
.CE(sig00000344),
.D(sig0000031b),
.Q(sig00000296)
);
FDE #(
.INIT ( 1'b0 ))
blk00000257 (
.C(aclk),
.CE(sig00000344),
.D(sig0000031c),
.Q(sig00000295)
);
FDE #(
.INIT ( 1'b0 ))
blk00000258 (
.C(aclk),
.CE(sig00000344),
.D(sig0000031d),
.Q(sig00000294)
);
FDE #(
.INIT ( 1'b0 ))
blk00000259 (
.C(aclk),
.CE(sig00000344),
.D(sig0000031e),
.Q(sig00000293)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025a (
.C(aclk),
.CE(sig00000344),
.D(sig0000031f),
.Q(sig00000292)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025b (
.C(aclk),
.CE(sig00000344),
.D(sig00000320),
.Q(sig00000291)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025c (
.C(aclk),
.CE(sig00000344),
.D(sig00000321),
.Q(sig00000290)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025d (
.C(aclk),
.CE(sig00000344),
.D(sig00000322),
.Q(sig0000028f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025e (
.C(aclk),
.CE(sig00000344),
.D(sig00000323),
.Q(sig0000028e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000025f (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000027c),
.Q(sig00000376)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000260 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000027b),
.Q(sig00000377)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000261 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000027a),
.Q(sig00000378)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000262 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000279),
.Q(sig00000379)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000263 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000278),
.Q(sig0000037a)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000264 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000277),
.Q(sig0000037b)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000265 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000276),
.Q(sig0000037c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000266 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000275),
.Q(sig0000037d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000267 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000274),
.Q(sig0000037e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000268 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000273),
.Q(sig0000037f)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000269 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000272),
.Q(sig00000380)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000026a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000271),
.Q(sig00000381)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000026b (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000270),
.Q(sig00000382)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000026c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000026f),
.Q(sig00000383)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000026d (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000026e),
.Q(sig00000384)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000026e (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000026d),
.Q(sig00000385)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000026f (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000026c),
.Q(sig00000386)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000270 (
.C(aclk),
.CE(sig00000344),
.D(sig00000376),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000203)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000271 (
.C(aclk),
.CE(sig00000344),
.D(sig00000377),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000202)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000272 (
.C(aclk),
.CE(sig00000344),
.D(sig00000378),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000201)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000273 (
.C(aclk),
.CE(sig00000344),
.D(sig00000379),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000200)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000274 (
.C(aclk),
.CE(sig00000344),
.D(sig0000037a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001ff)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000275 (
.C(aclk),
.CE(sig00000344),
.D(sig0000037b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001fe)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000276 (
.C(aclk),
.CE(sig00000344),
.D(sig0000037c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001fd)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000277 (
.C(aclk),
.CE(sig00000344),
.D(sig0000037d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001fc)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000278 (
.C(aclk),
.CE(sig00000344),
.D(sig0000037e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001fb)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000279 (
.C(aclk),
.CE(sig00000344),
.D(sig0000037f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001fa)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000027a (
.C(aclk),
.CE(sig00000344),
.D(sig00000380),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001f9)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000027b (
.C(aclk),
.CE(sig00000344),
.D(sig00000381),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001f8)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000027c (
.C(aclk),
.CE(sig00000344),
.D(sig00000382),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001f7)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000027d (
.C(aclk),
.CE(sig00000344),
.D(sig00000383),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001f6)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000027e (
.C(aclk),
.CE(sig00000344),
.D(sig00000384),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001f5)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000027f (
.C(aclk),
.CE(sig00000344),
.D(sig00000385),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001f4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000280 (
.C(aclk),
.CE(sig00000344),
.D(sig00000386),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001f3)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000281 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000029e),
.Q(sig00000387)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000282 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000029d),
.Q(sig00000388)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000283 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000029c),
.Q(sig00000389)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000284 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000029b),
.Q(sig0000038a)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000285 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000029a),
.Q(sig0000038b)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000286 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000299),
.Q(sig0000038c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000287 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000298),
.Q(sig0000038d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000288 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000297),
.Q(sig0000038e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000289 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000296),
.Q(sig0000038f)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000028a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000295),
.Q(sig00000390)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000028b (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000294),
.Q(sig00000391)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000028c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000293),
.Q(sig00000392)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000028d (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000292),
.Q(sig00000393)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000028e (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000291),
.Q(sig00000394)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000028f (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000290),
.Q(sig00000395)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000290 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000028f),
.Q(sig00000396)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000291 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000028e),
.Q(sig00000397)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000292 (
.C(aclk),
.CE(sig00000344),
.D(sig00000387),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000028d)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000293 (
.C(aclk),
.CE(sig00000344),
.D(sig00000388),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000028c)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000294 (
.C(aclk),
.CE(sig00000344),
.D(sig00000389),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000028b)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000295 (
.C(aclk),
.CE(sig00000344),
.D(sig0000038a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000028a)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000296 (
.C(aclk),
.CE(sig00000344),
.D(sig0000038b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000289)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000297 (
.C(aclk),
.CE(sig00000344),
.D(sig0000038c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000288)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000298 (
.C(aclk),
.CE(sig00000344),
.D(sig0000038d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000287)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000299 (
.C(aclk),
.CE(sig00000344),
.D(sig0000038e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000286)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000029a (
.C(aclk),
.CE(sig00000344),
.D(sig0000038f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000285)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000029b (
.C(aclk),
.CE(sig00000344),
.D(sig00000390),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000284)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000029c (
.C(aclk),
.CE(sig00000344),
.D(sig00000391),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000283)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000029d (
.C(aclk),
.CE(sig00000344),
.D(sig00000392),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000282)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000029e (
.C(aclk),
.CE(sig00000344),
.D(sig00000393),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000281)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000029f (
.C(aclk),
.CE(sig00000344),
.D(sig00000394),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000280)
);
FDRE #(
.INIT ( 1'b0 ))
blk000002a0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000395),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000027f)
);
FDRE #(
.INIT ( 1'b0 ))
blk000002a1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000396),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000027e)
);
FDRE #(
.INIT ( 1'b0 ))
blk000002a2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000397),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000027d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000002c7 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000208),
.Q(sig00000398)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000002c8 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000207),
.Q(sig00000399)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000002c9 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000206),
.Q(sig0000039a)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000002ca (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000205),
.Q(sig0000039b)
);
FDRE #(
.INIT ( 1'b0 ))
blk000002cb (
.C(aclk),
.CE(sig00000344),
.D(sig00000398),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000002cb_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000002cc (
.C(aclk),
.CE(sig00000344),
.D(sig00000399),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000002cc_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000002cd (
.C(aclk),
.CE(sig00000344),
.D(sig0000039a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000002cd_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000002ce (
.C(aclk),
.CE(sig00000344),
.D(sig0000039b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000002ce_Q_UNCONNECTED)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000002cf (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000020d),
.Q(sig0000039c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000002d0 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000020c),
.Q(sig0000039d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000002d1 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000020b),
.Q(sig0000039e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000002d2 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000020a),
.Q(sig0000039f)
);
FDRE #(
.INIT ( 1'b0 ))
blk000002d3 (
.C(aclk),
.CE(sig00000344),
.D(sig0000039c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001d9)
);
FDRE #(
.INIT ( 1'b0 ))
blk000002d4 (
.C(aclk),
.CE(sig00000344),
.D(sig0000039d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001d8)
);
FDRE #(
.INIT ( 1'b0 ))
blk000002d5 (
.C(aclk),
.CE(sig00000344),
.D(sig0000039e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000002d5_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000002d6 (
.C(aclk),
.CE(sig00000344),
.D(sig0000039f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000002d6_Q_UNCONNECTED)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002d7 (
.I0(sig00000455),
.I1(sig000004e5),
.I2(sig00000530),
.O(sig000003a0)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002d8 (
.I0(sig00000456),
.I1(sig000004e6),
.I2(sig00000530),
.O(sig000003a1)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002d9 (
.I0(sig00000457),
.I1(sig000004e7),
.I2(sig00000530),
.O(sig000003a2)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002da (
.I0(sig00000458),
.I1(sig000004e8),
.I2(sig00000530),
.O(sig000003a3)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002db (
.I0(sig00000459),
.I1(sig000004e9),
.I2(sig00000530),
.O(sig000003a4)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002dc (
.I0(sig0000045a),
.I1(sig000004ea),
.I2(sig00000530),
.O(sig000003a5)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002dd (
.I0(sig0000045b),
.I1(sig000004eb),
.I2(sig00000530),
.O(sig000003a6)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002de (
.I0(sig0000045c),
.I1(sig000004ec),
.I2(sig00000530),
.O(sig000003a7)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002df (
.I0(sig0000045d),
.I1(sig000004ed),
.I2(sig00000530),
.O(sig000003a8)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002e0 (
.I0(sig0000045e),
.I1(sig000004ee),
.I2(sig00000530),
.O(sig000003a9)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002e1 (
.I0(sig0000045f),
.I1(sig000004ef),
.I2(sig00000530),
.O(sig000003aa)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002e2 (
.I0(sig00000460),
.I1(sig000004f0),
.I2(sig00000530),
.O(sig000003ab)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002e3 (
.I0(sig00000461),
.I1(sig000004f1),
.I2(sig00000530),
.O(sig000003ac)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002e4 (
.I0(sig00000462),
.I1(sig000004f2),
.I2(sig00000530),
.O(sig000003ad)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002e5 (
.I0(sig00000463),
.I1(sig000004f3),
.I2(sig00000530),
.O(sig000003ae)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002e6 (
.I0(sig00000464),
.I1(sig000004f4),
.I2(sig00000530),
.O(sig000003af)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002e7 (
.I0(sig00000465),
.I1(sig000004f5),
.I2(sig00000530),
.O(sig000003b0)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002e8 (
.I0(sig00000466),
.I1(sig000004f6),
.I2(sig00000530),
.O(sig000003b1)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002e9 (
.I0(sig000004e5),
.I1(sig00000455),
.I2(sig00000530),
.O(sig000003b2)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002ea (
.I0(sig000004e6),
.I1(sig00000456),
.I2(sig00000530),
.O(sig000003b3)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002eb (
.I0(sig000004e7),
.I1(sig00000457),
.I2(sig00000530),
.O(sig000003b4)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002ec (
.I0(sig000004e8),
.I1(sig00000458),
.I2(sig00000530),
.O(sig000003b5)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002ed (
.I0(sig000004e9),
.I1(sig00000459),
.I2(sig00000530),
.O(sig000003b6)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002ee (
.I0(sig000004ea),
.I1(sig0000045a),
.I2(sig00000530),
.O(sig000003b7)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002ef (
.I0(sig000004eb),
.I1(sig0000045b),
.I2(sig00000530),
.O(sig000003b8)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002f0 (
.I0(sig000004ec),
.I1(sig0000045c),
.I2(sig00000530),
.O(sig000003b9)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002f1 (
.I0(sig000004ed),
.I1(sig0000045d),
.I2(sig00000530),
.O(sig000003ba)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002f2 (
.I0(sig000004ee),
.I1(sig0000045e),
.I2(sig00000530),
.O(sig000003bb)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002f3 (
.I0(sig000004ef),
.I1(sig0000045f),
.I2(sig00000530),
.O(sig000003bc)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002f4 (
.I0(sig000004f0),
.I1(sig00000460),
.I2(sig00000530),
.O(sig000003bd)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002f5 (
.I0(sig000004f1),
.I1(sig00000461),
.I2(sig00000530),
.O(sig000003be)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002f6 (
.I0(sig000004f2),
.I1(sig00000462),
.I2(sig00000530),
.O(sig000003bf)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002f7 (
.I0(sig000004f3),
.I1(sig00000463),
.I2(sig00000530),
.O(sig000003c0)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002f8 (
.I0(sig000004f4),
.I1(sig00000464),
.I2(sig00000530),
.O(sig000003c1)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002f9 (
.I0(sig000004f5),
.I1(sig00000465),
.I2(sig00000530),
.O(sig000003c2)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002fa (
.I0(sig000004f6),
.I1(sig00000466),
.I2(sig00000530),
.O(sig000003c3)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002fb (
.I0(sig000004af),
.I1(sig0000048b),
.I2(sig0000052e),
.O(sig000003c4)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002fc (
.I0(sig000004b0),
.I1(sig0000048c),
.I2(sig0000052e),
.O(sig000003c5)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002fd (
.I0(sig000004b1),
.I1(sig0000048d),
.I2(sig0000052e),
.O(sig000003c6)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002fe (
.I0(sig000004b2),
.I1(sig0000048e),
.I2(sig0000052e),
.O(sig000003c7)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000002ff (
.I0(sig000004b3),
.I1(sig0000048f),
.I2(sig0000052e),
.O(sig000003c8)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000300 (
.I0(sig000004b4),
.I1(sig00000490),
.I2(sig0000052e),
.O(sig000003c9)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000301 (
.I0(sig000004b5),
.I1(sig00000491),
.I2(sig0000052e),
.O(sig000003ca)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000302 (
.I0(sig000004b6),
.I1(sig00000492),
.I2(sig0000052e),
.O(sig000003cb)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000303 (
.I0(sig000004b7),
.I1(sig00000493),
.I2(sig0000052e),
.O(sig000003cc)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000304 (
.I0(sig000004b8),
.I1(sig00000494),
.I2(sig0000052e),
.O(sig000003cd)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000305 (
.I0(sig000004b9),
.I1(sig00000495),
.I2(sig0000052e),
.O(sig000003ce)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000306 (
.I0(sig000004ba),
.I1(sig00000496),
.I2(sig0000052e),
.O(sig000003cf)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000307 (
.I0(sig000004bb),
.I1(sig00000497),
.I2(sig0000052e),
.O(sig000003d0)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000308 (
.I0(sig000004bc),
.I1(sig00000498),
.I2(sig0000052e),
.O(sig000003d1)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000309 (
.I0(sig000004bd),
.I1(sig00000499),
.I2(sig0000052e),
.O(sig000003d2)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000030a (
.I0(sig000004be),
.I1(sig0000049a),
.I2(sig0000052e),
.O(sig000003d3)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000030b (
.I0(sig000004bf),
.I1(sig0000049b),
.I2(sig0000052e),
.O(sig000003d4)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000030c (
.I0(sig000004c0),
.I1(sig0000049c),
.I2(sig0000052e),
.O(sig000003d5)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000030d (
.I0(sig0000048b),
.I1(sig000004af),
.I2(sig0000052e),
.O(sig000003d6)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000030e (
.I0(sig0000048c),
.I1(sig000004b0),
.I2(sig0000052e),
.O(sig000003d7)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000030f (
.I0(sig0000048d),
.I1(sig000004b1),
.I2(sig0000052e),
.O(sig000003d8)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000310 (
.I0(sig0000048e),
.I1(sig000004b2),
.I2(sig0000052e),
.O(sig000003d9)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000311 (
.I0(sig0000048f),
.I1(sig000004b3),
.I2(sig0000052e),
.O(sig000003da)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000312 (
.I0(sig00000490),
.I1(sig000004b4),
.I2(sig0000052e),
.O(sig000003db)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000313 (
.I0(sig00000491),
.I1(sig000004b5),
.I2(sig0000052e),
.O(sig000003dc)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000314 (
.I0(sig00000492),
.I1(sig000004b6),
.I2(sig0000052e),
.O(sig000003dd)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000315 (
.I0(sig00000493),
.I1(sig000004b7),
.I2(sig0000052e),
.O(sig000003de)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000316 (
.I0(sig00000494),
.I1(sig000004b8),
.I2(sig0000052e),
.O(sig000003df)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000317 (
.I0(sig00000495),
.I1(sig000004b9),
.I2(sig0000052e),
.O(sig000003e0)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000318 (
.I0(sig00000496),
.I1(sig000004ba),
.I2(sig0000052e),
.O(sig000003e1)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000319 (
.I0(sig00000497),
.I1(sig000004bb),
.I2(sig0000052e),
.O(sig000003e2)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000031a (
.I0(sig00000498),
.I1(sig000004bc),
.I2(sig0000052e),
.O(sig000003e3)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000031b (
.I0(sig00000499),
.I1(sig000004bd),
.I2(sig0000052e),
.O(sig000003e4)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000031c (
.I0(sig0000049a),
.I1(sig000004be),
.I2(sig0000052e),
.O(sig000003e5)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000031d (
.I0(sig0000049b),
.I1(sig000004bf),
.I2(sig0000052e),
.O(sig000003e6)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000031e (
.I0(sig0000049c),
.I1(sig000004c0),
.I2(sig0000052e),
.O(sig000003e7)
);
MUXCY blk0000031f (
.CI(sig0000041d),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003e8),
.O(sig000003fa)
);
XORCY blk00000320 (
.CI(sig0000041d),
.LI(sig000003e8),
.O(sig000003fb)
);
MUXCY blk00000321 (
.CI(sig000003fa),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003e9),
.O(sig000003fc)
);
XORCY blk00000322 (
.CI(sig000003fa),
.LI(sig000003e9),
.O(sig000003fd)
);
MUXCY blk00000323 (
.CI(sig000003fc),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003ea),
.O(sig000003fe)
);
XORCY blk00000324 (
.CI(sig000003fc),
.LI(sig000003ea),
.O(sig000003ff)
);
MUXCY blk00000325 (
.CI(sig000003fe),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003eb),
.O(sig00000400)
);
XORCY blk00000326 (
.CI(sig000003fe),
.LI(sig000003eb),
.O(sig00000401)
);
MUXCY blk00000327 (
.CI(sig00000400),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003ec),
.O(sig00000402)
);
XORCY blk00000328 (
.CI(sig00000400),
.LI(sig000003ec),
.O(sig00000403)
);
MUXCY blk00000329 (
.CI(sig00000402),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003ed),
.O(sig00000404)
);
XORCY blk0000032a (
.CI(sig00000402),
.LI(sig000003ed),
.O(sig00000405)
);
MUXCY blk0000032b (
.CI(sig00000404),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003ee),
.O(sig00000406)
);
XORCY blk0000032c (
.CI(sig00000404),
.LI(sig000003ee),
.O(sig00000407)
);
MUXCY blk0000032d (
.CI(sig00000406),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003ef),
.O(sig00000408)
);
XORCY blk0000032e (
.CI(sig00000406),
.LI(sig000003ef),
.O(sig00000409)
);
MUXCY blk0000032f (
.CI(sig00000408),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003f0),
.O(sig0000040a)
);
XORCY blk00000330 (
.CI(sig00000408),
.LI(sig000003f0),
.O(sig0000040b)
);
MUXCY blk00000331 (
.CI(sig0000040a),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003f1),
.O(sig0000040c)
);
XORCY blk00000332 (
.CI(sig0000040a),
.LI(sig000003f1),
.O(sig0000040d)
);
MUXCY blk00000333 (
.CI(sig0000040c),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003f2),
.O(sig0000040e)
);
XORCY blk00000334 (
.CI(sig0000040c),
.LI(sig000003f2),
.O(sig0000040f)
);
MUXCY blk00000335 (
.CI(sig0000040e),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003f3),
.O(sig00000410)
);
XORCY blk00000336 (
.CI(sig0000040e),
.LI(sig000003f3),
.O(sig00000411)
);
MUXCY blk00000337 (
.CI(sig00000410),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003f4),
.O(sig00000412)
);
XORCY blk00000338 (
.CI(sig00000410),
.LI(sig000003f4),
.O(sig00000413)
);
MUXCY blk00000339 (
.CI(sig00000412),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003f5),
.O(sig00000414)
);
XORCY blk0000033a (
.CI(sig00000412),
.LI(sig000003f5),
.O(sig00000415)
);
MUXCY blk0000033b (
.CI(sig00000414),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003f6),
.O(sig00000416)
);
XORCY blk0000033c (
.CI(sig00000414),
.LI(sig000003f6),
.O(sig00000417)
);
MUXCY blk0000033d (
.CI(sig00000416),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003f7),
.O(sig00000418)
);
XORCY blk0000033e (
.CI(sig00000416),
.LI(sig000003f7),
.O(sig00000419)
);
MUXCY blk0000033f (
.CI(sig00000418),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000c5f),
.O(sig0000041a)
);
XORCY blk00000340 (
.CI(sig00000418),
.LI(sig00000c5f),
.O(sig0000041b)
);
MUXCY blk00000341 (
.CI(sig0000041a),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003f8),
.O(NLW_blk00000341_O_UNCONNECTED)
);
XORCY blk00000342 (
.CI(sig0000041a),
.LI(sig000003f8),
.O(sig0000041c)
);
MUXCY blk00000343 (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000003f9),
.O(sig0000041d)
);
MUXCY blk00000344 (
.CI(sig00000453),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000041e),
.O(sig00000430)
);
XORCY blk00000345 (
.CI(sig00000453),
.LI(sig0000041e),
.O(sig00000431)
);
MUXCY blk00000346 (
.CI(sig00000430),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000041f),
.O(sig00000432)
);
XORCY blk00000347 (
.CI(sig00000430),
.LI(sig0000041f),
.O(sig00000433)
);
MUXCY blk00000348 (
.CI(sig00000432),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000420),
.O(sig00000434)
);
XORCY blk00000349 (
.CI(sig00000432),
.LI(sig00000420),
.O(sig00000435)
);
MUXCY blk0000034a (
.CI(sig00000434),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000421),
.O(sig00000436)
);
XORCY blk0000034b (
.CI(sig00000434),
.LI(sig00000421),
.O(sig00000437)
);
MUXCY blk0000034c (
.CI(sig00000436),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000422),
.O(sig00000438)
);
XORCY blk0000034d (
.CI(sig00000436),
.LI(sig00000422),
.O(sig00000439)
);
MUXCY blk0000034e (
.CI(sig00000438),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000423),
.O(sig0000043a)
);
XORCY blk0000034f (
.CI(sig00000438),
.LI(sig00000423),
.O(sig0000043b)
);
MUXCY blk00000350 (
.CI(sig0000043a),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000424),
.O(sig0000043c)
);
XORCY blk00000351 (
.CI(sig0000043a),
.LI(sig00000424),
.O(sig0000043d)
);
MUXCY blk00000352 (
.CI(sig0000043c),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000425),
.O(sig0000043e)
);
XORCY blk00000353 (
.CI(sig0000043c),
.LI(sig00000425),
.O(sig0000043f)
);
MUXCY blk00000354 (
.CI(sig0000043e),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000426),
.O(sig00000440)
);
XORCY blk00000355 (
.CI(sig0000043e),
.LI(sig00000426),
.O(sig00000441)
);
MUXCY blk00000356 (
.CI(sig00000440),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000427),
.O(sig00000442)
);
XORCY blk00000357 (
.CI(sig00000440),
.LI(sig00000427),
.O(sig00000443)
);
MUXCY blk00000358 (
.CI(sig00000442),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000428),
.O(sig00000444)
);
XORCY blk00000359 (
.CI(sig00000442),
.LI(sig00000428),
.O(sig00000445)
);
MUXCY blk0000035a (
.CI(sig00000444),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000429),
.O(sig00000446)
);
XORCY blk0000035b (
.CI(sig00000444),
.LI(sig00000429),
.O(sig00000447)
);
MUXCY blk0000035c (
.CI(sig00000446),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000042a),
.O(sig00000448)
);
XORCY blk0000035d (
.CI(sig00000446),
.LI(sig0000042a),
.O(sig00000449)
);
MUXCY blk0000035e (
.CI(sig00000448),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000042b),
.O(sig0000044a)
);
XORCY blk0000035f (
.CI(sig00000448),
.LI(sig0000042b),
.O(sig0000044b)
);
MUXCY blk00000360 (
.CI(sig0000044a),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000042c),
.O(sig0000044c)
);
XORCY blk00000361 (
.CI(sig0000044a),
.LI(sig0000042c),
.O(sig0000044d)
);
MUXCY blk00000362 (
.CI(sig0000044c),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000042d),
.O(sig0000044e)
);
XORCY blk00000363 (
.CI(sig0000044c),
.LI(sig0000042d),
.O(sig0000044f)
);
MUXCY blk00000364 (
.CI(sig0000044e),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000c60),
.O(sig00000450)
);
XORCY blk00000365 (
.CI(sig0000044e),
.LI(sig00000c60),
.O(sig00000451)
);
MUXCY blk00000366 (
.CI(sig00000450),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000042e),
.O(NLW_blk00000366_O_UNCONNECTED)
);
XORCY blk00000367 (
.CI(sig00000450),
.LI(sig0000042e),
.O(sig00000452)
);
MUXCY blk00000368 (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig0000042f),
.O(sig00000453)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000369 (
.C(aclk),
.CE(sig00000344),
.D(sig000003a0),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004d3)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000036a (
.C(aclk),
.CE(sig00000344),
.D(sig000003a1),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004d4)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000036b (
.C(aclk),
.CE(sig00000344),
.D(sig000003a2),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004d5)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000036c (
.C(aclk),
.CE(sig00000344),
.D(sig000003a3),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004d6)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000036d (
.C(aclk),
.CE(sig00000344),
.D(sig000003a4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004d7)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000036e (
.C(aclk),
.CE(sig00000344),
.D(sig000003a5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004d8)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000036f (
.C(aclk),
.CE(sig00000344),
.D(sig000003a6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004d9)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000370 (
.C(aclk),
.CE(sig00000344),
.D(sig000003a7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004da)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000371 (
.C(aclk),
.CE(sig00000344),
.D(sig000003a8),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004db)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000372 (
.C(aclk),
.CE(sig00000344),
.D(sig000003a9),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004dc)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000373 (
.C(aclk),
.CE(sig00000344),
.D(sig000003aa),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004dd)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000374 (
.C(aclk),
.CE(sig00000344),
.D(sig000003ab),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004de)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000375 (
.C(aclk),
.CE(sig00000344),
.D(sig000003ac),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004df)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000376 (
.C(aclk),
.CE(sig00000344),
.D(sig000003ad),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004e0)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000377 (
.C(aclk),
.CE(sig00000344),
.D(sig000003ae),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004e1)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000378 (
.C(aclk),
.CE(sig00000344),
.D(sig000003af),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004e2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000379 (
.C(aclk),
.CE(sig00000344),
.D(sig000003b0),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004e3)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000037a (
.C(aclk),
.CE(sig00000344),
.D(sig000003b1),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004e4)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000037b (
.C(aclk),
.CE(sig00000344),
.D(sig000003b2),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004c1)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000037c (
.C(aclk),
.CE(sig00000344),
.D(sig000003b3),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004c2)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000037d (
.C(aclk),
.CE(sig00000344),
.D(sig000003b4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004c3)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000037e (
.C(aclk),
.CE(sig00000344),
.D(sig000003b5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004c4)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000037f (
.C(aclk),
.CE(sig00000344),
.D(sig000003b6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004c5)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000380 (
.C(aclk),
.CE(sig00000344),
.D(sig000003b7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004c6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000381 (
.C(aclk),
.CE(sig00000344),
.D(sig000003b8),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004c7)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000382 (
.C(aclk),
.CE(sig00000344),
.D(sig000003b9),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004c8)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000383 (
.C(aclk),
.CE(sig00000344),
.D(sig000003ba),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004c9)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000384 (
.C(aclk),
.CE(sig00000344),
.D(sig000003bb),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004ca)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000385 (
.C(aclk),
.CE(sig00000344),
.D(sig000003bc),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004cb)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000386 (
.C(aclk),
.CE(sig00000344),
.D(sig000003bd),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004cc)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000387 (
.C(aclk),
.CE(sig00000344),
.D(sig000003be),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004cd)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000388 (
.C(aclk),
.CE(sig00000344),
.D(sig000003bf),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004ce)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000389 (
.C(aclk),
.CE(sig00000344),
.D(sig000003c0),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004cf)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000038a (
.C(aclk),
.CE(sig00000344),
.D(sig000003c1),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004d0)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000038b (
.C(aclk),
.CE(sig00000344),
.D(sig000003c2),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004d1)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000038c (
.C(aclk),
.CE(sig00000344),
.D(sig000003c3),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004d2)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000038d (
.C(aclk),
.CE(sig00000344),
.D(sig000003c4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000479)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000038e (
.C(aclk),
.CE(sig00000344),
.D(sig000003c5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000047a)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000038f (
.C(aclk),
.CE(sig00000344),
.D(sig000003c6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000047b)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000390 (
.C(aclk),
.CE(sig00000344),
.D(sig000003c7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000047c)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000391 (
.C(aclk),
.CE(sig00000344),
.D(sig000003c8),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000047d)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000392 (
.C(aclk),
.CE(sig00000344),
.D(sig000003c9),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000047e)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000393 (
.C(aclk),
.CE(sig00000344),
.D(sig000003ca),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000047f)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000394 (
.C(aclk),
.CE(sig00000344),
.D(sig000003cb),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000480)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000395 (
.C(aclk),
.CE(sig00000344),
.D(sig000003cc),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000481)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000396 (
.C(aclk),
.CE(sig00000344),
.D(sig000003cd),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000482)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000397 (
.C(aclk),
.CE(sig00000344),
.D(sig000003ce),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000483)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000398 (
.C(aclk),
.CE(sig00000344),
.D(sig000003cf),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000484)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000399 (
.C(aclk),
.CE(sig00000344),
.D(sig000003d0),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000485)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000039a (
.C(aclk),
.CE(sig00000344),
.D(sig000003d1),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000486)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000039b (
.C(aclk),
.CE(sig00000344),
.D(sig000003d2),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000487)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000039c (
.C(aclk),
.CE(sig00000344),
.D(sig000003d3),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000488)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000039d (
.C(aclk),
.CE(sig00000344),
.D(sig000003d4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000489)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000039e (
.C(aclk),
.CE(sig00000344),
.D(sig000003d5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000048a)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000039f (
.C(aclk),
.CE(sig00000344),
.D(sig000003d6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001b4)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003a0 (
.C(aclk),
.CE(sig00000344),
.D(sig000003d7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001b5)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003a1 (
.C(aclk),
.CE(sig00000344),
.D(sig000003d8),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001b6)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003a2 (
.C(aclk),
.CE(sig00000344),
.D(sig000003d9),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001b7)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003a3 (
.C(aclk),
.CE(sig00000344),
.D(sig000003da),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001b8)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003a4 (
.C(aclk),
.CE(sig00000344),
.D(sig000003db),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001b9)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003a5 (
.C(aclk),
.CE(sig00000344),
.D(sig000003dc),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001ba)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003a6 (
.C(aclk),
.CE(sig00000344),
.D(sig000003dd),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001bb)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003a7 (
.C(aclk),
.CE(sig00000344),
.D(sig000003de),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001bc)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003a8 (
.C(aclk),
.CE(sig00000344),
.D(sig000003df),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001bd)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003a9 (
.C(aclk),
.CE(sig00000344),
.D(sig000003e0),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001be)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003aa (
.C(aclk),
.CE(sig00000344),
.D(sig000003e1),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001bf)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003ab (
.C(aclk),
.CE(sig00000344),
.D(sig000003e2),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001c0)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003ac (
.C(aclk),
.CE(sig00000344),
.D(sig000003e3),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001c1)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003ad (
.C(aclk),
.CE(sig00000344),
.D(sig000003e4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001c2)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003ae (
.C(aclk),
.CE(sig00000344),
.D(sig000003e5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001c3)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003af (
.C(aclk),
.CE(sig00000344),
.D(sig000003e6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001c4)
);
FDRE #(
.INIT ( 1'b0 ))
blk000003b0 (
.C(aclk),
.CE(sig00000344),
.D(sig000003e7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001c5)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b1 (
.C(aclk),
.CE(sig00000344),
.D(sig000003fb),
.Q(sig00000509)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b2 (
.C(aclk),
.CE(sig00000344),
.D(sig000003fd),
.Q(sig0000050a)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b3 (
.C(aclk),
.CE(sig00000344),
.D(sig000003ff),
.Q(sig0000050b)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000401),
.Q(sig0000050c)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000403),
.Q(sig0000050d)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000405),
.Q(sig0000050e)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000407),
.Q(sig0000050f)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000409),
.Q(sig00000510)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b9 (
.C(aclk),
.CE(sig00000344),
.D(sig0000040b),
.Q(sig00000511)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ba (
.C(aclk),
.CE(sig00000344),
.D(sig0000040d),
.Q(sig00000512)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bb (
.C(aclk),
.CE(sig00000344),
.D(sig0000040f),
.Q(sig00000513)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bc (
.C(aclk),
.CE(sig00000344),
.D(sig00000411),
.Q(sig00000514)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bd (
.C(aclk),
.CE(sig00000344),
.D(sig00000413),
.Q(sig00000515)
);
FDE #(
.INIT ( 1'b0 ))
blk000003be (
.C(aclk),
.CE(sig00000344),
.D(sig00000415),
.Q(sig00000516)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bf (
.C(aclk),
.CE(sig00000344),
.D(sig00000417),
.Q(sig00000517)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000419),
.Q(sig00000518)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c1 (
.C(aclk),
.CE(sig00000344),
.D(sig0000041b),
.Q(sig00000519)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c2 (
.C(aclk),
.CE(sig00000344),
.D(sig0000041c),
.Q(sig0000051a)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000431),
.Q(sig0000051b)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000433),
.Q(sig0000051c)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000435),
.Q(sig0000051d)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000437),
.Q(sig0000051e)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000439),
.Q(sig0000051f)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c8 (
.C(aclk),
.CE(sig00000344),
.D(sig0000043b),
.Q(sig00000520)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c9 (
.C(aclk),
.CE(sig00000344),
.D(sig0000043d),
.Q(sig00000521)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ca (
.C(aclk),
.CE(sig00000344),
.D(sig0000043f),
.Q(sig00000522)
);
FDE #(
.INIT ( 1'b0 ))
blk000003cb (
.C(aclk),
.CE(sig00000344),
.D(sig00000441),
.Q(sig00000523)
);
FDE #(
.INIT ( 1'b0 ))
blk000003cc (
.C(aclk),
.CE(sig00000344),
.D(sig00000443),
.Q(sig00000524)
);
FDE #(
.INIT ( 1'b0 ))
blk000003cd (
.C(aclk),
.CE(sig00000344),
.D(sig00000445),
.Q(sig00000525)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ce (
.C(aclk),
.CE(sig00000344),
.D(sig00000447),
.Q(sig00000526)
);
FDE #(
.INIT ( 1'b0 ))
blk000003cf (
.C(aclk),
.CE(sig00000344),
.D(sig00000449),
.Q(sig00000527)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d0 (
.C(aclk),
.CE(sig00000344),
.D(sig0000044b),
.Q(sig00000528)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d1 (
.C(aclk),
.CE(sig00000344),
.D(sig0000044d),
.Q(sig00000529)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d2 (
.C(aclk),
.CE(sig00000344),
.D(sig0000044f),
.Q(sig0000052a)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000451),
.Q(sig0000052b)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000452),
.Q(sig0000052c)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d5 (
.C(aclk),
.CE(sig00000344),
.D(sig000001e0),
.Q(sig00000532)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000454),
.Q(sig0000052d)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d7 (
.C(aclk),
.CE(sig00000344),
.D(sig000001d8),
.Q(sig00000531)
);
FD #(
.INIT ( 1'b0 ))
blk000003d8 (
.C(aclk),
.D(sig0000052c),
.Q(sig00000466)
);
FD #(
.INIT ( 1'b0 ))
blk000003d9 (
.C(aclk),
.D(sig0000052b),
.Q(sig00000465)
);
FD #(
.INIT ( 1'b0 ))
blk000003da (
.C(aclk),
.D(sig0000052a),
.Q(sig00000464)
);
FD #(
.INIT ( 1'b0 ))
blk000003db (
.C(aclk),
.D(sig00000529),
.Q(sig00000463)
);
FD #(
.INIT ( 1'b0 ))
blk000003dc (
.C(aclk),
.D(sig00000528),
.Q(sig00000462)
);
FD #(
.INIT ( 1'b0 ))
blk000003dd (
.C(aclk),
.D(sig00000527),
.Q(sig00000461)
);
FD #(
.INIT ( 1'b0 ))
blk000003de (
.C(aclk),
.D(sig00000526),
.Q(sig00000460)
);
FD #(
.INIT ( 1'b0 ))
blk000003df (
.C(aclk),
.D(sig00000525),
.Q(sig0000045f)
);
FD #(
.INIT ( 1'b0 ))
blk000003e0 (
.C(aclk),
.D(sig00000524),
.Q(sig0000045e)
);
FD #(
.INIT ( 1'b0 ))
blk000003e1 (
.C(aclk),
.D(sig00000523),
.Q(sig0000045d)
);
FD #(
.INIT ( 1'b0 ))
blk000003e2 (
.C(aclk),
.D(sig00000522),
.Q(sig0000045c)
);
FD #(
.INIT ( 1'b0 ))
blk000003e3 (
.C(aclk),
.D(sig00000521),
.Q(sig0000045b)
);
FD #(
.INIT ( 1'b0 ))
blk000003e4 (
.C(aclk),
.D(sig00000520),
.Q(sig0000045a)
);
FD #(
.INIT ( 1'b0 ))
blk000003e5 (
.C(aclk),
.D(sig0000051f),
.Q(sig00000459)
);
FD #(
.INIT ( 1'b0 ))
blk000003e6 (
.C(aclk),
.D(sig0000051e),
.Q(sig00000458)
);
FD #(
.INIT ( 1'b0 ))
blk000003e7 (
.C(aclk),
.D(sig0000051d),
.Q(sig00000457)
);
FD #(
.INIT ( 1'b0 ))
blk000003e8 (
.C(aclk),
.D(sig0000051c),
.Q(sig00000456)
);
FD #(
.INIT ( 1'b0 ))
blk000003e9 (
.C(aclk),
.D(sig0000051b),
.Q(sig00000455)
);
FD #(
.INIT ( 1'b0 ))
blk000003ea (
.C(aclk),
.D(sig0000051a),
.Q(sig00000478)
);
FD #(
.INIT ( 1'b0 ))
blk000003eb (
.C(aclk),
.D(sig00000519),
.Q(sig00000477)
);
FD #(
.INIT ( 1'b0 ))
blk000003ec (
.C(aclk),
.D(sig00000518),
.Q(sig00000476)
);
FD #(
.INIT ( 1'b0 ))
blk000003ed (
.C(aclk),
.D(sig00000517),
.Q(sig00000475)
);
FD #(
.INIT ( 1'b0 ))
blk000003ee (
.C(aclk),
.D(sig00000516),
.Q(sig00000474)
);
FD #(
.INIT ( 1'b0 ))
blk000003ef (
.C(aclk),
.D(sig00000515),
.Q(sig00000473)
);
FD #(
.INIT ( 1'b0 ))
blk000003f0 (
.C(aclk),
.D(sig00000514),
.Q(sig00000472)
);
FD #(
.INIT ( 1'b0 ))
blk000003f1 (
.C(aclk),
.D(sig00000513),
.Q(sig00000471)
);
FD #(
.INIT ( 1'b0 ))
blk000003f2 (
.C(aclk),
.D(sig00000512),
.Q(sig00000470)
);
FD #(
.INIT ( 1'b0 ))
blk000003f3 (
.C(aclk),
.D(sig00000511),
.Q(sig0000046f)
);
FD #(
.INIT ( 1'b0 ))
blk000003f4 (
.C(aclk),
.D(sig00000510),
.Q(sig0000046e)
);
FD #(
.INIT ( 1'b0 ))
blk000003f5 (
.C(aclk),
.D(sig0000050f),
.Q(sig0000046d)
);
FD #(
.INIT ( 1'b0 ))
blk000003f6 (
.C(aclk),
.D(sig0000050e),
.Q(sig0000046c)
);
FD #(
.INIT ( 1'b0 ))
blk000003f7 (
.C(aclk),
.D(sig0000050d),
.Q(sig0000046b)
);
FD #(
.INIT ( 1'b0 ))
blk000003f8 (
.C(aclk),
.D(sig0000050c),
.Q(sig0000046a)
);
FD #(
.INIT ( 1'b0 ))
blk000003f9 (
.C(aclk),
.D(sig0000050b),
.Q(sig00000469)
);
FD #(
.INIT ( 1'b0 ))
blk000003fa (
.C(aclk),
.D(sig0000050a),
.Q(sig00000468)
);
FD #(
.INIT ( 1'b0 ))
blk000003fb (
.C(aclk),
.D(sig00000509),
.Q(sig00000467)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000409 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000048a),
.Q(sig00000533)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000040a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000489),
.Q(sig00000534)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000040b (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000488),
.Q(sig00000535)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000040c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000487),
.Q(sig00000536)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000040d (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000486),
.Q(sig00000537)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000040e (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000485),
.Q(sig00000538)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000040f (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000484),
.Q(sig00000539)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000410 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000483),
.Q(sig0000053a)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000411 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000482),
.Q(sig0000053b)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000412 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000481),
.Q(sig0000053c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000413 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000480),
.Q(sig0000053d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000414 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000047f),
.Q(sig0000053e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000415 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000047e),
.Q(sig0000053f)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000416 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000047d),
.Q(sig00000540)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000417 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000047c),
.Q(sig00000541)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000418 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000047b),
.Q(sig00000542)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000419 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000047a),
.Q(sig00000543)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000041a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000479),
.Q(sig00000544)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000041b (
.C(aclk),
.CE(sig00000344),
.D(sig00000533),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001d7)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000041c (
.C(aclk),
.CE(sig00000344),
.D(sig00000534),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001d6)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000041d (
.C(aclk),
.CE(sig00000344),
.D(sig00000535),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001d5)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000041e (
.C(aclk),
.CE(sig00000344),
.D(sig00000536),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001d4)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000041f (
.C(aclk),
.CE(sig00000344),
.D(sig00000537),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001d3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000420 (
.C(aclk),
.CE(sig00000344),
.D(sig00000538),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001d2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000421 (
.C(aclk),
.CE(sig00000344),
.D(sig00000539),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001d1)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000422 (
.C(aclk),
.CE(sig00000344),
.D(sig0000053a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001d0)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000423 (
.C(aclk),
.CE(sig00000344),
.D(sig0000053b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001cf)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000424 (
.C(aclk),
.CE(sig00000344),
.D(sig0000053c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001ce)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000425 (
.C(aclk),
.CE(sig00000344),
.D(sig0000053d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001cd)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000426 (
.C(aclk),
.CE(sig00000344),
.D(sig0000053e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001cc)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000427 (
.C(aclk),
.CE(sig00000344),
.D(sig0000053f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001cb)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000428 (
.C(aclk),
.CE(sig00000344),
.D(sig00000540),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001ca)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000429 (
.C(aclk),
.CE(sig00000344),
.D(sig00000541),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001c9)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000042a (
.C(aclk),
.CE(sig00000344),
.D(sig00000542),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001c8)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000042b (
.C(aclk),
.CE(sig00000344),
.D(sig00000543),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001c7)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000042c (
.C(aclk),
.CE(sig00000344),
.D(sig00000544),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000001c6)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000042d (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004ae),
.Q(sig00000545)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000042e (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004ad),
.Q(sig00000546)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000042f (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004ac),
.Q(sig00000547)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000430 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004ab),
.Q(sig00000548)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000431 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004aa),
.Q(sig00000549)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000432 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004a9),
.Q(sig0000054a)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000433 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004a8),
.Q(sig0000054b)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000434 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004a7),
.Q(sig0000054c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000435 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004a6),
.Q(sig0000054d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000436 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004a5),
.Q(sig0000054e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000437 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004a4),
.Q(sig0000054f)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000438 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004a3),
.Q(sig00000550)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000439 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004a2),
.Q(sig00000551)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000043a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004a1),
.Q(sig00000552)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000043b (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004a0),
.Q(sig00000553)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000043c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000049f),
.Q(sig00000554)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000043d (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000049e),
.Q(sig00000555)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000043e (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000049d),
.Q(sig00000556)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000043f (
.C(aclk),
.CE(sig00000344),
.D(sig00000545),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000049c)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000440 (
.C(aclk),
.CE(sig00000344),
.D(sig00000546),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000049b)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000441 (
.C(aclk),
.CE(sig00000344),
.D(sig00000547),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000049a)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000442 (
.C(aclk),
.CE(sig00000344),
.D(sig00000548),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000499)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000443 (
.C(aclk),
.CE(sig00000344),
.D(sig00000549),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000498)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000444 (
.C(aclk),
.CE(sig00000344),
.D(sig0000054a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000497)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000445 (
.C(aclk),
.CE(sig00000344),
.D(sig0000054b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000496)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000446 (
.C(aclk),
.CE(sig00000344),
.D(sig0000054c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000495)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000447 (
.C(aclk),
.CE(sig00000344),
.D(sig0000054d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000494)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000448 (
.C(aclk),
.CE(sig00000344),
.D(sig0000054e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000493)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000449 (
.C(aclk),
.CE(sig00000344),
.D(sig0000054f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000492)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000044a (
.C(aclk),
.CE(sig00000344),
.D(sig00000550),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000491)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000044b (
.C(aclk),
.CE(sig00000344),
.D(sig00000551),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000490)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000044c (
.C(aclk),
.CE(sig00000344),
.D(sig00000552),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000048f)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000044d (
.C(aclk),
.CE(sig00000344),
.D(sig00000553),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000048e)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000044e (
.C(aclk),
.CE(sig00000344),
.D(sig00000554),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000048d)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000044f (
.C(aclk),
.CE(sig00000344),
.D(sig00000555),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000048c)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000450 (
.C(aclk),
.CE(sig00000344),
.D(sig00000556),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000048b)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000451 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000478),
.Q(sig00000557)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000452 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000477),
.Q(sig00000558)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000453 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000476),
.Q(sig00000559)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000454 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000475),
.Q(sig0000055a)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000455 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000474),
.Q(sig0000055b)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000456 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000473),
.Q(sig0000055c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000457 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000472),
.Q(sig0000055d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000458 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000471),
.Q(sig0000055e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000459 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000470),
.Q(sig0000055f)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000045a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000046f),
.Q(sig00000560)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000045b (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000046e),
.Q(sig00000561)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000045c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000046d),
.Q(sig00000562)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000045d (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000046c),
.Q(sig00000563)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000045e (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000046b),
.Q(sig00000564)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000045f (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000046a),
.Q(sig00000565)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000460 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000469),
.Q(sig00000566)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000461 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000468),
.Q(sig00000567)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000462 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000467),
.Q(sig00000568)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000463 (
.C(aclk),
.CE(sig00000344),
.D(sig00000557),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004f6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000464 (
.C(aclk),
.CE(sig00000344),
.D(sig00000558),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004f5)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000465 (
.C(aclk),
.CE(sig00000344),
.D(sig00000559),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004f4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000466 (
.C(aclk),
.CE(sig00000344),
.D(sig0000055a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004f3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000467 (
.C(aclk),
.CE(sig00000344),
.D(sig0000055b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004f2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000468 (
.C(aclk),
.CE(sig00000344),
.D(sig0000055c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004f1)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000469 (
.C(aclk),
.CE(sig00000344),
.D(sig0000055d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004f0)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000046a (
.C(aclk),
.CE(sig00000344),
.D(sig0000055e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004ef)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000046b (
.C(aclk),
.CE(sig00000344),
.D(sig0000055f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004ee)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000046c (
.C(aclk),
.CE(sig00000344),
.D(sig00000560),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004ed)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000046d (
.C(aclk),
.CE(sig00000344),
.D(sig00000561),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004ec)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000046e (
.C(aclk),
.CE(sig00000344),
.D(sig00000562),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004eb)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000046f (
.C(aclk),
.CE(sig00000344),
.D(sig00000563),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004ea)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000470 (
.C(aclk),
.CE(sig00000344),
.D(sig00000564),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004e9)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000471 (
.C(aclk),
.CE(sig00000344),
.D(sig00000565),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004e8)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000472 (
.C(aclk),
.CE(sig00000344),
.D(sig00000566),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004e7)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000473 (
.C(aclk),
.CE(sig00000344),
.D(sig00000567),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004e6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000474 (
.C(aclk),
.CE(sig00000344),
.D(sig00000568),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004e5)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000475 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004e4),
.Q(sig00000569)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000476 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004e3),
.Q(sig0000056a)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000477 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004e2),
.Q(sig0000056b)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000478 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004e1),
.Q(sig0000056c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000479 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004e0),
.Q(sig0000056d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000047a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004df),
.Q(sig0000056e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000047b (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004de),
.Q(sig0000056f)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000047c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004dd),
.Q(sig00000570)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000047d (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004dc),
.Q(sig00000571)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000047e (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004db),
.Q(sig00000572)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000047f (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004da),
.Q(sig00000573)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000480 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004d9),
.Q(sig00000574)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000481 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004d8),
.Q(sig00000575)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000482 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004d7),
.Q(sig00000576)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000483 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004d6),
.Q(sig00000577)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000484 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004d5),
.Q(sig00000578)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000485 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004d4),
.Q(sig00000579)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000486 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000004d3),
.Q(sig0000057a)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000487 (
.C(aclk),
.CE(sig00000344),
.D(sig00000569),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000508)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000488 (
.C(aclk),
.CE(sig00000344),
.D(sig0000056a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000507)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000489 (
.C(aclk),
.CE(sig00000344),
.D(sig0000056b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000506)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000048a (
.C(aclk),
.CE(sig00000344),
.D(sig0000056c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000505)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000048b (
.C(aclk),
.CE(sig00000344),
.D(sig0000056d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000504)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000048c (
.C(aclk),
.CE(sig00000344),
.D(sig0000056e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000503)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000048d (
.C(aclk),
.CE(sig00000344),
.D(sig0000056f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000502)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000048e (
.C(aclk),
.CE(sig00000344),
.D(sig00000570),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000501)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000048f (
.C(aclk),
.CE(sig00000344),
.D(sig00000571),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000500)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000490 (
.C(aclk),
.CE(sig00000344),
.D(sig00000572),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004ff)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000491 (
.C(aclk),
.CE(sig00000344),
.D(sig00000573),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004fe)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000492 (
.C(aclk),
.CE(sig00000344),
.D(sig00000574),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004fd)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000493 (
.C(aclk),
.CE(sig00000344),
.D(sig00000575),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004fc)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000494 (
.C(aclk),
.CE(sig00000344),
.D(sig00000576),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004fb)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000495 (
.C(aclk),
.CE(sig00000344),
.D(sig00000577),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004fa)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000496 (
.C(aclk),
.CE(sig00000344),
.D(sig00000578),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004f9)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000497 (
.C(aclk),
.CE(sig00000344),
.D(sig00000579),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004f8)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000498 (
.C(aclk),
.CE(sig00000344),
.D(sig0000057a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000004f7)
);
XORCY blk00000499 (
.CI(sig0000059f),
.LI(sig0000059d),
.O(sig0000057b)
);
XORCY blk0000049a (
.CI(sig000005a0),
.LI(sig0000058d),
.O(sig0000057c)
);
XORCY blk0000049b (
.CI(sig000005a1),
.LI(sig0000058e),
.O(sig0000057d)
);
XORCY blk0000049c (
.CI(sig000005a2),
.LI(sig0000058f),
.O(sig0000057e)
);
XORCY blk0000049d (
.CI(sig000005a3),
.LI(sig00000590),
.O(sig0000057f)
);
XORCY blk0000049e (
.CI(sig000005a4),
.LI(sig00000591),
.O(sig00000580)
);
XORCY blk0000049f (
.CI(sig000005a5),
.LI(sig00000592),
.O(sig00000581)
);
XORCY blk000004a0 (
.CI(sig000005a6),
.LI(sig00000593),
.O(sig00000582)
);
XORCY blk000004a1 (
.CI(sig000005a7),
.LI(sig00000594),
.O(sig00000583)
);
XORCY blk000004a2 (
.CI(sig000005a8),
.LI(sig00000595),
.O(sig00000584)
);
XORCY blk000004a3 (
.CI(sig000005a9),
.LI(sig00000596),
.O(sig00000585)
);
XORCY blk000004a4 (
.CI(sig000005aa),
.LI(sig00000597),
.O(sig00000586)
);
XORCY blk000004a5 (
.CI(sig000005ab),
.LI(sig00000598),
.O(sig00000587)
);
XORCY blk000004a6 (
.CI(sig000005ac),
.LI(sig00000599),
.O(sig00000588)
);
XORCY blk000004a7 (
.CI(sig000005ad),
.LI(sig0000059a),
.O(sig00000589)
);
XORCY blk000004a8 (
.CI(sig000005ae),
.LI(sig0000059b),
.O(sig0000058a)
);
XORCY blk000004a9 (
.CI(sig000005af),
.LI(sig0000059c),
.O(sig0000058b)
);
XORCY blk000004aa (
.CI(sig00000344),
.LI(sig0000059e),
.O(sig0000058c)
);
MUXCY blk000004ab (
.CI(sig000005a0),
.DI(sig00000507),
.S(sig0000058d),
.O(sig0000059f)
);
MUXCY blk000004ac (
.CI(sig000005a1),
.DI(sig00000506),
.S(sig0000058e),
.O(sig000005a0)
);
MUXCY blk000004ad (
.CI(sig000005a2),
.DI(sig00000505),
.S(sig0000058f),
.O(sig000005a1)
);
MUXCY blk000004ae (
.CI(sig000005a3),
.DI(sig00000504),
.S(sig00000590),
.O(sig000005a2)
);
MUXCY blk000004af (
.CI(sig000005a4),
.DI(sig00000503),
.S(sig00000591),
.O(sig000005a3)
);
MUXCY blk000004b0 (
.CI(sig000005a5),
.DI(sig00000502),
.S(sig00000592),
.O(sig000005a4)
);
MUXCY blk000004b1 (
.CI(sig000005a6),
.DI(sig00000501),
.S(sig00000593),
.O(sig000005a5)
);
MUXCY blk000004b2 (
.CI(sig000005a7),
.DI(sig00000500),
.S(sig00000594),
.O(sig000005a6)
);
MUXCY blk000004b3 (
.CI(sig000005a8),
.DI(sig000004ff),
.S(sig00000595),
.O(sig000005a7)
);
MUXCY blk000004b4 (
.CI(sig000005a9),
.DI(sig000004fe),
.S(sig00000596),
.O(sig000005a8)
);
MUXCY blk000004b5 (
.CI(sig000005aa),
.DI(sig000004fd),
.S(sig00000597),
.O(sig000005a9)
);
MUXCY blk000004b6 (
.CI(sig000005ab),
.DI(sig000004fc),
.S(sig00000598),
.O(sig000005aa)
);
MUXCY blk000004b7 (
.CI(sig000005ac),
.DI(sig000004fb),
.S(sig00000599),
.O(sig000005ab)
);
MUXCY blk000004b8 (
.CI(sig000005ad),
.DI(sig000004fa),
.S(sig0000059a),
.O(sig000005ac)
);
MUXCY blk000004b9 (
.CI(sig000005ae),
.DI(sig000004f9),
.S(sig0000059b),
.O(sig000005ad)
);
MUXCY blk000004ba (
.CI(sig000005af),
.DI(sig000004f8),
.S(sig0000059c),
.O(sig000005ae)
);
MUXCY blk000004bb (
.CI(sig00000344),
.DI(sig000004f7),
.S(sig0000059e),
.O(sig000005af)
);
XORCY blk000004bc (
.CI(sig000005d4),
.LI(sig000005d2),
.O(sig000005b0)
);
XORCY blk000004bd (
.CI(sig000005d5),
.LI(sig000005c2),
.O(sig000005b1)
);
XORCY blk000004be (
.CI(sig000005d6),
.LI(sig000005c3),
.O(sig000005b2)
);
XORCY blk000004bf (
.CI(sig000005d7),
.LI(sig000005c4),
.O(sig000005b3)
);
XORCY blk000004c0 (
.CI(sig000005d8),
.LI(sig000005c5),
.O(sig000005b4)
);
XORCY blk000004c1 (
.CI(sig000005d9),
.LI(sig000005c6),
.O(sig000005b5)
);
XORCY blk000004c2 (
.CI(sig000005da),
.LI(sig000005c7),
.O(sig000005b6)
);
XORCY blk000004c3 (
.CI(sig000005db),
.LI(sig000005c8),
.O(sig000005b7)
);
XORCY blk000004c4 (
.CI(sig000005dc),
.LI(sig000005c9),
.O(sig000005b8)
);
XORCY blk000004c5 (
.CI(sig000005dd),
.LI(sig000005ca),
.O(sig000005b9)
);
XORCY blk000004c6 (
.CI(sig000005de),
.LI(sig000005cb),
.O(sig000005ba)
);
XORCY blk000004c7 (
.CI(sig000005df),
.LI(sig000005cc),
.O(sig000005bb)
);
XORCY blk000004c8 (
.CI(sig000005e0),
.LI(sig000005cd),
.O(sig000005bc)
);
XORCY blk000004c9 (
.CI(sig000005e1),
.LI(sig000005ce),
.O(sig000005bd)
);
XORCY blk000004ca (
.CI(sig000005e2),
.LI(sig000005cf),
.O(sig000005be)
);
XORCY blk000004cb (
.CI(sig000005e3),
.LI(sig000005d0),
.O(sig000005bf)
);
XORCY blk000004cc (
.CI(sig000005e4),
.LI(sig000005d1),
.O(sig000005c0)
);
XORCY blk000004cd (
.CI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.LI(sig000005d3),
.O(sig000005c1)
);
MUXCY blk000004ce (
.CI(sig000005d5),
.DI(sig00000507),
.S(sig000005c2),
.O(sig000005d4)
);
MUXCY blk000004cf (
.CI(sig000005d6),
.DI(sig00000506),
.S(sig000005c3),
.O(sig000005d5)
);
MUXCY blk000004d0 (
.CI(sig000005d7),
.DI(sig00000505),
.S(sig000005c4),
.O(sig000005d6)
);
MUXCY blk000004d1 (
.CI(sig000005d8),
.DI(sig00000504),
.S(sig000005c5),
.O(sig000005d7)
);
MUXCY blk000004d2 (
.CI(sig000005d9),
.DI(sig00000503),
.S(sig000005c6),
.O(sig000005d8)
);
MUXCY blk000004d3 (
.CI(sig000005da),
.DI(sig00000502),
.S(sig000005c7),
.O(sig000005d9)
);
MUXCY blk000004d4 (
.CI(sig000005db),
.DI(sig00000501),
.S(sig000005c8),
.O(sig000005da)
);
MUXCY blk000004d5 (
.CI(sig000005dc),
.DI(sig00000500),
.S(sig000005c9),
.O(sig000005db)
);
MUXCY blk000004d6 (
.CI(sig000005dd),
.DI(sig000004ff),
.S(sig000005ca),
.O(sig000005dc)
);
MUXCY blk000004d7 (
.CI(sig000005de),
.DI(sig000004fe),
.S(sig000005cb),
.O(sig000005dd)
);
MUXCY blk000004d8 (
.CI(sig000005df),
.DI(sig000004fd),
.S(sig000005cc),
.O(sig000005de)
);
MUXCY blk000004d9 (
.CI(sig000005e0),
.DI(sig000004fc),
.S(sig000005cd),
.O(sig000005df)
);
MUXCY blk000004da (
.CI(sig000005e1),
.DI(sig000004fb),
.S(sig000005ce),
.O(sig000005e0)
);
MUXCY blk000004db (
.CI(sig000005e2),
.DI(sig000004fa),
.S(sig000005cf),
.O(sig000005e1)
);
MUXCY blk000004dc (
.CI(sig000005e3),
.DI(sig000004f9),
.S(sig000005d0),
.O(sig000005e2)
);
MUXCY blk000004dd (
.CI(sig000005e4),
.DI(sig000004f8),
.S(sig000005d1),
.O(sig000005e3)
);
MUXCY blk000004de (
.CI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.DI(sig000004f7),
.S(sig000005d3),
.O(sig000005e4)
);
FDE #(
.INIT ( 1'b0 ))
blk000004df (
.C(aclk),
.CE(sig00000344),
.D(sig000005b0),
.Q(sig000004c0)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e0 (
.C(aclk),
.CE(sig00000344),
.D(sig000005b1),
.Q(sig000004bf)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e1 (
.C(aclk),
.CE(sig00000344),
.D(sig000005b2),
.Q(sig000004be)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e2 (
.C(aclk),
.CE(sig00000344),
.D(sig000005b3),
.Q(sig000004bd)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e3 (
.C(aclk),
.CE(sig00000344),
.D(sig000005b4),
.Q(sig000004bc)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e4 (
.C(aclk),
.CE(sig00000344),
.D(sig000005b5),
.Q(sig000004bb)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e5 (
.C(aclk),
.CE(sig00000344),
.D(sig000005b6),
.Q(sig000004ba)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e6 (
.C(aclk),
.CE(sig00000344),
.D(sig000005b7),
.Q(sig000004b9)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e7 (
.C(aclk),
.CE(sig00000344),
.D(sig000005b8),
.Q(sig000004b8)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e8 (
.C(aclk),
.CE(sig00000344),
.D(sig000005b9),
.Q(sig000004b7)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e9 (
.C(aclk),
.CE(sig00000344),
.D(sig000005ba),
.Q(sig000004b6)
);
FDE #(
.INIT ( 1'b0 ))
blk000004ea (
.C(aclk),
.CE(sig00000344),
.D(sig000005bb),
.Q(sig000004b5)
);
FDE #(
.INIT ( 1'b0 ))
blk000004eb (
.C(aclk),
.CE(sig00000344),
.D(sig000005bc),
.Q(sig000004b4)
);
FDE #(
.INIT ( 1'b0 ))
blk000004ec (
.C(aclk),
.CE(sig00000344),
.D(sig000005bd),
.Q(sig000004b3)
);
FDE #(
.INIT ( 1'b0 ))
blk000004ed (
.C(aclk),
.CE(sig00000344),
.D(sig000005be),
.Q(sig000004b2)
);
FDE #(
.INIT ( 1'b0 ))
blk000004ee (
.C(aclk),
.CE(sig00000344),
.D(sig000005bf),
.Q(sig000004b1)
);
FDE #(
.INIT ( 1'b0 ))
blk000004ef (
.C(aclk),
.CE(sig00000344),
.D(sig000005c0),
.Q(sig000004b0)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f0 (
.C(aclk),
.CE(sig00000344),
.D(sig000005c1),
.Q(sig000004af)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f1 (
.C(aclk),
.CE(sig00000344),
.D(sig0000057b),
.Q(sig000004ae)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f2 (
.C(aclk),
.CE(sig00000344),
.D(sig0000057c),
.Q(sig000004ad)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f3 (
.C(aclk),
.CE(sig00000344),
.D(sig0000057d),
.Q(sig000004ac)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f4 (
.C(aclk),
.CE(sig00000344),
.D(sig0000057e),
.Q(sig000004ab)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f5 (
.C(aclk),
.CE(sig00000344),
.D(sig0000057f),
.Q(sig000004aa)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000580),
.Q(sig000004a9)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000581),
.Q(sig000004a8)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000582),
.Q(sig000004a7)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000583),
.Q(sig000004a6)
);
FDE #(
.INIT ( 1'b0 ))
blk000004fa (
.C(aclk),
.CE(sig00000344),
.D(sig00000584),
.Q(sig000004a5)
);
FDE #(
.INIT ( 1'b0 ))
blk000004fb (
.C(aclk),
.CE(sig00000344),
.D(sig00000585),
.Q(sig000004a4)
);
FDE #(
.INIT ( 1'b0 ))
blk000004fc (
.C(aclk),
.CE(sig00000344),
.D(sig00000586),
.Q(sig000004a3)
);
FDE #(
.INIT ( 1'b0 ))
blk000004fd (
.C(aclk),
.CE(sig00000344),
.D(sig00000587),
.Q(sig000004a2)
);
FDE #(
.INIT ( 1'b0 ))
blk000004fe (
.C(aclk),
.CE(sig00000344),
.D(sig00000588),
.Q(sig000004a1)
);
FDE #(
.INIT ( 1'b0 ))
blk000004ff (
.C(aclk),
.CE(sig00000344),
.D(sig00000589),
.Q(sig000004a0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000500 (
.C(aclk),
.CE(sig00000344),
.D(sig0000058a),
.Q(sig0000049f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000501 (
.C(aclk),
.CE(sig00000344),
.D(sig0000058b),
.Q(sig0000049e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000502 (
.C(aclk),
.CE(sig00000344),
.D(sig0000058c),
.Q(sig0000049d)
);
FD #(
.INIT ( 1'b0 ))
blk0000050c (
.C(aclk),
.D(sig000001b1),
.Q(sig000005f1)
);
FD #(
.INIT ( 1'b0 ))
blk0000050d (
.C(aclk),
.D(sig000001b0),
.Q(sig000005f0)
);
FD #(
.INIT ( 1'b0 ))
blk0000050e (
.C(aclk),
.D(sig000001b3),
.Q(sig000005f3)
);
FD #(
.INIT ( 1'b0 ))
blk0000050f (
.C(aclk),
.D(sig000001b2),
.Q(sig000005f2)
);
XORCY blk00000510 (
.CI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.LI(sig00000c62),
.O(NLW_blk00000510_O_UNCONNECTED)
);
XORCY blk00000511 (
.CI(sig000005f8),
.LI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.O(sig000005f4)
);
XORCY blk00000512 (
.CI(sig000005f9),
.LI(sig00000c61),
.O(sig000005f5)
);
XORCY blk00000513 (
.CI(sig000005fa),
.LI(sig000005f7),
.O(sig000005f6)
);
MUXCY blk00000514 (
.CI(sig000005f9),
.DI(sig000001b3),
.S(sig00000c61),
.O(sig000005f8)
);
MUXCY blk00000515 (
.CI(sig000005fa),
.DI(sig000001b2),
.S(sig000005f7),
.O(sig000005f9)
);
MUXCY blk00000516 (
.CI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000c62),
.O(sig000005fa)
);
FDE #(
.INIT ( 1'b0 ))
blk00000517 (
.C(aclk),
.CE(sig00000344),
.D(sig000005f6),
.Q(sig000005ed)
);
FDE #(
.INIT ( 1'b0 ))
blk00000518 (
.C(aclk),
.CE(sig00000344),
.D(sig000005f5),
.Q(sig000005ee)
);
FDE #(
.INIT ( 1'b0 ))
blk00000519 (
.C(aclk),
.CE(sig00000344),
.D(sig000005f4),
.Q(sig000005ef)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000051a (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(sig000005f2),
.I3(sig000005f2),
.I4(sig000005f0),
.I5(sig000005f1),
.O(sig000005fb)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000051b (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(sig000005f2),
.I2(sig000005f3),
.I3(sig000005ed),
.I4(sig000005f0),
.I5(sig000005f1),
.O(sig000005fc)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000051c (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(sig000005f3),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(sig000005ee),
.I4(sig000005f0),
.I5(sig000005f1),
.O(sig000005fd)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000051d (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(sig000005ef),
.I4(sig000005f0),
.I5(sig000005f1),
.O(sig000005fe)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000051e (
.C(aclk),
.CE(sig00000344),
.D(sig000005fb),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000005ea)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000051f (
.C(aclk),
.CE(sig00000344),
.D(sig000005fc),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000005eb)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000520 (
.C(aclk),
.CE(sig00000344),
.D(sig000005fd),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000005ec)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000521 (
.C(aclk),
.CE(sig00000344),
.D(sig000005fe),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000005e9)
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 1 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 1 ),
.DREG ( 1 ),
.INMODEREG ( 0 ),
.MASK ( 48'h000000000000 ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( "TRUE" ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000546 (
.PATTERNBDETECT(NLW_blk00000546_PATTERNBDETECT_UNCONNECTED),
.RSTC(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEB1(sig00000344),
.CEAD(sig00000344),
.MULTSIGNOUT(NLW_blk00000546_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000344),
.RSTM(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.MULTSIGNIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEB2(sig00000344),
.RSTCTRL(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEP(sig00000344),
.CARRYCASCOUT(NLW_blk00000546_CARRYCASCOUT_UNCONNECTED),
.RSTA(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CECARRYIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.UNDERFLOW(NLW_blk00000546_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000546_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.RSTALLCARRYIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CED(sig00000344),
.RSTD(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEALUMODE(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEA2(sig00000344),
.CLK(aclk),
.CEA1(sig00000344),
.RSTB(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.OVERFLOW(NLW_blk00000546_OVERFLOW_UNCONNECTED),
.CECTRL(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEM(sig00000344),
.CARRYIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CARRYCASCIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.RSTINMODE(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEINMODE(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.RSTP(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.ACOUT({\NLW_blk00000546_ACOUT<29>_UNCONNECTED , \NLW_blk00000546_ACOUT<28>_UNCONNECTED , \NLW_blk00000546_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000546_ACOUT<26>_UNCONNECTED , \NLW_blk00000546_ACOUT<25>_UNCONNECTED , \NLW_blk00000546_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000546_ACOUT<23>_UNCONNECTED , \NLW_blk00000546_ACOUT<22>_UNCONNECTED , \NLW_blk00000546_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000546_ACOUT<20>_UNCONNECTED , \NLW_blk00000546_ACOUT<19>_UNCONNECTED , \NLW_blk00000546_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000546_ACOUT<17>_UNCONNECTED , \NLW_blk00000546_ACOUT<16>_UNCONNECTED , \NLW_blk00000546_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000546_ACOUT<14>_UNCONNECTED , \NLW_blk00000546_ACOUT<13>_UNCONNECTED , \NLW_blk00000546_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000546_ACOUT<11>_UNCONNECTED , \NLW_blk00000546_ACOUT<10>_UNCONNECTED , \NLW_blk00000546_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000546_ACOUT<8>_UNCONNECTED , \NLW_blk00000546_ACOUT<7>_UNCONNECTED , \NLW_blk00000546_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000546_ACOUT<5>_UNCONNECTED , \NLW_blk00000546_ACOUT<4>_UNCONNECTED , \NLW_blk00000546_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000546_ACOUT<2>_UNCONNECTED , \NLW_blk00000546_ACOUT<1>_UNCONNECTED , \NLW_blk00000546_ACOUT<0>_UNCONNECTED }),
.OPMODE({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344, sig00000344,
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344,
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344}),
.PCIN({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.ALUMODE({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.C({sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c
, sig0000065c, sig0000065c, sig0000065d, sig0000065e, sig0000065f, sig00000660, sig00000661, sig00000662, sig00000663, sig00000664, sig00000665,
sig00000666, sig00000667, sig00000668, sig00000669, sig0000066a, sig0000066b, sig0000066c, sig0000066d, sig0000066e, sig0000066f, sig00000670,
sig00000671, sig00000672, sig00000673, sig00000674, sig00000675, sig00000676, sig00000677, sig00000678, sig00000679, sig0000067a, sig0000067b,
sig0000067c, sig0000067d, sig0000067e, sig0000067f}),
.CARRYOUT({\NLW_blk00000546_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000546_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000546_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000546_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344, sig00000344,
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.BCIN({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.B({sig00000643, sig00000644, sig00000645, sig00000646, sig00000647, sig00000648, sig00000649, sig0000064a, sig0000064b, sig0000064c, sig0000064d
, sig0000064e, sig0000064f, sig00000650, sig00000651, sig00000652, sig00000653, sig00000654}),
.BCOUT({\NLW_blk00000546_BCOUT<17>_UNCONNECTED , \NLW_blk00000546_BCOUT<16>_UNCONNECTED , \NLW_blk00000546_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000546_BCOUT<14>_UNCONNECTED , \NLW_blk00000546_BCOUT<13>_UNCONNECTED , \NLW_blk00000546_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000546_BCOUT<11>_UNCONNECTED , \NLW_blk00000546_BCOUT<10>_UNCONNECTED , \NLW_blk00000546_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000546_BCOUT<8>_UNCONNECTED , \NLW_blk00000546_BCOUT<7>_UNCONNECTED , \NLW_blk00000546_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000546_BCOUT<5>_UNCONNECTED , \NLW_blk00000546_BCOUT<4>_UNCONNECTED , \NLW_blk00000546_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000546_BCOUT<2>_UNCONNECTED , \NLW_blk00000546_BCOUT<1>_UNCONNECTED , \NLW_blk00000546_BCOUT<0>_UNCONNECTED }),
.D({sig00000758, sig00000758, sig00000758, sig00000758, sig00000758, sig00000758, sig00000758, sig00000758, sig00000758, sig00000757, sig00000756
, sig00000755, sig00000754, sig00000753, sig00000752, sig00000751, sig00000750, sig0000074f, sig0000074e, sig0000074d, sig0000074c, sig0000074b,
sig0000074a, sig00000749, \NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.P({\NLW_blk00000546_P<47>_UNCONNECTED , \NLW_blk00000546_P<46>_UNCONNECTED , \NLW_blk00000546_P<45>_UNCONNECTED ,
\NLW_blk00000546_P<44>_UNCONNECTED , \NLW_blk00000546_P<43>_UNCONNECTED , sig000005ff, sig00000600, sig00000601, sig00000602, sig00000603, sig00000604
, sig00000605, sig00000606, sig00000607, sig0000017a, sig00000179, sig00000178, sig00000177, sig00000176, sig00000175, sig00000174, sig00000173,
sig00000172, sig00000171, sig00000170, sig0000016f, sig0000016e, sig0000016d, sig0000016c, sig0000016b, sig0000016a, sig00000169, sig00000168,
sig00000167, sig00000166, sig00000165, sig00000164, sig00000163, sig00000620, sig00000621, sig00000622, sig00000623, sig00000624, sig00000625,
sig00000626, sig00000627, sig00000628, sig00000629}),
.A({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig0000062a, sig0000062a, sig0000062a, sig0000062a,
sig0000062a, sig0000062a, sig0000062a, sig0000062a, sig0000062a, sig00000633, sig00000634, sig00000635, sig00000636, sig00000637, sig00000638,
sig00000639, sig0000063a, sig0000063b, sig0000063c, sig0000063d, sig0000063e, sig0000063f, sig00000640, sig00000641,
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.PCOUT({\NLW_blk00000546_PCOUT<47>_UNCONNECTED , \NLW_blk00000546_PCOUT<46>_UNCONNECTED , \NLW_blk00000546_PCOUT<45>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<44>_UNCONNECTED , \NLW_blk00000546_PCOUT<43>_UNCONNECTED , \NLW_blk00000546_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<41>_UNCONNECTED , \NLW_blk00000546_PCOUT<40>_UNCONNECTED , \NLW_blk00000546_PCOUT<39>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<38>_UNCONNECTED , \NLW_blk00000546_PCOUT<37>_UNCONNECTED , \NLW_blk00000546_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<35>_UNCONNECTED , \NLW_blk00000546_PCOUT<34>_UNCONNECTED , \NLW_blk00000546_PCOUT<33>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<32>_UNCONNECTED , \NLW_blk00000546_PCOUT<31>_UNCONNECTED , \NLW_blk00000546_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<29>_UNCONNECTED , \NLW_blk00000546_PCOUT<28>_UNCONNECTED , \NLW_blk00000546_PCOUT<27>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<26>_UNCONNECTED , \NLW_blk00000546_PCOUT<25>_UNCONNECTED , \NLW_blk00000546_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<23>_UNCONNECTED , \NLW_blk00000546_PCOUT<22>_UNCONNECTED , \NLW_blk00000546_PCOUT<21>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<20>_UNCONNECTED , \NLW_blk00000546_PCOUT<19>_UNCONNECTED , \NLW_blk00000546_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<17>_UNCONNECTED , \NLW_blk00000546_PCOUT<16>_UNCONNECTED , \NLW_blk00000546_PCOUT<15>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<14>_UNCONNECTED , \NLW_blk00000546_PCOUT<13>_UNCONNECTED , \NLW_blk00000546_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<11>_UNCONNECTED , \NLW_blk00000546_PCOUT<10>_UNCONNECTED , \NLW_blk00000546_PCOUT<9>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<8>_UNCONNECTED , \NLW_blk00000546_PCOUT<7>_UNCONNECTED , \NLW_blk00000546_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<5>_UNCONNECTED , \NLW_blk00000546_PCOUT<4>_UNCONNECTED , \NLW_blk00000546_PCOUT<3>_UNCONNECTED ,
\NLW_blk00000546_PCOUT<2>_UNCONNECTED , \NLW_blk00000546_PCOUT<1>_UNCONNECTED , \NLW_blk00000546_PCOUT<0>_UNCONNECTED }),
.ACIN({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.CARRYINSEL({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]})
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 1 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.DREG ( 1 ),
.INMODEREG ( 0 ),
.MASK ( 48'h000000000000 ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( "TRUE" ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000547 (
.PATTERNBDETECT(NLW_blk00000547_PATTERNBDETECT_UNCONNECTED),
.RSTC(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEB1(sig00000344),
.CEAD(sig00000344),
.MULTSIGNOUT(NLW_blk00000547_MULTSIGNOUT_UNCONNECTED),
.CEC(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.RSTM(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.MULTSIGNIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEB2(sig00000344),
.RSTCTRL(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEP(sig00000344),
.CARRYCASCOUT(NLW_blk00000547_CARRYCASCOUT_UNCONNECTED),
.RSTA(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CECARRYIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.UNDERFLOW(NLW_blk00000547_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000547_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.RSTALLCARRYIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CED(sig00000344),
.RSTD(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEALUMODE(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEA2(sig00000344),
.CLK(aclk),
.CEA1(sig00000344),
.RSTB(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.OVERFLOW(NLW_blk00000547_OVERFLOW_UNCONNECTED),
.CECTRL(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEM(sig00000344),
.CARRYIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CARRYCASCIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.RSTINMODE(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEINMODE(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.RSTP(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.ACOUT({\NLW_blk00000547_ACOUT<29>_UNCONNECTED , \NLW_blk00000547_ACOUT<28>_UNCONNECTED , \NLW_blk00000547_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000547_ACOUT<26>_UNCONNECTED , \NLW_blk00000547_ACOUT<25>_UNCONNECTED , \NLW_blk00000547_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000547_ACOUT<23>_UNCONNECTED , \NLW_blk00000547_ACOUT<22>_UNCONNECTED , \NLW_blk00000547_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000547_ACOUT<20>_UNCONNECTED , \NLW_blk00000547_ACOUT<19>_UNCONNECTED , \NLW_blk00000547_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000547_ACOUT<17>_UNCONNECTED , \NLW_blk00000547_ACOUT<16>_UNCONNECTED , \NLW_blk00000547_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000547_ACOUT<14>_UNCONNECTED , \NLW_blk00000547_ACOUT<13>_UNCONNECTED , \NLW_blk00000547_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000547_ACOUT<11>_UNCONNECTED , \NLW_blk00000547_ACOUT<10>_UNCONNECTED , \NLW_blk00000547_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000547_ACOUT<8>_UNCONNECTED , \NLW_blk00000547_ACOUT<7>_UNCONNECTED , \NLW_blk00000547_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000547_ACOUT<5>_UNCONNECTED , \NLW_blk00000547_ACOUT<4>_UNCONNECTED , \NLW_blk00000547_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000547_ACOUT<2>_UNCONNECTED , \NLW_blk00000547_ACOUT<1>_UNCONNECTED , \NLW_blk00000547_ACOUT<0>_UNCONNECTED }),
.OPMODE({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344, sig00000344,
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344,
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344}),
.PCIN({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.ALUMODE({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.C({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344, sig00000344, sig00000344, sig00000344,
sig00000344, sig00000344, sig00000344, sig00000344, sig00000344}),
.CARRYOUT({\NLW_blk00000547_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000547_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000547_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000547_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344,
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.BCIN({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.B({sig00000699, sig00000699, sig0000069b, sig0000069c, sig0000069d, sig0000069e, sig0000069f, sig000006a0, sig000006a1, sig000006a2, sig000006a3
, sig000006a4, sig000006a5, sig000006a6, sig000006a7, sig000006a8, sig000006a9,
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.BCOUT({\NLW_blk00000547_BCOUT<17>_UNCONNECTED , \NLW_blk00000547_BCOUT<16>_UNCONNECTED , \NLW_blk00000547_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000547_BCOUT<14>_UNCONNECTED , \NLW_blk00000547_BCOUT<13>_UNCONNECTED , \NLW_blk00000547_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000547_BCOUT<11>_UNCONNECTED , \NLW_blk00000547_BCOUT<10>_UNCONNECTED , \NLW_blk00000547_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000547_BCOUT<8>_UNCONNECTED , \NLW_blk00000547_BCOUT<7>_UNCONNECTED , \NLW_blk00000547_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000547_BCOUT<5>_UNCONNECTED , \NLW_blk00000547_BCOUT<4>_UNCONNECTED , \NLW_blk00000547_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000547_BCOUT<2>_UNCONNECTED , \NLW_blk00000547_BCOUT<1>_UNCONNECTED , \NLW_blk00000547_BCOUT<0>_UNCONNECTED }),
.D({sig0000079a, sig0000079a, sig0000079a, sig0000079a, sig0000079a, sig0000079a, sig0000079a, sig0000079a, sig00000799, sig00000798, sig00000797
, sig00000796, sig00000795, sig00000794, sig00000793, sig00000792, sig00000791, sig00000790, sig0000078f, sig0000078e, sig0000078d, sig0000078c,
sig0000078b, sig0000078a, sig00000789}),
.P({\NLW_blk00000547_P<47>_UNCONNECTED , \NLW_blk00000547_P<46>_UNCONNECTED , \NLW_blk00000547_P<45>_UNCONNECTED ,
\NLW_blk00000547_P<44>_UNCONNECTED , \NLW_blk00000547_P<43>_UNCONNECTED , sig00000655, sig00000656, sig00000657, sig00000658, sig00000659, sig0000065a
, sig0000065b, sig0000065c, sig0000065d, sig0000065e, sig0000065f, sig00000660, sig00000661, sig00000662, sig00000663, sig00000664, sig00000665,
sig00000666, sig00000667, sig00000668, sig00000669, sig0000066a, sig0000066b, sig0000066c, sig0000066d, sig0000066e, sig0000066f, sig00000670,
sig00000671, sig00000672, sig00000673, sig00000674, sig00000675, sig00000676, sig00000677, sig00000678, sig00000679, sig0000067a, sig0000067b,
sig0000067c, sig0000067d, sig0000067e, sig0000067f}),
.A({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000680, sig00000680, sig00000680, sig00000680,
sig00000680, sig00000680, sig00000680, sig00000680, sig00000688, sig00000689, sig0000068a, sig0000068b, sig0000068c, sig0000068d, sig0000068e,
sig0000068f, sig00000690, sig00000691, sig00000692, sig00000693, sig00000694, sig00000695, sig00000696, sig00000697, sig00000698}),
.PCOUT({\NLW_blk00000547_PCOUT<47>_UNCONNECTED , \NLW_blk00000547_PCOUT<46>_UNCONNECTED , \NLW_blk00000547_PCOUT<45>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<44>_UNCONNECTED , \NLW_blk00000547_PCOUT<43>_UNCONNECTED , \NLW_blk00000547_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<41>_UNCONNECTED , \NLW_blk00000547_PCOUT<40>_UNCONNECTED , \NLW_blk00000547_PCOUT<39>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<38>_UNCONNECTED , \NLW_blk00000547_PCOUT<37>_UNCONNECTED , \NLW_blk00000547_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<35>_UNCONNECTED , \NLW_blk00000547_PCOUT<34>_UNCONNECTED , \NLW_blk00000547_PCOUT<33>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<32>_UNCONNECTED , \NLW_blk00000547_PCOUT<31>_UNCONNECTED , \NLW_blk00000547_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<29>_UNCONNECTED , \NLW_blk00000547_PCOUT<28>_UNCONNECTED , \NLW_blk00000547_PCOUT<27>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<26>_UNCONNECTED , \NLW_blk00000547_PCOUT<25>_UNCONNECTED , \NLW_blk00000547_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<23>_UNCONNECTED , \NLW_blk00000547_PCOUT<22>_UNCONNECTED , \NLW_blk00000547_PCOUT<21>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<20>_UNCONNECTED , \NLW_blk00000547_PCOUT<19>_UNCONNECTED , \NLW_blk00000547_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<17>_UNCONNECTED , \NLW_blk00000547_PCOUT<16>_UNCONNECTED , \NLW_blk00000547_PCOUT<15>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<14>_UNCONNECTED , \NLW_blk00000547_PCOUT<13>_UNCONNECTED , \NLW_blk00000547_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<11>_UNCONNECTED , \NLW_blk00000547_PCOUT<10>_UNCONNECTED , \NLW_blk00000547_PCOUT<9>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<8>_UNCONNECTED , \NLW_blk00000547_PCOUT<7>_UNCONNECTED , \NLW_blk00000547_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<5>_UNCONNECTED , \NLW_blk00000547_PCOUT<4>_UNCONNECTED , \NLW_blk00000547_PCOUT<3>_UNCONNECTED ,
\NLW_blk00000547_PCOUT<2>_UNCONNECTED , \NLW_blk00000547_PCOUT<1>_UNCONNECTED , \NLW_blk00000547_PCOUT<0>_UNCONNECTED }),
.ACIN({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.CARRYINSEL({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]})
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 1 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 1 ),
.DREG ( 1 ),
.INMODEREG ( 0 ),
.MASK ( 48'h000000000000 ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( "TRUE" ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000548 (
.PATTERNBDETECT(NLW_blk00000548_PATTERNBDETECT_UNCONNECTED),
.RSTC(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEB1(sig00000344),
.CEAD(sig00000344),
.MULTSIGNOUT(NLW_blk00000548_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000344),
.RSTM(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.MULTSIGNIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEB2(sig00000344),
.RSTCTRL(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEP(sig00000344),
.CARRYCASCOUT(NLW_blk00000548_CARRYCASCOUT_UNCONNECTED),
.RSTA(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CECARRYIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.UNDERFLOW(NLW_blk00000548_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000548_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.RSTALLCARRYIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CED(sig00000344),
.RSTD(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEALUMODE(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEA2(sig00000344),
.CLK(aclk),
.CEA1(sig00000344),
.RSTB(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.OVERFLOW(NLW_blk00000548_OVERFLOW_UNCONNECTED),
.CECTRL(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEM(sig00000344),
.CARRYIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CARRYCASCIN(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.RSTINMODE(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CEINMODE(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.RSTP(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.ACOUT({\NLW_blk00000548_ACOUT<29>_UNCONNECTED , \NLW_blk00000548_ACOUT<28>_UNCONNECTED , \NLW_blk00000548_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000548_ACOUT<26>_UNCONNECTED , \NLW_blk00000548_ACOUT<25>_UNCONNECTED , \NLW_blk00000548_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000548_ACOUT<23>_UNCONNECTED , \NLW_blk00000548_ACOUT<22>_UNCONNECTED , \NLW_blk00000548_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000548_ACOUT<20>_UNCONNECTED , \NLW_blk00000548_ACOUT<19>_UNCONNECTED , \NLW_blk00000548_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000548_ACOUT<17>_UNCONNECTED , \NLW_blk00000548_ACOUT<16>_UNCONNECTED , \NLW_blk00000548_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000548_ACOUT<14>_UNCONNECTED , \NLW_blk00000548_ACOUT<13>_UNCONNECTED , \NLW_blk00000548_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000548_ACOUT<11>_UNCONNECTED , \NLW_blk00000548_ACOUT<10>_UNCONNECTED , \NLW_blk00000548_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000548_ACOUT<8>_UNCONNECTED , \NLW_blk00000548_ACOUT<7>_UNCONNECTED , \NLW_blk00000548_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000548_ACOUT<5>_UNCONNECTED , \NLW_blk00000548_ACOUT<4>_UNCONNECTED , \NLW_blk00000548_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000548_ACOUT<2>_UNCONNECTED , \NLW_blk00000548_ACOUT<1>_UNCONNECTED , \NLW_blk00000548_ACOUT<0>_UNCONNECTED }),
.OPMODE({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344, sig00000344,
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344,
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344}),
.PCIN({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.ALUMODE({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344, sig00000344}),
.C({sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c, sig0000065c
, sig0000065c, sig0000065c, sig0000065d, sig0000065e, sig0000065f, sig00000660, sig00000661, sig00000662, sig00000663, sig00000664, sig00000665,
sig00000666, sig00000667, sig00000668, sig00000669, sig0000066a, sig0000066b, sig0000066c, sig0000066d, sig0000066e, sig0000066f, sig00000670,
sig00000671, sig00000672, sig00000673, sig00000674, sig00000675, sig00000676, sig00000677, sig00000678, sig00000679, sig0000067a, sig0000067b,
sig0000067c, sig0000067d, sig0000067e, sig0000067f}),
.CARRYOUT({\NLW_blk00000548_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000548_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000548_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000548_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig00000344,
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.BCIN({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.B({sig000006ef, sig000006f0, sig000006f1, sig000006f2, sig000006f3, sig000006f4, sig000006f5, sig000006f6, sig000006f7, sig000006f8, sig000006f9
, sig000006fa, sig000006fb, sig000006fc, sig000006fd, sig000006fe, sig000006ff, sig00000700}),
.BCOUT({\NLW_blk00000548_BCOUT<17>_UNCONNECTED , \NLW_blk00000548_BCOUT<16>_UNCONNECTED , \NLW_blk00000548_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000548_BCOUT<14>_UNCONNECTED , \NLW_blk00000548_BCOUT<13>_UNCONNECTED , \NLW_blk00000548_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000548_BCOUT<11>_UNCONNECTED , \NLW_blk00000548_BCOUT<10>_UNCONNECTED , \NLW_blk00000548_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000548_BCOUT<8>_UNCONNECTED , \NLW_blk00000548_BCOUT<7>_UNCONNECTED , \NLW_blk00000548_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000548_BCOUT<5>_UNCONNECTED , \NLW_blk00000548_BCOUT<4>_UNCONNECTED , \NLW_blk00000548_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000548_BCOUT<2>_UNCONNECTED , \NLW_blk00000548_BCOUT<1>_UNCONNECTED , \NLW_blk00000548_BCOUT<0>_UNCONNECTED }),
.D({sig00000758, sig00000758, sig00000758, sig00000758, sig00000758, sig00000758, sig00000758, sig00000758, sig00000758, sig00000757, sig00000756
, sig00000755, sig00000754, sig00000753, sig00000752, sig00000751, sig00000750, sig0000074f, sig0000074e, sig0000074d, sig0000074c, sig0000074b,
sig0000074a, sig00000749, \NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.P({\NLW_blk00000548_P<47>_UNCONNECTED , \NLW_blk00000548_P<46>_UNCONNECTED , \NLW_blk00000548_P<45>_UNCONNECTED ,
\NLW_blk00000548_P<44>_UNCONNECTED , \NLW_blk00000548_P<43>_UNCONNECTED , sig000006ab, sig000006ac, sig000006ad, sig000006ae, sig000006af, sig000006b0
, sig000006b1, sig000006b2, sig000006b3, sig00000192, sig00000191, sig00000190, sig0000018f, sig0000018e, sig0000018d, sig0000018c, sig0000018b,
sig0000018a, sig00000189, sig00000188, sig00000187, sig00000186, sig00000185, sig00000184, sig00000183, sig00000182, sig00000181, sig00000180,
sig0000017f, sig0000017e, sig0000017d, sig0000017c, sig0000017b, sig000006cc, sig000006cd, sig000006ce, sig000006cf, sig000006d0, sig000006d1,
sig000006d2, sig000006d3, sig000006d4, sig000006d5}),
.A({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1], sig0000062a, sig0000062a, sig0000062a, sig0000062a,
sig0000062a, sig0000062a, sig0000062a, sig0000062a, sig0000062a, sig00000633, sig00000634, sig00000635, sig00000636, sig00000637, sig00000638,
sig00000639, sig0000063a, sig0000063b, sig0000063c, sig0000063d, sig0000063e, sig0000063f, sig00000640, sig00000641,
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.PCOUT({\NLW_blk00000548_PCOUT<47>_UNCONNECTED , \NLW_blk00000548_PCOUT<46>_UNCONNECTED , \NLW_blk00000548_PCOUT<45>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<44>_UNCONNECTED , \NLW_blk00000548_PCOUT<43>_UNCONNECTED , \NLW_blk00000548_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<41>_UNCONNECTED , \NLW_blk00000548_PCOUT<40>_UNCONNECTED , \NLW_blk00000548_PCOUT<39>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<38>_UNCONNECTED , \NLW_blk00000548_PCOUT<37>_UNCONNECTED , \NLW_blk00000548_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<35>_UNCONNECTED , \NLW_blk00000548_PCOUT<34>_UNCONNECTED , \NLW_blk00000548_PCOUT<33>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<32>_UNCONNECTED , \NLW_blk00000548_PCOUT<31>_UNCONNECTED , \NLW_blk00000548_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<29>_UNCONNECTED , \NLW_blk00000548_PCOUT<28>_UNCONNECTED , \NLW_blk00000548_PCOUT<27>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<26>_UNCONNECTED , \NLW_blk00000548_PCOUT<25>_UNCONNECTED , \NLW_blk00000548_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<23>_UNCONNECTED , \NLW_blk00000548_PCOUT<22>_UNCONNECTED , \NLW_blk00000548_PCOUT<21>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<20>_UNCONNECTED , \NLW_blk00000548_PCOUT<19>_UNCONNECTED , \NLW_blk00000548_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<17>_UNCONNECTED , \NLW_blk00000548_PCOUT<16>_UNCONNECTED , \NLW_blk00000548_PCOUT<15>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<14>_UNCONNECTED , \NLW_blk00000548_PCOUT<13>_UNCONNECTED , \NLW_blk00000548_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<11>_UNCONNECTED , \NLW_blk00000548_PCOUT<10>_UNCONNECTED , \NLW_blk00000548_PCOUT<9>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<8>_UNCONNECTED , \NLW_blk00000548_PCOUT<7>_UNCONNECTED , \NLW_blk00000548_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<5>_UNCONNECTED , \NLW_blk00000548_PCOUT<4>_UNCONNECTED , \NLW_blk00000548_PCOUT<3>_UNCONNECTED ,
\NLW_blk00000548_PCOUT<2>_UNCONNECTED , \NLW_blk00000548_PCOUT<1>_UNCONNECTED , \NLW_blk00000548_PCOUT<0>_UNCONNECTED }),
.ACIN({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]}),
.CARRYINSEL({\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1],
\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]})
);
XORCY blk00000549 (
.CI(sig000007ad),
.LI(sig00000344),
.O(sig00000806)
);
XORCY blk0000054a (
.CI(sig000007af),
.LI(sig000007ae),
.O(sig00000805)
);
MUXCY blk0000054b (
.CI(sig000007af),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007ae),
.O(sig000007ad)
);
XORCY blk0000054c (
.CI(sig000007b1),
.LI(sig000007b0),
.O(sig00000804)
);
MUXCY blk0000054d (
.CI(sig000007b1),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007b0),
.O(sig000007af)
);
XORCY blk0000054e (
.CI(sig000007b3),
.LI(sig000007b2),
.O(sig00000803)
);
MUXCY blk0000054f (
.CI(sig000007b3),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007b2),
.O(sig000007b1)
);
XORCY blk00000550 (
.CI(sig000007b5),
.LI(sig000007b4),
.O(sig00000802)
);
MUXCY blk00000551 (
.CI(sig000007b5),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007b4),
.O(sig000007b3)
);
XORCY blk00000552 (
.CI(sig000007b7),
.LI(sig000007b6),
.O(sig00000801)
);
MUXCY blk00000553 (
.CI(sig000007b7),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007b6),
.O(sig000007b5)
);
XORCY blk00000554 (
.CI(sig000007b9),
.LI(sig000007b8),
.O(sig00000800)
);
MUXCY blk00000555 (
.CI(sig000007b9),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007b8),
.O(sig000007b7)
);
XORCY blk00000556 (
.CI(sig000007bb),
.LI(sig000007ba),
.O(sig000007ff)
);
MUXCY blk00000557 (
.CI(sig000007bb),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007ba),
.O(sig000007b9)
);
XORCY blk00000558 (
.CI(sig000007bc),
.LI(sig00000344),
.O(sig000007fe)
);
MUXCY blk00000559 (
.CI(sig000007bc),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000344),
.O(sig000007bb)
);
XORCY blk0000055a (
.CI(sig000007be),
.LI(sig000007bd),
.O(sig000007fd)
);
MUXCY blk0000055b (
.CI(sig000007be),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007bd),
.O(sig000007bc)
);
XORCY blk0000055c (
.CI(sig000007c0),
.LI(sig000007bf),
.O(sig000007fc)
);
MUXCY blk0000055d (
.CI(sig000007c0),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007bf),
.O(sig000007be)
);
XORCY blk0000055e (
.CI(sig000007c2),
.LI(sig000007c1),
.O(sig000007fb)
);
MUXCY blk0000055f (
.CI(sig000007c2),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007c1),
.O(sig000007c0)
);
XORCY blk00000560 (
.CI(sig000007c4),
.LI(sig000007c3),
.O(sig000007fa)
);
MUXCY blk00000561 (
.CI(sig000007c4),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007c3),
.O(sig000007c2)
);
XORCY blk00000562 (
.CI(sig000007c6),
.LI(sig000007c5),
.O(sig000007f9)
);
MUXCY blk00000563 (
.CI(sig000007c6),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007c5),
.O(sig000007c4)
);
XORCY blk00000564 (
.CI(sig000007c8),
.LI(sig000007c7),
.O(sig000007f8)
);
MUXCY blk00000565 (
.CI(sig000007c8),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007c7),
.O(sig000007c6)
);
XORCY blk00000566 (
.CI(sig00000344),
.LI(sig000007c9),
.O(sig000007f7)
);
MUXCY blk00000567 (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007c9),
.O(sig000007c8)
);
XORCY blk00000568 (
.CI(sig000007ca),
.LI(sig00000344),
.O(sig00000826)
);
XORCY blk00000569 (
.CI(sig000007cc),
.LI(sig000007cb),
.O(sig00000825)
);
MUXCY blk0000056a (
.CI(sig000007cc),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007cb),
.O(sig000007ca)
);
XORCY blk0000056b (
.CI(sig000007ce),
.LI(sig000007cd),
.O(sig00000824)
);
MUXCY blk0000056c (
.CI(sig000007ce),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007cd),
.O(sig000007cc)
);
XORCY blk0000056d (
.CI(sig000007d0),
.LI(sig000007cf),
.O(sig00000823)
);
MUXCY blk0000056e (
.CI(sig000007d0),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007cf),
.O(sig000007ce)
);
XORCY blk0000056f (
.CI(sig000007d2),
.LI(sig000007d1),
.O(sig00000822)
);
MUXCY blk00000570 (
.CI(sig000007d2),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007d1),
.O(sig000007d0)
);
XORCY blk00000571 (
.CI(sig000007d4),
.LI(sig000007d3),
.O(sig00000821)
);
MUXCY blk00000572 (
.CI(sig000007d4),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007d3),
.O(sig000007d2)
);
XORCY blk00000573 (
.CI(sig000007d6),
.LI(sig000007d5),
.O(sig00000820)
);
MUXCY blk00000574 (
.CI(sig000007d6),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007d5),
.O(sig000007d4)
);
XORCY blk00000575 (
.CI(sig000007d8),
.LI(sig000007d7),
.O(sig0000081f)
);
MUXCY blk00000576 (
.CI(sig000007d8),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007d7),
.O(sig000007d6)
);
XORCY blk00000577 (
.CI(sig000007d9),
.LI(sig00000344),
.O(sig0000081e)
);
MUXCY blk00000578 (
.CI(sig000007d9),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000344),
.O(sig000007d8)
);
XORCY blk00000579 (
.CI(sig000007db),
.LI(sig000007da),
.O(sig0000081d)
);
MUXCY blk0000057a (
.CI(sig000007db),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007da),
.O(sig000007d9)
);
XORCY blk0000057b (
.CI(sig000007dd),
.LI(sig000007dc),
.O(sig0000081c)
);
MUXCY blk0000057c (
.CI(sig000007dd),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007dc),
.O(sig000007db)
);
XORCY blk0000057d (
.CI(sig000007df),
.LI(sig000007de),
.O(sig0000081b)
);
MUXCY blk0000057e (
.CI(sig000007df),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007de),
.O(sig000007dd)
);
XORCY blk0000057f (
.CI(sig000007e1),
.LI(sig000007e0),
.O(sig0000081a)
);
MUXCY blk00000580 (
.CI(sig000007e1),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007e0),
.O(sig000007df)
);
XORCY blk00000581 (
.CI(sig000007e3),
.LI(sig000007e2),
.O(sig00000819)
);
MUXCY blk00000582 (
.CI(sig000007e3),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007e2),
.O(sig000007e1)
);
XORCY blk00000583 (
.CI(sig000007e5),
.LI(sig000007e4),
.O(sig00000818)
);
MUXCY blk00000584 (
.CI(sig000007e5),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007e4),
.O(sig000007e3)
);
XORCY blk00000585 (
.CI(sig00000344),
.LI(sig000007e6),
.O(sig00000817)
);
MUXCY blk00000586 (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig000007e6),
.O(sig000007e5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000587 (
.C(aclk),
.CE(sig00000344),
.D(sig00000816),
.Q(sig00000699)
);
FDE #(
.INIT ( 1'b0 ))
blk00000588 (
.C(aclk),
.CE(sig00000344),
.D(sig00000815),
.Q(sig0000069b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000589 (
.C(aclk),
.CE(sig00000344),
.D(sig00000814),
.Q(sig0000069c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000058a (
.C(aclk),
.CE(sig00000344),
.D(sig00000813),
.Q(sig0000069d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000058b (
.C(aclk),
.CE(sig00000344),
.D(sig00000812),
.Q(sig0000069e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000058c (
.C(aclk),
.CE(sig00000344),
.D(sig00000811),
.Q(sig0000069f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000058d (
.C(aclk),
.CE(sig00000344),
.D(sig00000810),
.Q(sig000006a0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000058e (
.C(aclk),
.CE(sig00000344),
.D(sig0000080f),
.Q(sig000006a1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000058f (
.C(aclk),
.CE(sig00000344),
.D(sig0000080e),
.Q(sig000006a2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000590 (
.C(aclk),
.CE(sig00000344),
.D(sig0000080d),
.Q(sig000006a3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000591 (
.C(aclk),
.CE(sig00000344),
.D(sig0000080c),
.Q(sig000006a4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000592 (
.C(aclk),
.CE(sig00000344),
.D(sig0000080b),
.Q(sig000006a5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000593 (
.C(aclk),
.CE(sig00000344),
.D(sig0000080a),
.Q(sig000006a6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000594 (
.C(aclk),
.CE(sig00000344),
.D(sig00000809),
.Q(sig000006a7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000595 (
.C(aclk),
.CE(sig00000344),
.D(sig00000808),
.Q(sig000006a8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000596 (
.C(aclk),
.CE(sig00000344),
.D(sig00000807),
.Q(sig000006a9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000597 (
.C(aclk),
.CE(sig00000344),
.D(sig000007f6),
.Q(sig00000778)
);
FDE #(
.INIT ( 1'b0 ))
blk00000598 (
.C(aclk),
.CE(sig00000344),
.D(sig000007f5),
.Q(sig00000777)
);
FDE #(
.INIT ( 1'b0 ))
blk00000599 (
.C(aclk),
.CE(sig00000344),
.D(sig000007f4),
.Q(sig00000776)
);
FDE #(
.INIT ( 1'b0 ))
blk0000059a (
.C(aclk),
.CE(sig00000344),
.D(sig000007f3),
.Q(sig00000775)
);
FDE #(
.INIT ( 1'b0 ))
blk0000059b (
.C(aclk),
.CE(sig00000344),
.D(sig000007f2),
.Q(sig00000774)
);
FDE #(
.INIT ( 1'b0 ))
blk0000059c (
.C(aclk),
.CE(sig00000344),
.D(sig000007f1),
.Q(sig00000773)
);
FDE #(
.INIT ( 1'b0 ))
blk0000059d (
.C(aclk),
.CE(sig00000344),
.D(sig000007f0),
.Q(sig00000772)
);
FDE #(
.INIT ( 1'b0 ))
blk0000059e (
.C(aclk),
.CE(sig00000344),
.D(sig000007ef),
.Q(sig00000771)
);
FDE #(
.INIT ( 1'b0 ))
blk0000059f (
.C(aclk),
.CE(sig00000344),
.D(sig000007ee),
.Q(sig00000770)
);
FDE #(
.INIT ( 1'b0 ))
blk000005a0 (
.C(aclk),
.CE(sig00000344),
.D(sig000007ed),
.Q(sig0000076f)
);
FDE #(
.INIT ( 1'b0 ))
blk000005a1 (
.C(aclk),
.CE(sig00000344),
.D(sig000007ec),
.Q(sig0000076e)
);
FDE #(
.INIT ( 1'b0 ))
blk000005a2 (
.C(aclk),
.CE(sig00000344),
.D(sig000007eb),
.Q(sig0000076d)
);
FDE #(
.INIT ( 1'b0 ))
blk000005a3 (
.C(aclk),
.CE(sig00000344),
.D(sig000007ea),
.Q(sig0000076c)
);
FDE #(
.INIT ( 1'b0 ))
blk000005a4 (
.C(aclk),
.CE(sig00000344),
.D(sig000007e9),
.Q(sig0000076b)
);
FDE #(
.INIT ( 1'b0 ))
blk000005a5 (
.C(aclk),
.CE(sig00000344),
.D(sig000007e8),
.Q(sig0000076a)
);
FDE #(
.INIT ( 1'b0 ))
blk000005a6 (
.C(aclk),
.CE(sig00000344),
.D(sig000007e7),
.Q(sig00000769)
);
FDE #(
.INIT ( 1'b0 ))
blk000005a7 (
.C(aclk),
.CE(sig00000344),
.D(sig000001c5),
.Q(sig0000079a)
);
FDE #(
.INIT ( 1'b0 ))
blk000005a8 (
.C(aclk),
.CE(sig00000344),
.D(sig000001c4),
.Q(sig00000799)
);
FDE #(
.INIT ( 1'b0 ))
blk000005a9 (
.C(aclk),
.CE(sig00000344),
.D(sig000001c3),
.Q(sig00000798)
);
FDE #(
.INIT ( 1'b0 ))
blk000005aa (
.C(aclk),
.CE(sig00000344),
.D(sig000001c2),
.Q(sig00000797)
);
FDE #(
.INIT ( 1'b0 ))
blk000005ab (
.C(aclk),
.CE(sig00000344),
.D(sig000001c1),
.Q(sig00000796)
);
FDE #(
.INIT ( 1'b0 ))
blk000005ac (
.C(aclk),
.CE(sig00000344),
.D(sig000001c0),
.Q(sig00000795)
);
FDE #(
.INIT ( 1'b0 ))
blk000005ad (
.C(aclk),
.CE(sig00000344),
.D(sig000001bf),
.Q(sig00000794)
);
FDE #(
.INIT ( 1'b0 ))
blk000005ae (
.C(aclk),
.CE(sig00000344),
.D(sig000001be),
.Q(sig00000793)
);
FDE #(
.INIT ( 1'b0 ))
blk000005af (
.C(aclk),
.CE(sig00000344),
.D(sig000001bd),
.Q(sig00000792)
);
FDE #(
.INIT ( 1'b0 ))
blk000005b0 (
.C(aclk),
.CE(sig00000344),
.D(sig000001bc),
.Q(sig00000791)
);
FDE #(
.INIT ( 1'b0 ))
blk000005b1 (
.C(aclk),
.CE(sig00000344),
.D(sig000001bb),
.Q(sig00000790)
);
FDE #(
.INIT ( 1'b0 ))
blk000005b2 (
.C(aclk),
.CE(sig00000344),
.D(sig000001ba),
.Q(sig0000078f)
);
FDE #(
.INIT ( 1'b0 ))
blk000005b3 (
.C(aclk),
.CE(sig00000344),
.D(sig000001b9),
.Q(sig0000078e)
);
FDE #(
.INIT ( 1'b0 ))
blk000005b4 (
.C(aclk),
.CE(sig00000344),
.D(sig000001b8),
.Q(sig0000078d)
);
FDE #(
.INIT ( 1'b0 ))
blk000005b5 (
.C(aclk),
.CE(sig00000344),
.D(sig000001b7),
.Q(sig0000078c)
);
FDE #(
.INIT ( 1'b0 ))
blk000005b6 (
.C(aclk),
.CE(sig00000344),
.D(sig000001b6),
.Q(sig0000078b)
);
FDE #(
.INIT ( 1'b0 ))
blk000005b7 (
.C(aclk),
.CE(sig00000344),
.D(sig000001b5),
.Q(sig0000078a)
);
FDE #(
.INIT ( 1'b0 ))
blk000005b8 (
.C(aclk),
.CE(sig00000344),
.D(sig000001b4),
.Q(sig00000789)
);
FDE #(
.INIT ( 1'b0 ))
blk000005b9 (
.C(aclk),
.CE(sig00000344),
.D(sig000001d7),
.Q(sig00000680)
);
FDE #(
.INIT ( 1'b0 ))
blk000005ba (
.C(aclk),
.CE(sig00000344),
.D(sig000001d6),
.Q(sig00000688)
);
FDE #(
.INIT ( 1'b0 ))
blk000005bb (
.C(aclk),
.CE(sig00000344),
.D(sig000001d5),
.Q(sig00000689)
);
FDE #(
.INIT ( 1'b0 ))
blk000005bc (
.C(aclk),
.CE(sig00000344),
.D(sig000001d4),
.Q(sig0000068a)
);
FDE #(
.INIT ( 1'b0 ))
blk000005bd (
.C(aclk),
.CE(sig00000344),
.D(sig000001d3),
.Q(sig0000068b)
);
FDE #(
.INIT ( 1'b0 ))
blk000005be (
.C(aclk),
.CE(sig00000344),
.D(sig000001d2),
.Q(sig0000068c)
);
FDE #(
.INIT ( 1'b0 ))
blk000005bf (
.C(aclk),
.CE(sig00000344),
.D(sig000001d1),
.Q(sig0000068d)
);
FDE #(
.INIT ( 1'b0 ))
blk000005c0 (
.C(aclk),
.CE(sig00000344),
.D(sig000001d0),
.Q(sig0000068e)
);
FDE #(
.INIT ( 1'b0 ))
blk000005c1 (
.C(aclk),
.CE(sig00000344),
.D(sig000001cf),
.Q(sig0000068f)
);
FDE #(
.INIT ( 1'b0 ))
blk000005c2 (
.C(aclk),
.CE(sig00000344),
.D(sig000001ce),
.Q(sig00000690)
);
FDE #(
.INIT ( 1'b0 ))
blk000005c3 (
.C(aclk),
.CE(sig00000344),
.D(sig000001cd),
.Q(sig00000691)
);
FDE #(
.INIT ( 1'b0 ))
blk000005c4 (
.C(aclk),
.CE(sig00000344),
.D(sig000001cc),
.Q(sig00000692)
);
FDE #(
.INIT ( 1'b0 ))
blk000005c5 (
.C(aclk),
.CE(sig00000344),
.D(sig000001cb),
.Q(sig00000693)
);
FDE #(
.INIT ( 1'b0 ))
blk000005c6 (
.C(aclk),
.CE(sig00000344),
.D(sig000001ca),
.Q(sig00000694)
);
FDE #(
.INIT ( 1'b0 ))
blk000005c7 (
.C(aclk),
.CE(sig00000344),
.D(sig000001c9),
.Q(sig00000695)
);
FDE #(
.INIT ( 1'b0 ))
blk000005c8 (
.C(aclk),
.CE(sig00000344),
.D(sig000001c8),
.Q(sig00000696)
);
FDE #(
.INIT ( 1'b0 ))
blk000005c9 (
.C(aclk),
.CE(sig00000344),
.D(sig000001c7),
.Q(sig00000697)
);
FDE #(
.INIT ( 1'b0 ))
blk000005ca (
.C(aclk),
.CE(sig00000344),
.D(sig000001c6),
.Q(sig00000698)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005d4 (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(sig0000017b),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000827)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005d5 (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(sig0000017b),
.I3(sig0000017c),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000828)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005d6 (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(sig0000017b),
.I2(sig0000017c),
.I3(sig0000017d),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000829)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005d7 (
.I0(sig0000017b),
.I1(sig0000017c),
.I2(sig0000017d),
.I3(sig0000017e),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000082a)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005d8 (
.I0(sig0000017c),
.I1(sig0000017d),
.I2(sig0000017e),
.I3(sig0000017f),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000082b)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005d9 (
.I0(sig0000017d),
.I1(sig0000017e),
.I2(sig0000017f),
.I3(sig00000180),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000082c)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005da (
.I0(sig0000017e),
.I1(sig0000017f),
.I2(sig00000180),
.I3(sig00000181),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000082d)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005db (
.I0(sig0000017f),
.I1(sig00000180),
.I2(sig00000181),
.I3(sig00000182),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000082e)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005dc (
.I0(sig00000180),
.I1(sig00000181),
.I2(sig00000182),
.I3(sig00000183),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000082f)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005dd (
.I0(sig00000181),
.I1(sig00000182),
.I2(sig00000183),
.I3(sig00000184),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000830)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005de (
.I0(sig00000182),
.I1(sig00000183),
.I2(sig00000184),
.I3(sig00000185),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000831)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005df (
.I0(sig00000183),
.I1(sig00000184),
.I2(sig00000185),
.I3(sig00000186),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000832)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005e0 (
.I0(sig00000184),
.I1(sig00000185),
.I2(sig00000186),
.I3(sig00000187),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000833)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005e1 (
.I0(sig00000185),
.I1(sig00000186),
.I2(sig00000187),
.I3(sig00000188),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000834)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005e2 (
.I0(sig00000186),
.I1(sig00000187),
.I2(sig00000188),
.I3(sig00000189),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000835)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005e3 (
.I0(sig00000187),
.I1(sig00000188),
.I2(sig00000189),
.I3(sig0000018a),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000836)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005e4 (
.I0(sig00000188),
.I1(sig00000189),
.I2(sig0000018a),
.I3(sig0000018b),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000837)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005e5 (
.I0(sig00000189),
.I1(sig0000018a),
.I2(sig0000018b),
.I3(sig0000018c),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000838)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005e6 (
.I0(sig0000018a),
.I1(sig0000018b),
.I2(sig0000018c),
.I3(sig0000018d),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000839)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005e7 (
.I0(sig0000018b),
.I1(sig0000018c),
.I2(sig0000018d),
.I3(sig0000018e),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000083a)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005e8 (
.I0(sig0000018c),
.I1(sig0000018d),
.I2(sig0000018e),
.I3(sig0000018f),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000083b)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005e9 (
.I0(sig0000018d),
.I1(sig0000018e),
.I2(sig0000018f),
.I3(sig00000190),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000083c)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005ea (
.I0(sig0000018e),
.I1(sig0000018f),
.I2(sig00000190),
.I3(sig00000191),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000083d)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005eb (
.I0(sig0000018f),
.I1(sig00000190),
.I2(sig00000191),
.I3(sig00000192),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000083e)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005ec (
.I0(sig00000190),
.I1(sig00000191),
.I2(sig00000192),
.I3(sig00000192),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000083f)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005ed (
.I0(sig00000191),
.I1(sig00000192),
.I2(sig00000192),
.I3(sig00000192),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000840)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000005ee (
.I0(sig00000192),
.I1(sig00000192),
.I2(sig00000192),
.I3(sig00000192),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000841)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005ef (
.C(aclk),
.CE(sig00000344),
.D(sig00000827),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000005ef_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005f0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000828),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000005f0_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005f1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000829),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000005f1_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005f2 (
.C(aclk),
.CE(sig00000344),
.D(sig0000082a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000005f2_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005f3 (
.C(aclk),
.CE(sig00000344),
.D(sig0000082b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000005f3_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005f4 (
.C(aclk),
.CE(sig00000344),
.D(sig0000082c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000005f4_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005f5 (
.C(aclk),
.CE(sig00000344),
.D(sig0000082d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000005f5_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005f6 (
.C(aclk),
.CE(sig00000344),
.D(sig0000082e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000005f6_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005f7 (
.C(aclk),
.CE(sig00000344),
.D(sig0000082f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000ae)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005f8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000830),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000af)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005f9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000831),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000b0)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005fa (
.C(aclk),
.CE(sig00000344),
.D(sig00000832),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000b1)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005fb (
.C(aclk),
.CE(sig00000344),
.D(sig00000833),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000b2)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005fc (
.C(aclk),
.CE(sig00000344),
.D(sig00000834),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000b3)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005fd (
.C(aclk),
.CE(sig00000344),
.D(sig00000835),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000b4)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005fe (
.C(aclk),
.CE(sig00000344),
.D(sig00000836),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000b5)
);
FDRE #(
.INIT ( 1'b0 ))
blk000005ff (
.C(aclk),
.CE(sig00000344),
.D(sig00000837),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000b6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000600 (
.C(aclk),
.CE(sig00000344),
.D(sig00000838),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000b7)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000601 (
.C(aclk),
.CE(sig00000344),
.D(sig00000839),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000b8)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000602 (
.C(aclk),
.CE(sig00000344),
.D(sig0000083a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000b9)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000603 (
.C(aclk),
.CE(sig00000344),
.D(sig0000083b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000ba)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000604 (
.C(aclk),
.CE(sig00000344),
.D(sig0000083c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000bb)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000605 (
.C(aclk),
.CE(sig00000344),
.D(sig0000083d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000bc)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000606 (
.C(aclk),
.CE(sig00000344),
.D(sig0000083e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000bd)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000607 (
.C(aclk),
.CE(sig00000344),
.D(sig0000083f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk00000607_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000608 (
.C(aclk),
.CE(sig00000344),
.D(sig00000840),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk00000608_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000609 (
.C(aclk),
.CE(sig00000344),
.D(sig00000841),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk00000609_Q_UNCONNECTED)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000060a (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(sig00000163),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000842)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000060b (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(sig00000163),
.I3(sig00000164),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000843)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000060c (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(sig00000163),
.I2(sig00000164),
.I3(sig00000165),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000844)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000060d (
.I0(sig00000163),
.I1(sig00000164),
.I2(sig00000165),
.I3(sig00000166),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000845)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000060e (
.I0(sig00000164),
.I1(sig00000165),
.I2(sig00000166),
.I3(sig00000167),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000846)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000060f (
.I0(sig00000165),
.I1(sig00000166),
.I2(sig00000167),
.I3(sig00000168),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000847)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000610 (
.I0(sig00000166),
.I1(sig00000167),
.I2(sig00000168),
.I3(sig00000169),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000848)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000611 (
.I0(sig00000167),
.I1(sig00000168),
.I2(sig00000169),
.I3(sig0000016a),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000849)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000612 (
.I0(sig00000168),
.I1(sig00000169),
.I2(sig0000016a),
.I3(sig0000016b),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000084a)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000613 (
.I0(sig00000169),
.I1(sig0000016a),
.I2(sig0000016b),
.I3(sig0000016c),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000084b)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000614 (
.I0(sig0000016a),
.I1(sig0000016b),
.I2(sig0000016c),
.I3(sig0000016d),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000084c)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000615 (
.I0(sig0000016b),
.I1(sig0000016c),
.I2(sig0000016d),
.I3(sig0000016e),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000084d)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000616 (
.I0(sig0000016c),
.I1(sig0000016d),
.I2(sig0000016e),
.I3(sig0000016f),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000084e)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000617 (
.I0(sig0000016d),
.I1(sig0000016e),
.I2(sig0000016f),
.I3(sig00000170),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000084f)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000618 (
.I0(sig0000016e),
.I1(sig0000016f),
.I2(sig00000170),
.I3(sig00000171),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000850)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000619 (
.I0(sig0000016f),
.I1(sig00000170),
.I2(sig00000171),
.I3(sig00000172),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000851)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000061a (
.I0(sig00000170),
.I1(sig00000171),
.I2(sig00000172),
.I3(sig00000173),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000852)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000061b (
.I0(sig00000171),
.I1(sig00000172),
.I2(sig00000173),
.I3(sig00000174),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000853)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000061c (
.I0(sig00000172),
.I1(sig00000173),
.I2(sig00000174),
.I3(sig00000175),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000854)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000061d (
.I0(sig00000173),
.I1(sig00000174),
.I2(sig00000175),
.I3(sig00000176),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000855)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000061e (
.I0(sig00000174),
.I1(sig00000175),
.I2(sig00000176),
.I3(sig00000177),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000856)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000061f (
.I0(sig00000175),
.I1(sig00000176),
.I2(sig00000177),
.I3(sig00000178),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000857)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000620 (
.I0(sig00000176),
.I1(sig00000177),
.I2(sig00000178),
.I3(sig00000179),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000858)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000621 (
.I0(sig00000177),
.I1(sig00000178),
.I2(sig00000179),
.I3(sig0000017a),
.I4(sig000001da),
.I5(sig000001db),
.O(sig00000859)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000622 (
.I0(sig00000178),
.I1(sig00000179),
.I2(sig0000017a),
.I3(sig0000017a),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000085a)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000623 (
.I0(sig00000179),
.I1(sig0000017a),
.I2(sig0000017a),
.I3(sig0000017a),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000085b)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000624 (
.I0(sig0000017a),
.I1(sig0000017a),
.I2(sig0000017a),
.I3(sig0000017a),
.I4(sig000001da),
.I5(sig000001db),
.O(sig0000085c)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000625 (
.C(aclk),
.CE(sig00000344),
.D(sig00000842),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk00000625_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000626 (
.C(aclk),
.CE(sig00000344),
.D(sig00000843),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk00000626_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000627 (
.C(aclk),
.CE(sig00000344),
.D(sig00000844),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk00000627_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000628 (
.C(aclk),
.CE(sig00000344),
.D(sig00000845),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk00000628_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000629 (
.C(aclk),
.CE(sig00000344),
.D(sig00000846),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk00000629_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000062a (
.C(aclk),
.CE(sig00000344),
.D(sig00000847),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk0000062a_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000062b (
.C(aclk),
.CE(sig00000344),
.D(sig00000848),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk0000062b_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000062c (
.C(aclk),
.CE(sig00000344),
.D(sig00000849),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk0000062c_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000062d (
.C(aclk),
.CE(sig00000344),
.D(sig0000084a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000009e)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000062e (
.C(aclk),
.CE(sig00000344),
.D(sig0000084b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000009f)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000062f (
.C(aclk),
.CE(sig00000344),
.D(sig0000084c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000a0)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000630 (
.C(aclk),
.CE(sig00000344),
.D(sig0000084d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000a1)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000631 (
.C(aclk),
.CE(sig00000344),
.D(sig0000084e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000a2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000632 (
.C(aclk),
.CE(sig00000344),
.D(sig0000084f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000a3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000633 (
.C(aclk),
.CE(sig00000344),
.D(sig00000850),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000a4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000634 (
.C(aclk),
.CE(sig00000344),
.D(sig00000851),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000a5)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000635 (
.C(aclk),
.CE(sig00000344),
.D(sig00000852),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000a6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000636 (
.C(aclk),
.CE(sig00000344),
.D(sig00000853),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000a7)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000637 (
.C(aclk),
.CE(sig00000344),
.D(sig00000854),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000a8)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000638 (
.C(aclk),
.CE(sig00000344),
.D(sig00000855),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000a9)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000639 (
.C(aclk),
.CE(sig00000344),
.D(sig00000856),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000aa)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000063a (
.C(aclk),
.CE(sig00000344),
.D(sig00000857),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000ab)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000063b (
.C(aclk),
.CE(sig00000344),
.D(sig00000858),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000ac)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000063c (
.C(aclk),
.CE(sig00000344),
.D(sig00000859),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000000ad)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000063d (
.C(aclk),
.CE(sig00000344),
.D(sig0000085a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk0000063d_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000063e (
.C(aclk),
.CE(sig00000344),
.D(sig0000085b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk0000063e_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000063f (
.C(aclk),
.CE(sig00000344),
.D(sig0000085c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk0000063f_Q_UNCONNECTED)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000645 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000085d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000646 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(sig00000344),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000085e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000647 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000891),
.Q(sig0000085f)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000648 (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(sig00000344),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000892),
.Q(sig00000860)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000649 (
.A0(sig00000344),
.A1(sig00000344),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000890),
.Q(sig00000861)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000064a (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000be),
.Q(sig00000863)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000064b (
.A0(sig00000344),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000bf),
.Q(sig00000864)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000064c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000c0),
.Q(sig00000865)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000064d (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(sig00000344),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000c1),
.Q(sig00000866)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000064e (
.C(aclk),
.CE(sig00000344),
.D(sig0000085d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk0000064e_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000064f (
.C(aclk),
.CE(sig00000344),
.D(sig0000085e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk0000064f_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000650 (
.C(aclk),
.CE(sig00000344),
.D(sig0000085f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000088c)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000651 (
.C(aclk),
.CE(sig00000344),
.D(sig00000860),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000088d)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000652 (
.C(aclk),
.CE(sig00000344),
.D(sig00000861),
.R(NLW_blk00000652_R_UNCONNECTED),
.Q(sig00000862)
);
FDR #(
.INIT ( 1'b0 ))
blk00000653 (
.C(aclk),
.D(sig00000862),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000070)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000654 (
.C(aclk),
.CE(sig00000344),
.D(sig00000863),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000891)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000655 (
.C(aclk),
.CE(sig00000344),
.D(sig00000864),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000892)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000656 (
.C(aclk),
.CE(sig00000344),
.D(sig00000865),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000893)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000657 (
.C(aclk),
.CE(sig00000344),
.D(sig00000866),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000894)
);
FD #(
.INIT ( 1'b0 ))
blk00000658 (
.C(aclk),
.D(sig00000867),
.Q(sig0000088f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000065d (
.C(aclk),
.CE(sig00000344),
.D(sig0000090a),
.Q(sig0000097f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000065e (
.C(aclk),
.CE(sig00000344),
.D(sig0000090b),
.Q(sig00000980)
);
FDE #(
.INIT ( 1'b0 ))
blk0000065f (
.C(aclk),
.CE(sig00000344),
.D(sig0000090c),
.Q(sig00000981)
);
FDE #(
.INIT ( 1'b0 ))
blk00000660 (
.C(aclk),
.CE(sig00000344),
.D(sig0000090d),
.Q(sig00000982)
);
FDE #(
.INIT ( 1'b0 ))
blk00000661 (
.C(aclk),
.CE(sig00000344),
.D(sig0000090e),
.Q(sig00000983)
);
FDE #(
.INIT ( 1'b0 ))
blk00000662 (
.C(aclk),
.CE(sig00000344),
.D(sig0000090f),
.Q(sig00000984)
);
FDE #(
.INIT ( 1'b0 ))
blk00000663 (
.C(aclk),
.CE(sig00000344),
.D(sig00000910),
.Q(sig00000985)
);
FDE #(
.INIT ( 1'b0 ))
blk00000664 (
.C(aclk),
.CE(sig00000344),
.D(sig00000911),
.Q(sig00000986)
);
FDE #(
.INIT ( 1'b0 ))
blk00000665 (
.C(aclk),
.CE(sig00000344),
.D(sig00000912),
.Q(sig00000987)
);
FDE #(
.INIT ( 1'b0 ))
blk00000666 (
.C(aclk),
.CE(sig00000344),
.D(sig00000913),
.Q(sig00000988)
);
FDE #(
.INIT ( 1'b0 ))
blk00000667 (
.C(aclk),
.CE(sig00000344),
.D(sig00000914),
.Q(sig00000989)
);
FDE #(
.INIT ( 1'b0 ))
blk00000668 (
.C(aclk),
.CE(sig00000344),
.D(sig00000915),
.Q(sig0000098a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000669 (
.C(aclk),
.CE(sig00000344),
.D(sig00000916),
.Q(sig0000098b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000066a (
.C(aclk),
.CE(sig00000344),
.D(sig00000917),
.Q(sig0000098c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000066b (
.C(aclk),
.CE(sig00000344),
.D(sig00000918),
.Q(sig0000098d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000066c (
.C(aclk),
.CE(sig00000344),
.D(sig00000919),
.Q(sig0000098e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000066d (
.C(aclk),
.CE(sig00000344),
.D(sig0000091a),
.Q(sig0000098f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000066e (
.C(aclk),
.CE(sig00000344),
.D(sig000008d8),
.Q(sig00000990)
);
FDE #(
.INIT ( 1'b0 ))
blk0000066f (
.C(aclk),
.CE(sig00000344),
.D(sig000008d9),
.Q(sig00000991)
);
FDE #(
.INIT ( 1'b0 ))
blk00000670 (
.C(aclk),
.CE(sig00000344),
.D(sig000008da),
.Q(sig00000992)
);
FDE #(
.INIT ( 1'b0 ))
blk00000671 (
.C(aclk),
.CE(sig00000344),
.D(sig000008db),
.Q(sig00000993)
);
FDE #(
.INIT ( 1'b0 ))
blk00000672 (
.C(aclk),
.CE(sig00000344),
.D(sig000008dc),
.Q(sig00000994)
);
FDE #(
.INIT ( 1'b0 ))
blk00000673 (
.C(aclk),
.CE(sig00000344),
.D(sig000008dd),
.Q(sig00000995)
);
FDE #(
.INIT ( 1'b0 ))
blk00000674 (
.C(aclk),
.CE(sig00000344),
.D(sig000008de),
.Q(sig00000996)
);
FDE #(
.INIT ( 1'b0 ))
blk00000675 (
.C(aclk),
.CE(sig00000344),
.D(sig000008df),
.Q(sig00000997)
);
FDE #(
.INIT ( 1'b0 ))
blk00000676 (
.C(aclk),
.CE(sig00000344),
.D(sig000008e0),
.Q(sig00000998)
);
FDE #(
.INIT ( 1'b0 ))
blk00000677 (
.C(aclk),
.CE(sig00000344),
.D(sig000008e1),
.Q(sig00000999)
);
FDE #(
.INIT ( 1'b0 ))
blk00000678 (
.C(aclk),
.CE(sig00000344),
.D(sig000008e2),
.Q(sig0000099a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000679 (
.C(aclk),
.CE(sig00000344),
.D(sig000008e3),
.Q(sig0000099b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000067a (
.C(aclk),
.CE(sig00000344),
.D(sig000008e4),
.Q(sig0000099c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000067b (
.C(aclk),
.CE(sig00000344),
.D(sig000008e5),
.Q(sig0000099d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000067c (
.C(aclk),
.CE(sig00000344),
.D(sig000008e6),
.Q(sig0000099e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000067d (
.C(aclk),
.CE(sig00000344),
.D(sig000008e7),
.Q(sig0000099f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000067e (
.C(aclk),
.CE(sig00000344),
.D(sig000008e8),
.Q(sig000009a0)
);
MUXCY blk0000067f (
.CI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.DI(sig000009a1),
.S(sig000008c7),
.O(sig000008b7)
);
MUXCY blk00000680 (
.CI(sig000008b7),
.DI(sig000009a2),
.S(sig000008c9),
.O(sig000008b8)
);
MUXCY blk00000681 (
.CI(sig000008b8),
.DI(sig000009a3),
.S(sig000008ca),
.O(sig000008b9)
);
MUXCY blk00000682 (
.CI(sig000008b9),
.DI(sig000009a4),
.S(sig000008cb),
.O(sig000008ba)
);
MUXCY blk00000683 (
.CI(sig000008ba),
.DI(sig000009a5),
.S(sig000008cc),
.O(sig000008bb)
);
MUXCY blk00000684 (
.CI(sig000008bb),
.DI(sig000009a6),
.S(sig000008cd),
.O(sig000008bc)
);
MUXCY blk00000685 (
.CI(sig000008bc),
.DI(sig000009a7),
.S(sig000008ce),
.O(sig000008bd)
);
MUXCY blk00000686 (
.CI(sig000008bd),
.DI(sig000009a8),
.S(sig000008cf),
.O(sig000008be)
);
MUXCY blk00000687 (
.CI(sig000008be),
.DI(sig000009a9),
.S(sig000008d0),
.O(sig000008bf)
);
MUXCY blk00000688 (
.CI(sig000008bf),
.DI(sig000009aa),
.S(sig000008d1),
.O(sig000008c0)
);
MUXCY blk00000689 (
.CI(sig000008c0),
.DI(sig000009ab),
.S(sig000008d2),
.O(sig000008c1)
);
MUXCY blk0000068a (
.CI(sig000008c1),
.DI(sig000009ac),
.S(sig000008d3),
.O(sig000008c2)
);
MUXCY blk0000068b (
.CI(sig000008c2),
.DI(sig000009ad),
.S(sig000008d4),
.O(sig000008c3)
);
MUXCY blk0000068c (
.CI(sig000008c3),
.DI(sig000009ae),
.S(sig000008d5),
.O(sig000008c4)
);
MUXCY blk0000068d (
.CI(sig000008c4),
.DI(sig000009af),
.S(sig000008d6),
.O(sig000008c5)
);
MUXCY blk0000068e (
.CI(sig000008c5),
.DI(sig000009b0),
.S(sig000008d7),
.O(sig000008c6)
);
XORCY blk0000068f (
.CI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.LI(sig000008c7),
.O(sig000008d8)
);
XORCY blk00000690 (
.CI(sig000008b7),
.LI(sig000008c9),
.O(sig000008d9)
);
XORCY blk00000691 (
.CI(sig000008b8),
.LI(sig000008ca),
.O(sig000008da)
);
XORCY blk00000692 (
.CI(sig000008b9),
.LI(sig000008cb),
.O(sig000008db)
);
XORCY blk00000693 (
.CI(sig000008ba),
.LI(sig000008cc),
.O(sig000008dc)
);
XORCY blk00000694 (
.CI(sig000008bb),
.LI(sig000008cd),
.O(sig000008dd)
);
XORCY blk00000695 (
.CI(sig000008bc),
.LI(sig000008ce),
.O(sig000008de)
);
XORCY blk00000696 (
.CI(sig000008bd),
.LI(sig000008cf),
.O(sig000008df)
);
XORCY blk00000697 (
.CI(sig000008be),
.LI(sig000008d0),
.O(sig000008e0)
);
XORCY blk00000698 (
.CI(sig000008bf),
.LI(sig000008d1),
.O(sig000008e1)
);
XORCY blk00000699 (
.CI(sig000008c0),
.LI(sig000008d2),
.O(sig000008e2)
);
XORCY blk0000069a (
.CI(sig000008c1),
.LI(sig000008d3),
.O(sig000008e3)
);
XORCY blk0000069b (
.CI(sig000008c2),
.LI(sig000008d4),
.O(sig000008e4)
);
XORCY blk0000069c (
.CI(sig000008c3),
.LI(sig000008d5),
.O(sig000008e5)
);
XORCY blk0000069d (
.CI(sig000008c4),
.LI(sig000008d6),
.O(sig000008e6)
);
XORCY blk0000069e (
.CI(sig000008c5),
.LI(sig000008d7),
.O(sig000008e7)
);
XORCY blk0000069f (
.CI(sig000008c6),
.LI(sig000008c8),
.O(sig000008e8)
);
MUXCY blk000006a0 (
.CI(sig00000344),
.DI(sig000009a1),
.S(sig000008f9),
.O(sig000008e9)
);
MUXCY blk000006a1 (
.CI(sig000008e9),
.DI(sig000009a2),
.S(sig000008fb),
.O(sig000008ea)
);
MUXCY blk000006a2 (
.CI(sig000008ea),
.DI(sig000009a3),
.S(sig000008fc),
.O(sig000008eb)
);
MUXCY blk000006a3 (
.CI(sig000008eb),
.DI(sig000009a4),
.S(sig000008fd),
.O(sig000008ec)
);
MUXCY blk000006a4 (
.CI(sig000008ec),
.DI(sig000009a5),
.S(sig000008fe),
.O(sig000008ed)
);
MUXCY blk000006a5 (
.CI(sig000008ed),
.DI(sig000009a6),
.S(sig000008ff),
.O(sig000008ee)
);
MUXCY blk000006a6 (
.CI(sig000008ee),
.DI(sig000009a7),
.S(sig00000900),
.O(sig000008ef)
);
MUXCY blk000006a7 (
.CI(sig000008ef),
.DI(sig000009a8),
.S(sig00000901),
.O(sig000008f0)
);
MUXCY blk000006a8 (
.CI(sig000008f0),
.DI(sig000009a9),
.S(sig00000902),
.O(sig000008f1)
);
MUXCY blk000006a9 (
.CI(sig000008f1),
.DI(sig000009aa),
.S(sig00000903),
.O(sig000008f2)
);
MUXCY blk000006aa (
.CI(sig000008f2),
.DI(sig000009ab),
.S(sig00000904),
.O(sig000008f3)
);
MUXCY blk000006ab (
.CI(sig000008f3),
.DI(sig000009ac),
.S(sig00000905),
.O(sig000008f4)
);
MUXCY blk000006ac (
.CI(sig000008f4),
.DI(sig000009ad),
.S(sig00000906),
.O(sig000008f5)
);
MUXCY blk000006ad (
.CI(sig000008f5),
.DI(sig000009ae),
.S(sig00000907),
.O(sig000008f6)
);
MUXCY blk000006ae (
.CI(sig000008f6),
.DI(sig000009af),
.S(sig00000908),
.O(sig000008f7)
);
MUXCY blk000006af (
.CI(sig000008f7),
.DI(sig000009b0),
.S(sig00000909),
.O(sig000008f8)
);
XORCY blk000006b0 (
.CI(sig00000344),
.LI(sig000008f9),
.O(sig0000090a)
);
XORCY blk000006b1 (
.CI(sig000008e9),
.LI(sig000008fb),
.O(sig0000090b)
);
XORCY blk000006b2 (
.CI(sig000008ea),
.LI(sig000008fc),
.O(sig0000090c)
);
XORCY blk000006b3 (
.CI(sig000008eb),
.LI(sig000008fd),
.O(sig0000090d)
);
XORCY blk000006b4 (
.CI(sig000008ec),
.LI(sig000008fe),
.O(sig0000090e)
);
XORCY blk000006b5 (
.CI(sig000008ed),
.LI(sig000008ff),
.O(sig0000090f)
);
XORCY blk000006b6 (
.CI(sig000008ee),
.LI(sig00000900),
.O(sig00000910)
);
XORCY blk000006b7 (
.CI(sig000008ef),
.LI(sig00000901),
.O(sig00000911)
);
XORCY blk000006b8 (
.CI(sig000008f0),
.LI(sig00000902),
.O(sig00000912)
);
XORCY blk000006b9 (
.CI(sig000008f1),
.LI(sig00000903),
.O(sig00000913)
);
XORCY blk000006ba (
.CI(sig000008f2),
.LI(sig00000904),
.O(sig00000914)
);
XORCY blk000006bb (
.CI(sig000008f3),
.LI(sig00000905),
.O(sig00000915)
);
XORCY blk000006bc (
.CI(sig000008f4),
.LI(sig00000906),
.O(sig00000916)
);
XORCY blk000006bd (
.CI(sig000008f5),
.LI(sig00000907),
.O(sig00000917)
);
XORCY blk000006be (
.CI(sig000008f6),
.LI(sig00000908),
.O(sig00000918)
);
XORCY blk000006bf (
.CI(sig000008f7),
.LI(sig00000909),
.O(sig00000919)
);
XORCY blk000006c0 (
.CI(sig000008f8),
.LI(sig000008fa),
.O(sig0000091a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006c1 (
.I0(sig00000990),
.I1(sig0000096e),
.I2(sig000009b1),
.O(sig0000091b)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006c2 (
.I0(sig00000991),
.I1(sig0000096f),
.I2(sig000009b1),
.O(sig0000091c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006c3 (
.I0(sig00000992),
.I1(sig00000970),
.I2(sig000009b1),
.O(sig0000091d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006c4 (
.I0(sig00000993),
.I1(sig00000971),
.I2(sig000009b1),
.O(sig0000091e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006c5 (
.I0(sig00000994),
.I1(sig00000972),
.I2(sig000009b1),
.O(sig0000091f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006c6 (
.I0(sig00000995),
.I1(sig00000973),
.I2(sig000009b1),
.O(sig00000920)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006c7 (
.I0(sig00000996),
.I1(sig00000974),
.I2(sig000009b1),
.O(sig00000921)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006c8 (
.I0(sig00000997),
.I1(sig00000975),
.I2(sig000009b1),
.O(sig00000922)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006c9 (
.I0(sig00000998),
.I1(sig00000976),
.I2(sig000009b1),
.O(sig00000923)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006ca (
.I0(sig00000999),
.I1(sig00000977),
.I2(sig000009b1),
.O(sig00000924)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006cb (
.I0(sig0000099a),
.I1(sig00000978),
.I2(sig000009b1),
.O(sig00000925)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006cc (
.I0(sig0000099b),
.I1(sig00000979),
.I2(sig000009b1),
.O(sig00000926)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006cd (
.I0(sig0000099c),
.I1(sig0000097a),
.I2(sig000009b1),
.O(sig00000927)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006ce (
.I0(sig0000099d),
.I1(sig0000097b),
.I2(sig000009b1),
.O(sig00000928)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006cf (
.I0(sig0000099e),
.I1(sig0000097c),
.I2(sig000009b1),
.O(sig00000929)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006d0 (
.I0(sig0000099f),
.I1(sig0000097d),
.I2(sig000009b1),
.O(sig0000092a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006d1 (
.I0(sig000009a0),
.I1(sig0000097e),
.I2(sig000009b1),
.O(sig0000092b)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006d2 (
.I0(sig0000096e),
.I1(sig00000990),
.I2(sig000009b1),
.O(sig0000092c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006d3 (
.I0(sig0000096f),
.I1(sig00000991),
.I2(sig000009b1),
.O(sig0000092d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006d4 (
.I0(sig00000970),
.I1(sig00000992),
.I2(sig000009b1),
.O(sig0000092e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006d5 (
.I0(sig00000971),
.I1(sig00000993),
.I2(sig000009b1),
.O(sig0000092f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006d6 (
.I0(sig00000972),
.I1(sig00000994),
.I2(sig000009b1),
.O(sig00000930)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006d7 (
.I0(sig00000973),
.I1(sig00000995),
.I2(sig000009b1),
.O(sig00000931)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006d8 (
.I0(sig00000974),
.I1(sig00000996),
.I2(sig000009b1),
.O(sig00000932)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006d9 (
.I0(sig00000975),
.I1(sig00000997),
.I2(sig000009b1),
.O(sig00000933)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006da (
.I0(sig00000976),
.I1(sig00000998),
.I2(sig000009b1),
.O(sig00000934)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006db (
.I0(sig00000977),
.I1(sig00000999),
.I2(sig000009b1),
.O(sig00000935)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006dc (
.I0(sig00000978),
.I1(sig0000099a),
.I2(sig000009b1),
.O(sig00000936)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006dd (
.I0(sig00000979),
.I1(sig0000099b),
.I2(sig000009b1),
.O(sig00000937)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006de (
.I0(sig0000097a),
.I1(sig0000099c),
.I2(sig000009b1),
.O(sig00000938)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006df (
.I0(sig0000097b),
.I1(sig0000099d),
.I2(sig000009b1),
.O(sig00000939)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006e0 (
.I0(sig0000097c),
.I1(sig0000099e),
.I2(sig000009b1),
.O(sig0000093a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006e1 (
.I0(sig0000097d),
.I1(sig0000099f),
.I2(sig000009b1),
.O(sig0000093b)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006e2 (
.I0(sig0000097e),
.I1(sig000009a0),
.I2(sig000009b1),
.O(sig0000093c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006e3 (
.I0(sig000000ae),
.I1(sig000009b4),
.I2(sig000000c1),
.O(sig0000093d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006e4 (
.I0(sig000000af),
.I1(sig000009b5),
.I2(sig000000c1),
.O(sig0000093e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006e5 (
.I0(sig000000b0),
.I1(sig000009b6),
.I2(sig000000c1),
.O(sig0000093f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006e6 (
.I0(sig000000b1),
.I1(sig000009b7),
.I2(sig000000c1),
.O(sig00000940)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006e7 (
.I0(sig000000b2),
.I1(sig000009b8),
.I2(sig000000c1),
.O(sig00000941)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006e8 (
.I0(sig000000b3),
.I1(sig000009b9),
.I2(sig000000c1),
.O(sig00000942)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006e9 (
.I0(sig000000b4),
.I1(sig000009ba),
.I2(sig000000c1),
.O(sig00000943)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006ea (
.I0(sig000000b5),
.I1(sig000009bb),
.I2(sig000000c1),
.O(sig00000944)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006eb (
.I0(sig000000b6),
.I1(sig000009bc),
.I2(sig000000c1),
.O(sig00000945)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006ec (
.I0(sig000000b7),
.I1(sig000009bd),
.I2(sig000000c1),
.O(sig00000946)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006ed (
.I0(sig000000b8),
.I1(sig000009be),
.I2(sig000000c1),
.O(sig00000947)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006ee (
.I0(sig000000b9),
.I1(sig000009bf),
.I2(sig000000c1),
.O(sig00000948)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006ef (
.I0(sig000000ba),
.I1(sig000009c0),
.I2(sig000000c1),
.O(sig00000949)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006f0 (
.I0(sig000000bb),
.I1(sig000009c1),
.I2(sig000000c1),
.O(sig0000094a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006f1 (
.I0(sig000000bc),
.I1(sig000009c2),
.I2(sig000000c1),
.O(sig0000094b)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006f2 (
.I0(sig000000bd),
.I1(sig000009c3),
.I2(sig000000c1),
.O(sig0000094c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006f3 (
.I0(sig000009b4),
.I1(sig000000ae),
.I2(sig000000c1),
.O(sig0000094d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006f4 (
.I0(sig000009b5),
.I1(sig000000af),
.I2(sig000000c1),
.O(sig0000094e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006f5 (
.I0(sig000009b6),
.I1(sig000000b0),
.I2(sig000000c1),
.O(sig0000094f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006f6 (
.I0(sig000009b7),
.I1(sig000000b1),
.I2(sig000000c1),
.O(sig00000950)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006f7 (
.I0(sig000009b8),
.I1(sig000000b2),
.I2(sig000000c1),
.O(sig00000951)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006f8 (
.I0(sig000009b9),
.I1(sig000000b3),
.I2(sig000000c1),
.O(sig00000952)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006f9 (
.I0(sig000009ba),
.I1(sig000000b4),
.I2(sig000000c1),
.O(sig00000953)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006fa (
.I0(sig000009bb),
.I1(sig000000b5),
.I2(sig000000c1),
.O(sig00000954)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006fb (
.I0(sig000009bc),
.I1(sig000000b6),
.I2(sig000000c1),
.O(sig00000955)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006fc (
.I0(sig000009bd),
.I1(sig000000b7),
.I2(sig000000c1),
.O(sig00000956)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006fd (
.I0(sig000009be),
.I1(sig000000b8),
.I2(sig000000c1),
.O(sig00000957)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006fe (
.I0(sig000009bf),
.I1(sig000000b9),
.I2(sig000000c1),
.O(sig00000958)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000006ff (
.I0(sig000009c0),
.I1(sig000000ba),
.I2(sig000000c1),
.O(sig00000959)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000700 (
.I0(sig000009c1),
.I1(sig000000bb),
.I2(sig000000c1),
.O(sig0000095a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000701 (
.I0(sig000009c2),
.I1(sig000000bc),
.I2(sig000000c1),
.O(sig0000095b)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000702 (
.I0(sig000009c3),
.I1(sig000000bd),
.I2(sig000000c1),
.O(sig0000095c)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000703 (
.C(aclk),
.CE(sig00000344),
.D(sig0000091b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000095d)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000704 (
.C(aclk),
.CE(sig00000344),
.D(sig0000091c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000095e)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000705 (
.C(aclk),
.CE(sig00000344),
.D(sig0000091d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000095f)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000706 (
.C(aclk),
.CE(sig00000344),
.D(sig0000091e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000960)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000707 (
.C(aclk),
.CE(sig00000344),
.D(sig0000091f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000961)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000708 (
.C(aclk),
.CE(sig00000344),
.D(sig00000920),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000962)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000709 (
.C(aclk),
.CE(sig00000344),
.D(sig00000921),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000963)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000070a (
.C(aclk),
.CE(sig00000344),
.D(sig00000922),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000964)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000070b (
.C(aclk),
.CE(sig00000344),
.D(sig00000923),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000965)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000070c (
.C(aclk),
.CE(sig00000344),
.D(sig00000924),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000966)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000070d (
.C(aclk),
.CE(sig00000344),
.D(sig00000925),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000967)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000070e (
.C(aclk),
.CE(sig00000344),
.D(sig00000926),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000968)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000070f (
.C(aclk),
.CE(sig00000344),
.D(sig00000927),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000969)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000710 (
.C(aclk),
.CE(sig00000344),
.D(sig00000928),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000096a)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000711 (
.C(aclk),
.CE(sig00000344),
.D(sig00000929),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000096b)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000712 (
.C(aclk),
.CE(sig00000344),
.D(sig0000092a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000096c)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000713 (
.C(aclk),
.CE(sig00000344),
.D(sig0000092b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000096d)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000714 (
.C(aclk),
.CE(sig00000344),
.D(sig0000092c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000895)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000715 (
.C(aclk),
.CE(sig00000344),
.D(sig0000092d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000896)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000716 (
.C(aclk),
.CE(sig00000344),
.D(sig0000092e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000897)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000717 (
.C(aclk),
.CE(sig00000344),
.D(sig0000092f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000898)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000718 (
.C(aclk),
.CE(sig00000344),
.D(sig00000930),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000899)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000719 (
.C(aclk),
.CE(sig00000344),
.D(sig00000931),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000089a)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000071a (
.C(aclk),
.CE(sig00000344),
.D(sig00000932),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000089b)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000071b (
.C(aclk),
.CE(sig00000344),
.D(sig00000933),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000089c)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000071c (
.C(aclk),
.CE(sig00000344),
.D(sig00000934),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000089d)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000071d (
.C(aclk),
.CE(sig00000344),
.D(sig00000935),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000089e)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000071e (
.C(aclk),
.CE(sig00000344),
.D(sig00000936),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000089f)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000071f (
.C(aclk),
.CE(sig00000344),
.D(sig00000937),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008a0)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000720 (
.C(aclk),
.CE(sig00000344),
.D(sig00000938),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008a1)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000721 (
.C(aclk),
.CE(sig00000344),
.D(sig00000939),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008a2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000722 (
.C(aclk),
.CE(sig00000344),
.D(sig0000093a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008a3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000723 (
.C(aclk),
.CE(sig00000344),
.D(sig0000093b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008a4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000724 (
.C(aclk),
.CE(sig00000344),
.D(sig0000093c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008a5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000725 (
.C(aclk),
.CE(sig00000344),
.D(sig000009b3),
.Q(sig000009b2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000726 (
.C(aclk),
.CE(sig00000344),
.D(sig0000093d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009d4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000727 (
.C(aclk),
.CE(sig00000344),
.D(sig0000093e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009d5)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000728 (
.C(aclk),
.CE(sig00000344),
.D(sig0000093f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009d6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000729 (
.C(aclk),
.CE(sig00000344),
.D(sig00000940),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009d7)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000072a (
.C(aclk),
.CE(sig00000344),
.D(sig00000941),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009d8)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000072b (
.C(aclk),
.CE(sig00000344),
.D(sig00000942),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009d9)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000072c (
.C(aclk),
.CE(sig00000344),
.D(sig00000943),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009da)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000072d (
.C(aclk),
.CE(sig00000344),
.D(sig00000944),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009db)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000072e (
.C(aclk),
.CE(sig00000344),
.D(sig00000945),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009dc)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000072f (
.C(aclk),
.CE(sig00000344),
.D(sig00000946),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009dd)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000730 (
.C(aclk),
.CE(sig00000344),
.D(sig00000947),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009de)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000731 (
.C(aclk),
.CE(sig00000344),
.D(sig00000948),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009df)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000732 (
.C(aclk),
.CE(sig00000344),
.D(sig00000949),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009e0)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000733 (
.C(aclk),
.CE(sig00000344),
.D(sig0000094a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009e1)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000734 (
.C(aclk),
.CE(sig00000344),
.D(sig0000094b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009e2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000735 (
.C(aclk),
.CE(sig00000344),
.D(sig0000094c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009e3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000736 (
.C(aclk),
.CE(sig00000344),
.D(sig0000094d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009c4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000737 (
.C(aclk),
.CE(sig00000344),
.D(sig0000094e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009c5)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000738 (
.C(aclk),
.CE(sig00000344),
.D(sig0000094f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009c6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000739 (
.C(aclk),
.CE(sig00000344),
.D(sig00000950),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009c7)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000073a (
.C(aclk),
.CE(sig00000344),
.D(sig00000951),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009c8)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000073b (
.C(aclk),
.CE(sig00000344),
.D(sig00000952),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009c9)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000073c (
.C(aclk),
.CE(sig00000344),
.D(sig00000953),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009ca)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000073d (
.C(aclk),
.CE(sig00000344),
.D(sig00000954),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009cb)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000073e (
.C(aclk),
.CE(sig00000344),
.D(sig00000955),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009cc)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000073f (
.C(aclk),
.CE(sig00000344),
.D(sig00000956),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009cd)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000740 (
.C(aclk),
.CE(sig00000344),
.D(sig00000957),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009ce)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000741 (
.C(aclk),
.CE(sig00000344),
.D(sig00000958),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009cf)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000742 (
.C(aclk),
.CE(sig00000344),
.D(sig00000959),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009d0)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000743 (
.C(aclk),
.CE(sig00000344),
.D(sig0000095a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009d1)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000744 (
.C(aclk),
.CE(sig00000344),
.D(sig0000095b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009d2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000745 (
.C(aclk),
.CE(sig00000344),
.D(sig0000095c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009d3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000746 (
.C(aclk),
.CE(sig00000344),
.D(sig000000c1),
.Q(sig000009b3)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000747 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009e3),
.Q(sig000009e4)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000748 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009e2),
.Q(sig000009e5)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000749 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009e1),
.Q(sig000009e6)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000074a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009e0),
.Q(sig000009e7)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000074b (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009df),
.Q(sig000009e8)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000074c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009de),
.Q(sig000009e9)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000074d (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009dd),
.Q(sig000009ea)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000074e (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009dc),
.Q(sig000009eb)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000074f (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009db),
.Q(sig000009ec)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000750 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009da),
.Q(sig000009ed)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000751 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009d9),
.Q(sig000009ee)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000752 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009d8),
.Q(sig000009ef)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000753 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009d7),
.Q(sig000009f0)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000754 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009d6),
.Q(sig000009f1)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000755 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009d5),
.Q(sig000009f2)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000756 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009d4),
.Q(sig000009f3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000757 (
.C(aclk),
.CE(sig00000344),
.D(sig000009e4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009b0)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000758 (
.C(aclk),
.CE(sig00000344),
.D(sig000009e5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009af)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000759 (
.C(aclk),
.CE(sig00000344),
.D(sig000009e6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009ae)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000075a (
.C(aclk),
.CE(sig00000344),
.D(sig000009e7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009ad)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000075b (
.C(aclk),
.CE(sig00000344),
.D(sig000009e8),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009ac)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000075c (
.C(aclk),
.CE(sig00000344),
.D(sig000009e9),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009ab)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000075d (
.C(aclk),
.CE(sig00000344),
.D(sig000009ea),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009aa)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000075e (
.C(aclk),
.CE(sig00000344),
.D(sig000009eb),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009a9)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000075f (
.C(aclk),
.CE(sig00000344),
.D(sig000009ec),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009a8)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000760 (
.C(aclk),
.CE(sig00000344),
.D(sig000009ed),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009a7)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000761 (
.C(aclk),
.CE(sig00000344),
.D(sig000009ee),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009a6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000762 (
.C(aclk),
.CE(sig00000344),
.D(sig000009ef),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009a5)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000763 (
.C(aclk),
.CE(sig00000344),
.D(sig000009f0),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009a4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000764 (
.C(aclk),
.CE(sig00000344),
.D(sig000009f1),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009a3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000765 (
.C(aclk),
.CE(sig00000344),
.D(sig000009f2),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009a2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000766 (
.C(aclk),
.CE(sig00000344),
.D(sig000009f3),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009a1)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000767 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000ad),
.Q(sig000009f4)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000768 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000ac),
.Q(sig000009f5)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000769 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000ab),
.Q(sig000009f6)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000076a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000aa),
.Q(sig000009f7)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000076b (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000a9),
.Q(sig000009f8)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000076c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000a8),
.Q(sig000009f9)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000076d (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000a7),
.Q(sig000009fa)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000076e (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000a6),
.Q(sig000009fb)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000076f (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000a5),
.Q(sig000009fc)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000770 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000a4),
.Q(sig000009fd)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000771 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000a3),
.Q(sig000009fe)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000772 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000a2),
.Q(sig000009ff)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000773 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000a1),
.Q(sig00000a00)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000774 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000a0),
.Q(sig00000a01)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000775 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000009f),
.Q(sig00000a02)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000776 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000009e),
.Q(sig00000a03)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000777 (
.C(aclk),
.CE(sig00000344),
.D(sig000009f4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009c3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000778 (
.C(aclk),
.CE(sig00000344),
.D(sig000009f5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009c2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000779 (
.C(aclk),
.CE(sig00000344),
.D(sig000009f6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009c1)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000077a (
.C(aclk),
.CE(sig00000344),
.D(sig000009f7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009c0)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000077b (
.C(aclk),
.CE(sig00000344),
.D(sig000009f8),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009bf)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000077c (
.C(aclk),
.CE(sig00000344),
.D(sig000009f9),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009be)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000077d (
.C(aclk),
.CE(sig00000344),
.D(sig000009fa),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009bd)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000077e (
.C(aclk),
.CE(sig00000344),
.D(sig000009fb),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009bc)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000077f (
.C(aclk),
.CE(sig00000344),
.D(sig000009fc),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009bb)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000780 (
.C(aclk),
.CE(sig00000344),
.D(sig000009fd),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009ba)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000781 (
.C(aclk),
.CE(sig00000344),
.D(sig000009fe),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009b9)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000782 (
.C(aclk),
.CE(sig00000344),
.D(sig000009ff),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009b8)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000783 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a00),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009b7)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000784 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a01),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009b6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000785 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a02),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009b5)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000786 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a03),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000009b4)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000787 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000096d),
.Q(sig00000a04)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000788 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000096c),
.Q(sig00000a05)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000789 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000096b),
.Q(sig00000a06)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000078a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000096a),
.Q(sig00000a07)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000078b (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000969),
.Q(sig00000a08)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000078c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000968),
.Q(sig00000a09)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000078d (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000967),
.Q(sig00000a0a)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000078e (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000966),
.Q(sig00000a0b)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk0000078f (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000965),
.Q(sig00000a0c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000790 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000964),
.Q(sig00000a0d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000791 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000963),
.Q(sig00000a0e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000792 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000962),
.Q(sig00000a0f)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000793 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000961),
.Q(sig00000a10)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000794 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000960),
.Q(sig00000a11)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000795 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000095f),
.Q(sig00000a12)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000796 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000095e),
.Q(sig00000a13)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000797 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000095d),
.Q(sig00000a14)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000798 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a04),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008b6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000799 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a05),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008b5)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000079a (
.C(aclk),
.CE(sig00000344),
.D(sig00000a06),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008b4)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000079b (
.C(aclk),
.CE(sig00000344),
.D(sig00000a07),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008b3)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000079c (
.C(aclk),
.CE(sig00000344),
.D(sig00000a08),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008b2)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000079d (
.C(aclk),
.CE(sig00000344),
.D(sig00000a09),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008b1)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000079e (
.C(aclk),
.CE(sig00000344),
.D(sig00000a0a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008b0)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000079f (
.C(aclk),
.CE(sig00000344),
.D(sig00000a0b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008af)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007a0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a0c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008ae)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007a1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a0d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008ad)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007a2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a0e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008ac)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007a3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a0f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008ab)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007a4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a10),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008aa)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007a5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a11),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008a9)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007a6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a12),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008a8)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007a7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a13),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008a7)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007a8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a14),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig000008a6)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007a9 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000098f),
.Q(sig00000a15)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007aa (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000098e),
.Q(sig00000a16)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007ab (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000098d),
.Q(sig00000a17)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007ac (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000098c),
.Q(sig00000a18)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007ad (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000098b),
.Q(sig00000a19)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007ae (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000098a),
.Q(sig00000a1a)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007af (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000989),
.Q(sig00000a1b)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007b0 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000988),
.Q(sig00000a1c)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007b1 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000987),
.Q(sig00000a1d)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007b2 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000986),
.Q(sig00000a1e)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007b3 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000985),
.Q(sig00000a1f)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007b4 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000984),
.Q(sig00000a20)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007b5 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000983),
.Q(sig00000a21)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007b6 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000982),
.Q(sig00000a22)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007b7 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000981),
.Q(sig00000a23)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007b8 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000980),
.Q(sig00000a24)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk000007b9 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000097f),
.Q(sig00000a25)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007ba (
.C(aclk),
.CE(sig00000344),
.D(sig00000a15),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000097e)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007bb (
.C(aclk),
.CE(sig00000344),
.D(sig00000a16),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000097d)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007bc (
.C(aclk),
.CE(sig00000344),
.D(sig00000a17),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000097c)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007bd (
.C(aclk),
.CE(sig00000344),
.D(sig00000a18),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000097b)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007be (
.C(aclk),
.CE(sig00000344),
.D(sig00000a19),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000097a)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007bf (
.C(aclk),
.CE(sig00000344),
.D(sig00000a1a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000979)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007c0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a1b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000978)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007c1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a1c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000977)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007c2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a1d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000976)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007c3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a1e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000975)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007c4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a1f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000974)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007c5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a20),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000973)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007c6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a21),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000972)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007c7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a22),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000971)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007c8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a23),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000970)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007c9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a24),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000096f)
);
FDRE #(
.INIT ( 1'b0 ))
blk000007ca (
.C(aclk),
.CE(sig00000344),
.D(sig00000a25),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000096e)
);
FDE #(
.INIT ( 1'b0 ))
blk000007d0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a7e),
.Q(sig00000b8d)
);
FDE #(
.INIT ( 1'b0 ))
blk000007d1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a7f),
.Q(sig00000b8e)
);
FDE #(
.INIT ( 1'b0 ))
blk000007d2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a80),
.Q(sig00000b8f)
);
FDE #(
.INIT ( 1'b0 ))
blk000007d3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a81),
.Q(sig00000b90)
);
FDE #(
.INIT ( 1'b0 ))
blk000007d4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a82),
.Q(sig00000b91)
);
FDE #(
.INIT ( 1'b0 ))
blk000007d5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a83),
.Q(sig00000b92)
);
FDE #(
.INIT ( 1'b0 ))
blk000007d6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a84),
.Q(sig00000b93)
);
FDE #(
.INIT ( 1'b0 ))
blk000007d7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a85),
.Q(sig00000b94)
);
FDE #(
.INIT ( 1'b0 ))
blk000007d8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a86),
.Q(sig00000b95)
);
FDE #(
.INIT ( 1'b0 ))
blk000007d9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a87),
.Q(sig00000b96)
);
FDE #(
.INIT ( 1'b0 ))
blk000007da (
.C(aclk),
.CE(sig00000344),
.D(sig00000a88),
.Q(sig00000b97)
);
FDE #(
.INIT ( 1'b0 ))
blk000007db (
.C(aclk),
.CE(sig00000344),
.D(sig00000a89),
.Q(sig00000b98)
);
FDE #(
.INIT ( 1'b0 ))
blk000007dc (
.C(aclk),
.CE(sig00000344),
.D(sig00000a8a),
.Q(sig00000b99)
);
FDE #(
.INIT ( 1'b0 ))
blk000007dd (
.C(aclk),
.CE(sig00000344),
.D(sig00000a8b),
.Q(sig00000b9a)
);
FDE #(
.INIT ( 1'b0 ))
blk000007de (
.C(aclk),
.CE(sig00000344),
.D(sig00000a8c),
.Q(sig00000b9b)
);
FDE #(
.INIT ( 1'b0 ))
blk000007df (
.C(aclk),
.CE(sig00000344),
.D(sig00000a8d),
.Q(sig00000b9c)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a8e),
.Q(sig00000b9d)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a8f),
.Q(sig00000b9e)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a49),
.Q(sig00000b9f)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a4a),
.Q(sig00000ba0)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a4b),
.Q(sig00000ba1)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a4c),
.Q(sig00000ba2)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a4d),
.Q(sig00000ba3)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a4e),
.Q(sig00000ba4)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a4f),
.Q(sig00000ba5)
);
FDE #(
.INIT ( 1'b0 ))
blk000007e9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a50),
.Q(sig00000ba6)
);
FDE #(
.INIT ( 1'b0 ))
blk000007ea (
.C(aclk),
.CE(sig00000344),
.D(sig00000a51),
.Q(sig00000ba7)
);
FDE #(
.INIT ( 1'b0 ))
blk000007eb (
.C(aclk),
.CE(sig00000344),
.D(sig00000a52),
.Q(sig00000ba8)
);
FDE #(
.INIT ( 1'b0 ))
blk000007ec (
.C(aclk),
.CE(sig00000344),
.D(sig00000a53),
.Q(sig00000ba9)
);
FDE #(
.INIT ( 1'b0 ))
blk000007ed (
.C(aclk),
.CE(sig00000344),
.D(sig00000a54),
.Q(sig00000baa)
);
FDE #(
.INIT ( 1'b0 ))
blk000007ee (
.C(aclk),
.CE(sig00000344),
.D(sig00000a55),
.Q(sig00000bab)
);
FDE #(
.INIT ( 1'b0 ))
blk000007ef (
.C(aclk),
.CE(sig00000344),
.D(sig00000a56),
.Q(sig00000bac)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a57),
.Q(sig00000bad)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a58),
.Q(sig00000bae)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a59),
.Q(sig00000baf)
);
FDE #(
.INIT ( 1'b0 ))
blk000007f3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a5a),
.Q(sig00000bb0)
);
MUXCY blk000007f4 (
.CI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.DI(sig00000be7),
.S(sig00000a37),
.O(sig00000a26)
);
MUXCY blk000007f5 (
.CI(sig00000a26),
.DI(sig00000be8),
.S(sig00000a39),
.O(sig00000a27)
);
MUXCY blk000007f6 (
.CI(sig00000a27),
.DI(sig00000be9),
.S(sig00000a3a),
.O(sig00000a28)
);
MUXCY blk000007f7 (
.CI(sig00000a28),
.DI(sig00000bea),
.S(sig00000a3b),
.O(sig00000a29)
);
MUXCY blk000007f8 (
.CI(sig00000a29),
.DI(sig00000beb),
.S(sig00000a3c),
.O(sig00000a2a)
);
MUXCY blk000007f9 (
.CI(sig00000a2a),
.DI(sig00000bec),
.S(sig00000a3d),
.O(sig00000a2b)
);
MUXCY blk000007fa (
.CI(sig00000a2b),
.DI(sig00000bed),
.S(sig00000a3e),
.O(sig00000a2c)
);
MUXCY blk000007fb (
.CI(sig00000a2c),
.DI(sig00000bee),
.S(sig00000a3f),
.O(sig00000a2d)
);
MUXCY blk000007fc (
.CI(sig00000a2d),
.DI(sig00000bef),
.S(sig00000a40),
.O(sig00000a2e)
);
MUXCY blk000007fd (
.CI(sig00000a2e),
.DI(sig00000bf0),
.S(sig00000a41),
.O(sig00000a2f)
);
MUXCY blk000007fe (
.CI(sig00000a2f),
.DI(sig00000bf1),
.S(sig00000a42),
.O(sig00000a30)
);
MUXCY blk000007ff (
.CI(sig00000a30),
.DI(sig00000bf2),
.S(sig00000a43),
.O(sig00000a31)
);
MUXCY blk00000800 (
.CI(sig00000a31),
.DI(sig00000bf3),
.S(sig00000a44),
.O(sig00000a32)
);
MUXCY blk00000801 (
.CI(sig00000a32),
.DI(sig00000bf4),
.S(sig00000a45),
.O(sig00000a33)
);
MUXCY blk00000802 (
.CI(sig00000a33),
.DI(sig00000bf5),
.S(sig00000a46),
.O(sig00000a34)
);
MUXCY blk00000803 (
.CI(sig00000a34),
.DI(sig00000bf6),
.S(sig00000a47),
.O(sig00000a35)
);
MUXCY blk00000804 (
.CI(sig00000a35),
.DI(sig00000bf7),
.S(sig00000a48),
.O(sig00000a36)
);
XORCY blk00000805 (
.CI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.LI(sig00000a37),
.O(sig00000a49)
);
XORCY blk00000806 (
.CI(sig00000a26),
.LI(sig00000a39),
.O(sig00000a4a)
);
XORCY blk00000807 (
.CI(sig00000a27),
.LI(sig00000a3a),
.O(sig00000a4b)
);
XORCY blk00000808 (
.CI(sig00000a28),
.LI(sig00000a3b),
.O(sig00000a4c)
);
XORCY blk00000809 (
.CI(sig00000a29),
.LI(sig00000a3c),
.O(sig00000a4d)
);
XORCY blk0000080a (
.CI(sig00000a2a),
.LI(sig00000a3d),
.O(sig00000a4e)
);
XORCY blk0000080b (
.CI(sig00000a2b),
.LI(sig00000a3e),
.O(sig00000a4f)
);
XORCY blk0000080c (
.CI(sig00000a2c),
.LI(sig00000a3f),
.O(sig00000a50)
);
XORCY blk0000080d (
.CI(sig00000a2d),
.LI(sig00000a40),
.O(sig00000a51)
);
XORCY blk0000080e (
.CI(sig00000a2e),
.LI(sig00000a41),
.O(sig00000a52)
);
XORCY blk0000080f (
.CI(sig00000a2f),
.LI(sig00000a42),
.O(sig00000a53)
);
XORCY blk00000810 (
.CI(sig00000a30),
.LI(sig00000a43),
.O(sig00000a54)
);
XORCY blk00000811 (
.CI(sig00000a31),
.LI(sig00000a44),
.O(sig00000a55)
);
XORCY blk00000812 (
.CI(sig00000a32),
.LI(sig00000a45),
.O(sig00000a56)
);
XORCY blk00000813 (
.CI(sig00000a33),
.LI(sig00000a46),
.O(sig00000a57)
);
XORCY blk00000814 (
.CI(sig00000a34),
.LI(sig00000a47),
.O(sig00000a58)
);
XORCY blk00000815 (
.CI(sig00000a35),
.LI(sig00000a48),
.O(sig00000a59)
);
XORCY blk00000816 (
.CI(sig00000a36),
.LI(sig00000a38),
.O(sig00000a5a)
);
MUXCY blk00000817 (
.CI(sig00000344),
.DI(sig00000be7),
.S(sig00000a6c),
.O(sig00000a5b)
);
MUXCY blk00000818 (
.CI(sig00000a5b),
.DI(sig00000be8),
.S(sig00000a6e),
.O(sig00000a5c)
);
MUXCY blk00000819 (
.CI(sig00000a5c),
.DI(sig00000be9),
.S(sig00000a6f),
.O(sig00000a5d)
);
MUXCY blk0000081a (
.CI(sig00000a5d),
.DI(sig00000bea),
.S(sig00000a70),
.O(sig00000a5e)
);
MUXCY blk0000081b (
.CI(sig00000a5e),
.DI(sig00000beb),
.S(sig00000a71),
.O(sig00000a5f)
);
MUXCY blk0000081c (
.CI(sig00000a5f),
.DI(sig00000bec),
.S(sig00000a72),
.O(sig00000a60)
);
MUXCY blk0000081d (
.CI(sig00000a60),
.DI(sig00000bed),
.S(sig00000a73),
.O(sig00000a61)
);
MUXCY blk0000081e (
.CI(sig00000a61),
.DI(sig00000bee),
.S(sig00000a74),
.O(sig00000a62)
);
MUXCY blk0000081f (
.CI(sig00000a62),
.DI(sig00000bef),
.S(sig00000a75),
.O(sig00000a63)
);
MUXCY blk00000820 (
.CI(sig00000a63),
.DI(sig00000bf0),
.S(sig00000a76),
.O(sig00000a64)
);
MUXCY blk00000821 (
.CI(sig00000a64),
.DI(sig00000bf1),
.S(sig00000a77),
.O(sig00000a65)
);
MUXCY blk00000822 (
.CI(sig00000a65),
.DI(sig00000bf2),
.S(sig00000a78),
.O(sig00000a66)
);
MUXCY blk00000823 (
.CI(sig00000a66),
.DI(sig00000bf3),
.S(sig00000a79),
.O(sig00000a67)
);
MUXCY blk00000824 (
.CI(sig00000a67),
.DI(sig00000bf4),
.S(sig00000a7a),
.O(sig00000a68)
);
MUXCY blk00000825 (
.CI(sig00000a68),
.DI(sig00000bf5),
.S(sig00000a7b),
.O(sig00000a69)
);
MUXCY blk00000826 (
.CI(sig00000a69),
.DI(sig00000bf6),
.S(sig00000a7c),
.O(sig00000a6a)
);
MUXCY blk00000827 (
.CI(sig00000a6a),
.DI(sig00000bf7),
.S(sig00000a7d),
.O(sig00000a6b)
);
XORCY blk00000828 (
.CI(sig00000344),
.LI(sig00000a6c),
.O(sig00000a7e)
);
XORCY blk00000829 (
.CI(sig00000a5b),
.LI(sig00000a6e),
.O(sig00000a7f)
);
XORCY blk0000082a (
.CI(sig00000a5c),
.LI(sig00000a6f),
.O(sig00000a80)
);
XORCY blk0000082b (
.CI(sig00000a5d),
.LI(sig00000a70),
.O(sig00000a81)
);
XORCY blk0000082c (
.CI(sig00000a5e),
.LI(sig00000a71),
.O(sig00000a82)
);
XORCY blk0000082d (
.CI(sig00000a5f),
.LI(sig00000a72),
.O(sig00000a83)
);
XORCY blk0000082e (
.CI(sig00000a60),
.LI(sig00000a73),
.O(sig00000a84)
);
XORCY blk0000082f (
.CI(sig00000a61),
.LI(sig00000a74),
.O(sig00000a85)
);
XORCY blk00000830 (
.CI(sig00000a62),
.LI(sig00000a75),
.O(sig00000a86)
);
XORCY blk00000831 (
.CI(sig00000a63),
.LI(sig00000a76),
.O(sig00000a87)
);
XORCY blk00000832 (
.CI(sig00000a64),
.LI(sig00000a77),
.O(sig00000a88)
);
XORCY blk00000833 (
.CI(sig00000a65),
.LI(sig00000a78),
.O(sig00000a89)
);
XORCY blk00000834 (
.CI(sig00000a66),
.LI(sig00000a79),
.O(sig00000a8a)
);
XORCY blk00000835 (
.CI(sig00000a67),
.LI(sig00000a7a),
.O(sig00000a8b)
);
XORCY blk00000836 (
.CI(sig00000a68),
.LI(sig00000a7b),
.O(sig00000a8c)
);
XORCY blk00000837 (
.CI(sig00000a69),
.LI(sig00000a7c),
.O(sig00000a8d)
);
XORCY blk00000838 (
.CI(sig00000a6a),
.LI(sig00000a7d),
.O(sig00000a8e)
);
XORCY blk00000839 (
.CI(sig00000a6b),
.LI(sig00000a6d),
.O(sig00000a8f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000842 (
.I0(sig00000b45),
.I1(sig00000bd5),
.I2(sig00000c20),
.O(sig00000a90)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000843 (
.I0(sig00000b46),
.I1(sig00000bd6),
.I2(sig00000c20),
.O(sig00000a91)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000844 (
.I0(sig00000b47),
.I1(sig00000bd7),
.I2(sig00000c20),
.O(sig00000a92)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000845 (
.I0(sig00000b48),
.I1(sig00000bd8),
.I2(sig00000c20),
.O(sig00000a93)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000846 (
.I0(sig00000b49),
.I1(sig00000bd9),
.I2(sig00000c20),
.O(sig00000a94)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000847 (
.I0(sig00000b4a),
.I1(sig00000bda),
.I2(sig00000c20),
.O(sig00000a95)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000848 (
.I0(sig00000b4b),
.I1(sig00000bdb),
.I2(sig00000c20),
.O(sig00000a96)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000849 (
.I0(sig00000b4c),
.I1(sig00000bdc),
.I2(sig00000c20),
.O(sig00000a97)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000084a (
.I0(sig00000b4d),
.I1(sig00000bdd),
.I2(sig00000c20),
.O(sig00000a98)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000084b (
.I0(sig00000b4e),
.I1(sig00000bde),
.I2(sig00000c20),
.O(sig00000a99)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000084c (
.I0(sig00000b4f),
.I1(sig00000bdf),
.I2(sig00000c20),
.O(sig00000a9a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000084d (
.I0(sig00000b50),
.I1(sig00000be0),
.I2(sig00000c20),
.O(sig00000a9b)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000084e (
.I0(sig00000b51),
.I1(sig00000be1),
.I2(sig00000c20),
.O(sig00000a9c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000084f (
.I0(sig00000b52),
.I1(sig00000be2),
.I2(sig00000c20),
.O(sig00000a9d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000850 (
.I0(sig00000b53),
.I1(sig00000be3),
.I2(sig00000c20),
.O(sig00000a9e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000851 (
.I0(sig00000b54),
.I1(sig00000be4),
.I2(sig00000c20),
.O(sig00000a9f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000852 (
.I0(sig00000b55),
.I1(sig00000be5),
.I2(sig00000c20),
.O(sig00000aa0)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000853 (
.I0(sig00000b56),
.I1(sig00000be6),
.I2(sig00000c20),
.O(sig00000aa1)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000854 (
.I0(sig00000bd5),
.I1(sig00000b45),
.I2(sig00000c20),
.O(sig00000aa2)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000855 (
.I0(sig00000bd6),
.I1(sig00000b46),
.I2(sig00000c20),
.O(sig00000aa3)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000856 (
.I0(sig00000bd7),
.I1(sig00000b47),
.I2(sig00000c20),
.O(sig00000aa4)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000857 (
.I0(sig00000bd8),
.I1(sig00000b48),
.I2(sig00000c20),
.O(sig00000aa5)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000858 (
.I0(sig00000bd9),
.I1(sig00000b49),
.I2(sig00000c20),
.O(sig00000aa6)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000859 (
.I0(sig00000bda),
.I1(sig00000b4a),
.I2(sig00000c20),
.O(sig00000aa7)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000085a (
.I0(sig00000bdb),
.I1(sig00000b4b),
.I2(sig00000c20),
.O(sig00000aa8)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000085b (
.I0(sig00000bdc),
.I1(sig00000b4c),
.I2(sig00000c20),
.O(sig00000aa9)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000085c (
.I0(sig00000bdd),
.I1(sig00000b4d),
.I2(sig00000c20),
.O(sig00000aaa)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000085d (
.I0(sig00000bde),
.I1(sig00000b4e),
.I2(sig00000c20),
.O(sig00000aab)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000085e (
.I0(sig00000bdf),
.I1(sig00000b4f),
.I2(sig00000c20),
.O(sig00000aac)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000085f (
.I0(sig00000be0),
.I1(sig00000b50),
.I2(sig00000c20),
.O(sig00000aad)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000860 (
.I0(sig00000be1),
.I1(sig00000b51),
.I2(sig00000c20),
.O(sig00000aae)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000861 (
.I0(sig00000be2),
.I1(sig00000b52),
.I2(sig00000c20),
.O(sig00000aaf)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000862 (
.I0(sig00000be3),
.I1(sig00000b53),
.I2(sig00000c20),
.O(sig00000ab0)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000863 (
.I0(sig00000be4),
.I1(sig00000b54),
.I2(sig00000c20),
.O(sig00000ab1)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000864 (
.I0(sig00000be5),
.I1(sig00000b55),
.I2(sig00000c20),
.O(sig00000ab2)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000865 (
.I0(sig00000be6),
.I1(sig00000b56),
.I2(sig00000c20),
.O(sig00000ab3)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000866 (
.I0(sig00000b9f),
.I1(sig00000b7b),
.I2(sig00000c1e),
.O(sig00000ab4)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000867 (
.I0(sig00000ba0),
.I1(sig00000b7c),
.I2(sig00000c1e),
.O(sig00000ab5)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000868 (
.I0(sig00000ba1),
.I1(sig00000b7d),
.I2(sig00000c1e),
.O(sig00000ab6)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000869 (
.I0(sig00000ba2),
.I1(sig00000b7e),
.I2(sig00000c1e),
.O(sig00000ab7)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000086a (
.I0(sig00000ba3),
.I1(sig00000b7f),
.I2(sig00000c1e),
.O(sig00000ab8)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000086b (
.I0(sig00000ba4),
.I1(sig00000b80),
.I2(sig00000c1e),
.O(sig00000ab9)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000086c (
.I0(sig00000ba5),
.I1(sig00000b81),
.I2(sig00000c1e),
.O(sig00000aba)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000086d (
.I0(sig00000ba6),
.I1(sig00000b82),
.I2(sig00000c1e),
.O(sig00000abb)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000086e (
.I0(sig00000ba7),
.I1(sig00000b83),
.I2(sig00000c1e),
.O(sig00000abc)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000086f (
.I0(sig00000ba8),
.I1(sig00000b84),
.I2(sig00000c1e),
.O(sig00000abd)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000870 (
.I0(sig00000ba9),
.I1(sig00000b85),
.I2(sig00000c1e),
.O(sig00000abe)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000871 (
.I0(sig00000baa),
.I1(sig00000b86),
.I2(sig00000c1e),
.O(sig00000abf)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000872 (
.I0(sig00000bab),
.I1(sig00000b87),
.I2(sig00000c1e),
.O(sig00000ac0)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000873 (
.I0(sig00000bac),
.I1(sig00000b88),
.I2(sig00000c1e),
.O(sig00000ac1)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000874 (
.I0(sig00000bad),
.I1(sig00000b89),
.I2(sig00000c1e),
.O(sig00000ac2)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000875 (
.I0(sig00000bae),
.I1(sig00000b8a),
.I2(sig00000c1e),
.O(sig00000ac3)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000876 (
.I0(sig00000baf),
.I1(sig00000b8b),
.I2(sig00000c1e),
.O(sig00000ac4)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000877 (
.I0(sig00000bb0),
.I1(sig00000b8c),
.I2(sig00000c1e),
.O(sig00000ac5)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000878 (
.I0(sig00000b7b),
.I1(sig00000b9f),
.I2(sig00000c1e),
.O(sig00000ac6)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000879 (
.I0(sig00000b7c),
.I1(sig00000ba0),
.I2(sig00000c1e),
.O(sig00000ac7)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000087a (
.I0(sig00000b7d),
.I1(sig00000ba1),
.I2(sig00000c1e),
.O(sig00000ac8)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000087b (
.I0(sig00000b7e),
.I1(sig00000ba2),
.I2(sig00000c1e),
.O(sig00000ac9)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000087c (
.I0(sig00000b7f),
.I1(sig00000ba3),
.I2(sig00000c1e),
.O(sig00000aca)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000087d (
.I0(sig00000b80),
.I1(sig00000ba4),
.I2(sig00000c1e),
.O(sig00000acb)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000087e (
.I0(sig00000b81),
.I1(sig00000ba5),
.I2(sig00000c1e),
.O(sig00000acc)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000087f (
.I0(sig00000b82),
.I1(sig00000ba6),
.I2(sig00000c1e),
.O(sig00000acd)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000880 (
.I0(sig00000b83),
.I1(sig00000ba7),
.I2(sig00000c1e),
.O(sig00000ace)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000881 (
.I0(sig00000b84),
.I1(sig00000ba8),
.I2(sig00000c1e),
.O(sig00000acf)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000882 (
.I0(sig00000b85),
.I1(sig00000ba9),
.I2(sig00000c1e),
.O(sig00000ad0)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000883 (
.I0(sig00000b86),
.I1(sig00000baa),
.I2(sig00000c1e),
.O(sig00000ad1)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000884 (
.I0(sig00000b87),
.I1(sig00000bab),
.I2(sig00000c1e),
.O(sig00000ad2)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000885 (
.I0(sig00000b88),
.I1(sig00000bac),
.I2(sig00000c1e),
.O(sig00000ad3)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000886 (
.I0(sig00000b89),
.I1(sig00000bad),
.I2(sig00000c1e),
.O(sig00000ad4)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000887 (
.I0(sig00000b8a),
.I1(sig00000bae),
.I2(sig00000c1e),
.O(sig00000ad5)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000888 (
.I0(sig00000b8b),
.I1(sig00000baf),
.I2(sig00000c1e),
.O(sig00000ad6)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000889 (
.I0(sig00000b8c),
.I1(sig00000bb0),
.I2(sig00000c1e),
.O(sig00000ad7)
);
MUXCY blk0000088a (
.CI(sig00000b0d),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ad8),
.O(sig00000aea)
);
XORCY blk0000088b (
.CI(sig00000b0d),
.LI(sig00000ad8),
.O(sig00000aeb)
);
MUXCY blk0000088c (
.CI(sig00000aea),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ad9),
.O(sig00000aec)
);
XORCY blk0000088d (
.CI(sig00000aea),
.LI(sig00000ad9),
.O(sig00000aed)
);
MUXCY blk0000088e (
.CI(sig00000aec),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ada),
.O(sig00000aee)
);
XORCY blk0000088f (
.CI(sig00000aec),
.LI(sig00000ada),
.O(sig00000aef)
);
MUXCY blk00000890 (
.CI(sig00000aee),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000adb),
.O(sig00000af0)
);
XORCY blk00000891 (
.CI(sig00000aee),
.LI(sig00000adb),
.O(sig00000af1)
);
MUXCY blk00000892 (
.CI(sig00000af0),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000adc),
.O(sig00000af2)
);
XORCY blk00000893 (
.CI(sig00000af0),
.LI(sig00000adc),
.O(sig00000af3)
);
MUXCY blk00000894 (
.CI(sig00000af2),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000add),
.O(sig00000af4)
);
XORCY blk00000895 (
.CI(sig00000af2),
.LI(sig00000add),
.O(sig00000af5)
);
MUXCY blk00000896 (
.CI(sig00000af4),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ade),
.O(sig00000af6)
);
XORCY blk00000897 (
.CI(sig00000af4),
.LI(sig00000ade),
.O(sig00000af7)
);
MUXCY blk00000898 (
.CI(sig00000af6),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000adf),
.O(sig00000af8)
);
XORCY blk00000899 (
.CI(sig00000af6),
.LI(sig00000adf),
.O(sig00000af9)
);
MUXCY blk0000089a (
.CI(sig00000af8),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ae0),
.O(sig00000afa)
);
XORCY blk0000089b (
.CI(sig00000af8),
.LI(sig00000ae0),
.O(sig00000afb)
);
MUXCY blk0000089c (
.CI(sig00000afa),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ae1),
.O(sig00000afc)
);
XORCY blk0000089d (
.CI(sig00000afa),
.LI(sig00000ae1),
.O(sig00000afd)
);
MUXCY blk0000089e (
.CI(sig00000afc),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ae2),
.O(sig00000afe)
);
XORCY blk0000089f (
.CI(sig00000afc),
.LI(sig00000ae2),
.O(sig00000aff)
);
MUXCY blk000008a0 (
.CI(sig00000afe),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ae3),
.O(sig00000b00)
);
XORCY blk000008a1 (
.CI(sig00000afe),
.LI(sig00000ae3),
.O(sig00000b01)
);
MUXCY blk000008a2 (
.CI(sig00000b00),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ae4),
.O(sig00000b02)
);
XORCY blk000008a3 (
.CI(sig00000b00),
.LI(sig00000ae4),
.O(sig00000b03)
);
MUXCY blk000008a4 (
.CI(sig00000b02),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ae5),
.O(sig00000b04)
);
XORCY blk000008a5 (
.CI(sig00000b02),
.LI(sig00000ae5),
.O(sig00000b05)
);
MUXCY blk000008a6 (
.CI(sig00000b04),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ae6),
.O(sig00000b06)
);
XORCY blk000008a7 (
.CI(sig00000b04),
.LI(sig00000ae6),
.O(sig00000b07)
);
MUXCY blk000008a8 (
.CI(sig00000b06),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ae7),
.O(sig00000b08)
);
XORCY blk000008a9 (
.CI(sig00000b06),
.LI(sig00000ae7),
.O(sig00000b09)
);
MUXCY blk000008aa (
.CI(sig00000b08),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000c63),
.O(sig00000b0a)
);
XORCY blk000008ab (
.CI(sig00000b08),
.LI(sig00000c63),
.O(sig00000b0b)
);
MUXCY blk000008ac (
.CI(sig00000b0a),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ae8),
.O(NLW_blk000008ac_O_UNCONNECTED)
);
XORCY blk000008ad (
.CI(sig00000b0a),
.LI(sig00000ae8),
.O(sig00000b0c)
);
MUXCY blk000008ae (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000ae9),
.O(sig00000b0d)
);
MUXCY blk000008af (
.CI(sig00000b43),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b0e),
.O(sig00000b20)
);
XORCY blk000008b0 (
.CI(sig00000b43),
.LI(sig00000b0e),
.O(sig00000b21)
);
MUXCY blk000008b1 (
.CI(sig00000b20),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b0f),
.O(sig00000b22)
);
XORCY blk000008b2 (
.CI(sig00000b20),
.LI(sig00000b0f),
.O(sig00000b23)
);
MUXCY blk000008b3 (
.CI(sig00000b22),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b10),
.O(sig00000b24)
);
XORCY blk000008b4 (
.CI(sig00000b22),
.LI(sig00000b10),
.O(sig00000b25)
);
MUXCY blk000008b5 (
.CI(sig00000b24),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b11),
.O(sig00000b26)
);
XORCY blk000008b6 (
.CI(sig00000b24),
.LI(sig00000b11),
.O(sig00000b27)
);
MUXCY blk000008b7 (
.CI(sig00000b26),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b12),
.O(sig00000b28)
);
XORCY blk000008b8 (
.CI(sig00000b26),
.LI(sig00000b12),
.O(sig00000b29)
);
MUXCY blk000008b9 (
.CI(sig00000b28),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b13),
.O(sig00000b2a)
);
XORCY blk000008ba (
.CI(sig00000b28),
.LI(sig00000b13),
.O(sig00000b2b)
);
MUXCY blk000008bb (
.CI(sig00000b2a),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b14),
.O(sig00000b2c)
);
XORCY blk000008bc (
.CI(sig00000b2a),
.LI(sig00000b14),
.O(sig00000b2d)
);
MUXCY blk000008bd (
.CI(sig00000b2c),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b15),
.O(sig00000b2e)
);
XORCY blk000008be (
.CI(sig00000b2c),
.LI(sig00000b15),
.O(sig00000b2f)
);
MUXCY blk000008bf (
.CI(sig00000b2e),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b16),
.O(sig00000b30)
);
XORCY blk000008c0 (
.CI(sig00000b2e),
.LI(sig00000b16),
.O(sig00000b31)
);
MUXCY blk000008c1 (
.CI(sig00000b30),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b17),
.O(sig00000b32)
);
XORCY blk000008c2 (
.CI(sig00000b30),
.LI(sig00000b17),
.O(sig00000b33)
);
MUXCY blk000008c3 (
.CI(sig00000b32),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b18),
.O(sig00000b34)
);
XORCY blk000008c4 (
.CI(sig00000b32),
.LI(sig00000b18),
.O(sig00000b35)
);
MUXCY blk000008c5 (
.CI(sig00000b34),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b19),
.O(sig00000b36)
);
XORCY blk000008c6 (
.CI(sig00000b34),
.LI(sig00000b19),
.O(sig00000b37)
);
MUXCY blk000008c7 (
.CI(sig00000b36),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b1a),
.O(sig00000b38)
);
XORCY blk000008c8 (
.CI(sig00000b36),
.LI(sig00000b1a),
.O(sig00000b39)
);
MUXCY blk000008c9 (
.CI(sig00000b38),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b1b),
.O(sig00000b3a)
);
XORCY blk000008ca (
.CI(sig00000b38),
.LI(sig00000b1b),
.O(sig00000b3b)
);
MUXCY blk000008cb (
.CI(sig00000b3a),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b1c),
.O(sig00000b3c)
);
XORCY blk000008cc (
.CI(sig00000b3a),
.LI(sig00000b1c),
.O(sig00000b3d)
);
MUXCY blk000008cd (
.CI(sig00000b3c),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b1d),
.O(sig00000b3e)
);
XORCY blk000008ce (
.CI(sig00000b3c),
.LI(sig00000b1d),
.O(sig00000b3f)
);
MUXCY blk000008cf (
.CI(sig00000b3e),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000c64),
.O(sig00000b40)
);
XORCY blk000008d0 (
.CI(sig00000b3e),
.LI(sig00000c64),
.O(sig00000b41)
);
MUXCY blk000008d1 (
.CI(sig00000b40),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b1e),
.O(NLW_blk000008d1_O_UNCONNECTED)
);
XORCY blk000008d2 (
.CI(sig00000b40),
.LI(sig00000b1e),
.O(sig00000b42)
);
MUXCY blk000008d3 (
.CI(sig00000344),
.DI(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.S(sig00000b1f),
.O(sig00000b43)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008d4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a90),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bc3)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008d5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a91),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bc4)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008d6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a92),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bc5)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008d7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a93),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bc6)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008d8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a94),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bc7)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008d9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a95),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bc8)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008da (
.C(aclk),
.CE(sig00000344),
.D(sig00000a96),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bc9)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008db (
.C(aclk),
.CE(sig00000344),
.D(sig00000a97),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bca)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008dc (
.C(aclk),
.CE(sig00000344),
.D(sig00000a98),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bcb)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008dd (
.C(aclk),
.CE(sig00000344),
.D(sig00000a99),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bcc)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008de (
.C(aclk),
.CE(sig00000344),
.D(sig00000a9a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bcd)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008df (
.C(aclk),
.CE(sig00000344),
.D(sig00000a9b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bce)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008e0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a9c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bcf)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008e1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a9d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bd0)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008e2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a9e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bd1)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008e3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000a9f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bd2)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008e4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000aa0),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bd3)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008e5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000aa1),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bd4)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008e6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000aa2),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bb1)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008e7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000aa3),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bb2)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008e8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000aa4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bb3)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008e9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000aa5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bb4)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008ea (
.C(aclk),
.CE(sig00000344),
.D(sig00000aa6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bb5)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008eb (
.C(aclk),
.CE(sig00000344),
.D(sig00000aa7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bb6)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008ec (
.C(aclk),
.CE(sig00000344),
.D(sig00000aa8),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bb7)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008ed (
.C(aclk),
.CE(sig00000344),
.D(sig00000aa9),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bb8)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008ee (
.C(aclk),
.CE(sig00000344),
.D(sig00000aaa),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bb9)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008ef (
.C(aclk),
.CE(sig00000344),
.D(sig00000aab),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bba)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008f0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000aac),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bbb)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008f1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000aad),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bbc)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008f2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000aae),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bbd)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008f3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000aaf),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bbe)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008f4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ab0),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bbf)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008f5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ab1),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bc0)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008f6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ab2),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bc1)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008f7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ab3),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000bc2)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008f8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ab4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b69)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008f9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ab5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b6a)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008fa (
.C(aclk),
.CE(sig00000344),
.D(sig00000ab6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b6b)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008fb (
.C(aclk),
.CE(sig00000344),
.D(sig00000ab7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b6c)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008fc (
.C(aclk),
.CE(sig00000344),
.D(sig00000ab8),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b6d)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008fd (
.C(aclk),
.CE(sig00000344),
.D(sig00000ab9),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b6e)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008fe (
.C(aclk),
.CE(sig00000344),
.D(sig00000aba),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b6f)
);
FDRE #(
.INIT ( 1'b0 ))
blk000008ff (
.C(aclk),
.CE(sig00000344),
.D(sig00000abb),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b70)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000900 (
.C(aclk),
.CE(sig00000344),
.D(sig00000abc),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b71)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000901 (
.C(aclk),
.CE(sig00000344),
.D(sig00000abd),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b72)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000902 (
.C(aclk),
.CE(sig00000344),
.D(sig00000abe),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b73)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000903 (
.C(aclk),
.CE(sig00000344),
.D(sig00000abf),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b74)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000904 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ac0),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b75)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000905 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ac1),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b76)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000906 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ac2),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b77)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000907 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ac3),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b78)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000908 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ac4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b79)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000909 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ac5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000b7a)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000090a (
.C(aclk),
.CE(sig00000344),
.D(sig00000ac6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000868)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000090b (
.C(aclk),
.CE(sig00000344),
.D(sig00000ac7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000869)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000090c (
.C(aclk),
.CE(sig00000344),
.D(sig00000ac8),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000086a)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000090d (
.C(aclk),
.CE(sig00000344),
.D(sig00000ac9),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000086b)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000090e (
.C(aclk),
.CE(sig00000344),
.D(sig00000aca),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000086c)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000090f (
.C(aclk),
.CE(sig00000344),
.D(sig00000acb),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000086d)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000910 (
.C(aclk),
.CE(sig00000344),
.D(sig00000acc),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000086e)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000911 (
.C(aclk),
.CE(sig00000344),
.D(sig00000acd),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000086f)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000912 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ace),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000870)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000913 (
.C(aclk),
.CE(sig00000344),
.D(sig00000acf),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000871)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000914 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ad0),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000872)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000915 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ad1),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000873)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000916 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ad2),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000874)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000917 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ad3),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000875)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000918 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ad4),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000876)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000919 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ad5),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000877)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000091a (
.C(aclk),
.CE(sig00000344),
.D(sig00000ad6),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000878)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000091b (
.C(aclk),
.CE(sig00000344),
.D(sig00000ad7),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000879)
);
FDE #(
.INIT ( 1'b0 ))
blk0000091c (
.C(aclk),
.CE(sig00000344),
.D(sig00000aeb),
.Q(sig00000bf9)
);
FDE #(
.INIT ( 1'b0 ))
blk0000091d (
.C(aclk),
.CE(sig00000344),
.D(sig00000aed),
.Q(sig00000bfa)
);
FDE #(
.INIT ( 1'b0 ))
blk0000091e (
.C(aclk),
.CE(sig00000344),
.D(sig00000aef),
.Q(sig00000bfb)
);
FDE #(
.INIT ( 1'b0 ))
blk0000091f (
.C(aclk),
.CE(sig00000344),
.D(sig00000af1),
.Q(sig00000bfc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000920 (
.C(aclk),
.CE(sig00000344),
.D(sig00000af3),
.Q(sig00000bfd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000921 (
.C(aclk),
.CE(sig00000344),
.D(sig00000af5),
.Q(sig00000bfe)
);
FDE #(
.INIT ( 1'b0 ))
blk00000922 (
.C(aclk),
.CE(sig00000344),
.D(sig00000af7),
.Q(sig00000bff)
);
FDE #(
.INIT ( 1'b0 ))
blk00000923 (
.C(aclk),
.CE(sig00000344),
.D(sig00000af9),
.Q(sig00000c00)
);
FDE #(
.INIT ( 1'b0 ))
blk00000924 (
.C(aclk),
.CE(sig00000344),
.D(sig00000afb),
.Q(sig00000c01)
);
FDE #(
.INIT ( 1'b0 ))
blk00000925 (
.C(aclk),
.CE(sig00000344),
.D(sig00000afd),
.Q(sig00000c02)
);
FDE #(
.INIT ( 1'b0 ))
blk00000926 (
.C(aclk),
.CE(sig00000344),
.D(sig00000aff),
.Q(sig00000c03)
);
FDE #(
.INIT ( 1'b0 ))
blk00000927 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b01),
.Q(sig00000c04)
);
FDE #(
.INIT ( 1'b0 ))
blk00000928 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b03),
.Q(sig00000c05)
);
FDE #(
.INIT ( 1'b0 ))
blk00000929 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b05),
.Q(sig00000c06)
);
FDE #(
.INIT ( 1'b0 ))
blk0000092a (
.C(aclk),
.CE(sig00000344),
.D(sig00000b07),
.Q(sig00000c07)
);
FDE #(
.INIT ( 1'b0 ))
blk0000092b (
.C(aclk),
.CE(sig00000344),
.D(sig00000b09),
.Q(sig00000c08)
);
FDE #(
.INIT ( 1'b0 ))
blk0000092c (
.C(aclk),
.CE(sig00000344),
.D(sig00000b0b),
.Q(sig00000c09)
);
FDE #(
.INIT ( 1'b0 ))
blk0000092d (
.C(aclk),
.CE(sig00000344),
.D(sig00000b0c),
.Q(sig00000c0a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000092e (
.C(aclk),
.CE(sig00000344),
.D(sig00000b21),
.Q(sig00000c0b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000092f (
.C(aclk),
.CE(sig00000344),
.D(sig00000b23),
.Q(sig00000c0c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000930 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b25),
.Q(sig00000c0d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000931 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b27),
.Q(sig00000c0e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000932 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b29),
.Q(sig00000c0f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000933 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b2b),
.Q(sig00000c10)
);
FDE #(
.INIT ( 1'b0 ))
blk00000934 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b2d),
.Q(sig00000c11)
);
FDE #(
.INIT ( 1'b0 ))
blk00000935 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b2f),
.Q(sig00000c12)
);
FDE #(
.INIT ( 1'b0 ))
blk00000936 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b31),
.Q(sig00000c13)
);
FDE #(
.INIT ( 1'b0 ))
blk00000937 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b33),
.Q(sig00000c14)
);
FDE #(
.INIT ( 1'b0 ))
blk00000938 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b35),
.Q(sig00000c15)
);
FDE #(
.INIT ( 1'b0 ))
blk00000939 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b37),
.Q(sig00000c16)
);
FDE #(
.INIT ( 1'b0 ))
blk0000093a (
.C(aclk),
.CE(sig00000344),
.D(sig00000b39),
.Q(sig00000c17)
);
FDE #(
.INIT ( 1'b0 ))
blk0000093b (
.C(aclk),
.CE(sig00000344),
.D(sig00000b3b),
.Q(sig00000c18)
);
FDE #(
.INIT ( 1'b0 ))
blk0000093c (
.C(aclk),
.CE(sig00000344),
.D(sig00000b3d),
.Q(sig00000c19)
);
FDE #(
.INIT ( 1'b0 ))
blk0000093d (
.C(aclk),
.CE(sig00000344),
.D(sig00000b3f),
.Q(sig00000c1a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000093e (
.C(aclk),
.CE(sig00000344),
.D(sig00000b41),
.Q(sig00000c1b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000093f (
.C(aclk),
.CE(sig00000344),
.D(sig00000b42),
.Q(sig00000c1c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000940 (
.C(aclk),
.CE(sig00000344),
.D(sig0000088e),
.Q(sig00000c22)
);
FDE #(
.INIT ( 1'b0 ))
blk00000941 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c1f),
.Q(sig00000c1e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000942 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b44),
.Q(sig00000c1d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000943 (
.C(aclk),
.CE(sig00000344),
.D(sig00000893),
.Q(sig00000c21)
);
FD #(
.INIT ( 1'b0 ))
blk00000944 (
.C(aclk),
.D(sig00000c1c),
.Q(sig00000b56)
);
FD #(
.INIT ( 1'b0 ))
blk00000945 (
.C(aclk),
.D(sig00000c1b),
.Q(sig00000b55)
);
FD #(
.INIT ( 1'b0 ))
blk00000946 (
.C(aclk),
.D(sig00000c1a),
.Q(sig00000b54)
);
FD #(
.INIT ( 1'b0 ))
blk00000947 (
.C(aclk),
.D(sig00000c19),
.Q(sig00000b53)
);
FD #(
.INIT ( 1'b0 ))
blk00000948 (
.C(aclk),
.D(sig00000c18),
.Q(sig00000b52)
);
FD #(
.INIT ( 1'b0 ))
blk00000949 (
.C(aclk),
.D(sig00000c17),
.Q(sig00000b51)
);
FD #(
.INIT ( 1'b0 ))
blk0000094a (
.C(aclk),
.D(sig00000c16),
.Q(sig00000b50)
);
FD #(
.INIT ( 1'b0 ))
blk0000094b (
.C(aclk),
.D(sig00000c15),
.Q(sig00000b4f)
);
FD #(
.INIT ( 1'b0 ))
blk0000094c (
.C(aclk),
.D(sig00000c14),
.Q(sig00000b4e)
);
FD #(
.INIT ( 1'b0 ))
blk0000094d (
.C(aclk),
.D(sig00000c13),
.Q(sig00000b4d)
);
FD #(
.INIT ( 1'b0 ))
blk0000094e (
.C(aclk),
.D(sig00000c12),
.Q(sig00000b4c)
);
FD #(
.INIT ( 1'b0 ))
blk0000094f (
.C(aclk),
.D(sig00000c11),
.Q(sig00000b4b)
);
FD #(
.INIT ( 1'b0 ))
blk00000950 (
.C(aclk),
.D(sig00000c10),
.Q(sig00000b4a)
);
FD #(
.INIT ( 1'b0 ))
blk00000951 (
.C(aclk),
.D(sig00000c0f),
.Q(sig00000b49)
);
FD #(
.INIT ( 1'b0 ))
blk00000952 (
.C(aclk),
.D(sig00000c0e),
.Q(sig00000b48)
);
FD #(
.INIT ( 1'b0 ))
blk00000953 (
.C(aclk),
.D(sig00000c0d),
.Q(sig00000b47)
);
FD #(
.INIT ( 1'b0 ))
blk00000954 (
.C(aclk),
.D(sig00000c0c),
.Q(sig00000b46)
);
FD #(
.INIT ( 1'b0 ))
blk00000955 (
.C(aclk),
.D(sig00000c0b),
.Q(sig00000b45)
);
FD #(
.INIT ( 1'b0 ))
blk00000956 (
.C(aclk),
.D(sig00000c0a),
.Q(sig00000b68)
);
FD #(
.INIT ( 1'b0 ))
blk00000957 (
.C(aclk),
.D(sig00000c09),
.Q(sig00000b67)
);
FD #(
.INIT ( 1'b0 ))
blk00000958 (
.C(aclk),
.D(sig00000c08),
.Q(sig00000b66)
);
FD #(
.INIT ( 1'b0 ))
blk00000959 (
.C(aclk),
.D(sig00000c07),
.Q(sig00000b65)
);
FD #(
.INIT ( 1'b0 ))
blk0000095a (
.C(aclk),
.D(sig00000c06),
.Q(sig00000b64)
);
FD #(
.INIT ( 1'b0 ))
blk0000095b (
.C(aclk),
.D(sig00000c05),
.Q(sig00000b63)
);
FD #(
.INIT ( 1'b0 ))
blk0000095c (
.C(aclk),
.D(sig00000c04),
.Q(sig00000b62)
);
FD #(
.INIT ( 1'b0 ))
blk0000095d (
.C(aclk),
.D(sig00000c03),
.Q(sig00000b61)
);
FD #(
.INIT ( 1'b0 ))
blk0000095e (
.C(aclk),
.D(sig00000c02),
.Q(sig00000b60)
);
FD #(
.INIT ( 1'b0 ))
blk0000095f (
.C(aclk),
.D(sig00000c01),
.Q(sig00000b5f)
);
FD #(
.INIT ( 1'b0 ))
blk00000960 (
.C(aclk),
.D(sig00000c00),
.Q(sig00000b5e)
);
FD #(
.INIT ( 1'b0 ))
blk00000961 (
.C(aclk),
.D(sig00000bff),
.Q(sig00000b5d)
);
FD #(
.INIT ( 1'b0 ))
blk00000962 (
.C(aclk),
.D(sig00000bfe),
.Q(sig00000b5c)
);
FD #(
.INIT ( 1'b0 ))
blk00000963 (
.C(aclk),
.D(sig00000bfd),
.Q(sig00000b5b)
);
FD #(
.INIT ( 1'b0 ))
blk00000964 (
.C(aclk),
.D(sig00000bfc),
.Q(sig00000b5a)
);
FD #(
.INIT ( 1'b0 ))
blk00000965 (
.C(aclk),
.D(sig00000bfb),
.Q(sig00000b59)
);
FD #(
.INIT ( 1'b0 ))
blk00000966 (
.C(aclk),
.D(sig00000bfa),
.Q(sig00000b58)
);
FD #(
.INIT ( 1'b0 ))
blk00000967 (
.C(aclk),
.D(sig00000bf9),
.Q(sig00000b57)
);
FDE #(
.INIT ( 1'b0 ))
blk00000968 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b7a),
.Q(sig0000088b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000969 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b79),
.Q(sig0000088a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000096a (
.C(aclk),
.CE(sig00000344),
.D(sig00000b78),
.Q(sig00000889)
);
FDE #(
.INIT ( 1'b0 ))
blk0000096b (
.C(aclk),
.CE(sig00000344),
.D(sig00000b77),
.Q(sig00000888)
);
FDE #(
.INIT ( 1'b0 ))
blk0000096c (
.C(aclk),
.CE(sig00000344),
.D(sig00000b76),
.Q(sig00000887)
);
FDE #(
.INIT ( 1'b0 ))
blk0000096d (
.C(aclk),
.CE(sig00000344),
.D(sig00000b75),
.Q(sig00000886)
);
FDE #(
.INIT ( 1'b0 ))
blk0000096e (
.C(aclk),
.CE(sig00000344),
.D(sig00000b74),
.Q(sig00000885)
);
FDE #(
.INIT ( 1'b0 ))
blk0000096f (
.C(aclk),
.CE(sig00000344),
.D(sig00000b73),
.Q(sig00000884)
);
FDE #(
.INIT ( 1'b0 ))
blk00000970 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b72),
.Q(sig00000883)
);
FDE #(
.INIT ( 1'b0 ))
blk00000971 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b71),
.Q(sig00000882)
);
FDE #(
.INIT ( 1'b0 ))
blk00000972 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b70),
.Q(sig00000881)
);
FDE #(
.INIT ( 1'b0 ))
blk00000973 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b6f),
.Q(sig00000880)
);
FDE #(
.INIT ( 1'b0 ))
blk00000974 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b6e),
.Q(sig0000087f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000975 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b6d),
.Q(sig0000087e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000976 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b6c),
.Q(sig0000087d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000977 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b6b),
.Q(sig0000087c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000978 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b6a),
.Q(sig0000087b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000979 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b69),
.Q(sig0000087a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000097a (
.C(aclk),
.CE(sig00000344),
.D(sig00000b9e),
.Q(sig00000b8c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000097b (
.C(aclk),
.CE(sig00000344),
.D(sig00000b9d),
.Q(sig00000b8b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000097c (
.C(aclk),
.CE(sig00000344),
.D(sig00000b9c),
.Q(sig00000b8a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000097d (
.C(aclk),
.CE(sig00000344),
.D(sig00000b9b),
.Q(sig00000b89)
);
FDE #(
.INIT ( 1'b0 ))
blk0000097e (
.C(aclk),
.CE(sig00000344),
.D(sig00000b9a),
.Q(sig00000b88)
);
FDE #(
.INIT ( 1'b0 ))
blk0000097f (
.C(aclk),
.CE(sig00000344),
.D(sig00000b99),
.Q(sig00000b87)
);
FDE #(
.INIT ( 1'b0 ))
blk00000980 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b98),
.Q(sig00000b86)
);
FDE #(
.INIT ( 1'b0 ))
blk00000981 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b97),
.Q(sig00000b85)
);
FDE #(
.INIT ( 1'b0 ))
blk00000982 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b96),
.Q(sig00000b84)
);
FDE #(
.INIT ( 1'b0 ))
blk00000983 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b95),
.Q(sig00000b83)
);
FDE #(
.INIT ( 1'b0 ))
blk00000984 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b94),
.Q(sig00000b82)
);
FDE #(
.INIT ( 1'b0 ))
blk00000985 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b93),
.Q(sig00000b81)
);
FDE #(
.INIT ( 1'b0 ))
blk00000986 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b92),
.Q(sig00000b80)
);
FDE #(
.INIT ( 1'b0 ))
blk00000987 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b91),
.Q(sig00000b7f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000988 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b90),
.Q(sig00000b7e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000989 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b8f),
.Q(sig00000b7d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000098a (
.C(aclk),
.CE(sig00000344),
.D(sig00000b8e),
.Q(sig00000b7c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000098b (
.C(aclk),
.CE(sig00000344),
.D(sig00000b8d),
.Q(sig00000b7b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000098c (
.C(aclk),
.CE(sig00000344),
.D(sig00000b68),
.Q(sig00000be6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000098d (
.C(aclk),
.CE(sig00000344),
.D(sig00000b67),
.Q(sig00000be5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000098e (
.C(aclk),
.CE(sig00000344),
.D(sig00000b66),
.Q(sig00000be4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000098f (
.C(aclk),
.CE(sig00000344),
.D(sig00000b65),
.Q(sig00000be3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000990 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b64),
.Q(sig00000be2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000991 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b63),
.Q(sig00000be1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000992 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b62),
.Q(sig00000be0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000993 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b61),
.Q(sig00000bdf)
);
FDE #(
.INIT ( 1'b0 ))
blk00000994 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b60),
.Q(sig00000bde)
);
FDE #(
.INIT ( 1'b0 ))
blk00000995 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b5f),
.Q(sig00000bdd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000996 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b5e),
.Q(sig00000bdc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000997 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b5d),
.Q(sig00000bdb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000998 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b5c),
.Q(sig00000bda)
);
FDE #(
.INIT ( 1'b0 ))
blk00000999 (
.C(aclk),
.CE(sig00000344),
.D(sig00000b5b),
.Q(sig00000bd9)
);
FDE #(
.INIT ( 1'b0 ))
blk0000099a (
.C(aclk),
.CE(sig00000344),
.D(sig00000b5a),
.Q(sig00000bd8)
);
FDE #(
.INIT ( 1'b0 ))
blk0000099b (
.C(aclk),
.CE(sig00000344),
.D(sig00000b59),
.Q(sig00000bd7)
);
FDE #(
.INIT ( 1'b0 ))
blk0000099c (
.C(aclk),
.CE(sig00000344),
.D(sig00000b58),
.Q(sig00000bd6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000099d (
.C(aclk),
.CE(sig00000344),
.D(sig00000b57),
.Q(sig00000bd5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000099e (
.C(aclk),
.CE(sig00000344),
.D(sig00000bd4),
.Q(sig00000bf8)
);
FDE #(
.INIT ( 1'b0 ))
blk0000099f (
.C(aclk),
.CE(sig00000344),
.D(sig00000bd3),
.Q(sig00000bf7)
);
FDE #(
.INIT ( 1'b0 ))
blk000009a0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000bd2),
.Q(sig00000bf6)
);
FDE #(
.INIT ( 1'b0 ))
blk000009a1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000bd1),
.Q(sig00000bf5)
);
FDE #(
.INIT ( 1'b0 ))
blk000009a2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000bd0),
.Q(sig00000bf4)
);
FDE #(
.INIT ( 1'b0 ))
blk000009a3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000bcf),
.Q(sig00000bf3)
);
FDE #(
.INIT ( 1'b0 ))
blk000009a4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000bce),
.Q(sig00000bf2)
);
FDE #(
.INIT ( 1'b0 ))
blk000009a5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000bcd),
.Q(sig00000bf1)
);
FDE #(
.INIT ( 1'b0 ))
blk000009a6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000bcc),
.Q(sig00000bf0)
);
FDE #(
.INIT ( 1'b0 ))
blk000009a7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000bcb),
.Q(sig00000bef)
);
FDE #(
.INIT ( 1'b0 ))
blk000009a8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000bca),
.Q(sig00000bee)
);
FDE #(
.INIT ( 1'b0 ))
blk000009a9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000bc9),
.Q(sig00000bed)
);
FDE #(
.INIT ( 1'b0 ))
blk000009aa (
.C(aclk),
.CE(sig00000344),
.D(sig00000bc8),
.Q(sig00000bec)
);
FDE #(
.INIT ( 1'b0 ))
blk000009ab (
.C(aclk),
.CE(sig00000344),
.D(sig00000bc7),
.Q(sig00000beb)
);
FDE #(
.INIT ( 1'b0 ))
blk000009ac (
.C(aclk),
.CE(sig00000344),
.D(sig00000bc6),
.Q(sig00000bea)
);
FDE #(
.INIT ( 1'b0 ))
blk000009ad (
.C(aclk),
.CE(sig00000344),
.D(sig00000bc5),
.Q(sig00000be9)
);
FDE #(
.INIT ( 1'b0 ))
blk000009ae (
.C(aclk),
.CE(sig00000344),
.D(sig00000bc4),
.Q(sig00000be8)
);
FDE #(
.INIT ( 1'b0 ))
blk000009af (
.C(aclk),
.CE(sig00000344),
.D(sig00000bc3),
.Q(sig00000be7)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009b0 (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(sig0000087a),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c23)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009b1 (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(sig0000087a),
.I3(sig0000087b),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c24)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009b2 (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(sig0000087a),
.I2(sig0000087b),
.I3(sig0000087c),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c25)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009b3 (
.I0(sig0000087a),
.I1(sig0000087b),
.I2(sig0000087c),
.I3(sig0000087d),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c26)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009b4 (
.I0(sig0000087b),
.I1(sig0000087c),
.I2(sig0000087d),
.I3(sig0000087e),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c27)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009b5 (
.I0(sig0000087c),
.I1(sig0000087d),
.I2(sig0000087e),
.I3(sig0000087f),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c28)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009b6 (
.I0(sig0000087d),
.I1(sig0000087e),
.I2(sig0000087f),
.I3(sig00000880),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c29)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009b7 (
.I0(sig0000087e),
.I1(sig0000087f),
.I2(sig00000880),
.I3(sig00000881),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c2a)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009b8 (
.I0(sig0000087f),
.I1(sig00000880),
.I2(sig00000881),
.I3(sig00000882),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c2b)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009b9 (
.I0(sig00000880),
.I1(sig00000881),
.I2(sig00000882),
.I3(sig00000883),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c2c)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009ba (
.I0(sig00000881),
.I1(sig00000882),
.I2(sig00000883),
.I3(sig00000884),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c2d)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009bb (
.I0(sig00000882),
.I1(sig00000883),
.I2(sig00000884),
.I3(sig00000885),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c2e)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009bc (
.I0(sig00000883),
.I1(sig00000884),
.I2(sig00000885),
.I3(sig00000886),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c2f)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009bd (
.I0(sig00000884),
.I1(sig00000885),
.I2(sig00000886),
.I3(sig00000887),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c30)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009be (
.I0(sig00000885),
.I1(sig00000886),
.I2(sig00000887),
.I3(sig00000888),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c31)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009bf (
.I0(sig00000886),
.I1(sig00000887),
.I2(sig00000888),
.I3(sig00000889),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c32)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009c0 (
.I0(sig00000887),
.I1(sig00000888),
.I2(sig00000889),
.I3(sig0000088a),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c33)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009c1 (
.I0(sig00000888),
.I1(sig00000889),
.I2(sig0000088a),
.I3(sig0000088b),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c34)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009c2 (
.I0(sig00000889),
.I1(sig0000088a),
.I2(sig0000088b),
.I3(sig0000088b),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c35)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009c3 (
.I0(sig0000088a),
.I1(sig0000088b),
.I2(sig0000088b),
.I3(sig0000088b),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c36)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009c4 (
.I0(sig0000088b),
.I1(sig0000088b),
.I2(sig0000088b),
.I3(sig0000088b),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c37)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009c5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c23),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000009c5_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009c6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c24),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000009c6_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009c7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c25),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000009c7_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009c8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c26),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000008c)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009c9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c27),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000008d)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009ca (
.C(aclk),
.CE(sig00000344),
.D(sig00000c28),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000008e)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009cb (
.C(aclk),
.CE(sig00000344),
.D(sig00000c29),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000008f)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009cc (
.C(aclk),
.CE(sig00000344),
.D(sig00000c2a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000090)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009cd (
.C(aclk),
.CE(sig00000344),
.D(sig00000c2b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000091)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009ce (
.C(aclk),
.CE(sig00000344),
.D(sig00000c2c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000092)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009cf (
.C(aclk),
.CE(sig00000344),
.D(sig00000c2d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000093)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009d0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c2e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000094)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009d1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c2f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000095)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009d2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c30),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000096)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009d3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c31),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000097)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009d4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c32),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000098)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009d5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c33),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000099)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009d6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c34),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000009a)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009d7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c35),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000009b)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009d8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c36),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000009d8_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009d9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c37),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000009d9_Q_UNCONNECTED)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009da (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I3(sig00000868),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c38)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009db (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I2(sig00000868),
.I3(sig00000869),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c39)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009dc (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.I1(sig00000868),
.I2(sig00000869),
.I3(sig0000086a),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c3a)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009dd (
.I0(sig00000868),
.I1(sig00000869),
.I2(sig0000086a),
.I3(sig0000086b),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c3b)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009de (
.I0(sig00000869),
.I1(sig0000086a),
.I2(sig0000086b),
.I3(sig0000086c),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c3c)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009df (
.I0(sig0000086a),
.I1(sig0000086b),
.I2(sig0000086c),
.I3(sig0000086d),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c3d)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009e0 (
.I0(sig0000086b),
.I1(sig0000086c),
.I2(sig0000086d),
.I3(sig0000086e),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c3e)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009e1 (
.I0(sig0000086c),
.I1(sig0000086d),
.I2(sig0000086e),
.I3(sig0000086f),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c3f)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009e2 (
.I0(sig0000086d),
.I1(sig0000086e),
.I2(sig0000086f),
.I3(sig00000870),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c40)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009e3 (
.I0(sig0000086e),
.I1(sig0000086f),
.I2(sig00000870),
.I3(sig00000871),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c41)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009e4 (
.I0(sig0000086f),
.I1(sig00000870),
.I2(sig00000871),
.I3(sig00000872),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c42)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009e5 (
.I0(sig00000870),
.I1(sig00000871),
.I2(sig00000872),
.I3(sig00000873),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c43)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009e6 (
.I0(sig00000871),
.I1(sig00000872),
.I2(sig00000873),
.I3(sig00000874),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c44)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009e7 (
.I0(sig00000872),
.I1(sig00000873),
.I2(sig00000874),
.I3(sig00000875),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c45)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009e8 (
.I0(sig00000873),
.I1(sig00000874),
.I2(sig00000875),
.I3(sig00000876),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c46)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009e9 (
.I0(sig00000874),
.I1(sig00000875),
.I2(sig00000876),
.I3(sig00000877),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c47)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009ea (
.I0(sig00000875),
.I1(sig00000876),
.I2(sig00000877),
.I3(sig00000878),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c48)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009eb (
.I0(sig00000876),
.I1(sig00000877),
.I2(sig00000878),
.I3(sig00000879),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c49)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009ec (
.I0(sig00000877),
.I1(sig00000878),
.I2(sig00000879),
.I3(sig00000879),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c4a)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009ed (
.I0(sig00000878),
.I1(sig00000879),
.I2(sig00000879),
.I3(sig00000879),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c4b)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk000009ee (
.I0(sig00000879),
.I1(sig00000879),
.I2(sig00000879),
.I3(sig00000879),
.I4(sig0000088c),
.I5(sig0000088d),
.O(sig00000c4c)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009ef (
.C(aclk),
.CE(sig00000344),
.D(sig00000c38),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000009ef_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009f0 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c39),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000009f0_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009f1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c3a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk000009f1_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009f2 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c3b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000007c)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009f3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c3c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000007d)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009f4 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c3d),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000007e)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009f5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c3e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000007f)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009f6 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c3f),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000080)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009f7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c40),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000081)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009f8 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c41),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000082)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009f9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c42),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000083)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009fa (
.C(aclk),
.CE(sig00000344),
.D(sig00000c43),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000084)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009fb (
.C(aclk),
.CE(sig00000344),
.D(sig00000c44),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000085)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009fc (
.C(aclk),
.CE(sig00000344),
.D(sig00000c45),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000086)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009fd (
.C(aclk),
.CE(sig00000344),
.D(sig00000c46),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000087)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009fe (
.C(aclk),
.CE(sig00000344),
.D(sig00000c47),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000088)
);
FDRE #(
.INIT ( 1'b0 ))
blk000009ff (
.C(aclk),
.CE(sig00000344),
.D(sig00000c48),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig00000089)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000a00 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c49),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000008a)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000a01 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c4a),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(sig0000008b)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000a02 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c4b),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk00000a02_Q_UNCONNECTED)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000a03 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c4c),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk00000a03_Q_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a04 (
.C(aclk),
.CE(sig00000344),
.D(sig0000008b),
.Q(sig00000012)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a05 (
.C(aclk),
.CE(sig00000344),
.D(sig0000008a),
.Q(sig00000011)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a06 (
.C(aclk),
.CE(sig00000344),
.D(sig00000089),
.Q(sig00000010)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a07 (
.C(aclk),
.CE(sig00000344),
.D(sig00000088),
.Q(sig0000000f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a08 (
.C(aclk),
.CE(sig00000344),
.D(sig00000087),
.Q(sig0000000e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a09 (
.C(aclk),
.CE(sig00000344),
.D(sig00000086),
.Q(sig0000000d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a0a (
.C(aclk),
.CE(sig00000344),
.D(sig00000085),
.Q(sig0000000c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a0b (
.C(aclk),
.CE(sig00000344),
.D(sig00000084),
.Q(sig0000000b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a0c (
.C(aclk),
.CE(sig00000344),
.D(sig00000083),
.Q(sig0000000a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a0d (
.C(aclk),
.CE(sig00000344),
.D(sig00000082),
.Q(sig00000009)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a0e (
.C(aclk),
.CE(sig00000344),
.D(sig00000081),
.Q(sig00000008)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a0f (
.C(aclk),
.CE(sig00000344),
.D(sig00000080),
.Q(sig00000007)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a10 (
.C(aclk),
.CE(sig00000344),
.D(sig0000007f),
.Q(sig00000006)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a11 (
.C(aclk),
.CE(sig00000344),
.D(sig0000007e),
.Q(sig00000005)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a12 (
.C(aclk),
.CE(sig00000344),
.D(sig0000007d),
.Q(sig00000004)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a13 (
.C(aclk),
.CE(sig00000344),
.D(sig0000007c),
.Q(sig00000003)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a14 (
.C(aclk),
.CE(sig00000344),
.D(sig0000009b),
.Q(sig00000022)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a15 (
.C(aclk),
.CE(sig00000344),
.D(sig0000009a),
.Q(sig00000021)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a16 (
.C(aclk),
.CE(sig00000344),
.D(sig00000099),
.Q(sig00000020)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a17 (
.C(aclk),
.CE(sig00000344),
.D(sig00000098),
.Q(sig0000001f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a18 (
.C(aclk),
.CE(sig00000344),
.D(sig00000097),
.Q(sig0000001e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a19 (
.C(aclk),
.CE(sig00000344),
.D(sig00000096),
.Q(sig0000001d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a1a (
.C(aclk),
.CE(sig00000344),
.D(sig00000095),
.Q(sig0000001c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a1b (
.C(aclk),
.CE(sig00000344),
.D(sig00000094),
.Q(sig0000001b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a1c (
.C(aclk),
.CE(sig00000344),
.D(sig00000093),
.Q(sig0000001a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a1d (
.C(aclk),
.CE(sig00000344),
.D(sig00000092),
.Q(sig00000019)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a1e (
.C(aclk),
.CE(sig00000344),
.D(sig00000091),
.Q(sig00000018)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a1f (
.C(aclk),
.CE(sig00000344),
.D(sig00000090),
.Q(sig00000017)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a20 (
.C(aclk),
.CE(sig00000344),
.D(sig0000008f),
.Q(sig00000016)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a21 (
.C(aclk),
.CE(sig00000344),
.D(sig0000008e),
.Q(sig00000015)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a22 (
.C(aclk),
.CE(sig00000344),
.D(sig0000008d),
.Q(sig00000014)
);
FDE #(
.INIT ( 1'b0 ))
blk00000a23 (
.C(aclk),
.CE(sig00000344),
.D(sig0000008c),
.Q(sig00000013)
);
SRL16E #(
.INIT ( 16'h0000 ))
blk00000a24 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000000ca),
.Q(sig00000c4d)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000a25 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c4d),
.R(NLW_blk00000a25_R_UNCONNECTED),
.Q(sig00000c4e)
);
FDR #(
.INIT ( 1'b0 ))
blk00000a26 (
.C(aclk),
.D(sig00000c4e),
.R(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.Q(NLW_blk00000a26_Q_UNCONNECTED)
);
LUT4 #(
.INIT ( 16'hAAA9 ))
blk00000a27 (
.I0(sig00000064),
.I1(sig00000053),
.I2(sig00000062),
.I3(sig00000063),
.O(sig00000055)
);
LUT6 #(
.INIT ( 64'h5555555700000003 ))
blk00000a28 (
.I0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/dv_resolved_prev ),
.I1(sig00000064),
.I2(sig00000063),
.I3(sig00000062),
.I4(sig00000053),
.I5(sig00000001),
.O(sig0000005c)
);
LUT5 #(
.INIT ( 32'h88888000 ))
blk00000a29 (
.I0(sig00000067),
.I1(sig0000006a),
.I2(sig00000066),
.I3(sig00000052),
.I4(sig00000002),
.O(sig0000005f)
);
LUT4 #(
.INIT ( 16'hAA80 ))
blk00000a2a (
.I0(sig00000067),
.I1(sig00000066),
.I2(sig00000052),
.I3(sig00000002),
.O(sig00000059)
);
LUT3 #(
.INIT ( 8'hA9 ))
blk00000a2b (
.I0(sig00000063),
.I1(sig00000053),
.I2(sig00000062),
.O(sig00000056)
);
LUT5 #(
.INIT ( 32'h00000008 ))
blk00000a2c (
.I0(sig00000001),
.I1(sig00000053),
.I2(sig00000062),
.I3(sig00000063),
.I4(sig00000064),
.O(sig00000060)
);
LUT4 #(
.INIT ( 16'hF888 ))
blk00000a2d (
.I0(sig00000067),
.I1(sig00000002),
.I2(sig00000066),
.I3(sig00000052),
.O(sig0000005d)
);
LUT4 #(
.INIT ( 16'h7FFF ))
blk00000a2e (
.I0(sig00000029),
.I1(sig0000002a),
.I2(sig00000027),
.I3(sig00000028),
.O(sig00000052)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a2f (
.I0(sig00000062),
.I1(sig00000053),
.O(sig00000057)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a30 (
.I0(sig00000069),
.I1(sig0000002c),
.O(sig0000005e)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a31 (
.I0(sig00000002),
.I1(sig0000006f),
.O(sig00000061)
);
LUT2 #(
.INIT ( 4'hB ))
blk00000a32 (
.I0(sig00000065),
.I1(sig0000006d),
.O(s_axis_config_tready)
);
LUT2 #(
.INIT ( 4'hB ))
blk00000a33 (
.I0(sig00000002),
.I1(sig0000006f),
.O(s_axis_data_tready)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a34 (
.I0(sig000000c8),
.I1(sig00000072),
.O(sig00000137)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a35 (
.I0(sig000000c7),
.I1(sig00000072),
.O(sig00000135)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a36 (
.I0(sig000000c6),
.I1(sig00000072),
.O(sig00000134)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a37 (
.I0(sig000000c5),
.I1(sig00000072),
.O(sig00000136)
);
LUT3 #(
.INIT ( 8'hB0 ))
blk00000a38 (
.I0(sig00000121),
.I1(sig00000002),
.I2(sig0000002d),
.O(sig0000011d)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a39 (
.I0(sig00000027),
.I1(sig00000121),
.O(sig0000012c)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a3a (
.I0(sig00000028),
.I1(sig00000121),
.O(sig0000012a)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a3b (
.I0(sig00000029),
.I1(sig00000121),
.O(sig00000129)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a3c (
.I0(sig0000002a),
.I1(sig00000121),
.O(sig0000012b)
);
LUT3 #(
.INIT ( 8'hF2 ))
blk00000a3d (
.I0(sig00000002),
.I1(sig00000121),
.I2(sig0000002d),
.O(sig0000011c)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a3e (
.I0(sig00000205),
.I1(sig00000150),
.O(sig00000144)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a3f (
.I0(sig00000206),
.I1(sig00000150),
.O(sig00000146)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a40 (
.I0(sig00000207),
.I1(sig00000150),
.O(sig00000147)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a41 (
.I0(sig00000208),
.I1(sig00000150),
.O(sig00000145)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000a42 (
.I0(sig000000c2),
.I1(sig000000c9),
.I2(sig000001e1),
.O(sig00000161)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a43 (
.I0(sig0000020a),
.I1(sig00000229),
.O(sig00000212)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a44 (
.I0(sig0000020b),
.I1(sig00000229),
.O(sig00000214)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a45 (
.I0(sig0000020c),
.I1(sig00000229),
.O(sig00000215)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a46 (
.I0(sig0000020d),
.I1(sig00000229),
.O(sig00000213)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a47 (
.I0(sig000002b0),
.I1(sig000002d3),
.O(sig00000333)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a48 (
.I0(sig000002ba),
.I1(sig000002dd),
.O(sig00000329)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a49 (
.I0(sig000002bb),
.I1(sig000002de),
.O(sig00000328)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a4a (
.I0(sig000002bc),
.I1(sig000002df),
.O(sig00000327)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a4b (
.I0(sig000002bd),
.I1(sig000002e0),
.O(sig00000326)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a4c (
.I0(sig000002be),
.I1(sig000002e1),
.O(sig00000325)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a4d (
.I0(sig000002bf),
.I1(sig000002e2),
.O(sig00000324)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a4e (
.I0(sig000002b1),
.I1(sig000002d4),
.O(sig00000332)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a4f (
.I0(sig000002b2),
.I1(sig000002d5),
.O(sig00000331)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a50 (
.I0(sig000002b3),
.I1(sig000002d6),
.O(sig00000330)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a51 (
.I0(sig000002b4),
.I1(sig000002d7),
.O(sig0000032f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a52 (
.I0(sig000002b5),
.I1(sig000002d8),
.O(sig0000032e)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a53 (
.I0(sig000002b6),
.I1(sig000002d9),
.O(sig0000032d)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a54 (
.I0(sig000002b7),
.I1(sig000002da),
.O(sig0000032c)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a55 (
.I0(sig000002b8),
.I1(sig000002db),
.O(sig0000032b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a56 (
.I0(sig000002b9),
.I1(sig000002dc),
.O(sig0000032a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a57 (
.I0(sig000002b0),
.I1(sig000002d3),
.O(sig00000365)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a58 (
.I0(sig000002ba),
.I1(sig000002dd),
.O(sig0000035b)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a59 (
.I0(sig000002bb),
.I1(sig000002de),
.O(sig0000035a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a5a (
.I0(sig000002bc),
.I1(sig000002df),
.O(sig00000359)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a5b (
.I0(sig000002bd),
.I1(sig000002e0),
.O(sig00000358)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a5c (
.I0(sig000002be),
.I1(sig000002e1),
.O(sig00000357)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a5d (
.I0(sig000002bf),
.I1(sig000002e2),
.O(sig00000356)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a5e (
.I0(sig000002b1),
.I1(sig000002d4),
.O(sig00000364)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a5f (
.I0(sig000002b2),
.I1(sig000002d5),
.O(sig00000363)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a60 (
.I0(sig000002b3),
.I1(sig000002d6),
.O(sig00000362)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a61 (
.I0(sig000002b4),
.I1(sig000002d7),
.O(sig00000361)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a62 (
.I0(sig000002b5),
.I1(sig000002d8),
.O(sig00000360)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a63 (
.I0(sig000002b6),
.I1(sig000002d9),
.O(sig0000035f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a64 (
.I0(sig000002b7),
.I1(sig000002da),
.O(sig0000035e)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a65 (
.I0(sig000002b8),
.I1(sig000002db),
.O(sig0000035d)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a66 (
.I0(sig000002b9),
.I1(sig000002dc),
.O(sig0000035c)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a67 (
.I0(sig000001e2),
.I1(sig000001f3),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003e8)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a68 (
.I0(sig000001e3),
.I1(sig000001f4),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003e9)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a69 (
.I0(sig000001e4),
.I1(sig000001f5),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003ea)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a6a (
.I0(sig000001e6),
.I1(sig000001f7),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003ec)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a6b (
.I0(sig000001e7),
.I1(sig000001f8),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003ed)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a6c (
.I0(sig000001e5),
.I1(sig000001f6),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003eb)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a6d (
.I0(sig000001e8),
.I1(sig000001f9),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003ee)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a6e (
.I0(sig000001e9),
.I1(sig000001fa),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003ef)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a6f (
.I0(sig000001ea),
.I1(sig000001fb),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003f0)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a70 (
.I0(sig000001eb),
.I1(sig000001fc),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003f1)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a71 (
.I0(sig000001ed),
.I1(sig000001fe),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003f3)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a72 (
.I0(sig000001ee),
.I1(sig000001ff),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003f4)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a73 (
.I0(sig000001ec),
.I1(sig000001fd),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003f2)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a74 (
.I0(sig000001ef),
.I1(sig00000200),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003f5)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a75 (
.I0(sig000001f0),
.I1(sig00000201),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003f6)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000a76 (
.I0(sig000001f1),
.I1(sig00000202),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig000003f7)
);
LUT4 #(
.INIT ( 16'h7D28 ))
blk00000a77 (
.I0(sig0000052d),
.I1(sig00000203),
.I2(sig00000532),
.I3(sig000001f2),
.O(sig000003f8)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a78 (
.I0(sig000001f3),
.I1(sig000001e2),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig0000041e)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a79 (
.I0(sig000001f4),
.I1(sig000001e3),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig0000041f)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a7a (
.I0(sig000001f5),
.I1(sig000001e4),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig00000420)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a7b (
.I0(sig000001f6),
.I1(sig000001e5),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig00000421)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a7c (
.I0(sig000001f7),
.I1(sig000001e6),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig00000422)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a7d (
.I0(sig000001f9),
.I1(sig000001e8),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig00000424)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a7e (
.I0(sig000001fa),
.I1(sig000001e9),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig00000425)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a7f (
.I0(sig000001f8),
.I1(sig000001e7),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig00000423)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a80 (
.I0(sig000001fb),
.I1(sig000001ea),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig00000426)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a81 (
.I0(sig000001fc),
.I1(sig000001eb),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig00000427)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a82 (
.I0(sig000001fd),
.I1(sig000001ec),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig00000428)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a83 (
.I0(sig000001fe),
.I1(sig000001ed),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig00000429)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a84 (
.I0(sig00000200),
.I1(sig000001ef),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig0000042b)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a85 (
.I0(sig00000201),
.I1(sig000001f0),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig0000042c)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a86 (
.I0(sig000001ff),
.I1(sig000001ee),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig0000042a)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000a87 (
.I0(sig00000202),
.I1(sig000001f1),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig0000042d)
);
LUT4 #(
.INIT ( 16'hD782 ))
blk00000a88 (
.I0(sig0000052d),
.I1(sig000001f2),
.I2(sig00000532),
.I3(sig00000203),
.O(sig0000042e)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000a89 (
.I0(sig0000052d),
.I1(sig00000532),
.O(sig000003f9)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000a8a (
.I0(sig0000052d),
.I1(sig00000532),
.O(sig0000042f)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000a8b (
.I0(sig000001d9),
.I1(sig000001d8),
.O(sig00000454)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a8c (
.I0(sig000004f7),
.I1(sig000004c1),
.O(sig0000059e)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a8d (
.I0(sig00000501),
.I1(sig000004cb),
.O(sig00000593)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a8e (
.I0(sig00000502),
.I1(sig000004cc),
.O(sig00000592)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a8f (
.I0(sig00000503),
.I1(sig000004cd),
.O(sig00000591)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a90 (
.I0(sig00000504),
.I1(sig000004ce),
.O(sig00000590)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a91 (
.I0(sig00000505),
.I1(sig000004cf),
.O(sig0000058f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a92 (
.I0(sig00000506),
.I1(sig000004d0),
.O(sig0000058e)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a93 (
.I0(sig00000507),
.I1(sig000004d1),
.O(sig0000058d)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a94 (
.I0(sig00000508),
.I1(sig000004d2),
.O(sig0000059d)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a95 (
.I0(sig000004f8),
.I1(sig000004c2),
.O(sig0000059c)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a96 (
.I0(sig000004f9),
.I1(sig000004c3),
.O(sig0000059b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a97 (
.I0(sig000004fa),
.I1(sig000004c4),
.O(sig0000059a)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a98 (
.I0(sig000004fb),
.I1(sig000004c5),
.O(sig00000599)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a99 (
.I0(sig000004fc),
.I1(sig000004c6),
.O(sig00000598)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a9a (
.I0(sig000004fd),
.I1(sig000004c7),
.O(sig00000597)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a9b (
.I0(sig000004fe),
.I1(sig000004c8),
.O(sig00000596)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a9c (
.I0(sig000004ff),
.I1(sig000004c9),
.O(sig00000595)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000a9d (
.I0(sig00000500),
.I1(sig000004ca),
.O(sig00000594)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a9e (
.I0(sig000004f7),
.I1(sig000004c1),
.O(sig000005d3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000a9f (
.I0(sig00000501),
.I1(sig000004cb),
.O(sig000005c8)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aa0 (
.I0(sig00000502),
.I1(sig000004cc),
.O(sig000005c7)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aa1 (
.I0(sig00000503),
.I1(sig000004cd),
.O(sig000005c6)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aa2 (
.I0(sig00000504),
.I1(sig000004ce),
.O(sig000005c5)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aa3 (
.I0(sig00000505),
.I1(sig000004cf),
.O(sig000005c4)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aa4 (
.I0(sig00000506),
.I1(sig000004d0),
.O(sig000005c3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aa5 (
.I0(sig00000507),
.I1(sig000004d1),
.O(sig000005c2)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aa6 (
.I0(sig00000508),
.I1(sig000004d2),
.O(sig000005d2)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aa7 (
.I0(sig000004f8),
.I1(sig000004c2),
.O(sig000005d1)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aa8 (
.I0(sig000004f9),
.I1(sig000004c3),
.O(sig000005d0)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aa9 (
.I0(sig000004fa),
.I1(sig000004c4),
.O(sig000005cf)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aaa (
.I0(sig000004fb),
.I1(sig000004c5),
.O(sig000005ce)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aab (
.I0(sig000004fc),
.I1(sig000004c6),
.O(sig000005cd)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aac (
.I0(sig000004fd),
.I1(sig000004c7),
.O(sig000005cc)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aad (
.I0(sig000004fe),
.I1(sig000004c8),
.O(sig000005cb)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aae (
.I0(sig000004ff),
.I1(sig000004c9),
.O(sig000005ca)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aaf (
.I0(sig00000500),
.I1(sig000004ca),
.O(sig000005c9)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ab0 (
.I0(sig000001b2),
.I1(sig000001b3),
.O(sig000005f7)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000ab1 (
.I0(sig0000009d),
.I1(sig0000009c),
.I2(sig0000088f),
.O(sig00000867)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ab2 (
.I0(sig000009aa),
.I1(sig000009cd),
.O(sig000008d1)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ab3 (
.I0(sig000009a9),
.I1(sig000009cc),
.O(sig000008d0)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ab4 (
.I0(sig000009a8),
.I1(sig000009cb),
.O(sig000008cf)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ab5 (
.I0(sig000009a7),
.I1(sig000009ca),
.O(sig000008ce)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ab6 (
.I0(sig000009a6),
.I1(sig000009c9),
.O(sig000008cd)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ab7 (
.I0(sig000009a5),
.I1(sig000009c8),
.O(sig000008cc)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ab8 (
.I0(sig000009a4),
.I1(sig000009c7),
.O(sig000008cb)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ab9 (
.I0(sig000009a3),
.I1(sig000009c6),
.O(sig000008ca)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000aba (
.I0(sig000009a2),
.I1(sig000009c5),
.O(sig000008c9)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000abb (
.I0(sig000009b0),
.I1(sig000009d3),
.O(sig000008c8)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000abc (
.I0(sig000009b0),
.I1(sig000009d3),
.O(sig000008d7)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000abd (
.I0(sig000009af),
.I1(sig000009d2),
.O(sig000008d6)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000abe (
.I0(sig000009ae),
.I1(sig000009d1),
.O(sig000008d5)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000abf (
.I0(sig000009ad),
.I1(sig000009d0),
.O(sig000008d4)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ac0 (
.I0(sig000009ac),
.I1(sig000009cf),
.O(sig000008d3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ac1 (
.I0(sig000009ab),
.I1(sig000009ce),
.O(sig000008d2)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ac2 (
.I0(sig000009a1),
.I1(sig000009c4),
.O(sig000008c7)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ac3 (
.I0(sig000009aa),
.I1(sig000009cd),
.O(sig00000903)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ac4 (
.I0(sig000009a9),
.I1(sig000009cc),
.O(sig00000902)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ac5 (
.I0(sig000009a8),
.I1(sig000009cb),
.O(sig00000901)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ac6 (
.I0(sig000009a7),
.I1(sig000009ca),
.O(sig00000900)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ac7 (
.I0(sig000009a6),
.I1(sig000009c9),
.O(sig000008ff)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ac8 (
.I0(sig000009a5),
.I1(sig000009c8),
.O(sig000008fe)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ac9 (
.I0(sig000009a4),
.I1(sig000009c7),
.O(sig000008fd)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000aca (
.I0(sig000009a3),
.I1(sig000009c6),
.O(sig000008fc)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000acb (
.I0(sig000009a2),
.I1(sig000009c5),
.O(sig000008fb)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000acc (
.I0(sig000009b0),
.I1(sig000009d3),
.O(sig000008fa)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000acd (
.I0(sig000009b0),
.I1(sig000009d3),
.O(sig00000909)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ace (
.I0(sig000009af),
.I1(sig000009d2),
.O(sig00000908)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000acf (
.I0(sig000009ae),
.I1(sig000009d1),
.O(sig00000907)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ad0 (
.I0(sig000009ad),
.I1(sig000009d0),
.O(sig00000906)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ad1 (
.I0(sig000009ac),
.I1(sig000009cf),
.O(sig00000905)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ad2 (
.I0(sig000009ab),
.I1(sig000009ce),
.O(sig00000904)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ad3 (
.I0(sig000009a1),
.I1(sig000009c4),
.O(sig000008f9)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ad4 (
.I0(sig00000bf0),
.I1(sig00000bba),
.O(sig00000a41)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ad5 (
.I0(sig00000bef),
.I1(sig00000bb9),
.O(sig00000a40)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ad6 (
.I0(sig00000bee),
.I1(sig00000bb8),
.O(sig00000a3f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ad7 (
.I0(sig00000bed),
.I1(sig00000bb7),
.O(sig00000a3e)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ad8 (
.I0(sig00000bec),
.I1(sig00000bb6),
.O(sig00000a3d)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ad9 (
.I0(sig00000beb),
.I1(sig00000bb5),
.O(sig00000a3c)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ada (
.I0(sig00000bea),
.I1(sig00000bb4),
.O(sig00000a3b)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000adb (
.I0(sig00000be9),
.I1(sig00000bb3),
.O(sig00000a3a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000adc (
.I0(sig00000be8),
.I1(sig00000bb2),
.O(sig00000a39)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000add (
.I0(sig00000bf8),
.I1(sig00000bc2),
.O(sig00000a38)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ade (
.I0(sig00000bf7),
.I1(sig00000bc1),
.O(sig00000a48)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000adf (
.I0(sig00000bf6),
.I1(sig00000bc0),
.O(sig00000a47)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ae0 (
.I0(sig00000bf5),
.I1(sig00000bbf),
.O(sig00000a46)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ae1 (
.I0(sig00000bf4),
.I1(sig00000bbe),
.O(sig00000a45)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ae2 (
.I0(sig00000bf3),
.I1(sig00000bbd),
.O(sig00000a44)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ae3 (
.I0(sig00000bf2),
.I1(sig00000bbc),
.O(sig00000a43)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ae4 (
.I0(sig00000bf1),
.I1(sig00000bbb),
.O(sig00000a42)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000ae5 (
.I0(sig00000be7),
.I1(sig00000bb1),
.O(sig00000a37)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ae6 (
.I0(sig00000bf0),
.I1(sig00000bba),
.O(sig00000a76)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ae7 (
.I0(sig00000bef),
.I1(sig00000bb9),
.O(sig00000a75)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ae8 (
.I0(sig00000bee),
.I1(sig00000bb8),
.O(sig00000a74)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000ae9 (
.I0(sig00000bed),
.I1(sig00000bb7),
.O(sig00000a73)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000aea (
.I0(sig00000bec),
.I1(sig00000bb6),
.O(sig00000a72)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000aeb (
.I0(sig00000beb),
.I1(sig00000bb5),
.O(sig00000a71)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000aec (
.I0(sig00000bea),
.I1(sig00000bb4),
.O(sig00000a70)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000aed (
.I0(sig00000be9),
.I1(sig00000bb3),
.O(sig00000a6f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000aee (
.I0(sig00000be8),
.I1(sig00000bb2),
.O(sig00000a6e)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000aef (
.I0(sig00000bf8),
.I1(sig00000bc2),
.O(sig00000a6d)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000af0 (
.I0(sig00000bf7),
.I1(sig00000bc1),
.O(sig00000a7d)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000af1 (
.I0(sig00000bf6),
.I1(sig00000bc0),
.O(sig00000a7c)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000af2 (
.I0(sig00000bf5),
.I1(sig00000bbf),
.O(sig00000a7b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000af3 (
.I0(sig00000bf4),
.I1(sig00000bbe),
.O(sig00000a7a)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000af4 (
.I0(sig00000bf3),
.I1(sig00000bbd),
.O(sig00000a79)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000af5 (
.I0(sig00000bf2),
.I1(sig00000bbc),
.O(sig00000a78)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000af6 (
.I0(sig00000bf1),
.I1(sig00000bbb),
.O(sig00000a77)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000af7 (
.I0(sig00000be7),
.I1(sig00000bb1),
.O(sig00000a6c)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000af8 (
.I0(sig00000895),
.I1(sig000008a6),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000ad8)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000af9 (
.I0(sig00000896),
.I1(sig000008a7),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000ad9)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000afa (
.I0(sig00000897),
.I1(sig000008a8),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000ada)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000afb (
.I0(sig00000899),
.I1(sig000008aa),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000adc)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000afc (
.I0(sig0000089a),
.I1(sig000008ab),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000add)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000afd (
.I0(sig00000898),
.I1(sig000008a9),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000adb)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000afe (
.I0(sig0000089b),
.I1(sig000008ac),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000ade)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000aff (
.I0(sig0000089c),
.I1(sig000008ad),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000adf)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000b00 (
.I0(sig0000089d),
.I1(sig000008ae),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000ae0)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000b01 (
.I0(sig0000089e),
.I1(sig000008af),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000ae1)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000b02 (
.I0(sig000008a0),
.I1(sig000008b1),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000ae3)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000b03 (
.I0(sig000008a1),
.I1(sig000008b2),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000ae4)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000b04 (
.I0(sig0000089f),
.I1(sig000008b0),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000ae2)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000b05 (
.I0(sig000008a2),
.I1(sig000008b3),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000ae5)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000b06 (
.I0(sig000008a3),
.I1(sig000008b4),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000ae6)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000b07 (
.I0(sig000008a4),
.I1(sig000008b5),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000ae7)
);
LUT4 #(
.INIT ( 16'h7D28 ))
blk00000b08 (
.I0(sig00000c1d),
.I1(sig000008b6),
.I2(sig00000c22),
.I3(sig000008a5),
.O(sig00000ae8)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b09 (
.I0(sig000008a6),
.I1(sig00000895),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b0e)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b0a (
.I0(sig000008a7),
.I1(sig00000896),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b0f)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b0b (
.I0(sig000008a8),
.I1(sig00000897),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b10)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b0c (
.I0(sig000008a9),
.I1(sig00000898),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b11)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b0d (
.I0(sig000008ab),
.I1(sig0000089a),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b13)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b0e (
.I0(sig000008ac),
.I1(sig0000089b),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b14)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b0f (
.I0(sig000008aa),
.I1(sig00000899),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b12)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b10 (
.I0(sig000008ad),
.I1(sig0000089c),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b15)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b11 (
.I0(sig000008ae),
.I1(sig0000089d),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b16)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b12 (
.I0(sig000008af),
.I1(sig0000089e),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b17)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b13 (
.I0(sig000008b0),
.I1(sig0000089f),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b18)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b14 (
.I0(sig000008b2),
.I1(sig000008a1),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b1a)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b15 (
.I0(sig000008b3),
.I1(sig000008a2),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b1b)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b16 (
.I0(sig000008b1),
.I1(sig000008a0),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b19)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b17 (
.I0(sig000008b4),
.I1(sig000008a3),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b1c)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b18 (
.I0(sig000008b5),
.I1(sig000008a4),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000b1d)
);
LUT4 #(
.INIT ( 16'hD782 ))
blk00000b19 (
.I0(sig00000c1d),
.I1(sig000008a5),
.I2(sig00000c22),
.I3(sig000008b6),
.O(sig00000b1e)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000b1a (
.I0(sig00000c1d),
.I1(sig00000c22),
.O(sig00000ae9)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b1b (
.I0(sig00000c1d),
.I1(sig00000c22),
.O(sig00000b1f)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000b1c (
.I0(sig00000894),
.I1(sig00000893),
.O(sig00000b44)
);
FDSE #(
.INIT ( 1'b0 ))
blk00000b1d (
.C(aclk),
.CE(sig00000001),
.D(sig00000055),
.S(sig0000005c),
.Q(sig00000064)
);
FDSE #(
.INIT ( 1'b0 ))
blk00000b1e (
.C(aclk),
.CE(sig00000001),
.D(sig00000056),
.S(sig0000005c),
.Q(sig00000063)
);
FDSE #(
.INIT ( 1'b0 ))
blk00000b1f (
.C(aclk),
.CE(sig00000001),
.D(sig00000057),
.S(sig0000005c),
.Q(sig00000062)
);
FDSE #(
.INIT ( 1'b0 ))
blk00000b20 (
.C(aclk),
.CE(sig00000001),
.D(sig00000058),
.S(sig0000005c),
.Q(sig00000053)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b21 (
.I0(sig00000029),
.I1(sig00000121),
.O(sig00000c4f)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b22 (
.I0(sig00000028),
.I1(sig00000121),
.O(sig00000c50)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b23 (
.I0(sig00000027),
.I1(sig00000121),
.O(sig00000c51)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b24 (
.I0(sig000000c6),
.I1(sig00000072),
.O(sig00000c52)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b25 (
.I0(sig000000c7),
.I1(sig00000072),
.O(sig00000c53)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b26 (
.I0(sig000000c8),
.I1(sig00000072),
.O(sig00000c54)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b27 (
.I0(sig00000205),
.I1(sig00000150),
.O(sig00000c55)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b28 (
.I0(sig00000206),
.I1(sig00000150),
.O(sig00000c56)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b29 (
.I0(sig00000207),
.I1(sig00000150),
.O(sig00000c57)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000b2a (
.I0(sig00000151),
.O(sig00000c58)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b2b (
.I0(sig0000020a),
.I1(sig00000229),
.O(sig00000c59)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b2c (
.I0(sig0000020b),
.I1(sig00000229),
.O(sig00000c5a)
);
LUT2 #(
.INIT ( 4'h2 ))
blk00000b2d (
.I0(sig0000020c),
.I1(sig00000229),
.O(sig00000c5b)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000b2e (
.I0(sig00000228),
.O(sig00000c5c)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000b2f (
.I0(sig000002bf),
.I1(sig000002e2),
.O(sig00000c5d)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000b30 (
.I0(sig000002bf),
.I1(sig000002e2),
.O(sig00000c5e)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000b31 (
.I0(sig000001f2),
.I1(sig00000203),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig00000c5f)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b32 (
.I0(sig00000203),
.I1(sig000001f2),
.I2(sig00000532),
.I3(sig0000052d),
.O(sig00000c60)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000b33 (
.I0(sig000001b3),
.O(sig00000c61)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000b34 (
.I0(sig000001b2),
.O(sig00000c62)
);
LUT4 #(
.INIT ( 16'h3CAA ))
blk00000b35 (
.I0(sig000008a5),
.I1(sig000008b6),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000c63)
);
LUT4 #(
.INIT ( 16'hC3AA ))
blk00000b36 (
.I0(sig000008b6),
.I1(sig000008a5),
.I2(sig00000c22),
.I3(sig00000c1d),
.O(sig00000c64)
);
FD #(
.INIT ( 1'b0 ))
blk00000b37 (
.C(aclk),
.D(sig00000c65),
.Q(sig0000006d)
);
FD #(
.INIT ( 1'b0 ))
blk00000b38 (
.C(aclk),
.D(sig00000c66),
.Q(sig0000006f)
);
LUT3 #(
.INIT ( 8'hA2 ))
blk00000b39 (
.I0(s_axis_config_tvalid),
.I1(sig0000006d),
.I2(sig00000065),
.O(sig0000006c)
);
LUT3 #(
.INIT ( 8'hA2 ))
blk00000b3a (
.I0(s_axis_data_tvalid),
.I1(sig0000006f),
.I2(sig00000002),
.O(sig0000006e)
);
LUT3 #(
.INIT ( 8'h60 ))
blk00000b3b (
.I0(sig000005e7),
.I1(sig000005e8),
.I2(sig00000806),
.O(sig000007f6)
);
LUT3 #(
.INIT ( 8'h60 ))
blk00000b3c (
.I0(sig000005e6),
.I1(sig000005e8),
.I2(sig00000826),
.O(sig00000816)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b3d (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig000001a0),
.I3(sig00000805),
.O(sig000007f5)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b3e (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig000001ae),
.I3(sig00000825),
.O(sig00000815)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b3f (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig00000193),
.I3(sig00000804),
.O(sig000007f4)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b40 (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig00000199),
.I3(sig00000824),
.O(sig00000814)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b41 (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig00000198),
.I3(sig00000803),
.O(sig000007f3)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b42 (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig00000198),
.I3(sig00000823),
.O(sig00000813)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b43 (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig0000019d),
.I3(sig00000802),
.O(sig000007f2)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b44 (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig0000019d),
.I3(sig00000822),
.O(sig00000812)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b45 (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig0000019c),
.I3(sig00000801),
.O(sig000007f1)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b46 (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig0000019c),
.I3(sig00000821),
.O(sig00000811)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b47 (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig0000019b),
.I3(sig00000800),
.O(sig000007f0)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b48 (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig00000194),
.I3(sig00000820),
.O(sig00000810)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b49 (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig00000193),
.I3(sig000007ff),
.O(sig000007ef)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b4a (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig00000199),
.I3(sig0000081f),
.O(sig0000080f)
);
LUT3 #(
.INIT ( 8'h60 ))
blk00000b4b (
.I0(sig000005e7),
.I1(sig000005e8),
.I2(sig000007fe),
.O(sig000007ee)
);
LUT3 #(
.INIT ( 8'h60 ))
blk00000b4c (
.I0(sig000005e6),
.I1(sig000005e8),
.I2(sig0000081e),
.O(sig0000080e)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b4d (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig00000199),
.I3(sig000007fd),
.O(sig000007ed)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b4e (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig00000193),
.I3(sig0000081d),
.O(sig0000080d)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b4f (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig00000198),
.I3(sig000007fc),
.O(sig000007ec)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b50 (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig00000198),
.I3(sig0000081c),
.O(sig0000080c)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b51 (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig00000194),
.I3(sig000007fb),
.O(sig000007eb)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b52 (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig0000019b),
.I3(sig0000081b),
.O(sig0000080b)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b53 (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig00000194),
.I3(sig000007fa),
.O(sig000007ea)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b54 (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig0000019b),
.I3(sig0000081a),
.O(sig0000080a)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b55 (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig00000194),
.I3(sig000007f9),
.O(sig000007e9)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b56 (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig0000019b),
.I3(sig00000819),
.O(sig00000809)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b57 (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig00000194),
.I3(sig000007f8),
.O(sig000007e8)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b58 (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig0000019b),
.I3(sig00000818),
.O(sig00000808)
);
LUT3 #(
.INIT ( 8'hF2 ))
blk00000b59 (
.I0(sig0000006d),
.I1(sig00000065),
.I2(s_axis_config_tvalid),
.O(sig00000c65)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b5a (
.I0(sig000005e8),
.I1(sig000005e7),
.I2(sig00000193),
.I3(sig000007f7),
.O(sig000007e7)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000b5b (
.I0(sig000005e8),
.I1(sig000005e6),
.I2(sig00000199),
.I3(sig00000817),
.O(sig00000807)
);
LUT3 #(
.INIT ( 8'hF2 ))
blk00000b5c (
.I0(sig0000006f),
.I1(sig00000002),
.I2(s_axis_data_tvalid),
.O(sig00000c66)
);
LUT5 #(
.INIT ( 32'h00800000 ))
blk00000b5d (
.I0(sig00000027),
.I1(sig00000029),
.I2(sig0000002a),
.I3(sig0000006b),
.I4(sig00000028),
.O(sig0000005b)
);
LUT6 #(
.INIT ( 64'h0888888888888888 ))
blk00000b5e (
.I0(sig00000002),
.I1(sig0000006b),
.I2(sig00000029),
.I3(sig0000002a),
.I4(sig00000027),
.I5(sig00000028),
.O(sig00000054)
);
LUT6 #(
.INIT ( 64'h2222222222F22222 ))
blk00000b5f (
.I0(sig00000068),
.I1(sig0000006f),
.I2(sig00000066),
.I3(sig00000052),
.I4(sig00000002),
.I5(s_axis_data_tvalid),
.O(sig0000005a)
);
MUXF7 blk00000b60 (
.I0(sig00000c67),
.I1(sig00000c68),
.S(sig00000052),
.O(sig0000002d)
);
LUT6 #(
.INIT ( 64'hFFFFDC54DC54DC54 ))
blk00000b61 (
.I0(sig00000002),
.I1(sig00000066),
.I2(sig00000067),
.I3(s_axis_data_tvalid),
.I4(sig0000006f),
.I5(sig00000068),
.O(sig00000c67)
);
LUT4 #(
.INIT ( 16'h8F88 ))
blk00000b62 (
.I0(sig00000068),
.I1(sig0000006f),
.I2(sig00000002),
.I3(sig00000067),
.O(sig00000c68)
);
INV blk00000b63 (
.I(sig000001a0),
.O(sig000007ae)
);
INV blk00000b64 (
.I(sig00000193),
.O(sig000007b0)
);
INV blk00000b65 (
.I(sig00000198),
.O(sig000007b2)
);
INV blk00000b66 (
.I(sig0000019d),
.O(sig000007b4)
);
INV blk00000b67 (
.I(sig0000019c),
.O(sig000007b6)
);
INV blk00000b68 (
.I(sig0000019b),
.O(sig000007b8)
);
INV blk00000b69 (
.I(sig00000193),
.O(sig000007ba)
);
INV blk00000b6a (
.I(sig00000199),
.O(sig000007bd)
);
INV blk00000b6b (
.I(sig00000198),
.O(sig000007bf)
);
INV blk00000b6c (
.I(sig00000194),
.O(sig000007c1)
);
INV blk00000b6d (
.I(sig00000194),
.O(sig000007c3)
);
INV blk00000b6e (
.I(sig00000194),
.O(sig000007c5)
);
INV blk00000b6f (
.I(sig00000194),
.O(sig000007c7)
);
INV blk00000b70 (
.I(sig00000193),
.O(sig000007c9)
);
INV blk00000b71 (
.I(sig000001ae),
.O(sig000007cb)
);
INV blk00000b72 (
.I(sig00000199),
.O(sig000007cd)
);
INV blk00000b73 (
.I(sig00000198),
.O(sig000007cf)
);
INV blk00000b74 (
.I(sig0000019d),
.O(sig000007d1)
);
INV blk00000b75 (
.I(sig0000019c),
.O(sig000007d3)
);
INV blk00000b76 (
.I(sig00000194),
.O(sig000007d5)
);
INV blk00000b77 (
.I(sig00000199),
.O(sig000007d7)
);
INV blk00000b78 (
.I(sig00000193),
.O(sig000007da)
);
INV blk00000b79 (
.I(sig00000198),
.O(sig000007dc)
);
INV blk00000b7a (
.I(sig0000019b),
.O(sig000007de)
);
INV blk00000b7b (
.I(sig0000019b),
.O(sig000007e0)
);
INV blk00000b7c (
.I(sig0000019b),
.O(sig000007e2)
);
INV blk00000b7d (
.I(sig0000019b),
.O(sig000007e4)
);
INV blk00000b7e (
.I(sig00000199),
.O(sig000007e6)
);
INV blk00000b7f (
.I(sig00000053),
.O(sig00000058)
);
INV blk00000b80 (
.I(sig00000072),
.O(sig00000075)
);
INV blk00000b81 (
.I(sig00000121),
.O(sig00000119)
);
INV blk00000b82 (
.I(sig00000150),
.O(sig00000157)
);
INV blk00000b83 (
.I(sig00000229),
.O(sig00000222)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b84 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000076a),
.Q(sig00000c69),
.Q15(NLW_blk00000b84_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b85 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c69),
.Q(sig0000074a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b86 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000001af),
.Q(sig00000c6a),
.Q15(NLW_blk00000b86_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b87 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c6a),
.Q(sig000005e5)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b88 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000769),
.Q(sig00000c6b),
.Q15(NLW_blk00000b88_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b89 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c6b),
.Q(sig00000749)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b8a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000076b),
.Q(sig00000c6c),
.Q15(NLW_blk00000b8a_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b8b (
.C(aclk),
.CE(sig00000344),
.D(sig00000c6c),
.Q(sig0000074b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b8c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000076c),
.Q(sig00000c6d),
.Q15(NLW_blk00000b8c_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b8d (
.C(aclk),
.CE(sig00000344),
.D(sig00000c6d),
.Q(sig0000074c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b8e (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000076d),
.Q(sig00000c6e),
.Q15(NLW_blk00000b8e_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b8f (
.C(aclk),
.CE(sig00000344),
.D(sig00000c6e),
.Q(sig0000074d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b90 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000076e),
.Q(sig00000c6f),
.Q15(NLW_blk00000b90_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b91 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c6f),
.Q(sig0000074e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b92 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000076f),
.Q(sig00000c70),
.Q15(NLW_blk00000b92_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b93 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c70),
.Q(sig0000074f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b94 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000770),
.Q(sig00000c71),
.Q15(NLW_blk00000b94_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b95 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c71),
.Q(sig00000750)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b96 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000773),
.Q(sig00000c72),
.Q15(NLW_blk00000b96_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b97 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c72),
.Q(sig00000753)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b98 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000771),
.Q(sig00000c73),
.Q15(NLW_blk00000b98_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b99 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c73),
.Q(sig00000751)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b9a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000772),
.Q(sig00000c74),
.Q15(NLW_blk00000b9a_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b9b (
.C(aclk),
.CE(sig00000344),
.D(sig00000c74),
.Q(sig00000752)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b9c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000774),
.Q(sig00000c75),
.Q15(NLW_blk00000b9c_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b9d (
.C(aclk),
.CE(sig00000344),
.D(sig00000c75),
.Q(sig00000754)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000b9e (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000775),
.Q(sig00000c76),
.Q15(NLW_blk00000b9e_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000b9f (
.C(aclk),
.CE(sig00000344),
.D(sig00000c76),
.Q(sig00000755)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000ba0 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000776),
.Q(sig00000c77),
.Q15(NLW_blk00000ba0_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000ba1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c77),
.Q(sig00000756)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000ba2 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000777),
.Q(sig00000c78),
.Q15(NLW_blk00000ba2_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000ba3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c78),
.Q(sig00000757)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000ba4 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000778),
.Q(sig00000c79),
.Q15(NLW_blk00000ba4_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000ba5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c79),
.Q(sig00000758)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000ba6 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000680),
.Q(sig00000c7a),
.Q15(NLW_blk00000ba6_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000ba7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c7a),
.Q(sig00000643)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000ba8 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000068a),
.Q(sig00000c7b),
.Q15(NLW_blk00000ba8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000ba9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c7b),
.Q(sig00000646)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000baa (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000688),
.Q(sig00000c7c),
.Q15(NLW_blk00000baa_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bab (
.C(aclk),
.CE(sig00000344),
.D(sig00000c7c),
.Q(sig00000644)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bac (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000689),
.Q(sig00000c7d),
.Q15(NLW_blk00000bac_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bad (
.C(aclk),
.CE(sig00000344),
.D(sig00000c7d),
.Q(sig00000645)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bae (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000068b),
.Q(sig00000c7e),
.Q15(NLW_blk00000bae_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000baf (
.C(aclk),
.CE(sig00000344),
.D(sig00000c7e),
.Q(sig00000647)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bb0 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000068c),
.Q(sig00000c7f),
.Q15(NLW_blk00000bb0_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bb1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c7f),
.Q(sig00000648)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bb2 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000068d),
.Q(sig00000c80),
.Q15(NLW_blk00000bb2_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bb3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c80),
.Q(sig00000649)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bb4 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000068e),
.Q(sig00000c81),
.Q15(NLW_blk00000bb4_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bb5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c81),
.Q(sig0000064a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bb6 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000068f),
.Q(sig00000c82),
.Q15(NLW_blk00000bb6_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bb7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c82),
.Q(sig0000064b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bb8 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000690),
.Q(sig00000c83),
.Q15(NLW_blk00000bb8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bb9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c83),
.Q(sig0000064c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bba (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000691),
.Q(sig00000c84),
.Q15(NLW_blk00000bba_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bbb (
.C(aclk),
.CE(sig00000344),
.D(sig00000c84),
.Q(sig0000064d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bbc (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000692),
.Q(sig00000c85),
.Q15(NLW_blk00000bbc_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bbd (
.C(aclk),
.CE(sig00000344),
.D(sig00000c85),
.Q(sig0000064e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bbe (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000693),
.Q(sig00000c86),
.Q15(NLW_blk00000bbe_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bbf (
.C(aclk),
.CE(sig00000344),
.D(sig00000c86),
.Q(sig0000064f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bc0 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000694),
.Q(sig00000c87),
.Q15(NLW_blk00000bc0_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bc1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c87),
.Q(sig00000650)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bc2 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000695),
.Q(sig00000c88),
.Q15(NLW_blk00000bc2_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bc3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c88),
.Q(sig00000651)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bc4 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000696),
.Q(sig00000c89),
.Q15(NLW_blk00000bc4_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bc5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c89),
.Q(sig00000652)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bc6 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000697),
.Q(sig00000c8a),
.Q15(NLW_blk00000bc6_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bc7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c8a),
.Q(sig00000653)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bc8 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000698),
.Q(sig00000c8b),
.Q15(NLW_blk00000bc8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bc9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c8b),
.Q(sig00000654)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bca (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000069c),
.Q(sig00000c8c),
.Q15(NLW_blk00000bca_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bcb (
.C(aclk),
.CE(sig00000344),
.D(sig00000c8c),
.Q(sig00000634)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bcc (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000699),
.Q(sig00000c8d),
.Q15(NLW_blk00000bcc_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bcd (
.C(aclk),
.CE(sig00000344),
.D(sig00000c8d),
.Q(sig0000062a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bce (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000069b),
.Q(sig00000c8e),
.Q15(NLW_blk00000bce_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bcf (
.C(aclk),
.CE(sig00000344),
.D(sig00000c8e),
.Q(sig00000633)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bd0 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000069d),
.Q(sig00000c8f),
.Q15(NLW_blk00000bd0_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bd1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c8f),
.Q(sig00000635)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bd2 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000069e),
.Q(sig00000c90),
.Q15(NLW_blk00000bd2_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bd3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c90),
.Q(sig00000636)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bd4 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000069f),
.Q(sig00000c91),
.Q15(NLW_blk00000bd4_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bd5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c91),
.Q(sig00000637)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bd6 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000006a0),
.Q(sig00000c92),
.Q15(NLW_blk00000bd6_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bd7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c92),
.Q(sig00000638)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bd8 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000006a1),
.Q(sig00000c93),
.Q15(NLW_blk00000bd8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bd9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c93),
.Q(sig00000639)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bda (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000006a2),
.Q(sig00000c94),
.Q15(NLW_blk00000bda_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bdb (
.C(aclk),
.CE(sig00000344),
.D(sig00000c94),
.Q(sig0000063a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bdc (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000006a3),
.Q(sig00000c95),
.Q15(NLW_blk00000bdc_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bdd (
.C(aclk),
.CE(sig00000344),
.D(sig00000c95),
.Q(sig0000063b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bde (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000006a4),
.Q(sig00000c96),
.Q15(NLW_blk00000bde_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bdf (
.C(aclk),
.CE(sig00000344),
.D(sig00000c96),
.Q(sig0000063c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000be0 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000006a5),
.Q(sig00000c97),
.Q15(NLW_blk00000be0_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000be1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c97),
.Q(sig0000063d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000be2 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000006a6),
.Q(sig00000c98),
.Q15(NLW_blk00000be2_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000be3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c98),
.Q(sig0000063e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000be4 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000006a7),
.Q(sig00000c99),
.Q15(NLW_blk00000be4_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000be5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c99),
.Q(sig0000063f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000be6 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000006a8),
.Q(sig00000c9a),
.Q15(NLW_blk00000be6_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000be7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c9a),
.Q(sig00000640)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000be8 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig000006a9),
.Q(sig00000c9b),
.Q15(NLW_blk00000be8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000be9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c9b),
.Q(sig00000641)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bea (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000079a),
.Q(sig00000c9c),
.Q15(NLW_blk00000bea_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000beb (
.C(aclk),
.CE(sig00000344),
.D(sig00000c9c),
.Q(sig000006ef)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bec (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000797),
.Q(sig00000c9d),
.Q15(NLW_blk00000bec_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bed (
.C(aclk),
.CE(sig00000344),
.D(sig00000c9d),
.Q(sig000006f2)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bee (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000799),
.Q(sig00000c9e),
.Q15(NLW_blk00000bee_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bef (
.C(aclk),
.CE(sig00000344),
.D(sig00000c9e),
.Q(sig000006f0)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bf0 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000798),
.Q(sig00000c9f),
.Q15(NLW_blk00000bf0_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bf1 (
.C(aclk),
.CE(sig00000344),
.D(sig00000c9f),
.Q(sig000006f1)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bf2 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000796),
.Q(sig00000ca0),
.Q15(NLW_blk00000bf2_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bf3 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ca0),
.Q(sig000006f3)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bf4 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000795),
.Q(sig00000ca1),
.Q15(NLW_blk00000bf4_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bf5 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ca1),
.Q(sig000006f4)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bf6 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000794),
.Q(sig00000ca2),
.Q15(NLW_blk00000bf6_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bf7 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ca2),
.Q(sig000006f5)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bf8 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000793),
.Q(sig00000ca3),
.Q15(NLW_blk00000bf8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bf9 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ca3),
.Q(sig000006f6)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bfa (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000792),
.Q(sig00000ca4),
.Q15(NLW_blk00000bfa_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bfb (
.C(aclk),
.CE(sig00000344),
.D(sig00000ca4),
.Q(sig000006f7)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bfc (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000791),
.Q(sig00000ca5),
.Q15(NLW_blk00000bfc_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bfd (
.C(aclk),
.CE(sig00000344),
.D(sig00000ca5),
.Q(sig000006f8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000bfe (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000790),
.Q(sig00000ca6),
.Q15(NLW_blk00000bfe_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000bff (
.C(aclk),
.CE(sig00000344),
.D(sig00000ca6),
.Q(sig000006f9)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000c00 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000078f),
.Q(sig00000ca7),
.Q15(NLW_blk00000c00_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000c01 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ca7),
.Q(sig000006fa)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000c02 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000078e),
.Q(sig00000ca8),
.Q15(NLW_blk00000c02_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000c03 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ca8),
.Q(sig000006fb)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000c04 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000078d),
.Q(sig00000ca9),
.Q15(NLW_blk00000c04_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000c05 (
.C(aclk),
.CE(sig00000344),
.D(sig00000ca9),
.Q(sig000006fc)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000c06 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000078c),
.Q(sig00000caa),
.Q15(NLW_blk00000c06_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000c07 (
.C(aclk),
.CE(sig00000344),
.D(sig00000caa),
.Q(sig000006fd)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000c08 (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000078b),
.Q(sig00000cab),
.Q15(NLW_blk00000c08_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000c09 (
.C(aclk),
.CE(sig00000344),
.D(sig00000cab),
.Q(sig000006fe)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000c0a (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000078a),
.Q(sig00000cac),
.Q15(NLW_blk00000c0a_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000c0b (
.C(aclk),
.CE(sig00000344),
.D(sig00000cac),
.Q(sig000006ff)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000c0c (
.A0(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A1(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A2(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.A3(\NlwRenamedSig_OI_U0/i_synth/axi_wrapper/blk_event_tlast_unexpected.events_to_transfer [1]),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000789),
.Q(sig00000cad),
.Q15(NLW_blk00000c0c_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000c0d (
.C(aclk),
.CE(sig00000344),
.D(sig00000cad),
.Q(sig00000700)
);
FDE #(
.INIT ( 1'b0 ))
\blk000000dc/blk000000e0 (
.C(aclk),
.CE(sig00000344),
.D(\blk000000dc/sig00000cb4 ),
.Q(sig00000120)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk000000dc/blk000000df (
.A0(\blk000000dc/sig00000cb3 ),
.A1(\blk000000dc/sig00000cb2 ),
.A2(\blk000000dc/sig00000cb2 ),
.A3(\blk000000dc/sig00000cb2 ),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000011f),
.Q(\blk000000dc/sig00000cb4 ),
.Q15(\NLW_blk000000dc/blk000000df_Q15_UNCONNECTED )
);
VCC \blk000000dc/blk000000de (
.P(\blk000000dc/sig00000cb3 )
);
GND \blk000000dc/blk000000dd (
.G(\blk000000dc/sig00000cb2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk000001f6/blk000001fa (
.C(aclk),
.CE(\blk000001f6/sig00000cb9 ),
.D(\blk000001f6/sig00000cba ),
.Q(sig000002c0)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk000001f6/blk000001f9 (
.A0(\blk000001f6/sig00000cb8 ),
.A1(\blk000001f6/sig00000cb9 ),
.A2(\blk000001f6/sig00000cb9 ),
.A3(\blk000001f6/sig00000cb8 ),
.CE(\blk000001f6/sig00000cb9 ),
.CLK(aclk),
.D(sig000002c1),
.Q(\blk000001f6/sig00000cba ),
.Q15(\NLW_blk000001f6/blk000001f9_Q15_UNCONNECTED )
);
VCC \blk000001f6/blk000001f8 (
.P(\blk000001f6/sig00000cb9 )
);
GND \blk000001f6/blk000001f7 (
.G(\blk000001f6/sig00000cb8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk000002a3/blk000002a9 (
.C(aclk),
.CE(\blk000002a3/sig00000cc1 ),
.D(\blk000002a3/sig00000cc3 ),
.Q(sig000000c1)
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk000002a3/blk000002a8 (
.CLK(aclk),
.D(sig00000206),
.CE(\blk000002a3/sig00000cc1 ),
.Q(\blk000002a3/sig00000cc3 ),
.Q31(\NLW_blk000002a3/blk000002a8_Q31_UNCONNECTED ),
.A({\blk000002a3/sig00000cc1 , \blk000002a3/sig00000cc1 , \blk000002a3/sig00000cc0 , \blk000002a3/sig00000cc1 , \blk000002a3/sig00000cc0 })
);
FDE #(
.INIT ( 1'b0 ))
\blk000002a3/blk000002a7 (
.C(aclk),
.CE(\blk000002a3/sig00000cc1 ),
.D(\blk000002a3/sig00000cc2 ),
.Q(sig000000c0)
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk000002a3/blk000002a6 (
.CLK(aclk),
.D(sig00000205),
.CE(\blk000002a3/sig00000cc1 ),
.Q(\blk000002a3/sig00000cc2 ),
.Q31(\NLW_blk000002a3/blk000002a6_Q31_UNCONNECTED ),
.A({\blk000002a3/sig00000cc1 , \blk000002a3/sig00000cc1 , \blk000002a3/sig00000cc0 , \blk000002a3/sig00000cc1 , \blk000002a3/sig00000cc0 })
);
VCC \blk000002a3/blk000002a5 (
.P(\blk000002a3/sig00000cc1 )
);
GND \blk000002a3/blk000002a4 (
.G(\blk000002a3/sig00000cc0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk000002aa/blk000002ae (
.C(aclk),
.CE(\blk000002aa/sig00000cc8 ),
.D(\blk000002aa/sig00000cc9 ),
.Q(sig0000014f)
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk000002aa/blk000002ad (
.CLK(aclk),
.D(sig00000204),
.CE(\blk000002aa/sig00000cc8 ),
.Q(\blk000002aa/sig00000cc9 ),
.Q31(\NLW_blk000002aa/blk000002ad_Q31_UNCONNECTED ),
.A({\blk000002aa/sig00000cc8 , \blk000002aa/sig00000cc8 , \blk000002aa/sig00000cc7 , \blk000002aa/sig00000cc7 , \blk000002aa/sig00000cc8 })
);
VCC \blk000002aa/blk000002ac (
.P(\blk000002aa/sig00000cc8 )
);
GND \blk000002aa/blk000002ab (
.G(\blk000002aa/sig00000cc7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk000002af/blk000002b3 (
.C(aclk),
.CE(\blk000002af/sig00000cce ),
.D(\blk000002af/sig00000ccf ),
.Q(sig000001e0)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk000002af/blk000002b2 (
.A0(\blk000002af/sig00000cce ),
.A1(\blk000002af/sig00000ccd ),
.A2(\blk000002af/sig00000ccd ),
.A3(\blk000002af/sig00000cce ),
.CE(\blk000002af/sig00000cce ),
.CLK(aclk),
.D(sig000001e1),
.Q(\blk000002af/sig00000ccf ),
.Q15(\NLW_blk000002af/blk000002b2_Q15_UNCONNECTED )
);
VCC \blk000002af/blk000002b1 (
.P(\blk000002af/sig00000cce )
);
GND \blk000002af/blk000002b0 (
.G(\blk000002af/sig00000ccd )
);
FDE #(
.INIT ( 1'b0 ))
\blk000002b4/blk000002b8 (
.C(aclk),
.CE(\blk000002b4/sig00000cd4 ),
.D(\blk000002b4/sig00000cd5 ),
.Q(sig0000009c)
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk000002b4/blk000002b7 (
.CLK(aclk),
.D(sig00000162),
.CE(\blk000002b4/sig00000cd4 ),
.Q(\blk000002b4/sig00000cd5 ),
.Q31(\NLW_blk000002b4/blk000002b7_Q31_UNCONNECTED ),
.A({\blk000002b4/sig00000cd4 , \blk000002b4/sig00000cd4 , \blk000002b4/sig00000cd3 , \blk000002b4/sig00000cd4 , \blk000002b4/sig00000cd3 })
);
VCC \blk000002b4/blk000002b6 (
.P(\blk000002b4/sig00000cd4 )
);
GND \blk000002b4/blk000002b5 (
.G(\blk000002b4/sig00000cd3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk000002b9/blk000002bf (
.C(aclk),
.CE(\blk000002b9/sig00000cdc ),
.D(\blk000002b9/sig00000cde ),
.Q(sig000001db)
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk000002b9/blk000002be (
.CLK(aclk),
.D(sig000001dd),
.CE(\blk000002b9/sig00000cdc ),
.Q(\blk000002b9/sig00000cde ),
.Q31(\NLW_blk000002b9/blk000002be_Q31_UNCONNECTED ),
.A({\blk000002b9/sig00000cdc , \blk000002b9/sig00000cdc , \blk000002b9/sig00000cdb , \blk000002b9/sig00000cdb , \blk000002b9/sig00000cdc })
);
FDE #(
.INIT ( 1'b0 ))
\blk000002b9/blk000002bd (
.C(aclk),
.CE(\blk000002b9/sig00000cdc ),
.D(\blk000002b9/sig00000cdd ),
.Q(sig000001da)
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk000002b9/blk000002bc (
.CLK(aclk),
.D(sig000001dc),
.CE(\blk000002b9/sig00000cdc ),
.Q(\blk000002b9/sig00000cdd ),
.Q31(\NLW_blk000002b9/blk000002bc_Q31_UNCONNECTED ),
.A({\blk000002b9/sig00000cdc , \blk000002b9/sig00000cdc , \blk000002b9/sig00000cdb , \blk000002b9/sig00000cdb , \blk000002b9/sig00000cdc })
);
VCC \blk000002b9/blk000002bb (
.P(\blk000002b9/sig00000cdc )
);
GND \blk000002b9/blk000002ba (
.G(\blk000002b9/sig00000cdb )
);
FDE #(
.INIT ( 1'b0 ))
\blk000002c0/blk000002c6 (
.C(aclk),
.CE(\blk000002c0/sig00000ce5 ),
.D(\blk000002c0/sig00000ce7 ),
.Q(sig000000bf)
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk000002c0/blk000002c5 (
.CLK(aclk),
.D(sig000001df),
.CE(\blk000002c0/sig00000ce5 ),
.Q(\blk000002c0/sig00000ce7 ),
.Q31(\NLW_blk000002c0/blk000002c5_Q31_UNCONNECTED ),
.A({\blk000002c0/sig00000ce5 , \blk000002c0/sig00000ce5 , \blk000002c0/sig00000ce4 , \blk000002c0/sig00000ce5 , \blk000002c0/sig00000ce4 })
);
FDE #(
.INIT ( 1'b0 ))
\blk000002c0/blk000002c4 (
.C(aclk),
.CE(\blk000002c0/sig00000ce5 ),
.D(\blk000002c0/sig00000ce6 ),
.Q(sig000000be)
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk000002c0/blk000002c3 (
.CLK(aclk),
.D(sig000001de),
.CE(\blk000002c0/sig00000ce5 ),
.Q(\blk000002c0/sig00000ce6 ),
.Q31(\NLW_blk000002c0/blk000002c3_Q31_UNCONNECTED ),
.A({\blk000002c0/sig00000ce5 , \blk000002c0/sig00000ce5 , \blk000002c0/sig00000ce4 , \blk000002c0/sig00000ce5 , \blk000002c0/sig00000ce4 })
);
VCC \blk000002c0/blk000002c2 (
.P(\blk000002c0/sig00000ce5 )
);
GND \blk000002c0/blk000002c1 (
.G(\blk000002c0/sig00000ce4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk000003fc/blk000003ff (
.C(aclk),
.CE(sig00000344),
.D(\blk000003fc/sig00000ced ),
.Q(sig0000052f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk000003fc/blk000003fe (
.A0(\blk000003fc/sig00000cec ),
.A1(\blk000003fc/sig00000cec ),
.A2(\blk000003fc/sig00000cec ),
.A3(\blk000003fc/sig00000cec ),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000530),
.Q(\blk000003fc/sig00000ced ),
.Q15(\NLW_blk000003fc/blk000003fe_Q15_UNCONNECTED )
);
GND \blk000003fc/blk000003fd (
.G(\blk000003fc/sig00000cec )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000400/blk00000403 (
.C(aclk),
.CE(sig00000344),
.D(\blk00000400/sig00000cf3 ),
.Q(sig00000530)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000400/blk00000402 (
.A0(\blk00000400/sig00000cf2 ),
.A1(\blk00000400/sig00000cf2 ),
.A2(\blk00000400/sig00000cf2 ),
.A3(\blk00000400/sig00000cf2 ),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000531),
.Q(\blk00000400/sig00000cf3 ),
.Q15(\NLW_blk00000400/blk00000402_Q15_UNCONNECTED )
);
GND \blk00000400/blk00000401 (
.G(\blk00000400/sig00000cf2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000404/blk00000408 (
.C(aclk),
.CE(\blk00000404/sig00000cf8 ),
.D(\blk00000404/sig00000cf9 ),
.Q(sig0000052e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000404/blk00000407 (
.A0(\blk00000404/sig00000cf7 ),
.A1(\blk00000404/sig00000cf8 ),
.A2(\blk00000404/sig00000cf7 ),
.A3(\blk00000404/sig00000cf7 ),
.CE(\blk00000404/sig00000cf8 ),
.CLK(aclk),
.D(sig0000052f),
.Q(\blk00000404/sig00000cf9 ),
.Q15(\NLW_blk00000404/blk00000407_Q15_UNCONNECTED )
);
VCC \blk00000404/blk00000406 (
.P(\blk00000404/sig00000cf8 )
);
GND \blk00000404/blk00000405 (
.G(\blk00000404/sig00000cf7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000503/blk00000507 (
.C(aclk),
.CE(\blk00000503/sig00000cfe ),
.D(\blk00000503/sig00000cff ),
.Q(sig000001af)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000503/blk00000506 (
.A0(\blk00000503/sig00000cfd ),
.A1(\blk00000503/sig00000cfe ),
.A2(\blk00000503/sig00000cfe ),
.A3(\blk00000503/sig00000cfe ),
.CE(\blk00000503/sig00000cfe ),
.CLK(aclk),
.D(sig00000162),
.Q(\blk00000503/sig00000cff ),
.Q15(\NLW_blk00000503/blk00000506_Q15_UNCONNECTED )
);
VCC \blk00000503/blk00000505 (
.P(\blk00000503/sig00000cfe )
);
GND \blk00000503/blk00000504 (
.G(\blk00000503/sig00000cfd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000508/blk0000050b (
.C(aclk),
.CE(sig00000344),
.D(\blk00000508/sig00000d05 ),
.Q(sig000005e8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000508/blk0000050a (
.A0(\blk00000508/sig00000d04 ),
.A1(\blk00000508/sig00000d04 ),
.A2(\blk00000508/sig00000d04 ),
.A3(\blk00000508/sig00000d04 ),
.CE(sig00000344),
.CLK(aclk),
.D(sig000005e9),
.Q(\blk00000508/sig00000d05 ),
.Q15(\NLW_blk00000508/blk0000050a_Q15_UNCONNECTED )
);
GND \blk00000508/blk00000509 (
.G(\blk00000508/sig00000d04 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000522/blk00000545 (
.C(aclk),
.CE(\blk00000522/sig00000d2b ),
.D(\blk00000522/sig00000d2d ),
.Q(sig00000198)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000522/blk00000544 (
.A0(\blk00000522/sig00000d2a ),
.A1(\blk00000522/sig00000d2a ),
.A2(\blk00000522/sig00000d2a ),
.A3(\blk00000522/sig00000d2a ),
.CE(\blk00000522/sig00000d2b ),
.CLK(aclk),
.D(sig000005ea),
.Q(\blk00000522/sig00000d2d ),
.Q15(\NLW_blk00000522/blk00000544_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000522/blk00000543 (
.C(aclk),
.CE(\blk00000522/sig00000d2b ),
.D(\blk00000522/sig00000d2c ),
.Q(sig000005e7)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000522/blk00000542 (
.A0(\blk00000522/sig00000d2a ),
.A1(\blk00000522/sig00000d2a ),
.A2(\blk00000522/sig00000d2a ),
.A3(\blk00000522/sig00000d2a ),
.CE(\blk00000522/sig00000d2b ),
.CLK(aclk),
.D(sig000005e5),
.Q(\blk00000522/sig00000d2c ),
.Q15(\NLW_blk00000522/blk00000542_Q15_UNCONNECTED )
);
VCC \blk00000522/blk00000541 (
.P(\blk00000522/sig00000d2b )
);
GND \blk00000522/blk00000540 (
.G(\blk00000522/sig00000d2a )
);
LUT3 #(
.INIT ( 8'hD8 ))
\blk00000522/blk0000053f (
.I0(\blk00000522/sig00000d0a ),
.I1(\blk00000522/sig00000d19 ),
.I2(\blk00000522/sig00000d1b ),
.O(\blk00000522/sig00000d1e )
);
LUT2 #(
.INIT ( 4'h2 ))
\blk00000522/blk0000053e (
.I0(\blk00000522/sig00000d09 ),
.I1(\blk00000522/sig00000d0a ),
.O(\blk00000522/sig00000d1d )
);
LUT3 #(
.INIT ( 8'hD8 ))
\blk00000522/blk0000053d (
.I0(\blk00000522/sig00000d0a ),
.I1(\blk00000522/sig00000d1b ),
.I2(\blk00000522/sig00000d19 ),
.O(\blk00000522/sig00000d21 )
);
LUT3 #(
.INIT ( 8'hD8 ))
\blk00000522/blk0000053c (
.I0(\blk00000522/sig00000d0a ),
.I1(\blk00000522/sig00000d1a ),
.I2(\blk00000522/sig00000d16 ),
.O(\blk00000522/sig00000d20 )
);
LUT3 #(
.INIT ( 8'hD8 ))
\blk00000522/blk0000053b (
.I0(\blk00000522/sig00000d0a ),
.I1(\blk00000522/sig00000d16 ),
.I2(\blk00000522/sig00000d1a ),
.O(\blk00000522/sig00000d1f )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000522/blk0000053a (
.I0(\blk00000522/sig00000d0a ),
.I1(\blk00000522/sig00000d09 ),
.O(\blk00000522/sig00000d1c )
);
LUT2 #(
.INIT ( 4'h1 ))
\blk00000522/blk00000539 (
.I0(sig000005ea),
.I1(sig000005eb),
.O(\blk00000522/sig00000d29 )
);
LUT2 #(
.INIT ( 4'hE ))
\blk00000522/blk00000538 (
.I0(sig000005eb),
.I1(sig000005ea),
.O(\blk00000522/sig00000d27 )
);
LUT2 #(
.INIT ( 4'h2 ))
\blk00000522/blk00000537 (
.I0(sig000005eb),
.I1(sig000005ea),
.O(\blk00000522/sig00000d26 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000522/blk00000536 (
.I0(sig000005ea),
.I1(sig000005eb),
.O(\blk00000522/sig00000d25 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000522/blk00000535 (
.I0(sig000005ea),
.I1(sig000005eb),
.O(\blk00000522/sig00000d24 )
);
LUT2 #(
.INIT ( 4'h2 ))
\blk00000522/blk00000534 (
.I0(sig000005ea),
.I1(sig000005eb),
.O(\blk00000522/sig00000d23 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk00000533 (
.C(aclk),
.D(\blk00000522/sig00000d1d ),
.Q(sig000001ae)
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk00000532 (
.C(aclk),
.D(\blk00000522/sig00000d1c ),
.Q(sig000001a0)
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk00000531 (
.C(aclk),
.D(\blk00000522/sig00000d17 ),
.Q(sig0000019d)
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk00000530 (
.C(aclk),
.D(\blk00000522/sig00000d18 ),
.Q(sig0000019c)
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk0000052f (
.C(aclk),
.D(\blk00000522/sig00000d21 ),
.Q(sig0000019b)
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk0000052e (
.C(aclk),
.D(\blk00000522/sig00000d1f ),
.Q(sig00000199)
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk0000052d (
.C(aclk),
.D(\blk00000522/sig00000d1e ),
.Q(sig00000194)
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk0000052c (
.C(aclk),
.D(\blk00000522/sig00000d20 ),
.Q(sig00000193)
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk0000052b (
.C(aclk),
.D(\blk00000522/sig00000d0a ),
.Q(sig000005e6)
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk0000052a (
.C(aclk),
.D(\blk00000522/sig00000d29 ),
.Q(\blk00000522/sig00000d09 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk00000529 (
.C(aclk),
.D(\blk00000522/sig00000d27 ),
.Q(\blk00000522/sig00000d17 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk00000528 (
.C(aclk),
.D(\blk00000522/sig00000d26 ),
.Q(\blk00000522/sig00000d18 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk00000527 (
.C(aclk),
.D(\blk00000522/sig00000d23 ),
.Q(\blk00000522/sig00000d1b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk00000526 (
.C(aclk),
.D(sig000005eb),
.Q(\blk00000522/sig00000d16 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk00000525 (
.C(aclk),
.D(\blk00000522/sig00000d25 ),
.Q(\blk00000522/sig00000d19 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk00000524 (
.C(aclk),
.D(\blk00000522/sig00000d24 ),
.Q(\blk00000522/sig00000d1a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000522/blk00000523 (
.C(aclk),
.D(sig000005ec),
.Q(\blk00000522/sig00000d0a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000640/blk00000644 (
.C(aclk),
.CE(sig00000344),
.D(\blk00000640/sig00000e36 ),
.Q(sig00000890)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000640/blk00000643 (
.A0(\blk00000640/sig00000e35 ),
.A1(\blk00000640/sig00000e34 ),
.A2(\blk00000640/sig00000e34 ),
.A3(\blk00000640/sig00000e34 ),
.CE(sig00000344),
.CLK(aclk),
.D(sig0000009d),
.Q(\blk00000640/sig00000e36 ),
.Q15(\NLW_blk00000640/blk00000643_Q15_UNCONNECTED )
);
VCC \blk00000640/blk00000642 (
.P(\blk00000640/sig00000e35 )
);
GND \blk00000640/blk00000641 (
.G(\blk00000640/sig00000e34 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000659/blk0000065c (
.C(aclk),
.CE(sig00000344),
.D(\blk00000659/sig00000e3c ),
.Q(sig000009b1)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000659/blk0000065b (
.A0(\blk00000659/sig00000e3b ),
.A1(\blk00000659/sig00000e3b ),
.A2(\blk00000659/sig00000e3b ),
.A3(\blk00000659/sig00000e3b ),
.CE(sig00000344),
.CLK(aclk),
.D(sig000009b2),
.Q(\blk00000659/sig00000e3c ),
.Q15(\NLW_blk00000659/blk0000065b_Q15_UNCONNECTED )
);
GND \blk00000659/blk0000065a (
.G(\blk00000659/sig00000e3b )
);
FDE #(
.INIT ( 1'b0 ))
\blk000007cb/blk000007cf (
.C(aclk),
.CE(\blk000007cb/sig00000e41 ),
.D(\blk000007cb/sig00000e42 ),
.Q(sig0000088e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk000007cb/blk000007ce (
.A0(\blk000007cb/sig00000e41 ),
.A1(\blk000007cb/sig00000e41 ),
.A2(\blk000007cb/sig00000e40 ),
.A3(\blk000007cb/sig00000e40 ),
.CE(\blk000007cb/sig00000e41 ),
.CLK(aclk),
.D(sig0000088f),
.Q(\blk000007cb/sig00000e42 ),
.Q15(\NLW_blk000007cb/blk000007ce_Q15_UNCONNECTED )
);
VCC \blk000007cb/blk000007cd (
.P(\blk000007cb/sig00000e41 )
);
GND \blk000007cb/blk000007cc (
.G(\blk000007cb/sig00000e40 )
);
FDE #(
.INIT ( 1'b0 ))
\blk0000083a/blk0000083d (
.C(aclk),
.CE(sig00000344),
.D(\blk0000083a/sig00000e48 ),
.Q(sig00000c20)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk0000083a/blk0000083c (
.A0(\blk0000083a/sig00000e47 ),
.A1(\blk0000083a/sig00000e47 ),
.A2(\blk0000083a/sig00000e47 ),
.A3(\blk0000083a/sig00000e47 ),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000c21),
.Q(\blk0000083a/sig00000e48 ),
.Q15(\NLW_blk0000083a/blk0000083c_Q15_UNCONNECTED )
);
GND \blk0000083a/blk0000083b (
.G(\blk0000083a/sig00000e47 )
);
FDE #(
.INIT ( 1'b0 ))
\blk0000083e/blk00000841 (
.C(aclk),
.CE(sig00000344),
.D(\blk0000083e/sig00000e4e ),
.Q(sig00000c1f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk0000083e/blk00000840 (
.A0(\blk0000083e/sig00000e4d ),
.A1(\blk0000083e/sig00000e4d ),
.A2(\blk0000083e/sig00000e4d ),
.A3(\blk0000083e/sig00000e4d ),
.CE(sig00000344),
.CLK(aclk),
.D(sig00000c20),
.Q(\blk0000083e/sig00000e4e ),
.Q15(\NLW_blk0000083e/blk00000840_Q15_UNCONNECTED )
);
GND \blk0000083e/blk0000083f (
.G(\blk0000083e/sig00000e4d )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
module membusif(
input wire clk,
input wire reset,
// Avalon Slave
input wire [1:0] s_address,
input wire s_write,
input wire s_read,
input wire [31:0] s_writedata,
output reg [31:0] s_readdata,
output wire s_waitrequest,
// Membus Master
output reg m_rq_cyc,
output reg m_rd_rq,
output reg m_wr_rq,
output wire [21:35] m_ma,
output wire [18:21] m_sel,
output reg m_fmc_select,
output wire [0:35] m_mb_write,
output wire m_wr_rs,
input wire [0:35] m_mb_read,
input wire m_addr_ack,
input wire m_rd_rs
);
reg [0:17] addr;
reg [0:35] word;
assign m_ma = addr[3:17];
assign m_sel = addr[0:3];
wire write_edge, read_edge;
edgedet e0(clk, reset, s_write, write_edge);
edgedet e1(clk, reset, s_read, read_edge);
reg waiting;
wire req = (write_edge|read_edge) & s_address == 2'h2;
assign s_waitrequest = req | waiting | (|waitcyc);
wire mb_write_pulse;
wire wr_rs = m_addr_ack & m_wr_rq;
bd mc_bd0(clk, ~reset, wr_rs, m_wr_rs);
bd2 mb_bd1(clk, ~reset, wr_rs, mb_write_pulse);
assign m_mb_write = mb_write_pulse ? word : 0;
reg [7:0] waitcyc;
always @(posedge clk or negedge reset) begin
if(~reset) begin
m_rq_cyc <= 0;
m_rd_rq <= 0;
m_wr_rq <= 0;
waiting <= 0;
addr <= 0;
m_fmc_select <= 0;
word <= 0;
waitcyc <= 0;
end else begin
if(write_edge) begin
case(s_address)
2'h0: begin
addr <= s_writedata[17:0];
m_fmc_select <= s_writedata[18];
end
2'h1: word[18:35] <= s_writedata[17:0];
2'h2: word[0:17] <= s_writedata[17:0];
endcase
end
if(req) begin
waiting <= 1;
m_rq_cyc <= 1;
if(s_write)
m_wr_rq <= 1;
else if(s_read) begin
m_rd_rq <= 1;
word <= 0;
end
end
// have to wait between cycles
// because fastmem can get stuck
if(waitcyc) begin
if(waitcyc == 'o14)
waitcyc <= 0;
else
waitcyc <= waitcyc + 1;
end
if(waiting & m_rd_rq)
word <= m_mb_read;
if(m_addr_ack) begin
m_rq_cyc <= 0;
waitcyc <= 1;
end
if(m_rd_rs) begin
m_rd_rq <= 0;
waiting <= 0;
end
if(m_wr_rs) begin
m_wr_rq <= 0;
waiting <= 0;
end
end
end
always @(*) begin
case(s_address)
2'h1: s_readdata <= { 14'b0, word[18:35] };
2'h2: s_readdata <= { 14'b0, word[0:17] };
default: s_readdata <= 32'b0;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLRTP_1_V
`define SKY130_FD_SC_LP__SRDLRTP_1_V
/**
* srdlrtp: ????.
*
* Verilog wrapper for srdlrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srdlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srdlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__srdlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.SLEEP_B(SLEEP_B),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__srdlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
SLEEP_B
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__srdlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLRTP_1_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:50:23 2016
/////////////////////////////////////////////////////////////
module FPU_Add_Subtract_Function_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
input [1:0] r_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_C, add_overflow_flag, FSM_exp_operation_A_S, intAS,
sign_final_result, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, DP_OP_42J152_122_8302_n26, DP_OP_42J152_122_8302_n25,
DP_OP_42J152_122_8302_n24, DP_OP_42J152_122_8302_n23,
DP_OP_42J152_122_8302_n22, DP_OP_42J152_122_8302_n21,
DP_OP_42J152_122_8302_n20, DP_OP_42J152_122_8302_n19,
DP_OP_42J152_122_8302_n18, DP_OP_42J152_122_8302_n17,
DP_OP_42J152_122_8302_n16, DP_OP_42J152_122_8302_n11,
DP_OP_42J152_122_8302_n10, DP_OP_42J152_122_8302_n9,
DP_OP_42J152_122_8302_n8, DP_OP_42J152_122_8302_n7,
DP_OP_42J152_122_8302_n6, DP_OP_42J152_122_8302_n5,
DP_OP_42J152_122_8302_n4, DP_OP_42J152_122_8302_n3,
DP_OP_42J152_122_8302_n2, DP_OP_42J152_122_8302_n1, n1577, n1578,
n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588,
n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598,
n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608,
n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618,
n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628,
n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638,
n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648,
n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658,
n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668,
n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678,
n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688,
n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698,
n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708,
n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718,
n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728,
n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738,
n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748,
n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758,
n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768,
n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778,
n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788,
n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798,
n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808,
n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818,
n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828,
n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838,
n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848,
n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858,
n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868,
n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878,
n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888,
n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898,
n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908,
n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918,
n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928,
n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938,
n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948,
n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958,
n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968,
n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978,
n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988,
n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998,
n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008,
n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018,
n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028,
n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038,
n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048,
n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058,
n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068,
n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078,
n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088,
n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098,
n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108,
n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118,
n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128,
n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138,
n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148,
n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158,
n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168,
n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178,
n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188,
n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198,
n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208,
n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218,
n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228,
n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238,
n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248,
n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258,
n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268,
n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278,
n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288,
n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298,
n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308,
n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318,
n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328,
n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338,
n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348,
n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358,
n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368,
n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378,
n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388,
n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398,
n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408,
n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418,
n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428,
n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438,
n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448,
n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458,
n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468,
n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478,
n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488,
n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498,
n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508,
n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518,
n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528,
n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538,
n2539, n2540, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549,
n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559,
n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569,
n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579,
n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589,
n2590, n2591, n2592, n2594, n2595, n2596, n2597, n2598, n2599, n2600,
n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610,
n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620,
n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630,
n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640,
n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650,
n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660,
n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670,
n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680,
n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690,
n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700,
n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710,
n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720,
n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730,
n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740,
n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750,
n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760,
n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770,
n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780,
n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790,
n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800,
n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810,
n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820,
n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830,
n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840,
n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850,
n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860,
n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870,
n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880,
n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890,
n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900,
n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910,
n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920,
n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930,
n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940,
n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950,
n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960,
n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970,
n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980,
n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990,
n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000,
n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010,
n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020,
n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030,
n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040,
n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050,
n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060,
n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070,
n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080,
n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090,
n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100,
n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120,
n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130,
n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140,
n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150,
n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160,
n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170,
n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180,
n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190,
n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200,
n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210,
n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220,
n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230,
n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240,
n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250,
n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270,
n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280,
n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290,
n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300,
n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310,
n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320,
n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330,
n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340,
n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350,
n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360,
n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370,
n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380,
n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390,
n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400,
n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410,
n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420,
n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430,
n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440,
n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450,
n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460,
n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470,
n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480,
n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490,
n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500,
n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510,
n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520,
n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528;
wire [1:0] FSM_selector_B;
wire [63:0] intDX;
wire [63:0] intDY;
wire [62:0] DMP;
wire [62:0] DmP;
wire [10:0] exp_oper_result;
wire [10:0] S_Oper_A_exp;
wire [5:0] LZA_output;
wire [54:0] Add_Subt_result;
wire [54:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [10:0] Exp_Operation_Module_Data_S;
wire [94:0] Barrel_Shifter_module_Mux_Array_Data_array;
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n1560), .CK(clk), .RN(n3516), .Q(
FS_Module_state_reg[0]), .QN(n3377) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(n1524), .CK(clk),
.RN(n3495), .QN(n1585) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(n1501), .CK(
clk), .RN(n3497), .QN(n1589) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(n1500), .CK(
clk), .RN(n3504), .QN(n1588) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(n1498), .CK(
clk), .RN(n3504), .QN(n1586) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_5_ ( .D(n1496), .CK(
clk), .RN(n3507), .Q(LZA_output[5]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_30_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .CK(clk), .RN(n3481),
.QN(n1591) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_29_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .CK(clk), .RN(n3481),
.QN(n1597) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_28_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .CK(clk), .RN(n3481),
.QN(n1594) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_27_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .CK(clk), .RN(n3482),
.QN(n1606) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_26_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .CK(clk), .RN(n3482),
.QN(n1595) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n3482),
.QN(n1596) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n3482),
.QN(n1592) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n3482),
.QN(n1604) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n3482),
.QN(n1602) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n3482),
.QN(n1601) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n3482),
.QN(n1598) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n3482),
.QN(n1600) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n3482),
.QN(n1599) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n3482),
.QN(n1603) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n3482),
.QN(n1593) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n3497),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[62]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n3483),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[61]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n3484),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[60]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n3497),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[59]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n3483),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[58]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n3484),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[57]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n3497),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[56]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n3483),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[55]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1459), .CK(clk),
.RN(n3510), .QN(n1578) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1460), .CK(clk),
.RN(n3491), .QN(n1579) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1461), .CK(clk),
.RN(n1611), .QN(n1581) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1462), .CK(clk),
.RN(n3499), .QN(n1582) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_44_ ( .D(n1213), .CK(clk),
.RN(n3502), .Q(DMP[44]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_42_ ( .D(n1211), .CK(clk),
.RN(n3502), .Q(DMP[42]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_62_ ( .D(n1168), .CK(clk),
.RN(n3506), .Q(DMP[62]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_61_ ( .D(n1166), .CK(clk),
.RN(n3505), .Q(DmP[61]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_60_ ( .D(n1165), .CK(clk),
.RN(n3481), .Q(DmP[60]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_59_ ( .D(n1164), .CK(clk),
.RN(n3518), .Q(DmP[59]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_58_ ( .D(n1163), .CK(clk),
.RN(n3505), .Q(DmP[58]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_57_ ( .D(n1162), .CK(clk),
.RN(n3504), .Q(DmP[57]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_56_ ( .D(n1161), .CK(clk),
.RN(n3504), .Q(DmP[56]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_55_ ( .D(n1160), .CK(clk),
.RN(n3504), .Q(DmP[55]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_54_ ( .D(n1159), .CK(clk),
.RN(n3504), .Q(DmP[54]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_53_ ( .D(n1158), .CK(clk),
.RN(n3518), .Q(DmP[53]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_52_ ( .D(n1157), .CK(clk),
.RN(n3505), .Q(DmP[52]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_51_ ( .D(n1156), .CK(clk),
.RN(n3491), .Q(DmP[51]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_50_ ( .D(n1155), .CK(clk),
.RN(n3491), .Q(DmP[50]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_49_ ( .D(n1154), .CK(clk),
.RN(n3491), .Q(DmP[49]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_48_ ( .D(n1153), .CK(clk),
.RN(n3491), .Q(DmP[48]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n1130), .CK(clk),
.RN(n3492), .Q(DmP[25]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n1108), .CK(clk), .RN(
n3487), .QN(n1605) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_62_ ( .D(n1104), .CK(clk),
.RN(n3518), .Q(DmP[62]) );
CMPR32X2TS DP_OP_42J152_122_8302_U12 ( .A(S_Oper_A_exp[0]), .B(
FSM_exp_operation_A_S), .C(DP_OP_42J152_122_8302_n26), .CO(
DP_OP_42J152_122_8302_n11), .S(Exp_Operation_Module_Data_S[0]) );
CMPR32X2TS DP_OP_42J152_122_8302_U11 ( .A(DP_OP_42J152_122_8302_n25), .B(
S_Oper_A_exp[1]), .C(DP_OP_42J152_122_8302_n11), .CO(
DP_OP_42J152_122_8302_n10), .S(Exp_Operation_Module_Data_S[1]) );
CMPR32X2TS DP_OP_42J152_122_8302_U10 ( .A(DP_OP_42J152_122_8302_n24), .B(
S_Oper_A_exp[2]), .C(DP_OP_42J152_122_8302_n10), .CO(
DP_OP_42J152_122_8302_n9), .S(Exp_Operation_Module_Data_S[2]) );
CMPR32X2TS DP_OP_42J152_122_8302_U9 ( .A(DP_OP_42J152_122_8302_n23), .B(
S_Oper_A_exp[3]), .C(DP_OP_42J152_122_8302_n9), .CO(
DP_OP_42J152_122_8302_n8), .S(Exp_Operation_Module_Data_S[3]) );
CMPR32X2TS DP_OP_42J152_122_8302_U8 ( .A(DP_OP_42J152_122_8302_n22), .B(
S_Oper_A_exp[4]), .C(DP_OP_42J152_122_8302_n8), .CO(
DP_OP_42J152_122_8302_n7), .S(Exp_Operation_Module_Data_S[4]) );
CMPR32X2TS DP_OP_42J152_122_8302_U7 ( .A(DP_OP_42J152_122_8302_n21), .B(
S_Oper_A_exp[5]), .C(DP_OP_42J152_122_8302_n7), .CO(
DP_OP_42J152_122_8302_n6), .S(Exp_Operation_Module_Data_S[5]) );
CMPR32X2TS DP_OP_42J152_122_8302_U6 ( .A(DP_OP_42J152_122_8302_n20), .B(
S_Oper_A_exp[6]), .C(DP_OP_42J152_122_8302_n6), .CO(
DP_OP_42J152_122_8302_n5), .S(Exp_Operation_Module_Data_S[6]) );
CMPR32X2TS DP_OP_42J152_122_8302_U5 ( .A(DP_OP_42J152_122_8302_n19), .B(
S_Oper_A_exp[7]), .C(DP_OP_42J152_122_8302_n5), .CO(
DP_OP_42J152_122_8302_n4), .S(Exp_Operation_Module_Data_S[7]) );
CMPR32X2TS DP_OP_42J152_122_8302_U4 ( .A(DP_OP_42J152_122_8302_n18), .B(
S_Oper_A_exp[8]), .C(DP_OP_42J152_122_8302_n4), .CO(
DP_OP_42J152_122_8302_n3), .S(Exp_Operation_Module_Data_S[8]) );
CMPR32X2TS DP_OP_42J152_122_8302_U3 ( .A(DP_OP_42J152_122_8302_n17), .B(
S_Oper_A_exp[9]), .C(DP_OP_42J152_122_8302_n3), .CO(
DP_OP_42J152_122_8302_n2), .S(Exp_Operation_Module_Data_S[9]) );
CMPR32X2TS DP_OP_42J152_122_8302_U2 ( .A(DP_OP_42J152_122_8302_n16), .B(
S_Oper_A_exp[10]), .C(DP_OP_42J152_122_8302_n2), .CO(
DP_OP_42J152_122_8302_n1), .S(Exp_Operation_Module_Data_S[10]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_53_ ( .D(n1495), .CK(clk),
.RN(n3503), .Q(Sgf_normalized_result[53]), .QN(n3470) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n1494), .CK(clk),
.RN(n3503), .Q(Sgf_normalized_result[52]), .QN(n3462) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n1493), .CK(clk),
.RN(n3503), .Q(Sgf_normalized_result[51]), .QN(n3461) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n1492), .CK(clk),
.RN(n3503), .Q(Sgf_normalized_result[50]), .QN(n3460) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n1491), .CK(clk),
.RN(n3503), .Q(Sgf_normalized_result[49]), .QN(n3455) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n1490), .CK(clk),
.RN(n3502), .Q(Sgf_normalized_result[48]), .QN(n3454) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n1488), .CK(clk),
.RN(n3502), .Q(Sgf_normalized_result[46]), .QN(n3443) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n1487), .CK(clk),
.RN(n3502), .Q(Sgf_normalized_result[45]), .QN(n3442) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n1486), .CK(clk),
.RN(n3502), .Q(Sgf_normalized_result[44]), .QN(n3441) );
DFFRX2TS XRegister_Q_reg_51_ ( .D(n1348), .CK(clk), .RN(n3488), .Q(intDX[51]), .QN(n3437) );
DFFRX2TS XRegister_Q_reg_59_ ( .D(n1356), .CK(clk), .RN(n3512), .Q(intDX[59]), .QN(n3436) );
DFFRX2TS XRegister_Q_reg_19_ ( .D(n1316), .CK(clk), .RN(n3519), .Q(intDX[19]), .QN(n3435) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n1485), .CK(clk),
.RN(n3502), .Q(Sgf_normalized_result[43]), .QN(n3434) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n1484), .CK(clk),
.RN(n3483), .Q(Sgf_normalized_result[42]), .QN(n3433) );
DFFRX2TS XRegister_Q_reg_34_ ( .D(n1331), .CK(clk), .RN(n3519), .Q(intDX[34]), .QN(n3430) );
DFFRX2TS XRegister_Q_reg_42_ ( .D(n1339), .CK(clk), .RN(n3488), .Q(intDX[42]), .QN(n3427) );
DFFRX2TS XRegister_Q_reg_46_ ( .D(n1343), .CK(clk), .RN(n3512), .Q(intDX[46]), .QN(n3425) );
DFFRX2TS XRegister_Q_reg_36_ ( .D(n1333), .CK(clk), .RN(n3487), .Q(intDX[36]), .QN(n3423) );
DFFRX2TS XRegister_Q_reg_41_ ( .D(n1338), .CK(clk), .RN(n3512), .Q(intDX[41]), .QN(n3422) );
DFFRX2TS XRegister_Q_reg_33_ ( .D(n1330), .CK(clk), .RN(n3511), .Q(intDX[33]), .QN(n3421) );
DFFRX2TS XRegister_Q_reg_57_ ( .D(n1354), .CK(clk), .RN(n3487), .Q(intDX[57]), .QN(n3420) );
DFFRX2TS XRegister_Q_reg_27_ ( .D(n1324), .CK(clk), .RN(n1612), .Q(intDX[27]), .QN(n3419) );
DFFRX2TS XRegister_Q_reg_28_ ( .D(n1325), .CK(clk), .RN(n3519), .Q(intDX[28]), .QN(n3418) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n1483), .CK(clk),
.RN(n3496), .Q(Sgf_normalized_result[41]), .QN(n3417) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n1482), .CK(clk),
.RN(n3484), .Q(Sgf_normalized_result[40]), .QN(n3416) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n1481), .CK(clk),
.RN(n3481), .Q(Sgf_normalized_result[39]), .QN(n3415) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n1480), .CK(clk),
.RN(n3497), .Q(Sgf_normalized_result[38]), .QN(n3414) );
DFFRX2TS XRegister_Q_reg_20_ ( .D(n1317), .CK(clk), .RN(n3500), .Q(intDX[20]), .QN(n3413) );
DFFRX2TS XRegister_Q_reg_25_ ( .D(n1322), .CK(clk), .RN(n3499), .Q(intDX[25]), .QN(n3412) );
DFFRX2TS XRegister_Q_reg_17_ ( .D(n1314), .CK(clk), .RN(n3513), .Q(intDX[17]), .QN(n3411) );
DFFRX2TS XRegister_Q_reg_8_ ( .D(n1305), .CK(clk), .RN(n3518), .Q(intDX[8]),
.QN(n3410) );
DFFRX2TS XRegister_Q_reg_49_ ( .D(n1346), .CK(clk), .RN(n3487), .Q(intDX[49]), .QN(n3409) );
DFFRX2TS XRegister_Q_reg_21_ ( .D(n1318), .CK(clk), .RN(n3511), .Q(intDX[21]), .QN(n3408) );
DFFRX2TS XRegister_Q_reg_13_ ( .D(n1310), .CK(clk), .RN(n3505), .Q(intDX[13]), .QN(n3406) );
DFFRX2TS XRegister_Q_reg_14_ ( .D(n1311), .CK(clk), .RN(n3518), .Q(intDX[14]), .QN(n3404) );
DFFRX2TS XRegister_Q_reg_3_ ( .D(n1300), .CK(clk), .RN(n3507), .Q(intDX[3]),
.QN(n3403) );
DFFRX2TS XRegister_Q_reg_11_ ( .D(n1308), .CK(clk), .RN(n3518), .Q(intDX[11]), .QN(n3402) );
DFFRX2TS YRegister_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n3511), .Q(intDY[16]), .QN(n3398) );
DFFRX2TS XRegister_Q_reg_53_ ( .D(n1350), .CK(clk), .RN(n3488), .Q(intDX[53]), .QN(n3397) );
DFFRX2TS XRegister_Q_reg_23_ ( .D(n1320), .CK(clk), .RN(n1611), .Q(intDX[23]), .QN(n3396) );
DFFRX2TS XRegister_Q_reg_12_ ( .D(n1309), .CK(clk), .RN(n3505), .Q(intDX[12]), .QN(n3393) );
DFFRX2TS YRegister_Q_reg_6_ ( .D(n1238), .CK(clk), .RN(n3491), .Q(intDY[6]),
.QN(n3389) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n1477), .CK(clk),
.RN(n3501), .Q(Sgf_normalized_result[35]), .QN(n3384) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n1475), .CK(clk),
.RN(n3501), .Q(Sgf_normalized_result[33]), .QN(n3382) );
DFFRX2TS Sel_B_Q_reg_0_ ( .D(n1440), .CK(clk), .RN(n1360), .Q(
FSM_selector_B[0]), .QN(n3380) );
DFFRX2TS YRegister_Q_reg_5_ ( .D(n1237), .CK(clk), .RN(n3491), .Q(intDY[5]),
.QN(n3379) );
DFFRX2TS YRegister_Q_reg_37_ ( .D(n1269), .CK(clk), .RN(n3513), .Q(intDY[37]), .QN(n3378) );
DFFRX2TS YRegister_Q_reg_38_ ( .D(n1270), .CK(clk), .RN(n3490), .Q(intDY[38]), .QN(n3376) );
DFFRX2TS YRegister_Q_reg_52_ ( .D(n1284), .CK(clk), .RN(n3489), .Q(intDY[52]), .QN(n3375) );
DFFRX2TS YRegister_Q_reg_10_ ( .D(n1242), .CK(clk), .RN(n3514), .Q(intDY[10]), .QN(n3374) );
DFFRX2TS YRegister_Q_reg_44_ ( .D(n1276), .CK(clk), .RN(n3489), .Q(intDY[44]), .QN(n3373) );
DFFRX2TS YRegister_Q_reg_48_ ( .D(n1280), .CK(clk), .RN(n3513), .Q(intDY[48]), .QN(n3372) );
DFFRX2TS YRegister_Q_reg_1_ ( .D(n1233), .CK(clk), .RN(n3491), .Q(intDY[1]),
.QN(n3366) );
DFFRX2TS YRegister_Q_reg_61_ ( .D(n1293), .CK(clk), .RN(n3519), .Q(intDY[61]), .QN(n3364) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1457), .CK(clk),
.RN(n3494), .Q(Sgf_normalized_result[15]), .QN(n3362) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1453), .CK(clk),
.RN(n3499), .Q(Sgf_normalized_result[11]), .QN(n3361) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1452), .CK(clk),
.RN(n3512), .Q(Sgf_normalized_result[10]), .QN(n3360) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1451), .CK(clk),
.RN(n1612), .Q(Sgf_normalized_result[9]), .QN(n3359) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1463), .CK(clk),
.RN(n1611), .Q(Sgf_normalized_result[21]), .QN(n3356) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1443), .CK(clk),
.RN(n3504), .Q(Sgf_normalized_result[1]), .QN(n3355) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1442), .CK(clk),
.RN(n3504), .Q(Sgf_normalized_result[0]), .QN(n3354) );
DFFRX1TS Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n1426), .CK(clk), .RN(
n3484), .Q(underflow_flag), .QN(n3346) );
DFFRX2TS XRegister_Q_reg_35_ ( .D(n1332), .CK(clk), .RN(n3515), .Q(intDX[35]), .QN(n3340) );
DFFRX2TS XRegister_Q_reg_26_ ( .D(n1323), .CK(clk), .RN(n3511), .Q(intDX[26]), .QN(n3339) );
DFFRX2TS XRegister_Q_reg_18_ ( .D(n1315), .CK(clk), .RN(n3508), .Q(intDX[18]), .QN(n3338) );
DFFRX2TS YRegister_Q_reg_62_ ( .D(n1294), .CK(clk), .RN(n1612), .Q(intDY[62]), .QN(n3336) );
DFFRX2TS XRegister_Q_reg_54_ ( .D(n1351), .CK(clk), .RN(n3487), .Q(intDX[54]), .QN(n3334) );
DFFRX2TS XRegister_Q_reg_22_ ( .D(n1319), .CK(clk), .RN(n3511), .Q(intDX[22]), .QN(n3333) );
DFFRX2TS XRegister_Q_reg_30_ ( .D(n1327), .CK(clk), .RN(n3519), .Q(intDX[30]), .QN(n3332) );
DFFRX2TS YRegister_Q_reg_7_ ( .D(n1239), .CK(clk), .RN(n3491), .Q(intDY[7]),
.QN(n3331) );
DFFRX2TS YRegister_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n3491), .Q(intDY[4]),
.QN(n3328) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n1559), .CK(clk), .RN(n3508), .Q(
FS_Module_state_reg[1]), .QN(n3327) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n1561), .CK(clk), .RN(n3516), .Q(
FS_Module_state_reg[3]), .QN(n3321) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n1558), .CK(clk), .RN(n3508), .Q(
FS_Module_state_reg[2]), .QN(n3318) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n1361),
.CK(clk), .RN(n3488), .Q(final_result_ieee[63]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n1395),
.CK(clk), .RN(n3486), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n1394),
.CK(clk), .RN(n3486), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n1393),
.CK(clk), .RN(n3520), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n1392),
.CK(clk), .RN(n3485), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n1391),
.CK(clk), .RN(n1610), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n1390),
.CK(clk), .RN(n3486), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n1389),
.CK(clk), .RN(n3520), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n1388),
.CK(clk), .RN(n3485), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n1387),
.CK(clk), .RN(n1610), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n1386),
.CK(clk), .RN(n3486), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n1385),
.CK(clk), .RN(n3520), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n1384),
.CK(clk), .RN(n3485), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n1383),
.CK(clk), .RN(n1610), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n1382),
.CK(clk), .RN(n3506), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n1381),
.CK(clk), .RN(n3502), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n1380),
.CK(clk), .RN(n3509), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n1379),
.CK(clk), .RN(n3517), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n1378),
.CK(clk), .RN(n3517), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n1377),
.CK(clk), .RN(n3509), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n1376),
.CK(clk), .RN(n3506), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n1375),
.CK(clk), .RN(n3506), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n1374),
.CK(clk), .RN(n3509), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n1373),
.CK(clk), .RN(n3517), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n1372),
.CK(clk), .RN(n3517), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n1371),
.CK(clk), .RN(n3506), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n1370),
.CK(clk), .RN(n3509), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n1369),
.CK(clk), .RN(n3517), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n1368),
.CK(clk), .RN(n3506), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n1367),
.CK(clk), .RN(n3509), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n1366),
.CK(clk), .RN(n3517), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n1365),
.CK(clk), .RN(n3506), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n1364),
.CK(clk), .RN(n3509), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n1363),
.CK(clk), .RN(n3517), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n1414),
.CK(clk), .RN(n3494), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n1413),
.CK(clk), .RN(n3494), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n1412),
.CK(clk), .RN(n3494), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n1411),
.CK(clk), .RN(n3494), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n1410),
.CK(clk), .RN(n3494), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n1409),
.CK(clk), .RN(n3494), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n1404),
.CK(clk), .RN(n3488), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n1403),
.CK(clk), .RN(n3485), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n1402),
.CK(clk), .RN(n3487), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n1400),
.CK(clk), .RN(n3512), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n1399),
.CK(clk), .RN(n3491), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n1398),
.CK(clk), .RN(n3500), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n1397),
.CK(clk), .RN(n3513), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n1396),
.CK(clk), .RN(n3487), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n1424),
.CK(clk), .RN(n3520), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n1422),
.CK(clk), .RN(n3485), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n1421),
.CK(clk), .RN(n1610), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n1419),
.CK(clk), .RN(n3486), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n1418),
.CK(clk), .RN(n3520), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n1417),
.CK(clk), .RN(n3485), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n1416),
.CK(clk), .RN(n1610), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n1415),
.CK(clk), .RN(n3486), .Q(final_result_ieee[62]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n1408),
.CK(clk), .RN(n3494), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n1407),
.CK(clk), .RN(n3499), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n1406),
.CK(clk), .RN(n1611), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n1405),
.CK(clk), .RN(n3519), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n1401),
.CK(clk), .RN(n1612), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n1425),
.CK(clk), .RN(n3485), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n1423),
.CK(clk), .RN(n1610), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n1420),
.CK(clk), .RN(n3486), .Q(final_result_ieee[57]) );
DFFRX1TS Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n1427), .CK(clk), .RN(
n3497), .Q(overflow_flag) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_32_ ( .D(n1535), .CK(clk),
.RN(n3497), .Q(Add_Subt_result[32]), .QN(n3438) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_33_ ( .D(n1536), .CK(clk),
.RN(n3484), .Q(Add_Subt_result[33]), .QN(n3444) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_52_ ( .D(n1555), .CK(clk),
.RN(n3512), .Q(Add_Subt_result[52]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n1503), .CK(clk),
.RN(n3483), .Q(Add_Subt_result[0]), .QN(n3468) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n1504), .CK(clk),
.RN(n3484), .Q(Add_Subt_result[1]), .QN(n3469) );
DFFRX2TS XRegister_Q_reg_29_ ( .D(n1326), .CK(clk), .RN(n1611), .Q(intDX[29]), .QN(n3407) );
DFFRX2TS XRegister_Q_reg_55_ ( .D(n1352), .CK(clk), .RN(n3487), .Q(intDX[55]), .QN(n3480) );
DFFRX2TS XRegister_Q_reg_45_ ( .D(n1342), .CK(clk), .RN(n3488), .Q(intDX[45]), .QN(n3478) );
DFFRX2TS XRegister_Q_reg_31_ ( .D(n1328), .CK(clk), .RN(n3519), .Q(intDX[31]), .QN(n3476) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n1511), .CK(clk),
.RN(n3496), .Q(Add_Subt_result[8]), .QN(n3344) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_26_ ( .D(n1529), .CK(clk),
.RN(n3494), .Q(Add_Subt_result[26]), .QN(n3447) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(n1526), .CK(clk),
.RN(n3495), .Q(Add_Subt_result[23]), .QN(n3320) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_28_ ( .D(n1531), .CK(clk),
.RN(n3497), .Q(Add_Subt_result[28]), .QN(n3350) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(n1527), .CK(clk),
.RN(n3495), .Q(Add_Subt_result[24]), .QN(n3446) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n1517), .CK(clk),
.RN(n3495), .Q(Add_Subt_result[14]), .QN(n3322) );
DFFRX2TS XRegister_Q_reg_15_ ( .D(n1312), .CK(clk), .RN(n1610), .Q(intDX[15]), .QN(n3528) );
DFFRX2TS XRegister_Q_reg_60_ ( .D(n1357), .CK(clk), .RN(n3517), .Q(intDX[60]), .QN(n3527) );
DFFRX2TS XRegister_Q_reg_58_ ( .D(n1355), .CK(clk), .RN(n3487), .Q(intDX[58]), .QN(n3477) );
DFFRX2TS XRegister_Q_reg_50_ ( .D(n1347), .CK(clk), .RN(n3487), .Q(intDX[50]), .QN(n3479) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(n1528), .CK(clk),
.RN(n3494), .Q(Add_Subt_result[25]), .QN(n3363) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_35_ ( .D(n1538), .CK(clk),
.RN(n3483), .Q(Add_Subt_result[35]), .QN(n3463) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_40_ ( .D(n1543), .CK(clk),
.RN(n3498), .Q(Add_Subt_result[40]), .QN(n3432) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_43_ ( .D(n1546), .CK(clk),
.RN(n3498), .Q(Add_Subt_result[43]), .QN(n3445) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_46_ ( .D(n1549), .CK(clk),
.RN(n3498), .Q(Add_Subt_result[46]), .QN(n3456) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_47_ ( .D(n1550), .CK(clk),
.RN(n3498), .Q(Add_Subt_result[47]), .QN(n3347) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_50_ ( .D(n1553), .CK(clk),
.RN(n3498), .Q(Add_Subt_result[50]), .QN(n3457) );
DFFRX1TS XRegister_Q_reg_6_ ( .D(n1303), .CK(clk), .RN(n3521), .Q(intDX[6]),
.QN(n3401) );
DFFRX1TS XRegister_Q_reg_24_ ( .D(n1321), .CK(clk), .RN(n3511), .Q(intDX[24]), .QN(n3388) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n1515), .CK(clk),
.RN(n3496), .Q(Add_Subt_result[12]), .QN(n3449) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_47_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .CK(clk), .RN(n3516),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[87]), .QN(n3472) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_48_ ( .D(n1551), .CK(clk),
.RN(n3486), .Q(Add_Subt_result[48]), .QN(n3348) );
DFFRX2TS YRegister_Q_reg_3_ ( .D(n1235), .CK(clk), .RN(n3491), .Q(intDY[3])
);
DFFRX2TS YRegister_Q_reg_53_ ( .D(n1285), .CK(clk), .RN(n3489), .Q(intDY[53]) );
DFFRX2TS YRegister_Q_reg_33_ ( .D(n1265), .CK(clk), .RN(n3513), .Q(intDY[33]) );
DFFRX2TS YRegister_Q_reg_43_ ( .D(n1275), .CK(clk), .RN(n3490), .Q(intDY[43]) );
DFFRX2TS YRegister_Q_reg_55_ ( .D(n1287), .CK(clk), .RN(n3489), .Q(intDY[55]) );
DFFRX2TS YRegister_Q_reg_41_ ( .D(n1273), .CK(clk), .RN(n3513), .Q(intDY[41]) );
DFFRX2TS YRegister_Q_reg_35_ ( .D(n1267), .CK(clk), .RN(n3490), .Q(intDY[35]) );
DFFRX2TS YRegister_Q_reg_15_ ( .D(n1247), .CK(clk), .RN(n3514), .Q(intDY[15]) );
DFFRX2TS YRegister_Q_reg_23_ ( .D(n1255), .CK(clk), .RN(n3510), .Q(intDY[23]) );
DFFRX2TS YRegister_Q_reg_31_ ( .D(n1263), .CK(clk), .RN(n3510), .Q(intDY[31]) );
DFFRX2TS YRegister_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n3510), .Q(intDY[13]) );
DFFRX2TS YRegister_Q_reg_29_ ( .D(n1261), .CK(clk), .RN(n3514), .Q(intDY[29]) );
DFFRX2TS YRegister_Q_reg_21_ ( .D(n1253), .CK(clk), .RN(n3514), .Q(intDY[21]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(n1525), .CK(clk),
.RN(n3495), .Q(Add_Subt_result[22]) );
DFFRX2TS YRegister_Q_reg_46_ ( .D(n1278), .CK(clk), .RN(n3489), .Q(intDY[46]) );
DFFRX2TS YRegister_Q_reg_60_ ( .D(n1292), .CK(clk), .RN(n3519), .Q(intDY[60]) );
DFFRX2TS YRegister_Q_reg_58_ ( .D(n1290), .CK(clk), .RN(n3515), .Q(intDY[58]) );
DFFRX2TS YRegister_Q_reg_11_ ( .D(n1243), .CK(clk), .RN(n3514), .Q(intDY[11]) );
DFFRX2TS YRegister_Q_reg_49_ ( .D(n1281), .CK(clk), .RN(n3489), .Q(intDY[49]) );
DFFRX2TS YRegister_Q_reg_28_ ( .D(n1260), .CK(clk), .RN(n3514), .Q(intDY[28]) );
DFFRX2TS YRegister_Q_reg_8_ ( .D(n1240), .CK(clk), .RN(n3510), .Q(intDY[8])
);
DFFRX2TS YRegister_Q_reg_26_ ( .D(n1258), .CK(clk), .RN(n3510), .Q(intDY[26]) );
DFFRX2TS YRegister_Q_reg_18_ ( .D(n1250), .CK(clk), .RN(n3510), .Q(intDY[18]) );
DFFRX2TS YRegister_Q_reg_40_ ( .D(n1272), .CK(clk), .RN(n3490), .Q(intDY[40]) );
DFFRX2TS YRegister_Q_reg_51_ ( .D(n1283), .CK(clk), .RN(n3489), .Q(intDY[51]) );
DFFRX2TS YRegister_Q_reg_19_ ( .D(n1251), .CK(clk), .RN(n3500), .Q(intDY[19]) );
DFFRX2TS YRegister_Q_reg_2_ ( .D(n1234), .CK(clk), .RN(n3491), .Q(intDY[2])
);
DFFRX2TS YRegister_Q_reg_9_ ( .D(n1241), .CK(clk), .RN(n3510), .Q(intDY[9])
);
DFFRX2TS YRegister_Q_reg_47_ ( .D(n1279), .CK(clk), .RN(n3489), .Q(intDY[47]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n1510), .CK(clk),
.RN(n3496), .Q(Add_Subt_result[7]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_29_ ( .D(n1532), .CK(clk),
.RN(n3494), .Q(Add_Subt_result[29]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(n1516), .CK(clk),
.RN(n3496), .Q(Add_Subt_result[13]) );
DFFRX2TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(n1562), .CK(
clk), .RN(n3507), .Q(add_overflow_flag) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_45_ ( .D(n1548), .CK(clk),
.RN(n3498), .Q(Add_Subt_result[45]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(n1520), .CK(clk),
.RN(n3495), .Q(Add_Subt_result[17]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_42_ ( .D(n1545), .CK(clk),
.RN(n3498), .Q(Add_Subt_result[42]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_49_ ( .D(n1552), .CK(clk),
.RN(n3498), .Q(Add_Subt_result[49]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_36_ ( .D(n1539), .CK(clk),
.RN(n3483), .Q(Add_Subt_result[36]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_31_ ( .D(n1534), .CK(clk),
.RN(n3495), .Q(Add_Subt_result[31]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(n1514), .CK(clk),
.RN(n3496), .Q(Add_Subt_result[11]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_37_ ( .D(n1540), .CK(clk),
.RN(n3484), .Q(Add_Subt_result[37]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n1508), .CK(clk),
.RN(n3496), .Q(Add_Subt_result[5]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(n1522), .CK(clk),
.RN(n3495), .Q(Add_Subt_result[19]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_39_ ( .D(n1542), .CK(clk),
.RN(n3498), .Q(Add_Subt_result[39]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_53_ ( .D(n1556), .CK(clk),
.RN(n3498), .Q(Add_Subt_result[53]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n1435), .CK(clk),
.RN(n3482), .Q(exp_oper_result[3]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n1437), .CK(clk),
.RN(n3505), .Q(exp_oper_result[1]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_34_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .CK(clk), .RN(n3481),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[74]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n1438), .CK(clk),
.RN(n3518), .Q(exp_oper_result[0]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_33_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .CK(clk), .RN(n3481),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[73]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_31_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .CK(clk), .RN(n3481),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[71]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_35_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .CK(clk), .RN(n3481),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[75]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n1434), .CK(clk),
.RN(n3506), .Q(exp_oper_result[4]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n1433), .CK(clk),
.RN(n3504), .Q(exp_oper_result[5]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n1436), .CK(clk),
.RN(n3505), .Q(exp_oper_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1444), .CK(clk),
.RN(n1611), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1445), .CK(clk),
.RN(n3513), .Q(Sgf_normalized_result[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1446), .CK(clk),
.RN(n3499), .Q(Sgf_normalized_result[4]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1447), .CK(clk),
.RN(n3483), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1448), .CK(clk),
.RN(n3501), .Q(Sgf_normalized_result[6]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1449), .CK(clk),
.RN(n3494), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1455), .CK(clk),
.RN(n3510), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1454), .CK(clk),
.RN(n1610), .Q(Sgf_normalized_result[12]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_9_ ( .D(n1429), .CK(clk),
.RN(n3517), .Q(exp_oper_result[9]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_8_ ( .D(n1430), .CK(clk),
.RN(n3506), .Q(exp_oper_result[8]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n1431), .CK(clk),
.RN(n3517), .Q(exp_oper_result[7]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n1432), .CK(clk),
.RN(n3506), .Q(exp_oper_result[6]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_10_ ( .D(n1428), .CK(clk),
.RN(n3507), .Q(exp_oper_result[10]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(n1497), .CK(
clk), .RN(n3504), .Q(LZA_output[4]) );
DFFRX1TS XRegister_Q_reg_43_ ( .D(n1340), .CK(clk), .RN(n3487), .Q(intDX[43]), .QN(n1590) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_44_ ( .D(n1547), .CK(clk),
.RN(n3498), .Q(Add_Subt_result[44]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n1175), .CK(clk), .RN(
n3515), .Q(DMP[6]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n1176), .CK(clk), .RN(
n3515), .Q(DMP[7]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n1181), .CK(clk),
.RN(n3495), .Q(DMP[12]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n1185), .CK(clk),
.RN(n3499), .Q(DMP[16]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n1186), .CK(clk),
.RN(n3515), .Q(DMP[17]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n1189), .CK(clk),
.RN(n3500), .Q(DMP[20]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n3484),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[64]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n3497),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[65]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n3483),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[66]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n3484),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[67]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n3497),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[68]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n3483),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[69]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n1122), .CK(clk),
.RN(n3493), .Q(DmP[17]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n1125), .CK(clk),
.RN(n3493), .Q(DmP[20]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n1127), .CK(clk),
.RN(n3493), .Q(DmP[22]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n1129), .CK(clk),
.RN(n3492), .Q(DmP[24]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_32_ ( .D(n1137), .CK(clk),
.RN(n3492), .Q(DmP[32]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_34_ ( .D(n1139), .CK(clk),
.RN(n1610), .Q(DmP[34]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_36_ ( .D(n1141), .CK(clk),
.RN(n3509), .Q(DmP[36]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_37_ ( .D(n1142), .CK(clk),
.RN(n3516), .Q(DmP[37]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_38_ ( .D(n1143), .CK(clk),
.RN(n3509), .Q(DmP[38]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_42_ ( .D(n1147), .CK(clk),
.RN(n3487), .Q(DmP[42]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_44_ ( .D(n1149), .CK(clk),
.RN(n3488), .Q(DmP[44]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_37_ ( .D(n1206), .CK(clk),
.RN(n3498), .Q(DMP[37]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_38_ ( .D(n1207), .CK(clk),
.RN(n3481), .Q(DMP[38]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n1105), .CK(clk), .RN(
n3500), .Q(DmP[0]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n1106), .CK(clk), .RN(
n3515), .Q(DmP[1]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n1109), .CK(clk), .RN(
n1611), .Q(DmP[4]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n1110), .CK(clk), .RN(
n3488), .Q(DmP[5]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n1111), .CK(clk), .RN(
n3494), .Q(DmP[6]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n1117), .CK(clk),
.RN(n3493), .Q(DmP[12]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n1119), .CK(clk),
.RN(n3485), .Q(DmP[14]) );
DFFRX2TS YRegister_Q_reg_36_ ( .D(n1268), .CK(clk), .RN(n3490), .Q(intDY[36]) );
DFFRX2TS YRegister_Q_reg_57_ ( .D(n1289), .CK(clk), .RN(n3519), .Q(intDY[57]) );
DFFRX2TS YRegister_Q_reg_25_ ( .D(n1257), .CK(clk), .RN(n3514), .Q(intDY[25]) );
DFFRX2TS YRegister_Q_reg_45_ ( .D(n1277), .CK(clk), .RN(n3489), .Q(intDY[45]) );
DFFRX2TS YRegister_Q_reg_17_ ( .D(n1249), .CK(clk), .RN(n3514), .Q(intDY[17]) );
DFFRX2TS YRegister_Q_reg_56_ ( .D(n1288), .CK(clk), .RN(n3511), .Q(intDY[56]) );
DFFRX2TS YRegister_Q_reg_24_ ( .D(n1256), .CK(clk), .RN(n3511), .Q(intDY[24]) );
DFFRX2TS YRegister_Q_reg_54_ ( .D(n1286), .CK(clk), .RN(n3489), .Q(intDY[54]) );
DFFRX2TS YRegister_Q_reg_12_ ( .D(n1244), .CK(clk), .RN(n3514), .Q(intDY[12]) );
DFFRX2TS YRegister_Q_reg_50_ ( .D(n1282), .CK(clk), .RN(n3489), .Q(intDY[50]) );
DFFRX2TS YRegister_Q_reg_20_ ( .D(n1252), .CK(clk), .RN(n3514), .Q(intDY[20]) );
DFFRX2TS YRegister_Q_reg_42_ ( .D(n1274), .CK(clk), .RN(n3490), .Q(intDY[42]) );
DFFRX2TS YRegister_Q_reg_34_ ( .D(n1266), .CK(clk), .RN(n3490), .Q(intDY[34]) );
DFFRX2TS YRegister_Q_reg_27_ ( .D(n1259), .CK(clk), .RN(n3510), .Q(intDY[27]) );
DFFRX2TS YRegister_Q_reg_39_ ( .D(n1271), .CK(clk), .RN(n3490), .Q(intDY[39]) );
DFFRX2TS YRegister_Q_reg_30_ ( .D(n1262), .CK(clk), .RN(n3510), .Q(intDY[30]) );
DFFRX2TS YRegister_Q_reg_22_ ( .D(n1254), .CK(clk), .RN(n3490), .Q(intDY[22]) );
DFFRX2TS YRegister_Q_reg_14_ ( .D(n1246), .CK(clk), .RN(n3514), .Q(intDY[14]) );
DFFRX2TS YRegister_Q_reg_59_ ( .D(n1291), .CK(clk), .RN(n3511), .Q(intDY[59]) );
DFFRX2TS YRegister_Q_reg_32_ ( .D(n1264), .CK(clk), .RN(n3513), .Q(intDY[32]) );
DFFRX2TS YRegister_Q_reg_0_ ( .D(n1232), .CK(clk), .RN(n3491), .Q(intDY[0])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_27_ ( .D(n1530), .CK(clk),
.RN(n3494), .Q(Add_Subt_result[27]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_51_ ( .D(n1554), .CK(clk),
.RN(n3512), .Q(Add_Subt_result[51]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_37_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .CK(clk), .RN(n3481),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[77]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_36_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .CK(clk), .RN(n3481),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[76]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_39_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .CK(clk), .RN(n3481),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[79]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_32_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .CK(clk), .RN(n3481),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[72]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_38_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .CK(clk), .RN(n3481),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[78]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_45_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .CK(clk), .RN(n3497),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[85]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_44_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .CK(clk), .RN(n3516),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[84]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_43_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .CK(clk), .RN(n3508),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[83]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_46_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .CK(clk), .RN(n3508),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[86]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_40_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .CK(clk), .RN(n3485),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[80]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1456), .CK(clk),
.RN(n3495), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1458), .CK(clk),
.RN(n1612), .Q(Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_42_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .CK(clk), .RN(n3516),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[82]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_41_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .CK(clk), .RN(n3516),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[81]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_54_ ( .D(n1563), .CK(clk),
.RN(n3502), .Q(Sgf_normalized_result[54]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n1472), .CK(clk),
.RN(n3500), .Q(Sgf_normalized_result[30]), .QN(n3370) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n1467), .CK(clk),
.RN(n3515), .Q(Sgf_normalized_result[25]), .QN(n3325) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n1471), .CK(clk),
.RN(n3499), .Q(Sgf_normalized_result[29]), .QN(n3369) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n1468), .CK(clk),
.RN(n1611), .Q(Sgf_normalized_result[26]), .QN(n3326) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n1470), .CK(clk),
.RN(n1612), .Q(Sgf_normalized_result[28]), .QN(n3368) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n1469), .CK(clk),
.RN(n3500), .Q(Sgf_normalized_result[27]), .QN(n3365) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n1196), .CK(clk),
.RN(n3515), .Q(DMP[27]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n1195), .CK(clk),
.RN(n3499), .Q(DMP[26]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n1194), .CK(clk),
.RN(n1611), .Q(DMP[25]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n1193), .CK(clk),
.RN(n1612), .Q(DMP[24]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n1192), .CK(clk),
.RN(n3500), .Q(DMP[23]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n1191), .CK(clk),
.RN(n3515), .Q(DMP[22]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n1473), .CK(clk),
.RN(n3501), .Q(Sgf_normalized_result[31]), .QN(n3371) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n1474), .CK(clk),
.RN(n3501), .Q(Sgf_normalized_result[32]), .QN(n3381) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n1476), .CK(clk),
.RN(n3501), .Q(Sgf_normalized_result[34]), .QN(n3383) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n1478), .CK(clk),
.RN(n3501), .Q(Sgf_normalized_result[36]), .QN(n3394) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_33_ ( .D(n1202), .CK(clk),
.RN(n3501), .Q(DMP[33]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_32_ ( .D(n1201), .CK(clk),
.RN(n3501), .Q(DMP[32]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_31_ ( .D(n1200), .CK(clk),
.RN(n3501), .Q(DMP[31]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n1199), .CK(clk),
.RN(n3486), .Q(DMP[30]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n1198), .CK(clk),
.RN(n1610), .Q(DMP[29]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n1197), .CK(clk),
.RN(n3485), .Q(DMP[28]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n1171), .CK(clk), .RN(
n3515), .Q(DMP[2]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n1170), .CK(clk), .RN(
n3500), .Q(DMP[1]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n1169), .CK(clk), .RN(
n3499), .Q(DMP[0]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n1479), .CK(clk),
.RN(n3520), .Q(Sgf_normalized_result[37]), .QN(n3395) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_39_ ( .D(n1208), .CK(clk),
.RN(n3502), .Q(DMP[39]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_36_ ( .D(n1205), .CK(clk),
.RN(n3519), .Q(DMP[36]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_35_ ( .D(n1204), .CK(clk),
.RN(n3498), .Q(DMP[35]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_34_ ( .D(n1203), .CK(clk),
.RN(n3519), .Q(DMP[34]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n1182), .CK(clk),
.RN(n3516), .Q(DMP[13]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n1180), .CK(clk),
.RN(n3516), .Q(DMP[11]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n1179), .CK(clk),
.RN(n3495), .Q(DMP[10]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_51_ ( .D(n1220), .CK(clk),
.RN(n3503), .Q(DMP[51]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_50_ ( .D(n1219), .CK(clk),
.RN(n3503), .Q(DMP[50]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_49_ ( .D(n1218), .CK(clk),
.RN(n3503), .Q(DMP[49]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_47_ ( .D(n1216), .CK(clk),
.RN(n3503), .Q(DMP[47]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_46_ ( .D(n1215), .CK(clk),
.RN(n3503), .Q(DMP[46]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n1118), .CK(clk),
.RN(n3493), .Q(DmP[13]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n1120), .CK(clk),
.RN(n3493), .Q(DmP[15]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n1121), .CK(clk),
.RN(n3493), .Q(DmP[16]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n1123), .CK(clk),
.RN(n3493), .Q(DmP[18]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n1124), .CK(clk),
.RN(n3493), .Q(DmP[19]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n1126), .CK(clk),
.RN(n3493), .Q(DmP[21]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n1128), .CK(clk),
.RN(n3493), .Q(DmP[23]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n1131), .CK(clk),
.RN(n3492), .Q(DmP[26]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n1132), .CK(clk),
.RN(n3492), .Q(DmP[27]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n1133), .CK(clk),
.RN(n3492), .Q(DmP[28]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n1134), .CK(clk),
.RN(n3492), .Q(DmP[29]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n1135), .CK(clk),
.RN(n3492), .Q(DmP[30]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_31_ ( .D(n1136), .CK(clk),
.RN(n3492), .Q(DmP[31]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_33_ ( .D(n1138), .CK(clk),
.RN(n3492), .Q(DmP[33]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_35_ ( .D(n1140), .CK(clk),
.RN(n3492), .Q(DmP[35]) );
DFFRX1TS XRegister_Q_reg_62_ ( .D(n1359), .CK(clk), .RN(n3491), .Q(intDX[62]), .QN(n3431) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n1188), .CK(clk),
.RN(n3500), .Q(DMP[19]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n1187), .CK(clk),
.RN(n3515), .Q(DMP[18]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n1184), .CK(clk),
.RN(n3516), .Q(DMP[15]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n1178), .CK(clk), .RN(
n3501), .Q(DMP[9]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n1177), .CK(clk), .RN(
n1611), .Q(DMP[8]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n1174), .CK(clk), .RN(
n3500), .Q(DMP[5]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n1173), .CK(clk), .RN(
n3505), .Q(DMP[4]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n3483),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[70]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n3484),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[63]) );
DFFRX1TS XRegister_Q_reg_16_ ( .D(n1313), .CK(clk), .RN(n3521), .Q(intDX[16]), .QN(n3391) );
DFFRX1TS XRegister_Q_reg_10_ ( .D(n1307), .CK(clk), .RN(n3521), .Q(intDX[10]), .QN(n3330) );
DFFRX1TS XRegister_Q_reg_9_ ( .D(n1306), .CK(clk), .RN(n3521), .Q(intDX[9]),
.QN(n3400) );
DFFRX1TS XRegister_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n3521), .Q(intDX[7]),
.QN(n3390) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_47_ ( .D(n1152), .CK(clk),
.RN(n3508), .Q(DmP[47]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_46_ ( .D(n1151), .CK(clk),
.RN(n3508), .Q(DmP[46]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_45_ ( .D(n1150), .CK(clk),
.RN(n3486), .Q(DmP[45]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_43_ ( .D(n1148), .CK(clk),
.RN(n3506), .Q(DmP[43]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_41_ ( .D(n1146), .CK(clk),
.RN(n3518), .Q(DmP[41]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_40_ ( .D(n1145), .CK(clk),
.RN(n3506), .Q(DmP[40]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_39_ ( .D(n1144), .CK(clk),
.RN(n3516), .Q(DmP[39]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_61_ ( .D(n1230), .CK(clk),
.RN(n3517), .Q(DMP[61]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_60_ ( .D(n1229), .CK(clk),
.RN(n3506), .Q(DMP[60]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_59_ ( .D(n1228), .CK(clk),
.RN(n3517), .Q(DMP[59]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_58_ ( .D(n1227), .CK(clk),
.RN(n3506), .Q(DMP[58]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_57_ ( .D(n1226), .CK(clk),
.RN(n3517), .Q(DMP[57]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_56_ ( .D(n1225), .CK(clk),
.RN(n3506), .Q(DMP[56]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_54_ ( .D(n1223), .CK(clk),
.RN(n3518), .Q(DMP[54]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_53_ ( .D(n1222), .CK(clk),
.RN(n3505), .Q(DMP[53]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_52_ ( .D(n1221), .CK(clk),
.RN(n3482), .Q(DMP[52]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_45_ ( .D(n1214), .CK(clk),
.RN(n3502), .Q(DMP[45]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_43_ ( .D(n1212), .CK(clk),
.RN(n3502), .Q(DMP[43]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_41_ ( .D(n1210), .CK(clk),
.RN(n3502), .Q(DMP[41]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_40_ ( .D(n1209), .CK(clk),
.RN(n3502), .Q(DMP[40]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n1190), .CK(clk),
.RN(n1612), .Q(DMP[21]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n1116), .CK(clk),
.RN(n3517), .Q(DmP[11]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n1115), .CK(clk),
.RN(n3512), .Q(DmP[10]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n1114), .CK(clk), .RN(
n3482), .Q(DmP[9]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n1113), .CK(clk), .RN(
n3510), .Q(DmP[8]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n1112), .CK(clk), .RN(
n3508), .Q(DmP[7]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n1107), .CK(clk), .RN(
n3508), .Q(DmP[2]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n1507), .CK(clk),
.RN(n3496), .Q(Add_Subt_result[4]), .QN(n3458) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n1557), .CK(clk), .RN(n1360), .Q(FSM_selector_C), .QN(n3367) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_34_ ( .D(n1537), .CK(clk),
.RN(n3483), .Q(Add_Subt_result[34]), .QN(n3351) );
DFFRX1TS YRegister_Q_reg_63_ ( .D(n1231), .CK(clk), .RN(n3508), .Q(intDY[63]) );
DFFRX1TS ASRegister_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n3508), .Q(intAS) );
DFFRX1TS Sel_B_Q_reg_1_ ( .D(n1439), .CK(clk), .RN(n1360), .Q(
FSM_selector_B[1]), .QN(n3473) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n1505), .CK(clk),
.RN(n3496), .Q(Add_Subt_result[2]), .QN(n3464) );
DFFRX1TS XRegister_Q_reg_63_ ( .D(n1296), .CK(clk), .RN(n3507), .Q(intDX[63]), .QN(n3353) );
DFFRX1TS XRegister_Q_reg_5_ ( .D(n1302), .CK(clk), .RN(n3507), .Q(intDX[5]),
.QN(n3329) );
DFFRX1TS XRegister_Q_reg_4_ ( .D(n1301), .CK(clk), .RN(n3507), .Q(intDX[4]),
.QN(n3392) );
DFFRX1TS XRegister_Q_reg_2_ ( .D(n1299), .CK(clk), .RN(n3507), .Q(intDX[2]),
.QN(n3337) );
DFFRX1TS XRegister_Q_reg_1_ ( .D(n1298), .CK(clk), .RN(n3507), .Q(intDX[1]),
.QN(n3399) );
DFFRX1TS XRegister_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n3507), .Q(intDX[0]),
.QN(n3405) );
DFFRX1TS XRegister_Q_reg_56_ ( .D(n1353), .CK(clk), .RN(n3512), .Q(intDX[56]), .QN(n3385) );
DFFRX1TS XRegister_Q_reg_47_ ( .D(n1344), .CK(clk), .RN(n3512), .Q(intDX[47]), .QN(n3341) );
DFFRX1TS XRegister_Q_reg_40_ ( .D(n1337), .CK(clk), .RN(n3488), .Q(intDX[40]), .QN(n3428) );
DFFRX1TS XRegister_Q_reg_39_ ( .D(n1336), .CK(clk), .RN(n3512), .Q(intDX[39]), .QN(n3342) );
DFFRX1TS XRegister_Q_reg_32_ ( .D(n1329), .CK(clk), .RN(n3499), .Q(intDX[32]), .QN(n3387) );
DFFRX1TS XRegister_Q_reg_61_ ( .D(n1358), .CK(clk), .RN(n3509), .Q(intDX[61]), .QN(n3335) );
DFFRX1TS XRegister_Q_reg_52_ ( .D(n1349), .CK(clk), .RN(n3487), .Q(intDX[52]), .QN(n3386) );
DFFRX1TS XRegister_Q_reg_48_ ( .D(n1345), .CK(clk), .RN(n3488), .Q(intDX[48]), .QN(n3424) );
DFFRX1TS XRegister_Q_reg_44_ ( .D(n1341), .CK(clk), .RN(n3488), .Q(intDX[44]), .QN(n3426) );
DFFRX1TS XRegister_Q_reg_38_ ( .D(n1335), .CK(clk), .RN(n3487), .Q(intDX[38]), .QN(n3429) );
DFFRX1TS XRegister_Q_reg_37_ ( .D(n1334), .CK(clk), .RN(n3487), .Q(intDX[37]), .QN(n3343) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n1506), .CK(clk),
.RN(n3496), .Q(Add_Subt_result[3]), .QN(n3459) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n1509), .CK(clk),
.RN(n3496), .Q(Add_Subt_result[6]), .QN(n3452) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n1512), .CK(clk),
.RN(n3496), .Q(Add_Subt_result[9]), .QN(n3439) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n1518), .CK(clk),
.RN(n3495), .Q(Add_Subt_result[15]), .QN(n3451) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n1513), .CK(clk),
.RN(n3496), .Q(Add_Subt_result[10]), .QN(n3450) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(n1519), .CK(clk),
.RN(n3495), .Q(Add_Subt_result[16]), .QN(n3319) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(n1521), .CK(clk),
.RN(n3495), .Q(Add_Subt_result[18]), .QN(n3448) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(n1523), .CK(clk),
.RN(n3495), .Q(Add_Subt_result[20]), .QN(n3440) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n1466), .CK(clk),
.RN(n1612), .Q(Sgf_normalized_result[24]), .QN(n3324) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1464), .CK(clk),
.RN(n1611), .Q(Sgf_normalized_result[22]), .QN(n3357) );
DFFRX1TS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n1167), .CK(clk),
.RN(n3507), .Q(sign_final_result), .QN(n3471) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1465), .CK(clk),
.RN(n3499), .Q(Sgf_normalized_result[23]), .QN(n3323) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1450), .CK(clk),
.RN(n3504), .Q(Sgf_normalized_result[8]), .QN(n3358) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_54_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[54]), .CK(clk), .RN(n3486),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[94]), .QN(n3465) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_49_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .CK(clk), .RN(n3497),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[89]), .QN(n3523) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_51_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .CK(clk), .RN(n3483),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[91]), .QN(n3526) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_48_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .CK(clk), .RN(n3484),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[88]), .QN(n3522) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_50_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .CK(clk), .RN(n3497),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[90]), .QN(n3524) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_52_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[52]), .CK(clk), .RN(n3483),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[92]), .QN(n3525) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_53_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[53]), .CK(clk), .RN(n3484),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[93]), .QN(n3466) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_30_ ( .D(n1533), .CK(clk),
.RN(n3494), .Q(Add_Subt_result[30]), .QN(n3352) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_38_ ( .D(n1541), .CK(clk),
.RN(n3484), .Q(Add_Subt_result[38]), .QN(n3467) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_41_ ( .D(n1544), .CK(clk),
.RN(n3497), .Q(Add_Subt_result[41]), .QN(n3349) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(n1499), .CK(
clk), .RN(n3516), .Q(LZA_output[0]), .QN(n3474) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_54_ ( .D(n1502), .CK(clk),
.RN(n3498), .Q(Add_Subt_result[54]), .QN(n3345) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n1489), .CK(clk),
.RN(n3502), .Q(Sgf_normalized_result[47]), .QN(n3453) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n1183), .CK(clk),
.RN(n3511), .Q(DMP[14]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n1172), .CK(clk), .RN(
n3484), .Q(DMP[3]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_48_ ( .D(n1217), .CK(clk),
.RN(n3503), .Q(DMP[48]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_55_ ( .D(n1224), .CK(clk),
.RN(n3517), .Q(DMP[55]) );
DFFRX4TS Sel_D_Q_reg_0_ ( .D(n1441), .CK(clk), .RN(n1360), .Q(n1583), .QN(
n3475) );
NAND2X2TS U1759 ( .A(n2063), .B(n2671), .Y(n1900) );
NAND2X1TS U1760 ( .A(n2607), .B(n3464), .Y(n2580) );
OR3X4TS U1761 ( .A(n1875), .B(n1874), .C(n2019), .Y(n2669) );
NOR2X1TS U1762 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[2]), .Y(
n1794) );
OAI2BB2XLTS U1763 ( .B0(n2150), .B1(n2149), .A0N(n2148), .A1N(n2147), .Y(
n2206) );
OAI221XLTS U1764 ( .A0(n2204), .A1(n2203), .B0(n2202), .B1(n2201), .C0(n2200), .Y(n2205) );
CLKINVX6TS U1765 ( .A(n1808), .Y(n1821) );
BUFX4TS U1766 ( .A(n1687), .Y(n1676) );
NAND2X1TS U1767 ( .A(n3280), .B(n3349), .Y(n2653) );
NAND2BX1TS U1768 ( .AN(n2639), .B(n2640), .Y(n2631) );
INVX4TS U1769 ( .A(n3475), .Y(n1607) );
INVX6TS U1770 ( .A(n1671), .Y(n1748) );
CLKBUFX2TS U1771 ( .A(n3475), .Y(n1671) );
INVX2TS U1772 ( .A(n2598), .Y(n2599) );
OAI21XLTS U1773 ( .A0(n2823), .A1(n2820), .B0(n2824), .Y(n1705) );
NOR2XLTS U1774 ( .A(n1753), .B(n3323), .Y(n1751) );
OAI21XLTS U1775 ( .A0(n2163), .A1(n2162), .B0(n2161), .Y(n2165) );
INVX2TS U1776 ( .A(n2573), .Y(n2579) );
INVX2TS U1777 ( .A(n2776), .Y(n2779) );
OR2X1TS U1778 ( .A(n2610), .B(Add_Subt_result[36]), .Y(n3283) );
NOR2XLTS U1779 ( .A(n3461), .B(n1607), .Y(n1650) );
BUFX4TS U1780 ( .A(n1680), .Y(n1687) );
NOR2X2TS U1781 ( .A(n3283), .B(Add_Subt_result[35]), .Y(n2782) );
OAI21XLTS U1782 ( .A0(n2860), .A1(n2834), .B0(n2833), .Y(n2839) );
AFHCINX2TS U1783 ( .CIN(n2683), .B(n2684), .A(n2685), .S(n2686), .CO(n2550)
);
AOI31XLTS U1784 ( .A0(n2785), .A1(n2784), .A2(n2783), .B0(n3288), .Y(n2786)
);
OAI211XLTS U1785 ( .A0(n3012), .A1(n3000), .B0(n1923), .C0(n1922), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[53]) );
OAI21XLTS U1786 ( .A0(n3390), .A1(n2382), .B0(n2359), .Y(n1112) );
OAI21XLTS U1787 ( .A0(n2442), .A1(n3385), .B0(n2424), .Y(n1225) );
OAI21XLTS U1788 ( .A0(n2458), .A1(n3392), .B0(n2452), .Y(n1173) );
OAI21XLTS U1789 ( .A0(n3332), .A1(n2376), .B0(n2370), .Y(n1135) );
OAI21XLTS U1790 ( .A0(n2439), .A1(n3409), .B0(n2410), .Y(n1218) );
OAI21XLTS U1791 ( .A0(n2442), .A1(n3418), .B0(n2400), .Y(n1197) );
OAI21XLTS U1792 ( .A0(n2442), .A1(n3419), .B0(n2406), .Y(n1196) );
OAI211XLTS U1793 ( .A0(n3036), .A1(n3095), .B0(n1831), .C0(n1830), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[44]) );
OAI21XLTS U1794 ( .A0(n3404), .A1(n2398), .B0(n2318), .Y(n1119) );
OAI21XLTS U1795 ( .A0(n3387), .A1(n2376), .B0(n2373), .Y(n1137) );
OAI21XLTS U1796 ( .A0(n2458), .A1(n3404), .B0(n2446), .Y(n1183) );
NAND2X1TS U1797 ( .A(n2665), .B(n3475), .Y(n1441) );
OAI21XLTS U1798 ( .A0(n2298), .A1(n1872), .B0(n2275), .Y(n1463) );
OAI21XLTS U1799 ( .A0(n3385), .A1(n2367), .B0(n2325), .Y(n1161) );
OAI211XLTS U1800 ( .A0(n3111), .A1(n1931), .B0(n1930), .C0(n1929), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
INVX2TS U1801 ( .A(n3475), .Y(n1752) );
NOR2X2TS U1802 ( .A(n3469), .B(n2580), .Y(n2606) );
CLKMX2X2TS U1803 ( .A(n2731), .B(Add_Subt_result[41]), .S0(n2791), .Y(n1544)
);
CLKMX2X2TS U1804 ( .A(n2702), .B(Add_Subt_result[40]), .S0(n2989), .Y(n1543)
);
NOR2X4TS U1805 ( .A(Add_Subt_result[13]), .B(n2584), .Y(n2773) );
CLKINVX2TS U1806 ( .A(n2584), .Y(n2768) );
CLKMX2X2TS U1807 ( .A(n2698), .B(Add_Subt_result[39]), .S0(n2984), .Y(n1542)
);
CLKMX2X2TS U1808 ( .A(n2735), .B(Add_Subt_result[38]), .S0(n2791), .Y(n1541)
);
CLKMX2X2TS U1809 ( .A(n2739), .B(Add_Subt_result[37]), .S0(n2710), .Y(n1540)
);
NOR2X4TS U1810 ( .A(Add_Subt_result[15]), .B(n2574), .Y(n2774) );
CLKMX2X2TS U1811 ( .A(n2743), .B(Add_Subt_result[36]), .S0(n2984), .Y(n1539)
);
NOR2BX4TS U1812 ( .AN(n2572), .B(Add_Subt_result[17]), .Y(n2660) );
CLKINVX1TS U1813 ( .A(n2602), .Y(n2775) );
AO22X1TS U1814 ( .A0(n2597), .A1(Add_Subt_result[22]), .B0(n2596), .B1(
Add_Subt_result[30]), .Y(n2642) );
CLKMX2X2TS U1815 ( .A(Exp_Operation_Module_Data_S[10]), .B(
exp_oper_result[10]), .S0(n2664), .Y(n1428) );
NAND4BX1TS U1816 ( .AN(n2465), .B(Exp_Operation_Module_Data_S[9]), .C(
Exp_Operation_Module_Data_S[8]), .D(Exp_Operation_Module_Data_S[7]),
.Y(n2467) );
CLKMX2X2TS U1817 ( .A(Exp_Operation_Module_Data_S[9]), .B(exp_oper_result[9]), .S0(n2664), .Y(n1429) );
NOR2X4TS U1818 ( .A(Add_Subt_result[26]), .B(n2638), .Y(n2625) );
CLKMX2X2TS U1819 ( .A(Exp_Operation_Module_Data_S[8]), .B(exp_oper_result[8]), .S0(n2664), .Y(n1430) );
OAI21X1TS U1820 ( .A0(n3436), .A1(n2367), .B0(n2324), .Y(n1164) );
OAI21X1TS U1821 ( .A0(n3527), .A1(n2367), .B0(n2326), .Y(n1165) );
OAI21X1TS U1822 ( .A0(n3431), .A1(n2382), .B0(n2358), .Y(n1104) );
OAI21X1TS U1823 ( .A0(n3340), .A1(n2398), .B0(n2352), .Y(n1140) );
OAI21X1TS U1824 ( .A0(n3424), .A1(n2444), .B0(n2333), .Y(n1153) );
OAI21X1TS U1825 ( .A0(n3339), .A1(n2376), .B0(n2372), .Y(n1131) );
OAI21X1TS U1826 ( .A0(n3386), .A1(n2382), .B0(n2322), .Y(n1157) );
OAI21X1TS U1827 ( .A0(n3397), .A1(n2382), .B0(n2331), .Y(n1158) );
OAI21X1TS U1828 ( .A0(n3334), .A1(n2382), .B0(n2362), .Y(n1159) );
OAI21X1TS U1829 ( .A0(n3480), .A1(n2367), .B0(n2330), .Y(n1160) );
OAI21X1TS U1830 ( .A0(n3420), .A1(n2367), .B0(n2366), .Y(n1162) );
OAI21X1TS U1831 ( .A0(n2442), .A1(n3430), .B0(n2402), .Y(n1203) );
OAI21X1TS U1832 ( .A0(n2442), .A1(n3423), .B0(n2412), .Y(n1205) );
OAI21X1TS U1833 ( .A0(n2442), .A1(n3386), .B0(n2423), .Y(n1221) );
OAI21X1TS U1834 ( .A0(n2435), .A1(n3343), .B0(n2431), .Y(n1206) );
OAI21X1TS U1835 ( .A0(n2442), .A1(n3340), .B0(n2414), .Y(n1204) );
OAI21X1TS U1836 ( .A0(n2278), .A1(n1872), .B0(n2267), .Y(n1458) );
OAI21X1TS U1837 ( .A0(n2435), .A1(n3334), .B0(n2409), .Y(n1223) );
OAI21X1TS U1838 ( .A0(n2435), .A1(n3397), .B0(n2417), .Y(n1222) );
OAI21X1TS U1839 ( .A0(n2442), .A1(n3480), .B0(n2422), .Y(n1224) );
OAI21X1TS U1840 ( .A0(n3011), .A1(n2998), .B0(n1849), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[50]) );
OAI21X1TS U1841 ( .A0(n2435), .A1(n3420), .B0(n2413), .Y(n1226) );
OAI21X1TS U1842 ( .A0(n2442), .A1(n3477), .B0(n2434), .Y(n1227) );
OAI21X1TS U1843 ( .A0(n3012), .A1(n2996), .B0(n1853), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[52]) );
OAI21X1TS U1844 ( .A0(n2435), .A1(n3436), .B0(n2405), .Y(n1228) );
OAI21X1TS U1845 ( .A0(n2435), .A1(n3527), .B0(n2408), .Y(n1229) );
OAI21X1TS U1846 ( .A0(n2442), .A1(n3335), .B0(n2421), .Y(n1230) );
OAI21X1TS U1847 ( .A0(n2435), .A1(n3437), .B0(n2404), .Y(n1220) );
OAI21X1TS U1848 ( .A0(n2435), .A1(n3429), .B0(n2425), .Y(n1207) );
OAI21X1TS U1849 ( .A0(n2442), .A1(n3476), .B0(n2420), .Y(n1200) );
OAI21X1TS U1850 ( .A0(n2442), .A1(n3332), .B0(n2399), .Y(n1199) );
OAI21X1TS U1851 ( .A0(n2041), .A1(n1872), .B0(n1891), .Y(n1460) );
OAI21X1TS U1852 ( .A0(n2442), .A1(n3407), .B0(n2441), .Y(n1198) );
OAI21X1TS U1853 ( .A0(n2263), .A1(n1872), .B0(n2064), .Y(n1461) );
OAI21X1TS U1854 ( .A0(n2442), .A1(n3387), .B0(n2419), .Y(n1201) );
OAI21X1TS U1855 ( .A0(n2051), .A1(n1872), .B0(n1886), .Y(n1459) );
OAI21X1TS U1856 ( .A0(n2442), .A1(n3421), .B0(n2418), .Y(n1202) );
OAI21X1TS U1857 ( .A0(n2215), .A1(n1872), .B0(n1880), .Y(n1462) );
OAI21X1TS U1858 ( .A0(n2307), .A1(n1872), .B0(n2286), .Y(n1464) );
OAI21X1TS U1859 ( .A0(n3032), .A1(n3095), .B0(n1836), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[45]) );
OAI211X1TS U1860 ( .A0(n3111), .A1(n3089), .B0(n2017), .C0(n2016), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
OAI21X1TS U1861 ( .A0(n2822), .A1(n2821), .B0(n2820), .Y(n2827) );
OAI211X1TS U1862 ( .A0(n3111), .A1(n3078), .B0(n1919), .C0(n1918), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[26]) );
OAI211X1TS U1863 ( .A0(n3111), .A1(n3084), .B0(n1934), .C0(n1933), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
OAI211X1TS U1864 ( .A0(n2999), .A1(n2996), .B0(n1857), .C0(n1856), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[49]) );
AND2X2TS U1865 ( .A(n1843), .B(n1842), .Y(n3014) );
AOI211X4TS U1866 ( .A0(n2208), .A1(n2207), .B0(n2206), .C0(n2205), .Y(n2312)
);
NOR2X1TS U1867 ( .A(n2794), .B(n2793), .Y(n2799) );
INVX4TS U1868 ( .A(n2992), .Y(n3010) );
OAI21X1TS U1869 ( .A0(n2944), .A1(n2941), .B0(n2945), .Y(n1775) );
INVX4TS U1870 ( .A(n1885), .Y(n2063) );
INVX4TS U1871 ( .A(n3004), .Y(n3013) );
INVX4TS U1872 ( .A(n3000), .Y(n2014) );
OAI21X1TS U1873 ( .A0(n2886), .A1(n2882), .B0(n2887), .Y(n1735) );
INVX1TS U1874 ( .A(n2394), .Y(n2389) );
INVX4TS U1875 ( .A(n3267), .Y(n2664) );
NOR3X4TS U1876 ( .A(n2631), .B(Add_Subt_result[43]), .C(Add_Subt_result[42]),
.Y(n3280) );
OR2X2TS U1877 ( .A(n1874), .B(n1869), .Y(n1580) );
CLKMX2X2TS U1878 ( .A(DMP[28]), .B(Sgf_normalized_result[30]), .S0(n1607),
.Y(n2971) );
CLKMX2X2TS U1879 ( .A(DMP[22]), .B(Sgf_normalized_result[24]), .S0(n1607),
.Y(n1781) );
CLKMX2X2TS U1880 ( .A(DMP[32]), .B(Sgf_normalized_result[34]), .S0(n1607),
.Y(n2758) );
CLKMX2X2TS U1881 ( .A(DMP[43]), .B(Sgf_normalized_result[45]), .S0(n1662),
.Y(n2709) );
CLKMX2X2TS U1882 ( .A(DMP[25]), .B(Sgf_normalized_result[27]), .S0(n2592),
.Y(n2988) );
CLKMX2X2TS U1883 ( .A(DMP[26]), .B(Sgf_normalized_result[28]), .S0(n1745),
.Y(n2762) );
CLKMX2X2TS U1884 ( .A(DMP[29]), .B(Sgf_normalized_result[31]), .S0(n1662),
.Y(n2952) );
CLKMX2X2TS U1885 ( .A(DMP[27]), .B(Sgf_normalized_result[29]), .S0(n1756),
.Y(n2975) );
CLKMX2X2TS U1886 ( .A(DMP[41]), .B(Sgf_normalized_result[43]), .S0(n2592),
.Y(n2726) );
CLKMX2X2TS U1887 ( .A(DMP[31]), .B(Sgf_normalized_result[33]), .S0(n1745),
.Y(n2754) );
NOR2X1TS U1888 ( .A(n1753), .B(n3357), .Y(n1750) );
INVX4TS U1889 ( .A(n3290), .Y(n3288) );
NOR2X1TS U1890 ( .A(n1753), .B(n3324), .Y(n1754) );
NOR2X1TS U1891 ( .A(n1748), .B(n3325), .Y(n1679) );
CLKMX2X2TS U1892 ( .A(DMP[23]), .B(Sgf_normalized_result[25]), .S0(n1662),
.Y(n2979) );
CLKMX2X2TS U1893 ( .A(DMP[24]), .B(Sgf_normalized_result[26]), .S0(n2595),
.Y(n2983) );
CLKMX2X2TS U1894 ( .A(DMP[30]), .B(Sgf_normalized_result[32]), .S0(n2592),
.Y(n2750) );
INVX4TS U1895 ( .A(n2008), .Y(n3259) );
NAND4X1TS U1896 ( .A(n1802), .B(n1801), .C(n1800), .D(n1799), .Y(n3255) );
NOR2X1TS U1897 ( .A(n2138), .B(intDX[56]), .Y(n2139) );
NAND2BX1TS U1898 ( .AN(intDY[21]), .B(intDX[21]), .Y(n2083) );
NOR3X1TS U1899 ( .A(Add_Subt_result[45]), .B(Add_Subt_result[46]), .C(
Add_Subt_result[44]), .Y(n2640) );
OAI21X1TS U1900 ( .A0(intDY[55]), .A1(n3480), .B0(intDY[54]), .Y(n2195) );
OR2X2TS U1901 ( .A(FSM_selector_B[1]), .B(FSM_selector_B[0]), .Y(n1817) );
NOR2X1TS U1902 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[1]), .Y(
n1790) );
MX2X2TS U1903 ( .A(n1789), .B(add_overflow_flag), .S0(n2984), .Y(n1562) );
CLKMX2X2TS U1904 ( .A(n2690), .B(Add_Subt_result[54]), .S0(n2710), .Y(n1502)
);
CLKMX2X2TS U1905 ( .A(n2694), .B(Add_Subt_result[53]), .S0(n2710), .Y(n1556)
);
CLKMX2X2TS U1906 ( .A(n2682), .B(Add_Subt_result[52]), .S0(n2989), .Y(n1555)
);
CLKMX2X2TS U1907 ( .A(n2678), .B(Add_Subt_result[51]), .S0(n2989), .Y(n1554)
);
AO21X1TS U1908 ( .A0(n1616), .A1(n3288), .B0(n2663), .Y(n1498) );
CLKMX2X2TS U1909 ( .A(n2557), .B(Add_Subt_result[50]), .S0(n2984), .Y(n1553)
);
AO21X1TS U1910 ( .A0(LZA_output[4]), .A1(n3288), .B0(n2618), .Y(n1497) );
AO21X1TS U1911 ( .A0(LZA_output[5]), .A1(n3288), .B0(n2590), .Y(n1496) );
CLKMX2X2TS U1912 ( .A(n2553), .B(Add_Subt_result[49]), .S0(n2984), .Y(n1552)
);
CLKMX2X2TS U1913 ( .A(n2686), .B(Add_Subt_result[48]), .S0(n2710), .Y(n1551)
);
AO21X1TS U1914 ( .A0(n1617), .A1(n3288), .B0(n2647), .Y(n1500) );
NAND4X1TS U1915 ( .A(n2658), .B(n2657), .C(n2656), .D(n2655), .Y(n2659) );
CLKMX2X2TS U1916 ( .A(n2719), .B(Add_Subt_result[47]), .S0(n2791), .Y(n1550)
);
NOR3X2TS U1917 ( .A(Add_Subt_result[1]), .B(n2580), .C(n3468), .Y(n2615) );
CLKMX2X2TS U1918 ( .A(n2715), .B(Add_Subt_result[46]), .S0(n2791), .Y(n1549)
);
CLKMX2X2TS U1919 ( .A(n2711), .B(Add_Subt_result[45]), .S0(n2989), .Y(n1548)
);
OAI211X1TS U1920 ( .A0(n2627), .A1(n3439), .B0(n2586), .C0(n2585), .Y(n2587)
);
CLKMX2X2TS U1921 ( .A(n2706), .B(Add_Subt_result[44]), .S0(n2710), .Y(n1547)
);
CLKMX2X2TS U1922 ( .A(n2727), .B(Add_Subt_result[43]), .S0(n2791), .Y(n1546)
);
INVX1TS U1923 ( .A(n2582), .Y(n2627) );
CLKMX2X2TS U1924 ( .A(n2723), .B(Add_Subt_result[42]), .S0(n2791), .Y(n1545)
);
NOR2X2TS U1925 ( .A(Add_Subt_result[10]), .B(n2637), .Y(n2582) );
NAND2X2TS U1926 ( .A(n2774), .B(n3322), .Y(n2584) );
NAND2X2TS U1927 ( .A(n2660), .B(n3319), .Y(n2574) );
NOR2X2TS U1928 ( .A(Add_Subt_result[18]), .B(n2581), .Y(n2572) );
NOR3X4TS U1929 ( .A(Add_Subt_result[22]), .B(n1642), .C(n2602), .Y(n2630) );
OAI21X1TS U1930 ( .A0(n2394), .A1(n3346), .B0(n2393), .Y(n1426) );
AFHCONX2TS U1931 ( .A(n2754), .B(n2753), .CI(n2752), .CON(n2756), .S(n2755)
);
NAND2X2TS U1932 ( .A(n2597), .B(n3320), .Y(n2602) );
NAND3BX2TS U1933 ( .AN(Add_Subt_result[27]), .B(n2654), .C(n3350), .Y(n2638)
);
OAI21X1TS U1934 ( .A0(n2943), .A1(n2942), .B0(n2941), .Y(n2948) );
OAI21X1TS U1935 ( .A0(n2491), .A1(n3333), .B0(n2475), .Y(n1191) );
OAI21X1TS U1936 ( .A0(n3402), .A1(n2398), .B0(n2323), .Y(n1116) );
OAI21X1TS U1937 ( .A0(n2491), .A1(n3408), .B0(n2479), .Y(n1190) );
OAI21X1TS U1938 ( .A0(n2491), .A1(n3388), .B0(n2483), .Y(n1193) );
OAI21X1TS U1939 ( .A0(n2439), .A1(n3427), .B0(n2403), .Y(n1211) );
OAI21X1TS U1940 ( .A0(n2458), .A1(n3403), .B0(n2450), .Y(n1172) );
OAI21X1TS U1941 ( .A0(n2491), .A1(n3412), .B0(n2472), .Y(n1194) );
OAI21X1TS U1942 ( .A0(n2439), .A1(n3422), .B0(n2411), .Y(n1210) );
OAI21X1TS U1943 ( .A0(n2439), .A1(n3428), .B0(n2427), .Y(n1209) );
OAI21X1TS U1944 ( .A0(n3335), .A1(n2367), .B0(n2343), .Y(n1166) );
OAI21X1TS U1945 ( .A0(n2439), .A1(n1590), .B0(n2433), .Y(n1212) );
OAI21X1TS U1946 ( .A0(n2491), .A1(n3339), .B0(n2474), .Y(n1195) );
OAI21X1TS U1947 ( .A0(n2491), .A1(n3337), .B0(n2484), .Y(n1171) );
OAI21X1TS U1948 ( .A0(n2439), .A1(n3478), .B0(n2407), .Y(n1214) );
NOR2X4TS U1949 ( .A(Add_Subt_result[29]), .B(n2777), .Y(n2654) );
OAI21X1TS U1950 ( .A0(n2439), .A1(n3426), .B0(n2428), .Y(n1213) );
OAI21X1TS U1951 ( .A0(n2458), .A1(n3399), .B0(n2455), .Y(n1170) );
OAI21X1TS U1952 ( .A0(n2458), .A1(n3401), .B0(n2451), .Y(n1175) );
OAI21X1TS U1953 ( .A0(n2491), .A1(n3396), .B0(n2480), .Y(n1192) );
OAI21X1TS U1954 ( .A0(n2458), .A1(n3390), .B0(n2456), .Y(n1176) );
OAI21X1TS U1955 ( .A0(n3410), .A1(n2367), .B0(n2364), .Y(n1113) );
OAI21X1TS U1956 ( .A0(n2491), .A1(n3405), .B0(n2490), .Y(n1169) );
OAI21X1TS U1957 ( .A0(n2458), .A1(n3393), .B0(n2445), .Y(n1181) );
OAI21X1TS U1958 ( .A0(n3437), .A1(n2382), .B0(n2347), .Y(n1156) );
OAI21X1TS U1959 ( .A0(n3391), .A1(n2398), .B0(n2337), .Y(n1121) );
OAI21X1TS U1960 ( .A0(n2458), .A1(n3330), .B0(n2457), .Y(n1179) );
OAI21X1TS U1961 ( .A0(n2439), .A1(n3342), .B0(n2426), .Y(n1208) );
OAI21X1TS U1962 ( .A0(n2491), .A1(n3391), .B0(n2487), .Y(n1185) );
OAI21X1TS U1963 ( .A0(n3426), .A1(n2444), .B0(n2332), .Y(n1149) );
OAI21X1TS U1964 ( .A0(n2491), .A1(n3411), .B0(n2476), .Y(n1186) );
OAI21X1TS U1965 ( .A0(n3419), .A1(n2376), .B0(n2369), .Y(n1132) );
OAI21X1TS U1966 ( .A0(n2439), .A1(n3341), .B0(n2429), .Y(n1216) );
OAI21X1TS U1967 ( .A0(n3418), .A1(n2376), .B0(n2371), .Y(n1133) );
OAI21X1TS U1968 ( .A0(n3407), .A1(n2376), .B0(n2361), .Y(n1134) );
OAI21X1TS U1969 ( .A0(n3396), .A1(n2382), .B0(n2381), .Y(n1128) );
OAI21X1TS U1970 ( .A0(n3476), .A1(n2376), .B0(n2375), .Y(n1136) );
OAI21X1TS U1971 ( .A0(n3477), .A1(n2367), .B0(n2327), .Y(n1163) );
OAI21X1TS U1972 ( .A0(n3408), .A1(n2382), .B0(n2354), .Y(n1126) );
OAI21X1TS U1973 ( .A0(n3421), .A1(n2376), .B0(n2340), .Y(n1138) );
OAI21X1TS U1974 ( .A0(n3435), .A1(n2398), .B0(n2344), .Y(n1124) );
OAI21X1TS U1975 ( .A0(n3401), .A1(n2398), .B0(n2355), .Y(n1111) );
OAI21X1TS U1976 ( .A0(n3427), .A1(n2444), .B0(n2338), .Y(n1147) );
OAI21X1TS U1977 ( .A0(n3338), .A1(n2398), .B0(n2383), .Y(n1123) );
OAI21X1TS U1978 ( .A0(n3429), .A1(n2367), .B0(n2336), .Y(n1143) );
OAI21X1TS U1979 ( .A0(n2491), .A1(n3435), .B0(n2477), .Y(n1188) );
OAI21X1TS U1980 ( .A0(n3528), .A1(n2398), .B0(n2328), .Y(n1120) );
OAI21X1TS U1981 ( .A0(n3343), .A1(n2398), .B0(n2334), .Y(n1142) );
OAI21X1TS U1982 ( .A0(n2491), .A1(n3338), .B0(n2471), .Y(n1187) );
OAI21X1TS U1983 ( .A0(n3412), .A1(n2382), .B0(n2351), .Y(n1130) );
OAI21X1TS U1984 ( .A0(n2491), .A1(n3528), .B0(n2473), .Y(n1184) );
OAI21X1TS U1985 ( .A0(n3406), .A1(n2382), .B0(n2329), .Y(n1118) );
OAI21X1TS U1986 ( .A0(n3423), .A1(n2398), .B0(n2345), .Y(n1141) );
OAI21X1TS U1987 ( .A0(n2458), .A1(n3400), .B0(n2454), .Y(n1178) );
OAI21X1TS U1988 ( .A0(n2439), .A1(n3425), .B0(n2401), .Y(n1215) );
OAI21X1TS U1989 ( .A0(n3430), .A1(n2376), .B0(n2335), .Y(n1139) );
OAI21X1TS U1990 ( .A0(n2458), .A1(n3410), .B0(n2449), .Y(n1177) );
OAI21X1TS U1991 ( .A0(n2458), .A1(n3329), .B0(n2453), .Y(n1174) );
OAI21X1TS U1992 ( .A0(n2439), .A1(n3424), .B0(n2430), .Y(n1217) );
OAI21X1TS U1993 ( .A0(n3388), .A1(n2382), .B0(n2379), .Y(n1129) );
OAI21X1TS U1994 ( .A0(n3478), .A1(n2444), .B0(n2443), .Y(n1150) );
OAI21X1TS U1995 ( .A0(n1590), .A1(n2444), .B0(n2346), .Y(n1148) );
OAI21X1TS U1996 ( .A0(n2439), .A1(n3479), .B0(n2438), .Y(n1219) );
OAI21X1TS U1997 ( .A0(n3333), .A1(n2382), .B0(n2378), .Y(n1127) );
OAI21X1TS U1998 ( .A0(n3411), .A1(n2398), .B0(n2377), .Y(n1122) );
OAI21X1TS U1999 ( .A0(n3342), .A1(n2367), .B0(n2348), .Y(n1144) );
OAI21X1TS U2000 ( .A0(n2458), .A1(n3406), .B0(n2447), .Y(n1182) );
OAI21X1TS U2001 ( .A0(n3413), .A1(n2398), .B0(n2397), .Y(n1125) );
OAI21X1TS U2002 ( .A0(n3341), .A1(n2444), .B0(n2342), .Y(n1152) );
OAI21X1TS U2003 ( .A0(n3399), .A1(n2376), .B0(n2353), .Y(n1106) );
OAI21X1TS U2004 ( .A0(n3479), .A1(n2382), .B0(n2350), .Y(n1155) );
OAI21X1TS U2005 ( .A0(n3422), .A1(n2444), .B0(n2341), .Y(n1146) );
OAI21X1TS U2006 ( .A0(n2491), .A1(n3413), .B0(n2478), .Y(n1189) );
OAI21X1TS U2007 ( .A0(n3425), .A1(n2444), .B0(n2339), .Y(n1151) );
OAI21X1TS U2008 ( .A0(n2458), .A1(n3402), .B0(n2448), .Y(n1180) );
OAI21X1TS U2009 ( .A0(n2912), .A1(n2911), .B0(n2910), .Y(n2917) );
OAI211X1TS U2010 ( .A0(n1629), .A1(n2266), .B0(n1645), .C0(n2254), .Y(n1490)
);
OAI21X1TS U2011 ( .A0(n3393), .A1(n2376), .B0(n2314), .Y(n1117) );
OAI21X1TS U2012 ( .A0(n3428), .A1(n2367), .B0(n2321), .Y(n1145) );
NAND3BX1TS U2013 ( .AN(n3106), .B(n3105), .C(n3104), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
OAI211X1TS U2014 ( .A0(n1629), .A1(n2257), .B0(n1645), .C0(n2256), .Y(n1491)
);
OAI211X1TS U2015 ( .A0(n2292), .A1(n1630), .B0(n1645), .C0(n2231), .Y(n1482)
);
OAI211X1TS U2016 ( .A0(n2238), .A1(n1630), .B0(n1645), .C0(n2237), .Y(n1484)
);
OAI211X1TS U2017 ( .A0(n2241), .A1(n1630), .B0(n1645), .C0(n2240), .Y(n1483)
);
OAI211X1TS U2018 ( .A0(n3111), .A1(n3073), .B0(n1868), .C0(n1867), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[27]) );
OAI211X1TS U2019 ( .A0(n1629), .A1(n2251), .B0(n1900), .C0(n2250), .Y(n1493)
);
OAI211X1TS U2020 ( .A0(n2519), .A1(n1629), .B0(n1900), .C0(n2222), .Y(n1486)
);
OAI21X1TS U2021 ( .A0(n2928), .A1(n2927), .B0(n2926), .Y(n2933) );
OAI21X1TS U2022 ( .A0(n3409), .A1(n2444), .B0(n2317), .Y(n1154) );
NAND3BX1TS U2023 ( .AN(n3114), .B(n3113), .C(n3112), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[20]) );
OAI222X1TS U2024 ( .A0(n3362), .A1(n2544), .B0(n1872), .B1(n2525), .C0(n2546), .C1(n2524), .Y(n1457) );
AFHCINX2TS U2025 ( .CIN(n2981), .B(n2982), .A(n2983), .S(n2985), .CO(n2986)
);
OAI211X1TS U2026 ( .A0(n2263), .A1(n1630), .B0(n1645), .C0(n2262), .Y(n1477)
);
OAI222X1TS U2027 ( .A0(n2531), .A1(n1872), .B0(n3354), .B1(n2544), .C0(n2530), .C1(n2546), .Y(n1442) );
OAI211X1TS U2028 ( .A0(n2522), .A1(n1630), .B0(n1645), .C0(n2235), .Y(n1487)
);
OAI211X1TS U2029 ( .A0(n1629), .A1(n2248), .B0(n1900), .C0(n2247), .Y(n1489)
);
OAI211X1TS U2030 ( .A0(n3040), .A1(n3095), .B0(n1910), .C0(n1909), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[43]) );
OAI211X1TS U2031 ( .A0(n2041), .A1(n1629), .B0(n1900), .C0(n1906), .Y(n1478)
);
OAI211X1TS U2032 ( .A0(n2516), .A1(n1630), .B0(n1645), .C0(n2228), .Y(n1485)
);
OAI211X1TS U2033 ( .A0(n1629), .A1(n2260), .B0(n1645), .C0(n2259), .Y(n1492)
);
OAI211X1TS U2034 ( .A0(n2278), .A1(n1630), .B0(n1645), .C0(n2277), .Y(n1480)
);
OAI211X1TS U2035 ( .A0(n1630), .A1(n2270), .B0(n1645), .C0(n2269), .Y(n1494)
);
OAI21X1TS U2036 ( .A0(n2435), .A1(n3431), .B0(n2416), .Y(n1168) );
OAI21X1TS U2037 ( .A0(n3400), .A1(n2367), .B0(n2320), .Y(n1114) );
OAI211X1TS U2038 ( .A0(n2528), .A1(n1630), .B0(n1645), .C0(n2293), .Y(n1488)
);
OAI222X1TS U2039 ( .A0(n3358), .A1(n2544), .B0(n1872), .B1(n2528), .C0(n2546), .C1(n2527), .Y(n1450) );
OAI211X1TS U2040 ( .A0(n2215), .A1(n1629), .B0(n1900), .C0(n1904), .Y(n1476)
);
OAI21X1TS U2041 ( .A0(n3330), .A1(n2367), .B0(n2319), .Y(n1115) );
OAI211X1TS U2042 ( .A0(n1630), .A1(n2531), .B0(n1645), .C0(n2311), .Y(n1563)
);
OAI211X1TS U2043 ( .A0(n1630), .A1(n2533), .B0(n1645), .C0(n2299), .Y(n1495)
);
OAI211X1TS U2044 ( .A0(n2298), .A1(n1629), .B0(n2288), .C0(n1900), .Y(n1475)
);
OAI211X1TS U2045 ( .A0(n2307), .A1(n1629), .B0(n2303), .C0(n1900), .Y(n1474)
);
OAI211X1TS U2046 ( .A0(n2051), .A1(n1629), .B0(n1900), .C0(n1902), .Y(n1479)
);
OAI21X1TS U2047 ( .A0(n2962), .A1(n2961), .B0(n2960), .Y(n2967) );
OAI211X1TS U2048 ( .A0(n3044), .A1(n3095), .B0(n1914), .C0(n1913), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[42]) );
OAI211X1TS U2049 ( .A0(n2525), .A1(n1630), .B0(n1645), .C0(n2245), .Y(n1481)
);
AOI222X1TS U2050 ( .A0(n2246), .A1(n2063), .B0(n2217), .B1(n2242), .C0(n2302), .C1(Sgf_normalized_result[7]), .Y(n2038) );
INVX3TS U2051 ( .A(n1899), .Y(n1629) );
NOR2X1TS U2052 ( .A(n2765), .B(n2764), .Y(n2766) );
OAI21X1TS U2053 ( .A0(n3405), .A1(n2376), .B0(n2316), .Y(n1105) );
INVX3TS U2054 ( .A(n1899), .Y(n1630) );
AOI222X1TS U2055 ( .A0(n2255), .A1(n2063), .B0(n2217), .B1(n2052), .C0(n2302), .C1(Sgf_normalized_result[5]), .Y(n2053) );
NAND2XLTS U2056 ( .A(n2313), .B(n2209), .Y(n2210) );
BUFX3TS U2057 ( .A(n1863), .Y(n3242) );
NOR2X6TS U2058 ( .A(n2313), .B(n2486), .Y(n2315) );
CLKAND2X2TS U2059 ( .A(n2496), .B(n2308), .Y(n1899) );
OAI21X1TS U2060 ( .A0(n2801), .A1(n1708), .B0(n1707), .Y(n2829) );
INVX3TS U2061 ( .A(n2993), .Y(n3225) );
INVX3TS U2062 ( .A(n2993), .Y(n3237) );
OR2X4TS U2063 ( .A(n2312), .B(n3258), .Y(n2415) );
INVX4TS U2064 ( .A(n3002), .Y(n3148) );
INVX4TS U2065 ( .A(n2996), .Y(n3167) );
AOI21X1TS U2066 ( .A0(n1692), .A1(n2790), .B0(n1691), .Y(n2801) );
OAI21X1TS U2067 ( .A0(n2963), .A1(n2960), .B0(n2964), .Y(n1783) );
NOR2BX2TS U2068 ( .AN(n3279), .B(n2653), .Y(n2598) );
NAND2X4TS U2069 ( .A(n2301), .B(n2308), .Y(n1872) );
NOR2X4TS U2070 ( .A(n2019), .B(n2224), .Y(n2495) );
NOR2X4TS U2071 ( .A(n2019), .B(n1613), .Y(n2539) );
NOR2X6TS U2072 ( .A(n1915), .B(n1932), .Y(n1815) );
NAND3BX1TS U2073 ( .AN(n2123), .B(n2116), .C(n2115), .Y(n2136) );
NOR2X1TS U2074 ( .A(n1917), .B(n1932), .Y(n1813) );
AND2X2TS U2075 ( .A(n1807), .B(FSM_selector_C), .Y(n1808) );
NAND2BX1TS U2076 ( .AN(n2631), .B(Add_Subt_result[43]), .Y(n2655) );
INVX1TS U2077 ( .A(n2631), .Y(n2632) );
NOR2X4TS U2078 ( .A(n2019), .B(n1877), .Y(n2543) );
INVX3TS U2079 ( .A(n2549), .Y(n2302) );
NOR2X1TS U2080 ( .A(n3417), .B(n1607), .Y(n1660) );
NOR2X1TS U2081 ( .A(n3433), .B(n1607), .Y(n1659) );
CLKMX2X2TS U2082 ( .A(DMP[39]), .B(Sgf_normalized_result[41]), .S0(n1607),
.Y(n2730) );
NOR2X1TS U2083 ( .A(n3416), .B(n1607), .Y(n1661) );
NOR2X1TS U2084 ( .A(n3415), .B(n1607), .Y(n1663) );
CLKMX2X2TS U2085 ( .A(DMP[36]), .B(Sgf_normalized_result[38]), .S0(n1607),
.Y(n2734) );
NAND2X1TS U2086 ( .A(n3278), .B(n3347), .Y(n2639) );
CLKAND2X2TS U2087 ( .A(n1875), .B(n1874), .Y(n1876) );
NAND3BX1TS U2088 ( .AN(overflow_flag), .B(n3294), .C(n3346), .Y(n2492) );
NAND2X4TS U2089 ( .A(n1806), .B(n1587), .Y(n1807) );
NOR2X1TS U2090 ( .A(n3442), .B(n1745), .Y(n1656) );
NOR2X1TS U2091 ( .A(n3441), .B(n1753), .Y(n1657) );
NOR2X1TS U2092 ( .A(n1753), .B(n3326), .Y(n1678) );
NOR2X1TS U2093 ( .A(n3460), .B(n1753), .Y(n1651) );
NOR2X1TS U2094 ( .A(n3455), .B(n1662), .Y(n1652) );
NOR2X1TS U2095 ( .A(n3454), .B(n1748), .Y(n1653) );
CLKMX2X2TS U2096 ( .A(DMP[40]), .B(Sgf_normalized_result[42]), .S0(n2595),
.Y(n2722) );
OAI211X1TS U2097 ( .A0(intDX[61]), .A1(n3364), .B0(n2146), .C0(n2145), .Y(
n2147) );
NOR2X1TS U2098 ( .A(n3382), .B(n1748), .Y(n1669) );
NOR2X1TS U2099 ( .A(n3453), .B(n2592), .Y(n1654) );
CLKMX2X2TS U2100 ( .A(DMP[38]), .B(Sgf_normalized_result[40]), .S0(n2592),
.Y(n2701) );
CLKMX2X2TS U2101 ( .A(DMP[37]), .B(Sgf_normalized_result[39]), .S0(n1756),
.Y(n2697) );
NOR2X1TS U2102 ( .A(n3414), .B(n1748), .Y(n1664) );
CLKMX2X2TS U2103 ( .A(DMP[35]), .B(Sgf_normalized_result[37]), .S0(n2592),
.Y(n2738) );
NOR2X1TS U2104 ( .A(n2186), .B(n2185), .Y(n2199) );
CLKMX2X2TS U2105 ( .A(DMP[34]), .B(Sgf_normalized_result[36]), .S0(n2595),
.Y(n2742) );
CLKMX2X2TS U2106 ( .A(DMP[33]), .B(Sgf_normalized_result[35]), .S0(n1756),
.Y(n2746) );
NOR2X1TS U2107 ( .A(n3443), .B(n1748), .Y(n1655) );
NOR2X1TS U2108 ( .A(n3383), .B(n1748), .Y(n1668) );
NOR2X1TS U2109 ( .A(n3434), .B(n1753), .Y(n1658) );
NOR2X1TS U2110 ( .A(n1748), .B(n3370), .Y(n1673) );
NAND2BX1TS U2111 ( .AN(n3255), .B(n3256), .Y(n2665) );
NOR2X1TS U2112 ( .A(n1753), .B(n3371), .Y(n1672) );
NOR2X1TS U2113 ( .A(n1748), .B(n3369), .Y(n1674) );
NOR2X1TS U2114 ( .A(n3381), .B(n1748), .Y(n1670) );
INVX1TS U2115 ( .A(n3266), .Y(n3270) );
NOR2X1TS U2116 ( .A(n1753), .B(n3368), .Y(n1675) );
NOR3X1TS U2117 ( .A(n3269), .B(add_overflow_flag), .C(FS_Module_state_reg[1]), .Y(n1587) );
AND2X4TS U2118 ( .A(n1792), .B(n1794), .Y(n2007) );
XOR2X2TS U2119 ( .A(n2209), .B(n3353), .Y(n2008) );
OAI211X2TS U2120 ( .A0(intDY[12]), .A1(n3393), .B0(n2110), .C0(n2084), .Y(
n2114) );
INVX1TS U2121 ( .A(n2608), .Y(n2616) );
NAND2X1TS U2122 ( .A(n3348), .B(n2648), .Y(n2776) );
NAND3X1TS U2123 ( .A(n3527), .B(n2144), .C(intDY[60]), .Y(n2145) );
OAI211X2TS U2124 ( .A0(intDY[28]), .A1(n3418), .B0(n2082), .C0(n2073), .Y(
n2132) );
NAND2BX1TS U2125 ( .AN(ack_FSM), .B(ready), .Y(n3271) );
OAI211X2TS U2126 ( .A0(intDY[20]), .A1(n3413), .B0(n2129), .C0(n2083), .Y(
n2123) );
OAI211X1TS U2127 ( .A0(n2385), .A1(FS_Module_state_reg[2]), .B0(
add_overflow_flag), .C0(n2384), .Y(n2386) );
OAI211X1TS U2128 ( .A0(n3421), .A1(intDY[33]), .B0(n2070), .C0(n2173), .Y(
n2071) );
NAND2BX1TS U2129 ( .AN(intDY[62]), .B(intDX[62]), .Y(n2148) );
NAND2BX1TS U2130 ( .AN(intDX[62]), .B(intDY[62]), .Y(n2146) );
NOR2X1TS U2131 ( .A(n3365), .B(n1583), .Y(n1677) );
NAND2BX1TS U2132 ( .AN(intDY[32]), .B(intDX[32]), .Y(n2070) );
NOR2X1TS U2133 ( .A(n3318), .B(FS_Module_state_reg[0]), .Y(n1840) );
NOR2X1TS U2134 ( .A(n3318), .B(FS_Module_state_reg[1]), .Y(n1791) );
NOR2X1TS U2135 ( .A(n3321), .B(FS_Module_state_reg[1]), .Y(n1841) );
NAND2BX1TS U2136 ( .AN(intDY[59]), .B(intDX[59]), .Y(n2140) );
NOR2X1TS U2137 ( .A(n3395), .B(n1583), .Y(n1665) );
NOR2X1TS U2138 ( .A(n3394), .B(n1583), .Y(n1666) );
NOR2X1TS U2139 ( .A(n3384), .B(n1583), .Y(n1667) );
INVX4TS U2140 ( .A(n1817), .Y(n1577) );
NOR2X4TS U2141 ( .A(n3380), .B(FSM_selector_B[1]), .Y(n1810) );
NOR2X1TS U2142 ( .A(Add_Subt_result[52]), .B(Add_Subt_result[51]), .Y(n2652)
);
NAND2BX1TS U2143 ( .AN(intDY[29]), .B(intDX[29]), .Y(n2073) );
NOR2X1TS U2144 ( .A(n3327), .B(FS_Module_state_reg[0]), .Y(n1792) );
NAND2BX1TS U2145 ( .AN(intDY[47]), .B(intDX[47]), .Y(n2151) );
NAND2BX1TS U2146 ( .AN(intDY[19]), .B(intDX[19]), .Y(n2120) );
NOR2X1TS U2147 ( .A(n3397), .B(intDY[53]), .Y(n2065) );
OAI21X1TS U2148 ( .A0(intDY[31]), .A1(n3476), .B0(intDY[30]), .Y(n2078) );
NAND2BX1TS U2149 ( .AN(intDY[27]), .B(intDX[27]), .Y(n2075) );
NAND2BX1TS U2150 ( .AN(intDY[41]), .B(intDX[41]), .Y(n2069) );
NAND2BX1TS U2151 ( .AN(intDY[51]), .B(intDX[51]), .Y(n2190) );
NAND2BX1TS U2152 ( .AN(intDY[40]), .B(intDX[40]), .Y(n2068) );
OAI21X2TS U2153 ( .A0(n2892), .A1(n1786), .B0(n1785), .Y(n2977) );
AOI21X2TS U2154 ( .A0(n2829), .A1(n1740), .B0(n1739), .Y(n2892) );
AFHCINX4TS U2155 ( .CIN(n2756), .B(n2757), .A(n2758), .S(n2759), .CO(n2744)
);
OAI211X1TS U2156 ( .A0(Add_Subt_result[5]), .A1(n2619), .B0(n2629), .C0(
n3452), .Y(n2623) );
INVX4TS U2157 ( .A(n3475), .Y(n1662) );
INVX4TS U2158 ( .A(n3475), .Y(n1756) );
INVX4TS U2159 ( .A(n3475), .Y(n2592) );
MX2X1TS U2160 ( .A(DMP[49]), .B(Sgf_normalized_result[51]), .S0(n1662), .Y(
n2677) );
NOR2X1TS U2161 ( .A(n2961), .B(n2963), .Y(n1784) );
NOR2X1TS U2162 ( .A(n2919), .B(n1778), .Y(n2955) );
AFHCONX2TS U2163 ( .A(n2988), .B(n2987), .CI(n2986), .CON(n2760), .S(n2990)
);
AFHCONX2TS U2164 ( .A(n2952), .B(n2951), .CI(n2950), .CON(n2748), .S(n2953)
);
AFHCONX2TS U2165 ( .A(n2552), .B(n2551), .CI(n2550), .CON(n2554), .S(n2553)
);
MX2X1TS U2166 ( .A(DMP[47]), .B(Sgf_normalized_result[49]), .S0(n1756), .Y(
n2552) );
AFHCONX2TS U2167 ( .A(n2709), .B(n2708), .CI(n2707), .CON(n2712), .S(n2711)
);
NAND2X1TS U2168 ( .A(n2936), .B(n1776), .Y(n1778) );
NOR2XLTS U2169 ( .A(n1748), .B(n3361), .Y(n1713) );
MX2X1TS U2170 ( .A(DMP[9]), .B(Sgf_normalized_result[11]), .S0(n1745), .Y(
n1727) );
MX2X1TS U2171 ( .A(DMP[11]), .B(Sgf_normalized_result[13]), .S0(n1756), .Y(
n1731) );
MX2X1TS U2172 ( .A(DMP[20]), .B(Sgf_normalized_result[22]), .S0(n2592), .Y(
n1773) );
MX2X1TS U2173 ( .A(DMP[10]), .B(Sgf_normalized_result[12]), .S0(n1745), .Y(
n1729) );
MX2X1TS U2174 ( .A(DMP[12]), .B(Sgf_normalized_result[14]), .S0(n2592), .Y(
n1733) );
MX2X1TS U2175 ( .A(DMP[17]), .B(n1632), .S0(n1752), .Y(n1767) );
MX2X1TS U2176 ( .A(DMP[18]), .B(n1631), .S0(n1662), .Y(n1769) );
MX2X1TS U2177 ( .A(DMP[15]), .B(n1634), .S0(n2595), .Y(n1761) );
MX2X1TS U2178 ( .A(DMP[16]), .B(n1633), .S0(n2592), .Y(n1763) );
MX2X1TS U2179 ( .A(DMP[21]), .B(Sgf_normalized_result[23]), .S0(n1756), .Y(
n1779) );
MX2X1TS U2180 ( .A(DMP[14]), .B(Sgf_normalized_result[16]), .S0(n1662), .Y(
n1759) );
NOR2XLTS U2181 ( .A(n1753), .B(n3360), .Y(n1712) );
MX2X1TS U2182 ( .A(DMP[8]), .B(Sgf_normalized_result[10]), .S0(n1756), .Y(
n1723) );
NOR2XLTS U2183 ( .A(n1748), .B(n3362), .Y(n1741) );
MX2X1TS U2184 ( .A(DMP[13]), .B(Sgf_normalized_result[15]), .S0(n2592), .Y(
n1757) );
NOR2XLTS U2185 ( .A(n1753), .B(n3359), .Y(n1711) );
MX2X1TS U2186 ( .A(DMP[7]), .B(Sgf_normalized_result[9]), .S0(n1752), .Y(
n1721) );
XOR2X1TS U2187 ( .A(n1787), .B(n1709), .Y(n1718) );
MX2X1TS U2188 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n1756), .Y(
n1717) );
MX2X1TS U2189 ( .A(DMP[6]), .B(Sgf_normalized_result[8]), .S0(n1662), .Y(
n1719) );
MX2X1TS U2190 ( .A(DMP[3]), .B(Sgf_normalized_result[5]), .S0(n1607), .Y(
n1701) );
MX2X1TS U2191 ( .A(DMP[4]), .B(Sgf_normalized_result[6]), .S0(n1756), .Y(
n1703) );
MX2X1TS U2192 ( .A(DMP[52]), .B(exp_oper_result[0]), .S0(n1662), .Y(
S_Oper_A_exp[0]) );
AO21XLTS U2193 ( .A0(DmP[52]), .A1(n3380), .B0(n2569), .Y(n2570) );
NOR2XLTS U2194 ( .A(n1748), .B(n3356), .Y(n1749) );
MX2X1TS U2195 ( .A(DMP[19]), .B(Sgf_normalized_result[21]), .S0(n1745), .Y(
n1771) );
MX2X1TS U2196 ( .A(DMP[54]), .B(exp_oper_result[2]), .S0(n1662), .Y(
S_Oper_A_exp[2]) );
AO22XLTS U2197 ( .A0(n1614), .A1(n1810), .B0(n1577), .B1(DmP[54]), .Y(n2567)
);
MX2X1TS U2198 ( .A(DMP[51]), .B(Sgf_normalized_result[53]), .S0(n1756), .Y(
n2692) );
NOR2XLTS U2199 ( .A(n3470), .B(n1752), .Y(n1648) );
BUFX6TS U2200 ( .A(n1680), .Y(n1787) );
AFHCONX2TS U2201 ( .A(n2975), .B(n2974), .CI(n2973), .CON(n2969), .S(n2976)
);
AFHCONX2TS U2202 ( .A(n2718), .B(n2717), .CI(n2716), .CON(n2683), .S(n2719)
);
MX2X1TS U2203 ( .A(DMP[45]), .B(Sgf_normalized_result[47]), .S0(n1607), .Y(
n2718) );
AFHCONX2TS U2204 ( .A(n2979), .B(n2978), .CI(n2977), .CON(n2981), .S(n2980)
);
MX2X1TS U2205 ( .A(DMP[56]), .B(exp_oper_result[4]), .S0(n1662), .Y(
S_Oper_A_exp[4]) );
AO22XLTS U2206 ( .A0(LZA_output[4]), .A1(n1810), .B0(n1577), .B1(DmP[56]),
.Y(n2565) );
MX2X1TS U2207 ( .A(DMP[58]), .B(exp_oper_result[6]), .S0(n1745), .Y(
S_Oper_A_exp[6]) );
MX2X1TS U2208 ( .A(DMP[60]), .B(exp_oper_result[8]), .S0(n1745), .Y(
S_Oper_A_exp[8]) );
NOR2XLTS U2209 ( .A(Add_Subt_result[4]), .B(Add_Subt_result[3]), .Y(n2575)
);
AOI2BB2XLTS U2210 ( .B0(intDX[1]), .B1(n3366), .A0N(intDY[0]), .A1N(n2087),
.Y(n2088) );
NAND2BXLTS U2211 ( .AN(intDX[9]), .B(intDY[9]), .Y(n2101) );
NAND3XLTS U2212 ( .A(n3410), .B(n2100), .C(intDY[8]), .Y(n2102) );
NOR2XLTS U2213 ( .A(n2098), .B(intDX[10]), .Y(n2099) );
AOI2BB2XLTS U2214 ( .B0(intDY[3]), .B1(n3403), .A0N(intDX[2]), .A1N(n2090),
.Y(n2091) );
NAND2BXLTS U2215 ( .AN(intDY[2]), .B(intDX[2]), .Y(n2089) );
NAND2BXLTS U2216 ( .AN(intDY[9]), .B(intDX[9]), .Y(n2100) );
NAND2BXLTS U2217 ( .AN(intDY[13]), .B(intDX[13]), .Y(n2084) );
NOR2XLTS U2218 ( .A(n2130), .B(intDX[24]), .Y(n2074) );
OAI21XLTS U2219 ( .A0(intDX[37]), .A1(n3378), .B0(n2168), .Y(n2177) );
NAND3XLTS U2220 ( .A(n3423), .B(n2167), .C(intDY[36]), .Y(n2168) );
NOR2XLTS U2221 ( .A(n2152), .B(intDX[44]), .Y(n2153) );
AOI2BB2XLTS U2222 ( .B0(intDY[53]), .B1(n3397), .A0N(intDX[52]), .A1N(n2184),
.Y(n2186) );
NOR2X1TS U2223 ( .A(n2942), .B(n2944), .Y(n1776) );
MX2X1TS U2224 ( .A(DMP[1]), .B(Sgf_normalized_result[3]), .S0(n2595), .Y(
n1697) );
MX2X1TS U2225 ( .A(DMP[0]), .B(Sgf_normalized_result[2]), .S0(n1745), .Y(
n1689) );
MX2X1TS U2226 ( .A(DMP[2]), .B(Sgf_normalized_result[4]), .S0(n1607), .Y(
n1699) );
NAND2X1TS U2227 ( .A(n2650), .B(n2652), .Y(n2778) );
AOI221X1TS U2228 ( .A0(n3426), .A1(intDY[44]), .B0(intDY[43]), .B1(n1590),
.C0(n1962), .Y(n1963) );
OAI21XLTS U2229 ( .A0(n2669), .A1(n3524), .B0(n2497), .Y(n2498) );
OAI21XLTS U2230 ( .A0(n2669), .A1(n3525), .B0(n2493), .Y(n2494) );
OAI21XLTS U2231 ( .A0(n2669), .A1(n3466), .B0(n2503), .Y(n2504) );
AO21XLTS U2232 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[80]), .A1(
n2279), .B0(n2022), .Y(n2229) );
AOI222X1TS U2233 ( .A0(n3042), .A1(n1643), .B0(n3046), .B1(n1644), .C0(n3021), .C1(n1628), .Y(n3036) );
AOI222X1TS U2234 ( .A0(n3038), .A1(n1643), .B0(n3042), .B1(n1644), .C0(n3021), .C1(n3062), .Y(n3032) );
AOI222X1TS U2235 ( .A0(n3076), .A1(n1643), .B0(n3082), .B1(n1644), .C0(n3050), .C1(n1628), .Y(n3069) );
AO21XLTS U2236 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[82]), .A1(
n2279), .B0(n2032), .Y(n2219) );
AO21XLTS U2237 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[81]), .A1(
n2279), .B0(n2027), .Y(n2232) );
CLKAND2X2TS U2238 ( .A(n2282), .B(n1882), .Y(n2052) );
CLKAND2X2TS U2239 ( .A(n2282), .B(n1888), .Y(n2042) );
CLKAND2X2TS U2240 ( .A(n2282), .B(n1873), .Y(n2216) );
AOI222X1TS U2241 ( .A0(n3063), .A1(n3067), .B0(n3050), .B1(n1815), .C0(n3059), .C1(n3062), .Y(n3058) );
AOI222X1TS U2242 ( .A0(n3070), .A1(n1643), .B0(n3076), .B1(n1815), .C0(n3050), .C1(n3062), .Y(n3065) );
CLKAND2X2TS U2243 ( .A(Exp_Operation_Module_Data_S[0]), .B(n3267), .Y(n2594)
);
AOI222X1TS U2244 ( .A0(n3050), .A1(n1643), .B0(n3070), .B1(n1644), .C0(n3063), .C1(n3062), .Y(n3061) );
MX2X1TS U2245 ( .A(DMP[53]), .B(exp_oper_result[1]), .S0(n1745), .Y(
S_Oper_A_exp[1]) );
AO22XLTS U2246 ( .A0(n1616), .A1(n1810), .B0(n1577), .B1(DmP[53]), .Y(n2568)
);
NAND2BXLTS U2247 ( .AN(Sgf_normalized_result[54]), .B(n1607), .Y(n2688) );
NAND4XLTS U2248 ( .A(n3280), .B(n3279), .C(Add_Subt_result[37]), .D(n3467),
.Y(n3281) );
AFHCONX2TS U2249 ( .A(n2726), .B(n2725), .CI(n2724), .CON(n2703), .S(n2727)
);
CLKAND2X2TS U2250 ( .A(n1824), .B(n1823), .Y(n3005) );
CLKAND2X2TS U2251 ( .A(n1827), .B(n1826), .Y(n2997) );
CLKAND2X2TS U2252 ( .A(n1820), .B(n1819), .Y(n2999) );
OAI21XLTS U2253 ( .A0(n2669), .A1(n3472), .B0(n2540), .Y(n2542) );
AO22XLTS U2254 ( .A0(n2279), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(n1625), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n2280) );
OAI21XLTS U2255 ( .A0(n3522), .A1(n2669), .B0(n2508), .Y(n2509) );
OAI21XLTS U2256 ( .A0(n3465), .A1(n2669), .B0(n2505), .Y(n2506) );
INVX2TS U2257 ( .A(n2920), .Y(n2921) );
CLKAND2X2TS U2258 ( .A(n2592), .B(Sgf_normalized_result[1]), .Y(n1682) );
NOR2XLTS U2259 ( .A(n1753), .B(n3355), .Y(n1681) );
NOR2XLTS U2260 ( .A(n1753), .B(n3354), .Y(n1685) );
CLKAND2X2TS U2261 ( .A(n1662), .B(Sgf_normalized_result[0]), .Y(n1686) );
NOR2XLTS U2262 ( .A(n3462), .B(n1748), .Y(n1649) );
INVX4TS U2263 ( .A(n3254), .Y(n2984) );
NAND4BXLTS U2264 ( .AN(n2464), .B(Exp_Operation_Module_Data_S[6]), .C(
Exp_Operation_Module_Data_S[5]), .D(Exp_Operation_Module_Data_S[4]),
.Y(n2465) );
NAND4XLTS U2265 ( .A(Exp_Operation_Module_Data_S[3]), .B(
Exp_Operation_Module_Data_S[2]), .C(Exp_Operation_Module_Data_S[1]),
.D(n2594), .Y(n2464) );
MX2X1TS U2266 ( .A(DMP[57]), .B(exp_oper_result[5]), .S0(n1756), .Y(
S_Oper_A_exp[5]) );
MX2X1TS U2267 ( .A(DMP[55]), .B(exp_oper_result[3]), .S0(n1745), .Y(
S_Oper_A_exp[3]) );
AO22XLTS U2268 ( .A0(n1617), .A1(n1810), .B0(n1577), .B1(DmP[55]), .Y(n2566)
);
MX2X1TS U2269 ( .A(DMP[61]), .B(exp_oper_result[9]), .S0(n2592), .Y(
S_Oper_A_exp[9]) );
MX2X1TS U2270 ( .A(DMP[59]), .B(exp_oper_result[7]), .S0(n2595), .Y(
S_Oper_A_exp[7]) );
INVX4TS U2271 ( .A(n3254), .Y(n2710) );
AO22XLTS U2272 ( .A0(n2281), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(n1625), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n2271) );
AO22XLTS U2273 ( .A0(n2279), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(n1625), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(n2054) );
OAI211X1TS U2274 ( .A0(n2528), .A1(n2291), .B0(n2021), .C0(n2020), .Y(n2230)
);
OAI211X1TS U2275 ( .A0(n2516), .A1(n2291), .B0(n2227), .C0(n2226), .Y(n2514)
);
OAI211X1TS U2276 ( .A0(n2278), .A1(n2291), .B0(n2056), .C0(n2055), .Y(n2253)
);
INVX4TS U2277 ( .A(n3254), .Y(n2791) );
AO22XLTS U2278 ( .A0(n2281), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(n1625), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n1870) );
AO22XLTS U2279 ( .A0(n3228), .A1(Add_Subt_result[1]), .B0(n1608), .B1(
Add_Subt_result[53]), .Y(n3243) );
AOI222X1TS U2280 ( .A0(n3122), .A1(n1643), .B0(n3128), .B1(n1644), .C0(n3116), .C1(n3062), .Y(n1931) );
AOI222X1TS U2281 ( .A0(n3081), .A1(n3067), .B0(n2013), .B1(n1815), .C0(n3075), .C1(n1818), .Y(n3073) );
AOI222X1TS U2282 ( .A0(n3093), .A1(n3067), .B0(n3094), .B1(n1815), .C0(n2013), .C1(n1628), .Y(n3089) );
AOI222X1TS U2283 ( .A0(n3086), .A1(n3067), .B0(n3093), .B1(n1815), .C0(n2013), .C1(n3062), .Y(n3084) );
AOI2BB2XLTS U2284 ( .B0(n2654), .B1(Add_Subt_result[28]), .A0N(n3279), .A1N(
n2653), .Y(n2656) );
INVX4TS U2285 ( .A(n3254), .Y(n2989) );
NAND4XLTS U2286 ( .A(n3185), .B(n3184), .C(n3183), .D(n3182), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
NAND4XLTS U2287 ( .A(n3138), .B(n3137), .C(n3136), .D(n3135), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
OAI21XLTS U2288 ( .A0(n2669), .A1(n3526), .B0(n2668), .Y(n2670) );
AO22XLTS U2289 ( .A0(n3023), .A1(n3071), .B0(n3038), .B1(n3010), .Y(n1912)
);
NAND4XLTS U2290 ( .A(n3028), .B(n3027), .C(n3026), .D(n3025), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[46]) );
AO22XLTS U2291 ( .A0(n3020), .A1(n3071), .B0(n3021), .B1(n3010), .Y(n1908)
);
MX2X1TS U2292 ( .A(n2990), .B(Add_Subt_result[27]), .S0(n2984), .Y(n1530) );
AO22XLTS U2293 ( .A0(n3317), .A1(Data_Y[0]), .B0(n1627), .B1(intDY[0]), .Y(
n1232) );
AO22XLTS U2294 ( .A0(n3313), .A1(Data_Y[32]), .B0(n3309), .B1(intDY[32]),
.Y(n1264) );
AO22XLTS U2295 ( .A0(n3312), .A1(Data_Y[59]), .B0(n3307), .B1(intDY[59]),
.Y(n1291) );
AO22XLTS U2296 ( .A0(n3314), .A1(Data_Y[14]), .B0(n3315), .B1(intDY[14]),
.Y(n1246) );
AO22XLTS U2297 ( .A0(n3316), .A1(Data_Y[22]), .B0(n3315), .B1(intDY[22]),
.Y(n1254) );
AO22XLTS U2298 ( .A0(n3308), .A1(Data_Y[30]), .B0(n3309), .B1(intDY[30]),
.Y(n1262) );
AO22XLTS U2299 ( .A0(n3308), .A1(Data_Y[39]), .B0(n3309), .B1(intDY[39]),
.Y(n1271) );
AO22XLTS U2300 ( .A0(n3310), .A1(Data_Y[27]), .B0(n3315), .B1(intDY[27]),
.Y(n1259) );
AO22XLTS U2301 ( .A0(n3310), .A1(Data_Y[34]), .B0(n3309), .B1(intDY[34]),
.Y(n1266) );
AO22XLTS U2302 ( .A0(n3308), .A1(Data_Y[42]), .B0(n3309), .B1(intDY[42]),
.Y(n1274) );
AO22XLTS U2303 ( .A0(n3311), .A1(Data_Y[20]), .B0(n3315), .B1(intDY[20]),
.Y(n1252) );
AO22XLTS U2304 ( .A0(n3311), .A1(Data_Y[50]), .B0(n3307), .B1(intDY[50]),
.Y(n1282) );
AO22XLTS U2305 ( .A0(n3311), .A1(Data_Y[54]), .B0(n3307), .B1(intDY[54]),
.Y(n1286) );
AO22XLTS U2306 ( .A0(n3311), .A1(Data_Y[24]), .B0(n3315), .B1(intDY[24]),
.Y(n1256) );
AO22XLTS U2307 ( .A0(n3311), .A1(Data_Y[56]), .B0(n3307), .B1(intDY[56]),
.Y(n1288) );
AO22XLTS U2308 ( .A0(n3311), .A1(Data_Y[17]), .B0(n3315), .B1(intDY[17]),
.Y(n1249) );
AO22XLTS U2309 ( .A0(n3308), .A1(Data_Y[45]), .B0(n3307), .B1(intDY[45]),
.Y(n1277) );
AO22XLTS U2310 ( .A0(n3317), .A1(Data_Y[25]), .B0(n3315), .B1(intDY[25]),
.Y(n1257) );
AO22XLTS U2311 ( .A0(n3311), .A1(Data_Y[57]), .B0(n3307), .B1(intDY[57]),
.Y(n1289) );
AO22XLTS U2312 ( .A0(n3308), .A1(Data_Y[36]), .B0(n3309), .B1(intDY[36]),
.Y(n1268) );
NAND4XLTS U2313 ( .A(n3145), .B(n3144), .C(n3143), .D(n3142), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
NAND4XLTS U2314 ( .A(n3152), .B(n3151), .C(n3150), .D(n3149), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
NAND4XLTS U2315 ( .A(n3159), .B(n3158), .C(n3157), .D(n3156), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
NAND4XLTS U2316 ( .A(n3166), .B(n3165), .C(n3164), .D(n3163), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
NAND4XLTS U2317 ( .A(n3173), .B(n3172), .C(n3171), .D(n3170), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
NAND4XLTS U2318 ( .A(n3179), .B(n3178), .C(n3177), .D(n3176), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
MX2X1TS U2319 ( .A(Exp_Operation_Module_Data_S[6]), .B(exp_oper_result[6]),
.S0(n2664), .Y(n1432) );
MX2X1TS U2320 ( .A(Exp_Operation_Module_Data_S[7]), .B(exp_oper_result[7]),
.S0(n2664), .Y(n1431) );
AOI222X1TS U2321 ( .A0(n2258), .A1(n2063), .B0(n2217), .B1(n2042), .C0(n2302), .C1(Sgf_normalized_result[4]), .Y(n2043) );
AOI222X1TS U2322 ( .A0(n2249), .A1(n2063), .B0(n2217), .B1(n2060), .C0(n2302), .C1(Sgf_normalized_result[3]), .Y(n2048) );
MX2X1TS U2323 ( .A(Exp_Operation_Module_Data_S[2]), .B(exp_oper_result[2]),
.S0(n2664), .Y(n1436) );
MX2X1TS U2324 ( .A(Exp_Operation_Module_Data_S[5]), .B(exp_oper_result[5]),
.S0(n2664), .Y(n1433) );
MX2X1TS U2325 ( .A(Exp_Operation_Module_Data_S[4]), .B(exp_oper_result[4]),
.S0(n2664), .Y(n1434) );
MX2X1TS U2326 ( .A(Exp_Operation_Module_Data_S[1]), .B(exp_oper_result[1]),
.S0(n2664), .Y(n1437) );
MX2X1TS U2327 ( .A(Exp_Operation_Module_Data_S[3]), .B(exp_oper_result[3]),
.S0(n2664), .Y(n1435) );
MX2X1TS U2328 ( .A(n2925), .B(Add_Subt_result[19]), .S0(n2984), .Y(n1522) );
MX2X1TS U2329 ( .A(n2863), .B(Add_Subt_result[11]), .S0(n2710), .Y(n1514) );
MX2X1TS U2330 ( .A(n2953), .B(Add_Subt_result[31]), .S0(n2984), .Y(n1534) );
MX2X1TS U2331 ( .A(n2909), .B(Add_Subt_result[17]), .S0(n2710), .Y(n1520) );
MX2X1TS U2332 ( .A(n2881), .B(Add_Subt_result[13]), .S0(n2989), .Y(n1516) );
MX2X1TS U2333 ( .A(n2976), .B(Add_Subt_result[29]), .S0(n2989), .Y(n1532) );
AO22XLTS U2334 ( .A0(n3311), .A1(Data_Y[47]), .B0(n3306), .B1(intDY[47]),
.Y(n1279) );
AO22XLTS U2335 ( .A0(n3314), .A1(Data_Y[19]), .B0(n3315), .B1(intDY[19]),
.Y(n1251) );
AO22XLTS U2336 ( .A0(n3311), .A1(Data_Y[51]), .B0(n3307), .B1(intDY[51]),
.Y(n1283) );
AO22XLTS U2337 ( .A0(n3308), .A1(Data_Y[40]), .B0(n3309), .B1(intDY[40]),
.Y(n1272) );
AO22XLTS U2338 ( .A0(n3311), .A1(Data_Y[18]), .B0(n3315), .B1(intDY[18]),
.Y(n1250) );
AO22XLTS U2339 ( .A0(n3312), .A1(Data_Y[26]), .B0(n3315), .B1(intDY[26]),
.Y(n1258) );
AO22XLTS U2340 ( .A0(n3313), .A1(Data_Y[28]), .B0(n3309), .B1(intDY[28]),
.Y(n1260) );
AO22XLTS U2341 ( .A0(n3311), .A1(Data_Y[49]), .B0(n3306), .B1(intDY[49]),
.Y(n1281) );
AO22XLTS U2342 ( .A0(n3312), .A1(Data_Y[58]), .B0(n3307), .B1(intDY[58]),
.Y(n1290) );
AO22XLTS U2343 ( .A0(n3312), .A1(Data_Y[60]), .B0(n3307), .B1(intDY[60]),
.Y(n1292) );
AO22XLTS U2344 ( .A0(n3308), .A1(Data_Y[46]), .B0(n3306), .B1(intDY[46]),
.Y(n1278) );
MX2X1TS U2345 ( .A(n2949), .B(Add_Subt_result[22]), .S0(n2989), .Y(n1525) );
AO22XLTS U2346 ( .A0(n3317), .A1(Data_Y[21]), .B0(n3315), .B1(intDY[21]),
.Y(n1253) );
AO22XLTS U2347 ( .A0(n3308), .A1(Data_Y[29]), .B0(n3309), .B1(intDY[29]),
.Y(n1261) );
AO22XLTS U2348 ( .A0(n3317), .A1(Data_Y[13]), .B0(n3315), .B1(intDY[13]),
.Y(n1245) );
AO22XLTS U2349 ( .A0(n3312), .A1(Data_Y[31]), .B0(n3309), .B1(intDY[31]),
.Y(n1263) );
AO22XLTS U2350 ( .A0(n3310), .A1(Data_Y[23]), .B0(n3315), .B1(intDY[23]),
.Y(n1255) );
AO22XLTS U2351 ( .A0(n3313), .A1(Data_Y[15]), .B0(n3315), .B1(intDY[15]),
.Y(n1247) );
AO22XLTS U2352 ( .A0(n3308), .A1(Data_Y[35]), .B0(n3309), .B1(intDY[35]),
.Y(n1267) );
AO22XLTS U2353 ( .A0(n3308), .A1(Data_Y[41]), .B0(n3309), .B1(intDY[41]),
.Y(n1273) );
AO22XLTS U2354 ( .A0(n3311), .A1(Data_Y[55]), .B0(n3307), .B1(intDY[55]),
.Y(n1287) );
AO22XLTS U2355 ( .A0(n3308), .A1(Data_Y[43]), .B0(n3307), .B1(intDY[43]),
.Y(n1275) );
AO22XLTS U2356 ( .A0(n3312), .A1(Data_Y[33]), .B0(n3309), .B1(intDY[33]),
.Y(n1265) );
AO22XLTS U2357 ( .A0(n3311), .A1(Data_Y[53]), .B0(n3307), .B1(intDY[53]),
.Y(n1285) );
NAND4XLTS U2358 ( .A(n3018), .B(n3017), .C(n3016), .D(n3015), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[47]) );
MX2X1TS U2359 ( .A(n2873), .B(Add_Subt_result[12]), .S0(n2710), .Y(n1515) );
MX2X1TS U2360 ( .A(n2747), .B(Add_Subt_result[35]), .S0(n2989), .Y(n1538) );
MX2X1TS U2361 ( .A(n2972), .B(Add_Subt_result[30]), .S0(n2984), .Y(n1533) );
OAI21XLTS U2362 ( .A0(n3011), .A1(n2996), .B0(n1851), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[51]) );
MX2X1TS U2363 ( .A(n2980), .B(Add_Subt_result[25]), .S0(n2710), .Y(n1528) );
OAI211XLTS U2364 ( .A0(intDX[63]), .A1(n2211), .B0(n2210), .C0(n2007), .Y(
n2212) );
MX2X1TS U2365 ( .A(n2891), .B(Add_Subt_result[14]), .S0(n2989), .Y(n1517) );
MX2X1TS U2366 ( .A(n2934), .B(Add_Subt_result[20]), .S0(n2710), .Y(n1523) );
MX2X1TS U2367 ( .A(n2918), .B(Add_Subt_result[18]), .S0(n2989), .Y(n1521) );
MX2X1TS U2368 ( .A(n2968), .B(Add_Subt_result[24]), .S0(n2989), .Y(n1527) );
MX2X1TS U2369 ( .A(n2763), .B(Add_Subt_result[28]), .S0(n2989), .Y(n1531) );
MX2X1TS U2370 ( .A(n2959), .B(Add_Subt_result[23]), .S0(n2710), .Y(n1526) );
MX2X1TS U2371 ( .A(n2904), .B(Add_Subt_result[16]), .S0(n2984), .Y(n1519) );
MX2X1TS U2372 ( .A(n2857), .B(Add_Subt_result[10]), .S0(n2710), .Y(n1513) );
MX2X1TS U2373 ( .A(n2985), .B(Add_Subt_result[26]), .S0(n2984), .Y(n1529) );
MX2X1TS U2374 ( .A(n2895), .B(Add_Subt_result[15]), .S0(n2984), .Y(n1518) );
MX2X1TS U2375 ( .A(n2847), .B(Add_Subt_result[9]), .S0(n2984), .Y(n1512) );
MX2X1TS U2376 ( .A(n2840), .B(Add_Subt_result[8]), .S0(n2989), .Y(n1511) );
MX2X1TS U2377 ( .A(n2828), .B(Add_Subt_result[6]), .S0(n2710), .Y(n1509) );
MX2X1TS U2378 ( .A(n2755), .B(Add_Subt_result[33]), .S0(n2984), .Y(n1536) );
MX2X1TS U2379 ( .A(n2751), .B(Add_Subt_result[32]), .S0(n2710), .Y(n1535) );
NAND4XLTS U2380 ( .A(n3274), .B(n3273), .C(n3272), .D(n3271), .Y(n1558) );
NAND3XLTS U2381 ( .A(n3265), .B(n3264), .C(n3263), .Y(n1561) );
AOI211XLTS U2382 ( .A0(FS_Module_state_reg[3]), .A1(n3262), .B0(n3261), .C0(
n3268), .Y(n3264) );
MX2X1TS U2383 ( .A(n2759), .B(Add_Subt_result[34]), .S0(n2710), .Y(n1537) );
OAI222X1TS U2384 ( .A0(n3359), .A1(n2549), .B0(n1872), .B1(n2522), .C0(n2546), .C1(n2521), .Y(n1451) );
OAI222X1TS U2385 ( .A0(n3360), .A1(n2549), .B0(n1872), .B1(n2519), .C0(n2546), .C1(n2518), .Y(n1452) );
OAI222X1TS U2386 ( .A0(n3361), .A1(n2549), .B0(n1872), .B1(n2516), .C0(n2546), .C1(n2515), .Y(n1453) );
NAND4XLTS U2387 ( .A(n3253), .B(n3252), .C(n3251), .D(n3250), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
NAND4XLTS U2388 ( .A(n3235), .B(n3234), .C(n3233), .D(n3232), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
NAND4XLTS U2389 ( .A(n3224), .B(n3223), .C(n3222), .D(n3221), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
NAND4XLTS U2390 ( .A(n3215), .B(n3214), .C(n3213), .D(n3212), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
NAND4XLTS U2391 ( .A(n3209), .B(n3208), .C(n3207), .D(n3206), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
NAND4XLTS U2392 ( .A(n3203), .B(n3202), .C(n3201), .D(n3200), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
NAND4XLTS U2393 ( .A(n3197), .B(n3196), .C(n3195), .D(n3194), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
NAND4XLTS U2394 ( .A(n3191), .B(n3190), .C(n3189), .D(n3188), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
NAND4XLTS U2395 ( .A(n3132), .B(n3131), .C(n3130), .D(n3129), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
NAND4XLTS U2396 ( .A(n3126), .B(n3125), .C(n3124), .D(n3123), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
NAND4XLTS U2397 ( .A(n3120), .B(n3119), .C(n3118), .D(n3117), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
AO22XLTS U2398 ( .A0(n3155), .A1(n2014), .B0(n3103), .B1(n3148), .Y(n1928)
);
NAND4XLTS U2399 ( .A(n3100), .B(n3099), .C(n3098), .D(n3097), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[22]) );
OAI211XLTS U2400 ( .A0(n1931), .A1(n3095), .B0(n1898), .C0(n1897), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI2BB2XLTS U2401 ( .B0(n3167), .B1(n3116), .A0N(n3109), .A1N(n2015), .Y(
n2016) );
AOI2BB2XLTS U2402 ( .B0(n3071), .B1(n3081), .A0N(n3102), .A1N(n2015), .Y(
n1933) );
MX2X1TS U2403 ( .A(n2940), .B(n1642), .S0(n2989), .Y(n1524) );
INVX2TS U2404 ( .A(n1807), .Y(n1858) );
BUFX3TS U2405 ( .A(n1858), .Y(n3139) );
OR2X1TS U2406 ( .A(n1917), .B(n3110), .Y(n1584) );
INVX4TS U2407 ( .A(n1807), .Y(n1608) );
OAI21XLTS U2408 ( .A0(n3337), .A1(n2415), .B0(n2363), .Y(n1107) );
INVX2TS U2409 ( .A(n1605), .Y(n1609) );
BUFX4TS U2410 ( .A(n1612), .Y(n3519) );
MXI2X1TS U2411 ( .A(n3380), .B(add_overflow_flag), .S0(n2591), .Y(n1440) );
NOR3X1TS U2412 ( .A(n3321), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[2]), .Y(n2591) );
NOR4X2TS U2413 ( .A(n2066), .B(n2138), .C(n2150), .D(n2142), .Y(n2196) );
OAI21XLTS U2414 ( .A0(n2224), .A1(n3524), .B0(n2223), .Y(n2032) );
OAI21XLTS U2415 ( .A0(n2224), .A1(n3522), .B0(n2223), .Y(n2022) );
OAI21X1TS U2416 ( .A0(n2224), .A1(n3472), .B0(n2223), .Y(n2034) );
NAND2X4TS U2417 ( .A(n1920), .B(n1869), .Y(n2223) );
AOI222X1TS U2418 ( .A0(n2230), .A1(n2063), .B0(n2302), .B1(
Sgf_normalized_result[14]), .C0(n2229), .C1(n2217), .Y(n2023) );
AOI222X1TS U2419 ( .A0(n2236), .A1(n2063), .B0(n2302), .B1(
Sgf_normalized_result[12]), .C0(n2219), .C1(n2217), .Y(n2033) );
AOI222X1TS U2420 ( .A0(n2239), .A1(n2063), .B0(n2302), .B1(
Sgf_normalized_result[13]), .C0(n2232), .C1(n2217), .Y(n2028) );
BUFX4TS U2421 ( .A(n3510), .Y(n3502) );
BUFX4TS U2422 ( .A(n3498), .Y(n3481) );
BUFX4TS U2423 ( .A(n3496), .Y(n3482) );
BUFX3TS U2424 ( .A(n3497), .Y(n1610) );
BUFX3TS U2425 ( .A(n3521), .Y(n3518) );
BUFX4TS U2426 ( .A(n3513), .Y(n3494) );
BUFX4TS U2427 ( .A(n3513), .Y(n3510) );
OAI21X2TS U2428 ( .A0(n3266), .A1(n3269), .B0(n3272), .Y(n3261) );
BUFX3TS U2429 ( .A(n3511), .Y(n1611) );
BUFX3TS U2430 ( .A(n3511), .Y(n1612) );
INVX2TS U2431 ( .A(n1876), .Y(n1613) );
OAI21X2TS U2432 ( .A0(n2283), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .B0(n2282), .Y(n2531)
);
BUFX4TS U2433 ( .A(n1646), .Y(n3312) );
BUFX4TS U2434 ( .A(n3509), .Y(n3517) );
BUFX4TS U2435 ( .A(n3509), .Y(n3506) );
OAI21X2TS U2436 ( .A0(n3464), .A1(n3219), .B0(n3218), .Y(n3241) );
NOR2X2TS U2437 ( .A(n1718), .B(n1717), .Y(n2834) );
OAI21X2TS U2438 ( .A0(n2283), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(n2282), .Y(n2533)
);
BUFX4TS U2439 ( .A(n3490), .Y(n3495) );
BUFX4TS U2440 ( .A(n3490), .Y(n3511) );
BUFX4TS U2441 ( .A(n3519), .Y(n3496) );
BUFX4TS U2442 ( .A(n3519), .Y(n3497) );
BUFX4TS U2443 ( .A(n3519), .Y(n3483) );
BUFX4TS U2444 ( .A(n3519), .Y(n3484) );
BUFX3TS U2445 ( .A(n3518), .Y(n3513) );
BUFX4TS U2446 ( .A(n1612), .Y(n3498) );
BUFX4TS U2447 ( .A(n3513), .Y(n3491) );
BUFX4TS U2448 ( .A(n3316), .Y(n3311) );
OAI21X4TS U2449 ( .A0(n1821), .A1(n3351), .B0(n1866), .Y(n3087) );
OAI21X4TS U2450 ( .A0(n3352), .A1(n1821), .B0(n1862), .Y(n3086) );
BUFX4TS U2451 ( .A(n2014), .Y(n3239) );
BUFX4TS U2452 ( .A(n3051), .Y(n3246) );
AOI222X1TS U2453 ( .A0(n3075), .A1(n3067), .B0(n3081), .B1(n1815), .C0(n3066), .C1(n1628), .Y(n3091) );
OAI2BB1X2TS U2454 ( .A0N(Add_Subt_result[33]), .A1N(n3161), .B0(n1861), .Y(
n3075) );
OAI2BB1X2TS U2455 ( .A0N(Add_Subt_result[32]), .A1N(n3161), .B0(n1859), .Y(
n3081) );
OAI2BB1X2TS U2456 ( .A0N(Add_Subt_result[41]), .A1N(n3161), .B0(n3029), .Y(
n3059) );
AOI21X1TS U2457 ( .A0(n2617), .A1(n2662), .B0(n3288), .Y(n2618) );
AOI211X2TS U2458 ( .A0(intDX[44]), .A1(n3373), .B0(n2152), .C0(n2162), .Y(
n2160) );
INVX2TS U2459 ( .A(n1589), .Y(n1614) );
OAI31X1TS U2460 ( .A0(n3260), .A1(n3259), .A2(n3258), .B0(n3301), .Y(n3268)
);
INVX4TS U2461 ( .A(n2007), .Y(n3258) );
INVX2TS U2462 ( .A(n1593), .Y(n1615) );
INVX2TS U2463 ( .A(n1586), .Y(n1616) );
INVX2TS U2464 ( .A(n1588), .Y(n1617) );
INVX2TS U2465 ( .A(n1603), .Y(n1618) );
INVX2TS U2466 ( .A(n1599), .Y(n1619) );
INVX2TS U2467 ( .A(n1600), .Y(n1620) );
INVX2TS U2468 ( .A(n1598), .Y(n1621) );
INVX2TS U2469 ( .A(n1601), .Y(n1622) );
INVX2TS U2470 ( .A(n1602), .Y(n1623) );
INVX2TS U2471 ( .A(n1604), .Y(n1624) );
BUFX4TS U2472 ( .A(n3079), .Y(n3095) );
AOI222X1TS U2473 ( .A0(n3082), .A1(n3067), .B0(n3066), .B1(n1815), .C0(n3076), .C1(n3062), .Y(n3074) );
OAI21X2TS U2474 ( .A0(n1821), .A1(n3463), .B0(n3055), .Y(n3066) );
BUFX4TS U2475 ( .A(n3367), .Y(n3153) );
BUFX4TS U2476 ( .A(n3367), .Y(n3216) );
BUFX4TS U2477 ( .A(n3367), .Y(n3054) );
OAI21X4TS U2478 ( .A0(n3320), .A1(n3219), .B0(n1893), .Y(n3128) );
OAI21X4TS U2479 ( .A0(n3363), .A1(n1821), .B0(n1894), .Y(n3116) );
OAI21X4TS U2480 ( .A0(n3452), .A1(n1821), .B0(n3192), .Y(n3245) );
OAI21X4TS U2481 ( .A0(n3446), .A1(n3219), .B0(n1892), .Y(n3122) );
AOI22X2TS U2482 ( .A0(n1917), .A1(n1916), .B0(n3094), .B1(n1915), .Y(n3102)
);
OAI21X2TS U2483 ( .A0(n3350), .A1(n3219), .B0(n1865), .Y(n3094) );
BUFX3TS U2484 ( .A(n2315), .Y(n2470) );
BUFX4TS U2485 ( .A(n3013), .Y(n3107) );
BUFX4TS U2486 ( .A(n3013), .Y(n3248) );
BUFX4TS U2487 ( .A(n3167), .Y(n3244) );
BUFX4TS U2488 ( .A(n2543), .Y(n2666) );
AOI211X1TS U2489 ( .A0(Add_Subt_result[27]), .A1(n2654), .B0(n2612), .C0(
n2611), .Y(n2613) );
OAI21X2TS U2490 ( .A0(n3459), .A1(n1821), .B0(n3210), .Y(n3247) );
BUFX4TS U2491 ( .A(n1863), .Y(n3229) );
BUFX4TS U2492 ( .A(n2539), .Y(n2667) );
BUFX4TS U2493 ( .A(n2495), .Y(n2295) );
INVX2TS U2494 ( .A(n1580), .Y(n1625) );
INVX4TS U2495 ( .A(n2315), .Y(n2442) );
INVX4TS U2496 ( .A(n2415), .Y(n2485) );
INVX2TS U2497 ( .A(n3303), .Y(n1626) );
INVX3TS U2498 ( .A(n1626), .Y(n1627) );
INVX3TS U2499 ( .A(n3294), .Y(n2991) );
INVX3TS U2500 ( .A(n3298), .Y(n3297) );
AOI211X2TS U2501 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[88]), .A1(
n2281), .B0(n2538), .C0(n2280), .Y(n2307) );
AOI211X2TS U2502 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[94]), .A1(
n2281), .B0(n2538), .C0(n2054), .Y(n2278) );
NOR2X4TS U2503 ( .A(n2223), .B(n1874), .Y(n2538) );
INVX2TS U2504 ( .A(n1584), .Y(n1628) );
AOI22X2TS U2505 ( .A0(n1917), .A1(n3103), .B0(n1916), .B1(n1915), .Y(n3109)
);
OAI21X2TS U2506 ( .A0(n3447), .A1(n1821), .B0(n1895), .Y(n3103) );
INVX2TS U2507 ( .A(n1582), .Y(n1631) );
INVX2TS U2508 ( .A(n1581), .Y(n1632) );
INVX2TS U2509 ( .A(n1579), .Y(n1633) );
INVX2TS U2510 ( .A(n1578), .Y(n1634) );
AOI21X2TS U2511 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[86]), .A1(
n2279), .B0(n2018), .Y(n2528) );
AOI21X2TS U2512 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[83]), .A1(
n2279), .B0(n2225), .Y(n2516) );
AOI21X2TS U2513 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[84]), .A1(
n2279), .B0(n2029), .Y(n2519) );
AOI21X2TS U2514 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[85]), .A1(
n2279), .B0(n2024), .Y(n2522) );
INVX2TS U2515 ( .A(n1592), .Y(n1635) );
AOI21X2TS U2516 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[79]), .A1(
n2279), .B0(n2034), .Y(n2525) );
INVX2TS U2517 ( .A(n1596), .Y(n1636) );
INVX2TS U2518 ( .A(n1595), .Y(n1637) );
INVX2TS U2519 ( .A(n1606), .Y(n1638) );
INVX2TS U2520 ( .A(n1594), .Y(n1639) );
INVX2TS U2521 ( .A(n1597), .Y(n1640) );
INVX2TS U2522 ( .A(n1591), .Y(n1641) );
AOI211X2TS U2523 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[76]), .A1(
n2279), .B0(n2538), .C0(n1887), .Y(n2041) );
AOI211X2TS U2524 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[77]), .A1(
n2279), .B0(n2538), .C0(n1881), .Y(n2051) );
INVX2TS U2525 ( .A(n1585), .Y(n1642) );
OAI221X1TS U2526 ( .A0(n3337), .A1(intDY[2]), .B0(n3405), .B1(intDY[0]),
.C0(n1985), .Y(n1988) );
OAI221XLTS U2527 ( .A0(n3476), .A1(intDY[31]), .B0(n3387), .B1(intDY[32]),
.C0(n1976), .Y(n1981) );
AOI32X1TS U2528 ( .A0(n3477), .A1(n2140), .A2(intDY[58]), .B0(intDY[59]),
.B1(n3436), .Y(n2141) );
AOI221X1TS U2529 ( .A0(n3527), .A1(intDY[60]), .B0(intDY[59]), .B1(n3436),
.C0(n1938), .Y(n1948) );
OAI221X1TS U2530 ( .A0(n3406), .A1(intDY[13]), .B0(n3404), .B1(intDY[14]),
.C0(n1991), .Y(n1998) );
OAI221X1TS U2531 ( .A0(n3408), .A1(intDY[21]), .B0(n3333), .B1(intDY[22]),
.C0(n1967), .Y(n1974) );
OAI221X1TS U2532 ( .A0(n3407), .A1(intDY[29]), .B0(n3332), .B1(intDY[30]),
.C0(n1975), .Y(n1982) );
AOI221X1TS U2533 ( .A0(n3428), .A1(intDY[40]), .B0(intDY[39]), .B1(n3342),
.C0(n1952), .Y(n1957) );
AOI32X1TS U2534 ( .A0(n3339), .A1(n2075), .A2(intDY[26]), .B0(intDY[27]),
.B1(n3419), .Y(n2076) );
OAI221XLTS U2535 ( .A0(n3419), .A1(intDY[27]), .B0(n3418), .B1(intDY[28]),
.C0(n1978), .Y(n1979) );
AOI221X1TS U2536 ( .A0(n3430), .A1(intDY[34]), .B0(intDY[33]), .B1(n3421),
.C0(n1953), .Y(n1956) );
AOI221X1TS U2537 ( .A0(n3427), .A1(intDY[42]), .B0(intDY[41]), .B1(n3422),
.C0(n1961), .Y(n1964) );
OAI221XLTS U2538 ( .A0(n3435), .A1(intDY[19]), .B0(n3413), .B1(intDY[20]),
.C0(n1970), .Y(n1971) );
AOI32X1TS U2539 ( .A0(n3479), .A1(n2190), .A2(intDY[50]), .B0(intDY[51]),
.B1(n3437), .Y(n2191) );
OAI221X1TS U2540 ( .A0(n3409), .A1(intDY[49]), .B0(n3479), .B1(intDY[50]),
.C0(n1941), .Y(n1944) );
OAI221XLTS U2541 ( .A0(n3402), .A1(intDY[11]), .B0(n3393), .B1(intDY[12]),
.C0(n1994), .Y(n1995) );
OAI221X1TS U2542 ( .A0(n3397), .A1(intDY[53]), .B0(n3334), .B1(intDY[54]),
.C0(n1939), .Y(n1946) );
OAI221XLTS U2543 ( .A0(n3396), .A1(intDY[23]), .B0(n3388), .B1(intDY[24]),
.C0(n1968), .Y(n1973) );
OAI221XLTS U2544 ( .A0(n3480), .A1(intDY[55]), .B0(n3385), .B1(intDY[56]),
.C0(n1940), .Y(n1945) );
OAI221X1TS U2545 ( .A0(n3411), .A1(intDY[17]), .B0(n3338), .B1(intDY[18]),
.C0(n1969), .Y(n1972) );
AOI221X1TS U2546 ( .A0(n3425), .A1(intDY[46]), .B0(intDY[45]), .B1(n3478),
.C0(n1959), .Y(n1966) );
OAI221X1TS U2547 ( .A0(n3412), .A1(intDY[25]), .B0(n3339), .B1(intDY[26]),
.C0(n1977), .Y(n1980) );
AOI221X1TS U2548 ( .A0(n3477), .A1(intDY[58]), .B0(intDY[57]), .B1(n3420),
.C0(n1937), .Y(n1949) );
AOI221X1TS U2549 ( .A0(n3423), .A1(intDY[36]), .B0(intDY[35]), .B1(n3340),
.C0(n1954), .Y(n1955) );
OAI221X1TS U2550 ( .A0(n3329), .A1(intDY[5]), .B0(n3401), .B1(intDY[6]),
.C0(n1983), .Y(n1990) );
OAI21XLTS U2551 ( .A0(n3329), .A1(n2415), .B0(n2356), .Y(n1110) );
OAI21XLTS U2552 ( .A0(n3392), .A1(n2415), .B0(n2357), .Y(n1109) );
NAND2X2TS U2553 ( .A(n1806), .B(n1793), .Y(n3266) );
NOR2X2TS U2554 ( .A(n3318), .B(FS_Module_state_reg[3]), .Y(n1806) );
XOR2XLTS U2555 ( .A(n2793), .B(n2794), .Y(n2792) );
NOR2X1TS U2556 ( .A(n2793), .B(n2795), .Y(n1692) );
NOR2X2TS U2557 ( .A(n1683), .B(n1682), .Y(n2793) );
AOI31XLTS U2558 ( .A0(n2012), .A1(n2011), .A2(n2010), .B0(n3262), .Y(n1560)
);
AOI211X1TS U2559 ( .A0(FS_Module_state_reg[1]), .A1(n3262), .B0(n1796), .C0(
n1795), .Y(n1803) );
OAI21X2TS U2560 ( .A0(beg_FSM), .A1(n1360), .B0(n3271), .Y(n3262) );
NOR2X2TS U2561 ( .A(n2011), .B(n3318), .Y(n2460) );
BUFX4TS U2562 ( .A(n3516), .Y(n3487) );
BUFX4TS U2563 ( .A(n1610), .Y(n3516) );
INVX2TS U2564 ( .A(intDX[43]), .Y(n2155) );
OAI21X2TS U2565 ( .A0(n3320), .A1(n1807), .B0(n1860), .Y(n2013) );
OAI21X4TS U2566 ( .A0(n3363), .A1(n1807), .B0(n1864), .Y(n3093) );
OAI21X4TS U2567 ( .A0(n3449), .A1(n1807), .B0(n1911), .Y(n3056) );
OAI21X4TS U2568 ( .A0(n3452), .A1(n1807), .B0(n1825), .Y(n3030) );
OR2X4TS U2569 ( .A(n2673), .B(n1807), .Y(n2548) );
CLKINVX3TS U2570 ( .A(n2019), .Y(n2291) );
NOR2XLTS U2571 ( .A(n2312), .B(n3257), .Y(n2211) );
NOR4X2TS U2572 ( .A(n2006), .B(n2005), .C(n2004), .D(n2003), .Y(n3257) );
BUFX4TS U2573 ( .A(n3148), .Y(n3071) );
INVX4TS U2574 ( .A(n2395), .Y(n2439) );
BUFX4TS U2575 ( .A(n2315), .Y(n2380) );
INVX2TS U2576 ( .A(n1828), .Y(n1643) );
BUFX3TS U2577 ( .A(n1813), .Y(n3067) );
AOI22X2TS U2578 ( .A0(LZA_output[4]), .A1(n1810), .B0(n1577), .B1(
exp_oper_result[4]), .Y(n1875) );
AOI211X1TS U2579 ( .A0(n2672), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(n2671), .C0(n2670), .Y(n2674) );
AOI211X2TS U2580 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[75]), .A1(
n2279), .B0(n2538), .C0(n2044), .Y(n2263) );
AOI211X2TS U2581 ( .A0(n2279), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(n2538), .C0(n2271), .Y(n2298) );
AOI211X2TS U2582 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[74]), .A1(
n2279), .B0(n2538), .C0(n1870), .Y(n2215) );
OAI21X2TS U2583 ( .A0(n3458), .A1(n1821), .B0(n3204), .Y(n3240) );
INVX2TS U2584 ( .A(n1848), .Y(n1644) );
AOI222X4TS U2585 ( .A0(n3034), .A1(n1643), .B0(n3056), .B1(n1644), .C0(n3046), .C1(n3062), .Y(n3044) );
AOI222X1TS U2586 ( .A0(n3046), .A1(n1643), .B0(n3034), .B1(n1644), .C0(n3042), .C1(n3062), .Y(n3040) );
AOI222X1TS U2587 ( .A0(n3059), .A1(n1643), .B0(n3063), .B1(n1815), .C0(n3034), .C1(n1628), .Y(n3053) );
AOI222X4TS U2588 ( .A0(n3056), .A1(n3067), .B0(n3059), .B1(n1815), .C0(n3034), .C1(n3062), .Y(n3048) );
AOI222X1TS U2589 ( .A0(n3066), .A1(n3067), .B0(n3087), .B1(n1815), .C0(n3082), .C1(n3062), .Y(n3080) );
AOI222X1TS U2590 ( .A0(n3087), .A1(n3067), .B0(n3075), .B1(n1815), .C0(n3066), .C1(n3062), .Y(n3085) );
AOI222X1TS U2591 ( .A0(n2013), .A1(n3067), .B0(n3086), .B1(n1815), .C0(n3081), .C1(n3062), .Y(n3078) );
INVX4TS U2592 ( .A(n2669), .Y(n2304) );
INVX3TS U2593 ( .A(n3294), .Y(n3301) );
BUFX4TS U2594 ( .A(n1900), .Y(n1645) );
NOR2X2TS U2595 ( .A(Add_Subt_result[40]), .B(Add_Subt_result[39]), .Y(n3279)
);
OAI2BB1X2TS U2596 ( .A0N(Add_Subt_result[39]), .A1N(n3161), .B0(n3037), .Y(
n3050) );
OAI2BB1X2TS U2597 ( .A0N(Add_Subt_result[37]), .A1N(n3161), .B0(n3045), .Y(
n3076) );
AOI32X1TS U2598 ( .A0(Add_Subt_result[11]), .A1(n2768), .A2(n3449), .B0(
Add_Subt_result[13]), .B1(n2768), .Y(n2769) );
OAI2BB1X2TS U2599 ( .A0N(Add_Subt_result[36]), .A1N(n3161), .B0(n3049), .Y(
n3082) );
NOR2X1TS U2600 ( .A(Add_Subt_result[50]), .B(Add_Subt_result[49]), .Y(n2648)
);
OAI211XLTS U2601 ( .A0(Add_Subt_result[42]), .A1(Add_Subt_result[40]), .B0(
n2632), .C0(n3445), .Y(n2633) );
OAI2BB1X2TS U2602 ( .A0N(Add_Subt_result[45]), .A1N(n1808), .B0(n1809), .Y(
n3042) );
OAI21XLTS U2603 ( .A0(Add_Subt_result[10]), .A1(Add_Subt_result[13]), .B0(
n2768), .Y(n2585) );
NOR3X4TS U2604 ( .A(Add_Subt_result[8]), .B(Add_Subt_result[7]), .C(n2576),
.Y(n2629) );
OAI221X1TS U2605 ( .A0(n3400), .A1(intDY[9]), .B0(n3330), .B1(intDY[10]),
.C0(n1993), .Y(n1996) );
AOI32X1TS U2606 ( .A0(n3338), .A1(n2120), .A2(intDY[18]), .B0(intDY[19]),
.B1(n3435), .Y(n2121) );
OAI221XLTS U2607 ( .A0(n3437), .A1(intDY[51]), .B0(n3386), .B1(intDY[52]),
.C0(n1942), .Y(n1943) );
OAI211XLTS U2608 ( .A0(intDY[8]), .A1(n3410), .B0(n2100), .C0(n2103), .Y(
n2112) );
OAI221XLTS U2609 ( .A0(n3390), .A1(intDY[7]), .B0(n3410), .B1(intDY[8]),
.C0(n1984), .Y(n1989) );
OAI21XLTS U2610 ( .A0(intDY[29]), .A1(n3407), .B0(intDY[28]), .Y(n2072) );
OAI21XLTS U2611 ( .A0(intDY[13]), .A1(n3406), .B0(intDY[12]), .Y(n2097) );
OAI21XLTS U2612 ( .A0(intDY[23]), .A1(n3396), .B0(intDY[22]), .Y(n2125) );
OAI21XLTS U2613 ( .A0(intDY[15]), .A1(n3528), .B0(intDY[14]), .Y(n2106) );
OAI221XLTS U2614 ( .A0(n3528), .A1(intDY[15]), .B0(n3391), .B1(intDY[16]),
.C0(n1992), .Y(n1997) );
OAI21XLTS U2615 ( .A0(intDY[41]), .A1(n3422), .B0(intDY[40]), .Y(n2154) );
OAI21XLTS U2616 ( .A0(intDY[43]), .A1(n2155), .B0(intDY[42]), .Y(n2156) );
OAI21XLTS U2617 ( .A0(intDY[33]), .A1(n3421), .B0(intDY[32]), .Y(n2170) );
OAI21XLTS U2618 ( .A0(intDY[53]), .A1(n3397), .B0(intDY[52]), .Y(n2184) );
OAI21XLTS U2619 ( .A0(intDY[3]), .A1(n3403), .B0(intDY[2]), .Y(n2090) );
OAI211XLTS U2620 ( .A0(n3403), .A1(intDY[3]), .B0(n2089), .C0(n2088), .Y(
n2092) );
OAI221XLTS U2621 ( .A0(n3403), .A1(intDY[3]), .B0(n3392), .B1(intDY[4]),
.C0(n1986), .Y(n1987) );
AND2X2TS U2622 ( .A(n1794), .B(n1793), .Y(n1646) );
OAI21XLTS U2623 ( .A0(intDX[1]), .A1(n3366), .B0(intDX[0]), .Y(n2087) );
OAI21XLTS U2624 ( .A0(intDY[35]), .A1(n3340), .B0(intDY[34]), .Y(n2171) );
NOR2XLTS U2625 ( .A(n2188), .B(intDX[48]), .Y(n2189) );
NOR2XLTS U2626 ( .A(n2118), .B(intDX[16]), .Y(n2119) );
OAI21XLTS U2627 ( .A0(intDY[21]), .A1(n3408), .B0(intDY[20]), .Y(n2117) );
NOR2XLTS U2628 ( .A(n1753), .B(n3358), .Y(n1710) );
INVX2TS U2629 ( .A(n2919), .Y(n2922) );
NAND2X1TS U2630 ( .A(n2955), .B(n1784), .Y(n1786) );
OAI21XLTS U2631 ( .A0(n2224), .A1(n3523), .B0(n2223), .Y(n2027) );
OAI21XLTS U2632 ( .A0(n2669), .A1(n3523), .B0(n2501), .Y(n2502) );
AFHCINX2TS U2633 ( .CIN(n2554), .B(n2555), .A(n2556), .S(n2557), .CO(n2675)
);
OAI21XLTS U2634 ( .A0(n2007), .A1(n3471), .B0(n2212), .Y(n1167) );
OAI21XLTS U2635 ( .A0(n3403), .A1(n2415), .B0(n2368), .Y(n1108) );
XNOR2X2TS U2636 ( .A(intAS), .B(intDY[63]), .Y(n2209) );
NOR2X4TS U2637 ( .A(n3259), .B(n1748), .Y(n1680) );
NOR2BX1TS U2638 ( .AN(Sgf_normalized_result[54]), .B(n2592), .Y(n1647) );
XOR2X1TS U2639 ( .A(n1687), .B(n1647), .Y(n2689) );
INVX4TS U2640 ( .A(n3475), .Y(n1745) );
XOR2X1TS U2641 ( .A(n1687), .B(n1648), .Y(n2693) );
MX2X1TS U2642 ( .A(DMP[50]), .B(Sgf_normalized_result[52]), .S0(n1756), .Y(
n2681) );
XOR2X1TS U2643 ( .A(n1687), .B(n1649), .Y(n2680) );
XOR2X1TS U2644 ( .A(n1687), .B(n1650), .Y(n2676) );
MX2X1TS U2645 ( .A(DMP[48]), .B(Sgf_normalized_result[50]), .S0(n1662), .Y(
n2556) );
XOR2X1TS U2646 ( .A(n1687), .B(n1651), .Y(n2555) );
XOR2X1TS U2647 ( .A(n1687), .B(n1652), .Y(n2551) );
MX2X1TS U2648 ( .A(DMP[46]), .B(Sgf_normalized_result[48]), .S0(n2592), .Y(
n2685) );
XOR2X1TS U2649 ( .A(n1687), .B(n1653), .Y(n2684) );
XOR2X1TS U2650 ( .A(n1687), .B(n1654), .Y(n2717) );
MX2X1TS U2651 ( .A(DMP[44]), .B(Sgf_normalized_result[46]), .S0(n1756), .Y(
n2714) );
XOR2X1TS U2652 ( .A(n1687), .B(n1655), .Y(n2713) );
XOR2X1TS U2653 ( .A(n1687), .B(n1656), .Y(n2708) );
MX2X1TS U2654 ( .A(DMP[42]), .B(Sgf_normalized_result[44]), .S0(n1607), .Y(
n2705) );
XOR2X1TS U2655 ( .A(n1687), .B(n1657), .Y(n2704) );
XOR2X1TS U2656 ( .A(n1676), .B(n1658), .Y(n2725) );
XOR2X1TS U2657 ( .A(n1687), .B(n1659), .Y(n2721) );
XOR2X1TS U2658 ( .A(n1676), .B(n1660), .Y(n2729) );
XOR2X1TS U2659 ( .A(n1676), .B(n1661), .Y(n2700) );
XOR2X1TS U2660 ( .A(n1676), .B(n1663), .Y(n2696) );
XOR2X1TS U2661 ( .A(n1676), .B(n1664), .Y(n2733) );
XOR2X1TS U2662 ( .A(n1676), .B(n1665), .Y(n2737) );
XOR2X1TS U2663 ( .A(n1676), .B(n1666), .Y(n2741) );
XOR2X1TS U2664 ( .A(n1676), .B(n1667), .Y(n2745) );
XOR2X1TS U2665 ( .A(n1676), .B(n1668), .Y(n2757) );
XOR2X1TS U2666 ( .A(n1676), .B(n1669), .Y(n2753) );
XOR2X1TS U2667 ( .A(n1676), .B(n1670), .Y(n2749) );
INVX4TS U2668 ( .A(n1671), .Y(n1753) );
XOR2X1TS U2669 ( .A(n1676), .B(n1672), .Y(n2951) );
XOR2X1TS U2670 ( .A(n1676), .B(n1673), .Y(n2970) );
XOR2X1TS U2671 ( .A(n1676), .B(n1674), .Y(n2974) );
XOR2X1TS U2672 ( .A(n1676), .B(n1675), .Y(n2761) );
BUFX8TS U2673 ( .A(n1680), .Y(n1755) );
XOR2X1TS U2674 ( .A(n1755), .B(n1677), .Y(n2987) );
XOR2X1TS U2675 ( .A(n1755), .B(n1678), .Y(n2982) );
XOR2X1TS U2676 ( .A(n1755), .B(n1679), .Y(n2978) );
XOR2X1TS U2677 ( .A(n1787), .B(n1681), .Y(n1683) );
OR2X1TS U2678 ( .A(n1753), .B(Sgf_normalized_result[2]), .Y(n1684) );
XOR2X1TS U2679 ( .A(n1787), .B(n1684), .Y(n1690) );
NOR2X1TS U2680 ( .A(n1690), .B(n1689), .Y(n2795) );
XOR2X1TS U2681 ( .A(n1680), .B(n1685), .Y(n2787) );
INVX2TS U2682 ( .A(n2787), .Y(n1688) );
NOR2X1TS U2683 ( .A(n1687), .B(n1686), .Y(n2788) );
NOR2X1TS U2684 ( .A(n1688), .B(n2788), .Y(n2790) );
NAND2X1TS U2685 ( .A(n1690), .B(n1689), .Y(n2796) );
INVX2TS U2686 ( .A(n2796), .Y(n1691) );
NOR2BX1TS U2687 ( .AN(Sgf_normalized_result[3]), .B(n1662), .Y(n1693) );
XOR2X1TS U2688 ( .A(n1787), .B(n1693), .Y(n1698) );
NOR2X1TS U2689 ( .A(n1698), .B(n1697), .Y(n2802) );
NOR2BX1TS U2690 ( .AN(Sgf_normalized_result[4]), .B(n1745), .Y(n1694) );
XOR2X1TS U2691 ( .A(n1787), .B(n1694), .Y(n1700) );
NOR2X2TS U2692 ( .A(n1700), .B(n1699), .Y(n2808) );
NOR2X1TS U2693 ( .A(n2802), .B(n2808), .Y(n2815) );
NOR2BX1TS U2694 ( .AN(Sgf_normalized_result[5]), .B(n1745), .Y(n1695) );
XOR2X1TS U2695 ( .A(n1787), .B(n1695), .Y(n1702) );
NOR2X2TS U2696 ( .A(n1702), .B(n1701), .Y(n2821) );
NOR2BX1TS U2697 ( .AN(Sgf_normalized_result[6]), .B(n1752), .Y(n1696) );
XOR2X1TS U2698 ( .A(n1787), .B(n1696), .Y(n1704) );
NOR2X2TS U2699 ( .A(n1704), .B(n1703), .Y(n2823) );
NOR2X1TS U2700 ( .A(n2821), .B(n2823), .Y(n1706) );
NAND2X1TS U2701 ( .A(n2815), .B(n1706), .Y(n1708) );
NAND2X1TS U2702 ( .A(n1698), .B(n1697), .Y(n2805) );
NAND2X1TS U2703 ( .A(n1700), .B(n1699), .Y(n2809) );
OAI21X1TS U2704 ( .A0(n2808), .A1(n2805), .B0(n2809), .Y(n2814) );
NAND2X1TS U2705 ( .A(n1702), .B(n1701), .Y(n2820) );
NAND2X1TS U2706 ( .A(n1704), .B(n1703), .Y(n2824) );
AOI21X1TS U2707 ( .A0(n2814), .A1(n1706), .B0(n1705), .Y(n1707) );
NOR2BX1TS U2708 ( .AN(Sgf_normalized_result[7]), .B(n1662), .Y(n1709) );
XOR2X1TS U2709 ( .A(n1787), .B(n1710), .Y(n1720) );
NOR2X2TS U2710 ( .A(n1720), .B(n1719), .Y(n2835) );
NOR2X1TS U2711 ( .A(n2834), .B(n2835), .Y(n2841) );
XOR2X1TS U2712 ( .A(n1787), .B(n1711), .Y(n1722) );
NOR2X1TS U2713 ( .A(n1722), .B(n1721), .Y(n2845) );
XOR2X1TS U2714 ( .A(n1787), .B(n1712), .Y(n1724) );
NOR2X2TS U2715 ( .A(n1724), .B(n1723), .Y(n2852) );
NOR2X1TS U2716 ( .A(n2845), .B(n2852), .Y(n1726) );
NAND2X1TS U2717 ( .A(n2841), .B(n1726), .Y(n2859) );
XOR2X1TS U2718 ( .A(n1787), .B(n1713), .Y(n1728) );
NOR2X1TS U2719 ( .A(n1728), .B(n1727), .Y(n2861) );
NOR2BX1TS U2720 ( .AN(Sgf_normalized_result[12]), .B(n1752), .Y(n1714) );
XOR2X1TS U2721 ( .A(n1787), .B(n1714), .Y(n1730) );
NOR2X2TS U2722 ( .A(n1730), .B(n1729), .Y(n2868) );
NOR2X1TS U2723 ( .A(n2861), .B(n2868), .Y(n2874) );
NOR2BX1TS U2724 ( .AN(Sgf_normalized_result[13]), .B(n1756), .Y(n1715) );
XOR2X1TS U2725 ( .A(n1755), .B(n1715), .Y(n1732) );
NOR2X1TS U2726 ( .A(n1732), .B(n1731), .Y(n2879) );
NOR2BX1TS U2727 ( .AN(Sgf_normalized_result[14]), .B(n1756), .Y(n1716) );
XOR2X1TS U2728 ( .A(n1755), .B(n1716), .Y(n1734) );
NOR2X2TS U2729 ( .A(n1734), .B(n1733), .Y(n2886) );
NOR2X1TS U2730 ( .A(n2879), .B(n2886), .Y(n1736) );
NAND2X1TS U2731 ( .A(n2874), .B(n1736), .Y(n1738) );
NOR2X1TS U2732 ( .A(n2859), .B(n1738), .Y(n1740) );
NAND2X1TS U2733 ( .A(n1718), .B(n1717), .Y(n2833) );
NAND2X1TS U2734 ( .A(n1720), .B(n1719), .Y(n2836) );
OAI21X1TS U2735 ( .A0(n2835), .A1(n2833), .B0(n2836), .Y(n2842) );
NAND2X1TS U2736 ( .A(n1722), .B(n1721), .Y(n2848) );
NAND2X1TS U2737 ( .A(n1724), .B(n1723), .Y(n2853) );
OAI21X1TS U2738 ( .A0(n2852), .A1(n2848), .B0(n2853), .Y(n1725) );
AOI21X1TS U2739 ( .A0(n2842), .A1(n1726), .B0(n1725), .Y(n2858) );
NAND2X1TS U2740 ( .A(n1728), .B(n1727), .Y(n2864) );
NAND2X1TS U2741 ( .A(n1730), .B(n1729), .Y(n2869) );
OAI21X1TS U2742 ( .A0(n2868), .A1(n2864), .B0(n2869), .Y(n2875) );
NAND2X1TS U2743 ( .A(n1732), .B(n1731), .Y(n2882) );
NAND2X1TS U2744 ( .A(n1734), .B(n1733), .Y(n2887) );
AOI21X1TS U2745 ( .A0(n2875), .A1(n1736), .B0(n1735), .Y(n1737) );
OAI21X1TS U2746 ( .A0(n2858), .A1(n1738), .B0(n1737), .Y(n1739) );
XOR2X1TS U2747 ( .A(n1755), .B(n1741), .Y(n1758) );
NOR2X1TS U2748 ( .A(n1758), .B(n1757), .Y(n2893) );
NOR2BX1TS U2749 ( .AN(Sgf_normalized_result[16]), .B(n1745), .Y(n1742) );
XOR2X1TS U2750 ( .A(n1755), .B(n1742), .Y(n1760) );
NOR2X2TS U2751 ( .A(n1760), .B(n1759), .Y(n2899) );
NOR2X1TS U2752 ( .A(n2893), .B(n2899), .Y(n2906) );
NOR2BX1TS U2753 ( .AN(n1634), .B(n2595), .Y(n1743) );
XOR2X1TS U2754 ( .A(n1755), .B(n1743), .Y(n1762) );
NOR2X2TS U2755 ( .A(n1762), .B(n1761), .Y(n2911) );
NOR2BX1TS U2756 ( .AN(n1633), .B(n1752), .Y(n1744) );
XOR2X1TS U2757 ( .A(n1755), .B(n1744), .Y(n1764) );
NOR2X2TS U2758 ( .A(n1764), .B(n1763), .Y(n2913) );
NOR2X1TS U2759 ( .A(n2911), .B(n2913), .Y(n1766) );
NAND2X1TS U2760 ( .A(n2906), .B(n1766), .Y(n2919) );
NOR2BX1TS U2761 ( .AN(n1632), .B(n2592), .Y(n1746) );
XOR2X1TS U2762 ( .A(n1755), .B(n1746), .Y(n1768) );
NOR2X2TS U2763 ( .A(n1768), .B(n1767), .Y(n2927) );
NOR2BX1TS U2764 ( .AN(n1631), .B(n2595), .Y(n1747) );
XOR2X1TS U2765 ( .A(n1755), .B(n1747), .Y(n1770) );
NOR2X2TS U2766 ( .A(n1770), .B(n1769), .Y(n2929) );
NOR2X1TS U2767 ( .A(n2927), .B(n2929), .Y(n2936) );
XOR2X1TS U2768 ( .A(n1755), .B(n1749), .Y(n1772) );
NOR2X2TS U2769 ( .A(n1772), .B(n1771), .Y(n2942) );
XOR2X1TS U2770 ( .A(n1755), .B(n1750), .Y(n1774) );
NOR2X2TS U2771 ( .A(n1774), .B(n1773), .Y(n2944) );
XOR2X1TS U2772 ( .A(n1755), .B(n1751), .Y(n1780) );
NOR2X2TS U2773 ( .A(n1780), .B(n1779), .Y(n2961) );
XOR2X1TS U2774 ( .A(n1755), .B(n1754), .Y(n1782) );
NOR2X2TS U2775 ( .A(n1782), .B(n1781), .Y(n2963) );
NAND2X1TS U2776 ( .A(n1758), .B(n1757), .Y(n2896) );
NAND2X1TS U2777 ( .A(n1760), .B(n1759), .Y(n2900) );
OAI21X1TS U2778 ( .A0(n2899), .A1(n2896), .B0(n2900), .Y(n2905) );
NAND2X1TS U2779 ( .A(n1762), .B(n1761), .Y(n2910) );
NAND2X1TS U2780 ( .A(n1764), .B(n1763), .Y(n2914) );
OAI21X1TS U2781 ( .A0(n2913), .A1(n2910), .B0(n2914), .Y(n1765) );
AOI21X1TS U2782 ( .A0(n2905), .A1(n1766), .B0(n1765), .Y(n2920) );
NAND2X1TS U2783 ( .A(n1768), .B(n1767), .Y(n2926) );
NAND2X1TS U2784 ( .A(n1770), .B(n1769), .Y(n2930) );
OAI21X1TS U2785 ( .A0(n2929), .A1(n2926), .B0(n2930), .Y(n2935) );
NAND2X1TS U2786 ( .A(n1772), .B(n1771), .Y(n2941) );
NAND2X1TS U2787 ( .A(n1774), .B(n1773), .Y(n2945) );
AOI21X1TS U2788 ( .A0(n2935), .A1(n1776), .B0(n1775), .Y(n1777) );
OAI21X1TS U2789 ( .A0(n2920), .A1(n1778), .B0(n1777), .Y(n2954) );
NAND2X1TS U2790 ( .A(n1780), .B(n1779), .Y(n2960) );
NAND2X1TS U2791 ( .A(n1782), .B(n1781), .Y(n2964) );
AOI21X1TS U2792 ( .A0(n2954), .A1(n1784), .B0(n1783), .Y(n1785) );
XOR2X4TS U2793 ( .A(n1788), .B(n1787), .Y(n1789) );
AND2X2TS U2794 ( .A(n1806), .B(FS_Module_state_reg[1]), .Y(n3254) );
NAND2X1TS U2795 ( .A(n3377), .B(n1790), .Y(n2011) );
OR2X2TS U2796 ( .A(n2011), .B(FS_Module_state_reg[2]), .Y(n1360) );
NOR4X1TS U2797 ( .A(FS_Module_state_reg[0]), .B(n3318), .C(n3321), .D(n3327),
.Y(ready) );
NOR2X1TS U2798 ( .A(FS_Module_state_reg[1]), .B(n3377), .Y(n1793) );
NOR2XLTS U2799 ( .A(FSM_selector_C), .B(n3266), .Y(n1796) );
NOR2X1TS U2800 ( .A(n3321), .B(n3377), .Y(n2385) );
AND2X2TS U2801 ( .A(n2385), .B(n1791), .Y(n3298) );
BUFX3TS U2802 ( .A(n3298), .Y(n3294) );
INVX4TS U2803 ( .A(n2007), .Y(n2396) );
NAND3X1TS U2804 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[1]),
.C(n3318), .Y(n3263) );
NAND2BX1TS U2805 ( .AN(n3263), .B(n3377), .Y(n2010) );
INVX4TS U2806 ( .A(n1646), .Y(n3303) );
NAND4XLTS U2807 ( .A(n3301), .B(n2396), .C(n2010), .D(n3303), .Y(n1795) );
INVX2TS U2808 ( .A(r_mode[0]), .Y(n1797) );
NAND2X1TS U2809 ( .A(n1797), .B(sign_final_result), .Y(n1802) );
INVX2TS U2810 ( .A(r_mode[1]), .Y(n1798) );
NAND2X1TS U2811 ( .A(n1798), .B(n3471), .Y(n1801) );
OR2X1TS U2812 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n1800) );
NAND2X1TS U2813 ( .A(r_mode[0]), .B(r_mode[1]), .Y(n1799) );
NAND3X1TS U2814 ( .A(FS_Module_state_reg[3]), .B(n3318), .C(n3327), .Y(n3273) );
NOR2X2TS U2815 ( .A(n3377), .B(n3273), .Y(n3256) );
OAI211XLTS U2816 ( .A0(n3377), .A1(n2791), .B0(n1803), .C0(n2665), .Y(n1559)
);
INVX2TS U2817 ( .A(rst), .Y(n3521) );
BUFX3TS U2818 ( .A(n3510), .Y(n3514) );
CLKBUFX2TS U2819 ( .A(n3518), .Y(n3520) );
BUFX3TS U2820 ( .A(n3516), .Y(n3512) );
BUFX3TS U2821 ( .A(n3485), .Y(n3492) );
BUFX3TS U2822 ( .A(n3513), .Y(n3493) );
BUFX3TS U2823 ( .A(n3485), .Y(n3509) );
BUFX3TS U2824 ( .A(n3511), .Y(n3515) );
BUFX3TS U2825 ( .A(n3521), .Y(n3505) );
BUFX3TS U2826 ( .A(n3518), .Y(n3486) );
BUFX3TS U2827 ( .A(n3505), .Y(n3490) );
BUFX3TS U2828 ( .A(n3496), .Y(n3489) );
BUFX3TS U2829 ( .A(n3505), .Y(n3501) );
BUFX3TS U2830 ( .A(n3511), .Y(n3500) );
BUFX3TS U2831 ( .A(n3505), .Y(n3508) );
BUFX3TS U2832 ( .A(n3511), .Y(n3499) );
BUFX3TS U2833 ( .A(n3521), .Y(n3504) );
BUFX3TS U2834 ( .A(n3516), .Y(n3488) );
BUFX3TS U2835 ( .A(n3483), .Y(n3485) );
BUFX3TS U2836 ( .A(n3509), .Y(n3507) );
BUFX3TS U2837 ( .A(n3367), .Y(n3269) );
OAI21XLTS U2838 ( .A0(n2791), .A1(FS_Module_state_reg[0]), .B0(n3153), .Y(
n1557) );
AOI21X1TS U2839 ( .A0(n3471), .A1(n3346), .B0(overflow_flag), .Y(n1804) );
AO22XLTS U2840 ( .A0(n3294), .A1(n1804), .B0(n3297), .B1(
final_result_ieee[63]), .Y(n1361) );
BUFX3TS U2841 ( .A(n3510), .Y(n3503) );
NOR2X2TS U2842 ( .A(FS_Module_state_reg[0]), .B(n3273), .Y(n3290) );
NAND2X1TS U2843 ( .A(add_overflow_flag), .B(n3290), .Y(n1805) );
OAI211XLTS U2844 ( .A0(n3290), .A1(n3473), .B0(n1805), .C0(n2010), .Y(n1439)
);
BUFX4TS U2845 ( .A(n1821), .Y(n3219) );
AOI22X1TS U2846 ( .A0(n3139), .A1(Add_Subt_result[9]), .B0(DmP[43]), .B1(
n3216), .Y(n1809) );
NAND2X1TS U2847 ( .A(n1810), .B(LZA_output[0]), .Y(n1812) );
NAND2X1TS U2848 ( .A(n3380), .B(FSM_selector_B[1]), .Y(n1811) );
NAND2X1TS U2849 ( .A(n1812), .B(n1811), .Y(n2569) );
AOI21X2TS U2850 ( .A0(exp_oper_result[0]), .A1(n3380), .B0(n2569), .Y(n1917)
);
AOI22X2TS U2851 ( .A0(n1616), .A1(n1810), .B0(n1577), .B1(exp_oper_result[1]), .Y(n3110) );
INVX2TS U2852 ( .A(n3110), .Y(n1932) );
INVX4TS U2853 ( .A(n1821), .Y(n3228) );
AOI22X1TS U2854 ( .A0(n3228), .A1(Add_Subt_result[44]), .B0(DmP[42]), .B1(
n3216), .Y(n1814) );
OAI21X2TS U2855 ( .A0(n3450), .A1(n1807), .B0(n1814), .Y(n3046) );
INVX2TS U2856 ( .A(n1917), .Y(n1915) );
AOI22X1TS U2857 ( .A0(n1608), .A1(Add_Subt_result[7]), .B0(DmP[45]), .B1(
n3216), .Y(n1816) );
OAI2BB1X2TS U2858 ( .A0N(Add_Subt_result[47]), .A1N(n3228), .B0(n1816), .Y(
n3021) );
AO22X2TS U2859 ( .A0(n1614), .A1(n1810), .B0(n1577), .B1(exp_oper_result[2]),
.Y(n3079) );
NOR2X1TS U2860 ( .A(n3110), .B(n1915), .Y(n1818) );
BUFX4TS U2861 ( .A(n1818), .Y(n3062) );
NAND2X1TS U2862 ( .A(n3095), .B(n3062), .Y(n2995) );
INVX2TS U2863 ( .A(n2995), .Y(n3051) );
NAND2X1TS U2864 ( .A(n3228), .B(Add_Subt_result[50]), .Y(n1820) );
AOI2BB2XLTS U2865 ( .B0(DmP[48]), .B1(n3269), .A0N(n1807), .A1N(n3458), .Y(
n1819) );
INVX2TS U2866 ( .A(n2999), .Y(n3020) );
INVX4TS U2867 ( .A(n3079), .Y(n3092) );
NAND2X2TS U2868 ( .A(n3092), .B(n3062), .Y(n2998) );
INVX2TS U2869 ( .A(n2998), .Y(n1863) );
INVX4TS U2870 ( .A(n1821), .Y(n3161) );
AOI22X1TS U2871 ( .A0(n3139), .A1(Add_Subt_result[8]), .B0(DmP[44]), .B1(
n3153), .Y(n1822) );
OAI2BB1X2TS U2872 ( .A0N(Add_Subt_result[46]), .A1N(n3161), .B0(n1822), .Y(
n3038) );
AOI22X1TS U2873 ( .A0(n3051), .A1(n3020), .B0(n1863), .B1(n3038), .Y(n1831)
);
NAND2X1TS U2874 ( .A(n3095), .B(n1628), .Y(n3002) );
NAND2X1TS U2875 ( .A(n3228), .B(Add_Subt_result[51]), .Y(n1824) );
AOI2BB2XLTS U2876 ( .B0(DmP[49]), .B1(n3216), .A0N(n1807), .A1N(n3459), .Y(
n1823) );
INVX2TS U2877 ( .A(n3005), .Y(n3019) );
AOI22X1TS U2878 ( .A0(n3228), .A1(Add_Subt_result[48]), .B0(DmP[46]), .B1(
n3153), .Y(n1825) );
INVX2TS U2879 ( .A(n3030), .Y(n3001) );
NAND2X2TS U2880 ( .A(n1815), .B(n3095), .Y(n2992) );
NAND2X1TS U2881 ( .A(n3228), .B(Add_Subt_result[49]), .Y(n1827) );
BUFX3TS U2882 ( .A(n1858), .Y(n3217) );
AOI22X1TS U2883 ( .A0(n3217), .A1(Add_Subt_result[5]), .B0(DmP[47]), .B1(
n3216), .Y(n1826) );
INVX4TS U2884 ( .A(n3079), .Y(n3111) );
INVX2TS U2885 ( .A(n3067), .Y(n1828) );
OR2X2TS U2886 ( .A(n3111), .B(n1828), .Y(n2993) );
OAI22X1TS U2887 ( .A0(n3001), .A1(n2992), .B0(n2997), .B1(n2993), .Y(n1829)
);
AOI21X1TS U2888 ( .A0(n3071), .A1(n3019), .B0(n1829), .Y(n1830) );
BUFX3TS U2889 ( .A(n3051), .Y(n3227) );
NAND2X1TS U2890 ( .A(n3228), .B(Add_Subt_result[52]), .Y(n1833) );
AOI2BB2XLTS U2891 ( .B0(DmP[50]), .B1(n3269), .A0N(n1807), .A1N(n3464), .Y(
n1832) );
AND2X2TS U2892 ( .A(n1833), .B(n1832), .Y(n3011) );
OAI22X1TS U2893 ( .A0(n3011), .A1(n3002), .B0(n2997), .B1(n2992), .Y(n1835)
);
NAND2X2TS U2894 ( .A(n3092), .B(n1628), .Y(n3004) );
OAI22X1TS U2895 ( .A0(n2999), .A1(n2993), .B0(n3001), .B1(n3004), .Y(n1834)
);
AOI211X1TS U2896 ( .A0(n3227), .A1(n3019), .B0(n1835), .C0(n1834), .Y(n1836)
);
NAND2X1TS U2897 ( .A(n2460), .B(FSM_selector_C), .Y(n1839) );
INVX2TS U2898 ( .A(n3263), .Y(n1837) );
NAND2X1TS U2899 ( .A(FS_Module_state_reg[0]), .B(n1837), .Y(n1838) );
NAND2X1TS U2900 ( .A(n1839), .B(n1838), .Y(n2394) );
NAND2X1TS U2901 ( .A(n1841), .B(n1840), .Y(n3272) );
OA21X2TS U2902 ( .A0(n2394), .A1(n3261), .B0(add_overflow_flag), .Y(n1920)
);
INVX2TS U2903 ( .A(n1920), .Y(n3003) );
NOR2X2TS U2904 ( .A(n3111), .B(n3003), .Y(n1921) );
INVX2TS U2905 ( .A(n1815), .Y(n1848) );
NAND2X2TS U2906 ( .A(n3092), .B(n3067), .Y(n2996) );
NAND2X1TS U2907 ( .A(n3228), .B(n3345), .Y(n1843) );
NAND2X1TS U2908 ( .A(n1608), .B(n3468), .Y(n1842) );
INVX2TS U2909 ( .A(n3014), .Y(n2994) );
OAI22X1TS U2910 ( .A0(n3005), .A1(n2996), .B0(n2992), .B1(n2994), .Y(n1847)
);
NAND2X2TS U2911 ( .A(n3111), .B(n1815), .Y(n3000) );
NAND2X1TS U2912 ( .A(n3228), .B(Add_Subt_result[53]), .Y(n1845) );
AOI2BB2XLTS U2913 ( .B0(DmP[51]), .B1(n3153), .A0N(n1807), .A1N(n3469), .Y(
n1844) );
AND2X2TS U2914 ( .A(n1845), .B(n1844), .Y(n3012) );
OAI22X1TS U2915 ( .A0(n2999), .A1(n3000), .B0(n3012), .B1(n3004), .Y(n1846)
);
AOI211X1TS U2916 ( .A0(n1921), .A1(n1848), .B0(n1847), .C0(n1846), .Y(n1849)
);
OAI22X1TS U2917 ( .A0(n3005), .A1(n3000), .B0(n3012), .B1(n2998), .Y(n1850)
);
AOI211X1TS U2918 ( .A0(n3248), .A1(n3014), .B0(n1921), .C0(n1850), .Y(n1851)
);
OAI22X1TS U2919 ( .A0(n3011), .A1(n3000), .B0(n2998), .B1(n2994), .Y(n1852)
);
AOI211X1TS U2920 ( .A0(n1628), .A1(n1920), .B0(n1921), .C0(n1852), .Y(n1853)
);
OAI22X1TS U2921 ( .A0(n3012), .A1(n2992), .B0(n2997), .B1(n3000), .Y(n1855)
);
OAI22X1TS U2922 ( .A0(n3011), .A1(n3004), .B0(n3005), .B1(n2998), .Y(n1854)
);
AOI211X1TS U2923 ( .A0(n1921), .A1(n1932), .B0(n1855), .C0(n1854), .Y(n1857)
);
NAND2X1TS U2924 ( .A(n3014), .B(n3237), .Y(n1856) );
AOI22X1TS U2925 ( .A0(n3217), .A1(Add_Subt_result[22]), .B0(DmP[30]), .B1(
n3269), .Y(n1859) );
AOI22X1TS U2926 ( .A0(Add_Subt_result[31]), .A1(n3228), .B0(DmP[29]), .B1(
n3153), .Y(n1860) );
AOI22X1TS U2927 ( .A0(n3217), .A1(n1642), .B0(DmP[31]), .B1(n3269), .Y(n1861) );
AOI22X1TS U2928 ( .A0(Add_Subt_result[24]), .A1(n3217), .B0(DmP[28]), .B1(
n3153), .Y(n1862) );
AOI22X1TS U2929 ( .A0(Add_Subt_result[29]), .A1(n3228), .B0(DmP[27]), .B1(
n3153), .Y(n1864) );
AOI22X1TS U2930 ( .A0(n3248), .A1(n3086), .B0(n1863), .B1(n3093), .Y(n1868)
);
AO22XLTS U2931 ( .A0(FSM_selector_C), .A1(Add_Subt_result[27]), .B0(n3269),
.B1(DmP[25]), .Y(n1916) );
AOI22X1TS U2932 ( .A0(Add_Subt_result[26]), .A1(n3217), .B0(DmP[26]), .B1(
n3269), .Y(n1865) );
NOR2X1TS U2933 ( .A(n1932), .B(n3102), .Y(n1896) );
AOI22X1TS U2934 ( .A0(n3217), .A1(Add_Subt_result[20]), .B0(DmP[32]), .B1(
n3054), .Y(n1866) );
AOI22X1TS U2935 ( .A0(n3111), .A1(n1896), .B0(n3071), .B1(n3087), .Y(n1867)
);
AOI22X2TS U2936 ( .A0(n1617), .A1(n1810), .B0(n1577), .B1(exp_oper_result[3]), .Y(n1874) );
INVX4TS U2937 ( .A(n1613), .Y(n2279) );
INVX2TS U2938 ( .A(n1875), .Y(n1869) );
NAND2X1TS U2939 ( .A(n1869), .B(n1874), .Y(n1877) );
INVX2TS U2940 ( .A(n1877), .Y(n2281) );
NAND2X2TS U2941 ( .A(n3266), .B(n3272), .Y(n2544) );
BUFX3TS U2942 ( .A(n2544), .Y(n2549) );
INVX4TS U2943 ( .A(n2549), .Y(n2673) );
INVX4TS U2944 ( .A(n2548), .Y(n2301) );
NAND2X1TS U2945 ( .A(n1810), .B(LZA_output[5]), .Y(n2563) );
NAND2X1TS U2946 ( .A(n1577), .B(exp_oper_result[5]), .Y(n1871) );
NAND2X2TS U2947 ( .A(n2563), .B(n1871), .Y(n2019) );
INVX4TS U2948 ( .A(n2019), .Y(n2308) );
NAND2X2TS U2949 ( .A(n1613), .B(n1920), .Y(n2272) );
NAND2X2TS U2950 ( .A(n2272), .B(n1613), .Y(n2282) );
NAND2X1TS U2951 ( .A(n2272), .B(n3525), .Y(n1873) );
INVX2TS U2952 ( .A(n2216), .Y(n2270) );
INVX2TS U2953 ( .A(n1625), .Y(n2224) );
AOI22X1TS U2954 ( .A0(n2495), .A1(n1639), .B0(n2294), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n1879) );
BUFX3TS U2955 ( .A(n2539), .Y(n2507) );
AOI22X1TS U2956 ( .A0(n2507), .A1(n1621), .B0(n2543), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(n1878) );
OAI211X1TS U2957 ( .A0(n2308), .A1(n2270), .B0(n1879), .C0(n1878), .Y(n1903)
);
NOR2X1TS U2958 ( .A(n2673), .B(n3217), .Y(n2058) );
INVX2TS U2959 ( .A(n2058), .Y(n1885) );
INVX2TS U2960 ( .A(n1885), .Y(n2496) );
AOI22X1TS U2961 ( .A0(n1903), .A1(n2496), .B0(n2673), .B1(n1631), .Y(n1880)
);
AO22XLTS U2962 ( .A0(n2281), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(n1625), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n1881) );
NAND2X1TS U2963 ( .A(n2272), .B(n3523), .Y(n1882) );
INVX2TS U2964 ( .A(n2052), .Y(n2257) );
AOI22X1TS U2965 ( .A0(n2495), .A1(n1636), .B0(n2294), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n1884) );
AOI22X1TS U2966 ( .A0(n2667), .A1(n1618), .B0(n2666), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(n1883) );
OAI211X1TS U2967 ( .A0(n2308), .A1(n2257), .B0(n1884), .C0(n1883), .Y(n1901)
);
AOI22X1TS U2968 ( .A0(n1901), .A1(n2063), .B0(n2673), .B1(n1634), .Y(n1886)
);
AO22XLTS U2969 ( .A0(n2281), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(n1625), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n1887) );
NAND2X1TS U2970 ( .A(n2272), .B(n3524), .Y(n1888) );
INVX2TS U2971 ( .A(n2042), .Y(n2260) );
AOI22X1TS U2972 ( .A0(n2495), .A1(n1637), .B0(n2294), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n1890) );
AOI22X1TS U2973 ( .A0(n2507), .A1(n1619), .B0(n2666), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(n1889) );
OAI211X1TS U2974 ( .A0(n2308), .A1(n2260), .B0(n1890), .C0(n1889), .Y(n1905)
);
AOI22X1TS U2975 ( .A0(n1905), .A1(n2496), .B0(n2673), .B1(n1633), .Y(n1891)
);
AOI22X1TS U2976 ( .A0(Add_Subt_result[30]), .A1(n1858), .B0(DmP[22]), .B1(
n3216), .Y(n1892) );
AOI22X1TS U2977 ( .A0(Add_Subt_result[31]), .A1(n1858), .B0(DmP[21]), .B1(
n3054), .Y(n1893) );
AOI22X1TS U2978 ( .A0(Add_Subt_result[29]), .A1(n1608), .B0(DmP[23]), .B1(
n3153), .Y(n1894) );
AOI22X1TS U2979 ( .A0(Add_Subt_result[28]), .A1(n3217), .B0(DmP[24]), .B1(
n3269), .Y(n1895) );
AOI22X1TS U2980 ( .A0(n3107), .A1(n3103), .B0(n3051), .B1(n3093), .Y(n1898)
);
AOI22X1TS U2981 ( .A0(n3148), .A1(n3086), .B0(n1896), .B1(n3095), .Y(n1897)
);
NOR2X4TS U2982 ( .A(n2308), .B(n3003), .Y(n2671) );
INVX4TS U2983 ( .A(n2549), .Y(n2310) );
AOI22X1TS U2984 ( .A0(n2310), .A1(Sgf_normalized_result[37]), .B0(n2301),
.B1(n1901), .Y(n1902) );
AOI22X1TS U2985 ( .A0(n2302), .A1(Sgf_normalized_result[34]), .B0(n2301),
.B1(n1903), .Y(n1904) );
AOI22X1TS U2986 ( .A0(n2310), .A1(Sgf_normalized_result[36]), .B0(n2301),
.B1(n1905), .Y(n1906) );
AOI22X1TS U2987 ( .A0(n3217), .A1(Add_Subt_result[11]), .B0(DmP[41]), .B1(
n3269), .Y(n1907) );
OAI2BB1X1TS U2988 ( .A0N(Add_Subt_result[43]), .A1N(n3161), .B0(n1907), .Y(
n3034) );
AOI22X1TS U2989 ( .A0(n3225), .A1(n3030), .B0(n3107), .B1(n3038), .Y(n1910)
);
INVX2TS U2990 ( .A(n2997), .Y(n3023) );
AOI21X1TS U2991 ( .A0(n3051), .A1(n3023), .B0(n1908), .Y(n1909) );
AOI22X1TS U2992 ( .A0(n3228), .A1(Add_Subt_result[42]), .B0(DmP[40]), .B1(
n3054), .Y(n1911) );
AOI22X1TS U2993 ( .A0(n3225), .A1(n3021), .B0(n3013), .B1(n3042), .Y(n1914)
);
AOI21X1TS U2994 ( .A0(n3051), .A1(n3030), .B0(n1912), .Y(n1913) );
AOI22X1TS U2995 ( .A0(n3107), .A1(n3093), .B0(n3242), .B1(n3094), .Y(n1919)
);
NOR2X1TS U2996 ( .A(n1932), .B(n3109), .Y(n3096) );
AOI22X1TS U2997 ( .A0(n3111), .A1(n3096), .B0(n3071), .B1(n3075), .Y(n1918)
);
AOI22X1TS U2998 ( .A0(n1920), .A1(n1932), .B0(n3244), .B1(n3014), .Y(n1923)
);
INVX2TS U2999 ( .A(n1921), .Y(n1922) );
AOI22X1TS U3000 ( .A0(n1858), .A1(Add_Subt_result[32]), .B0(DmP[20]), .B1(
n3054), .Y(n1924) );
OAI2BB1X2TS U3001 ( .A0N(Add_Subt_result[22]), .A1N(n3161), .B0(n1924), .Y(
n3134) );
AOI22X1TS U3002 ( .A0(n3139), .A1(Add_Subt_result[34]), .B0(DmP[18]), .B1(
n3153), .Y(n1925) );
OAI21X4TS U3003 ( .A0(n3440), .A1(n3219), .B0(n1925), .Y(n3147) );
AOI22X1TS U3004 ( .A0(n3248), .A1(n3134), .B0(n3244), .B1(n3147), .Y(n1930)
);
AOI22X1TS U3005 ( .A0(n1858), .A1(Add_Subt_result[33]), .B0(DmP[19]), .B1(
n3216), .Y(n1926) );
OAI2BB1X2TS U3006 ( .A0N(n1642), .A1N(n3161), .B0(n1926), .Y(n3141) );
AOI22X1TS U3007 ( .A0(n1608), .A1(Add_Subt_result[35]), .B0(DmP[17]), .B1(
n3153), .Y(n1927) );
OAI2BB1X2TS U3008 ( .A0N(Add_Subt_result[19]), .A1N(n3161), .B0(n1927), .Y(
n3155) );
AOI21X1TS U3009 ( .A0(n1863), .A1(n3141), .B0(n1928), .Y(n1929) );
AOI22X1TS U3010 ( .A0(n3239), .A1(n3116), .B0(n3244), .B1(n3103), .Y(n1934)
);
NAND2X1TS U3011 ( .A(n3111), .B(n1932), .Y(n2015) );
AOI22X1TS U3012 ( .A0(n3399), .A1(intDY[1]), .B0(n3335), .B1(intDY[61]), .Y(
n1935) );
OAI221XLTS U3013 ( .A0(n3399), .A1(intDY[1]), .B0(n3335), .B1(intDY[61]),
.C0(n1935), .Y(n1936) );
AOI221X1TS U3014 ( .A0(intDX[62]), .A1(n3336), .B0(n3431), .B1(intDY[62]),
.C0(n1936), .Y(n1950) );
OAI22X1TS U3015 ( .A0(n3477), .A1(intDY[58]), .B0(n3420), .B1(intDY[57]),
.Y(n1937) );
OAI22X1TS U3016 ( .A0(n3527), .A1(intDY[60]), .B0(n3436), .B1(intDY[59]),
.Y(n1938) );
AOI22X1TS U3017 ( .A0(n3397), .A1(intDY[53]), .B0(n3334), .B1(intDY[54]),
.Y(n1939) );
AOI22X1TS U3018 ( .A0(n3480), .A1(intDY[55]), .B0(n3385), .B1(intDY[56]),
.Y(n1940) );
AOI22X1TS U3019 ( .A0(n3409), .A1(intDY[49]), .B0(n3479), .B1(intDY[50]),
.Y(n1941) );
AOI22X1TS U3020 ( .A0(n3437), .A1(intDY[51]), .B0(n3386), .B1(intDY[52]),
.Y(n1942) );
NOR4X1TS U3021 ( .A(n1946), .B(n1945), .C(n1944), .D(n1943), .Y(n1947) );
NAND4XLTS U3022 ( .A(n1950), .B(n1949), .C(n1948), .D(n1947), .Y(n2006) );
OAI22X1TS U3023 ( .A0(n3429), .A1(intDY[38]), .B0(n3343), .B1(intDY[37]),
.Y(n1951) );
AOI221X1TS U3024 ( .A0(n3429), .A1(intDY[38]), .B0(intDY[37]), .B1(n3343),
.C0(n1951), .Y(n1958) );
OAI22X1TS U3025 ( .A0(n3428), .A1(intDY[40]), .B0(n3342), .B1(intDY[39]),
.Y(n1952) );
OAI22X1TS U3026 ( .A0(n3430), .A1(intDY[34]), .B0(n3421), .B1(intDY[33]),
.Y(n1953) );
OAI22X1TS U3027 ( .A0(n3423), .A1(intDY[36]), .B0(n3340), .B1(intDY[35]),
.Y(n1954) );
NAND4XLTS U3028 ( .A(n1958), .B(n1957), .C(n1956), .D(n1955), .Y(n2005) );
OAI22X1TS U3029 ( .A0(n3425), .A1(intDY[46]), .B0(n3478), .B1(intDY[45]),
.Y(n1959) );
OAI22X1TS U3030 ( .A0(n3424), .A1(intDY[48]), .B0(n3341), .B1(intDY[47]),
.Y(n1960) );
AOI221X1TS U3031 ( .A0(n3424), .A1(intDY[48]), .B0(intDY[47]), .B1(n3341),
.C0(n1960), .Y(n1965) );
OAI22X1TS U3032 ( .A0(n3427), .A1(intDY[42]), .B0(n3422), .B1(intDY[41]),
.Y(n1961) );
OAI22X1TS U3033 ( .A0(n3426), .A1(intDY[44]), .B0(n1590), .B1(intDY[43]),
.Y(n1962) );
NAND4XLTS U3034 ( .A(n1966), .B(n1965), .C(n1964), .D(n1963), .Y(n2004) );
AOI22X1TS U3035 ( .A0(n3408), .A1(intDY[21]), .B0(n3333), .B1(intDY[22]),
.Y(n1967) );
AOI22X1TS U3036 ( .A0(n3396), .A1(intDY[23]), .B0(n3388), .B1(intDY[24]),
.Y(n1968) );
AOI22X1TS U3037 ( .A0(n3411), .A1(intDY[17]), .B0(n3338), .B1(intDY[18]),
.Y(n1969) );
AOI22X1TS U3038 ( .A0(n3435), .A1(intDY[19]), .B0(n3413), .B1(intDY[20]),
.Y(n1970) );
NOR4X1TS U3039 ( .A(n1974), .B(n1973), .C(n1972), .D(n1971), .Y(n2002) );
AOI22X1TS U3040 ( .A0(n3407), .A1(intDY[29]), .B0(n3332), .B1(intDY[30]),
.Y(n1975) );
AOI22X1TS U3041 ( .A0(n3476), .A1(intDY[31]), .B0(n3387), .B1(intDY[32]),
.Y(n1976) );
AOI22X1TS U3042 ( .A0(n3412), .A1(intDY[25]), .B0(n3339), .B1(intDY[26]),
.Y(n1977) );
AOI22X1TS U3043 ( .A0(n3419), .A1(intDY[27]), .B0(n3418), .B1(intDY[28]),
.Y(n1978) );
NOR4X1TS U3044 ( .A(n1982), .B(n1981), .C(n1980), .D(n1979), .Y(n2001) );
AOI22X1TS U3045 ( .A0(n3329), .A1(intDY[5]), .B0(n3401), .B1(intDY[6]), .Y(
n1983) );
AOI22X1TS U3046 ( .A0(n3390), .A1(intDY[7]), .B0(n3410), .B1(intDY[8]), .Y(
n1984) );
AOI22X1TS U3047 ( .A0(n3337), .A1(intDY[2]), .B0(n3405), .B1(intDY[0]), .Y(
n1985) );
AOI22X1TS U3048 ( .A0(n3403), .A1(intDY[3]), .B0(n3392), .B1(intDY[4]), .Y(
n1986) );
NOR4X1TS U3049 ( .A(n1990), .B(n1989), .C(n1988), .D(n1987), .Y(n2000) );
AOI22X1TS U3050 ( .A0(n3406), .A1(intDY[13]), .B0(n3404), .B1(intDY[14]),
.Y(n1991) );
AOI22X1TS U3051 ( .A0(n3528), .A1(intDY[15]), .B0(n3391), .B1(intDY[16]),
.Y(n1992) );
AOI22X1TS U3052 ( .A0(n3400), .A1(intDY[9]), .B0(n3330), .B1(intDY[10]), .Y(
n1993) );
AOI22X1TS U3053 ( .A0(n3402), .A1(intDY[11]), .B0(n3393), .B1(intDY[12]),
.Y(n1994) );
NOR4X1TS U3054 ( .A(n1998), .B(n1997), .C(n1996), .D(n1995), .Y(n1999) );
NAND4XLTS U3055 ( .A(n2002), .B(n2001), .C(n2000), .D(n1999), .Y(n2003) );
INVX4TS U3056 ( .A(n2007), .Y(n2489) );
AOI21X1TS U3057 ( .A0(n3257), .A1(n2008), .B0(n2489), .Y(n2009) );
NOR3XLTS U3058 ( .A(n2009), .B(n3256), .C(n3261), .Y(n2012) );
AOI22X1TS U3059 ( .A0(n3246), .A1(n3086), .B0(n2014), .B1(n3122), .Y(n2017)
);
OAI21X1TS U3060 ( .A0(n2224), .A1(n3465), .B0(n2223), .Y(n2018) );
AOI22X1TS U3061 ( .A0(n2295), .A1(n1623), .B0(n2304), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(n2021) );
AOI22X1TS U3062 ( .A0(n2667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(n2666), .B1(n1641), .Y(n2020) );
INVX2TS U3063 ( .A(n1872), .Y(n2217) );
INVX2TS U3064 ( .A(n2023), .Y(n1456) );
OAI21X1TS U3065 ( .A0(n2224), .A1(n3466), .B0(n2223), .Y(n2024) );
AOI22X1TS U3066 ( .A0(n2295), .A1(n1622), .B0(n2304), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(n2026) );
AOI22X1TS U3067 ( .A0(n2667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(n2666), .B1(n1640), .Y(n2025) );
OAI211X1TS U3068 ( .A0(n2522), .A1(n2291), .B0(n2026), .C0(n2025), .Y(n2239)
);
INVX2TS U3069 ( .A(n2028), .Y(n1455) );
OAI21X1TS U3070 ( .A0(n2224), .A1(n3525), .B0(n2223), .Y(n2029) );
AOI22X1TS U3071 ( .A0(n2295), .A1(n1621), .B0(n2304), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(n2031) );
AOI22X1TS U3072 ( .A0(n2667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(n2666), .B1(n1639), .Y(n2030) );
OAI211X1TS U3073 ( .A0(n2519), .A1(n2308), .B0(n2031), .C0(n2030), .Y(n2236)
);
INVX2TS U3074 ( .A(n2033), .Y(n1454) );
INVX2TS U3075 ( .A(n2669), .Y(n2294) );
AOI22X1TS U3076 ( .A0(n2295), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(n2304), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(n2036) );
AOI22X1TS U3077 ( .A0(n2667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[62]), .B0(n2666), .B1(n1624), .Y(n2035) );
OAI211X1TS U3078 ( .A0(n2525), .A1(n2291), .B0(n2036), .C0(n2035), .Y(n2246)
);
NAND2X1TS U3079 ( .A(n2272), .B(n3472), .Y(n2037) );
CLKAND2X2TS U3080 ( .A(n2282), .B(n2037), .Y(n2242) );
INVX2TS U3081 ( .A(n2038), .Y(n1449) );
AOI22X1TS U3082 ( .A0(n2295), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(n2304), .B1(n1639), .Y(n2040) );
BUFX3TS U3083 ( .A(n2543), .Y(n2536) );
AOI22X1TS U3084 ( .A0(n2667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[59]), .B0(n2536), .B1(n1621), .Y(n2039) );
OAI211X1TS U3085 ( .A0(n2041), .A1(n2291), .B0(n2040), .C0(n2039), .Y(n2258)
);
INVX2TS U3086 ( .A(n2043), .Y(n1446) );
AO22XLTS U3087 ( .A0(n2281), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(n1625), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n2044) );
AOI22X1TS U3088 ( .A0(n2295), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(n2304), .B1(n1638), .Y(n2046) );
AOI22X1TS U3089 ( .A0(n2507), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[58]), .B0(n2536), .B1(n1620), .Y(n2045) );
OAI211X1TS U3090 ( .A0(n2263), .A1(n2291), .B0(n2046), .C0(n2045), .Y(n2249)
);
NAND2X1TS U3091 ( .A(n2272), .B(n3526), .Y(n2047) );
CLKAND2X2TS U3092 ( .A(n2282), .B(n2047), .Y(n2060) );
INVX2TS U3093 ( .A(n2048), .Y(n1445) );
AOI22X1TS U3094 ( .A0(n2295), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(n2304), .B1(n1640), .Y(n2050) );
AOI22X1TS U3095 ( .A0(n2507), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[60]), .B0(n2536), .B1(n1622), .Y(n2049) );
OAI211X1TS U3096 ( .A0(n2051), .A1(n2291), .B0(n2050), .C0(n2049), .Y(n2255)
);
INVX2TS U3097 ( .A(n2053), .Y(n1447) );
AOI22X1TS U3098 ( .A0(n2295), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(n2304), .B1(n1641), .Y(n2056) );
AOI22X1TS U3099 ( .A0(n2507), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[61]), .B0(n2536), .B1(n1623), .Y(n2055) );
NAND2X1TS U3100 ( .A(n2272), .B(n3522), .Y(n2057) );
CLKAND2X2TS U3101 ( .A(n2282), .B(n2057), .Y(n2252) );
AOI222X1TS U3102 ( .A0(n2253), .A1(n2058), .B0(n2217), .B1(n2252), .C0(n2302), .C1(Sgf_normalized_result[6]), .Y(n2059) );
INVX2TS U3103 ( .A(n2059), .Y(n1448) );
INVX2TS U3104 ( .A(n2060), .Y(n2251) );
AOI22X1TS U3105 ( .A0(n2295), .A1(n1638), .B0(n2304), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n2062) );
AOI22X1TS U3106 ( .A0(n2507), .A1(n1620), .B0(n2543), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(n2061) );
OAI211X1TS U3107 ( .A0(n2308), .A1(n2251), .B0(n2062), .C0(n2061), .Y(n2261)
);
AOI22X1TS U3108 ( .A0(n2261), .A1(n2063), .B0(n2673), .B1(n1632), .Y(n2064)
);
OAI22X1TS U3109 ( .A0(n3480), .A1(intDY[55]), .B0(intDY[54]), .B1(n3334),
.Y(n2185) );
AOI211X1TS U3110 ( .A0(intDX[52]), .A1(n3375), .B0(n2065), .C0(n2185), .Y(
n2187) );
NOR2BX1TS U3111 ( .AN(intDX[56]), .B(intDY[56]), .Y(n2066) );
NOR2X1TS U3112 ( .A(n3420), .B(intDY[57]), .Y(n2138) );
NAND2X1TS U3113 ( .A(n3364), .B(intDX[61]), .Y(n2144) );
OAI211X1TS U3114 ( .A0(intDY[60]), .A1(n3527), .B0(n2148), .C0(n2144), .Y(
n2150) );
OAI21X1TS U3115 ( .A0(intDY[58]), .A1(n3477), .B0(n2140), .Y(n2142) );
NOR2X1TS U3116 ( .A(n3409), .B(intDY[49]), .Y(n2188) );
OAI21X1TS U3117 ( .A0(intDY[50]), .A1(n3479), .B0(n2190), .Y(n2194) );
AOI211X1TS U3118 ( .A0(intDX[48]), .A1(n3372), .B0(n2188), .C0(n2194), .Y(
n2067) );
NAND3X1TS U3119 ( .A(n2187), .B(n2196), .C(n2067), .Y(n2204) );
NOR2BX1TS U3120 ( .AN(intDX[39]), .B(intDY[39]), .Y(n2179) );
AOI21X1TS U3121 ( .A0(intDX[38]), .A1(n3376), .B0(n2179), .Y(n2178) );
NAND2X1TS U3122 ( .A(n3378), .B(intDX[37]), .Y(n2167) );
OAI211X1TS U3123 ( .A0(intDY[36]), .A1(n3423), .B0(n2178), .C0(n2167), .Y(
n2169) );
NOR2X1TS U3124 ( .A(n3478), .B(intDY[45]), .Y(n2152) );
OAI21X1TS U3125 ( .A0(intDY[46]), .A1(n3425), .B0(n2151), .Y(n2162) );
OA22X1TS U3126 ( .A0(n3427), .A1(intDY[42]), .B0(n2155), .B1(intDY[43]), .Y(
n2158) );
NAND4X1TS U3127 ( .A(n2160), .B(n2158), .C(n2069), .D(n2068), .Y(n2202) );
OA22X1TS U3128 ( .A0(n3430), .A1(intDY[34]), .B0(n3340), .B1(intDY[35]), .Y(
n2173) );
NOR4X1TS U3129 ( .A(n2204), .B(n2169), .C(n2202), .D(n2071), .Y(n2208) );
OA22X1TS U3130 ( .A0(n3332), .A1(intDY[30]), .B0(n3476), .B1(intDY[31]), .Y(
n2082) );
OAI2BB2XLTS U3131 ( .B0(intDX[28]), .B1(n2072), .A0N(intDY[29]), .A1N(n3407),
.Y(n2081) );
OAI21X1TS U3132 ( .A0(intDY[26]), .A1(n3339), .B0(n2075), .Y(n2133) );
NOR2X1TS U3133 ( .A(n3412), .B(intDY[25]), .Y(n2130) );
AOI22X1TS U3134 ( .A0(n2074), .A1(intDY[24]), .B0(intDY[25]), .B1(n3412),
.Y(n2077) );
OAI32X1TS U3135 ( .A0(n2133), .A1(n2132), .A2(n2077), .B0(n2076), .B1(n2132),
.Y(n2080) );
OAI2BB2XLTS U3136 ( .B0(intDX[30]), .B1(n2078), .A0N(intDY[31]), .A1N(n3476),
.Y(n2079) );
AOI211X1TS U3137 ( .A0(n2082), .A1(n2081), .B0(n2080), .C0(n2079), .Y(n2137)
);
OA22X1TS U3138 ( .A0(n3333), .A1(intDY[22]), .B0(n3396), .B1(intDY[23]), .Y(
n2129) );
OA22X1TS U3139 ( .A0(n3404), .A1(intDY[14]), .B0(n3528), .B1(intDY[15]), .Y(
n2110) );
OAI2BB1X1TS U3140 ( .A0N(n3379), .A1N(intDX[5]), .B0(intDY[4]), .Y(n2085) );
OAI22X1TS U3141 ( .A0(intDX[4]), .A1(n2085), .B0(n3379), .B1(intDX[5]), .Y(
n2096) );
OAI2BB1X1TS U3142 ( .A0N(n3331), .A1N(intDX[7]), .B0(intDY[6]), .Y(n2086) );
OAI22X1TS U3143 ( .A0(intDX[6]), .A1(n2086), .B0(n3331), .B1(intDX[7]), .Y(
n2095) );
AOI222X1TS U3144 ( .A0(intDX[4]), .A1(n3328), .B0(intDX[5]), .B1(n3379),
.C0(n2092), .C1(n2091), .Y(n2094) );
AOI22X1TS U3145 ( .A0(intDX[7]), .A1(n3331), .B0(intDX[6]), .B1(n3389), .Y(
n2093) );
OAI32X1TS U3146 ( .A0(n2096), .A1(n2095), .A2(n2094), .B0(n2093), .B1(n2095),
.Y(n2113) );
NOR2X1TS U3147 ( .A(n3402), .B(intDY[11]), .Y(n2098) );
AOI21X1TS U3148 ( .A0(intDX[10]), .A1(n3374), .B0(n2098), .Y(n2103) );
OAI2BB2XLTS U3149 ( .B0(intDX[12]), .B1(n2097), .A0N(intDY[13]), .A1N(n3406),
.Y(n2109) );
AOI22X1TS U3150 ( .A0(intDY[11]), .A1(n3402), .B0(intDY[10]), .B1(n2099),
.Y(n2105) );
AOI21X1TS U3151 ( .A0(n2102), .A1(n2101), .B0(n2114), .Y(n2104) );
OAI2BB2XLTS U3152 ( .B0(n2105), .B1(n2114), .A0N(n2104), .A1N(n2103), .Y(
n2108) );
OAI2BB2XLTS U3153 ( .B0(intDX[14]), .B1(n2106), .A0N(intDY[15]), .A1N(n3528),
.Y(n2107) );
AOI211X1TS U3154 ( .A0(n2110), .A1(n2109), .B0(n2108), .C0(n2107), .Y(n2111)
);
OAI31X1TS U3155 ( .A0(n2114), .A1(n2113), .A2(n2112), .B0(n2111), .Y(n2116)
);
NOR2X1TS U3156 ( .A(n3411), .B(intDY[17]), .Y(n2118) );
OAI21X1TS U3157 ( .A0(intDY[18]), .A1(n3338), .B0(n2120), .Y(n2124) );
AOI211X1TS U3158 ( .A0(intDX[16]), .A1(n3398), .B0(n2118), .C0(n2124), .Y(
n2115) );
OAI2BB2XLTS U3159 ( .B0(intDX[20]), .B1(n2117), .A0N(intDY[21]), .A1N(n3408),
.Y(n2128) );
AOI22X1TS U3160 ( .A0(n2119), .A1(intDY[16]), .B0(intDY[17]), .B1(n3411),
.Y(n2122) );
OAI32X1TS U3161 ( .A0(n2124), .A1(n2123), .A2(n2122), .B0(n2121), .B1(n2123),
.Y(n2127) );
OAI2BB2XLTS U3162 ( .B0(intDX[22]), .B1(n2125), .A0N(intDY[23]), .A1N(n3396),
.Y(n2126) );
AOI211X1TS U3163 ( .A0(n2129), .A1(n2128), .B0(n2127), .C0(n2126), .Y(n2135)
);
NOR2BX1TS U3164 ( .AN(intDX[24]), .B(intDY[24]), .Y(n2131) );
OR4X2TS U3165 ( .A(n2133), .B(n2132), .C(n2131), .D(n2130), .Y(n2134) );
AOI32X1TS U3166 ( .A0(n2137), .A1(n2136), .A2(n2135), .B0(n2134), .B1(n2137),
.Y(n2207) );
AOI22X1TS U3167 ( .A0(intDY[57]), .A1(n3420), .B0(intDY[56]), .B1(n2139),
.Y(n2143) );
OA21XLTS U3168 ( .A0(n2143), .A1(n2142), .B0(n2141), .Y(n2149) );
NOR2BX1TS U3169 ( .AN(n2151), .B(intDX[46]), .Y(n2166) );
AOI22X1TS U3170 ( .A0(intDY[45]), .A1(n3478), .B0(intDY[44]), .B1(n2153),
.Y(n2163) );
OAI2BB2XLTS U3171 ( .B0(intDX[40]), .B1(n2154), .A0N(intDY[41]), .A1N(n3422),
.Y(n2159) );
OAI2BB2XLTS U3172 ( .B0(intDX[42]), .B1(n2156), .A0N(intDY[43]), .A1N(n2155),
.Y(n2157) );
AOI32X1TS U3173 ( .A0(n2160), .A1(n2159), .A2(n2158), .B0(n2157), .B1(n2160),
.Y(n2161) );
NOR2BX1TS U3174 ( .AN(intDY[47]), .B(intDX[47]), .Y(n2164) );
AOI211X1TS U3175 ( .A0(intDY[46]), .A1(n2166), .B0(n2165), .C0(n2164), .Y(
n2203) );
INVX2TS U3176 ( .A(n2169), .Y(n2175) );
OAI2BB2XLTS U3177 ( .B0(intDX[32]), .B1(n2170), .A0N(intDY[33]), .A1N(n3421),
.Y(n2174) );
OAI2BB2XLTS U3178 ( .B0(intDX[34]), .B1(n2171), .A0N(intDY[35]), .A1N(n3340),
.Y(n2172) );
AOI32X1TS U3179 ( .A0(n2175), .A1(n2174), .A2(n2173), .B0(n2172), .B1(n2175),
.Y(n2176) );
OAI2BB1X1TS U3180 ( .A0N(n2178), .A1N(n2177), .B0(n2176), .Y(n2183) );
NOR2BX1TS U3181 ( .AN(intDY[39]), .B(intDX[39]), .Y(n2182) );
NOR3X1TS U3182 ( .A(n3376), .B(n2179), .C(intDX[38]), .Y(n2181) );
INVX2TS U3183 ( .A(n2204), .Y(n2180) );
OAI31X1TS U3184 ( .A0(n2183), .A1(n2182), .A2(n2181), .B0(n2180), .Y(n2201)
);
INVX2TS U3185 ( .A(n2187), .Y(n2193) );
AOI22X1TS U3186 ( .A0(intDY[49]), .A1(n3409), .B0(intDY[48]), .B1(n2189),
.Y(n2192) );
OAI32X1TS U3187 ( .A0(n2194), .A1(n2193), .A2(n2192), .B0(n2191), .B1(n2193),
.Y(n2198) );
OAI2BB2XLTS U3188 ( .B0(intDX[54]), .B1(n2195), .A0N(intDY[55]), .A1N(n3480),
.Y(n2197) );
OAI31X1TS U3189 ( .A0(n2199), .A1(n2198), .A2(n2197), .B0(n2196), .Y(n2200)
);
INVX2TS U3190 ( .A(n2312), .Y(n2313) );
BUFX3TS U3191 ( .A(n2495), .Y(n2672) );
AOI22X1TS U3192 ( .A0(n2672), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(n2304), .B1(n1637), .Y(n2214) );
AOI22X1TS U3193 ( .A0(n2507), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[57]), .B0(n2536), .B1(n1619), .Y(n2213) );
OAI211X1TS U3194 ( .A0(n2215), .A1(n2291), .B0(n2214), .C0(n2213), .Y(n2268)
);
AOI222X1TS U3195 ( .A0(n2268), .A1(n2496), .B0(n2217), .B1(n2216), .C0(n2302), .C1(Sgf_normalized_result[2]), .Y(n2218) );
INVX2TS U3196 ( .A(n2218), .Y(n1444) );
INVX2TS U3197 ( .A(n2219), .Y(n2238) );
AOI22X1TS U3198 ( .A0(n2295), .A1(n1619), .B0(n2294), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(n2221) );
AOI22X1TS U3199 ( .A0(n2667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(n2666), .B1(n1637), .Y(n2220) );
OAI211X1TS U3200 ( .A0(n2238), .A1(n2291), .B0(n2221), .C0(n2220), .Y(n2517)
);
AOI22X1TS U3201 ( .A0(n2310), .A1(Sgf_normalized_result[44]), .B0(n2301),
.B1(n2517), .Y(n2222) );
OAI21X1TS U3202 ( .A0(n2224), .A1(n3526), .B0(n2223), .Y(n2225) );
AOI22X1TS U3203 ( .A0(n2295), .A1(n1620), .B0(n2304), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(n2227) );
AOI22X1TS U3204 ( .A0(n2667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(n2666), .B1(n1638), .Y(n2226) );
AOI22X1TS U3205 ( .A0(n2310), .A1(Sgf_normalized_result[43]), .B0(n2301),
.B1(n2514), .Y(n2228) );
INVX2TS U3206 ( .A(n2229), .Y(n2292) );
AOI22X1TS U3207 ( .A0(n2310), .A1(Sgf_normalized_result[40]), .B0(n2301),
.B1(n2230), .Y(n2231) );
INVX2TS U3208 ( .A(n2232), .Y(n2241) );
AOI22X1TS U3209 ( .A0(n2295), .A1(n1618), .B0(n2304), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(n2234) );
AOI22X1TS U3210 ( .A0(n2667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(n2666), .B1(n1636), .Y(n2233) );
OAI211X1TS U3211 ( .A0(n2241), .A1(n2308), .B0(n2234), .C0(n2233), .Y(n2520)
);
AOI22X1TS U3212 ( .A0(n2310), .A1(Sgf_normalized_result[45]), .B0(n2301),
.B1(n2520), .Y(n2235) );
AOI22X1TS U3213 ( .A0(n2310), .A1(Sgf_normalized_result[42]), .B0(n2301),
.B1(n2236), .Y(n2237) );
AOI22X1TS U3214 ( .A0(n2310), .A1(Sgf_normalized_result[41]), .B0(n2301),
.B1(n2239), .Y(n2240) );
INVX2TS U3215 ( .A(n2242), .Y(n2248) );
AOI22X1TS U3216 ( .A0(n2295), .A1(n1624), .B0(n2304), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n2244) );
AOI22X1TS U3217 ( .A0(n2667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(n2666), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(n2243) );
OAI211X1TS U3218 ( .A0(n2308), .A1(n2248), .B0(n2244), .C0(n2243), .Y(n2523)
);
AOI22X1TS U3219 ( .A0(n2310), .A1(Sgf_normalized_result[39]), .B0(n2301),
.B1(n2523), .Y(n2245) );
INVX2TS U3220 ( .A(n2548), .Y(n2309) );
AOI22X1TS U3221 ( .A0(n2310), .A1(Sgf_normalized_result[47]), .B0(n2309),
.B1(n2246), .Y(n2247) );
AOI22X1TS U3222 ( .A0(n2673), .A1(Sgf_normalized_result[51]), .B0(n2309),
.B1(n2249), .Y(n2250) );
INVX2TS U3223 ( .A(n2252), .Y(n2266) );
AOI22X1TS U3224 ( .A0(n2310), .A1(Sgf_normalized_result[48]), .B0(n2309),
.B1(n2253), .Y(n2254) );
AOI22X1TS U3225 ( .A0(n2310), .A1(Sgf_normalized_result[49]), .B0(n2309),
.B1(n2255), .Y(n2256) );
AOI22X1TS U3226 ( .A0(n2673), .A1(Sgf_normalized_result[50]), .B0(n2309),
.B1(n2258), .Y(n2259) );
AOI22X1TS U3227 ( .A0(n2302), .A1(Sgf_normalized_result[35]), .B0(n2301),
.B1(n2261), .Y(n2262) );
AOI22X1TS U3228 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[80]), .A1(
n2304), .B0(n2672), .B1(n1635), .Y(n2265) );
AOI22X1TS U3229 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[72]), .A1(
n2543), .B0(n2507), .B1(n1615), .Y(n2264) );
OAI211X1TS U3230 ( .A0(n2308), .A1(n2266), .B0(n2265), .C0(n2264), .Y(n2276)
);
AOI22X1TS U3231 ( .A0(n2276), .A1(n2496), .B0(n2673), .B1(
Sgf_normalized_result[16]), .Y(n2267) );
AOI22X1TS U3232 ( .A0(n2673), .A1(Sgf_normalized_result[52]), .B0(n2309),
.B1(n2268), .Y(n2269) );
INVX2TS U3233 ( .A(n2272), .Y(n2283) );
AOI22X1TS U3234 ( .A0(n2507), .A1(n1622), .B0(n2666), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(n2274) );
AOI22X1TS U3235 ( .A0(n2295), .A1(n1640), .B0(n2294), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n2273) );
OAI211X1TS U3236 ( .A0(n2308), .A1(n2533), .B0(n2274), .C0(n2273), .Y(n2287)
);
AOI22X1TS U3237 ( .A0(n2287), .A1(n2496), .B0(n2673), .B1(
Sgf_normalized_result[21]), .Y(n2275) );
AOI22X1TS U3238 ( .A0(n2310), .A1(Sgf_normalized_result[38]), .B0(n2301),
.B1(n2276), .Y(n2277) );
AOI22X1TS U3239 ( .A0(n2672), .A1(n1641), .B0(n2294), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(n2285) );
AOI22X1TS U3240 ( .A0(n2507), .A1(n1623), .B0(n2666), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(n2284) );
OAI211X1TS U3241 ( .A0(n2308), .A1(n2531), .B0(n2285), .C0(n2284), .Y(n2300)
);
AOI22X1TS U3242 ( .A0(n2300), .A1(n2496), .B0(n2673), .B1(
Sgf_normalized_result[22]), .Y(n2286) );
AOI22X1TS U3243 ( .A0(n2302), .A1(Sgf_normalized_result[33]), .B0(n2301),
.B1(n2287), .Y(n2288) );
AOI22X1TS U3244 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[72]), .A1(
n2304), .B0(n1615), .B1(n2672), .Y(n2290) );
AOI22X1TS U3245 ( .A0(n2667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(n2666), .B1(n1635), .Y(n2289) );
OAI211X1TS U3246 ( .A0(n2292), .A1(n2291), .B0(n2290), .C0(n2289), .Y(n2526)
);
AOI22X1TS U3247 ( .A0(n2310), .A1(Sgf_normalized_result[46]), .B0(n2309),
.B1(n2526), .Y(n2293) );
AOI22X1TS U3248 ( .A0(n2667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[56]), .B0(n2666), .B1(n1618), .Y(n2297) );
AOI22X1TS U3249 ( .A0(n2295), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(n2294), .B1(n1636), .Y(n2296) );
OAI211X1TS U3250 ( .A0(n2308), .A1(n2298), .B0(n2297), .C0(n2296), .Y(n2532)
);
AOI22X1TS U3251 ( .A0(n2673), .A1(Sgf_normalized_result[53]), .B0(n2309),
.B1(n2532), .Y(n2299) );
AOI22X1TS U3252 ( .A0(n2302), .A1(Sgf_normalized_result[32]), .B0(n2301),
.B1(n2300), .Y(n2303) );
AOI22X1TS U3253 ( .A0(n2672), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(n2294), .B1(n1635), .Y(n2306) );
AOI22X1TS U3254 ( .A0(n2507), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[55]), .B0(n2536), .B1(n1615), .Y(n2305) );
OAI211X1TS U3255 ( .A0(n2308), .A1(n2307), .B0(n2306), .C0(n2305), .Y(n2529)
);
AOI22X1TS U3256 ( .A0(n2310), .A1(Sgf_normalized_result[54]), .B0(n2309),
.B1(n2529), .Y(n2311) );
BUFX3TS U3257 ( .A(n2415), .Y(n2376) );
INVX4TS U3258 ( .A(n2007), .Y(n2486) );
INVX4TS U3259 ( .A(n2007), .Y(n2365) );
AOI22X1TS U3260 ( .A0(n2315), .A1(intDY[12]), .B0(DmP[12]), .B1(n2365), .Y(
n2314) );
AOI22X1TS U3261 ( .A0(n2315), .A1(intDY[0]), .B0(DmP[0]), .B1(n3258), .Y(
n2316) );
BUFX3TS U3262 ( .A(n2415), .Y(n2444) );
INVX4TS U3263 ( .A(n2007), .Y(n2374) );
AOI22X1TS U3264 ( .A0(DmP[49]), .A1(n2374), .B0(intDY[49]), .B1(n2315), .Y(
n2317) );
BUFX3TS U3265 ( .A(n2415), .Y(n2398) );
AOI22X1TS U3266 ( .A0(n2315), .A1(intDY[14]), .B0(DmP[14]), .B1(n2365), .Y(
n2318) );
BUFX3TS U3267 ( .A(n2415), .Y(n2367) );
AOI22X1TS U3268 ( .A0(n2315), .A1(intDY[10]), .B0(DmP[10]), .B1(n2365), .Y(
n2319) );
AOI22X1TS U3269 ( .A0(n2315), .A1(intDY[9]), .B0(DmP[9]), .B1(n2365), .Y(
n2320) );
AOI22X1TS U3270 ( .A0(DmP[40]), .A1(n2374), .B0(intDY[40]), .B1(n2315), .Y(
n2321) );
BUFX3TS U3271 ( .A(n2415), .Y(n2382) );
BUFX3TS U3272 ( .A(n2315), .Y(n2349) );
AOI22X1TS U3273 ( .A0(n2470), .A1(intDY[52]), .B0(DmP[52]), .B1(n2365), .Y(
n2322) );
BUFX3TS U3274 ( .A(n2315), .Y(n2360) );
AOI22X1TS U3275 ( .A0(n2349), .A1(intDY[11]), .B0(DmP[11]), .B1(n2365), .Y(
n2323) );
INVX4TS U3276 ( .A(n2007), .Y(n2481) );
AOI22X1TS U3277 ( .A0(n2380), .A1(intDY[59]), .B0(DmP[59]), .B1(n2481), .Y(
n2324) );
AOI22X1TS U3278 ( .A0(n2395), .A1(intDY[56]), .B0(DmP[56]), .B1(n2365), .Y(
n2325) );
AOI22X1TS U3279 ( .A0(n2470), .A1(intDY[60]), .B0(DmP[60]), .B1(n2365), .Y(
n2326) );
AOI22X1TS U3280 ( .A0(n2360), .A1(intDY[58]), .B0(DmP[58]), .B1(n2365), .Y(
n2327) );
AOI22X1TS U3281 ( .A0(n2395), .A1(intDY[15]), .B0(DmP[15]), .B1(n2396), .Y(
n2328) );
AOI22X1TS U3282 ( .A0(n2380), .A1(intDY[13]), .B0(DmP[13]), .B1(n2365), .Y(
n2329) );
AOI22X1TS U3283 ( .A0(n2380), .A1(intDY[55]), .B0(DmP[55]), .B1(n2365), .Y(
n2330) );
AOI22X1TS U3284 ( .A0(n2349), .A1(intDY[53]), .B0(DmP[53]), .B1(n2365), .Y(
n2331) );
AOI22X1TS U3285 ( .A0(DmP[44]), .A1(n2374), .B0(intDY[44]), .B1(n2360), .Y(
n2332) );
AOI22X1TS U3286 ( .A0(DmP[48]), .A1(n2489), .B0(intDY[48]), .B1(n2470), .Y(
n2333) );
AOI22X1TS U3287 ( .A0(DmP[37]), .A1(n2374), .B0(intDY[37]), .B1(n2360), .Y(
n2334) );
AOI22X1TS U3288 ( .A0(DmP[34]), .A1(n2374), .B0(intDY[34]), .B1(n2360), .Y(
n2335) );
AOI22X1TS U3289 ( .A0(DmP[38]), .A1(n2374), .B0(intDY[38]), .B1(n2360), .Y(
n2336) );
AOI22X1TS U3290 ( .A0(n2380), .A1(intDY[16]), .B0(DmP[16]), .B1(n2365), .Y(
n2337) );
AOI22X1TS U3291 ( .A0(DmP[42]), .A1(n2374), .B0(intDY[42]), .B1(n2360), .Y(
n2338) );
AOI22X1TS U3292 ( .A0(DmP[46]), .A1(n2396), .B0(intDY[46]), .B1(n2349), .Y(
n2339) );
AOI22X1TS U3293 ( .A0(DmP[33]), .A1(n2374), .B0(intDY[33]), .B1(n2349), .Y(
n2340) );
AOI22X1TS U3294 ( .A0(DmP[41]), .A1(n2489), .B0(intDY[41]), .B1(n2395), .Y(
n2341) );
AOI22X1TS U3295 ( .A0(DmP[47]), .A1(n2374), .B0(intDY[47]), .B1(n2380), .Y(
n2342) );
AOI22X1TS U3296 ( .A0(n2349), .A1(intDY[61]), .B0(DmP[61]), .B1(n2481), .Y(
n2343) );
AOI22X1TS U3297 ( .A0(DmP[19]), .A1(n2396), .B0(intDY[19]), .B1(n2380), .Y(
n2344) );
AOI22X1TS U3298 ( .A0(DmP[36]), .A1(n2374), .B0(intDY[36]), .B1(n2360), .Y(
n2345) );
AOI22X1TS U3299 ( .A0(DmP[43]), .A1(n2489), .B0(intDY[43]), .B1(n2349), .Y(
n2346) );
AOI22X1TS U3300 ( .A0(DmP[51]), .A1(n2374), .B0(intDY[51]), .B1(n2380), .Y(
n2347) );
AOI22X1TS U3301 ( .A0(DmP[39]), .A1(n2489), .B0(intDY[39]), .B1(n2380), .Y(
n2348) );
AOI22X1TS U3302 ( .A0(DmP[50]), .A1(n2489), .B0(intDY[50]), .B1(n2395), .Y(
n2350) );
AOI22X1TS U3303 ( .A0(DmP[25]), .A1(n2396), .B0(intDY[25]), .B1(n2380), .Y(
n2351) );
AOI22X1TS U3304 ( .A0(DmP[35]), .A1(n2489), .B0(intDY[35]), .B1(n2470), .Y(
n2352) );
BUFX3TS U3305 ( .A(n2315), .Y(n2395) );
AOI22X1TS U3306 ( .A0(n2360), .A1(intDY[1]), .B0(DmP[1]), .B1(n3258), .Y(
n2353) );
AOI22X1TS U3307 ( .A0(DmP[21]), .A1(n2396), .B0(intDY[21]), .B1(n2380), .Y(
n2354) );
AOI22X1TS U3308 ( .A0(n2360), .A1(intDY[6]), .B0(DmP[6]), .B1(n3258), .Y(
n2355) );
AOI22X1TS U3309 ( .A0(n2470), .A1(intDY[5]), .B0(DmP[5]), .B1(n3258), .Y(
n2356) );
AOI22X1TS U3310 ( .A0(n2470), .A1(intDY[4]), .B0(DmP[4]), .B1(n3258), .Y(
n2357) );
AOI22X1TS U3311 ( .A0(n2470), .A1(intDY[62]), .B0(DmP[62]), .B1(n3258), .Y(
n2358) );
AOI22X1TS U3312 ( .A0(n2349), .A1(intDY[7]), .B0(DmP[7]), .B1(n3258), .Y(
n2359) );
AOI22X1TS U3313 ( .A0(DmP[29]), .A1(n2374), .B0(intDY[29]), .B1(n2395), .Y(
n2361) );
AOI22X1TS U3314 ( .A0(n2380), .A1(intDY[54]), .B0(DmP[54]), .B1(n2365), .Y(
n2362) );
AOI22X1TS U3315 ( .A0(n2380), .A1(intDY[2]), .B0(DmP[2]), .B1(n3258), .Y(
n2363) );
AOI22X1TS U3316 ( .A0(n2395), .A1(intDY[8]), .B0(DmP[8]), .B1(n3258), .Y(
n2364) );
AOI22X1TS U3317 ( .A0(n2380), .A1(intDY[57]), .B0(DmP[57]), .B1(n2365), .Y(
n2366) );
INVX4TS U3318 ( .A(n2007), .Y(n2436) );
AOI22X1TS U3319 ( .A0(n2349), .A1(intDY[3]), .B0(n1609), .B1(n2436), .Y(
n2368) );
AOI22X1TS U3320 ( .A0(DmP[27]), .A1(n2396), .B0(intDY[27]), .B1(n2395), .Y(
n2369) );
AOI22X1TS U3321 ( .A0(DmP[30]), .A1(n2374), .B0(intDY[30]), .B1(n2349), .Y(
n2370) );
AOI22X1TS U3322 ( .A0(DmP[28]), .A1(n2396), .B0(intDY[28]), .B1(n2380), .Y(
n2371) );
AOI22X1TS U3323 ( .A0(DmP[26]), .A1(n2396), .B0(intDY[26]), .B1(n2470), .Y(
n2372) );
AOI22X1TS U3324 ( .A0(DmP[32]), .A1(n2374), .B0(intDY[32]), .B1(n2395), .Y(
n2373) );
AOI22X1TS U3325 ( .A0(DmP[31]), .A1(n2374), .B0(intDY[31]), .B1(n2395), .Y(
n2375) );
AOI22X1TS U3326 ( .A0(DmP[17]), .A1(n2396), .B0(intDY[17]), .B1(n2395), .Y(
n2377) );
AOI22X1TS U3327 ( .A0(DmP[22]), .A1(n2396), .B0(intDY[22]), .B1(n2349), .Y(
n2378) );
AOI22X1TS U3328 ( .A0(DmP[24]), .A1(n2396), .B0(intDY[24]), .B1(n2380), .Y(
n2379) );
AOI22X1TS U3329 ( .A0(DmP[23]), .A1(n2396), .B0(intDY[23]), .B1(n2349), .Y(
n2381) );
AOI22X1TS U3330 ( .A0(DmP[18]), .A1(n2396), .B0(intDY[18]), .B1(n2349), .Y(
n2383) );
INVX2TS U3331 ( .A(n3256), .Y(n2388) );
NAND2X1TS U3332 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[2]),
.Y(n2384) );
AOI211X1TS U3333 ( .A0(n2460), .A1(n3269), .B0(n2386), .C0(n3254), .Y(n2387)
);
NAND3X4TS U3334 ( .A(n2388), .B(n2673), .C(n2387), .Y(FSM_exp_operation_A_S)
);
XOR2X1TS U3335 ( .A(DP_OP_42J152_122_8302_n1), .B(FSM_exp_operation_A_S),
.Y(n2459) );
OR4X2TS U3336 ( .A(Exp_Operation_Module_Data_S[2]), .B(
Exp_Operation_Module_Data_S[1]), .C(Exp_Operation_Module_Data_S[0]),
.D(n2389), .Y(n2390) );
OR4X2TS U3337 ( .A(Exp_Operation_Module_Data_S[5]), .B(
Exp_Operation_Module_Data_S[4]), .C(Exp_Operation_Module_Data_S[3]),
.D(n2390), .Y(n2391) );
OR4X2TS U3338 ( .A(Exp_Operation_Module_Data_S[8]), .B(
Exp_Operation_Module_Data_S[7]), .C(Exp_Operation_Module_Data_S[6]),
.D(n2391), .Y(n2392) );
OR4X2TS U3339 ( .A(n2459), .B(Exp_Operation_Module_Data_S[10]), .C(
Exp_Operation_Module_Data_S[9]), .D(n2392), .Y(n2393) );
AOI22X1TS U3340 ( .A0(DmP[20]), .A1(n2396), .B0(intDY[20]), .B1(n2360), .Y(
n2397) );
INVX4TS U3341 ( .A(n2415), .Y(n2440) );
AOI22X1TS U3342 ( .A0(n2440), .A1(intDY[30]), .B0(DMP[30]), .B1(n2481), .Y(
n2399) );
AOI22X1TS U3343 ( .A0(n2440), .A1(intDY[28]), .B0(DMP[28]), .B1(n2481), .Y(
n2400) );
INVX4TS U3344 ( .A(n2415), .Y(n2437) );
INVX4TS U3345 ( .A(n2007), .Y(n2432) );
AOI22X1TS U3346 ( .A0(n2437), .A1(intDY[46]), .B0(DMP[46]), .B1(n2432), .Y(
n2401) );
AOI22X1TS U3347 ( .A0(n2440), .A1(intDY[34]), .B0(DMP[34]), .B1(n2432), .Y(
n2402) );
AOI22X1TS U3348 ( .A0(n2437), .A1(intDY[42]), .B0(DMP[42]), .B1(n2432), .Y(
n2403) );
INVX2TS U3349 ( .A(n2315), .Y(n2435) );
AOI22X1TS U3350 ( .A0(n2437), .A1(intDY[51]), .B0(DMP[51]), .B1(n2436), .Y(
n2404) );
INVX4TS U3351 ( .A(n2415), .Y(n2488) );
AOI22X1TS U3352 ( .A0(n2488), .A1(intDY[59]), .B0(DMP[59]), .B1(n2436), .Y(
n2405) );
AOI22X1TS U3353 ( .A0(n2440), .A1(intDY[27]), .B0(DMP[27]), .B1(n2481), .Y(
n2406) );
AOI22X1TS U3354 ( .A0(n2437), .A1(intDY[45]), .B0(DMP[45]), .B1(n2432), .Y(
n2407) );
AOI22X1TS U3355 ( .A0(n2488), .A1(intDY[60]), .B0(DMP[60]), .B1(n2436), .Y(
n2408) );
AOI22X1TS U3356 ( .A0(n2437), .A1(intDY[54]), .B0(DMP[54]), .B1(n2436), .Y(
n2409) );
AOI22X1TS U3357 ( .A0(n2437), .A1(intDY[49]), .B0(DMP[49]), .B1(n2436), .Y(
n2410) );
AOI22X1TS U3358 ( .A0(n2440), .A1(intDY[41]), .B0(DMP[41]), .B1(n2432), .Y(
n2411) );
AOI22X1TS U3359 ( .A0(n2440), .A1(intDY[36]), .B0(DMP[36]), .B1(n2432), .Y(
n2412) );
AOI22X1TS U3360 ( .A0(n2488), .A1(intDY[57]), .B0(DMP[57]), .B1(n2436), .Y(
n2413) );
AOI22X1TS U3361 ( .A0(n2440), .A1(intDY[35]), .B0(DMP[35]), .B1(n2432), .Y(
n2414) );
INVX2TS U3362 ( .A(n2415), .Y(n2482) );
AOI22X1TS U3363 ( .A0(n2482), .A1(intDY[62]), .B0(DMP[62]), .B1(n2481), .Y(
n2416) );
AOI22X1TS U3364 ( .A0(n2437), .A1(intDY[53]), .B0(DMP[53]), .B1(n2436), .Y(
n2417) );
AOI22X1TS U3365 ( .A0(n2440), .A1(intDY[33]), .B0(DMP[33]), .B1(n2481), .Y(
n2418) );
AOI22X1TS U3366 ( .A0(n2440), .A1(intDY[32]), .B0(DMP[32]), .B1(n2432), .Y(
n2419) );
AOI22X1TS U3367 ( .A0(n2440), .A1(intDY[31]), .B0(DMP[31]), .B1(n2481), .Y(
n2420) );
AOI22X1TS U3368 ( .A0(n2488), .A1(intDY[61]), .B0(DMP[61]), .B1(n2436), .Y(
n2421) );
AOI22X1TS U3369 ( .A0(n2437), .A1(intDY[55]), .B0(DMP[55]), .B1(n2436), .Y(
n2422) );
AOI22X1TS U3370 ( .A0(n2437), .A1(intDY[52]), .B0(DMP[52]), .B1(n2436), .Y(
n2423) );
AOI22X1TS U3371 ( .A0(n2437), .A1(intDY[56]), .B0(DMP[56]), .B1(n2436), .Y(
n2424) );
AOI22X1TS U3372 ( .A0(n2440), .A1(intDY[38]), .B0(DMP[38]), .B1(n2432), .Y(
n2425) );
AOI22X1TS U3373 ( .A0(n2440), .A1(intDY[39]), .B0(DMP[39]), .B1(n2432), .Y(
n2426) );
AOI22X1TS U3374 ( .A0(n2440), .A1(intDY[40]), .B0(DMP[40]), .B1(n2432), .Y(
n2427) );
AOI22X1TS U3375 ( .A0(n2437), .A1(intDY[44]), .B0(DMP[44]), .B1(n2432), .Y(
n2428) );
AOI22X1TS U3376 ( .A0(n2437), .A1(intDY[47]), .B0(DMP[47]), .B1(n2436), .Y(
n2429) );
AOI22X1TS U3377 ( .A0(n2437), .A1(intDY[48]), .B0(DMP[48]), .B1(n2432), .Y(
n2430) );
AOI22X1TS U3378 ( .A0(n2440), .A1(intDY[37]), .B0(DMP[37]), .B1(n2432), .Y(
n2431) );
AOI22X1TS U3379 ( .A0(n2437), .A1(intDY[43]), .B0(DMP[43]), .B1(n2432), .Y(
n2433) );
AOI22X1TS U3380 ( .A0(n2488), .A1(intDY[58]), .B0(DMP[58]), .B1(n2436), .Y(
n2434) );
AOI22X1TS U3381 ( .A0(n2437), .A1(intDY[50]), .B0(DMP[50]), .B1(n2436), .Y(
n2438) );
AOI22X1TS U3382 ( .A0(n2440), .A1(intDY[29]), .B0(DMP[29]), .B1(n2481), .Y(
n2441) );
AOI22X1TS U3383 ( .A0(DmP[45]), .A1(n2489), .B0(intDY[45]), .B1(n2395), .Y(
n2443) );
INVX4TS U3384 ( .A(n2360), .Y(n2458) );
AOI22X1TS U3385 ( .A0(n2486), .A1(DMP[12]), .B0(intDY[12]), .B1(n2485), .Y(
n2445) );
AOI22X1TS U3386 ( .A0(n2486), .A1(DMP[14]), .B0(intDY[14]), .B1(n2485), .Y(
n2446) );
AOI22X1TS U3387 ( .A0(n2486), .A1(DMP[13]), .B0(intDY[13]), .B1(n2485), .Y(
n2447) );
AOI22X1TS U3388 ( .A0(n2486), .A1(DMP[11]), .B0(intDY[11]), .B1(n2485), .Y(
n2448) );
AOI22X1TS U3389 ( .A0(n2486), .A1(DMP[8]), .B0(intDY[8]), .B1(n2488), .Y(
n2449) );
AOI22X1TS U3390 ( .A0(n2489), .A1(DMP[3]), .B0(intDY[3]), .B1(n2488), .Y(
n2450) );
AOI22X1TS U3391 ( .A0(n2489), .A1(DMP[6]), .B0(intDY[6]), .B1(n2488), .Y(
n2451) );
AOI22X1TS U3392 ( .A0(n2489), .A1(DMP[4]), .B0(intDY[4]), .B1(n2488), .Y(
n2452) );
AOI22X1TS U3393 ( .A0(n2489), .A1(DMP[5]), .B0(intDY[5]), .B1(n2488), .Y(
n2453) );
AOI22X1TS U3394 ( .A0(n2486), .A1(DMP[9]), .B0(intDY[9]), .B1(n2485), .Y(
n2454) );
AOI22X1TS U3395 ( .A0(n2489), .A1(DMP[1]), .B0(intDY[1]), .B1(n2488), .Y(
n2455) );
AOI22X1TS U3396 ( .A0(n2486), .A1(DMP[7]), .B0(intDY[7]), .B1(n2488), .Y(
n2456) );
AOI22X1TS U3397 ( .A0(n2486), .A1(DMP[10]), .B0(intDY[10]), .B1(n2485), .Y(
n2457) );
INVX2TS U3398 ( .A(n2459), .Y(n2469) );
INVX2TS U3399 ( .A(Exp_Operation_Module_Data_S[10]), .Y(n2468) );
INVX2TS U3400 ( .A(n2460), .Y(n2463) );
NOR2XLTS U3401 ( .A(FS_Module_state_reg[2]), .B(n3377), .Y(n2461) );
NAND2X1TS U3402 ( .A(n2461), .B(FS_Module_state_reg[1]), .Y(n2462) );
NAND2X1TS U3403 ( .A(n2463), .B(n2462), .Y(n3267) );
NAND2X1TS U3404 ( .A(n2664), .B(overflow_flag), .Y(n2466) );
OAI31X1TS U3405 ( .A0(n2469), .A1(n2468), .A2(n2467), .B0(n2466), .Y(n1427)
);
INVX4TS U3406 ( .A(n2360), .Y(n2491) );
AOI22X1TS U3407 ( .A0(n2486), .A1(DMP[18]), .B0(intDY[18]), .B1(n2485), .Y(
n2471) );
AOI22X1TS U3408 ( .A0(n2482), .A1(intDY[25]), .B0(DMP[25]), .B1(n2481), .Y(
n2472) );
AOI22X1TS U3409 ( .A0(n2486), .A1(DMP[15]), .B0(intDY[15]), .B1(n2485), .Y(
n2473) );
AOI22X1TS U3410 ( .A0(n2482), .A1(intDY[26]), .B0(DMP[26]), .B1(n2481), .Y(
n2474) );
AOI22X1TS U3411 ( .A0(n2482), .A1(intDY[22]), .B0(DMP[22]), .B1(n2481), .Y(
n2475) );
AOI22X1TS U3412 ( .A0(n2486), .A1(DMP[17]), .B0(intDY[17]), .B1(n2485), .Y(
n2476) );
AOI22X1TS U3413 ( .A0(n2486), .A1(DMP[19]), .B0(intDY[19]), .B1(n2485), .Y(
n2477) );
AOI22X1TS U3414 ( .A0(n2486), .A1(DMP[20]), .B0(intDY[20]), .B1(n2485), .Y(
n2478) );
AOI22X1TS U3415 ( .A0(n2482), .A1(intDY[21]), .B0(DMP[21]), .B1(n2481), .Y(
n2479) );
AOI22X1TS U3416 ( .A0(n2482), .A1(intDY[23]), .B0(DMP[23]), .B1(n2481), .Y(
n2480) );
AOI22X1TS U3417 ( .A0(n2482), .A1(intDY[24]), .B0(DMP[24]), .B1(n2481), .Y(
n2483) );
AOI22X1TS U3418 ( .A0(n2489), .A1(DMP[2]), .B0(intDY[2]), .B1(n2488), .Y(
n2484) );
AOI22X1TS U3419 ( .A0(n2486), .A1(DMP[16]), .B0(intDY[16]), .B1(n2485), .Y(
n2487) );
AOI22X1TS U3420 ( .A0(n2489), .A1(DMP[0]), .B0(intDY[0]), .B1(n2488), .Y(
n2490) );
INVX2TS U3421 ( .A(n2492), .Y(n3292) );
BUFX3TS U3422 ( .A(n3292), .Y(n3296) );
INVX4TS U3423 ( .A(n3296), .Y(n3300) );
OAI2BB2XLTS U3424 ( .B0(n3359), .B1(n3300), .A0N(final_result_ieee[7]),
.A1N(n2991), .Y(n1407) );
OAI2BB2XLTS U3425 ( .B0(n3360), .B1(n3300), .A0N(final_result_ieee[8]),
.A1N(n2991), .Y(n1406) );
OAI2BB2XLTS U3426 ( .B0(n3361), .B1(n3300), .A0N(final_result_ieee[9]),
.A1N(n2991), .Y(n1405) );
OAI2BB2XLTS U3427 ( .B0(n3358), .B1(n3300), .A0N(final_result_ieee[6]),
.A1N(n2991), .Y(n1408) );
OAI2BB2XLTS U3428 ( .B0(n3362), .B1(n3300), .A0N(final_result_ieee[13]),
.A1N(n2991), .Y(n1401) );
AOI22X1TS U3429 ( .A0(n2539), .A1(n1639), .B0(n2536), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n2493) );
AOI211X1TS U3430 ( .A0(n2495), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(n2671), .C0(n2494), .Y(n2499) );
INVX4TS U3431 ( .A(n2496), .Y(n2546) );
AOI22X1TS U3432 ( .A0(n2539), .A1(n1637), .B0(n2536), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n2497) );
AOI211X1TS U3433 ( .A0(n2495), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(n2671), .C0(n2498), .Y(n2500) );
OAI222X1TS U3434 ( .A0(n3326), .A1(n2544), .B0(n2548), .B1(n2499), .C0(n2546), .C1(n2500), .Y(n1468) );
OAI222X1TS U3435 ( .A0(n3368), .A1(n2544), .B0(n2548), .B1(n2500), .C0(n2546), .C1(n2499), .Y(n1470) );
AOI22X1TS U3436 ( .A0(n2539), .A1(n1636), .B0(n2536), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n2501) );
AOI211X1TS U3437 ( .A0(n2672), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(n2671), .C0(n2502), .Y(n2510) );
AOI22X1TS U3438 ( .A0(n2667), .A1(n1640), .B0(n2536), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n2503) );
AOI211X1TS U3439 ( .A0(n2672), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(n2671), .C0(n2504), .Y(n2511) );
OAI222X1TS U3440 ( .A0(n3369), .A1(n2549), .B0(n2548), .B1(n2510), .C0(n2546), .C1(n2511), .Y(n1471) );
AOI22X1TS U3441 ( .A0(n2539), .A1(n1641), .B0(n2536), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(n2505) );
AOI211X1TS U3442 ( .A0(n2672), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(n2671), .C0(n2506), .Y(n2512) );
AOI22X1TS U3443 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[80]), .A1(
n2536), .B0(n2507), .B1(n1635), .Y(n2508) );
AOI211X1TS U3444 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[72]), .A1(
n2672), .B0(n2671), .C0(n2509), .Y(n2513) );
OAI222X1TS U3445 ( .A0(n3324), .A1(n2544), .B0(n2548), .B1(n2512), .C0(n2546), .C1(n2513), .Y(n1466) );
OAI222X1TS U3446 ( .A0(n3325), .A1(n2544), .B0(n2548), .B1(n2511), .C0(n2546), .C1(n2510), .Y(n1467) );
OAI222X1TS U3447 ( .A0(n3370), .A1(n2549), .B0(n2548), .B1(n2513), .C0(n2546), .C1(n2512), .Y(n1472) );
INVX2TS U3448 ( .A(n2514), .Y(n2515) );
INVX2TS U3449 ( .A(n2517), .Y(n2518) );
INVX2TS U3450 ( .A(n2520), .Y(n2521) );
INVX2TS U3451 ( .A(n2523), .Y(n2524) );
INVX2TS U3452 ( .A(n2526), .Y(n2527) );
INVX2TS U3453 ( .A(n2529), .Y(n2530) );
INVX2TS U3454 ( .A(n2532), .Y(n2534) );
OAI222X1TS U3455 ( .A0(n2546), .A1(n2534), .B0(n3355), .B1(n2549), .C0(n1872), .C1(n2533), .Y(n1443) );
AOI22X1TS U3456 ( .A0(n2667), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[71]), .B0(n2672), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n2535) );
OAI2BB1X1TS U3457 ( .A0N(n2536), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(n2535), .Y(n2537)
);
NOR3X1TS U3458 ( .A(n2671), .B(n2538), .C(n2537), .Y(n2545) );
AOI22X1TS U3459 ( .A0(n2539), .A1(n1624), .B0(n2672), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(n2540) );
AOI211X1TS U3460 ( .A0(n2543), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(n2671), .C0(n2542), .Y(n2547) );
OAI222X1TS U3461 ( .A0(n3323), .A1(n2544), .B0(n2548), .B1(n2545), .C0(n2546), .C1(n2547), .Y(n1465) );
OAI222X1TS U3462 ( .A0(n3371), .A1(n2549), .B0(n2548), .B1(n2547), .C0(n2546), .C1(n2545), .Y(n1473) );
CLKAND2X2TS U3463 ( .A(n1577), .B(DmP[62]), .Y(n2558) );
XOR2X1TS U3464 ( .A(FSM_exp_operation_A_S), .B(n2558), .Y(
DP_OP_42J152_122_8302_n16) );
CLKAND2X2TS U3465 ( .A(n1577), .B(DmP[61]), .Y(n2559) );
XOR2X1TS U3466 ( .A(FSM_exp_operation_A_S), .B(n2559), .Y(
DP_OP_42J152_122_8302_n17) );
CLKAND2X2TS U3467 ( .A(n1577), .B(DmP[60]), .Y(n2560) );
XOR2X1TS U3468 ( .A(FSM_exp_operation_A_S), .B(n2560), .Y(
DP_OP_42J152_122_8302_n18) );
CLKAND2X2TS U3469 ( .A(n1577), .B(DmP[59]), .Y(n2561) );
XOR2X1TS U3470 ( .A(FSM_exp_operation_A_S), .B(n2561), .Y(
DP_OP_42J152_122_8302_n19) );
CLKAND2X2TS U3471 ( .A(n1577), .B(DmP[58]), .Y(n2562) );
XOR2X1TS U3472 ( .A(FSM_exp_operation_A_S), .B(n2562), .Y(
DP_OP_42J152_122_8302_n20) );
OAI2BB1X1TS U3473 ( .A0N(DmP[57]), .A1N(n1577), .B0(n2563), .Y(n2564) );
XOR2X1TS U3474 ( .A(FSM_exp_operation_A_S), .B(n2564), .Y(
DP_OP_42J152_122_8302_n21) );
XOR2X1TS U3475 ( .A(FSM_exp_operation_A_S), .B(n2565), .Y(
DP_OP_42J152_122_8302_n22) );
XOR2X1TS U3476 ( .A(FSM_exp_operation_A_S), .B(n2566), .Y(
DP_OP_42J152_122_8302_n23) );
XOR2X1TS U3477 ( .A(FSM_exp_operation_A_S), .B(n2567), .Y(
DP_OP_42J152_122_8302_n24) );
XOR2X1TS U3478 ( .A(FSM_exp_operation_A_S), .B(n2568), .Y(
DP_OP_42J152_122_8302_n25) );
XOR2X1TS U3479 ( .A(FSM_exp_operation_A_S), .B(n2570), .Y(
DP_OP_42J152_122_8302_n26) );
INVX4TS U3480 ( .A(n3316), .Y(n2571) );
MX2X1TS U3481 ( .A(add_subt), .B(intAS), .S0(n2571), .Y(n1295) );
MX2X1TS U3482 ( .A(Data_Y[63]), .B(intDY[63]), .S0(n2571), .Y(n1231) );
MX2X1TS U3483 ( .A(Data_X[18]), .B(intDX[18]), .S0(n2571), .Y(n1315) );
MX2X1TS U3484 ( .A(Data_X[17]), .B(intDX[17]), .S0(n2571), .Y(n1314) );
MX2X1TS U3485 ( .A(Data_X[16]), .B(intDX[16]), .S0(n2571), .Y(n1313) );
MX2X1TS U3486 ( .A(Data_X[15]), .B(intDX[15]), .S0(n2571), .Y(n1312) );
MX2X1TS U3487 ( .A(Data_X[14]), .B(intDX[14]), .S0(n2571), .Y(n1311) );
MX2X1TS U3488 ( .A(Data_X[13]), .B(intDX[13]), .S0(n2571), .Y(n1310) );
MX2X1TS U3489 ( .A(Data_X[12]), .B(intDX[12]), .S0(n2571), .Y(n1309) );
MX2X1TS U3490 ( .A(Data_X[11]), .B(intDX[11]), .S0(n2571), .Y(n1308) );
MX2X1TS U3491 ( .A(Data_X[10]), .B(intDX[10]), .S0(n2571), .Y(n1307) );
MX2X1TS U3492 ( .A(Data_X[9]), .B(intDX[9]), .S0(n2571), .Y(n1306) );
MX2X1TS U3493 ( .A(Data_X[8]), .B(intDX[8]), .S0(n2571), .Y(n1305) );
MX2X1TS U3494 ( .A(Data_X[7]), .B(intDX[7]), .S0(n3303), .Y(n1304) );
MX2X1TS U3495 ( .A(Data_X[6]), .B(intDX[6]), .S0(n3303), .Y(n1303) );
MX2X1TS U3496 ( .A(Data_X[5]), .B(intDX[5]), .S0(n3303), .Y(n1302) );
MX2X1TS U3497 ( .A(Data_X[4]), .B(intDX[4]), .S0(n3303), .Y(n1301) );
MX2X1TS U3498 ( .A(Data_X[3]), .B(intDX[3]), .S0(n3303), .Y(n1300) );
MX2X1TS U3499 ( .A(Data_X[2]), .B(intDX[2]), .S0(n3303), .Y(n1299) );
MX2X1TS U3500 ( .A(Data_X[1]), .B(intDX[1]), .S0(n3303), .Y(n1298) );
MX2X1TS U3501 ( .A(Data_X[0]), .B(intDX[0]), .S0(n3303), .Y(n1297) );
MX2X1TS U3502 ( .A(Data_X[63]), .B(intDX[63]), .S0(n3303), .Y(n1296) );
NOR2X1TS U3503 ( .A(Add_Subt_result[20]), .B(Add_Subt_result[19]), .Y(n2608)
);
NOR2X1TS U3504 ( .A(Add_Subt_result[31]), .B(Add_Subt_result[32]), .Y(n2609)
);
NOR2X1TS U3505 ( .A(Add_Subt_result[53]), .B(Add_Subt_result[54]), .Y(n2650)
);
NOR2X2TS U3506 ( .A(n2778), .B(n2776), .Y(n3278) );
NOR2X1TS U3507 ( .A(Add_Subt_result[37]), .B(Add_Subt_result[38]), .Y(n2600)
);
NAND2X2TS U3508 ( .A(n2598), .B(n2600), .Y(n2610) );
NAND2X2TS U3509 ( .A(n2782), .B(n3351), .Y(n2765) );
NOR3BX2TS U3510 ( .AN(n2609), .B(n2765), .C(Add_Subt_result[33]), .Y(n2596)
);
NAND2X2TS U3511 ( .A(n2596), .B(n3352), .Y(n2777) );
NAND2X2TS U3512 ( .A(n2625), .B(n3363), .Y(n2636) );
NOR2X2TS U3513 ( .A(Add_Subt_result[24]), .B(n2636), .Y(n2597) );
NAND2X2TS U3514 ( .A(n2608), .B(n2630), .Y(n2581) );
NOR2X1TS U3515 ( .A(Add_Subt_result[12]), .B(Add_Subt_result[11]), .Y(n2573)
);
NAND2X2TS U3516 ( .A(n2573), .B(n2773), .Y(n2637) );
NAND2X2TS U3517 ( .A(n2582), .B(n3439), .Y(n2576) );
NOR2X1TS U3518 ( .A(Add_Subt_result[6]), .B(Add_Subt_result[5]), .Y(n2583)
);
NAND2X2TS U3519 ( .A(n2629), .B(n2583), .Y(n2635) );
NOR3X2TS U3520 ( .A(Add_Subt_result[4]), .B(Add_Subt_result[3]), .C(n2635),
.Y(n2607) );
AOI21X1TS U3521 ( .A0(n2572), .A1(Add_Subt_result[17]), .B0(n2606), .Y(n3291) );
NOR2X1TS U3522 ( .A(n2574), .B(n3451), .Y(n3287) );
NOR2XLTS U3523 ( .A(Add_Subt_result[8]), .B(Add_Subt_result[7]), .Y(n2577)
);
OAI22X1TS U3524 ( .A0(n2577), .A1(n2576), .B0(n2575), .B1(n2635), .Y(n2578)
);
AOI211X1TS U3525 ( .A0(n2773), .A1(n2579), .B0(n3287), .C0(n2578), .Y(n2658)
);
AOI31XLTS U3526 ( .A0(n3319), .A1(n3448), .A2(n3322), .B0(n2581), .Y(n2588)
);
OAI2BB1X1TS U3527 ( .A0N(n2583), .A1N(n3464), .B0(n2629), .Y(n2586) );
NOR4BX1TS U3528 ( .AN(n2658), .B(n2615), .C(n2588), .D(n2587), .Y(n2589) );
AOI21X1TS U3529 ( .A0(n3291), .A1(n2589), .B0(n3288), .Y(n2590) );
MX2X1TS U3530 ( .A(DMP[62]), .B(exp_oper_result[10]), .S0(n1745), .Y(
S_Oper_A_exp[10]) );
INVX2TS U3531 ( .A(n3475), .Y(n2595) );
AO21XLTS U3532 ( .A0(n2664), .A1(exp_oper_result[0]), .B0(n2594), .Y(n1438)
);
NOR4X1TS U3533 ( .A(Add_Subt_result[26]), .B(Add_Subt_result[29]), .C(
Add_Subt_result[28]), .D(Add_Subt_result[25]), .Y(n2604) );
OAI22X1TS U3534 ( .A0(n3283), .A1(n3351), .B0(n2600), .B1(n2599), .Y(n2601)
);
AOI211X1TS U3535 ( .A0(n2782), .A1(Add_Subt_result[33]), .B0(n2642), .C0(
n2601), .Y(n2603) );
NAND2X1TS U3536 ( .A(n2775), .B(n1642), .Y(n2624) );
OAI211XLTS U3537 ( .A0(n2604), .A1(n2777), .B0(n2603), .C0(n2624), .Y(n2605)
);
AOI211X1TS U3538 ( .A0(Add_Subt_result[2]), .A1(n2607), .B0(n2606), .C0(
n2605), .Y(n2617) );
NOR3X1TS U3539 ( .A(n2765), .B(Add_Subt_result[33]), .C(n2609), .Y(n2612) );
AOI2BB1X1TS U3540 ( .A0N(Add_Subt_result[35]), .A1N(Add_Subt_result[36]),
.B0(n2610), .Y(n2611) );
AOI32X1TS U3541 ( .A0(n3320), .A1(n2613), .A2(n3446), .B0(n2636), .B1(n2613),
.Y(n2614) );
AOI211X1TS U3542 ( .A0(n2630), .A1(n2616), .B0(n2615), .C0(n2614), .Y(n2662)
);
NOR2XLTS U3543 ( .A(Add_Subt_result[4]), .B(n3459), .Y(n2619) );
AOI21X1TS U3544 ( .A0(n3432), .A1(Add_Subt_result[39]), .B0(
Add_Subt_result[41]), .Y(n2620) );
NOR2BX1TS U3545 ( .AN(n3280), .B(n2620), .Y(n2621) );
AOI31XLTS U3546 ( .A0(Add_Subt_result[19]), .A1(n2630), .A2(n3440), .B0(
n2621), .Y(n2622) );
OAI211X1TS U3547 ( .A0(n2624), .A1(Add_Subt_result[22]), .B0(n2623), .C0(
n2622), .Y(n2767) );
AOI21X1TS U3548 ( .A0(Add_Subt_result[7]), .A1(n3344), .B0(
Add_Subt_result[9]), .Y(n2628) );
AOI32X1TS U3549 ( .A0(Add_Subt_result[23]), .A1(n2625), .A2(n3446), .B0(
Add_Subt_result[25]), .B1(n2625), .Y(n2626) );
OAI211X1TS U3550 ( .A0(n2628), .A1(n2627), .B0(n2626), .C0(n2655), .Y(n3286)
);
AOI22X1TS U3551 ( .A0(Add_Subt_result[20]), .A1(n2630), .B0(n2629), .B1(
Add_Subt_result[6]), .Y(n2634) );
OAI211X1TS U3552 ( .A0(n3458), .A1(n2635), .B0(n2634), .C0(n2633), .Y(n2772)
);
NOR3X1TS U3553 ( .A(n2767), .B(n3286), .C(n2772), .Y(n2646) );
NOR2XLTS U3554 ( .A(n3446), .B(n2636), .Y(n2644) );
AOI21X1TS U3555 ( .A0(n3450), .A1(n3344), .B0(n2637), .Y(n2643) );
OAI22X1TS U3556 ( .A0(n2640), .A1(n2639), .B0(n3447), .B1(n2638), .Y(n2641)
);
NOR4X1TS U3557 ( .A(n2644), .B(n2643), .C(n2642), .D(n2641), .Y(n2645) );
AOI21X1TS U3558 ( .A0(n2646), .A1(n2645), .B0(n3288), .Y(n2647) );
NOR3BX1TS U3559 ( .AN(Add_Subt_result[44]), .B(Add_Subt_result[45]), .C(
Add_Subt_result[46]), .Y(n2649) );
OAI31X1TS U3560 ( .A0(n2649), .A1(Add_Subt_result[47]), .A2(
Add_Subt_result[48]), .B0(n2648), .Y(n2651) );
OAI2BB1X1TS U3561 ( .A0N(n2652), .A1N(n2651), .B0(n2650), .Y(n2657) );
AOI21X1TS U3562 ( .A0(Add_Subt_result[16]), .A1(n2660), .B0(n2659), .Y(n2661) );
AOI21X1TS U3563 ( .A0(n2662), .A1(n2661), .B0(n3288), .Y(n2663) );
AOI22X1TS U3564 ( .A0(n2667), .A1(n1638), .B0(n2666), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n2668) );
MXI2X1TS U3565 ( .A(n2674), .B(n3365), .S0(n2673), .Y(n1469) );
AFHCONX2TS U3566 ( .A(n2677), .B(n2676), .CI(n2675), .CON(n2679), .S(n2678)
);
AFHCINX2TS U3567 ( .CIN(n2679), .B(n2680), .A(n2681), .S(n2682), .CO(n2691)
);
CMPR32X2TS U3568 ( .A(n2689), .B(n2688), .C(n2687), .CO(n1788), .S(n2690) );
CMPR32X2TS U3569 ( .A(n2693), .B(n2692), .C(n2691), .CO(n2687), .S(n2694) );
AFHCONX2TS U3570 ( .A(n2697), .B(n2696), .CI(n2695), .CON(n2699), .S(n2698)
);
AFHCINX2TS U3571 ( .CIN(n2699), .B(n2700), .A(n2701), .S(n2702), .CO(n2728)
);
AFHCINX4TS U3572 ( .CIN(n2703), .B(n2704), .A(n2705), .S(n2706), .CO(n2707)
);
AFHCINX4TS U3573 ( .CIN(n2712), .B(n2713), .A(n2714), .S(n2715), .CO(n2716)
);
AFHCINX2TS U3574 ( .CIN(n2720), .B(n2721), .A(n2722), .S(n2723), .CO(n2724)
);
AFHCONX2TS U3575 ( .A(n2730), .B(n2729), .CI(n2728), .CON(n2720), .S(n2731)
);
AFHCINX2TS U3576 ( .CIN(n2732), .B(n2733), .A(n2734), .S(n2735), .CO(n2695)
);
AFHCONX2TS U3577 ( .A(n2738), .B(n2737), .CI(n2736), .CON(n2732), .S(n2739)
);
AFHCINX2TS U3578 ( .CIN(n2740), .B(n2741), .A(n2742), .S(n2743), .CO(n2736)
);
AFHCONX2TS U3579 ( .A(n2746), .B(n2745), .CI(n2744), .CON(n2740), .S(n2747)
);
AFHCINX4TS U3580 ( .CIN(n2748), .B(n2749), .A(n2750), .S(n2751), .CO(n2752)
);
AFHCINX4TS U3581 ( .CIN(n2760), .B(n2761), .A(n2762), .S(n2763), .CO(n2973)
);
AOI21X1TS U3582 ( .A0(Add_Subt_result[27]), .A1(n3350), .B0(
Add_Subt_result[29]), .Y(n2771) );
AOI21X1TS U3583 ( .A0(n3438), .A1(Add_Subt_result[31]), .B0(
Add_Subt_result[33]), .Y(n2764) );
AOI211X1TS U3584 ( .A0(n3278), .A1(Add_Subt_result[47]), .B0(n2767), .C0(
n2766), .Y(n2770) );
OAI211X1TS U3585 ( .A0(n2771), .A1(n2777), .B0(n2770), .C0(n2769), .Y(n3285)
);
AOI211X1TS U3586 ( .A0(Add_Subt_result[12]), .A1(n2773), .B0(n3285), .C0(
n2772), .Y(n2785) );
AOI22X1TS U3587 ( .A0(n2775), .A1(Add_Subt_result[22]), .B0(
Add_Subt_result[14]), .B1(n2774), .Y(n2784) );
AO21XLTS U3588 ( .A0(n3444), .A1(Add_Subt_result[32]), .B0(
Add_Subt_result[34]), .Y(n2781) );
OAI22X1TS U3589 ( .A0(n2779), .A1(n2778), .B0(n2777), .B1(n3350), .Y(n2780)
);
AOI21X1TS U3590 ( .A0(n2782), .A1(n2781), .B0(n2780), .Y(n2783) );
AO21X1TS U3591 ( .A0(n1614), .A1(n3288), .B0(n2786), .Y(n1501) );
XNOR2X1TS U3592 ( .A(n2788), .B(n2787), .Y(n2789) );
MX2X1TS U3593 ( .A(n2789), .B(Add_Subt_result[0]), .S0(n2791), .Y(n1503) );
INVX2TS U3594 ( .A(n2790), .Y(n2794) );
MX2X1TS U3595 ( .A(n2792), .B(Add_Subt_result[1]), .S0(n2791), .Y(n1504) );
INVX2TS U3596 ( .A(n2795), .Y(n2797) );
NAND2X1TS U3597 ( .A(n2797), .B(n2796), .Y(n2798) );
XNOR2X1TS U3598 ( .A(n2799), .B(n2798), .Y(n2800) );
MX2X1TS U3599 ( .A(n2800), .B(Add_Subt_result[2]), .S0(n2791), .Y(n1505) );
INVX2TS U3600 ( .A(n2801), .Y(n2816) );
INVX2TS U3601 ( .A(n2802), .Y(n2807) );
NAND2X1TS U3602 ( .A(n2807), .B(n2805), .Y(n2803) );
XNOR2X1TS U3603 ( .A(n2816), .B(n2803), .Y(n2804) );
MX2X1TS U3604 ( .A(n2804), .B(Add_Subt_result[3]), .S0(n2791), .Y(n1506) );
INVX2TS U3605 ( .A(n2805), .Y(n2806) );
AOI21X1TS U3606 ( .A0(n2816), .A1(n2807), .B0(n2806), .Y(n2812) );
INVX2TS U3607 ( .A(n2808), .Y(n2810) );
NAND2X1TS U3608 ( .A(n2810), .B(n2809), .Y(n2811) );
XOR2X1TS U3609 ( .A(n2812), .B(n2811), .Y(n2813) );
MX2X1TS U3610 ( .A(n2813), .B(Add_Subt_result[4]), .S0(n2791), .Y(n1507) );
AOI21X1TS U3611 ( .A0(n2816), .A1(n2815), .B0(n2814), .Y(n2822) );
INVX2TS U3612 ( .A(n2821), .Y(n2817) );
NAND2X1TS U3613 ( .A(n2817), .B(n2820), .Y(n2818) );
XOR2X1TS U3614 ( .A(n2822), .B(n2818), .Y(n2819) );
MX2X1TS U3615 ( .A(n2819), .B(Add_Subt_result[5]), .S0(n2791), .Y(n1508) );
INVX2TS U3616 ( .A(n2823), .Y(n2825) );
NAND2X1TS U3617 ( .A(n2825), .B(n2824), .Y(n2826) );
XNOR2X1TS U3618 ( .A(n2827), .B(n2826), .Y(n2828) );
INVX2TS U3619 ( .A(n2829), .Y(n2860) );
INVX2TS U3620 ( .A(n2834), .Y(n2830) );
NAND2X1TS U3621 ( .A(n2830), .B(n2833), .Y(n2831) );
XOR2X1TS U3622 ( .A(n2860), .B(n2831), .Y(n2832) );
MX2X1TS U3623 ( .A(n2832), .B(Add_Subt_result[7]), .S0(n2791), .Y(n1510) );
INVX2TS U3624 ( .A(n2835), .Y(n2837) );
NAND2X1TS U3625 ( .A(n2837), .B(n2836), .Y(n2838) );
XNOR2X1TS U3626 ( .A(n2839), .B(n2838), .Y(n2840) );
INVX2TS U3627 ( .A(n2841), .Y(n2844) );
INVX2TS U3628 ( .A(n2842), .Y(n2843) );
OAI21X1TS U3629 ( .A0(n2860), .A1(n2844), .B0(n2843), .Y(n2851) );
INVX2TS U3630 ( .A(n2845), .Y(n2850) );
NAND2X1TS U3631 ( .A(n2850), .B(n2848), .Y(n2846) );
XNOR2X1TS U3632 ( .A(n2851), .B(n2846), .Y(n2847) );
INVX2TS U3633 ( .A(n2848), .Y(n2849) );
AOI21X1TS U3634 ( .A0(n2851), .A1(n2850), .B0(n2849), .Y(n2856) );
INVX2TS U3635 ( .A(n2852), .Y(n2854) );
NAND2X1TS U3636 ( .A(n2854), .B(n2853), .Y(n2855) );
XOR2X1TS U3637 ( .A(n2856), .B(n2855), .Y(n2857) );
OAI21X1TS U3638 ( .A0(n2860), .A1(n2859), .B0(n2858), .Y(n2867) );
INVX2TS U3639 ( .A(n2867), .Y(n2878) );
INVX2TS U3640 ( .A(n2861), .Y(n2866) );
NAND2X1TS U3641 ( .A(n2866), .B(n2864), .Y(n2862) );
XOR2X1TS U3642 ( .A(n2878), .B(n2862), .Y(n2863) );
INVX2TS U3643 ( .A(n2864), .Y(n2865) );
AOI21X1TS U3644 ( .A0(n2867), .A1(n2866), .B0(n2865), .Y(n2872) );
INVX2TS U3645 ( .A(n2868), .Y(n2870) );
NAND2X1TS U3646 ( .A(n2870), .B(n2869), .Y(n2871) );
XOR2X1TS U3647 ( .A(n2872), .B(n2871), .Y(n2873) );
INVX2TS U3648 ( .A(n2874), .Y(n2877) );
INVX2TS U3649 ( .A(n2875), .Y(n2876) );
OAI21X1TS U3650 ( .A0(n2878), .A1(n2877), .B0(n2876), .Y(n2885) );
INVX2TS U3651 ( .A(n2879), .Y(n2884) );
NAND2X1TS U3652 ( .A(n2884), .B(n2882), .Y(n2880) );
XNOR2X1TS U3653 ( .A(n2885), .B(n2880), .Y(n2881) );
INVX2TS U3654 ( .A(n2882), .Y(n2883) );
AOI21X1TS U3655 ( .A0(n2885), .A1(n2884), .B0(n2883), .Y(n2890) );
INVX2TS U3656 ( .A(n2886), .Y(n2888) );
NAND2X1TS U3657 ( .A(n2888), .B(n2887), .Y(n2889) );
XOR2X1TS U3658 ( .A(n2890), .B(n2889), .Y(n2891) );
INVX2TS U3659 ( .A(n2892), .Y(n2956) );
INVX2TS U3660 ( .A(n2893), .Y(n2898) );
NAND2X1TS U3661 ( .A(n2898), .B(n2896), .Y(n2894) );
XNOR2X1TS U3662 ( .A(n2956), .B(n2894), .Y(n2895) );
INVX2TS U3663 ( .A(n2896), .Y(n2897) );
AOI21X1TS U3664 ( .A0(n2956), .A1(n2898), .B0(n2897), .Y(n2903) );
INVX2TS U3665 ( .A(n2899), .Y(n2901) );
NAND2X1TS U3666 ( .A(n2901), .B(n2900), .Y(n2902) );
XOR2X1TS U3667 ( .A(n2903), .B(n2902), .Y(n2904) );
AOI21X1TS U3668 ( .A0(n2956), .A1(n2906), .B0(n2905), .Y(n2912) );
INVX2TS U3669 ( .A(n2911), .Y(n2907) );
NAND2X1TS U3670 ( .A(n2907), .B(n2910), .Y(n2908) );
XOR2X1TS U3671 ( .A(n2912), .B(n2908), .Y(n2909) );
INVX2TS U3672 ( .A(n2913), .Y(n2915) );
NAND2X1TS U3673 ( .A(n2915), .B(n2914), .Y(n2916) );
XNOR2X1TS U3674 ( .A(n2917), .B(n2916), .Y(n2918) );
AOI21X1TS U3675 ( .A0(n2956), .A1(n2922), .B0(n2921), .Y(n2928) );
INVX2TS U3676 ( .A(n2928), .Y(n2937) );
INVX2TS U3677 ( .A(n2927), .Y(n2923) );
NAND2X1TS U3678 ( .A(n2923), .B(n2926), .Y(n2924) );
XNOR2X1TS U3679 ( .A(n2937), .B(n2924), .Y(n2925) );
INVX2TS U3680 ( .A(n2929), .Y(n2931) );
NAND2X1TS U3681 ( .A(n2931), .B(n2930), .Y(n2932) );
XNOR2X1TS U3682 ( .A(n2933), .B(n2932), .Y(n2934) );
AOI21X1TS U3683 ( .A0(n2937), .A1(n2936), .B0(n2935), .Y(n2943) );
INVX2TS U3684 ( .A(n2942), .Y(n2938) );
NAND2X1TS U3685 ( .A(n2938), .B(n2941), .Y(n2939) );
XOR2X1TS U3686 ( .A(n2943), .B(n2939), .Y(n2940) );
INVX2TS U3687 ( .A(n2944), .Y(n2946) );
NAND2X1TS U3688 ( .A(n2946), .B(n2945), .Y(n2947) );
XNOR2X1TS U3689 ( .A(n2948), .B(n2947), .Y(n2949) );
AOI21X1TS U3690 ( .A0(n2956), .A1(n2955), .B0(n2954), .Y(n2962) );
INVX2TS U3691 ( .A(n2961), .Y(n2957) );
NAND2X1TS U3692 ( .A(n2957), .B(n2960), .Y(n2958) );
XOR2X1TS U3693 ( .A(n2962), .B(n2958), .Y(n2959) );
INVX2TS U3694 ( .A(n2963), .Y(n2965) );
NAND2X1TS U3695 ( .A(n2965), .B(n2964), .Y(n2966) );
XNOR2X1TS U3696 ( .A(n2967), .B(n2966), .Y(n2968) );
AFHCINX4TS U3697 ( .CIN(n2969), .B(n2970), .A(n2971), .S(n2972), .CO(n2950)
);
AO22XLTS U3698 ( .A0(n3296), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[0]), .B1(n2991), .Y(n1414) );
AO22XLTS U3699 ( .A0(n3296), .A1(Sgf_normalized_result[3]), .B0(
final_result_ieee[1]), .B1(n2991), .Y(n1413) );
AO22XLTS U3700 ( .A0(n3296), .A1(Sgf_normalized_result[4]), .B0(
final_result_ieee[2]), .B1(n2991), .Y(n1412) );
AO22XLTS U3701 ( .A0(n3296), .A1(Sgf_normalized_result[5]), .B0(
final_result_ieee[3]), .B1(n2991), .Y(n1411) );
AO22XLTS U3702 ( .A0(n3296), .A1(Sgf_normalized_result[6]), .B0(
final_result_ieee[4]), .B1(n2991), .Y(n1410) );
AO22XLTS U3703 ( .A0(n3296), .A1(Sgf_normalized_result[7]), .B0(
final_result_ieee[5]), .B1(n2991), .Y(n1409) );
AO22XLTS U3704 ( .A0(n3292), .A1(Sgf_normalized_result[12]), .B0(
final_result_ieee[10]), .B1(n2991), .Y(n1404) );
AO22XLTS U3705 ( .A0(n3292), .A1(Sgf_normalized_result[13]), .B0(
final_result_ieee[11]), .B1(n2991), .Y(n1403) );
AO22XLTS U3706 ( .A0(n3292), .A1(Sgf_normalized_result[14]), .B0(
final_result_ieee[12]), .B1(n3301), .Y(n1402) );
AO22XLTS U3707 ( .A0(n3292), .A1(Sgf_normalized_result[16]), .B0(
final_result_ieee[14]), .B1(n3301), .Y(n1400) );
AO22XLTS U3708 ( .A0(n3292), .A1(n1634), .B0(final_result_ieee[15]), .B1(
n3301), .Y(n1399) );
AO22XLTS U3709 ( .A0(n3292), .A1(n1633), .B0(final_result_ieee[16]), .B1(
n3301), .Y(n1398) );
AO22XLTS U3710 ( .A0(n3292), .A1(n1632), .B0(final_result_ieee[17]), .B1(
n3301), .Y(n1397) );
AO22XLTS U3711 ( .A0(n3296), .A1(n1631), .B0(final_result_ieee[18]), .B1(
n3301), .Y(n1396) );
AOI22X1TS U3712 ( .A0(n3239), .A1(n2994), .B0(n3003), .B1(n3000), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[54]) );
OAI22X1TS U3713 ( .A0(n3012), .A1(n2993), .B0(n3011), .B1(n2992), .Y(n3009)
);
OAI22X1TS U3714 ( .A0(n2997), .A1(n2996), .B0(n2995), .B1(n2994), .Y(n3008)
);
OAI22X1TS U3715 ( .A0(n3001), .A1(n3000), .B0(n2999), .B1(n2998), .Y(n3007)
);
OAI22X1TS U3716 ( .A0(n3005), .A1(n3004), .B0(n3003), .B1(n3002), .Y(n3006)
);
OR4X2TS U3717 ( .A(n3009), .B(n3008), .C(n3007), .D(n3006), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[48]) );
BUFX3TS U3718 ( .A(n3010), .Y(n3226) );
INVX2TS U3719 ( .A(n3011), .Y(n3022) );
AOI22X1TS U3720 ( .A0(n3226), .A1(n3019), .B0(n3237), .B1(n3022), .Y(n3018)
);
INVX2TS U3721 ( .A(n3012), .Y(n3024) );
AOI22X1TS U3722 ( .A0(n3227), .A1(n3024), .B0(n3167), .B1(n3030), .Y(n3017)
);
AOI22X1TS U3723 ( .A0(n3229), .A1(n3023), .B0(n3239), .B1(n3021), .Y(n3016)
);
BUFX3TS U3724 ( .A(n3148), .Y(n3231) );
AOI22X1TS U3725 ( .A0(n3231), .A1(n3014), .B0(n3248), .B1(n3020), .Y(n3015)
);
AOI22X1TS U3726 ( .A0(n3010), .A1(n3020), .B0(n3237), .B1(n3019), .Y(n3028)
);
AOI22X1TS U3727 ( .A0(n3246), .A1(n3022), .B0(n3244), .B1(n3021), .Y(n3027)
);
AOI22X1TS U3728 ( .A0(n3242), .A1(n3030), .B0(n2014), .B1(n3038), .Y(n3026)
);
AOI22X1TS U3729 ( .A0(n3071), .A1(n3024), .B0(n3107), .B1(n3023), .Y(n3025)
);
AOI22X1TS U3730 ( .A0(n3217), .A1(Add_Subt_result[13]), .B0(DmP[39]), .B1(
n3269), .Y(n3029) );
AOI22X1TS U3731 ( .A0(n3071), .A1(n3030), .B0(n3013), .B1(n3046), .Y(n3031)
);
OAI221XLTS U3732 ( .A0(n3092), .A1(n3032), .B0(n3079), .B1(n3048), .C0(n3031), .Y(Barrel_Shifter_module_Mux_Array_Data_array[41]) );
CLKBUFX2TS U3733 ( .A(n3095), .Y(n3090) );
AOI22X1TS U3734 ( .A0(n3228), .A1(Add_Subt_result[40]), .B0(DmP[38]), .B1(
n3054), .Y(n3033) );
OAI21X2TS U3735 ( .A0(n3322), .A1(n1807), .B0(n3033), .Y(n3063) );
AOI22X1TS U3736 ( .A0(n3242), .A1(n3056), .B0(n3227), .B1(n3038), .Y(n3035)
);
OAI221XLTS U3737 ( .A0(n3111), .A1(n3036), .B0(n3090), .B1(n3053), .C0(n3035), .Y(Barrel_Shifter_module_Mux_Array_Data_array[40]) );
AOI22X1TS U3738 ( .A0(n1608), .A1(Add_Subt_result[15]), .B0(DmP[37]), .B1(
n3216), .Y(n3037) );
AOI22X1TS U3739 ( .A0(n3013), .A1(n3056), .B0(n3071), .B1(n3038), .Y(n3039)
);
OAI221XLTS U3740 ( .A0(n3111), .A1(n3040), .B0(n3090), .B1(n3058), .C0(n3039), .Y(Barrel_Shifter_module_Mux_Array_Data_array[39]) );
AOI22X1TS U3741 ( .A0(n1858), .A1(Add_Subt_result[16]), .B0(DmP[36]), .B1(
n3054), .Y(n3041) );
OAI2BB1X2TS U3742 ( .A0N(Add_Subt_result[38]), .A1N(n3161), .B0(n3041), .Y(
n3070) );
AOI22X1TS U3743 ( .A0(n3013), .A1(n3059), .B0(n3071), .B1(n3042), .Y(n3043)
);
OAI221XLTS U3744 ( .A0(n3092), .A1(n3044), .B0(n3090), .B1(n3061), .C0(n3043), .Y(Barrel_Shifter_module_Mux_Array_Data_array[38]) );
AOI22X1TS U3745 ( .A0(n3217), .A1(Add_Subt_result[17]), .B0(DmP[35]), .B1(
n3054), .Y(n3045) );
AOI22X1TS U3746 ( .A0(n3071), .A1(n3046), .B0(n3013), .B1(n3063), .Y(n3047)
);
OAI221XLTS U3747 ( .A0(n3092), .A1(n3048), .B0(n3090), .B1(n3065), .C0(n3047), .Y(Barrel_Shifter_module_Mux_Array_Data_array[37]) );
AOI22X1TS U3748 ( .A0(n3139), .A1(Add_Subt_result[18]), .B0(DmP[34]), .B1(
n3216), .Y(n3049) );
AOI22X1TS U3749 ( .A0(n3242), .A1(n3070), .B0(n3051), .B1(n3056), .Y(n3052)
);
OAI221XLTS U3750 ( .A0(n3092), .A1(n3053), .B0(n3090), .B1(n3069), .C0(n3052), .Y(Barrel_Shifter_module_Mux_Array_Data_array[36]) );
AOI22X1TS U3751 ( .A0(n3217), .A1(Add_Subt_result[19]), .B0(DmP[33]), .B1(
n3269), .Y(n3055) );
AOI22X1TS U3752 ( .A0(n3013), .A1(n3070), .B0(n3071), .B1(n3056), .Y(n3057)
);
OAI221XLTS U3753 ( .A0(n3092), .A1(n3058), .B0(n3095), .B1(n3074), .C0(n3057), .Y(Barrel_Shifter_module_Mux_Array_Data_array[35]) );
AOI22X1TS U3754 ( .A0(n3107), .A1(n3076), .B0(n3071), .B1(n3059), .Y(n3060)
);
OAI221XLTS U3755 ( .A0(n3092), .A1(n3061), .B0(n3095), .B1(n3080), .C0(n3060), .Y(Barrel_Shifter_module_Mux_Array_Data_array[34]) );
AOI22X1TS U3756 ( .A0(n3071), .A1(n3063), .B0(n3013), .B1(n3082), .Y(n3064)
);
OAI221XLTS U3757 ( .A0(n3092), .A1(n3065), .B0(n3095), .B1(n3085), .C0(n3064), .Y(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
AOI22X1TS U3758 ( .A0(n3227), .A1(n3070), .B0(n3242), .B1(n3087), .Y(n3068)
);
OAI221XLTS U3759 ( .A0(n3092), .A1(n3069), .B0(n3095), .B1(n3091), .C0(n3068), .Y(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
AOI22X1TS U3760 ( .A0(n3071), .A1(n3070), .B0(n3013), .B1(n3087), .Y(n3072)
);
OAI221XLTS U3761 ( .A0(n3092), .A1(n3074), .B0(n3079), .B1(n3073), .C0(n3072), .Y(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
AOI22X1TS U3762 ( .A0(n3148), .A1(n3076), .B0(n3013), .B1(n3075), .Y(n3077)
);
OAI221XLTS U3763 ( .A0(n3092), .A1(n3080), .B0(n3079), .B1(n3078), .C0(n3077), .Y(Barrel_Shifter_module_Mux_Array_Data_array[30]) );
AOI22X1TS U3764 ( .A0(n3148), .A1(n3082), .B0(n3013), .B1(n3081), .Y(n3083)
);
OAI221XLTS U3765 ( .A0(n3092), .A1(n3085), .B0(n3090), .B1(n3084), .C0(n3083), .Y(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
AOI22X1TS U3766 ( .A0(n3227), .A1(n3087), .B0(n3242), .B1(n3086), .Y(n3088)
);
OAI221XLTS U3767 ( .A0(n3092), .A1(n3091), .B0(n3090), .B1(n3089), .C0(n3088), .Y(Barrel_Shifter_module_Mux_Array_Data_array[28]) );
AOI22X1TS U3768 ( .A0(n3107), .A1(n3116), .B0(n1863), .B1(n3122), .Y(n3100)
);
AOI22X1TS U3769 ( .A0(n3148), .A1(n3093), .B0(n3244), .B1(n3128), .Y(n3099)
);
AOI22X1TS U3770 ( .A0(n3246), .A1(n3094), .B0(n2014), .B1(n3134), .Y(n3098)
);
NAND2X1TS U3771 ( .A(n3096), .B(n3095), .Y(n3097) );
AOI22X1TS U3772 ( .A0(n3013), .A1(n3122), .B0(n3242), .B1(n3128), .Y(n3101)
);
OAI31X1TS U3773 ( .A0(n3111), .A1(n3110), .A2(n3102), .B0(n3101), .Y(n3106)
);
AOI22X1TS U3774 ( .A0(n3010), .A1(n3116), .B0(n3237), .B1(n3103), .Y(n3105)
);
AOI22X1TS U3775 ( .A0(n3167), .A1(n3134), .B0(n2014), .B1(n3141), .Y(n3104)
);
AOI22X1TS U3776 ( .A0(n3013), .A1(n3128), .B0(n3242), .B1(n3134), .Y(n3108)
);
OAI31X1TS U3777 ( .A0(n3111), .A1(n3110), .A2(n3109), .B0(n3108), .Y(n3114)
);
AOI22X1TS U3778 ( .A0(n3010), .A1(n3122), .B0(n3237), .B1(n3116), .Y(n3113)
);
AOI22X1TS U3779 ( .A0(n3167), .A1(n3141), .B0(n3239), .B1(n3147), .Y(n3112)
);
AOI22X1TS U3780 ( .A0(n3010), .A1(n3134), .B0(n3237), .B1(n3128), .Y(n3120)
);
AOI22X1TS U3781 ( .A0(n3246), .A1(n3122), .B0(n3244), .B1(n3155), .Y(n3119)
);
AOI22X1TS U3782 ( .A0(n1608), .A1(Add_Subt_result[36]), .B0(DmP[16]), .B1(
n3054), .Y(n3115) );
OAI21X4TS U3783 ( .A0(n3448), .A1(n3219), .B0(n3115), .Y(n3162) );
AOI22X1TS U3784 ( .A0(n3242), .A1(n3147), .B0(n2014), .B1(n3162), .Y(n3118)
);
AOI22X1TS U3785 ( .A0(n3148), .A1(n3116), .B0(n3107), .B1(n3141), .Y(n3117)
);
AOI22X1TS U3786 ( .A0(n3010), .A1(n3141), .B0(n3237), .B1(n3134), .Y(n3126)
);
AOI22X1TS U3787 ( .A0(n3246), .A1(n3128), .B0(n3244), .B1(n3162), .Y(n3125)
);
AOI22X1TS U3788 ( .A0(n1858), .A1(Add_Subt_result[37]), .B0(DmP[15]), .B1(
n3054), .Y(n3121) );
OAI2BB1X2TS U3789 ( .A0N(Add_Subt_result[17]), .A1N(n3161), .B0(n3121), .Y(
n3169) );
AOI22X1TS U3790 ( .A0(n3242), .A1(n3155), .B0(n2014), .B1(n3169), .Y(n3124)
);
AOI22X1TS U3791 ( .A0(n3148), .A1(n3122), .B0(n3248), .B1(n3147), .Y(n3123)
);
AOI22X1TS U3792 ( .A0(n3010), .A1(n3147), .B0(n3237), .B1(n3141), .Y(n3132)
);
AOI22X1TS U3793 ( .A0(n3246), .A1(n3134), .B0(n3244), .B1(n3169), .Y(n3131)
);
AOI22X1TS U3794 ( .A0(n3139), .A1(Add_Subt_result[38]), .B0(DmP[14]), .B1(
n3216), .Y(n3127) );
OAI21X4TS U3795 ( .A0(n3319), .A1(n3219), .B0(n3127), .Y(n3175) );
AOI22X1TS U3796 ( .A0(n3242), .A1(n3162), .B0(n2014), .B1(n3175), .Y(n3130)
);
AOI22X1TS U3797 ( .A0(n3148), .A1(n3128), .B0(n3107), .B1(n3155), .Y(n3129)
);
AOI22X1TS U3798 ( .A0(n3010), .A1(n3155), .B0(n3237), .B1(n3147), .Y(n3138)
);
AOI22X1TS U3799 ( .A0(n3246), .A1(n3141), .B0(n3244), .B1(n3175), .Y(n3137)
);
AOI22X1TS U3800 ( .A0(n1608), .A1(Add_Subt_result[39]), .B0(DmP[13]), .B1(
n3216), .Y(n3133) );
OAI21X4TS U3801 ( .A0(n3451), .A1(n3219), .B0(n3133), .Y(n3181) );
AOI22X1TS U3802 ( .A0(n3229), .A1(n3169), .B0(n2014), .B1(n3181), .Y(n3136)
);
AOI22X1TS U3803 ( .A0(n3148), .A1(n3134), .B0(n3248), .B1(n3162), .Y(n3135)
);
AOI22X1TS U3804 ( .A0(n3010), .A1(n3162), .B0(n3237), .B1(n3155), .Y(n3145)
);
AOI22X1TS U3805 ( .A0(n3246), .A1(n3147), .B0(n3244), .B1(n3181), .Y(n3144)
);
AOI22X1TS U3806 ( .A0(n1608), .A1(Add_Subt_result[40]), .B0(DmP[12]), .B1(
n3216), .Y(n3140) );
OAI21X4TS U3807 ( .A0(n3322), .A1(n3219), .B0(n3140), .Y(n3187) );
AOI22X1TS U3808 ( .A0(n3242), .A1(n3175), .B0(n2014), .B1(n3187), .Y(n3143)
);
AOI22X1TS U3809 ( .A0(n3148), .A1(n3141), .B0(n3107), .B1(n3169), .Y(n3142)
);
AOI22X1TS U3810 ( .A0(n3010), .A1(n3169), .B0(n3237), .B1(n3162), .Y(n3152)
);
AOI22X1TS U3811 ( .A0(n3246), .A1(n3155), .B0(n3244), .B1(n3187), .Y(n3151)
);
AOI22X1TS U3812 ( .A0(n1608), .A1(Add_Subt_result[41]), .B0(DmP[11]), .B1(
n3153), .Y(n3146) );
OAI2BB1X2TS U3813 ( .A0N(Add_Subt_result[13]), .A1N(n3161), .B0(n3146), .Y(
n3193) );
AOI22X1TS U3814 ( .A0(n3242), .A1(n3181), .B0(n2014), .B1(n3193), .Y(n3150)
);
AOI22X1TS U3815 ( .A0(n3148), .A1(n3147), .B0(n3248), .B1(n3175), .Y(n3149)
);
AOI22X1TS U3816 ( .A0(n3226), .A1(n3175), .B0(n3237), .B1(n3169), .Y(n3159)
);
AOI22X1TS U3817 ( .A0(n3246), .A1(n3162), .B0(n3244), .B1(n3193), .Y(n3158)
);
AOI22X1TS U3818 ( .A0(n1608), .A1(Add_Subt_result[42]), .B0(DmP[10]), .B1(
n3153), .Y(n3154) );
OAI21X4TS U3819 ( .A0(n3449), .A1(n3219), .B0(n3154), .Y(n3199) );
AOI22X1TS U3820 ( .A0(n3229), .A1(n3187), .B0(n2014), .B1(n3199), .Y(n3157)
);
AOI22X1TS U3821 ( .A0(n3231), .A1(n3155), .B0(n3107), .B1(n3181), .Y(n3156)
);
AOI22X1TS U3822 ( .A0(n3226), .A1(n3181), .B0(n3225), .B1(n3175), .Y(n3166)
);
AOI22X1TS U3823 ( .A0(n3227), .A1(n3169), .B0(n3244), .B1(n3199), .Y(n3165)
);
AOI22X1TS U3824 ( .A0(n1608), .A1(Add_Subt_result[43]), .B0(DmP[9]), .B1(
n3054), .Y(n3160) );
OAI2BB1X2TS U3825 ( .A0N(Add_Subt_result[11]), .A1N(n3161), .B0(n3160), .Y(
n3205) );
AOI22X1TS U3826 ( .A0(n3229), .A1(n3193), .B0(n2014), .B1(n3205), .Y(n3164)
);
AOI22X1TS U3827 ( .A0(n3231), .A1(n3162), .B0(n3248), .B1(n3187), .Y(n3163)
);
AOI22X1TS U3828 ( .A0(n3226), .A1(n3187), .B0(n3225), .B1(n3181), .Y(n3173)
);
AOI22X1TS U3829 ( .A0(n3227), .A1(n3175), .B0(n3167), .B1(n3205), .Y(n3172)
);
AOI22X1TS U3830 ( .A0(n3139), .A1(Add_Subt_result[44]), .B0(DmP[8]), .B1(
n3153), .Y(n3168) );
OAI21X4TS U3831 ( .A0(n3450), .A1(n3219), .B0(n3168), .Y(n3211) );
AOI22X1TS U3832 ( .A0(n3229), .A1(n3199), .B0(n3239), .B1(n3211), .Y(n3171)
);
AOI22X1TS U3833 ( .A0(n3231), .A1(n3169), .B0(n3107), .B1(n3193), .Y(n3170)
);
AOI22X1TS U3834 ( .A0(n3226), .A1(n3193), .B0(n3225), .B1(n3187), .Y(n3179)
);
AOI22X1TS U3835 ( .A0(n3227), .A1(n3181), .B0(n3167), .B1(n3211), .Y(n3178)
);
AOI22X1TS U3836 ( .A0(n3139), .A1(Add_Subt_result[45]), .B0(DmP[7]), .B1(
n3054), .Y(n3174) );
OAI21X4TS U3837 ( .A0(n3439), .A1(n3219), .B0(n3174), .Y(n3220) );
AOI22X1TS U3838 ( .A0(n3229), .A1(n3205), .B0(n3239), .B1(n3220), .Y(n3177)
);
AOI22X1TS U3839 ( .A0(n3231), .A1(n3175), .B0(n3248), .B1(n3199), .Y(n3176)
);
AOI22X1TS U3840 ( .A0(n3226), .A1(n3199), .B0(n3225), .B1(n3193), .Y(n3185)
);
AOI22X1TS U3841 ( .A0(n3227), .A1(n3187), .B0(n3167), .B1(n3220), .Y(n3184)
);
AOI22X1TS U3842 ( .A0(n1608), .A1(Add_Subt_result[46]), .B0(DmP[6]), .B1(
n3054), .Y(n3180) );
OAI21X4TS U3843 ( .A0(n3344), .A1(n1821), .B0(n3180), .Y(n3230) );
AOI22X1TS U3844 ( .A0(n3229), .A1(n3211), .B0(n3239), .B1(n3230), .Y(n3183)
);
AOI22X1TS U3845 ( .A0(n3231), .A1(n3181), .B0(n3107), .B1(n3205), .Y(n3182)
);
AOI22X1TS U3846 ( .A0(n3226), .A1(n3205), .B0(n3225), .B1(n3199), .Y(n3191)
);
AOI22X1TS U3847 ( .A0(n3227), .A1(n3193), .B0(n3167), .B1(n3230), .Y(n3190)
);
AOI22X1TS U3848 ( .A0(n3139), .A1(Add_Subt_result[47]), .B0(DmP[5]), .B1(
n3153), .Y(n3186) );
OAI2BB1X2TS U3849 ( .A0N(Add_Subt_result[7]), .A1N(n3228), .B0(n3186), .Y(
n3249) );
AOI22X1TS U3850 ( .A0(n3229), .A1(n3220), .B0(n3239), .B1(n3249), .Y(n3189)
);
AOI22X1TS U3851 ( .A0(n3231), .A1(n3187), .B0(n3248), .B1(n3211), .Y(n3188)
);
AOI22X1TS U3852 ( .A0(n3226), .A1(n3211), .B0(n3225), .B1(n3205), .Y(n3197)
);
AOI22X1TS U3853 ( .A0(n3246), .A1(n3199), .B0(n3167), .B1(n3249), .Y(n3196)
);
AOI22X1TS U3854 ( .A0(n3139), .A1(Add_Subt_result[48]), .B0(DmP[4]), .B1(
n3153), .Y(n3192) );
AOI22X1TS U3855 ( .A0(n3229), .A1(n3230), .B0(n2014), .B1(n3245), .Y(n3195)
);
AOI22X1TS U3856 ( .A0(n3231), .A1(n3193), .B0(n3248), .B1(n3220), .Y(n3194)
);
AOI22X1TS U3857 ( .A0(n3226), .A1(n3220), .B0(n3225), .B1(n3211), .Y(n3203)
);
AOI22X1TS U3858 ( .A0(n3227), .A1(n3205), .B0(n3244), .B1(n3245), .Y(n3202)
);
AOI22X1TS U3859 ( .A0(n1608), .A1(Add_Subt_result[49]), .B0(n1609), .B1(
n3054), .Y(n3198) );
OAI2BB1X2TS U3860 ( .A0N(Add_Subt_result[5]), .A1N(n1808), .B0(n3198), .Y(
n3236) );
AOI22X1TS U3861 ( .A0(n3229), .A1(n3249), .B0(n3239), .B1(n3236), .Y(n3201)
);
AOI22X1TS U3862 ( .A0(n3231), .A1(n3199), .B0(n3107), .B1(n3230), .Y(n3200)
);
AOI22X1TS U3863 ( .A0(n3226), .A1(n3230), .B0(n3225), .B1(n3220), .Y(n3209)
);
AOI22X1TS U3864 ( .A0(n3246), .A1(n3211), .B0(n3167), .B1(n3236), .Y(n3208)
);
AOI22X1TS U3865 ( .A0(n3139), .A1(Add_Subt_result[50]), .B0(DmP[2]), .B1(
n3216), .Y(n3204) );
AOI22X1TS U3866 ( .A0(n3229), .A1(n3245), .B0(n3239), .B1(n3240), .Y(n3207)
);
AOI22X1TS U3867 ( .A0(n3231), .A1(n3205), .B0(n3107), .B1(n3249), .Y(n3206)
);
AOI22X1TS U3868 ( .A0(n3226), .A1(n3249), .B0(n3225), .B1(n3230), .Y(n3215)
);
AOI22X1TS U3869 ( .A0(n3227), .A1(n3220), .B0(n3167), .B1(n3240), .Y(n3214)
);
AOI22X1TS U3870 ( .A0(n1608), .A1(Add_Subt_result[51]), .B0(DmP[1]), .B1(
n3216), .Y(n3210) );
AOI22X1TS U3871 ( .A0(n3229), .A1(n3236), .B0(n3239), .B1(n3247), .Y(n3213)
);
AOI22X1TS U3872 ( .A0(n3231), .A1(n3211), .B0(n3248), .B1(n3245), .Y(n3212)
);
AOI22X1TS U3873 ( .A0(n3226), .A1(n3245), .B0(n3225), .B1(n3249), .Y(n3224)
);
AOI22X1TS U3874 ( .A0(n3139), .A1(Add_Subt_result[52]), .B0(DmP[0]), .B1(
n3216), .Y(n3218) );
AOI22X1TS U3875 ( .A0(n3246), .A1(n3230), .B0(n3239), .B1(n3241), .Y(n3223)
);
AOI22X1TS U3876 ( .A0(n3229), .A1(n3240), .B0(n3167), .B1(n3247), .Y(n3222)
);
AOI22X1TS U3877 ( .A0(n3231), .A1(n3220), .B0(n3248), .B1(n3236), .Y(n3221)
);
AOI22X1TS U3878 ( .A0(n3226), .A1(n3236), .B0(n3225), .B1(n3245), .Y(n3235)
);
AOI22X1TS U3879 ( .A0(n3246), .A1(n3249), .B0(n3167), .B1(n3241), .Y(n3234)
);
AOI22X1TS U3880 ( .A0(n3229), .A1(n3247), .B0(n3239), .B1(n3243), .Y(n3233)
);
AOI22X1TS U3881 ( .A0(n3231), .A1(n3230), .B0(n3107), .B1(n3240), .Y(n3232)
);
OAI22X1TS U3882 ( .A0(n1821), .A1(n3468), .B0(n3345), .B1(n1807), .Y(n3238)
);
AOI22X1TS U3883 ( .A0(n3239), .A1(n3238), .B0(n3237), .B1(n3236), .Y(n3253)
);
AOI22X1TS U3884 ( .A0(n3229), .A1(n3241), .B0(n3010), .B1(n3240), .Y(n3252)
);
AOI22X1TS U3885 ( .A0(n3246), .A1(n3245), .B0(n3244), .B1(n3243), .Y(n3251)
);
AOI22X1TS U3886 ( .A0(n3148), .A1(n3249), .B0(n3248), .B1(n3247), .Y(n3250)
);
AOI21X1TS U3887 ( .A0(n3256), .A1(n3255), .B0(n3254), .Y(n3265) );
INVX2TS U3888 ( .A(n3257), .Y(n3260) );
AOI211X1TS U3889 ( .A0(n3270), .A1(n3054), .B0(n3268), .C0(n3267), .Y(n3274)
);
AOI21X1TS U3890 ( .A0(n3457), .A1(Add_Subt_result[49]), .B0(
Add_Subt_result[51]), .Y(n3275) );
AOI2BB1XLTS U3891 ( .A0N(n3275), .A1N(Add_Subt_result[52]), .B0(
Add_Subt_result[53]), .Y(n3276) );
NOR2XLTS U3892 ( .A(n3276), .B(Add_Subt_result[54]), .Y(n3277) );
AOI31XLTS U3893 ( .A0(n3278), .A1(Add_Subt_result[45]), .A2(n3456), .B0(
n3277), .Y(n3282) );
OAI211X1TS U3894 ( .A0(n3283), .A1(n3463), .B0(n3282), .C0(n3281), .Y(n3284)
);
NOR4X1TS U3895 ( .A(n3287), .B(n3286), .C(n3285), .D(n3284), .Y(n3289) );
AOI32X1TS U3896 ( .A0(n3291), .A1(n3290), .A2(n3289), .B0(n3474), .B1(n3288),
.Y(n1499) );
INVX2TS U3897 ( .A(n3292), .Y(n3293) );
OA22X1TS U3898 ( .A0(n3298), .A1(final_result_ieee[52]), .B0(
exp_oper_result[0]), .B1(n3293), .Y(n1425) );
OA22X1TS U3899 ( .A0(exp_oper_result[1]), .A1(n3293), .B0(n3294), .B1(
final_result_ieee[53]), .Y(n1424) );
OA22X1TS U3900 ( .A0(n3294), .A1(final_result_ieee[54]), .B0(
exp_oper_result[2]), .B1(n3293), .Y(n1423) );
INVX4TS U3901 ( .A(n3296), .Y(n3295) );
OA22X1TS U3902 ( .A0(exp_oper_result[3]), .A1(n3295), .B0(n3294), .B1(
final_result_ieee[55]), .Y(n1422) );
OA22X1TS U3903 ( .A0(exp_oper_result[4]), .A1(n3295), .B0(n3294), .B1(
final_result_ieee[56]), .Y(n1421) );
OA22X1TS U3904 ( .A0(n3294), .A1(final_result_ieee[57]), .B0(
exp_oper_result[5]), .B1(n3293), .Y(n1420) );
OA22X1TS U3905 ( .A0(exp_oper_result[6]), .A1(n3295), .B0(n3294), .B1(
final_result_ieee[58]), .Y(n1419) );
OA22X1TS U3906 ( .A0(exp_oper_result[7]), .A1(n3295), .B0(n3298), .B1(
final_result_ieee[59]), .Y(n1418) );
OA22X1TS U3907 ( .A0(exp_oper_result[8]), .A1(n3295), .B0(n3298), .B1(
final_result_ieee[60]), .Y(n1417) );
OA22X1TS U3908 ( .A0(exp_oper_result[9]), .A1(n3295), .B0(n3298), .B1(
final_result_ieee[61]), .Y(n1416) );
OA22X1TS U3909 ( .A0(exp_oper_result[10]), .A1(n3295), .B0(n3298), .B1(
final_result_ieee[62]), .Y(n1415) );
OAI2BB2XLTS U3910 ( .B0(n3356), .B1(n3295), .A0N(final_result_ieee[19]),
.A1N(n3301), .Y(n1395) );
OAI2BB2XLTS U3911 ( .B0(n3357), .B1(n3295), .A0N(final_result_ieee[20]),
.A1N(n3297), .Y(n1394) );
OAI2BB2XLTS U3912 ( .B0(n3323), .B1(n3295), .A0N(final_result_ieee[21]),
.A1N(n3297), .Y(n1393) );
OAI2BB2XLTS U3913 ( .B0(n3324), .B1(n3295), .A0N(final_result_ieee[22]),
.A1N(n3297), .Y(n1392) );
OAI2BB2XLTS U3914 ( .B0(n3325), .B1(n3295), .A0N(final_result_ieee[23]),
.A1N(n3297), .Y(n1391) );
OAI2BB2XLTS U3915 ( .B0(n3326), .B1(n3295), .A0N(final_result_ieee[24]),
.A1N(n3297), .Y(n1390) );
OAI2BB2XLTS U3916 ( .B0(n3365), .B1(n3295), .A0N(final_result_ieee[25]),
.A1N(n3297), .Y(n1389) );
OAI2BB2XLTS U3917 ( .B0(n3368), .B1(n3295), .A0N(final_result_ieee[26]),
.A1N(n3297), .Y(n1388) );
INVX4TS U3918 ( .A(n3296), .Y(n3302) );
OAI2BB2XLTS U3919 ( .B0(n3369), .B1(n3302), .A0N(final_result_ieee[27]),
.A1N(n3297), .Y(n1387) );
OAI2BB2XLTS U3920 ( .B0(n3370), .B1(n3302), .A0N(final_result_ieee[28]),
.A1N(n3297), .Y(n1386) );
OAI2BB2XLTS U3921 ( .B0(n3371), .B1(n3302), .A0N(final_result_ieee[29]),
.A1N(n3297), .Y(n1385) );
OAI2BB2XLTS U3922 ( .B0(n3381), .B1(n3302), .A0N(final_result_ieee[30]),
.A1N(n3297), .Y(n1384) );
OAI2BB2XLTS U3923 ( .B0(n3382), .B1(n3302), .A0N(final_result_ieee[31]),
.A1N(n3297), .Y(n1383) );
INVX4TS U3924 ( .A(n3298), .Y(n3299) );
OAI2BB2XLTS U3925 ( .B0(n3383), .B1(n3302), .A0N(final_result_ieee[32]),
.A1N(n3299), .Y(n1382) );
OAI2BB2XLTS U3926 ( .B0(n3384), .B1(n3302), .A0N(final_result_ieee[33]),
.A1N(n3299), .Y(n1381) );
OAI2BB2XLTS U3927 ( .B0(n3394), .B1(n3302), .A0N(final_result_ieee[34]),
.A1N(n3299), .Y(n1380) );
OAI2BB2XLTS U3928 ( .B0(n3395), .B1(n3302), .A0N(final_result_ieee[35]),
.A1N(n3299), .Y(n1379) );
OAI2BB2XLTS U3929 ( .B0(n3414), .B1(n3302), .A0N(final_result_ieee[36]),
.A1N(n3299), .Y(n1378) );
OAI2BB2XLTS U3930 ( .B0(n3415), .B1(n3302), .A0N(final_result_ieee[37]),
.A1N(n3299), .Y(n1377) );
OAI2BB2XLTS U3931 ( .B0(n3416), .B1(n3302), .A0N(final_result_ieee[38]),
.A1N(n3299), .Y(n1376) );
OAI2BB2XLTS U3932 ( .B0(n3417), .B1(n3302), .A0N(final_result_ieee[39]),
.A1N(n3299), .Y(n1375) );
OAI2BB2XLTS U3933 ( .B0(n3433), .B1(n3302), .A0N(final_result_ieee[40]),
.A1N(n3299), .Y(n1374) );
OAI2BB2XLTS U3934 ( .B0(n3434), .B1(n3300), .A0N(final_result_ieee[41]),
.A1N(n3299), .Y(n1373) );
OAI2BB2XLTS U3935 ( .B0(n3441), .B1(n3300), .A0N(final_result_ieee[42]),
.A1N(n3299), .Y(n1372) );
OAI2BB2XLTS U3936 ( .B0(n3442), .B1(n3300), .A0N(final_result_ieee[43]),
.A1N(n3299), .Y(n1371) );
OAI2BB2XLTS U3937 ( .B0(n3443), .B1(n3300), .A0N(final_result_ieee[44]),
.A1N(n3299), .Y(n1370) );
OAI2BB2XLTS U3938 ( .B0(n3453), .B1(n3300), .A0N(final_result_ieee[45]),
.A1N(n3299), .Y(n1369) );
OAI2BB2XLTS U3939 ( .B0(n3454), .B1(n3300), .A0N(final_result_ieee[46]),
.A1N(n3299), .Y(n1368) );
OAI2BB2XLTS U3940 ( .B0(n3455), .B1(n3300), .A0N(final_result_ieee[47]),
.A1N(n3301), .Y(n1367) );
OAI2BB2XLTS U3941 ( .B0(n3460), .B1(n3300), .A0N(final_result_ieee[48]),
.A1N(n3301), .Y(n1366) );
OAI2BB2XLTS U3942 ( .B0(n3461), .B1(n3300), .A0N(final_result_ieee[49]),
.A1N(n3301), .Y(n1365) );
OAI2BB2XLTS U3943 ( .B0(n3462), .B1(n3300), .A0N(final_result_ieee[50]),
.A1N(n3301), .Y(n1364) );
OAI2BB2XLTS U3944 ( .B0(n3470), .B1(n3302), .A0N(final_result_ieee[51]),
.A1N(n3301), .Y(n1363) );
AO22XLTS U3945 ( .A0(n3303), .A1(intDX[62]), .B0(n1626), .B1(Data_X[62]),
.Y(n1359) );
AO22XLTS U3946 ( .A0(n3303), .A1(intDX[61]), .B0(n1626), .B1(Data_X[61]),
.Y(n1358) );
AO22XLTS U3947 ( .A0(n3303), .A1(intDX[60]), .B0(n1626), .B1(Data_X[60]),
.Y(n1357) );
AO22XLTS U3948 ( .A0(n3303), .A1(intDX[59]), .B0(n1626), .B1(Data_X[59]),
.Y(n1356) );
INVX4TS U3949 ( .A(n1646), .Y(n3304) );
AO22XLTS U3950 ( .A0(n3304), .A1(intDX[58]), .B0(n1626), .B1(Data_X[58]),
.Y(n1355) );
BUFX3TS U3951 ( .A(n1646), .Y(n3313) );
AO22XLTS U3952 ( .A0(n3304), .A1(intDX[57]), .B0(n3313), .B1(Data_X[57]),
.Y(n1354) );
AO22XLTS U3953 ( .A0(n3304), .A1(intDX[56]), .B0(n3313), .B1(Data_X[56]),
.Y(n1353) );
AO22XLTS U3954 ( .A0(n3304), .A1(intDX[55]), .B0(n3313), .B1(Data_X[55]),
.Y(n1352) );
AO22XLTS U3955 ( .A0(n3304), .A1(intDX[54]), .B0(n3313), .B1(Data_X[54]),
.Y(n1351) );
AO22XLTS U3956 ( .A0(n3304), .A1(intDX[53]), .B0(n3313), .B1(Data_X[53]),
.Y(n1350) );
AO22XLTS U3957 ( .A0(n3304), .A1(intDX[52]), .B0(n3313), .B1(Data_X[52]),
.Y(n1349) );
AO22XLTS U3958 ( .A0(n3304), .A1(intDX[51]), .B0(n3313), .B1(Data_X[51]),
.Y(n1348) );
AO22XLTS U3959 ( .A0(n3304), .A1(intDX[50]), .B0(n3313), .B1(Data_X[50]),
.Y(n1347) );
AO22XLTS U3960 ( .A0(n3304), .A1(intDX[49]), .B0(n3313), .B1(Data_X[49]),
.Y(n1346) );
AO22XLTS U3961 ( .A0(n3304), .A1(intDX[48]), .B0(n3313), .B1(Data_X[48]),
.Y(n1345) );
AO22XLTS U3962 ( .A0(n3304), .A1(intDX[47]), .B0(n3313), .B1(Data_X[47]),
.Y(n1344) );
BUFX3TS U3963 ( .A(n1646), .Y(n3314) );
AO22XLTS U3964 ( .A0(n3304), .A1(intDX[46]), .B0(n3314), .B1(Data_X[46]),
.Y(n1343) );
AO22XLTS U3965 ( .A0(n3304), .A1(intDX[45]), .B0(n3314), .B1(Data_X[45]),
.Y(n1342) );
BUFX3TS U3966 ( .A(n3314), .Y(n3316) );
INVX4TS U3967 ( .A(n3316), .Y(n3305) );
AO22XLTS U3968 ( .A0(n3305), .A1(intDX[44]), .B0(n3314), .B1(Data_X[44]),
.Y(n1341) );
AO22XLTS U3969 ( .A0(n3304), .A1(intDX[43]), .B0(n3314), .B1(Data_X[43]),
.Y(n1340) );
AO22XLTS U3970 ( .A0(n3305), .A1(intDX[42]), .B0(n3314), .B1(Data_X[42]),
.Y(n1339) );
AO22XLTS U3971 ( .A0(n3305), .A1(intDX[41]), .B0(n3314), .B1(Data_X[41]),
.Y(n1338) );
AO22XLTS U3972 ( .A0(n3305), .A1(intDX[40]), .B0(n3314), .B1(Data_X[40]),
.Y(n1337) );
AO22XLTS U3973 ( .A0(n3305), .A1(intDX[39]), .B0(n3314), .B1(Data_X[39]),
.Y(n1336) );
AO22XLTS U3974 ( .A0(n3305), .A1(intDX[38]), .B0(n3314), .B1(Data_X[38]),
.Y(n1335) );
AO22XLTS U3975 ( .A0(n3305), .A1(intDX[37]), .B0(n3314), .B1(Data_X[37]),
.Y(n1334) );
AO22XLTS U3976 ( .A0(n3305), .A1(intDX[36]), .B0(n3314), .B1(Data_X[36]),
.Y(n1333) );
BUFX3TS U3977 ( .A(n1646), .Y(n3310) );
AO22XLTS U3978 ( .A0(n3305), .A1(intDX[35]), .B0(n3310), .B1(Data_X[35]),
.Y(n1332) );
AO22XLTS U3979 ( .A0(n3305), .A1(intDX[34]), .B0(n3310), .B1(Data_X[34]),
.Y(n1331) );
AO22XLTS U3980 ( .A0(n3305), .A1(intDX[33]), .B0(n3310), .B1(Data_X[33]),
.Y(n1330) );
AO22XLTS U3981 ( .A0(n3305), .A1(intDX[32]), .B0(n3310), .B1(Data_X[32]),
.Y(n1329) );
INVX4TS U3982 ( .A(n3316), .Y(n3306) );
AO22XLTS U3983 ( .A0(n3306), .A1(intDX[31]), .B0(n3310), .B1(Data_X[31]),
.Y(n1328) );
AO22XLTS U3984 ( .A0(n3305), .A1(intDX[30]), .B0(n3310), .B1(Data_X[30]),
.Y(n1327) );
AO22XLTS U3985 ( .A0(n3305), .A1(intDX[29]), .B0(n3310), .B1(Data_X[29]),
.Y(n1326) );
AO22XLTS U3986 ( .A0(n3305), .A1(intDX[28]), .B0(n3310), .B1(Data_X[28]),
.Y(n1325) );
AO22XLTS U3987 ( .A0(n3306), .A1(intDX[27]), .B0(n3310), .B1(Data_X[27]),
.Y(n1324) );
AO22XLTS U3988 ( .A0(n3306), .A1(intDX[26]), .B0(n3310), .B1(Data_X[26]),
.Y(n1323) );
AO22XLTS U3989 ( .A0(n3306), .A1(intDX[25]), .B0(n3310), .B1(Data_X[25]),
.Y(n1322) );
AO22XLTS U3990 ( .A0(n3306), .A1(intDX[24]), .B0(n3312), .B1(Data_X[24]),
.Y(n1321) );
AO22XLTS U3991 ( .A0(n3306), .A1(intDX[23]), .B0(n3312), .B1(Data_X[23]),
.Y(n1320) );
AO22XLTS U3992 ( .A0(n3306), .A1(intDX[22]), .B0(n3312), .B1(Data_X[22]),
.Y(n1319) );
AO22XLTS U3993 ( .A0(n3306), .A1(intDX[21]), .B0(n3312), .B1(Data_X[21]),
.Y(n1318) );
AO22XLTS U3994 ( .A0(n3306), .A1(intDX[20]), .B0(n3312), .B1(Data_X[20]),
.Y(n1317) );
AO22XLTS U3995 ( .A0(n3306), .A1(intDX[19]), .B0(n3312), .B1(Data_X[19]),
.Y(n1316) );
AO22XLTS U3996 ( .A0(n3306), .A1(intDY[62]), .B0(n3312), .B1(Data_Y[62]),
.Y(n1294) );
INVX4TS U3997 ( .A(n3316), .Y(n3307) );
AO22XLTS U3998 ( .A0(n3312), .A1(Data_Y[61]), .B0(n3307), .B1(intDY[61]),
.Y(n1293) );
AO22XLTS U3999 ( .A0(n3311), .A1(Data_Y[52]), .B0(n3307), .B1(intDY[52]),
.Y(n1284) );
AO22XLTS U4000 ( .A0(n3311), .A1(Data_Y[48]), .B0(n3306), .B1(intDY[48]),
.Y(n1280) );
BUFX3TS U4001 ( .A(n1646), .Y(n3308) );
AO22XLTS U4002 ( .A0(n3308), .A1(Data_Y[44]), .B0(n3307), .B1(intDY[44]),
.Y(n1276) );
INVX4TS U4003 ( .A(n3316), .Y(n3309) );
AO22XLTS U4004 ( .A0(n3308), .A1(Data_Y[38]), .B0(n3309), .B1(intDY[38]),
.Y(n1270) );
AO22XLTS U4005 ( .A0(n3308), .A1(Data_Y[37]), .B0(n3309), .B1(intDY[37]),
.Y(n1269) );
INVX4TS U4006 ( .A(n3316), .Y(n3315) );
BUFX3TS U4007 ( .A(n1646), .Y(n3317) );
AO22XLTS U4008 ( .A0(n3312), .A1(Data_Y[16]), .B0(n3315), .B1(intDY[16]),
.Y(n1248) );
AO22XLTS U4009 ( .A0(n3317), .A1(Data_Y[12]), .B0(n1627), .B1(intDY[12]),
.Y(n1244) );
AO22XLTS U4010 ( .A0(n3317), .A1(Data_Y[11]), .B0(n1627), .B1(intDY[11]),
.Y(n1243) );
AO22XLTS U4011 ( .A0(n3317), .A1(Data_Y[10]), .B0(n1627), .B1(intDY[10]),
.Y(n1242) );
AO22XLTS U4012 ( .A0(n3317), .A1(Data_Y[9]), .B0(n1627), .B1(intDY[9]), .Y(
n1241) );
AO22XLTS U4013 ( .A0(n3317), .A1(Data_Y[8]), .B0(n1627), .B1(intDY[8]), .Y(
n1240) );
AO22XLTS U4014 ( .A0(n3317), .A1(Data_Y[7]), .B0(n1627), .B1(intDY[7]), .Y(
n1239) );
AO22XLTS U4015 ( .A0(n3317), .A1(Data_Y[6]), .B0(n1627), .B1(intDY[6]), .Y(
n1238) );
AO22XLTS U4016 ( .A0(n3317), .A1(Data_Y[5]), .B0(n1627), .B1(intDY[5]), .Y(
n1237) );
AO22XLTS U4017 ( .A0(n3317), .A1(Data_Y[4]), .B0(n1627), .B1(intDY[4]), .Y(
n1236) );
AO22XLTS U4018 ( .A0(n3317), .A1(Data_Y[3]), .B0(n1627), .B1(intDY[3]), .Y(
n1235) );
AO22XLTS U4019 ( .A0(n1626), .A1(Data_Y[2]), .B0(n1627), .B1(intDY[2]), .Y(
n1234) );
AO22XLTS U4020 ( .A0(n3316), .A1(Data_Y[1]), .B0(n1627), .B1(intDY[1]), .Y(
n1233) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk20.tcl_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_FUNCTIONAL_V
`define SKY130_FD_SC_LP__ISO0N_FUNCTIONAL_V
/**
* iso0n: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__iso0n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Name Output Other arguments
and and0 (X , A, SLEEP_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_FUNCTIONAL_V |
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : iReg.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 5, 2008 ** //
// ** Description : Internal Register for Newton core ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 5, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : August 19, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. Register 0 functional modification ** //
// ** 2. Bit ReOrdering function change to for loop ** //
// ** 3. Register 1 and Register 2 counter modify to use ** //
// ** Write Enable bits ** //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 3 ** //
// ** Author : kaylangu ** //
// ** Date : October 23, 2008 ** //
// ** FileName : ** //
// ** Notes : Change interrupt signal to be only one clock long ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module iReg
(/*AUTOARG*/
// Outputs
ESCR, WPTR, ICNT, FREQ, OCNT, FCNT,
// Inputs
clk, arst, idata, iaddr, iwe, FIR_WE, WFIFO_WE
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter r0setclr = 15; // Register 0 set/clr bit
parameter initWM = 8'h60;
// parameter ModuleVersion = 2;
// DATA TYPE - INPUTS AND OUTPUTS
input clk; // 100MHz Clock from BUS
input arst; // Asynchronous Reset (positive logic)
input [15:0] idata;
input [13:0] iaddr;
input iwe;
input FIR_WE;
input WFIFO_WE;
output [15:0] ESCR;
output [15:0] WPTR;
output [15:0] ICNT;
output [15:0] FREQ;
output [15:0] OCNT;
output [15:0] FCNT;
// DATA TYPE - INTERNAL REG
reg OVFL_MSK; // Overflow Mask
reg WMI_MSK; // WMI Mask
reg OVFL; // Overflow for CPTR
reg WMI; // Watermark Interrupt
reg [15:0] ICNT; // Counts the numbers of inputs
reg [7:0] OCNT_WM; // Output counter watermark
reg [7:0] OCNT_int; // Counts the numbers of outputs
reg FIR_WE_dly1;
reg [10:0] CPTR;
reg [15:0] FCNT;
reg SYNC;
// reg iReg_intr_d1;
// reg iReg_intr_1d;
reg [6:0] FREQ_int;
reg NEWFREQ;
reg START;
// DATA TYPE - INTERNAL WIRES
wire setclr;
wire reg0w;
wire reg1w;
wire reg2w;
wire reg3w;
wire reg4w;
//**************************************************************************//
//* REG 1 *//
//**************************************************************************//
assign setclr = reg0w & idata[r0setclr];
assign reg0w = (iaddr[2:0] == 3'h1) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OVFL_MSK <= 1'b0;
else if (reg0w & idata[10])
OVFL_MSK <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
WMI_MSK <= 1'b0;
else if (reg0w & idata[9])
WMI_MSK <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OVFL <= 1'b0;
else if (CPTR[10] == 1'b1) // BRAM pointer overflows
OVFL <= 1'b1;
else if (reg0w & idata[2])
OVFL <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
START <= 1'b0;
else if (reg0w & idata[3])
START <= idata[r0setclr];
else if (WMI | (FCNT[11:0] == 12'b1111_1111_1110))
START <= 1'b0;
else
START <= START;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
FIR_WE_dly1 <= 1'b0;
else
FIR_WE_dly1 <= FIR_WE;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
WMI <= 1'b0;
else if (FIR_WE_dly1 & (OCNT_int[7:0] == OCNT_WM[7:0])) // Output counter overflows
WMI <= 1'b1;
else if (reg0w & idata[1])
WMI <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
SYNC <= 1'b0;
else if (reg0w & idata[0])
SYNC <= idata[r0setclr];
// Read out
assign ESCR[15:0] = {setclr, 4'd0, OVFL_MSK, WMI_MSK, 5'd0, START,
OVFL, WMI, SYNC};
//**************************************************************************//
//* REG 2 *//
//**************************************************************************//
/*always @ (posedge clk or posedge arst)
if (arst != 1'b0)
SPTR[9:0] <= 10'd0;
else if (Bus2IP_WrCE[1])
SPTR[9:0] <= idata[25:16];*/
assign reg1w = (iaddr[2:0] == 3'h2) & iwe;
always @ (posedge clk or posedge SYNC)
if (SYNC != 1'b0)
CPTR[10:0] <= 11'd0;
else if (OVFL == 1'b1)
CPTR[10] <= 1'b0;
// else if (SYNC)
// CPTR[10:0] <= 11'd0;
else
CPTR[10:0] <= CPTR[10:0] + FIR_WE; //Pointer to BRAM address
// Readout
assign WPTR[15:0] = {6'd0, CPTR[9:0]};
//**************************************************************************//
//* REG 3 *//
//**************************************************************************//
assign reg2w = (iaddr[2:0] == 3'h3) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
ICNT[15:0] <= 16'd0;
else if (reg2w)
ICNT[15:0] <= idata[15:0];
else
ICNT[15:0] <= ICNT[15:0] + WFIFO_WE;
//**************************************************************************//
//* REG 4 *//
//**************************************************************************//
assign reg3w = (iaddr[2:0] == 3'h4) & iwe;
assign setclrf = reg3w & idata[7];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
FREQ_int[6:0] <= 7'h41; //Resets to frequency 65MHz
else if (setclrf)
FREQ_int[6:0] <= idata[6:0];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
NEWFREQ <= 1'b0;
else if (reg3w )
NEWFREQ <= idata[14];
assign FREQ[15:0] = {1'b0, NEWFREQ, 6'd0, setclrf, FREQ_int[6:0]};
//**************************************************************************//
//* REG 5 *//
//**************************************************************************//
assign reg4w = (iaddr[2:0] == 3'h5) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OCNT_WM[7:0] <= initWM;
else if (reg4w)
OCNT_WM[7:0] <= idata[15:8];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OCNT_int[7:0] <= 8'd0;
else if (reg4w)
OCNT_int[7:0] <= idata[7:0];
else
OCNT_int[7:0] <= OCNT_int[7:0] + FIR_WE;
// Read out
assign OCNT[15:0] = {OCNT_WM[7:0], OCNT_int[7:0]};
//**************************************************************************//
//* REG 6 *//
//**************************************************************************//
assign reg5w = (iaddr[2:0] == 3'h6) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
FCNT[15:0] <= 16'd0;
else if (reg5w)
FCNT[15:0] <= idata[15:0];
else if (START)
FCNT[15:0] <= FCNT[15:0] + 1;
//**************************************************************************//
//* Read Out *//
//**************************************************************************//
//always @ (/*AS*/Bus2IP_RdCE or ESCR or ICNT or OCNT or WPTR)
/*begin
IP2Bus_Data_int[31:0] = 32'b0;
case (1'b1)
Bus2IP_RdCE[0] : IP2Bus_Data_int[31:0] = ESCR[31:0];
Bus2IP_RdCE[1] : IP2Bus_Data_int[31:0] = WPTR[31:0];
Bus2IP_RdCE[2] : IP2Bus_Data_int[31:0] = ICNT[31:0];
Bus2IP_RdCE[3] : IP2Bus_Data_int[31:0] = OCNT[31:0];
endcase // case (1'b1)
end*/
// assign iReg2IP_RdAck = |Bus2IP_RdCE[0:3];
// assign IP2Bus_WrAck = |Bus2IP_WrCE[0:3];
endmodule // iReg
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 40: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 40: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 40: 0] entry_0;
reg [ 40: 0] entry_1;
wire full;
reg rd_address;
reg [ 40: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_sdram (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 15: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 11: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 15: 0] zs_dq;
output [ 1: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 21: 0] az_addr;
input [ 1: 0] az_be_n;
input az_cs;
input [ 15: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 21: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 15: 0] active_data;
reg [ 1: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 7: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 21: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 15: 0] f_data;
wire [ 1: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 40: 0] fifo_read_data;
reg [ 11: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 11: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 12: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 11: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 15: 0] zs_dq;
wire [ 1: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{16{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
nios_system_sdram_input_efifo_module the_nios_system_sdram_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[21],f_addr[8]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 5000;
else if (refresh_counter == 0)
refresh_counter <= 781;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {12{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {12{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 0;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 3;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{2{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[21],active_addr[8]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[20 : 9]} == {f_addr[20 : 9]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {4{1'b0}},f_addr[7 : 0] } : { {4{1'b0}},active_addr[7 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 12'b000000000000;
m_data <= 16'b0000000000000000;
m_dqm <= 2'b00;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 0;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[20 : 9];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 1;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 0;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {12{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 3;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DECAP_4_V
`define SKY130_FD_SC_HS__DECAP_4_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__decap_4 (
VPWR,
VGND
);
input VPWR;
input VGND;
sky130_fd_sc_hs__decap base (
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DECAP_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTP_BEHAVIORAL_PP_V |
// megafunction wizard: %ALTIOBUF%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altiobuf_bidir
// ============================================================
// File Name: hyper_dbuf.v
// Megafunction Name(s):
// altiobuf_bidir
//
// Simulation Library Files(s):
// cyclonev
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
//altiobuf_bidir CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=8 OPEN_DRAIN_OUTPUT="FALSE" USE_DIFFERENTIAL_MODE="FALSE" USE_DYNAMIC_TERMINATION_CONTROL="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataio dataout oe
//VERSION_BEGIN 14.0 cbx_altiobuf_bidir 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_stratixiii 2014:06:05:09:45:41:SJ cbx_stratixv 2014:06:05:09:45:41:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = cyclonev_io_ibuf 8 cyclonev_io_obuf 8
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hyper_dbuf_iobuf_bidir_soo
(
datain,
dataio,
dataout,
oe) ;
input [7:0] datain;
inout [7:0] dataio;
output [7:0] dataout;
input [7:0] oe;
wire [7:0] wire_ibufa_i;
wire [7:0] wire_ibufa_o;
wire [7:0] wire_obufa_i;
wire [7:0] wire_obufa_o;
wire [7:0] wire_obufa_oe;
cyclonev_io_ibuf ibufa_0
(
.i(wire_ibufa_i[0:0]),
.o(wire_ibufa_o[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_0.bus_hold = "false",
ibufa_0.differential_mode = "false",
ibufa_0.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_1
(
.i(wire_ibufa_i[1:1]),
.o(wire_ibufa_o[1:1])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_1.bus_hold = "false",
ibufa_1.differential_mode = "false",
ibufa_1.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_2
(
.i(wire_ibufa_i[2:2]),
.o(wire_ibufa_o[2:2])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_2.bus_hold = "false",
ibufa_2.differential_mode = "false",
ibufa_2.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_3
(
.i(wire_ibufa_i[3:3]),
.o(wire_ibufa_o[3:3])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_3.bus_hold = "false",
ibufa_3.differential_mode = "false",
ibufa_3.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_4
(
.i(wire_ibufa_i[4:4]),
.o(wire_ibufa_o[4:4])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_4.bus_hold = "false",
ibufa_4.differential_mode = "false",
ibufa_4.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_5
(
.i(wire_ibufa_i[5:5]),
.o(wire_ibufa_o[5:5])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_5.bus_hold = "false",
ibufa_5.differential_mode = "false",
ibufa_5.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_6
(
.i(wire_ibufa_i[6:6]),
.o(wire_ibufa_o[6:6])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_6.bus_hold = "false",
ibufa_6.differential_mode = "false",
ibufa_6.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_7
(
.i(wire_ibufa_i[7:7]),
.o(wire_ibufa_o[7:7])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_7.bus_hold = "false",
ibufa_7.differential_mode = "false",
ibufa_7.lpm_type = "cyclonev_io_ibuf";
assign
wire_ibufa_i = dataio;
cyclonev_io_obuf obufa_0
(
.i(wire_obufa_i[0:0]),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_1
(
.i(wire_obufa_i[1:1]),
.o(wire_obufa_o[1:1]),
.obar(),
.oe(wire_obufa_oe[1:1])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_1.bus_hold = "false",
obufa_1.open_drain_output = "false",
obufa_1.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_2
(
.i(wire_obufa_i[2:2]),
.o(wire_obufa_o[2:2]),
.obar(),
.oe(wire_obufa_oe[2:2])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_2.bus_hold = "false",
obufa_2.open_drain_output = "false",
obufa_2.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_3
(
.i(wire_obufa_i[3:3]),
.o(wire_obufa_o[3:3]),
.obar(),
.oe(wire_obufa_oe[3:3])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_3.bus_hold = "false",
obufa_3.open_drain_output = "false",
obufa_3.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_4
(
.i(wire_obufa_i[4:4]),
.o(wire_obufa_o[4:4]),
.obar(),
.oe(wire_obufa_oe[4:4])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_4.bus_hold = "false",
obufa_4.open_drain_output = "false",
obufa_4.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_5
(
.i(wire_obufa_i[5:5]),
.o(wire_obufa_o[5:5]),
.obar(),
.oe(wire_obufa_oe[5:5])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_5.bus_hold = "false",
obufa_5.open_drain_output = "false",
obufa_5.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_6
(
.i(wire_obufa_i[6:6]),
.o(wire_obufa_o[6:6]),
.obar(),
.oe(wire_obufa_oe[6:6])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_6.bus_hold = "false",
obufa_6.open_drain_output = "false",
obufa_6.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_7
(
.i(wire_obufa_i[7:7]),
.o(wire_obufa_o[7:7]),
.obar(),
.oe(wire_obufa_oe[7:7])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_7.bus_hold = "false",
obufa_7.open_drain_output = "false",
obufa_7.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_i = datain,
wire_obufa_oe = oe;
assign
dataio = wire_obufa_o,
dataout = wire_ibufa_o;
endmodule //hyper_dbuf_iobuf_bidir_soo
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module hyper_dbuf (
datain,
oe,
dataio,
dataout);
input [7:0] datain;
input [7:0] oe;
inout [7:0] dataio;
output [7:0] dataout;
wire [7:0] sub_wire0;
wire [7:0] dataout = sub_wire0[7:0];
hyper_dbuf_iobuf_bidir_soo hyper_dbuf_iobuf_bidir_soo_component (
.datain (datain),
.oe (oe),
.dataio (dataio),
.dataout (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
// Retrieval info: CONSTANT: left_shift_series_termination_control STRING "FALSE"
// Retrieval info: CONSTANT: number_of_channels NUMERIC "8"
// Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
// Retrieval info: CONSTANT: use_differential_mode STRING "FALSE"
// Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"
// Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
// Retrieval info: USED_PORT: datain 0 0 8 0 INPUT NODEFVAL "datain[7..0]"
// Retrieval info: USED_PORT: dataio 0 0 8 0 BIDIR NODEFVAL "dataio[7..0]"
// Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
// Retrieval info: USED_PORT: oe 0 0 8 0 INPUT NODEFVAL "oe[7..0]"
// Retrieval info: CONNECT: @datain 0 0 8 0 datain 0 0 8 0
// Retrieval info: CONNECT: @oe 0 0 8 0 oe 0 0 8 0
// Retrieval info: CONNECT: dataio 0 0 8 0 @dataio 0 0 8 0
// Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL hyper_dbuf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hyper_dbuf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hyper_dbuf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hyper_dbuf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hyper_dbuf_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hyper_dbuf_bb.v FALSE
// Retrieval info: LIB_FILE: cyclonev
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:53:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top affine_block_ieee754_fp_multiplier_1_1 -prefix
// affine_block_ieee754_fp_multiplier_1_1_ affine_block_ieee754_fp_multiplier_0_0_sim_netlist.v
// Design : affine_block_ieee754_fp_multiplier_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "affine_block_ieee754_fp_multiplier_0_0,ieee754_fp_multiplier,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ieee754_fp_multiplier,Vivado 2016.4" *)
(* NotValidForBitStream *)
module affine_block_ieee754_fp_multiplier_1_1
(x,
y,
z);
input [31:0]x;
input [31:0]y;
output [31:0]z;
wire [31:0]x;
wire [31:0]y;
wire [31:0]z;
wire \z[30]_INST_0_i_23_n_0 ;
wire \z[30]_INST_0_i_24_n_0 ;
wire \z[30]_INST_0_i_25_n_0 ;
wire \z[30]_INST_0_i_26_n_0 ;
wire \z[30]_INST_0_i_27_n_0 ;
wire \z[30]_INST_0_i_28_n_0 ;
wire \z[30]_INST_0_i_4_n_0 ;
wire \z[30]_INST_0_i_84_n_0 ;
wire \z[30]_INST_0_i_85_n_0 ;
wire \z[30]_INST_0_i_86_n_0 ;
wire \z[30]_INST_0_i_87_n_0 ;
wire \z[30]_INST_0_i_88_n_0 ;
wire \z[30]_INST_0_i_89_n_0 ;
wire \z[30]_INST_0_i_90_n_0 ;
wire \z[30]_INST_0_i_91_n_0 ;
wire \z[30]_INST_0_i_92_n_0 ;
wire \z[30]_INST_0_i_93_n_0 ;
wire [22:0]z_mantissa;
affine_block_ieee754_fp_multiplier_1_1_ieee754_fp_multiplier U0
(.x(x[30:0]),
.y(y[30:0]),
.y_11__s_port_(\z[30]_INST_0_i_4_n_0 ),
.z(z[30:23]),
.z_mantissa(z_mantissa));
LUT2 #(
.INIT(4'h2))
\z[0]_INST_0
(.I0(z_mantissa[0]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[0]));
LUT2 #(
.INIT(4'h2))
\z[10]_INST_0
(.I0(z_mantissa[10]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[10]));
LUT2 #(
.INIT(4'h2))
\z[11]_INST_0
(.I0(z_mantissa[11]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[11]));
LUT2 #(
.INIT(4'h2))
\z[12]_INST_0
(.I0(z_mantissa[12]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[12]));
LUT2 #(
.INIT(4'h2))
\z[13]_INST_0
(.I0(z_mantissa[13]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[13]));
LUT2 #(
.INIT(4'h2))
\z[14]_INST_0
(.I0(z_mantissa[14]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[14]));
LUT2 #(
.INIT(4'h2))
\z[15]_INST_0
(.I0(z_mantissa[15]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[15]));
LUT2 #(
.INIT(4'h2))
\z[16]_INST_0
(.I0(z_mantissa[16]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[16]));
LUT2 #(
.INIT(4'h2))
\z[17]_INST_0
(.I0(z_mantissa[17]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[17]));
LUT2 #(
.INIT(4'h2))
\z[18]_INST_0
(.I0(z_mantissa[18]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[18]));
LUT2 #(
.INIT(4'h2))
\z[19]_INST_0
(.I0(z_mantissa[19]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[19]));
LUT2 #(
.INIT(4'h2))
\z[1]_INST_0
(.I0(z_mantissa[1]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[1]));
LUT2 #(
.INIT(4'h2))
\z[20]_INST_0
(.I0(z_mantissa[20]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[20]));
LUT2 #(
.INIT(4'h2))
\z[21]_INST_0
(.I0(z_mantissa[21]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[21]));
LUT2 #(
.INIT(4'h2))
\z[22]_INST_0
(.I0(z_mantissa[22]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[22]));
LUT2 #(
.INIT(4'h2))
\z[2]_INST_0
(.I0(z_mantissa[2]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[2]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_23
(.I0(x[29]),
.I1(x[4]),
.I2(x[11]),
.I3(x[13]),
.I4(\z[30]_INST_0_i_84_n_0 ),
.O(\z[30]_INST_0_i_23_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_24
(.I0(x[25]),
.I1(x[20]),
.I2(x[15]),
.I3(x[22]),
.I4(\z[30]_INST_0_i_85_n_0 ),
.O(\z[30]_INST_0_i_24_n_0 ));
LUT6 #(
.INIT(64'h0000000000000004))
\z[30]_INST_0_i_25
(.I0(\z[30]_INST_0_i_86_n_0 ),
.I1(\z[30]_INST_0_i_87_n_0 ),
.I2(\z[30]_INST_0_i_88_n_0 ),
.I3(x[24]),
.I4(x[10]),
.I5(x[2]),
.O(\z[30]_INST_0_i_25_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_26
(.I0(y[30]),
.I1(y[5]),
.I2(y[0]),
.I3(y[1]),
.I4(\z[30]_INST_0_i_89_n_0 ),
.O(\z[30]_INST_0_i_26_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_27
(.I0(y[29]),
.I1(y[18]),
.I2(y[2]),
.I3(y[10]),
.I4(\z[30]_INST_0_i_90_n_0 ),
.O(\z[30]_INST_0_i_27_n_0 ));
LUT6 #(
.INIT(64'h0000000000000004))
\z[30]_INST_0_i_28
(.I0(\z[30]_INST_0_i_91_n_0 ),
.I1(\z[30]_INST_0_i_92_n_0 ),
.I2(\z[30]_INST_0_i_93_n_0 ),
.I3(y[12]),
.I4(y[20]),
.I5(y[4]),
.O(\z[30]_INST_0_i_28_n_0 ));
LUT6 #(
.INIT(64'h101010FF10101010))
\z[30]_INST_0_i_4
(.I0(\z[30]_INST_0_i_23_n_0 ),
.I1(\z[30]_INST_0_i_24_n_0 ),
.I2(\z[30]_INST_0_i_25_n_0 ),
.I3(\z[30]_INST_0_i_26_n_0 ),
.I4(\z[30]_INST_0_i_27_n_0 ),
.I5(\z[30]_INST_0_i_28_n_0 ),
.O(\z[30]_INST_0_i_4_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_84
(.I0(x[9]),
.I1(x[3]),
.I2(x[17]),
.I3(x[7]),
.O(\z[30]_INST_0_i_84_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_85
(.I0(x[18]),
.I1(x[30]),
.I2(x[21]),
.I3(x[6]),
.O(\z[30]_INST_0_i_85_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_86
(.I0(x[14]),
.I1(x[12]),
.I2(x[8]),
.I3(x[27]),
.O(\z[30]_INST_0_i_86_n_0 ));
LUT4 #(
.INIT(16'h0001))
\z[30]_INST_0_i_87
(.I0(x[28]),
.I1(x[23]),
.I2(x[19]),
.I3(x[1]),
.O(\z[30]_INST_0_i_87_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_88
(.I0(x[0]),
.I1(x[26]),
.I2(x[16]),
.I3(x[5]),
.O(\z[30]_INST_0_i_88_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_89
(.I0(y[14]),
.I1(y[8]),
.I2(y[24]),
.I3(y[27]),
.O(\z[30]_INST_0_i_89_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_90
(.I0(y[7]),
.I1(y[26]),
.I2(y[17]),
.I3(y[6]),
.O(\z[30]_INST_0_i_90_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_91
(.I0(y[21]),
.I1(y[15]),
.I2(y[22]),
.I3(y[23]),
.O(\z[30]_INST_0_i_91_n_0 ));
LUT4 #(
.INIT(16'h0001))
\z[30]_INST_0_i_92
(.I0(y[19]),
.I1(y[28]),
.I2(y[9]),
.I3(y[3]),
.O(\z[30]_INST_0_i_92_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_93
(.I0(y[16]),
.I1(y[25]),
.I2(y[13]),
.I3(y[11]),
.O(\z[30]_INST_0_i_93_n_0 ));
LUT2 #(
.INIT(4'h6))
\z[31]_INST_0
(.I0(y[31]),
.I1(x[31]),
.O(z[31]));
LUT2 #(
.INIT(4'h2))
\z[3]_INST_0
(.I0(z_mantissa[3]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[3]));
LUT2 #(
.INIT(4'h2))
\z[4]_INST_0
(.I0(z_mantissa[4]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[4]));
LUT2 #(
.INIT(4'h2))
\z[5]_INST_0
(.I0(z_mantissa[5]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[5]));
LUT2 #(
.INIT(4'h2))
\z[6]_INST_0
(.I0(z_mantissa[6]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[6]));
LUT2 #(
.INIT(4'h2))
\z[7]_INST_0
(.I0(z_mantissa[7]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[7]));
LUT2 #(
.INIT(4'h2))
\z[8]_INST_0
(.I0(z_mantissa[8]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[8]));
LUT2 #(
.INIT(4'h2))
\z[9]_INST_0
(.I0(z_mantissa[9]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[9]));
endmodule
module affine_block_ieee754_fp_multiplier_1_1_ieee754_fp_multiplier
(z,
z_mantissa,
x,
y,
y_11__s_port_);
output [7:0]z;
output [22:0]z_mantissa;
input [30:0]x;
input [30:0]y;
input y_11__s_port_;
wire L1;
wire L1_carry__0_i_1_n_0;
wire L1_carry__0_i_2_n_0;
wire L1_carry__0_i_3_n_0;
wire L1_carry__0_i_4_n_0;
wire L1_carry__0_i_5_n_0;
wire L1_carry__0_i_6_n_0;
wire L1_carry__0_i_7_n_0;
wire L1_carry__0_i_8_n_0;
wire L1_carry__0_n_0;
wire L1_carry__0_n_1;
wire L1_carry__0_n_2;
wire L1_carry__0_n_3;
wire L1_carry__1_i_1_n_0;
wire L1_carry__1_i_2_n_0;
wire L1_carry__1_i_3_n_0;
wire L1_carry__1_i_4_n_0;
wire L1_carry__1_i_5_n_0;
wire L1_carry__1_i_6_n_0;
wire L1_carry__1_i_7_n_0;
wire L1_carry__1_i_8_n_0;
wire L1_carry__1_n_0;
wire L1_carry__1_n_1;
wire L1_carry__1_n_2;
wire L1_carry__1_n_3;
wire L1_carry__2_i_1_n_0;
wire L1_carry__2_i_2_n_0;
wire L1_carry__2_i_3_n_0;
wire L1_carry__2_i_4_n_0;
wire L1_carry__2_i_5_n_0;
wire L1_carry__2_i_6_n_0;
wire L1_carry__2_i_7_n_0;
wire L1_carry__2_n_1;
wire L1_carry__2_n_2;
wire L1_carry__2_n_3;
wire L1_carry_i_10_n_0;
wire L1_carry_i_11_n_0;
wire L1_carry_i_12_n_0;
wire L1_carry_i_13_n_0;
wire L1_carry_i_14_n_0;
wire L1_carry_i_15_n_0;
wire L1_carry_i_16_n_0;
wire L1_carry_i_17_n_0;
wire L1_carry_i_18_n_0;
wire L1_carry_i_19_n_0;
wire L1_carry_i_1_n_0;
wire L1_carry_i_20_n_0;
wire L1_carry_i_21_n_0;
wire L1_carry_i_22_n_0;
wire L1_carry_i_23_n_0;
wire L1_carry_i_24_n_0;
wire L1_carry_i_25_n_0;
wire L1_carry_i_26_n_0;
wire L1_carry_i_27_n_0;
wire L1_carry_i_28_n_0;
wire L1_carry_i_29_n_0;
wire L1_carry_i_2_n_0;
wire L1_carry_i_30_n_0;
wire L1_carry_i_31_n_0;
wire L1_carry_i_32_n_0;
wire L1_carry_i_33_n_0;
wire L1_carry_i_34_n_0;
wire L1_carry_i_35_n_0;
wire L1_carry_i_36_n_0;
wire L1_carry_i_37_n_0;
wire L1_carry_i_38_n_0;
wire L1_carry_i_39_n_0;
wire L1_carry_i_3_n_0;
wire L1_carry_i_40_n_0;
wire L1_carry_i_41_n_0;
wire L1_carry_i_42_n_0;
wire L1_carry_i_43_n_0;
wire L1_carry_i_44_n_0;
wire L1_carry_i_45_n_0;
wire L1_carry_i_46_n_0;
wire L1_carry_i_47_n_0;
wire L1_carry_i_48_n_0;
wire L1_carry_i_49_n_0;
wire L1_carry_i_4_n_0;
wire L1_carry_i_50_n_0;
wire L1_carry_i_51_n_0;
wire L1_carry_i_52_n_0;
wire L1_carry_i_53_n_0;
wire L1_carry_i_54_n_0;
wire L1_carry_i_5_n_0;
wire L1_carry_i_6_n_0;
wire L1_carry_i_7_n_0;
wire L1_carry_i_8_n_0;
wire L1_carry_i_9_n_0;
wire L1_carry_n_0;
wire L1_carry_n_1;
wire L1_carry_n_2;
wire L1_carry_n_3;
wire _carry__0_i_1_n_0;
wire _carry__0_i_2_n_0;
wire _carry__0_i_3_n_0;
wire _carry__0_i_4_n_0;
wire _carry__0_n_0;
wire _carry__0_n_1;
wire _carry__0_n_2;
wire _carry__0_n_3;
wire _carry__0_n_4;
wire _carry__0_n_5;
wire _carry__0_n_6;
wire _carry__0_n_7;
wire _carry__1_i_1_n_0;
wire _carry__1_i_2_n_0;
wire _carry__1_i_3_n_0;
wire _carry__1_i_4_n_0;
wire _carry__1_n_0;
wire _carry__1_n_1;
wire _carry__1_n_2;
wire _carry__1_n_3;
wire _carry__1_n_4;
wire _carry__1_n_5;
wire _carry__1_n_6;
wire _carry__1_n_7;
wire _carry__2_i_1_n_0;
wire _carry__2_i_2_n_0;
wire _carry__2_i_3_n_0;
wire _carry__2_i_4_n_0;
wire _carry__2_n_0;
wire _carry__2_n_1;
wire _carry__2_n_2;
wire _carry__2_n_3;
wire _carry__2_n_4;
wire _carry__2_n_5;
wire _carry__2_n_6;
wire _carry__2_n_7;
wire _carry__3_i_1_n_0;
wire _carry__3_i_2_n_0;
wire _carry__3_i_3_n_0;
wire _carry__3_i_4_n_0;
wire _carry__3_n_0;
wire _carry__3_n_1;
wire _carry__3_n_2;
wire _carry__3_n_3;
wire _carry__3_n_4;
wire _carry__3_n_5;
wire _carry__3_n_6;
wire _carry__3_n_7;
wire _carry__4_i_1_n_0;
wire _carry__4_i_2_n_0;
wire _carry__4_i_3_n_0;
wire _carry__4_i_4_n_0;
wire _carry__4_n_0;
wire _carry__4_n_1;
wire _carry__4_n_2;
wire _carry__4_n_3;
wire _carry__4_n_4;
wire _carry__4_n_5;
wire _carry__4_n_6;
wire _carry__4_n_7;
wire _carry__5_i_1_n_0;
wire _carry__5_i_2_n_0;
wire _carry__5_i_3_n_0;
wire _carry__5_i_4_n_0;
wire _carry__5_n_0;
wire _carry__5_n_1;
wire _carry__5_n_2;
wire _carry__5_n_3;
wire _carry__5_n_4;
wire _carry__5_n_5;
wire _carry__5_n_6;
wire _carry__5_n_7;
wire _carry__6_i_1_n_0;
wire _carry__6_i_2_n_0;
wire _carry__6_n_3;
wire _carry__6_n_6;
wire _carry__6_n_7;
wire _carry_i_10_n_0;
wire _carry_i_11_n_0;
wire _carry_i_12_n_0;
wire _carry_i_13_n_0;
wire _carry_i_14_n_0;
wire _carry_i_15_n_0;
wire _carry_i_16_n_0;
wire _carry_i_17_n_0;
wire _carry_i_18_n_0;
wire _carry_i_19_n_0;
wire _carry_i_1_n_0;
wire _carry_i_20_n_0;
wire _carry_i_21_n_0;
wire _carry_i_22_n_0;
wire _carry_i_23_n_0;
wire _carry_i_24_n_0;
wire _carry_i_2_n_0;
wire _carry_i_3_n_0;
wire _carry_i_4_n_0;
wire _carry_i_6_n_0;
wire _carry_i_7_n_0;
wire _carry_i_8_n_0;
wire _carry_i_9_n_0;
wire _carry_n_0;
wire _carry_n_1;
wire _carry_n_2;
wire _carry_n_3;
wire _carry_n_4;
wire _carry_n_5;
wire _carry_n_6;
wire _carry_n_7;
wire [7:0]data0;
wire [7:0]data1;
wire [47:0]msb1__1;
wire msb1_n_106;
wire msb1_n_107;
wire msb1_n_108;
wire msb1_n_109;
wire msb1_n_110;
wire msb1_n_111;
wire msb1_n_112;
wire msb1_n_113;
wire msb1_n_114;
wire msb1_n_115;
wire msb1_n_116;
wire msb1_n_117;
wire msb1_n_118;
wire msb1_n_119;
wire msb1_n_120;
wire msb1_n_121;
wire msb1_n_122;
wire msb1_n_123;
wire msb1_n_124;
wire msb1_n_125;
wire msb1_n_126;
wire msb1_n_127;
wire msb1_n_128;
wire msb1_n_129;
wire msb1_n_130;
wire msb1_n_131;
wire msb1_n_132;
wire msb1_n_133;
wire msb1_n_134;
wire msb1_n_135;
wire msb1_n_136;
wire msb1_n_137;
wire msb1_n_138;
wire msb1_n_139;
wire msb1_n_140;
wire msb1_n_141;
wire msb1_n_142;
wire msb1_n_143;
wire msb1_n_144;
wire msb1_n_145;
wire msb1_n_146;
wire msb1_n_147;
wire msb1_n_148;
wire msb1_n_149;
wire msb1_n_150;
wire msb1_n_151;
wire msb1_n_152;
wire msb1_n_153;
wire msb1_n_58;
wire msb1_n_59;
wire msb1_n_60;
wire msb1_n_61;
wire msb1_n_62;
wire msb1_n_63;
wire msb1_n_64;
wire msb1_n_65;
wire msb1_n_66;
wire msb1_n_67;
wire msb1_n_68;
wire msb1_n_69;
wire msb1_n_70;
wire msb1_n_71;
wire msb1_n_72;
wire msb1_n_73;
wire msb1_n_74;
wire msb1_n_75;
wire msb1_n_76;
wire msb1_n_77;
wire msb1_n_78;
wire msb1_n_79;
wire msb1_n_80;
wire msb1_n_81;
wire msb1_n_82;
wire msb1_n_83;
wire msb1_n_84;
wire msb1_n_85;
wire msb1_n_86;
wire msb1_n_87;
wire msb1_n_88;
wire [1:1]p_0_in;
wire [22:0]sel0;
wire [30:0]x;
wire [30:0]y;
wire y_11__s_net_1;
wire [7:0]z;
wire \z[11]_INST_0_i_1_n_0 ;
wire \z[11]_INST_0_i_1_n_1 ;
wire \z[11]_INST_0_i_1_n_2 ;
wire \z[11]_INST_0_i_1_n_3 ;
wire \z[11]_INST_0_i_3_n_0 ;
wire \z[11]_INST_0_i_6_n_0 ;
wire \z[11]_INST_0_i_7_n_0 ;
wire \z[11]_INST_0_i_8_n_0 ;
wire \z[11]_INST_0_i_9_n_0 ;
wire \z[15]_INST_0_i_1_n_0 ;
wire \z[15]_INST_0_i_1_n_1 ;
wire \z[15]_INST_0_i_1_n_2 ;
wire \z[15]_INST_0_i_1_n_3 ;
wire \z[15]_INST_0_i_6_n_0 ;
wire \z[15]_INST_0_i_7_n_0 ;
wire \z[15]_INST_0_i_8_n_0 ;
wire \z[19]_INST_0_i_1_n_0 ;
wire \z[19]_INST_0_i_1_n_1 ;
wire \z[19]_INST_0_i_1_n_2 ;
wire \z[19]_INST_0_i_1_n_3 ;
wire \z[22]_INST_0_i_1_n_2 ;
wire \z[22]_INST_0_i_1_n_3 ;
wire \z[22]_INST_0_i_5_n_0 ;
wire \z[22]_INST_0_i_6_n_0 ;
wire \z[30]_INST_0_i_100_n_0 ;
wire \z[30]_INST_0_i_101_n_0 ;
wire \z[30]_INST_0_i_102_n_0 ;
wire \z[30]_INST_0_i_103_n_0 ;
wire \z[30]_INST_0_i_104_n_0 ;
wire \z[30]_INST_0_i_105_n_0 ;
wire \z[30]_INST_0_i_106_n_0 ;
wire \z[30]_INST_0_i_107_n_0 ;
wire \z[30]_INST_0_i_108_n_0 ;
wire \z[30]_INST_0_i_109_n_0 ;
wire \z[30]_INST_0_i_110_n_0 ;
wire \z[30]_INST_0_i_111_n_0 ;
wire \z[30]_INST_0_i_112_n_0 ;
wire \z[30]_INST_0_i_113_n_0 ;
wire \z[30]_INST_0_i_114_n_0 ;
wire \z[30]_INST_0_i_115_n_0 ;
wire \z[30]_INST_0_i_116_n_0 ;
wire \z[30]_INST_0_i_117_n_0 ;
wire \z[30]_INST_0_i_118_n_0 ;
wire \z[30]_INST_0_i_119_n_0 ;
wire \z[30]_INST_0_i_11_n_0 ;
wire \z[30]_INST_0_i_120_n_0 ;
wire \z[30]_INST_0_i_121_n_0 ;
wire \z[30]_INST_0_i_122_n_0 ;
wire \z[30]_INST_0_i_123_n_0 ;
wire \z[30]_INST_0_i_124_n_0 ;
wire \z[30]_INST_0_i_125_n_0 ;
wire \z[30]_INST_0_i_126_n_0 ;
wire \z[30]_INST_0_i_127_n_0 ;
wire \z[30]_INST_0_i_128_n_0 ;
wire \z[30]_INST_0_i_129_n_0 ;
wire \z[30]_INST_0_i_130_n_0 ;
wire \z[30]_INST_0_i_131_n_0 ;
wire \z[30]_INST_0_i_132_n_0 ;
wire \z[30]_INST_0_i_133_n_0 ;
wire \z[30]_INST_0_i_134_n_0 ;
wire \z[30]_INST_0_i_135_n_0 ;
wire \z[30]_INST_0_i_136_n_0 ;
wire \z[30]_INST_0_i_137_n_0 ;
wire \z[30]_INST_0_i_138_n_0 ;
wire \z[30]_INST_0_i_139_n_0 ;
wire \z[30]_INST_0_i_13_n_0 ;
wire \z[30]_INST_0_i_140_n_0 ;
wire \z[30]_INST_0_i_141_n_0 ;
wire \z[30]_INST_0_i_142_n_0 ;
wire \z[30]_INST_0_i_143_n_0 ;
wire \z[30]_INST_0_i_144_n_0 ;
wire \z[30]_INST_0_i_145_n_0 ;
wire \z[30]_INST_0_i_146_n_0 ;
wire \z[30]_INST_0_i_147_n_0 ;
wire \z[30]_INST_0_i_148_n_0 ;
wire \z[30]_INST_0_i_149_n_0 ;
wire \z[30]_INST_0_i_14_n_0 ;
wire \z[30]_INST_0_i_150_n_0 ;
wire \z[30]_INST_0_i_151_n_0 ;
wire \z[30]_INST_0_i_152_n_0 ;
wire \z[30]_INST_0_i_153_n_0 ;
wire \z[30]_INST_0_i_154_n_0 ;
wire \z[30]_INST_0_i_155_n_0 ;
wire \z[30]_INST_0_i_156_n_0 ;
wire \z[30]_INST_0_i_157_n_0 ;
wire \z[30]_INST_0_i_158_n_0 ;
wire \z[30]_INST_0_i_159_n_0 ;
wire \z[30]_INST_0_i_15_n_0 ;
wire \z[30]_INST_0_i_160_n_0 ;
wire \z[30]_INST_0_i_161_n_0 ;
wire \z[30]_INST_0_i_162_n_0 ;
wire \z[30]_INST_0_i_163_n_0 ;
wire \z[30]_INST_0_i_164_n_0 ;
wire \z[30]_INST_0_i_165_n_0 ;
wire \z[30]_INST_0_i_166_n_0 ;
wire \z[30]_INST_0_i_167_n_0 ;
wire \z[30]_INST_0_i_168_n_0 ;
wire \z[30]_INST_0_i_169_n_0 ;
wire \z[30]_INST_0_i_16_n_0 ;
wire \z[30]_INST_0_i_170_n_0 ;
wire \z[30]_INST_0_i_171_n_0 ;
wire \z[30]_INST_0_i_172_n_0 ;
wire \z[30]_INST_0_i_173_n_0 ;
wire \z[30]_INST_0_i_174_n_0 ;
wire \z[30]_INST_0_i_175_n_0 ;
wire \z[30]_INST_0_i_176_n_0 ;
wire \z[30]_INST_0_i_177_n_0 ;
wire \z[30]_INST_0_i_178_n_0 ;
wire \z[30]_INST_0_i_179_n_0 ;
wire \z[30]_INST_0_i_17_n_0 ;
wire \z[30]_INST_0_i_180_n_0 ;
wire \z[30]_INST_0_i_181_n_0 ;
wire \z[30]_INST_0_i_182_n_0 ;
wire \z[30]_INST_0_i_183_n_0 ;
wire \z[30]_INST_0_i_184_n_0 ;
wire \z[30]_INST_0_i_185_n_0 ;
wire \z[30]_INST_0_i_186_n_0 ;
wire \z[30]_INST_0_i_187_n_0 ;
wire \z[30]_INST_0_i_188_n_0 ;
wire \z[30]_INST_0_i_189_n_0 ;
wire \z[30]_INST_0_i_18_n_0 ;
wire \z[30]_INST_0_i_190_n_0 ;
wire \z[30]_INST_0_i_191_n_0 ;
wire \z[30]_INST_0_i_192_n_0 ;
wire \z[30]_INST_0_i_193_n_0 ;
wire \z[30]_INST_0_i_194_n_0 ;
wire \z[30]_INST_0_i_195_n_0 ;
wire \z[30]_INST_0_i_196_n_0 ;
wire \z[30]_INST_0_i_197_n_0 ;
wire \z[30]_INST_0_i_198_n_0 ;
wire \z[30]_INST_0_i_199_n_0 ;
wire \z[30]_INST_0_i_19_n_0 ;
wire \z[30]_INST_0_i_1_n_0 ;
wire \z[30]_INST_0_i_200_n_0 ;
wire \z[30]_INST_0_i_201_n_0 ;
wire \z[30]_INST_0_i_202_n_0 ;
wire \z[30]_INST_0_i_203_n_0 ;
wire \z[30]_INST_0_i_204_n_0 ;
wire \z[30]_INST_0_i_205_n_0 ;
wire \z[30]_INST_0_i_206_n_0 ;
wire \z[30]_INST_0_i_207_n_0 ;
wire \z[30]_INST_0_i_208_n_0 ;
wire \z[30]_INST_0_i_209_n_0 ;
wire \z[30]_INST_0_i_20_n_0 ;
wire \z[30]_INST_0_i_210_n_0 ;
wire \z[30]_INST_0_i_211_n_0 ;
wire \z[30]_INST_0_i_212_n_0 ;
wire \z[30]_INST_0_i_213_n_0 ;
wire \z[30]_INST_0_i_214_n_0 ;
wire \z[30]_INST_0_i_215_n_0 ;
wire \z[30]_INST_0_i_216_n_0 ;
wire \z[30]_INST_0_i_217_n_0 ;
wire \z[30]_INST_0_i_218_n_0 ;
wire \z[30]_INST_0_i_219_n_0 ;
wire \z[30]_INST_0_i_21_n_0 ;
wire \z[30]_INST_0_i_220_n_0 ;
wire \z[30]_INST_0_i_221_n_0 ;
wire \z[30]_INST_0_i_222_n_0 ;
wire \z[30]_INST_0_i_223_n_0 ;
wire \z[30]_INST_0_i_224_n_0 ;
wire \z[30]_INST_0_i_225_n_0 ;
wire \z[30]_INST_0_i_226_n_0 ;
wire \z[30]_INST_0_i_227_n_0 ;
wire \z[30]_INST_0_i_228_n_0 ;
wire \z[30]_INST_0_i_229_n_0 ;
wire \z[30]_INST_0_i_22_n_0 ;
wire \z[30]_INST_0_i_230_n_0 ;
wire \z[30]_INST_0_i_231_n_0 ;
wire \z[30]_INST_0_i_232_n_0 ;
wire \z[30]_INST_0_i_233_n_0 ;
wire \z[30]_INST_0_i_234_n_0 ;
wire \z[30]_INST_0_i_235_n_0 ;
wire \z[30]_INST_0_i_236_n_0 ;
wire \z[30]_INST_0_i_237_n_0 ;
wire \z[30]_INST_0_i_238_n_0 ;
wire \z[30]_INST_0_i_239_n_0 ;
wire \z[30]_INST_0_i_240_n_0 ;
wire \z[30]_INST_0_i_241_n_0 ;
wire \z[30]_INST_0_i_242_n_0 ;
wire \z[30]_INST_0_i_243_n_0 ;
wire \z[30]_INST_0_i_244_n_0 ;
wire \z[30]_INST_0_i_245_n_0 ;
wire \z[30]_INST_0_i_246_n_0 ;
wire \z[30]_INST_0_i_29_n_0 ;
wire \z[30]_INST_0_i_2_n_0 ;
wire \z[30]_INST_0_i_30_n_0 ;
wire \z[30]_INST_0_i_31_n_0 ;
wire \z[30]_INST_0_i_32_n_0 ;
wire \z[30]_INST_0_i_33_n_0 ;
wire \z[30]_INST_0_i_34_n_0 ;
wire \z[30]_INST_0_i_35_n_0 ;
wire \z[30]_INST_0_i_36_n_0 ;
wire \z[30]_INST_0_i_37_n_0 ;
wire \z[30]_INST_0_i_38_n_0 ;
wire \z[30]_INST_0_i_39_n_0 ;
wire \z[30]_INST_0_i_3_n_0 ;
wire \z[30]_INST_0_i_40_n_0 ;
wire \z[30]_INST_0_i_41_n_0 ;
wire \z[30]_INST_0_i_42_n_0 ;
wire \z[30]_INST_0_i_43_n_0 ;
wire \z[30]_INST_0_i_44_n_0 ;
wire \z[30]_INST_0_i_45_n_0 ;
wire \z[30]_INST_0_i_46_n_0 ;
wire \z[30]_INST_0_i_47_n_0 ;
wire \z[30]_INST_0_i_48_n_0 ;
wire \z[30]_INST_0_i_49_n_0 ;
wire \z[30]_INST_0_i_50_n_0 ;
wire \z[30]_INST_0_i_51_n_0 ;
wire \z[30]_INST_0_i_52_n_0 ;
wire \z[30]_INST_0_i_53_n_0 ;
wire \z[30]_INST_0_i_54_n_0 ;
wire \z[30]_INST_0_i_55_n_0 ;
wire \z[30]_INST_0_i_56_n_0 ;
wire \z[30]_INST_0_i_57_n_0 ;
wire \z[30]_INST_0_i_58_n_0 ;
wire \z[30]_INST_0_i_59_n_0 ;
wire \z[30]_INST_0_i_5_n_0 ;
wire \z[30]_INST_0_i_60_n_0 ;
wire \z[30]_INST_0_i_61_n_0 ;
wire \z[30]_INST_0_i_62_n_0 ;
wire \z[30]_INST_0_i_63_n_0 ;
wire \z[30]_INST_0_i_64_n_0 ;
wire \z[30]_INST_0_i_65_n_0 ;
wire \z[30]_INST_0_i_66_n_0 ;
wire \z[30]_INST_0_i_67_n_0 ;
wire \z[30]_INST_0_i_68_n_0 ;
wire \z[30]_INST_0_i_69_n_0 ;
wire \z[30]_INST_0_i_6_n_0 ;
wire \z[30]_INST_0_i_70_n_0 ;
wire \z[30]_INST_0_i_71_n_0 ;
wire \z[30]_INST_0_i_72_n_0 ;
wire \z[30]_INST_0_i_73_n_0 ;
wire \z[30]_INST_0_i_74_n_0 ;
wire \z[30]_INST_0_i_75_n_0 ;
wire \z[30]_INST_0_i_76_n_0 ;
wire \z[30]_INST_0_i_77_n_0 ;
wire \z[30]_INST_0_i_78_n_0 ;
wire \z[30]_INST_0_i_79_n_0 ;
wire \z[30]_INST_0_i_80_n_0 ;
wire \z[30]_INST_0_i_81_n_0 ;
wire \z[30]_INST_0_i_82_n_0 ;
wire \z[30]_INST_0_i_83_n_0 ;
wire \z[30]_INST_0_i_94_n_0 ;
wire \z[30]_INST_0_i_95_n_0 ;
wire \z[30]_INST_0_i_96_n_0 ;
wire \z[30]_INST_0_i_97_n_0 ;
wire \z[30]_INST_0_i_98_n_0 ;
wire \z[30]_INST_0_i_99_n_0 ;
wire \z[30]_INST_0_i_9_n_0 ;
wire \z[3]_INST_0_i_1_n_0 ;
wire \z[3]_INST_0_i_1_n_1 ;
wire \z[3]_INST_0_i_1_n_2 ;
wire \z[3]_INST_0_i_1_n_3 ;
wire \z[3]_INST_0_i_2_n_0 ;
wire \z[3]_INST_0_i_3_n_0 ;
wire \z[3]_INST_0_i_5_n_0 ;
wire \z[3]_INST_0_i_6_n_0 ;
wire \z[3]_INST_0_i_7_n_0 ;
wire \z[3]_INST_0_i_8_n_0 ;
wire \z[3]_INST_0_i_9_n_0 ;
wire \z[7]_INST_0_i_10_n_0 ;
wire \z[7]_INST_0_i_11_n_0 ;
wire \z[7]_INST_0_i_12_n_0 ;
wire \z[7]_INST_0_i_1_n_0 ;
wire \z[7]_INST_0_i_1_n_1 ;
wire \z[7]_INST_0_i_1_n_2 ;
wire \z[7]_INST_0_i_1_n_3 ;
wire \z[7]_INST_0_i_6_n_0 ;
wire \z[7]_INST_0_i_7_n_0 ;
wire \z[7]_INST_0_i_8_n_0 ;
wire \z[7]_INST_0_i_9_n_0 ;
wire z_exponent0__0_carry__0_i_1_n_0;
wire z_exponent0__0_carry__0_i_2_n_0;
wire z_exponent0__0_carry__0_i_3_n_0;
wire z_exponent0__0_carry__0_i_4_n_0;
wire z_exponent0__0_carry__0_i_5_n_0;
wire z_exponent0__0_carry__0_i_6_n_0;
wire z_exponent0__0_carry__0_i_7_n_0;
wire z_exponent0__0_carry__0_i_8_n_0;
wire z_exponent0__0_carry__0_n_1;
wire z_exponent0__0_carry__0_n_2;
wire z_exponent0__0_carry__0_n_3;
wire z_exponent0__0_carry_i_1_n_0;
wire z_exponent0__0_carry_i_2_n_0;
wire z_exponent0__0_carry_i_3_n_0;
wire z_exponent0__0_carry_i_4_n_0;
wire z_exponent0__0_carry_i_5_n_0;
wire z_exponent0__0_carry_i_6_n_0;
wire z_exponent0__0_carry_i_7_n_0;
wire z_exponent0__0_carry_n_0;
wire z_exponent0__0_carry_n_1;
wire z_exponent0__0_carry_n_2;
wire z_exponent0__0_carry_n_3;
wire z_exponent1_carry__0_n_1;
wire z_exponent1_carry__0_n_2;
wire z_exponent1_carry__0_n_3;
wire z_exponent1_carry_i_1__0_n_0;
wire z_exponent1_carry_i_1_n_0;
wire z_exponent1_carry_i_2__0_n_0;
wire z_exponent1_carry_i_2_n_0;
wire z_exponent1_carry_i_3__0_n_0;
wire z_exponent1_carry_i_3_n_0;
wire z_exponent1_carry_i_4__0_n_0;
wire z_exponent1_carry_i_4_n_0;
wire z_exponent1_carry_i_5_n_0;
wire z_exponent1_carry_n_0;
wire z_exponent1_carry_n_1;
wire z_exponent1_carry_n_2;
wire z_exponent1_carry_n_3;
wire [22:0]z_mantissa;
wire [3:0]NLW_L1_carry_O_UNCONNECTED;
wire [3:0]NLW_L1_carry__0_O_UNCONNECTED;
wire [3:0]NLW_L1_carry__1_O_UNCONNECTED;
wire [3:0]NLW_L1_carry__2_O_UNCONNECTED;
wire [3:1]NLW__carry__6_CO_UNCONNECTED;
wire [3:2]NLW__carry__6_O_UNCONNECTED;
wire NLW_msb1_CARRYCASCOUT_UNCONNECTED;
wire NLW_msb1_MULTSIGNOUT_UNCONNECTED;
wire NLW_msb1_OVERFLOW_UNCONNECTED;
wire NLW_msb1_PATTERNBDETECT_UNCONNECTED;
wire NLW_msb1_PATTERNDETECT_UNCONNECTED;
wire NLW_msb1_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_msb1_ACOUT_UNCONNECTED;
wire [17:0]NLW_msb1_BCOUT_UNCONNECTED;
wire [3:0]NLW_msb1_CARRYOUT_UNCONNECTED;
wire NLW_msb1__0_CARRYCASCOUT_UNCONNECTED;
wire NLW_msb1__0_MULTSIGNOUT_UNCONNECTED;
wire NLW_msb1__0_OVERFLOW_UNCONNECTED;
wire NLW_msb1__0_PATTERNBDETECT_UNCONNECTED;
wire NLW_msb1__0_PATTERNDETECT_UNCONNECTED;
wire NLW_msb1__0_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_msb1__0_ACOUT_UNCONNECTED;
wire [17:0]NLW_msb1__0_BCOUT_UNCONNECTED;
wire [3:0]NLW_msb1__0_CARRYOUT_UNCONNECTED;
wire [47:31]NLW_msb1__0_P_UNCONNECTED;
wire [47:0]NLW_msb1__0_PCOUT_UNCONNECTED;
wire [3:2]\NLW_z[22]_INST_0_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_z[22]_INST_0_i_1_O_UNCONNECTED ;
wire [3:3]NLW_z_exponent0__0_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_z_exponent1_carry__0_CO_UNCONNECTED;
assign y_11__s_net_1 = y_11__s_port_;
CARRY4 L1_carry
(.CI(1'b0),
.CO({L1_carry_n_0,L1_carry_n_1,L1_carry_n_2,L1_carry_n_3}),
.CYINIT(1'b1),
.DI({L1_carry_i_1_n_0,L1_carry_i_2_n_0,L1_carry_i_3_n_0,L1_carry_i_4_n_0}),
.O(NLW_L1_carry_O_UNCONNECTED[3:0]),
.S({L1_carry_i_5_n_0,L1_carry_i_6_n_0,L1_carry_i_7_n_0,L1_carry_i_8_n_0}));
CARRY4 L1_carry__0
(.CI(L1_carry_n_0),
.CO({L1_carry__0_n_0,L1_carry__0_n_1,L1_carry__0_n_2,L1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({L1_carry__0_i_1_n_0,L1_carry__0_i_2_n_0,L1_carry__0_i_3_n_0,L1_carry__0_i_4_n_0}),
.O(NLW_L1_carry__0_O_UNCONNECTED[3:0]),
.S({L1_carry__0_i_5_n_0,L1_carry__0_i_6_n_0,L1_carry__0_i_7_n_0,L1_carry__0_i_8_n_0}));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__0_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_1_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__0_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__0_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__0_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__0_i_5
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__0_i_6
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__0_i_7
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__0_i_8
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_8_n_0));
CARRY4 L1_carry__1
(.CI(L1_carry__0_n_0),
.CO({L1_carry__1_n_0,L1_carry__1_n_1,L1_carry__1_n_2,L1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({L1_carry__1_i_1_n_0,L1_carry__1_i_2_n_0,L1_carry__1_i_3_n_0,L1_carry__1_i_4_n_0}),
.O(NLW_L1_carry__1_O_UNCONNECTED[3:0]),
.S({L1_carry__1_i_5_n_0,L1_carry__1_i_6_n_0,L1_carry__1_i_7_n_0,L1_carry__1_i_8_n_0}));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__1_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__1_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__1_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__1_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__1_i_5
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__1_i_6
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__1_i_7
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__1_i_8
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_8_n_0));
CARRY4 L1_carry__2
(.CI(L1_carry__1_n_0),
.CO({L1,L1_carry__2_n_1,L1_carry__2_n_2,L1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,L1_carry__2_i_1_n_0,L1_carry__2_i_2_n_0,L1_carry__2_i_3_n_0}),
.O(NLW_L1_carry__2_O_UNCONNECTED[3:0]),
.S({L1_carry__2_i_4_n_0,L1_carry__2_i_5_n_0,L1_carry__2_i_6_n_0,L1_carry__2_i_7_n_0}));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__2_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_1_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__2_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_2_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__2_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__2_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__2_i_5
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__2_i_6
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__2_i_7
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_7_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry_i_1_n_0));
LUT6 #(
.INIT(64'h4555FFFF45554555))
L1_carry_i_10
(.I0(L1_carry_i_24_n_0),
.I1(L1_carry_i_25_n_0),
.I2(L1_carry_i_26_n_0),
.I3(L1_carry_i_27_n_0),
.I4(L1_carry_i_28_n_0),
.I5(L1_carry_i_29_n_0),
.O(L1_carry_i_10_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFF7550000))
L1_carry_i_11
(.I0(L1_carry_i_30_n_0),
.I1(L1_carry_i_31_n_0),
.I2(L1_carry_i_32_n_0),
.I3(L1_carry_i_33_n_0),
.I4(L1_carry_i_34_n_0),
.I5(L1_carry_i_35_n_0),
.O(L1_carry_i_11_n_0));
LUT3 #(
.INIT(8'h2A))
L1_carry_i_12
(.I0(L1_carry_i_13_n_0),
.I1(L1_carry_i_22_n_0),
.I2(L1_carry_i_19_n_0),
.O(L1_carry_i_12_n_0));
LUT6 #(
.INIT(64'h0001000000000000))
L1_carry_i_13
(.I0(msb1__1[40]),
.I1(msb1__1[41]),
.I2(msb1__1[43]),
.I3(msb1__1[42]),
.I4(L1_carry_i_34_n_0),
.I5(L1_carry_i_23_n_0),
.O(L1_carry_i_13_n_0));
LUT5 #(
.INIT(32'hA9AA5555))
L1_carry_i_14
(.I0(L1_carry_i_12_n_0),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_10_n_0),
.I3(_carry_i_1_n_0),
.I4(L1_carry_i_9_n_0),
.O(L1_carry_i_14_n_0));
LUT6 #(
.INIT(64'h0200AAAAFDFF5555))
L1_carry_i_15
(.I0(L1_carry_i_12_n_0),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_10_n_0),
.I3(_carry_i_1_n_0),
.I4(L1_carry_i_9_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry_i_15_n_0));
LUT3 #(
.INIT(8'h65))
L1_carry_i_16
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_10_n_0),
.I2(_carry_i_1_n_0),
.O(L1_carry_i_16_n_0));
LUT4 #(
.INIT(16'h10EF))
L1_carry_i_17
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_10_n_0),
.I2(_carry_i_1_n_0),
.I3(L1_carry_i_9_n_0),
.O(L1_carry_i_17_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h00000002))
L1_carry_i_18
(.I0(L1_carry_i_34_n_0),
.I1(msb1__1[42]),
.I2(msb1__1[43]),
.I3(msb1__1[41]),
.I4(msb1__1[40]),
.O(L1_carry_i_18_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h00000002))
L1_carry_i_19
(.I0(L1_carry_i_36_n_0),
.I1(msb1__1[26]),
.I2(msb1__1[27]),
.I3(msb1__1[25]),
.I4(msb1__1[24]),
.O(L1_carry_i_19_n_0));
LUT2 #(
.INIT(4'hB))
L1_carry_i_2
(.I0(L1_carry_i_14_n_0),
.I1(L1_carry_i_15_n_0),
.O(L1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h0001))
L1_carry_i_20
(.I0(msb1__1[10]),
.I1(msb1__1[11]),
.I2(msb1__1[9]),
.I3(msb1__1[8]),
.O(L1_carry_i_20_n_0));
LUT4 #(
.INIT(16'hFFFE))
L1_carry_i_21
(.I0(msb1__1[14]),
.I1(msb1__1[15]),
.I2(msb1__1[13]),
.I3(msb1__1[12]),
.O(L1_carry_i_21_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00000002))
L1_carry_i_22
(.I0(L1_carry_i_37_n_0),
.I1(msb1__1[16]),
.I2(msb1__1[17]),
.I3(msb1__1[19]),
.I4(msb1__1[18]),
.O(L1_carry_i_22_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00000002))
L1_carry_i_23
(.I0(L1_carry_i_33_n_0),
.I1(msb1__1[32]),
.I2(msb1__1[33]),
.I3(msb1__1[35]),
.I4(msb1__1[34]),
.O(L1_carry_i_23_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF000EFFFF))
L1_carry_i_24
(.I0(msb1__1[39]),
.I1(msb1__1[38]),
.I2(msb1__1[41]),
.I3(msb1__1[40]),
.I4(L1_carry_i_29_n_0),
.I5(L1_carry_i_38_n_0),
.O(L1_carry_i_24_n_0));
LUT6 #(
.INIT(64'h000000000000F100))
L1_carry_i_25
(.I0(L1_carry_i_39_n_0),
.I1(L1_carry_i_40_n_0),
.I2(L1_carry_i_41_n_0),
.I3(L1_carry_i_42_n_0),
.I4(msb1__1[35]),
.I5(msb1__1[34]),
.O(L1_carry_i_25_n_0));
LUT6 #(
.INIT(64'h1111110011111101))
L1_carry_i_26
(.I0(msb1__1[37]),
.I1(msb1__1[36]),
.I2(msb1__1[33]),
.I3(msb1__1[34]),
.I4(msb1__1[35]),
.I5(msb1__1[32]),
.O(L1_carry_i_26_n_0));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT2 #(
.INIT(4'h1))
L1_carry_i_27
(.I0(msb1__1[41]),
.I1(msb1__1[40]),
.O(L1_carry_i_27_n_0));
LUT6 #(
.INIT(64'h1111111011111111))
L1_carry_i_28
(.I0(msb1__1[45]),
.I1(msb1__1[44]),
.I2(L1_carry_i_43_n_0),
.I3(L1_carry_i_44_n_0),
.I4(L1_carry_i_39_n_0),
.I5(L1_carry_i_45_n_0),
.O(L1_carry_i_28_n_0));
LUT2 #(
.INIT(4'h1))
L1_carry_i_29
(.I0(msb1__1[46]),
.I1(msb1__1[47]),
.O(L1_carry_i_29_n_0));
LUT2 #(
.INIT(4'hB))
L1_carry_i_3
(.I0(L1_carry_i_16_n_0),
.I1(L1_carry_i_17_n_0),
.O(L1_carry_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h0001))
L1_carry_i_30
(.I0(msb1__1[40]),
.I1(msb1__1[41]),
.I2(msb1__1[43]),
.I3(msb1__1[42]),
.O(L1_carry_i_30_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0001))
L1_carry_i_31
(.I0(msb1__1[34]),
.I1(msb1__1[35]),
.I2(msb1__1[33]),
.I3(msb1__1[32]),
.O(L1_carry_i_31_n_0));
LUT6 #(
.INIT(64'h8A888A888A88AA88))
L1_carry_i_32
(.I0(L1_carry_i_36_n_0),
.I1(L1_carry_i_46_n_0),
.I2(L1_carry_i_47_n_0),
.I3(L1_carry_i_37_n_0),
.I4(L1_carry_i_20_n_0),
.I5(L1_carry_i_21_n_0),
.O(L1_carry_i_32_n_0));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
L1_carry_i_33
(.I0(msb1__1[37]),
.I1(msb1__1[36]),
.I2(msb1__1[38]),
.I3(msb1__1[39]),
.O(L1_carry_i_33_n_0));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'h0001))
L1_carry_i_34
(.I0(msb1__1[47]),
.I1(msb1__1[46]),
.I2(msb1__1[45]),
.I3(msb1__1[44]),
.O(L1_carry_i_34_n_0));
LUT6 #(
.INIT(64'h0000400000000000))
L1_carry_i_35
(.I0(L1_carry_i_48_n_0),
.I1(L1_carry_i_49_n_0),
.I2(L1_carry_i_34_n_0),
.I3(L1_carry_i_36_n_0),
.I4(L1_carry_i_21_n_0),
.I5(L1_carry_i_37_n_0),
.O(L1_carry_i_35_n_0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h0001))
L1_carry_i_36
(.I0(msb1__1[28]),
.I1(msb1__1[29]),
.I2(msb1__1[30]),
.I3(msb1__1[31]),
.O(L1_carry_i_36_n_0));
LUT4 #(
.INIT(16'h0001))
L1_carry_i_37
(.I0(msb1__1[23]),
.I1(msb1__1[22]),
.I2(msb1__1[20]),
.I3(msb1__1[21]),
.O(L1_carry_i_37_n_0));
LUT2 #(
.INIT(4'hE))
L1_carry_i_38
(.I0(msb1__1[42]),
.I1(msb1__1[43]),
.O(L1_carry_i_38_n_0));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT4 #(
.INIT(16'hFFFE))
L1_carry_i_39
(.I0(msb1__1[23]),
.I1(msb1__1[22]),
.I2(msb1__1[18]),
.I3(msb1__1[19]),
.O(L1_carry_i_39_n_0));
LUT2 #(
.INIT(4'hD))
L1_carry_i_4
(.I0(_carry_i_1_n_0),
.I1(L1_carry_i_10_n_0),
.O(L1_carry_i_4_n_0));
LUT6 #(
.INIT(64'h000000000000FFF2))
L1_carry_i_40
(.I0(L1_carry_i_50_n_0),
.I1(L1_carry_i_51_n_0),
.I2(msb1__1[15]),
.I3(msb1__1[14]),
.I4(msb1__1[17]),
.I5(msb1__1[16]),
.O(L1_carry_i_40_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFE0FF))
L1_carry_i_41
(.I0(msb1__1[21]),
.I1(msb1__1[20]),
.I2(L1_carry_i_52_n_0),
.I3(L1_carry_i_53_n_0),
.I4(msb1__1[25]),
.I5(msb1__1[24]),
.O(L1_carry_i_41_n_0));
LUT6 #(
.INIT(64'h1111111111110001))
L1_carry_i_42
(.I0(msb1__1[30]),
.I1(msb1__1[31]),
.I2(msb1__1[26]),
.I3(msb1__1[27]),
.I4(msb1__1[29]),
.I5(msb1__1[28]),
.O(L1_carry_i_42_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFEFFFF))
L1_carry_i_43
(.I0(msb1__1[2]),
.I1(msb1__1[3]),
.I2(msb1__1[26]),
.I3(msb1__1[27]),
.I4(L1_carry_i_54_n_0),
.I5(L1_carry_i_38_n_0),
.O(L1_carry_i_43_n_0));
LUT4 #(
.INIT(16'hFFFE))
L1_carry_i_44
(.I0(msb1__1[7]),
.I1(msb1__1[6]),
.I2(msb1__1[10]),
.I3(msb1__1[11]),
.O(L1_carry_i_44_n_0));
LUT6 #(
.INIT(64'h0000000000000001))
L1_carry_i_45
(.I0(msb1__1[34]),
.I1(msb1__1[35]),
.I2(msb1__1[15]),
.I3(msb1__1[14]),
.I4(msb1__1[31]),
.I5(msb1__1[30]),
.O(L1_carry_i_45_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hFFFE))
L1_carry_i_46
(.I0(msb1__1[24]),
.I1(msb1__1[25]),
.I2(msb1__1[27]),
.I3(msb1__1[26]),
.O(L1_carry_i_46_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
L1_carry_i_47
(.I0(msb1__1[18]),
.I1(msb1__1[19]),
.I2(msb1__1[17]),
.I3(msb1__1[16]),
.O(L1_carry_i_47_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
L1_carry_i_48
(.I0(msb1__1[7]),
.I1(msb1__1[6]),
.I2(msb1__1[39]),
.I3(msb1__1[38]),
.I4(msb1__1[36]),
.I5(msb1__1[37]),
.O(L1_carry_i_48_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h1))
L1_carry_i_49
(.I0(msb1__1[5]),
.I1(msb1__1[4]),
.O(L1_carry_i_49_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry_i_5
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry_i_5_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF1))
L1_carry_i_50
(.I0(msb1__1[4]),
.I1(msb1__1[5]),
.I2(msb1__1[11]),
.I3(msb1__1[10]),
.I4(msb1__1[6]),
.I5(msb1__1[7]),
.O(L1_carry_i_50_n_0));
LUT6 #(
.INIT(64'hEEEEEEEEEEEEFFFE))
L1_carry_i_51
(.I0(msb1__1[13]),
.I1(msb1__1[12]),
.I2(msb1__1[8]),
.I3(msb1__1[9]),
.I4(msb1__1[11]),
.I5(msb1__1[10]),
.O(L1_carry_i_51_n_0));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h1))
L1_carry_i_52
(.I0(msb1__1[22]),
.I1(msb1__1[23]),
.O(L1_carry_i_52_n_0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h1))
L1_carry_i_53
(.I0(msb1__1[29]),
.I1(msb1__1[28]),
.O(L1_carry_i_53_n_0));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'h1))
L1_carry_i_54
(.I0(msb1__1[39]),
.I1(msb1__1[38]),
.O(L1_carry_i_54_n_0));
LUT2 #(
.INIT(4'h2))
L1_carry_i_6
(.I0(L1_carry_i_15_n_0),
.I1(L1_carry_i_14_n_0),
.O(L1_carry_i_6_n_0));
LUT2 #(
.INIT(4'h2))
L1_carry_i_7
(.I0(L1_carry_i_17_n_0),
.I1(L1_carry_i_16_n_0),
.O(L1_carry_i_7_n_0));
LUT2 #(
.INIT(4'h2))
L1_carry_i_8
(.I0(_carry_i_1_n_0),
.I1(L1_carry_i_10_n_0),
.O(L1_carry_i_8_n_0));
LUT6 #(
.INIT(64'h00808888AAAAAAAA))
L1_carry_i_9
(.I0(L1_carry_i_18_n_0),
.I1(L1_carry_i_19_n_0),
.I2(L1_carry_i_20_n_0),
.I3(L1_carry_i_21_n_0),
.I4(L1_carry_i_22_n_0),
.I5(L1_carry_i_23_n_0),
.O(L1_carry_i_9_n_0));
CARRY4 _carry
(.CI(1'b0),
.CO({_carry_n_0,_carry_n_1,_carry_n_2,_carry_n_3}),
.CYINIT(_carry_i_1_n_0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry_n_4,_carry_n_5,_carry_n_6,_carry_n_7}),
.S({_carry_i_2_n_0,_carry_i_3_n_0,_carry_i_4_n_0,p_0_in}));
CARRY4 _carry__0
(.CI(_carry_n_0),
.CO({_carry__0_n_0,_carry__0_n_1,_carry__0_n_2,_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry__0_n_4,_carry__0_n_5,_carry__0_n_6,_carry__0_n_7}),
.S({_carry__0_i_1_n_0,_carry__0_i_2_n_0,_carry__0_i_3_n_0,_carry__0_i_4_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__0_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__0_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__0_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__0_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h0200AAAAFDFF5555))
_carry__0_i_4
(.I0(L1_carry_i_12_n_0),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_10_n_0),
.I3(_carry_i_1_n_0),
.I4(L1_carry_i_9_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__0_i_4_n_0));
CARRY4 _carry__1
(.CI(_carry__0_n_0),
.CO({_carry__1_n_0,_carry__1_n_1,_carry__1_n_2,_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry__1_n_4,_carry__1_n_5,_carry__1_n_6,_carry__1_n_7}),
.S({_carry__1_i_1_n_0,_carry__1_i_2_n_0,_carry__1_i_3_n_0,_carry__1_i_4_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__1_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__1_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__1_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__1_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__1_i_4_n_0));
CARRY4 _carry__2
(.CI(_carry__1_n_0),
.CO({_carry__2_n_0,_carry__2_n_1,_carry__2_n_2,_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry__2_n_4,_carry__2_n_5,_carry__2_n_6,_carry__2_n_7}),
.S({_carry__2_i_1_n_0,_carry__2_i_2_n_0,_carry__2_i_3_n_0,_carry__2_i_4_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__2_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__2_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__2_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__2_i_2_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__2_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__2_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__2_i_4_n_0));
CARRY4 _carry__3
(.CI(_carry__2_n_0),
.CO({_carry__3_n_0,_carry__3_n_1,_carry__3_n_2,_carry__3_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry__3_n_4,_carry__3_n_5,_carry__3_n_6,_carry__3_n_7}),
.S({_carry__3_i_1_n_0,_carry__3_i_2_n_0,_carry__3_i_3_n_0,_carry__3_i_4_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__3_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__3_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__3_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__3_i_2_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__3_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__3_i_3_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__3_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__3_i_4_n_0));
CARRY4 _carry__4
(.CI(_carry__3_n_0),
.CO({_carry__4_n_0,_carry__4_n_1,_carry__4_n_2,_carry__4_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry__4_n_4,_carry__4_n_5,_carry__4_n_6,_carry__4_n_7}),
.S({_carry__4_i_1_n_0,_carry__4_i_2_n_0,_carry__4_i_3_n_0,_carry__4_i_4_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__4_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__4_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__4_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__4_i_2_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__4_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__4_i_3_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__4_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__4_i_4_n_0));
CARRY4 _carry__5
(.CI(_carry__4_n_0),
.CO({_carry__5_n_0,_carry__5_n_1,_carry__5_n_2,_carry__5_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry__5_n_4,_carry__5_n_5,_carry__5_n_6,_carry__5_n_7}),
.S({_carry__5_i_1_n_0,_carry__5_i_2_n_0,_carry__5_i_3_n_0,_carry__5_i_4_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__5_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__5_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__5_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__5_i_2_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__5_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__5_i_3_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__5_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__5_i_4_n_0));
CARRY4 _carry__6
(.CI(_carry__5_n_0),
.CO({NLW__carry__6_CO_UNCONNECTED[3:1],_carry__6_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW__carry__6_O_UNCONNECTED[3:2],_carry__6_n_6,_carry__6_n_7}),
.S({1'b0,1'b0,_carry__6_i_1_n_0,_carry__6_i_2_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__6_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__6_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__6_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__6_i_2_n_0));
LUT5 #(
.INIT(32'hBBBBABAA))
_carry_i_1
(.I0(msb1__1[47]),
.I1(_carry_i_6_n_0),
.I2(_carry_i_7_n_0),
.I3(_carry_i_8_n_0),
.I4(_carry_i_9_n_0),
.O(_carry_i_1_n_0));
LUT2 #(
.INIT(4'h9))
_carry_i_10
(.I0(_carry_i_1_n_0),
.I1(L1_carry_i_10_n_0),
.O(_carry_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT2 #(
.INIT(4'hE))
_carry_i_11
(.I0(msb1__1[42]),
.I1(msb1__1[40]),
.O(_carry_i_11_n_0));
LUT6 #(
.INIT(64'hFFF0FFF0FFFFFFF4))
_carry_i_12
(.I0(msb1__1[25]),
.I1(msb1__1[24]),
.I2(msb1__1[28]),
.I3(_carry_i_18_n_0),
.I4(msb1__1[26]),
.I5(msb1__1[27]),
.O(_carry_i_12_n_0));
LUT6 #(
.INIT(64'hFFF0FFF0FFFFFFF4))
_carry_i_13
(.I0(msb1__1[15]),
.I1(msb1__1[14]),
.I2(msb1__1[18]),
.I3(_carry_i_19_n_0),
.I4(msb1__1[16]),
.I5(msb1__1[17]),
.O(_carry_i_13_n_0));
LUT5 #(
.INIT(32'h0000EFEE))
_carry_i_14
(.I0(_carry_i_20_n_0),
.I1(msb1__1[7]),
.I2(msb1__1[6]),
.I3(msb1__1[5]),
.I4(_carry_i_21_n_0),
.O(_carry_i_14_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF00BA))
_carry_i_15
(.I0(msb1__1[11]),
.I1(msb1__1[10]),
.I2(msb1__1[9]),
.I3(msb1__1[12]),
.I4(_carry_i_22_n_0),
.I5(msb1__1[13]),
.O(_carry_i_15_n_0));
LUT6 #(
.INIT(64'hFFF0FFF0FFFFFFF4))
_carry_i_16
(.I0(msb1__1[20]),
.I1(msb1__1[19]),
.I2(msb1__1[23]),
.I3(_carry_i_23_n_0),
.I4(msb1__1[21]),
.I5(msb1__1[22]),
.O(_carry_i_16_n_0));
LUT6 #(
.INIT(64'hFFF0FFF0FFFFFFF4))
_carry_i_17
(.I0(msb1__1[30]),
.I1(msb1__1[29]),
.I2(msb1__1[33]),
.I3(_carry_i_24_n_0),
.I4(msb1__1[31]),
.I5(msb1__1[32]),
.O(_carry_i_17_n_0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'hE))
_carry_i_18
(.I0(msb1__1[32]),
.I1(msb1__1[30]),
.O(_carry_i_18_n_0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'hE))
_carry_i_19
(.I0(msb1__1[22]),
.I1(msb1__1[20]),
.O(_carry_i_19_n_0));
LUT5 #(
.INIT(32'h555DAAA2))
_carry_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.O(_carry_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'h5504))
_carry_i_20
(.I0(msb1__1[4]),
.I1(msb1__1[1]),
.I2(msb1__1[2]),
.I3(msb1__1[3]),
.O(_carry_i_20_n_0));
LUT5 #(
.INIT(32'hFFFFFFF4))
_carry_i_21
(.I0(msb1__1[7]),
.I1(msb1__1[6]),
.I2(msb1__1[12]),
.I3(msb1__1[10]),
.I4(msb1__1[8]),
.O(_carry_i_21_n_0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'hE))
_carry_i_22
(.I0(msb1__1[17]),
.I1(msb1__1[15]),
.O(_carry_i_22_n_0));
LUT2 #(
.INIT(4'hE))
_carry_i_23
(.I0(msb1__1[27]),
.I1(msb1__1[25]),
.O(_carry_i_23_n_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'hE))
_carry_i_24
(.I0(msb1__1[37]),
.I1(msb1__1[35]),
.O(_carry_i_24_n_0));
LUT4 #(
.INIT(16'h10EF))
_carry_i_3
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_10_n_0),
.I2(_carry_i_1_n_0),
.I3(L1_carry_i_9_n_0),
.O(_carry_i_3_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_4
(.I0(L1_carry_i_16_n_0),
.O(_carry_i_4_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_5
(.I0(_carry_i_10_n_0),
.O(p_0_in));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hBA))
_carry_i_6
(.I0(msb1__1[46]),
.I1(msb1__1[45]),
.I2(msb1__1[44]),
.O(_carry_i_6_n_0));
LUT6 #(
.INIT(64'hFFF0FFF0FFFFFFF4))
_carry_i_7
(.I0(msb1__1[35]),
.I1(msb1__1[34]),
.I2(msb1__1[38]),
.I3(_carry_i_11_n_0),
.I4(msb1__1[36]),
.I5(msb1__1[37]),
.O(_carry_i_7_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF55551110))
_carry_i_8
(.I0(_carry_i_12_n_0),
.I1(_carry_i_13_n_0),
.I2(_carry_i_14_n_0),
.I3(_carry_i_15_n_0),
.I4(_carry_i_16_n_0),
.I5(_carry_i_17_n_0),
.O(_carry_i_8_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF00F4))
_carry_i_9
(.I0(msb1__1[40]),
.I1(msb1__1[39]),
.I2(msb1__1[41]),
.I3(msb1__1[42]),
.I4(msb1__1[45]),
.I5(msb1__1[43]),
.O(_carry_i_9_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
msb1
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,y[22:0]}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_msb1_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,x[16:0]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_msb1_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_msb1_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_msb1_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_msb1_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_msb1_OVERFLOW_UNCONNECTED),
.P({msb1_n_58,msb1_n_59,msb1_n_60,msb1_n_61,msb1_n_62,msb1_n_63,msb1_n_64,msb1_n_65,msb1_n_66,msb1_n_67,msb1_n_68,msb1_n_69,msb1_n_70,msb1_n_71,msb1_n_72,msb1_n_73,msb1_n_74,msb1_n_75,msb1_n_76,msb1_n_77,msb1_n_78,msb1_n_79,msb1_n_80,msb1_n_81,msb1_n_82,msb1_n_83,msb1_n_84,msb1_n_85,msb1_n_86,msb1_n_87,msb1_n_88,msb1__1[16:0]}),
.PATTERNBDETECT(NLW_msb1_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_msb1_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({msb1_n_106,msb1_n_107,msb1_n_108,msb1_n_109,msb1_n_110,msb1_n_111,msb1_n_112,msb1_n_113,msb1_n_114,msb1_n_115,msb1_n_116,msb1_n_117,msb1_n_118,msb1_n_119,msb1_n_120,msb1_n_121,msb1_n_122,msb1_n_123,msb1_n_124,msb1_n_125,msb1_n_126,msb1_n_127,msb1_n_128,msb1_n_129,msb1_n_130,msb1_n_131,msb1_n_132,msb1_n_133,msb1_n_134,msb1_n_135,msb1_n_136,msb1_n_137,msb1_n_138,msb1_n_139,msb1_n_140,msb1_n_141,msb1_n_142,msb1_n_143,msb1_n_144,msb1_n_145,msb1_n_146,msb1_n_147,msb1_n_148,msb1_n_149,msb1_n_150,msb1_n_151,msb1_n_152,msb1_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_msb1_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
msb1__0
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,y[22:0]}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_msb1__0_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,x[22:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_msb1__0_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_msb1__0_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_msb1__0_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_msb1__0_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_msb1__0_OVERFLOW_UNCONNECTED),
.P({NLW_msb1__0_P_UNCONNECTED[47:31],msb1__1[47:17]}),
.PATTERNBDETECT(NLW_msb1__0_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_msb1__0_PATTERNDETECT_UNCONNECTED),
.PCIN({msb1_n_106,msb1_n_107,msb1_n_108,msb1_n_109,msb1_n_110,msb1_n_111,msb1_n_112,msb1_n_113,msb1_n_114,msb1_n_115,msb1_n_116,msb1_n_117,msb1_n_118,msb1_n_119,msb1_n_120,msb1_n_121,msb1_n_122,msb1_n_123,msb1_n_124,msb1_n_125,msb1_n_126,msb1_n_127,msb1_n_128,msb1_n_129,msb1_n_130,msb1_n_131,msb1_n_132,msb1_n_133,msb1_n_134,msb1_n_135,msb1_n_136,msb1_n_137,msb1_n_138,msb1_n_139,msb1_n_140,msb1_n_141,msb1_n_142,msb1_n_143,msb1_n_144,msb1_n_145,msb1_n_146,msb1_n_147,msb1_n_148,msb1_n_149,msb1_n_150,msb1_n_151,msb1_n_152,msb1_n_153}),
.PCOUT(NLW_msb1__0_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_msb1__0_UNDERFLOW_UNCONNECTED));
CARRY4 \z[11]_INST_0_i_1
(.CI(\z[7]_INST_0_i_1_n_0 ),
.CO({\z[11]_INST_0_i_1_n_0 ,\z[11]_INST_0_i_1_n_1 ,\z[11]_INST_0_i_1_n_2 ,\z[11]_INST_0_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z_mantissa[11:8]),
.S({sel0[11],\z[11]_INST_0_i_3_n_0 ,sel0[9:8]}));
LUT1 #(
.INIT(2'h1))
\z[11]_INST_0_i_2
(.I0(\z[30]_INST_0_i_11_n_0 ),
.O(sel0[11]));
LUT5 #(
.INIT(32'hFFFF8A80))
\z[11]_INST_0_i_3
(.I0(L1),
.I1(\z[30]_INST_0_i_50_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_47_n_0 ),
.I4(\z[30]_INST_0_i_51_n_0 ),
.O(\z[11]_INST_0_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\z[11]_INST_0_i_4
(.I0(\z[11]_INST_0_i_6_n_0 ),
.O(sel0[9]));
LUT1 #(
.INIT(2'h1))
\z[11]_INST_0_i_5
(.I0(\z[11]_INST_0_i_7_n_0 ),
.O(sel0[8]));
LUT5 #(
.INIT(32'h000047FF))
\z[11]_INST_0_i_6
(.I0(\z[11]_INST_0_i_8_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[30]_INST_0_i_50_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_52_n_0 ),
.O(\z[11]_INST_0_i_6_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[11]_INST_0_i_7
(.I0(\z[11]_INST_0_i_9_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[11]_INST_0_i_8_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_54_n_0 ),
.O(\z[11]_INST_0_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\z[11]_INST_0_i_8
(.I0(\z[30]_INST_0_i_121_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_98_n_0 ),
.O(\z[11]_INST_0_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\z[11]_INST_0_i_9
(.I0(\z[30]_INST_0_i_100_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_101_n_0 ),
.O(\z[11]_INST_0_i_9_n_0 ));
CARRY4 \z[15]_INST_0_i_1
(.CI(\z[11]_INST_0_i_1_n_0 ),
.CO({\z[15]_INST_0_i_1_n_0 ,\z[15]_INST_0_i_1_n_1 ,\z[15]_INST_0_i_1_n_2 ,\z[15]_INST_0_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z_mantissa[15:12]),
.S(sel0[15:12]));
LUT1 #(
.INIT(2'h1))
\z[15]_INST_0_i_2
(.I0(\z[30]_INST_0_i_14_n_0 ),
.O(sel0[15]));
LUT1 #(
.INIT(2'h1))
\z[15]_INST_0_i_3
(.I0(\z[30]_INST_0_i_15_n_0 ),
.O(sel0[14]));
LUT1 #(
.INIT(2'h1))
\z[15]_INST_0_i_4
(.I0(\z[15]_INST_0_i_6_n_0 ),
.O(sel0[13]));
LUT1 #(
.INIT(2'h1))
\z[15]_INST_0_i_5
(.I0(\z[15]_INST_0_i_7_n_0 ),
.O(sel0[12]));
LUT5 #(
.INIT(32'h000047FF))
\z[15]_INST_0_i_6
(.I0(\z[15]_INST_0_i_8_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[30]_INST_0_i_60_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_63_n_0 ),
.O(\z[15]_INST_0_i_6_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[15]_INST_0_i_7
(.I0(\z[30]_INST_0_i_48_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[15]_INST_0_i_8_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_65_n_0 ),
.O(\z[15]_INST_0_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\z[15]_INST_0_i_8
(.I0(\z[30]_INST_0_i_142_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_120_n_0 ),
.O(\z[15]_INST_0_i_8_n_0 ));
CARRY4 \z[19]_INST_0_i_1
(.CI(\z[15]_INST_0_i_1_n_0 ),
.CO({\z[19]_INST_0_i_1_n_0 ,\z[19]_INST_0_i_1_n_1 ,\z[19]_INST_0_i_1_n_2 ,\z[19]_INST_0_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z_mantissa[19:16]),
.S(sel0[19:16]));
LUT1 #(
.INIT(2'h1))
\z[19]_INST_0_i_2
(.I0(\z[30]_INST_0_i_17_n_0 ),
.O(sel0[19]));
LUT1 #(
.INIT(2'h1))
\z[19]_INST_0_i_3
(.I0(\z[30]_INST_0_i_18_n_0 ),
.O(sel0[18]));
LUT1 #(
.INIT(2'h1))
\z[19]_INST_0_i_4
(.I0(\z[30]_INST_0_i_19_n_0 ),
.O(sel0[17]));
LUT1 #(
.INIT(2'h1))
\z[19]_INST_0_i_5
(.I0(\z[30]_INST_0_i_20_n_0 ),
.O(sel0[16]));
CARRY4 \z[22]_INST_0_i_1
(.CI(\z[19]_INST_0_i_1_n_0 ),
.CO({\NLW_z[22]_INST_0_i_1_CO_UNCONNECTED [3:2],\z[22]_INST_0_i_1_n_2 ,\z[22]_INST_0_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_z[22]_INST_0_i_1_O_UNCONNECTED [3],z_mantissa[22:20]}),
.S({1'b0,sel0[22:20]}));
LUT5 #(
.INIT(32'hF2F2FFF2))
\z[22]_INST_0_i_2
(.I0(\z[30]_INST_0_i_57_n_0 ),
.I1(\z[30]_INST_0_i_81_n_0 ),
.I2(\z[30]_INST_0_i_76_n_0 ),
.I3(L1),
.I4(\z[22]_INST_0_i_5_n_0 ),
.O(sel0[22]));
LUT1 #(
.INIT(2'h1))
\z[22]_INST_0_i_3
(.I0(\z[30]_INST_0_i_22_n_0 ),
.O(sel0[21]));
LUT6 #(
.INIT(64'h22F222F2FFFF22F2))
\z[22]_INST_0_i_4
(.I0(\z[30]_INST_0_i_43_n_0 ),
.I1(\z[30]_INST_0_i_82_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_67_n_0 ),
.I4(L1),
.I5(\z[22]_INST_0_i_6_n_0 ),
.O(sel0[20]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[22]_INST_0_i_5
(.I0(\z[30]_INST_0_i_168_n_0 ),
.I1(\z[30]_INST_0_i_154_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_159_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_158_n_0 ),
.O(\z[22]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[22]_INST_0_i_6
(.I0(\z[30]_INST_0_i_154_n_0 ),
.I1(\z[30]_INST_0_i_155_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_158_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_152_n_0 ),
.O(\z[22]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[23]_INST_0
(.I0(data0[0]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[0]),
.I5(y_11__s_net_1),
.O(z[0]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[24]_INST_0
(.I0(data0[1]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[1]),
.I5(y_11__s_net_1),
.O(z[1]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[25]_INST_0
(.I0(data0[2]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[2]),
.I5(y_11__s_net_1),
.O(z[2]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[26]_INST_0
(.I0(data0[3]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[3]),
.I5(y_11__s_net_1),
.O(z[3]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[27]_INST_0
(.I0(data0[4]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[4]),
.I5(y_11__s_net_1),
.O(z[4]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[28]_INST_0
(.I0(data0[5]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[5]),
.I5(y_11__s_net_1),
.O(z[5]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[29]_INST_0
(.I0(data0[6]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[6]),
.I5(y_11__s_net_1),
.O(z[6]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[30]_INST_0
(.I0(data0[7]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[7]),
.I5(y_11__s_net_1),
.O(z[7]));
LUT6 #(
.INIT(64'hFFFFEFFFFFFFFFFF))
\z[30]_INST_0_i_1
(.I0(\z[30]_INST_0_i_5_n_0 ),
.I1(\z[30]_INST_0_i_6_n_0 ),
.I2(sel0[3]),
.I3(sel0[0]),
.I4(\z[30]_INST_0_i_9_n_0 ),
.I5(sel0[2]),
.O(\z[30]_INST_0_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFF8A80))
\z[30]_INST_0_i_10
(.I0(L1),
.I1(\z[30]_INST_0_i_44_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_37_n_0 ),
.I4(\z[30]_INST_0_i_46_n_0 ),
.O(sel0[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_100
(.I0(\z[30]_INST_0_i_181_n_0 ),
.I1(\z[30]_INST_0_i_182_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_183_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_184_n_0 ),
.O(\z[30]_INST_0_i_100_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_101
(.I0(\z[30]_INST_0_i_185_n_0 ),
.I1(\z[30]_INST_0_i_186_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_187_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_188_n_0 ),
.O(\z[30]_INST_0_i_101_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_102
(.I0(\z[30]_INST_0_i_189_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_171_n_0 ),
.O(\z[30]_INST_0_i_102_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFF4FFF7))
\z[30]_INST_0_i_103
(.I0(msb1__1[1]),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_118_n_0 ),
.I3(\z[30]_INST_0_i_170_n_0 ),
.I4(msb1__1[3]),
.I5(\z[30]_INST_0_i_169_n_0 ),
.O(\z[30]_INST_0_i_103_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_104
(.I0(\z[30]_INST_0_i_183_n_0 ),
.I1(\z[30]_INST_0_i_184_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_190_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_181_n_0 ),
.O(\z[30]_INST_0_i_104_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_105
(.I0(\z[30]_INST_0_i_187_n_0 ),
.I1(\z[30]_INST_0_i_188_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_191_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_185_n_0 ),
.O(\z[30]_INST_0_i_105_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_106
(.I0(\z[30]_INST_0_i_175_n_0 ),
.I1(\z[30]_INST_0_i_176_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_192_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_173_n_0 ),
.O(\z[30]_INST_0_i_106_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEAEFFFF))
\z[30]_INST_0_i_107
(.I0(\z[30]_INST_0_i_118_n_0 ),
.I1(_carry_n_4),
.I2(L1),
.I3(L1_carry_i_14_n_0),
.I4(msb1__1[3]),
.I5(\z[30]_INST_0_i_169_n_0 ),
.O(\z[30]_INST_0_i_107_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_108
(.I0(\z[30]_INST_0_i_179_n_0 ),
.I1(\z[30]_INST_0_i_180_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_193_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_177_n_0 ),
.O(\z[30]_INST_0_i_108_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFF4F7FFFF))
\z[30]_INST_0_i_109
(.I0(msb1__1[0]),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_118_n_0 ),
.I3(msb1__1[2]),
.I4(\z[30]_INST_0_i_194_n_0 ),
.I5(\z[30]_INST_0_i_169_n_0 ),
.O(\z[30]_INST_0_i_109_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[30]_INST_0_i_11
(.I0(\z[30]_INST_0_i_47_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[30]_INST_0_i_48_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_49_n_0 ),
.O(\z[30]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_110
(.I0(\z[30]_INST_0_i_190_n_0 ),
.I1(\z[30]_INST_0_i_181_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_195_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_183_n_0 ),
.O(\z[30]_INST_0_i_110_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_111
(.I0(\z[30]_INST_0_i_191_n_0 ),
.I1(L1_carry_i_17_n_0),
.I2(\z[30]_INST_0_i_185_n_0 ),
.O(\z[30]_INST_0_i_111_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_112
(.I0(\z[30]_INST_0_i_196_n_0 ),
.I1(L1_carry_i_17_n_0),
.I2(\z[30]_INST_0_i_187_n_0 ),
.O(\z[30]_INST_0_i_112_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_113
(.I0(\z[30]_INST_0_i_192_n_0 ),
.I1(L1_carry_i_17_n_0),
.I2(\z[30]_INST_0_i_173_n_0 ),
.O(\z[30]_INST_0_i_113_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_114
(.I0(\z[30]_INST_0_i_197_n_0 ),
.I1(L1_carry_i_17_n_0),
.I2(\z[30]_INST_0_i_175_n_0 ),
.O(\z[30]_INST_0_i_114_n_0 ));
LUT6 #(
.INIT(64'h3FFF3FAAFFFFFFFF))
\z[30]_INST_0_i_115
(.I0(_carry_n_5),
.I1(L1_carry_i_17_n_0),
.I2(\z[30]_INST_0_i_198_n_0 ),
.I3(L1),
.I4(_carry_n_4),
.I5(msb1__1[0]),
.O(\z[30]_INST_0_i_115_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\z[30]_INST_0_i_116
(.I0(\z[30]_INST_0_i_199_n_0 ),
.I1(_carry__0_n_6),
.I2(_carry__5_n_6),
.I3(_carry__0_n_5),
.I4(\z[30]_INST_0_i_200_n_0 ),
.I5(\z[30]_INST_0_i_201_n_0 ),
.O(\z[30]_INST_0_i_116_n_0 ));
LUT6 #(
.INIT(64'hFF3FFFFFFF3FAFAF))
\z[30]_INST_0_i_117
(.I0(_carry_n_5),
.I1(L1_carry_i_17_n_0),
.I2(msb1__1[1]),
.I3(L1_carry_i_14_n_0),
.I4(L1),
.I5(_carry_n_4),
.O(\z[30]_INST_0_i_117_n_0 ));
LUT5 #(
.INIT(32'h3C33AAAA))
\z[30]_INST_0_i_118
(.I0(_carry_n_6),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_10_n_0),
.I3(_carry_i_1_n_0),
.I4(L1),
.O(\z[30]_INST_0_i_118_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEAEFFFF))
\z[30]_INST_0_i_119
(.I0(\z[30]_INST_0_i_118_n_0 ),
.I1(_carry_n_4),
.I2(L1),
.I3(L1_carry_i_14_n_0),
.I4(msb1__1[1]),
.I5(\z[30]_INST_0_i_169_n_0 ),
.O(\z[30]_INST_0_i_119_n_0 ));
LUT5 #(
.INIT(32'hFFFF8A80))
\z[30]_INST_0_i_12
(.I0(L1),
.I1(\z[30]_INST_0_i_50_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_47_n_0 ),
.I4(\z[30]_INST_0_i_51_n_0 ),
.O(sel0[10]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_120
(.I0(\z[30]_INST_0_i_176_n_0 ),
.I1(\z[30]_INST_0_i_202_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_173_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_174_n_0 ),
.O(\z[30]_INST_0_i_120_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_121
(.I0(\z[30]_INST_0_i_180_n_0 ),
.I1(\z[30]_INST_0_i_203_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_177_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_178_n_0 ),
.O(\z[30]_INST_0_i_121_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_122
(.I0(\z[30]_INST_0_i_184_n_0 ),
.I1(\z[30]_INST_0_i_204_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_181_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_182_n_0 ),
.O(\z[30]_INST_0_i_122_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_123
(.I0(\z[30]_INST_0_i_188_n_0 ),
.I1(\z[30]_INST_0_i_205_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_185_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_186_n_0 ),
.O(\z[30]_INST_0_i_123_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\z[30]_INST_0_i_124
(.I0(\z[30]_INST_0_i_206_n_0 ),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(\z[30]_INST_0_i_207_n_0 ),
.I3(\z[30]_INST_0_i_95_n_0 ),
.I4(\z[30]_INST_0_i_208_n_0 ),
.O(\z[30]_INST_0_i_124_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\z[30]_INST_0_i_125
(.I0(\z[30]_INST_0_i_209_n_0 ),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(\z[30]_INST_0_i_132_n_0 ),
.I3(\z[30]_INST_0_i_95_n_0 ),
.I4(\z[30]_INST_0_i_210_n_0 ),
.O(\z[30]_INST_0_i_125_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\z[30]_INST_0_i_126
(.I0(\z[30]_INST_0_i_96_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_206_n_0 ),
.I3(\z[30]_INST_0_i_118_n_0 ),
.I4(\z[30]_INST_0_i_207_n_0 ),
.O(\z[30]_INST_0_i_126_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\z[30]_INST_0_i_127
(.I0(\z[30]_INST_0_i_172_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_209_n_0 ),
.I3(\z[30]_INST_0_i_118_n_0 ),
.I4(\z[30]_INST_0_i_132_n_0 ),
.O(\z[30]_INST_0_i_127_n_0 ));
LUT6 #(
.INIT(64'hAFA03030AFA03F3F))
\z[30]_INST_0_i_128
(.I0(\z[30]_INST_0_i_211_n_0 ),
.I1(\z[30]_INST_0_i_212_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_213_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_202_n_0 ),
.O(\z[30]_INST_0_i_128_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\z[30]_INST_0_i_129
(.I0(\z[30]_INST_0_i_178_n_0 ),
.I1(\z[30]_INST_0_i_214_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_180_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_203_n_0 ),
.O(\z[30]_INST_0_i_129_n_0 ));
LUT5 #(
.INIT(32'h115F1F5F))
\z[30]_INST_0_i_13
(.I0(\z[30]_INST_0_i_52_n_0 ),
.I1(\z[30]_INST_0_i_53_n_0 ),
.I2(\z[30]_INST_0_i_54_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_55_n_0 ),
.O(\z[30]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'h505FC0C0505FCFCF))
\z[30]_INST_0_i_130
(.I0(\z[30]_INST_0_i_182_n_0 ),
.I1(\z[30]_INST_0_i_215_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_184_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_204_n_0 ),
.O(\z[30]_INST_0_i_130_n_0 ));
LUT6 #(
.INIT(64'hA0AF3030A0AF3F3F))
\z[30]_INST_0_i_131
(.I0(\z[30]_INST_0_i_216_n_0 ),
.I1(\z[30]_INST_0_i_217_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_188_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_205_n_0 ),
.O(\z[30]_INST_0_i_131_n_0 ));
LUT6 #(
.INIT(64'h1510D5DFFFFFFFFF))
\z[30]_INST_0_i_132
(.I0(msb1__1[0]),
.I1(L1_carry_i_17_n_0),
.I2(L1),
.I3(_carry_n_5),
.I4(msb1__1[8]),
.I5(\z[30]_INST_0_i_194_n_0 ),
.O(\z[30]_INST_0_i_132_n_0 ));
LUT6 #(
.INIT(64'hFFF444F4FFF777F7))
\z[30]_INST_0_i_133
(.I0(msb1__1[4]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(_carry_n_4),
.I3(L1),
.I4(L1_carry_i_14_n_0),
.I5(msb1__1[12]),
.O(\z[30]_INST_0_i_133_n_0 ));
LUT6 #(
.INIT(64'h1510D5DFFFFFFFFF))
\z[30]_INST_0_i_134
(.I0(msb1__1[2]),
.I1(L1_carry_i_17_n_0),
.I2(L1),
.I3(_carry_n_5),
.I4(msb1__1[10]),
.I5(\z[30]_INST_0_i_194_n_0 ),
.O(\z[30]_INST_0_i_134_n_0 ));
LUT6 #(
.INIT(64'h1510D5DFFFFFFFFF))
\z[30]_INST_0_i_135
(.I0(msb1__1[6]),
.I1(L1_carry_i_17_n_0),
.I2(L1),
.I3(_carry_n_5),
.I4(msb1__1[14]),
.I5(\z[30]_INST_0_i_194_n_0 ),
.O(\z[30]_INST_0_i_135_n_0 ));
LUT5 #(
.INIT(32'hAFBBA088))
\z[30]_INST_0_i_136
(.I0(\z[30]_INST_0_i_207_n_0 ),
.I1(_carry_n_6),
.I2(L1_carry_i_16_n_0),
.I3(L1),
.I4(\z[30]_INST_0_i_146_n_0 ),
.O(\z[30]_INST_0_i_136_n_0 ));
LUT5 #(
.INIT(32'hAFBBA088))
\z[30]_INST_0_i_137
(.I0(\z[30]_INST_0_i_218_n_0 ),
.I1(_carry_n_6),
.I2(L1_carry_i_16_n_0),
.I3(L1),
.I4(\z[30]_INST_0_i_148_n_0 ),
.O(\z[30]_INST_0_i_137_n_0 ));
LUT6 #(
.INIT(64'hB080FFFFB0800000))
\z[30]_INST_0_i_138
(.I0(msb1__1[36]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[20]),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_217_n_0 ),
.O(\z[30]_INST_0_i_138_n_0 ));
LUT6 #(
.INIT(64'hB8BB8888B8B88888))
\z[30]_INST_0_i_139
(.I0(\z[30]_INST_0_i_188_n_0 ),
.I1(L1_carry_i_17_n_0),
.I2(msb1__1[40]),
.I3(L1_carry_i_14_n_0),
.I4(L1_carry_i_15_n_0),
.I5(msb1__1[24]),
.O(\z[30]_INST_0_i_139_n_0 ));
LUT6 #(
.INIT(64'hDD0DDD0D0000DD0D))
\z[30]_INST_0_i_14
(.I0(L1),
.I1(\z[30]_INST_0_i_56_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_58_n_0 ),
.I4(\z[30]_INST_0_i_43_n_0 ),
.I5(\z[30]_INST_0_i_59_n_0 ),
.O(\z[30]_INST_0_i_14_n_0 ));
LUT6 #(
.INIT(64'hB080FFFFB0800000))
\z[30]_INST_0_i_140
(.I0(msb1__1[37]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[21]),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_212_n_0 ),
.O(\z[30]_INST_0_i_140_n_0 ));
LUT6 #(
.INIT(64'hB080FFFFB0800000))
\z[30]_INST_0_i_141
(.I0(msb1__1[33]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[17]),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_202_n_0 ),
.O(\z[30]_INST_0_i_141_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_142
(.I0(\z[30]_INST_0_i_178_n_0 ),
.I1(\z[30]_INST_0_i_214_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_180_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_203_n_0 ),
.O(\z[30]_INST_0_i_142_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\z[30]_INST_0_i_143
(.I0(\z[30]_INST_0_i_208_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_207_n_0 ),
.I3(\z[30]_INST_0_i_118_n_0 ),
.I4(\z[30]_INST_0_i_146_n_0 ),
.O(\z[30]_INST_0_i_143_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\z[30]_INST_0_i_144
(.I0(\z[30]_INST_0_i_210_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_132_n_0 ),
.I3(\z[30]_INST_0_i_118_n_0 ),
.I4(\z[30]_INST_0_i_133_n_0 ),
.O(\z[30]_INST_0_i_144_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_145
(.I0(\z[30]_INST_0_i_186_n_0 ),
.I1(\z[30]_INST_0_i_217_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_188_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_205_n_0 ),
.O(\z[30]_INST_0_i_145_n_0 ));
LUT6 #(
.INIT(64'h4747FF47FFFFFF47))
\z[30]_INST_0_i_146
(.I0(msb1__1[5]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(msb1__1[13]),
.I3(_carry_n_4),
.I4(L1),
.I5(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_146_n_0 ));
LUT6 #(
.INIT(64'h77CF44CC77CF77CF))
\z[30]_INST_0_i_147
(.I0(msb1__1[9]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(msb1__1[1]),
.I3(\z[30]_INST_0_i_194_n_0 ),
.I4(\z[30]_INST_0_i_170_n_0 ),
.I5(msb1__1[17]),
.O(\z[30]_INST_0_i_147_n_0 ));
LUT6 #(
.INIT(64'h7757555777F7FFF7))
\z[30]_INST_0_i_148
(.I0(\z[30]_INST_0_i_194_n_0 ),
.I1(msb1__1[15]),
.I2(_carry_n_5),
.I3(L1),
.I4(L1_carry_i_17_n_0),
.I5(msb1__1[7]),
.O(\z[30]_INST_0_i_148_n_0 ));
LUT6 #(
.INIT(64'hFF00FFFF47474747))
\z[30]_INST_0_i_149
(.I0(msb1__1[19]),
.I1(\z[30]_INST_0_i_194_n_0 ),
.I2(msb1__1[3]),
.I3(\z[30]_INST_0_i_170_n_0 ),
.I4(msb1__1[11]),
.I5(\z[30]_INST_0_i_169_n_0 ),
.O(\z[30]_INST_0_i_149_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[30]_INST_0_i_15
(.I0(\z[30]_INST_0_i_60_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[30]_INST_0_i_61_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_62_n_0 ),
.O(\z[30]_INST_0_i_15_n_0 ));
LUT5 #(
.INIT(32'hAFBBA088))
\z[30]_INST_0_i_150
(.I0(\z[30]_INST_0_i_133_n_0 ),
.I1(_carry_n_6),
.I2(L1_carry_i_16_n_0),
.I3(L1),
.I4(\z[30]_INST_0_i_166_n_0 ),
.O(\z[30]_INST_0_i_150_n_0 ));
LUT5 #(
.INIT(32'hF5DD0511))
\z[30]_INST_0_i_151
(.I0(\z[30]_INST_0_i_163_n_0 ),
.I1(_carry_n_6),
.I2(L1_carry_i_16_n_0),
.I3(L1),
.I4(\z[30]_INST_0_i_135_n_0 ),
.O(\z[30]_INST_0_i_151_n_0 ));
LUT5 #(
.INIT(32'hB888B8BB))
\z[30]_INST_0_i_152
(.I0(\z[30]_INST_0_i_219_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_211_n_0 ),
.I3(L1_carry_i_17_n_0),
.I4(\z[30]_INST_0_i_212_n_0 ),
.O(\z[30]_INST_0_i_152_n_0 ));
LUT6 #(
.INIT(64'h505FC0C0505FCFCF))
\z[30]_INST_0_i_153
(.I0(\z[30]_INST_0_i_203_n_0 ),
.I1(\z[30]_INST_0_i_220_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_178_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_214_n_0 ),
.O(\z[30]_INST_0_i_153_n_0 ));
LUT5 #(
.INIT(32'h8BBB8B88))
\z[30]_INST_0_i_154
(.I0(\z[30]_INST_0_i_221_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_182_n_0 ),
.I3(L1_carry_i_17_n_0),
.I4(\z[30]_INST_0_i_215_n_0 ),
.O(\z[30]_INST_0_i_154_n_0 ));
LUT5 #(
.INIT(32'hB888B8BB))
\z[30]_INST_0_i_155
(.I0(\z[30]_INST_0_i_222_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_216_n_0 ),
.I3(L1_carry_i_17_n_0),
.I4(\z[30]_INST_0_i_217_n_0 ),
.O(\z[30]_INST_0_i_155_n_0 ));
LUT5 #(
.INIT(32'hAFBBA088))
\z[30]_INST_0_i_156
(.I0(\z[30]_INST_0_i_146_n_0 ),
.I1(_carry_n_6),
.I2(L1_carry_i_16_n_0),
.I3(L1),
.I4(\z[30]_INST_0_i_147_n_0 ),
.O(\z[30]_INST_0_i_156_n_0 ));
LUT5 #(
.INIT(32'hAFBBA088))
\z[30]_INST_0_i_157
(.I0(\z[30]_INST_0_i_134_n_0 ),
.I1(_carry_n_6),
.I2(L1_carry_i_16_n_0),
.I3(L1),
.I4(\z[30]_INST_0_i_135_n_0 ),
.O(\z[30]_INST_0_i_157_n_0 ));
LUT5 #(
.INIT(32'h8BBB8B88))
\z[30]_INST_0_i_158
(.I0(\z[30]_INST_0_i_223_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_203_n_0 ),
.I3(L1_carry_i_17_n_0),
.I4(\z[30]_INST_0_i_220_n_0 ),
.O(\z[30]_INST_0_i_158_n_0 ));
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_159
(.I0(\z[30]_INST_0_i_224_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_219_n_0 ),
.O(\z[30]_INST_0_i_159_n_0 ));
LUT5 #(
.INIT(32'h115F1F5F))
\z[30]_INST_0_i_16
(.I0(\z[30]_INST_0_i_63_n_0 ),
.I1(\z[30]_INST_0_i_64_n_0 ),
.I2(\z[30]_INST_0_i_65_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_66_n_0 ),
.O(\z[30]_INST_0_i_16_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_160
(.I0(\z[30]_INST_0_i_225_n_0 ),
.I1(\z[30]_INST_0_i_222_n_0 ),
.I2(_carry_i_10_n_0),
.I3(\z[30]_INST_0_i_221_n_0 ),
.I4(L1_carry_i_16_n_0),
.I5(\z[30]_INST_0_i_226_n_0 ),
.O(\z[30]_INST_0_i_160_n_0 ));
LUT5 #(
.INIT(32'hB888B8BB))
\z[30]_INST_0_i_161
(.I0(\z[30]_INST_0_i_166_n_0 ),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(\z[30]_INST_0_i_227_n_0 ),
.I3(\z[30]_INST_0_i_169_n_0 ),
.I4(\z[30]_INST_0_i_228_n_0 ),
.O(\z[30]_INST_0_i_161_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\z[30]_INST_0_i_162
(.I0(msb1__1[14]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(msb1__1[6]),
.I3(\z[30]_INST_0_i_170_n_0 ),
.I4(msb1__1[22]),
.O(\z[30]_INST_0_i_162_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\z[30]_INST_0_i_163
(.I0(msb1__1[10]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(msb1__1[2]),
.I3(\z[30]_INST_0_i_170_n_0 ),
.I4(msb1__1[18]),
.O(\z[30]_INST_0_i_163_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_164
(.I0(\z[30]_INST_0_i_223_n_0 ),
.I1(\z[30]_INST_0_i_229_n_0 ),
.I2(_carry_i_10_n_0),
.I3(\z[30]_INST_0_i_219_n_0 ),
.I4(L1_carry_i_16_n_0),
.I5(\z[30]_INST_0_i_230_n_0 ),
.O(\z[30]_INST_0_i_164_n_0 ));
LUT5 #(
.INIT(32'h47CC47FF))
\z[30]_INST_0_i_165
(.I0(msb1__1[13]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(msb1__1[21]),
.I3(\z[30]_INST_0_i_194_n_0 ),
.I4(msb1__1[5]),
.O(\z[30]_INST_0_i_165_n_0 ));
LUT6 #(
.INIT(64'h4447CCCF4447FFFF))
\z[30]_INST_0_i_166
(.I0(msb1__1[8]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(\z[30]_INST_0_i_170_n_0 ),
.I3(msb1__1[16]),
.I4(\z[30]_INST_0_i_194_n_0 ),
.I5(msb1__1[0]),
.O(\z[30]_INST_0_i_166_n_0 ));
LUT6 #(
.INIT(64'hB0BFB0B0B0BFBFBF))
\z[30]_INST_0_i_167
(.I0(\z[30]_INST_0_i_170_n_0 ),
.I1(msb1__1[12]),
.I2(\z[30]_INST_0_i_169_n_0 ),
.I3(msb1__1[20]),
.I4(\z[30]_INST_0_i_194_n_0 ),
.I5(msb1__1[4]),
.O(\z[30]_INST_0_i_167_n_0 ));
LUT6 #(
.INIT(64'h7477FFFF74770000))
\z[30]_INST_0_i_168
(.I0(\z[30]_INST_0_i_217_n_0 ),
.I1(L1_carry_i_17_n_0),
.I2(L1_carry_i_14_n_0),
.I3(\z[30]_INST_0_i_231_n_0 ),
.I4(L1_carry_i_16_n_0),
.I5(\z[30]_INST_0_i_222_n_0 ),
.O(\z[30]_INST_0_i_168_n_0 ));
LUT6 #(
.INIT(64'hAAA6FFFFAAA60000))
\z[30]_INST_0_i_169
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1),
.I5(_carry_n_5),
.O(\z[30]_INST_0_i_169_n_0 ));
LUT6 #(
.INIT(64'hDD0DDD0D0000DD0D))
\z[30]_INST_0_i_17
(.I0(\z[30]_INST_0_i_43_n_0 ),
.I1(\z[30]_INST_0_i_67_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_68_n_0 ),
.I4(L1),
.I5(\z[30]_INST_0_i_69_n_0 ),
.O(\z[30]_INST_0_i_17_n_0 ));
LUT6 #(
.INIT(64'h9A55FFFF9A550000))
\z[30]_INST_0_i_170
(.I0(L1_carry_i_12_n_0),
.I1(\z[30]_INST_0_i_232_n_0 ),
.I2(_carry_i_1_n_0),
.I3(L1_carry_i_9_n_0),
.I4(L1),
.I5(_carry_n_4),
.O(\z[30]_INST_0_i_170_n_0 ));
LUT6 #(
.INIT(64'hFF7FFF7FFF70FF7F))
\z[30]_INST_0_i_171
(.I0(\z[30]_INST_0_i_194_n_0 ),
.I1(msb1__1[0]),
.I2(\z[30]_INST_0_i_118_n_0 ),
.I3(\z[30]_INST_0_i_169_n_0 ),
.I4(msb1__1[4]),
.I5(\z[30]_INST_0_i_170_n_0 ),
.O(\z[30]_INST_0_i_171_n_0 ));
LUT5 #(
.INIT(32'hF4FFF7FF))
\z[30]_INST_0_i_172
(.I0(msb1__1[2]),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(\z[30]_INST_0_i_169_n_0 ),
.I3(\z[30]_INST_0_i_194_n_0 ),
.I4(msb1__1[6]),
.O(\z[30]_INST_0_i_172_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_173
(.I0(msb1__1[29]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[13]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[45]),
.O(\z[30]_INST_0_i_173_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hB080))
\z[30]_INST_0_i_174
(.I0(msb1__1[37]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[21]),
.O(\z[30]_INST_0_i_174_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_175
(.I0(msb1__1[25]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[9]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[41]),
.O(\z[30]_INST_0_i_175_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hB080))
\z[30]_INST_0_i_176
(.I0(msb1__1[33]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[17]),
.O(\z[30]_INST_0_i_176_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_177
(.I0(msb1__1[27]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[11]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[43]),
.O(\z[30]_INST_0_i_177_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h88C0))
\z[30]_INST_0_i_178
(.I0(msb1__1[19]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[35]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_178_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_179
(.I0(msb1__1[23]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[7]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[39]),
.O(\z[30]_INST_0_i_179_n_0 ));
LUT6 #(
.INIT(64'hDD0DDD0D0000DD0D))
\z[30]_INST_0_i_18
(.I0(\z[30]_INST_0_i_43_n_0 ),
.I1(\z[30]_INST_0_i_68_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_70_n_0 ),
.I4(L1),
.I5(\z[30]_INST_0_i_71_n_0 ),
.O(\z[30]_INST_0_i_18_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hACACF000))
\z[30]_INST_0_i_180
(.I0(msb1__1[15]),
.I1(msb1__1[47]),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[31]),
.I4(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_180_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_181
(.I0(msb1__1[30]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[14]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[46]),
.O(\z[30]_INST_0_i_181_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h88C0))
\z[30]_INST_0_i_182
(.I0(msb1__1[22]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[38]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_182_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_183
(.I0(msb1__1[26]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[10]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[42]),
.O(\z[30]_INST_0_i_183_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h88C0))
\z[30]_INST_0_i_184
(.I0(msb1__1[18]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[34]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_184_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_185
(.I0(msb1__1[28]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[12]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[44]),
.O(\z[30]_INST_0_i_185_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hB080))
\z[30]_INST_0_i_186
(.I0(msb1__1[36]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[20]),
.O(\z[30]_INST_0_i_186_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_187
(.I0(msb1__1[24]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[8]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[40]),
.O(\z[30]_INST_0_i_187_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h88C0))
\z[30]_INST_0_i_188
(.I0(msb1__1[16]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[32]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_188_n_0 ));
LUT6 #(
.INIT(64'hBFFFFFFFBFFFBFBF))
\z[30]_INST_0_i_189
(.I0(\z[30]_INST_0_i_118_n_0 ),
.I1(msb1__1[2]),
.I2(\z[30]_INST_0_i_194_n_0 ),
.I3(L1_carry_i_17_n_0),
.I4(L1),
.I5(_carry_n_5),
.O(\z[30]_INST_0_i_189_n_0 ));
LUT6 #(
.INIT(64'hDD0DDD0D0000DD0D))
\z[30]_INST_0_i_19
(.I0(\z[30]_INST_0_i_57_n_0 ),
.I1(\z[30]_INST_0_i_72_n_0 ),
.I2(\z[30]_INST_0_i_43_n_0 ),
.I3(\z[30]_INST_0_i_70_n_0 ),
.I4(L1),
.I5(\z[30]_INST_0_i_73_n_0 ),
.O(\z[30]_INST_0_i_19_n_0 ));
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_190
(.I0(msb1__1[22]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[6]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[38]),
.O(\z[30]_INST_0_i_190_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_191
(.I0(msb1__1[20]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[4]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[36]),
.O(\z[30]_INST_0_i_191_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_192
(.I0(msb1__1[21]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[5]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[37]),
.O(\z[30]_INST_0_i_192_n_0 ));
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_193
(.I0(msb1__1[19]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[3]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[35]),
.O(\z[30]_INST_0_i_193_n_0 ));
LUT6 #(
.INIT(64'h5DA200005DA2FFFF))
\z[30]_INST_0_i_194
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(\z[30]_INST_0_i_232_n_0 ),
.I3(L1_carry_i_12_n_0),
.I4(L1),
.I5(_carry_n_4),
.O(\z[30]_INST_0_i_194_n_0 ));
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_195
(.I0(msb1__1[18]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[2]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[34]),
.O(\z[30]_INST_0_i_195_n_0 ));
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_196
(.I0(msb1__1[16]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[0]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[32]),
.O(\z[30]_INST_0_i_196_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_197
(.I0(msb1__1[17]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[1]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[33]),
.O(\z[30]_INST_0_i_197_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h555DAAA2))
\z[30]_INST_0_i_198
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.O(\z[30]_INST_0_i_198_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_199
(.I0(_carry__2_n_4),
.I1(_carry__3_n_4),
.I2(_carry__4_n_4),
.I3(_carry__5_n_5),
.I4(\z[30]_INST_0_i_233_n_0 ),
.O(\z[30]_INST_0_i_199_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\z[30]_INST_0_i_2
(.I0(\z[30]_INST_0_i_11_n_0 ),
.I1(sel0[10]),
.I2(\z[30]_INST_0_i_13_n_0 ),
.I3(\z[30]_INST_0_i_14_n_0 ),
.I4(\z[30]_INST_0_i_15_n_0 ),
.I5(\z[30]_INST_0_i_16_n_0 ),
.O(\z[30]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hDD0DDD0D0000DD0D))
\z[30]_INST_0_i_20
(.I0(\z[30]_INST_0_i_43_n_0 ),
.I1(\z[30]_INST_0_i_72_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_59_n_0 ),
.I4(L1),
.I5(\z[30]_INST_0_i_74_n_0 ),
.O(\z[30]_INST_0_i_20_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_200
(.I0(_carry__1_n_4),
.I1(_carry__6_n_6),
.I2(_carry__0_n_7),
.I3(_carry__4_n_5),
.I4(\z[30]_INST_0_i_234_n_0 ),
.O(\z[30]_INST_0_i_200_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_201
(.I0(_carry__2_n_5),
.I1(_carry__6_n_7),
.I2(_carry__0_n_4),
.I3(_carry__5_n_7),
.I4(\z[30]_INST_0_i_235_n_0 ),
.O(\z[30]_INST_0_i_201_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_202
(.I0(msb1__1[41]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[25]),
.O(\z[30]_INST_0_i_202_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_203
(.I0(msb1__1[39]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[23]),
.O(\z[30]_INST_0_i_203_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_204
(.I0(msb1__1[42]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[26]),
.O(\z[30]_INST_0_i_204_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_205
(.I0(msb1__1[40]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[24]),
.O(\z[30]_INST_0_i_205_n_0 ));
LUT6 #(
.INIT(64'hFF3FFFFFFF3FAFAF))
\z[30]_INST_0_i_206
(.I0(_carry_n_5),
.I1(L1_carry_i_17_n_0),
.I2(msb1__1[5]),
.I3(L1_carry_i_14_n_0),
.I4(L1),
.I5(_carry_n_4),
.O(\z[30]_INST_0_i_206_n_0 ));
LUT6 #(
.INIT(64'h4747FF47FFFFFF47))
\z[30]_INST_0_i_207
(.I0(msb1__1[1]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(msb1__1[9]),
.I3(_carry_n_4),
.I4(L1),
.I5(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_207_n_0 ));
LUT6 #(
.INIT(64'hFFFFCF44FFFFCF77))
\z[30]_INST_0_i_208
(.I0(msb1__1[7]),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(msb1__1[3]),
.I3(\z[30]_INST_0_i_169_n_0 ),
.I4(\z[30]_INST_0_i_170_n_0 ),
.I5(msb1__1[11]),
.O(\z[30]_INST_0_i_208_n_0 ));
LUT6 #(
.INIT(64'hFF3FFFFFFF3FAFAF))
\z[30]_INST_0_i_209
(.I0(_carry_n_5),
.I1(L1_carry_i_17_n_0),
.I2(msb1__1[4]),
.I3(L1_carry_i_14_n_0),
.I4(L1),
.I5(_carry_n_4),
.O(\z[30]_INST_0_i_209_n_0 ));
LUT6 #(
.INIT(64'h101010FF10101010))
\z[30]_INST_0_i_21
(.I0(\z[30]_INST_0_i_75_n_0 ),
.I1(\z[30]_INST_0_i_76_n_0 ),
.I2(\z[30]_INST_0_i_77_n_0 ),
.I3(\z[30]_INST_0_i_78_n_0 ),
.I4(\z[30]_INST_0_i_79_n_0 ),
.I5(\z[30]_INST_0_i_80_n_0 ),
.O(\z[30]_INST_0_i_21_n_0 ));
LUT6 #(
.INIT(64'hCF44CF77FFFFFFFF))
\z[30]_INST_0_i_210
(.I0(msb1__1[6]),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(msb1__1[2]),
.I3(\z[30]_INST_0_i_169_n_0 ),
.I4(msb1__1[10]),
.I5(\z[30]_INST_0_i_194_n_0 ),
.O(\z[30]_INST_0_i_210_n_0 ));
LUT4 #(
.INIT(16'h773F))
\z[30]_INST_0_i_211
(.I0(msb1__1[21]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[37]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_211_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_212
(.I0(msb1__1[45]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[29]),
.O(\z[30]_INST_0_i_212_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'h773F))
\z[30]_INST_0_i_213
(.I0(msb1__1[17]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[33]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_213_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_214
(.I0(msb1__1[43]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[27]),
.O(\z[30]_INST_0_i_214_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h4F5F))
\z[30]_INST_0_i_215
(.I0(msb1__1[46]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[30]),
.O(\z[30]_INST_0_i_215_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h773F))
\z[30]_INST_0_i_216
(.I0(msb1__1[20]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[36]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_216_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_217
(.I0(msb1__1[44]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[28]),
.O(\z[30]_INST_0_i_217_n_0 ));
LUT6 #(
.INIT(64'hFFF444F4FFF777F7))
\z[30]_INST_0_i_218
(.I0(msb1__1[3]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(_carry_n_4),
.I3(L1),
.I4(L1_carry_i_14_n_0),
.I5(msb1__1[11]),
.O(\z[30]_INST_0_i_218_n_0 ));
LUT6 #(
.INIT(64'h3F103F1FFFFFFFFF))
\z[30]_INST_0_i_219
(.I0(msb1__1[25]),
.I1(msb1__1[41]),
.I2(L1_carry_i_17_n_0),
.I3(L1_carry_i_14_n_0),
.I4(msb1__1[33]),
.I5(L1_carry_i_15_n_0),
.O(\z[30]_INST_0_i_219_n_0 ));
LUT6 #(
.INIT(64'hDD0DDD0D0000DD0D))
\z[30]_INST_0_i_22
(.I0(\z[30]_INST_0_i_43_n_0 ),
.I1(\z[30]_INST_0_i_81_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_82_n_0 ),
.I4(L1),
.I5(\z[30]_INST_0_i_83_n_0 ),
.O(\z[30]_INST_0_i_22_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h3777))
\z[30]_INST_0_i_220
(.I0(msb1__1[47]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[31]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_220_n_0 ));
LUT6 #(
.INIT(64'h103F1F3FFFFFFFFF))
\z[30]_INST_0_i_221
(.I0(msb1__1[26]),
.I1(msb1__1[42]),
.I2(L1_carry_i_17_n_0),
.I3(\z[30]_INST_0_i_198_n_0 ),
.I4(msb1__1[34]),
.I5(L1_carry_i_15_n_0),
.O(\z[30]_INST_0_i_221_n_0 ));
LUT6 #(
.INIT(64'h103F1F3FFFFFFFFF))
\z[30]_INST_0_i_222
(.I0(msb1__1[24]),
.I1(msb1__1[40]),
.I2(L1_carry_i_17_n_0),
.I3(\z[30]_INST_0_i_198_n_0 ),
.I4(msb1__1[32]),
.I5(L1_carry_i_15_n_0),
.O(\z[30]_INST_0_i_222_n_0 ));
LUT6 #(
.INIT(64'h103F1F3FFFFFFFFF))
\z[30]_INST_0_i_223
(.I0(msb1__1[27]),
.I1(msb1__1[43]),
.I2(L1_carry_i_17_n_0),
.I3(\z[30]_INST_0_i_198_n_0 ),
.I4(msb1__1[35]),
.I5(L1_carry_i_15_n_0),
.O(\z[30]_INST_0_i_223_n_0 ));
LUT6 #(
.INIT(64'h3F103F1FFFFFFFFF))
\z[30]_INST_0_i_224
(.I0(msb1__1[29]),
.I1(msb1__1[45]),
.I2(L1_carry_i_17_n_0),
.I3(L1_carry_i_14_n_0),
.I4(msb1__1[37]),
.I5(L1_carry_i_15_n_0),
.O(\z[30]_INST_0_i_224_n_0 ));
LUT6 #(
.INIT(64'h3F103F1FFFFFFFFF))
\z[30]_INST_0_i_225
(.I0(msb1__1[28]),
.I1(msb1__1[44]),
.I2(L1_carry_i_17_n_0),
.I3(L1_carry_i_14_n_0),
.I4(msb1__1[36]),
.I5(L1_carry_i_15_n_0),
.O(\z[30]_INST_0_i_225_n_0 ));
LUT6 #(
.INIT(64'hE0E0E0E0E0EFEFEF))
\z[30]_INST_0_i_226
(.I0(\z[30]_INST_0_i_236_n_0 ),
.I1(\z[30]_INST_0_i_237_n_0 ),
.I2(L1_carry_i_17_n_0),
.I3(msb1__1[46]),
.I4(L1_carry_i_15_n_0),
.I5(\z[30]_INST_0_i_238_n_0 ),
.O(\z[30]_INST_0_i_226_n_0 ));
LUT4 #(
.INIT(16'hE2FF))
\z[30]_INST_0_i_227
(.I0(_carry_n_4),
.I1(L1),
.I2(L1_carry_i_14_n_0),
.I3(msb1__1[12]),
.O(\z[30]_INST_0_i_227_n_0 ));
LUT5 #(
.INIT(32'hBFBA808A))
\z[30]_INST_0_i_228
(.I0(msb1__1[20]),
.I1(\z[30]_INST_0_i_198_n_0 ),
.I2(L1),
.I3(_carry_n_4),
.I4(msb1__1[4]),
.O(\z[30]_INST_0_i_228_n_0 ));
LUT6 #(
.INIT(64'h10105050101F5F5F))
\z[30]_INST_0_i_229
(.I0(\z[30]_INST_0_i_239_n_0 ),
.I1(msb1__1[39]),
.I2(L1_carry_i_17_n_0),
.I3(msb1__1[47]),
.I4(L1_carry_i_15_n_0),
.I5(\z[30]_INST_0_i_240_n_0 ),
.O(\z[30]_INST_0_i_229_n_0 ));
LUT6 #(
.INIT(64'h50503030505F3F3F))
\z[30]_INST_0_i_230
(.I0(\z[30]_INST_0_i_241_n_0 ),
.I1(\z[30]_INST_0_i_242_n_0 ),
.I2(L1_carry_i_17_n_0),
.I3(\z[30]_INST_0_i_243_n_0 ),
.I4(\z[30]_INST_0_i_198_n_0 ),
.I5(\z[30]_INST_0_i_244_n_0 ),
.O(\z[30]_INST_0_i_230_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h8))
\z[30]_INST_0_i_231
(.I0(L1_carry_i_15_n_0),
.I1(msb1__1[36]),
.O(\z[30]_INST_0_i_231_n_0 ));
LUT6 #(
.INIT(64'hAEAEAEAEFFFFFFAE))
\z[30]_INST_0_i_232
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_29_n_0),
.I2(L1_carry_i_28_n_0),
.I3(\z[30]_INST_0_i_245_n_0 ),
.I4(L1_carry_i_25_n_0),
.I5(L1_carry_i_24_n_0),
.O(\z[30]_INST_0_i_232_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_233
(.I0(_carry__2_n_6),
.I1(_carry__1_n_6),
.I2(_carry__3_n_6),
.I3(_carry__1_n_7),
.O(\z[30]_INST_0_i_233_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_234
(.I0(_carry__2_n_7),
.I1(L1),
.I2(_carry__3_n_5),
.I3(_carry__1_n_5),
.O(\z[30]_INST_0_i_234_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_235
(.I0(_carry__5_n_4),
.I1(_carry__3_n_7),
.I2(_carry__4_n_6),
.I3(_carry__4_n_7),
.O(\z[30]_INST_0_i_235_n_0 ));
LUT6 #(
.INIT(64'hC3CC333341441111))
\z[30]_INST_0_i_236
(.I0(msb1__1[38]),
.I1(L1_carry_i_12_n_0),
.I2(\z[30]_INST_0_i_232_n_0 ),
.I3(_carry_i_1_n_0),
.I4(L1_carry_i_9_n_0),
.I5(L1_carry_i_13_n_0),
.O(\z[30]_INST_0_i_236_n_0 ));
LUT6 #(
.INIT(64'h343344441C11CCCC))
\z[30]_INST_0_i_237
(.I0(msb1__1[22]),
.I1(L1_carry_i_12_n_0),
.I2(\z[30]_INST_0_i_232_n_0 ),
.I3(_carry_i_1_n_0),
.I4(L1_carry_i_9_n_0),
.I5(L1_carry_i_13_n_0),
.O(\z[30]_INST_0_i_237_n_0 ));
LUT6 #(
.INIT(64'h0808880820200020))
\z[30]_INST_0_i_238
(.I0(msb1__1[30]),
.I1(L1_carry_i_13_n_0),
.I2(L1_carry_i_9_n_0),
.I3(_carry_i_1_n_0),
.I4(\z[30]_INST_0_i_232_n_0 ),
.I5(L1_carry_i_12_n_0),
.O(\z[30]_INST_0_i_238_n_0 ));
LUT6 #(
.INIT(64'h0808880820200020))
\z[30]_INST_0_i_239
(.I0(msb1__1[23]),
.I1(L1_carry_i_13_n_0),
.I2(L1_carry_i_9_n_0),
.I3(_carry_i_1_n_0),
.I4(\z[30]_INST_0_i_232_n_0 ),
.I5(L1_carry_i_12_n_0),
.O(\z[30]_INST_0_i_239_n_0 ));
LUT6 #(
.INIT(64'h0800888820220000))
\z[30]_INST_0_i_240
(.I0(msb1__1[31]),
.I1(L1_carry_i_12_n_0),
.I2(\z[30]_INST_0_i_232_n_0 ),
.I3(_carry_i_1_n_0),
.I4(L1_carry_i_9_n_0),
.I5(L1_carry_i_13_n_0),
.O(\z[30]_INST_0_i_240_n_0 ));
LUT6 #(
.INIT(64'h66A6555500000000))
\z[30]_INST_0_i_241
(.I0(L1_carry_i_13_n_0),
.I1(L1_carry_i_9_n_0),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_232_n_0 ),
.I4(L1_carry_i_12_n_0),
.I5(msb1__1[21]),
.O(\z[30]_INST_0_i_241_n_0 ));
LUT6 #(
.INIT(64'h66A6555500000000))
\z[30]_INST_0_i_242
(.I0(L1_carry_i_13_n_0),
.I1(L1_carry_i_9_n_0),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_232_n_0 ),
.I4(L1_carry_i_12_n_0),
.I5(msb1__1[37]),
.O(\z[30]_INST_0_i_242_n_0 ));
LUT6 #(
.INIT(64'h66A6555500000000))
\z[30]_INST_0_i_243
(.I0(L1_carry_i_13_n_0),
.I1(L1_carry_i_9_n_0),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_232_n_0 ),
.I4(L1_carry_i_12_n_0),
.I5(msb1__1[29]),
.O(\z[30]_INST_0_i_243_n_0 ));
LUT6 #(
.INIT(64'h66A6555500000000))
\z[30]_INST_0_i_244
(.I0(L1_carry_i_13_n_0),
.I1(L1_carry_i_9_n_0),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_232_n_0 ),
.I4(L1_carry_i_12_n_0),
.I5(msb1__1[45]),
.O(\z[30]_INST_0_i_244_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFF5D5))
\z[30]_INST_0_i_245
(.I0(L1_carry_i_27_n_0),
.I1(msb1__1[32]),
.I2(\z[30]_INST_0_i_246_n_0 ),
.I3(msb1__1[33]),
.I4(msb1__1[36]),
.I5(msb1__1[37]),
.O(\z[30]_INST_0_i_245_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h1))
\z[30]_INST_0_i_246
(.I0(msb1__1[35]),
.I1(msb1__1[34]),
.O(\z[30]_INST_0_i_246_n_0 ));
LUT6 #(
.INIT(64'h4700FFFF47004700))
\z[30]_INST_0_i_29
(.I0(\z[30]_INST_0_i_94_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_96_n_0 ),
.I3(\z[30]_INST_0_i_43_n_0 ),
.I4(\z[30]_INST_0_i_97_n_0 ),
.I5(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_29_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\z[30]_INST_0_i_3
(.I0(\z[30]_INST_0_i_17_n_0 ),
.I1(\z[30]_INST_0_i_18_n_0 ),
.I2(\z[30]_INST_0_i_19_n_0 ),
.I3(\z[30]_INST_0_i_20_n_0 ),
.I4(\z[30]_INST_0_i_21_n_0 ),
.I5(\z[30]_INST_0_i_22_n_0 ),
.O(\z[30]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_30
(.I0(\z[30]_INST_0_i_98_n_0 ),
.I1(\z[30]_INST_0_i_99_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_100_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_101_n_0 ),
.O(\z[30]_INST_0_i_30_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_31
(.I0(\z[30]_INST_0_i_102_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_103_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_31_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_32
(.I0(\z[30]_INST_0_i_104_n_0 ),
.I1(\z[30]_INST_0_i_105_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_99_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_106_n_0 ),
.O(\z[30]_INST_0_i_32_n_0 ));
LUT6 #(
.INIT(64'h47FF474700FF0000))
\z[30]_INST_0_i_33
(.I0(\z[30]_INST_0_i_107_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_94_n_0 ),
.I3(\z[30]_INST_0_i_97_n_0 ),
.I4(\z[30]_INST_0_i_43_n_0 ),
.I5(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_34
(.I0(\z[30]_INST_0_i_101_n_0 ),
.I1(\z[30]_INST_0_i_104_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_98_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_99_n_0 ),
.O(\z[30]_INST_0_i_34_n_0 ));
LUT6 #(
.INIT(64'h4700FFFF47004700))
\z[30]_INST_0_i_35
(.I0(\z[30]_INST_0_i_107_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_94_n_0 ),
.I3(\z[30]_INST_0_i_43_n_0 ),
.I4(\z[30]_INST_0_i_102_n_0 ),
.I5(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_35_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_36
(.I0(\z[30]_INST_0_i_99_n_0 ),
.I1(\z[30]_INST_0_i_106_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_101_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_104_n_0 ),
.O(\z[30]_INST_0_i_36_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_37
(.I0(\z[30]_INST_0_i_106_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_108_n_0 ),
.O(\z[30]_INST_0_i_37_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_38
(.I0(\z[30]_INST_0_i_104_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_105_n_0 ),
.O(\z[30]_INST_0_i_38_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_39
(.I0(\z[30]_INST_0_i_103_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_109_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_39_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\z[30]_INST_0_i_40
(.I0(\z[30]_INST_0_i_110_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_111_n_0 ),
.I3(L1_carry_i_16_n_0),
.I4(\z[30]_INST_0_i_112_n_0 ),
.O(\z[30]_INST_0_i_40_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\z[30]_INST_0_i_41
(.I0(\z[30]_INST_0_i_108_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_113_n_0 ),
.I3(L1_carry_i_16_n_0),
.I4(\z[30]_INST_0_i_114_n_0 ),
.O(\z[30]_INST_0_i_41_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFD8))
\z[30]_INST_0_i_42
(.I0(L1),
.I1(L1_carry_i_16_n_0),
.I2(_carry_n_6),
.I3(\z[30]_INST_0_i_115_n_0 ),
.I4(\z[30]_INST_0_i_95_n_0 ),
.O(\z[30]_INST_0_i_42_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h2))
\z[30]_INST_0_i_43
(.I0(_carry_i_1_n_0),
.I1(\z[30]_INST_0_i_116_n_0 ),
.O(\z[30]_INST_0_i_43_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_44
(.I0(\z[30]_INST_0_i_105_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_110_n_0 ),
.O(\z[30]_INST_0_i_44_n_0 ));
LUT6 #(
.INIT(64'h0000040F00000404))
\z[30]_INST_0_i_45
(.I0(\z[30]_INST_0_i_117_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_95_n_0 ),
.I3(\z[30]_INST_0_i_115_n_0 ),
.I4(\z[30]_INST_0_i_118_n_0 ),
.I5(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_45_n_0 ));
LUT5 #(
.INIT(32'h10FF1010))
\z[30]_INST_0_i_46
(.I0(\z[30]_INST_0_i_95_n_0 ),
.I1(\z[30]_INST_0_i_119_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_109_n_0 ),
.I4(\z[30]_INST_0_i_43_n_0 ),
.O(\z[30]_INST_0_i_46_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_47
(.I0(\z[30]_INST_0_i_120_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_121_n_0 ),
.O(\z[30]_INST_0_i_47_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_48
(.I0(\z[30]_INST_0_i_122_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_123_n_0 ),
.O(\z[30]_INST_0_i_48_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_49
(.I0(\z[30]_INST_0_i_124_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_125_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_49_n_0 ));
LUT5 #(
.INIT(32'h115F1F5F))
\z[30]_INST_0_i_5
(.I0(\z[30]_INST_0_i_29_n_0 ),
.I1(\z[30]_INST_0_i_30_n_0 ),
.I2(\z[30]_INST_0_i_31_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_32_n_0 ),
.O(\z[30]_INST_0_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_50
(.I0(\z[30]_INST_0_i_123_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_100_n_0 ),
.O(\z[30]_INST_0_i_50_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_51
(.I0(\z[30]_INST_0_i_125_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_126_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_51_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_52
(.I0(\z[30]_INST_0_i_126_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_127_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_52_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_53
(.I0(\z[30]_INST_0_i_121_n_0 ),
.I1(\z[30]_INST_0_i_98_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_123_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_100_n_0 ),
.O(\z[30]_INST_0_i_53_n_0 ));
LUT6 #(
.INIT(64'h47FF474700FF0000))
\z[30]_INST_0_i_54
(.I0(\z[30]_INST_0_i_94_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_96_n_0 ),
.I3(\z[30]_INST_0_i_127_n_0 ),
.I4(\z[30]_INST_0_i_43_n_0 ),
.I5(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_54_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_55
(.I0(\z[30]_INST_0_i_100_n_0 ),
.I1(\z[30]_INST_0_i_101_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_121_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_98_n_0 ),
.O(\z[30]_INST_0_i_55_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_56
(.I0(\z[30]_INST_0_i_128_n_0 ),
.I1(\z[30]_INST_0_i_129_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_130_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_131_n_0 ),
.O(\z[30]_INST_0_i_56_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h1))
\z[30]_INST_0_i_57
(.I0(_carry_i_1_n_0),
.I1(\z[30]_INST_0_i_116_n_0 ),
.O(\z[30]_INST_0_i_57_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_58
(.I0(\z[30]_INST_0_i_132_n_0 ),
.I1(\z[30]_INST_0_i_133_n_0 ),
.I2(\z[30]_INST_0_i_95_n_0 ),
.I3(\z[30]_INST_0_i_134_n_0 ),
.I4(\z[30]_INST_0_i_118_n_0 ),
.I5(\z[30]_INST_0_i_135_n_0 ),
.O(\z[30]_INST_0_i_58_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_59
(.I0(\z[30]_INST_0_i_136_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_137_n_0 ),
.O(\z[30]_INST_0_i_59_n_0 ));
LUT5 #(
.INIT(32'h115F1F5F))
\z[30]_INST_0_i_6
(.I0(\z[30]_INST_0_i_33_n_0 ),
.I1(\z[30]_INST_0_i_34_n_0 ),
.I2(\z[30]_INST_0_i_35_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_36_n_0 ),
.O(\z[30]_INST_0_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\z[30]_INST_0_i_60
(.I0(\z[30]_INST_0_i_138_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_139_n_0 ),
.I3(_carry_i_10_n_0),
.I4(\z[30]_INST_0_i_122_n_0 ),
.O(\z[30]_INST_0_i_60_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\z[30]_INST_0_i_61
(.I0(\z[30]_INST_0_i_140_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_141_n_0 ),
.I3(_carry_i_10_n_0),
.I4(\z[30]_INST_0_i_142_n_0 ),
.O(\z[30]_INST_0_i_61_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_62
(.I0(\z[30]_INST_0_i_58_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_143_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_62_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_63
(.I0(\z[30]_INST_0_i_143_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_144_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_63_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_64
(.I0(\z[30]_INST_0_i_142_n_0 ),
.I1(\z[30]_INST_0_i_120_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_145_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_122_n_0 ),
.O(\z[30]_INST_0_i_64_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_65
(.I0(\z[30]_INST_0_i_144_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_124_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_65_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_66
(.I0(\z[30]_INST_0_i_122_n_0 ),
.I1(\z[30]_INST_0_i_123_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_142_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_120_n_0 ),
.O(\z[30]_INST_0_i_66_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_67
(.I0(\z[30]_INST_0_i_146_n_0 ),
.I1(\z[30]_INST_0_i_147_n_0 ),
.I2(\z[30]_INST_0_i_95_n_0 ),
.I3(\z[30]_INST_0_i_148_n_0 ),
.I4(\z[30]_INST_0_i_118_n_0 ),
.I5(\z[30]_INST_0_i_149_n_0 ),
.O(\z[30]_INST_0_i_67_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_68
(.I0(\z[30]_INST_0_i_150_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_151_n_0 ),
.O(\z[30]_INST_0_i_68_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_69
(.I0(\z[30]_INST_0_i_152_n_0 ),
.I1(\z[30]_INST_0_i_153_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_154_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_155_n_0 ),
.O(\z[30]_INST_0_i_69_n_0 ));
LUT5 #(
.INIT(32'hFFFF8A80))
\z[30]_INST_0_i_7
(.I0(L1),
.I1(\z[30]_INST_0_i_37_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_38_n_0 ),
.I4(\z[30]_INST_0_i_39_n_0 ),
.O(sel0[3]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_70
(.I0(\z[30]_INST_0_i_137_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_156_n_0 ),
.O(\z[30]_INST_0_i_70_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_71
(.I0(\z[30]_INST_0_i_155_n_0 ),
.I1(\z[30]_INST_0_i_130_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_152_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_153_n_0 ),
.O(\z[30]_INST_0_i_71_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_72
(.I0(\z[30]_INST_0_i_157_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_150_n_0 ),
.O(\z[30]_INST_0_i_72_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_73
(.I0(\z[30]_INST_0_i_153_n_0 ),
.I1(\z[30]_INST_0_i_128_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_155_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_130_n_0 ),
.O(\z[30]_INST_0_i_73_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_74
(.I0(\z[30]_INST_0_i_130_n_0 ),
.I1(\z[30]_INST_0_i_131_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_153_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_128_n_0 ),
.O(\z[30]_INST_0_i_74_n_0 ));
LUT6 #(
.INIT(64'h000002A2AAAA02A2))
\z[30]_INST_0_i_75
(.I0(L1),
.I1(\z[30]_INST_0_i_158_n_0 ),
.I2(_carry_i_10_n_0),
.I3(\z[30]_INST_0_i_159_n_0 ),
.I4(_carry_i_1_n_0),
.I5(\z[30]_INST_0_i_160_n_0 ),
.O(\z[30]_INST_0_i_75_n_0 ));
LUT6 #(
.INIT(64'h4C4C4C4040404C40))
\z[30]_INST_0_i_76
(.I0(\z[30]_INST_0_i_161_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_95_n_0 ),
.I3(\z[30]_INST_0_i_162_n_0 ),
.I4(\z[30]_INST_0_i_118_n_0 ),
.I5(\z[30]_INST_0_i_163_n_0 ),
.O(\z[30]_INST_0_i_76_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'hB))
\z[30]_INST_0_i_77
(.I0(\z[30]_INST_0_i_81_n_0 ),
.I1(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_77_n_0 ));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\z[30]_INST_0_i_78
(.I0(L1),
.I1(\z[30]_INST_0_i_164_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_155_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_154_n_0 ),
.O(\z[30]_INST_0_i_78_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'h2))
\z[30]_INST_0_i_79
(.I0(\z[30]_INST_0_i_57_n_0 ),
.I1(\z[30]_INST_0_i_67_n_0 ),
.O(\z[30]_INST_0_i_79_n_0 ));
LUT6 #(
.INIT(64'h8A80FFFF8A808A80))
\z[30]_INST_0_i_8
(.I0(L1),
.I1(\z[30]_INST_0_i_40_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_41_n_0 ),
.I4(\z[30]_INST_0_i_42_n_0 ),
.I5(\z[30]_INST_0_i_43_n_0 ),
.O(sel0[0]));
LUT2 #(
.INIT(4'hB))
\z[30]_INST_0_i_80
(.I0(\z[30]_INST_0_i_82_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.O(\z[30]_INST_0_i_80_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_81
(.I0(\z[30]_INST_0_i_148_n_0 ),
.I1(\z[30]_INST_0_i_149_n_0 ),
.I2(\z[30]_INST_0_i_95_n_0 ),
.I3(\z[30]_INST_0_i_147_n_0 ),
.I4(\z[30]_INST_0_i_118_n_0 ),
.I5(\z[30]_INST_0_i_165_n_0 ),
.O(\z[30]_INST_0_i_81_n_0 ));
LUT6 #(
.INIT(64'hCFC05F5FCFC05050))
\z[30]_INST_0_i_82
(.I0(\z[30]_INST_0_i_163_n_0 ),
.I1(\z[30]_INST_0_i_135_n_0 ),
.I2(\z[30]_INST_0_i_95_n_0 ),
.I3(\z[30]_INST_0_i_166_n_0 ),
.I4(\z[30]_INST_0_i_118_n_0 ),
.I5(\z[30]_INST_0_i_167_n_0 ),
.O(\z[30]_INST_0_i_82_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_83
(.I0(\z[30]_INST_0_i_158_n_0 ),
.I1(\z[30]_INST_0_i_152_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_168_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_154_n_0 ),
.O(\z[30]_INST_0_i_83_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[30]_INST_0_i_9
(.I0(\z[30]_INST_0_i_41_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[30]_INST_0_i_44_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_45_n_0 ),
.O(\z[30]_INST_0_i_9_n_0 ));
LUT5 #(
.INIT(32'hFFFFF4F7))
\z[30]_INST_0_i_94
(.I0(msb1__1[1]),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(\z[30]_INST_0_i_169_n_0 ),
.I3(msb1__1[5]),
.I4(\z[30]_INST_0_i_170_n_0 ),
.O(\z[30]_INST_0_i_94_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hCA))
\z[30]_INST_0_i_95
(.I0(_carry_n_7),
.I1(_carry_i_10_n_0),
.I2(L1),
.O(\z[30]_INST_0_i_95_n_0 ));
LUT5 #(
.INIT(32'hFFFFF4F7))
\z[30]_INST_0_i_96
(.I0(msb1__1[3]),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(\z[30]_INST_0_i_170_n_0 ),
.I3(msb1__1[7]),
.I4(\z[30]_INST_0_i_169_n_0 ),
.O(\z[30]_INST_0_i_96_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_97
(.I0(\z[30]_INST_0_i_171_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_172_n_0 ),
.O(\z[30]_INST_0_i_97_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_98
(.I0(\z[30]_INST_0_i_173_n_0 ),
.I1(\z[30]_INST_0_i_174_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_175_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_176_n_0 ),
.O(\z[30]_INST_0_i_98_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_99
(.I0(\z[30]_INST_0_i_177_n_0 ),
.I1(\z[30]_INST_0_i_178_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_179_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_180_n_0 ),
.O(\z[30]_INST_0_i_99_n_0 ));
CARRY4 \z[3]_INST_0_i_1
(.CI(1'b0),
.CO({\z[3]_INST_0_i_1_n_0 ,\z[3]_INST_0_i_1_n_1 ,\z[3]_INST_0_i_1_n_2 ,\z[3]_INST_0_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,sel0[0]}),
.O(z_mantissa[3:0]),
.S({\z[3]_INST_0_i_2_n_0 ,\z[3]_INST_0_i_3_n_0 ,sel0[1],\z[3]_INST_0_i_5_n_0 }));
LUT5 #(
.INIT(32'hFFFF8A80))
\z[3]_INST_0_i_2
(.I0(L1),
.I1(\z[30]_INST_0_i_37_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_38_n_0 ),
.I4(\z[30]_INST_0_i_39_n_0 ),
.O(\z[3]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFF8A80))
\z[3]_INST_0_i_3
(.I0(L1),
.I1(\z[30]_INST_0_i_44_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_37_n_0 ),
.I4(\z[30]_INST_0_i_46_n_0 ),
.O(\z[3]_INST_0_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\z[3]_INST_0_i_4
(.I0(\z[30]_INST_0_i_9_n_0 ),
.O(sel0[1]));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAA9AA))
\z[3]_INST_0_i_5
(.I0(sel0[0]),
.I1(\z[30]_INST_0_i_3_n_0 ),
.I2(\z[3]_INST_0_i_6_n_0 ),
.I3(\z[3]_INST_0_i_7_n_0 ),
.I4(\z[3]_INST_0_i_8_n_0 ),
.I5(\z[3]_INST_0_i_9_n_0 ),
.O(\z[3]_INST_0_i_5_n_0 ));
LUT4 #(
.INIT(16'hFFF7))
\z[3]_INST_0_i_6
(.I0(sel0[0]),
.I1(sel0[2]),
.I2(\z[7]_INST_0_i_8_n_0 ),
.I3(\z[7]_INST_0_i_6_n_0 ),
.O(\z[3]_INST_0_i_6_n_0 ));
LUT4 #(
.INIT(16'h0004))
\z[3]_INST_0_i_7
(.I0(\z[7]_INST_0_i_9_n_0 ),
.I1(sel0[10]),
.I2(\z[30]_INST_0_i_11_n_0 ),
.I3(\z[30]_INST_0_i_15_n_0 ),
.O(\z[3]_INST_0_i_7_n_0 ));
LUT4 #(
.INIT(16'hFFEF))
\z[3]_INST_0_i_8
(.I0(\z[15]_INST_0_i_7_n_0 ),
.I1(\z[15]_INST_0_i_6_n_0 ),
.I2(sel0[3]),
.I3(\z[7]_INST_0_i_7_n_0 ),
.O(\z[3]_INST_0_i_8_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[3]_INST_0_i_9
(.I0(\z[30]_INST_0_i_9_n_0 ),
.I1(\z[11]_INST_0_i_6_n_0 ),
.I2(\z[11]_INST_0_i_7_n_0 ),
.I3(\z[30]_INST_0_i_14_n_0 ),
.O(\z[3]_INST_0_i_9_n_0 ));
CARRY4 \z[7]_INST_0_i_1
(.CI(\z[3]_INST_0_i_1_n_0 ),
.CO({\z[7]_INST_0_i_1_n_0 ,\z[7]_INST_0_i_1_n_1 ,\z[7]_INST_0_i_1_n_2 ,\z[7]_INST_0_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z_mantissa[7:4]),
.S(sel0[7:4]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\z[7]_INST_0_i_10
(.I0(\z[30]_INST_0_i_98_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_99_n_0 ),
.O(\z[7]_INST_0_i_10_n_0 ));
LUT3 #(
.INIT(8'hB8))
\z[7]_INST_0_i_11
(.I0(\z[30]_INST_0_i_101_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_104_n_0 ),
.O(\z[7]_INST_0_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\z[7]_INST_0_i_12
(.I0(\z[30]_INST_0_i_99_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_106_n_0 ),
.O(\z[7]_INST_0_i_12_n_0 ));
LUT1 #(
.INIT(2'h1))
\z[7]_INST_0_i_2
(.I0(\z[7]_INST_0_i_6_n_0 ),
.O(sel0[7]));
LUT1 #(
.INIT(2'h1))
\z[7]_INST_0_i_3
(.I0(\z[7]_INST_0_i_7_n_0 ),
.O(sel0[6]));
LUT1 #(
.INIT(2'h1))
\z[7]_INST_0_i_4
(.I0(\z[7]_INST_0_i_8_n_0 ),
.O(sel0[5]));
LUT1 #(
.INIT(2'h1))
\z[7]_INST_0_i_5
(.I0(\z[7]_INST_0_i_9_n_0 ),
.O(sel0[4]));
LUT5 #(
.INIT(32'h000047FF))
\z[7]_INST_0_i_6
(.I0(\z[7]_INST_0_i_10_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[11]_INST_0_i_9_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_29_n_0 ),
.O(\z[7]_INST_0_i_6_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[7]_INST_0_i_7
(.I0(\z[7]_INST_0_i_11_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[7]_INST_0_i_10_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_33_n_0 ),
.O(\z[7]_INST_0_i_7_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[7]_INST_0_i_8
(.I0(\z[7]_INST_0_i_12_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[7]_INST_0_i_11_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_35_n_0 ),
.O(\z[7]_INST_0_i_8_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[7]_INST_0_i_9
(.I0(\z[30]_INST_0_i_38_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[7]_INST_0_i_12_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_31_n_0 ),
.O(\z[7]_INST_0_i_9_n_0 ));
CARRY4 z_exponent0__0_carry
(.CI(1'b0),
.CO({z_exponent0__0_carry_n_0,z_exponent0__0_carry_n_1,z_exponent0__0_carry_n_2,z_exponent0__0_carry_n_3}),
.CYINIT(1'b1),
.DI({z_exponent0__0_carry_i_1_n_0,z_exponent0__0_carry_i_2_n_0,z_exponent0__0_carry_i_3_n_0,1'b1}),
.O(data0[3:0]),
.S({z_exponent0__0_carry_i_4_n_0,z_exponent0__0_carry_i_5_n_0,z_exponent0__0_carry_i_6_n_0,z_exponent0__0_carry_i_7_n_0}));
CARRY4 z_exponent0__0_carry__0
(.CI(z_exponent0__0_carry_n_0),
.CO({NLW_z_exponent0__0_carry__0_CO_UNCONNECTED[3],z_exponent0__0_carry__0_n_1,z_exponent0__0_carry__0_n_2,z_exponent0__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,z_exponent0__0_carry__0_i_1_n_0,z_exponent0__0_carry__0_i_2_n_0,z_exponent0__0_carry__0_i_3_n_0}),
.O(data0[7:4]),
.S({z_exponent0__0_carry__0_i_4_n_0,z_exponent0__0_carry__0_i_5_n_0,z_exponent0__0_carry__0_i_6_n_0,z_exponent0__0_carry__0_i_7_n_0}));
LUT5 #(
.INIT(32'hFFA9A900))
z_exponent0__0_carry__0_i_1
(.I0(L1_carry_i_13_n_0),
.I1(z_exponent0__0_carry__0_i_8_n_0),
.I2(L1_carry_i_12_n_0),
.I3(y[28]),
.I4(x[28]),
.O(z_exponent0__0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair3" *)
LUT4 #(
.INIT(16'hF990))
z_exponent0__0_carry__0_i_2
(.I0(L1_carry_i_12_n_0),
.I1(z_exponent0__0_carry__0_i_8_n_0),
.I2(y[27]),
.I3(x[27]),
.O(z_exponent0__0_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'hFF1E1E00))
z_exponent0__0_carry__0_i_3
(.I0(L1_carry_i_10_n_0),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_9_n_0),
.I3(y[26]),
.I4(x[26]),
.O(z_exponent0__0_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h6999699969999996))
z_exponent0__0_carry__0_i_4
(.I0(x[30]),
.I1(y[30]),
.I2(x[29]),
.I3(y[29]),
.I4(msb1__1[47]),
.I5(msb1__1[46]),
.O(z_exponent0__0_carry__0_i_4_n_0));
LUT5 #(
.INIT(32'h96969669))
z_exponent0__0_carry__0_i_5
(.I0(z_exponent0__0_carry__0_i_1_n_0),
.I1(y[29]),
.I2(x[29]),
.I3(msb1__1[46]),
.I4(msb1__1[47]),
.O(z_exponent0__0_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h56A9A956A95656A9))
z_exponent0__0_carry__0_i_6
(.I0(L1_carry_i_13_n_0),
.I1(z_exponent0__0_carry__0_i_8_n_0),
.I2(L1_carry_i_12_n_0),
.I3(z_exponent0__0_carry__0_i_2_n_0),
.I4(y[28]),
.I5(x[28]),
.O(z_exponent0__0_carry__0_i_6_n_0));
LUT5 #(
.INIT(32'h69969669))
z_exponent0__0_carry__0_i_7
(.I0(L1_carry_i_12_n_0),
.I1(z_exponent0__0_carry__0_i_8_n_0),
.I2(z_exponent0__0_carry__0_i_3_n_0),
.I3(x[27]),
.I4(y[27]),
.O(z_exponent0__0_carry__0_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h01))
z_exponent0__0_carry__0_i_8
(.I0(L1_carry_i_9_n_0),
.I1(L1_carry_i_10_n_0),
.I2(L1_carry_i_11_n_0),
.O(z_exponent0__0_carry__0_i_8_n_0));
(* HLUTNM = "lutpair2" *)
LUT4 #(
.INIT(16'hF660))
z_exponent0__0_carry_i_1
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_10_n_0),
.I2(y[25]),
.I3(x[25]),
.O(z_exponent0__0_carry_i_1_n_0));
(* HLUTNM = "lutpair1" *)
LUT3 #(
.INIT(8'hE8))
z_exponent0__0_carry_i_2
(.I0(y[24]),
.I1(x[24]),
.I2(L1_carry_i_10_n_0),
.O(z_exponent0__0_carry_i_2_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'hE8))
z_exponent0__0_carry_i_3
(.I0(x[23]),
.I1(y[23]),
.I2(_carry_i_1_n_0),
.O(z_exponent0__0_carry_i_3_n_0));
LUT6 #(
.INIT(64'hE11E1EE11EE1E11E))
z_exponent0__0_carry_i_4
(.I0(L1_carry_i_10_n_0),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_9_n_0),
.I3(z_exponent0__0_carry_i_1_n_0),
.I4(y[26]),
.I5(x[26]),
.O(z_exponent0__0_carry_i_4_n_0));
LUT5 #(
.INIT(32'h96696996))
z_exponent0__0_carry_i_5
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_10_n_0),
.I2(z_exponent0__0_carry_i_2_n_0),
.I3(y[25]),
.I4(x[25]),
.O(z_exponent0__0_carry_i_5_n_0));
LUT4 #(
.INIT(16'h6996))
z_exponent0__0_carry_i_6
(.I0(y[24]),
.I1(L1_carry_i_10_n_0),
.I2(x[24]),
.I3(z_exponent0__0_carry_i_3_n_0),
.O(z_exponent0__0_carry_i_6_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'h69))
z_exponent0__0_carry_i_7
(.I0(x[23]),
.I1(y[23]),
.I2(_carry_i_1_n_0),
.O(z_exponent0__0_carry_i_7_n_0));
CARRY4 z_exponent1_carry
(.CI(1'b0),
.CO({z_exponent1_carry_n_0,z_exponent1_carry_n_1,z_exponent1_carry_n_2,z_exponent1_carry_n_3}),
.CYINIT(1'b0),
.DI({z_exponent0__0_carry_i_1_n_0,z_exponent0__0_carry_i_2_n_0,z_exponent1_carry_i_1__0_n_0,x[23]}),
.O(data1[3:0]),
.S({z_exponent1_carry_i_2__0_n_0,z_exponent1_carry_i_3__0_n_0,z_exponent1_carry_i_4_n_0,z_exponent1_carry_i_5_n_0}));
CARRY4 z_exponent1_carry__0
(.CI(z_exponent1_carry_n_0),
.CO({NLW_z_exponent1_carry__0_CO_UNCONNECTED[3],z_exponent1_carry__0_n_1,z_exponent1_carry__0_n_2,z_exponent1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,z_exponent0__0_carry__0_i_1_n_0,z_exponent0__0_carry__0_i_2_n_0,z_exponent0__0_carry__0_i_3_n_0}),
.O(data1[7:4]),
.S({z_exponent1_carry_i_1_n_0,z_exponent1_carry_i_2_n_0,z_exponent1_carry_i_3_n_0,z_exponent1_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h6999699969999996))
z_exponent1_carry_i_1
(.I0(x[30]),
.I1(y[30]),
.I2(x[29]),
.I3(y[29]),
.I4(msb1__1[47]),
.I5(msb1__1[46]),
.O(z_exponent1_carry_i_1_n_0));
(* HLUTNM = "lutpair4" *)
LUT2 #(
.INIT(4'hE))
z_exponent1_carry_i_1__0
(.I0(y[23]),
.I1(_carry_i_1_n_0),
.O(z_exponent1_carry_i_1__0_n_0));
LUT5 #(
.INIT(32'h96969669))
z_exponent1_carry_i_2
(.I0(z_exponent0__0_carry__0_i_1_n_0),
.I1(y[29]),
.I2(x[29]),
.I3(msb1__1[46]),
.I4(msb1__1[47]),
.O(z_exponent1_carry_i_2_n_0));
LUT6 #(
.INIT(64'hE11E1EE11EE1E11E))
z_exponent1_carry_i_2__0
(.I0(L1_carry_i_10_n_0),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_9_n_0),
.I3(z_exponent0__0_carry_i_1_n_0),
.I4(y[26]),
.I5(x[26]),
.O(z_exponent1_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h56A9A956A95656A9))
z_exponent1_carry_i_3
(.I0(L1_carry_i_13_n_0),
.I1(z_exponent0__0_carry__0_i_8_n_0),
.I2(L1_carry_i_12_n_0),
.I3(z_exponent0__0_carry__0_i_2_n_0),
.I4(y[28]),
.I5(x[28]),
.O(z_exponent1_carry_i_3_n_0));
(* HLUTNM = "lutpair2" *)
LUT5 #(
.INIT(32'h96696996))
z_exponent1_carry_i_3__0
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_10_n_0),
.I2(y[25]),
.I3(x[25]),
.I4(z_exponent0__0_carry_i_2_n_0),
.O(z_exponent1_carry_i_3__0_n_0));
(* HLUTNM = "lutpair1" *)
LUT4 #(
.INIT(16'h6996))
z_exponent1_carry_i_4
(.I0(y[24]),
.I1(x[24]),
.I2(L1_carry_i_10_n_0),
.I3(z_exponent1_carry_i_1__0_n_0),
.O(z_exponent1_carry_i_4_n_0));
(* HLUTNM = "lutpair3" *)
LUT5 #(
.INIT(32'h69969669))
z_exponent1_carry_i_4__0
(.I0(L1_carry_i_12_n_0),
.I1(z_exponent0__0_carry__0_i_8_n_0),
.I2(y[27]),
.I3(x[27]),
.I4(z_exponent0__0_carry__0_i_3_n_0),
.O(z_exponent1_carry_i_4__0_n_0));
(* HLUTNM = "lutpair4" *)
LUT3 #(
.INIT(8'h69))
z_exponent1_carry_i_5
(.I0(y[23]),
.I1(_carry_i_1_n_0),
.I2(x[23]),
.O(z_exponent1_carry_i_5_n_0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_TB_V
`define SKY130_FD_SC_HDLL__NOR4_TB_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hdll__nor4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_dir_in.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_dir_in(/*AUTOARG*/
// Outputs
lkup_wr_data_c5, rddata_out_c6, so,
// Inputs
lkup_wr_data_c4, rd_data1_out_c5, rd_data2_out_c5, rd_enable1_c5,
rclk, si, se, sehold
);
output [32:0] lkup_wr_data_c5; // Top 3 bits per bit pitch
output [31:0] rddata_out_c6;
output so;
input [32:0] lkup_wr_data_c4;
input [31:0] rd_data1_out_c5; // TOp 3 bits per bit pitch
input [31:0] rd_data2_out_c5; // Down 3 bits per bit pitch
input rd_enable1_c5; // Right
input rclk;
input si, se;
input sehold;
wire [31:0] rddata_out_c5;
wire clk_en;
// USE A MUX2 FLOP to replace sehold_mux & ff_lkup_wr_data_c5
//mux2ds #(33) sehold_mux(.dout (lkup_wr_data_c4_in[32:0]) ,
//.in0(lkup_wr_data_c5[32:0]), .in1(lkup_wr_data_c4[32:0]),
//.sel0(sehold), .sel1(~sehold));
clken_buf clk_buf (.clk(clk_en), .rclk(rclk), .enb_l(sehold), .tmb_l(~se));
// bits {0,1,2 } {3,4,5}.... occupy the same bit pitches
dff_s #(33) ff_lkup_wr_data_c5 // Use an 8X flop. no buffer following the flop.
(.q (lkup_wr_data_c5[32:0]),
.din (lkup_wr_data_c4[32:0]),
.clk (clk_en),
.se (se), .si (), .so ()
) ;
// bits {0,1,2 } {3,4,5}.... occupy the same bit pitches
mux2ds #(32) mux_rddata_out_c5(.dout (rddata_out_c5[31:0]) ,
.in0(rd_data1_out_c5[31:0]), .in1(rd_data2_out_c5[31:0]),
.sel0(rd_enable1_c5), .sel1(~rd_enable1_c5));
dff_s #(32) ff_rddata_out_c6 // Use an 16X buffer following a 1X mx flop.
(.q (rddata_out_c6[31:0]),
.din (rddata_out_c5[31:0]),
.clk (rclk),
.se (se), .si (), .so ()
) ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O2BB2A_FUNCTIONAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2bb2a (
VPWR,
VGND,
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2A_FUNCTIONAL_PP_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:11:15 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57,
n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132,
n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148;
OAI21X2TS U46 ( .A0(n113), .A1(n112), .B0(n46), .Y(res[16]) );
NAND2XLTS U47 ( .A(n68), .B(n117), .Y(n119) );
NAND2XLTS U48 ( .A(n39), .B(n114), .Y(n116) );
NAND2X4TS U49 ( .A(n113), .B(n71), .Y(n46) );
CLKBUFX2TS U50 ( .A(n137), .Y(n33) );
OR2X2TS U51 ( .A(n78), .B(in1[14]), .Y(n39) );
OAI21X1TS U52 ( .A0(n76), .A1(in2[14]), .B0(add_sub), .Y(n74) );
INVX4TS U53 ( .A(n34), .Y(n48) );
NAND2X1TS U54 ( .A(n76), .B(add_sub), .Y(n77) );
CLKXOR2X2TS U55 ( .A(n80), .B(in2[13]), .Y(n81) );
NOR2XLTS U56 ( .A(n79), .B(n101), .Y(n80) );
NAND2XLTS U57 ( .A(n82), .B(add_sub), .Y(n83) );
NAND2BX2TS U58 ( .AN(in2[13]), .B(n79), .Y(n76) );
NOR2X2TS U59 ( .A(n82), .B(in2[12]), .Y(n79) );
NAND2X1TS U60 ( .A(n86), .B(add_sub), .Y(n87) );
NAND2X2TS U61 ( .A(in1[8]), .B(n70), .Y(n31) );
NAND2BX2TS U62 ( .AN(in2[9]), .B(n102), .Y(n86) );
NOR2X4TS U63 ( .A(n99), .B(in2[8]), .Y(n102) );
NAND2X1TS U64 ( .A(n99), .B(add_sub), .Y(n100) );
NAND2X4TS U65 ( .A(n127), .B(in1[6]), .Y(n97) );
NOR2X6TS U66 ( .A(n95), .B(in2[6]), .Y(n88) );
OR2X6TS U67 ( .A(n137), .B(in1[5]), .Y(n69) );
NAND2X4TS U68 ( .A(n95), .B(add_sub), .Y(n96) );
INVX3TS U69 ( .A(n67), .Y(n54) );
INVX6TS U70 ( .A(n133), .Y(n94) );
INVX8TS U71 ( .A(in2[3]), .Y(n62) );
INVX6TS U72 ( .A(in2[2]), .Y(n63) );
INVX6TS U73 ( .A(in2[1]), .Y(n64) );
INVX6TS U74 ( .A(in2[0]), .Y(n65) );
NOR2XLTS U75 ( .A(n102), .B(n101), .Y(n103) );
NAND2X1TS U76 ( .A(add_sub), .B(in2[0]), .Y(n130) );
OR2X4TS U77 ( .A(n92), .B(n101), .Y(n93) );
NOR2XLTS U78 ( .A(n84), .B(n101), .Y(n85) );
ADDHXLTS U79 ( .A(in2[0]), .B(in1[0]), .CO(n140), .S(res[0]) );
NAND2X4TS U80 ( .A(n50), .B(n48), .Y(n47) );
XNOR2X2TS U81 ( .A(n83), .B(in2[12]), .Y(n109) );
NAND2BX4TS U82 ( .AN(in2[11]), .B(n84), .Y(n82) );
XNOR2X2TS U83 ( .A(n87), .B(in2[10]), .Y(n111) );
NOR2X4TS U84 ( .A(n86), .B(in2[10]), .Y(n84) );
NOR2X4TS U85 ( .A(in2[4]), .B(in2[3]), .Y(n72) );
XOR2X1TS U86 ( .A(n116), .B(n115), .Y(res[14]) );
AND2X2TS U87 ( .A(n71), .B(n112), .Y(n38) );
OR2X4TS U88 ( .A(n75), .B(in1[15]), .Y(n71) );
NAND2X2TS U89 ( .A(n75), .B(in1[15]), .Y(n112) );
OR2X4TS U90 ( .A(n81), .B(in1[13]), .Y(n68) );
XOR2X1TS U91 ( .A(n129), .B(n128), .Y(res[6]) );
XOR2X1TS U92 ( .A(n139), .B(n138), .Y(res[5]) );
OAI21X1TS U93 ( .A0(n33), .A1(in1[5]), .B0(n126), .Y(n129) );
NAND2BX1TS U94 ( .AN(n132), .B(n131), .Y(n134) );
OAI211X1TS U95 ( .A0(in1[2]), .A1(n143), .B0(in1[1]), .C0(n141), .Y(n132) );
OAI21X1TS U96 ( .A0(in2[0]), .A1(in2[1]), .B0(add_sub), .Y(n124) );
NAND2X8TS U97 ( .A(n47), .B(n49), .Y(n113) );
NAND2X8TS U98 ( .A(n44), .B(n121), .Y(n70) );
XOR3X1TS U99 ( .A(n70), .B(in1[8]), .C(n120), .Y(res[8]) );
NAND2X2TS U100 ( .A(n120), .B(n70), .Y(n30) );
NAND2X2TS U101 ( .A(in1[8]), .B(n120), .Y(n32) );
NAND3X6TS U102 ( .A(n31), .B(n30), .C(n32), .Y(n105) );
XNOR2X4TS U103 ( .A(n100), .B(in2[8]), .Y(n120) );
NOR2X4TS U104 ( .A(n101), .B(in2[4]), .Y(n60) );
AND2X8TS U105 ( .A(n145), .B(in1[3]), .Y(n66) );
NAND2X8TS U106 ( .A(n90), .B(n73), .Y(n95) );
AND2X6TS U107 ( .A(n92), .B(n72), .Y(n90) );
NOR2X2TS U108 ( .A(n88), .B(n101), .Y(n89) );
XNOR2X2TS U109 ( .A(n74), .B(in2[15]), .Y(n75) );
NOR2X4TS U110 ( .A(n51), .B(n114), .Y(n50) );
NAND2BX4TS U111 ( .AN(in2[7]), .B(n88), .Y(n99) );
NAND2X2TS U112 ( .A(n101), .B(in2[4]), .Y(n59) );
NAND2X6TS U113 ( .A(n58), .B(in2[4]), .Y(n57) );
NAND2X4TS U114 ( .A(n61), .B(n60), .Y(n56) );
AO22XLTS U115 ( .A0(n148), .A1(in1[4]), .B0(n145), .B1(in1[3]), .Y(n125) );
INVX4TS U116 ( .A(n61), .Y(n58) );
XNOR2X2TS U117 ( .A(n77), .B(in2[14]), .Y(n78) );
INVX12TS U118 ( .A(add_sub), .Y(n101) );
NAND2X2TS U119 ( .A(n78), .B(in1[14]), .Y(n114) );
XOR2XLTS U120 ( .A(n148), .B(n147), .Y(res[4]) );
XNOR2X1TS U121 ( .A(n127), .B(in1[6]), .Y(n128) );
NAND2X1TS U122 ( .A(n35), .B(n121), .Y(n123) );
INVX2TS U123 ( .A(in1[9]), .Y(n43) );
XNOR2X1TS U124 ( .A(n33), .B(n136), .Y(n138) );
OR2X1TS U125 ( .A(n145), .B(in1[3]), .Y(n131) );
NOR2X2TS U126 ( .A(n34), .B(n51), .Y(n115) );
NOR2X4TS U127 ( .A(n101), .B(n90), .Y(n91) );
XNOR2X1TS U128 ( .A(n105), .B(n42), .Y(res[9]) );
AND2X8TS U129 ( .A(n118), .B(n68), .Y(n34) );
OR2X4TS U130 ( .A(in1[7]), .B(n98), .Y(n35) );
NAND2X2TS U131 ( .A(n81), .B(in1[13]), .Y(n117) );
OR2X4TS U132 ( .A(n127), .B(in1[6]), .Y(n36) );
NAND2X2TS U133 ( .A(n137), .B(in1[5]), .Y(n37) );
NAND2X2TS U134 ( .A(n98), .B(in1[7]), .Y(n121) );
XOR2X1TS U135 ( .A(n104), .B(n43), .Y(n42) );
CLKXOR2X2TS U136 ( .A(n103), .B(in2[9]), .Y(n104) );
AOI31X1TS U137 ( .A0(n143), .A1(in1[2]), .A2(n131), .B0(n125), .Y(n135) );
XNOR2X2TS U138 ( .A(n124), .B(in2[2]), .Y(n143) );
NAND2X8TS U139 ( .A(n40), .B(n37), .Y(n52) );
NAND2X8TS U140 ( .A(n69), .B(n53), .Y(n40) );
XOR2X2TS U141 ( .A(n113), .B(n38), .Y(res[15]) );
OAI2BB1X4TS U142 ( .A0N(in1[9]), .A1N(n105), .B0(n41), .Y(n110) );
OAI21X4TS U143 ( .A0(n105), .A1(in1[9]), .B0(n104), .Y(n41) );
NAND2X8TS U144 ( .A(n122), .B(n35), .Y(n44) );
XOR2X4TS U145 ( .A(n89), .B(in2[7]), .Y(n98) );
NAND2X8TS U146 ( .A(n45), .B(n97), .Y(n122) );
NAND2X8TS U147 ( .A(n52), .B(n36), .Y(n45) );
NOR3X8TS U148 ( .A(in2[1]), .B(in2[0]), .C(in2[2]), .Y(n92) );
NOR2X8TS U149 ( .A(n118), .B(n117), .Y(n51) );
OAI21X4TS U150 ( .A0(n34), .A1(n51), .B0(n39), .Y(n49) );
NAND2X8TS U151 ( .A(n55), .B(n54), .Y(n53) );
NAND2X8TS U152 ( .A(n66), .B(n94), .Y(n55) );
NAND3X8TS U153 ( .A(n57), .B(n56), .C(n59), .Y(n148) );
NOR2X8TS U154 ( .A(n148), .B(in1[4]), .Y(n133) );
NAND4X8TS U155 ( .A(n65), .B(n64), .C(n63), .D(n62), .Y(n61) );
XNOR2X1TS U156 ( .A(n119), .B(n118), .Y(res[13]) );
XNOR2X1TS U157 ( .A(n123), .B(n122), .Y(res[7]) );
XNOR2X4TS U158 ( .A(n93), .B(in2[3]), .Y(n145) );
XNOR2X4TS U159 ( .A(n96), .B(in2[6]), .Y(n127) );
AND2X4TS U160 ( .A(n148), .B(in1[4]), .Y(n67) );
INVX2TS U161 ( .A(in2[5]), .Y(n73) );
CLKXOR2X2TS U162 ( .A(n85), .B(in2[11]), .Y(n107) );
XOR2X4TS U163 ( .A(n91), .B(in2[5]), .Y(n137) );
ADDFHX4TS U164 ( .A(n107), .B(in1[11]), .CI(n106), .CO(n108), .S(res[11]) );
ADDFHX4TS U165 ( .A(n109), .B(in1[12]), .CI(n108), .CO(n118), .S(res[12]) );
ADDFHX4TS U166 ( .A(n111), .B(in1[10]), .CI(n110), .CO(n106), .S(res[10]) );
OAI2BB2XLTS U167 ( .B0(n135), .B1(n133), .A0N(n137), .A1N(in1[5]), .Y(n126)
);
XNOR2X1TS U168 ( .A(n130), .B(in2[1]), .Y(n141) );
AOI21X1TS U169 ( .A0(n135), .A1(n134), .B0(n133), .Y(n139) );
INVX2TS U170 ( .A(in1[5]), .Y(n136) );
CMPR32X2TS U171 ( .A(in1[1]), .B(n141), .C(n140), .CO(n142), .S(res[1]) );
CMPR32X2TS U172 ( .A(in1[2]), .B(n143), .C(n142), .CO(n144), .S(res[2]) );
CMPR32X2TS U173 ( .A(in1[3]), .B(n145), .C(n144), .CO(n146), .S(res[3]) );
XOR2X1TS U174 ( .A(in1[4]), .B(n146), .Y(n147) );
initial $sdf_annotate("Approx_adder_ACAIN8Q5_syn.sdf");
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:50:25 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_xbar_0_sim_netlist.v
// Design : DemoInterconnect_xbar_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "DemoInterconnect_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI AWADDR [31:0] [95:64]" *) input [95:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI AWPROT [2:0] [8:6]" *) input [8:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWVALID [0:0] [2:2]" *) input [2:0]s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWREADY [0:0] [2:2]" *) output [2:0]s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI WDATA [31:0] [95:64]" *) input [95:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI WSTRB [3:0] [11:8]" *) input [11:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WVALID [0:0] [2:2]" *) input [2:0]s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WREADY [0:0] [2:2]" *) output [2:0]s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI BRESP [1:0] [5:4]" *) output [5:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI BVALID [0:0] [2:2]" *) output [2:0]s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI BREADY [0:0] [2:2]" *) input [2:0]s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI ARADDR [31:0] [95:64]" *) input [95:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI ARPROT [2:0] [8:6]" *) input [8:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARVALID [0:0] [2:2]" *) input [2:0]s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARREADY [0:0] [2:2]" *) output [2:0]s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI RDATA [31:0] [95:64]" *) output [95:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI RRESP [1:0] [5:4]" *) output [5:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RVALID [0:0] [2:2]" *) output [2:0]s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RREADY [0:0] [2:2]" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME S01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME S02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [2:0]s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI AWADDR [31:0] [223:192]" *) output [223:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI AWPROT [2:0] [20:18]" *) output [20:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWVALID [0:0] [6:6]" *) output [6:0]m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWREADY [0:0] [6:6]" *) input [6:0]m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI WDATA [31:0] [223:192]" *) output [223:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20], xilinx.com:interface:aximm:1.0 M06_AXI WSTRB [3:0] [27:24]" *) output [27:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WVALID [0:0] [6:6]" *) output [6:0]m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WREADY [0:0] [6:6]" *) input [6:0]m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI BRESP [1:0] [13:12]" *) input [13:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BVALID [0:0] [6:6]" *) input [6:0]m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BREADY [0:0] [6:6]" *) output [6:0]m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI ARADDR [31:0] [223:192]" *) output [223:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI ARPROT [2:0] [20:18]" *) output [20:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARVALID [0:0] [6:6]" *) output [6:0]m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARREADY [0:0] [6:6]" *) input [6:0]m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI RDATA [31:0] [223:192]" *) input [223:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI RRESP [1:0] [13:12]" *) input [13:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RVALID [0:0] [6:6]" *) input [6:0]m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RREADY [0:0] [6:6]" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M05_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M06_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) output [6:0]m_axi_rready;
wire aclk;
wire aresetn;
wire [223:0]m_axi_araddr;
wire [20:0]m_axi_arprot;
wire [6:0]m_axi_arready;
wire [6:0]m_axi_arvalid;
wire [223:0]m_axi_awaddr;
wire [20:0]m_axi_awprot;
wire [6:0]m_axi_awready;
wire [6:0]m_axi_awvalid;
wire [6:0]m_axi_bready;
wire [13:0]m_axi_bresp;
wire [6:0]m_axi_bvalid;
wire [223:0]m_axi_rdata;
wire [6:0]m_axi_rready;
wire [13:0]m_axi_rresp;
wire [6:0]m_axi_rvalid;
wire [223:0]m_axi_wdata;
wire [6:0]m_axi_wready;
wire [27:0]m_axi_wstrb;
wire [6:0]m_axi_wvalid;
wire [95:0]s_axi_araddr;
wire [8:0]s_axi_arprot;
wire [2:0]s_axi_arready;
wire [2:0]s_axi_arvalid;
wire [95:0]s_axi_awaddr;
wire [8:0]s_axi_awprot;
wire [2:0]s_axi_awready;
wire [2:0]s_axi_awvalid;
wire [2:0]s_axi_bready;
wire [5:0]s_axi_bresp;
wire [2:0]s_axi_bvalid;
wire [95:0]s_axi_rdata;
wire [2:0]s_axi_rready;
wire [5:0]s_axi_rresp;
wire [2:0]s_axi_rvalid;
wire [95:0]s_axi_wdata;
wire [2:0]s_axi_wready;
wire [11:0]s_axi_wstrb;
wire [2:0]s_axi_wvalid;
wire [13:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [27:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [6:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [55:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [6:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [27:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [27:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [20:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [6:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [13:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [27:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [6:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [55:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [6:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [27:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [27:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [20:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [6:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [6:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [6:0]NLW_inst_m_axi_wlast_UNCONNECTED;
wire [6:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [2:0]NLW_inst_s_axi_bid_UNCONNECTED;
wire [2:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [2:0]NLW_inst_s_axi_rid_UNCONNECTED;
wire [2:0]NLW_inst_s_axi_rlast_UNCONNECTED;
wire [2:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_PROTOCOL = "2" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_CONNECTIVITY_MODE = "0" *)
(* C_DEBUG = "1" *)
(* C_FAMILY = "artix7" *)
(* C_M_AXI_ADDR_WIDTH = "224'b00000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100" *)
(* C_M_AXI_BASE_ADDR = "448'b0000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "224'b00000000000000000000000000000111000000000000000000000000000001110000000000000000000000000000011100000000000000000000000000000111000000000000000000000000000001110000000000000000000000000000011100000000000000000000000000000111" *)
(* C_M_AXI_READ_ISSUING = "224'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_SECURE = "224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "224'b00000000000000000000000000000111000000000000000000000000000001110000000000000000000000000000011100000000000000000000000000000111000000000000000000000000000001110000000000000000000000000000011100000000000000000000000000000111" *)
(* C_M_AXI_WRITE_ISSUING = "224'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "7" *)
(* C_NUM_SLAVE_SLOTS = "3" *)
(* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_S_AXI_BASE_ID = "96'b000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000" *)
(* C_S_AXI_READ_ACCEPTANCE = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_S_AXI_SINGLE_THREAD = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_S_AXI_THREAD_ID_WIDTH = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_S_AXI_WRITE_ACCEPTANCE = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "artix7" *)
(* P_INCR = "2'b01" *)
(* P_LEN = "8" *)
(* P_LOCK = "1" *)
(* P_M_AXI_ERR_MODE = "224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "7'b1111111" *)
(* P_M_AXI_SUPPORTS_WRITE = "7'b1111111" *)
(* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_HIGH_ID = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_SUPPORTS_READ = "3'b111" *)
(* P_S_AXI_SUPPORTS_WRITE = "3'b111" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[13:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[27:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[6:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[55:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[6:0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[27:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[27:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[20:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[6:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[13:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[27:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[6:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[55:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[6:0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[27:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[27:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[20:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[6:0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[6:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[6:0]),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[6:0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock({1'b0,1'b0,1'b0}),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(s_axi_arready),
.s_axi_arsize({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_aruser({1'b0,1'b0,1'b0}),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock({1'b0,1'b0,1'b0}),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(s_axi_awready),
.s_axi_awsize({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awuser({1'b0,1'b0,1'b0}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[2:0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[2:0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[2:0]),
.s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[2:0]),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[2:0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid({1'b0,1'b0,1'b0}),
.s_axi_wlast({1'b1,1'b1,1'b1}),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser({1'b0,1'b0,1'b0}),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_addr_arbiter_sasd
(reset,
m_valid_i,
aa_grant_rnw,
\m_ready_d_reg[1] ,
E,
p_2_in,
\m_atarget_enc_reg[2] ,
\gen_axilite.s_axi_bvalid_i_reg ,
s_axi_awready,
\m_atarget_enc_reg[1] ,
\m_atarget_enc_reg[0] ,
mi_arready_mux,
m_axi_arvalid,
aa_rvalid,
\m_ready_d_reg[1]_0 ,
\gen_arbiter.m_valid_i_reg_0 ,
mi_awready_mux,
\gen_arbiter.m_valid_i_reg_1 ,
m_ready_d0,
m_axi_bready,
aa_wvalid,
s_axi_wready,
s_axi_bvalid,
m_axi_wvalid,
m_axi_wstrb,
m_axi_wdata,
s_axi_arready,
s_axi_rvalid,
D,
m_axi_awvalid,
\m_axi_awprot[20] ,
\gen_axilite.s_axi_bvalid_i_reg_0 ,
aclk,
m_ready_d,
sr_rvalid,
s_axi_arvalid,
s_axi_awvalid,
aresetn_d,
m_ready_d_0,
\gen_axilite.s_axi_arready_i_reg ,
Q,
s_axi_rready,
\m_atarget_enc_reg[1]_0 ,
\m_atarget_enc_reg[1]_1 ,
s_ready_i0__2,
\m_atarget_enc_reg[2]_0 ,
\m_atarget_enc_reg[0]_0 ,
\gen_axilite.s_axi_bvalid_i_reg_1 ,
\m_atarget_enc_reg[0]_1 ,
s_axi_bready,
\m_atarget_enc_reg[2]_1 ,
\m_atarget_enc_reg[0]_2 ,
\gen_axilite.s_axi_awready_i_reg ,
\m_atarget_enc_reg[0]_3 ,
m_axi_arready,
m_atarget_enc,
\m_atarget_enc_reg[0]_4 ,
\gen_axilite.s_axi_awready_i_reg_0 ,
\m_atarget_enc_reg[0]_5 ,
\m_atarget_enc_reg[2]_2 ,
s_axi_wvalid,
s_axi_wstrb,
s_axi_wdata,
s_axi_araddr,
s_axi_awaddr,
s_axi_arprot,
s_axi_awprot,
\m_payload_i_reg[0] ,
mi_bvalid,
mi_wready);
output reset;
output m_valid_i;
output aa_grant_rnw;
output \m_ready_d_reg[1] ;
output [0:0]E;
output p_2_in;
output \m_atarget_enc_reg[2] ;
output \gen_axilite.s_axi_bvalid_i_reg ;
output [2:0]s_axi_awready;
output \m_atarget_enc_reg[1] ;
output \m_atarget_enc_reg[0] ;
output mi_arready_mux;
output [6:0]m_axi_arvalid;
output aa_rvalid;
output [0:0]\m_ready_d_reg[1]_0 ;
output \gen_arbiter.m_valid_i_reg_0 ;
output mi_awready_mux;
output [1:0]\gen_arbiter.m_valid_i_reg_1 ;
output [0:0]m_ready_d0;
output [6:0]m_axi_bready;
output aa_wvalid;
output [2:0]s_axi_wready;
output [2:0]s_axi_bvalid;
output [6:0]m_axi_wvalid;
output [3:0]m_axi_wstrb;
output [31:0]m_axi_wdata;
output [2:0]s_axi_arready;
output [2:0]s_axi_rvalid;
output [7:0]D;
output [6:0]m_axi_awvalid;
output [34:0]\m_axi_awprot[20] ;
output \gen_axilite.s_axi_bvalid_i_reg_0 ;
input aclk;
input [1:0]m_ready_d;
input sr_rvalid;
input [2:0]s_axi_arvalid;
input [2:0]s_axi_awvalid;
input aresetn_d;
input [2:0]m_ready_d_0;
input \gen_axilite.s_axi_arready_i_reg ;
input [7:0]Q;
input [2:0]s_axi_rready;
input \m_atarget_enc_reg[1]_0 ;
input \m_atarget_enc_reg[1]_1 ;
input [0:0]s_ready_i0__2;
input \m_atarget_enc_reg[2]_0 ;
input \m_atarget_enc_reg[0]_0 ;
input \gen_axilite.s_axi_bvalid_i_reg_1 ;
input \m_atarget_enc_reg[0]_1 ;
input [2:0]s_axi_bready;
input \m_atarget_enc_reg[2]_1 ;
input \m_atarget_enc_reg[0]_2 ;
input \gen_axilite.s_axi_awready_i_reg ;
input \m_atarget_enc_reg[0]_3 ;
input [5:0]m_axi_arready;
input [2:0]m_atarget_enc;
input \m_atarget_enc_reg[0]_4 ;
input \gen_axilite.s_axi_awready_i_reg_0 ;
input \m_atarget_enc_reg[0]_5 ;
input \m_atarget_enc_reg[2]_2 ;
input [2:0]s_axi_wvalid;
input [11:0]s_axi_wstrb;
input [95:0]s_axi_wdata;
input [95:0]s_axi_araddr;
input [95:0]s_axi_awaddr;
input [8:0]s_axi_arprot;
input [8:0]s_axi_awprot;
input \m_payload_i_reg[0] ;
input [0:0]mi_bvalid;
input [0:0]mi_wready;
wire [7:0]D;
wire [0:0]E;
wire [7:0]Q;
wire aa_awready;
wire aa_bvalid;
wire aa_grant_any;
wire [1:0]aa_grant_enc;
wire [2:0]aa_grant_hot;
wire aa_grant_rnw;
wire aa_rvalid;
wire aa_wready;
wire aa_wvalid;
wire aclk;
wire [48:1]amesg_mux;
wire aresetn_d;
wire found_rr;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ;
wire \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ;
wire \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2__2 ;
wire \gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2__2 ;
wire \gen_addr_decoder.addr_decoder_inst/gen_target[2].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2__4 ;
wire \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2__4 ;
wire \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ;
wire \gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2 ;
wire \gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ;
wire \gen_arbiter.any_grant_i_1_n_0 ;
wire \gen_arbiter.any_grant_i_2_n_0 ;
wire \gen_arbiter.grant_rnw_i_1_n_0 ;
wire \gen_arbiter.grant_rnw_i_2_n_0 ;
wire \gen_arbiter.last_rr_hot[0]_i_1_n_0 ;
wire \gen_arbiter.last_rr_hot[0]_i_3_n_0 ;
wire \gen_arbiter.last_rr_hot[2]_i_1_n_0 ;
wire \gen_arbiter.last_rr_hot[2]_i_5_n_0 ;
wire \gen_arbiter.last_rr_hot_reg_n_0_[0] ;
wire \gen_arbiter.m_amesg_i[32]_i_5_n_0 ;
wire \gen_arbiter.m_amesg_i[32]_i_6_n_0 ;
wire \gen_arbiter.m_amesg_i[32]_i_8_n_0 ;
wire \gen_arbiter.m_grant_enc_i[0]_i_2_n_0 ;
wire \gen_arbiter.m_grant_enc_i[0]_i_3_n_0 ;
wire \gen_arbiter.m_grant_hot_i[0]_i_1_n_0 ;
wire \gen_arbiter.m_grant_hot_i[0]_i_2_n_0 ;
wire \gen_arbiter.m_grant_hot_i[1]_i_1_n_0 ;
wire \gen_arbiter.m_grant_hot_i[1]_i_2_n_0 ;
wire \gen_arbiter.m_grant_hot_i[2]_i_10_n_0 ;
wire \gen_arbiter.m_grant_hot_i[2]_i_1_n_0 ;
wire \gen_arbiter.m_grant_hot_i[2]_i_2_n_0 ;
wire \gen_arbiter.m_grant_hot_i[2]_i_5_n_0 ;
wire \gen_arbiter.m_grant_hot_i[2]_i_6_n_0 ;
wire \gen_arbiter.m_grant_hot_i[2]_i_9_n_0 ;
wire \gen_arbiter.m_valid_i_i_1_n_0 ;
wire \gen_arbiter.m_valid_i_reg_0 ;
wire [1:0]\gen_arbiter.m_valid_i_reg_1 ;
wire \gen_arbiter.s_ready_i[0]_i_1_n_0 ;
wire \gen_arbiter.s_ready_i[1]_i_1_n_0 ;
wire \gen_arbiter.s_ready_i[2]_i_1_n_0 ;
wire \gen_axilite.s_axi_arready_i_reg ;
wire \gen_axilite.s_axi_awready_i_reg ;
wire \gen_axilite.s_axi_awready_i_reg_0 ;
wire \gen_axilite.s_axi_bvalid_i_reg ;
wire \gen_axilite.s_axi_bvalid_i_reg_0 ;
wire \gen_axilite.s_axi_bvalid_i_reg_1 ;
wire [2:0]m_atarget_enc;
wire \m_atarget_enc_reg[0] ;
wire \m_atarget_enc_reg[0]_0 ;
wire \m_atarget_enc_reg[0]_1 ;
wire \m_atarget_enc_reg[0]_2 ;
wire \m_atarget_enc_reg[0]_3 ;
wire \m_atarget_enc_reg[0]_4 ;
wire \m_atarget_enc_reg[0]_5 ;
wire \m_atarget_enc_reg[1] ;
wire \m_atarget_enc_reg[1]_0 ;
wire \m_atarget_enc_reg[1]_1 ;
wire \m_atarget_enc_reg[2] ;
wire \m_atarget_enc_reg[2]_0 ;
wire \m_atarget_enc_reg[2]_1 ;
wire \m_atarget_enc_reg[2]_2 ;
wire \m_atarget_hot[3]_i_2_n_0 ;
wire \m_atarget_hot[7]_i_3_n_0 ;
wire \m_atarget_hot[7]_i_7_n_0 ;
wire \m_atarget_hot[7]_i_8_n_0 ;
wire [5:0]m_axi_arready;
wire [6:0]m_axi_arvalid;
wire [34:0]\m_axi_awprot[20] ;
wire [6:0]m_axi_awvalid;
wire [6:0]m_axi_bready;
wire [31:0]m_axi_wdata;
wire [3:0]m_axi_wstrb;
wire [6:0]m_axi_wvalid;
wire \m_payload_i[34]_i_4_n_0 ;
wire \m_payload_i_reg[0] ;
wire [1:0]m_ready_d;
wire [0:0]m_ready_d0;
wire \m_ready_d[1]_i_5_n_0 ;
wire \m_ready_d[1]_i_7_n_0 ;
wire \m_ready_d[1]_i_8_n_0 ;
wire [2:0]m_ready_d_0;
wire \m_ready_d_reg[1] ;
wire [0:0]\m_ready_d_reg[1]_0 ;
wire m_valid_i;
wire match;
wire mi_arready_mux;
wire mi_awready_mux;
wire [0:0]mi_bvalid;
wire [0:0]mi_wready;
wire [1:0]next_enc;
wire p_0_in;
wire p_0_in11_in;
wire [0:0]p_0_out__0;
wire p_2_in;
wire p_2_in_0;
wire p_3_in;
wire p_5_in;
wire reset;
wire [176:1]s_amesg;
wire \s_arvalid_reg[0]_i_1_n_0 ;
wire \s_arvalid_reg[1]_i_1_n_0 ;
wire \s_arvalid_reg[2]_i_1_n_0 ;
wire \s_arvalid_reg[2]_i_2_n_0 ;
wire \s_arvalid_reg_reg_n_0_[0] ;
wire \s_arvalid_reg_reg_n_0_[1] ;
wire \s_arvalid_reg_reg_n_0_[2] ;
wire [2:0]s_awvalid_reg;
wire [2:0]s_awvalid_reg0;
wire [95:0]s_axi_araddr;
wire [8:0]s_axi_arprot;
wire [2:0]s_axi_arready;
wire [2:0]s_axi_arvalid;
wire [95:0]s_axi_awaddr;
wire [8:0]s_axi_awprot;
wire [2:0]s_axi_awready;
wire [2:0]s_axi_awvalid;
wire [2:0]s_axi_bready;
wire [2:0]s_axi_bvalid;
wire \s_axi_bvalid[2]_INST_0_i_2_n_0 ;
wire [2:0]s_axi_rready;
wire [2:0]s_axi_rvalid;
wire [95:0]s_axi_wdata;
wire [2:0]s_axi_wready;
wire \s_axi_wready[2]_INST_0_i_2_n_0 ;
wire [11:0]s_axi_wstrb;
wire [2:0]s_axi_wvalid;
wire [2:0]s_ready_i;
wire [0:0]s_ready_i0__2;
wire sr_rvalid;
wire [1:0]target_mi_enc;
LUT6 #(
.INIT(64'h0808088888880888))
\gen_arbiter.any_grant_i_1
(.I0(\gen_arbiter.any_grant_i_2_n_0 ),
.I1(aresetn_d),
.I2(m_valid_i),
.I3(aa_awready),
.I4(aa_grant_rnw),
.I5(\m_payload_i_reg[0] ),
.O(\gen_arbiter.any_grant_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAE))
\gen_arbiter.any_grant_i_2
(.I0(aa_grant_any),
.I1(found_rr),
.I2(m_valid_i),
.O(\gen_arbiter.any_grant_i_2_n_0 ));
FDRE \gen_arbiter.any_grant_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_arbiter.any_grant_i_1_n_0 ),
.Q(aa_grant_any),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hFFEF0020))
\gen_arbiter.grant_rnw_i_1
(.I0(\gen_arbiter.grant_rnw_i_2_n_0 ),
.I1(aa_grant_any),
.I2(found_rr),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(\gen_arbiter.grant_rnw_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.grant_rnw_i_2
(.I0(next_enc[0]),
.I1(\s_arvalid_reg[1]_i_1_n_0 ),
.I2(\s_arvalid_reg[2]_i_2_n_0 ),
.I3(next_enc[1]),
.I4(\s_arvalid_reg[0]_i_1_n_0 ),
.I5(\gen_arbiter.last_rr_hot[0]_i_1_n_0 ),
.O(\gen_arbiter.grant_rnw_i_2_n_0 ));
FDRE \gen_arbiter.grant_rnw_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_arbiter.grant_rnw_i_1_n_0 ),
.Q(aa_grant_rnw),
.R(reset));
LUT6 #(
.INIT(64'hEEEEEEEE00EE00E0))
\gen_arbiter.last_rr_hot[0]_i_1
(.I0(s_axi_arvalid[0]),
.I1(s_axi_awvalid[0]),
.I2(aa_grant_enc[0]),
.I3(p_2_in_0),
.I4(\gen_arbiter.last_rr_hot[0]_i_3_n_0 ),
.I5(p_5_in),
.O(\gen_arbiter.last_rr_hot[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'hE))
\gen_arbiter.last_rr_hot[0]_i_2
(.I0(s_axi_awvalid[2]),
.I1(s_axi_arvalid[2]),
.O(p_2_in_0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h02))
\gen_arbiter.last_rr_hot[0]_i_3
(.I0(\gen_arbiter.last_rr_hot_reg_n_0_[0] ),
.I1(s_axi_arvalid[1]),
.I2(s_axi_awvalid[1]),
.O(\gen_arbiter.last_rr_hot[0]_i_3_n_0 ));
LUT3 #(
.INIT(8'h04))
\gen_arbiter.last_rr_hot[2]_i_1
(.I0(m_valid_i),
.I1(found_rr),
.I2(aa_grant_any),
.O(\gen_arbiter.last_rr_hot[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEEEEEEEE00EE00E0))
\gen_arbiter.last_rr_hot[2]_i_2
(.I0(s_axi_arvalid[2]),
.I1(s_axi_awvalid[2]),
.I2(\gen_arbiter.last_rr_hot_reg_n_0_[0] ),
.I3(p_0_in11_in),
.I4(\gen_arbiter.last_rr_hot[2]_i_5_n_0 ),
.I5(aa_grant_enc[0]),
.O(next_enc[1]));
LUT6 #(
.INIT(64'hFFFFFAFAFFCCFAC8))
\gen_arbiter.last_rr_hot[2]_i_3
(.I0(p_2_in_0),
.I1(\gen_arbiter.last_rr_hot_reg_n_0_[0] ),
.I2(p_0_in11_in),
.I3(p_5_in),
.I4(\gen_arbiter.m_grant_enc_i[0]_i_2_n_0 ),
.I5(aa_grant_enc[0]),
.O(found_rr));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'hE))
\gen_arbiter.last_rr_hot[2]_i_4
(.I0(s_axi_awvalid[1]),
.I1(s_axi_arvalid[1]),
.O(p_0_in11_in));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h02))
\gen_arbiter.last_rr_hot[2]_i_5
(.I0(p_5_in),
.I1(s_axi_arvalid[0]),
.I2(s_axi_awvalid[0]),
.O(\gen_arbiter.last_rr_hot[2]_i_5_n_0 ));
FDRE \gen_arbiter.last_rr_hot_reg[0]
(.C(aclk),
.CE(\gen_arbiter.last_rr_hot[2]_i_1_n_0 ),
.D(\gen_arbiter.last_rr_hot[0]_i_1_n_0 ),
.Q(\gen_arbiter.last_rr_hot_reg_n_0_[0] ),
.R(reset));
FDSE \gen_arbiter.last_rr_hot_reg[2]
(.C(aclk),
.CE(\gen_arbiter.last_rr_hot[2]_i_1_n_0 ),
.D(next_enc[1]),
.Q(p_5_in),
.S(reset));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[10]_i_1
(.I0(s_amesg[138]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[10]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[74]),
.O(amesg_mux[10]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[10]_i_2
(.I0(s_axi_araddr[73]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[73]),
.O(s_amesg[138]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[10]_i_3
(.I0(s_axi_araddr[9]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[9]),
.O(s_amesg[10]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[10]_i_4
(.I0(s_axi_araddr[41]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[41]),
.O(s_amesg[74]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[11]_i_1
(.I0(s_amesg[139]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[11]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[75]),
.O(amesg_mux[11]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[11]_i_2
(.I0(s_axi_araddr[74]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[74]),
.O(s_amesg[139]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[11]_i_3
(.I0(s_axi_araddr[10]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[10]),
.O(s_amesg[11]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[11]_i_4
(.I0(s_axi_araddr[42]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[42]),
.O(s_amesg[75]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[12]_i_1
(.I0(s_amesg[140]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[12]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[76]),
.O(amesg_mux[12]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[12]_i_2
(.I0(s_axi_araddr[75]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[75]),
.O(s_amesg[140]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[12]_i_3
(.I0(s_axi_araddr[11]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[11]),
.O(s_amesg[12]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[12]_i_4
(.I0(s_axi_araddr[43]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[43]),
.O(s_amesg[76]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[13]_i_1
(.I0(s_amesg[141]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[13]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[77]),
.O(amesg_mux[13]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[13]_i_2
(.I0(s_axi_araddr[76]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[76]),
.O(s_amesg[141]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[13]_i_3
(.I0(s_axi_araddr[12]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[12]),
.O(s_amesg[13]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[13]_i_4
(.I0(s_axi_araddr[44]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[44]),
.O(s_amesg[77]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[14]_i_1
(.I0(s_amesg[142]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[14]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[78]),
.O(amesg_mux[14]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[14]_i_2
(.I0(s_axi_araddr[77]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[77]),
.O(s_amesg[142]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[14]_i_3
(.I0(s_axi_araddr[13]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[13]),
.O(s_amesg[14]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[14]_i_4
(.I0(s_axi_araddr[45]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[45]),
.O(s_amesg[78]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[15]_i_1
(.I0(s_amesg[143]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[15]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[79]),
.O(amesg_mux[15]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[15]_i_2
(.I0(s_axi_araddr[78]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[78]),
.O(s_amesg[143]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[15]_i_3
(.I0(s_axi_araddr[14]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[14]),
.O(s_amesg[15]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[15]_i_4
(.I0(s_axi_araddr[46]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[46]),
.O(s_amesg[79]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[16]_i_1
(.I0(s_amesg[144]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[16]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[80]),
.O(amesg_mux[16]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[16]_i_2
(.I0(s_axi_araddr[79]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[79]),
.O(s_amesg[144]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[16]_i_3
(.I0(s_axi_araddr[15]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[15]),
.O(s_amesg[16]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[16]_i_4
(.I0(s_axi_araddr[47]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[47]),
.O(s_amesg[80]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[17]_i_1
(.I0(s_amesg[145]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[17]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[81]),
.O(amesg_mux[17]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[17]_i_2
(.I0(s_axi_araddr[80]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[80]),
.O(s_amesg[145]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[17]_i_3
(.I0(s_axi_araddr[16]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[16]),
.O(s_amesg[17]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[17]_i_4
(.I0(s_axi_araddr[48]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[48]),
.O(s_amesg[81]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[18]_i_1
(.I0(s_amesg[146]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[18]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[82]),
.O(amesg_mux[18]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[18]_i_2
(.I0(s_axi_araddr[81]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[81]),
.O(s_amesg[146]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[18]_i_3
(.I0(s_axi_araddr[17]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[17]),
.O(s_amesg[18]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[18]_i_4
(.I0(s_axi_araddr[49]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[49]),
.O(s_amesg[82]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[19]_i_1
(.I0(s_amesg[147]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[19]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[83]),
.O(amesg_mux[19]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[19]_i_2
(.I0(s_axi_araddr[82]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[82]),
.O(s_amesg[147]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[19]_i_3
(.I0(s_axi_araddr[18]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[18]),
.O(s_amesg[19]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[19]_i_4
(.I0(s_axi_araddr[50]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[50]),
.O(s_amesg[83]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[1]_i_1
(.I0(s_amesg[129]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[1]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[65]),
.O(amesg_mux[1]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[1]_i_2
(.I0(s_axi_araddr[64]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[64]),
.O(s_amesg[129]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[1]_i_3
(.I0(s_axi_araddr[0]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[0]),
.O(s_amesg[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[1]_i_4
(.I0(s_axi_araddr[32]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[32]),
.O(s_amesg[65]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[20]_i_1
(.I0(s_amesg[148]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[20]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[84]),
.O(amesg_mux[20]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[20]_i_2
(.I0(s_axi_araddr[83]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[83]),
.O(s_amesg[148]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[20]_i_3
(.I0(s_axi_araddr[19]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[19]),
.O(s_amesg[20]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[20]_i_4
(.I0(s_axi_araddr[51]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[51]),
.O(s_amesg[84]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[21]_i_1
(.I0(s_amesg[149]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[21]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[85]),
.O(amesg_mux[21]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[21]_i_2
(.I0(s_axi_araddr[84]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[84]),
.O(s_amesg[149]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[21]_i_3
(.I0(s_axi_araddr[20]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[20]),
.O(s_amesg[21]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[21]_i_4
(.I0(s_axi_araddr[52]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[52]),
.O(s_amesg[85]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[22]_i_1
(.I0(s_amesg[150]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[22]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[86]),
.O(amesg_mux[22]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[22]_i_2
(.I0(s_axi_araddr[85]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[85]),
.O(s_amesg[150]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[22]_i_3
(.I0(s_axi_araddr[21]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[21]),
.O(s_amesg[22]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[22]_i_4
(.I0(s_axi_araddr[53]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[53]),
.O(s_amesg[86]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[23]_i_1
(.I0(s_amesg[151]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[23]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[87]),
.O(amesg_mux[23]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[23]_i_2
(.I0(s_axi_araddr[86]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[86]),
.O(s_amesg[151]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[23]_i_3
(.I0(s_axi_araddr[22]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[22]),
.O(s_amesg[23]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[23]_i_4
(.I0(s_axi_araddr[54]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[54]),
.O(s_amesg[87]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[24]_i_1
(.I0(s_amesg[152]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[24]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[88]),
.O(amesg_mux[24]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[24]_i_2
(.I0(s_axi_araddr[87]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[87]),
.O(s_amesg[152]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[24]_i_3
(.I0(s_axi_araddr[23]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[23]),
.O(s_amesg[24]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[24]_i_4
(.I0(s_axi_araddr[55]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[55]),
.O(s_amesg[88]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[25]_i_1
(.I0(s_amesg[153]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[25]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[89]),
.O(amesg_mux[25]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[25]_i_2
(.I0(s_axi_araddr[88]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[88]),
.O(s_amesg[153]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[25]_i_3
(.I0(s_axi_araddr[24]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[24]),
.O(s_amesg[25]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[25]_i_4
(.I0(s_axi_araddr[56]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[56]),
.O(s_amesg[89]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[26]_i_1
(.I0(s_amesg[154]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[26]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[90]),
.O(amesg_mux[26]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[26]_i_2
(.I0(s_axi_araddr[89]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[89]),
.O(s_amesg[154]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[26]_i_3
(.I0(s_axi_araddr[25]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[25]),
.O(s_amesg[26]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[26]_i_4
(.I0(s_axi_araddr[57]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[57]),
.O(s_amesg[90]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[27]_i_1
(.I0(s_amesg[155]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[27]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[91]),
.O(amesg_mux[27]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[27]_i_2
(.I0(s_axi_araddr[90]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[90]),
.O(s_amesg[155]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[27]_i_3
(.I0(s_axi_araddr[26]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[26]),
.O(s_amesg[27]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[27]_i_4
(.I0(s_axi_araddr[58]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[58]),
.O(s_amesg[91]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[28]_i_1
(.I0(s_amesg[156]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[28]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[92]),
.O(amesg_mux[28]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[28]_i_2
(.I0(s_axi_araddr[91]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[91]),
.O(s_amesg[156]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[28]_i_3
(.I0(s_axi_araddr[27]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[27]),
.O(s_amesg[28]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[28]_i_4
(.I0(s_axi_araddr[59]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[59]),
.O(s_amesg[92]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[29]_i_1
(.I0(s_amesg[157]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[29]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[93]),
.O(amesg_mux[29]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[29]_i_2
(.I0(s_axi_araddr[92]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[92]),
.O(s_amesg[157]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[29]_i_3
(.I0(s_axi_araddr[28]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[28]),
.O(s_amesg[29]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[29]_i_4
(.I0(s_axi_araddr[60]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[60]),
.O(s_amesg[93]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[2]_i_1
(.I0(s_amesg[130]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[2]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[66]),
.O(amesg_mux[2]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[2]_i_2
(.I0(s_axi_araddr[65]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[65]),
.O(s_amesg[130]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[2]_i_3
(.I0(s_axi_araddr[1]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[1]),
.O(s_amesg[2]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[2]_i_4
(.I0(s_axi_araddr[33]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[33]),
.O(s_amesg[66]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[30]_i_1
(.I0(s_amesg[158]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[30]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[94]),
.O(amesg_mux[30]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[30]_i_2
(.I0(s_axi_araddr[93]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[93]),
.O(s_amesg[158]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[30]_i_3
(.I0(s_axi_araddr[29]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[29]),
.O(s_amesg[30]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[30]_i_4
(.I0(s_axi_araddr[61]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[61]),
.O(s_amesg[94]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[31]_i_1
(.I0(s_amesg[159]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[31]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[95]),
.O(amesg_mux[31]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[31]_i_2
(.I0(s_axi_araddr[94]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[94]),
.O(s_amesg[159]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[31]_i_3
(.I0(s_axi_araddr[30]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[30]),
.O(s_amesg[31]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[31]_i_4
(.I0(s_axi_araddr[62]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[62]),
.O(s_amesg[95]));
LUT1 #(
.INIT(2'h1))
\gen_arbiter.m_amesg_i[32]_i_1
(.I0(aresetn_d),
.O(reset));
LUT1 #(
.INIT(2'h1))
\gen_arbiter.m_amesg_i[32]_i_2
(.I0(aa_grant_any),
.O(p_0_in));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[32]_i_3
(.I0(s_amesg[160]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[32]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[96]),
.O(amesg_mux[32]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[32]_i_4
(.I0(s_axi_araddr[95]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[95]),
.O(s_amesg[160]));
LUT2 #(
.INIT(4'h2))
\gen_arbiter.m_amesg_i[32]_i_5
(.I0(next_enc[1]),
.I1(next_enc[0]),
.O(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ));
LUT2 #(
.INIT(4'h1))
\gen_arbiter.m_amesg_i[32]_i_6
(.I0(next_enc[0]),
.I1(next_enc[1]),
.O(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[32]_i_7
(.I0(s_axi_araddr[31]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[31]),
.O(s_amesg[32]));
LUT2 #(
.INIT(4'h2))
\gen_arbiter.m_amesg_i[32]_i_8
(.I0(next_enc[0]),
.I1(next_enc[1]),
.O(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[32]_i_9
(.I0(s_axi_araddr[63]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[63]),
.O(s_amesg[96]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[3]_i_1
(.I0(s_amesg[131]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[3]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[67]),
.O(amesg_mux[3]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[3]_i_2
(.I0(s_axi_araddr[66]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[66]),
.O(s_amesg[131]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[3]_i_3
(.I0(s_axi_araddr[2]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[2]),
.O(s_amesg[3]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[3]_i_4
(.I0(s_axi_araddr[34]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[34]),
.O(s_amesg[67]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[46]_i_1
(.I0(s_amesg[174]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[46]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[110]),
.O(amesg_mux[46]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[46]_i_2
(.I0(s_axi_arprot[6]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awprot[6]),
.O(s_amesg[174]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[46]_i_3
(.I0(s_axi_arprot[0]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awprot[0]),
.O(s_amesg[46]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[46]_i_4
(.I0(s_axi_arprot[3]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awprot[3]),
.O(s_amesg[110]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[47]_i_1
(.I0(s_amesg[175]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[47]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[111]),
.O(amesg_mux[47]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[47]_i_2
(.I0(s_axi_arprot[7]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awprot[7]),
.O(s_amesg[175]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[47]_i_3
(.I0(s_axi_arprot[1]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awprot[1]),
.O(s_amesg[47]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[47]_i_4
(.I0(s_axi_arprot[4]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awprot[4]),
.O(s_amesg[111]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[48]_i_1
(.I0(s_amesg[176]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[48]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[112]),
.O(amesg_mux[48]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[48]_i_2
(.I0(s_axi_arprot[8]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awprot[8]),
.O(s_amesg[176]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[48]_i_3
(.I0(s_axi_arprot[2]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awprot[2]),
.O(s_amesg[48]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[48]_i_4
(.I0(s_axi_arprot[5]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awprot[5]),
.O(s_amesg[112]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[4]_i_1
(.I0(s_amesg[132]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[4]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[68]),
.O(amesg_mux[4]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[4]_i_2
(.I0(s_axi_araddr[67]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[67]),
.O(s_amesg[132]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[4]_i_3
(.I0(s_axi_araddr[3]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[3]),
.O(s_amesg[4]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[4]_i_4
(.I0(s_axi_araddr[35]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[35]),
.O(s_amesg[68]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[5]_i_1
(.I0(s_amesg[133]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[5]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[69]),
.O(amesg_mux[5]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[5]_i_2
(.I0(s_axi_araddr[68]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[68]),
.O(s_amesg[133]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[5]_i_3
(.I0(s_axi_araddr[4]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[4]),
.O(s_amesg[5]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[5]_i_4
(.I0(s_axi_araddr[36]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[36]),
.O(s_amesg[69]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[6]_i_1
(.I0(s_amesg[134]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[6]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[70]),
.O(amesg_mux[6]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[6]_i_2
(.I0(s_axi_araddr[69]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[69]),
.O(s_amesg[134]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[6]_i_3
(.I0(s_axi_araddr[5]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[5]),
.O(s_amesg[6]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[6]_i_4
(.I0(s_axi_araddr[37]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[37]),
.O(s_amesg[70]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[7]_i_1
(.I0(s_amesg[135]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[7]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[71]),
.O(amesg_mux[7]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[7]_i_2
(.I0(s_axi_araddr[70]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[70]),
.O(s_amesg[135]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[7]_i_3
(.I0(s_axi_araddr[6]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[6]),
.O(s_amesg[7]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[7]_i_4
(.I0(s_axi_araddr[38]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[38]),
.O(s_amesg[71]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[8]_i_1
(.I0(s_amesg[136]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[8]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[72]),
.O(amesg_mux[8]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[8]_i_2
(.I0(s_axi_araddr[71]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[71]),
.O(s_amesg[136]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[8]_i_3
(.I0(s_axi_araddr[7]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[7]),
.O(s_amesg[8]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[8]_i_4
(.I0(s_axi_araddr[39]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[39]),
.O(s_amesg[72]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\gen_arbiter.m_amesg_i[9]_i_1
(.I0(s_amesg[137]),
.I1(\gen_arbiter.m_amesg_i[32]_i_5_n_0 ),
.I2(\gen_arbiter.m_amesg_i[32]_i_6_n_0 ),
.I3(s_amesg[9]),
.I4(\gen_arbiter.m_amesg_i[32]_i_8_n_0 ),
.I5(s_amesg[73]),
.O(amesg_mux[9]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[9]_i_2
(.I0(s_axi_araddr[72]),
.I1(s_axi_arvalid[2]),
.I2(s_awvalid_reg[2]),
.I3(s_axi_awaddr[72]),
.O(s_amesg[137]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[9]_i_3
(.I0(s_axi_araddr[8]),
.I1(s_axi_arvalid[0]),
.I2(s_awvalid_reg[0]),
.I3(s_axi_awaddr[8]),
.O(s_amesg[9]));
LUT4 #(
.INIT(16'hFB08))
\gen_arbiter.m_amesg_i[9]_i_4
(.I0(s_axi_araddr[40]),
.I1(s_axi_arvalid[1]),
.I2(s_awvalid_reg[1]),
.I3(s_axi_awaddr[40]),
.O(s_amesg[73]));
FDRE \gen_arbiter.m_amesg_i_reg[10]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[10]),
.Q(\m_axi_awprot[20] [9]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[11]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[11]),
.Q(\m_axi_awprot[20] [10]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[12]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[12]),
.Q(\m_axi_awprot[20] [11]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[13]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[13]),
.Q(\m_axi_awprot[20] [12]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[14]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[14]),
.Q(\m_axi_awprot[20] [13]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[15]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[15]),
.Q(\m_axi_awprot[20] [14]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[16]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[16]),
.Q(\m_axi_awprot[20] [15]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[17]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[17]),
.Q(\m_axi_awprot[20] [16]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[18]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[18]),
.Q(\m_axi_awprot[20] [17]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[19]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[19]),
.Q(\m_axi_awprot[20] [18]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[1]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[1]),
.Q(\m_axi_awprot[20] [0]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[20]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[20]),
.Q(\m_axi_awprot[20] [19]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[21]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[21]),
.Q(\m_axi_awprot[20] [20]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[22]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[22]),
.Q(\m_axi_awprot[20] [21]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[23]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[23]),
.Q(\m_axi_awprot[20] [22]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[24]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[24]),
.Q(\m_axi_awprot[20] [23]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[25]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[25]),
.Q(\m_axi_awprot[20] [24]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[26]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[26]),
.Q(\m_axi_awprot[20] [25]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[27]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[27]),
.Q(\m_axi_awprot[20] [26]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[28]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[28]),
.Q(\m_axi_awprot[20] [27]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[29]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[29]),
.Q(\m_axi_awprot[20] [28]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[2]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[2]),
.Q(\m_axi_awprot[20] [1]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[30]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[30]),
.Q(\m_axi_awprot[20] [29]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[31]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[31]),
.Q(\m_axi_awprot[20] [30]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[32]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[32]),
.Q(\m_axi_awprot[20] [31]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[3]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[3]),
.Q(\m_axi_awprot[20] [2]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[46]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[46]),
.Q(\m_axi_awprot[20] [32]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[47]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[47]),
.Q(\m_axi_awprot[20] [33]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[48]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[48]),
.Q(\m_axi_awprot[20] [34]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[4]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[4]),
.Q(\m_axi_awprot[20] [3]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[5]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[5]),
.Q(\m_axi_awprot[20] [4]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[6]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[6]),
.Q(\m_axi_awprot[20] [5]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[7]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[7]),
.Q(\m_axi_awprot[20] [6]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[8]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[8]),
.Q(\m_axi_awprot[20] [7]),
.R(reset));
FDRE \gen_arbiter.m_amesg_i_reg[9]
(.C(aclk),
.CE(p_0_in),
.D(amesg_mux[9]),
.Q(\m_axi_awprot[20] [8]),
.R(reset));
LUT6 #(
.INIT(64'hEEEEEEEE00EE00E0))
\gen_arbiter.m_grant_enc_i[0]_i_1
(.I0(s_axi_arvalid[1]),
.I1(s_axi_awvalid[1]),
.I2(p_5_in),
.I3(\gen_arbiter.m_grant_enc_i[0]_i_2_n_0 ),
.I4(\gen_arbiter.m_grant_enc_i[0]_i_3_n_0 ),
.I5(\gen_arbiter.last_rr_hot_reg_n_0_[0] ),
.O(next_enc[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'hE))
\gen_arbiter.m_grant_enc_i[0]_i_2
(.I0(s_axi_awvalid[0]),
.I1(s_axi_arvalid[0]),
.O(\gen_arbiter.m_grant_enc_i[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h02))
\gen_arbiter.m_grant_enc_i[0]_i_3
(.I0(aa_grant_enc[0]),
.I1(s_axi_arvalid[2]),
.I2(s_axi_awvalid[2]),
.O(\gen_arbiter.m_grant_enc_i[0]_i_3_n_0 ));
FDRE \gen_arbiter.m_grant_enc_i_reg[0]
(.C(aclk),
.CE(\gen_arbiter.last_rr_hot[2]_i_1_n_0 ),
.D(next_enc[0]),
.Q(aa_grant_enc[0]),
.R(reset));
FDRE \gen_arbiter.m_grant_enc_i_reg[1]
(.C(aclk),
.CE(\gen_arbiter.last_rr_hot[2]_i_1_n_0 ),
.D(next_enc[1]),
.Q(aa_grant_enc[1]),
.R(reset));
LUT6 #(
.INIT(64'h0808088888880888))
\gen_arbiter.m_grant_hot_i[0]_i_1
(.I0(\gen_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
.I1(aresetn_d),
.I2(m_valid_i),
.I3(aa_awready),
.I4(aa_grant_rnw),
.I5(\m_payload_i_reg[0] ),
.O(\gen_arbiter.m_grant_hot_i[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFAB00005500))
\gen_arbiter.m_grant_hot_i[0]_i_2
(.I0(m_valid_i),
.I1(next_enc[0]),
.I2(next_enc[1]),
.I3(\gen_arbiter.last_rr_hot[0]_i_1_n_0 ),
.I4(aa_grant_any),
.I5(aa_grant_hot[0]),
.O(\gen_arbiter.m_grant_hot_i[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0808088888880888))
\gen_arbiter.m_grant_hot_i[1]_i_1
(.I0(\gen_arbiter.m_grant_hot_i[1]_i_2_n_0 ),
.I1(aresetn_d),
.I2(m_valid_i),
.I3(aa_awready),
.I4(aa_grant_rnw),
.I5(\m_payload_i_reg[0] ),
.O(\gen_arbiter.m_grant_hot_i[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\gen_arbiter.m_grant_hot_i[1]_i_2
(.I0(next_enc[0]),
.I1(m_valid_i),
.I2(found_rr),
.I3(aa_grant_any),
.I4(aa_grant_hot[1]),
.O(\gen_arbiter.m_grant_hot_i[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0808088888880888))
\gen_arbiter.m_grant_hot_i[2]_i_1
(.I0(\gen_arbiter.m_grant_hot_i[2]_i_2_n_0 ),
.I1(aresetn_d),
.I2(m_valid_i),
.I3(aa_awready),
.I4(aa_grant_rnw),
.I5(\m_payload_i_reg[0] ),
.O(\gen_arbiter.m_grant_hot_i[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h3B380B08))
\gen_arbiter.m_grant_hot_i[2]_i_10
(.I0(s_axi_bready[2]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_bready[0]),
.I4(s_axi_bready[1]),
.O(\gen_arbiter.m_grant_hot_i[2]_i_10_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\gen_arbiter.m_grant_hot_i[2]_i_2
(.I0(next_enc[1]),
.I1(m_valid_i),
.I2(found_rr),
.I3(aa_grant_any),
.I4(aa_grant_hot[2]),
.O(\gen_arbiter.m_grant_hot_i[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF800F800F8000000))
\gen_arbiter.m_grant_hot_i[2]_i_3
(.I0(\gen_arbiter.m_grant_hot_i[2]_i_5_n_0 ),
.I1(\gen_arbiter.m_grant_hot_i[2]_i_6_n_0 ),
.I2(m_ready_d_0[1]),
.I3(s_ready_i0__2),
.I4(m_ready_d_0[0]),
.I5(p_0_out__0),
.O(aa_awready));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h7))
\gen_arbiter.m_grant_hot_i[2]_i_5
(.I0(aa_grant_enc[0]),
.I1(aa_grant_enc[1]),
.O(\gen_arbiter.m_grant_hot_i[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA800000000))
\gen_arbiter.m_grant_hot_i[2]_i_6
(.I0(\gen_arbiter.m_grant_hot_i[2]_i_9_n_0 ),
.I1(\m_atarget_enc_reg[2]_1 ),
.I2(\m_atarget_enc_reg[0]_2 ),
.I3(\gen_axilite.s_axi_awready_i_reg ),
.I4(\m_atarget_enc_reg[0]_3 ),
.I5(\s_axi_wready[2]_INST_0_i_2_n_0 ),
.O(\gen_arbiter.m_grant_hot_i[2]_i_6_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA800000000))
\gen_arbiter.m_grant_hot_i[2]_i_8
(.I0(\gen_arbiter.m_grant_hot_i[2]_i_10_n_0 ),
.I1(\m_atarget_enc_reg[2]_0 ),
.I2(\m_atarget_enc_reg[0]_0 ),
.I3(\gen_axilite.s_axi_bvalid_i_reg_1 ),
.I4(\m_atarget_enc_reg[0]_1 ),
.I5(\s_axi_bvalid[2]_INST_0_i_2_n_0 ),
.O(p_0_out__0));
LUT5 #(
.INIT(32'h3B380B08))
\gen_arbiter.m_grant_hot_i[2]_i_9
(.I0(s_axi_wvalid[2]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wvalid[0]),
.I4(s_axi_wvalid[1]),
.O(\gen_arbiter.m_grant_hot_i[2]_i_9_n_0 ));
FDRE \gen_arbiter.m_grant_hot_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_arbiter.m_grant_hot_i[0]_i_1_n_0 ),
.Q(aa_grant_hot[0]),
.R(1'b0));
FDRE \gen_arbiter.m_grant_hot_i_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_arbiter.m_grant_hot_i[1]_i_1_n_0 ),
.Q(aa_grant_hot[1]),
.R(1'b0));
FDRE \gen_arbiter.m_grant_hot_i_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\gen_arbiter.m_grant_hot_i[2]_i_1_n_0 ),
.Q(aa_grant_hot[2]),
.R(1'b0));
LUT6 #(
.INIT(64'h7747FFFF77470000))
\gen_arbiter.m_valid_i_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(aa_grant_rnw),
.I2(\gen_arbiter.m_valid_i_reg_1 [1]),
.I3(\gen_arbiter.m_valid_i_reg_0 ),
.I4(m_valid_i),
.I5(aa_grant_any),
.O(\gen_arbiter.m_valid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_arbiter.m_valid_i_i_1_n_0 ),
.Q(m_valid_i),
.R(reset));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h0800))
\gen_arbiter.s_ready_i[0]_i_1
(.I0(aa_grant_hot[0]),
.I1(aresetn_d),
.I2(m_valid_i),
.I3(aa_grant_any),
.O(\gen_arbiter.s_ready_i[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h0800))
\gen_arbiter.s_ready_i[1]_i_1
(.I0(aa_grant_hot[1]),
.I1(aresetn_d),
.I2(m_valid_i),
.I3(aa_grant_any),
.O(\gen_arbiter.s_ready_i[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h0800))
\gen_arbiter.s_ready_i[2]_i_1
(.I0(aa_grant_hot[2]),
.I1(aresetn_d),
.I2(m_valid_i),
.I3(aa_grant_any),
.O(\gen_arbiter.s_ready_i[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_arbiter.s_ready_i[0]_i_1_n_0 ),
.Q(s_ready_i[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gen_arbiter.s_ready_i_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_arbiter.s_ready_i[1]_i_1_n_0 ),
.Q(s_ready_i[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gen_arbiter.s_ready_i_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\gen_arbiter.s_ready_i[2]_i_1_n_0 ),
.Q(s_ready_i[2]),
.R(1'b0));
LUT6 #(
.INIT(64'h7C4C4C4C4C4C4C4C))
\gen_axilite.s_axi_bvalid_i_i_1
(.I0(p_3_in),
.I1(mi_bvalid),
.I2(Q[7]),
.I3(aa_wvalid),
.I4(\gen_axilite.s_axi_bvalid_i_reg ),
.I5(mi_wready),
.O(\gen_axilite.s_axi_bvalid_i_reg_0 ));
LUT6 #(
.INIT(64'hBBBBBBBBBBBBBBFB))
\m_atarget_enc[0]_i_1
(.I0(target_mi_enc[0]),
.I1(match),
.I2(\m_atarget_hot[7]_i_3_n_0 ),
.I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ),
.I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ),
.I5(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ),
.O(\m_atarget_enc_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hFE))
\m_atarget_enc[0]_i_2
(.I0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ),
.I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ),
.I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ),
.O(target_mi_enc[0]));
LUT6 #(
.INIT(64'hBBBBBBBBBBBBBBFB))
\m_atarget_enc[1]_i_1
(.I0(target_mi_enc[1]),
.I1(match),
.I2(\m_atarget_hot[7]_i_3_n_0 ),
.I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ),
.I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ),
.I5(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ),
.O(\m_atarget_enc_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hFE))
\m_atarget_enc[1]_i_2
(.I0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ),
.I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ),
.I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ),
.O(target_mi_enc[1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hFFFFFFFD))
\m_atarget_enc[2]_i_1
(.I0(match),
.I1(\m_atarget_hot[7]_i_3_n_0 ),
.I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ),
.I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ),
.I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ),
.O(\m_atarget_enc_reg[2] ));
LUT5 #(
.INIT(32'h2A000000))
\m_atarget_hot[0]_i_1
(.I0(aa_grant_any),
.I1(\m_atarget_hot[3]_i_2_n_0 ),
.I2(\m_atarget_hot[7]_i_3_n_0 ),
.I3(match),
.I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ),
.O(D[0]));
LUT5 #(
.INIT(32'h02000000))
\m_atarget_hot[0]_i_2
(.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ),
.I1(\m_axi_awprot[20] [12]),
.I2(\m_axi_awprot[20] [13]),
.I3(\gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2__2 ),
.I4(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\m_atarget_hot[0]_i_3
(.I0(\m_axi_awprot[20] [18]),
.I1(\m_axi_awprot[20] [17]),
.I2(\m_axi_awprot[20] [19]),
.I3(\m_axi_awprot[20] [14]),
.I4(\m_axi_awprot[20] [15]),
.I5(\m_axi_awprot[20] [16]),
.O(\gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2__2 ));
LUT5 #(
.INIT(32'h2A000000))
\m_atarget_hot[1]_i_1
(.I0(aa_grant_any),
.I1(\m_atarget_hot[3]_i_2_n_0 ),
.I2(\m_atarget_hot[7]_i_3_n_0 ),
.I3(match),
.I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ),
.O(D[1]));
LUT5 #(
.INIT(32'h02000000))
\m_atarget_hot[1]_i_2
(.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ),
.I1(\m_axi_awprot[20] [12]),
.I2(\m_axi_awprot[20] [13]),
.I3(\gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2__2 ),
.I4(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ));
LUT6 #(
.INIT(64'h0000000000000100))
\m_atarget_hot[1]_i_3
(.I0(\m_axi_awprot[20] [18]),
.I1(\m_axi_awprot[20] [17]),
.I2(\m_axi_awprot[20] [19]),
.I3(\m_axi_awprot[20] [16]),
.I4(\m_axi_awprot[20] [14]),
.I5(\m_axi_awprot[20] [15]),
.O(\gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2__2 ));
LUT5 #(
.INIT(32'h2A000000))
\m_atarget_hot[2]_i_1
(.I0(aa_grant_any),
.I1(\m_atarget_hot[3]_i_2_n_0 ),
.I2(\m_atarget_hot[7]_i_3_n_0 ),
.I3(match),
.I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ),
.O(D[2]));
LUT5 #(
.INIT(32'h02000000))
\m_atarget_hot[2]_i_2
(.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ),
.I1(\m_axi_awprot[20] [12]),
.I2(\m_axi_awprot[20] [13]),
.I3(\gen_addr_decoder.addr_decoder_inst/gen_target[2].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2__4 ),
.I4(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ));
LUT6 #(
.INIT(64'h0000000000000100))
\m_atarget_hot[2]_i_3
(.I0(\m_axi_awprot[20] [18]),
.I1(\m_axi_awprot[20] [16]),
.I2(\m_axi_awprot[20] [19]),
.I3(\m_axi_awprot[20] [17]),
.I4(\m_axi_awprot[20] [14]),
.I5(\m_axi_awprot[20] [15]),
.O(\gen_addr_decoder.addr_decoder_inst/gen_target[2].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2__4 ));
LUT5 #(
.INIT(32'h2A000000))
\m_atarget_hot[3]_i_1
(.I0(aa_grant_any),
.I1(\m_atarget_hot[3]_i_2_n_0 ),
.I2(\m_atarget_hot[7]_i_3_n_0 ),
.I3(match),
.I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h01))
\m_atarget_hot[3]_i_2
(.I0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ),
.I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ),
.I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ),
.O(\m_atarget_hot[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'h02000000))
\m_atarget_hot[3]_i_3
(.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ),
.I1(\m_axi_awprot[20] [12]),
.I2(\m_axi_awprot[20] [13]),
.I3(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2__4 ),
.I4(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ));
LUT6 #(
.INIT(64'h0000000000000001))
\m_atarget_hot[3]_i_4
(.I0(\m_axi_awprot[20] [24]),
.I1(\m_axi_awprot[20] [23]),
.I2(\m_axi_awprot[20] [25]),
.I3(\m_axi_awprot[20] [20]),
.I4(\m_axi_awprot[20] [21]),
.I5(\m_axi_awprot[20] [22]),
.O(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3 ));
LUT6 #(
.INIT(64'h0001000000000000))
\m_atarget_hot[3]_i_5
(.I0(\m_axi_awprot[20] [18]),
.I1(\m_axi_awprot[20] [15]),
.I2(\m_axi_awprot[20] [19]),
.I3(\m_axi_awprot[20] [14]),
.I4(\m_axi_awprot[20] [16]),
.I5(\m_axi_awprot[20] [17]),
.O(\gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2__4 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'h80))
\m_atarget_hot[4]_i_1
(.I0(aa_grant_any),
.I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ),
.I2(match),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'h80))
\m_atarget_hot[5]_i_1
(.I0(aa_grant_any),
.I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ),
.I2(match),
.O(D[5]));
LUT3 #(
.INIT(8'h80))
\m_atarget_hot[6]_i_1
(.I0(aa_grant_any),
.I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ),
.I2(match),
.O(D[6]));
LUT6 #(
.INIT(64'h22222222222222A2))
\m_atarget_hot[7]_i_1
(.I0(aa_grant_any),
.I1(match),
.I2(\m_atarget_hot[7]_i_3_n_0 ),
.I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ),
.I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ),
.I5(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ),
.O(D[7]));
LUT6 #(
.INIT(64'h0000000000000001))
\m_atarget_hot[7]_i_10
(.I0(\m_axi_awprot[20] [30]),
.I1(\m_axi_awprot[20] [29]),
.I2(\m_axi_awprot[20] [31]),
.I3(\m_axi_awprot[20] [26]),
.I4(\m_axi_awprot[20] [27]),
.I5(\m_axi_awprot[20] [28]),
.O(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hFFFEFFFF))
\m_atarget_hot[7]_i_2
(.I0(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ),
.I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ),
.I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ),
.I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ),
.I4(\m_atarget_hot[7]_i_7_n_0 ),
.O(match));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00000001))
\m_atarget_hot[7]_i_3
(.I0(\m_atarget_hot[7]_i_7_n_0 ),
.I1(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3 ),
.I2(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2 ),
.I3(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0 ),
.I4(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1 ),
.O(\m_atarget_hot[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0008000000000000))
\m_atarget_hot[7]_i_4
(.I0(\m_atarget_hot[7]_i_8_n_0 ),
.I1(\m_axi_awprot[20] [21]),
.I2(\m_axi_awprot[20] [20]),
.I3(\m_axi_awprot[20] [22]),
.I4(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2 ),
.I5(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_5 ));
LUT6 #(
.INIT(64'h0008000000000000))
\m_atarget_hot[7]_i_5
(.I0(\m_atarget_hot[7]_i_8_n_0 ),
.I1(\m_axi_awprot[20] [20]),
.I2(\m_axi_awprot[20] [21]),
.I3(\m_axi_awprot[20] [22]),
.I4(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2 ),
.I5(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_4 ));
LUT6 #(
.INIT(64'h2000000000000000))
\m_atarget_hot[7]_i_6
(.I0(\m_atarget_hot[7]_i_8_n_0 ),
.I1(\m_axi_awprot[20] [22]),
.I2(\m_axi_awprot[20] [20]),
.I3(\m_axi_awprot[20] [21]),
.I4(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2 ),
.I5(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.O(\gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_6 ));
LUT6 #(
.INIT(64'hF7F7F7FFFFFFFFFF))
\m_atarget_hot[7]_i_7
(.I0(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4 ),
.I1(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2 ),
.I2(\m_axi_awprot[20] [22]),
.I3(\m_axi_awprot[20] [20]),
.I4(\m_axi_awprot[20] [21]),
.I5(\m_atarget_hot[7]_i_8_n_0 ),
.O(\m_atarget_hot[7]_i_7_n_0 ));
LUT3 #(
.INIT(8'h01))
\m_atarget_hot[7]_i_8
(.I0(\m_axi_awprot[20] [25]),
.I1(\m_axi_awprot[20] [23]),
.I2(\m_axi_awprot[20] [24]),
.O(\m_atarget_hot[7]_i_8_n_0 ));
LUT4 #(
.INIT(16'h0001))
\m_atarget_hot[7]_i_9
(.I0(\m_axi_awprot[20] [18]),
.I1(\m_axi_awprot[20] [19]),
.I2(\m_axi_awprot[20] [17]),
.I3(\m_axi_awprot[20] [16]),
.O(\gen_addr_decoder.addr_decoder_inst/gen_target[6].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'h2000))
\m_axi_arvalid[0]_INST_0
(.I0(Q[0]),
.I1(m_ready_d[1]),
.I2(aa_grant_rnw),
.I3(m_valid_i),
.O(m_axi_arvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'h2000))
\m_axi_arvalid[1]_INST_0
(.I0(Q[1]),
.I1(m_ready_d[1]),
.I2(aa_grant_rnw),
.I3(m_valid_i),
.O(m_axi_arvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h2000))
\m_axi_arvalid[2]_INST_0
(.I0(Q[2]),
.I1(m_ready_d[1]),
.I2(aa_grant_rnw),
.I3(m_valid_i),
.O(m_axi_arvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h2000))
\m_axi_arvalid[3]_INST_0
(.I0(Q[3]),
.I1(m_ready_d[1]),
.I2(aa_grant_rnw),
.I3(m_valid_i),
.O(m_axi_arvalid[3]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h2000))
\m_axi_arvalid[4]_INST_0
(.I0(Q[4]),
.I1(m_ready_d[1]),
.I2(aa_grant_rnw),
.I3(m_valid_i),
.O(m_axi_arvalid[4]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h2000))
\m_axi_arvalid[5]_INST_0
(.I0(Q[5]),
.I1(m_ready_d[1]),
.I2(aa_grant_rnw),
.I3(m_valid_i),
.O(m_axi_arvalid[5]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h2000))
\m_axi_arvalid[6]_INST_0
(.I0(Q[6]),
.I1(m_ready_d[1]),
.I2(aa_grant_rnw),
.I3(m_valid_i),
.O(m_axi_arvalid[6]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[0]_INST_0
(.I0(Q[0]),
.I1(m_ready_d_0[2]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.O(m_axi_awvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[1]_INST_0
(.I0(Q[1]),
.I1(m_ready_d_0[2]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.O(m_axi_awvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[2]_INST_0
(.I0(Q[2]),
.I1(m_ready_d_0[2]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.O(m_axi_awvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[3]_INST_0
(.I0(Q[3]),
.I1(m_ready_d_0[2]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.O(m_axi_awvalid[3]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[4]_INST_0
(.I0(Q[4]),
.I1(m_ready_d_0[2]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.O(m_axi_awvalid[4]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[5]_INST_0
(.I0(Q[5]),
.I1(m_ready_d_0[2]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.O(m_axi_awvalid[5]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[6]_INST_0
(.I0(Q[6]),
.I1(m_ready_d_0[2]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.O(m_axi_awvalid[6]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h8))
\m_axi_bready[0]_INST_0
(.I0(Q[0]),
.I1(p_3_in),
.O(m_axi_bready[0]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT2 #(
.INIT(4'h8))
\m_axi_bready[1]_INST_0
(.I0(Q[1]),
.I1(p_3_in),
.O(m_axi_bready[1]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT2 #(
.INIT(4'h8))
\m_axi_bready[2]_INST_0
(.I0(Q[2]),
.I1(p_3_in),
.O(m_axi_bready[2]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT2 #(
.INIT(4'h8))
\m_axi_bready[3]_INST_0
(.I0(Q[3]),
.I1(p_3_in),
.O(m_axi_bready[3]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT2 #(
.INIT(4'h8))
\m_axi_bready[4]_INST_0
(.I0(Q[4]),
.I1(p_3_in),
.O(m_axi_bready[4]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h8))
\m_axi_bready[5]_INST_0
(.I0(Q[5]),
.I1(p_3_in),
.O(m_axi_bready[5]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT2 #(
.INIT(4'h8))
\m_axi_bready[6]_INST_0
(.I0(Q[6]),
.I1(p_3_in),
.O(m_axi_bready[6]));
LUT6 #(
.INIT(64'h3B380B0800000000))
\m_axi_bready[6]_INST_0_i_1
(.I0(s_axi_bready[2]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_bready[0]),
.I4(s_axi_bready[1]),
.I5(\s_axi_bvalid[2]_INST_0_i_2_n_0 ),
.O(p_3_in));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[0]_INST_0
(.I0(s_axi_wdata[64]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[0]),
.I4(s_axi_wdata[32]),
.O(m_axi_wdata[0]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[10]_INST_0
(.I0(s_axi_wdata[74]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[10]),
.I4(s_axi_wdata[42]),
.O(m_axi_wdata[10]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[11]_INST_0
(.I0(s_axi_wdata[75]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[11]),
.I4(s_axi_wdata[43]),
.O(m_axi_wdata[11]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[12]_INST_0
(.I0(s_axi_wdata[76]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[12]),
.I4(s_axi_wdata[44]),
.O(m_axi_wdata[12]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[13]_INST_0
(.I0(s_axi_wdata[77]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[13]),
.I4(s_axi_wdata[45]),
.O(m_axi_wdata[13]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[14]_INST_0
(.I0(s_axi_wdata[78]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[14]),
.I4(s_axi_wdata[46]),
.O(m_axi_wdata[14]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[15]_INST_0
(.I0(s_axi_wdata[79]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[15]),
.I4(s_axi_wdata[47]),
.O(m_axi_wdata[15]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[16]_INST_0
(.I0(s_axi_wdata[80]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[16]),
.I4(s_axi_wdata[48]),
.O(m_axi_wdata[16]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[17]_INST_0
(.I0(s_axi_wdata[81]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[17]),
.I4(s_axi_wdata[49]),
.O(m_axi_wdata[17]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[18]_INST_0
(.I0(s_axi_wdata[82]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[18]),
.I4(s_axi_wdata[50]),
.O(m_axi_wdata[18]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[19]_INST_0
(.I0(s_axi_wdata[83]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[19]),
.I4(s_axi_wdata[51]),
.O(m_axi_wdata[19]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[1]_INST_0
(.I0(s_axi_wdata[65]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[1]),
.I4(s_axi_wdata[33]),
.O(m_axi_wdata[1]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[20]_INST_0
(.I0(s_axi_wdata[84]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[20]),
.I4(s_axi_wdata[52]),
.O(m_axi_wdata[20]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[21]_INST_0
(.I0(s_axi_wdata[85]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[21]),
.I4(s_axi_wdata[53]),
.O(m_axi_wdata[21]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[22]_INST_0
(.I0(s_axi_wdata[86]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[22]),
.I4(s_axi_wdata[54]),
.O(m_axi_wdata[22]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[23]_INST_0
(.I0(s_axi_wdata[87]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[23]),
.I4(s_axi_wdata[55]),
.O(m_axi_wdata[23]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[24]_INST_0
(.I0(s_axi_wdata[88]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[24]),
.I4(s_axi_wdata[56]),
.O(m_axi_wdata[24]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[25]_INST_0
(.I0(s_axi_wdata[89]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[25]),
.I4(s_axi_wdata[57]),
.O(m_axi_wdata[25]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[26]_INST_0
(.I0(s_axi_wdata[90]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[26]),
.I4(s_axi_wdata[58]),
.O(m_axi_wdata[26]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[27]_INST_0
(.I0(s_axi_wdata[91]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[27]),
.I4(s_axi_wdata[59]),
.O(m_axi_wdata[27]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[28]_INST_0
(.I0(s_axi_wdata[92]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[28]),
.I4(s_axi_wdata[60]),
.O(m_axi_wdata[28]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[29]_INST_0
(.I0(s_axi_wdata[93]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[29]),
.I4(s_axi_wdata[61]),
.O(m_axi_wdata[29]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[2]_INST_0
(.I0(s_axi_wdata[66]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[2]),
.I4(s_axi_wdata[34]),
.O(m_axi_wdata[2]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[30]_INST_0
(.I0(s_axi_wdata[94]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[30]),
.I4(s_axi_wdata[62]),
.O(m_axi_wdata[30]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[31]_INST_0
(.I0(s_axi_wdata[95]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[31]),
.I4(s_axi_wdata[63]),
.O(m_axi_wdata[31]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[3]_INST_0
(.I0(s_axi_wdata[67]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[3]),
.I4(s_axi_wdata[35]),
.O(m_axi_wdata[3]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[4]_INST_0
(.I0(s_axi_wdata[68]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[4]),
.I4(s_axi_wdata[36]),
.O(m_axi_wdata[4]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[5]_INST_0
(.I0(s_axi_wdata[69]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[5]),
.I4(s_axi_wdata[37]),
.O(m_axi_wdata[5]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[6]_INST_0
(.I0(s_axi_wdata[70]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[6]),
.I4(s_axi_wdata[38]),
.O(m_axi_wdata[6]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[7]_INST_0
(.I0(s_axi_wdata[71]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[7]),
.I4(s_axi_wdata[39]),
.O(m_axi_wdata[7]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[8]_INST_0
(.I0(s_axi_wdata[72]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[8]),
.I4(s_axi_wdata[40]),
.O(m_axi_wdata[8]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wdata[9]_INST_0
(.I0(s_axi_wdata[73]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wdata[9]),
.I4(s_axi_wdata[41]),
.O(m_axi_wdata[9]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wstrb[0]_INST_0
(.I0(s_axi_wstrb[8]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wstrb[0]),
.I4(s_axi_wstrb[4]),
.O(m_axi_wstrb[0]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wstrb[1]_INST_0
(.I0(s_axi_wstrb[9]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wstrb[1]),
.I4(s_axi_wstrb[5]),
.O(m_axi_wstrb[1]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wstrb[2]_INST_0
(.I0(s_axi_wstrb[10]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wstrb[2]),
.I4(s_axi_wstrb[6]),
.O(m_axi_wstrb[2]));
LUT5 #(
.INIT(32'h3B380B08))
\m_axi_wstrb[3]_INST_0
(.I0(s_axi_wstrb[11]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_wstrb[3]),
.I4(s_axi_wstrb[7]),
.O(m_axi_wstrb[3]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h8))
\m_axi_wvalid[0]_INST_0
(.I0(Q[0]),
.I1(aa_wvalid),
.O(m_axi_wvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT2 #(
.INIT(4'h8))
\m_axi_wvalid[1]_INST_0
(.I0(Q[1]),
.I1(aa_wvalid),
.O(m_axi_wvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT2 #(
.INIT(4'h8))
\m_axi_wvalid[2]_INST_0
(.I0(Q[2]),
.I1(aa_wvalid),
.O(m_axi_wvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT2 #(
.INIT(4'h8))
\m_axi_wvalid[3]_INST_0
(.I0(Q[3]),
.I1(aa_wvalid),
.O(m_axi_wvalid[3]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT2 #(
.INIT(4'h8))
\m_axi_wvalid[4]_INST_0
(.I0(Q[4]),
.I1(aa_wvalid),
.O(m_axi_wvalid[4]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h8))
\m_axi_wvalid[5]_INST_0
(.I0(Q[5]),
.I1(aa_wvalid),
.O(m_axi_wvalid[5]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT2 #(
.INIT(4'h8))
\m_axi_wvalid[6]_INST_0
(.I0(Q[6]),
.I1(aa_wvalid),
.O(m_axi_wvalid[6]));
LUT6 #(
.INIT(64'h00AA88A0000088A0))
\m_axi_wvalid[6]_INST_0_i_1
(.I0(\s_axi_wready[2]_INST_0_i_2_n_0 ),
.I1(s_axi_wvalid[1]),
.I2(s_axi_wvalid[0]),
.I3(aa_grant_enc[0]),
.I4(aa_grant_enc[1]),
.I5(s_axi_wvalid[2]),
.O(aa_wvalid));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT2 #(
.INIT(4'hB))
\m_payload_i[34]_i_1
(.I0(p_2_in),
.I1(sr_rvalid),
.O(E));
LUT6 #(
.INIT(64'h3B380B0800000000))
\m_payload_i[34]_i_3
(.I0(s_axi_rready[2]),
.I1(aa_grant_enc[1]),
.I2(aa_grant_enc[0]),
.I3(s_axi_rready[0]),
.I4(s_axi_rready[1]),
.I5(\m_payload_i[34]_i_4_n_0 ),
.O(p_2_in));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h08))
\m_payload_i[34]_i_4
(.I0(m_valid_i),
.I1(aa_grant_rnw),
.I2(m_ready_d[0]),
.O(\m_payload_i[34]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hFFFF0800))
\m_ready_d[0]_i_2
(.I0(p_3_in),
.I1(aa_bvalid),
.I2(aa_grant_rnw),
.I3(m_valid_i),
.I4(m_ready_d_0[0]),
.O(m_ready_d0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h7000))
\m_ready_d[1]_i_2
(.I0(aa_grant_enc[1]),
.I1(aa_grant_enc[0]),
.I2(aa_wready),
.I3(aa_wvalid),
.O(\m_ready_d_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h08))
\m_ready_d[1]_i_2__0
(.I0(m_valid_i),
.I1(aa_grant_rnw),
.I2(m_ready_d[1]),
.O(\m_ready_d_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h070707FF))
\m_ready_d[1]_i_3__0
(.I0(p_3_in),
.I1(aa_bvalid),
.I2(m_ready_d_0[0]),
.I3(mi_awready_mux),
.I4(m_ready_d_0[2]),
.O(\gen_arbiter.m_valid_i_reg_0 ));
LUT5 #(
.INIT(32'hAAAAAAA8))
\m_ready_d[1]_i_4
(.I0(\m_ready_d_reg[1] ),
.I1(\m_ready_d[1]_i_5_n_0 ),
.I2(\gen_axilite.s_axi_arready_i_reg ),
.I3(\m_ready_d[1]_i_7_n_0 ),
.I4(\m_ready_d[1]_i_8_n_0 ),
.O(mi_arready_mux));
LUT5 #(
.INIT(32'h0C00A000))
\m_ready_d[1]_i_5
(.I0(m_axi_arready[4]),
.I1(m_axi_arready[5]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.O(\m_ready_d[1]_i_5_n_0 ));
LUT5 #(
.INIT(32'h000A00C0))
\m_ready_d[1]_i_7
(.I0(m_axi_arready[1]),
.I1(m_axi_arready[0]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.O(\m_ready_d[1]_i_7_n_0 ));
LUT5 #(
.INIT(32'h0A0000C0))
\m_ready_d[1]_i_8
(.I0(m_axi_arready[2]),
.I1(m_axi_arready[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\m_ready_d[1]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'h04))
\m_ready_d[2]_i_2
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.I2(m_ready_d_0[2]),
.O(\gen_axilite.s_axi_bvalid_i_reg ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hAAEAEAEA))
\m_ready_d[2]_i_3
(.I0(m_ready_d_0[1]),
.I1(aa_wvalid),
.I2(aa_wready),
.I3(aa_grant_enc[0]),
.I4(aa_grant_enc[1]),
.O(\gen_arbiter.m_valid_i_reg_1 [1]));
LUT5 #(
.INIT(32'hAAAAAAA8))
\m_ready_d[2]_i_4
(.I0(\gen_axilite.s_axi_bvalid_i_reg ),
.I1(\m_atarget_enc_reg[0]_4 ),
.I2(\gen_axilite.s_axi_awready_i_reg_0 ),
.I3(\m_atarget_enc_reg[0]_5 ),
.I4(\m_atarget_enc_reg[2]_2 ),
.O(mi_awready_mux));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hEA))
\m_ready_d[2]_i_5
(.I0(m_ready_d_0[0]),
.I1(aa_bvalid),
.I2(p_3_in),
.O(\gen_arbiter.m_valid_i_reg_1 [0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h40404000))
m_valid_i_i_2
(.I0(m_ready_d[0]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(\m_atarget_enc_reg[1]_0 ),
.I4(\m_atarget_enc_reg[1]_1 ),
.O(aa_rvalid));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h2))
\s_arvalid_reg[0]_i_1
(.I0(s_axi_arvalid[0]),
.I1(s_awvalid_reg[0]),
.O(\s_arvalid_reg[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h2))
\s_arvalid_reg[1]_i_1
(.I0(s_axi_arvalid[1]),
.I1(s_awvalid_reg[1]),
.O(\s_arvalid_reg[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFEFF))
\s_arvalid_reg[2]_i_1
(.I0(s_ready_i[0]),
.I1(s_ready_i[2]),
.I2(s_ready_i[1]),
.I3(aresetn_d),
.O(\s_arvalid_reg[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h2))
\s_arvalid_reg[2]_i_2
(.I0(s_axi_arvalid[2]),
.I1(s_awvalid_reg[2]),
.O(\s_arvalid_reg[2]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\s_arvalid_reg_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_arvalid_reg[0]_i_1_n_0 ),
.Q(\s_arvalid_reg_reg_n_0_[0] ),
.R(\s_arvalid_reg[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_arvalid_reg_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_arvalid_reg[1]_i_1_n_0 ),
.Q(\s_arvalid_reg_reg_n_0_[1] ),
.R(\s_arvalid_reg[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_arvalid_reg_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\s_arvalid_reg[2]_i_2_n_0 ),
.Q(\s_arvalid_reg_reg_n_0_[2] ),
.R(\s_arvalid_reg[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h4500))
\s_awvalid_reg[0]_i_1
(.I0(\s_arvalid_reg_reg_n_0_[0] ),
.I1(s_awvalid_reg[0]),
.I2(s_axi_arvalid[0]),
.I3(s_axi_awvalid[0]),
.O(s_awvalid_reg0[0]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h4500))
\s_awvalid_reg[1]_i_1
(.I0(\s_arvalid_reg_reg_n_0_[1] ),
.I1(s_awvalid_reg[1]),
.I2(s_axi_arvalid[1]),
.I3(s_axi_awvalid[1]),
.O(s_awvalid_reg0[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h4500))
\s_awvalid_reg[2]_i_1
(.I0(\s_arvalid_reg_reg_n_0_[2] ),
.I1(s_awvalid_reg[2]),
.I2(s_axi_arvalid[2]),
.I3(s_axi_awvalid[2]),
.O(s_awvalid_reg0[2]));
FDRE #(
.INIT(1'b0))
\s_awvalid_reg_reg[0]
(.C(aclk),
.CE(1'b1),
.D(s_awvalid_reg0[0]),
.Q(s_awvalid_reg[0]),
.R(\s_arvalid_reg[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_awvalid_reg_reg[1]
(.C(aclk),
.CE(1'b1),
.D(s_awvalid_reg0[1]),
.Q(s_awvalid_reg[1]),
.R(\s_arvalid_reg[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_awvalid_reg_reg[2]
(.C(aclk),
.CE(1'b1),
.D(s_awvalid_reg0[2]),
.Q(s_awvalid_reg[2]),
.R(\s_arvalid_reg[2]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\s_axi_arready[0]_INST_0
(.I0(s_ready_i[0]),
.I1(aa_grant_rnw),
.O(s_axi_arready[0]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'h8))
\s_axi_arready[1]_INST_0
(.I0(s_ready_i[1]),
.I1(aa_grant_rnw),
.O(s_axi_arready[1]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h8))
\s_axi_arready[2]_INST_0
(.I0(s_ready_i[2]),
.I1(aa_grant_rnw),
.O(s_axi_arready[2]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h2))
\s_axi_awready[0]_INST_0
(.I0(s_ready_i[0]),
.I1(aa_grant_rnw),
.O(s_axi_awready[0]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'h2))
\s_axi_awready[1]_INST_0
(.I0(s_ready_i[1]),
.I1(aa_grant_rnw),
.O(s_axi_awready[1]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h2))
\s_axi_awready[2]_INST_0
(.I0(s_ready_i[2]),
.I1(aa_grant_rnw),
.O(s_axi_awready[2]));
LUT2 #(
.INIT(4'h8))
\s_axi_bvalid[0]_INST_0
(.I0(aa_grant_hot[0]),
.I1(aa_bvalid),
.O(s_axi_bvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT2 #(
.INIT(4'h8))
\s_axi_bvalid[1]_INST_0
(.I0(aa_grant_hot[1]),
.I1(aa_bvalid),
.O(s_axi_bvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT2 #(
.INIT(4'h8))
\s_axi_bvalid[2]_INST_0
(.I0(aa_grant_hot[2]),
.I1(aa_bvalid),
.O(s_axi_bvalid[2]));
LUT5 #(
.INIT(32'hAAAAAAA8))
\s_axi_bvalid[2]_INST_0_i_1
(.I0(\s_axi_bvalid[2]_INST_0_i_2_n_0 ),
.I1(\m_atarget_enc_reg[0]_1 ),
.I2(\gen_axilite.s_axi_bvalid_i_reg_1 ),
.I3(\m_atarget_enc_reg[0]_0 ),
.I4(\m_atarget_enc_reg[2]_0 ),
.O(aa_bvalid));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h04))
\s_axi_bvalid[2]_INST_0_i_2
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.I2(m_ready_d_0[0]),
.O(\s_axi_bvalid[2]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT2 #(
.INIT(4'h8))
\s_axi_rvalid[0]_INST_0
(.I0(aa_grant_hot[0]),
.I1(sr_rvalid),
.O(s_axi_rvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT2 #(
.INIT(4'h8))
\s_axi_rvalid[1]_INST_0
(.I0(aa_grant_hot[1]),
.I1(sr_rvalid),
.O(s_axi_rvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT2 #(
.INIT(4'h8))
\s_axi_rvalid[2]_INST_0
(.I0(aa_grant_hot[2]),
.I1(sr_rvalid),
.O(s_axi_rvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\s_axi_wready[0]_INST_0
(.I0(aa_grant_hot[0]),
.I1(aa_wready),
.O(s_axi_wready[0]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT2 #(
.INIT(4'h8))
\s_axi_wready[1]_INST_0
(.I0(aa_grant_hot[1]),
.I1(aa_wready),
.O(s_axi_wready[1]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT2 #(
.INIT(4'h8))
\s_axi_wready[2]_INST_0
(.I0(aa_grant_hot[2]),
.I1(aa_wready),
.O(s_axi_wready[2]));
LUT5 #(
.INIT(32'hAAAAAAA8))
\s_axi_wready[2]_INST_0_i_1
(.I0(\s_axi_wready[2]_INST_0_i_2_n_0 ),
.I1(\m_atarget_enc_reg[0]_3 ),
.I2(\gen_axilite.s_axi_awready_i_reg ),
.I3(\m_atarget_enc_reg[0]_2 ),
.I4(\m_atarget_enc_reg[2]_1 ),
.O(aa_wready));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'h04))
\s_axi_wready[2]_INST_0_i_2
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.I2(m_ready_d_0[1]),
.O(\s_axi_wready[2]_INST_0_i_2_n_0 ));
endmodule
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_PROTOCOL = "2" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "0" *) (* C_DEBUG = "1" *)
(* C_FAMILY = "artix7" *) (* C_M_AXI_ADDR_WIDTH = "224'b00000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100" *) (* C_M_AXI_BASE_ADDR = "448'b0000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "224'b00000000000000000000000000000111000000000000000000000000000001110000000000000000000000000000011100000000000000000000000000000111000000000000000000000000000001110000000000000000000000000000011100000000000000000000000000000111" *) (* C_M_AXI_READ_ISSUING = "224'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_SECURE = "224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "224'b00000000000000000000000000000111000000000000000000000000000001110000000000000000000000000000011100000000000000000000000000000111000000000000000000000000000001110000000000000000000000000000011100000000000000000000000000000111" *) (* C_M_AXI_WRITE_ISSUING = "224'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "7" *) (* C_NUM_SLAVE_SLOTS = "3" *) (* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_S_AXI_BASE_ID = "96'b000000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000000" *) (* C_S_AXI_READ_ACCEPTANCE = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_S_AXI_SINGLE_THREAD = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_S_AXI_THREAD_ID_WIDTH = "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_S_AXI_WRITE_ACCEPTANCE = "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* P_ADDR_DECODE = "1" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "artix7" *) (* P_INCR = "2'b01" *) (* P_LEN = "8" *)
(* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "224'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* P_M_AXI_SUPPORTS_READ = "7'b1111111" *)
(* P_M_AXI_SUPPORTS_WRITE = "7'b1111111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) (* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_SUPPORTS_READ = "3'b111" *)
(* P_S_AXI_SUPPORTS_WRITE = "3'b111" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_axi_crossbar
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [2:0]s_axi_awid;
input [95:0]s_axi_awaddr;
input [23:0]s_axi_awlen;
input [8:0]s_axi_awsize;
input [5:0]s_axi_awburst;
input [2:0]s_axi_awlock;
input [11:0]s_axi_awcache;
input [8:0]s_axi_awprot;
input [11:0]s_axi_awqos;
input [2:0]s_axi_awuser;
input [2:0]s_axi_awvalid;
output [2:0]s_axi_awready;
input [2:0]s_axi_wid;
input [95:0]s_axi_wdata;
input [11:0]s_axi_wstrb;
input [2:0]s_axi_wlast;
input [2:0]s_axi_wuser;
input [2:0]s_axi_wvalid;
output [2:0]s_axi_wready;
output [2:0]s_axi_bid;
output [5:0]s_axi_bresp;
output [2:0]s_axi_buser;
output [2:0]s_axi_bvalid;
input [2:0]s_axi_bready;
input [2:0]s_axi_arid;
input [95:0]s_axi_araddr;
input [23:0]s_axi_arlen;
input [8:0]s_axi_arsize;
input [5:0]s_axi_arburst;
input [2:0]s_axi_arlock;
input [11:0]s_axi_arcache;
input [8:0]s_axi_arprot;
input [11:0]s_axi_arqos;
input [2:0]s_axi_aruser;
input [2:0]s_axi_arvalid;
output [2:0]s_axi_arready;
output [2:0]s_axi_rid;
output [95:0]s_axi_rdata;
output [5:0]s_axi_rresp;
output [2:0]s_axi_rlast;
output [2:0]s_axi_ruser;
output [2:0]s_axi_rvalid;
input [2:0]s_axi_rready;
output [6:0]m_axi_awid;
output [223:0]m_axi_awaddr;
output [55:0]m_axi_awlen;
output [20:0]m_axi_awsize;
output [13:0]m_axi_awburst;
output [6:0]m_axi_awlock;
output [27:0]m_axi_awcache;
output [20:0]m_axi_awprot;
output [27:0]m_axi_awregion;
output [27:0]m_axi_awqos;
output [6:0]m_axi_awuser;
output [6:0]m_axi_awvalid;
input [6:0]m_axi_awready;
output [6:0]m_axi_wid;
output [223:0]m_axi_wdata;
output [27:0]m_axi_wstrb;
output [6:0]m_axi_wlast;
output [6:0]m_axi_wuser;
output [6:0]m_axi_wvalid;
input [6:0]m_axi_wready;
input [6:0]m_axi_bid;
input [13:0]m_axi_bresp;
input [6:0]m_axi_buser;
input [6:0]m_axi_bvalid;
output [6:0]m_axi_bready;
output [6:0]m_axi_arid;
output [223:0]m_axi_araddr;
output [55:0]m_axi_arlen;
output [20:0]m_axi_arsize;
output [13:0]m_axi_arburst;
output [6:0]m_axi_arlock;
output [27:0]m_axi_arcache;
output [20:0]m_axi_arprot;
output [27:0]m_axi_arregion;
output [27:0]m_axi_arqos;
output [6:0]m_axi_aruser;
output [6:0]m_axi_arvalid;
input [6:0]m_axi_arready;
input [6:0]m_axi_rid;
input [223:0]m_axi_rdata;
input [13:0]m_axi_rresp;
input [6:0]m_axi_rlast;
input [6:0]m_axi_ruser;
input [6:0]m_axi_rvalid;
output [6:0]m_axi_rready;
wire \<const0> ;
wire aclk;
wire aresetn;
wire [31:12]\^m_axi_araddr ;
wire [6:0]m_axi_arready;
wire [6:0]m_axi_arvalid;
wire [203:192]\^m_axi_awaddr ;
wire [20:18]\^m_axi_awprot ;
wire [6:0]m_axi_awready;
wire [6:0]m_axi_awvalid;
wire [6:0]m_axi_bready;
wire [13:0]m_axi_bresp;
wire [6:0]m_axi_bvalid;
wire [223:0]m_axi_rdata;
wire [6:0]m_axi_rready;
wire [13:0]m_axi_rresp;
wire [6:0]m_axi_rvalid;
wire [223:192]\^m_axi_wdata ;
wire [6:0]m_axi_wready;
wire [27:24]\^m_axi_wstrb ;
wire [6:0]m_axi_wvalid;
wire [95:0]s_axi_araddr;
wire [8:0]s_axi_arprot;
wire [2:0]s_axi_arready;
wire [2:0]s_axi_arvalid;
wire [95:0]s_axi_awaddr;
wire [8:0]s_axi_awprot;
wire [2:0]s_axi_awready;
wire [2:0]s_axi_awvalid;
wire [2:0]s_axi_bready;
wire [5:4]\^s_axi_bresp ;
wire [2:0]s_axi_bvalid;
wire [95:64]\^s_axi_rdata ;
wire [2:0]s_axi_rready;
wire [5:4]\^s_axi_rresp ;
wire [2:0]s_axi_rvalid;
wire [95:0]s_axi_wdata;
wire [2:0]s_axi_wready;
wire [11:0]s_axi_wstrb;
wire [2:0]s_axi_wvalid;
assign m_axi_araddr[223:204] = \^m_axi_araddr [31:12];
assign m_axi_araddr[203:192] = \^m_axi_awaddr [203:192];
assign m_axi_araddr[191:172] = \^m_axi_araddr [31:12];
assign m_axi_araddr[171:160] = \^m_axi_awaddr [203:192];
assign m_axi_araddr[159:140] = \^m_axi_araddr [31:12];
assign m_axi_araddr[139:128] = \^m_axi_awaddr [203:192];
assign m_axi_araddr[127:108] = \^m_axi_araddr [31:12];
assign m_axi_araddr[107:96] = \^m_axi_awaddr [203:192];
assign m_axi_araddr[95:76] = \^m_axi_araddr [31:12];
assign m_axi_araddr[75:64] = \^m_axi_awaddr [203:192];
assign m_axi_araddr[63:44] = \^m_axi_araddr [31:12];
assign m_axi_araddr[43:32] = \^m_axi_awaddr [203:192];
assign m_axi_araddr[31:12] = \^m_axi_araddr [31:12];
assign m_axi_araddr[11:0] = \^m_axi_awaddr [203:192];
assign m_axi_arburst[13] = \<const0> ;
assign m_axi_arburst[12] = \<const0> ;
assign m_axi_arburst[11] = \<const0> ;
assign m_axi_arburst[10] = \<const0> ;
assign m_axi_arburst[9] = \<const0> ;
assign m_axi_arburst[8] = \<const0> ;
assign m_axi_arburst[7] = \<const0> ;
assign m_axi_arburst[6] = \<const0> ;
assign m_axi_arburst[5] = \<const0> ;
assign m_axi_arburst[4] = \<const0> ;
assign m_axi_arburst[3] = \<const0> ;
assign m_axi_arburst[2] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[27] = \<const0> ;
assign m_axi_arcache[26] = \<const0> ;
assign m_axi_arcache[25] = \<const0> ;
assign m_axi_arcache[24] = \<const0> ;
assign m_axi_arcache[23] = \<const0> ;
assign m_axi_arcache[22] = \<const0> ;
assign m_axi_arcache[21] = \<const0> ;
assign m_axi_arcache[20] = \<const0> ;
assign m_axi_arcache[19] = \<const0> ;
assign m_axi_arcache[18] = \<const0> ;
assign m_axi_arcache[17] = \<const0> ;
assign m_axi_arcache[16] = \<const0> ;
assign m_axi_arcache[15] = \<const0> ;
assign m_axi_arcache[14] = \<const0> ;
assign m_axi_arcache[13] = \<const0> ;
assign m_axi_arcache[12] = \<const0> ;
assign m_axi_arcache[11] = \<const0> ;
assign m_axi_arcache[10] = \<const0> ;
assign m_axi_arcache[9] = \<const0> ;
assign m_axi_arcache[8] = \<const0> ;
assign m_axi_arcache[7] = \<const0> ;
assign m_axi_arcache[6] = \<const0> ;
assign m_axi_arcache[5] = \<const0> ;
assign m_axi_arcache[4] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[6] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[55] = \<const0> ;
assign m_axi_arlen[54] = \<const0> ;
assign m_axi_arlen[53] = \<const0> ;
assign m_axi_arlen[52] = \<const0> ;
assign m_axi_arlen[51] = \<const0> ;
assign m_axi_arlen[50] = \<const0> ;
assign m_axi_arlen[49] = \<const0> ;
assign m_axi_arlen[48] = \<const0> ;
assign m_axi_arlen[47] = \<const0> ;
assign m_axi_arlen[46] = \<const0> ;
assign m_axi_arlen[45] = \<const0> ;
assign m_axi_arlen[44] = \<const0> ;
assign m_axi_arlen[43] = \<const0> ;
assign m_axi_arlen[42] = \<const0> ;
assign m_axi_arlen[41] = \<const0> ;
assign m_axi_arlen[40] = \<const0> ;
assign m_axi_arlen[39] = \<const0> ;
assign m_axi_arlen[38] = \<const0> ;
assign m_axi_arlen[37] = \<const0> ;
assign m_axi_arlen[36] = \<const0> ;
assign m_axi_arlen[35] = \<const0> ;
assign m_axi_arlen[34] = \<const0> ;
assign m_axi_arlen[33] = \<const0> ;
assign m_axi_arlen[32] = \<const0> ;
assign m_axi_arlen[31] = \<const0> ;
assign m_axi_arlen[30] = \<const0> ;
assign m_axi_arlen[29] = \<const0> ;
assign m_axi_arlen[28] = \<const0> ;
assign m_axi_arlen[27] = \<const0> ;
assign m_axi_arlen[26] = \<const0> ;
assign m_axi_arlen[25] = \<const0> ;
assign m_axi_arlen[24] = \<const0> ;
assign m_axi_arlen[23] = \<const0> ;
assign m_axi_arlen[22] = \<const0> ;
assign m_axi_arlen[21] = \<const0> ;
assign m_axi_arlen[20] = \<const0> ;
assign m_axi_arlen[19] = \<const0> ;
assign m_axi_arlen[18] = \<const0> ;
assign m_axi_arlen[17] = \<const0> ;
assign m_axi_arlen[16] = \<const0> ;
assign m_axi_arlen[15] = \<const0> ;
assign m_axi_arlen[14] = \<const0> ;
assign m_axi_arlen[13] = \<const0> ;
assign m_axi_arlen[12] = \<const0> ;
assign m_axi_arlen[11] = \<const0> ;
assign m_axi_arlen[10] = \<const0> ;
assign m_axi_arlen[9] = \<const0> ;
assign m_axi_arlen[8] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[6] = \<const0> ;
assign m_axi_arlock[5] = \<const0> ;
assign m_axi_arlock[4] = \<const0> ;
assign m_axi_arlock[3] = \<const0> ;
assign m_axi_arlock[2] = \<const0> ;
assign m_axi_arlock[1] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[20:18] = \^m_axi_awprot [20:18];
assign m_axi_arprot[17:15] = \^m_axi_awprot [20:18];
assign m_axi_arprot[14:12] = \^m_axi_awprot [20:18];
assign m_axi_arprot[11:9] = \^m_axi_awprot [20:18];
assign m_axi_arprot[8:6] = \^m_axi_awprot [20:18];
assign m_axi_arprot[5:3] = \^m_axi_awprot [20:18];
assign m_axi_arprot[2:0] = \^m_axi_awprot [20:18];
assign m_axi_arqos[27] = \<const0> ;
assign m_axi_arqos[26] = \<const0> ;
assign m_axi_arqos[25] = \<const0> ;
assign m_axi_arqos[24] = \<const0> ;
assign m_axi_arqos[23] = \<const0> ;
assign m_axi_arqos[22] = \<const0> ;
assign m_axi_arqos[21] = \<const0> ;
assign m_axi_arqos[20] = \<const0> ;
assign m_axi_arqos[19] = \<const0> ;
assign m_axi_arqos[18] = \<const0> ;
assign m_axi_arqos[17] = \<const0> ;
assign m_axi_arqos[16] = \<const0> ;
assign m_axi_arqos[15] = \<const0> ;
assign m_axi_arqos[14] = \<const0> ;
assign m_axi_arqos[13] = \<const0> ;
assign m_axi_arqos[12] = \<const0> ;
assign m_axi_arqos[11] = \<const0> ;
assign m_axi_arqos[10] = \<const0> ;
assign m_axi_arqos[9] = \<const0> ;
assign m_axi_arqos[8] = \<const0> ;
assign m_axi_arqos[7] = \<const0> ;
assign m_axi_arqos[6] = \<const0> ;
assign m_axi_arqos[5] = \<const0> ;
assign m_axi_arqos[4] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[27] = \<const0> ;
assign m_axi_arregion[26] = \<const0> ;
assign m_axi_arregion[25] = \<const0> ;
assign m_axi_arregion[24] = \<const0> ;
assign m_axi_arregion[23] = \<const0> ;
assign m_axi_arregion[22] = \<const0> ;
assign m_axi_arregion[21] = \<const0> ;
assign m_axi_arregion[20] = \<const0> ;
assign m_axi_arregion[19] = \<const0> ;
assign m_axi_arregion[18] = \<const0> ;
assign m_axi_arregion[17] = \<const0> ;
assign m_axi_arregion[16] = \<const0> ;
assign m_axi_arregion[15] = \<const0> ;
assign m_axi_arregion[14] = \<const0> ;
assign m_axi_arregion[13] = \<const0> ;
assign m_axi_arregion[12] = \<const0> ;
assign m_axi_arregion[11] = \<const0> ;
assign m_axi_arregion[10] = \<const0> ;
assign m_axi_arregion[9] = \<const0> ;
assign m_axi_arregion[8] = \<const0> ;
assign m_axi_arregion[7] = \<const0> ;
assign m_axi_arregion[6] = \<const0> ;
assign m_axi_arregion[5] = \<const0> ;
assign m_axi_arregion[4] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[20] = \<const0> ;
assign m_axi_arsize[19] = \<const0> ;
assign m_axi_arsize[18] = \<const0> ;
assign m_axi_arsize[17] = \<const0> ;
assign m_axi_arsize[16] = \<const0> ;
assign m_axi_arsize[15] = \<const0> ;
assign m_axi_arsize[14] = \<const0> ;
assign m_axi_arsize[13] = \<const0> ;
assign m_axi_arsize[12] = \<const0> ;
assign m_axi_arsize[11] = \<const0> ;
assign m_axi_arsize[10] = \<const0> ;
assign m_axi_arsize[9] = \<const0> ;
assign m_axi_arsize[8] = \<const0> ;
assign m_axi_arsize[7] = \<const0> ;
assign m_axi_arsize[6] = \<const0> ;
assign m_axi_arsize[5] = \<const0> ;
assign m_axi_arsize[4] = \<const0> ;
assign m_axi_arsize[3] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[6] = \<const0> ;
assign m_axi_aruser[5] = \<const0> ;
assign m_axi_aruser[4] = \<const0> ;
assign m_axi_aruser[3] = \<const0> ;
assign m_axi_aruser[2] = \<const0> ;
assign m_axi_aruser[1] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awaddr[223:204] = \^m_axi_araddr [31:12];
assign m_axi_awaddr[203:192] = \^m_axi_awaddr [203:192];
assign m_axi_awaddr[191:172] = \^m_axi_araddr [31:12];
assign m_axi_awaddr[171:160] = \^m_axi_awaddr [203:192];
assign m_axi_awaddr[159:140] = \^m_axi_araddr [31:12];
assign m_axi_awaddr[139:128] = \^m_axi_awaddr [203:192];
assign m_axi_awaddr[127:108] = \^m_axi_araddr [31:12];
assign m_axi_awaddr[107:96] = \^m_axi_awaddr [203:192];
assign m_axi_awaddr[95:76] = \^m_axi_araddr [31:12];
assign m_axi_awaddr[75:64] = \^m_axi_awaddr [203:192];
assign m_axi_awaddr[63:44] = \^m_axi_araddr [31:12];
assign m_axi_awaddr[43:32] = \^m_axi_awaddr [203:192];
assign m_axi_awaddr[31:12] = \^m_axi_araddr [31:12];
assign m_axi_awaddr[11:0] = \^m_axi_awaddr [203:192];
assign m_axi_awburst[13] = \<const0> ;
assign m_axi_awburst[12] = \<const0> ;
assign m_axi_awburst[11] = \<const0> ;
assign m_axi_awburst[10] = \<const0> ;
assign m_axi_awburst[9] = \<const0> ;
assign m_axi_awburst[8] = \<const0> ;
assign m_axi_awburst[7] = \<const0> ;
assign m_axi_awburst[6] = \<const0> ;
assign m_axi_awburst[5] = \<const0> ;
assign m_axi_awburst[4] = \<const0> ;
assign m_axi_awburst[3] = \<const0> ;
assign m_axi_awburst[2] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[27] = \<const0> ;
assign m_axi_awcache[26] = \<const0> ;
assign m_axi_awcache[25] = \<const0> ;
assign m_axi_awcache[24] = \<const0> ;
assign m_axi_awcache[23] = \<const0> ;
assign m_axi_awcache[22] = \<const0> ;
assign m_axi_awcache[21] = \<const0> ;
assign m_axi_awcache[20] = \<const0> ;
assign m_axi_awcache[19] = \<const0> ;
assign m_axi_awcache[18] = \<const0> ;
assign m_axi_awcache[17] = \<const0> ;
assign m_axi_awcache[16] = \<const0> ;
assign m_axi_awcache[15] = \<const0> ;
assign m_axi_awcache[14] = \<const0> ;
assign m_axi_awcache[13] = \<const0> ;
assign m_axi_awcache[12] = \<const0> ;
assign m_axi_awcache[11] = \<const0> ;
assign m_axi_awcache[10] = \<const0> ;
assign m_axi_awcache[9] = \<const0> ;
assign m_axi_awcache[8] = \<const0> ;
assign m_axi_awcache[7] = \<const0> ;
assign m_axi_awcache[6] = \<const0> ;
assign m_axi_awcache[5] = \<const0> ;
assign m_axi_awcache[4] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[6] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[55] = \<const0> ;
assign m_axi_awlen[54] = \<const0> ;
assign m_axi_awlen[53] = \<const0> ;
assign m_axi_awlen[52] = \<const0> ;
assign m_axi_awlen[51] = \<const0> ;
assign m_axi_awlen[50] = \<const0> ;
assign m_axi_awlen[49] = \<const0> ;
assign m_axi_awlen[48] = \<const0> ;
assign m_axi_awlen[47] = \<const0> ;
assign m_axi_awlen[46] = \<const0> ;
assign m_axi_awlen[45] = \<const0> ;
assign m_axi_awlen[44] = \<const0> ;
assign m_axi_awlen[43] = \<const0> ;
assign m_axi_awlen[42] = \<const0> ;
assign m_axi_awlen[41] = \<const0> ;
assign m_axi_awlen[40] = \<const0> ;
assign m_axi_awlen[39] = \<const0> ;
assign m_axi_awlen[38] = \<const0> ;
assign m_axi_awlen[37] = \<const0> ;
assign m_axi_awlen[36] = \<const0> ;
assign m_axi_awlen[35] = \<const0> ;
assign m_axi_awlen[34] = \<const0> ;
assign m_axi_awlen[33] = \<const0> ;
assign m_axi_awlen[32] = \<const0> ;
assign m_axi_awlen[31] = \<const0> ;
assign m_axi_awlen[30] = \<const0> ;
assign m_axi_awlen[29] = \<const0> ;
assign m_axi_awlen[28] = \<const0> ;
assign m_axi_awlen[27] = \<const0> ;
assign m_axi_awlen[26] = \<const0> ;
assign m_axi_awlen[25] = \<const0> ;
assign m_axi_awlen[24] = \<const0> ;
assign m_axi_awlen[23] = \<const0> ;
assign m_axi_awlen[22] = \<const0> ;
assign m_axi_awlen[21] = \<const0> ;
assign m_axi_awlen[20] = \<const0> ;
assign m_axi_awlen[19] = \<const0> ;
assign m_axi_awlen[18] = \<const0> ;
assign m_axi_awlen[17] = \<const0> ;
assign m_axi_awlen[16] = \<const0> ;
assign m_axi_awlen[15] = \<const0> ;
assign m_axi_awlen[14] = \<const0> ;
assign m_axi_awlen[13] = \<const0> ;
assign m_axi_awlen[12] = \<const0> ;
assign m_axi_awlen[11] = \<const0> ;
assign m_axi_awlen[10] = \<const0> ;
assign m_axi_awlen[9] = \<const0> ;
assign m_axi_awlen[8] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[6] = \<const0> ;
assign m_axi_awlock[5] = \<const0> ;
assign m_axi_awlock[4] = \<const0> ;
assign m_axi_awlock[3] = \<const0> ;
assign m_axi_awlock[2] = \<const0> ;
assign m_axi_awlock[1] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[20:18] = \^m_axi_awprot [20:18];
assign m_axi_awprot[17:15] = \^m_axi_awprot [20:18];
assign m_axi_awprot[14:12] = \^m_axi_awprot [20:18];
assign m_axi_awprot[11:9] = \^m_axi_awprot [20:18];
assign m_axi_awprot[8:6] = \^m_axi_awprot [20:18];
assign m_axi_awprot[5:3] = \^m_axi_awprot [20:18];
assign m_axi_awprot[2:0] = \^m_axi_awprot [20:18];
assign m_axi_awqos[27] = \<const0> ;
assign m_axi_awqos[26] = \<const0> ;
assign m_axi_awqos[25] = \<const0> ;
assign m_axi_awqos[24] = \<const0> ;
assign m_axi_awqos[23] = \<const0> ;
assign m_axi_awqos[22] = \<const0> ;
assign m_axi_awqos[21] = \<const0> ;
assign m_axi_awqos[20] = \<const0> ;
assign m_axi_awqos[19] = \<const0> ;
assign m_axi_awqos[18] = \<const0> ;
assign m_axi_awqos[17] = \<const0> ;
assign m_axi_awqos[16] = \<const0> ;
assign m_axi_awqos[15] = \<const0> ;
assign m_axi_awqos[14] = \<const0> ;
assign m_axi_awqos[13] = \<const0> ;
assign m_axi_awqos[12] = \<const0> ;
assign m_axi_awqos[11] = \<const0> ;
assign m_axi_awqos[10] = \<const0> ;
assign m_axi_awqos[9] = \<const0> ;
assign m_axi_awqos[8] = \<const0> ;
assign m_axi_awqos[7] = \<const0> ;
assign m_axi_awqos[6] = \<const0> ;
assign m_axi_awqos[5] = \<const0> ;
assign m_axi_awqos[4] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[27] = \<const0> ;
assign m_axi_awregion[26] = \<const0> ;
assign m_axi_awregion[25] = \<const0> ;
assign m_axi_awregion[24] = \<const0> ;
assign m_axi_awregion[23] = \<const0> ;
assign m_axi_awregion[22] = \<const0> ;
assign m_axi_awregion[21] = \<const0> ;
assign m_axi_awregion[20] = \<const0> ;
assign m_axi_awregion[19] = \<const0> ;
assign m_axi_awregion[18] = \<const0> ;
assign m_axi_awregion[17] = \<const0> ;
assign m_axi_awregion[16] = \<const0> ;
assign m_axi_awregion[15] = \<const0> ;
assign m_axi_awregion[14] = \<const0> ;
assign m_axi_awregion[13] = \<const0> ;
assign m_axi_awregion[12] = \<const0> ;
assign m_axi_awregion[11] = \<const0> ;
assign m_axi_awregion[10] = \<const0> ;
assign m_axi_awregion[9] = \<const0> ;
assign m_axi_awregion[8] = \<const0> ;
assign m_axi_awregion[7] = \<const0> ;
assign m_axi_awregion[6] = \<const0> ;
assign m_axi_awregion[5] = \<const0> ;
assign m_axi_awregion[4] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[20] = \<const0> ;
assign m_axi_awsize[19] = \<const0> ;
assign m_axi_awsize[18] = \<const0> ;
assign m_axi_awsize[17] = \<const0> ;
assign m_axi_awsize[16] = \<const0> ;
assign m_axi_awsize[15] = \<const0> ;
assign m_axi_awsize[14] = \<const0> ;
assign m_axi_awsize[13] = \<const0> ;
assign m_axi_awsize[12] = \<const0> ;
assign m_axi_awsize[11] = \<const0> ;
assign m_axi_awsize[10] = \<const0> ;
assign m_axi_awsize[9] = \<const0> ;
assign m_axi_awsize[8] = \<const0> ;
assign m_axi_awsize[7] = \<const0> ;
assign m_axi_awsize[6] = \<const0> ;
assign m_axi_awsize[5] = \<const0> ;
assign m_axi_awsize[4] = \<const0> ;
assign m_axi_awsize[3] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[6] = \<const0> ;
assign m_axi_awuser[5] = \<const0> ;
assign m_axi_awuser[4] = \<const0> ;
assign m_axi_awuser[3] = \<const0> ;
assign m_axi_awuser[2] = \<const0> ;
assign m_axi_awuser[1] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[223:192] = \^m_axi_wdata [223:192];
assign m_axi_wdata[191:160] = \^m_axi_wdata [223:192];
assign m_axi_wdata[159:128] = \^m_axi_wdata [223:192];
assign m_axi_wdata[127:96] = \^m_axi_wdata [223:192];
assign m_axi_wdata[95:64] = \^m_axi_wdata [223:192];
assign m_axi_wdata[63:32] = \^m_axi_wdata [223:192];
assign m_axi_wdata[31:0] = \^m_axi_wdata [223:192];
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast[6] = \<const0> ;
assign m_axi_wlast[5] = \<const0> ;
assign m_axi_wlast[4] = \<const0> ;
assign m_axi_wlast[3] = \<const0> ;
assign m_axi_wlast[2] = \<const0> ;
assign m_axi_wlast[1] = \<const0> ;
assign m_axi_wlast[0] = \<const0> ;
assign m_axi_wstrb[27:24] = \^m_axi_wstrb [27:24];
assign m_axi_wstrb[23:20] = \^m_axi_wstrb [27:24];
assign m_axi_wstrb[19:16] = \^m_axi_wstrb [27:24];
assign m_axi_wstrb[15:12] = \^m_axi_wstrb [27:24];
assign m_axi_wstrb[11:8] = \^m_axi_wstrb [27:24];
assign m_axi_wstrb[7:4] = \^m_axi_wstrb [27:24];
assign m_axi_wstrb[3:0] = \^m_axi_wstrb [27:24];
assign m_axi_wuser[6] = \<const0> ;
assign m_axi_wuser[5] = \<const0> ;
assign m_axi_wuser[4] = \<const0> ;
assign m_axi_wuser[3] = \<const0> ;
assign m_axi_wuser[2] = \<const0> ;
assign m_axi_wuser[1] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[5:4] = \^s_axi_bresp [5:4];
assign s_axi_bresp[3:2] = \^s_axi_bresp [5:4];
assign s_axi_bresp[1:0] = \^s_axi_bresp [5:4];
assign s_axi_buser[2] = \<const0> ;
assign s_axi_buser[1] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_rdata[95:64] = \^s_axi_rdata [95:64];
assign s_axi_rdata[63:32] = \^s_axi_rdata [95:64];
assign s_axi_rdata[31:0] = \^s_axi_rdata [95:64];
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast[2] = \<const0> ;
assign s_axi_rlast[1] = \<const0> ;
assign s_axi_rlast[0] = \<const0> ;
assign s_axi_rresp[5:4] = \^s_axi_rresp [5:4];
assign s_axi_rresp[3:2] = \^s_axi_rresp [5:4];
assign s_axi_rresp[1:0] = \^s_axi_rresp [5:4];
assign s_axi_ruser[2] = \<const0> ;
assign s_axi_ruser[1] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_crossbar_sasd \gen_sasd.crossbar_sasd_0
(.Q({\^m_axi_awprot ,\^m_axi_araddr ,\^m_axi_awaddr }),
.aclk(aclk),
.aresetn(aresetn),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(\^m_axi_wdata ),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(\^m_axi_wstrb ),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(\^s_axi_bresp ),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rdata[95] ({\^s_axi_rdata ,\^s_axi_rresp }),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_crossbar_sasd
(s_axi_awready,
Q,
\s_axi_rdata[95] ,
m_axi_arvalid,
m_axi_bready,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
m_axi_wvalid,
m_axi_wstrb,
m_axi_wdata,
s_axi_arready,
s_axi_rvalid,
m_axi_awvalid,
m_axi_rready,
s_axi_arvalid,
s_axi_awvalid,
aclk,
aresetn,
s_axi_rready,
s_axi_bready,
m_axi_wready,
m_axi_rvalid,
m_axi_arready,
m_axi_awready,
m_axi_bvalid,
m_axi_rdata,
m_axi_rresp,
m_axi_bresp,
s_axi_wvalid,
s_axi_wstrb,
s_axi_wdata,
s_axi_araddr,
s_axi_awaddr,
s_axi_arprot,
s_axi_awprot);
output [2:0]s_axi_awready;
output [34:0]Q;
output [33:0]\s_axi_rdata[95] ;
output [6:0]m_axi_arvalid;
output [6:0]m_axi_bready;
output [2:0]s_axi_wready;
output [2:0]s_axi_bvalid;
output [1:0]s_axi_bresp;
output [6:0]m_axi_wvalid;
output [3:0]m_axi_wstrb;
output [31:0]m_axi_wdata;
output [2:0]s_axi_arready;
output [2:0]s_axi_rvalid;
output [6:0]m_axi_awvalid;
output [6:0]m_axi_rready;
input [2:0]s_axi_arvalid;
input [2:0]s_axi_awvalid;
input aclk;
input aresetn;
input [2:0]s_axi_rready;
input [2:0]s_axi_bready;
input [6:0]m_axi_wready;
input [6:0]m_axi_rvalid;
input [6:0]m_axi_arready;
input [6:0]m_axi_awready;
input [6:0]m_axi_bvalid;
input [223:0]m_axi_rdata;
input [13:0]m_axi_rresp;
input [13:0]m_axi_bresp;
input [2:0]s_axi_wvalid;
input [11:0]s_axi_wstrb;
input [95:0]s_axi_wdata;
input [95:0]s_axi_araddr;
input [95:0]s_axi_awaddr;
input [8:0]s_axi_arprot;
input [8:0]s_axi_awprot;
wire [34:0]Q;
wire aa_grant_rnw;
wire aa_rready;
wire aa_rvalid;
wire aa_wvalid;
wire aclk;
wire addr_arbiter_inst_n_11;
wire addr_arbiter_inst_n_12;
wire addr_arbiter_inst_n_141;
wire addr_arbiter_inst_n_23;
wire addr_arbiter_inst_n_3;
wire addr_arbiter_inst_n_4;
wire addr_arbiter_inst_n_6;
wire addr_arbiter_inst_n_7;
wire aresetn;
wire aresetn_d;
wire f_mux_return7;
wire \gen_decerr.decerr_slave_inst_n_2 ;
wire \gen_decerr.decerr_slave_inst_n_3 ;
wire \gen_decerr.decerr_slave_inst_n_4 ;
wire \gen_decerr.decerr_slave_inst_n_5 ;
wire \gen_decerr.decerr_slave_inst_n_6 ;
wire [2:0]m_atarget_enc;
wire [7:0]m_atarget_hot;
wire [7:0]m_atarget_hot0;
wire [6:0]m_axi_arready;
wire [6:0]m_axi_arvalid;
wire [6:0]m_axi_awready;
wire [6:0]m_axi_awvalid;
wire [6:0]m_axi_bready;
wire [13:0]m_axi_bresp;
wire [6:0]m_axi_bvalid;
wire [223:0]m_axi_rdata;
wire [6:0]m_axi_rready;
wire [13:0]m_axi_rresp;
wire [6:0]m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire [6:0]m_axi_wready;
wire [3:0]m_axi_wstrb;
wire [6:0]m_axi_wvalid;
wire [1:0]m_ready_d;
wire [0:0]m_ready_d0;
wire [2:0]m_ready_d_0;
wire m_valid_i;
wire mi_arready_mux;
wire mi_awready_mux;
wire [7:7]mi_bvalid;
wire [7:7]mi_wready;
wire [1:1]p_0_out__0;
wire p_2_in;
wire reg_slice_r_n_2;
wire reg_slice_r_n_3;
wire reg_slice_r_n_4;
wire reg_slice_r_n_5;
wire reset;
wire [95:0]s_axi_araddr;
wire [8:0]s_axi_arprot;
wire [2:0]s_axi_arready;
wire [2:0]s_axi_arvalid;
wire [95:0]s_axi_awaddr;
wire [8:0]s_axi_awprot;
wire [2:0]s_axi_awready;
wire [2:0]s_axi_awvalid;
wire [2:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire \s_axi_bresp[0]_INST_0_i_1_n_0 ;
wire \s_axi_bresp[0]_INST_0_i_2_n_0 ;
wire \s_axi_bresp[1]_INST_0_i_1_n_0 ;
wire \s_axi_bresp[1]_INST_0_i_4_n_0 ;
wire [2:0]s_axi_bvalid;
wire [33:0]\s_axi_rdata[95] ;
wire [2:0]s_axi_rready;
wire [2:0]s_axi_rvalid;
wire [95:0]s_axi_wdata;
wire [2:0]s_axi_wready;
wire [11:0]s_axi_wstrb;
wire [2:0]s_axi_wvalid;
wire [2:0]s_ready_i0__2;
wire splitter_aw_n_0;
wire splitter_aw_n_10;
wire splitter_aw_n_11;
wire splitter_aw_n_12;
wire splitter_aw_n_5;
wire splitter_aw_n_6;
wire splitter_aw_n_7;
wire splitter_aw_n_8;
wire splitter_aw_n_9;
wire sr_rvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_addr_arbiter_sasd addr_arbiter_inst
(.D(m_atarget_hot0),
.E(addr_arbiter_inst_n_4),
.Q(m_atarget_hot),
.aa_grant_rnw(aa_grant_rnw),
.aa_rvalid(aa_rvalid),
.aa_wvalid(aa_wvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_arbiter.m_valid_i_reg_0 (addr_arbiter_inst_n_23),
.\gen_arbiter.m_valid_i_reg_1 (s_ready_i0__2[1:0]),
.\gen_axilite.s_axi_arready_i_reg (\gen_decerr.decerr_slave_inst_n_3 ),
.\gen_axilite.s_axi_awready_i_reg (\gen_decerr.decerr_slave_inst_n_6 ),
.\gen_axilite.s_axi_awready_i_reg_0 (\gen_decerr.decerr_slave_inst_n_4 ),
.\gen_axilite.s_axi_bvalid_i_reg (addr_arbiter_inst_n_7),
.\gen_axilite.s_axi_bvalid_i_reg_0 (addr_arbiter_inst_n_141),
.\gen_axilite.s_axi_bvalid_i_reg_1 (\gen_decerr.decerr_slave_inst_n_5 ),
.m_atarget_enc(m_atarget_enc),
.\m_atarget_enc_reg[0] (addr_arbiter_inst_n_12),
.\m_atarget_enc_reg[0]_0 (splitter_aw_n_8),
.\m_atarget_enc_reg[0]_1 (splitter_aw_n_10),
.\m_atarget_enc_reg[0]_2 (splitter_aw_n_0),
.\m_atarget_enc_reg[0]_3 (splitter_aw_n_9),
.\m_atarget_enc_reg[0]_4 (splitter_aw_n_7),
.\m_atarget_enc_reg[0]_5 (splitter_aw_n_6),
.\m_atarget_enc_reg[1] (addr_arbiter_inst_n_11),
.\m_atarget_enc_reg[1]_0 (\gen_decerr.decerr_slave_inst_n_2 ),
.\m_atarget_enc_reg[1]_1 (reg_slice_r_n_5),
.\m_atarget_enc_reg[2] (addr_arbiter_inst_n_6),
.\m_atarget_enc_reg[2]_0 (splitter_aw_n_11),
.\m_atarget_enc_reg[2]_1 (splitter_aw_n_12),
.\m_atarget_enc_reg[2]_2 (splitter_aw_n_5),
.m_axi_arready(m_axi_arready[6:1]),
.m_axi_arvalid(m_axi_arvalid),
.\m_axi_awprot[20] (Q),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wvalid(m_axi_wvalid),
.\m_payload_i_reg[0] (reg_slice_r_n_2),
.m_ready_d(m_ready_d),
.m_ready_d0(m_ready_d0),
.m_ready_d_0(m_ready_d_0),
.\m_ready_d_reg[1] (addr_arbiter_inst_n_3),
.\m_ready_d_reg[1]_0 (p_0_out__0),
.m_valid_i(m_valid_i),
.mi_arready_mux(mi_arready_mux),
.mi_awready_mux(mi_awready_mux),
.mi_bvalid(mi_bvalid),
.mi_wready(mi_wready),
.p_2_in(p_2_in),
.reset(reset),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i0__2(s_ready_i0__2[2]),
.sr_rvalid(sr_rvalid));
FDRE #(
.INIT(1'b0))
aresetn_d_reg__0
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(aresetn_d),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_decerr_slave \gen_decerr.decerr_slave_inst
(.Q(m_atarget_hot[7]),
.aa_rready(aa_rready),
.aa_wvalid(aa_wvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_arbiter.any_grant_reg (\gen_decerr.decerr_slave_inst_n_5 ),
.\gen_arbiter.any_grant_reg_0 (\gen_decerr.decerr_slave_inst_n_6 ),
.\gen_arbiter.grant_rnw_reg (addr_arbiter_inst_n_7),
.\gen_arbiter.m_valid_i_reg (addr_arbiter_inst_n_3),
.\gen_axilite.s_axi_bvalid_i_reg_0 (addr_arbiter_inst_n_141),
.m_atarget_enc(m_atarget_enc),
.m_axi_arready(m_axi_arready[0]),
.m_axi_awready(m_axi_awready[0]),
.m_axi_bvalid(m_axi_bvalid[0]),
.m_axi_rvalid({m_axi_rvalid[6:5],m_axi_rvalid[0]}),
.m_axi_wready(m_axi_wready[0]),
.\m_ready_d_reg[1] (\gen_decerr.decerr_slave_inst_n_3 ),
.\m_ready_d_reg[2] (\gen_decerr.decerr_slave_inst_n_4 ),
.mi_bvalid(mi_bvalid),
.mi_wready(mi_wready),
.reset(reset),
.s_ready_i_reg(\gen_decerr.decerr_slave_inst_n_2 ));
FDRE #(
.INIT(1'b0))
\m_atarget_enc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_12),
.Q(m_atarget_enc[0]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_enc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_11),
.Q(m_atarget_enc[1]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_enc_reg[2]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_6),
.Q(m_atarget_enc[2]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[0]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[0]),
.Q(m_atarget_hot[0]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[1]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[1]),
.Q(m_atarget_hot[1]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[2]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[2]),
.Q(m_atarget_hot[2]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[3]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[3]),
.Q(m_atarget_hot[3]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[4]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[4]),
.Q(m_atarget_hot[4]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[5]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[5]),
.Q(m_atarget_hot[5]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[6]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[6]),
.Q(m_atarget_hot[6]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[7]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[7]),
.Q(m_atarget_hot[7]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice reg_slice_r
(.E(addr_arbiter_inst_n_4),
.Q(m_atarget_hot[6:0]),
.aa_rready(aa_rready),
.aa_rvalid(aa_rvalid),
.aclk(aclk),
.f_mux_return7(f_mux_return7),
.m_atarget_enc(m_atarget_enc),
.m_axi_rdata(m_axi_rdata),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid[4:1]),
.m_ready_d(m_ready_d),
.\m_ready_d_reg[0] (reg_slice_r_n_2),
.\m_ready_d_reg[1] (reg_slice_r_n_4),
.mi_arready_mux(mi_arready_mux),
.p_2_in(p_2_in),
.reset(reset),
.\s_axi_rdata[95] (\s_axi_rdata[95] ),
.s_ready_i_reg_0(reg_slice_r_n_5),
.\skid_buffer_reg[34]_0 (reg_slice_r_n_3),
.sr_rvalid(sr_rvalid));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\s_axi_bresp[0]_INST_0
(.I0(\s_axi_bresp[0]_INST_0_i_1_n_0 ),
.I1(m_axi_bresp[4]),
.I2(reg_slice_r_n_3),
.I3(m_axi_bresp[2]),
.I4(f_mux_return7),
.I5(\s_axi_bresp[0]_INST_0_i_2_n_0 ),
.O(s_axi_bresp[0]));
LUT5 #(
.INIT(32'h0A0000C0))
\s_axi_bresp[0]_INST_0_i_1
(.I0(m_axi_bresp[6]),
.I1(m_axi_bresp[8]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\s_axi_bresp[0]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0A0C00FF0A0C000))
\s_axi_bresp[0]_INST_0_i_2
(.I0(m_axi_bresp[12]),
.I1(m_axi_bresp[10]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_bresp[0]),
.O(\s_axi_bresp[0]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\s_axi_bresp[1]_INST_0
(.I0(\s_axi_bresp[1]_INST_0_i_1_n_0 ),
.I1(m_axi_bresp[5]),
.I2(reg_slice_r_n_3),
.I3(m_axi_bresp[3]),
.I4(f_mux_return7),
.I5(\s_axi_bresp[1]_INST_0_i_4_n_0 ),
.O(s_axi_bresp[1]));
LUT5 #(
.INIT(32'h0A0000C0))
\s_axi_bresp[1]_INST_0_i_1
(.I0(m_axi_bresp[7]),
.I1(m_axi_bresp[9]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\s_axi_bresp[1]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0A0C00FF0A0C000))
\s_axi_bresp[1]_INST_0_i_4
(.I0(m_axi_bresp[13]),
.I1(m_axi_bresp[11]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_bresp[1]),
.O(\s_axi_bresp[1]_INST_0_i_4_n_0 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0 splitter_ar
(.aa_grant_rnw(aa_grant_rnw),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_arbiter.m_valid_i_reg (addr_arbiter_inst_n_3),
.\m_payload_i_reg[0] (reg_slice_r_n_4),
.\m_payload_i_reg[0]_0 (reg_slice_r_n_2),
.m_ready_d(m_ready_d),
.m_valid_i(m_valid_i),
.mi_arready_mux(mi_arready_mux));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter splitter_aw
(.aa_grant_rnw(aa_grant_rnw),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_arbiter.any_grant_reg (splitter_aw_n_0),
.\gen_arbiter.any_grant_reg_0 (splitter_aw_n_8),
.\gen_arbiter.any_grant_reg_1 (splitter_aw_n_9),
.\gen_arbiter.any_grant_reg_2 (splitter_aw_n_10),
.\gen_arbiter.any_grant_reg_3 (splitter_aw_n_11),
.\gen_arbiter.any_grant_reg_4 (splitter_aw_n_12),
.\gen_arbiter.grant_rnw_reg (addr_arbiter_inst_n_7),
.\gen_arbiter.m_grant_enc_i_reg[1] (p_0_out__0),
.\gen_axilite.s_axi_awready_i_reg (\gen_decerr.decerr_slave_inst_n_4 ),
.m_atarget_enc(m_atarget_enc),
.m_axi_awready(m_axi_awready[6:1]),
.m_axi_bvalid(m_axi_bvalid[6:1]),
.m_axi_wready(m_axi_wready[6:1]),
.m_ready_d(m_ready_d_0),
.m_ready_d0(m_ready_d0),
.\m_ready_d_reg[0]_0 (addr_arbiter_inst_n_23),
.\m_ready_d_reg[1]_0 (s_ready_i0__2[1:0]),
.\m_ready_d_reg[2]_0 (splitter_aw_n_5),
.\m_ready_d_reg[2]_1 (splitter_aw_n_6),
.\m_ready_d_reg[2]_2 (splitter_aw_n_7),
.m_valid_i(m_valid_i),
.mi_awready_mux(mi_awready_mux),
.s_ready_i0__2(s_ready_i0__2[2]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_decerr_slave
(mi_bvalid,
mi_wready,
s_ready_i_reg,
\m_ready_d_reg[1] ,
\m_ready_d_reg[2] ,
\gen_arbiter.any_grant_reg ,
\gen_arbiter.any_grant_reg_0 ,
reset,
\gen_axilite.s_axi_bvalid_i_reg_0 ,
aclk,
aresetn_d,
Q,
\gen_arbiter.m_valid_i_reg ,
m_atarget_enc,
m_axi_rvalid,
m_axi_arready,
m_axi_awready,
m_axi_bvalid,
m_axi_wready,
aa_rready,
\gen_arbiter.grant_rnw_reg ,
aa_wvalid);
output [0:0]mi_bvalid;
output [0:0]mi_wready;
output s_ready_i_reg;
output \m_ready_d_reg[1] ;
output \m_ready_d_reg[2] ;
output \gen_arbiter.any_grant_reg ;
output \gen_arbiter.any_grant_reg_0 ;
input reset;
input \gen_axilite.s_axi_bvalid_i_reg_0 ;
input aclk;
input aresetn_d;
input [0:0]Q;
input \gen_arbiter.m_valid_i_reg ;
input [2:0]m_atarget_enc;
input [2:0]m_axi_rvalid;
input [0:0]m_axi_arready;
input [0:0]m_axi_awready;
input [0:0]m_axi_bvalid;
input [0:0]m_axi_wready;
input aa_rready;
input \gen_arbiter.grant_rnw_reg ;
input aa_wvalid;
wire [0:0]Q;
wire aa_rready;
wire aa_wvalid;
wire aclk;
wire aresetn_d;
wire \gen_arbiter.any_grant_reg ;
wire \gen_arbiter.any_grant_reg_0 ;
wire \gen_arbiter.grant_rnw_reg ;
wire \gen_arbiter.m_valid_i_reg ;
wire \gen_axilite.s_axi_arready_i_i_1_n_0 ;
wire \gen_axilite.s_axi_awready_i_i_1_n_0 ;
wire \gen_axilite.s_axi_bvalid_i_reg_0 ;
wire \gen_axilite.s_axi_rvalid_i_i_1_n_0 ;
wire [2:0]m_atarget_enc;
wire [0:0]m_axi_arready;
wire [0:0]m_axi_awready;
wire [0:0]m_axi_bvalid;
wire [2:0]m_axi_rvalid;
wire [0:0]m_axi_wready;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[2] ;
wire m_valid_i_i_5_n_0;
wire [7:7]mi_arready;
wire [0:0]mi_bvalid;
wire [7:7]mi_rvalid;
wire [0:0]mi_wready;
wire reset;
wire s_ready_i_reg;
LUT5 #(
.INIT(32'h88882AAA))
\gen_axilite.s_axi_arready_i_i_1
(.I0(aresetn_d),
.I1(mi_arready),
.I2(Q),
.I3(\gen_arbiter.m_valid_i_reg ),
.I4(mi_rvalid),
.O(\gen_axilite.s_axi_arready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axilite.s_axi_arready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_arready_i_i_1_n_0 ),
.Q(mi_arready),
.R(1'b0));
LUT5 #(
.INIT(32'hBFFF4000))
\gen_axilite.s_axi_awready_i_i_1
(.I0(mi_bvalid),
.I1(\gen_arbiter.grant_rnw_reg ),
.I2(aa_wvalid),
.I3(Q),
.I4(mi_wready),
.O(\gen_axilite.s_axi_awready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axilite.s_axi_awready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_awready_i_i_1_n_0 ),
.Q(mi_wready),
.R(reset));
FDRE #(
.INIT(1'b0))
\gen_axilite.s_axi_bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_bvalid_i_reg_0 ),
.Q(mi_bvalid),
.R(reset));
LUT5 #(
.INIT(32'h74CC44CC))
\gen_axilite.s_axi_rvalid_i_i_1
(.I0(aa_rready),
.I1(mi_rvalid),
.I2(\gen_arbiter.m_valid_i_reg ),
.I3(Q),
.I4(mi_arready),
.O(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axilite.s_axi_rvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ),
.Q(mi_rvalid),
.R(reset));
LUT5 #(
.INIT(32'hA000000C))
\m_ready_d[1]_i_6
(.I0(mi_arready),
.I1(m_axi_arready),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[2]),
.O(\m_ready_d_reg[1] ));
LUT5 #(
.INIT(32'hA000000C))
\m_ready_d[2]_i_7
(.I0(mi_wready),
.I1(m_axi_awready),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[2]),
.O(\m_ready_d_reg[2] ));
LUT6 #(
.INIT(64'hFFFFFFFF48400800))
m_valid_i_i_3
(.I0(m_atarget_enc[1]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_axi_rvalid[2]),
.I4(m_axi_rvalid[1]),
.I5(m_valid_i_i_5_n_0),
.O(s_ready_i_reg));
LUT5 #(
.INIT(32'hA000000C))
m_valid_i_i_5
(.I0(mi_rvalid),
.I1(m_axi_rvalid[0]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[2]),
.O(m_valid_i_i_5_n_0));
LUT5 #(
.INIT(32'hA000000C))
\s_axi_bvalid[2]_INST_0_i_4
(.I0(mi_bvalid),
.I1(m_axi_bvalid),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[2]),
.O(\gen_arbiter.any_grant_reg ));
LUT5 #(
.INIT(32'hA000000C))
\s_axi_wready[2]_INST_0_i_4
(.I0(mi_wready),
.I1(m_axi_wready),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[2]),
.O(\gen_arbiter.any_grant_reg_0 ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter
(\gen_arbiter.any_grant_reg ,
s_ready_i0__2,
m_ready_d,
\m_ready_d_reg[2]_0 ,
\m_ready_d_reg[2]_1 ,
\m_ready_d_reg[2]_2 ,
\gen_arbiter.any_grant_reg_0 ,
\gen_arbiter.any_grant_reg_1 ,
\gen_arbiter.any_grant_reg_2 ,
\gen_arbiter.any_grant_reg_3 ,
\gen_arbiter.any_grant_reg_4 ,
m_axi_wready,
m_atarget_enc,
\gen_axilite.s_axi_awready_i_reg ,
\gen_arbiter.grant_rnw_reg ,
m_axi_awready,
m_axi_bvalid,
aresetn_d,
\m_ready_d_reg[1]_0 ,
mi_awready_mux,
m_valid_i,
aa_grant_rnw,
\gen_arbiter.m_grant_enc_i_reg[1] ,
\m_ready_d_reg[0]_0 ,
m_ready_d0,
aclk);
output \gen_arbiter.any_grant_reg ;
output [0:0]s_ready_i0__2;
output [2:0]m_ready_d;
output \m_ready_d_reg[2]_0 ;
output \m_ready_d_reg[2]_1 ;
output \m_ready_d_reg[2]_2 ;
output \gen_arbiter.any_grant_reg_0 ;
output \gen_arbiter.any_grant_reg_1 ;
output \gen_arbiter.any_grant_reg_2 ;
output \gen_arbiter.any_grant_reg_3 ;
output \gen_arbiter.any_grant_reg_4 ;
input [5:0]m_axi_wready;
input [2:0]m_atarget_enc;
input \gen_axilite.s_axi_awready_i_reg ;
input \gen_arbiter.grant_rnw_reg ;
input [5:0]m_axi_awready;
input [5:0]m_axi_bvalid;
input aresetn_d;
input [1:0]\m_ready_d_reg[1]_0 ;
input mi_awready_mux;
input m_valid_i;
input aa_grant_rnw;
input [0:0]\gen_arbiter.m_grant_enc_i_reg[1] ;
input \m_ready_d_reg[0]_0 ;
input [0:0]m_ready_d0;
input aclk;
wire aa_grant_rnw;
wire aclk;
wire aresetn_d;
wire \gen_arbiter.any_grant_reg ;
wire \gen_arbiter.any_grant_reg_0 ;
wire \gen_arbiter.any_grant_reg_1 ;
wire \gen_arbiter.any_grant_reg_2 ;
wire \gen_arbiter.any_grant_reg_3 ;
wire \gen_arbiter.any_grant_reg_4 ;
wire \gen_arbiter.grant_rnw_reg ;
wire [0:0]\gen_arbiter.m_grant_enc_i_reg[1] ;
wire \gen_axilite.s_axi_awready_i_reg ;
wire [2:0]m_atarget_enc;
wire [5:0]m_axi_awready;
wire [5:0]m_axi_bvalid;
wire [5:0]m_axi_wready;
wire [2:0]m_ready_d;
wire [0:0]m_ready_d0;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d[2]_i_1_n_0 ;
wire \m_ready_d_reg[0]_0 ;
wire [1:0]\m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[2]_0 ;
wire \m_ready_d_reg[2]_1 ;
wire \m_ready_d_reg[2]_2 ;
wire m_valid_i;
wire mi_awready_mux;
wire [0:0]s_ready_i0__2;
LUT6 #(
.INIT(64'hFFFFFFFEAAAAAAAA))
\gen_arbiter.m_grant_hot_i[2]_i_7
(.I0(m_ready_d[2]),
.I1(\m_ready_d_reg[2]_0 ),
.I2(\m_ready_d_reg[2]_1 ),
.I3(\gen_axilite.s_axi_awready_i_reg ),
.I4(\m_ready_d_reg[2]_2 ),
.I5(\gen_arbiter.grant_rnw_reg ),
.O(s_ready_i0__2));
LUT5 #(
.INIT(32'h88880008))
\m_ready_d[0]_i_1
(.I0(m_ready_d0),
.I1(aresetn_d),
.I2(\gen_arbiter.m_grant_enc_i_reg[1] ),
.I3(m_ready_d[1]),
.I4(\m_ready_d_reg[0]_0 ),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0F0200000000000))
\m_ready_d[1]_i_1
(.I0(m_valid_i),
.I1(aa_grant_rnw),
.I2(aresetn_d),
.I3(\gen_arbiter.m_grant_enc_i_reg[1] ),
.I4(m_ready_d[1]),
.I5(\m_ready_d_reg[0]_0 ),
.O(\m_ready_d[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C080C00CC88CC00))
\m_ready_d[2]_i_1
(.I0(\gen_arbiter.grant_rnw_reg ),
.I1(aresetn_d),
.I2(\m_ready_d_reg[1]_0 [1]),
.I3(m_ready_d[2]),
.I4(mi_awready_mux),
.I5(\m_ready_d_reg[1]_0 [0]),
.O(\m_ready_d[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0C00A000))
\m_ready_d[2]_i_6
(.I0(m_axi_awready[4]),
.I1(m_axi_awready[5]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.O(\m_ready_d_reg[2]_2 ));
LUT5 #(
.INIT(32'h000A00C0))
\m_ready_d[2]_i_8
(.I0(m_axi_awready[1]),
.I1(m_axi_awready[0]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.O(\m_ready_d_reg[2]_1 ));
LUT5 #(
.INIT(32'h0A0000C0))
\m_ready_d[2]_i_9
(.I0(m_axi_awready[2]),
.I1(m_axi_awready[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\m_ready_d_reg[2]_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[2]_i_1_n_0 ),
.Q(m_ready_d[2]),
.R(1'b0));
LUT5 #(
.INIT(32'h0C00A000))
\s_axi_bvalid[2]_INST_0_i_3
(.I0(m_axi_bvalid[4]),
.I1(m_axi_bvalid[5]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.O(\gen_arbiter.any_grant_reg_2 ));
LUT5 #(
.INIT(32'h000A00C0))
\s_axi_bvalid[2]_INST_0_i_5
(.I0(m_axi_bvalid[1]),
.I1(m_axi_bvalid[0]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.O(\gen_arbiter.any_grant_reg_0 ));
LUT5 #(
.INIT(32'h0A0000C0))
\s_axi_bvalid[2]_INST_0_i_6
(.I0(m_axi_bvalid[2]),
.I1(m_axi_bvalid[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\gen_arbiter.any_grant_reg_3 ));
LUT5 #(
.INIT(32'h0C00A000))
\s_axi_wready[2]_INST_0_i_3
(.I0(m_axi_wready[4]),
.I1(m_axi_wready[5]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.O(\gen_arbiter.any_grant_reg_1 ));
LUT5 #(
.INIT(32'h000A00C0))
\s_axi_wready[2]_INST_0_i_5
(.I0(m_axi_wready[1]),
.I1(m_axi_wready[0]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.O(\gen_arbiter.any_grant_reg ));
LUT5 #(
.INIT(32'h0A0000C0))
\s_axi_wready[2]_INST_0_i_6
(.I0(m_axi_wready[2]),
.I1(m_axi_wready[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\gen_arbiter.any_grant_reg_4 ));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_15_splitter" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_15_splitter__parameterized0
(m_ready_d,
\gen_arbiter.m_valid_i_reg ,
aresetn_d,
\m_payload_i_reg[0] ,
mi_arready_mux,
aa_grant_rnw,
m_valid_i,
\m_payload_i_reg[0]_0 ,
aclk);
output [1:0]m_ready_d;
input \gen_arbiter.m_valid_i_reg ;
input aresetn_d;
input \m_payload_i_reg[0] ;
input mi_arready_mux;
input aa_grant_rnw;
input m_valid_i;
input \m_payload_i_reg[0]_0 ;
input aclk;
wire aa_grant_rnw;
wire aclk;
wire aresetn_d;
wire \gen_arbiter.m_valid_i_reg ;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [1:0]m_ready_d;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire m_valid_i;
wire mi_arready_mux;
LUT6 #(
.INIT(64'h00000000EAAA0000))
\m_ready_d[0]_i_1
(.I0(m_ready_d[0]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(\m_payload_i_reg[0] ),
.I4(aresetn_d),
.I5(\m_payload_i_reg[0]_0 ),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000C000C00080000))
\m_ready_d[1]_i_1
(.I0(\gen_arbiter.m_valid_i_reg ),
.I1(aresetn_d),
.I2(\m_payload_i_reg[0] ),
.I3(m_ready_d[0]),
.I4(mi_arready_mux),
.I5(m_ready_d[1]),
.O(\m_ready_d[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice
(sr_rvalid,
aa_rready,
\m_ready_d_reg[0] ,
\skid_buffer_reg[34]_0 ,
\m_ready_d_reg[1] ,
s_ready_i_reg_0,
f_mux_return7,
m_axi_rready,
\s_axi_rdata[95] ,
aclk,
p_2_in,
m_ready_d,
mi_arready_mux,
m_atarget_enc,
aa_rvalid,
m_axi_rvalid,
m_axi_rdata,
m_axi_rresp,
Q,
reset,
E);
output sr_rvalid;
output aa_rready;
output \m_ready_d_reg[0] ;
output \skid_buffer_reg[34]_0 ;
output \m_ready_d_reg[1] ;
output s_ready_i_reg_0;
output f_mux_return7;
output [6:0]m_axi_rready;
output [33:0]\s_axi_rdata[95] ;
input aclk;
input p_2_in;
input [1:0]m_ready_d;
input mi_arready_mux;
input [2:0]m_atarget_enc;
input aa_rvalid;
input [3:0]m_axi_rvalid;
input [223:0]m_axi_rdata;
input [13:0]m_axi_rresp;
input [6:0]Q;
input reset;
input [0:0]E;
wire [0:0]E;
wire [6:0]Q;
wire [34:1]aa_rmesg;
wire aa_rready;
wire aa_rvalid;
wire aclk;
wire \aresetn_d_reg_n_0_[1] ;
wire f_mux_return7;
wire [2:0]m_atarget_enc;
wire [223:0]m_axi_rdata;
wire [6:0]m_axi_rready;
wire [13:0]m_axi_rresp;
wire [3:0]m_axi_rvalid;
wire \m_payload_i_reg_n_0_[0] ;
wire [1:0]m_ready_d;
wire \m_ready_d_reg[0] ;
wire \m_ready_d_reg[1] ;
wire m_valid_i_i_1_n_0;
wire m_valid_i_i_6_n_0;
wire mi_arready_mux;
wire [1:1]p_0_in;
wire p_2_in;
wire reset;
wire [33:0]\s_axi_rdata[95] ;
wire s_ready_i_i_1_n_0;
wire s_ready_i_reg_0;
wire [34:1]skid_buffer;
wire \skid_buffer[10]_i_2_n_0 ;
wire \skid_buffer[10]_i_3_n_0 ;
wire \skid_buffer[11]_i_2_n_0 ;
wire \skid_buffer[11]_i_3_n_0 ;
wire \skid_buffer[12]_i_2_n_0 ;
wire \skid_buffer[12]_i_3_n_0 ;
wire \skid_buffer[13]_i_2_n_0 ;
wire \skid_buffer[13]_i_3_n_0 ;
wire \skid_buffer[14]_i_2_n_0 ;
wire \skid_buffer[14]_i_3_n_0 ;
wire \skid_buffer[15]_i_2_n_0 ;
wire \skid_buffer[15]_i_3_n_0 ;
wire \skid_buffer[16]_i_2_n_0 ;
wire \skid_buffer[16]_i_3_n_0 ;
wire \skid_buffer[17]_i_2_n_0 ;
wire \skid_buffer[17]_i_3_n_0 ;
wire \skid_buffer[18]_i_2_n_0 ;
wire \skid_buffer[18]_i_3_n_0 ;
wire \skid_buffer[19]_i_2_n_0 ;
wire \skid_buffer[19]_i_3_n_0 ;
wire \skid_buffer[1]_i_2_n_0 ;
wire \skid_buffer[1]_i_3_n_0 ;
wire \skid_buffer[20]_i_2_n_0 ;
wire \skid_buffer[20]_i_3_n_0 ;
wire \skid_buffer[21]_i_2_n_0 ;
wire \skid_buffer[21]_i_3_n_0 ;
wire \skid_buffer[22]_i_2_n_0 ;
wire \skid_buffer[22]_i_3_n_0 ;
wire \skid_buffer[23]_i_2_n_0 ;
wire \skid_buffer[23]_i_3_n_0 ;
wire \skid_buffer[24]_i_2_n_0 ;
wire \skid_buffer[24]_i_3_n_0 ;
wire \skid_buffer[25]_i_2_n_0 ;
wire \skid_buffer[25]_i_3_n_0 ;
wire \skid_buffer[26]_i_2_n_0 ;
wire \skid_buffer[26]_i_3_n_0 ;
wire \skid_buffer[27]_i_2_n_0 ;
wire \skid_buffer[27]_i_3_n_0 ;
wire \skid_buffer[28]_i_2_n_0 ;
wire \skid_buffer[28]_i_3_n_0 ;
wire \skid_buffer[29]_i_2_n_0 ;
wire \skid_buffer[29]_i_3_n_0 ;
wire \skid_buffer[2]_i_2_n_0 ;
wire \skid_buffer[2]_i_3_n_0 ;
wire \skid_buffer[30]_i_2_n_0 ;
wire \skid_buffer[30]_i_3_n_0 ;
wire \skid_buffer[31]_i_2_n_0 ;
wire \skid_buffer[31]_i_3_n_0 ;
wire \skid_buffer[32]_i_2_n_0 ;
wire \skid_buffer[32]_i_3_n_0 ;
wire \skid_buffer[33]_i_2_n_0 ;
wire \skid_buffer[33]_i_3_n_0 ;
wire \skid_buffer[34]_i_2_n_0 ;
wire \skid_buffer[34]_i_3_n_0 ;
wire \skid_buffer[3]_i_2_n_0 ;
wire \skid_buffer[3]_i_3_n_0 ;
wire \skid_buffer[4]_i_2_n_0 ;
wire \skid_buffer[4]_i_3_n_0 ;
wire \skid_buffer[5]_i_2_n_0 ;
wire \skid_buffer[5]_i_3_n_0 ;
wire \skid_buffer[6]_i_2_n_0 ;
wire \skid_buffer[6]_i_3_n_0 ;
wire \skid_buffer[7]_i_2_n_0 ;
wire \skid_buffer[7]_i_3_n_0 ;
wire \skid_buffer[8]_i_2_n_0 ;
wire \skid_buffer[8]_i_3_n_0 ;
wire \skid_buffer[9]_i_2_n_0 ;
wire \skid_buffer[9]_i_3_n_0 ;
wire \skid_buffer_reg[34]_0 ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire sr_rvalid;
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(1'b1),
.Q(p_0_in),
.R(reset));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(p_0_in),
.Q(\aresetn_d_reg_n_0_[1] ),
.R(reset));
LUT6 #(
.INIT(64'hFF80FF80FF800000))
\gen_arbiter.m_grant_hot_i[2]_i_4
(.I0(\m_payload_i_reg_n_0_[0] ),
.I1(p_2_in),
.I2(sr_rvalid),
.I3(m_ready_d[0]),
.I4(mi_arready_mux),
.I5(m_ready_d[1]),
.O(\m_ready_d_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[0]_INST_0
(.I0(Q[0]),
.I1(aa_rready),
.O(m_axi_rready[0]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[1]_INST_0
(.I0(Q[1]),
.I1(aa_rready),
.O(m_axi_rready[1]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[2]_INST_0
(.I0(Q[2]),
.I1(aa_rready),
.O(m_axi_rready[2]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[3]_INST_0
(.I0(Q[3]),
.I1(aa_rready),
.O(m_axi_rready[3]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[4]_INST_0
(.I0(Q[4]),
.I1(aa_rready),
.O(m_axi_rready[4]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[5]_INST_0
(.I0(Q[5]),
.I1(aa_rready),
.O(m_axi_rready[5]));
LUT2 #(
.INIT(4'h8))
\m_axi_rready[6]_INST_0
(.I0(Q[6]),
.I1(aa_rready),
.O(m_axi_rready[6]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[10]_i_1
(.I0(aa_rmesg[10]),
.I1(\skid_buffer_reg_n_0_[10] ),
.I2(aa_rready),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[11]_i_1
(.I0(aa_rmesg[11]),
.I1(\skid_buffer_reg_n_0_[11] ),
.I2(aa_rready),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[12]_i_1
(.I0(aa_rmesg[12]),
.I1(\skid_buffer_reg_n_0_[12] ),
.I2(aa_rready),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[13]_i_1
(.I0(aa_rmesg[13]),
.I1(\skid_buffer_reg_n_0_[13] ),
.I2(aa_rready),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[14]_i_1
(.I0(aa_rmesg[14]),
.I1(\skid_buffer_reg_n_0_[14] ),
.I2(aa_rready),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[15]_i_1
(.I0(aa_rmesg[15]),
.I1(\skid_buffer_reg_n_0_[15] ),
.I2(aa_rready),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[16]_i_1
(.I0(aa_rmesg[16]),
.I1(\skid_buffer_reg_n_0_[16] ),
.I2(aa_rready),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[17]_i_1
(.I0(aa_rmesg[17]),
.I1(\skid_buffer_reg_n_0_[17] ),
.I2(aa_rready),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[18]_i_1
(.I0(aa_rmesg[18]),
.I1(\skid_buffer_reg_n_0_[18] ),
.I2(aa_rready),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[19]_i_1
(.I0(aa_rmesg[19]),
.I1(\skid_buffer_reg_n_0_[19] ),
.I2(aa_rready),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[1]_i_1
(.I0(aa_rmesg[1]),
.I1(\skid_buffer_reg_n_0_[1] ),
.I2(aa_rready),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[20]_i_1
(.I0(aa_rmesg[20]),
.I1(\skid_buffer_reg_n_0_[20] ),
.I2(aa_rready),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[21]_i_1
(.I0(aa_rmesg[21]),
.I1(\skid_buffer_reg_n_0_[21] ),
.I2(aa_rready),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[22]_i_1
(.I0(aa_rmesg[22]),
.I1(\skid_buffer_reg_n_0_[22] ),
.I2(aa_rready),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[23]_i_1
(.I0(aa_rmesg[23]),
.I1(\skid_buffer_reg_n_0_[23] ),
.I2(aa_rready),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[24]_i_1
(.I0(aa_rmesg[24]),
.I1(\skid_buffer_reg_n_0_[24] ),
.I2(aa_rready),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[25]_i_1
(.I0(aa_rmesg[25]),
.I1(\skid_buffer_reg_n_0_[25] ),
.I2(aa_rready),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[26]_i_1
(.I0(aa_rmesg[26]),
.I1(\skid_buffer_reg_n_0_[26] ),
.I2(aa_rready),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[27]_i_1
(.I0(aa_rmesg[27]),
.I1(\skid_buffer_reg_n_0_[27] ),
.I2(aa_rready),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[28]_i_1
(.I0(aa_rmesg[28]),
.I1(\skid_buffer_reg_n_0_[28] ),
.I2(aa_rready),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[29]_i_1
(.I0(aa_rmesg[29]),
.I1(\skid_buffer_reg_n_0_[29] ),
.I2(aa_rready),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[2]_i_1
(.I0(aa_rmesg[2]),
.I1(\skid_buffer_reg_n_0_[2] ),
.I2(aa_rready),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[30]_i_1
(.I0(aa_rmesg[30]),
.I1(\skid_buffer_reg_n_0_[30] ),
.I2(aa_rready),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[31]_i_1
(.I0(aa_rmesg[31]),
.I1(\skid_buffer_reg_n_0_[31] ),
.I2(aa_rready),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[32]_i_1
(.I0(aa_rmesg[32]),
.I1(\skid_buffer_reg_n_0_[32] ),
.I2(aa_rready),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[33]_i_1
(.I0(aa_rmesg[33]),
.I1(\skid_buffer_reg_n_0_[33] ),
.I2(aa_rready),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[34]_i_2
(.I0(aa_rmesg[34]),
.I1(\skid_buffer_reg_n_0_[34] ),
.I2(aa_rready),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[3]_i_1
(.I0(aa_rmesg[3]),
.I1(\skid_buffer_reg_n_0_[3] ),
.I2(aa_rready),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[4]_i_1
(.I0(aa_rmesg[4]),
.I1(\skid_buffer_reg_n_0_[4] ),
.I2(aa_rready),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[5]_i_1
(.I0(aa_rmesg[5]),
.I1(\skid_buffer_reg_n_0_[5] ),
.I2(aa_rready),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[6]_i_1
(.I0(aa_rmesg[6]),
.I1(\skid_buffer_reg_n_0_[6] ),
.I2(aa_rready),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[7]_i_1
(.I0(aa_rmesg[7]),
.I1(\skid_buffer_reg_n_0_[7] ),
.I2(aa_rready),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[8]_i_1
(.I0(aa_rmesg[8]),
.I1(\skid_buffer_reg_n_0_[8] ),
.I2(aa_rready),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hAC))
\m_payload_i[9]_i_1
(.I0(aa_rmesg[9]),
.I1(\skid_buffer_reg_n_0_[9] ),
.I2(aa_rready),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(1'b1),
.Q(\m_payload_i_reg_n_0_[0] ),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(\s_axi_rdata[95] [9]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(\s_axi_rdata[95] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(\s_axi_rdata[95] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(\s_axi_rdata[95] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(\s_axi_rdata[95] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(\s_axi_rdata[95] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(\s_axi_rdata[95] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(\s_axi_rdata[95] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(\s_axi_rdata[95] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(\s_axi_rdata[95] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(\s_axi_rdata[95] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(\s_axi_rdata[95] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(\s_axi_rdata[95] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(\s_axi_rdata[95] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(\s_axi_rdata[95] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(\s_axi_rdata[95] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(\s_axi_rdata[95] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(\s_axi_rdata[95] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(\s_axi_rdata[95] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(\s_axi_rdata[95] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(\s_axi_rdata[95] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(\s_axi_rdata[95] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(\s_axi_rdata[95] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(\s_axi_rdata[95] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(\s_axi_rdata[95] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(\s_axi_rdata[95] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(\s_axi_rdata[95] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(\s_axi_rdata[95] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(\s_axi_rdata[95] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(\s_axi_rdata[95] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(\s_axi_rdata[95] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(\s_axi_rdata[95] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(\s_axi_rdata[95] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(\s_axi_rdata[95] [8]),
.R(1'b0));
LUT3 #(
.INIT(8'h80))
\m_ready_d[1]_i_3
(.I0(\m_payload_i_reg_n_0_[0] ),
.I1(p_2_in),
.I2(sr_rvalid),
.O(\m_ready_d_reg[1] ));
LUT5 #(
.INIT(32'hF040F0F0))
m_valid_i_i_1
(.I0(p_2_in),
.I1(sr_rvalid),
.I2(\aresetn_d_reg_n_0_[1] ),
.I3(aa_rvalid),
.I4(aa_rready),
.O(m_valid_i_i_1_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF12021000))
m_valid_i_i_4
(.I0(m_atarget_enc[1]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_axi_rvalid[0]),
.I4(m_axi_rvalid[1]),
.I5(m_valid_i_i_6_n_0),
.O(s_ready_i_reg_0));
LUT5 #(
.INIT(32'h0A0000C0))
m_valid_i_i_6
(.I0(m_axi_rvalid[2]),
.I1(m_axi_rvalid[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(m_valid_i_i_6_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1_n_0),
.Q(sr_rvalid),
.R(1'b0));
LUT3 #(
.INIT(8'h02))
\s_axi_bresp[1]_INST_0_i_2
(.I0(m_atarget_enc[1]),
.I1(m_atarget_enc[0]),
.I2(m_atarget_enc[2]),
.O(\skid_buffer_reg[34]_0 ));
LUT3 #(
.INIT(8'h02))
\s_axi_bresp[1]_INST_0_i_3
(.I0(m_atarget_enc[0]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[1]),
.O(f_mux_return7));
LUT5 #(
.INIT(32'hB0B0F0B0))
s_ready_i_i_1
(.I0(p_2_in),
.I1(sr_rvalid),
.I2(p_0_in),
.I3(aa_rready),
.I4(aa_rvalid),
.O(s_ready_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1_n_0),
.Q(aa_rready),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[10]_i_1
(.I0(\skid_buffer[10]_i_2_n_0 ),
.I1(m_axi_rdata[71]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[39]),
.I4(f_mux_return7),
.I5(\skid_buffer[10]_i_3_n_0 ),
.O(aa_rmesg[10]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[10]_i_2
(.I0(m_axi_rdata[103]),
.I1(m_axi_rdata[135]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[10]_i_3
(.I0(m_axi_rdata[199]),
.I1(m_axi_rdata[167]),
.I2(m_axi_rdata[7]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[11]_i_1
(.I0(\skid_buffer[11]_i_2_n_0 ),
.I1(m_axi_rdata[72]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[40]),
.I4(f_mux_return7),
.I5(\skid_buffer[11]_i_3_n_0 ),
.O(aa_rmesg[11]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[11]_i_2
(.I0(m_axi_rdata[104]),
.I1(m_axi_rdata[136]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[11]_i_3
(.I0(m_axi_rdata[200]),
.I1(m_axi_rdata[168]),
.I2(m_axi_rdata[8]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[12]_i_1
(.I0(\skid_buffer[12]_i_2_n_0 ),
.I1(m_axi_rdata[73]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[41]),
.I4(f_mux_return7),
.I5(\skid_buffer[12]_i_3_n_0 ),
.O(aa_rmesg[12]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[12]_i_2
(.I0(m_axi_rdata[105]),
.I1(m_axi_rdata[137]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[12]_i_3
(.I0(m_axi_rdata[201]),
.I1(m_axi_rdata[169]),
.I2(m_axi_rdata[9]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[13]_i_1
(.I0(\skid_buffer[13]_i_2_n_0 ),
.I1(m_axi_rdata[74]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[42]),
.I4(f_mux_return7),
.I5(\skid_buffer[13]_i_3_n_0 ),
.O(aa_rmesg[13]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[13]_i_2
(.I0(m_axi_rdata[106]),
.I1(m_axi_rdata[138]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[13]_i_3
(.I0(m_axi_rdata[202]),
.I1(m_axi_rdata[170]),
.I2(m_axi_rdata[10]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[13]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[14]_i_1
(.I0(\skid_buffer[14]_i_2_n_0 ),
.I1(m_axi_rdata[75]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[43]),
.I4(f_mux_return7),
.I5(\skid_buffer[14]_i_3_n_0 ),
.O(aa_rmesg[14]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[14]_i_2
(.I0(m_axi_rdata[107]),
.I1(m_axi_rdata[139]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[14]_i_3
(.I0(m_axi_rdata[203]),
.I1(m_axi_rdata[171]),
.I2(m_axi_rdata[11]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[15]_i_1
(.I0(\skid_buffer[15]_i_2_n_0 ),
.I1(m_axi_rdata[76]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[44]),
.I4(f_mux_return7),
.I5(\skid_buffer[15]_i_3_n_0 ),
.O(aa_rmesg[15]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[15]_i_2
(.I0(m_axi_rdata[108]),
.I1(m_axi_rdata[140]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[15]_i_3
(.I0(m_axi_rdata[204]),
.I1(m_axi_rdata[172]),
.I2(m_axi_rdata[12]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[16]_i_1
(.I0(\skid_buffer[16]_i_2_n_0 ),
.I1(m_axi_rdata[77]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[45]),
.I4(f_mux_return7),
.I5(\skid_buffer[16]_i_3_n_0 ),
.O(aa_rmesg[16]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[16]_i_2
(.I0(m_axi_rdata[109]),
.I1(m_axi_rdata[141]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[16]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[16]_i_3
(.I0(m_axi_rdata[205]),
.I1(m_axi_rdata[173]),
.I2(m_axi_rdata[13]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[16]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[17]_i_1
(.I0(\skid_buffer[17]_i_2_n_0 ),
.I1(m_axi_rdata[78]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[46]),
.I4(f_mux_return7),
.I5(\skid_buffer[17]_i_3_n_0 ),
.O(aa_rmesg[17]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[17]_i_2
(.I0(m_axi_rdata[110]),
.I1(m_axi_rdata[142]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[17]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[17]_i_3
(.I0(m_axi_rdata[206]),
.I1(m_axi_rdata[174]),
.I2(m_axi_rdata[14]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[17]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[18]_i_1
(.I0(\skid_buffer[18]_i_2_n_0 ),
.I1(m_axi_rdata[79]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[47]),
.I4(f_mux_return7),
.I5(\skid_buffer[18]_i_3_n_0 ),
.O(aa_rmesg[18]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[18]_i_2
(.I0(m_axi_rdata[111]),
.I1(m_axi_rdata[143]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[18]_i_3
(.I0(m_axi_rdata[207]),
.I1(m_axi_rdata[175]),
.I2(m_axi_rdata[15]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[18]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[19]_i_1
(.I0(\skid_buffer[19]_i_2_n_0 ),
.I1(m_axi_rdata[80]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[48]),
.I4(f_mux_return7),
.I5(\skid_buffer[19]_i_3_n_0 ),
.O(aa_rmesg[19]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[19]_i_2
(.I0(m_axi_rdata[112]),
.I1(m_axi_rdata[144]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[19]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[19]_i_3
(.I0(m_axi_rdata[208]),
.I1(m_axi_rdata[176]),
.I2(m_axi_rdata[16]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[19]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[1]_i_1
(.I0(\skid_buffer[1]_i_2_n_0 ),
.I1(m_axi_rresp[4]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rresp[2]),
.I4(f_mux_return7),
.I5(\skid_buffer[1]_i_3_n_0 ),
.O(aa_rmesg[1]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[1]_i_2
(.I0(m_axi_rresp[6]),
.I1(m_axi_rresp[8]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF0A0C00FF0A0C000))
\skid_buffer[1]_i_3
(.I0(m_axi_rresp[12]),
.I1(m_axi_rresp[10]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_rresp[0]),
.O(\skid_buffer[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[20]_i_1
(.I0(\skid_buffer[20]_i_2_n_0 ),
.I1(m_axi_rdata[81]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[49]),
.I4(f_mux_return7),
.I5(\skid_buffer[20]_i_3_n_0 ),
.O(aa_rmesg[20]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[20]_i_2
(.I0(m_axi_rdata[113]),
.I1(m_axi_rdata[145]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[20]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[20]_i_3
(.I0(m_axi_rdata[209]),
.I1(m_axi_rdata[177]),
.I2(m_axi_rdata[17]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[20]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[21]_i_1
(.I0(\skid_buffer[21]_i_2_n_0 ),
.I1(m_axi_rdata[82]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[50]),
.I4(f_mux_return7),
.I5(\skid_buffer[21]_i_3_n_0 ),
.O(aa_rmesg[21]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[21]_i_2
(.I0(m_axi_rdata[114]),
.I1(m_axi_rdata[146]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[21]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[21]_i_3
(.I0(m_axi_rdata[210]),
.I1(m_axi_rdata[178]),
.I2(m_axi_rdata[18]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[21]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[22]_i_1
(.I0(\skid_buffer[22]_i_2_n_0 ),
.I1(m_axi_rdata[83]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[51]),
.I4(f_mux_return7),
.I5(\skid_buffer[22]_i_3_n_0 ),
.O(aa_rmesg[22]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[22]_i_2
(.I0(m_axi_rdata[115]),
.I1(m_axi_rdata[147]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[22]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[22]_i_3
(.I0(m_axi_rdata[211]),
.I1(m_axi_rdata[179]),
.I2(m_axi_rdata[19]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[22]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[23]_i_1
(.I0(\skid_buffer[23]_i_2_n_0 ),
.I1(m_axi_rdata[84]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[52]),
.I4(f_mux_return7),
.I5(\skid_buffer[23]_i_3_n_0 ),
.O(aa_rmesg[23]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[23]_i_2
(.I0(m_axi_rdata[116]),
.I1(m_axi_rdata[148]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[23]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[23]_i_3
(.I0(m_axi_rdata[212]),
.I1(m_axi_rdata[180]),
.I2(m_axi_rdata[20]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[23]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[24]_i_1
(.I0(\skid_buffer[24]_i_2_n_0 ),
.I1(m_axi_rdata[85]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[53]),
.I4(f_mux_return7),
.I5(\skid_buffer[24]_i_3_n_0 ),
.O(aa_rmesg[24]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[24]_i_2
(.I0(m_axi_rdata[117]),
.I1(m_axi_rdata[149]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[24]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[24]_i_3
(.I0(m_axi_rdata[213]),
.I1(m_axi_rdata[181]),
.I2(m_axi_rdata[21]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[24]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[25]_i_1
(.I0(\skid_buffer[25]_i_2_n_0 ),
.I1(m_axi_rdata[86]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[54]),
.I4(f_mux_return7),
.I5(\skid_buffer[25]_i_3_n_0 ),
.O(aa_rmesg[25]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[25]_i_2
(.I0(m_axi_rdata[118]),
.I1(m_axi_rdata[150]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[25]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[25]_i_3
(.I0(m_axi_rdata[214]),
.I1(m_axi_rdata[182]),
.I2(m_axi_rdata[22]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[25]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[26]_i_1
(.I0(\skid_buffer[26]_i_2_n_0 ),
.I1(m_axi_rdata[87]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[55]),
.I4(f_mux_return7),
.I5(\skid_buffer[26]_i_3_n_0 ),
.O(aa_rmesg[26]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[26]_i_2
(.I0(m_axi_rdata[119]),
.I1(m_axi_rdata[151]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[26]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[26]_i_3
(.I0(m_axi_rdata[215]),
.I1(m_axi_rdata[183]),
.I2(m_axi_rdata[23]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[26]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[27]_i_1
(.I0(\skid_buffer[27]_i_2_n_0 ),
.I1(m_axi_rdata[88]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[56]),
.I4(f_mux_return7),
.I5(\skid_buffer[27]_i_3_n_0 ),
.O(aa_rmesg[27]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[27]_i_2
(.I0(m_axi_rdata[120]),
.I1(m_axi_rdata[152]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[27]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[27]_i_3
(.I0(m_axi_rdata[216]),
.I1(m_axi_rdata[184]),
.I2(m_axi_rdata[24]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[27]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[28]_i_1
(.I0(\skid_buffer[28]_i_2_n_0 ),
.I1(m_axi_rdata[89]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[57]),
.I4(f_mux_return7),
.I5(\skid_buffer[28]_i_3_n_0 ),
.O(aa_rmesg[28]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[28]_i_2
(.I0(m_axi_rdata[121]),
.I1(m_axi_rdata[153]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[28]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[28]_i_3
(.I0(m_axi_rdata[217]),
.I1(m_axi_rdata[185]),
.I2(m_axi_rdata[25]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[28]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[29]_i_1
(.I0(\skid_buffer[29]_i_2_n_0 ),
.I1(m_axi_rdata[90]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[58]),
.I4(f_mux_return7),
.I5(\skid_buffer[29]_i_3_n_0 ),
.O(aa_rmesg[29]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[29]_i_2
(.I0(m_axi_rdata[122]),
.I1(m_axi_rdata[154]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[29]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[29]_i_3
(.I0(m_axi_rdata[218]),
.I1(m_axi_rdata[186]),
.I2(m_axi_rdata[26]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[29]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[2]_i_1
(.I0(\skid_buffer[2]_i_2_n_0 ),
.I1(m_axi_rresp[5]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rresp[3]),
.I4(f_mux_return7),
.I5(\skid_buffer[2]_i_3_n_0 ),
.O(aa_rmesg[2]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[2]_i_2
(.I0(m_axi_rresp[7]),
.I1(m_axi_rresp[9]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF0A0C00FF0A0C000))
\skid_buffer[2]_i_3
(.I0(m_axi_rresp[13]),
.I1(m_axi_rresp[11]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_rresp[1]),
.O(\skid_buffer[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[30]_i_1
(.I0(\skid_buffer[30]_i_2_n_0 ),
.I1(m_axi_rdata[91]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[59]),
.I4(f_mux_return7),
.I5(\skid_buffer[30]_i_3_n_0 ),
.O(aa_rmesg[30]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[30]_i_2
(.I0(m_axi_rdata[123]),
.I1(m_axi_rdata[155]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[30]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[30]_i_3
(.I0(m_axi_rdata[219]),
.I1(m_axi_rdata[187]),
.I2(m_axi_rdata[27]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[30]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[31]_i_1
(.I0(\skid_buffer[31]_i_2_n_0 ),
.I1(m_axi_rdata[92]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[60]),
.I4(f_mux_return7),
.I5(\skid_buffer[31]_i_3_n_0 ),
.O(aa_rmesg[31]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[31]_i_2
(.I0(m_axi_rdata[124]),
.I1(m_axi_rdata[156]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[31]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[31]_i_3
(.I0(m_axi_rdata[220]),
.I1(m_axi_rdata[188]),
.I2(m_axi_rdata[28]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[31]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[32]_i_1
(.I0(\skid_buffer[32]_i_2_n_0 ),
.I1(m_axi_rdata[93]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[61]),
.I4(f_mux_return7),
.I5(\skid_buffer[32]_i_3_n_0 ),
.O(aa_rmesg[32]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[32]_i_2
(.I0(m_axi_rdata[125]),
.I1(m_axi_rdata[157]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[32]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[32]_i_3
(.I0(m_axi_rdata[221]),
.I1(m_axi_rdata[189]),
.I2(m_axi_rdata[29]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[32]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[33]_i_1
(.I0(\skid_buffer[33]_i_2_n_0 ),
.I1(m_axi_rdata[94]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[62]),
.I4(f_mux_return7),
.I5(\skid_buffer[33]_i_3_n_0 ),
.O(aa_rmesg[33]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[33]_i_2
(.I0(m_axi_rdata[126]),
.I1(m_axi_rdata[158]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[33]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[33]_i_3
(.I0(m_axi_rdata[222]),
.I1(m_axi_rdata[190]),
.I2(m_axi_rdata[30]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[33]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[34]_i_1
(.I0(\skid_buffer[34]_i_2_n_0 ),
.I1(m_axi_rdata[95]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[63]),
.I4(f_mux_return7),
.I5(\skid_buffer[34]_i_3_n_0 ),
.O(aa_rmesg[34]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[34]_i_2
(.I0(m_axi_rdata[127]),
.I1(m_axi_rdata[159]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[34]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[34]_i_3
(.I0(m_axi_rdata[223]),
.I1(m_axi_rdata[191]),
.I2(m_axi_rdata[31]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[34]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[3]_i_1
(.I0(\skid_buffer[3]_i_2_n_0 ),
.I1(m_axi_rdata[64]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[32]),
.I4(f_mux_return7),
.I5(\skid_buffer[3]_i_3_n_0 ),
.O(aa_rmesg[3]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[3]_i_2
(.I0(m_axi_rdata[96]),
.I1(m_axi_rdata[128]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[3]_i_3
(.I0(m_axi_rdata[192]),
.I1(m_axi_rdata[160]),
.I2(m_axi_rdata[0]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[4]_i_1
(.I0(\skid_buffer[4]_i_2_n_0 ),
.I1(m_axi_rdata[65]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[33]),
.I4(f_mux_return7),
.I5(\skid_buffer[4]_i_3_n_0 ),
.O(aa_rmesg[4]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[4]_i_2
(.I0(m_axi_rdata[97]),
.I1(m_axi_rdata[129]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[4]_i_3
(.I0(m_axi_rdata[193]),
.I1(m_axi_rdata[161]),
.I2(m_axi_rdata[1]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[5]_i_1
(.I0(\skid_buffer[5]_i_2_n_0 ),
.I1(m_axi_rdata[66]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[34]),
.I4(f_mux_return7),
.I5(\skid_buffer[5]_i_3_n_0 ),
.O(aa_rmesg[5]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[5]_i_2
(.I0(m_axi_rdata[98]),
.I1(m_axi_rdata[130]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[5]_i_3
(.I0(m_axi_rdata[194]),
.I1(m_axi_rdata[162]),
.I2(m_axi_rdata[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[6]_i_1
(.I0(\skid_buffer[6]_i_2_n_0 ),
.I1(m_axi_rdata[67]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[35]),
.I4(f_mux_return7),
.I5(\skid_buffer[6]_i_3_n_0 ),
.O(aa_rmesg[6]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[6]_i_2
(.I0(m_axi_rdata[99]),
.I1(m_axi_rdata[131]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[6]_i_3
(.I0(m_axi_rdata[195]),
.I1(m_axi_rdata[163]),
.I2(m_axi_rdata[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[7]_i_1
(.I0(\skid_buffer[7]_i_2_n_0 ),
.I1(m_axi_rdata[68]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[36]),
.I4(f_mux_return7),
.I5(\skid_buffer[7]_i_3_n_0 ),
.O(aa_rmesg[7]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[7]_i_2
(.I0(m_axi_rdata[100]),
.I1(m_axi_rdata[132]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[7]_i_3
(.I0(m_axi_rdata[196]),
.I1(m_axi_rdata[164]),
.I2(m_axi_rdata[4]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[8]_i_1
(.I0(\skid_buffer[8]_i_2_n_0 ),
.I1(m_axi_rdata[69]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[37]),
.I4(f_mux_return7),
.I5(\skid_buffer[8]_i_3_n_0 ),
.O(aa_rmesg[8]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[8]_i_2
(.I0(m_axi_rdata[101]),
.I1(m_axi_rdata[133]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[8]_i_3
(.I0(m_axi_rdata[197]),
.I1(m_axi_rdata[165]),
.I2(m_axi_rdata[5]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[8]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFEAEAEA))
\skid_buffer[9]_i_1
(.I0(\skid_buffer[9]_i_2_n_0 ),
.I1(m_axi_rdata[70]),
.I2(\skid_buffer_reg[34]_0 ),
.I3(m_axi_rdata[38]),
.I4(f_mux_return7),
.I5(\skid_buffer[9]_i_3_n_0 ),
.O(aa_rmesg[9]));
LUT5 #(
.INIT(32'h0A0000C0))
\skid_buffer[9]_i_2
(.I0(m_axi_rdata[102]),
.I1(m_axi_rdata[134]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.O(\skid_buffer[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00CCAA00000000F0))
\skid_buffer[9]_i_3
(.I0(m_axi_rdata[198]),
.I1(m_axi_rdata[166]),
.I2(m_axi_rdata[6]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[2]),
.O(\skid_buffer[9]_i_3_n_0 ));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[34]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(aa_rready),
.D(aa_rmesg[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
(** * StlcProp: Properties of STLC *)
Require Export Stlc.
Module STLCProp.
Import STLC.
(** In this chapter, we develop the fundamental theory of the Simply
Typed Lambda Calculus -- in particular, the type safety
theorem. *)
(* ###################################################################### *)
(** * Canonical Forms *)
Lemma canonical_forms_bool : forall t,
empty |- t \in TBool ->
value t ->
(t = ttrue) \/ (t = tfalse).
Proof.
intros t HT HVal.
inversion HVal; intros; subst; try inversion HT; auto.
Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Proof.
intros t T1 T2 HT HVal.
inversion HVal; intros; subst; try inversion HT; subst; auto.
exists x0. exists t0. auto.
Qed.
(* ###################################################################### *)
(** * Progress *)
(** As before, the _progress_ theorem tells us that closed, well-typed
terms are not stuck: either a well-typed term is a value, or it
can take an evaluation step. The proof is a relatively
straightforward extension of the progress proof we saw in the
[Types] chapter. *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
(** _Proof_: by induction on the derivation of [|- t \in T].
- The last rule of the derivation cannot be [T_Var], since a
variable is never well typed in an empty context.
- The [T_True], [T_False], and [T_Abs] cases are trivial, since in
each of these cases we know immediately that [t] is a value.
- If the last rule of the derivation was [T_App], then [t = t1
t2], and we know that [t1] and [t2] are also well typed in the
empty context; in particular, there exists a type [T2] such that
[|- t1 \in T2 -> T] and [|- t2 \in T2]. By the induction
hypothesis, either [t1] is a value or it can take an evaluation
step.
- If [t1] is a value, we now consider [t2], which by the other
induction hypothesis must also either be a value or take an
evaluation step.
- Suppose [t2] is a value. Since [t1] is a value with an
arrow type, it must be a lambda abstraction; hence [t1
t2] can take a step by [ST_AppAbs].
- Otherwise, [t2] can take a step, and hence so can [t1
t2] by [ST_App2].
- If [t1] can take a step, then so can [t1 t2] by [ST_App1].
- If the last rule of the derivation was [T_If], then [t = if t1
then t2 else t3], where [t1] has type [Bool]. By the IH, [t1]
either is a value or takes a step.
- If [t1] is a value, then since it has type [Bool] it must be
either [true] or [false]. If it is [true], then [t] steps
to [t2]; otherwise it steps to [t3].
- Otherwise, [t1] takes a step, and therefore so does [t] (by
[ST_If]).
*)
Proof with eauto.
intros t T Ht.
remember (@empty ty) as Gamma.
has_type_cases (induction Ht) Case; subst Gamma...
Case "T_Var".
(* contradictory: variables cannot be typed in an
empty context *)
inversion H.
Case "T_App".
(* [t] = [t1 t2]. Proceed by cases on whether [t1] is a
value or steps... *)
right. destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is also a value".
assert (exists x0 t0, t1 = tabs x0 T11 t0).
eapply canonical_forms_fun; eauto.
destruct H1 as [x0 [t0 Heq]]. subst.
exists ([x0:=t2]t0)...
SSCase "t2 steps".
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_If".
right. destruct IHHt1...
SCase "t1 is a value".
destruct (canonical_forms_bool t1); subst; eauto.
SCase "t1 also steps".
inversion H as [t1' Hstp]. exists (tif t1' t2 t3)...
Qed.
(** **** Exercise: 3 stars, optional (progress_from_term_ind) *)
(** Show that progress can also be proved by induction on terms
instead of induction on typing derivations. *)
Theorem progress' : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof.
intros t.
t_cases (induction t) Case; intros T Ht; auto.
Case "tvar".
inversion Ht; subst.
inversion H1.
Case "tapp".
inversion Ht; subst.
right.
assert (\empty |- t1 \in TArrow T11 T) by apply H2.
apply IHt1 in H2.
apply IHt2 in H4.
destruct H2.
destruct H4.
assert (exists x u, t1 = tabs x T11 u).
eapply canonical_forms_fun.
apply H.
apply H0.
inversion H2; subst; clear H2.
inversion H3; subst; clear H3.
eauto.
inversion H1; subst; clear H1.
eauto.
inversion H0; subst; clear H0.
eauto.
Case "tif".
inversion Ht; subst.
right.
assert (\empty |- t1 \in TBool) by apply H3.
apply IHt1 in H3.
destruct H3.
assert (t1 = ttrue \/ t1 = tfalse).
apply canonical_forms_bool.
apply H.
apply H0.
destruct H1; rewrite H1; eauto.
inversion H0; subst.
eauto.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Preservation *)
(** The other half of the type soundness property is the preservation
of types during reduction. For this, we need to develop some
technical machinery for reasoning about variables and
substitution. Working from top to bottom (the high-level property
we are actually interested in to the lowest-level technical lemmas
that are needed by various cases of the more interesting proofs),
the story goes like this:
- The _preservation theorem_ is proved by induction on a typing
derivation, pretty much as we did in the [Types] chapter. The
one case that is significantly different is the one for the
[ST_AppAbs] rule, which is defined using the substitution
operation. To see that this step preserves typing, we need to
know that the substitution itself does. So we prove a...
- _substitution lemma_, stating that substituting a (closed)
term [s] for a variable [x] in a term [t] preserves the type
of [t]. The proof goes by induction on the form of [t] and
requires looking at all the different cases in the definition
of substitition. This time, the tricky cases are the ones for
variables and for function abstractions. In both cases, we
discover that we need to take a term [s] that has been shown
to be well-typed in some context [Gamma] and consider the same
term [s] in a slightly different context [Gamma']. For this
we prove a...
- _context invariance_ lemma, showing that typing is preserved
under "inessential changes" to the context [Gamma] -- in
particular, changes that do not affect any of the free
variables of the term. For this, we need a careful definition
of
- the _free variables_ of a term -- i.e., the variables occuring
in the term that are not in the scope of a function
abstraction that binds them.
*)
(* ###################################################################### *)
(** ** Free Occurrences *)
(** A variable [x] _appears free in_ a term _t_ if [t] contains some
occurrence of [x] that is not under an abstraction labeled [x]. For example:
- [y] appears free, but [x] does not, in [\x:T->U. x y]
- both [x] and [y] appear free in [(\x:T->U. x y) x]
- no variables appear free in [\x:T->U. \y:T. x y] *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3).
Tactic Notation "afi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "afi_var"
| Case_aux c "afi_app1" | Case_aux c "afi_app2"
| Case_aux c "afi_abs"
| Case_aux c "afi_if1" | Case_aux c "afi_if2"
| Case_aux c "afi_if3" ].
Hint Constructors appears_free_in.
(** A term in which no variables appear free is said to be _closed_. *)
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
(* ###################################################################### *)
(** ** Substitution *)
(** We first need a technical lemma connecting free variables and
typing contexts. If a variable [x] appears free in a term [t],
and if we know [t] is well typed in context [Gamma], then it must
be the case that [Gamma] assigns a type to [x]. *)
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
(** _Proof_: We show, by induction on the proof that [x] appears free
in [t], that, for all contexts [Gamma], if [t] is well typed
under [Gamma], then [Gamma] assigns some type to [x].
- If the last rule used was [afi_var], then [t = x], and from
the assumption that [t] is well typed under [Gamma] we have
immediately that [Gamma] assigns a type to [x].
- If the last rule used was [afi_app1], then [t = t1 t2] and [x]
appears free in [t1]. Since [t] is well typed under [Gamma],
we can see from the typing rules that [t1] must also be, and
the IH then tells us that [Gamma] assigns [x] a type.
- Almost all the other cases are similar: [x] appears free in a
subterm of [t], and since [t] is well typed under [Gamma], we
know the subterm of [t] in which [x] appears is well typed
under [Gamma] as well, and the IH gives us exactly the
conclusion we want.
- The only remaining case is [afi_abs]. In this case [t =
\y:T11.t12], and [x] appears free in [t12]; we also know that
[x] is different from [y]. The difference from the previous
cases is that whereas [t] is well typed under [Gamma], its
body [t12] is well typed under [(Gamma, y:T11)], so the IH
allows us to conclude that [x] is assigned some type by the
extended context [(Gamma, y:T11)]. To conclude that [Gamma]
assigns a type to [x], we appeal to lemma [extend_neq], noting
that [x] and [y] are different variables. *)
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
afi_cases (induction H) Case;
intros; try solve [inversion H0; eauto].
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite extend_neq in H7; assumption.
Qed.
(** Next, we'll need the fact that any term [t] which is well typed in
the empty context is closed -- that is, it has no free variables. *)
(** **** Exercise: 2 stars, optional (typable_empty__closed) *)
Corollary typable_empty__closed : forall t T,
empty |- t \in T ->
closed t.
Proof.
intros t T H x H1.
assert (exists T' : ty, \empty x = Some T').
eapply free_in_context; eauto.
inversion H0.
inversion H2.
Qed.
(** [] *)
(** Sometimes, when we have a proof [Gamma |- t : T], we will need to
replace [Gamma] by a different context [Gamma']. When is it safe
to do this? Intuitively, it must at least be the case that
[Gamma'] assigns the same types as [Gamma] to all the variables
that appear free in [t]. In fact, this is the only condition that
is needed. *)
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
(** _Proof_: By induction on the derivation of [Gamma |- t \in T].
- If the last rule in the derivation was [T_Var], then [t = x]
and [Gamma x = T]. By assumption, [Gamma' x = T] as well, and
hence [Gamma' |- t \in T] by [T_Var].
- If the last rule was [T_Abs], then [t = \y:T11. t12], with [T
= T11 -> T12] and [Gamma, y:T11 |- t12 \in T12]. The induction
hypothesis is that for any context [Gamma''], if [Gamma,
y:T11] and [Gamma''] assign the same types to all the free
variables in [t12], then [t12] has type [T12] under [Gamma''].
Let [Gamma'] be a context which agrees with [Gamma] on the
free variables in [t]; we must show [Gamma' |- \y:T11. t12 \in
T11 -> T12].
By [T_Abs], it suffices to show that [Gamma', y:T11 |- t12 \in
T12]. By the IH (setting [Gamma'' = Gamma', y:T11]), it
suffices to show that [Gamma, y:T11] and [Gamma', y:T11] agree
on all the variables that appear free in [t12].
Any variable occurring free in [t12] must either be [y], or
some other variable. [Gamma, y:T11] and [Gamma', y:T11]
clearly agree on [y]. Otherwise, we note that any variable
other than [y] which occurs free in [t12] also occurs free in
[t = \y:T11. t12], and by assumption [Gamma] and [Gamma']
agree on all such variables, and hence so do [Gamma, y:T11]
and [Gamma', y:T11].
- If the last rule was [T_App], then [t = t1 t2], with [Gamma |-
t1 \in T2 -> T] and [Gamma |- t2 \in T2]. One induction
hypothesis states that for all contexts [Gamma'], if [Gamma']
agrees with [Gamma] on the free variables in [t1], then [t1]
has type [T2 -> T] under [Gamma']; there is a similar IH for
[t2]. We must show that [t1 t2] also has type [T] under
[Gamma'], given the assumption that [Gamma'] agrees with
[Gamma] on all the free variables in [t1 t2]. By [T_App], it
suffices to show that [t1] and [t2] each have the same type
under [Gamma'] as under [Gamma]. However, we note that all
free variables in [t1] are also free in [t1 t2], and similarly
for free variables in [t2]; hence the desired result follows
by the two IHs.
*)
Proof with eauto.
intros.
generalize dependent Gamma'.
has_type_cases (induction H) Case; intros; auto.
Case "T_Var".
apply T_Var. rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [extend Gamma x T11] *)
unfold extend. destruct (eq_id_dec x0 x1)...
Case "T_App".
apply T_App with T11...
Qed.
(** Now we come to the conceptual heart of the proof that reduction
preserves types -- namely, the observation that _substitution_
preserves types.
Formally, the so-called _Substitution Lemma_ says this: suppose we
have a term [t] with a free variable [x], and suppose we've been
able to assign a type [T] to [t] under the assumption that [x] has
some type [U]. Also, suppose that we have some other term [v] and
that we've shown that [v] has type [U]. Then, since [v] satisfies
the assumption we made about [x] when typing [t], we should be
able to substitute [v] for each of the occurrences of [x] in [t]
and obtain a new term that still has type [T]. *)
(** _Lemma_: If [Gamma,x:U |- t \in T] and [|- v \in U], then [Gamma |-
[x:=v]t \in T]. *)
Lemma substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
(** One technical subtlety in the statement of the lemma is that we
assign [v] the type [U] in the _empty_ context -- in other words,
we assume [v] is closed. This assumption considerably simplifies
the [T_Abs] case of the proof (compared to assuming [Gamma |- v \in
U], which would be the other reasonable assumption at this point)
because the context invariance lemma then tells us that [v] has
type [U] in any context at all -- we don't have to worry about
free variables in [v] clashing with the variable being introduced
into the context by [T_Abs].
_Proof_: We prove, by induction on [t], that, for all [T] and
[Gamma], if [Gamma,x:U |- t \in T] and [|- v \in U], then [Gamma |-
[x:=v]t \in T].
- If [t] is a variable, there are two cases to consider, depending
on whether [t] is [x] or some other variable.
- If [t = x], then from the fact that [Gamma, x:U |- x \in T] we
conclude that [U = T]. We must show that [[x:=v]x = v] has
type [T] under [Gamma], given the assumption that [v] has
type [U = T] under the empty context. This follows from
context invariance: if a closed term has type [T] in the
empty context, it has that type in any context.
- If [t] is some variable [y] that is not equal to [x], then
we need only note that [y] has the same type under [Gamma,
x:U] as under [Gamma].
- If [t] is an abstraction [\y:T11. t12], then the IH tells us,
for all [Gamma'] and [T'], that if [Gamma',x:U |- t12 \in T']
and [|- v \in U], then [Gamma' |- [x:=v]t12 \in T'].
The substitution in the conclusion behaves differently,
depending on whether [x] and [y] are the same variable name.
First, suppose [x = y]. Then, by the definition of
substitution, [[x:=v]t = t], so we just need to show [Gamma |-
t \in T]. But we know [Gamma,x:U |- t : T], and since the
variable [y] does not appear free in [\y:T11. t12], the
context invariance lemma yields [Gamma |- t \in T].
Second, suppose [x <> y]. We know [Gamma,x:U,y:T11 |- t12 \in
T12] by inversion of the typing relation, and [Gamma,y:T11,x:U
|- t12 \in T12] follows from this by the context invariance
lemma, so the IH applies, giving us [Gamma,y:T11 |- [x:=v]t12 \in
T12]. By [T_Abs], [Gamma |- \y:T11. [x:=v]t12 \in T11->T12], and
by the definition of substitution (noting that [x <> y]),
[Gamma |- \y:T11. [x:=v]t12 \in T11->T12] as required.
- If [t] is an application [t1 t2], the result follows
straightforwardly from the definition of substitution and the
induction hypotheses.
- The remaining cases are similar to the application case.
Another technical note: This proof is a rare case where an
induction on terms, rather than typing derivations, yields a
simpler argument. The reason for this is that the assumption
[extend Gamma x U |- t \in T] is not completely generic, in
the sense that one of the "slots" in the typing relation -- namely
the context -- is not just a variable, and this means that Coq's
native induction tactic does not give us the induction hypothesis
that we want. It is possible to work around this, but the needed
generalization is a little tricky. The term [t], on the other
hand, _is_ completely generic. *)
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma. generalize dependent T.
t_cases (induction t) Case; intros T Gamma H;
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
Case "tvar".
rename i into y. destruct (eq_id_dec x y).
SCase "x=y".
subst.
rewrite extend_eq in H2.
inversion H2; subst. clear H2.
eapply context_invariance... intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
apply T_Var. rewrite extend_neq in H2...
Case "tabs".
rename i into y. apply T_Abs.
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
(** The substitution lemma can be viewed as a kind of "commutation"
property. Intuitively, it says that substitution and typing can
be done in either order: we can either assign types to the terms
[t] and [v] separately (under suitable contexts) and then combine
them using substitution, or we can substitute first and then
assign a type to [ [x:=v] t ] -- the result is the same either
way. *)
(* ###################################################################### *)
(** ** Main Theorem *)
(** We now have the tools we need to prove preservation: if a closed
term [t] has type [T], and takes an evaluation step to [t'], then [t']
is also a closed term with type [T]. In other words, the small-step
evaluation relation preserves types.
*)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
(** _Proof_: by induction on the derivation of [|- t \in T].
- We can immediately rule out [T_Var], [T_Abs], [T_True], and
[T_False] as the final rules in the derivation, since in each of
these cases [t] cannot take a step.
- If the last rule in the derivation was [T_App], then [t = t1
t2]. There are three cases to consider, one for each rule that
could have been used to show that [t1 t2] takes a step to [t'].
- If [t1 t2] takes a step by [ST_App1], with [t1] stepping to
[t1'], then by the IH [t1'] has the same type as [t1], and
hence [t1' t2] has the same type as [t1 t2].
- The [ST_App2] case is similar.
- If [t1 t2] takes a step by [ST_AppAbs], then [t1 =
\x:T11.t12] and [t1 t2] steps to [[x:=t2]t12]; the
desired result now follows from the fact that substitution
preserves types.
- If the last rule in the derivation was [T_If], then [t = if t1
then t2 else t3], and there are again three cases depending on
how [t] steps.
- If [t] steps to [t2] or [t3], the result is immediate, since
[t2] and [t3] have the same type as [t].
- Otherwise, [t] steps by [ST_If], and the desired conclusion
follows directly from the induction hypothesis.
*)
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HE; subst Gamma; subst;
try solve [inversion HE; subst; auto].
Case "T_App".
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [eauto] takes care of them *)
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
Qed.
(** **** Exercise: 2 stars (subject_expansion_stlc) *)
(** An exercise in the [Types] chapter asked about the subject
expansion property for the simple language of arithmetic and
boolean expressions. Does this property hold for STLC? That is,
is it always the case that, if [t ==> t'] and [has_type t' T],
then [empty |- t \in T]? If so, prove it. If not, give a
counter-example not involving conditionals.
No, [tif ttrue ttrue (tvar x)] is a counter example.
[]
*)
Example subject_expansion_stlc_false : exists t t' T,
t ==> t' /\ empty |- t' \in T /\ ~ empty |- t \in T.
Proof.
exists (tif ttrue ttrue (tvar x)).
repeat eapply ex_intro.
repeat split.
repeat constructor.
apply T_True.
intros H.
inversion H; subst; clear H.
inversion H7; subst; clear H7.
inversion H1.
Qed.
(* ###################################################################### *)
(** * Type Soundness *)
(** **** Exercise: 2 stars, optional (type_soundness) *)
(** Put progress and preservation together and show that a well-typed
term can _never_ reach a stuck state. *)
Definition stuck (t:tm) : Prop :=
(normal_form step) t /\ ~ value t.
Corollary soundness : forall t t' T,
empty |- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T Hhas_type Hmulti. unfold stuck.
intros [Hnf Hnot_val]. unfold normal_form in Hnf.
induction Hmulti.
apply progress in Hhas_type.
destruct Hhas_type; eauto.
apply IHHmulti; eauto.
eapply preservation; eauto.
Qed.
(* ###################################################################### *)
(** * Uniqueness of Types *)
(** **** Exercise: 3 stars (types_unique) *)
(** Another pleasant property of the STLC is that types are
unique: a given term (in a given context) has at most one
type. *)
(** Formalize this statement and prove it. *)
Theorem types_unique : forall t gamma T T',
T <> T' -> gamma |- t \in T -> ~ gamma |- t \in T'.
Proof.
intros t.
t_cases (induction t) Case; intros gamma T T' H H0 H1;
inversion H0; subst; clear H0;
inversion H1; subst; clear H1.
Case "tvar".
rewrite H4 in H3.
inversion H3.
contradiction.
Case "tapp".
eapply IHt1 in H5.
apply H5.
apply H4.
intros H1.
inversion H1; subst; clear H1.
eauto.
Case "tabs".
eapply IHt in H6.
apply H6.
apply H7.
intros H1.
inversion H1; subst.
eauto.
Case "ttrue".
eauto.
Case "tfalse".
eauto.
Case "tif".
eapply IHt2 in H8; eauto.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 1 star (progress_preservation_statement) *)
(** Without peeking, write down the progress and preservation
theorems for the simply typed lambda-calculus. *)
(* progress : If some [tm] has type, it's a value or it can make a step *)
(* preservation : If some [tm] has type and make a step, the stepped [tm] also has that type *)
(** [] *)
(** **** Exercise: 2 stars (stlc_variation1) *)
(** Suppose we add a new term [zap] with the following reduction rule:
--------- (ST_Zap)
t ==> zap
and the following typing rule:
---------------- (T_Zap)
Gamma |- zap : T
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
becomes false
[tif ttrue ttrue tfalse] ==> [ttrue] by [ST_IfTrue]
[tif ttrue ttrue tfalse] ==> [zap] by [ST_Zap]
- Progress
remains true
- Preservation
becomes false
[ttrue] : [TBool]
[zap] : [T]
[]
*)
(** **** Exercise: 2 stars (stlc_variation2) *)
(** Suppose instead that we add a new term [foo] with the following reduction rules:
----------------- (ST_Foo1)
(\x:A. x) ==> foo
------------ (ST_Foo2)
foo ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
becomse false
[(\x:Bool .x) ttrue] ==> [ttrue] by [ST_AppAbs]
[(\x:Bool .x) ttrue] ==> [foo true] by [ST_Foo1]
- Progress
remains true
- Preservation
becomes false
[\x:A. x] : [A -> A]
[foo] : None
[]
*)
(** **** Exercise: 2 stars (stlc_variation3) *)
(** Suppose instead that we remove the rule [ST_App1] from the [step]
relation. Which of the following properties of the STLC remain
true in the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
remains true
- Progress
becomes false
[(tif ttrue idB idB) ttrue]
- Preservation
remains true
[]
*)
(** **** Exercise: 2 stars, optional (stlc_variation4) *)
(** Suppose instead that we add the following new rule to the reduction relation:
---------------------------------- (ST_FunnyIfTrue)
(if true then t1 else t2) ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
becomes false
[tif ttrue tfalse tfalse] ==> [tfalse] by [ST_IfTrue]
[tif ttrue tfalse tfalse] ==> [ttrue] by [ST_FunnyIfTrue]
- Progress
remains true
- Preservation
becomes false
[tif ttrue idB idB] : Bool -> Bool
[ttrue] : Bool
*)
(** **** Exercise: 2 stars, optional (stlc_variation5) *)
(** Suppose instead that we add the following new rule to the typing relation:
Gamma |- t1 \in Bool->Bool->Bool
Gamma |- t2 \in Bool
------------------------------ (T_FunnyApp)
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
remains true
- Progress
remains true
- Preservation
becomes false
[(\x:Bool. \y:Bool. x) ttrue] : Bool
[(\y:Bool. ttrue)] : Bool -> Bool
*)
(** **** Exercise: 2 stars, optional (stlc_variation6) *)
(** Suppose instead that we add the following new rule to the typing relation:
Gamma |- t1 \in Bool
Gamma |- t2 \in Bool
--------------------- (T_FunnyApp')
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
remains true
- Progress
becomes false
[ttrue ttrue]
- Preservation
remains true
*)
(** **** Exercise: 2 stars, optional (stlc_variation7) *)
(** Suppose we add the following new rule to the typing
relation of the STLC:
------------------- (T_FunnyAbs)
|- \x:Bool.t \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
remains true
- Progress
remains true
- Preservation
becomes false
[idBB idB] : Bool -> Bool
[idB] : Bool
[]
*)
End STLCProp.
(* ###################################################################### *)
(* ###################################################################### *)
(** ** Exercise: STLC with Arithmetic *)
(** To see how the STLC might function as the core of a real
programming language, let's extend it with a concrete base
type of numbers and some constants and primitive
operators. *)
Module STLCArith.
(** To types, we add a base type of natural numbers (and remove
booleans, for brevity) *)
Inductive ty : Type :=
| TArrow : ty -> ty -> ty
| TNat : ty.
(** To terms, we add natural number constants, along with
successor, predecessor, multiplication, and zero-testing... *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "tnat"
| Case_aux c "tsucc" | Case_aux c "tpred"
| Case_aux c "tmult" | Case_aux c "tif0" ].
(** **** Exercise: 4 stars (stlc_arith) *)
(** Finish formalizing the definition and properties of the STLC extended
with arithmetic. Specifically:
- Copy the whole development of STLC that we went through above (from
the definition of values through the Progress theorem), and
paste it into the file at this point.
- Extend the definitions of the [subst] operation and the [step]
relation to include appropriate clauses for the arithmetic operators.
- Extend the proofs of all the properties (up to [soundness]) of
the original STLC to deal with the new syntactic forms. Make
sure Coq accepts the whole file. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_nat : forall x,
value (tnat x).
Hint Constructors value.
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tabs x' T t1 =>
tabs x' T (if eq_id_dec x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| tnat n =>
tnat n
| tsucc t =>
tsucc ([x:=s] t)
| tpred t =>
tpred ([x:=s] t)
| tmult t1 t2 =>
tmult ([x:=s] t1) ([x:=s] t2)
| tif0 t1 t2 t3 =>
tif0 ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
end
where "'[' x ':=' s ']' t" := (subst x s t).
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif0 (tnat 0) t1 t2) ==> t1
| ST_IfFalse : forall n t1 t2,
n <> 0 ->
(tif0 (tnat n) t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif0 t1 t2 t3) ==> (tif0 t1' t2 t3)
| ST_Succ : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_Mult1 : forall t1 t1' t2,
t1 ==> t1' ->
(tmult t1 t2) ==> (tmult t1' t2)
| ST_Mult2 : forall t1 t2 t2',
value t1 ->
t2 ==> t2' ->
(tmult t1 t2) ==> (tmult t1 t2')
| ST_SuccNat : forall n,
(tsucc (tnat n)) ==> (tnat (n + 1))
| ST_PredNat : forall n,
(tpred (tnat n)) ==> (tnat (n - 1))
| ST_MultNat : forall n1 n2,
(tmult (tnat n1) (tnat n2)) ==> (tnat (n1 * n2))
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
| Case_aux c "ST_Succ" | Case_aux c "ST_Pred"
| Case_aux c "ST_Mult1" | Case_aux c "ST_Mult2"
| Case_aux c "ST_SuccNat" | Case_aux c "ST_PredNat"
| Case_aux c "ST_MultNat" ].
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Theorem step_deterministic : deterministic step.
Proof with eauto.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2;
inversion Hy2; subst; try (solve by inversion)...
Case "ST_AppAbs".
inversion H4; subst; try (solve by inversion)...
Case "ST_App1".
apply IHHy1 in H2.
rewrite H2...
inversion H1; subst; inversion Hy1.
Case "ST_App2".
inversion H3; subst; inversion Hy1.
inversion H; subst; inversion H3.
apply IHHy1 in H4.
rewrite H4...
Case "ST_IfTrue".
exfalso.
apply H3...
Case "ST_IfFalse".
exfalso.
apply H...
Case "ST_If".
apply IHHy1 in H3.
rewrite H3...
Case "ST_Succ".
apply IHHy1 in H0.
rewrite H0...
Case "ST_Pred".
apply IHHy1 in H0.
rewrite H0...
Case "ST_Mult1".
apply IHHy1 in H2.
rewrite H2...
inversion H1; subst; inversion Hy1.
Case "ST_Mult2".
inversion H; subst; inversion H3.
apply IHHy1 in H4.
rewrite H4...
Qed.
Definition context := partial_map ty.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_Nat : forall Gamma n,
Gamma |- (tnat n) \in TNat
| T_If0 : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif0 t1 t2 t3 \in T
| T_Succ : forall Gamma t,
Gamma |- t \in TNat ->
Gamma |- tsucc t \in TNat
| T_Pred : forall Gamma t,
Gamma |- t \in TNat ->
Gamma |- tpred t \in TNat
| T_Mult : forall Gamma t1 t2,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in TNat ->
Gamma |- tmult t1 t2 \in TNat
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_Nat"
| Case_aux c "T_If0" | Case_aux c "T_Succ"
| Case_aux c "T_Pred" | Case_aux c "T_Mult" ].
Hint Constructors has_type.
Lemma canonical_forms_nat : forall t,
empty |- t \in TNat ->
value t ->
exists n, t = tnat n.
Proof.
intros t HT HVal.
inversion HVal; intros; subst; try inversion HT; auto.
exists n.
rewrite H1.
auto.
Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Proof.
intros t T1 T2 HT HVal.
inversion HVal; intros; subst; try inversion HT; subst; auto.
exists x. exists t0. auto.
Qed.
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof.
intros t.
t_cases (induction t) Case; intros T Ht; auto.
Case "tvar".
inversion Ht; subst.
inversion H1.
Case "tapp".
inversion Ht; subst.
right.
assert (\empty |- t1 \in TArrow T11 T) by apply H2.
apply IHt1 in H2.
apply IHt2 in H4.
destruct H2.
destruct H4.
assert (exists x u, t1 = tabs x T11 u).
eapply canonical_forms_fun.
apply H.
apply H0.
inversion H2; subst; clear H2.
inversion H3; subst; clear H3.
eauto.
inversion H1; subst; clear H1.
eauto.
inversion H0; subst; clear H0.
eauto.
Case "tsucc".
inversion Ht; subst.
right.
assert (\empty |- t \in TNat) by apply H1.
apply IHt in H1.
destruct H1.
assert (exists n, t = tnat n).
apply canonical_forms_nat.
apply H.
apply H0.
inversion H1; subst; clear H1.
eauto.
inversion H0; subst; clear H0.
eauto.
Case "tpred".
inversion Ht; subst.
right.
assert (\empty |- t \in TNat) by apply H1.
apply IHt in H1.
destruct H1.
assert (exists n, t = tnat n).
apply canonical_forms_nat.
apply H.
apply H0.
inversion H1; subst; clear H1.
eauto.
inversion H0; subst; clear H0.
eauto.
Case "tmult".
inversion Ht; subst.
right.
assert (\empty |- t1 \in TNat) by apply H2.
apply IHt1 in H2.
destruct H2.
assert (\empty |- t2 \in TNat) by apply H4.
apply IHt2 in H4.
destruct H4.
assert (exists n, t1 = tnat n).
apply canonical_forms_nat.
apply H.
apply H0.
assert (exists n, t2 = tnat n).
apply canonical_forms_nat.
apply H1.
apply H2.
inversion H3; subst; clear H3.
inversion H4; subst; clear H4.
eauto.
inversion H2; subst; clear H2.
eauto.
inversion H0; subst; clear H0.
eauto.
Case "tif0".
inversion Ht; subst.
right.
assert (\empty |- t1 \in TNat) by apply H3.
apply IHt1 in H3.
destruct H3.
assert (exists n, t1 = tnat n).
apply canonical_forms_nat.
apply H.
apply H0.
inversion H1; subst; clear H1.
destruct x; eauto.
inversion H0; subst; clear H0.
eauto.
Qed.
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if01 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if02 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if03 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_succ : forall x t,
appears_free_in x t ->
appears_free_in x (tsucc t)
| afi_pred : forall x t,
appears_free_in x t ->
appears_free_in x (tpred t)
| afi_mult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tmult t1 t2)
| afi_mult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tmult t1 t2).
Tactic Notation "afi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "afi_var" | Case_aux c "afi_app1"
| Case_aux c "afi_app2" | Case_aux c "afi_abs"
| Case_aux c "afi_if01" | Case_aux c "afi_if02"
| Case_aux c "afi_if03" | Case_aux c "afi_succ"
| Case_aux c "afi_pred" | Case_aux c "afi_mult1"
| Case_aux c "afi_mult2" ].
Hint Constructors appears_free_in.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof.
intros x t T Gamma H H0.
generalize dependent Gamma.
generalize dependent T.
afi_cases (induction H) Case;
intros; try solve [inversion H0; eauto].
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite extend_neq in H7; assumption.
Qed.
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
Proof with eauto.
intros.
generalize dependent Gamma'.
has_type_cases (induction H) Case; intros; auto.
Case "T_Var".
apply T_Var.
rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type.
intros x1 Hafi.
unfold extend.
destruct (eq_id_dec x x1)...
Case "T_App".
apply T_App with T11...
Qed.
Lemma substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma.
generalize dependent T.
t_cases (induction t) Case; intros T Gamma H;
inversion H; subst; simpl...
Case "tvar".
rename i into y.
destruct (eq_id_dec x y).
SCase "x=y".
subst.
rewrite extend_eq in H2.
inversion H2; subst.
clear H2.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
apply T_Var.
rewrite extend_neq in H2...
Case "tabs".
rename i into y.
apply T_Abs.
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi.
unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt.
eapply context_invariance...
intros z Hafi.
unfold extend.
destruct (eq_id_dec y z)...
subst.
rewrite neq_id...
Qed.
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
Proof with eauto.
remember empty as Gamma.
intros t t' T HT.
generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HE; subst Gamma; subst;
try solve [inversion HE; subst; auto].
Case "T_App".
inversion HE; subst...
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
Qed.
Definition stuck (t:tm) : Prop :=
(normal_form step) t /\ ~ value t.
Corollary soundness : forall t t' T,
empty |- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T Hhas_type Hmulti.
unfold stuck.
intros [Hnf Hnot_val].
unfold normal_form in Hnf.
induction Hmulti.
apply progress in Hhas_type.
destruct Hhas_type; eauto.
apply IHHmulti; eauto.
eapply preservation; eauto.
Qed.
(** [] *)
End STLCArith.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
/****************************************************************************
* Copyright (c) 2009 by Focus Robotics. All rights reserved.
*
* This program is an unpublished work fully protected by the United States
* copyright laws and is considered a trade secret belonging to the copyright
* holder. No part of this design may be reproduced stored in a retrieval
* system, or transmitted, in any form or by any means, electronic,
* mechanical, photocopying, recording, or otherwise, without prior written
* permission of Focus Robotics, Inc.
*
* Proprietary and Confidential
*
* Created By : Andrew Worcester
* Creation_Date: Tue Mar 10 2009
*
* Brief Description: Full client for the Focus Robotics Control Interconnect
* that supports reads and writes made to us from another block as well as reads
* and writes originating from this block made to another block.
*
* Functionality:
*
* Issues:
* - The interface currently seems a little clumsy. I am hoping to clean it up
* to be a little more compact and general as I work with it.
*
* Limitations:
*
* Testing:
*
* Synthesis:
*
******************************************************************************/
module fric_client
(
clk,
rst,
fric_in,
fric_out,
slave_addr, // addr out for read or write requests sent to this block
slave_wdat,
slave_wstb,
slave_rdat, // replay data in to reply to a read request made to us
master_type,
master_port,
master_addr, // type, port, and addr in for reads or writes from this block
master_wdat, // write data sent from this block
master_tstb, // transaction strobe -- initiate based on above
master_trdy, // flow control, tstb may only be asserted when this is already high
master_rstb, // reply strobe out to alert block that reply has arrived
master_rdat // reply data out
);
// Input/Output Declarations
input clk;
input rst;
input [7:0] fric_in;
output [7:0] fric_out;
output [7:0] slave_addr;
output [15:0] slave_wdat;
output slave_wstb;
input [15:0] slave_rdat;
input [3:0] master_type;
input [3:0] master_port;
input [7:0] master_addr;
input [15:0] master_wdat;
input master_tstb;
output master_trdy;
output master_rstb;
output [15:0] master_rday;
// Parameter Declarations
// Wire and Reg Declarations
// RTL
/****************************************************************************
* Fric In Sequencer (fis)
*
* The FSM in this subblock must accept any type of incoming packet, both new
* requests from other blocks and acks for requests we have previously made.
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
/****************************************************************************
* Fric Out Sequencer (fos)
*
* The Fric output sequencer must be able to send both new requests and acks
* for requests previously made to us.
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
/****************************************************************************
* Fric Reply Generator (frg)
*
* This subblock monitors requests made of us and forms the appropriate reply
* packets. This subblock controls the slave interface.
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
/****************************************************************************
* Fric Request Muxer (frm)
*
* This subblock controls the master interface and allows both the master
* interface and the FRG to send outgoing data to the fos.
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
/****************************************************************************
* Subblock
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
endmodule // fric_client
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: tx_link
*
*/
`default_nettype none
module tx_link #(
parameter LOG_FPW = 2,
parameter FPW = 4,
parameter DWIDTH = FPW*128,
parameter NUM_LANES = 8,
parameter RF_COUNTER_SIZE = 64,
parameter HMC_RX_AC_COUPLED = 1,
parameter MAX_RTC_RET_LOG = 8,
parameter LOG_MAX_RX_TOKENS = 8,
parameter LOG_MAX_HMC_TOKENS= 10,
parameter LOG_IRTRY_TIMOUT = 8,
parameter XIL_CNT_PIPELINED = 0,
//Debug
parameter DBG_RX_TOKEN_MON = 1,
parameter OPEN_RSP_MODE = 0
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
input wire res_n,
//----------------------------------
//----TO HMC PHY
//----------------------------------
output wire [DWIDTH-1:0] phy_scrambled_data_out,
//----------------------------------
//----HMC IF
//----------------------------------
output reg LXRXPS,
input wire LXTXPS,
//----------------------------------
//----Input data
//----------------------------------
input wire [DWIDTH-1:0] d_in_data,
input wire [FPW-1:0] d_in_flit_is_hdr,
input wire [FPW-1:0] d_in_flit_is_tail,
input wire [FPW-1:0] d_in_flit_is_valid,
input wire d_in_empty,
input wire d_in_a_empty,
output reg d_in_shift_out,
//----------------------------------
//----RX Block
//----------------------------------
input wire rx_force_tx_retry,
input wire rx_error_abort_mode,
input wire rx_error_abort_mode_cleared,
input wire [7:0] rx_hmc_frp,
input wire [7:0] rx_rrp,
input wire [MAX_RTC_RET_LOG-1:0] rx_returned_tokens,
input wire [LOG_FPW:0] rx_hmc_tokens_to_return,
input wire [LOG_FPW:0] rx_hmc_poisoned_tokens_to_return,
//----------------------------------
//----RF
//----------------------------------
//Monitoring 1-cycle set to increment
output reg rf_cnt_retry,
output wire [RF_COUNTER_SIZE-1:0] rf_sent_p,
output wire [RF_COUNTER_SIZE-1:0] rf_sent_np,
output wire [RF_COUNTER_SIZE-1:0] rf_sent_r,
output reg rf_run_length_bit_flip,
output reg rf_error_abort_not_cleared,
//Status
input wire rf_link_is_up,
input wire rf_hmc_received_init_null,
input wire rf_descramblers_aligned,
output wire [1:0] rf_tx_init_status,
output reg [LOG_MAX_HMC_TOKENS-1:0]rf_hmc_tokens_av,
output wire [LOG_MAX_RX_TOKENS-1:0]rf_rx_tokens_av,
//Control
input wire rf_hmc_sleep_requested,
input wire rf_warm_reset,
input wire rf_scrambler_disable,
input wire [LOG_MAX_RX_TOKENS-1:0]rf_rx_buffer_rtc,
input wire [4:0] rf_irtry_to_send,
input wire rf_run_length_enable
);
`include "hmc_field_functions.h"
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//------------------------------------------------------------------------------------General Assignments
localparam LANE_WIDTH = (DWIDTH/NUM_LANES);
integer i_f; //counts to FPW
integer i_t; //counts to number of TS1 packets in a word
//Packet command 3-MSB definition
localparam PKT_WRITE = 3'b001;
localparam PKT_MISC_WRITE = 3'b010;
localparam PKT_READ = 3'b110;
localparam PKT_MODE_READ = 3'b101;
localparam PKT_P_WRITE = 3'b011;
localparam PKT_MISC_P_WRITE = 3'b100;
localparam CMD_IRTRY = 6'b000011;
//------------------------------------------------------------------------------------Scrambler
wire [14:0] seed_lane [NUM_LANES-1:0];
assign seed_lane[0] = 15'h4D56;
assign seed_lane[1] = 15'h47FF;
assign seed_lane[2] = 15'h75B8;
assign seed_lane[3] = 15'h1E18;
assign seed_lane[4] = 15'h2E10;
assign seed_lane[5] = 15'h3EB2;
assign seed_lane[6] = 15'h4302;
assign seed_lane[7] = 15'h1380;
generate
if(NUM_LANES==16) begin : seed_gen_16x
assign seed_lane[8] = 15'h3EB3;
assign seed_lane[9] = 15'h2769;
assign seed_lane[10] = 15'h4580;
assign seed_lane[11] = 15'h5665;
assign seed_lane[12] = 15'h6318;
assign seed_lane[13] = 15'h6014;
assign seed_lane[14] = 15'h077B;
assign seed_lane[15] = 15'h261F;
end
endgenerate
wire [NUM_LANES-1:0] bit_was_flipped;
//------------------------------------------------------------------------------------FSM and States
reg [2:0] state;
reg [1:0] init_state;
localparam INIT_TX_NULL_1 = 2'b00;
localparam INIT_TX_TS1 = 2'b01;
localparam INIT_TX_NULL_2 = 2'b11;
localparam INIT_DONE = 2'b10;
localparam INIT = 3'b000;
localparam IDLE = 3'b001;
localparam TX = 3'b010;
localparam HMC_RTRY = 3'b011;
localparam SLEEP = 3'b100;
localparam WAIT_FOR_HMC = 3'b101;
localparam LNK_RTRY = 3'b110;
localparam DEBUG = 3'b111;
assign rf_tx_init_status = init_state;
reg rtc_rx_initialize;
//------------------------------------------------------------------------------------DATA and ORDERING
//reorder incoming data to FLITs
wire [127:0] d_in_flit [FPW-1:0];
genvar f;
generate
for(f = 0; f < (FPW); f = f + 1) begin : reorder_input_data_to_flits
assign d_in_flit[f] = d_in_data[127+(f*128):f*128];
end
endgenerate
//Create a mask and an input buffer that is necessary if packet transmission is interrupted and packets remain untransmitted
reg d_in_use_buf;
reg [127:0] d_in_buf_flit [FPW-2:0];
reg [FPW-2:0] d_in_buf_flit_is_hdr;
reg [FPW-2:0] d_in_buf_flit_is_valid;
//Reorder the data per lane
wire [DWIDTH-1:0] data_rdy;
wire [DWIDTH-1:0] data_to_scrambler;
genvar l,n;
generate
for(n = 0; n < NUM_LANES; n = n + 1) begin : reorder_data_to_lanes
for(l = 0; l < LANE_WIDTH; l = l + 1) begin
assign data_to_scrambler[l+n*LANE_WIDTH] = data_rdy[l*NUM_LANES+n];
end
end
endgenerate
//------------------------------------------------------------------------------------Init Regs
localparam TS1_SEQ_INC_VAL_PER_CYCLE = (NUM_LANES==8) ? FPW : (FPW/2);
localparam LOG_CYCLES_NULL_TO_SEND = (FPW == 2) ? 4 :
(FPW == 4) ? 3 :
(FPW == 6) ? 3 :
2;
wire [(NUM_LANES*4)-1:0] ts1_seq_part_reordered [TS1_SEQ_INC_VAL_PER_CYCLE-1:0]; //ts1 seq is 4 bits
reg [3:0] ts1_seq_nr_per_flit [TS1_SEQ_INC_VAL_PER_CYCLE-1:0];
wire [127:0] ts1_flit [FPW-1:0];
reg [LOG_CYCLES_NULL_TO_SEND-1:0] num_null_cycles_sent;
generate
for(f = 0; f < TS1_SEQ_INC_VAL_PER_CYCLE; f = f + 1) begin : generate_lane_dependent_ts1_sequence
for(n=0; n<4; n=n+1) begin
assign ts1_seq_part_reordered[f][(n*NUM_LANES)+NUM_LANES-1:(n*NUM_LANES)] = {NUM_LANES{ts1_seq_nr_per_flit[f][n]}};
end
if(NUM_LANES==8) begin
assign ts1_flit[f] = {
32'hffffffff,32'h0,1'h1,7'h0,7'b1111111,1'h0,7'h0,1'h1,1'h0,7'b1111111,ts1_seq_part_reordered[f]
};
end else begin
assign ts1_flit[f*2+1] = {
64'hffffffffffffffff,64'h0
};
assign ts1_flit[f*2] = {
16'h8000,16'hfffe,16'h0001,16'h7fff,ts1_seq_part_reordered[f]
};
end
end
endgenerate
//------------------------------------------------------------------------------------Counter variables
reg [LOG_FPW:0] rf_sent_p_comb;
reg [LOG_FPW:0] rf_sent_np_comb;
reg [LOG_FPW:0] rf_sent_r_comb;
//------------------------------------------------------------------------------------SEQ FRP RTC Stage
reg [127:0] data2rtc_stage_flit [FPW-1:0];
reg [FPW-1:0] data2rtc_stage_flit_is_hdr;
reg [FPW-1:0] data2rtc_stage_flit_is_tail;
reg [FPW-1:0] data2rtc_stage_flit_is_valid;
reg data2rtc_stage_is_flow;
reg data2rtc_stage_force_tx_retry;
reg [127:0] data2seq_frp_stage_flit [FPW-1:0];
reg [FPW-1:0] data2seq_frp_stage_flit_is_hdr;
reg [FPW-1:0] data2seq_frp_stage_flit_is_tail;
reg [FPW-1:0] data2seq_frp_stage_flit_is_valid;
reg data2seq_frp_stage_is_flow;
reg data2seq_frp_stage_force_tx_retry;
//Information used to fill the retry buffer
reg [LOG_FPW-1:0] target_temp [FPW:0];
reg [LOG_FPW-1:0] next_target;
reg [LOG_FPW-1:0] target [FPW-1:0];
reg [LOG_FPW:0] tx_seqnum_inc;
reg [2:0] tx_seqnum_temp [FPW-1:0];
//------------------------------------------------------------------------------------RETRY
//HMC
//Number of cycles to wait until start HMC retry is issued again (when RX error abort is not cleared)
reg [LOG_IRTRY_TIMOUT-1:0] error_abort_mode_clr_cnt;
reg force_hmc_retry;
reg [4:0] irtry_start_retry_cnt;
reg [4:0] irtry_clear_error_cnt;
wire [63:0] irtry_hdr;
assign irtry_hdr = {6'h0,34'h0,9'h0,4'h1,4'h1,1'h0,6'b000011};
//------------------------------------------------------------------------------------Retry Buffer
localparam RAM_ADDR_SIZE = (FPW == 2) ? 7 :
(FPW == 4) ? 6 :
(FPW == 6) ? 5 :
(FPW == 8) ? 5 :
1;
reg [127:0] data2ram_flit [FPW-1:0];
reg [127:0] data2ram_flit_temp [FPW-1:0];
reg [FPW-1:0] data2ram_flit_is_hdr;
reg [FPW-1:0] data2ram_flit_is_tail;
reg [FPW-1:0] data2ram_flit_is_valid;
reg data2ram_force_tx_retry;
//Header/Tail fields, and at the same time form the RAM read pointer
reg [RAM_ADDR_SIZE-1:0] tx_frp_adr [FPW-1:0];
reg [2:0] tx_seqnum;
reg [FPW-1:0] ram_w_en ;
reg ram_r_en;
wire [RAM_ADDR_SIZE-1:0] ram_w_addr_next;
assign ram_w_addr_next = tx_frp_adr[0] + 1;
reg [RAM_ADDR_SIZE-1:0] ram_r_addr_temp;
reg [FPW-1:0] ram_r_mask;
wire [128+3-1:0] ram_r_data [FPW-1:0];
reg [128+3-1:0] ram_w_data [FPW-1:0];
wire [RAM_ADDR_SIZE-1:0] ram_r_addr;
assign ram_r_addr = rx_rrp[7:8-RAM_ADDR_SIZE];
//Avoid overwriting not acknowleged FLITs in the retry buffer
wire [RAM_ADDR_SIZE-1:0] ram_result;
assign ram_result = ram_r_addr - ram_w_addr_next;
//A safe value since ram_w_addr_next is calculated some cycles after packets were accepted
wire ram_full;
assign ram_full = (ram_result<9 && ram_result>0) ? 1'b1 : 1'b0 ;
//Regs for TX Link retry handling
reg tx_retry_finished;
reg tx_retry_ongoing;
reg tx_link_retry_request; //Sample the retry request
//------------------------------------------------------------------------------------RRP Stage
reg [127:0] data2rrp_stage_flit [FPW-1:0];
reg [FPW-1:0] data2rrp_stage_flit_is_hdr;
reg [FPW-1:0] data2rrp_stage_flit_is_tail;
reg [FPW-1:0] data2rrp_stage_flit_is_valid;
`ifdef SIMULATION
//We dont want to crash a simulation run because PRETs are still travelling upon test completion, so we include a trigger to only send PRETs when necessary in simulation
//In hardware, PRETs will be sent whenever there is no valid FLIT on position 0 -> reduces the overall pointer return delay
reg [7:0] last_transmitted_rx_hmc_frp;
`else
reg send_prets;
`endif
//------------------------------------------------------------------------------------CRC
reg [127:0] data2crc_flit [FPW-1:0];
wire [DWIDTH-1:0] data2crc;
reg [FPW-1:0] data2crc_flit_is_hdr;
reg [FPW-1:0] data2crc_flit_is_tail;
generate
for(f = 0; f < (FPW); f = f + 1) begin : concatenate_flits_to_single_reg
assign data2crc[(f*128)+127:(f*128)] = data2crc_flit[f];
end
endgenerate
//------------------------------------------------------------------------------------FLOW PACKETS
//TRET
wire [63:0] tret_hdr;
assign tret_hdr = {6'h0,34'h0,9'h0,4'h1,4'h1,1'h0,6'b000010};
//PRET
wire [63:0] pret_hdr;
assign pret_hdr = {6'h0,34'h0,9'h0,4'h1,4'h1,1'h0,6'b000001};
//------------------------------------------------------------------------------------RTC HANDLING
//Registers for the RTC field in request packets
reg rtc_return;
reg [4:0] rtc_return_val;
//A safe value to not send more FLITs than the HMC can buffer
reg [LOG_FPW-1:0] num_flits_in_buf;
reg [LOG_FPW:0] num_flits_transmitted;
reg [LOG_MAX_RX_TOKENS-1:0]remaining_tokens;
localparam TOKENS_THRESHOLD= (FPW == 2) ? 11 :
(FPW == 4) ? 15 :
(FPW == 6) ? 23 :
(FPW == 8) ? 23 :
1;
wire hmc_tokens_av;
assign hmc_tokens_av = ((rf_hmc_tokens_av+num_flits_in_buf+rx_returned_tokens) > TOKENS_THRESHOLD) ? 1'b1 : 1'b0;
//Return a maximum of 31 tokens
wire [4:0] outstanding_tokens_to_return;
assign outstanding_tokens_to_return = (OPEN_RSP_MODE==0) ? (remaining_tokens > 31 ? 31 : remaining_tokens[4:0]) : 5'h0;
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------LOGIC STARTS HERE---------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//====================================================================
//---------------------------------MISC
//====================================================================
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
rf_run_length_bit_flip <= 1'b0;
end else begin
rf_run_length_bit_flip <= |bit_was_flipped;
end
end
//====================================================================
//---------------------------------Monitor Remaining Tokens in the RX input buffer, just a debug help
//====================================================================
//Track the remaining tokens in the rx input buffer. This is optional since the HMC must make sure not to send more tokens than RX can buffer, useful for debugging
generate
if(DBG_RX_TOKEN_MON==1 && OPEN_RSP_MODE==0) begin : Tokens_in_RX_buf
reg [6:0] sum_requested_tokens; //Count the amount of tokens requested from the HMC
reg [6:0] sum_requested_tokens_temp; //Use this register for combinational logic
always @(*) begin
sum_requested_tokens_temp = {7{1'b0}};
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
if(data2rtc_stage_flit_is_hdr[i_f] && data2rtc_stage_flit_is_valid[i_f]) begin
if(cmd_type(data2rtc_stage_flit[i_f]) == PKT_READ ||
cmd_type(data2rtc_stage_flit[i_f]) == PKT_MODE_READ ) begin
//it is either a data read or mode read
sum_requested_tokens_temp = sum_requested_tokens_temp + num_requested_flits(data2rtc_stage_flit[i_f]);
end else if( (cmd_type(data2rtc_stage_flit[i_f]) == PKT_WRITE) ||
(cmd_type(data2rtc_stage_flit[i_f]) == PKT_MISC_WRITE) ) begin
//it is not a posted transaction, so 1 token will be returned as response
sum_requested_tokens_temp = sum_requested_tokens_temp + 1;
end
end
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
sum_requested_tokens <= {7{1'b0}};
end else begin
sum_requested_tokens <= sum_requested_tokens_temp;
end
end
//Monitor remaining tokens in the openHMC RX input buffer
reg [LOG_MAX_RX_TOKENS-1:0] rx_tokens_av;
assign rf_rx_tokens_av = rx_tokens_av;
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
rx_tokens_av <= {LOG_MAX_RX_TOKENS{1'b0}};
end else begin
if(state==INIT_TX_NULL_1)begin
//initialize token counts when HMC init is not done
rx_tokens_av <= rf_rx_buffer_rtc;
end else begin
//calculate remaining tokens in RX buffers
rx_tokens_av <= rx_tokens_av + rx_hmc_tokens_to_return - sum_requested_tokens;
end
end
end
end else begin
assign rf_rx_tokens_av = {LOG_MAX_RX_TOKENS{1'b0}};
end
endgenerate
//=======================================================================================================================
//---------------------------------ALL OTHER LOGIC HERE
//=======================================================================================================================
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
//----Init Regs
for(i_t=0;i_t<TS1_SEQ_INC_VAL_PER_CYCLE;i_t=i_t+1) begin //set
ts1_seq_nr_per_flit[i_t]<= i_t;
end
num_null_cycles_sent <= {LOG_CYCLES_NULL_TO_SEND{1'b0}};
//General
init_state <= INIT_TX_NULL_1;
rtc_rx_initialize <= 1'b1;
end
else begin
case(init_state)
//---------------------------------INIT. Refer to Initialization section in the specification
INIT_TX_NULL_1: begin
//---init_state---
if(rf_hmc_received_init_null)begin
init_state <= INIT_TX_TS1;
end
end
INIT_TX_TS1: begin
rtc_rx_initialize <= 1'b0;
for(i_t=0;i_t<TS1_SEQ_INC_VAL_PER_CYCLE;i_t=i_t+1) begin
ts1_seq_nr_per_flit[i_t] <= ts1_seq_nr_per_flit[i_t] + TS1_SEQ_INC_VAL_PER_CYCLE;
end
//---init_state---
if(rf_descramblers_aligned)begin
init_state <= INIT_TX_NULL_2;
end
end
INIT_TX_NULL_2: begin
//Issue at least 32 NULL FLITs before going active
if(&num_null_cycles_sent && rf_link_is_up) begin
init_state <= INIT_DONE;
end
num_null_cycles_sent <= num_null_cycles_sent + 1;
end
default: begin
end
endcase
if(!LXTXPS || rf_warm_reset) begin
init_state <= INIT_TX_NULL_1;
if(rf_warm_reset)
rtc_rx_initialize <= 1'b1;
end
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
`ifdef RESET_ALL
if(!res_n) begin
for(i_f=0;i_f<FPW;i_f=i_f+1) data2rtc_stage_flit[i_f] <= {128{1'b0}};
for(i_f=0;i_f<FPW-1;i_f=i_f+1) d_in_buf_flit[i_f] <= {128{1'b0}};
end else
`endif
begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
data2rtc_stage_flit[i_f] <= {128{1'b0}};
end
case(state)
INIT: begin
if(init_state == INIT_TX_TS1) begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
data2rtc_stage_flit[i_f] <= ts1_flit[i_f];
end
end
end
IDLE: begin
if(|remaining_tokens && !ram_full)begin
data2rtc_stage_flit[0] <= {{64{1'b0}},tret_hdr};
end
end
TX: begin
//Choose the data source
if(d_in_use_buf) begin
for(i_f=0;i_f<FPW-1;i_f=i_f+1) begin
data2rtc_stage_flit[i_f+1] <= d_in_buf_flit[i_f];
end
end else begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
data2rtc_stage_flit[i_f] <= d_in_flit[i_f];
end
end
for(i_f=0;i_f<FPW-1;i_f=i_f+1)begin
//No matter what, fill the buffer
d_in_buf_flit[i_f] <= d_in_flit[i_f+1];
end
end
HMC_RTRY: begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin //Send IRTRY start retry
data2rtc_stage_flit[i_f] <= {48'h0,8'b00000001,8'h00,irtry_hdr};
end
end
LNK_RTRY: begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin //Send IRTRY clear error abort
data2rtc_stage_flit[i_f] <= {48'h0,8'b00000010,8'h00,irtry_hdr};
end
end
endcase
end
if(!res_n) begin
data2rtc_stage_flit_is_hdr <= {FPW{1'b0}};
data2rtc_stage_flit_is_tail <= {FPW{1'b0}};
data2rtc_stage_flit_is_valid <= {FPW{1'b0}};
data2rtc_stage_is_flow <= 1'b0;
data2rtc_stage_force_tx_retry <= 1'b0;
d_in_shift_out <= 1'b0;
//----Reset the input buffer reg
d_in_buf_flit_is_hdr <= {FPW-1{1'b0}};
d_in_buf_flit_is_valid <= {FPW-1{1'b0}};
d_in_use_buf <= 1'b0;
//General
state <= INIT;
//Token Flow Control
remaining_tokens <= {LOG_MAX_RX_TOKENS{1'b0}};
rtc_return_val <= {5{1'b0}};
rtc_return <= 1'b0;
//Retry
irtry_start_retry_cnt <= {5{1'b0}};
irtry_clear_error_cnt <= {5{1'b0}};
//HMC Control
LXRXPS <= 1'b1;
//Flow Control
tx_link_retry_request <= 1'b0;
end
else begin
//====================================================================
//---------------------------------INIT
//====================================================================
//Reset control signals
d_in_shift_out <= 1'b0;
irtry_start_retry_cnt <= {5{1'b0}};
irtry_clear_error_cnt <= {5{1'b0}};
//HMC Control
LXRXPS <= 1'b1;
if(rx_force_tx_retry)begin
tx_link_retry_request <= 1'b1;
end
//RTC
rtc_return <= 1'b0;
//Initialize rtc to be transmitted after reset and warm reset
if(rtc_rx_initialize) begin
remaining_tokens <= rf_rx_buffer_rtc;
end else begin
remaining_tokens <= remaining_tokens + rx_hmc_tokens_to_return + rx_hmc_poisoned_tokens_to_return;
end
//Reset information bits
data2rtc_stage_flit_is_hdr <= {FPW{1'b0}};
data2rtc_stage_flit_is_tail <= {FPW{1'b0}};
data2rtc_stage_flit_is_valid <= {FPW{1'b0}};
data2rtc_stage_is_flow <= 1'b0;
data2rtc_stage_force_tx_retry <= 1'b0;
rtc_return_val <= outstanding_tokens_to_return;
case(state)
//====================================================================
//---------------------------------Normal operation (including init TRETs)
//====================================================================
// Some branches to other states may be removed in HMC_RTRY for instance.
// Saves logic if an additional cycle in IDLE is acceptable
INIT: begin
if(init_state==INIT_DONE) state <= IDLE;
end
IDLE: begin
//Issue NULL Flits if there's nothing else to do
//SEND TRET PACKET even if there are no tokens available
if(|remaining_tokens && !ram_full)begin
data2rtc_stage_flit_is_hdr[0] <= 1'b1;
data2rtc_stage_flit_is_tail[0] <= 1'b1;
data2rtc_stage_flit_is_valid[0] <= 1'b1;
remaining_tokens <= remaining_tokens + rx_hmc_tokens_to_return + rx_hmc_poisoned_tokens_to_return - outstanding_tokens_to_return;
rtc_return <= 1'b1;
end
// //---State---
if(force_hmc_retry) begin
state <= HMC_RTRY;
end else if(tx_link_retry_request) begin
state <= LNK_RTRY;
end else if(rf_hmc_sleep_requested) begin
state <= SLEEP;
end else if(!d_in_empty && !ram_full && hmc_tokens_av) begin
state <= TX;
d_in_shift_out <= ~d_in_use_buf;
end
end
TX: begin
//Get and transmit data
//First set control signals
d_in_use_buf <= 1'b0;
d_in_shift_out <= 1'b1;
//Fill the buffer
d_in_buf_flit_is_hdr <= d_in_flit_is_hdr[FPW-1:1];
d_in_buf_flit_is_valid <= d_in_flit_is_valid[FPW-1:1];
//If there is data buffered - use it
data2rtc_stage_flit_is_hdr <= d_in_use_buf ? {d_in_buf_flit_is_hdr,1'b0} : d_in_flit_is_hdr;
data2rtc_stage_flit_is_tail <= d_in_use_buf ? {FPW{1'b0}} : d_in_flit_is_tail;
data2rtc_stage_flit_is_valid <= d_in_use_buf ? {d_in_buf_flit_is_valid,1'b0} : d_in_flit_is_valid;
//Set RTC to be added in the next step
if( |remaining_tokens &&
(!d_in_use_buf && |d_in_flit_is_tail)
) begin
remaining_tokens <= remaining_tokens + rx_hmc_tokens_to_return + rx_hmc_poisoned_tokens_to_return - outstanding_tokens_to_return;
rtc_return <= 1'b1;
end
//Exit state if seen a tail and exit condition occured
if( ((!d_in_use_buf && |d_in_flit_is_tail)) &&
(force_hmc_retry || ram_full || tx_link_retry_request || !hmc_tokens_av || d_in_a_empty)) begin
d_in_shift_out <= 1'b0;
case ({force_hmc_retry,tx_link_retry_request})
2'b00: state <= IDLE;
2'b01: state <= LNK_RTRY;
default: state <= HMC_RTRY;
endcase
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
if(!d_in_use_buf && d_in_flit_is_tail[i_f])begin
data2rtc_stage_flit_is_valid <= {FPW{1'b1}} >> {FPW-1-i_f};
end
end
for(i_f=1;i_f<FPW;i_f=i_f+1)begin
if(d_in_flit_is_tail[i_f])begin
d_in_buf_flit_is_hdr <= d_in_flit_is_hdr[FPW-1:1] & ({FPW-1{1'b1}} << i_f);
d_in_buf_flit_is_valid <= d_in_flit_is_valid[FPW-1:1] & ({FPW-1{1'b1}} << i_f);
end
end
//Use buf next time TX state is entered if there is a packet pending
if(!d_in_use_buf && (d_in_flit_is_hdr[FPW-1:1] > d_in_flit_is_tail[FPW-1:1]))begin
d_in_use_buf <= 1'b1;
end
end
end
//---------------------------------An error in RX path occured - send irtry start packets
HMC_RTRY: begin
data2rtc_stage_is_flow <= 1'b1;
irtry_start_retry_cnt <= irtry_start_retry_cnt + FPW;
if(irtry_start_retry_cnt+FPW >= rf_irtry_to_send)begin
irtry_start_retry_cnt <= {5{1'b0}};
state <= IDLE;
end
end
//---------------------------------HMC sent start retry packets -
// re-send all valid packets in RAM after sending clear error packets
LNK_RTRY: begin
if(!tx_retry_ongoing && (tx_link_retry_request || |irtry_clear_error_cnt)) begin
data2rtc_stage_is_flow <= 1'b1;
if(irtry_clear_error_cnt+FPW >= rf_irtry_to_send)begin
irtry_clear_error_cnt <= {5{1'b0}};
data2rtc_stage_force_tx_retry <= 1'b1;
end else begin
irtry_clear_error_cnt <= irtry_clear_error_cnt + FPW;
end
end
if(tx_retry_finished && !tx_link_retry_request) begin
state <= IDLE;
end
if(!tx_retry_ongoing && !rx_force_tx_retry) begin
tx_link_retry_request <= 1'b0;
end
end
//---------------------------------Power State Management
SLEEP: begin
if(rf_hmc_sleep_requested) begin
LXRXPS <= 1'b0;
end else begin
state <= WAIT_FOR_HMC;
end
end
WAIT_FOR_HMC: begin
if(LXTXPS) begin
state <= INIT;
end
end
endcase
//Warm Reset
if(rf_warm_reset) begin
//in case of a warm reset request, continue at INIT_TX_NULL_2 sequence and intialize tokens to be returned
state <= INIT;
end
end
end
//====================================================================
//---------------------------------HMC input buffer Token Handling
//====================================================================
//Count the tokens that were used and make sure the HMC has enough tokens in its input buffer left
//This always block remains combinational to save one cycle
always @(*) begin
num_flits_transmitted = {LOG_FPW+1{1'b0}};
num_flits_in_buf = {LOG_FPW{1'b0}};
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
if(d_in_flit_is_valid[i_f] && d_in_shift_out) begin
num_flits_transmitted = num_flits_transmitted + 1;
end
end
for(i_f=0;i_f<FPW-1;i_f=i_f+1)begin
if(d_in_buf_flit_is_valid[i_f] && d_in_use_buf) begin
num_flits_in_buf = num_flits_in_buf + 1;
end
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
rf_hmc_tokens_av <= {LOG_MAX_HMC_TOKENS{1'b0}};
end else begin
rf_hmc_tokens_av <= rf_hmc_tokens_av + rx_returned_tokens - num_flits_transmitted;
end
end
//====================================================================
//---------------------------------Counter in the RF, currently only data transactions are counted
//====================================================================
always @(*) begin
rf_sent_p_comb = {LOG_FPW+1{1'b0}};
rf_sent_np_comb = {LOG_FPW+1{1'b0}};
rf_sent_r_comb = {LOG_FPW+1{1'b0}};
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
if(data2seq_frp_stage_flit_is_hdr[i_f])begin
//split into independent cases to avoid dependencies
//Instead of comparing the entire cmd field, try to reduce logic effort
//All non-posted types have either bit 3 or 4 in the cmd set:
if( data2seq_frp_stage_flit[i_f][3] ^ data2seq_frp_stage_flit[i_f][4] ) begin
rf_sent_np_comb = rf_sent_np_comb + {{LOG_FPW{1'b0}},1'b1};
end
//Only reads have bit 4 and 5 set:
if(data2seq_frp_stage_flit[i_f][4] && data2seq_frp_stage_flit[i_f][5] ) begin
rf_sent_r_comb = rf_sent_r_comb + {{LOG_FPW{1'b0}},1'b1};
end
//Otherwise it's a posted write
if(cmd_type(data2seq_frp_stage_flit[i_f])==PKT_P_WRITE)begin
rf_sent_p_comb = rf_sent_p_comb + {{LOG_FPW{1'b0}},1'b1};
end
end
end
end
`ifdef XILINX
openhmc_counter48_wrapper_xilinx #(
.INC_SIZE(LOG_FPW+1),
.PIPELINED(XIL_CNT_PIPELINED)
) cnt_sent_p (
.clk(clk),
.res_n(res_n),
.inc_value(rf_sent_p_comb),
.value(rf_sent_p)
);
openhmc_counter48_wrapper_xilinx #(
.INC_SIZE(LOG_FPW+1),
.PIPELINED(XIL_CNT_PIPELINED)
) cnt_sent_np (
.clk(clk),
.res_n(res_n),
.inc_value(rf_sent_np_comb),
.value(rf_sent_np)
);
openhmc_counter48_wrapper_xilinx #(
.INC_SIZE(LOG_FPW+1),
.PIPELINED(XIL_CNT_PIPELINED)
) cnt_sent_r (
.clk(clk),
.res_n(res_n),
.inc_value(rf_sent_r_comb),
.value(rf_sent_r)
);
`else
reg [RF_COUNTER_SIZE-1:0] rf_sent_p_temp;
reg [RF_COUNTER_SIZE-1:0] rf_sent_np_temp;
reg [RF_COUNTER_SIZE-1:0] rf_sent_r_temp;
assign rf_sent_p = rf_sent_p_temp;
assign rf_sent_np = rf_sent_np_temp;
assign rf_sent_r = rf_sent_r_temp;
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
rf_sent_p_temp <= {RF_COUNTER_SIZE{1'b0}};
rf_sent_np_temp <= {RF_COUNTER_SIZE{1'b0}};
rf_sent_r_temp <= {RF_COUNTER_SIZE{1'b0}};
end else begin
rf_sent_p_temp <= rf_sent_p_temp + {{RF_COUNTER_SIZE-LOG_FPW-1{1'b0}},rf_sent_p_comb};
rf_sent_np_temp <= rf_sent_np_temp + {{RF_COUNTER_SIZE-LOG_FPW-1{1'b0}},rf_sent_np_comb};
rf_sent_r_temp <= rf_sent_r_temp + {{RF_COUNTER_SIZE-LOG_FPW-1{1'b0}},rf_sent_r_comb};
end
end
`endif
//====================================================================
//---------------------------------HMC Retry Logic
//====================================================================
//Monitor RX error abort mode - if the timer expires send another series of start retry packets
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
error_abort_mode_clr_cnt <= {8{1'b0}};
force_hmc_retry <= 1'b0;
rf_error_abort_not_cleared <= 1'b0;
end else begin
rf_error_abort_not_cleared <= 1'b0;
if(rx_error_abort_mode)begin
error_abort_mode_clr_cnt <= error_abort_mode_clr_cnt + 1; //decrement counter
end
if(rx_error_abort_mode_cleared) begin
error_abort_mode_clr_cnt <= {8{1'b0}};
end
if(&error_abort_mode_clr_cnt) begin
rf_error_abort_not_cleared <= 1'b1;
end
if((rx_error_abort_mode && state!=HMC_RTRY && |error_abort_mode_clr_cnt==1'b0) || (&error_abort_mode_clr_cnt))begin
force_hmc_retry <= 1'b1;
end else begin
if(state==HMC_RTRY)begin
force_hmc_retry <= 1'b0;
end
end
end
end
//====================================================================
//---------------------------------RTC Stage
//====================================================================
generate
if(OPEN_RSP_MODE==0) begin : RTC_stage
reg [4:0] data2seq_frp_stage_flit_rtc [FPW-1:0];
reg rtc_return_sent;
always @(*) begin
rtc_return_sent = 0;
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
if(data2rtc_stage_flit_is_tail[i_f] && !rtc_return_sent && rtc_return) begin
//Return outstanding tokens, but only once per cycle
data2seq_frp_stage_flit_rtc[i_f] = rtc_return_val;
rtc_return_sent = 1'b1;
end else begin
data2seq_frp_stage_flit_rtc[i_f] = 5'h00;
end
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
`ifdef ASYNC_RES
if(!res_n)
data2seq_frp_stage_flit[i_f] <= {128{1'b0}};
else
`endif
begin
data2seq_frp_stage_flit[i_f] <= data2rtc_stage_flit[i_f];
if(data2rtc_stage_flit_is_tail[i_f]) begin
data2seq_frp_stage_flit[i_f][64+31:64+27] <= data2seq_frp_stage_flit_rtc[i_f];
end
end
end
end
end else begin
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
`ifdef ASYNC_RES
if(!res_n)
data2seq_frp_stage_flit[i_f] <= {128{1'b0}};
else
`endif
begin
data2seq_frp_stage_flit[i_f] <= data2rtc_stage_flit[i_f];
end
end
end
end
endgenerate
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
`ifdef RESET_ALL
if(!res_n) begin
data2seq_frp_stage_flit_is_hdr <= {FPW{1'b0}};
data2seq_frp_stage_flit_is_tail <= {FPW{1'b0}};
data2seq_frp_stage_flit_is_valid <= {FPW{1'b0}};
data2seq_frp_stage_is_flow <= 1'b0;
data2seq_frp_stage_force_tx_retry <= 1'b0;
end else
`endif
begin
data2seq_frp_stage_flit_is_hdr <= data2rtc_stage_flit_is_hdr & data2rtc_stage_flit_is_valid;
data2seq_frp_stage_flit_is_tail <= data2rtc_stage_flit_is_tail & data2rtc_stage_flit_is_valid;
data2seq_frp_stage_flit_is_valid <= data2rtc_stage_flit_is_valid;
data2seq_frp_stage_is_flow <= data2rtc_stage_is_flow;
data2seq_frp_stage_force_tx_retry <= data2rtc_stage_force_tx_retry;
end
end
//====================================================================
//---------------------------------Seqnum and FRP Stage
//====================================================================
always @(*) begin
tx_seqnum_inc = {LOG_FPW{1'b0}};
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
tx_seqnum_temp[i_f] = 0;
if(data2seq_frp_stage_flit_is_tail[i_f])begin
tx_seqnum_inc = tx_seqnum_inc + 1;
tx_seqnum_temp[i_f] = tx_seqnum + tx_seqnum_inc;
end
end
target_temp[0] = next_target;
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
if(data2rtc_stage_flit_is_valid[i_f]) begin
target_temp[i_f+1] = target_temp[i_f] + 1;
if(target_temp[i_f+1]==FPW)
target_temp[i_f+1]=0;
end else begin
target_temp[i_f+1] = target_temp[i_f];
end
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
//Reset the target RAM location and seqnum
tx_seqnum <= {LOG_FPW{1'b0}};
next_target <= {LOG_FPW{1'b0}};
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
target[i_f] <= {FPW{1'b0}};
end
end else begin
tx_seqnum <= tx_seqnum + tx_seqnum_inc;
if(!data2rtc_stage_is_flow) begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
target[i_f] <= target_temp[i_f];
end
next_target <= target_temp[FPW];
end
end
end
//Constant propagation, no need for reset condition
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
`ifdef RESET_ALL
if(!res_n) data2ram_flit[i_f] <= {128{1'b0}};
else
`endif
begin
data2ram_flit[i_f] <= data2seq_frp_stage_flit[i_f];
if(data2seq_frp_stage_flit_is_tail[i_f]) begin
data2ram_flit[i_f][64+15+3:64+8] <= {tx_seqnum_temp[i_f],tx_frp_adr[target[i_f]],target[i_f]};
end
end
end
data2ram_flit_is_hdr <= data2seq_frp_stage_flit_is_hdr | {FPW{data2seq_frp_stage_is_flow}};
data2ram_flit_is_tail <= data2seq_frp_stage_flit_is_tail;
data2ram_flit_is_valid <= data2seq_frp_stage_flit_is_valid | {FPW{data2seq_frp_stage_is_flow}};
data2ram_force_tx_retry <= data2seq_frp_stage_force_tx_retry;
if(!res_n) begin
`ifdef RESET_ALL
data2ram_flit_is_hdr <= {FPW{1'b0}};
data2ram_flit_is_tail <= {FPW{1'b0}};
data2ram_flit_is_valid <= {FPW{1'b0}};
data2ram_force_tx_retry <= 1'b0;
`endif
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
tx_frp_adr[i_f] <= {RAM_ADDR_SIZE{1'b0}};
end
end else begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
if(data2seq_frp_stage_flit_is_valid[i_f]) begin
tx_frp_adr[target[i_f]] <= tx_frp_adr[target[i_f]] + 1;
end
end
end
end
//====================================================================
//---------------------------------Fill RAM
//====================================================================
//-- Always assign FLITs to RAM write register
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
ram_w_data[target[i_f]] <= { data2seq_frp_stage_flit_is_valid[i_f],
data2seq_frp_stage_flit_is_tail[i_f],
data2seq_frp_stage_flit_is_hdr[i_f],
data2seq_frp_stage_flit[i_f]
};
if(data2seq_frp_stage_flit_is_tail[i_f])begin
ram_w_data[target[i_f]][64+15+3:64+8] <= {tx_seqnum_temp[i_f],tx_frp_adr[target[i_f]],target[i_f]};
end
end
if(!res_n) begin
ram_w_en <= {FPW{1'b0}};
end else begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
if(data2seq_frp_stage_flit_is_valid[i_f]) begin
ram_w_en[target[i_f]] <= 1'b1;
end else begin
ram_w_en[target[i_f]] <= 1'b0;
end
end
end
end
//====================================================================
//---------------------------------Select Data Source: Valid sources are the Retry Buffers or regular data stream.
//====================================================================
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
`ifdef RESET_ALL
if(!res_n) data2rrp_stage_flit[i_f] <= {128{1'b0}};
else
`endif
begin
if(tx_retry_ongoing) begin
//-- If there's a TX retry ongoing increment read address until it equals the write address
data2rrp_stage_flit[i_f] <= ram_r_data[i_f][127:0];
end else begin
//Propagate data from normal packet stream
data2rrp_stage_flit[i_f] <= data2ram_flit[i_f];
end
end
end
if(!res_n) begin
//Reset control signals
tx_retry_finished <= 1'b0;
tx_retry_ongoing <= 1'b0;
rf_cnt_retry <= 1'b0;
//Ram
ram_r_en <= 1'b0;
ram_r_addr_temp <= {RAM_ADDR_SIZE{1'b0}};
ram_r_mask <= {FPW{1'b0}};
//Data propagation
data2rrp_stage_flit_is_hdr <= {FPW{1'b0}};
data2rrp_stage_flit_is_tail <= {FPW{1'b0}};
data2rrp_stage_flit_is_valid <= {FPW{1'b0}};
end else begin
tx_retry_finished <= 1'b0;
tx_retry_ongoing <= 1'b0;
rf_cnt_retry <= 1'b0;
ram_r_en <= 1'b0;
ram_r_addr_temp <= {RAM_ADDR_SIZE{1'b0}};
ram_r_mask <= {FPW{1'b0}};
//if there is a retry request coming set the ram address to last received rrp
if(data2seq_frp_stage_force_tx_retry) begin
ram_r_en <= 1'b1;
ram_r_addr_temp <= ram_r_addr+1;
end
if(!tx_retry_ongoing) begin
data2rrp_stage_flit_is_hdr <= data2ram_flit_is_hdr;
data2rrp_stage_flit_is_tail <= data2ram_flit_is_tail;
data2rrp_stage_flit_is_valid <= data2ram_flit_is_valid;
//Switch to retry if requested
if(data2ram_force_tx_retry) begin
if(ram_r_addr_temp == ram_w_addr_next) begin //if the next address is the write address -> no retry.
tx_retry_finished <= 1'b1;
end else begin
ram_r_mask <= ({FPW{1'b1}}) << (rx_rrp[8-RAM_ADDR_SIZE-1:0]);
ram_r_addr_temp <= ram_r_addr_temp+1;
ram_r_en <= 1'b1;
rf_cnt_retry <= 1'b1;
tx_retry_ongoing <= 1'b1;
end
end
end else begin
//-- If there's a TX retry ongoing increment read addr until it equals the write address
ram_r_mask <= {FPW{1'b1}};
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
data2rrp_stage_flit_is_hdr[i_f] <= ram_r_mask[i_f] ? ram_r_data[i_f][128] :1'b0 ;
data2rrp_stage_flit_is_tail[i_f] <= ram_r_mask[i_f] ? ram_r_data[i_f][128+1] :1'b0 ;
data2rrp_stage_flit_is_valid[i_f] <= ram_r_mask[i_f] ? ram_r_data[i_f][128+2] :1'b0 ;
end
//if the next address is the write address -> retry finished
if(ram_r_addr_temp == ram_w_addr_next) begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
if(i_f >= target[0] && !(tx_frp_adr[0]==tx_frp_adr[FPW-1]))begin
data2rrp_stage_flit_is_hdr[i_f] <= 1'b0;
data2rrp_stage_flit_is_tail[i_f] <= 1'b0;
data2rrp_stage_flit_is_valid[i_f] <= 1'b0;
end
end
tx_retry_finished <= 1'b1;
end else begin
ram_r_addr_temp <= ram_r_addr_temp + 1;
tx_retry_ongoing <= 1'b1;
ram_r_en <= 1'b1;
end
end
end
end
//====================================================================
//---------------------------------Add RRP
//====================================================================
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
`ifdef RESET_ALL
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
data2crc_flit[i_f] <= {128{1'b0}};
end
`endif
begin
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
data2crc_flit[i_f] <= (data2rrp_stage_flit_is_valid[i_f] || !init_state[1]) ? data2rrp_stage_flit[i_f] : {128{1'b0}};
//Add the RRP
if(data2rrp_stage_flit_is_tail[i_f] || (data2rrp_stage_flit_is_hdr[i_f] && is_req_flow(data2rrp_stage_flit[i_f])))begin
data2crc_flit[i_f][64+7:64] <= rx_hmc_frp;
end
//Increment the FRP by 1, It points to the next possible FLIT position -> retry will start there
if(data2rrp_stage_flit_is_tail[i_f])begin
data2crc_flit[i_f][64+15:64+8] <= data2rrp_stage_flit[i_f][64+15:64+8] + 1;
end
end
`ifdef SIMULATION
if((last_transmitted_rx_hmc_frp != rx_hmc_frp) && !data2rrp_stage_flit_is_valid[0])begin `else
if(!data2rrp_stage_flit_is_valid[0] && send_prets)begin `endif
data2crc_flit[0][63:0] <= pret_hdr;
data2crc_flit[0][64+7:64] <= rx_hmc_frp;
end
end
if(!res_n) begin
`ifdef SIMULATION
//----Reset control signals
last_transmitted_rx_hmc_frp <= {8{1'b0}};
`else
send_prets <= 1'b0;
`endif
//----Data
data2crc_flit_is_hdr <= {FPW{1'b0}};
data2crc_flit_is_tail <= {FPW{1'b0}};
end else begin
//Propagate signals
data2crc_flit_is_hdr <= data2rrp_stage_flit_is_hdr;
data2crc_flit_is_tail <= data2rrp_stage_flit_is_tail | ((data2rrp_stage_flit_is_hdr[FPW-1] && cmd(data2rrp_stage_flit[FPW-1])==CMD_IRTRY) ? {FPW{1'b1}} : {FPW{1'b0}}) ;
`ifdef SIMULATION
//If there is a tail, remember the last transmitted RRP. Otherwise generate PRET if there is a new RRP
if(|data2rrp_stage_flit_is_tail)begin
last_transmitted_rx_hmc_frp <= rx_hmc_frp;
end
if((last_transmitted_rx_hmc_frp != rx_hmc_frp) && !data2rrp_stage_flit_is_valid[0])begin
data2crc_flit_is_hdr[0] <= 1'b1;
data2crc_flit_is_tail[0] <= 1'b1;
last_transmitted_rx_hmc_frp <= rx_hmc_frp;
end
`else
if(|data2crc_flit_is_hdr) send_prets <= 1'b1;
if(rf_hmc_sleep_requested || rf_warm_reset) send_prets <= 1'b0;
if(!data2rrp_stage_flit_is_valid[0] && send_prets)begin
data2crc_flit_is_hdr[0] <= 1'b1;
data2crc_flit_is_tail[0] <= 1'b1;
end
`endif
end
end
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//Retry Buffer
generate
for(f=0;f<FPW;f=f+1)begin : retry_buffer_gen
openhmc_ram #(
.DATASIZE(128+3), //FLIT + tail/hdr/valid indicator
.ADDRSIZE(RAM_ADDR_SIZE)
)
retry_buffer_per_lane_I
(
.clk(clk),
.wen(ram_w_en[f]),
.wdata(ram_w_data[f]),
.waddr(tx_frp_adr[f]),
.ren(ram_r_en),
.raddr(ram_r_addr_temp),
.rdata(ram_r_data[f])
);
end
endgenerate
//HMC CRC Logic
tx_crc_combine #(
.DWIDTH(DWIDTH),
.FPW(FPW),
.LOG_FPW(LOG_FPW)
)
tx_crc_combine_I
(
.clk(clk),
.res_n(res_n),
.d_in_hdr(data2crc_flit_is_hdr),
.d_in_tail(data2crc_flit_is_tail),
.d_in_data(data2crc),
.d_out_data(data_rdy)
);
//Scrambler
generate
for(n=0;n<NUM_LANES;n=n+1) begin : scrambler_gen
tx_scrambler #(
.LANE_WIDTH(LANE_WIDTH),
.HMC_RX_AC_COUPLED(HMC_RX_AC_COUPLED)
)
scrambler_I
(
.clk(clk),
.res_n(res_n),
.disable_scrambler(rf_scrambler_disable),
.seed(seed_lane[n]), // unique per lane
.data_in(data_to_scrambler[n*LANE_WIDTH+LANE_WIDTH-1:n*LANE_WIDTH]),
.data_out(phy_scrambled_data_out[n*LANE_WIDTH+LANE_WIDTH-1:n*LANE_WIDTH]),
.rf_run_length_enable(rf_run_length_enable && ~rf_scrambler_disable),
.rf_run_length_bit_flip(bit_was_flipped[n])
);
end
endgenerate
endmodule
`default_nettype wire
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_2x.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_2x (
areset,
clkswitch,
configupdate,
inclk0,
inclk1,
scanclk,
scanclkena,
scandata,
activeclock,
c0,
c1,
locked,
scandataout,
scandone);
input areset;
input clkswitch;
input configupdate;
input inclk0;
input inclk1;
input scanclk;
input scanclkena;
input scandata;
output activeclock;
output c0;
output c1;
output locked;
output scandataout;
output scandone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 clkswitch;
tri0 configupdate;
tri0 scanclkena;
tri0 scandata;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [4:0] sub_wire1;
wire sub_wire4;
wire sub_wire5;
wire sub_wire6;
wire sub_wire9 = inclk1;
wire activeclock = sub_wire0;
wire [1:1] sub_wire3 = sub_wire1[1:1];
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire c0 = sub_wire2;
wire c1 = sub_wire3;
wire locked = sub_wire4;
wire scandataout = sub_wire5;
wire scandone = sub_wire6;
wire sub_wire7 = inclk0;
wire [1:0] sub_wire8 = {sub_wire9, sub_wire7};
altpll altpll_component (
.areset (areset),
.clkswitch (clkswitch),
.configupdate (configupdate),
.inclk (sub_wire8),
.scanclk (scanclk),
.scanclkena (scanclkena),
.scandata (scandata),
.activeclock (sub_wire0),
.clk (sub_wire1),
.locked (sub_wire4),
.scandataout (sub_wire5),
.scandone (sub_wire6),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "HIGH",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.inclk1_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_2x",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_USED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_USED",
altpll_component.port_configupdate = "PORT_USED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_USED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_USED",
altpll_component.port_scandata = "PORT_USED",
altpll_component.port_scandataout = "PORT_USED",
altpll_component.port_scandone = "PORT_USED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.primary_clock = "inclk0",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.switch_over_type = "MANUAL",
altpll_component.width_clock = 5,
`ifdef NO_PLI
altpll_component.scan_chain_mif_file = "pll_2x.rif"
`else
altpll_component.scan_chain_mif_file = "pll_2x.hex"
`endif
;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "1"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "27.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "27.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.hex"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INCLK1_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PRIMARY_CLOCK STRING "inclk0"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: SWITCH_OVER_TYPE STRING "MANUAL"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_2x.hex"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: activeclock 0 0 0 0 OUTPUT GND "activeclock"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: clkswitch 0 0 0 0 INPUT GND "clkswitch"
// Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: inclk1 0 0 0 0 INPUT_CLK_EXT GND "inclk1"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
// Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
// Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
// Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @clkswitch 0 0 0 0 clkswitch 0 0 0 0
// Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 inclk1 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
// Retrieval info: CONNECT: activeclock 0 0 0 0 @activeclock 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
// Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.mif TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.hex TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: mem_2k.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mem_2k (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [63:0] data;
input [10:0] rdaddress;
input rdclock;
input [10:0] wraddress;
input wrclock;
input wren;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({64{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 64,
altsyncram_component.width_b = 64,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL rdaddress[10..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL wraddress[10..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
// Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_2k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_2k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_2k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_2k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_2k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_2k_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_2k_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_2k_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_BEHAVIORAL_V |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_hdr_fifo.v
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The tx_hdr_fifo module implements a simple fifo for a packet
// (WR_TX_HDR) header and three metadata signals: WR_TX_HDR_ABLANKS,
// WR_TX_HDR_LEN, WR_TX_HDR_NOPAYLOAD. NOPAYLOAD indicates that the header is not
// followed by a payload. HDR_LEN indicates the length of the header in
// dwords. The ABLANKS signal indicates how many dwords should be inserted between
// the header and payload.
//
// The intended use for this module is between the interface specific tx formatter
// (TXC or TXR) and the alignment pipeline, in parallel with the tx_data_pipeline
// which contains a fifo for payloads.
//
// Author: Dustin Richmond (@darichmond)
// Co-Authors:
//----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_hdr_fifo
#(parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_PIPELINE_INPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: WR_TX_HDR
input WR_TX_HDR_VALID,
input [(C_MAX_HDR_WIDTH)-1:0] WR_TX_HDR,
input [`SIG_LEN_W-1:0] WR_TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] WR_TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] WR_TX_HDR_PACKET_LEN,
input WR_TX_HDR_NOPAYLOAD,
output WR_TX_HDR_READY,
// Interface: RD_TX_HDR
output RD_TX_HDR_VALID,
output [(C_MAX_HDR_WIDTH)-1:0] RD_TX_HDR,
output [`SIG_LEN_W-1:0] RD_TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] RD_TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] RD_TX_HDR_PACKET_LEN,
output RD_TX_HDR_NOPAYLOAD,
input RD_TX_HDR_READY
);
`include "functions.vh"
// Size of the header, plus the three metadata signals
localparam C_WIDTH = (C_MAX_HDR_WIDTH) + `SIG_NONPAY_W + `SIG_PACKETLEN_W + 1 + `SIG_LEN_W;
wire RST;
wire wWrTxHdrReady;
wire wWrTxHdrValid;
wire [(C_MAX_HDR_WIDTH)-1:0] wWrTxHdr;
wire [`SIG_NONPAY_W-1:0] wWrTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wWrTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wWrTxHdrPayloadLen;
wire wWrTxHdrNoPayload;
wire wRdTxHdrReady;
wire wRdTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wRdTxHdr;
wire [`SIG_NONPAY_W-1:0] wRdTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wRdTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wRdTxHdrPayloadLen;
wire wRdTxHdrNoPayload;
assign RST = RST_IN;
pipeline
#(
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
input_pipeline_inst
(
// Outputs
.WR_DATA_READY (WR_TX_HDR_READY),
.RD_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.RD_DATA_VALID (wWrTxHdrValid),
// Inputs
.WR_DATA ({WR_TX_HDR,WR_TX_HDR_NONPAY_LEN,WR_TX_HDR_PACKET_LEN,WR_TX_HDR_PAYLOAD_LEN,WR_TX_HDR_NOPAYLOAD}),
.WR_DATA_VALID (WR_TX_HDR_VALID),
.RD_DATA_READY (wWrTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
fifo
#(
// Parameters
.C_DELAY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH),
.C_DEPTH (C_DEPTH_PACKETS))
fifo_inst
(
// Outputs
.RD_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_READY (wWrTxHdrReady),
.RD_VALID (wRdTxHdrValid),
// Inputs
.WR_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.WR_VALID (wWrTxHdrValid),
.RD_READY (wRdTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST (RST));
pipeline
#(
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
output_pipeline_inst
(
// Outputs
.WR_DATA_READY (wRdTxHdrReady),
.RD_DATA ({RD_TX_HDR,RD_TX_HDR_NONPAY_LEN,RD_TX_HDR_PACKET_LEN,RD_TX_HDR_PAYLOAD_LEN,RD_TX_HDR_NOPAYLOAD}),
.RD_DATA_VALID (RD_TX_HDR_VALID),
// Inputs
.WR_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_DATA_VALID (wRdTxHdrValid),
.RD_DATA_READY (RD_TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/")
// End:
|
// megafunction wizard: %ALTFP_SINCOS%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_sincos
// ============================================================
// File Name: sin.v
// Megafunction Name(s):
// altfp_sincos
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
//altfp_sincos CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" OPERATION="SIN" PIPELINE=36 ROUNDING="TO_NEAREST" WIDTH_EXP=8 WIDTH_MAN=23 clock data result
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altfp_sincos_cordic_m CBX_AUTO_BLACKBOX="ALL" DEPTH=18 DEVICE_FAMILY="Cyclone V" INDEXPOINT=2 WIDTH=34 aclr clken clock indexbit radians sincos sincosbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=0 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_45b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_0_w;
wire [47:0] valuenode_2_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_0_w[47:14]) | ({34{indexbit}} & valuenode_2_w[45:12])),
valuenode_0_w = 48'b001100100100001111110110101010001000100001011010,
valuenode_2_w = 48'b000011111010110110111010111111001001011001000000;
endmodule //sin_altfp_sincos_cordic_atan_45b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=10 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_l6b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_10_w;
wire [47:0] valuenode_12_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_10_w[47:14]) | ({34{indexbit}} & valuenode_12_w[45:12])),
valuenode_10_w = 48'b000000000000111111111111111111111010101010101011,
valuenode_12_w = 48'b000000000000001111111111111111111111111010101011;
endmodule //sin_altfp_sincos_cordic_atan_l6b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=11 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_m6b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_11_w;
wire [47:0] valuenode_13_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_11_w[47:14]) | ({34{indexbit}} & valuenode_13_w[45:12])),
valuenode_11_w = 48'b000000000000011111111111111111111111010101010101,
valuenode_13_w = 48'b000000000000000111111111111111111111111111010101;
endmodule //sin_altfp_sincos_cordic_atan_m6b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=12 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_n6b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_12_w;
wire [47:0] valuenode_14_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_12_w[47:14]) | ({34{indexbit}} & valuenode_14_w[45:12])),
valuenode_12_w = 48'b000000000000001111111111111111111111111010101011,
valuenode_14_w = 48'b000000000000000011111111111111111111111111111011;
endmodule //sin_altfp_sincos_cordic_atan_n6b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=13 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_o6b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_13_w;
wire [47:0] valuenode_15_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_13_w[47:14]) | ({34{indexbit}} & valuenode_15_w[45:12])),
valuenode_13_w = 48'b000000000000000111111111111111111111111111010101,
valuenode_15_w = 48'b000000000000000001111111111111111111111111111111;
endmodule //sin_altfp_sincos_cordic_atan_o6b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=1 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_55b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_1_w;
wire [47:0] valuenode_3_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_1_w[47:14]) | ({34{indexbit}} & valuenode_3_w[45:12])),
valuenode_1_w = 48'b000111011010110001100111000001010110000110111011,
valuenode_3_w = 48'b000001111111010101101110101001101010101100001100;
endmodule //sin_altfp_sincos_cordic_atan_55b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=2 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_65b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_2_w;
wire [47:0] valuenode_4_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_2_w[47:14]) | ({34{indexbit}} & valuenode_4_w[45:12])),
valuenode_2_w = 48'b000011111010110110111010111111001001011001000000,
valuenode_4_w = 48'b000000111111111010101011011101101110010110100000;
endmodule //sin_altfp_sincos_cordic_atan_65b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=3 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_75b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_3_w;
wire [47:0] valuenode_5_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_3_w[47:14]) | ({34{indexbit}} & valuenode_5_w[45:12])),
valuenode_3_w = 48'b000001111111010101101110101001101010101100001100,
valuenode_5_w = 48'b000000011111111111010101010110111011101010010111;
endmodule //sin_altfp_sincos_cordic_atan_75b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=4 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_85b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_4_w;
wire [47:0] valuenode_6_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_4_w[47:14]) | ({34{indexbit}} & valuenode_6_w[45:12])),
valuenode_4_w = 48'b000000111111111010101011011101101110010110100000,
valuenode_6_w = 48'b000000001111111111111010101010101101110111011100;
endmodule //sin_altfp_sincos_cordic_atan_85b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=5 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_95b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_5_w;
wire [47:0] valuenode_7_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_5_w[47:14]) | ({34{indexbit}} & valuenode_7_w[45:12])),
valuenode_5_w = 48'b000000011111111111010101010110111011101010010111,
valuenode_7_w = 48'b000000000111111111111111010101010101011011101111;
endmodule //sin_altfp_sincos_cordic_atan_95b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=6 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_a5b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_6_w;
wire [47:0] valuenode_8_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_6_w[47:14]) | ({34{indexbit}} & valuenode_8_w[45:12])),
valuenode_6_w = 48'b000000001111111111111010101010101101110111011100,
valuenode_8_w = 48'b000000000011111111111111111010101010101010110111;
endmodule //sin_altfp_sincos_cordic_atan_a5b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=7 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_b5b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_7_w;
wire [47:0] valuenode_9_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_7_w[47:14]) | ({34{indexbit}} & valuenode_9_w[45:12])),
valuenode_7_w = 48'b000000000111111111111111010101010101011011101111,
valuenode_9_w = 48'b000000000001111111111111111111010101010101010110;
endmodule //sin_altfp_sincos_cordic_atan_b5b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=8 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_c5b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_10_w;
wire [47:0] valuenode_8_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_8_w[47:14]) | ({34{indexbit}} & valuenode_10_w[45:12])),
valuenode_10_w = 48'b000000000000111111111111111111111010101010101011,
valuenode_8_w = 48'b000000000011111111111111111010101010101010110111;
endmodule //sin_altfp_sincos_cordic_atan_c5b
//altfp_sincos_cordic_atan CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" indexpoint=2 START=9 WIDTH=34 arctan indexbit
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_atan_d5b
(
arctan,
indexbit) ;
output [33:0] arctan;
input indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 indexbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] valuenode_11_w;
wire [47:0] valuenode_9_w;
assign
arctan = (({34{(~ indexbit)}} & valuenode_9_w[47:14]) | ({34{indexbit}} & valuenode_11_w[45:12])),
valuenode_11_w = 48'b000000000000011111111111111111111111010101010101,
valuenode_9_w = 48'b000000000001111111111111111111010101010101010110;
endmodule //sin_altfp_sincos_cordic_atan_d5b
//altfp_sincos_cordic_start CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" WIDTH=34 index value
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources = lpm_mux 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_start_709
(
index,
value) ;
input [3:0] index;
output [33:0] value;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [3:0] index;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [33:0] wire_mux1_result;
wire [35:0] valuenode_0_w;
wire [35:0] valuenode_10_w;
wire [35:0] valuenode_11_w;
wire [35:0] valuenode_12_w;
wire [35:0] valuenode_13_w;
wire [35:0] valuenode_14_w;
wire [35:0] valuenode_15_w;
wire [35:0] valuenode_1_w;
wire [35:0] valuenode_2_w;
wire [35:0] valuenode_3_w;
wire [35:0] valuenode_4_w;
wire [35:0] valuenode_5_w;
wire [35:0] valuenode_6_w;
wire [35:0] valuenode_7_w;
wire [35:0] valuenode_8_w;
wire [35:0] valuenode_9_w;
lpm_mux mux1
(
.data({valuenode_15_w[35:2], valuenode_14_w[35:2], valuenode_13_w[35:2], valuenode_12_w[35:2], valuenode_11_w[35:2], valuenode_10_w[35:2], valuenode_9_w[35:2], valuenode_8_w[35:2], valuenode_7_w[35:2], valuenode_6_w[35:2], valuenode_5_w[35:2], valuenode_4_w[35:2], valuenode_3_w[35:2], valuenode_2_w[35:2], valuenode_1_w[35:2], valuenode_0_w[35:2]}),
.result(wire_mux1_result),
.sel(index)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mux1.lpm_size = 16,
mux1.lpm_width = 34,
mux1.lpm_widths = 4,
mux1.lpm_type = "lpm_mux";
assign
value = wire_mux1_result,
valuenode_0_w = 36'b001001101101110100111011011010100001,
valuenode_10_w = 36'b001111111111111111111101010101010101,
valuenode_11_w = 36'b001111111111111111111111010101010101,
valuenode_12_w = 36'b001111111111111111111111111101010101,
valuenode_13_w = 36'b001111111111111111111111110101010101,
valuenode_14_w = 36'b001111111111111111111111111111110101,
valuenode_15_w = 36'b001111111111111111111111111111010101,
valuenode_1_w = 36'b001101101111011001010110110001011010,
valuenode_2_w = 36'b001111010111001100011101111111111011,
valuenode_3_w = 36'b001111110101011101000011101100100100,
valuenode_4_w = 36'b001111111101010101110100100001100000,
valuenode_5_w = 36'b001111111111010101010111010010011001,
valuenode_6_w = 36'b001111111111110101010101011101001010,
valuenode_7_w = 36'b001111111111111101010101010101110101,
valuenode_8_w = 36'b001111111111111111010101010101010111,
valuenode_9_w = 36'b001111111111111111110101010101010101;
endmodule //sin_altfp_sincos_cordic_start_709
//synthesis_resources = lpm_add_sub 39 lpm_mult 1 lpm_mux 1 reg 1598
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_cordic_m_e5e
(
aclr,
clken,
clock,
indexbit,
radians,
sincos,
sincosbit) ;
input aclr;
input clken;
input clock;
input indexbit;
input [33:0] radians;
output [33:0] sincos;
input sincosbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 indexbit;
tri0 [33:0] radians;
tri0 sincosbit;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [33:0] wire_cata_0_cordic_atan_arctan;
wire [33:0] wire_cata_10_cordic_atan_arctan;
wire [33:0] wire_cata_11_cordic_atan_arctan;
wire [33:0] wire_cata_12_cordic_atan_arctan;
wire [33:0] wire_cata_13_cordic_atan_arctan;
wire [33:0] wire_cata_1_cordic_atan_arctan;
wire [33:0] wire_cata_2_cordic_atan_arctan;
wire [33:0] wire_cata_3_cordic_atan_arctan;
wire [33:0] wire_cata_4_cordic_atan_arctan;
wire [33:0] wire_cata_5_cordic_atan_arctan;
wire [33:0] wire_cata_6_cordic_atan_arctan;
wire [33:0] wire_cata_7_cordic_atan_arctan;
wire [33:0] wire_cata_8_cordic_atan_arctan;
wire [33:0] wire_cata_9_cordic_atan_arctan;
wire [33:0] wire_cxs_value;
reg [33:0] cdaff_0;
reg [33:0] cdaff_1;
reg [33:0] cdaff_2;
reg [16:0] indexbitff;
reg [16:0] sincosbitff;
reg [33:0] sincosff;
reg [33:0] x_pipeff_0;
reg [33:0] x_pipeff_1;
reg [33:0] x_pipeff_10;
reg [33:0] x_pipeff_11;
reg [33:0] x_pipeff_12;
reg [33:0] x_pipeff_13;
reg [33:0] x_pipeff_2;
reg [33:0] x_pipeff_3;
reg [33:0] x_pipeff_4;
reg [33:0] x_pipeff_5;
reg [33:0] x_pipeff_6;
reg [33:0] x_pipeff_7;
reg [33:0] x_pipeff_8;
reg [33:0] x_pipeff_9;
reg [33:0] y_pipeff_0;
reg [33:0] y_pipeff_1;
reg [33:0] y_pipeff_10;
reg [33:0] y_pipeff_11;
reg [33:0] y_pipeff_12;
reg [33:0] y_pipeff_13;
reg [33:0] y_pipeff_2;
reg [33:0] y_pipeff_3;
reg [33:0] y_pipeff_4;
reg [33:0] y_pipeff_5;
reg [33:0] y_pipeff_6;
reg [33:0] y_pipeff_7;
reg [33:0] y_pipeff_8;
reg [33:0] y_pipeff_9;
reg [33:0] z_pipeff_0;
reg [33:0] z_pipeff_1;
reg [33:0] z_pipeff_10;
reg [33:0] z_pipeff_11;
reg [33:0] z_pipeff_12;
reg [33:0] z_pipeff_13;
reg [33:0] z_pipeff_2;
reg [33:0] z_pipeff_3;
reg [33:0] z_pipeff_4;
reg [33:0] z_pipeff_5;
reg [33:0] z_pipeff_6;
reg [33:0] z_pipeff_7;
reg [33:0] z_pipeff_8;
reg [33:0] z_pipeff_9;
wire [33:0] wire_sincos_add_result;
wire [33:0] wire_x_pipenode_10_add_result;
wire [33:0] wire_x_pipenode_11_add_result;
wire [33:0] wire_x_pipenode_12_add_result;
wire [33:0] wire_x_pipenode_13_add_result;
wire [33:0] wire_x_pipenode_2_add_result;
wire [33:0] wire_x_pipenode_3_add_result;
wire [33:0] wire_x_pipenode_4_add_result;
wire [33:0] wire_x_pipenode_5_add_result;
wire [33:0] wire_x_pipenode_6_add_result;
wire [33:0] wire_x_pipenode_7_add_result;
wire [33:0] wire_x_pipenode_8_add_result;
wire [33:0] wire_x_pipenode_9_add_result;
wire [33:0] wire_y_pipeff1_add_result;
wire [33:0] wire_y_pipenode_10_add_result;
wire [33:0] wire_y_pipenode_11_add_result;
wire [33:0] wire_y_pipenode_12_add_result;
wire [33:0] wire_y_pipenode_13_add_result;
wire [33:0] wire_y_pipenode_2_add_result;
wire [33:0] wire_y_pipenode_3_add_result;
wire [33:0] wire_y_pipenode_4_add_result;
wire [33:0] wire_y_pipenode_5_add_result;
wire [33:0] wire_y_pipenode_6_add_result;
wire [33:0] wire_y_pipenode_7_add_result;
wire [33:0] wire_y_pipenode_8_add_result;
wire [33:0] wire_y_pipenode_9_add_result;
wire [33:0] wire_z_pipeff1_sub_result;
wire [33:0] wire_z_pipenode_10_add_result;
wire [33:0] wire_z_pipenode_11_add_result;
wire [33:0] wire_z_pipenode_12_add_result;
wire [33:0] wire_z_pipenode_13_add_result;
wire [33:0] wire_z_pipenode_2_add_result;
wire [33:0] wire_z_pipenode_3_add_result;
wire [33:0] wire_z_pipenode_4_add_result;
wire [33:0] wire_z_pipenode_5_add_result;
wire [33:0] wire_z_pipenode_6_add_result;
wire [33:0] wire_z_pipenode_7_add_result;
wire [33:0] wire_z_pipenode_8_add_result;
wire [33:0] wire_z_pipenode_9_add_result;
wire [67:0] wire_cmx_result;
wire [33:0] atannode_0_w;
wire [33:0] atannode_10_w;
wire [33:0] atannode_11_w;
wire [33:0] atannode_12_w;
wire [33:0] atannode_1_w;
wire [33:0] atannode_2_w;
wire [33:0] atannode_3_w;
wire [33:0] atannode_4_w;
wire [33:0] atannode_5_w;
wire [33:0] atannode_6_w;
wire [33:0] atannode_7_w;
wire [33:0] atannode_8_w;
wire [33:0] atannode_9_w;
wire [33:0] delay_input_w;
wire [33:0] delay_pipe_w;
wire [33:0] estimate_w;
wire [3:0] indexpointnum_w;
wire [33:0] multiplier_input_w;
wire [67:0] multipliernode_w;
wire [33:0] post_estimate_w;
wire [33:0] pre_estimate_w;
wire [33:0] radians_load_node_w;
wire [3:0] startindex_w;
wire [33:0] x_pipenode_10_w;
wire [33:0] x_pipenode_11_w;
wire [33:0] x_pipenode_12_w;
wire [33:0] x_pipenode_13_w;
wire [33:0] x_pipenode_2_w;
wire [33:0] x_pipenode_3_w;
wire [33:0] x_pipenode_4_w;
wire [33:0] x_pipenode_5_w;
wire [33:0] x_pipenode_6_w;
wire [33:0] x_pipenode_7_w;
wire [33:0] x_pipenode_8_w;
wire [33:0] x_pipenode_9_w;
wire [33:0] x_prenode_10_w;
wire [33:0] x_prenode_11_w;
wire [33:0] x_prenode_12_w;
wire [33:0] x_prenode_13_w;
wire [33:0] x_prenode_2_w;
wire [33:0] x_prenode_3_w;
wire [33:0] x_prenode_4_w;
wire [33:0] x_prenode_5_w;
wire [33:0] x_prenode_6_w;
wire [33:0] x_prenode_7_w;
wire [33:0] x_prenode_8_w;
wire [33:0] x_prenode_9_w;
wire [33:0] x_prenodeone_10_w;
wire [33:0] x_prenodeone_11_w;
wire [33:0] x_prenodeone_12_w;
wire [33:0] x_prenodeone_13_w;
wire [33:0] x_prenodeone_2_w;
wire [33:0] x_prenodeone_3_w;
wire [33:0] x_prenodeone_4_w;
wire [33:0] x_prenodeone_5_w;
wire [33:0] x_prenodeone_6_w;
wire [33:0] x_prenodeone_7_w;
wire [33:0] x_prenodeone_8_w;
wire [33:0] x_prenodeone_9_w;
wire [33:0] x_prenodetwo_10_w;
wire [33:0] x_prenodetwo_11_w;
wire [33:0] x_prenodetwo_12_w;
wire [33:0] x_prenodetwo_13_w;
wire [33:0] x_prenodetwo_2_w;
wire [33:0] x_prenodetwo_3_w;
wire [33:0] x_prenodetwo_4_w;
wire [33:0] x_prenodetwo_5_w;
wire [33:0] x_prenodetwo_6_w;
wire [33:0] x_prenodetwo_7_w;
wire [33:0] x_prenodetwo_8_w;
wire [33:0] x_prenodetwo_9_w;
wire [33:0] x_start_node_w;
wire [33:0] x_subnode_10_w;
wire [33:0] x_subnode_11_w;
wire [33:0] x_subnode_12_w;
wire [33:0] x_subnode_13_w;
wire [33:0] x_subnode_2_w;
wire [33:0] x_subnode_3_w;
wire [33:0] x_subnode_4_w;
wire [33:0] x_subnode_5_w;
wire [33:0] x_subnode_6_w;
wire [33:0] x_subnode_7_w;
wire [33:0] x_subnode_8_w;
wire [33:0] x_subnode_9_w;
wire [33:0] y_pipenode_10_w;
wire [33:0] y_pipenode_11_w;
wire [33:0] y_pipenode_12_w;
wire [33:0] y_pipenode_13_w;
wire [33:0] y_pipenode_2_w;
wire [33:0] y_pipenode_3_w;
wire [33:0] y_pipenode_4_w;
wire [33:0] y_pipenode_5_w;
wire [33:0] y_pipenode_6_w;
wire [33:0] y_pipenode_7_w;
wire [33:0] y_pipenode_8_w;
wire [33:0] y_pipenode_9_w;
wire [33:0] y_prenode_10_w;
wire [33:0] y_prenode_11_w;
wire [33:0] y_prenode_12_w;
wire [33:0] y_prenode_13_w;
wire [33:0] y_prenode_2_w;
wire [33:0] y_prenode_3_w;
wire [33:0] y_prenode_4_w;
wire [33:0] y_prenode_5_w;
wire [33:0] y_prenode_6_w;
wire [33:0] y_prenode_7_w;
wire [33:0] y_prenode_8_w;
wire [33:0] y_prenode_9_w;
wire [33:0] y_prenodeone_10_w;
wire [33:0] y_prenodeone_11_w;
wire [33:0] y_prenodeone_12_w;
wire [33:0] y_prenodeone_13_w;
wire [33:0] y_prenodeone_2_w;
wire [33:0] y_prenodeone_3_w;
wire [33:0] y_prenodeone_4_w;
wire [33:0] y_prenodeone_5_w;
wire [33:0] y_prenodeone_6_w;
wire [33:0] y_prenodeone_7_w;
wire [33:0] y_prenodeone_8_w;
wire [33:0] y_prenodeone_9_w;
wire [33:0] y_prenodetwo_10_w;
wire [33:0] y_prenodetwo_11_w;
wire [33:0] y_prenodetwo_12_w;
wire [33:0] y_prenodetwo_13_w;
wire [33:0] y_prenodetwo_2_w;
wire [33:0] y_prenodetwo_3_w;
wire [33:0] y_prenodetwo_4_w;
wire [33:0] y_prenodetwo_5_w;
wire [33:0] y_prenodetwo_6_w;
wire [33:0] y_prenodetwo_7_w;
wire [33:0] y_prenodetwo_8_w;
wire [33:0] y_prenodetwo_9_w;
wire [33:0] y_subnode_10_w;
wire [33:0] y_subnode_11_w;
wire [33:0] y_subnode_12_w;
wire [33:0] y_subnode_13_w;
wire [33:0] y_subnode_1_w;
wire [33:0] y_subnode_2_w;
wire [33:0] y_subnode_3_w;
wire [33:0] y_subnode_4_w;
wire [33:0] y_subnode_5_w;
wire [33:0] y_subnode_6_w;
wire [33:0] y_subnode_7_w;
wire [33:0] y_subnode_8_w;
wire [33:0] y_subnode_9_w;
wire [33:0] z_pipenode_10_w;
wire [33:0] z_pipenode_11_w;
wire [33:0] z_pipenode_12_w;
wire [33:0] z_pipenode_13_w;
wire [33:0] z_pipenode_2_w;
wire [33:0] z_pipenode_3_w;
wire [33:0] z_pipenode_4_w;
wire [33:0] z_pipenode_5_w;
wire [33:0] z_pipenode_6_w;
wire [33:0] z_pipenode_7_w;
wire [33:0] z_pipenode_8_w;
wire [33:0] z_pipenode_9_w;
wire [33:0] z_subnode_10_w;
wire [33:0] z_subnode_11_w;
wire [33:0] z_subnode_12_w;
wire [33:0] z_subnode_13_w;
wire [33:0] z_subnode_2_w;
wire [33:0] z_subnode_3_w;
wire [33:0] z_subnode_4_w;
wire [33:0] z_subnode_5_w;
wire [33:0] z_subnode_6_w;
wire [33:0] z_subnode_7_w;
wire [33:0] z_subnode_8_w;
wire [33:0] z_subnode_9_w;
sin_altfp_sincos_cordic_atan_45b cata_0_cordic_atan
(
.arctan(wire_cata_0_cordic_atan_arctan),
.indexbit(indexbitff[0]));
sin_altfp_sincos_cordic_atan_l6b cata_10_cordic_atan
(
.arctan(wire_cata_10_cordic_atan_arctan),
.indexbit(indexbitff[10]));
sin_altfp_sincos_cordic_atan_m6b cata_11_cordic_atan
(
.arctan(wire_cata_11_cordic_atan_arctan),
.indexbit(indexbitff[11]));
sin_altfp_sincos_cordic_atan_n6b cata_12_cordic_atan
(
.arctan(wire_cata_12_cordic_atan_arctan),
.indexbit(indexbitff[12]));
sin_altfp_sincos_cordic_atan_o6b cata_13_cordic_atan
(
.arctan(wire_cata_13_cordic_atan_arctan),
.indexbit(indexbitff[13]));
sin_altfp_sincos_cordic_atan_55b cata_1_cordic_atan
(
.arctan(wire_cata_1_cordic_atan_arctan),
.indexbit(indexbitff[1]));
sin_altfp_sincos_cordic_atan_65b cata_2_cordic_atan
(
.arctan(wire_cata_2_cordic_atan_arctan),
.indexbit(indexbitff[2]));
sin_altfp_sincos_cordic_atan_75b cata_3_cordic_atan
(
.arctan(wire_cata_3_cordic_atan_arctan),
.indexbit(indexbitff[3]));
sin_altfp_sincos_cordic_atan_85b cata_4_cordic_atan
(
.arctan(wire_cata_4_cordic_atan_arctan),
.indexbit(indexbitff[4]));
sin_altfp_sincos_cordic_atan_95b cata_5_cordic_atan
(
.arctan(wire_cata_5_cordic_atan_arctan),
.indexbit(indexbitff[5]));
sin_altfp_sincos_cordic_atan_a5b cata_6_cordic_atan
(
.arctan(wire_cata_6_cordic_atan_arctan),
.indexbit(indexbitff[6]));
sin_altfp_sincos_cordic_atan_b5b cata_7_cordic_atan
(
.arctan(wire_cata_7_cordic_atan_arctan),
.indexbit(indexbitff[7]));
sin_altfp_sincos_cordic_atan_c5b cata_8_cordic_atan
(
.arctan(wire_cata_8_cordic_atan_arctan),
.indexbit(indexbitff[8]));
sin_altfp_sincos_cordic_atan_d5b cata_9_cordic_atan
(
.arctan(wire_cata_9_cordic_atan_arctan),
.indexbit(indexbitff[9]));
sin_altfp_sincos_cordic_start_709 cxs
(
.index(startindex_w),
.value(wire_cxs_value));
// synopsys translate_off
initial
cdaff_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) cdaff_0 <= 34'b0;
else if (clken == 1'b1) cdaff_0 <= delay_input_w;
// synopsys translate_off
initial
cdaff_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) cdaff_1 <= 34'b0;
else if (clken == 1'b1) cdaff_1 <= cdaff_0;
// synopsys translate_off
initial
cdaff_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) cdaff_2 <= 34'b0;
else if (clken == 1'b1) cdaff_2 <= cdaff_1;
// synopsys translate_off
initial
indexbitff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) indexbitff <= 17'b0;
else if (clken == 1'b1) indexbitff <= {indexbitff[15:0], indexbit};
// synopsys translate_off
initial
sincosbitff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sincosbitff <= 17'b0;
else if (clken == 1'b1) sincosbitff <= {sincosbitff[15:0], sincosbit};
// synopsys translate_off
initial
sincosff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sincosff <= 34'b0;
else if (clken == 1'b1) sincosff <= wire_sincos_add_result;
// synopsys translate_off
initial
x_pipeff_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_0 <= 34'b0;
else if (clken == 1'b1) x_pipeff_0 <= x_start_node_w;
// synopsys translate_off
initial
x_pipeff_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_1 <= 34'b0;
else if (clken == 1'b1) x_pipeff_1 <= x_pipeff_0;
// synopsys translate_off
initial
x_pipeff_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_10 <= 34'b0;
else if (clken == 1'b1) x_pipeff_10 <= x_pipenode_10_w;
// synopsys translate_off
initial
x_pipeff_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_11 <= 34'b0;
else if (clken == 1'b1) x_pipeff_11 <= x_pipenode_11_w;
// synopsys translate_off
initial
x_pipeff_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_12 <= 34'b0;
else if (clken == 1'b1) x_pipeff_12 <= x_pipenode_12_w;
// synopsys translate_off
initial
x_pipeff_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_13 <= 34'b0;
else if (clken == 1'b1) x_pipeff_13 <= x_pipenode_13_w;
// synopsys translate_off
initial
x_pipeff_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_2 <= 34'b0;
else if (clken == 1'b1) x_pipeff_2 <= x_pipenode_2_w;
// synopsys translate_off
initial
x_pipeff_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_3 <= 34'b0;
else if (clken == 1'b1) x_pipeff_3 <= x_pipenode_3_w;
// synopsys translate_off
initial
x_pipeff_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_4 <= 34'b0;
else if (clken == 1'b1) x_pipeff_4 <= x_pipenode_4_w;
// synopsys translate_off
initial
x_pipeff_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_5 <= 34'b0;
else if (clken == 1'b1) x_pipeff_5 <= x_pipenode_5_w;
// synopsys translate_off
initial
x_pipeff_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_6 <= 34'b0;
else if (clken == 1'b1) x_pipeff_6 <= x_pipenode_6_w;
// synopsys translate_off
initial
x_pipeff_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_7 <= 34'b0;
else if (clken == 1'b1) x_pipeff_7 <= x_pipenode_7_w;
// synopsys translate_off
initial
x_pipeff_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_8 <= 34'b0;
else if (clken == 1'b1) x_pipeff_8 <= x_pipenode_8_w;
// synopsys translate_off
initial
x_pipeff_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_pipeff_9 <= 34'b0;
else if (clken == 1'b1) x_pipeff_9 <= x_pipenode_9_w;
// synopsys translate_off
initial
y_pipeff_0[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[0:0] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[0:0] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[1:1] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[1:1] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[2:2] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[2:2] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[3:3] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[3:3] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[4:4] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[4:4] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[5:5] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[5:5] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[5:5] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[6:6] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[6:6] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[6:6] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[7:7] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[7:7] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[7:7] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[8:8] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[8:8] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[8:8] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[9:9] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[9:9] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[9:9] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[10:10] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[10:10] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[10:10] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[11:11] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[11:11] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[11:11] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[12:12] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[12:12] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[12:12] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[13:13] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[13:13] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[13:13] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[14:14] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[14:14] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[14:14] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[15:15] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[15:15] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[15:15] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[16:16] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[16:16] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[16:16] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[17:17] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[17:17] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[17:17] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[18:18] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[18:18] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[18:18] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[19:19] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[19:19] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[19:19] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[20:20] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[20:20] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[20:20] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[21:21] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[21:21] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[21:21] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[22:22] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[22:22] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[22:22] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[23:23] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[23:23] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[23:23] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[24:24] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[24:24] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[24:24] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[25:25] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[25:25] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[25:25] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[26:26] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[26:26] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[26:26] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[27:27] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[27:27] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[27:27] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[28:28] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[28:28] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[28:28] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[29:29] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[29:29] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[29:29] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[30:30] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[30:30] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[30:30] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[31:31] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[31:31] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[31:31] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[32:32] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[32:32] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[32:32] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_0[33:33] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_0[33:33] <= 1'b0;
else if (clken == 1'b1) y_pipeff_0[33:33] <= 1'b0;
// synopsys translate_off
initial
y_pipeff_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_1 <= 34'b0;
else if (clken == 1'b1) y_pipeff_1 <= wire_y_pipeff1_add_result;
// synopsys translate_off
initial
y_pipeff_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_10 <= 34'b0;
else if (clken == 1'b1) y_pipeff_10 <= y_pipenode_10_w;
// synopsys translate_off
initial
y_pipeff_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_11 <= 34'b0;
else if (clken == 1'b1) y_pipeff_11 <= y_pipenode_11_w;
// synopsys translate_off
initial
y_pipeff_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_12 <= 34'b0;
else if (clken == 1'b1) y_pipeff_12 <= y_pipenode_12_w;
// synopsys translate_off
initial
y_pipeff_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_13 <= 34'b0;
else if (clken == 1'b1) y_pipeff_13 <= y_pipenode_13_w;
// synopsys translate_off
initial
y_pipeff_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_2 <= 34'b0;
else if (clken == 1'b1) y_pipeff_2 <= y_pipenode_2_w;
// synopsys translate_off
initial
y_pipeff_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_3 <= 34'b0;
else if (clken == 1'b1) y_pipeff_3 <= y_pipenode_3_w;
// synopsys translate_off
initial
y_pipeff_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_4 <= 34'b0;
else if (clken == 1'b1) y_pipeff_4 <= y_pipenode_4_w;
// synopsys translate_off
initial
y_pipeff_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_5 <= 34'b0;
else if (clken == 1'b1) y_pipeff_5 <= y_pipenode_5_w;
// synopsys translate_off
initial
y_pipeff_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_6 <= 34'b0;
else if (clken == 1'b1) y_pipeff_6 <= y_pipenode_6_w;
// synopsys translate_off
initial
y_pipeff_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_7 <= 34'b0;
else if (clken == 1'b1) y_pipeff_7 <= y_pipenode_7_w;
// synopsys translate_off
initial
y_pipeff_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_8 <= 34'b0;
else if (clken == 1'b1) y_pipeff_8 <= y_pipenode_8_w;
// synopsys translate_off
initial
y_pipeff_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) y_pipeff_9 <= 34'b0;
else if (clken == 1'b1) y_pipeff_9 <= y_pipenode_9_w;
// synopsys translate_off
initial
z_pipeff_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_0 <= 34'b0;
else if (clken == 1'b1) z_pipeff_0 <= radians_load_node_w;
// synopsys translate_off
initial
z_pipeff_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_1 <= 34'b0;
else if (clken == 1'b1) z_pipeff_1 <= wire_z_pipeff1_sub_result;
// synopsys translate_off
initial
z_pipeff_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_10 <= 34'b0;
else if (clken == 1'b1) z_pipeff_10 <= z_pipenode_10_w;
// synopsys translate_off
initial
z_pipeff_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_11 <= 34'b0;
else if (clken == 1'b1) z_pipeff_11 <= z_pipenode_11_w;
// synopsys translate_off
initial
z_pipeff_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_12 <= 34'b0;
else if (clken == 1'b1) z_pipeff_12 <= z_pipenode_12_w;
// synopsys translate_off
initial
z_pipeff_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_13 <= 34'b0;
else if (clken == 1'b1) z_pipeff_13 <= z_pipenode_13_w;
// synopsys translate_off
initial
z_pipeff_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_2 <= 34'b0;
else if (clken == 1'b1) z_pipeff_2 <= z_pipenode_2_w;
// synopsys translate_off
initial
z_pipeff_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_3 <= 34'b0;
else if (clken == 1'b1) z_pipeff_3 <= z_pipenode_3_w;
// synopsys translate_off
initial
z_pipeff_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_4 <= 34'b0;
else if (clken == 1'b1) z_pipeff_4 <= z_pipenode_4_w;
// synopsys translate_off
initial
z_pipeff_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_5 <= 34'b0;
else if (clken == 1'b1) z_pipeff_5 <= z_pipenode_5_w;
// synopsys translate_off
initial
z_pipeff_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_6 <= 34'b0;
else if (clken == 1'b1) z_pipeff_6 <= z_pipenode_6_w;
// synopsys translate_off
initial
z_pipeff_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_7 <= 34'b0;
else if (clken == 1'b1) z_pipeff_7 <= z_pipenode_7_w;
// synopsys translate_off
initial
z_pipeff_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_8 <= 34'b0;
else if (clken == 1'b1) z_pipeff_8 <= z_pipenode_8_w;
// synopsys translate_off
initial
z_pipeff_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) z_pipeff_9 <= 34'b0;
else if (clken == 1'b1) z_pipeff_9 <= z_pipenode_9_w;
lpm_add_sub sincos_add
(
.cin((~ sincosbitff[16])),
.cout(),
.dataa(delay_pipe_w),
.datab(post_estimate_w),
.overflow(),
.result(wire_sincos_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
sincos_add.lpm_direction = "ADD",
sincos_add.lpm_representation = "UNSIGNED",
sincos_add.lpm_width = 34,
sincos_add.lpm_type = "lpm_add_sub";
lpm_add_sub x_pipenode_10_add
(
.cin(z_pipeff_9[33]),
.cout(),
.dataa(x_pipeff_9),
.datab(x_subnode_10_w),
.overflow(),
.result(wire_x_pipenode_10_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_pipenode_10_add.lpm_direction = "ADD",
x_pipenode_10_add.lpm_representation = "UNSIGNED",
x_pipenode_10_add.lpm_width = 34,
x_pipenode_10_add.lpm_type = "lpm_add_sub";
lpm_add_sub x_pipenode_11_add
(
.cin(z_pipeff_10[33]),
.cout(),
.dataa(x_pipeff_10),
.datab(x_subnode_11_w),
.overflow(),
.result(wire_x_pipenode_11_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_pipenode_11_add.lpm_direction = "ADD",
x_pipenode_11_add.lpm_representation = "UNSIGNED",
x_pipenode_11_add.lpm_width = 34,
x_pipenode_11_add.lpm_type = "lpm_add_sub";
lpm_add_sub x_pipenode_12_add
(
.cin(z_pipeff_11[33]),
.cout(),
.dataa(x_pipeff_11),
.datab(x_subnode_12_w),
.overflow(),
.result(wire_x_pipenode_12_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_pipenode_12_add.lpm_direction = "ADD",
x_pipenode_12_add.lpm_representation = "UNSIGNED",
x_pipenode_12_add.lpm_width = 34,
x_pipenode_12_add.lpm_type = "lpm_add_sub";
lpm_add_sub x_pipenode_13_add
(
.cin(z_pipeff_12[33]),
.cout(),
.dataa(x_pipeff_12),
.datab(x_subnode_13_w),
.overflow(),
.result(wire_x_pipenode_13_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_pipenode_13_add.lpm_direction = "ADD",
x_pipenode_13_add.lpm_representation = "UNSIGNED",
x_pipenode_13_add.lpm_width = 34,
x_pipenode_13_add.lpm_type = "lpm_add_sub";
lpm_add_sub x_pipenode_2_add
(
.cin(z_pipeff_1[33]),
.cout(),
.dataa(x_pipeff_1),
.datab(x_subnode_2_w),
.overflow(),
.result(wire_x_pipenode_2_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_pipenode_2_add.lpm_direction = "ADD",
x_pipenode_2_add.lpm_representation = "UNSIGNED",
x_pipenode_2_add.lpm_width = 34,
x_pipenode_2_add.lpm_type = "lpm_add_sub";
lpm_add_sub x_pipenode_3_add
(
.cin(z_pipeff_2[33]),
.cout(),
.dataa(x_pipeff_2),
.datab(x_subnode_3_w),
.overflow(),
.result(wire_x_pipenode_3_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_pipenode_3_add.lpm_direction = "ADD",
x_pipenode_3_add.lpm_representation = "UNSIGNED",
x_pipenode_3_add.lpm_width = 34,
x_pipenode_3_add.lpm_type = "lpm_add_sub";
lpm_add_sub x_pipenode_4_add
(
.cin(z_pipeff_3[33]),
.cout(),
.dataa(x_pipeff_3),
.datab(x_subnode_4_w),
.overflow(),
.result(wire_x_pipenode_4_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_pipenode_4_add.lpm_direction = "ADD",
x_pipenode_4_add.lpm_representation = "UNSIGNED",
x_pipenode_4_add.lpm_width = 34,
x_pipenode_4_add.lpm_type = "lpm_add_sub";
lpm_add_sub x_pipenode_5_add
(
.cin(z_pipeff_4[33]),
.cout(),
.dataa(x_pipeff_4),
.datab(x_subnode_5_w),
.overflow(),
.result(wire_x_pipenode_5_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_pipenode_5_add.lpm_direction = "ADD",
x_pipenode_5_add.lpm_representation = "UNSIGNED",
x_pipenode_5_add.lpm_width = 34,
x_pipenode_5_add.lpm_type = "lpm_add_sub";
lpm_add_sub x_pipenode_6_add
(
.cin(z_pipeff_5[33]),
.cout(),
.dataa(x_pipeff_5),
.datab(x_subnode_6_w),
.overflow(),
.result(wire_x_pipenode_6_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_pipenode_6_add.lpm_direction = "ADD",
x_pipenode_6_add.lpm_representation = "UNSIGNED",
x_pipenode_6_add.lpm_width = 34,
x_pipenode_6_add.lpm_type = "lpm_add_sub";
lpm_add_sub x_pipenode_7_add
(
.cin(z_pipeff_6[33]),
.cout(),
.dataa(x_pipeff_6),
.datab(x_subnode_7_w),
.overflow(),
.result(wire_x_pipenode_7_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_pipenode_7_add.lpm_direction = "ADD",
x_pipenode_7_add.lpm_representation = "UNSIGNED",
x_pipenode_7_add.lpm_width = 34,
x_pipenode_7_add.lpm_type = "lpm_add_sub";
lpm_add_sub x_pipenode_8_add
(
.cin(z_pipeff_7[33]),
.cout(),
.dataa(x_pipeff_7),
.datab(x_subnode_8_w),
.overflow(),
.result(wire_x_pipenode_8_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_pipenode_8_add.lpm_direction = "ADD",
x_pipenode_8_add.lpm_representation = "UNSIGNED",
x_pipenode_8_add.lpm_width = 34,
x_pipenode_8_add.lpm_type = "lpm_add_sub";
lpm_add_sub x_pipenode_9_add
(
.cin(z_pipeff_8[33]),
.cout(),
.dataa(x_pipeff_8),
.datab(x_subnode_9_w),
.overflow(),
.result(wire_x_pipenode_9_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_pipenode_9_add.lpm_direction = "ADD",
x_pipenode_9_add.lpm_representation = "UNSIGNED",
x_pipenode_9_add.lpm_width = 34,
x_pipenode_9_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipeff1_add
(
.cout(),
.dataa(y_pipeff_0),
.datab(y_subnode_1_w),
.overflow(),
.result(wire_y_pipeff1_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipeff1_add.lpm_direction = "ADD",
y_pipeff1_add.lpm_representation = "UNSIGNED",
y_pipeff1_add.lpm_width = 34,
y_pipeff1_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipenode_10_add
(
.cin(z_pipeff_9[33]),
.cout(),
.dataa(y_pipeff_9),
.datab(y_subnode_10_w),
.overflow(),
.result(wire_y_pipenode_10_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipenode_10_add.lpm_direction = "ADD",
y_pipenode_10_add.lpm_representation = "UNSIGNED",
y_pipenode_10_add.lpm_width = 34,
y_pipenode_10_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipenode_11_add
(
.cin(z_pipeff_10[33]),
.cout(),
.dataa(y_pipeff_10),
.datab(y_subnode_11_w),
.overflow(),
.result(wire_y_pipenode_11_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipenode_11_add.lpm_direction = "ADD",
y_pipenode_11_add.lpm_representation = "UNSIGNED",
y_pipenode_11_add.lpm_width = 34,
y_pipenode_11_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipenode_12_add
(
.cin(z_pipeff_11[33]),
.cout(),
.dataa(y_pipeff_11),
.datab(y_subnode_12_w),
.overflow(),
.result(wire_y_pipenode_12_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipenode_12_add.lpm_direction = "ADD",
y_pipenode_12_add.lpm_representation = "UNSIGNED",
y_pipenode_12_add.lpm_width = 34,
y_pipenode_12_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipenode_13_add
(
.cin(z_pipeff_12[33]),
.cout(),
.dataa(y_pipeff_12),
.datab(y_subnode_13_w),
.overflow(),
.result(wire_y_pipenode_13_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipenode_13_add.lpm_direction = "ADD",
y_pipenode_13_add.lpm_representation = "UNSIGNED",
y_pipenode_13_add.lpm_width = 34,
y_pipenode_13_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipenode_2_add
(
.cin(z_pipeff_1[33]),
.cout(),
.dataa(y_pipeff_1),
.datab(y_subnode_2_w),
.overflow(),
.result(wire_y_pipenode_2_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipenode_2_add.lpm_direction = "ADD",
y_pipenode_2_add.lpm_representation = "UNSIGNED",
y_pipenode_2_add.lpm_width = 34,
y_pipenode_2_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipenode_3_add
(
.cin(z_pipeff_2[33]),
.cout(),
.dataa(y_pipeff_2),
.datab(y_subnode_3_w),
.overflow(),
.result(wire_y_pipenode_3_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipenode_3_add.lpm_direction = "ADD",
y_pipenode_3_add.lpm_representation = "UNSIGNED",
y_pipenode_3_add.lpm_width = 34,
y_pipenode_3_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipenode_4_add
(
.cin(z_pipeff_3[33]),
.cout(),
.dataa(y_pipeff_3),
.datab(y_subnode_4_w),
.overflow(),
.result(wire_y_pipenode_4_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipenode_4_add.lpm_direction = "ADD",
y_pipenode_4_add.lpm_representation = "UNSIGNED",
y_pipenode_4_add.lpm_width = 34,
y_pipenode_4_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipenode_5_add
(
.cin(z_pipeff_4[33]),
.cout(),
.dataa(y_pipeff_4),
.datab(y_subnode_5_w),
.overflow(),
.result(wire_y_pipenode_5_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipenode_5_add.lpm_direction = "ADD",
y_pipenode_5_add.lpm_representation = "UNSIGNED",
y_pipenode_5_add.lpm_width = 34,
y_pipenode_5_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipenode_6_add
(
.cin(z_pipeff_5[33]),
.cout(),
.dataa(y_pipeff_5),
.datab(y_subnode_6_w),
.overflow(),
.result(wire_y_pipenode_6_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipenode_6_add.lpm_direction = "ADD",
y_pipenode_6_add.lpm_representation = "UNSIGNED",
y_pipenode_6_add.lpm_width = 34,
y_pipenode_6_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipenode_7_add
(
.cin(z_pipeff_6[33]),
.cout(),
.dataa(y_pipeff_6),
.datab(y_subnode_7_w),
.overflow(),
.result(wire_y_pipenode_7_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipenode_7_add.lpm_direction = "ADD",
y_pipenode_7_add.lpm_representation = "UNSIGNED",
y_pipenode_7_add.lpm_width = 34,
y_pipenode_7_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipenode_8_add
(
.cin(z_pipeff_7[33]),
.cout(),
.dataa(y_pipeff_7),
.datab(y_subnode_8_w),
.overflow(),
.result(wire_y_pipenode_8_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipenode_8_add.lpm_direction = "ADD",
y_pipenode_8_add.lpm_representation = "UNSIGNED",
y_pipenode_8_add.lpm_width = 34,
y_pipenode_8_add.lpm_type = "lpm_add_sub";
lpm_add_sub y_pipenode_9_add
(
.cin(z_pipeff_8[33]),
.cout(),
.dataa(y_pipeff_8),
.datab(y_subnode_9_w),
.overflow(),
.result(wire_y_pipenode_9_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
y_pipenode_9_add.lpm_direction = "ADD",
y_pipenode_9_add.lpm_representation = "UNSIGNED",
y_pipenode_9_add.lpm_width = 34,
y_pipenode_9_add.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipeff1_sub
(
.cout(),
.dataa(z_pipeff_0),
.datab(atannode_0_w),
.overflow(),
.result(wire_z_pipeff1_sub_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipeff1_sub.lpm_direction = "SUB",
z_pipeff1_sub.lpm_representation = "UNSIGNED",
z_pipeff1_sub.lpm_width = 34,
z_pipeff1_sub.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipenode_10_add
(
.cin(z_pipeff_9[33]),
.cout(),
.dataa(z_pipeff_9),
.datab(z_subnode_10_w),
.overflow(),
.result(wire_z_pipenode_10_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipenode_10_add.lpm_direction = "ADD",
z_pipenode_10_add.lpm_representation = "UNSIGNED",
z_pipenode_10_add.lpm_width = 34,
z_pipenode_10_add.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipenode_11_add
(
.cin(z_pipeff_10[33]),
.cout(),
.dataa(z_pipeff_10),
.datab(z_subnode_11_w),
.overflow(),
.result(wire_z_pipenode_11_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipenode_11_add.lpm_direction = "ADD",
z_pipenode_11_add.lpm_representation = "UNSIGNED",
z_pipenode_11_add.lpm_width = 34,
z_pipenode_11_add.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipenode_12_add
(
.cin(z_pipeff_11[33]),
.cout(),
.dataa(z_pipeff_11),
.datab(z_subnode_12_w),
.overflow(),
.result(wire_z_pipenode_12_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipenode_12_add.lpm_direction = "ADD",
z_pipenode_12_add.lpm_representation = "UNSIGNED",
z_pipenode_12_add.lpm_width = 34,
z_pipenode_12_add.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipenode_13_add
(
.cin(z_pipeff_12[33]),
.cout(),
.dataa(z_pipeff_12),
.datab(z_subnode_13_w),
.overflow(),
.result(wire_z_pipenode_13_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipenode_13_add.lpm_direction = "ADD",
z_pipenode_13_add.lpm_representation = "UNSIGNED",
z_pipenode_13_add.lpm_width = 34,
z_pipenode_13_add.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipenode_2_add
(
.cin(z_pipeff_1[33]),
.cout(),
.dataa(z_pipeff_1),
.datab(z_subnode_2_w),
.overflow(),
.result(wire_z_pipenode_2_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipenode_2_add.lpm_direction = "ADD",
z_pipenode_2_add.lpm_representation = "UNSIGNED",
z_pipenode_2_add.lpm_width = 34,
z_pipenode_2_add.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipenode_3_add
(
.cin(z_pipeff_2[33]),
.cout(),
.dataa(z_pipeff_2),
.datab(z_subnode_3_w),
.overflow(),
.result(wire_z_pipenode_3_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipenode_3_add.lpm_direction = "ADD",
z_pipenode_3_add.lpm_representation = "UNSIGNED",
z_pipenode_3_add.lpm_width = 34,
z_pipenode_3_add.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipenode_4_add
(
.cin(z_pipeff_3[33]),
.cout(),
.dataa(z_pipeff_3),
.datab(z_subnode_4_w),
.overflow(),
.result(wire_z_pipenode_4_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipenode_4_add.lpm_direction = "ADD",
z_pipenode_4_add.lpm_representation = "UNSIGNED",
z_pipenode_4_add.lpm_width = 34,
z_pipenode_4_add.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipenode_5_add
(
.cin(z_pipeff_4[33]),
.cout(),
.dataa(z_pipeff_4),
.datab(z_subnode_5_w),
.overflow(),
.result(wire_z_pipenode_5_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipenode_5_add.lpm_direction = "ADD",
z_pipenode_5_add.lpm_representation = "UNSIGNED",
z_pipenode_5_add.lpm_width = 34,
z_pipenode_5_add.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipenode_6_add
(
.cin(z_pipeff_5[33]),
.cout(),
.dataa(z_pipeff_5),
.datab(z_subnode_6_w),
.overflow(),
.result(wire_z_pipenode_6_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipenode_6_add.lpm_direction = "ADD",
z_pipenode_6_add.lpm_representation = "UNSIGNED",
z_pipenode_6_add.lpm_width = 34,
z_pipenode_6_add.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipenode_7_add
(
.cin(z_pipeff_6[33]),
.cout(),
.dataa(z_pipeff_6),
.datab(z_subnode_7_w),
.overflow(),
.result(wire_z_pipenode_7_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipenode_7_add.lpm_direction = "ADD",
z_pipenode_7_add.lpm_representation = "UNSIGNED",
z_pipenode_7_add.lpm_width = 34,
z_pipenode_7_add.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipenode_8_add
(
.cin(z_pipeff_7[33]),
.cout(),
.dataa(z_pipeff_7),
.datab(z_subnode_8_w),
.overflow(),
.result(wire_z_pipenode_8_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipenode_8_add.lpm_direction = "ADD",
z_pipenode_8_add.lpm_representation = "UNSIGNED",
z_pipenode_8_add.lpm_width = 34,
z_pipenode_8_add.lpm_type = "lpm_add_sub";
lpm_add_sub z_pipenode_9_add
(
.cin(z_pipeff_8[33]),
.cout(),
.dataa(z_pipeff_8),
.datab(z_subnode_9_w),
.overflow(),
.result(wire_z_pipenode_9_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
z_pipenode_9_add.lpm_direction = "ADD",
z_pipenode_9_add.lpm_representation = "UNSIGNED",
z_pipenode_9_add.lpm_width = 34,
z_pipenode_9_add.lpm_type = "lpm_add_sub";
lpm_mult cmx
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa(multiplier_input_w),
.datab(z_pipeff_13),
.result(wire_cmx_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmx.lpm_pipeline = 3,
cmx.lpm_representation = "SIGNED",
cmx.lpm_widtha = 34,
cmx.lpm_widthb = 34,
cmx.lpm_widthp = 68,
cmx.lpm_type = "lpm_mult";
assign
atannode_0_w = wire_cata_0_cordic_atan_arctan,
atannode_10_w = wire_cata_10_cordic_atan_arctan,
atannode_11_w = wire_cata_11_cordic_atan_arctan,
atannode_12_w = wire_cata_12_cordic_atan_arctan,
atannode_1_w = wire_cata_1_cordic_atan_arctan,
atannode_2_w = wire_cata_2_cordic_atan_arctan,
atannode_3_w = wire_cata_3_cordic_atan_arctan,
atannode_4_w = wire_cata_4_cordic_atan_arctan,
atannode_5_w = wire_cata_5_cordic_atan_arctan,
atannode_6_w = wire_cata_6_cordic_atan_arctan,
atannode_7_w = wire_cata_7_cordic_atan_arctan,
atannode_8_w = wire_cata_8_cordic_atan_arctan,
atannode_9_w = wire_cata_9_cordic_atan_arctan,
delay_input_w = ((x_pipeff_13 & {34{(~ sincosbitff[13])}}) | (y_pipeff_13 & {34{sincosbitff[13]}})),
delay_pipe_w = cdaff_2,
estimate_w = {((pre_estimate_w[33] & (~ indexbitff[16])) | (pre_estimate_w[33] & indexbitff[16])), ((pre_estimate_w[32] & (~ indexbitff[16])) | (pre_estimate_w[33] & indexbitff[16])), ((pre_estimate_w[31] & (~ indexbitff[16])) | (pre_estimate_w[33] & indexbitff[16])), ((pre_estimate_w[30] & (~ indexbitff[16])) | (pre_estimate_w[32] & indexbitff[16])), ((pre_estimate_w[29] & (~ indexbitff[16])) | (pre_estimate_w[31] & indexbitff[16])), ((pre_estimate_w[28] & (~ indexbitff[16])) | (pre_estimate_w[30] & indexbitff[16])), ((pre_estimate_w[27] & (~ indexbitff[16])) | (pre_estimate_w[29] & indexbitff[16])), ((pre_estimate_w[26] & (~ indexbitff[16])) | (pre_estimate_w[28] & indexbitff[16])), ((pre_estimate_w[25] & (~ indexbitff[16])) | (pre_estimate_w[27] & indexbitff[16])), ((pre_estimate_w[24] & (~ indexbitff[16])) | (pre_estimate_w[26] & indexbitff[16])), ((pre_estimate_w[23] & (~ indexbitff[16])) | (pre_estimate_w[25] & indexbitff[16])), ((pre_estimate_w[22] & (~ indexbitff[16])) | (pre_estimate_w[24] & indexbitff[16])), ((pre_estimate_w[21] & (~ indexbitff[16])) | (pre_estimate_w[23] & indexbitff[16])), ((pre_estimate_w[20] & (~ indexbitff[16])) | (pre_estimate_w[22] & indexbitff[16])), ((pre_estimate_w[19] & (~ indexbitff[16])) | (pre_estimate_w[21] & indexbitff[16])), ((pre_estimate_w[18] & (~ indexbitff[16])) | (pre_estimate_w[20] & indexbitff[16])), ((pre_estimate_w[17] & (~ indexbitff[16])) | (pre_estimate_w[19] & indexbitff[16])), ((pre_estimate_w[16] & (~ indexbitff[16])) | (pre_estimate_w[18] & indexbitff[16])), ((pre_estimate_w[15] & (~ indexbitff[16])) | (pre_estimate_w[17] & indexbitff[16])), ((pre_estimate_w[14] & (~ indexbitff[16])) | (pre_estimate_w[16] & indexbitff[16])), ((pre_estimate_w[13] & (~ indexbitff[16])) | (pre_estimate_w[15] & indexbitff[16])), ((pre_estimate_w[12] & (~ indexbitff[16])) | (pre_estimate_w[14] & indexbitff[16])), ((pre_estimate_w[11] & (~ indexbitff[16])) | (pre_estimate_w[13] & indexbitff[16])), ((pre_estimate_w[10] & (~ indexbitff[16])) | (pre_estimate_w[12] & indexbitff[16]
)), ((pre_estimate_w[9] & (~ indexbitff[16])) | (pre_estimate_w[11] & indexbitff[16])), ((pre_estimate_w[8] & (~ indexbitff[16])) | (pre_estimate_w[10] & indexbitff[16])), ((pre_estimate_w[7] & (~ indexbitff[16])) | (pre_estimate_w[9] & indexbitff[16])), ((pre_estimate_w[6] & (~ indexbitff[16])) | (pre_estimate_w[8] & indexbitff[16])), ((pre_estimate_w[5] & (~ indexbitff[16])) | (pre_estimate_w[7] & indexbitff[16])), ((pre_estimate_w[4] & (~ indexbitff[16])) | (pre_estimate_w[6] & indexbitff[16])), ((pre_estimate_w[3] & (~ indexbitff[16])) | (pre_estimate_w[5] & indexbitff[16])), ((pre_estimate_w[2] & (~ indexbitff[16])) | (pre_estimate_w[4] & indexbitff[16])), ((pre_estimate_w[1] & (~ indexbitff[16])) | (pre_estimate_w[3] & indexbitff[16])), ((pre_estimate_w[0] & (~ indexbitff[16])) | (pre_estimate_w[2] & indexbitff[16]))},
indexpointnum_w = {4{1'b0}},
multiplier_input_w = ((x_pipeff_13 & {34{sincosbitff[13]}}) | (y_pipeff_13 & {34{(~ sincosbitff[13])}})),
multipliernode_w = wire_cmx_result,
post_estimate_w = (estimate_w ^ {34{(~ sincosbitff[16])}}),
pre_estimate_w = multipliernode_w[65:32],
radians_load_node_w = {((radians[33] & (~ indexbit)) | (radians[31] & indexbit)), ((radians[32] & (~ indexbit)) | (radians[30] & indexbit)), ((radians[31] & (~ indexbit)) | (radians[29] & indexbit)), ((radians[30] & (~ indexbit)) | (radians[28] & indexbit)), ((radians[29] & (~ indexbit)) | (radians[27] & indexbit)), ((radians[28] & (~ indexbit)) | (radians[26] & indexbit)), ((radians[27] & (~ indexbit)) | (radians[25] & indexbit)), ((radians[26] & (~ indexbit)) | (radians[24] & indexbit)), ((radians[25] & (~ indexbit)) | (radians[23] & indexbit)), ((radians[24] & (~ indexbit)) | (radians[22] & indexbit)), ((radians[23] & (~ indexbit)) | (radians[21] & indexbit)), ((radians[22] & (~ indexbit)) | (radians[20] & indexbit)), ((radians[21] & (~ indexbit)) | (radians[19] & indexbit)), ((radians[20] & (~ indexbit)) | (radians[18] & indexbit)), ((radians[19] & (~ indexbit)) | (radians[17] & indexbit)), ((radians[18] & (~ indexbit)) | (radians[16] & indexbit)), ((radians[17] & (~ indexbit)) | (radians[15] & indexbit)), ((radians[16] & (~ indexbit)) | (radians[14] & indexbit)), ((radians[15] & (~ indexbit)) | (radians[13] & indexbit)), ((radians[14] & (~ indexbit)) | (radians[12] & indexbit)), ((radians[13] & (~ indexbit)) | (radians[11] & indexbit)), ((radians[12] & (~ indexbit)) | (radians[10] & indexbit)), ((radians[11] & (~ indexbit)) | (radians[9] & indexbit)), ((radians[10] & (~ indexbit)) | (radians[8] & indexbit)), ((radians[9] & (~ indexbit)) | (radians[7] & indexbit)), ((radians[8] & (~ indexbit)) | (radians[6] & indexbit)), ((radians[7] & (~ indexbit)) | (radians[5] & indexbit)), ((radians[6] & (~ indexbit)) | (radians[4] & indexbit)), ((radians[5] & (~ indexbit)) | (radians[3] & indexbit)), ((radians[4] & (~ indexbit)) | (radians[2] & indexbit)), ((radians[3] & (~ indexbit)) | (radians[1] & indexbit)), ((radians[2] & (~ indexbit)) | (radians[0] & indexbit)), (radians[1] & (~ indexbit)), (radians[0] & (~ indexbit))},
sincos = sincosff,
startindex_w = (indexpointnum_w & {4{indexbit}}),
x_pipenode_10_w = wire_x_pipenode_10_add_result,
x_pipenode_11_w = wire_x_pipenode_11_add_result,
x_pipenode_12_w = wire_x_pipenode_12_add_result,
x_pipenode_13_w = wire_x_pipenode_13_add_result,
x_pipenode_2_w = wire_x_pipenode_2_add_result,
x_pipenode_3_w = wire_x_pipenode_3_add_result,
x_pipenode_4_w = wire_x_pipenode_4_add_result,
x_pipenode_5_w = wire_x_pipenode_5_add_result,
x_pipenode_6_w = wire_x_pipenode_6_add_result,
x_pipenode_7_w = wire_x_pipenode_7_add_result,
x_pipenode_8_w = wire_x_pipenode_8_add_result,
x_pipenode_9_w = wire_x_pipenode_9_add_result,
x_prenode_10_w = {((x_prenodeone_10_w[33] & (~ indexbitff[9])) | (x_prenodetwo_10_w[33] & indexbitff[9])), ((x_prenodeone_10_w[32] & (~ indexbitff[9])) | (x_prenodetwo_10_w[32] & indexbitff[9])), ((x_prenodeone_10_w[31] & (~ indexbitff[9])) | (x_prenodetwo_10_w[31] & indexbitff[9])), ((x_prenodeone_10_w[30] & (~ indexbitff[9])) | (x_prenodetwo_10_w[30] & indexbitff[9])), ((x_prenodeone_10_w[29] & (~ indexbitff[9])) | (x_prenodetwo_10_w[29] & indexbitff[9])), ((x_prenodeone_10_w[28] & (~ indexbitff[9])) | (x_prenodetwo_10_w[28] & indexbitff[9])), ((x_prenodeone_10_w[27] & (~ indexbitff[9])) | (x_prenodetwo_10_w[27] & indexbitff[9])), ((x_prenodeone_10_w[26] & (~ indexbitff[9])) | (x_prenodetwo_10_w[26] & indexbitff[9])), ((x_prenodeone_10_w[25] & (~ indexbitff[9])) | (x_prenodetwo_10_w[25] & indexbitff[9])), ((x_prenodeone_10_w[24] & (~ indexbitff[9])) | (x_prenodetwo_10_w[24] & indexbitff[9])), ((x_prenodeone_10_w[23] & (~ indexbitff[9])) | (x_prenodetwo_10_w[23] & indexbitff[9])), ((x_prenodeone_10_w[22] & (~ indexbitff[9])) | (x_prenodetwo_10_w[22] & indexbitff[9])), ((x_prenodeone_10_w[21] & (~ indexbitff[9])) | (x_prenodetwo_10_w[21] & indexbitff[9])), ((x_prenodeone_10_w[20] & (~ indexbitff[9])) | (x_prenodetwo_10_w[20] & indexbitff[9])), ((x_prenodeone_10_w[19] & (~ indexbitff[9])) | (x_prenodetwo_10_w[19] & indexbitff[9])), ((x_prenodeone_10_w[18] & (~ indexbitff[9])) | (x_prenodetwo_10_w[18] & indexbitff[9])), ((x_prenodeone_10_w[17] & (~ indexbitff[9])) | (x_prenodetwo_10_w[17] & indexbitff[9])), ((x_prenodeone_10_w[16] & (~ indexbitff[9])) | (x_prenodetwo_10_w[16] & indexbitff[9])), ((x_prenodeone_10_w[15] & (~ indexbitff[9])) | (x_prenodetwo_10_w[15] & indexbitff[9])), ((x_prenodeone_10_w[14] & (~ indexbitff[9])) | (x_prenodetwo_10_w[14] & indexbitff[9])), ((x_prenodeone_10_w[13] & (~ indexbitff[9])) | (x_prenodetwo_10_w[13] & indexbitff[9])), ((x_prenodeone_10_w[12] & (~ indexbitff[9])) | (x_prenodetwo_10_w[12] & indexbitff[9])), ((x_prenodeone_10_w[11] & (~ indexbitff[9])) | (x_prenodetwo_10_w[11]
& indexbitff[9])), ((x_prenodeone_10_w[10] & (~ indexbitff[9])) | (x_prenodetwo_10_w[10] & indexbitff[9])), ((x_prenodeone_10_w[9] & (~ indexbitff[9])) | (x_prenodetwo_10_w[9] & indexbitff[9])), ((x_prenodeone_10_w[8] & (~ indexbitff[9])) | (x_prenodetwo_10_w[8] & indexbitff[9])), ((x_prenodeone_10_w[7] & (~ indexbitff[9])) | (x_prenodetwo_10_w[7] & indexbitff[9])), ((x_prenodeone_10_w[6] & (~ indexbitff[9])) | (x_prenodetwo_10_w[6] & indexbitff[9])), ((x_prenodeone_10_w[5] & (~ indexbitff[9])) | (x_prenodetwo_10_w[5] & indexbitff[9])), ((x_prenodeone_10_w[4] & (~ indexbitff[9])) | (x_prenodetwo_10_w[4] & indexbitff[9])), ((x_prenodeone_10_w[3] & (~ indexbitff[9])) | (x_prenodetwo_10_w[3] & indexbitff[9])), ((x_prenodeone_10_w[2] & (~ indexbitff[9])) | (x_prenodetwo_10_w[2] & indexbitff[9])), ((x_prenodeone_10_w[1] & (~ indexbitff[9])) | (x_prenodetwo_10_w[1] & indexbitff[9])), ((x_prenodeone_10_w[0] & (~ indexbitff[9])) | (x_prenodetwo_10_w[0] & indexbitff[9]))},
x_prenode_11_w = {((x_prenodeone_11_w[33] & (~ indexbitff[10])) | (x_prenodetwo_11_w[33] & indexbitff[10])), ((x_prenodeone_11_w[32] & (~ indexbitff[10])) | (x_prenodetwo_11_w[32] & indexbitff[10])), ((x_prenodeone_11_w[31] & (~ indexbitff[10])) | (x_prenodetwo_11_w[31] & indexbitff[10])), ((x_prenodeone_11_w[30] & (~ indexbitff[10])) | (x_prenodetwo_11_w[30] & indexbitff[10])), ((x_prenodeone_11_w[29] & (~ indexbitff[10])) | (x_prenodetwo_11_w[29] & indexbitff[10])), ((x_prenodeone_11_w[28] & (~ indexbitff[10])) | (x_prenodetwo_11_w[28] & indexbitff[10])), ((x_prenodeone_11_w[27] & (~ indexbitff[10])) | (x_prenodetwo_11_w[27] & indexbitff[10])), ((x_prenodeone_11_w[26] & (~ indexbitff[10])) | (x_prenodetwo_11_w[26] & indexbitff[10])), ((x_prenodeone_11_w[25] & (~ indexbitff[10])) | (x_prenodetwo_11_w[25] & indexbitff[10])), ((x_prenodeone_11_w[24] & (~ indexbitff[10])) | (x_prenodetwo_11_w[24] & indexbitff[10])), ((x_prenodeone_11_w[23] & (~ indexbitff[10])) | (x_prenodetwo_11_w[23] & indexbitff[10])), ((x_prenodeone_11_w[22] & (~ indexbitff[10])) | (x_prenodetwo_11_w[22] & indexbitff[10])), ((x_prenodeone_11_w[21] & (~ indexbitff[10])) | (x_prenodetwo_11_w[21] & indexbitff[10])), ((x_prenodeone_11_w[20] & (~ indexbitff[10])) | (x_prenodetwo_11_w[20] & indexbitff[10])), ((x_prenodeone_11_w[19] & (~ indexbitff[10])) | (x_prenodetwo_11_w[19] & indexbitff[10])), ((x_prenodeone_11_w[18] & (~ indexbitff[10])) | (x_prenodetwo_11_w[18] & indexbitff[10])), ((x_prenodeone_11_w[17] & (~ indexbitff[10])) | (x_prenodetwo_11_w[17] & indexbitff[10])), ((x_prenodeone_11_w[16] & (~ indexbitff[10])) | (x_prenodetwo_11_w[16] & indexbitff[10])), ((x_prenodeone_11_w[15] & (~ indexbitff[10])) | (x_prenodetwo_11_w[15] & indexbitff[10])), ((x_prenodeone_11_w[14] & (~ indexbitff[10])) | (x_prenodetwo_11_w[14] & indexbitff[10])), ((x_prenodeone_11_w[13] & (~ indexbitff[10])) | (x_prenodetwo_11_w[13] & indexbitff[10])), ((x_prenodeone_11_w[12] & (~ indexbitff[10])) | (x_prenodetwo_11_w[12] & indexbitff[10])), ((x_prenodeone_11_w[11] &
(~ indexbitff[10])) | (x_prenodetwo_11_w[11] & indexbitff[10])), ((x_prenodeone_11_w[10] & (~ indexbitff[10])) | (x_prenodetwo_11_w[10] & indexbitff[10])), ((x_prenodeone_11_w[9] & (~ indexbitff[10])) | (x_prenodetwo_11_w[9] & indexbitff[10])), ((x_prenodeone_11_w[8] & (~ indexbitff[10])) | (x_prenodetwo_11_w[8] & indexbitff[10])), ((x_prenodeone_11_w[7] & (~ indexbitff[10])) | (x_prenodetwo_11_w[7] & indexbitff[10])), ((x_prenodeone_11_w[6] & (~ indexbitff[10])) | (x_prenodetwo_11_w[6] & indexbitff[10])), ((x_prenodeone_11_w[5] & (~ indexbitff[10])) | (x_prenodetwo_11_w[5] & indexbitff[10])), ((x_prenodeone_11_w[4] & (~ indexbitff[10])) | (x_prenodetwo_11_w[4] & indexbitff[10])), ((x_prenodeone_11_w[3] & (~ indexbitff[10])) | (x_prenodetwo_11_w[3] & indexbitff[10])), ((x_prenodeone_11_w[2] & (~ indexbitff[10])) | (x_prenodetwo_11_w[2] & indexbitff[10])), ((x_prenodeone_11_w[1] & (~ indexbitff[10])) | (x_prenodetwo_11_w[1] & indexbitff[10])), ((x_prenodeone_11_w[0] & (~ indexbitff[10])) | (x_prenodetwo_11_w[0] & indexbitff[10]))},
x_prenode_12_w = {((x_prenodeone_12_w[33] & (~ indexbitff[11])) | (x_prenodetwo_12_w[33] & indexbitff[11])), ((x_prenodeone_12_w[32] & (~ indexbitff[11])) | (x_prenodetwo_12_w[32] & indexbitff[11])), ((x_prenodeone_12_w[31] & (~ indexbitff[11])) | (x_prenodetwo_12_w[31] & indexbitff[11])), ((x_prenodeone_12_w[30] & (~ indexbitff[11])) | (x_prenodetwo_12_w[30] & indexbitff[11])), ((x_prenodeone_12_w[29] & (~ indexbitff[11])) | (x_prenodetwo_12_w[29] & indexbitff[11])), ((x_prenodeone_12_w[28] & (~ indexbitff[11])) | (x_prenodetwo_12_w[28] & indexbitff[11])), ((x_prenodeone_12_w[27] & (~ indexbitff[11])) | (x_prenodetwo_12_w[27] & indexbitff[11])), ((x_prenodeone_12_w[26] & (~ indexbitff[11])) | (x_prenodetwo_12_w[26] & indexbitff[11])), ((x_prenodeone_12_w[25] & (~ indexbitff[11])) | (x_prenodetwo_12_w[25] & indexbitff[11])), ((x_prenodeone_12_w[24] & (~ indexbitff[11])) | (x_prenodetwo_12_w[24] & indexbitff[11])), ((x_prenodeone_12_w[23] & (~ indexbitff[11])) | (x_prenodetwo_12_w[23] & indexbitff[11])), ((x_prenodeone_12_w[22] & (~ indexbitff[11])) | (x_prenodetwo_12_w[22] & indexbitff[11])), ((x_prenodeone_12_w[21] & (~ indexbitff[11])) | (x_prenodetwo_12_w[21] & indexbitff[11])), ((x_prenodeone_12_w[20] & (~ indexbitff[11])) | (x_prenodetwo_12_w[20] & indexbitff[11])), ((x_prenodeone_12_w[19] & (~ indexbitff[11])) | (x_prenodetwo_12_w[19] & indexbitff[11])), ((x_prenodeone_12_w[18] & (~ indexbitff[11])) | (x_prenodetwo_12_w[18] & indexbitff[11])), ((x_prenodeone_12_w[17] & (~ indexbitff[11])) | (x_prenodetwo_12_w[17] & indexbitff[11])), ((x_prenodeone_12_w[16] & (~ indexbitff[11])) | (x_prenodetwo_12_w[16] & indexbitff[11])), ((x_prenodeone_12_w[15] & (~ indexbitff[11])) | (x_prenodetwo_12_w[15] & indexbitff[11])), ((x_prenodeone_12_w[14] & (~ indexbitff[11])) | (x_prenodetwo_12_w[14] & indexbitff[11])), ((x_prenodeone_12_w[13] & (~ indexbitff[11])) | (x_prenodetwo_12_w[13] & indexbitff[11])), ((x_prenodeone_12_w[12] & (~ indexbitff[11])) | (x_prenodetwo_12_w[12] & indexbitff[11])), ((x_prenodeone_12_w[11] &
(~ indexbitff[11])) | (x_prenodetwo_12_w[11] & indexbitff[11])), ((x_prenodeone_12_w[10] & (~ indexbitff[11])) | (x_prenodetwo_12_w[10] & indexbitff[11])), ((x_prenodeone_12_w[9] & (~ indexbitff[11])) | (x_prenodetwo_12_w[9] & indexbitff[11])), ((x_prenodeone_12_w[8] & (~ indexbitff[11])) | (x_prenodetwo_12_w[8] & indexbitff[11])), ((x_prenodeone_12_w[7] & (~ indexbitff[11])) | (x_prenodetwo_12_w[7] & indexbitff[11])), ((x_prenodeone_12_w[6] & (~ indexbitff[11])) | (x_prenodetwo_12_w[6] & indexbitff[11])), ((x_prenodeone_12_w[5] & (~ indexbitff[11])) | (x_prenodetwo_12_w[5] & indexbitff[11])), ((x_prenodeone_12_w[4] & (~ indexbitff[11])) | (x_prenodetwo_12_w[4] & indexbitff[11])), ((x_prenodeone_12_w[3] & (~ indexbitff[11])) | (x_prenodetwo_12_w[3] & indexbitff[11])), ((x_prenodeone_12_w[2] & (~ indexbitff[11])) | (x_prenodetwo_12_w[2] & indexbitff[11])), ((x_prenodeone_12_w[1] & (~ indexbitff[11])) | (x_prenodetwo_12_w[1] & indexbitff[11])), ((x_prenodeone_12_w[0] & (~ indexbitff[11])) | (x_prenodetwo_12_w[0] & indexbitff[11]))},
x_prenode_13_w = {((x_prenodeone_13_w[33] & (~ indexbitff[12])) | (x_prenodetwo_13_w[33] & indexbitff[12])), ((x_prenodeone_13_w[32] & (~ indexbitff[12])) | (x_prenodetwo_13_w[32] & indexbitff[12])), ((x_prenodeone_13_w[31] & (~ indexbitff[12])) | (x_prenodetwo_13_w[31] & indexbitff[12])), ((x_prenodeone_13_w[30] & (~ indexbitff[12])) | (x_prenodetwo_13_w[30] & indexbitff[12])), ((x_prenodeone_13_w[29] & (~ indexbitff[12])) | (x_prenodetwo_13_w[29] & indexbitff[12])), ((x_prenodeone_13_w[28] & (~ indexbitff[12])) | (x_prenodetwo_13_w[28] & indexbitff[12])), ((x_prenodeone_13_w[27] & (~ indexbitff[12])) | (x_prenodetwo_13_w[27] & indexbitff[12])), ((x_prenodeone_13_w[26] & (~ indexbitff[12])) | (x_prenodetwo_13_w[26] & indexbitff[12])), ((x_prenodeone_13_w[25] & (~ indexbitff[12])) | (x_prenodetwo_13_w[25] & indexbitff[12])), ((x_prenodeone_13_w[24] & (~ indexbitff[12])) | (x_prenodetwo_13_w[24] & indexbitff[12])), ((x_prenodeone_13_w[23] & (~ indexbitff[12])) | (x_prenodetwo_13_w[23] & indexbitff[12])), ((x_prenodeone_13_w[22] & (~ indexbitff[12])) | (x_prenodetwo_13_w[22] & indexbitff[12])), ((x_prenodeone_13_w[21] & (~ indexbitff[12])) | (x_prenodetwo_13_w[21] & indexbitff[12])), ((x_prenodeone_13_w[20] & (~ indexbitff[12])) | (x_prenodetwo_13_w[20] & indexbitff[12])), ((x_prenodeone_13_w[19] & (~ indexbitff[12])) | (x_prenodetwo_13_w[19] & indexbitff[12])), ((x_prenodeone_13_w[18] & (~ indexbitff[12])) | (x_prenodetwo_13_w[18] & indexbitff[12])), ((x_prenodeone_13_w[17] & (~ indexbitff[12])) | (x_prenodetwo_13_w[17] & indexbitff[12])), ((x_prenodeone_13_w[16] & (~ indexbitff[12])) | (x_prenodetwo_13_w[16] & indexbitff[12])), ((x_prenodeone_13_w[15] & (~ indexbitff[12])) | (x_prenodetwo_13_w[15] & indexbitff[12])), ((x_prenodeone_13_w[14] & (~ indexbitff[12])) | (x_prenodetwo_13_w[14] & indexbitff[12])), ((x_prenodeone_13_w[13] & (~ indexbitff[12])) | (x_prenodetwo_13_w[13] & indexbitff[12])), ((x_prenodeone_13_w[12] & (~ indexbitff[12])) | (x_prenodetwo_13_w[12] & indexbitff[12])), ((x_prenodeone_13_w[11] &
(~ indexbitff[12])) | (x_prenodetwo_13_w[11] & indexbitff[12])), ((x_prenodeone_13_w[10] & (~ indexbitff[12])) | (x_prenodetwo_13_w[10] & indexbitff[12])), ((x_prenodeone_13_w[9] & (~ indexbitff[12])) | (x_prenodetwo_13_w[9] & indexbitff[12])), ((x_prenodeone_13_w[8] & (~ indexbitff[12])) | (x_prenodetwo_13_w[8] & indexbitff[12])), ((x_prenodeone_13_w[7] & (~ indexbitff[12])) | (x_prenodetwo_13_w[7] & indexbitff[12])), ((x_prenodeone_13_w[6] & (~ indexbitff[12])) | (x_prenodetwo_13_w[6] & indexbitff[12])), ((x_prenodeone_13_w[5] & (~ indexbitff[12])) | (x_prenodetwo_13_w[5] & indexbitff[12])), ((x_prenodeone_13_w[4] & (~ indexbitff[12])) | (x_prenodetwo_13_w[4] & indexbitff[12])), ((x_prenodeone_13_w[3] & (~ indexbitff[12])) | (x_prenodetwo_13_w[3] & indexbitff[12])), ((x_prenodeone_13_w[2] & (~ indexbitff[12])) | (x_prenodetwo_13_w[2] & indexbitff[12])), ((x_prenodeone_13_w[1] & (~ indexbitff[12])) | (x_prenodetwo_13_w[1] & indexbitff[12])), ((x_prenodeone_13_w[0] & (~ indexbitff[12])) | (x_prenodetwo_13_w[0] & indexbitff[12]))},
x_prenode_2_w = {((x_prenodeone_2_w[33] & (~ indexbitff[1])) | (x_prenodetwo_2_w[33] & indexbitff[1])), ((x_prenodeone_2_w[32] & (~ indexbitff[1])) | (x_prenodetwo_2_w[32] & indexbitff[1])), ((x_prenodeone_2_w[31] & (~ indexbitff[1])) | (x_prenodetwo_2_w[31] & indexbitff[1])), ((x_prenodeone_2_w[30] & (~ indexbitff[1])) | (x_prenodetwo_2_w[30] & indexbitff[1])), ((x_prenodeone_2_w[29] & (~ indexbitff[1])) | (x_prenodetwo_2_w[29] & indexbitff[1])), ((x_prenodeone_2_w[28] & (~ indexbitff[1])) | (x_prenodetwo_2_w[28] & indexbitff[1])), ((x_prenodeone_2_w[27] & (~ indexbitff[1])) | (x_prenodetwo_2_w[27] & indexbitff[1])), ((x_prenodeone_2_w[26] & (~ indexbitff[1])) | (x_prenodetwo_2_w[26] & indexbitff[1])), ((x_prenodeone_2_w[25] & (~ indexbitff[1])) | (x_prenodetwo_2_w[25] & indexbitff[1])), ((x_prenodeone_2_w[24] & (~ indexbitff[1])) | (x_prenodetwo_2_w[24] & indexbitff[1])), ((x_prenodeone_2_w[23] & (~ indexbitff[1])) | (x_prenodetwo_2_w[23] & indexbitff[1])), ((x_prenodeone_2_w[22] & (~ indexbitff[1])) | (x_prenodetwo_2_w[22] & indexbitff[1])), ((x_prenodeone_2_w[21] & (~ indexbitff[1])) | (x_prenodetwo_2_w[21] & indexbitff[1])), ((x_prenodeone_2_w[20] & (~ indexbitff[1])) | (x_prenodetwo_2_w[20] & indexbitff[1])), ((x_prenodeone_2_w[19] & (~ indexbitff[1])) | (x_prenodetwo_2_w[19] & indexbitff[1])), ((x_prenodeone_2_w[18] & (~ indexbitff[1])) | (x_prenodetwo_2_w[18] & indexbitff[1])), ((x_prenodeone_2_w[17] & (~ indexbitff[1])) | (x_prenodetwo_2_w[17] & indexbitff[1])), ((x_prenodeone_2_w[16] & (~ indexbitff[1])) | (x_prenodetwo_2_w[16] & indexbitff[1])), ((x_prenodeone_2_w[15] & (~ indexbitff[1])) | (x_prenodetwo_2_w[15] & indexbitff[1])), ((x_prenodeone_2_w[14] & (~ indexbitff[1])) | (x_prenodetwo_2_w[14] & indexbitff[1])), ((x_prenodeone_2_w[13] & (~ indexbitff[1])) | (x_prenodetwo_2_w[13] & indexbitff[1])), ((x_prenodeone_2_w[12] & (~ indexbitff[1])) | (x_prenodetwo_2_w[12] & indexbitff[1])), ((x_prenodeone_2_w[11] & (~ indexbitff[1])) | (x_prenodetwo_2_w[11] & indexbitff[1])), ((x_prenodeone_2_w[10] & (~ indexbitff[1]
)) | (x_prenodetwo_2_w[10] & indexbitff[1])), ((x_prenodeone_2_w[9] & (~ indexbitff[1])) | (x_prenodetwo_2_w[9] & indexbitff[1])), ((x_prenodeone_2_w[8] & (~ indexbitff[1])) | (x_prenodetwo_2_w[8] & indexbitff[1])), ((x_prenodeone_2_w[7] & (~ indexbitff[1])) | (x_prenodetwo_2_w[7] & indexbitff[1])), ((x_prenodeone_2_w[6] & (~ indexbitff[1])) | (x_prenodetwo_2_w[6] & indexbitff[1])), ((x_prenodeone_2_w[5] & (~ indexbitff[1])) | (x_prenodetwo_2_w[5] & indexbitff[1])), ((x_prenodeone_2_w[4] & (~ indexbitff[1])) | (x_prenodetwo_2_w[4] & indexbitff[1])), ((x_prenodeone_2_w[3] & (~ indexbitff[1])) | (x_prenodetwo_2_w[3] & indexbitff[1])), ((x_prenodeone_2_w[2] & (~ indexbitff[1])) | (x_prenodetwo_2_w[2] & indexbitff[1])), ((x_prenodeone_2_w[1] & (~ indexbitff[1])) | (x_prenodetwo_2_w[1] & indexbitff[1])), ((x_prenodeone_2_w[0] & (~ indexbitff[1])) | (x_prenodetwo_2_w[0] & indexbitff[1]))},
x_prenode_3_w = {((x_prenodeone_3_w[33] & (~ indexbitff[2])) | (x_prenodetwo_3_w[33] & indexbitff[2])), ((x_prenodeone_3_w[32] & (~ indexbitff[2])) | (x_prenodetwo_3_w[32] & indexbitff[2])), ((x_prenodeone_3_w[31] & (~ indexbitff[2])) | (x_prenodetwo_3_w[31] & indexbitff[2])), ((x_prenodeone_3_w[30] & (~ indexbitff[2])) | (x_prenodetwo_3_w[30] & indexbitff[2])), ((x_prenodeone_3_w[29] & (~ indexbitff[2])) | (x_prenodetwo_3_w[29] & indexbitff[2])), ((x_prenodeone_3_w[28] & (~ indexbitff[2])) | (x_prenodetwo_3_w[28] & indexbitff[2])), ((x_prenodeone_3_w[27] & (~ indexbitff[2])) | (x_prenodetwo_3_w[27] & indexbitff[2])), ((x_prenodeone_3_w[26] & (~ indexbitff[2])) | (x_prenodetwo_3_w[26] & indexbitff[2])), ((x_prenodeone_3_w[25] & (~ indexbitff[2])) | (x_prenodetwo_3_w[25] & indexbitff[2])), ((x_prenodeone_3_w[24] & (~ indexbitff[2])) | (x_prenodetwo_3_w[24] & indexbitff[2])), ((x_prenodeone_3_w[23] & (~ indexbitff[2])) | (x_prenodetwo_3_w[23] & indexbitff[2])), ((x_prenodeone_3_w[22] & (~ indexbitff[2])) | (x_prenodetwo_3_w[22] & indexbitff[2])), ((x_prenodeone_3_w[21] & (~ indexbitff[2])) | (x_prenodetwo_3_w[21] & indexbitff[2])), ((x_prenodeone_3_w[20] & (~ indexbitff[2])) | (x_prenodetwo_3_w[20] & indexbitff[2])), ((x_prenodeone_3_w[19] & (~ indexbitff[2])) | (x_prenodetwo_3_w[19] & indexbitff[2])), ((x_prenodeone_3_w[18] & (~ indexbitff[2])) | (x_prenodetwo_3_w[18] & indexbitff[2])), ((x_prenodeone_3_w[17] & (~ indexbitff[2])) | (x_prenodetwo_3_w[17] & indexbitff[2])), ((x_prenodeone_3_w[16] & (~ indexbitff[2])) | (x_prenodetwo_3_w[16] & indexbitff[2])), ((x_prenodeone_3_w[15] & (~ indexbitff[2])) | (x_prenodetwo_3_w[15] & indexbitff[2])), ((x_prenodeone_3_w[14] & (~ indexbitff[2])) | (x_prenodetwo_3_w[14] & indexbitff[2])), ((x_prenodeone_3_w[13] & (~ indexbitff[2])) | (x_prenodetwo_3_w[13] & indexbitff[2])), ((x_prenodeone_3_w[12] & (~ indexbitff[2])) | (x_prenodetwo_3_w[12] & indexbitff[2])), ((x_prenodeone_3_w[11] & (~ indexbitff[2])) | (x_prenodetwo_3_w[11] & indexbitff[2])), ((x_prenodeone_3_w[10] & (~ indexbitff[2]
)) | (x_prenodetwo_3_w[10] & indexbitff[2])), ((x_prenodeone_3_w[9] & (~ indexbitff[2])) | (x_prenodetwo_3_w[9] & indexbitff[2])), ((x_prenodeone_3_w[8] & (~ indexbitff[2])) | (x_prenodetwo_3_w[8] & indexbitff[2])), ((x_prenodeone_3_w[7] & (~ indexbitff[2])) | (x_prenodetwo_3_w[7] & indexbitff[2])), ((x_prenodeone_3_w[6] & (~ indexbitff[2])) | (x_prenodetwo_3_w[6] & indexbitff[2])), ((x_prenodeone_3_w[5] & (~ indexbitff[2])) | (x_prenodetwo_3_w[5] & indexbitff[2])), ((x_prenodeone_3_w[4] & (~ indexbitff[2])) | (x_prenodetwo_3_w[4] & indexbitff[2])), ((x_prenodeone_3_w[3] & (~ indexbitff[2])) | (x_prenodetwo_3_w[3] & indexbitff[2])), ((x_prenodeone_3_w[2] & (~ indexbitff[2])) | (x_prenodetwo_3_w[2] & indexbitff[2])), ((x_prenodeone_3_w[1] & (~ indexbitff[2])) | (x_prenodetwo_3_w[1] & indexbitff[2])), ((x_prenodeone_3_w[0] & (~ indexbitff[2])) | (x_prenodetwo_3_w[0] & indexbitff[2]))},
x_prenode_4_w = {((x_prenodeone_4_w[33] & (~ indexbitff[3])) | (x_prenodetwo_4_w[33] & indexbitff[3])), ((x_prenodeone_4_w[32] & (~ indexbitff[3])) | (x_prenodetwo_4_w[32] & indexbitff[3])), ((x_prenodeone_4_w[31] & (~ indexbitff[3])) | (x_prenodetwo_4_w[31] & indexbitff[3])), ((x_prenodeone_4_w[30] & (~ indexbitff[3])) | (x_prenodetwo_4_w[30] & indexbitff[3])), ((x_prenodeone_4_w[29] & (~ indexbitff[3])) | (x_prenodetwo_4_w[29] & indexbitff[3])), ((x_prenodeone_4_w[28] & (~ indexbitff[3])) | (x_prenodetwo_4_w[28] & indexbitff[3])), ((x_prenodeone_4_w[27] & (~ indexbitff[3])) | (x_prenodetwo_4_w[27] & indexbitff[3])), ((x_prenodeone_4_w[26] & (~ indexbitff[3])) | (x_prenodetwo_4_w[26] & indexbitff[3])), ((x_prenodeone_4_w[25] & (~ indexbitff[3])) | (x_prenodetwo_4_w[25] & indexbitff[3])), ((x_prenodeone_4_w[24] & (~ indexbitff[3])) | (x_prenodetwo_4_w[24] & indexbitff[3])), ((x_prenodeone_4_w[23] & (~ indexbitff[3])) | (x_prenodetwo_4_w[23] & indexbitff[3])), ((x_prenodeone_4_w[22] & (~ indexbitff[3])) | (x_prenodetwo_4_w[22] & indexbitff[3])), ((x_prenodeone_4_w[21] & (~ indexbitff[3])) | (x_prenodetwo_4_w[21] & indexbitff[3])), ((x_prenodeone_4_w[20] & (~ indexbitff[3])) | (x_prenodetwo_4_w[20] & indexbitff[3])), ((x_prenodeone_4_w[19] & (~ indexbitff[3])) | (x_prenodetwo_4_w[19] & indexbitff[3])), ((x_prenodeone_4_w[18] & (~ indexbitff[3])) | (x_prenodetwo_4_w[18] & indexbitff[3])), ((x_prenodeone_4_w[17] & (~ indexbitff[3])) | (x_prenodetwo_4_w[17] & indexbitff[3])), ((x_prenodeone_4_w[16] & (~ indexbitff[3])) | (x_prenodetwo_4_w[16] & indexbitff[3])), ((x_prenodeone_4_w[15] & (~ indexbitff[3])) | (x_prenodetwo_4_w[15] & indexbitff[3])), ((x_prenodeone_4_w[14] & (~ indexbitff[3])) | (x_prenodetwo_4_w[14] & indexbitff[3])), ((x_prenodeone_4_w[13] & (~ indexbitff[3])) | (x_prenodetwo_4_w[13] & indexbitff[3])), ((x_prenodeone_4_w[12] & (~ indexbitff[3])) | (x_prenodetwo_4_w[12] & indexbitff[3])), ((x_prenodeone_4_w[11] & (~ indexbitff[3])) | (x_prenodetwo_4_w[11] & indexbitff[3])), ((x_prenodeone_4_w[10] & (~ indexbitff[3]
)) | (x_prenodetwo_4_w[10] & indexbitff[3])), ((x_prenodeone_4_w[9] & (~ indexbitff[3])) | (x_prenodetwo_4_w[9] & indexbitff[3])), ((x_prenodeone_4_w[8] & (~ indexbitff[3])) | (x_prenodetwo_4_w[8] & indexbitff[3])), ((x_prenodeone_4_w[7] & (~ indexbitff[3])) | (x_prenodetwo_4_w[7] & indexbitff[3])), ((x_prenodeone_4_w[6] & (~ indexbitff[3])) | (x_prenodetwo_4_w[6] & indexbitff[3])), ((x_prenodeone_4_w[5] & (~ indexbitff[3])) | (x_prenodetwo_4_w[5] & indexbitff[3])), ((x_prenodeone_4_w[4] & (~ indexbitff[3])) | (x_prenodetwo_4_w[4] & indexbitff[3])), ((x_prenodeone_4_w[3] & (~ indexbitff[3])) | (x_prenodetwo_4_w[3] & indexbitff[3])), ((x_prenodeone_4_w[2] & (~ indexbitff[3])) | (x_prenodetwo_4_w[2] & indexbitff[3])), ((x_prenodeone_4_w[1] & (~ indexbitff[3])) | (x_prenodetwo_4_w[1] & indexbitff[3])), ((x_prenodeone_4_w[0] & (~ indexbitff[3])) | (x_prenodetwo_4_w[0] & indexbitff[3]))},
x_prenode_5_w = {((x_prenodeone_5_w[33] & (~ indexbitff[4])) | (x_prenodetwo_5_w[33] & indexbitff[4])), ((x_prenodeone_5_w[32] & (~ indexbitff[4])) | (x_prenodetwo_5_w[32] & indexbitff[4])), ((x_prenodeone_5_w[31] & (~ indexbitff[4])) | (x_prenodetwo_5_w[31] & indexbitff[4])), ((x_prenodeone_5_w[30] & (~ indexbitff[4])) | (x_prenodetwo_5_w[30] & indexbitff[4])), ((x_prenodeone_5_w[29] & (~ indexbitff[4])) | (x_prenodetwo_5_w[29] & indexbitff[4])), ((x_prenodeone_5_w[28] & (~ indexbitff[4])) | (x_prenodetwo_5_w[28] & indexbitff[4])), ((x_prenodeone_5_w[27] & (~ indexbitff[4])) | (x_prenodetwo_5_w[27] & indexbitff[4])), ((x_prenodeone_5_w[26] & (~ indexbitff[4])) | (x_prenodetwo_5_w[26] & indexbitff[4])), ((x_prenodeone_5_w[25] & (~ indexbitff[4])) | (x_prenodetwo_5_w[25] & indexbitff[4])), ((x_prenodeone_5_w[24] & (~ indexbitff[4])) | (x_prenodetwo_5_w[24] & indexbitff[4])), ((x_prenodeone_5_w[23] & (~ indexbitff[4])) | (x_prenodetwo_5_w[23] & indexbitff[4])), ((x_prenodeone_5_w[22] & (~ indexbitff[4])) | (x_prenodetwo_5_w[22] & indexbitff[4])), ((x_prenodeone_5_w[21] & (~ indexbitff[4])) | (x_prenodetwo_5_w[21] & indexbitff[4])), ((x_prenodeone_5_w[20] & (~ indexbitff[4])) | (x_prenodetwo_5_w[20] & indexbitff[4])), ((x_prenodeone_5_w[19] & (~ indexbitff[4])) | (x_prenodetwo_5_w[19] & indexbitff[4])), ((x_prenodeone_5_w[18] & (~ indexbitff[4])) | (x_prenodetwo_5_w[18] & indexbitff[4])), ((x_prenodeone_5_w[17] & (~ indexbitff[4])) | (x_prenodetwo_5_w[17] & indexbitff[4])), ((x_prenodeone_5_w[16] & (~ indexbitff[4])) | (x_prenodetwo_5_w[16] & indexbitff[4])), ((x_prenodeone_5_w[15] & (~ indexbitff[4])) | (x_prenodetwo_5_w[15] & indexbitff[4])), ((x_prenodeone_5_w[14] & (~ indexbitff[4])) | (x_prenodetwo_5_w[14] & indexbitff[4])), ((x_prenodeone_5_w[13] & (~ indexbitff[4])) | (x_prenodetwo_5_w[13] & indexbitff[4])), ((x_prenodeone_5_w[12] & (~ indexbitff[4])) | (x_prenodetwo_5_w[12] & indexbitff[4])), ((x_prenodeone_5_w[11] & (~ indexbitff[4])) | (x_prenodetwo_5_w[11] & indexbitff[4])), ((x_prenodeone_5_w[10] & (~ indexbitff[4]
)) | (x_prenodetwo_5_w[10] & indexbitff[4])), ((x_prenodeone_5_w[9] & (~ indexbitff[4])) | (x_prenodetwo_5_w[9] & indexbitff[4])), ((x_prenodeone_5_w[8] & (~ indexbitff[4])) | (x_prenodetwo_5_w[8] & indexbitff[4])), ((x_prenodeone_5_w[7] & (~ indexbitff[4])) | (x_prenodetwo_5_w[7] & indexbitff[4])), ((x_prenodeone_5_w[6] & (~ indexbitff[4])) | (x_prenodetwo_5_w[6] & indexbitff[4])), ((x_prenodeone_5_w[5] & (~ indexbitff[4])) | (x_prenodetwo_5_w[5] & indexbitff[4])), ((x_prenodeone_5_w[4] & (~ indexbitff[4])) | (x_prenodetwo_5_w[4] & indexbitff[4])), ((x_prenodeone_5_w[3] & (~ indexbitff[4])) | (x_prenodetwo_5_w[3] & indexbitff[4])), ((x_prenodeone_5_w[2] & (~ indexbitff[4])) | (x_prenodetwo_5_w[2] & indexbitff[4])), ((x_prenodeone_5_w[1] & (~ indexbitff[4])) | (x_prenodetwo_5_w[1] & indexbitff[4])), ((x_prenodeone_5_w[0] & (~ indexbitff[4])) | (x_prenodetwo_5_w[0] & indexbitff[4]))},
x_prenode_6_w = {((x_prenodeone_6_w[33] & (~ indexbitff[5])) | (x_prenodetwo_6_w[33] & indexbitff[5])), ((x_prenodeone_6_w[32] & (~ indexbitff[5])) | (x_prenodetwo_6_w[32] & indexbitff[5])), ((x_prenodeone_6_w[31] & (~ indexbitff[5])) | (x_prenodetwo_6_w[31] & indexbitff[5])), ((x_prenodeone_6_w[30] & (~ indexbitff[5])) | (x_prenodetwo_6_w[30] & indexbitff[5])), ((x_prenodeone_6_w[29] & (~ indexbitff[5])) | (x_prenodetwo_6_w[29] & indexbitff[5])), ((x_prenodeone_6_w[28] & (~ indexbitff[5])) | (x_prenodetwo_6_w[28] & indexbitff[5])), ((x_prenodeone_6_w[27] & (~ indexbitff[5])) | (x_prenodetwo_6_w[27] & indexbitff[5])), ((x_prenodeone_6_w[26] & (~ indexbitff[5])) | (x_prenodetwo_6_w[26] & indexbitff[5])), ((x_prenodeone_6_w[25] & (~ indexbitff[5])) | (x_prenodetwo_6_w[25] & indexbitff[5])), ((x_prenodeone_6_w[24] & (~ indexbitff[5])) | (x_prenodetwo_6_w[24] & indexbitff[5])), ((x_prenodeone_6_w[23] & (~ indexbitff[5])) | (x_prenodetwo_6_w[23] & indexbitff[5])), ((x_prenodeone_6_w[22] & (~ indexbitff[5])) | (x_prenodetwo_6_w[22] & indexbitff[5])), ((x_prenodeone_6_w[21] & (~ indexbitff[5])) | (x_prenodetwo_6_w[21] & indexbitff[5])), ((x_prenodeone_6_w[20] & (~ indexbitff[5])) | (x_prenodetwo_6_w[20] & indexbitff[5])), ((x_prenodeone_6_w[19] & (~ indexbitff[5])) | (x_prenodetwo_6_w[19] & indexbitff[5])), ((x_prenodeone_6_w[18] & (~ indexbitff[5])) | (x_prenodetwo_6_w[18] & indexbitff[5])), ((x_prenodeone_6_w[17] & (~ indexbitff[5])) | (x_prenodetwo_6_w[17] & indexbitff[5])), ((x_prenodeone_6_w[16] & (~ indexbitff[5])) | (x_prenodetwo_6_w[16] & indexbitff[5])), ((x_prenodeone_6_w[15] & (~ indexbitff[5])) | (x_prenodetwo_6_w[15] & indexbitff[5])), ((x_prenodeone_6_w[14] & (~ indexbitff[5])) | (x_prenodetwo_6_w[14] & indexbitff[5])), ((x_prenodeone_6_w[13] & (~ indexbitff[5])) | (x_prenodetwo_6_w[13] & indexbitff[5])), ((x_prenodeone_6_w[12] & (~ indexbitff[5])) | (x_prenodetwo_6_w[12] & indexbitff[5])), ((x_prenodeone_6_w[11] & (~ indexbitff[5])) | (x_prenodetwo_6_w[11] & indexbitff[5])), ((x_prenodeone_6_w[10] & (~ indexbitff[5]
)) | (x_prenodetwo_6_w[10] & indexbitff[5])), ((x_prenodeone_6_w[9] & (~ indexbitff[5])) | (x_prenodetwo_6_w[9] & indexbitff[5])), ((x_prenodeone_6_w[8] & (~ indexbitff[5])) | (x_prenodetwo_6_w[8] & indexbitff[5])), ((x_prenodeone_6_w[7] & (~ indexbitff[5])) | (x_prenodetwo_6_w[7] & indexbitff[5])), ((x_prenodeone_6_w[6] & (~ indexbitff[5])) | (x_prenodetwo_6_w[6] & indexbitff[5])), ((x_prenodeone_6_w[5] & (~ indexbitff[5])) | (x_prenodetwo_6_w[5] & indexbitff[5])), ((x_prenodeone_6_w[4] & (~ indexbitff[5])) | (x_prenodetwo_6_w[4] & indexbitff[5])), ((x_prenodeone_6_w[3] & (~ indexbitff[5])) | (x_prenodetwo_6_w[3] & indexbitff[5])), ((x_prenodeone_6_w[2] & (~ indexbitff[5])) | (x_prenodetwo_6_w[2] & indexbitff[5])), ((x_prenodeone_6_w[1] & (~ indexbitff[5])) | (x_prenodetwo_6_w[1] & indexbitff[5])), ((x_prenodeone_6_w[0] & (~ indexbitff[5])) | (x_prenodetwo_6_w[0] & indexbitff[5]))},
x_prenode_7_w = {((x_prenodeone_7_w[33] & (~ indexbitff[6])) | (x_prenodetwo_7_w[33] & indexbitff[6])), ((x_prenodeone_7_w[32] & (~ indexbitff[6])) | (x_prenodetwo_7_w[32] & indexbitff[6])), ((x_prenodeone_7_w[31] & (~ indexbitff[6])) | (x_prenodetwo_7_w[31] & indexbitff[6])), ((x_prenodeone_7_w[30] & (~ indexbitff[6])) | (x_prenodetwo_7_w[30] & indexbitff[6])), ((x_prenodeone_7_w[29] & (~ indexbitff[6])) | (x_prenodetwo_7_w[29] & indexbitff[6])), ((x_prenodeone_7_w[28] & (~ indexbitff[6])) | (x_prenodetwo_7_w[28] & indexbitff[6])), ((x_prenodeone_7_w[27] & (~ indexbitff[6])) | (x_prenodetwo_7_w[27] & indexbitff[6])), ((x_prenodeone_7_w[26] & (~ indexbitff[6])) | (x_prenodetwo_7_w[26] & indexbitff[6])), ((x_prenodeone_7_w[25] & (~ indexbitff[6])) | (x_prenodetwo_7_w[25] & indexbitff[6])), ((x_prenodeone_7_w[24] & (~ indexbitff[6])) | (x_prenodetwo_7_w[24] & indexbitff[6])), ((x_prenodeone_7_w[23] & (~ indexbitff[6])) | (x_prenodetwo_7_w[23] & indexbitff[6])), ((x_prenodeone_7_w[22] & (~ indexbitff[6])) | (x_prenodetwo_7_w[22] & indexbitff[6])), ((x_prenodeone_7_w[21] & (~ indexbitff[6])) | (x_prenodetwo_7_w[21] & indexbitff[6])), ((x_prenodeone_7_w[20] & (~ indexbitff[6])) | (x_prenodetwo_7_w[20] & indexbitff[6])), ((x_prenodeone_7_w[19] & (~ indexbitff[6])) | (x_prenodetwo_7_w[19] & indexbitff[6])), ((x_prenodeone_7_w[18] & (~ indexbitff[6])) | (x_prenodetwo_7_w[18] & indexbitff[6])), ((x_prenodeone_7_w[17] & (~ indexbitff[6])) | (x_prenodetwo_7_w[17] & indexbitff[6])), ((x_prenodeone_7_w[16] & (~ indexbitff[6])) | (x_prenodetwo_7_w[16] & indexbitff[6])), ((x_prenodeone_7_w[15] & (~ indexbitff[6])) | (x_prenodetwo_7_w[15] & indexbitff[6])), ((x_prenodeone_7_w[14] & (~ indexbitff[6])) | (x_prenodetwo_7_w[14] & indexbitff[6])), ((x_prenodeone_7_w[13] & (~ indexbitff[6])) | (x_prenodetwo_7_w[13] & indexbitff[6])), ((x_prenodeone_7_w[12] & (~ indexbitff[6])) | (x_prenodetwo_7_w[12] & indexbitff[6])), ((x_prenodeone_7_w[11] & (~ indexbitff[6])) | (x_prenodetwo_7_w[11] & indexbitff[6])), ((x_prenodeone_7_w[10] & (~ indexbitff[6]
)) | (x_prenodetwo_7_w[10] & indexbitff[6])), ((x_prenodeone_7_w[9] & (~ indexbitff[6])) | (x_prenodetwo_7_w[9] & indexbitff[6])), ((x_prenodeone_7_w[8] & (~ indexbitff[6])) | (x_prenodetwo_7_w[8] & indexbitff[6])), ((x_prenodeone_7_w[7] & (~ indexbitff[6])) | (x_prenodetwo_7_w[7] & indexbitff[6])), ((x_prenodeone_7_w[6] & (~ indexbitff[6])) | (x_prenodetwo_7_w[6] & indexbitff[6])), ((x_prenodeone_7_w[5] & (~ indexbitff[6])) | (x_prenodetwo_7_w[5] & indexbitff[6])), ((x_prenodeone_7_w[4] & (~ indexbitff[6])) | (x_prenodetwo_7_w[4] & indexbitff[6])), ((x_prenodeone_7_w[3] & (~ indexbitff[6])) | (x_prenodetwo_7_w[3] & indexbitff[6])), ((x_prenodeone_7_w[2] & (~ indexbitff[6])) | (x_prenodetwo_7_w[2] & indexbitff[6])), ((x_prenodeone_7_w[1] & (~ indexbitff[6])) | (x_prenodetwo_7_w[1] & indexbitff[6])), ((x_prenodeone_7_w[0] & (~ indexbitff[6])) | (x_prenodetwo_7_w[0] & indexbitff[6]))},
x_prenode_8_w = {((x_prenodeone_8_w[33] & (~ indexbitff[7])) | (x_prenodetwo_8_w[33] & indexbitff[7])), ((x_prenodeone_8_w[32] & (~ indexbitff[7])) | (x_prenodetwo_8_w[32] & indexbitff[7])), ((x_prenodeone_8_w[31] & (~ indexbitff[7])) | (x_prenodetwo_8_w[31] & indexbitff[7])), ((x_prenodeone_8_w[30] & (~ indexbitff[7])) | (x_prenodetwo_8_w[30] & indexbitff[7])), ((x_prenodeone_8_w[29] & (~ indexbitff[7])) | (x_prenodetwo_8_w[29] & indexbitff[7])), ((x_prenodeone_8_w[28] & (~ indexbitff[7])) | (x_prenodetwo_8_w[28] & indexbitff[7])), ((x_prenodeone_8_w[27] & (~ indexbitff[7])) | (x_prenodetwo_8_w[27] & indexbitff[7])), ((x_prenodeone_8_w[26] & (~ indexbitff[7])) | (x_prenodetwo_8_w[26] & indexbitff[7])), ((x_prenodeone_8_w[25] & (~ indexbitff[7])) | (x_prenodetwo_8_w[25] & indexbitff[7])), ((x_prenodeone_8_w[24] & (~ indexbitff[7])) | (x_prenodetwo_8_w[24] & indexbitff[7])), ((x_prenodeone_8_w[23] & (~ indexbitff[7])) | (x_prenodetwo_8_w[23] & indexbitff[7])), ((x_prenodeone_8_w[22] & (~ indexbitff[7])) | (x_prenodetwo_8_w[22] & indexbitff[7])), ((x_prenodeone_8_w[21] & (~ indexbitff[7])) | (x_prenodetwo_8_w[21] & indexbitff[7])), ((x_prenodeone_8_w[20] & (~ indexbitff[7])) | (x_prenodetwo_8_w[20] & indexbitff[7])), ((x_prenodeone_8_w[19] & (~ indexbitff[7])) | (x_prenodetwo_8_w[19] & indexbitff[7])), ((x_prenodeone_8_w[18] & (~ indexbitff[7])) | (x_prenodetwo_8_w[18] & indexbitff[7])), ((x_prenodeone_8_w[17] & (~ indexbitff[7])) | (x_prenodetwo_8_w[17] & indexbitff[7])), ((x_prenodeone_8_w[16] & (~ indexbitff[7])) | (x_prenodetwo_8_w[16] & indexbitff[7])), ((x_prenodeone_8_w[15] & (~ indexbitff[7])) | (x_prenodetwo_8_w[15] & indexbitff[7])), ((x_prenodeone_8_w[14] & (~ indexbitff[7])) | (x_prenodetwo_8_w[14] & indexbitff[7])), ((x_prenodeone_8_w[13] & (~ indexbitff[7])) | (x_prenodetwo_8_w[13] & indexbitff[7])), ((x_prenodeone_8_w[12] & (~ indexbitff[7])) | (x_prenodetwo_8_w[12] & indexbitff[7])), ((x_prenodeone_8_w[11] & (~ indexbitff[7])) | (x_prenodetwo_8_w[11] & indexbitff[7])), ((x_prenodeone_8_w[10] & (~ indexbitff[7]
)) | (x_prenodetwo_8_w[10] & indexbitff[7])), ((x_prenodeone_8_w[9] & (~ indexbitff[7])) | (x_prenodetwo_8_w[9] & indexbitff[7])), ((x_prenodeone_8_w[8] & (~ indexbitff[7])) | (x_prenodetwo_8_w[8] & indexbitff[7])), ((x_prenodeone_8_w[7] & (~ indexbitff[7])) | (x_prenodetwo_8_w[7] & indexbitff[7])), ((x_prenodeone_8_w[6] & (~ indexbitff[7])) | (x_prenodetwo_8_w[6] & indexbitff[7])), ((x_prenodeone_8_w[5] & (~ indexbitff[7])) | (x_prenodetwo_8_w[5] & indexbitff[7])), ((x_prenodeone_8_w[4] & (~ indexbitff[7])) | (x_prenodetwo_8_w[4] & indexbitff[7])), ((x_prenodeone_8_w[3] & (~ indexbitff[7])) | (x_prenodetwo_8_w[3] & indexbitff[7])), ((x_prenodeone_8_w[2] & (~ indexbitff[7])) | (x_prenodetwo_8_w[2] & indexbitff[7])), ((x_prenodeone_8_w[1] & (~ indexbitff[7])) | (x_prenodetwo_8_w[1] & indexbitff[7])), ((x_prenodeone_8_w[0] & (~ indexbitff[7])) | (x_prenodetwo_8_w[0] & indexbitff[7]))},
x_prenode_9_w = {((x_prenodeone_9_w[33] & (~ indexbitff[8])) | (x_prenodetwo_9_w[33] & indexbitff[8])), ((x_prenodeone_9_w[32] & (~ indexbitff[8])) | (x_prenodetwo_9_w[32] & indexbitff[8])), ((x_prenodeone_9_w[31] & (~ indexbitff[8])) | (x_prenodetwo_9_w[31] & indexbitff[8])), ((x_prenodeone_9_w[30] & (~ indexbitff[8])) | (x_prenodetwo_9_w[30] & indexbitff[8])), ((x_prenodeone_9_w[29] & (~ indexbitff[8])) | (x_prenodetwo_9_w[29] & indexbitff[8])), ((x_prenodeone_9_w[28] & (~ indexbitff[8])) | (x_prenodetwo_9_w[28] & indexbitff[8])), ((x_prenodeone_9_w[27] & (~ indexbitff[8])) | (x_prenodetwo_9_w[27] & indexbitff[8])), ((x_prenodeone_9_w[26] & (~ indexbitff[8])) | (x_prenodetwo_9_w[26] & indexbitff[8])), ((x_prenodeone_9_w[25] & (~ indexbitff[8])) | (x_prenodetwo_9_w[25] & indexbitff[8])), ((x_prenodeone_9_w[24] & (~ indexbitff[8])) | (x_prenodetwo_9_w[24] & indexbitff[8])), ((x_prenodeone_9_w[23] & (~ indexbitff[8])) | (x_prenodetwo_9_w[23] & indexbitff[8])), ((x_prenodeone_9_w[22] & (~ indexbitff[8])) | (x_prenodetwo_9_w[22] & indexbitff[8])), ((x_prenodeone_9_w[21] & (~ indexbitff[8])) | (x_prenodetwo_9_w[21] & indexbitff[8])), ((x_prenodeone_9_w[20] & (~ indexbitff[8])) | (x_prenodetwo_9_w[20] & indexbitff[8])), ((x_prenodeone_9_w[19] & (~ indexbitff[8])) | (x_prenodetwo_9_w[19] & indexbitff[8])), ((x_prenodeone_9_w[18] & (~ indexbitff[8])) | (x_prenodetwo_9_w[18] & indexbitff[8])), ((x_prenodeone_9_w[17] & (~ indexbitff[8])) | (x_prenodetwo_9_w[17] & indexbitff[8])), ((x_prenodeone_9_w[16] & (~ indexbitff[8])) | (x_prenodetwo_9_w[16] & indexbitff[8])), ((x_prenodeone_9_w[15] & (~ indexbitff[8])) | (x_prenodetwo_9_w[15] & indexbitff[8])), ((x_prenodeone_9_w[14] & (~ indexbitff[8])) | (x_prenodetwo_9_w[14] & indexbitff[8])), ((x_prenodeone_9_w[13] & (~ indexbitff[8])) | (x_prenodetwo_9_w[13] & indexbitff[8])), ((x_prenodeone_9_w[12] & (~ indexbitff[8])) | (x_prenodetwo_9_w[12] & indexbitff[8])), ((x_prenodeone_9_w[11] & (~ indexbitff[8])) | (x_prenodetwo_9_w[11] & indexbitff[8])), ((x_prenodeone_9_w[10] & (~ indexbitff[8]
)) | (x_prenodetwo_9_w[10] & indexbitff[8])), ((x_prenodeone_9_w[9] & (~ indexbitff[8])) | (x_prenodetwo_9_w[9] & indexbitff[8])), ((x_prenodeone_9_w[8] & (~ indexbitff[8])) | (x_prenodetwo_9_w[8] & indexbitff[8])), ((x_prenodeone_9_w[7] & (~ indexbitff[8])) | (x_prenodetwo_9_w[7] & indexbitff[8])), ((x_prenodeone_9_w[6] & (~ indexbitff[8])) | (x_prenodetwo_9_w[6] & indexbitff[8])), ((x_prenodeone_9_w[5] & (~ indexbitff[8])) | (x_prenodetwo_9_w[5] & indexbitff[8])), ((x_prenodeone_9_w[4] & (~ indexbitff[8])) | (x_prenodetwo_9_w[4] & indexbitff[8])), ((x_prenodeone_9_w[3] & (~ indexbitff[8])) | (x_prenodetwo_9_w[3] & indexbitff[8])), ((x_prenodeone_9_w[2] & (~ indexbitff[8])) | (x_prenodetwo_9_w[2] & indexbitff[8])), ((x_prenodeone_9_w[1] & (~ indexbitff[8])) | (x_prenodetwo_9_w[1] & indexbitff[8])), ((x_prenodeone_9_w[0] & (~ indexbitff[8])) | (x_prenodetwo_9_w[0] & indexbitff[8]))},
x_prenodeone_10_w = {{10{(~ y_pipeff_9[33])}}, (~ y_pipeff_9[32]), (~ y_pipeff_9[31]), (~ y_pipeff_9[30]), (~ y_pipeff_9[29]), (~ y_pipeff_9[28]), (~ y_pipeff_9[27]), (~ y_pipeff_9[26]), (~ y_pipeff_9[25]), (~ y_pipeff_9[24]), (~ y_pipeff_9[23]), (~ y_pipeff_9[22]), (~ y_pipeff_9[21]), (~ y_pipeff_9[20]), (~ y_pipeff_9[19]), (~ y_pipeff_9[18]), (~ y_pipeff_9[17]), (~ y_pipeff_9[16]), (~ y_pipeff_9[15]), (~ y_pipeff_9[14]), (~ y_pipeff_9[13]), (~ y_pipeff_9[12]), (~ y_pipeff_9[11]), (~ y_pipeff_9[10]), (~ y_pipeff_9[9])},
x_prenodeone_11_w = {{11{(~ y_pipeff_10[33])}}, (~ y_pipeff_10[32]), (~ y_pipeff_10[31]), (~ y_pipeff_10[30]), (~ y_pipeff_10[29]), (~ y_pipeff_10[28]), (~ y_pipeff_10[27]), (~ y_pipeff_10[26]), (~ y_pipeff_10[25]), (~ y_pipeff_10[24]), (~ y_pipeff_10[23]), (~ y_pipeff_10[22]), (~ y_pipeff_10[21]), (~ y_pipeff_10[20]), (~ y_pipeff_10[19]), (~ y_pipeff_10[18]), (~ y_pipeff_10[17]), (~ y_pipeff_10[16]), (~ y_pipeff_10[15]), (~ y_pipeff_10[14]), (~ y_pipeff_10[13]), (~ y_pipeff_10[12]), (~ y_pipeff_10[11]), (~ y_pipeff_10[10])},
x_prenodeone_12_w = {{12{(~ y_pipeff_11[33])}}, (~ y_pipeff_11[32]), (~ y_pipeff_11[31]), (~ y_pipeff_11[30]), (~ y_pipeff_11[29]), (~ y_pipeff_11[28]), (~ y_pipeff_11[27]), (~ y_pipeff_11[26]), (~ y_pipeff_11[25]), (~ y_pipeff_11[24]), (~ y_pipeff_11[23]), (~ y_pipeff_11[22]), (~ y_pipeff_11[21]), (~ y_pipeff_11[20]), (~ y_pipeff_11[19]), (~ y_pipeff_11[18]), (~ y_pipeff_11[17]), (~ y_pipeff_11[16]), (~ y_pipeff_11[15]), (~ y_pipeff_11[14]), (~ y_pipeff_11[13]), (~ y_pipeff_11[12]), (~ y_pipeff_11[11])},
x_prenodeone_13_w = {{13{(~ y_pipeff_12[33])}}, (~ y_pipeff_12[32]), (~ y_pipeff_12[31]), (~ y_pipeff_12[30]), (~ y_pipeff_12[29]), (~ y_pipeff_12[28]), (~ y_pipeff_12[27]), (~ y_pipeff_12[26]), (~ y_pipeff_12[25]), (~ y_pipeff_12[24]), (~ y_pipeff_12[23]), (~ y_pipeff_12[22]), (~ y_pipeff_12[21]), (~ y_pipeff_12[20]), (~ y_pipeff_12[19]), (~ y_pipeff_12[18]), (~ y_pipeff_12[17]), (~ y_pipeff_12[16]), (~ y_pipeff_12[15]), (~ y_pipeff_12[14]), (~ y_pipeff_12[13]), (~ y_pipeff_12[12])},
x_prenodeone_2_w = {{2{(~ y_pipeff_1[33])}}, (~ y_pipeff_1[32]), (~ y_pipeff_1[31]), (~ y_pipeff_1[30]), (~ y_pipeff_1[29]), (~ y_pipeff_1[28]), (~ y_pipeff_1[27]), (~ y_pipeff_1[26]), (~ y_pipeff_1[25]), (~ y_pipeff_1[24]), (~ y_pipeff_1[23]), (~ y_pipeff_1[22]), (~ y_pipeff_1[21]), (~ y_pipeff_1[20]), (~ y_pipeff_1[19]), (~ y_pipeff_1[18]), (~ y_pipeff_1[17]), (~ y_pipeff_1[16]), (~ y_pipeff_1[15]), (~ y_pipeff_1[14]), (~ y_pipeff_1[13]), (~ y_pipeff_1[12]), (~ y_pipeff_1[11]), (~ y_pipeff_1[10]), (~ y_pipeff_1[9]), (~ y_pipeff_1[8]), (~ y_pipeff_1[7]), (~ y_pipeff_1[6]), (~ y_pipeff_1[5]), (~ y_pipeff_1[4]), (~ y_pipeff_1[3]), (~ y_pipeff_1[2]), (~ y_pipeff_1[1])},
x_prenodeone_3_w = {{3{(~ y_pipeff_2[33])}}, (~ y_pipeff_2[32]), (~ y_pipeff_2[31]), (~ y_pipeff_2[30]), (~ y_pipeff_2[29]), (~ y_pipeff_2[28]), (~ y_pipeff_2[27]), (~ y_pipeff_2[26]), (~ y_pipeff_2[25]), (~ y_pipeff_2[24]), (~ y_pipeff_2[23]), (~ y_pipeff_2[22]), (~ y_pipeff_2[21]), (~ y_pipeff_2[20]), (~ y_pipeff_2[19]), (~ y_pipeff_2[18]), (~ y_pipeff_2[17]), (~ y_pipeff_2[16]), (~ y_pipeff_2[15]), (~ y_pipeff_2[14]), (~ y_pipeff_2[13]), (~ y_pipeff_2[12]), (~ y_pipeff_2[11]), (~ y_pipeff_2[10]), (~ y_pipeff_2[9]), (~ y_pipeff_2[8]), (~ y_pipeff_2[7]), (~ y_pipeff_2[6]), (~ y_pipeff_2[5]), (~ y_pipeff_2[4]), (~ y_pipeff_2[3]), (~ y_pipeff_2[2])},
x_prenodeone_4_w = {{4{(~ y_pipeff_3[33])}}, (~ y_pipeff_3[32]), (~ y_pipeff_3[31]), (~ y_pipeff_3[30]), (~ y_pipeff_3[29]), (~ y_pipeff_3[28]), (~ y_pipeff_3[27]), (~ y_pipeff_3[26]), (~ y_pipeff_3[25]), (~ y_pipeff_3[24]), (~ y_pipeff_3[23]), (~ y_pipeff_3[22]), (~ y_pipeff_3[21]), (~ y_pipeff_3[20]), (~ y_pipeff_3[19]), (~ y_pipeff_3[18]), (~ y_pipeff_3[17]), (~ y_pipeff_3[16]), (~ y_pipeff_3[15]), (~ y_pipeff_3[14]), (~ y_pipeff_3[13]), (~ y_pipeff_3[12]), (~ y_pipeff_3[11]), (~ y_pipeff_3[10]), (~ y_pipeff_3[9]), (~ y_pipeff_3[8]), (~ y_pipeff_3[7]), (~ y_pipeff_3[6]), (~ y_pipeff_3[5]), (~ y_pipeff_3[4]), (~ y_pipeff_3[3])},
x_prenodeone_5_w = {{5{(~ y_pipeff_4[33])}}, (~ y_pipeff_4[32]), (~ y_pipeff_4[31]), (~ y_pipeff_4[30]), (~ y_pipeff_4[29]), (~ y_pipeff_4[28]), (~ y_pipeff_4[27]), (~ y_pipeff_4[26]), (~ y_pipeff_4[25]), (~ y_pipeff_4[24]), (~ y_pipeff_4[23]), (~ y_pipeff_4[22]), (~ y_pipeff_4[21]), (~ y_pipeff_4[20]), (~ y_pipeff_4[19]), (~ y_pipeff_4[18]), (~ y_pipeff_4[17]), (~ y_pipeff_4[16]), (~ y_pipeff_4[15]), (~ y_pipeff_4[14]), (~ y_pipeff_4[13]), (~ y_pipeff_4[12]), (~ y_pipeff_4[11]), (~ y_pipeff_4[10]), (~ y_pipeff_4[9]), (~ y_pipeff_4[8]), (~ y_pipeff_4[7]), (~ y_pipeff_4[6]), (~ y_pipeff_4[5]), (~ y_pipeff_4[4])},
x_prenodeone_6_w = {{6{(~ y_pipeff_5[33])}}, (~ y_pipeff_5[32]), (~ y_pipeff_5[31]), (~ y_pipeff_5[30]), (~ y_pipeff_5[29]), (~ y_pipeff_5[28]), (~ y_pipeff_5[27]), (~ y_pipeff_5[26]), (~ y_pipeff_5[25]), (~ y_pipeff_5[24]), (~ y_pipeff_5[23]), (~ y_pipeff_5[22]), (~ y_pipeff_5[21]), (~ y_pipeff_5[20]), (~ y_pipeff_5[19]), (~ y_pipeff_5[18]), (~ y_pipeff_5[17]), (~ y_pipeff_5[16]), (~ y_pipeff_5[15]), (~ y_pipeff_5[14]), (~ y_pipeff_5[13]), (~ y_pipeff_5[12]), (~ y_pipeff_5[11]), (~ y_pipeff_5[10]), (~ y_pipeff_5[9]), (~ y_pipeff_5[8]), (~ y_pipeff_5[7]), (~ y_pipeff_5[6]), (~ y_pipeff_5[5])},
x_prenodeone_7_w = {{7{(~ y_pipeff_6[33])}}, (~ y_pipeff_6[32]), (~ y_pipeff_6[31]), (~ y_pipeff_6[30]), (~ y_pipeff_6[29]), (~ y_pipeff_6[28]), (~ y_pipeff_6[27]), (~ y_pipeff_6[26]), (~ y_pipeff_6[25]), (~ y_pipeff_6[24]), (~ y_pipeff_6[23]), (~ y_pipeff_6[22]), (~ y_pipeff_6[21]), (~ y_pipeff_6[20]), (~ y_pipeff_6[19]), (~ y_pipeff_6[18]), (~ y_pipeff_6[17]), (~ y_pipeff_6[16]), (~ y_pipeff_6[15]), (~ y_pipeff_6[14]), (~ y_pipeff_6[13]), (~ y_pipeff_6[12]), (~ y_pipeff_6[11]), (~ y_pipeff_6[10]), (~ y_pipeff_6[9]), (~ y_pipeff_6[8]), (~ y_pipeff_6[7]), (~ y_pipeff_6[6])},
x_prenodeone_8_w = {{8{(~ y_pipeff_7[33])}}, (~ y_pipeff_7[32]), (~ y_pipeff_7[31]), (~ y_pipeff_7[30]), (~ y_pipeff_7[29]), (~ y_pipeff_7[28]), (~ y_pipeff_7[27]), (~ y_pipeff_7[26]), (~ y_pipeff_7[25]), (~ y_pipeff_7[24]), (~ y_pipeff_7[23]), (~ y_pipeff_7[22]), (~ y_pipeff_7[21]), (~ y_pipeff_7[20]), (~ y_pipeff_7[19]), (~ y_pipeff_7[18]), (~ y_pipeff_7[17]), (~ y_pipeff_7[16]), (~ y_pipeff_7[15]), (~ y_pipeff_7[14]), (~ y_pipeff_7[13]), (~ y_pipeff_7[12]), (~ y_pipeff_7[11]), (~ y_pipeff_7[10]), (~ y_pipeff_7[9]), (~ y_pipeff_7[8]), (~ y_pipeff_7[7])},
x_prenodeone_9_w = {{9{(~ y_pipeff_8[33])}}, (~ y_pipeff_8[32]), (~ y_pipeff_8[31]), (~ y_pipeff_8[30]), (~ y_pipeff_8[29]), (~ y_pipeff_8[28]), (~ y_pipeff_8[27]), (~ y_pipeff_8[26]), (~ y_pipeff_8[25]), (~ y_pipeff_8[24]), (~ y_pipeff_8[23]), (~ y_pipeff_8[22]), (~ y_pipeff_8[21]), (~ y_pipeff_8[20]), (~ y_pipeff_8[19]), (~ y_pipeff_8[18]), (~ y_pipeff_8[17]), (~ y_pipeff_8[16]), (~ y_pipeff_8[15]), (~ y_pipeff_8[14]), (~ y_pipeff_8[13]), (~ y_pipeff_8[12]), (~ y_pipeff_8[11]), (~ y_pipeff_8[10]), (~ y_pipeff_8[9]), (~ y_pipeff_8[8])},
x_prenodetwo_10_w = {{12{(~ y_pipeff_9[33])}}, (~ y_pipeff_9[32]), (~ y_pipeff_9[31]), (~ y_pipeff_9[30]), (~ y_pipeff_9[29]), (~ y_pipeff_9[28]), (~ y_pipeff_9[27]), (~ y_pipeff_9[26]), (~ y_pipeff_9[25]), (~ y_pipeff_9[24]), (~ y_pipeff_9[23]), (~ y_pipeff_9[22]), (~ y_pipeff_9[21]), (~ y_pipeff_9[20]), (~ y_pipeff_9[19]), (~ y_pipeff_9[18]), (~ y_pipeff_9[17]), (~ y_pipeff_9[16]), (~ y_pipeff_9[15]), (~ y_pipeff_9[14]), (~ y_pipeff_9[13]), (~ y_pipeff_9[12]), (~ y_pipeff_9[11])},
x_prenodetwo_11_w = {{13{(~ y_pipeff_10[33])}}, (~ y_pipeff_10[32]), (~ y_pipeff_10[31]), (~ y_pipeff_10[30]), (~ y_pipeff_10[29]), (~ y_pipeff_10[28]), (~ y_pipeff_10[27]), (~ y_pipeff_10[26]), (~ y_pipeff_10[25]), (~ y_pipeff_10[24]), (~ y_pipeff_10[23]), (~ y_pipeff_10[22]), (~ y_pipeff_10[21]), (~ y_pipeff_10[20]), (~ y_pipeff_10[19]), (~ y_pipeff_10[18]), (~ y_pipeff_10[17]), (~ y_pipeff_10[16]), (~ y_pipeff_10[15]), (~ y_pipeff_10[14]), (~ y_pipeff_10[13]), (~ y_pipeff_10[12])},
x_prenodetwo_12_w = {{14{(~ y_pipeff_11[33])}}, (~ y_pipeff_11[32]), (~ y_pipeff_11[31]), (~ y_pipeff_11[30]), (~ y_pipeff_11[29]), (~ y_pipeff_11[28]), (~ y_pipeff_11[27]), (~ y_pipeff_11[26]), (~ y_pipeff_11[25]), (~ y_pipeff_11[24]), (~ y_pipeff_11[23]), (~ y_pipeff_11[22]), (~ y_pipeff_11[21]), (~ y_pipeff_11[20]), (~ y_pipeff_11[19]), (~ y_pipeff_11[18]), (~ y_pipeff_11[17]), (~ y_pipeff_11[16]), (~ y_pipeff_11[15]), (~ y_pipeff_11[14]), (~ y_pipeff_11[13])},
x_prenodetwo_13_w = {{15{(~ y_pipeff_12[33])}}, (~ y_pipeff_12[32]), (~ y_pipeff_12[31]), (~ y_pipeff_12[30]), (~ y_pipeff_12[29]), (~ y_pipeff_12[28]), (~ y_pipeff_12[27]), (~ y_pipeff_12[26]), (~ y_pipeff_12[25]), (~ y_pipeff_12[24]), (~ y_pipeff_12[23]), (~ y_pipeff_12[22]), (~ y_pipeff_12[21]), (~ y_pipeff_12[20]), (~ y_pipeff_12[19]), (~ y_pipeff_12[18]), (~ y_pipeff_12[17]), (~ y_pipeff_12[16]), (~ y_pipeff_12[15]), (~ y_pipeff_12[14])},
x_prenodetwo_2_w = {{4{(~ y_pipeff_1[33])}}, (~ y_pipeff_1[32]), (~ y_pipeff_1[31]), (~ y_pipeff_1[30]), (~ y_pipeff_1[29]), (~ y_pipeff_1[28]), (~ y_pipeff_1[27]), (~ y_pipeff_1[26]), (~ y_pipeff_1[25]), (~ y_pipeff_1[24]), (~ y_pipeff_1[23]), (~ y_pipeff_1[22]), (~ y_pipeff_1[21]), (~ y_pipeff_1[20]), (~ y_pipeff_1[19]), (~ y_pipeff_1[18]), (~ y_pipeff_1[17]), (~ y_pipeff_1[16]), (~ y_pipeff_1[15]), (~ y_pipeff_1[14]), (~ y_pipeff_1[13]), (~ y_pipeff_1[12]), (~ y_pipeff_1[11]), (~ y_pipeff_1[10]), (~ y_pipeff_1[9]), (~ y_pipeff_1[8]), (~ y_pipeff_1[7]), (~ y_pipeff_1[6]), (~ y_pipeff_1[5]), (~ y_pipeff_1[4]), (~ y_pipeff_1[3])},
x_prenodetwo_3_w = {{5{(~ y_pipeff_2[33])}}, (~ y_pipeff_2[32]), (~ y_pipeff_2[31]), (~ y_pipeff_2[30]), (~ y_pipeff_2[29]), (~ y_pipeff_2[28]), (~ y_pipeff_2[27]), (~ y_pipeff_2[26]), (~ y_pipeff_2[25]), (~ y_pipeff_2[24]), (~ y_pipeff_2[23]), (~ y_pipeff_2[22]), (~ y_pipeff_2[21]), (~ y_pipeff_2[20]), (~ y_pipeff_2[19]), (~ y_pipeff_2[18]), (~ y_pipeff_2[17]), (~ y_pipeff_2[16]), (~ y_pipeff_2[15]), (~ y_pipeff_2[14]), (~ y_pipeff_2[13]), (~ y_pipeff_2[12]), (~ y_pipeff_2[11]), (~ y_pipeff_2[10]), (~ y_pipeff_2[9]), (~ y_pipeff_2[8]), (~ y_pipeff_2[7]), (~ y_pipeff_2[6]), (~ y_pipeff_2[5]), (~ y_pipeff_2[4])},
x_prenodetwo_4_w = {{6{(~ y_pipeff_3[33])}}, (~ y_pipeff_3[32]), (~ y_pipeff_3[31]), (~ y_pipeff_3[30]), (~ y_pipeff_3[29]), (~ y_pipeff_3[28]), (~ y_pipeff_3[27]), (~ y_pipeff_3[26]), (~ y_pipeff_3[25]), (~ y_pipeff_3[24]), (~ y_pipeff_3[23]), (~ y_pipeff_3[22]), (~ y_pipeff_3[21]), (~ y_pipeff_3[20]), (~ y_pipeff_3[19]), (~ y_pipeff_3[18]), (~ y_pipeff_3[17]), (~ y_pipeff_3[16]), (~ y_pipeff_3[15]), (~ y_pipeff_3[14]), (~ y_pipeff_3[13]), (~ y_pipeff_3[12]), (~ y_pipeff_3[11]), (~ y_pipeff_3[10]), (~ y_pipeff_3[9]), (~ y_pipeff_3[8]), (~ y_pipeff_3[7]), (~ y_pipeff_3[6]), (~ y_pipeff_3[5])},
x_prenodetwo_5_w = {{7{(~ y_pipeff_4[33])}}, (~ y_pipeff_4[32]), (~ y_pipeff_4[31]), (~ y_pipeff_4[30]), (~ y_pipeff_4[29]), (~ y_pipeff_4[28]), (~ y_pipeff_4[27]), (~ y_pipeff_4[26]), (~ y_pipeff_4[25]), (~ y_pipeff_4[24]), (~ y_pipeff_4[23]), (~ y_pipeff_4[22]), (~ y_pipeff_4[21]), (~ y_pipeff_4[20]), (~ y_pipeff_4[19]), (~ y_pipeff_4[18]), (~ y_pipeff_4[17]), (~ y_pipeff_4[16]), (~ y_pipeff_4[15]), (~ y_pipeff_4[14]), (~ y_pipeff_4[13]), (~ y_pipeff_4[12]), (~ y_pipeff_4[11]), (~ y_pipeff_4[10]), (~ y_pipeff_4[9]), (~ y_pipeff_4[8]), (~ y_pipeff_4[7]), (~ y_pipeff_4[6])},
x_prenodetwo_6_w = {{8{(~ y_pipeff_5[33])}}, (~ y_pipeff_5[32]), (~ y_pipeff_5[31]), (~ y_pipeff_5[30]), (~ y_pipeff_5[29]), (~ y_pipeff_5[28]), (~ y_pipeff_5[27]), (~ y_pipeff_5[26]), (~ y_pipeff_5[25]), (~ y_pipeff_5[24]), (~ y_pipeff_5[23]), (~ y_pipeff_5[22]), (~ y_pipeff_5[21]), (~ y_pipeff_5[20]), (~ y_pipeff_5[19]), (~ y_pipeff_5[18]), (~ y_pipeff_5[17]), (~ y_pipeff_5[16]), (~ y_pipeff_5[15]), (~ y_pipeff_5[14]), (~ y_pipeff_5[13]), (~ y_pipeff_5[12]), (~ y_pipeff_5[11]), (~ y_pipeff_5[10]), (~ y_pipeff_5[9]), (~ y_pipeff_5[8]), (~ y_pipeff_5[7])},
x_prenodetwo_7_w = {{9{(~ y_pipeff_6[33])}}, (~ y_pipeff_6[32]), (~ y_pipeff_6[31]), (~ y_pipeff_6[30]), (~ y_pipeff_6[29]), (~ y_pipeff_6[28]), (~ y_pipeff_6[27]), (~ y_pipeff_6[26]), (~ y_pipeff_6[25]), (~ y_pipeff_6[24]), (~ y_pipeff_6[23]), (~ y_pipeff_6[22]), (~ y_pipeff_6[21]), (~ y_pipeff_6[20]), (~ y_pipeff_6[19]), (~ y_pipeff_6[18]), (~ y_pipeff_6[17]), (~ y_pipeff_6[16]), (~ y_pipeff_6[15]), (~ y_pipeff_6[14]), (~ y_pipeff_6[13]), (~ y_pipeff_6[12]), (~ y_pipeff_6[11]), (~ y_pipeff_6[10]), (~ y_pipeff_6[9]), (~ y_pipeff_6[8])},
x_prenodetwo_8_w = {{10{(~ y_pipeff_7[33])}}, (~ y_pipeff_7[32]), (~ y_pipeff_7[31]), (~ y_pipeff_7[30]), (~ y_pipeff_7[29]), (~ y_pipeff_7[28]), (~ y_pipeff_7[27]), (~ y_pipeff_7[26]), (~ y_pipeff_7[25]), (~ y_pipeff_7[24]), (~ y_pipeff_7[23]), (~ y_pipeff_7[22]), (~ y_pipeff_7[21]), (~ y_pipeff_7[20]), (~ y_pipeff_7[19]), (~ y_pipeff_7[18]), (~ y_pipeff_7[17]), (~ y_pipeff_7[16]), (~ y_pipeff_7[15]), (~ y_pipeff_7[14]), (~ y_pipeff_7[13]), (~ y_pipeff_7[12]), (~ y_pipeff_7[11]), (~ y_pipeff_7[10]), (~ y_pipeff_7[9])},
x_prenodetwo_9_w = {{11{(~ y_pipeff_8[33])}}, (~ y_pipeff_8[32]), (~ y_pipeff_8[31]), (~ y_pipeff_8[30]), (~ y_pipeff_8[29]), (~ y_pipeff_8[28]), (~ y_pipeff_8[27]), (~ y_pipeff_8[26]), (~ y_pipeff_8[25]), (~ y_pipeff_8[24]), (~ y_pipeff_8[23]), (~ y_pipeff_8[22]), (~ y_pipeff_8[21]), (~ y_pipeff_8[20]), (~ y_pipeff_8[19]), (~ y_pipeff_8[18]), (~ y_pipeff_8[17]), (~ y_pipeff_8[16]), (~ y_pipeff_8[15]), (~ y_pipeff_8[14]), (~ y_pipeff_8[13]), (~ y_pipeff_8[12]), (~ y_pipeff_8[11]), (~ y_pipeff_8[10])},
x_start_node_w = wire_cxs_value,
x_subnode_10_w = {(x_prenode_10_w[33] ^ z_pipeff_9[33]), (x_prenode_10_w[32] ^ z_pipeff_9[33]), (x_prenode_10_w[31] ^ z_pipeff_9[33]), (x_prenode_10_w[30] ^ z_pipeff_9[33]), (x_prenode_10_w[29] ^ z_pipeff_9[33]), (x_prenode_10_w[28] ^ z_pipeff_9[33]), (x_prenode_10_w[27] ^ z_pipeff_9[33]), (x_prenode_10_w[26] ^ z_pipeff_9[33]), (x_prenode_10_w[25] ^ z_pipeff_9[33]), (x_prenode_10_w[24] ^ z_pipeff_9[33]), (x_prenode_10_w[23] ^ z_pipeff_9[33]), (x_prenode_10_w[22] ^ z_pipeff_9[33]), (x_prenode_10_w[21] ^ z_pipeff_9[33]), (x_prenode_10_w[20] ^ z_pipeff_9[33]), (x_prenode_10_w[19] ^ z_pipeff_9[33]), (x_prenode_10_w[18] ^ z_pipeff_9[33]), (x_prenode_10_w[17] ^ z_pipeff_9[33]), (x_prenode_10_w[16] ^ z_pipeff_9[33]), (x_prenode_10_w[15] ^ z_pipeff_9[33]), (x_prenode_10_w[14] ^ z_pipeff_9[33]), (x_prenode_10_w[13] ^ z_pipeff_9[33]), (x_prenode_10_w[12] ^ z_pipeff_9[33]), (x_prenode_10_w[11] ^ z_pipeff_9[33]), (x_prenode_10_w[10] ^ z_pipeff_9[33]), (x_prenode_10_w[9] ^ z_pipeff_9[33]), (x_prenode_10_w[8] ^ z_pipeff_9[33]), (x_prenode_10_w[7] ^ z_pipeff_9[33]), (x_prenode_10_w[6] ^ z_pipeff_9[33]), (x_prenode_10_w[5] ^ z_pipeff_9[33]), (x_prenode_10_w[4] ^ z_pipeff_9[33]), (x_prenode_10_w[3] ^ z_pipeff_9[33]), (x_prenode_10_w[2] ^ z_pipeff_9[33]), (x_prenode_10_w[1] ^ z_pipeff_9[33]), (x_prenode_10_w[0] ^ z_pipeff_9[33])},
x_subnode_11_w = {(x_prenode_11_w[33] ^ z_pipeff_10[33]), (x_prenode_11_w[32] ^ z_pipeff_10[33]), (x_prenode_11_w[31] ^ z_pipeff_10[33]), (x_prenode_11_w[30] ^ z_pipeff_10[33]), (x_prenode_11_w[29] ^ z_pipeff_10[33]), (x_prenode_11_w[28] ^ z_pipeff_10[33]), (x_prenode_11_w[27] ^ z_pipeff_10[33]), (x_prenode_11_w[26] ^ z_pipeff_10[33]), (x_prenode_11_w[25] ^ z_pipeff_10[33]), (x_prenode_11_w[24] ^ z_pipeff_10[33]), (x_prenode_11_w[23] ^ z_pipeff_10[33]), (x_prenode_11_w[22] ^ z_pipeff_10[33]), (x_prenode_11_w[21] ^ z_pipeff_10[33]), (x_prenode_11_w[20] ^ z_pipeff_10[33]), (x_prenode_11_w[19] ^ z_pipeff_10[33]), (x_prenode_11_w[18] ^ z_pipeff_10[33]), (x_prenode_11_w[17] ^ z_pipeff_10[33]), (x_prenode_11_w[16] ^ z_pipeff_10[33]), (x_prenode_11_w[15] ^ z_pipeff_10[33]), (x_prenode_11_w[14] ^ z_pipeff_10[33]), (x_prenode_11_w[13] ^ z_pipeff_10[33]), (x_prenode_11_w[12] ^ z_pipeff_10[33]), (x_prenode_11_w[11] ^ z_pipeff_10[33]), (x_prenode_11_w[10] ^ z_pipeff_10[33]), (x_prenode_11_w[9] ^ z_pipeff_10[33]), (x_prenode_11_w[8] ^ z_pipeff_10[33]), (x_prenode_11_w[7] ^ z_pipeff_10[33]), (x_prenode_11_w[6] ^ z_pipeff_10[33]), (x_prenode_11_w[5] ^ z_pipeff_10[33]), (x_prenode_11_w[4] ^ z_pipeff_10[33]), (x_prenode_11_w[3] ^ z_pipeff_10[33]), (x_prenode_11_w[2] ^ z_pipeff_10[33]), (x_prenode_11_w[1] ^ z_pipeff_10[33]), (x_prenode_11_w[0] ^ z_pipeff_10[33])},
x_subnode_12_w = {(x_prenode_12_w[33] ^ z_pipeff_11[33]), (x_prenode_12_w[32] ^ z_pipeff_11[33]), (x_prenode_12_w[31] ^ z_pipeff_11[33]), (x_prenode_12_w[30] ^ z_pipeff_11[33]), (x_prenode_12_w[29] ^ z_pipeff_11[33]), (x_prenode_12_w[28] ^ z_pipeff_11[33]), (x_prenode_12_w[27] ^ z_pipeff_11[33]), (x_prenode_12_w[26] ^ z_pipeff_11[33]), (x_prenode_12_w[25] ^ z_pipeff_11[33]), (x_prenode_12_w[24] ^ z_pipeff_11[33]), (x_prenode_12_w[23] ^ z_pipeff_11[33]), (x_prenode_12_w[22] ^ z_pipeff_11[33]), (x_prenode_12_w[21] ^ z_pipeff_11[33]), (x_prenode_12_w[20] ^ z_pipeff_11[33]), (x_prenode_12_w[19] ^ z_pipeff_11[33]), (x_prenode_12_w[18] ^ z_pipeff_11[33]), (x_prenode_12_w[17] ^ z_pipeff_11[33]), (x_prenode_12_w[16] ^ z_pipeff_11[33]), (x_prenode_12_w[15] ^ z_pipeff_11[33]), (x_prenode_12_w[14] ^ z_pipeff_11[33]), (x_prenode_12_w[13] ^ z_pipeff_11[33]), (x_prenode_12_w[12] ^ z_pipeff_11[33]), (x_prenode_12_w[11] ^ z_pipeff_11[33]), (x_prenode_12_w[10] ^ z_pipeff_11[33]), (x_prenode_12_w[9] ^ z_pipeff_11[33]), (x_prenode_12_w[8] ^ z_pipeff_11[33]), (x_prenode_12_w[7] ^ z_pipeff_11[33]), (x_prenode_12_w[6] ^ z_pipeff_11[33]), (x_prenode_12_w[5] ^ z_pipeff_11[33]), (x_prenode_12_w[4] ^ z_pipeff_11[33]), (x_prenode_12_w[3] ^ z_pipeff_11[33]), (x_prenode_12_w[2] ^ z_pipeff_11[33]), (x_prenode_12_w[1] ^ z_pipeff_11[33]), (x_prenode_12_w[0] ^ z_pipeff_11[33])},
x_subnode_13_w = {(x_prenode_13_w[33] ^ z_pipeff_12[33]), (x_prenode_13_w[32] ^ z_pipeff_12[33]), (x_prenode_13_w[31] ^ z_pipeff_12[33]), (x_prenode_13_w[30] ^ z_pipeff_12[33]), (x_prenode_13_w[29] ^ z_pipeff_12[33]), (x_prenode_13_w[28] ^ z_pipeff_12[33]), (x_prenode_13_w[27] ^ z_pipeff_12[33]), (x_prenode_13_w[26] ^ z_pipeff_12[33]), (x_prenode_13_w[25] ^ z_pipeff_12[33]), (x_prenode_13_w[24] ^ z_pipeff_12[33]), (x_prenode_13_w[23] ^ z_pipeff_12[33]), (x_prenode_13_w[22] ^ z_pipeff_12[33]), (x_prenode_13_w[21] ^ z_pipeff_12[33]), (x_prenode_13_w[20] ^ z_pipeff_12[33]), (x_prenode_13_w[19] ^ z_pipeff_12[33]), (x_prenode_13_w[18] ^ z_pipeff_12[33]), (x_prenode_13_w[17] ^ z_pipeff_12[33]), (x_prenode_13_w[16] ^ z_pipeff_12[33]), (x_prenode_13_w[15] ^ z_pipeff_12[33]), (x_prenode_13_w[14] ^ z_pipeff_12[33]), (x_prenode_13_w[13] ^ z_pipeff_12[33]), (x_prenode_13_w[12] ^ z_pipeff_12[33]), (x_prenode_13_w[11] ^ z_pipeff_12[33]), (x_prenode_13_w[10] ^ z_pipeff_12[33]), (x_prenode_13_w[9] ^ z_pipeff_12[33]), (x_prenode_13_w[8] ^ z_pipeff_12[33]), (x_prenode_13_w[7] ^ z_pipeff_12[33]), (x_prenode_13_w[6] ^ z_pipeff_12[33]), (x_prenode_13_w[5] ^ z_pipeff_12[33]), (x_prenode_13_w[4] ^ z_pipeff_12[33]), (x_prenode_13_w[3] ^ z_pipeff_12[33]), (x_prenode_13_w[2] ^ z_pipeff_12[33]), (x_prenode_13_w[1] ^ z_pipeff_12[33]), (x_prenode_13_w[0] ^ z_pipeff_12[33])},
x_subnode_2_w = {(x_prenode_2_w[33] ^ z_pipeff_1[33]), (x_prenode_2_w[32] ^ z_pipeff_1[33]), (x_prenode_2_w[31] ^ z_pipeff_1[33]), (x_prenode_2_w[30] ^ z_pipeff_1[33]), (x_prenode_2_w[29] ^ z_pipeff_1[33]), (x_prenode_2_w[28] ^ z_pipeff_1[33]), (x_prenode_2_w[27] ^ z_pipeff_1[33]), (x_prenode_2_w[26] ^ z_pipeff_1[33]), (x_prenode_2_w[25] ^ z_pipeff_1[33]), (x_prenode_2_w[24] ^ z_pipeff_1[33]), (x_prenode_2_w[23] ^ z_pipeff_1[33]), (x_prenode_2_w[22] ^ z_pipeff_1[33]), (x_prenode_2_w[21] ^ z_pipeff_1[33]), (x_prenode_2_w[20] ^ z_pipeff_1[33]), (x_prenode_2_w[19] ^ z_pipeff_1[33]), (x_prenode_2_w[18] ^ z_pipeff_1[33]), (x_prenode_2_w[17] ^ z_pipeff_1[33]), (x_prenode_2_w[16] ^ z_pipeff_1[33]), (x_prenode_2_w[15] ^ z_pipeff_1[33]), (x_prenode_2_w[14] ^ z_pipeff_1[33]), (x_prenode_2_w[13] ^ z_pipeff_1[33]), (x_prenode_2_w[12] ^ z_pipeff_1[33]), (x_prenode_2_w[11] ^ z_pipeff_1[33]), (x_prenode_2_w[10] ^ z_pipeff_1[33]), (x_prenode_2_w[9] ^ z_pipeff_1[33]), (x_prenode_2_w[8] ^ z_pipeff_1[33]), (x_prenode_2_w[7] ^ z_pipeff_1[33]), (x_prenode_2_w[6] ^ z_pipeff_1[33]), (x_prenode_2_w[5] ^ z_pipeff_1[33]), (x_prenode_2_w[4] ^ z_pipeff_1[33]), (x_prenode_2_w[3] ^ z_pipeff_1[33]), (x_prenode_2_w[2] ^ z_pipeff_1[33]), (x_prenode_2_w[1] ^ z_pipeff_1[33]), (x_prenode_2_w[0] ^ z_pipeff_1[33])},
x_subnode_3_w = {(x_prenode_3_w[33] ^ z_pipeff_2[33]), (x_prenode_3_w[32] ^ z_pipeff_2[33]), (x_prenode_3_w[31] ^ z_pipeff_2[33]), (x_prenode_3_w[30] ^ z_pipeff_2[33]), (x_prenode_3_w[29] ^ z_pipeff_2[33]), (x_prenode_3_w[28] ^ z_pipeff_2[33]), (x_prenode_3_w[27] ^ z_pipeff_2[33]), (x_prenode_3_w[26] ^ z_pipeff_2[33]), (x_prenode_3_w[25] ^ z_pipeff_2[33]), (x_prenode_3_w[24] ^ z_pipeff_2[33]), (x_prenode_3_w[23] ^ z_pipeff_2[33]), (x_prenode_3_w[22] ^ z_pipeff_2[33]), (x_prenode_3_w[21] ^ z_pipeff_2[33]), (x_prenode_3_w[20] ^ z_pipeff_2[33]), (x_prenode_3_w[19] ^ z_pipeff_2[33]), (x_prenode_3_w[18] ^ z_pipeff_2[33]), (x_prenode_3_w[17] ^ z_pipeff_2[33]), (x_prenode_3_w[16] ^ z_pipeff_2[33]), (x_prenode_3_w[15] ^ z_pipeff_2[33]), (x_prenode_3_w[14] ^ z_pipeff_2[33]), (x_prenode_3_w[13] ^ z_pipeff_2[33]), (x_prenode_3_w[12] ^ z_pipeff_2[33]), (x_prenode_3_w[11] ^ z_pipeff_2[33]), (x_prenode_3_w[10] ^ z_pipeff_2[33]), (x_prenode_3_w[9] ^ z_pipeff_2[33]), (x_prenode_3_w[8] ^ z_pipeff_2[33]), (x_prenode_3_w[7] ^ z_pipeff_2[33]), (x_prenode_3_w[6] ^ z_pipeff_2[33]), (x_prenode_3_w[5] ^ z_pipeff_2[33]), (x_prenode_3_w[4] ^ z_pipeff_2[33]), (x_prenode_3_w[3] ^ z_pipeff_2[33]), (x_prenode_3_w[2] ^ z_pipeff_2[33]), (x_prenode_3_w[1] ^ z_pipeff_2[33]), (x_prenode_3_w[0] ^ z_pipeff_2[33])},
x_subnode_4_w = {(x_prenode_4_w[33] ^ z_pipeff_3[33]), (x_prenode_4_w[32] ^ z_pipeff_3[33]), (x_prenode_4_w[31] ^ z_pipeff_3[33]), (x_prenode_4_w[30] ^ z_pipeff_3[33]), (x_prenode_4_w[29] ^ z_pipeff_3[33]), (x_prenode_4_w[28] ^ z_pipeff_3[33]), (x_prenode_4_w[27] ^ z_pipeff_3[33]), (x_prenode_4_w[26] ^ z_pipeff_3[33]), (x_prenode_4_w[25] ^ z_pipeff_3[33]), (x_prenode_4_w[24] ^ z_pipeff_3[33]), (x_prenode_4_w[23] ^ z_pipeff_3[33]), (x_prenode_4_w[22] ^ z_pipeff_3[33]), (x_prenode_4_w[21] ^ z_pipeff_3[33]), (x_prenode_4_w[20] ^ z_pipeff_3[33]), (x_prenode_4_w[19] ^ z_pipeff_3[33]), (x_prenode_4_w[18] ^ z_pipeff_3[33]), (x_prenode_4_w[17] ^ z_pipeff_3[33]), (x_prenode_4_w[16] ^ z_pipeff_3[33]), (x_prenode_4_w[15] ^ z_pipeff_3[33]), (x_prenode_4_w[14] ^ z_pipeff_3[33]), (x_prenode_4_w[13] ^ z_pipeff_3[33]), (x_prenode_4_w[12] ^ z_pipeff_3[33]), (x_prenode_4_w[11] ^ z_pipeff_3[33]), (x_prenode_4_w[10] ^ z_pipeff_3[33]), (x_prenode_4_w[9] ^ z_pipeff_3[33]), (x_prenode_4_w[8] ^ z_pipeff_3[33]), (x_prenode_4_w[7] ^ z_pipeff_3[33]), (x_prenode_4_w[6] ^ z_pipeff_3[33]), (x_prenode_4_w[5] ^ z_pipeff_3[33]), (x_prenode_4_w[4] ^ z_pipeff_3[33]), (x_prenode_4_w[3] ^ z_pipeff_3[33]), (x_prenode_4_w[2] ^ z_pipeff_3[33]), (x_prenode_4_w[1] ^ z_pipeff_3[33]), (x_prenode_4_w[0] ^ z_pipeff_3[33])},
x_subnode_5_w = {(x_prenode_5_w[33] ^ z_pipeff_4[33]), (x_prenode_5_w[32] ^ z_pipeff_4[33]), (x_prenode_5_w[31] ^ z_pipeff_4[33]), (x_prenode_5_w[30] ^ z_pipeff_4[33]), (x_prenode_5_w[29] ^ z_pipeff_4[33]), (x_prenode_5_w[28] ^ z_pipeff_4[33]), (x_prenode_5_w[27] ^ z_pipeff_4[33]), (x_prenode_5_w[26] ^ z_pipeff_4[33]), (x_prenode_5_w[25] ^ z_pipeff_4[33]), (x_prenode_5_w[24] ^ z_pipeff_4[33]), (x_prenode_5_w[23] ^ z_pipeff_4[33]), (x_prenode_5_w[22] ^ z_pipeff_4[33]), (x_prenode_5_w[21] ^ z_pipeff_4[33]), (x_prenode_5_w[20] ^ z_pipeff_4[33]), (x_prenode_5_w[19] ^ z_pipeff_4[33]), (x_prenode_5_w[18] ^ z_pipeff_4[33]), (x_prenode_5_w[17] ^ z_pipeff_4[33]), (x_prenode_5_w[16] ^ z_pipeff_4[33]), (x_prenode_5_w[15] ^ z_pipeff_4[33]), (x_prenode_5_w[14] ^ z_pipeff_4[33]), (x_prenode_5_w[13] ^ z_pipeff_4[33]), (x_prenode_5_w[12] ^ z_pipeff_4[33]), (x_prenode_5_w[11] ^ z_pipeff_4[33]), (x_prenode_5_w[10] ^ z_pipeff_4[33]), (x_prenode_5_w[9] ^ z_pipeff_4[33]), (x_prenode_5_w[8] ^ z_pipeff_4[33]), (x_prenode_5_w[7] ^ z_pipeff_4[33]), (x_prenode_5_w[6] ^ z_pipeff_4[33]), (x_prenode_5_w[5] ^ z_pipeff_4[33]), (x_prenode_5_w[4] ^ z_pipeff_4[33]), (x_prenode_5_w[3] ^ z_pipeff_4[33]), (x_prenode_5_w[2] ^ z_pipeff_4[33]), (x_prenode_5_w[1] ^ z_pipeff_4[33]), (x_prenode_5_w[0] ^ z_pipeff_4[33])},
x_subnode_6_w = {(x_prenode_6_w[33] ^ z_pipeff_5[33]), (x_prenode_6_w[32] ^ z_pipeff_5[33]), (x_prenode_6_w[31] ^ z_pipeff_5[33]), (x_prenode_6_w[30] ^ z_pipeff_5[33]), (x_prenode_6_w[29] ^ z_pipeff_5[33]), (x_prenode_6_w[28] ^ z_pipeff_5[33]), (x_prenode_6_w[27] ^ z_pipeff_5[33]), (x_prenode_6_w[26] ^ z_pipeff_5[33]), (x_prenode_6_w[25] ^ z_pipeff_5[33]), (x_prenode_6_w[24] ^ z_pipeff_5[33]), (x_prenode_6_w[23] ^ z_pipeff_5[33]), (x_prenode_6_w[22] ^ z_pipeff_5[33]), (x_prenode_6_w[21] ^ z_pipeff_5[33]), (x_prenode_6_w[20] ^ z_pipeff_5[33]), (x_prenode_6_w[19] ^ z_pipeff_5[33]), (x_prenode_6_w[18] ^ z_pipeff_5[33]), (x_prenode_6_w[17] ^ z_pipeff_5[33]), (x_prenode_6_w[16] ^ z_pipeff_5[33]), (x_prenode_6_w[15] ^ z_pipeff_5[33]), (x_prenode_6_w[14] ^ z_pipeff_5[33]), (x_prenode_6_w[13] ^ z_pipeff_5[33]), (x_prenode_6_w[12] ^ z_pipeff_5[33]), (x_prenode_6_w[11] ^ z_pipeff_5[33]), (x_prenode_6_w[10] ^ z_pipeff_5[33]), (x_prenode_6_w[9] ^ z_pipeff_5[33]), (x_prenode_6_w[8] ^ z_pipeff_5[33]), (x_prenode_6_w[7] ^ z_pipeff_5[33]), (x_prenode_6_w[6] ^ z_pipeff_5[33]), (x_prenode_6_w[5] ^ z_pipeff_5[33]), (x_prenode_6_w[4] ^ z_pipeff_5[33]), (x_prenode_6_w[3] ^ z_pipeff_5[33]), (x_prenode_6_w[2] ^ z_pipeff_5[33]), (x_prenode_6_w[1] ^ z_pipeff_5[33]), (x_prenode_6_w[0] ^ z_pipeff_5[33])},
x_subnode_7_w = {(x_prenode_7_w[33] ^ z_pipeff_6[33]), (x_prenode_7_w[32] ^ z_pipeff_6[33]), (x_prenode_7_w[31] ^ z_pipeff_6[33]), (x_prenode_7_w[30] ^ z_pipeff_6[33]), (x_prenode_7_w[29] ^ z_pipeff_6[33]), (x_prenode_7_w[28] ^ z_pipeff_6[33]), (x_prenode_7_w[27] ^ z_pipeff_6[33]), (x_prenode_7_w[26] ^ z_pipeff_6[33]), (x_prenode_7_w[25] ^ z_pipeff_6[33]), (x_prenode_7_w[24] ^ z_pipeff_6[33]), (x_prenode_7_w[23] ^ z_pipeff_6[33]), (x_prenode_7_w[22] ^ z_pipeff_6[33]), (x_prenode_7_w[21] ^ z_pipeff_6[33]), (x_prenode_7_w[20] ^ z_pipeff_6[33]), (x_prenode_7_w[19] ^ z_pipeff_6[33]), (x_prenode_7_w[18] ^ z_pipeff_6[33]), (x_prenode_7_w[17] ^ z_pipeff_6[33]), (x_prenode_7_w[16] ^ z_pipeff_6[33]), (x_prenode_7_w[15] ^ z_pipeff_6[33]), (x_prenode_7_w[14] ^ z_pipeff_6[33]), (x_prenode_7_w[13] ^ z_pipeff_6[33]), (x_prenode_7_w[12] ^ z_pipeff_6[33]), (x_prenode_7_w[11] ^ z_pipeff_6[33]), (x_prenode_7_w[10] ^ z_pipeff_6[33]), (x_prenode_7_w[9] ^ z_pipeff_6[33]), (x_prenode_7_w[8] ^ z_pipeff_6[33]), (x_prenode_7_w[7] ^ z_pipeff_6[33]), (x_prenode_7_w[6] ^ z_pipeff_6[33]), (x_prenode_7_w[5] ^ z_pipeff_6[33]), (x_prenode_7_w[4] ^ z_pipeff_6[33]), (x_prenode_7_w[3] ^ z_pipeff_6[33]), (x_prenode_7_w[2] ^ z_pipeff_6[33]), (x_prenode_7_w[1] ^ z_pipeff_6[33]), (x_prenode_7_w[0] ^ z_pipeff_6[33])},
x_subnode_8_w = {(x_prenode_8_w[33] ^ z_pipeff_7[33]), (x_prenode_8_w[32] ^ z_pipeff_7[33]), (x_prenode_8_w[31] ^ z_pipeff_7[33]), (x_prenode_8_w[30] ^ z_pipeff_7[33]), (x_prenode_8_w[29] ^ z_pipeff_7[33]), (x_prenode_8_w[28] ^ z_pipeff_7[33]), (x_prenode_8_w[27] ^ z_pipeff_7[33]), (x_prenode_8_w[26] ^ z_pipeff_7[33]), (x_prenode_8_w[25] ^ z_pipeff_7[33]), (x_prenode_8_w[24] ^ z_pipeff_7[33]), (x_prenode_8_w[23] ^ z_pipeff_7[33]), (x_prenode_8_w[22] ^ z_pipeff_7[33]), (x_prenode_8_w[21] ^ z_pipeff_7[33]), (x_prenode_8_w[20] ^ z_pipeff_7[33]), (x_prenode_8_w[19] ^ z_pipeff_7[33]), (x_prenode_8_w[18] ^ z_pipeff_7[33]), (x_prenode_8_w[17] ^ z_pipeff_7[33]), (x_prenode_8_w[16] ^ z_pipeff_7[33]), (x_prenode_8_w[15] ^ z_pipeff_7[33]), (x_prenode_8_w[14] ^ z_pipeff_7[33]), (x_prenode_8_w[13] ^ z_pipeff_7[33]), (x_prenode_8_w[12] ^ z_pipeff_7[33]), (x_prenode_8_w[11] ^ z_pipeff_7[33]), (x_prenode_8_w[10] ^ z_pipeff_7[33]), (x_prenode_8_w[9] ^ z_pipeff_7[33]), (x_prenode_8_w[8] ^ z_pipeff_7[33]), (x_prenode_8_w[7] ^ z_pipeff_7[33]), (x_prenode_8_w[6] ^ z_pipeff_7[33]), (x_prenode_8_w[5] ^ z_pipeff_7[33]), (x_prenode_8_w[4] ^ z_pipeff_7[33]), (x_prenode_8_w[3] ^ z_pipeff_7[33]), (x_prenode_8_w[2] ^ z_pipeff_7[33]), (x_prenode_8_w[1] ^ z_pipeff_7[33]), (x_prenode_8_w[0] ^ z_pipeff_7[33])},
x_subnode_9_w = {(x_prenode_9_w[33] ^ z_pipeff_8[33]), (x_prenode_9_w[32] ^ z_pipeff_8[33]), (x_prenode_9_w[31] ^ z_pipeff_8[33]), (x_prenode_9_w[30] ^ z_pipeff_8[33]), (x_prenode_9_w[29] ^ z_pipeff_8[33]), (x_prenode_9_w[28] ^ z_pipeff_8[33]), (x_prenode_9_w[27] ^ z_pipeff_8[33]), (x_prenode_9_w[26] ^ z_pipeff_8[33]), (x_prenode_9_w[25] ^ z_pipeff_8[33]), (x_prenode_9_w[24] ^ z_pipeff_8[33]), (x_prenode_9_w[23] ^ z_pipeff_8[33]), (x_prenode_9_w[22] ^ z_pipeff_8[33]), (x_prenode_9_w[21] ^ z_pipeff_8[33]), (x_prenode_9_w[20] ^ z_pipeff_8[33]), (x_prenode_9_w[19] ^ z_pipeff_8[33]), (x_prenode_9_w[18] ^ z_pipeff_8[33]), (x_prenode_9_w[17] ^ z_pipeff_8[33]), (x_prenode_9_w[16] ^ z_pipeff_8[33]), (x_prenode_9_w[15] ^ z_pipeff_8[33]), (x_prenode_9_w[14] ^ z_pipeff_8[33]), (x_prenode_9_w[13] ^ z_pipeff_8[33]), (x_prenode_9_w[12] ^ z_pipeff_8[33]), (x_prenode_9_w[11] ^ z_pipeff_8[33]), (x_prenode_9_w[10] ^ z_pipeff_8[33]), (x_prenode_9_w[9] ^ z_pipeff_8[33]), (x_prenode_9_w[8] ^ z_pipeff_8[33]), (x_prenode_9_w[7] ^ z_pipeff_8[33]), (x_prenode_9_w[6] ^ z_pipeff_8[33]), (x_prenode_9_w[5] ^ z_pipeff_8[33]), (x_prenode_9_w[4] ^ z_pipeff_8[33]), (x_prenode_9_w[3] ^ z_pipeff_8[33]), (x_prenode_9_w[2] ^ z_pipeff_8[33]), (x_prenode_9_w[1] ^ z_pipeff_8[33]), (x_prenode_9_w[0] ^ z_pipeff_8[33])},
y_pipenode_10_w = wire_y_pipenode_10_add_result,
y_pipenode_11_w = wire_y_pipenode_11_add_result,
y_pipenode_12_w = wire_y_pipenode_12_add_result,
y_pipenode_13_w = wire_y_pipenode_13_add_result,
y_pipenode_2_w = wire_y_pipenode_2_add_result,
y_pipenode_3_w = wire_y_pipenode_3_add_result,
y_pipenode_4_w = wire_y_pipenode_4_add_result,
y_pipenode_5_w = wire_y_pipenode_5_add_result,
y_pipenode_6_w = wire_y_pipenode_6_add_result,
y_pipenode_7_w = wire_y_pipenode_7_add_result,
y_pipenode_8_w = wire_y_pipenode_8_add_result,
y_pipenode_9_w = wire_y_pipenode_9_add_result,
y_prenode_10_w = {((y_prenodeone_10_w[33] & (~ indexbitff[9])) | (y_prenodetwo_10_w[33] & indexbitff[9])), ((y_prenodeone_10_w[32] & (~ indexbitff[9])) | (y_prenodetwo_10_w[32] & indexbitff[9])), ((y_prenodeone_10_w[31] & (~ indexbitff[9])) | (y_prenodetwo_10_w[31] & indexbitff[9])), ((y_prenodeone_10_w[30] & (~ indexbitff[9])) | (y_prenodetwo_10_w[30] & indexbitff[9])), ((y_prenodeone_10_w[29] & (~ indexbitff[9])) | (y_prenodetwo_10_w[29] & indexbitff[9])), ((y_prenodeone_10_w[28] & (~ indexbitff[9])) | (y_prenodetwo_10_w[28] & indexbitff[9])), ((y_prenodeone_10_w[27] & (~ indexbitff[9])) | (y_prenodetwo_10_w[27] & indexbitff[9])), ((y_prenodeone_10_w[26] & (~ indexbitff[9])) | (y_prenodetwo_10_w[26] & indexbitff[9])), ((y_prenodeone_10_w[25] & (~ indexbitff[9])) | (y_prenodetwo_10_w[25] & indexbitff[9])), ((y_prenodeone_10_w[24] & (~ indexbitff[9])) | (y_prenodetwo_10_w[24] & indexbitff[9])), ((y_prenodeone_10_w[23] & (~ indexbitff[9])) | (y_prenodetwo_10_w[23] & indexbitff[9])), ((y_prenodeone_10_w[22] & (~ indexbitff[9])) | (y_prenodetwo_10_w[22] & indexbitff[9])), ((y_prenodeone_10_w[21] & (~ indexbitff[9])) | (y_prenodetwo_10_w[21] & indexbitff[9])), ((y_prenodeone_10_w[20] & (~ indexbitff[9])) | (y_prenodetwo_10_w[20] & indexbitff[9])), ((y_prenodeone_10_w[19] & (~ indexbitff[9])) | (y_prenodetwo_10_w[19] & indexbitff[9])), ((y_prenodeone_10_w[18] & (~ indexbitff[9])) | (y_prenodetwo_10_w[18] & indexbitff[9])), ((y_prenodeone_10_w[17] & (~ indexbitff[9])) | (y_prenodetwo_10_w[17] & indexbitff[9])), ((y_prenodeone_10_w[16] & (~ indexbitff[9])) | (y_prenodetwo_10_w[16] & indexbitff[9])), ((y_prenodeone_10_w[15] & (~ indexbitff[9])) | (y_prenodetwo_10_w[15] & indexbitff[9])), ((y_prenodeone_10_w[14] & (~ indexbitff[9])) | (y_prenodetwo_10_w[14] & indexbitff[9])), ((y_prenodeone_10_w[13] & (~ indexbitff[9])) | (y_prenodetwo_10_w[13] & indexbitff[9])), ((y_prenodeone_10_w[12] & (~ indexbitff[9])) | (y_prenodetwo_10_w[12] & indexbitff[9])), ((y_prenodeone_10_w[11] & (~ indexbitff[9])) | (y_prenodetwo_10_w[11]
& indexbitff[9])), ((y_prenodeone_10_w[10] & (~ indexbitff[9])) | (y_prenodetwo_10_w[10] & indexbitff[9])), ((y_prenodeone_10_w[9] & (~ indexbitff[9])) | (y_prenodetwo_10_w[9] & indexbitff[9])), ((y_prenodeone_10_w[8] & (~ indexbitff[9])) | (y_prenodetwo_10_w[8] & indexbitff[9])), ((y_prenodeone_10_w[7] & (~ indexbitff[9])) | (y_prenodetwo_10_w[7] & indexbitff[9])), ((y_prenodeone_10_w[6] & (~ indexbitff[9])) | (y_prenodetwo_10_w[6] & indexbitff[9])), ((y_prenodeone_10_w[5] & (~ indexbitff[9])) | (y_prenodetwo_10_w[5] & indexbitff[9])), ((y_prenodeone_10_w[4] & (~ indexbitff[9])) | (y_prenodetwo_10_w[4] & indexbitff[9])), ((y_prenodeone_10_w[3] & (~ indexbitff[9])) | (y_prenodetwo_10_w[3] & indexbitff[9])), ((y_prenodeone_10_w[2] & (~ indexbitff[9])) | (y_prenodetwo_10_w[2] & indexbitff[9])), ((y_prenodeone_10_w[1] & (~ indexbitff[9])) | (y_prenodetwo_10_w[1] & indexbitff[9])), ((y_prenodeone_10_w[0] & (~ indexbitff[9])) | (y_prenodetwo_10_w[0] & indexbitff[9]))},
y_prenode_11_w = {((y_prenodeone_11_w[33] & (~ indexbitff[10])) | (y_prenodetwo_11_w[33] & indexbitff[10])), ((y_prenodeone_11_w[32] & (~ indexbitff[10])) | (y_prenodetwo_11_w[32] & indexbitff[10])), ((y_prenodeone_11_w[31] & (~ indexbitff[10])) | (y_prenodetwo_11_w[31] & indexbitff[10])), ((y_prenodeone_11_w[30] & (~ indexbitff[10])) | (y_prenodetwo_11_w[30] & indexbitff[10])), ((y_prenodeone_11_w[29] & (~ indexbitff[10])) | (y_prenodetwo_11_w[29] & indexbitff[10])), ((y_prenodeone_11_w[28] & (~ indexbitff[10])) | (y_prenodetwo_11_w[28] & indexbitff[10])), ((y_prenodeone_11_w[27] & (~ indexbitff[10])) | (y_prenodetwo_11_w[27] & indexbitff[10])), ((y_prenodeone_11_w[26] & (~ indexbitff[10])) | (y_prenodetwo_11_w[26] & indexbitff[10])), ((y_prenodeone_11_w[25] & (~ indexbitff[10])) | (y_prenodetwo_11_w[25] & indexbitff[10])), ((y_prenodeone_11_w[24] & (~ indexbitff[10])) | (y_prenodetwo_11_w[24] & indexbitff[10])), ((y_prenodeone_11_w[23] & (~ indexbitff[10])) | (y_prenodetwo_11_w[23] & indexbitff[10])), ((y_prenodeone_11_w[22] & (~ indexbitff[10])) | (y_prenodetwo_11_w[22] & indexbitff[10])), ((y_prenodeone_11_w[21] & (~ indexbitff[10])) | (y_prenodetwo_11_w[21] & indexbitff[10])), ((y_prenodeone_11_w[20] & (~ indexbitff[10])) | (y_prenodetwo_11_w[20] & indexbitff[10])), ((y_prenodeone_11_w[19] & (~ indexbitff[10])) | (y_prenodetwo_11_w[19] & indexbitff[10])), ((y_prenodeone_11_w[18] & (~ indexbitff[10])) | (y_prenodetwo_11_w[18] & indexbitff[10])), ((y_prenodeone_11_w[17] & (~ indexbitff[10])) | (y_prenodetwo_11_w[17] & indexbitff[10])), ((y_prenodeone_11_w[16] & (~ indexbitff[10])) | (y_prenodetwo_11_w[16] & indexbitff[10])), ((y_prenodeone_11_w[15] & (~ indexbitff[10])) | (y_prenodetwo_11_w[15] & indexbitff[10])), ((y_prenodeone_11_w[14] & (~ indexbitff[10])) | (y_prenodetwo_11_w[14] & indexbitff[10])), ((y_prenodeone_11_w[13] & (~ indexbitff[10])) | (y_prenodetwo_11_w[13] & indexbitff[10])), ((y_prenodeone_11_w[12] & (~ indexbitff[10])) | (y_prenodetwo_11_w[12] & indexbitff[10])), ((y_prenodeone_11_w[11] &
(~ indexbitff[10])) | (y_prenodetwo_11_w[11] & indexbitff[10])), ((y_prenodeone_11_w[10] & (~ indexbitff[10])) | (y_prenodetwo_11_w[10] & indexbitff[10])), ((y_prenodeone_11_w[9] & (~ indexbitff[10])) | (y_prenodetwo_11_w[9] & indexbitff[10])), ((y_prenodeone_11_w[8] & (~ indexbitff[10])) | (y_prenodetwo_11_w[8] & indexbitff[10])), ((y_prenodeone_11_w[7] & (~ indexbitff[10])) | (y_prenodetwo_11_w[7] & indexbitff[10])), ((y_prenodeone_11_w[6] & (~ indexbitff[10])) | (y_prenodetwo_11_w[6] & indexbitff[10])), ((y_prenodeone_11_w[5] & (~ indexbitff[10])) | (y_prenodetwo_11_w[5] & indexbitff[10])), ((y_prenodeone_11_w[4] & (~ indexbitff[10])) | (y_prenodetwo_11_w[4] & indexbitff[10])), ((y_prenodeone_11_w[3] & (~ indexbitff[10])) | (y_prenodetwo_11_w[3] & indexbitff[10])), ((y_prenodeone_11_w[2] & (~ indexbitff[10])) | (y_prenodetwo_11_w[2] & indexbitff[10])), ((y_prenodeone_11_w[1] & (~ indexbitff[10])) | (y_prenodetwo_11_w[1] & indexbitff[10])), ((y_prenodeone_11_w[0] & (~ indexbitff[10])) | (y_prenodetwo_11_w[0] & indexbitff[10]))},
y_prenode_12_w = {((y_prenodeone_12_w[33] & (~ indexbitff[11])) | (y_prenodetwo_12_w[33] & indexbitff[11])), ((y_prenodeone_12_w[32] & (~ indexbitff[11])) | (y_prenodetwo_12_w[32] & indexbitff[11])), ((y_prenodeone_12_w[31] & (~ indexbitff[11])) | (y_prenodetwo_12_w[31] & indexbitff[11])), ((y_prenodeone_12_w[30] & (~ indexbitff[11])) | (y_prenodetwo_12_w[30] & indexbitff[11])), ((y_prenodeone_12_w[29] & (~ indexbitff[11])) | (y_prenodetwo_12_w[29] & indexbitff[11])), ((y_prenodeone_12_w[28] & (~ indexbitff[11])) | (y_prenodetwo_12_w[28] & indexbitff[11])), ((y_prenodeone_12_w[27] & (~ indexbitff[11])) | (y_prenodetwo_12_w[27] & indexbitff[11])), ((y_prenodeone_12_w[26] & (~ indexbitff[11])) | (y_prenodetwo_12_w[26] & indexbitff[11])), ((y_prenodeone_12_w[25] & (~ indexbitff[11])) | (y_prenodetwo_12_w[25] & indexbitff[11])), ((y_prenodeone_12_w[24] & (~ indexbitff[11])) | (y_prenodetwo_12_w[24] & indexbitff[11])), ((y_prenodeone_12_w[23] & (~ indexbitff[11])) | (y_prenodetwo_12_w[23] & indexbitff[11])), ((y_prenodeone_12_w[22] & (~ indexbitff[11])) | (y_prenodetwo_12_w[22] & indexbitff[11])), ((y_prenodeone_12_w[21] & (~ indexbitff[11])) | (y_prenodetwo_12_w[21] & indexbitff[11])), ((y_prenodeone_12_w[20] & (~ indexbitff[11])) | (y_prenodetwo_12_w[20] & indexbitff[11])), ((y_prenodeone_12_w[19] & (~ indexbitff[11])) | (y_prenodetwo_12_w[19] & indexbitff[11])), ((y_prenodeone_12_w[18] & (~ indexbitff[11])) | (y_prenodetwo_12_w[18] & indexbitff[11])), ((y_prenodeone_12_w[17] & (~ indexbitff[11])) | (y_prenodetwo_12_w[17] & indexbitff[11])), ((y_prenodeone_12_w[16] & (~ indexbitff[11])) | (y_prenodetwo_12_w[16] & indexbitff[11])), ((y_prenodeone_12_w[15] & (~ indexbitff[11])) | (y_prenodetwo_12_w[15] & indexbitff[11])), ((y_prenodeone_12_w[14] & (~ indexbitff[11])) | (y_prenodetwo_12_w[14] & indexbitff[11])), ((y_prenodeone_12_w[13] & (~ indexbitff[11])) | (y_prenodetwo_12_w[13] & indexbitff[11])), ((y_prenodeone_12_w[12] & (~ indexbitff[11])) | (y_prenodetwo_12_w[12] & indexbitff[11])), ((y_prenodeone_12_w[11] &
(~ indexbitff[11])) | (y_prenodetwo_12_w[11] & indexbitff[11])), ((y_prenodeone_12_w[10] & (~ indexbitff[11])) | (y_prenodetwo_12_w[10] & indexbitff[11])), ((y_prenodeone_12_w[9] & (~ indexbitff[11])) | (y_prenodetwo_12_w[9] & indexbitff[11])), ((y_prenodeone_12_w[8] & (~ indexbitff[11])) | (y_prenodetwo_12_w[8] & indexbitff[11])), ((y_prenodeone_12_w[7] & (~ indexbitff[11])) | (y_prenodetwo_12_w[7] & indexbitff[11])), ((y_prenodeone_12_w[6] & (~ indexbitff[11])) | (y_prenodetwo_12_w[6] & indexbitff[11])), ((y_prenodeone_12_w[5] & (~ indexbitff[11])) | (y_prenodetwo_12_w[5] & indexbitff[11])), ((y_prenodeone_12_w[4] & (~ indexbitff[11])) | (y_prenodetwo_12_w[4] & indexbitff[11])), ((y_prenodeone_12_w[3] & (~ indexbitff[11])) | (y_prenodetwo_12_w[3] & indexbitff[11])), ((y_prenodeone_12_w[2] & (~ indexbitff[11])) | (y_prenodetwo_12_w[2] & indexbitff[11])), ((y_prenodeone_12_w[1] & (~ indexbitff[11])) | (y_prenodetwo_12_w[1] & indexbitff[11])), ((y_prenodeone_12_w[0] & (~ indexbitff[11])) | (y_prenodetwo_12_w[0] & indexbitff[11]))},
y_prenode_13_w = {((y_prenodeone_13_w[33] & (~ indexbitff[12])) | (y_prenodetwo_13_w[33] & indexbitff[12])), ((y_prenodeone_13_w[32] & (~ indexbitff[12])) | (y_prenodetwo_13_w[32] & indexbitff[12])), ((y_prenodeone_13_w[31] & (~ indexbitff[12])) | (y_prenodetwo_13_w[31] & indexbitff[12])), ((y_prenodeone_13_w[30] & (~ indexbitff[12])) | (y_prenodetwo_13_w[30] & indexbitff[12])), ((y_prenodeone_13_w[29] & (~ indexbitff[12])) | (y_prenodetwo_13_w[29] & indexbitff[12])), ((y_prenodeone_13_w[28] & (~ indexbitff[12])) | (y_prenodetwo_13_w[28] & indexbitff[12])), ((y_prenodeone_13_w[27] & (~ indexbitff[12])) | (y_prenodetwo_13_w[27] & indexbitff[12])), ((y_prenodeone_13_w[26] & (~ indexbitff[12])) | (y_prenodetwo_13_w[26] & indexbitff[12])), ((y_prenodeone_13_w[25] & (~ indexbitff[12])) | (y_prenodetwo_13_w[25] & indexbitff[12])), ((y_prenodeone_13_w[24] & (~ indexbitff[12])) | (y_prenodetwo_13_w[24] & indexbitff[12])), ((y_prenodeone_13_w[23] & (~ indexbitff[12])) | (y_prenodetwo_13_w[23] & indexbitff[12])), ((y_prenodeone_13_w[22] & (~ indexbitff[12])) | (y_prenodetwo_13_w[22] & indexbitff[12])), ((y_prenodeone_13_w[21] & (~ indexbitff[12])) | (y_prenodetwo_13_w[21] & indexbitff[12])), ((y_prenodeone_13_w[20] & (~ indexbitff[12])) | (y_prenodetwo_13_w[20] & indexbitff[12])), ((y_prenodeone_13_w[19] & (~ indexbitff[12])) | (y_prenodetwo_13_w[19] & indexbitff[12])), ((y_prenodeone_13_w[18] & (~ indexbitff[12])) | (y_prenodetwo_13_w[18] & indexbitff[12])), ((y_prenodeone_13_w[17] & (~ indexbitff[12])) | (y_prenodetwo_13_w[17] & indexbitff[12])), ((y_prenodeone_13_w[16] & (~ indexbitff[12])) | (y_prenodetwo_13_w[16] & indexbitff[12])), ((y_prenodeone_13_w[15] & (~ indexbitff[12])) | (y_prenodetwo_13_w[15] & indexbitff[12])), ((y_prenodeone_13_w[14] & (~ indexbitff[12])) | (y_prenodetwo_13_w[14] & indexbitff[12])), ((y_prenodeone_13_w[13] & (~ indexbitff[12])) | (y_prenodetwo_13_w[13] & indexbitff[12])), ((y_prenodeone_13_w[12] & (~ indexbitff[12])) | (y_prenodetwo_13_w[12] & indexbitff[12])), ((y_prenodeone_13_w[11] &
(~ indexbitff[12])) | (y_prenodetwo_13_w[11] & indexbitff[12])), ((y_prenodeone_13_w[10] & (~ indexbitff[12])) | (y_prenodetwo_13_w[10] & indexbitff[12])), ((y_prenodeone_13_w[9] & (~ indexbitff[12])) | (y_prenodetwo_13_w[9] & indexbitff[12])), ((y_prenodeone_13_w[8] & (~ indexbitff[12])) | (y_prenodetwo_13_w[8] & indexbitff[12])), ((y_prenodeone_13_w[7] & (~ indexbitff[12])) | (y_prenodetwo_13_w[7] & indexbitff[12])), ((y_prenodeone_13_w[6] & (~ indexbitff[12])) | (y_prenodetwo_13_w[6] & indexbitff[12])), ((y_prenodeone_13_w[5] & (~ indexbitff[12])) | (y_prenodetwo_13_w[5] & indexbitff[12])), ((y_prenodeone_13_w[4] & (~ indexbitff[12])) | (y_prenodetwo_13_w[4] & indexbitff[12])), ((y_prenodeone_13_w[3] & (~ indexbitff[12])) | (y_prenodetwo_13_w[3] & indexbitff[12])), ((y_prenodeone_13_w[2] & (~ indexbitff[12])) | (y_prenodetwo_13_w[2] & indexbitff[12])), ((y_prenodeone_13_w[1] & (~ indexbitff[12])) | (y_prenodetwo_13_w[1] & indexbitff[12])), ((y_prenodeone_13_w[0] & (~ indexbitff[12])) | (y_prenodetwo_13_w[0] & indexbitff[12]))},
y_prenode_2_w = {((y_prenodeone_2_w[33] & (~ indexbitff[1])) | (y_prenodetwo_2_w[33] & indexbitff[1])), ((y_prenodeone_2_w[32] & (~ indexbitff[1])) | (y_prenodetwo_2_w[32] & indexbitff[1])), ((y_prenodeone_2_w[31] & (~ indexbitff[1])) | (y_prenodetwo_2_w[31] & indexbitff[1])), ((y_prenodeone_2_w[30] & (~ indexbitff[1])) | (y_prenodetwo_2_w[30] & indexbitff[1])), ((y_prenodeone_2_w[29] & (~ indexbitff[1])) | (y_prenodetwo_2_w[29] & indexbitff[1])), ((y_prenodeone_2_w[28] & (~ indexbitff[1])) | (y_prenodetwo_2_w[28] & indexbitff[1])), ((y_prenodeone_2_w[27] & (~ indexbitff[1])) | (y_prenodetwo_2_w[27] & indexbitff[1])), ((y_prenodeone_2_w[26] & (~ indexbitff[1])) | (y_prenodetwo_2_w[26] & indexbitff[1])), ((y_prenodeone_2_w[25] & (~ indexbitff[1])) | (y_prenodetwo_2_w[25] & indexbitff[1])), ((y_prenodeone_2_w[24] & (~ indexbitff[1])) | (y_prenodetwo_2_w[24] & indexbitff[1])), ((y_prenodeone_2_w[23] & (~ indexbitff[1])) | (y_prenodetwo_2_w[23] & indexbitff[1])), ((y_prenodeone_2_w[22] & (~ indexbitff[1])) | (y_prenodetwo_2_w[22] & indexbitff[1])), ((y_prenodeone_2_w[21] & (~ indexbitff[1])) | (y_prenodetwo_2_w[21] & indexbitff[1])), ((y_prenodeone_2_w[20] & (~ indexbitff[1])) | (y_prenodetwo_2_w[20] & indexbitff[1])), ((y_prenodeone_2_w[19] & (~ indexbitff[1])) | (y_prenodetwo_2_w[19] & indexbitff[1])), ((y_prenodeone_2_w[18] & (~ indexbitff[1])) | (y_prenodetwo_2_w[18] & indexbitff[1])), ((y_prenodeone_2_w[17] & (~ indexbitff[1])) | (y_prenodetwo_2_w[17] & indexbitff[1])), ((y_prenodeone_2_w[16] & (~ indexbitff[1])) | (y_prenodetwo_2_w[16] & indexbitff[1])), ((y_prenodeone_2_w[15] & (~ indexbitff[1])) | (y_prenodetwo_2_w[15] & indexbitff[1])), ((y_prenodeone_2_w[14] & (~ indexbitff[1])) | (y_prenodetwo_2_w[14] & indexbitff[1])), ((y_prenodeone_2_w[13] & (~ indexbitff[1])) | (y_prenodetwo_2_w[13] & indexbitff[1])), ((y_prenodeone_2_w[12] & (~ indexbitff[1])) | (y_prenodetwo_2_w[12] & indexbitff[1])), ((y_prenodeone_2_w[11] & (~ indexbitff[1])) | (y_prenodetwo_2_w[11] & indexbitff[1])), ((y_prenodeone_2_w[10] & (~ indexbitff[1]
)) | (y_prenodetwo_2_w[10] & indexbitff[1])), ((y_prenodeone_2_w[9] & (~ indexbitff[1])) | (y_prenodetwo_2_w[9] & indexbitff[1])), ((y_prenodeone_2_w[8] & (~ indexbitff[1])) | (y_prenodetwo_2_w[8] & indexbitff[1])), ((y_prenodeone_2_w[7] & (~ indexbitff[1])) | (y_prenodetwo_2_w[7] & indexbitff[1])), ((y_prenodeone_2_w[6] & (~ indexbitff[1])) | (y_prenodetwo_2_w[6] & indexbitff[1])), ((y_prenodeone_2_w[5] & (~ indexbitff[1])) | (y_prenodetwo_2_w[5] & indexbitff[1])), ((y_prenodeone_2_w[4] & (~ indexbitff[1])) | (y_prenodetwo_2_w[4] & indexbitff[1])), ((y_prenodeone_2_w[3] & (~ indexbitff[1])) | (y_prenodetwo_2_w[3] & indexbitff[1])), ((y_prenodeone_2_w[2] & (~ indexbitff[1])) | (y_prenodetwo_2_w[2] & indexbitff[1])), ((y_prenodeone_2_w[1] & (~ indexbitff[1])) | (y_prenodetwo_2_w[1] & indexbitff[1])), ((y_prenodeone_2_w[0] & (~ indexbitff[1])) | (y_prenodetwo_2_w[0] & indexbitff[1]))},
y_prenode_3_w = {((y_prenodeone_3_w[33] & (~ indexbitff[2])) | (y_prenodetwo_3_w[33] & indexbitff[2])), ((y_prenodeone_3_w[32] & (~ indexbitff[2])) | (y_prenodetwo_3_w[32] & indexbitff[2])), ((y_prenodeone_3_w[31] & (~ indexbitff[2])) | (y_prenodetwo_3_w[31] & indexbitff[2])), ((y_prenodeone_3_w[30] & (~ indexbitff[2])) | (y_prenodetwo_3_w[30] & indexbitff[2])), ((y_prenodeone_3_w[29] & (~ indexbitff[2])) | (y_prenodetwo_3_w[29] & indexbitff[2])), ((y_prenodeone_3_w[28] & (~ indexbitff[2])) | (y_prenodetwo_3_w[28] & indexbitff[2])), ((y_prenodeone_3_w[27] & (~ indexbitff[2])) | (y_prenodetwo_3_w[27] & indexbitff[2])), ((y_prenodeone_3_w[26] & (~ indexbitff[2])) | (y_prenodetwo_3_w[26] & indexbitff[2])), ((y_prenodeone_3_w[25] & (~ indexbitff[2])) | (y_prenodetwo_3_w[25] & indexbitff[2])), ((y_prenodeone_3_w[24] & (~ indexbitff[2])) | (y_prenodetwo_3_w[24] & indexbitff[2])), ((y_prenodeone_3_w[23] & (~ indexbitff[2])) | (y_prenodetwo_3_w[23] & indexbitff[2])), ((y_prenodeone_3_w[22] & (~ indexbitff[2])) | (y_prenodetwo_3_w[22] & indexbitff[2])), ((y_prenodeone_3_w[21] & (~ indexbitff[2])) | (y_prenodetwo_3_w[21] & indexbitff[2])), ((y_prenodeone_3_w[20] & (~ indexbitff[2])) | (y_prenodetwo_3_w[20] & indexbitff[2])), ((y_prenodeone_3_w[19] & (~ indexbitff[2])) | (y_prenodetwo_3_w[19] & indexbitff[2])), ((y_prenodeone_3_w[18] & (~ indexbitff[2])) | (y_prenodetwo_3_w[18] & indexbitff[2])), ((y_prenodeone_3_w[17] & (~ indexbitff[2])) | (y_prenodetwo_3_w[17] & indexbitff[2])), ((y_prenodeone_3_w[16] & (~ indexbitff[2])) | (y_prenodetwo_3_w[16] & indexbitff[2])), ((y_prenodeone_3_w[15] & (~ indexbitff[2])) | (y_prenodetwo_3_w[15] & indexbitff[2])), ((y_prenodeone_3_w[14] & (~ indexbitff[2])) | (y_prenodetwo_3_w[14] & indexbitff[2])), ((y_prenodeone_3_w[13] & (~ indexbitff[2])) | (y_prenodetwo_3_w[13] & indexbitff[2])), ((y_prenodeone_3_w[12] & (~ indexbitff[2])) | (y_prenodetwo_3_w[12] & indexbitff[2])), ((y_prenodeone_3_w[11] & (~ indexbitff[2])) | (y_prenodetwo_3_w[11] & indexbitff[2])), ((y_prenodeone_3_w[10] & (~ indexbitff[2]
)) | (y_prenodetwo_3_w[10] & indexbitff[2])), ((y_prenodeone_3_w[9] & (~ indexbitff[2])) | (y_prenodetwo_3_w[9] & indexbitff[2])), ((y_prenodeone_3_w[8] & (~ indexbitff[2])) | (y_prenodetwo_3_w[8] & indexbitff[2])), ((y_prenodeone_3_w[7] & (~ indexbitff[2])) | (y_prenodetwo_3_w[7] & indexbitff[2])), ((y_prenodeone_3_w[6] & (~ indexbitff[2])) | (y_prenodetwo_3_w[6] & indexbitff[2])), ((y_prenodeone_3_w[5] & (~ indexbitff[2])) | (y_prenodetwo_3_w[5] & indexbitff[2])), ((y_prenodeone_3_w[4] & (~ indexbitff[2])) | (y_prenodetwo_3_w[4] & indexbitff[2])), ((y_prenodeone_3_w[3] & (~ indexbitff[2])) | (y_prenodetwo_3_w[3] & indexbitff[2])), ((y_prenodeone_3_w[2] & (~ indexbitff[2])) | (y_prenodetwo_3_w[2] & indexbitff[2])), ((y_prenodeone_3_w[1] & (~ indexbitff[2])) | (y_prenodetwo_3_w[1] & indexbitff[2])), ((y_prenodeone_3_w[0] & (~ indexbitff[2])) | (y_prenodetwo_3_w[0] & indexbitff[2]))},
y_prenode_4_w = {((y_prenodeone_4_w[33] & (~ indexbitff[3])) | (y_prenodetwo_4_w[33] & indexbitff[3])), ((y_prenodeone_4_w[32] & (~ indexbitff[3])) | (y_prenodetwo_4_w[32] & indexbitff[3])), ((y_prenodeone_4_w[31] & (~ indexbitff[3])) | (y_prenodetwo_4_w[31] & indexbitff[3])), ((y_prenodeone_4_w[30] & (~ indexbitff[3])) | (y_prenodetwo_4_w[30] & indexbitff[3])), ((y_prenodeone_4_w[29] & (~ indexbitff[3])) | (y_prenodetwo_4_w[29] & indexbitff[3])), ((y_prenodeone_4_w[28] & (~ indexbitff[3])) | (y_prenodetwo_4_w[28] & indexbitff[3])), ((y_prenodeone_4_w[27] & (~ indexbitff[3])) | (y_prenodetwo_4_w[27] & indexbitff[3])), ((y_prenodeone_4_w[26] & (~ indexbitff[3])) | (y_prenodetwo_4_w[26] & indexbitff[3])), ((y_prenodeone_4_w[25] & (~ indexbitff[3])) | (y_prenodetwo_4_w[25] & indexbitff[3])), ((y_prenodeone_4_w[24] & (~ indexbitff[3])) | (y_prenodetwo_4_w[24] & indexbitff[3])), ((y_prenodeone_4_w[23] & (~ indexbitff[3])) | (y_prenodetwo_4_w[23] & indexbitff[3])), ((y_prenodeone_4_w[22] & (~ indexbitff[3])) | (y_prenodetwo_4_w[22] & indexbitff[3])), ((y_prenodeone_4_w[21] & (~ indexbitff[3])) | (y_prenodetwo_4_w[21] & indexbitff[3])), ((y_prenodeone_4_w[20] & (~ indexbitff[3])) | (y_prenodetwo_4_w[20] & indexbitff[3])), ((y_prenodeone_4_w[19] & (~ indexbitff[3])) | (y_prenodetwo_4_w[19] & indexbitff[3])), ((y_prenodeone_4_w[18] & (~ indexbitff[3])) | (y_prenodetwo_4_w[18] & indexbitff[3])), ((y_prenodeone_4_w[17] & (~ indexbitff[3])) | (y_prenodetwo_4_w[17] & indexbitff[3])), ((y_prenodeone_4_w[16] & (~ indexbitff[3])) | (y_prenodetwo_4_w[16] & indexbitff[3])), ((y_prenodeone_4_w[15] & (~ indexbitff[3])) | (y_prenodetwo_4_w[15] & indexbitff[3])), ((y_prenodeone_4_w[14] & (~ indexbitff[3])) | (y_prenodetwo_4_w[14] & indexbitff[3])), ((y_prenodeone_4_w[13] & (~ indexbitff[3])) | (y_prenodetwo_4_w[13] & indexbitff[3])), ((y_prenodeone_4_w[12] & (~ indexbitff[3])) | (y_prenodetwo_4_w[12] & indexbitff[3])), ((y_prenodeone_4_w[11] & (~ indexbitff[3])) | (y_prenodetwo_4_w[11] & indexbitff[3])), ((y_prenodeone_4_w[10] & (~ indexbitff[3]
)) | (y_prenodetwo_4_w[10] & indexbitff[3])), ((y_prenodeone_4_w[9] & (~ indexbitff[3])) | (y_prenodetwo_4_w[9] & indexbitff[3])), ((y_prenodeone_4_w[8] & (~ indexbitff[3])) | (y_prenodetwo_4_w[8] & indexbitff[3])), ((y_prenodeone_4_w[7] & (~ indexbitff[3])) | (y_prenodetwo_4_w[7] & indexbitff[3])), ((y_prenodeone_4_w[6] & (~ indexbitff[3])) | (y_prenodetwo_4_w[6] & indexbitff[3])), ((y_prenodeone_4_w[5] & (~ indexbitff[3])) | (y_prenodetwo_4_w[5] & indexbitff[3])), ((y_prenodeone_4_w[4] & (~ indexbitff[3])) | (y_prenodetwo_4_w[4] & indexbitff[3])), ((y_prenodeone_4_w[3] & (~ indexbitff[3])) | (y_prenodetwo_4_w[3] & indexbitff[3])), ((y_prenodeone_4_w[2] & (~ indexbitff[3])) | (y_prenodetwo_4_w[2] & indexbitff[3])), ((y_prenodeone_4_w[1] & (~ indexbitff[3])) | (y_prenodetwo_4_w[1] & indexbitff[3])), ((y_prenodeone_4_w[0] & (~ indexbitff[3])) | (y_prenodetwo_4_w[0] & indexbitff[3]))},
y_prenode_5_w = {((y_prenodeone_5_w[33] & (~ indexbitff[4])) | (y_prenodetwo_5_w[33] & indexbitff[4])), ((y_prenodeone_5_w[32] & (~ indexbitff[4])) | (y_prenodetwo_5_w[32] & indexbitff[4])), ((y_prenodeone_5_w[31] & (~ indexbitff[4])) | (y_prenodetwo_5_w[31] & indexbitff[4])), ((y_prenodeone_5_w[30] & (~ indexbitff[4])) | (y_prenodetwo_5_w[30] & indexbitff[4])), ((y_prenodeone_5_w[29] & (~ indexbitff[4])) | (y_prenodetwo_5_w[29] & indexbitff[4])), ((y_prenodeone_5_w[28] & (~ indexbitff[4])) | (y_prenodetwo_5_w[28] & indexbitff[4])), ((y_prenodeone_5_w[27] & (~ indexbitff[4])) | (y_prenodetwo_5_w[27] & indexbitff[4])), ((y_prenodeone_5_w[26] & (~ indexbitff[4])) | (y_prenodetwo_5_w[26] & indexbitff[4])), ((y_prenodeone_5_w[25] & (~ indexbitff[4])) | (y_prenodetwo_5_w[25] & indexbitff[4])), ((y_prenodeone_5_w[24] & (~ indexbitff[4])) | (y_prenodetwo_5_w[24] & indexbitff[4])), ((y_prenodeone_5_w[23] & (~ indexbitff[4])) | (y_prenodetwo_5_w[23] & indexbitff[4])), ((y_prenodeone_5_w[22] & (~ indexbitff[4])) | (y_prenodetwo_5_w[22] & indexbitff[4])), ((y_prenodeone_5_w[21] & (~ indexbitff[4])) | (y_prenodetwo_5_w[21] & indexbitff[4])), ((y_prenodeone_5_w[20] & (~ indexbitff[4])) | (y_prenodetwo_5_w[20] & indexbitff[4])), ((y_prenodeone_5_w[19] & (~ indexbitff[4])) | (y_prenodetwo_5_w[19] & indexbitff[4])), ((y_prenodeone_5_w[18] & (~ indexbitff[4])) | (y_prenodetwo_5_w[18] & indexbitff[4])), ((y_prenodeone_5_w[17] & (~ indexbitff[4])) | (y_prenodetwo_5_w[17] & indexbitff[4])), ((y_prenodeone_5_w[16] & (~ indexbitff[4])) | (y_prenodetwo_5_w[16] & indexbitff[4])), ((y_prenodeone_5_w[15] & (~ indexbitff[4])) | (y_prenodetwo_5_w[15] & indexbitff[4])), ((y_prenodeone_5_w[14] & (~ indexbitff[4])) | (y_prenodetwo_5_w[14] & indexbitff[4])), ((y_prenodeone_5_w[13] & (~ indexbitff[4])) | (y_prenodetwo_5_w[13] & indexbitff[4])), ((y_prenodeone_5_w[12] & (~ indexbitff[4])) | (y_prenodetwo_5_w[12] & indexbitff[4])), ((y_prenodeone_5_w[11] & (~ indexbitff[4])) | (y_prenodetwo_5_w[11] & indexbitff[4])), ((y_prenodeone_5_w[10] & (~ indexbitff[4]
)) | (y_prenodetwo_5_w[10] & indexbitff[4])), ((y_prenodeone_5_w[9] & (~ indexbitff[4])) | (y_prenodetwo_5_w[9] & indexbitff[4])), ((y_prenodeone_5_w[8] & (~ indexbitff[4])) | (y_prenodetwo_5_w[8] & indexbitff[4])), ((y_prenodeone_5_w[7] & (~ indexbitff[4])) | (y_prenodetwo_5_w[7] & indexbitff[4])), ((y_prenodeone_5_w[6] & (~ indexbitff[4])) | (y_prenodetwo_5_w[6] & indexbitff[4])), ((y_prenodeone_5_w[5] & (~ indexbitff[4])) | (y_prenodetwo_5_w[5] & indexbitff[4])), ((y_prenodeone_5_w[4] & (~ indexbitff[4])) | (y_prenodetwo_5_w[4] & indexbitff[4])), ((y_prenodeone_5_w[3] & (~ indexbitff[4])) | (y_prenodetwo_5_w[3] & indexbitff[4])), ((y_prenodeone_5_w[2] & (~ indexbitff[4])) | (y_prenodetwo_5_w[2] & indexbitff[4])), ((y_prenodeone_5_w[1] & (~ indexbitff[4])) | (y_prenodetwo_5_w[1] & indexbitff[4])), ((y_prenodeone_5_w[0] & (~ indexbitff[4])) | (y_prenodetwo_5_w[0] & indexbitff[4]))},
y_prenode_6_w = {((y_prenodeone_6_w[33] & (~ indexbitff[5])) | (y_prenodetwo_6_w[33] & indexbitff[5])), ((y_prenodeone_6_w[32] & (~ indexbitff[5])) | (y_prenodetwo_6_w[32] & indexbitff[5])), ((y_prenodeone_6_w[31] & (~ indexbitff[5])) | (y_prenodetwo_6_w[31] & indexbitff[5])), ((y_prenodeone_6_w[30] & (~ indexbitff[5])) | (y_prenodetwo_6_w[30] & indexbitff[5])), ((y_prenodeone_6_w[29] & (~ indexbitff[5])) | (y_prenodetwo_6_w[29] & indexbitff[5])), ((y_prenodeone_6_w[28] & (~ indexbitff[5])) | (y_prenodetwo_6_w[28] & indexbitff[5])), ((y_prenodeone_6_w[27] & (~ indexbitff[5])) | (y_prenodetwo_6_w[27] & indexbitff[5])), ((y_prenodeone_6_w[26] & (~ indexbitff[5])) | (y_prenodetwo_6_w[26] & indexbitff[5])), ((y_prenodeone_6_w[25] & (~ indexbitff[5])) | (y_prenodetwo_6_w[25] & indexbitff[5])), ((y_prenodeone_6_w[24] & (~ indexbitff[5])) | (y_prenodetwo_6_w[24] & indexbitff[5])), ((y_prenodeone_6_w[23] & (~ indexbitff[5])) | (y_prenodetwo_6_w[23] & indexbitff[5])), ((y_prenodeone_6_w[22] & (~ indexbitff[5])) | (y_prenodetwo_6_w[22] & indexbitff[5])), ((y_prenodeone_6_w[21] & (~ indexbitff[5])) | (y_prenodetwo_6_w[21] & indexbitff[5])), ((y_prenodeone_6_w[20] & (~ indexbitff[5])) | (y_prenodetwo_6_w[20] & indexbitff[5])), ((y_prenodeone_6_w[19] & (~ indexbitff[5])) | (y_prenodetwo_6_w[19] & indexbitff[5])), ((y_prenodeone_6_w[18] & (~ indexbitff[5])) | (y_prenodetwo_6_w[18] & indexbitff[5])), ((y_prenodeone_6_w[17] & (~ indexbitff[5])) | (y_prenodetwo_6_w[17] & indexbitff[5])), ((y_prenodeone_6_w[16] & (~ indexbitff[5])) | (y_prenodetwo_6_w[16] & indexbitff[5])), ((y_prenodeone_6_w[15] & (~ indexbitff[5])) | (y_prenodetwo_6_w[15] & indexbitff[5])), ((y_prenodeone_6_w[14] & (~ indexbitff[5])) | (y_prenodetwo_6_w[14] & indexbitff[5])), ((y_prenodeone_6_w[13] & (~ indexbitff[5])) | (y_prenodetwo_6_w[13] & indexbitff[5])), ((y_prenodeone_6_w[12] & (~ indexbitff[5])) | (y_prenodetwo_6_w[12] & indexbitff[5])), ((y_prenodeone_6_w[11] & (~ indexbitff[5])) | (y_prenodetwo_6_w[11] & indexbitff[5])), ((y_prenodeone_6_w[10] & (~ indexbitff[5]
)) | (y_prenodetwo_6_w[10] & indexbitff[5])), ((y_prenodeone_6_w[9] & (~ indexbitff[5])) | (y_prenodetwo_6_w[9] & indexbitff[5])), ((y_prenodeone_6_w[8] & (~ indexbitff[5])) | (y_prenodetwo_6_w[8] & indexbitff[5])), ((y_prenodeone_6_w[7] & (~ indexbitff[5])) | (y_prenodetwo_6_w[7] & indexbitff[5])), ((y_prenodeone_6_w[6] & (~ indexbitff[5])) | (y_prenodetwo_6_w[6] & indexbitff[5])), ((y_prenodeone_6_w[5] & (~ indexbitff[5])) | (y_prenodetwo_6_w[5] & indexbitff[5])), ((y_prenodeone_6_w[4] & (~ indexbitff[5])) | (y_prenodetwo_6_w[4] & indexbitff[5])), ((y_prenodeone_6_w[3] & (~ indexbitff[5])) | (y_prenodetwo_6_w[3] & indexbitff[5])), ((y_prenodeone_6_w[2] & (~ indexbitff[5])) | (y_prenodetwo_6_w[2] & indexbitff[5])), ((y_prenodeone_6_w[1] & (~ indexbitff[5])) | (y_prenodetwo_6_w[1] & indexbitff[5])), ((y_prenodeone_6_w[0] & (~ indexbitff[5])) | (y_prenodetwo_6_w[0] & indexbitff[5]))},
y_prenode_7_w = {((y_prenodeone_7_w[33] & (~ indexbitff[6])) | (y_prenodetwo_7_w[33] & indexbitff[6])), ((y_prenodeone_7_w[32] & (~ indexbitff[6])) | (y_prenodetwo_7_w[32] & indexbitff[6])), ((y_prenodeone_7_w[31] & (~ indexbitff[6])) | (y_prenodetwo_7_w[31] & indexbitff[6])), ((y_prenodeone_7_w[30] & (~ indexbitff[6])) | (y_prenodetwo_7_w[30] & indexbitff[6])), ((y_prenodeone_7_w[29] & (~ indexbitff[6])) | (y_prenodetwo_7_w[29] & indexbitff[6])), ((y_prenodeone_7_w[28] & (~ indexbitff[6])) | (y_prenodetwo_7_w[28] & indexbitff[6])), ((y_prenodeone_7_w[27] & (~ indexbitff[6])) | (y_prenodetwo_7_w[27] & indexbitff[6])), ((y_prenodeone_7_w[26] & (~ indexbitff[6])) | (y_prenodetwo_7_w[26] & indexbitff[6])), ((y_prenodeone_7_w[25] & (~ indexbitff[6])) | (y_prenodetwo_7_w[25] & indexbitff[6])), ((y_prenodeone_7_w[24] & (~ indexbitff[6])) | (y_prenodetwo_7_w[24] & indexbitff[6])), ((y_prenodeone_7_w[23] & (~ indexbitff[6])) | (y_prenodetwo_7_w[23] & indexbitff[6])), ((y_prenodeone_7_w[22] & (~ indexbitff[6])) | (y_prenodetwo_7_w[22] & indexbitff[6])), ((y_prenodeone_7_w[21] & (~ indexbitff[6])) | (y_prenodetwo_7_w[21] & indexbitff[6])), ((y_prenodeone_7_w[20] & (~ indexbitff[6])) | (y_prenodetwo_7_w[20] & indexbitff[6])), ((y_prenodeone_7_w[19] & (~ indexbitff[6])) | (y_prenodetwo_7_w[19] & indexbitff[6])), ((y_prenodeone_7_w[18] & (~ indexbitff[6])) | (y_prenodetwo_7_w[18] & indexbitff[6])), ((y_prenodeone_7_w[17] & (~ indexbitff[6])) | (y_prenodetwo_7_w[17] & indexbitff[6])), ((y_prenodeone_7_w[16] & (~ indexbitff[6])) | (y_prenodetwo_7_w[16] & indexbitff[6])), ((y_prenodeone_7_w[15] & (~ indexbitff[6])) | (y_prenodetwo_7_w[15] & indexbitff[6])), ((y_prenodeone_7_w[14] & (~ indexbitff[6])) | (y_prenodetwo_7_w[14] & indexbitff[6])), ((y_prenodeone_7_w[13] & (~ indexbitff[6])) | (y_prenodetwo_7_w[13] & indexbitff[6])), ((y_prenodeone_7_w[12] & (~ indexbitff[6])) | (y_prenodetwo_7_w[12] & indexbitff[6])), ((y_prenodeone_7_w[11] & (~ indexbitff[6])) | (y_prenodetwo_7_w[11] & indexbitff[6])), ((y_prenodeone_7_w[10] & (~ indexbitff[6]
)) | (y_prenodetwo_7_w[10] & indexbitff[6])), ((y_prenodeone_7_w[9] & (~ indexbitff[6])) | (y_prenodetwo_7_w[9] & indexbitff[6])), ((y_prenodeone_7_w[8] & (~ indexbitff[6])) | (y_prenodetwo_7_w[8] & indexbitff[6])), ((y_prenodeone_7_w[7] & (~ indexbitff[6])) | (y_prenodetwo_7_w[7] & indexbitff[6])), ((y_prenodeone_7_w[6] & (~ indexbitff[6])) | (y_prenodetwo_7_w[6] & indexbitff[6])), ((y_prenodeone_7_w[5] & (~ indexbitff[6])) | (y_prenodetwo_7_w[5] & indexbitff[6])), ((y_prenodeone_7_w[4] & (~ indexbitff[6])) | (y_prenodetwo_7_w[4] & indexbitff[6])), ((y_prenodeone_7_w[3] & (~ indexbitff[6])) | (y_prenodetwo_7_w[3] & indexbitff[6])), ((y_prenodeone_7_w[2] & (~ indexbitff[6])) | (y_prenodetwo_7_w[2] & indexbitff[6])), ((y_prenodeone_7_w[1] & (~ indexbitff[6])) | (y_prenodetwo_7_w[1] & indexbitff[6])), ((y_prenodeone_7_w[0] & (~ indexbitff[6])) | (y_prenodetwo_7_w[0] & indexbitff[6]))},
y_prenode_8_w = {((y_prenodeone_8_w[33] & (~ indexbitff[7])) | (y_prenodetwo_8_w[33] & indexbitff[7])), ((y_prenodeone_8_w[32] & (~ indexbitff[7])) | (y_prenodetwo_8_w[32] & indexbitff[7])), ((y_prenodeone_8_w[31] & (~ indexbitff[7])) | (y_prenodetwo_8_w[31] & indexbitff[7])), ((y_prenodeone_8_w[30] & (~ indexbitff[7])) | (y_prenodetwo_8_w[30] & indexbitff[7])), ((y_prenodeone_8_w[29] & (~ indexbitff[7])) | (y_prenodetwo_8_w[29] & indexbitff[7])), ((y_prenodeone_8_w[28] & (~ indexbitff[7])) | (y_prenodetwo_8_w[28] & indexbitff[7])), ((y_prenodeone_8_w[27] & (~ indexbitff[7])) | (y_prenodetwo_8_w[27] & indexbitff[7])), ((y_prenodeone_8_w[26] & (~ indexbitff[7])) | (y_prenodetwo_8_w[26] & indexbitff[7])), ((y_prenodeone_8_w[25] & (~ indexbitff[7])) | (y_prenodetwo_8_w[25] & indexbitff[7])), ((y_prenodeone_8_w[24] & (~ indexbitff[7])) | (y_prenodetwo_8_w[24] & indexbitff[7])), ((y_prenodeone_8_w[23] & (~ indexbitff[7])) | (y_prenodetwo_8_w[23] & indexbitff[7])), ((y_prenodeone_8_w[22] & (~ indexbitff[7])) | (y_prenodetwo_8_w[22] & indexbitff[7])), ((y_prenodeone_8_w[21] & (~ indexbitff[7])) | (y_prenodetwo_8_w[21] & indexbitff[7])), ((y_prenodeone_8_w[20] & (~ indexbitff[7])) | (y_prenodetwo_8_w[20] & indexbitff[7])), ((y_prenodeone_8_w[19] & (~ indexbitff[7])) | (y_prenodetwo_8_w[19] & indexbitff[7])), ((y_prenodeone_8_w[18] & (~ indexbitff[7])) | (y_prenodetwo_8_w[18] & indexbitff[7])), ((y_prenodeone_8_w[17] & (~ indexbitff[7])) | (y_prenodetwo_8_w[17] & indexbitff[7])), ((y_prenodeone_8_w[16] & (~ indexbitff[7])) | (y_prenodetwo_8_w[16] & indexbitff[7])), ((y_prenodeone_8_w[15] & (~ indexbitff[7])) | (y_prenodetwo_8_w[15] & indexbitff[7])), ((y_prenodeone_8_w[14] & (~ indexbitff[7])) | (y_prenodetwo_8_w[14] & indexbitff[7])), ((y_prenodeone_8_w[13] & (~ indexbitff[7])) | (y_prenodetwo_8_w[13] & indexbitff[7])), ((y_prenodeone_8_w[12] & (~ indexbitff[7])) | (y_prenodetwo_8_w[12] & indexbitff[7])), ((y_prenodeone_8_w[11] & (~ indexbitff[7])) | (y_prenodetwo_8_w[11] & indexbitff[7])), ((y_prenodeone_8_w[10] & (~ indexbitff[7]
)) | (y_prenodetwo_8_w[10] & indexbitff[7])), ((y_prenodeone_8_w[9] & (~ indexbitff[7])) | (y_prenodetwo_8_w[9] & indexbitff[7])), ((y_prenodeone_8_w[8] & (~ indexbitff[7])) | (y_prenodetwo_8_w[8] & indexbitff[7])), ((y_prenodeone_8_w[7] & (~ indexbitff[7])) | (y_prenodetwo_8_w[7] & indexbitff[7])), ((y_prenodeone_8_w[6] & (~ indexbitff[7])) | (y_prenodetwo_8_w[6] & indexbitff[7])), ((y_prenodeone_8_w[5] & (~ indexbitff[7])) | (y_prenodetwo_8_w[5] & indexbitff[7])), ((y_prenodeone_8_w[4] & (~ indexbitff[7])) | (y_prenodetwo_8_w[4] & indexbitff[7])), ((y_prenodeone_8_w[3] & (~ indexbitff[7])) | (y_prenodetwo_8_w[3] & indexbitff[7])), ((y_prenodeone_8_w[2] & (~ indexbitff[7])) | (y_prenodetwo_8_w[2] & indexbitff[7])), ((y_prenodeone_8_w[1] & (~ indexbitff[7])) | (y_prenodetwo_8_w[1] & indexbitff[7])), ((y_prenodeone_8_w[0] & (~ indexbitff[7])) | (y_prenodetwo_8_w[0] & indexbitff[7]))},
y_prenode_9_w = {((y_prenodeone_9_w[33] & (~ indexbitff[8])) | (y_prenodetwo_9_w[33] & indexbitff[8])), ((y_prenodeone_9_w[32] & (~ indexbitff[8])) | (y_prenodetwo_9_w[32] & indexbitff[8])), ((y_prenodeone_9_w[31] & (~ indexbitff[8])) | (y_prenodetwo_9_w[31] & indexbitff[8])), ((y_prenodeone_9_w[30] & (~ indexbitff[8])) | (y_prenodetwo_9_w[30] & indexbitff[8])), ((y_prenodeone_9_w[29] & (~ indexbitff[8])) | (y_prenodetwo_9_w[29] & indexbitff[8])), ((y_prenodeone_9_w[28] & (~ indexbitff[8])) | (y_prenodetwo_9_w[28] & indexbitff[8])), ((y_prenodeone_9_w[27] & (~ indexbitff[8])) | (y_prenodetwo_9_w[27] & indexbitff[8])), ((y_prenodeone_9_w[26] & (~ indexbitff[8])) | (y_prenodetwo_9_w[26] & indexbitff[8])), ((y_prenodeone_9_w[25] & (~ indexbitff[8])) | (y_prenodetwo_9_w[25] & indexbitff[8])), ((y_prenodeone_9_w[24] & (~ indexbitff[8])) | (y_prenodetwo_9_w[24] & indexbitff[8])), ((y_prenodeone_9_w[23] & (~ indexbitff[8])) | (y_prenodetwo_9_w[23] & indexbitff[8])), ((y_prenodeone_9_w[22] & (~ indexbitff[8])) | (y_prenodetwo_9_w[22] & indexbitff[8])), ((y_prenodeone_9_w[21] & (~ indexbitff[8])) | (y_prenodetwo_9_w[21] & indexbitff[8])), ((y_prenodeone_9_w[20] & (~ indexbitff[8])) | (y_prenodetwo_9_w[20] & indexbitff[8])), ((y_prenodeone_9_w[19] & (~ indexbitff[8])) | (y_prenodetwo_9_w[19] & indexbitff[8])), ((y_prenodeone_9_w[18] & (~ indexbitff[8])) | (y_prenodetwo_9_w[18] & indexbitff[8])), ((y_prenodeone_9_w[17] & (~ indexbitff[8])) | (y_prenodetwo_9_w[17] & indexbitff[8])), ((y_prenodeone_9_w[16] & (~ indexbitff[8])) | (y_prenodetwo_9_w[16] & indexbitff[8])), ((y_prenodeone_9_w[15] & (~ indexbitff[8])) | (y_prenodetwo_9_w[15] & indexbitff[8])), ((y_prenodeone_9_w[14] & (~ indexbitff[8])) | (y_prenodetwo_9_w[14] & indexbitff[8])), ((y_prenodeone_9_w[13] & (~ indexbitff[8])) | (y_prenodetwo_9_w[13] & indexbitff[8])), ((y_prenodeone_9_w[12] & (~ indexbitff[8])) | (y_prenodetwo_9_w[12] & indexbitff[8])), ((y_prenodeone_9_w[11] & (~ indexbitff[8])) | (y_prenodetwo_9_w[11] & indexbitff[8])), ((y_prenodeone_9_w[10] & (~ indexbitff[8]
)) | (y_prenodetwo_9_w[10] & indexbitff[8])), ((y_prenodeone_9_w[9] & (~ indexbitff[8])) | (y_prenodetwo_9_w[9] & indexbitff[8])), ((y_prenodeone_9_w[8] & (~ indexbitff[8])) | (y_prenodetwo_9_w[8] & indexbitff[8])), ((y_prenodeone_9_w[7] & (~ indexbitff[8])) | (y_prenodetwo_9_w[7] & indexbitff[8])), ((y_prenodeone_9_w[6] & (~ indexbitff[8])) | (y_prenodetwo_9_w[6] & indexbitff[8])), ((y_prenodeone_9_w[5] & (~ indexbitff[8])) | (y_prenodetwo_9_w[5] & indexbitff[8])), ((y_prenodeone_9_w[4] & (~ indexbitff[8])) | (y_prenodetwo_9_w[4] & indexbitff[8])), ((y_prenodeone_9_w[3] & (~ indexbitff[8])) | (y_prenodetwo_9_w[3] & indexbitff[8])), ((y_prenodeone_9_w[2] & (~ indexbitff[8])) | (y_prenodetwo_9_w[2] & indexbitff[8])), ((y_prenodeone_9_w[1] & (~ indexbitff[8])) | (y_prenodetwo_9_w[1] & indexbitff[8])), ((y_prenodeone_9_w[0] & (~ indexbitff[8])) | (y_prenodetwo_9_w[0] & indexbitff[8]))},
y_prenodeone_10_w = {{9{x_pipeff_9[33]}}, x_pipeff_9[33:9]},
y_prenodeone_11_w = {{10{x_pipeff_10[33]}}, x_pipeff_10[33:10]},
y_prenodeone_12_w = {{11{x_pipeff_11[33]}}, x_pipeff_11[33:11]},
y_prenodeone_13_w = {{12{x_pipeff_12[33]}}, x_pipeff_12[33:12]},
y_prenodeone_2_w = {x_pipeff_1[33], x_pipeff_1[33:1]},
y_prenodeone_3_w = {{2{x_pipeff_2[33]}}, x_pipeff_2[33:2]},
y_prenodeone_4_w = {{3{x_pipeff_3[33]}}, x_pipeff_3[33:3]},
y_prenodeone_5_w = {{4{x_pipeff_4[33]}}, x_pipeff_4[33:4]},
y_prenodeone_6_w = {{5{x_pipeff_5[33]}}, x_pipeff_5[33:5]},
y_prenodeone_7_w = {{6{x_pipeff_6[33]}}, x_pipeff_6[33:6]},
y_prenodeone_8_w = {{7{x_pipeff_7[33]}}, x_pipeff_7[33:7]},
y_prenodeone_9_w = {{8{x_pipeff_8[33]}}, x_pipeff_8[33:8]},
y_prenodetwo_10_w = {{11{x_pipeff_9[33]}}, x_pipeff_9[33:11]},
y_prenodetwo_11_w = {{12{x_pipeff_10[33]}}, x_pipeff_10[33:12]},
y_prenodetwo_12_w = {{13{x_pipeff_11[33]}}, x_pipeff_11[33:13]},
y_prenodetwo_13_w = {{14{x_pipeff_12[33]}}, x_pipeff_12[33:14]},
y_prenodetwo_2_w = {{3{x_pipeff_1[33]}}, x_pipeff_1[33:3]},
y_prenodetwo_3_w = {{4{x_pipeff_2[33]}}, x_pipeff_2[33:4]},
y_prenodetwo_4_w = {{5{x_pipeff_3[33]}}, x_pipeff_3[33:5]},
y_prenodetwo_5_w = {{6{x_pipeff_4[33]}}, x_pipeff_4[33:6]},
y_prenodetwo_6_w = {{7{x_pipeff_5[33]}}, x_pipeff_5[33:7]},
y_prenodetwo_7_w = {{8{x_pipeff_6[33]}}, x_pipeff_6[33:8]},
y_prenodetwo_8_w = {{9{x_pipeff_7[33]}}, x_pipeff_7[33:9]},
y_prenodetwo_9_w = {{10{x_pipeff_8[33]}}, x_pipeff_8[33:10]},
y_subnode_10_w = {(y_prenode_10_w[33] ^ z_pipeff_9[33]), (y_prenode_10_w[32] ^ z_pipeff_9[33]), (y_prenode_10_w[31] ^ z_pipeff_9[33]), (y_prenode_10_w[30] ^ z_pipeff_9[33]), (y_prenode_10_w[29] ^ z_pipeff_9[33]), (y_prenode_10_w[28] ^ z_pipeff_9[33]), (y_prenode_10_w[27] ^ z_pipeff_9[33]), (y_prenode_10_w[26] ^ z_pipeff_9[33]), (y_prenode_10_w[25] ^ z_pipeff_9[33]), (y_prenode_10_w[24] ^ z_pipeff_9[33]), (y_prenode_10_w[23] ^ z_pipeff_9[33]), (y_prenode_10_w[22] ^ z_pipeff_9[33]), (y_prenode_10_w[21] ^ z_pipeff_9[33]), (y_prenode_10_w[20] ^ z_pipeff_9[33]), (y_prenode_10_w[19] ^ z_pipeff_9[33]), (y_prenode_10_w[18] ^ z_pipeff_9[33]), (y_prenode_10_w[17] ^ z_pipeff_9[33]), (y_prenode_10_w[16] ^ z_pipeff_9[33]), (y_prenode_10_w[15] ^ z_pipeff_9[33]), (y_prenode_10_w[14] ^ z_pipeff_9[33]), (y_prenode_10_w[13] ^ z_pipeff_9[33]), (y_prenode_10_w[12] ^ z_pipeff_9[33]), (y_prenode_10_w[11] ^ z_pipeff_9[33]), (y_prenode_10_w[10] ^ z_pipeff_9[33]), (y_prenode_10_w[9] ^ z_pipeff_9[33]), (y_prenode_10_w[8] ^ z_pipeff_9[33]), (y_prenode_10_w[7] ^ z_pipeff_9[33]), (y_prenode_10_w[6] ^ z_pipeff_9[33]), (y_prenode_10_w[5] ^ z_pipeff_9[33]), (y_prenode_10_w[4] ^ z_pipeff_9[33]), (y_prenode_10_w[3] ^ z_pipeff_9[33]), (y_prenode_10_w[2] ^ z_pipeff_9[33]), (y_prenode_10_w[1] ^ z_pipeff_9[33]), (y_prenode_10_w[0] ^ z_pipeff_9[33])},
y_subnode_11_w = {(y_prenode_11_w[33] ^ z_pipeff_10[33]), (y_prenode_11_w[32] ^ z_pipeff_10[33]), (y_prenode_11_w[31] ^ z_pipeff_10[33]), (y_prenode_11_w[30] ^ z_pipeff_10[33]), (y_prenode_11_w[29] ^ z_pipeff_10[33]), (y_prenode_11_w[28] ^ z_pipeff_10[33]), (y_prenode_11_w[27] ^ z_pipeff_10[33]), (y_prenode_11_w[26] ^ z_pipeff_10[33]), (y_prenode_11_w[25] ^ z_pipeff_10[33]), (y_prenode_11_w[24] ^ z_pipeff_10[33]), (y_prenode_11_w[23] ^ z_pipeff_10[33]), (y_prenode_11_w[22] ^ z_pipeff_10[33]), (y_prenode_11_w[21] ^ z_pipeff_10[33]), (y_prenode_11_w[20] ^ z_pipeff_10[33]), (y_prenode_11_w[19] ^ z_pipeff_10[33]), (y_prenode_11_w[18] ^ z_pipeff_10[33]), (y_prenode_11_w[17] ^ z_pipeff_10[33]), (y_prenode_11_w[16] ^ z_pipeff_10[33]), (y_prenode_11_w[15] ^ z_pipeff_10[33]), (y_prenode_11_w[14] ^ z_pipeff_10[33]), (y_prenode_11_w[13] ^ z_pipeff_10[33]), (y_prenode_11_w[12] ^ z_pipeff_10[33]), (y_prenode_11_w[11] ^ z_pipeff_10[33]), (y_prenode_11_w[10] ^ z_pipeff_10[33]), (y_prenode_11_w[9] ^ z_pipeff_10[33]), (y_prenode_11_w[8] ^ z_pipeff_10[33]), (y_prenode_11_w[7] ^ z_pipeff_10[33]), (y_prenode_11_w[6] ^ z_pipeff_10[33]), (y_prenode_11_w[5] ^ z_pipeff_10[33]), (y_prenode_11_w[4] ^ z_pipeff_10[33]), (y_prenode_11_w[3] ^ z_pipeff_10[33]), (y_prenode_11_w[2] ^ z_pipeff_10[33]), (y_prenode_11_w[1] ^ z_pipeff_10[33]), (y_prenode_11_w[0] ^ z_pipeff_10[33])},
y_subnode_12_w = {(y_prenode_12_w[33] ^ z_pipeff_11[33]), (y_prenode_12_w[32] ^ z_pipeff_11[33]), (y_prenode_12_w[31] ^ z_pipeff_11[33]), (y_prenode_12_w[30] ^ z_pipeff_11[33]), (y_prenode_12_w[29] ^ z_pipeff_11[33]), (y_prenode_12_w[28] ^ z_pipeff_11[33]), (y_prenode_12_w[27] ^ z_pipeff_11[33]), (y_prenode_12_w[26] ^ z_pipeff_11[33]), (y_prenode_12_w[25] ^ z_pipeff_11[33]), (y_prenode_12_w[24] ^ z_pipeff_11[33]), (y_prenode_12_w[23] ^ z_pipeff_11[33]), (y_prenode_12_w[22] ^ z_pipeff_11[33]), (y_prenode_12_w[21] ^ z_pipeff_11[33]), (y_prenode_12_w[20] ^ z_pipeff_11[33]), (y_prenode_12_w[19] ^ z_pipeff_11[33]), (y_prenode_12_w[18] ^ z_pipeff_11[33]), (y_prenode_12_w[17] ^ z_pipeff_11[33]), (y_prenode_12_w[16] ^ z_pipeff_11[33]), (y_prenode_12_w[15] ^ z_pipeff_11[33]), (y_prenode_12_w[14] ^ z_pipeff_11[33]), (y_prenode_12_w[13] ^ z_pipeff_11[33]), (y_prenode_12_w[12] ^ z_pipeff_11[33]), (y_prenode_12_w[11] ^ z_pipeff_11[33]), (y_prenode_12_w[10] ^ z_pipeff_11[33]), (y_prenode_12_w[9] ^ z_pipeff_11[33]), (y_prenode_12_w[8] ^ z_pipeff_11[33]), (y_prenode_12_w[7] ^ z_pipeff_11[33]), (y_prenode_12_w[6] ^ z_pipeff_11[33]), (y_prenode_12_w[5] ^ z_pipeff_11[33]), (y_prenode_12_w[4] ^ z_pipeff_11[33]), (y_prenode_12_w[3] ^ z_pipeff_11[33]), (y_prenode_12_w[2] ^ z_pipeff_11[33]), (y_prenode_12_w[1] ^ z_pipeff_11[33]), (y_prenode_12_w[0] ^ z_pipeff_11[33])},
y_subnode_13_w = {(y_prenode_13_w[33] ^ z_pipeff_12[33]), (y_prenode_13_w[32] ^ z_pipeff_12[33]), (y_prenode_13_w[31] ^ z_pipeff_12[33]), (y_prenode_13_w[30] ^ z_pipeff_12[33]), (y_prenode_13_w[29] ^ z_pipeff_12[33]), (y_prenode_13_w[28] ^ z_pipeff_12[33]), (y_prenode_13_w[27] ^ z_pipeff_12[33]), (y_prenode_13_w[26] ^ z_pipeff_12[33]), (y_prenode_13_w[25] ^ z_pipeff_12[33]), (y_prenode_13_w[24] ^ z_pipeff_12[33]), (y_prenode_13_w[23] ^ z_pipeff_12[33]), (y_prenode_13_w[22] ^ z_pipeff_12[33]), (y_prenode_13_w[21] ^ z_pipeff_12[33]), (y_prenode_13_w[20] ^ z_pipeff_12[33]), (y_prenode_13_w[19] ^ z_pipeff_12[33]), (y_prenode_13_w[18] ^ z_pipeff_12[33]), (y_prenode_13_w[17] ^ z_pipeff_12[33]), (y_prenode_13_w[16] ^ z_pipeff_12[33]), (y_prenode_13_w[15] ^ z_pipeff_12[33]), (y_prenode_13_w[14] ^ z_pipeff_12[33]), (y_prenode_13_w[13] ^ z_pipeff_12[33]), (y_prenode_13_w[12] ^ z_pipeff_12[33]), (y_prenode_13_w[11] ^ z_pipeff_12[33]), (y_prenode_13_w[10] ^ z_pipeff_12[33]), (y_prenode_13_w[9] ^ z_pipeff_12[33]), (y_prenode_13_w[8] ^ z_pipeff_12[33]), (y_prenode_13_w[7] ^ z_pipeff_12[33]), (y_prenode_13_w[6] ^ z_pipeff_12[33]), (y_prenode_13_w[5] ^ z_pipeff_12[33]), (y_prenode_13_w[4] ^ z_pipeff_12[33]), (y_prenode_13_w[3] ^ z_pipeff_12[33]), (y_prenode_13_w[2] ^ z_pipeff_12[33]), (y_prenode_13_w[1] ^ z_pipeff_12[33]), (y_prenode_13_w[0] ^ z_pipeff_12[33])},
y_subnode_1_w = {(x_pipeff_0[33] & (~ indexbitff[0])), (x_pipeff_0[32] & (~ indexbitff[0])), ((x_pipeff_0[31] & (~ indexbitff[0])) | (x_pipeff_0[33] & indexbitff[0])), ((x_pipeff_0[30] & (~ indexbitff[0])) | (x_pipeff_0[32] & indexbitff[0])), ((x_pipeff_0[29] & (~ indexbitff[0])) | (x_pipeff_0[31] & indexbitff[0])), ((x_pipeff_0[28] & (~ indexbitff[0])) | (x_pipeff_0[30] & indexbitff[0])), ((x_pipeff_0[27] & (~ indexbitff[0])) | (x_pipeff_0[29] & indexbitff[0])), ((x_pipeff_0[26] & (~ indexbitff[0])) | (x_pipeff_0[28] & indexbitff[0])), ((x_pipeff_0[25] & (~ indexbitff[0])) | (x_pipeff_0[27] & indexbitff[0])), ((x_pipeff_0[24] & (~ indexbitff[0])) | (x_pipeff_0[26] & indexbitff[0])), ((x_pipeff_0[23] & (~ indexbitff[0])) | (x_pipeff_0[25] & indexbitff[0])), ((x_pipeff_0[22] & (~ indexbitff[0])) | (x_pipeff_0[24] & indexbitff[0])), ((x_pipeff_0[21] & (~ indexbitff[0])) | (x_pipeff_0[23] & indexbitff[0])), ((x_pipeff_0[20] & (~ indexbitff[0])) | (x_pipeff_0[22] & indexbitff[0])), ((x_pipeff_0[19] & (~ indexbitff[0])) | (x_pipeff_0[21] & indexbitff[0])), ((x_pipeff_0[18] & (~ indexbitff[0])) | (x_pipeff_0[20] & indexbitff[0])), ((x_pipeff_0[17] & (~ indexbitff[0])) | (x_pipeff_0[19] & indexbitff[0])), ((x_pipeff_0[16] & (~ indexbitff[0])) | (x_pipeff_0[18] & indexbitff[0])), ((x_pipeff_0[15] & (~ indexbitff[0])) | (x_pipeff_0[17] & indexbitff[0])), ((x_pipeff_0[14] & (~ indexbitff[0])) | (x_pipeff_0[16] & indexbitff[0])), ((x_pipeff_0[13] & (~ indexbitff[0])) | (x_pipeff_0[15] & indexbitff[0])), ((x_pipeff_0[12] & (~ indexbitff[0])) | (x_pipeff_0[14] & indexbitff[0])), ((x_pipeff_0[11] & (~ indexbitff[0])) | (x_pipeff_0[13] & indexbitff[0])), ((x_pipeff_0[10] & (~ indexbitff[0])) | (x_pipeff_0[12] & indexbitff[0])), ((x_pipeff_0[9] & (~ indexbitff[0])) | (x_pipeff_0[11] & indexbitff[0])), ((x_pipeff_0[8] & (~ indexbitff[0])) | (x_pipeff_0[10] & indexbitff[0])), ((x_pipeff_0[7] & (~ indexbitff[0])) | (x_pipeff_0[9] & indexbitff[0])), ((x_pipeff_0[6] & (~ indexbitff[0])) | (x_pipeff_0[8] & indexbitff[0])), ((x_pipeff_0[5]
& (~ indexbitff[0])) | (x_pipeff_0[7] & indexbitff[0])), ((x_pipeff_0[4] & (~ indexbitff[0])) | (x_pipeff_0[6] & indexbitff[0])), ((x_pipeff_0[3] & (~ indexbitff[0])) | (x_pipeff_0[5] & indexbitff[0])), ((x_pipeff_0[2] & (~ indexbitff[0])) | (x_pipeff_0[4] & indexbitff[0])), ((x_pipeff_0[1] & (~ indexbitff[0])) | (x_pipeff_0[3] & indexbitff[0])), ((x_pipeff_0[0] & (~ indexbitff[0])) | (x_pipeff_0[2] & indexbitff[0]))},
y_subnode_2_w = {(y_prenode_2_w[33] ^ z_pipeff_1[33]), (y_prenode_2_w[32] ^ z_pipeff_1[33]), (y_prenode_2_w[31] ^ z_pipeff_1[33]), (y_prenode_2_w[30] ^ z_pipeff_1[33]), (y_prenode_2_w[29] ^ z_pipeff_1[33]), (y_prenode_2_w[28] ^ z_pipeff_1[33]), (y_prenode_2_w[27] ^ z_pipeff_1[33]), (y_prenode_2_w[26] ^ z_pipeff_1[33]), (y_prenode_2_w[25] ^ z_pipeff_1[33]), (y_prenode_2_w[24] ^ z_pipeff_1[33]), (y_prenode_2_w[23] ^ z_pipeff_1[33]), (y_prenode_2_w[22] ^ z_pipeff_1[33]), (y_prenode_2_w[21] ^ z_pipeff_1[33]), (y_prenode_2_w[20] ^ z_pipeff_1[33]), (y_prenode_2_w[19] ^ z_pipeff_1[33]), (y_prenode_2_w[18] ^ z_pipeff_1[33]), (y_prenode_2_w[17] ^ z_pipeff_1[33]), (y_prenode_2_w[16] ^ z_pipeff_1[33]), (y_prenode_2_w[15] ^ z_pipeff_1[33]), (y_prenode_2_w[14] ^ z_pipeff_1[33]), (y_prenode_2_w[13] ^ z_pipeff_1[33]), (y_prenode_2_w[12] ^ z_pipeff_1[33]), (y_prenode_2_w[11] ^ z_pipeff_1[33]), (y_prenode_2_w[10] ^ z_pipeff_1[33]), (y_prenode_2_w[9] ^ z_pipeff_1[33]), (y_prenode_2_w[8] ^ z_pipeff_1[33]), (y_prenode_2_w[7] ^ z_pipeff_1[33]), (y_prenode_2_w[6] ^ z_pipeff_1[33]), (y_prenode_2_w[5] ^ z_pipeff_1[33]), (y_prenode_2_w[4] ^ z_pipeff_1[33]), (y_prenode_2_w[3] ^ z_pipeff_1[33]), (y_prenode_2_w[2] ^ z_pipeff_1[33]), (y_prenode_2_w[1] ^ z_pipeff_1[33]), (y_prenode_2_w[0] ^ z_pipeff_1[33])},
y_subnode_3_w = {(y_prenode_3_w[33] ^ z_pipeff_2[33]), (y_prenode_3_w[32] ^ z_pipeff_2[33]), (y_prenode_3_w[31] ^ z_pipeff_2[33]), (y_prenode_3_w[30] ^ z_pipeff_2[33]), (y_prenode_3_w[29] ^ z_pipeff_2[33]), (y_prenode_3_w[28] ^ z_pipeff_2[33]), (y_prenode_3_w[27] ^ z_pipeff_2[33]), (y_prenode_3_w[26] ^ z_pipeff_2[33]), (y_prenode_3_w[25] ^ z_pipeff_2[33]), (y_prenode_3_w[24] ^ z_pipeff_2[33]), (y_prenode_3_w[23] ^ z_pipeff_2[33]), (y_prenode_3_w[22] ^ z_pipeff_2[33]), (y_prenode_3_w[21] ^ z_pipeff_2[33]), (y_prenode_3_w[20] ^ z_pipeff_2[33]), (y_prenode_3_w[19] ^ z_pipeff_2[33]), (y_prenode_3_w[18] ^ z_pipeff_2[33]), (y_prenode_3_w[17] ^ z_pipeff_2[33]), (y_prenode_3_w[16] ^ z_pipeff_2[33]), (y_prenode_3_w[15] ^ z_pipeff_2[33]), (y_prenode_3_w[14] ^ z_pipeff_2[33]), (y_prenode_3_w[13] ^ z_pipeff_2[33]), (y_prenode_3_w[12] ^ z_pipeff_2[33]), (y_prenode_3_w[11] ^ z_pipeff_2[33]), (y_prenode_3_w[10] ^ z_pipeff_2[33]), (y_prenode_3_w[9] ^ z_pipeff_2[33]), (y_prenode_3_w[8] ^ z_pipeff_2[33]), (y_prenode_3_w[7] ^ z_pipeff_2[33]), (y_prenode_3_w[6] ^ z_pipeff_2[33]), (y_prenode_3_w[5] ^ z_pipeff_2[33]), (y_prenode_3_w[4] ^ z_pipeff_2[33]), (y_prenode_3_w[3] ^ z_pipeff_2[33]), (y_prenode_3_w[2] ^ z_pipeff_2[33]), (y_prenode_3_w[1] ^ z_pipeff_2[33]), (y_prenode_3_w[0] ^ z_pipeff_2[33])},
y_subnode_4_w = {(y_prenode_4_w[33] ^ z_pipeff_3[33]), (y_prenode_4_w[32] ^ z_pipeff_3[33]), (y_prenode_4_w[31] ^ z_pipeff_3[33]), (y_prenode_4_w[30] ^ z_pipeff_3[33]), (y_prenode_4_w[29] ^ z_pipeff_3[33]), (y_prenode_4_w[28] ^ z_pipeff_3[33]), (y_prenode_4_w[27] ^ z_pipeff_3[33]), (y_prenode_4_w[26] ^ z_pipeff_3[33]), (y_prenode_4_w[25] ^ z_pipeff_3[33]), (y_prenode_4_w[24] ^ z_pipeff_3[33]), (y_prenode_4_w[23] ^ z_pipeff_3[33]), (y_prenode_4_w[22] ^ z_pipeff_3[33]), (y_prenode_4_w[21] ^ z_pipeff_3[33]), (y_prenode_4_w[20] ^ z_pipeff_3[33]), (y_prenode_4_w[19] ^ z_pipeff_3[33]), (y_prenode_4_w[18] ^ z_pipeff_3[33]), (y_prenode_4_w[17] ^ z_pipeff_3[33]), (y_prenode_4_w[16] ^ z_pipeff_3[33]), (y_prenode_4_w[15] ^ z_pipeff_3[33]), (y_prenode_4_w[14] ^ z_pipeff_3[33]), (y_prenode_4_w[13] ^ z_pipeff_3[33]), (y_prenode_4_w[12] ^ z_pipeff_3[33]), (y_prenode_4_w[11] ^ z_pipeff_3[33]), (y_prenode_4_w[10] ^ z_pipeff_3[33]), (y_prenode_4_w[9] ^ z_pipeff_3[33]), (y_prenode_4_w[8] ^ z_pipeff_3[33]), (y_prenode_4_w[7] ^ z_pipeff_3[33]), (y_prenode_4_w[6] ^ z_pipeff_3[33]), (y_prenode_4_w[5] ^ z_pipeff_3[33]), (y_prenode_4_w[4] ^ z_pipeff_3[33]), (y_prenode_4_w[3] ^ z_pipeff_3[33]), (y_prenode_4_w[2] ^ z_pipeff_3[33]), (y_prenode_4_w[1] ^ z_pipeff_3[33]), (y_prenode_4_w[0] ^ z_pipeff_3[33])},
y_subnode_5_w = {(y_prenode_5_w[33] ^ z_pipeff_4[33]), (y_prenode_5_w[32] ^ z_pipeff_4[33]), (y_prenode_5_w[31] ^ z_pipeff_4[33]), (y_prenode_5_w[30] ^ z_pipeff_4[33]), (y_prenode_5_w[29] ^ z_pipeff_4[33]), (y_prenode_5_w[28] ^ z_pipeff_4[33]), (y_prenode_5_w[27] ^ z_pipeff_4[33]), (y_prenode_5_w[26] ^ z_pipeff_4[33]), (y_prenode_5_w[25] ^ z_pipeff_4[33]), (y_prenode_5_w[24] ^ z_pipeff_4[33]), (y_prenode_5_w[23] ^ z_pipeff_4[33]), (y_prenode_5_w[22] ^ z_pipeff_4[33]), (y_prenode_5_w[21] ^ z_pipeff_4[33]), (y_prenode_5_w[20] ^ z_pipeff_4[33]), (y_prenode_5_w[19] ^ z_pipeff_4[33]), (y_prenode_5_w[18] ^ z_pipeff_4[33]), (y_prenode_5_w[17] ^ z_pipeff_4[33]), (y_prenode_5_w[16] ^ z_pipeff_4[33]), (y_prenode_5_w[15] ^ z_pipeff_4[33]), (y_prenode_5_w[14] ^ z_pipeff_4[33]), (y_prenode_5_w[13] ^ z_pipeff_4[33]), (y_prenode_5_w[12] ^ z_pipeff_4[33]), (y_prenode_5_w[11] ^ z_pipeff_4[33]), (y_prenode_5_w[10] ^ z_pipeff_4[33]), (y_prenode_5_w[9] ^ z_pipeff_4[33]), (y_prenode_5_w[8] ^ z_pipeff_4[33]), (y_prenode_5_w[7] ^ z_pipeff_4[33]), (y_prenode_5_w[6] ^ z_pipeff_4[33]), (y_prenode_5_w[5] ^ z_pipeff_4[33]), (y_prenode_5_w[4] ^ z_pipeff_4[33]), (y_prenode_5_w[3] ^ z_pipeff_4[33]), (y_prenode_5_w[2] ^ z_pipeff_4[33]), (y_prenode_5_w[1] ^ z_pipeff_4[33]), (y_prenode_5_w[0] ^ z_pipeff_4[33])},
y_subnode_6_w = {(y_prenode_6_w[33] ^ z_pipeff_5[33]), (y_prenode_6_w[32] ^ z_pipeff_5[33]), (y_prenode_6_w[31] ^ z_pipeff_5[33]), (y_prenode_6_w[30] ^ z_pipeff_5[33]), (y_prenode_6_w[29] ^ z_pipeff_5[33]), (y_prenode_6_w[28] ^ z_pipeff_5[33]), (y_prenode_6_w[27] ^ z_pipeff_5[33]), (y_prenode_6_w[26] ^ z_pipeff_5[33]), (y_prenode_6_w[25] ^ z_pipeff_5[33]), (y_prenode_6_w[24] ^ z_pipeff_5[33]), (y_prenode_6_w[23] ^ z_pipeff_5[33]), (y_prenode_6_w[22] ^ z_pipeff_5[33]), (y_prenode_6_w[21] ^ z_pipeff_5[33]), (y_prenode_6_w[20] ^ z_pipeff_5[33]), (y_prenode_6_w[19] ^ z_pipeff_5[33]), (y_prenode_6_w[18] ^ z_pipeff_5[33]), (y_prenode_6_w[17] ^ z_pipeff_5[33]), (y_prenode_6_w[16] ^ z_pipeff_5[33]), (y_prenode_6_w[15] ^ z_pipeff_5[33]), (y_prenode_6_w[14] ^ z_pipeff_5[33]), (y_prenode_6_w[13] ^ z_pipeff_5[33]), (y_prenode_6_w[12] ^ z_pipeff_5[33]), (y_prenode_6_w[11] ^ z_pipeff_5[33]), (y_prenode_6_w[10] ^ z_pipeff_5[33]), (y_prenode_6_w[9] ^ z_pipeff_5[33]), (y_prenode_6_w[8] ^ z_pipeff_5[33]), (y_prenode_6_w[7] ^ z_pipeff_5[33]), (y_prenode_6_w[6] ^ z_pipeff_5[33]), (y_prenode_6_w[5] ^ z_pipeff_5[33]), (y_prenode_6_w[4] ^ z_pipeff_5[33]), (y_prenode_6_w[3] ^ z_pipeff_5[33]), (y_prenode_6_w[2] ^ z_pipeff_5[33]), (y_prenode_6_w[1] ^ z_pipeff_5[33]), (y_prenode_6_w[0] ^ z_pipeff_5[33])},
y_subnode_7_w = {(y_prenode_7_w[33] ^ z_pipeff_6[33]), (y_prenode_7_w[32] ^ z_pipeff_6[33]), (y_prenode_7_w[31] ^ z_pipeff_6[33]), (y_prenode_7_w[30] ^ z_pipeff_6[33]), (y_prenode_7_w[29] ^ z_pipeff_6[33]), (y_prenode_7_w[28] ^ z_pipeff_6[33]), (y_prenode_7_w[27] ^ z_pipeff_6[33]), (y_prenode_7_w[26] ^ z_pipeff_6[33]), (y_prenode_7_w[25] ^ z_pipeff_6[33]), (y_prenode_7_w[24] ^ z_pipeff_6[33]), (y_prenode_7_w[23] ^ z_pipeff_6[33]), (y_prenode_7_w[22] ^ z_pipeff_6[33]), (y_prenode_7_w[21] ^ z_pipeff_6[33]), (y_prenode_7_w[20] ^ z_pipeff_6[33]), (y_prenode_7_w[19] ^ z_pipeff_6[33]), (y_prenode_7_w[18] ^ z_pipeff_6[33]), (y_prenode_7_w[17] ^ z_pipeff_6[33]), (y_prenode_7_w[16] ^ z_pipeff_6[33]), (y_prenode_7_w[15] ^ z_pipeff_6[33]), (y_prenode_7_w[14] ^ z_pipeff_6[33]), (y_prenode_7_w[13] ^ z_pipeff_6[33]), (y_prenode_7_w[12] ^ z_pipeff_6[33]), (y_prenode_7_w[11] ^ z_pipeff_6[33]), (y_prenode_7_w[10] ^ z_pipeff_6[33]), (y_prenode_7_w[9] ^ z_pipeff_6[33]), (y_prenode_7_w[8] ^ z_pipeff_6[33]), (y_prenode_7_w[7] ^ z_pipeff_6[33]), (y_prenode_7_w[6] ^ z_pipeff_6[33]), (y_prenode_7_w[5] ^ z_pipeff_6[33]), (y_prenode_7_w[4] ^ z_pipeff_6[33]), (y_prenode_7_w[3] ^ z_pipeff_6[33]), (y_prenode_7_w[2] ^ z_pipeff_6[33]), (y_prenode_7_w[1] ^ z_pipeff_6[33]), (y_prenode_7_w[0] ^ z_pipeff_6[33])},
y_subnode_8_w = {(y_prenode_8_w[33] ^ z_pipeff_7[33]), (y_prenode_8_w[32] ^ z_pipeff_7[33]), (y_prenode_8_w[31] ^ z_pipeff_7[33]), (y_prenode_8_w[30] ^ z_pipeff_7[33]), (y_prenode_8_w[29] ^ z_pipeff_7[33]), (y_prenode_8_w[28] ^ z_pipeff_7[33]), (y_prenode_8_w[27] ^ z_pipeff_7[33]), (y_prenode_8_w[26] ^ z_pipeff_7[33]), (y_prenode_8_w[25] ^ z_pipeff_7[33]), (y_prenode_8_w[24] ^ z_pipeff_7[33]), (y_prenode_8_w[23] ^ z_pipeff_7[33]), (y_prenode_8_w[22] ^ z_pipeff_7[33]), (y_prenode_8_w[21] ^ z_pipeff_7[33]), (y_prenode_8_w[20] ^ z_pipeff_7[33]), (y_prenode_8_w[19] ^ z_pipeff_7[33]), (y_prenode_8_w[18] ^ z_pipeff_7[33]), (y_prenode_8_w[17] ^ z_pipeff_7[33]), (y_prenode_8_w[16] ^ z_pipeff_7[33]), (y_prenode_8_w[15] ^ z_pipeff_7[33]), (y_prenode_8_w[14] ^ z_pipeff_7[33]), (y_prenode_8_w[13] ^ z_pipeff_7[33]), (y_prenode_8_w[12] ^ z_pipeff_7[33]), (y_prenode_8_w[11] ^ z_pipeff_7[33]), (y_prenode_8_w[10] ^ z_pipeff_7[33]), (y_prenode_8_w[9] ^ z_pipeff_7[33]), (y_prenode_8_w[8] ^ z_pipeff_7[33]), (y_prenode_8_w[7] ^ z_pipeff_7[33]), (y_prenode_8_w[6] ^ z_pipeff_7[33]), (y_prenode_8_w[5] ^ z_pipeff_7[33]), (y_prenode_8_w[4] ^ z_pipeff_7[33]), (y_prenode_8_w[3] ^ z_pipeff_7[33]), (y_prenode_8_w[2] ^ z_pipeff_7[33]), (y_prenode_8_w[1] ^ z_pipeff_7[33]), (y_prenode_8_w[0] ^ z_pipeff_7[33])},
y_subnode_9_w = {(y_prenode_9_w[33] ^ z_pipeff_8[33]), (y_prenode_9_w[32] ^ z_pipeff_8[33]), (y_prenode_9_w[31] ^ z_pipeff_8[33]), (y_prenode_9_w[30] ^ z_pipeff_8[33]), (y_prenode_9_w[29] ^ z_pipeff_8[33]), (y_prenode_9_w[28] ^ z_pipeff_8[33]), (y_prenode_9_w[27] ^ z_pipeff_8[33]), (y_prenode_9_w[26] ^ z_pipeff_8[33]), (y_prenode_9_w[25] ^ z_pipeff_8[33]), (y_prenode_9_w[24] ^ z_pipeff_8[33]), (y_prenode_9_w[23] ^ z_pipeff_8[33]), (y_prenode_9_w[22] ^ z_pipeff_8[33]), (y_prenode_9_w[21] ^ z_pipeff_8[33]), (y_prenode_9_w[20] ^ z_pipeff_8[33]), (y_prenode_9_w[19] ^ z_pipeff_8[33]), (y_prenode_9_w[18] ^ z_pipeff_8[33]), (y_prenode_9_w[17] ^ z_pipeff_8[33]), (y_prenode_9_w[16] ^ z_pipeff_8[33]), (y_prenode_9_w[15] ^ z_pipeff_8[33]), (y_prenode_9_w[14] ^ z_pipeff_8[33]), (y_prenode_9_w[13] ^ z_pipeff_8[33]), (y_prenode_9_w[12] ^ z_pipeff_8[33]), (y_prenode_9_w[11] ^ z_pipeff_8[33]), (y_prenode_9_w[10] ^ z_pipeff_8[33]), (y_prenode_9_w[9] ^ z_pipeff_8[33]), (y_prenode_9_w[8] ^ z_pipeff_8[33]), (y_prenode_9_w[7] ^ z_pipeff_8[33]), (y_prenode_9_w[6] ^ z_pipeff_8[33]), (y_prenode_9_w[5] ^ z_pipeff_8[33]), (y_prenode_9_w[4] ^ z_pipeff_8[33]), (y_prenode_9_w[3] ^ z_pipeff_8[33]), (y_prenode_9_w[2] ^ z_pipeff_8[33]), (y_prenode_9_w[1] ^ z_pipeff_8[33]), (y_prenode_9_w[0] ^ z_pipeff_8[33])},
z_pipenode_10_w = wire_z_pipenode_10_add_result,
z_pipenode_11_w = wire_z_pipenode_11_add_result,
z_pipenode_12_w = wire_z_pipenode_12_add_result,
z_pipenode_13_w = wire_z_pipenode_13_add_result,
z_pipenode_2_w = wire_z_pipenode_2_add_result,
z_pipenode_3_w = wire_z_pipenode_3_add_result,
z_pipenode_4_w = wire_z_pipenode_4_add_result,
z_pipenode_5_w = wire_z_pipenode_5_add_result,
z_pipenode_6_w = wire_z_pipenode_6_add_result,
z_pipenode_7_w = wire_z_pipenode_7_add_result,
z_pipenode_8_w = wire_z_pipenode_8_add_result,
z_pipenode_9_w = wire_z_pipenode_9_add_result,
z_subnode_10_w = {((~ atannode_9_w[33]) ^ z_pipeff_9[33]), ((~ atannode_9_w[32]) ^ z_pipeff_9[33]), ((~ atannode_9_w[31]) ^ z_pipeff_9[33]), ((~ atannode_9_w[30]) ^ z_pipeff_9[33]), ((~ atannode_9_w[29]) ^ z_pipeff_9[33]), ((~ atannode_9_w[28]) ^ z_pipeff_9[33]), ((~ atannode_9_w[27]) ^ z_pipeff_9[33]), ((~ atannode_9_w[26]) ^ z_pipeff_9[33]), ((~ atannode_9_w[25]) ^ z_pipeff_9[33]), ((~ atannode_9_w[24]) ^ z_pipeff_9[33]), ((~ atannode_9_w[23]) ^ z_pipeff_9[33]), ((~ atannode_9_w[22]) ^ z_pipeff_9[33]), ((~ atannode_9_w[21]) ^ z_pipeff_9[33]), ((~ atannode_9_w[20]) ^ z_pipeff_9[33]), ((~ atannode_9_w[19]) ^ z_pipeff_9[33]), ((~ atannode_9_w[18]) ^ z_pipeff_9[33]), ((~ atannode_9_w[17]) ^ z_pipeff_9[33]), ((~ atannode_9_w[16]) ^ z_pipeff_9[33]), ((~ atannode_9_w[15]) ^ z_pipeff_9[33]), ((~ atannode_9_w[14]) ^ z_pipeff_9[33]), ((~ atannode_9_w[13]) ^ z_pipeff_9[33]), ((~ atannode_9_w[12]) ^ z_pipeff_9[33]), ((~ atannode_9_w[11]) ^ z_pipeff_9[33]), ((~ atannode_9_w[10]) ^ z_pipeff_9[33]), ((~ atannode_9_w[9]) ^ z_pipeff_9[33]), ((~ atannode_9_w[8]) ^ z_pipeff_9[33]), ((~ atannode_9_w[7]) ^ z_pipeff_9[33]), ((~ atannode_9_w[6]) ^ z_pipeff_9[33]), ((~ atannode_9_w[5]) ^ z_pipeff_9[33]), ((~ atannode_9_w[4]) ^ z_pipeff_9[33]), ((~ atannode_9_w[3]) ^ z_pipeff_9[33]), ((~ atannode_9_w[2]) ^ z_pipeff_9[33]), ((~ atannode_9_w[1]) ^ z_pipeff_9[33]), ((~ atannode_9_w[0]) ^ z_pipeff_9[33])},
z_subnode_11_w = {((~ atannode_10_w[33]) ^ z_pipeff_10[33]), ((~ atannode_10_w[32]) ^ z_pipeff_10[33]), ((~ atannode_10_w[31]) ^ z_pipeff_10[33]), ((~ atannode_10_w[30]) ^ z_pipeff_10[33]), ((~ atannode_10_w[29]) ^ z_pipeff_10[33]), ((~ atannode_10_w[28]) ^ z_pipeff_10[33]), ((~ atannode_10_w[27]) ^ z_pipeff_10[33]), ((~ atannode_10_w[26]) ^ z_pipeff_10[33]), ((~ atannode_10_w[25]) ^ z_pipeff_10[33]), ((~ atannode_10_w[24]) ^ z_pipeff_10[33]), ((~ atannode_10_w[23]) ^ z_pipeff_10[33]), ((~ atannode_10_w[22]) ^ z_pipeff_10[33]), ((~ atannode_10_w[21]) ^ z_pipeff_10[33]), ((~ atannode_10_w[20]) ^ z_pipeff_10[33]), ((~ atannode_10_w[19]) ^ z_pipeff_10[33]), ((~ atannode_10_w[18]) ^ z_pipeff_10[33]), ((~ atannode_10_w[17]) ^ z_pipeff_10[33]), ((~ atannode_10_w[16]) ^ z_pipeff_10[33]), ((~ atannode_10_w[15]) ^ z_pipeff_10[33]), ((~ atannode_10_w[14]) ^ z_pipeff_10[33]), ((~ atannode_10_w[13]) ^ z_pipeff_10[33]), ((~ atannode_10_w[12]) ^ z_pipeff_10[33]), ((~ atannode_10_w[11]) ^ z_pipeff_10[33]), ((~ atannode_10_w[10]) ^ z_pipeff_10[33]), ((~ atannode_10_w[9]) ^ z_pipeff_10[33]), ((~ atannode_10_w[8]) ^ z_pipeff_10[33]), ((~ atannode_10_w[7]) ^ z_pipeff_10[33]), ((~ atannode_10_w[6]) ^ z_pipeff_10[33]), ((~ atannode_10_w[5]) ^ z_pipeff_10[33]), ((~ atannode_10_w[4]) ^ z_pipeff_10[33]), ((~ atannode_10_w[3]) ^ z_pipeff_10[33]), ((~ atannode_10_w[2]) ^ z_pipeff_10[33]), ((~ atannode_10_w[1]) ^ z_pipeff_10[33]), ((~ atannode_10_w[0]) ^ z_pipeff_10[33])},
z_subnode_12_w = {((~ atannode_11_w[33]) ^ z_pipeff_11[33]), ((~ atannode_11_w[32]) ^ z_pipeff_11[33]), ((~ atannode_11_w[31]) ^ z_pipeff_11[33]), ((~ atannode_11_w[30]) ^ z_pipeff_11[33]), ((~ atannode_11_w[29]) ^ z_pipeff_11[33]), ((~ atannode_11_w[28]) ^ z_pipeff_11[33]), ((~ atannode_11_w[27]) ^ z_pipeff_11[33]), ((~ atannode_11_w[26]) ^ z_pipeff_11[33]), ((~ atannode_11_w[25]) ^ z_pipeff_11[33]), ((~ atannode_11_w[24]) ^ z_pipeff_11[33]), ((~ atannode_11_w[23]) ^ z_pipeff_11[33]), ((~ atannode_11_w[22]) ^ z_pipeff_11[33]), ((~ atannode_11_w[21]) ^ z_pipeff_11[33]), ((~ atannode_11_w[20]) ^ z_pipeff_11[33]), ((~ atannode_11_w[19]) ^ z_pipeff_11[33]), ((~ atannode_11_w[18]) ^ z_pipeff_11[33]), ((~ atannode_11_w[17]) ^ z_pipeff_11[33]), ((~ atannode_11_w[16]) ^ z_pipeff_11[33]), ((~ atannode_11_w[15]) ^ z_pipeff_11[33]), ((~ atannode_11_w[14]) ^ z_pipeff_11[33]), ((~ atannode_11_w[13]) ^ z_pipeff_11[33]), ((~ atannode_11_w[12]) ^ z_pipeff_11[33]), ((~ atannode_11_w[11]) ^ z_pipeff_11[33]), ((~ atannode_11_w[10]) ^ z_pipeff_11[33]), ((~ atannode_11_w[9]) ^ z_pipeff_11[33]), ((~ atannode_11_w[8]) ^ z_pipeff_11[33]), ((~ atannode_11_w[7]) ^ z_pipeff_11[33]), ((~ atannode_11_w[6]) ^ z_pipeff_11[33]), ((~ atannode_11_w[5]) ^ z_pipeff_11[33]), ((~ atannode_11_w[4]) ^ z_pipeff_11[33]), ((~ atannode_11_w[3]) ^ z_pipeff_11[33]), ((~ atannode_11_w[2]) ^ z_pipeff_11[33]), ((~ atannode_11_w[1]) ^ z_pipeff_11[33]), ((~ atannode_11_w[0]) ^ z_pipeff_11[33])},
z_subnode_13_w = {((~ atannode_12_w[33]) ^ z_pipeff_12[33]), ((~ atannode_12_w[32]) ^ z_pipeff_12[33]), ((~ atannode_12_w[31]) ^ z_pipeff_12[33]), ((~ atannode_12_w[30]) ^ z_pipeff_12[33]), ((~ atannode_12_w[29]) ^ z_pipeff_12[33]), ((~ atannode_12_w[28]) ^ z_pipeff_12[33]), ((~ atannode_12_w[27]) ^ z_pipeff_12[33]), ((~ atannode_12_w[26]) ^ z_pipeff_12[33]), ((~ atannode_12_w[25]) ^ z_pipeff_12[33]), ((~ atannode_12_w[24]) ^ z_pipeff_12[33]), ((~ atannode_12_w[23]) ^ z_pipeff_12[33]), ((~ atannode_12_w[22]) ^ z_pipeff_12[33]), ((~ atannode_12_w[21]) ^ z_pipeff_12[33]), ((~ atannode_12_w[20]) ^ z_pipeff_12[33]), ((~ atannode_12_w[19]) ^ z_pipeff_12[33]), ((~ atannode_12_w[18]) ^ z_pipeff_12[33]), ((~ atannode_12_w[17]) ^ z_pipeff_12[33]), ((~ atannode_12_w[16]) ^ z_pipeff_12[33]), ((~ atannode_12_w[15]) ^ z_pipeff_12[33]), ((~ atannode_12_w[14]) ^ z_pipeff_12[33]), ((~ atannode_12_w[13]) ^ z_pipeff_12[33]), ((~ atannode_12_w[12]) ^ z_pipeff_12[33]), ((~ atannode_12_w[11]) ^ z_pipeff_12[33]), ((~ atannode_12_w[10]) ^ z_pipeff_12[33]), ((~ atannode_12_w[9]) ^ z_pipeff_12[33]), ((~ atannode_12_w[8]) ^ z_pipeff_12[33]), ((~ atannode_12_w[7]) ^ z_pipeff_12[33]), ((~ atannode_12_w[6]) ^ z_pipeff_12[33]), ((~ atannode_12_w[5]) ^ z_pipeff_12[33]), ((~ atannode_12_w[4]) ^ z_pipeff_12[33]), ((~ atannode_12_w[3]) ^ z_pipeff_12[33]), ((~ atannode_12_w[2]) ^ z_pipeff_12[33]), ((~ atannode_12_w[1]) ^ z_pipeff_12[33]), ((~ atannode_12_w[0]) ^ z_pipeff_12[33])},
z_subnode_2_w = {((~ atannode_1_w[33]) ^ z_pipeff_1[33]), ((~ atannode_1_w[32]) ^ z_pipeff_1[33]), ((~ atannode_1_w[31]) ^ z_pipeff_1[33]), ((~ atannode_1_w[30]) ^ z_pipeff_1[33]), ((~ atannode_1_w[29]) ^ z_pipeff_1[33]), ((~ atannode_1_w[28]) ^ z_pipeff_1[33]), ((~ atannode_1_w[27]) ^ z_pipeff_1[33]), ((~ atannode_1_w[26]) ^ z_pipeff_1[33]), ((~ atannode_1_w[25]) ^ z_pipeff_1[33]), ((~ atannode_1_w[24]) ^ z_pipeff_1[33]), ((~ atannode_1_w[23]) ^ z_pipeff_1[33]), ((~ atannode_1_w[22]) ^ z_pipeff_1[33]), ((~ atannode_1_w[21]) ^ z_pipeff_1[33]), ((~ atannode_1_w[20]) ^ z_pipeff_1[33]), ((~ atannode_1_w[19]) ^ z_pipeff_1[33]), ((~ atannode_1_w[18]) ^ z_pipeff_1[33]), ((~ atannode_1_w[17]) ^ z_pipeff_1[33]), ((~ atannode_1_w[16]) ^ z_pipeff_1[33]), ((~ atannode_1_w[15]) ^ z_pipeff_1[33]), ((~ atannode_1_w[14]) ^ z_pipeff_1[33]), ((~ atannode_1_w[13]) ^ z_pipeff_1[33]), ((~ atannode_1_w[12]) ^ z_pipeff_1[33]), ((~ atannode_1_w[11]) ^ z_pipeff_1[33]), ((~ atannode_1_w[10]) ^ z_pipeff_1[33]), ((~ atannode_1_w[9]) ^ z_pipeff_1[33]), ((~ atannode_1_w[8]) ^ z_pipeff_1[33]), ((~ atannode_1_w[7]) ^ z_pipeff_1[33]), ((~ atannode_1_w[6]) ^ z_pipeff_1[33]), ((~ atannode_1_w[5]) ^ z_pipeff_1[33]), ((~ atannode_1_w[4]) ^ z_pipeff_1[33]), ((~ atannode_1_w[3]) ^ z_pipeff_1[33]), ((~ atannode_1_w[2]) ^ z_pipeff_1[33]), ((~ atannode_1_w[1]) ^ z_pipeff_1[33]), ((~ atannode_1_w[0]) ^ z_pipeff_1[33])},
z_subnode_3_w = {((~ atannode_2_w[33]) ^ z_pipeff_2[33]), ((~ atannode_2_w[32]) ^ z_pipeff_2[33]), ((~ atannode_2_w[31]) ^ z_pipeff_2[33]), ((~ atannode_2_w[30]) ^ z_pipeff_2[33]), ((~ atannode_2_w[29]) ^ z_pipeff_2[33]), ((~ atannode_2_w[28]) ^ z_pipeff_2[33]), ((~ atannode_2_w[27]) ^ z_pipeff_2[33]), ((~ atannode_2_w[26]) ^ z_pipeff_2[33]), ((~ atannode_2_w[25]) ^ z_pipeff_2[33]), ((~ atannode_2_w[24]) ^ z_pipeff_2[33]), ((~ atannode_2_w[23]) ^ z_pipeff_2[33]), ((~ atannode_2_w[22]) ^ z_pipeff_2[33]), ((~ atannode_2_w[21]) ^ z_pipeff_2[33]), ((~ atannode_2_w[20]) ^ z_pipeff_2[33]), ((~ atannode_2_w[19]) ^ z_pipeff_2[33]), ((~ atannode_2_w[18]) ^ z_pipeff_2[33]), ((~ atannode_2_w[17]) ^ z_pipeff_2[33]), ((~ atannode_2_w[16]) ^ z_pipeff_2[33]), ((~ atannode_2_w[15]) ^ z_pipeff_2[33]), ((~ atannode_2_w[14]) ^ z_pipeff_2[33]), ((~ atannode_2_w[13]) ^ z_pipeff_2[33]), ((~ atannode_2_w[12]) ^ z_pipeff_2[33]), ((~ atannode_2_w[11]) ^ z_pipeff_2[33]), ((~ atannode_2_w[10]) ^ z_pipeff_2[33]), ((~ atannode_2_w[9]) ^ z_pipeff_2[33]), ((~ atannode_2_w[8]) ^ z_pipeff_2[33]), ((~ atannode_2_w[7]) ^ z_pipeff_2[33]), ((~ atannode_2_w[6]) ^ z_pipeff_2[33]), ((~ atannode_2_w[5]) ^ z_pipeff_2[33]), ((~ atannode_2_w[4]) ^ z_pipeff_2[33]), ((~ atannode_2_w[3]) ^ z_pipeff_2[33]), ((~ atannode_2_w[2]) ^ z_pipeff_2[33]), ((~ atannode_2_w[1]) ^ z_pipeff_2[33]), ((~ atannode_2_w[0]) ^ z_pipeff_2[33])},
z_subnode_4_w = {((~ atannode_3_w[33]) ^ z_pipeff_3[33]), ((~ atannode_3_w[32]) ^ z_pipeff_3[33]), ((~ atannode_3_w[31]) ^ z_pipeff_3[33]), ((~ atannode_3_w[30]) ^ z_pipeff_3[33]), ((~ atannode_3_w[29]) ^ z_pipeff_3[33]), ((~ atannode_3_w[28]) ^ z_pipeff_3[33]), ((~ atannode_3_w[27]) ^ z_pipeff_3[33]), ((~ atannode_3_w[26]) ^ z_pipeff_3[33]), ((~ atannode_3_w[25]) ^ z_pipeff_3[33]), ((~ atannode_3_w[24]) ^ z_pipeff_3[33]), ((~ atannode_3_w[23]) ^ z_pipeff_3[33]), ((~ atannode_3_w[22]) ^ z_pipeff_3[33]), ((~ atannode_3_w[21]) ^ z_pipeff_3[33]), ((~ atannode_3_w[20]) ^ z_pipeff_3[33]), ((~ atannode_3_w[19]) ^ z_pipeff_3[33]), ((~ atannode_3_w[18]) ^ z_pipeff_3[33]), ((~ atannode_3_w[17]) ^ z_pipeff_3[33]), ((~ atannode_3_w[16]) ^ z_pipeff_3[33]), ((~ atannode_3_w[15]) ^ z_pipeff_3[33]), ((~ atannode_3_w[14]) ^ z_pipeff_3[33]), ((~ atannode_3_w[13]) ^ z_pipeff_3[33]), ((~ atannode_3_w[12]) ^ z_pipeff_3[33]), ((~ atannode_3_w[11]) ^ z_pipeff_3[33]), ((~ atannode_3_w[10]) ^ z_pipeff_3[33]), ((~ atannode_3_w[9]) ^ z_pipeff_3[33]), ((~ atannode_3_w[8]) ^ z_pipeff_3[33]), ((~ atannode_3_w[7]) ^ z_pipeff_3[33]), ((~ atannode_3_w[6]) ^ z_pipeff_3[33]), ((~ atannode_3_w[5]) ^ z_pipeff_3[33]), ((~ atannode_3_w[4]) ^ z_pipeff_3[33]), ((~ atannode_3_w[3]) ^ z_pipeff_3[33]), ((~ atannode_3_w[2]) ^ z_pipeff_3[33]), ((~ atannode_3_w[1]) ^ z_pipeff_3[33]), ((~ atannode_3_w[0]) ^ z_pipeff_3[33])},
z_subnode_5_w = {((~ atannode_4_w[33]) ^ z_pipeff_4[33]), ((~ atannode_4_w[32]) ^ z_pipeff_4[33]), ((~ atannode_4_w[31]) ^ z_pipeff_4[33]), ((~ atannode_4_w[30]) ^ z_pipeff_4[33]), ((~ atannode_4_w[29]) ^ z_pipeff_4[33]), ((~ atannode_4_w[28]) ^ z_pipeff_4[33]), ((~ atannode_4_w[27]) ^ z_pipeff_4[33]), ((~ atannode_4_w[26]) ^ z_pipeff_4[33]), ((~ atannode_4_w[25]) ^ z_pipeff_4[33]), ((~ atannode_4_w[24]) ^ z_pipeff_4[33]), ((~ atannode_4_w[23]) ^ z_pipeff_4[33]), ((~ atannode_4_w[22]) ^ z_pipeff_4[33]), ((~ atannode_4_w[21]) ^ z_pipeff_4[33]), ((~ atannode_4_w[20]) ^ z_pipeff_4[33]), ((~ atannode_4_w[19]) ^ z_pipeff_4[33]), ((~ atannode_4_w[18]) ^ z_pipeff_4[33]), ((~ atannode_4_w[17]) ^ z_pipeff_4[33]), ((~ atannode_4_w[16]) ^ z_pipeff_4[33]), ((~ atannode_4_w[15]) ^ z_pipeff_4[33]), ((~ atannode_4_w[14]) ^ z_pipeff_4[33]), ((~ atannode_4_w[13]) ^ z_pipeff_4[33]), ((~ atannode_4_w[12]) ^ z_pipeff_4[33]), ((~ atannode_4_w[11]) ^ z_pipeff_4[33]), ((~ atannode_4_w[10]) ^ z_pipeff_4[33]), ((~ atannode_4_w[9]) ^ z_pipeff_4[33]), ((~ atannode_4_w[8]) ^ z_pipeff_4[33]), ((~ atannode_4_w[7]) ^ z_pipeff_4[33]), ((~ atannode_4_w[6]) ^ z_pipeff_4[33]), ((~ atannode_4_w[5]) ^ z_pipeff_4[33]), ((~ atannode_4_w[4]) ^ z_pipeff_4[33]), ((~ atannode_4_w[3]) ^ z_pipeff_4[33]), ((~ atannode_4_w[2]) ^ z_pipeff_4[33]), ((~ atannode_4_w[1]) ^ z_pipeff_4[33]), ((~ atannode_4_w[0]) ^ z_pipeff_4[33])},
z_subnode_6_w = {((~ atannode_5_w[33]) ^ z_pipeff_5[33]), ((~ atannode_5_w[32]) ^ z_pipeff_5[33]), ((~ atannode_5_w[31]) ^ z_pipeff_5[33]), ((~ atannode_5_w[30]) ^ z_pipeff_5[33]), ((~ atannode_5_w[29]) ^ z_pipeff_5[33]), ((~ atannode_5_w[28]) ^ z_pipeff_5[33]), ((~ atannode_5_w[27]) ^ z_pipeff_5[33]), ((~ atannode_5_w[26]) ^ z_pipeff_5[33]), ((~ atannode_5_w[25]) ^ z_pipeff_5[33]), ((~ atannode_5_w[24]) ^ z_pipeff_5[33]), ((~ atannode_5_w[23]) ^ z_pipeff_5[33]), ((~ atannode_5_w[22]) ^ z_pipeff_5[33]), ((~ atannode_5_w[21]) ^ z_pipeff_5[33]), ((~ atannode_5_w[20]) ^ z_pipeff_5[33]), ((~ atannode_5_w[19]) ^ z_pipeff_5[33]), ((~ atannode_5_w[18]) ^ z_pipeff_5[33]), ((~ atannode_5_w[17]) ^ z_pipeff_5[33]), ((~ atannode_5_w[16]) ^ z_pipeff_5[33]), ((~ atannode_5_w[15]) ^ z_pipeff_5[33]), ((~ atannode_5_w[14]) ^ z_pipeff_5[33]), ((~ atannode_5_w[13]) ^ z_pipeff_5[33]), ((~ atannode_5_w[12]) ^ z_pipeff_5[33]), ((~ atannode_5_w[11]) ^ z_pipeff_5[33]), ((~ atannode_5_w[10]) ^ z_pipeff_5[33]), ((~ atannode_5_w[9]) ^ z_pipeff_5[33]), ((~ atannode_5_w[8]) ^ z_pipeff_5[33]), ((~ atannode_5_w[7]) ^ z_pipeff_5[33]), ((~ atannode_5_w[6]) ^ z_pipeff_5[33]), ((~ atannode_5_w[5]) ^ z_pipeff_5[33]), ((~ atannode_5_w[4]) ^ z_pipeff_5[33]), ((~ atannode_5_w[3]) ^ z_pipeff_5[33]), ((~ atannode_5_w[2]) ^ z_pipeff_5[33]), ((~ atannode_5_w[1]) ^ z_pipeff_5[33]), ((~ atannode_5_w[0]) ^ z_pipeff_5[33])},
z_subnode_7_w = {((~ atannode_6_w[33]) ^ z_pipeff_6[33]), ((~ atannode_6_w[32]) ^ z_pipeff_6[33]), ((~ atannode_6_w[31]) ^ z_pipeff_6[33]), ((~ atannode_6_w[30]) ^ z_pipeff_6[33]), ((~ atannode_6_w[29]) ^ z_pipeff_6[33]), ((~ atannode_6_w[28]) ^ z_pipeff_6[33]), ((~ atannode_6_w[27]) ^ z_pipeff_6[33]), ((~ atannode_6_w[26]) ^ z_pipeff_6[33]), ((~ atannode_6_w[25]) ^ z_pipeff_6[33]), ((~ atannode_6_w[24]) ^ z_pipeff_6[33]), ((~ atannode_6_w[23]) ^ z_pipeff_6[33]), ((~ atannode_6_w[22]) ^ z_pipeff_6[33]), ((~ atannode_6_w[21]) ^ z_pipeff_6[33]), ((~ atannode_6_w[20]) ^ z_pipeff_6[33]), ((~ atannode_6_w[19]) ^ z_pipeff_6[33]), ((~ atannode_6_w[18]) ^ z_pipeff_6[33]), ((~ atannode_6_w[17]) ^ z_pipeff_6[33]), ((~ atannode_6_w[16]) ^ z_pipeff_6[33]), ((~ atannode_6_w[15]) ^ z_pipeff_6[33]), ((~ atannode_6_w[14]) ^ z_pipeff_6[33]), ((~ atannode_6_w[13]) ^ z_pipeff_6[33]), ((~ atannode_6_w[12]) ^ z_pipeff_6[33]), ((~ atannode_6_w[11]) ^ z_pipeff_6[33]), ((~ atannode_6_w[10]) ^ z_pipeff_6[33]), ((~ atannode_6_w[9]) ^ z_pipeff_6[33]), ((~ atannode_6_w[8]) ^ z_pipeff_6[33]), ((~ atannode_6_w[7]) ^ z_pipeff_6[33]), ((~ atannode_6_w[6]) ^ z_pipeff_6[33]), ((~ atannode_6_w[5]) ^ z_pipeff_6[33]), ((~ atannode_6_w[4]) ^ z_pipeff_6[33]), ((~ atannode_6_w[3]) ^ z_pipeff_6[33]), ((~ atannode_6_w[2]) ^ z_pipeff_6[33]), ((~ atannode_6_w[1]) ^ z_pipeff_6[33]), ((~ atannode_6_w[0]) ^ z_pipeff_6[33])},
z_subnode_8_w = {((~ atannode_7_w[33]) ^ z_pipeff_7[33]), ((~ atannode_7_w[32]) ^ z_pipeff_7[33]), ((~ atannode_7_w[31]) ^ z_pipeff_7[33]), ((~ atannode_7_w[30]) ^ z_pipeff_7[33]), ((~ atannode_7_w[29]) ^ z_pipeff_7[33]), ((~ atannode_7_w[28]) ^ z_pipeff_7[33]), ((~ atannode_7_w[27]) ^ z_pipeff_7[33]), ((~ atannode_7_w[26]) ^ z_pipeff_7[33]), ((~ atannode_7_w[25]) ^ z_pipeff_7[33]), ((~ atannode_7_w[24]) ^ z_pipeff_7[33]), ((~ atannode_7_w[23]) ^ z_pipeff_7[33]), ((~ atannode_7_w[22]) ^ z_pipeff_7[33]), ((~ atannode_7_w[21]) ^ z_pipeff_7[33]), ((~ atannode_7_w[20]) ^ z_pipeff_7[33]), ((~ atannode_7_w[19]) ^ z_pipeff_7[33]), ((~ atannode_7_w[18]) ^ z_pipeff_7[33]), ((~ atannode_7_w[17]) ^ z_pipeff_7[33]), ((~ atannode_7_w[16]) ^ z_pipeff_7[33]), ((~ atannode_7_w[15]) ^ z_pipeff_7[33]), ((~ atannode_7_w[14]) ^ z_pipeff_7[33]), ((~ atannode_7_w[13]) ^ z_pipeff_7[33]), ((~ atannode_7_w[12]) ^ z_pipeff_7[33]), ((~ atannode_7_w[11]) ^ z_pipeff_7[33]), ((~ atannode_7_w[10]) ^ z_pipeff_7[33]), ((~ atannode_7_w[9]) ^ z_pipeff_7[33]), ((~ atannode_7_w[8]) ^ z_pipeff_7[33]), ((~ atannode_7_w[7]) ^ z_pipeff_7[33]), ((~ atannode_7_w[6]) ^ z_pipeff_7[33]), ((~ atannode_7_w[5]) ^ z_pipeff_7[33]), ((~ atannode_7_w[4]) ^ z_pipeff_7[33]), ((~ atannode_7_w[3]) ^ z_pipeff_7[33]), ((~ atannode_7_w[2]) ^ z_pipeff_7[33]), ((~ atannode_7_w[1]) ^ z_pipeff_7[33]), ((~ atannode_7_w[0]) ^ z_pipeff_7[33])},
z_subnode_9_w = {((~ atannode_8_w[33]) ^ z_pipeff_8[33]), ((~ atannode_8_w[32]) ^ z_pipeff_8[33]), ((~ atannode_8_w[31]) ^ z_pipeff_8[33]), ((~ atannode_8_w[30]) ^ z_pipeff_8[33]), ((~ atannode_8_w[29]) ^ z_pipeff_8[33]), ((~ atannode_8_w[28]) ^ z_pipeff_8[33]), ((~ atannode_8_w[27]) ^ z_pipeff_8[33]), ((~ atannode_8_w[26]) ^ z_pipeff_8[33]), ((~ atannode_8_w[25]) ^ z_pipeff_8[33]), ((~ atannode_8_w[24]) ^ z_pipeff_8[33]), ((~ atannode_8_w[23]) ^ z_pipeff_8[33]), ((~ atannode_8_w[22]) ^ z_pipeff_8[33]), ((~ atannode_8_w[21]) ^ z_pipeff_8[33]), ((~ atannode_8_w[20]) ^ z_pipeff_8[33]), ((~ atannode_8_w[19]) ^ z_pipeff_8[33]), ((~ atannode_8_w[18]) ^ z_pipeff_8[33]), ((~ atannode_8_w[17]) ^ z_pipeff_8[33]), ((~ atannode_8_w[16]) ^ z_pipeff_8[33]), ((~ atannode_8_w[15]) ^ z_pipeff_8[33]), ((~ atannode_8_w[14]) ^ z_pipeff_8[33]), ((~ atannode_8_w[13]) ^ z_pipeff_8[33]), ((~ atannode_8_w[12]) ^ z_pipeff_8[33]), ((~ atannode_8_w[11]) ^ z_pipeff_8[33]), ((~ atannode_8_w[10]) ^ z_pipeff_8[33]), ((~ atannode_8_w[9]) ^ z_pipeff_8[33]), ((~ atannode_8_w[8]) ^ z_pipeff_8[33]), ((~ atannode_8_w[7]) ^ z_pipeff_8[33]), ((~ atannode_8_w[6]) ^ z_pipeff_8[33]), ((~ atannode_8_w[5]) ^ z_pipeff_8[33]), ((~ atannode_8_w[4]) ^ z_pipeff_8[33]), ((~ atannode_8_w[3]) ^ z_pipeff_8[33]), ((~ atannode_8_w[2]) ^ z_pipeff_8[33]), ((~ atannode_8_w[1]) ^ z_pipeff_8[33]), ((~ atannode_8_w[0]) ^ z_pipeff_8[33])};
endmodule //sin_altfp_sincos_cordic_m_e5e
//altfp_sincos_range CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" WIDTH_EXP=8 WIDTH_MAN=23 aclr circle clken clock data negcircle
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//altfp_sincos_srrt CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" address basefraction incexponent incmantissa
//VERSION_BEGIN 14.1 cbx_altfp_sincos 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_clshift 2014:12:03:18:16:05:SJ cbx_lpm_mult 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_padd 2014:12:03:18:16:05:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
//synthesis_resources = lpm_mux 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_srrt_koa
(
address,
basefraction,
incexponent,
incmantissa) ;
input [7:0] address;
output [35:0] basefraction;
output [7:0] incexponent;
output [55:0] incmantissa;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [7:0] address;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [99:0] wire_mux2_result;
lpm_mux mux2
(
.data({{8{1'b0}}, 56'b10011010011011101110000001101101101100010100101011001000, 8'b00110110, 28'b1101100010100101011001100101, 8'b00000001, 56'b10011010011011101110000001101101101100010100101011010000, 8'b00011011, 28'b0110110001010010101100110010, {8{1'b0}}, 56'b10100110100110111011100000011011011011000101001010111000, 8'b00001101, 28'b1011011000101001010110011001, 8'b00000001, 56'b10100110100110111011100000011011011011000101001010110000, 8'b00000110, 28'b1101101100010100101011001101, {8{1'b0}}, 56'b10101001101001101110111000000110110110110001010010110000, 8'b00000011, 28'b0110110110001010010101100110, {8{1'b0}}, 56'b11010100110100110111011100000011011011011000101001100000, 8'b10000001, 28'b1011011011000101001010110011, {8{1'b0}}, 56'b11101010011010011011101110000001101101101100010100011000, 8'b11000000, 28'b1101101101100010100101011010, {8{1'b0}}, 56'b11110101001101001101110111000000110110110110001010011000, 8'b11100000, 28'b0110110110110001010010101101, {8{1'b0}}, 56'b11111010100110100110111011100000011011011011000101010000, 8'b01110000, 28'b0011011011011000101001010110, 8'b00000001, 56'b11111010100110100110111011100000011011011011000101010000, 8'b10111000, 28'b0001101101101100010100101011, 8'b00000010, 56'b11111010100110100110111011100000011011011011000101010000, 8'b11011100, 28'b0000110110110110001010010110, 8'b00000011, 56'b11111010100110100110111011100000011011011011000100101000, 8'b11101110, 28'b0000011011011011000101001011, {8{1'b0}}, 56'b10001111101010011010011011101110000001101101101100011000, 8'b01110111, 28'b0000001101101101100010100101, 8'b00000001, 56'b10001111101010011010011011101110000001101101101100100000, 8'b10111011, 28'b1000000110110110110001010011, {8{1'b0}}, 56'b10100011111010100110100110111011100000011011011011001000, 8'b11011101, 28'b1100000011011011011000101001, {8{1'b0}}, 56'b11010001111101010011010011011101110000001101101101010000, 8'b01101110, 28'b1110000001101101101100010101, {8{1'b0}}, 56'b11101000111110101001101001101110111000000110110110111000, 8'b00110111, 28'b0111000000110110110110001010
, {8{1'b0}}, 56'b11110100011111010100110100110111011100000011011011011000, 8'b10011011, 28'b1011100000011011011011000101, {8{1'b0}}, 56'b11111010001111101010011010011011101110000001101101101000, 8'b01001101, 28'b1101110000001101101101100011, 8'b00000001, 56'b11111010001111101010011010011011101110000001101110000000, 8'b10100110, 28'b1110111000000110110110110001, {8{1'b0}}, 56'b10111110100011111010100110100110111011100000011011100000, 8'b11010011, 28'b0111011100000011011011011001, 8'b00000001, 56'b10111110100011111010100110100110111011100000011011101000, 8'b01101001, 28'b1011101110000001101101101100, {8{1'b0}}, 56'b10101111101000111110101001101001101110111000000110111000, 8'b00110100, 28'b1101110111000000110110110110, 8'b00000001, 56'b10101111101000111110101001101001101110111000000110110000, 8'b10011010, 28'b0110111011100000011011011011, {8{1'b0}}, 56'b10101011111010001111101010011010011011101110000001110000, 8'b01001101, 28'b0011011101110000001101101110, {8{1'b0}}, 56'b11010101111101000111110101001101001101110111000000111000, 8'b10100110, 28'b1001101110111000000110110111, {8{1'b0}}, 56'b11101010111110100011111010100110100110111011100000110000, 8'b01010011, 28'b0100110111011100000011011011, 8'b00000001, 56'b11101010111110100011111010100110100110111011100000100000, 8'b10101001, 28'b1010011011101110000001101110, 8'b00000010, 56'b11101010111110100011111010100110100110111011011111111000, 8'b11010100, 28'b1101001101110111000000110111, {8{1'b0}}, 56'b10011101010111110100011111010100110100110111011100000000, 8'b11101010, 28'b0110100110111011100000011011, 8'b00000001, 56'b10011101010111110100011111010100110100110111011100011000, 8'b11110101, 28'b0011010011011101110000001110, 8'b00000010, 56'b10011101010111110100011111010100110100110111011100011000, 8'b11111010, 28'b1001101001101110111000000111, 8'b00000011, 56'b10011101010111110100011111010100110100110111011100011000, 8'b01111101, 28'b0100110100110111011100000011, 8'b00000100, 56'b10011101010111110100011111010100110100110111011110010000, 8'b00111110, 28'b1010011010011011101110000010
, {8{1'b0}}, 56'b10000100111010101111101000111110101001101001101111000000, 8'b00011111, 28'b0101001101001101110111000001, {8{1'b0}}, 56'b11000010011101010111110100011111010100110100110111011000, 8'b10001111, 28'b1010100110100110111011100000, {8{1'b0}}, 56'b11100001001110101011111010001111101010011010011011110000, 8'b01000111, 28'b1101010011010011011101110000, {8{1'b0}}, 56'b11110000100111010101111101000111110101001101001110000000, 8'b10100011, 28'b1110101001101001101110111000, {8{1'b0}}, 56'b11111000010011101010111110100011111010100110100110111000, 8'b11010001, 28'b1111010100110100110111011100, {8{1'b0}}, 56'b11111100001001110101011111010001111101010011010011011000, 8'b11101000, 28'b1111101010011010011011101110, {8{1'b0}}, 56'b11111110000100111010101111101000111110101001101001110000, 8'b11110100, 28'b0111110101001101001101110111, 8'b00000001, 56'b11111110000100111010101111101000111110101001101010000000, 8'b11111010, 28'b0011111010100110100110111100, 8'b00000010, 56'b11111110000100111010101111101000111110101001101001110000, 8'b01111101, 28'b0001111101010011010011011110, {8{1'b0}}, 56'b10011111110000100111010101111101000111110101001101011000, 8'b10111110, 28'b1000111110101001101001101111, 8'b00000001, 56'b10011111110000100111010101111101000111110101001101100000, 8'b01011111, 28'b0100011111010100110100110111, {8{1'b0}}, 56'b10100111111100001001110101011111010001111101010011010000, 8'b10101111, 28'b1010001111101010011010011100, 8'b00000001, 56'b10100111111100001001110101011111010001111101010011100000, 8'b01010111, 28'b1101000111110101001101001110, 8'b00000010, 56'b10100111111100001001110101011111010001111101010011010000, 8'b10101011, 28'b1110100011111010100110100111, {8{1'b0}}, 56'b10010100111111100001001110101011111010001111101010011000, 8'b11010101, 28'b1111010001111101010011010011, 8'b00000001, 56'b10010100111111100001001110101011111010001111101010101000, 8'b11101010, 28'b1111101000111110101001101010, {8{1'b0}}, 56'b10100101001111111000010011101010111110100011111010101000, 8'b01110101, 28'b0111110100011111010100110101
, 8'b00000001, 56'b10100101001111111000010011101010111110100011111010101000, 8'b00111010, 28'b1011111010001111101010011010, {8{1'b0}}, 56'b10101001010011111110000100111010101111101000111110101000, 8'b10011101, 28'b0101111101000111110101001101, 8'b00000001, 56'b10101001010011111110000100111010101111101000111110111000, 8'b01001110, 28'b1010111110100011111010100111, 8'b00000010, 56'b10101001010011111110000100111010101111101000111110111000, 8'b00100111, 28'b0101011111010001111101010011, 8'b00000011, 56'b10101001010011111110000100111010101111101000111110111000, 8'b00010011, 28'b1010101111101000111110101010, 8'b00000100, 56'b10101001010011111110000100111010101111101000111110111000, 8'b00001001, 28'b1101010111110100011111010101, 8'b00000101, 56'b10101001010011111110000100111010101111101001000000110000, 8'b10000100, 28'b1110101011111010001111101010, {8{1'b0}}, 56'b10000010101001010011111110000100111010101111101001001000, 8'b11000010, 28'b0111010101111101000111110101, 8'b00000001, 56'b10000010101001010011111110000100111010101111101001010000, 8'b11100001, 28'b0011101010111110100011111011, 8'b00000010, 56'b10000010101001010011111110000100111010101111101000111000, 8'b11110000, 28'b1001110101011111010001111101, 8'b00000011, 56'b10000010101001010011111110000100111010101111101001100000, 8'b11111000, 28'b0100111010101111101000111111, {8{1'b0}}, 56'b10001000001010100101001111111000010011101010111110100000, 8'b11111100, 28'b0010011101010111110100011111, 8'b00000001, 56'b10001000001010100101001111111000010011101010111110100000, 8'b11111110, 28'b0001001110101011111010010000, 8'b00000010, 56'b10001000001010100101001111111000010011101010111110100000, 8'b01111111, 28'b0000100111010101111101001000, {8{1'b0}}, 56'b10010001000001010100101001111111000010011101011000010000, 8'b00111111, 28'b1000010011101010111110100100, {8{1'b0}}, 56'b11001000100000101010010100111111100001001110101011111000, 8'b10011111, 28'b1100001001110101011111010010, {8{1'b0}}, 56'b11100100010000010101001010011111110000100111010101111000, 8'b01001111, 28'b1110000100111010101111101001
, 8'b00000001, 56'b11100100010000010101001010011111110000100111010101110000, 8'b10100111, 28'b1111000010011101010111110100, 8'b00000010, 56'b11100100010000010101001010011111110000100111010110001000, 8'b01010011, 28'b1111100001001110101011111010, {8{1'b0}}, 56'b10011100100010000010101001010011111110000100111010111000, 8'b00101001, 28'b1111110000100111010101111101, 8'b00000001, 56'b10011100100010000010101001010011111110000100111010111000, 8'b10010100, 28'b1111111000010011101010111111, 8'b00000010, 56'b10011100100010000010101001010011111110000100111010110000, 8'b01001010, 28'b0111111100001001110101011111, {8{1'b0}}, 56'b10010011100100010000010101001010011111110000100111011000, 8'b10100101, 28'b0011111110000100111010110000, {8{1'b0}}, 56'b11001001110010001000001010100101001111111000010011101000, 8'b01010010, 28'b1001111111000010011101011000, {8{1'b0}}, 56'b11100100111001000100000101010010100111111100001001111000, 8'b10101001, 28'b0100111111100001001110101100, 8'b00000001, 56'b11100100111001000100000101010010100111111100001001101000, 8'b01010100, 28'b1010011111110000100111010110, {8{1'b0}}, 56'b10111001001110010001000001010100101001111111000010011000, 8'b00101010, 28'b0101001111111000010011101011, {8{1'b0}}, 56'b11011100100111001000100000101010010100111111100001011000, 8'b00010101, 28'b0010100111111100001001110101, 8'b00000001, 56'b11011100100111001000100000101010010100111111100001011000, 8'b00001010, 28'b1001010011111110000100111011, {8{1'b0}}, 56'b10110111001001110010001000001010100101001111111000011000, 8'b00000101, 28'b0100101001111111000010011101, {8{1'b0}}, 56'b11011011100100111001000100000101010010100111111100001000, 8'b10000010, 28'b1010010100111111100001001111, 8'b00000001, 56'b11011011100100111001000100000101010010100111111011111000, 8'b01000001, 28'b0101001010011111110000100111, 8'b00000010, 56'b11011011100100111001000100000101010010100111111100001000, 8'b00100000, 28'b1010100101001111111000010100, 8'b00000011, 56'b11011011100100111001000100000101010010100111111100100000, 8'b00010000, 28'b0101010010100111111100001010
, 8'b00000100, 56'b11011011100100111001000100000101010010100111111010111000, 8'b10001000, 28'b0010101001010011111110000101, 8'b00000101, 56'b11011011100100111001000100000101010010100111111001101000, 8'b01000100, 28'b0001010100101001111111000010, {8{1'b0}}, 56'b10000011011011100100111001000100000101010010101000000000, 8'b00100010, 28'b0000101010010100111111100001, {8{1'b0}}, 56'b11000001101101110010011100100010000010101001010100001000, 8'b10010001, 28'b0000010101001010011111110001, 8'b00000001, 56'b11000001101101110010011100100010000010101001010011110000, 8'b11001000, 28'b1000001010100101001111111000, 8'b00000010, 56'b11000001101101110010011100100010000010101001010100001000, 8'b11100100, 28'b0100000101010010100111111100, {8{1'b0}}, 56'b10011000001101101110010011100100010000010101001010100000, 8'b01110010, 28'b0010000010101001010011111110, {8{1'b0}}, 56'b11001100000110110111001001110010001000001010100101010000, 8'b00111001, 28'b0001000001010100101001111111, {8{1'b0}}, 56'b11100110000011011011100100111001000100000101010010101000, 8'b10011100, 28'b1000100000101010010101000000, {8{1'b0}}, 56'b11110011000001101101110010011100100010000010101001001000, 8'b01001110, 28'b0100010000010101001010100000, {8{1'b0}}, 56'b11111001100000110110111001001110010001000001010100101000, 8'b00100111, 28'b0010001000001010100101010000, 8'b00000001, 56'b11111001100000110110111001001110010001000001010100101000, 8'b10010011, 28'b1001000100000101010010101000, {8{1'b0}}, 56'b10111110011000001101101110010011100100010000010101010000, 8'b11001001, 28'b1100100010000010101001010100, 8'b00000001, 56'b10111110011000001101101110010011100100010000010101011000, 8'b11100100, 28'b1110010001000001010100101010, 8'b00000010, 56'b10111110011000001101101110010011100100010000010101000000, 8'b01110010, 28'b0111001000100000101010010101, 8'b00000011, 56'b10111110011000001101101110010011100100010000010101110000, 8'b10111001, 28'b0011100100010000010101001010, {8{1'b0}}, 56'b10001011111001100000110110111001001110010001000001011000, 8'b11011100, 28'b1001110010001000001010100101
, 8'b00000001, 56'b10001011111001100000110110111001001110010001000001010000, 8'b01101110, 28'b0100111001000100000101010011, {8{1'b0}}, 56'b10100010111110011000001101101110010011100100010000010000, 8'b10110111, 28'b0010011100100010000010101001, 8'b00000001, 56'b10100010111110011000001101101110010011100100010000011000, 8'b11011011, 28'b1001001110010001000001010101, 8'b00000010, 56'b10100010111110011000001101101110010011100100010000011000, 8'b01101101, 28'b1100100111001000100000101010, 8'b00000011, 56'b10100010111110011000001101101110010011100100010000011000, 8'b00110110, 28'b1110010011100100010000010101, 8'b00000100, 56'b10100010111110011000001101101110010011100100010000011000, 8'b00011011, 28'b0111001001110010001000001011, 8'b00000101, 56'b10100010111110011000001101101110010011100100010000011000, 8'b00001101, 28'b1011100100111001000100000101, 8'b00000110, 56'b10100010111110011000001101101110010011100100010000011000, 8'b00000110, 28'b1101110010011100100010000011, 8'b00000111, 56'b10100010111110011000001101101110010011100100010000011000, 8'b10000011, 28'b0110111001001110010001000001, 8'b00001000, 56'b10100010111110011000001101101110010011100101100001111000, 8'b11000001, 28'b1011011100100111001000100001, 8'b00001001, 56'b10100010111110011000001101101110010011100100010000011000, 8'b01100000, 28'b1101101110010011100100010000, 8'b00001010, 56'b10100010111110011000001101101110010011100100010000011000, 8'b00110000, 28'b0110110111001001110010001000, 8'b00001011, 56'b10100010111110011000001101101110010011100100010000011000, 8'b10011000, 28'b0011011011100100111001000100, 8'b00001100, 56'b10100010111110011000001101101110010011100100010000011000, 8'b11001100, 28'b0001101101110010011100100010, 8'b00001101, 56'b10100010111110011000001101101110010011100100010000011000, 8'b11100110, 28'b0000110110111001001110010001, 8'b00001110, 56'b10100010111110011000001101101110010011100100010000011000, 8'b11110011, 28'b0000011011011100100111001001, 8'b00001111, 56'b10100010111110011000001101101110010011100100010000011000, 8'b11111001, 28'b1000001101101110010011100100
, 8'b00010000, 56'b10100010111110011000001101101110010011100100010000011000, 8'b01111100, 28'b1100000110110111001001110010, 8'b00010001, 56'b10100010111110011000001101101110001001011000010110111000, 8'b10111110, 28'b0110000011011011100100111001, 8'b00010010, 56'b10100010111110011000001101101110010011100100010000011000, 8'b01011111, 28'b0011000001101101110010011101, 8'b00010011, 56'b10100010111110011000001101101110011000101010001101001000, 8'b00101111, 28'b1001100000110110111001001110, 8'b00010100, 56'b10100010111110011000001101101110010011100100010000011000, 8'b00010111, 28'b1100110000011011011100100111, 8'b00010101, 56'b10100010111110011000001101101110010011100100010000011000, 8'b10001011, 28'b1110011000001101101110010100, 8'b00010110, 56'b10100010111110011000001101101110010011100100010000011000, 8'b01000101, 28'b1111001100000110110111001010, 8'b00010111, 56'b10100010111110011000001101101110010011100100010000011000, 8'b10100010, 28'b1111100110000011011011100101, 8'b00011000, 56'b10100010111110011000001101110000110110100010101000101000, 8'b01010001, 28'b0111110011000001101101110010, 8'b00011001, 56'b10100010111110011000001101101110010011100100010000011000, 8'b00101000, 28'b1011111001100000110110111001, 8'b00011010, 56'b10100010111110011000001101101110010011100100010000011000, 8'b00010100, 28'b0101111100110000011011011101, 8'b00011011, 56'b10100010111110011000001101101110010011100100010000011000, 8'b00001010, 28'b0010111110011000001101101110, 8'b00011100, 56'b10100010111110011000001101101110010011100100010000011000, 8'b00000101, 28'b0001011111001100000110110111, 8'b00011101, 56'b10100010111110011000001101101110010011100100010000011000, 8'b00000010, 28'b1000101111100110000011011100, 8'b00011110, 56'b10100010111110011000001101101110010011100100010000011000, 8'b00000001, 28'b0100010111110011000001101110, 8'b00011111, 56'b10100010111110011000001101101110010011100100010000011000, {8{1'b0}}, 28'b1010001011111001100000110111, 8'b00100000, 56'b10100010111110011000001101101110010011100100010000011000, {8{1'b0}}, 28'b0101000101111100110000011011
, 8'b00100001, 56'b10100010111110011000001101101110010011100100010000011000, {8{1'b0}}, 28'b0010100010111110011000001110, 8'b00100010, 56'b10100010111110011000001101101110010011100100010000011000, {8{1'b0}}, 28'b0001010001011111001100000111, 8'b00100011, 56'b10100010111110011000001101101110010011100100010000011000, {8{1'b0}}, 28'b0000101000101111100110000011, 8'b00100100, 56'b10100010111110011000001101101110010011100100010000011000, {8{1'b0}}, 28'b0000010100010111110011000010, 8'b00100101, 56'b10100010111110011000001101101110010011100100010000011000, {8{1'b0}}, 28'b0000001010001011111001100001, 8'b00100110, 56'b10100010111110011000001101101110010011100100010000011000, {8{1'b0}}, 28'b0000000101000101111100110000, 8'b00100111, 56'b10100010111110011000001101101110010011100100010000011000, {8{1'b0}}, 28'b0000000010100010111110011000, 8'b00101000, 56'b10100010111110011000001101101110010011100100010000011000, {8{1'b0}}, 28'b0000000001010001011111001100, 8'b00101001, 56'b10100010111110011000001101101110010011100100010000011000, {8{1'b0}}, 28'b0000000000101000101111100110, 8'b00101010, 56'b10100010111110011000001101101110010011100100010000011000, {8{1'b0}}, 28'b0000000000010100010111110011, {110{{100{1'b0}}}}}),
.result(wire_mux2_result),
.sel(address)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mux2.lpm_size = 256,
mux2.lpm_width = 100,
mux2.lpm_widths = 8,
mux2.lpm_type = "lpm_mux";
assign
basefraction = wire_mux2_result[35:0],
incexponent = wire_mux2_result[99:92],
incmantissa = wire_mux2_result[91:36];
endmodule //sin_altfp_sincos_srrt_koa
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //sin_altpriority_encoder_3e8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //sin_altpriority_encoder_3v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder10_q;
wire wire_altpriority_encoder10_zero;
wire [0:0] wire_altpriority_encoder9_q;
sin_altpriority_encoder_3e8 altpriority_encoder10
(
.data(data[3:2]),
.q(wire_altpriority_encoder10_q),
.zero(wire_altpriority_encoder10_zero));
sin_altpriority_encoder_3v7 altpriority_encoder9
(
.data(data[1:0]),
.q(wire_altpriority_encoder9_q));
assign
q = {(~ wire_altpriority_encoder10_zero), ((wire_altpriority_encoder10_zero & wire_altpriority_encoder9_q) | ((~ wire_altpriority_encoder10_zero) & wire_altpriority_encoder10_q))};
endmodule //sin_altpriority_encoder_6v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
wire [0:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
sin_altpriority_encoder_3e8 altpriority_encoder11
(
.data(data[1:0]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
sin_altpriority_encoder_3e8 altpriority_encoder12
(
.data(data[3:2]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero));
assign
q = {(~ wire_altpriority_encoder12_zero), ((wire_altpriority_encoder12_zero & wire_altpriority_encoder11_q) | ((~ wire_altpriority_encoder12_zero) & wire_altpriority_encoder12_q))},
zero = (wire_altpriority_encoder11_zero & wire_altpriority_encoder12_zero);
endmodule //sin_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder7_q;
wire [1:0] wire_altpriority_encoder8_q;
wire wire_altpriority_encoder8_zero;
sin_altpriority_encoder_6v7 altpriority_encoder7
(
.data(data[3:0]),
.q(wire_altpriority_encoder7_q));
sin_altpriority_encoder_6e8 altpriority_encoder8
(
.data(data[7:4]),
.q(wire_altpriority_encoder8_q),
.zero(wire_altpriority_encoder8_zero));
assign
q = {(~ wire_altpriority_encoder8_zero), (({2{wire_altpriority_encoder8_zero}} & wire_altpriority_encoder7_q) | ({2{(~ wire_altpriority_encoder8_zero)}} & wire_altpriority_encoder8_q))};
endmodule //sin_altpriority_encoder_bv7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
wire [1:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
sin_altpriority_encoder_6e8 altpriority_encoder13
(
.data(data[3:0]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
sin_altpriority_encoder_6e8 altpriority_encoder14
(
.data(data[7:4]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
assign
q = {(~ wire_altpriority_encoder14_zero), (({2{wire_altpriority_encoder14_zero}} & wire_altpriority_encoder13_q) | ({2{(~ wire_altpriority_encoder14_zero)}} & wire_altpriority_encoder14_q))},
zero = (wire_altpriority_encoder13_zero & wire_altpriority_encoder14_zero);
endmodule //sin_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder5_q;
wire [2:0] wire_altpriority_encoder6_q;
wire wire_altpriority_encoder6_zero;
sin_altpriority_encoder_bv7 altpriority_encoder5
(
.data(data[7:0]),
.q(wire_altpriority_encoder5_q));
sin_altpriority_encoder_be8 altpriority_encoder6
(
.data(data[15:8]),
.q(wire_altpriority_encoder6_q),
.zero(wire_altpriority_encoder6_zero));
assign
q = {(~ wire_altpriority_encoder6_zero), (({3{wire_altpriority_encoder6_zero}} & wire_altpriority_encoder5_q) | ({3{(~ wire_altpriority_encoder6_zero)}} & wire_altpriority_encoder6_q))};
endmodule //sin_altpriority_encoder_r08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
wire [2:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
sin_altpriority_encoder_be8 altpriority_encoder15
(
.data(data[7:0]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
sin_altpriority_encoder_be8 altpriority_encoder16
(
.data(data[15:8]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
assign
q = {(~ wire_altpriority_encoder16_zero), (({3{wire_altpriority_encoder16_zero}} & wire_altpriority_encoder15_q) | ({3{(~ wire_altpriority_encoder16_zero)}} & wire_altpriority_encoder16_q))},
zero = (wire_altpriority_encoder15_zero & wire_altpriority_encoder16_zero);
endmodule //sin_altpriority_encoder_rf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altpriority_encoder_qb6
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder3_q;
wire [3:0] wire_altpriority_encoder4_q;
wire wire_altpriority_encoder4_zero;
sin_altpriority_encoder_r08 altpriority_encoder3
(
.data(data[15:0]),
.q(wire_altpriority_encoder3_q));
sin_altpriority_encoder_rf8 altpriority_encoder4
(
.data(data[31:16]),
.q(wire_altpriority_encoder4_q),
.zero(wire_altpriority_encoder4_zero));
assign
q = {(~ wire_altpriority_encoder4_zero), (({4{wire_altpriority_encoder4_zero}} & wire_altpriority_encoder3_q) | ({4{(~ wire_altpriority_encoder4_zero)}} & wire_altpriority_encoder4_q))};
endmodule //sin_altpriority_encoder_qb6
//synthesis_resources = lpm_add_sub 8 lpm_clshift 2 lpm_mult 1 lpm_mux 1 reg 780
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_range_b6c
(
aclr,
circle,
clken,
clock,
data,
negcircle) ;
input aclr;
output [35:0] circle;
input clken;
input clock;
input [31:0] data;
output [35:0] negcircle;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [31:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [35:0] wire_fp_range_table1_basefraction;
wire [7:0] wire_fp_range_table1_incexponent;
wire [55:0] wire_fp_range_table1_incmantissa;
wire [4:0] wire_clz23_q;
reg [35:0] basefractiondelff;
reg [35:0] basefractionff;
reg [35:0] cbfd_0;
reg [35:0] cbfd_1;
reg [35:0] cbfd_2;
reg [35:0] cbfd_3;
reg [35:0] cbfd_4;
reg [35:0] cbfd_5;
reg [36:0] circleff;
reg [7:0] exponentff;
reg [7:0] incexponentff;
reg [55:0] incmantissaff;
reg [4:0] leadff;
reg [22:0] mantissadelff;
reg [22:0] mantissaff;
reg [22:0] mantissamultiplierff;
reg [77:0] multipliernormff;
reg [35:0] negbasefractiondelff;
reg [36:0] negcircleff;
reg [8:0] negrangeexponentff4;
reg [8:0] negrangeexponentff5;
reg [8:0] rangeexponentff_0;
reg [8:0] rangeexponentff_1;
reg [8:0] rangeexponentff_2;
reg [8:0] rangeexponentff_3;
reg [8:0] rangeexponentff_4;
reg [8:0] rangeexponentff_5;
reg [77:0] rotateff;
reg [7:0] tableaddressff;
wire [36:0] wire_circle_add_result;
wire [8:0] wire_exponent_adjust_sub_result;
wire [35:0] wire_negbasedractiondel_sub_result;
wire [36:0] wire_negcircle_add_result;
wire [8:0] wire_negrangeexponent_sub4_result;
wire [8:0] wire_negrangeexponent_sub5_result;
wire [8:0] wire_rangeexponent_sub1_result;
wire [8:0] wire_rangeexponent_sub5_result;
wire [22:0] wire_csftin_result;
wire [77:0] wire_fp_lsft_rsft78_result;
wire [78:0] wire_mult23x56_result;
wire [35:0] basefractiondelnode_w;
wire [35:0] basefractionnode_w;
wire [36:0] circlenode_w;
wire [8:0] const_23_w;
wire [7:0] incexponentnode_w;
wire [55:0] incmantissanode_w;
wire [4:0] leadnode_w;
wire [8:0] mantissaexponentnode_w;
wire [22:0] mantissamultipliernode_w;
wire [78:0] multipliernode_w;
wire [77:0] multipliernormnode_w;
wire [35:0] negbasefractiondelnode_w;
wire [36:0] negcirclenode_w;
wire [35:0] negrotatenode_w;
wire [77:0] rotatenode_w;
sin_altfp_sincos_srrt_koa fp_range_table1
(
.address(tableaddressff),
.basefraction(wire_fp_range_table1_basefraction),
.incexponent(wire_fp_range_table1_incexponent),
.incmantissa(wire_fp_range_table1_incmantissa));
sin_altpriority_encoder_qb6 clz23
(
.data({mantissaff, {9{1'b1}}}),
.q(wire_clz23_q));
// synopsys translate_off
initial
basefractiondelff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) basefractiondelff <= 36'b0;
else if (clken == 1'b1) basefractiondelff <= basefractiondelnode_w;
// synopsys translate_off
initial
basefractionff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) basefractionff <= 36'b0;
else if (clken == 1'b1) basefractionff <= basefractionnode_w;
// synopsys translate_off
initial
cbfd_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) cbfd_0 <= 36'b0;
else if (clken == 1'b1) cbfd_0 <= basefractionff;
// synopsys translate_off
initial
cbfd_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) cbfd_1 <= 36'b0;
else if (clken == 1'b1) cbfd_1 <= cbfd_0;
// synopsys translate_off
initial
cbfd_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) cbfd_2 <= 36'b0;
else if (clken == 1'b1) cbfd_2 <= cbfd_1;
// synopsys translate_off
initial
cbfd_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) cbfd_3 <= 36'b0;
else if (clken == 1'b1) cbfd_3 <= cbfd_2;
// synopsys translate_off
initial
cbfd_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) cbfd_4 <= 36'b0;
else if (clken == 1'b1) cbfd_4 <= cbfd_3;
// synopsys translate_off
initial
cbfd_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) cbfd_5 <= 36'b0;
else if (clken == 1'b1) cbfd_5 <= cbfd_4;
// synopsys translate_off
initial
circleff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) circleff <= 37'b0;
else if (clken == 1'b1) circleff <= circlenode_w;
// synopsys translate_off
initial
exponentff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponentff <= 8'b0;
else if (clken == 1'b1) exponentff <= data[30:23];
// synopsys translate_off
initial
incexponentff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) incexponentff <= 8'b0;
else if (clken == 1'b1) incexponentff <= incexponentnode_w;
// synopsys translate_off
initial
incmantissaff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) incmantissaff <= 56'b0;
else if (clken == 1'b1) incmantissaff <= incmantissanode_w;
// synopsys translate_off
initial
leadff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) leadff <= 5'b0;
else if (clken == 1'b1) leadff <= leadnode_w;
// synopsys translate_off
initial
mantissadelff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissadelff <= 23'b0;
else if (clken == 1'b1) mantissadelff <= mantissaff;
// synopsys translate_off
initial
mantissaff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissaff <= 23'b0;
else if (clken == 1'b1) mantissaff <= data[22:0];
// synopsys translate_off
initial
mantissamultiplierff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissamultiplierff <= 23'b0;
else if (clken == 1'b1) mantissamultiplierff <= mantissamultipliernode_w;
// synopsys translate_off
initial
multipliernormff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) multipliernormff <= 78'b0;
else if (clken == 1'b1) multipliernormff <= multipliernormnode_w;
// synopsys translate_off
initial
negbasefractiondelff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) negbasefractiondelff <= 36'b0;
else if (clken == 1'b1) negbasefractiondelff <= negbasefractiondelnode_w;
// synopsys translate_off
initial
negcircleff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) negcircleff <= 37'b0;
else if (clken == 1'b1) negcircleff <= negcirclenode_w;
// synopsys translate_off
initial
negrangeexponentff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) negrangeexponentff4 <= 9'b0;
else if (clken == 1'b1) negrangeexponentff4 <= wire_negrangeexponent_sub4_result;
// synopsys translate_off
initial
negrangeexponentff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) negrangeexponentff5 <= 9'b0;
else if (clken == 1'b1) negrangeexponentff5 <= wire_negrangeexponent_sub5_result;
// synopsys translate_off
initial
rangeexponentff_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rangeexponentff_0 <= 9'b0;
else if (clken == 1'b1) rangeexponentff_0 <= mantissaexponentnode_w;
// synopsys translate_off
initial
rangeexponentff_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rangeexponentff_1 <= 9'b0;
else if (clken == 1'b1) rangeexponentff_1 <= wire_rangeexponent_sub1_result;
// synopsys translate_off
initial
rangeexponentff_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rangeexponentff_2 <= 9'b0;
else if (clken == 1'b1) rangeexponentff_2 <= rangeexponentff_1;
// synopsys translate_off
initial
rangeexponentff_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rangeexponentff_3 <= 9'b0;
else if (clken == 1'b1) rangeexponentff_3 <= rangeexponentff_2;
// synopsys translate_off
initial
rangeexponentff_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rangeexponentff_4 <= 9'b0;
else if (clken == 1'b1) rangeexponentff_4 <= rangeexponentff_3;
// synopsys translate_off
initial
rangeexponentff_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rangeexponentff_5 <= 9'b0;
else if (clken == 1'b1) rangeexponentff_5 <= wire_rangeexponent_sub5_result;
// synopsys translate_off
initial
rotateff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rotateff <= 78'b0;
else if (clken == 1'b1) rotateff <= rotatenode_w;
// synopsys translate_off
initial
tableaddressff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tableaddressff <= 8'b0;
else if (clken == 1'b1) tableaddressff <= exponentff;
lpm_add_sub circle_add
(
.cout(),
.dataa({1'b0, basefractiondelff}),
.datab({1'b0, rotateff[77:42]}),
.overflow(),
.result(wire_circle_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
circle_add.lpm_direction = "ADD",
circle_add.lpm_representation = "UNSIGNED",
circle_add.lpm_width = 37,
circle_add.lpm_type = "lpm_add_sub";
lpm_add_sub exponent_adjust_sub
(
.cout(),
.dataa(const_23_w),
.datab({{4{1'b0}}, leadff}),
.overflow(),
.result(wire_exponent_adjust_sub_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exponent_adjust_sub.lpm_direction = "SUB",
exponent_adjust_sub.lpm_representation = "UNSIGNED",
exponent_adjust_sub.lpm_width = 9,
exponent_adjust_sub.lpm_type = "lpm_add_sub";
lpm_add_sub negbasedractiondel_sub
(
.cout(),
.dataa({36{1'b0}}),
.datab(basefractiondelnode_w[35:0]),
.overflow(),
.result(wire_negbasedractiondel_sub_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
negbasedractiondel_sub.lpm_direction = "SUB",
negbasedractiondel_sub.lpm_representation = "UNSIGNED",
negbasedractiondel_sub.lpm_width = 36,
negbasedractiondel_sub.lpm_type = "lpm_add_sub";
lpm_add_sub negcircle_add
(
.cin(1'b1),
.cout(),
.dataa({1'b1, negbasefractiondelff}),
.datab({1'b1, negrotatenode_w}),
.overflow(),
.result(wire_negcircle_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
negcircle_add.lpm_direction = "ADD",
negcircle_add.lpm_representation = "UNSIGNED",
negcircle_add.lpm_width = 37,
negcircle_add.lpm_type = "lpm_add_sub";
lpm_add_sub negrangeexponent_sub4
(
.cout(),
.dataa({1'b1, {8{1'b0}}}),
.datab(rangeexponentff_3),
.overflow(),
.result(wire_negrangeexponent_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
negrangeexponent_sub4.lpm_direction = "SUB",
negrangeexponent_sub4.lpm_representation = "UNSIGNED",
negrangeexponent_sub4.lpm_width = 9,
negrangeexponent_sub4.lpm_type = "lpm_add_sub";
lpm_add_sub negrangeexponent_sub5
(
.cout(),
.dataa(negrangeexponentff4),
.datab({{8{1'b0}}, (~ multipliernode_w[78])}),
.overflow(),
.result(wire_negrangeexponent_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
negrangeexponent_sub5.lpm_direction = "ADD",
negrangeexponent_sub5.lpm_representation = "UNSIGNED",
negrangeexponent_sub5.lpm_width = 9,
negrangeexponent_sub5.lpm_type = "lpm_add_sub";
lpm_add_sub rangeexponent_sub1
(
.cout(),
.dataa(rangeexponentff_0),
.datab({1'b0, incexponentff}),
.overflow(),
.result(wire_rangeexponent_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rangeexponent_sub1.lpm_direction = "SUB",
rangeexponent_sub1.lpm_representation = "UNSIGNED",
rangeexponent_sub1.lpm_width = 9,
rangeexponent_sub1.lpm_type = "lpm_add_sub";
lpm_add_sub rangeexponent_sub5
(
.cout(),
.dataa(rangeexponentff_4),
.datab({{8{1'b0}}, (~ multipliernode_w[78])}),
.overflow(),
.result(wire_rangeexponent_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rangeexponent_sub5.lpm_direction = "SUB",
rangeexponent_sub5.lpm_representation = "UNSIGNED",
rangeexponent_sub5.lpm_width = 9,
rangeexponent_sub5.lpm_type = "lpm_add_sub";
lpm_clshift csftin
(
.data(mantissadelff),
.direction(1'b0),
.distance(leadff),
.overflow(),
.result(wire_csftin_result),
.underflow()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csftin.lpm_width = 23,
csftin.lpm_widthdist = 5,
csftin.lpm_type = "lpm_clshift";
lpm_clshift fp_lsft_rsft78
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.data(multipliernormff),
.direction(negrangeexponentff5[8]),
.distance((({7{(~ negrangeexponentff5[8])}} & rangeexponentff_5[6:0]) | ({7{negrangeexponentff5[8]}} & negrangeexponentff5[6:0]))),
.overflow(),
.result(wire_fp_lsft_rsft78_result),
.underflow());
defparam
fp_lsft_rsft78.lpm_pipeline = 1,
fp_lsft_rsft78.lpm_width = 78,
fp_lsft_rsft78.lpm_widthdist = 7,
fp_lsft_rsft78.lpm_type = "lpm_clshift";
lpm_mult mult23x56
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa(mantissamultiplierff),
.datab(incmantissaff),
.result(wire_mult23x56_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult23x56.lpm_pipeline = 4,
mult23x56.lpm_representation = "UNSIGNED",
mult23x56.lpm_widtha = 23,
mult23x56.lpm_widthb = 56,
mult23x56.lpm_widthp = 79,
mult23x56.lpm_type = "lpm_mult";
assign
basefractiondelnode_w = cbfd_5,
basefractionnode_w = wire_fp_range_table1_basefraction,
circle = circleff[35:0],
circlenode_w = wire_circle_add_result,
const_23_w = 9'b000010111,
incexponentnode_w = wire_fp_range_table1_incexponent,
incmantissanode_w = wire_fp_range_table1_incmantissa,
leadnode_w = (~ wire_clz23_q),
mantissaexponentnode_w = wire_exponent_adjust_sub_result,
mantissamultipliernode_w = wire_csftin_result,
multipliernode_w = wire_mult23x56_result,
multipliernormnode_w = {((multipliernode_w[78] & multipliernode_w[78]) | (multipliernode_w[77] & (~ multipliernode_w[78]))), ((multipliernode_w[77] & multipliernode_w[78]) | (multipliernode_w[76] & (~ multipliernode_w[78]))), ((multipliernode_w[76] & multipliernode_w[78]) | (multipliernode_w[75] & (~ multipliernode_w[78]))), ((multipliernode_w[75] & multipliernode_w[78]) | (multipliernode_w[74] & (~ multipliernode_w[78]))), ((multipliernode_w[74] & multipliernode_w[78]) | (multipliernode_w[73] & (~ multipliernode_w[78]))), ((multipliernode_w[73] & multipliernode_w[78]) | (multipliernode_w[72] & (~ multipliernode_w[78]))), ((multipliernode_w[72] & multipliernode_w[78]) | (multipliernode_w[71] & (~ multipliernode_w[78]))), ((multipliernode_w[71] & multipliernode_w[78]) | (multipliernode_w[70] & (~ multipliernode_w[78]))), ((multipliernode_w[70] & multipliernode_w[78]) | (multipliernode_w[69] & (~ multipliernode_w[78]))), ((multipliernode_w[69] & multipliernode_w[78]) | (multipliernode_w[68] & (~ multipliernode_w[78]))), ((multipliernode_w[68] & multipliernode_w[78]) | (multipliernode_w[67] & (~ multipliernode_w[78]))), ((multipliernode_w[67] & multipliernode_w[78]) | (multipliernode_w[66] & (~ multipliernode_w[78]))), ((multipliernode_w[66] & multipliernode_w[78]) | (multipliernode_w[65] & (~ multipliernode_w[78]))), ((multipliernode_w[65] & multipliernode_w[78]) | (multipliernode_w[64] & (~ multipliernode_w[78]))), ((multipliernode_w[64] & multipliernode_w[78]) | (multipliernode_w[63] & (~ multipliernode_w[78]))), ((multipliernode_w[63] & multipliernode_w[78]) | (multipliernode_w[62] & (~ multipliernode_w[78]))), ((multipliernode_w[62] & multipliernode_w[78]) | (multipliernode_w[61] & (~ multipliernode_w[78]))), ((multipliernode_w[61] & multipliernode_w[78]) | (multipliernode_w[60] & (~ multipliernode_w[78]))), ((multipliernode_w[60] & multipliernode_w[78]) | (multipliernode_w[59] & (~ multipliernode_w[78]))), ((multipliernode_w[59] & multipliernode_w[78]) | (multipliernode_w[58] & (~ multipliernode_w[78]))), ((multipliernode_w[58]
& multipliernode_w[78]) | (multipliernode_w[57] & (~ multipliernode_w[78]))), ((multipliernode_w[57] & multipliernode_w[78]) | (multipliernode_w[56] & (~ multipliernode_w[78]))), ((multipliernode_w[56] & multipliernode_w[78]) | (multipliernode_w[55] & (~ multipliernode_w[78]))), ((multipliernode_w[55] & multipliernode_w[78]) | (multipliernode_w[54] & (~ multipliernode_w[78]))), ((multipliernode_w[54] & multipliernode_w[78]) | (multipliernode_w[53] & (~ multipliernode_w[78]))), ((multipliernode_w[53] & multipliernode_w[78]) | (multipliernode_w[52] & (~ multipliernode_w[78]))), ((multipliernode_w[52] & multipliernode_w[78]) | (multipliernode_w[51] & (~ multipliernode_w[78]))), ((multipliernode_w[51] & multipliernode_w[78]) | (multipliernode_w[50] & (~ multipliernode_w[78]))), ((multipliernode_w[50] & multipliernode_w[78]) | (multipliernode_w[49] & (~ multipliernode_w[78]))), ((multipliernode_w[49] & multipliernode_w[78]) | (multipliernode_w[48] & (~ multipliernode_w[78]))), ((multipliernode_w[48] & multipliernode_w[78]) | (multipliernode_w[47] & (~ multipliernode_w[78]))), ((multipliernode_w[47] & multipliernode_w[78]) | (multipliernode_w[46] & (~ multipliernode_w[78]))), ((multipliernode_w[46] & multipliernode_w[78]) | (multipliernode_w[45] & (~ multipliernode_w[78]))), ((multipliernode_w[45] & multipliernode_w[78]) | (multipliernode_w[44] & (~ multipliernode_w[78]))), ((multipliernode_w[44] & multipliernode_w[78]) | (multipliernode_w[43] & (~ multipliernode_w[78]))), ((multipliernode_w[43] & multipliernode_w[78]) | (multipliernode_w[42] & (~ multipliernode_w[78]))), ((multipliernode_w[42] & multipliernode_w[78]) | (multipliernode_w[41] & (~ multipliernode_w[78]))), ((multipliernode_w[41] & multipliernode_w[78]) | (multipliernode_w[40] & (~ multipliernode_w[78]))), ((multipliernode_w[40] & multipliernode_w[78]) | (multipliernode_w[39] & (~ multipliernode_w[78]))), ((multipliernode_w[39] & multipliernode_w[78]) | (multipliernode_w[38] & (~ multipliernode_w[78]))), ((multipliernode_w[38] & multipliernode_w[78]) | (multipliernode_w[37]
& (~ multipliernode_w[78]))), ((multipliernode_w[37] & multipliernode_w[78]) | (multipliernode_w[36] & (~ multipliernode_w[78]))), ((multipliernode_w[36] & multipliernode_w[78]) | (multipliernode_w[35] & (~ multipliernode_w[78]))), ((multipliernode_w[35] & multipliernode_w[78]) | (multipliernode_w[34] & (~ multipliernode_w[78]))), ((multipliernode_w[34] & multipliernode_w[78]) | (multipliernode_w[33] & (~ multipliernode_w[78]))), ((multipliernode_w[33] & multipliernode_w[78]) | (multipliernode_w[32] & (~ multipliernode_w[78]))), ((multipliernode_w[32] & multipliernode_w[78]) | (multipliernode_w[31] & (~ multipliernode_w[78]))), ((multipliernode_w[31] & multipliernode_w[78]) | (multipliernode_w[30] & (~ multipliernode_w[78]))), ((multipliernode_w[30] & multipliernode_w[78]) | (multipliernode_w[29] & (~ multipliernode_w[78]))), ((multipliernode_w[29] & multipliernode_w[78]) | (multipliernode_w[28] & (~ multipliernode_w[78]))), ((multipliernode_w[28] & multipliernode_w[78]) | (multipliernode_w[27] & (~ multipliernode_w[78]))), ((multipliernode_w[27] & multipliernode_w[78]) | (multipliernode_w[26] & (~ multipliernode_w[78]))), ((multipliernode_w[26] & multipliernode_w[78]) | (multipliernode_w[25] & (~ multipliernode_w[78]))), ((multipliernode_w[25] & multipliernode_w[78]) | (multipliernode_w[24] & (~ multipliernode_w[78]))), ((multipliernode_w[24] & multipliernode_w[78]) | (multipliernode_w[23] & (~ multipliernode_w[78]))), ((multipliernode_w[23] & multipliernode_w[78]) | (multipliernode_w[22] & (~ multipliernode_w[78]))), ((multipliernode_w[22] & multipliernode_w[78]) | (multipliernode_w[21] & (~ multipliernode_w[78]))), ((multipliernode_w[21] & multipliernode_w[78]) | (multipliernode_w[20] & (~ multipliernode_w[78]))), ((multipliernode_w[20] & multipliernode_w[78]) | (multipliernode_w[19] & (~ multipliernode_w[78]))), ((multipliernode_w[19] & multipliernode_w[78]) | (multipliernode_w[18] & (~ multipliernode_w[78]))), ((multipliernode_w[18] & multipliernode_w[78]) | (multipliernode_w[17] & (~ multipliernode_w[78]))
), ((multipliernode_w[17] & multipliernode_w[78]) | (multipliernode_w[16] & (~ multipliernode_w[78]))), ((multipliernode_w[16] & multipliernode_w[78]) | (multipliernode_w[15] & (~ multipliernode_w[78]))), ((multipliernode_w[15] & multipliernode_w[78]) | (multipliernode_w[14] & (~ multipliernode_w[78]))), ((multipliernode_w[14] & multipliernode_w[78]) | (multipliernode_w[13] & (~ multipliernode_w[78]))), ((multipliernode_w[13] & multipliernode_w[78]) | (multipliernode_w[12] & (~ multipliernode_w[78]))), ((multipliernode_w[12] & multipliernode_w[78]) | (multipliernode_w[11] & (~ multipliernode_w[78]))), ((multipliernode_w[11] & multipliernode_w[78]) | (multipliernode_w[10] & (~ multipliernode_w[78]))), ((multipliernode_w[10] & multipliernode_w[78]) | (multipliernode_w[9] & (~ multipliernode_w[78]))), ((multipliernode_w[9] & multipliernode_w[78]) | (multipliernode_w[8] & (~ multipliernode_w[78]))), ((multipliernode_w[8] & multipliernode_w[78]) | (multipliernode_w[7] & (~ multipliernode_w[78]))), ((multipliernode_w[7] & multipliernode_w[78]) | (multipliernode_w[6] & (~ multipliernode_w[78]))), ((multipliernode_w[6] & multipliernode_w[78]) | (multipliernode_w[5] & (~ multipliernode_w[78]))), ((multipliernode_w[5] & multipliernode_w[78]) | (multipliernode_w[4] & (~ multipliernode_w[78]))), ((multipliernode_w[4] & multipliernode_w[78]) | (multipliernode_w[3] & (~ multipliernode_w[78]))), ((multipliernode_w[3] & multipliernode_w[78]) | (multipliernode_w[2] & (~ multipliernode_w[78]))), ((multipliernode_w[2] & multipliernode_w[78]) | (multipliernode_w[1] & (~ multipliernode_w[78]))), ((multipliernode_w[1] & multipliernode_w[78]) | (multipliernode_w[0] & (~ multipliernode_w[78])))},
negbasefractiondelnode_w = wire_negbasedractiondel_sub_result,
negcircle = negcircleff[35:0],
negcirclenode_w = wire_negcircle_add_result,
negrotatenode_w = {(~ rotateff[77]), (~ rotateff[76]), (~ rotateff[75]), (~ rotateff[74]), (~ rotateff[73]), (~ rotateff[72]), (~ rotateff[71]), (~ rotateff[70]), (~ rotateff[69]), (~ rotateff[68]), (~ rotateff[67]), (~ rotateff[66]), (~ rotateff[65]), (~ rotateff[64]), (~ rotateff[63]), (~ rotateff[62]), (~ rotateff[61]), (~ rotateff[60]), (~ rotateff[59]), (~ rotateff[58]), (~ rotateff[57]), (~ rotateff[56]), (~ rotateff[55]), (~ rotateff[54]), (~ rotateff[53]), (~ rotateff[52]), (~ rotateff[51]), (~ rotateff[50]), (~ rotateff[49]), (~ rotateff[48]), (~ rotateff[47]), (~ rotateff[46]), (~ rotateff[45]), (~ rotateff[44]), (~ rotateff[43]), (~ rotateff[42])},
rotatenode_w = wire_fp_lsft_rsft78_result;
endmodule //sin_altfp_sincos_range_b6c
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=64 WIDTHAD=6 data q
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altpriority_encoder_q08
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder19_q;
wire [3:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
sin_altpriority_encoder_r08 altpriority_encoder19
(
.data(data[15:0]),
.q(wire_altpriority_encoder19_q));
sin_altpriority_encoder_rf8 altpriority_encoder20
(
.data(data[31:16]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
assign
q = {(~ wire_altpriority_encoder20_zero), (({4{wire_altpriority_encoder20_zero}} & wire_altpriority_encoder19_q) | ({4{(~ wire_altpriority_encoder20_zero)}} & wire_altpriority_encoder20_q))};
endmodule //sin_altpriority_encoder_q08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q zero
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altpriority_encoder_qf8
(
data,
q,
zero) ;
input [31:0] data;
output [4:0] q;
output zero;
wire [3:0] wire_altpriority_encoder21_q;
wire wire_altpriority_encoder21_zero;
wire [3:0] wire_altpriority_encoder22_q;
wire wire_altpriority_encoder22_zero;
sin_altpriority_encoder_rf8 altpriority_encoder21
(
.data(data[15:0]),
.q(wire_altpriority_encoder21_q),
.zero(wire_altpriority_encoder21_zero));
sin_altpriority_encoder_rf8 altpriority_encoder22
(
.data(data[31:16]),
.q(wire_altpriority_encoder22_q),
.zero(wire_altpriority_encoder22_zero));
assign
q = {(~ wire_altpriority_encoder22_zero), (({4{wire_altpriority_encoder22_zero}} & wire_altpriority_encoder21_q) | ({4{(~ wire_altpriority_encoder22_zero)}} & wire_altpriority_encoder22_q))},
zero = (wire_altpriority_encoder21_zero & wire_altpriority_encoder22_zero);
endmodule //sin_altpriority_encoder_qf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altpriority_encoder_0c6
(
data,
q) ;
input [63:0] data;
output [5:0] q;
wire [4:0] wire_altpriority_encoder17_q;
wire [4:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
sin_altpriority_encoder_q08 altpriority_encoder17
(
.data(data[31:0]),
.q(wire_altpriority_encoder17_q));
sin_altpriority_encoder_qf8 altpriority_encoder18
(
.data(data[63:32]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
assign
q = {(~ wire_altpriority_encoder18_zero), (({5{wire_altpriority_encoder18_zero}} & wire_altpriority_encoder17_q) | ({5{(~ wire_altpriority_encoder18_zero)}} & wire_altpriority_encoder18_q))};
endmodule //sin_altpriority_encoder_0c6
//synthesis_resources = lpm_add_sub 52 lpm_clshift 3 lpm_mult 3 lpm_mux 2 reg 3720
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module sin_altfp_sincos_47e
(
clock,
data,
result) ;
input clock;
input [31:0] data;
output [31:0] result;
wire [33:0] wire_ccc_cordic_m_sincos;
wire [35:0] wire_crr_fp_range1_circle;
wire [35:0] wire_crr_fp_range1_negcircle;
wire [5:0] wire_clz_q;
reg [5:0] countff;
reg [7:0] exponentinff;
reg [7:0] exponentnormff;
reg [7:0] exponentoutff;
reg [35:0] fixed_sincosff;
reg [31:0] input_delay_ff_0;
reg [31:0] input_delay_ff_1;
reg [31:0] input_delay_ff_10;
reg [31:0] input_delay_ff_11;
reg [31:0] input_delay_ff_12;
reg [31:0] input_delay_ff_13;
reg [31:0] input_delay_ff_14;
reg [31:0] input_delay_ff_15;
reg [31:0] input_delay_ff_16;
reg [31:0] input_delay_ff_17;
reg [31:0] input_delay_ff_18;
reg [31:0] input_delay_ff_19;
reg [31:0] input_delay_ff_2;
reg [31:0] input_delay_ff_20;
reg [31:0] input_delay_ff_21;
reg [31:0] input_delay_ff_22;
reg [31:0] input_delay_ff_23;
reg [31:0] input_delay_ff_24;
reg [31:0] input_delay_ff_25;
reg [31:0] input_delay_ff_26;
reg [31:0] input_delay_ff_27;
reg [31:0] input_delay_ff_28;
reg [31:0] input_delay_ff_29;
reg [31:0] input_delay_ff_3;
reg [31:0] input_delay_ff_30;
reg [31:0] input_delay_ff_31;
reg [31:0] input_delay_ff_32;
reg [31:0] input_delay_ff_33;
reg [31:0] input_delay_ff_34;
reg [31:0] input_delay_ff_4;
reg [31:0] input_delay_ff_5;
reg [31:0] input_delay_ff_6;
reg [31:0] input_delay_ff_7;
reg [31:0] input_delay_ff_8;
reg [31:0] input_delay_ff_9;
reg [22:0] mantissanormff;
reg [22:0] mantissaoutff;
reg [35:0] quadrant_sumff;
reg [3:0] select_sincosff;
reg [33:0] selectoutputff;
reg [23:0] signcalcff;
reg [10:0] signinff;
reg signoutff;
wire [8:0] wire_exponentcheck_sub_result;
wire [7:0] wire_exponentnorm_add_result;
wire [7:0] wire_exponentnormmode_sub_result;
wire [22:0] wire_mantissanorm_add_result;
wire [35:0] wire_quadrantsum_add_result;
wire [35:0] wire_sft_result;
wire [33:0] wire_cmul_result;
wire aclr;
wire [35:0] circle_w;
wire clk_en;
wire [5:0] countnode_w;
wire [8:0] exponentcheck_w;
wire [7:0] exponentnormmode_w;
wire [33:0] fixed_sincos_w;
wire [35:0] fixed_sincosnode_w;
wire [35:0] fraction_quadrant_w;
wire indexbit_w;
wire [15:0] indexcheck_w;
wire [31:0] input_number_delay_w;
wire [31:0] input_number_w;
wire [35:0] mantissanormnode_w;
wire [35:0] negative_quadrant_w;
wire [35:0] negcircle_w;
wire [35:0] one_term_w;
wire [23:0] overflownode_w;
wire [35:0] piovertwo_w;
wire [35:0] positive_quadrant_w;
wire [33:0] quadrant_w;
wire quadrantselect_w;
wire quadrantsign_w;
wire [33:0] radiansnode_w;
wire [7:0] value_128_w;
wire [7:0] value_x73_w;
wire [35:0] zerovec_w;
sin_altfp_sincos_cordic_m_e5e ccc_cordic_m
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.indexbit(indexbit_w),
.radians(radiansnode_w),
.sincos(wire_ccc_cordic_m_sincos),
.sincosbit(select_sincosff[3]));
sin_altfp_sincos_range_b6c crr_fp_range1
(
.aclr(aclr),
.circle(wire_crr_fp_range1_circle),
.clken(clk_en),
.clock(clock),
.data(data),
.negcircle(wire_crr_fp_range1_negcircle));
sin_altpriority_encoder_0c6 clz
(
.data({fixed_sincosnode_w, {28{1'b1}}}),
.q(wire_clz_q));
// synopsys translate_off
initial
countff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) countff <= 6'b0;
else if (clk_en == 1'b1) countff <= countnode_w;
// synopsys translate_off
initial
exponentinff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponentinff <= 8'b0;
else if (clk_en == 1'b1) exponentinff <= data[30:23];
// synopsys translate_off
initial
exponentnormff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponentnormff <= 8'b0;
else if (clk_en == 1'b1) exponentnormff <= wire_exponentnorm_add_result;
// synopsys translate_off
initial
exponentoutff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponentoutff <= 8'b0;
else if (clk_en == 1'b1) exponentoutff <= ((exponentnormff & {8{(~ selectoutputff[33])}}) | (input_number_delay_w[30:23] & {8{selectoutputff[33]}}));
// synopsys translate_off
initial
fixed_sincosff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) fixed_sincosff <= 36'b0;
else if (clk_en == 1'b1) fixed_sincosff <= fixed_sincosnode_w;
// synopsys translate_off
initial
input_delay_ff_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_0 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_0 <= input_number_w;
// synopsys translate_off
initial
input_delay_ff_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_1 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_1 <= input_delay_ff_0;
// synopsys translate_off
initial
input_delay_ff_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_10 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_10 <= input_delay_ff_9;
// synopsys translate_off
initial
input_delay_ff_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_11 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_11 <= input_delay_ff_10;
// synopsys translate_off
initial
input_delay_ff_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_12 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_12 <= input_delay_ff_11;
// synopsys translate_off
initial
input_delay_ff_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_13 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_13 <= input_delay_ff_12;
// synopsys translate_off
initial
input_delay_ff_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_14 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_14 <= input_delay_ff_13;
// synopsys translate_off
initial
input_delay_ff_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_15 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_15 <= input_delay_ff_14;
// synopsys translate_off
initial
input_delay_ff_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_16 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_16 <= input_delay_ff_15;
// synopsys translate_off
initial
input_delay_ff_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_17 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_17 <= input_delay_ff_16;
// synopsys translate_off
initial
input_delay_ff_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_18 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_18 <= input_delay_ff_17;
// synopsys translate_off
initial
input_delay_ff_19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_19 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_19 <= input_delay_ff_18;
// synopsys translate_off
initial
input_delay_ff_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_2 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_2 <= input_delay_ff_1;
// synopsys translate_off
initial
input_delay_ff_20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_20 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_20 <= input_delay_ff_19;
// synopsys translate_off
initial
input_delay_ff_21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_21 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_21 <= input_delay_ff_20;
// synopsys translate_off
initial
input_delay_ff_22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_22 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_22 <= input_delay_ff_21;
// synopsys translate_off
initial
input_delay_ff_23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_23 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_23 <= input_delay_ff_22;
// synopsys translate_off
initial
input_delay_ff_24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_24 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_24 <= input_delay_ff_23;
// synopsys translate_off
initial
input_delay_ff_25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_25 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_25 <= input_delay_ff_24;
// synopsys translate_off
initial
input_delay_ff_26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_26 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_26 <= input_delay_ff_25;
// synopsys translate_off
initial
input_delay_ff_27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_27 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_27 <= input_delay_ff_26;
// synopsys translate_off
initial
input_delay_ff_28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_28 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_28 <= input_delay_ff_27;
// synopsys translate_off
initial
input_delay_ff_29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_29 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_29 <= input_delay_ff_28;
// synopsys translate_off
initial
input_delay_ff_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_3 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_3 <= input_delay_ff_2;
// synopsys translate_off
initial
input_delay_ff_30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_30 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_30 <= input_delay_ff_29;
// synopsys translate_off
initial
input_delay_ff_31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_31 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_31 <= input_delay_ff_30;
// synopsys translate_off
initial
input_delay_ff_32 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_32 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_32 <= input_delay_ff_31;
// synopsys translate_off
initial
input_delay_ff_33 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_33 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_33 <= input_delay_ff_32;
// synopsys translate_off
initial
input_delay_ff_34 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_34 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_34 <= input_delay_ff_33;
// synopsys translate_off
initial
input_delay_ff_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_4 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_4 <= input_delay_ff_3;
// synopsys translate_off
initial
input_delay_ff_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_5 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_5 <= input_delay_ff_4;
// synopsys translate_off
initial
input_delay_ff_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_6 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_6 <= input_delay_ff_5;
// synopsys translate_off
initial
input_delay_ff_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_7 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_7 <= input_delay_ff_6;
// synopsys translate_off
initial
input_delay_ff_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_8 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_8 <= input_delay_ff_7;
// synopsys translate_off
initial
input_delay_ff_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_delay_ff_9 <= 32'b0;
else if (clk_en == 1'b1) input_delay_ff_9 <= input_delay_ff_8;
// synopsys translate_off
initial
mantissanormff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissanormff <= 23'b0;
else if (clk_en == 1'b1) mantissanormff <= wire_mantissanorm_add_result;
// synopsys translate_off
initial
mantissaoutff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissaoutff <= 23'b0;
else if (clk_en == 1'b1) mantissaoutff <= ((mantissanormff & {23{(~ selectoutputff[33])}}) | (input_number_delay_w[22:0] & {23{selectoutputff[33]}}));
// synopsys translate_off
initial
quadrant_sumff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quadrant_sumff <= 36'b0;
else if (clk_en == 1'b1) quadrant_sumff <= wire_quadrantsum_add_result;
// synopsys translate_off
initial
select_sincosff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) select_sincosff <= 4'b0;
else if (clk_en == 1'b1) select_sincosff <= {select_sincosff[2:0], quadrant_w[33]};
// synopsys translate_off
initial
selectoutputff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) selectoutputff <= 34'b0;
else if (clk_en == 1'b1) selectoutputff <= {selectoutputff[32:0], exponentcheck_w[8]};
// synopsys translate_off
initial
signcalcff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) signcalcff <= 24'b0;
else if (clk_en == 1'b1) signcalcff <= {signcalcff[22:0], (quadrantsign_w ^ signinff[10])};
// synopsys translate_off
initial
signinff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) signinff <= 11'b0;
else if (clk_en == 1'b1) signinff <= {signinff[9:0], data[31]};
// synopsys translate_off
initial
signoutff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) signoutff <= 1'b0;
else if (clk_en == 1'b1) signoutff <= ((signcalcff[23] & (~ selectoutputff[33])) | (input_number_delay_w[31] & selectoutputff[33]));
lpm_add_sub exponentcheck_sub
(
.cout(),
.dataa({1'b0, exponentinff}),
.datab({1'b0, value_x73_w}),
.overflow(),
.result(wire_exponentcheck_sub_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exponentcheck_sub.lpm_direction = "SUB",
exponentcheck_sub.lpm_representation = "UNSIGNED",
exponentcheck_sub.lpm_width = 9,
exponentcheck_sub.lpm_type = "lpm_add_sub";
lpm_add_sub exponentnorm_add
(
.cout(),
.dataa(exponentnormmode_w[7:0]),
.datab({{7{1'b0}}, overflownode_w[23]}),
.overflow(),
.result(wire_exponentnorm_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exponentnorm_add.lpm_direction = "ADD",
exponentnorm_add.lpm_representation = "UNSIGNED",
exponentnorm_add.lpm_width = 8,
exponentnorm_add.lpm_type = "lpm_add_sub";
lpm_add_sub exponentnormmode_sub
(
.cout(),
.dataa(value_128_w),
.datab({{2{1'b0}}, countff}),
.overflow(),
.result(wire_exponentnormmode_sub_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exponentnormmode_sub.lpm_direction = "SUB",
exponentnormmode_sub.lpm_representation = "UNSIGNED",
exponentnormmode_sub.lpm_width = 8,
exponentnormmode_sub.lpm_type = "lpm_add_sub";
lpm_add_sub mantissanorm_add
(
.cout(),
.dataa(mantissanormnode_w[34:12]),
.datab({{22{1'b0}}, mantissanormnode_w[11]}),
.overflow(),
.result(wire_mantissanorm_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mantissanorm_add.lpm_direction = "ADD",
mantissanorm_add.lpm_representation = "UNSIGNED",
mantissanorm_add.lpm_width = 23,
mantissanorm_add.lpm_type = "lpm_add_sub";
lpm_add_sub quadrantsum_add
(
.cin((~ quadrant_w[33])),
.cout(),
.dataa(one_term_w),
.datab(fraction_quadrant_w),
.overflow(),
.result(wire_quadrantsum_add_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
quadrantsum_add.lpm_direction = "ADD",
quadrantsum_add.lpm_representation = "UNSIGNED",
quadrantsum_add.lpm_width = 36,
quadrantsum_add.lpm_type = "lpm_add_sub";
lpm_clshift sft
(
.data(fixed_sincosff),
.direction(1'b0),
.distance(countff),
.overflow(),
.result(wire_sft_result),
.underflow()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
sft.lpm_width = 36,
sft.lpm_widthdist = 6,
sft.lpm_type = "lpm_clshift";
lpm_mult cmul
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(quadrant_sumff),
.datab(piovertwo_w),
.result(wire_cmul_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmul.lpm_pipeline = 3,
cmul.lpm_representation = "UNSIGNED",
cmul.lpm_widtha = 36,
cmul.lpm_widthb = 36,
cmul.lpm_widthp = 34,
cmul.lpm_type = "lpm_mult";
assign
aclr = 1'b0,
circle_w = wire_crr_fp_range1_circle,
clk_en = 1'b1,
countnode_w = (~ wire_clz_q),
exponentcheck_w = wire_exponentcheck_sub_result,
exponentnormmode_w = wire_exponentnormmode_sub_result,
fixed_sincos_w = wire_ccc_cordic_m_sincos,
fixed_sincosnode_w = {fixed_sincos_w, zerovec_w[1:0]},
fraction_quadrant_w = ((positive_quadrant_w & {36{quadrant_w[33]}}) | (negative_quadrant_w & {36{(~ quadrant_w[33])}})),
indexbit_w = (~ indexcheck_w[3]),
indexcheck_w = {(indexcheck_w[14] | radiansnode_w[18]), (indexcheck_w[13] | radiansnode_w[19]), (indexcheck_w[12] | radiansnode_w[20]), (indexcheck_w[11] | radiansnode_w[21]), (indexcheck_w[10] | radiansnode_w[22]), (indexcheck_w[9] | radiansnode_w[23]), (indexcheck_w[8] | radiansnode_w[24]), (indexcheck_w[7] | radiansnode_w[25]), (indexcheck_w[6] | radiansnode_w[26]), (indexcheck_w[5] | radiansnode_w[27]), (indexcheck_w[4] | radiansnode_w[28]), (indexcheck_w[3] | radiansnode_w[29]), (indexcheck_w[2] | radiansnode_w[30]), (indexcheck_w[1] | radiansnode_w[31]), (indexcheck_w[0] | radiansnode_w[32]), radiansnode_w[32]},
input_number_delay_w = input_delay_ff_34,
input_number_w = data,
mantissanormnode_w = wire_sft_result,
negative_quadrant_w = (~ positive_quadrant_w),
negcircle_w = wire_crr_fp_range1_negcircle,
one_term_w = {(~ quadrant_w[33]), zerovec_w[34:0]},
overflownode_w = {(mantissanormnode_w[34] & overflownode_w[22]), (mantissanormnode_w[33] & overflownode_w[21]), (mantissanormnode_w[32] & overflownode_w[20]), (mantissanormnode_w[31] & overflownode_w[19]), (mantissanormnode_w[30] & overflownode_w[18]), (mantissanormnode_w[29] & overflownode_w[17]), (mantissanormnode_w[28] & overflownode_w[16]), (mantissanormnode_w[27] & overflownode_w[15]), (mantissanormnode_w[26] & overflownode_w[14]), (mantissanormnode_w[25] & overflownode_w[13]), (mantissanormnode_w[24] & overflownode_w[12]), (mantissanormnode_w[23] & overflownode_w[11]), (mantissanormnode_w[22] & overflownode_w[10]), (mantissanormnode_w[21] & overflownode_w[9]), (mantissanormnode_w[20] & overflownode_w[8]), (mantissanormnode_w[19] & overflownode_w[7]), (mantissanormnode_w[18] & overflownode_w[6]), (mantissanormnode_w[17] & overflownode_w[5]), (mantissanormnode_w[16] & overflownode_w[4]), (mantissanormnode_w[15] & overflownode_w[3]), (mantissanormnode_w[14] & overflownode_w[2]), (mantissanormnode_w[13] & overflownode_w[1]), (mantissanormnode_w[12] & overflownode_w[0]), mantissanormnode_w[11]},
piovertwo_w = 36'b110010010000111111011010101000100010,
positive_quadrant_w = {1'b0, quadrant_w, 1'b0},
quadrant_w = ((circle_w[33:0] & {34{(~ quadrantselect_w)}}) | (negcircle_w[33:0] & {34{quadrantselect_w}})),
quadrantselect_w = circle_w[34],
quadrantsign_w = circle_w[35],
radiansnode_w = wire_cmul_result,
result = {signoutff, exponentoutff, mantissaoutff},
value_128_w = 8'b10000000,
value_x73_w = 8'b01110011,
zerovec_w = {36{1'b0}};
endmodule //sin_altfp_sincos_47e
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sin (
clock,
data,
result);
input clock;
input [31:0] data;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
sin_altfp_sincos_47e sin_altfp_sincos_47e_component (
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: OPERATION STRING "SIN"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "36"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sin.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sin.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sin.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sin.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sin_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sin_bb.v TRUE
|
// ======================================================================
// IceTimer.v generated from TopDesign.cysch
// 03/23/2015 at 22:37
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PSOC5LP 3
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_PANTHER 4
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 1
`define CYDEV_CHIP_REV_EXPECT 3
`define CYDEV_CHIP_DIE_ACTUAL 1
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4D 2
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4A 3
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4F 4
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5B 5
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_MEMBER_5A 6
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_FAMILY_USED 1
`define CYDEV_CHIP_MEMBER_USED 1
`define CYDEV_CHIP_REVISION_USED 3
// CharLCD_v2_10(ConversionRoutines=true, CUSTOM0=0,E,8,8,8,E,0, CUSTOM1=0,A,A,4,4,4,0, CUSTOM2=0,E,A,E,8,8,0, CUSTOM3=0,E,A,C,A,A,0, CUSTOM4=0,E,8,C,8,E,0, CUSTOM5=0,E,8,E,2,E,0, CUSTOM6=0,E,8,E,2,E,0, CUSTOM7=0,4,4,4,0,4,0, CustomCharacterSet=0, TypeReplacementString=uint8, CY_COMPONENT_NAME=CharLCD_v2_10, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=LCD, CY_INSTANCE_SHORT_NAME=LCD, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.1 SP1, INSTANCE_NAME=LCD, )
module CharLCD_v2_10_0 ;
wire [6:0] tmpOE__LCDPort_net;
wire [6:0] tmpFB_6__LCDPort_net;
wire [6:0] tmpIO_6__LCDPort_net;
wire [0:0] tmpINTERRUPT_0__LCDPort_net;
electrical [0:0] tmpSIOVREF__LCDPort_net;
cy_psoc3_pins_v1_10
#(.id("eac6719e-57a0-443e-b031-12c3844529de/ed092b9b-d398-4703-be89-cebf998501f6"),
.drive_mode(21'b110_110_110_110_110_110_110),
.ibuf_enabled(7'b1_1_1_1_1_1_1),
.init_dr_st(7'b0_0_0_0_0_0_0),
.input_clk_en(0),
.input_sync(7'b1_1_1_1_1_1_1),
.input_sync_mode(7'b0_0_0_0_0_0_0),
.intr_mode(14'b00_00_00_00_00_00_00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(",,,,,,"),
.layout_mode("CONTIGUOUS"),
.oe_conn(7'b0_0_0_0_0_0_0),
.oe_reset(0),
.oe_sync(7'b0_0_0_0_0_0_0),
.output_clk_en(0),
.output_clock_mode(7'b0_0_0_0_0_0_0),
.output_conn(7'b0_0_0_0_0_0_0),
.output_mode(7'b0_0_0_0_0_0_0),
.output_reset(0),
.output_sync(7'b0_0_0_0_0_0_0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(",,,,,,"),
.pin_mode("OOOOOOO"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(7'b1_1_1_1_1_1_1),
.sio_ibuf(""),
.sio_info(14'b00_00_00_00_00_00_00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(7'b0_0_0_0_0_0_0),
.spanning(0),
.use_annotation(7'b0_0_0_0_0_0_0),
.vtrip(14'b10_10_10_10_10_10_10),
.width(7),
.ovt_hyst_trim(7'b0_0_0_0_0_0_0),
.ovt_needed(7'b0_0_0_0_0_0_0),
.ovt_slew_control(14'b00_00_00_00_00_00_00),
.input_buffer_sel(14'b00_00_00_00_00_00_00))
LCDPort
(.oe(tmpOE__LCDPort_net),
.y({7'b0}),
.fb({tmpFB_6__LCDPort_net[6:0]}),
.io({tmpIO_6__LCDPort_net[6:0]}),
.siovref(tmpSIOVREF__LCDPort_net),
.interrupt({tmpINTERRUPT_0__LCDPort_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LCDPort_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{7'b1111111} : {7'b1111111};
endmodule
// Component: Debouncer_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Debouncer_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Debouncer_v1_0\Debouncer_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Debouncer_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Debouncer_v1_0\Debouncer_v1_0.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: OneTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v"
`endif
// Component: B_Counter_v2_40
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Counter_v2_40"
`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Counter_v2_40\B_Counter_v2_40.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Counter_v2_40"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Counter_v2_40\B_Counter_v2_40.v"
`endif
// Counter_v2_40(CaptureMode=0, CaptureModeSoftware=0, ClockMode=0, CompareMode=0, CompareModeSoftware=0, CompareStatusEdgeSense=true, CompareValue=60, CONTROL3=0, ControlRegRemoved=1, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG8, CySetRegReplacementString=CY_SET_REG8, EnableMode=1, FF16=false, FF8=false, FixedFunction=false, FixedFunctionUsed=0, InitCounterValue=0, InterruptOnCapture=false, InterruptOnCompare=false, InterruptOnOverUnderFlow=false, InterruptOnTC=false, Period=60, RegDefReplacementString=reg8, RegSizeReplacementString=uint8, ReloadOnCapture=false, ReloadOnCompare=false, ReloadOnOverUnder=true, ReloadOnReset=true, Resolution=8, RstStatusReplacementString=sSTSReg_rstSts, RunMode=0, UDB16=false, UDB24=false, UDB32=false, UDB8=true, UDBControlReg=false, UseInterrupt=true, VerilogSectionReplacementString=sC8, CY_COMPONENT_NAME=Counter_v2_40, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=sec_CNTR, CY_INSTANCE_SHORT_NAME=sec_CNTR, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=40, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.1 SP1, INSTANCE_NAME=sec_CNTR, )
module Counter_v2_40_1 (
clock,
comp,
tc,
reset,
interrupt,
enable,
capture,
upCnt,
downCnt,
up_ndown,
count);
input clock;
output comp;
output tc;
input reset;
output interrupt;
input enable;
input capture;
input upCnt;
input downCnt;
input up_ndown;
input count;
parameter CaptureMode = 0;
parameter ClockMode = 0;
parameter CompareMode = 0;
parameter CompareStatusEdgeSense = 1;
parameter EnableMode = 1;
parameter ReloadOnCapture = 0;
parameter ReloadOnCompare = 0;
parameter ReloadOnOverUnder = 1;
parameter ReloadOnReset = 1;
parameter Resolution = 8;
parameter RunMode = 0;
parameter UseInterrupt = 1;
wire Net_54;
wire Net_102;
wire Net_95;
wire Net_82;
wire Net_91;
wire Net_89;
wire Net_49;
wire Net_48;
wire Net_42;
wire Net_43;
// int_vm (cy_virtualmux_v1_0)
assign interrupt = Net_43;
// TC_vm (cy_virtualmux_v1_0)
assign tc = Net_49;
ZeroTerminal ZeroTerminal_1 (
.z(Net_82));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_89 = up_ndown;
ZeroTerminal ZeroTerminal_2 (
.z(Net_95));
// vmEnableMode (cy_virtualmux_v1_0)
assign Net_91 = Net_102;
OneTerminal OneTerminal_1 (
.o(Net_102));
B_Counter_v2_40 CounterUDB (
.reset(reset),
.tc_out(Net_49),
.cmp_out(comp),
.clock(clock),
.irq_out(Net_43),
.up_ndown(Net_89),
.upcnt(upCnt),
.dwncnt(downCnt),
.enable(enable),
.capture(capture),
.count(count));
defparam CounterUDB.CaptureMode = 0;
defparam CounterUDB.ClockMode = 0;
defparam CounterUDB.CompareMode = 0;
defparam CounterUDB.CompareStatusEdgeSense = 1;
defparam CounterUDB.EnableMode = 1;
defparam CounterUDB.ReloadOnCapture = 0;
defparam CounterUDB.ReloadOnCompare = 0;
defparam CounterUDB.ReloadOnOverUnder = 1;
defparam CounterUDB.ReloadOnReset = 1;
defparam CounterUDB.Resolution = 8;
defparam CounterUDB.RunMode = 0;
defparam CounterUDB.UseInterrupt = 1;
endmodule
// Component: not_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\not_v1_0\not_v1_0.v"
`endif
// Counter_v2_40(CaptureMode=0, CaptureModeSoftware=0, ClockMode=0, CompareMode=0, CompareModeSoftware=0, CompareStatusEdgeSense=true, CompareValue=60, CONTROL3=0, ControlRegRemoved=1, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG8, CySetRegReplacementString=CY_SET_REG8, EnableMode=1, FF16=false, FF8=false, FixedFunction=false, FixedFunctionUsed=0, InitCounterValue=0, InterruptOnCapture=false, InterruptOnCompare=false, InterruptOnOverUnderFlow=false, InterruptOnTC=false, Period=60, RegDefReplacementString=reg8, RegSizeReplacementString=uint8, ReloadOnCapture=false, ReloadOnCompare=false, ReloadOnOverUnder=true, ReloadOnReset=true, Resolution=8, RstStatusReplacementString=sSTSReg_rstSts, RunMode=0, UDB16=false, UDB24=false, UDB32=false, UDB8=true, UDBControlReg=false, UseInterrupt=true, VerilogSectionReplacementString=sC8, CY_COMPONENT_NAME=Counter_v2_40, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=min_CNTR, CY_INSTANCE_SHORT_NAME=min_CNTR, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=40, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.1 SP1, INSTANCE_NAME=min_CNTR, )
module Counter_v2_40_2 (
clock,
comp,
tc,
reset,
interrupt,
enable,
capture,
upCnt,
downCnt,
up_ndown,
count);
input clock;
output comp;
output tc;
input reset;
output interrupt;
input enable;
input capture;
input upCnt;
input downCnt;
input up_ndown;
input count;
parameter CaptureMode = 0;
parameter ClockMode = 0;
parameter CompareMode = 0;
parameter CompareStatusEdgeSense = 1;
parameter EnableMode = 1;
parameter ReloadOnCapture = 0;
parameter ReloadOnCompare = 0;
parameter ReloadOnOverUnder = 1;
parameter ReloadOnReset = 1;
parameter Resolution = 8;
parameter RunMode = 0;
parameter UseInterrupt = 1;
wire Net_54;
wire Net_102;
wire Net_95;
wire Net_82;
wire Net_91;
wire Net_89;
wire Net_49;
wire Net_48;
wire Net_42;
wire Net_43;
// int_vm (cy_virtualmux_v1_0)
assign interrupt = Net_43;
// TC_vm (cy_virtualmux_v1_0)
assign tc = Net_49;
ZeroTerminal ZeroTerminal_1 (
.z(Net_82));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_89 = up_ndown;
ZeroTerminal ZeroTerminal_2 (
.z(Net_95));
// vmEnableMode (cy_virtualmux_v1_0)
assign Net_91 = Net_102;
OneTerminal OneTerminal_1 (
.o(Net_102));
B_Counter_v2_40 CounterUDB (
.reset(reset),
.tc_out(Net_49),
.cmp_out(comp),
.clock(clock),
.irq_out(Net_43),
.up_ndown(Net_89),
.upcnt(upCnt),
.dwncnt(downCnt),
.enable(enable),
.capture(capture),
.count(count));
defparam CounterUDB.CaptureMode = 0;
defparam CounterUDB.ClockMode = 0;
defparam CounterUDB.CompareMode = 0;
defparam CounterUDB.CompareStatusEdgeSense = 1;
defparam CounterUDB.EnableMode = 1;
defparam CounterUDB.ReloadOnCapture = 0;
defparam CounterUDB.ReloadOnCompare = 0;
defparam CounterUDB.ReloadOnOverUnder = 1;
defparam CounterUDB.ReloadOnReset = 1;
defparam CounterUDB.Resolution = 8;
defparam CounterUDB.RunMode = 0;
defparam CounterUDB.UseInterrupt = 1;
endmodule
// Timer_v2_70(CaptureAlternatingFall=false, CaptureAlternatingRise=false, CaptureCount=2, CaptureCounterEnabled=false, CaptureInputEnabled=false, CaptureMode=0, CONTROL3=1, ControlRegRemoved=0, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG8, CySetRegReplacementString=CY_SET_REG8, DeviceFamily=PSoC3, EnableMode=2, FF16=false, FF8=true, FixedFunction=true, FixedFunctionUsed=1, HWCaptureCounterEnabled=false, InterruptOnCapture=false, InterruptOnFIFOFull=false, InterruptOnTC=false, IntOnCapture=0, IntOnFIFOFull=0, IntOnTC=0, NumberOfCaptures=1, param45=1, Period=99, RegDefReplacementString=reg8, RegSizeReplacementString=uint8, Resolution=8, RstStatusReplacementString=rstSts, RunMode=0, SiliconRevision=3, SoftwareCaptureModeEnabled=false, SoftwareTriggerModeEnabled=false, TriggerInputEnabled=false, TriggerMode=0, UDB16=false, UDB24=false, UDB32=false, UDB8=false, UDBControlReg=false, UsesHWEnable=1, VerilogSectionReplacementString=sT8, CY_COMPONENT_NAME=Timer_v2_70, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=Timer, CY_INSTANCE_SHORT_NAME=Timer, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=70, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.1 SP1, INSTANCE_NAME=Timer, )
module Timer_v2_70_3 (
clock,
reset,
interrupt,
enable,
capture,
trigger,
capture_out,
tc);
input clock;
input reset;
output interrupt;
input enable;
input capture;
input trigger;
output capture_out;
output tc;
parameter CaptureCount = 2;
parameter CaptureCounterEnabled = 0;
parameter DeviceFamily = "PSoC3";
parameter InterruptOnCapture = 0;
parameter InterruptOnTC = 0;
parameter Resolution = 8;
parameter SiliconRevision = "3";
wire Net_261;
wire Net_260;
wire Net_266;
wire Net_102;
wire Net_55;
wire Net_57;
wire Net_53;
wire Net_51;
cy_psoc3_timer_v1_0 TimerHW (
.timer_reset(reset),
.capture(capture),
.enable(Net_266),
.kill(Net_260),
.clock(clock),
.tc(Net_51),
.compare(Net_261),
.interrupt(Net_57));
ZeroTerminal ZeroTerminal_1 (
.z(Net_260));
// VirtualMux_2 (cy_virtualmux_v1_0)
assign interrupt = Net_57;
// VirtualMux_3 (cy_virtualmux_v1_0)
assign tc = Net_51;
OneTerminal OneTerminal_1 (
.o(Net_102));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_266 = enable;
endmodule
// Counter_v2_40(CaptureMode=0, CaptureModeSoftware=0, ClockMode=0, CompareMode=5, CompareModeSoftware=1, CompareStatusEdgeSense=true, CompareValue=10, CONTROL3=0, ControlRegRemoved=0, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG8, CySetRegReplacementString=CY_SET_REG8, EnableMode=1, FF16=false, FF8=false, FixedFunction=false, FixedFunctionUsed=0, InitCounterValue=0, InterruptOnCapture=false, InterruptOnCompare=false, InterruptOnOverUnderFlow=false, InterruptOnTC=false, Period=10, RegDefReplacementString=reg8, RegSizeReplacementString=uint8, ReloadOnCapture=false, ReloadOnCompare=false, ReloadOnOverUnder=true, ReloadOnReset=true, Resolution=8, RstStatusReplacementString=sSTSReg_rstSts, RunMode=0, UDB16=false, UDB24=false, UDB32=false, UDB8=true, UDBControlReg=true, UseInterrupt=true, VerilogSectionReplacementString=sC8, CY_COMPONENT_NAME=Counter_v2_40, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=tenthSec_CNTR, CY_INSTANCE_SHORT_NAME=tenthSec_CNTR, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=40, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.1 SP1, INSTANCE_NAME=tenthSec_CNTR, )
module Counter_v2_40_4 (
clock,
comp,
tc,
reset,
interrupt,
enable,
capture,
upCnt,
downCnt,
up_ndown,
count);
input clock;
output comp;
output tc;
input reset;
output interrupt;
input enable;
input capture;
input upCnt;
input downCnt;
input up_ndown;
input count;
parameter CaptureMode = 0;
parameter ClockMode = 0;
parameter CompareMode = 5;
parameter CompareStatusEdgeSense = 1;
parameter EnableMode = 1;
parameter ReloadOnCapture = 0;
parameter ReloadOnCompare = 0;
parameter ReloadOnOverUnder = 1;
parameter ReloadOnReset = 1;
parameter Resolution = 8;
parameter RunMode = 0;
parameter UseInterrupt = 1;
wire Net_54;
wire Net_102;
wire Net_95;
wire Net_82;
wire Net_91;
wire Net_89;
wire Net_49;
wire Net_48;
wire Net_42;
wire Net_43;
// int_vm (cy_virtualmux_v1_0)
assign interrupt = Net_43;
// TC_vm (cy_virtualmux_v1_0)
assign tc = Net_49;
ZeroTerminal ZeroTerminal_1 (
.z(Net_82));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_89 = up_ndown;
ZeroTerminal ZeroTerminal_2 (
.z(Net_95));
// vmEnableMode (cy_virtualmux_v1_0)
assign Net_91 = Net_102;
OneTerminal OneTerminal_1 (
.o(Net_102));
B_Counter_v2_40 CounterUDB (
.reset(reset),
.tc_out(Net_49),
.cmp_out(comp),
.clock(clock),
.irq_out(Net_43),
.up_ndown(Net_89),
.upcnt(upCnt),
.dwncnt(downCnt),
.enable(enable),
.capture(capture),
.count(count));
defparam CounterUDB.CaptureMode = 0;
defparam CounterUDB.ClockMode = 0;
defparam CounterUDB.CompareMode = 5;
defparam CounterUDB.CompareStatusEdgeSense = 1;
defparam CounterUDB.EnableMode = 1;
defparam CounterUDB.ReloadOnCapture = 0;
defparam CounterUDB.ReloadOnCompare = 0;
defparam CounterUDB.ReloadOnOverUnder = 1;
defparam CounterUDB.ReloadOnReset = 1;
defparam CounterUDB.Resolution = 8;
defparam CounterUDB.RunMode = 0;
defparam CounterUDB.UseInterrupt = 1;
endmodule
// Counter_v2_40(CaptureMode=0, CaptureModeSoftware=0, ClockMode=0, CompareMode=0, CompareModeSoftware=0, CompareStatusEdgeSense=true, CompareValue=255, CONTROL3=0, ControlRegRemoved=1, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG8, CySetRegReplacementString=CY_SET_REG8, EnableMode=1, FF16=false, FF8=false, FixedFunction=false, FixedFunctionUsed=0, InitCounterValue=0, InterruptOnCapture=false, InterruptOnCompare=false, InterruptOnOverUnderFlow=false, InterruptOnTC=false, Period=255, RegDefReplacementString=reg8, RegSizeReplacementString=uint8, ReloadOnCapture=false, ReloadOnCompare=false, ReloadOnOverUnder=true, ReloadOnReset=true, Resolution=8, RstStatusReplacementString=sSTSReg_rstSts, RunMode=0, UDB16=false, UDB24=false, UDB32=false, UDB8=true, UDBControlReg=false, UseInterrupt=true, VerilogSectionReplacementString=sC8, CY_COMPONENT_NAME=Counter_v2_40, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=hr_CNTR, CY_INSTANCE_SHORT_NAME=hr_CNTR, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=40, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.1 SP1, INSTANCE_NAME=hr_CNTR, )
module Counter_v2_40_5 (
clock,
comp,
tc,
reset,
interrupt,
enable,
capture,
upCnt,
downCnt,
up_ndown,
count);
input clock;
output comp;
output tc;
input reset;
output interrupt;
input enable;
input capture;
input upCnt;
input downCnt;
input up_ndown;
input count;
parameter CaptureMode = 0;
parameter ClockMode = 0;
parameter CompareMode = 0;
parameter CompareStatusEdgeSense = 1;
parameter EnableMode = 1;
parameter ReloadOnCapture = 0;
parameter ReloadOnCompare = 0;
parameter ReloadOnOverUnder = 1;
parameter ReloadOnReset = 1;
parameter Resolution = 8;
parameter RunMode = 0;
parameter UseInterrupt = 1;
wire Net_54;
wire Net_102;
wire Net_95;
wire Net_82;
wire Net_91;
wire Net_89;
wire Net_49;
wire Net_48;
wire Net_42;
wire Net_43;
// int_vm (cy_virtualmux_v1_0)
assign interrupt = Net_43;
// TC_vm (cy_virtualmux_v1_0)
assign tc = Net_49;
ZeroTerminal ZeroTerminal_1 (
.z(Net_82));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_89 = up_ndown;
ZeroTerminal ZeroTerminal_2 (
.z(Net_95));
// vmEnableMode (cy_virtualmux_v1_0)
assign Net_91 = Net_102;
OneTerminal OneTerminal_1 (
.o(Net_102));
B_Counter_v2_40 CounterUDB (
.reset(reset),
.tc_out(Net_49),
.cmp_out(comp),
.clock(clock),
.irq_out(Net_43),
.up_ndown(Net_89),
.upcnt(upCnt),
.dwncnt(downCnt),
.enable(enable),
.capture(capture),
.count(count));
defparam CounterUDB.CaptureMode = 0;
defparam CounterUDB.ClockMode = 0;
defparam CounterUDB.CompareMode = 0;
defparam CounterUDB.CompareStatusEdgeSense = 1;
defparam CounterUDB.EnableMode = 1;
defparam CounterUDB.ReloadOnCapture = 0;
defparam CounterUDB.ReloadOnCompare = 0;
defparam CounterUDB.ReloadOnOverUnder = 1;
defparam CounterUDB.ReloadOnReset = 1;
defparam CounterUDB.Resolution = 8;
defparam CounterUDB.RunMode = 0;
defparam CounterUDB.UseInterrupt = 1;
endmodule
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// Component: cy_sync_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_sync_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_sync_v1_0\cy_sync_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_sync_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_sync_v1_0\cy_sync_v1_0.v"
`endif
// top
module top ;
wire Net_981;
wire Net_980;
wire Net_979;
wire Net_978;
wire Net_976;
wire Net_974;
wire Net_973;
wire Net_1063;
wire Net_1061;
wire Net_1060;
wire Net_1059;
wire Net_1058;
wire Net_1057;
wire Net_1056;
wire Net_820;
wire Net_819;
wire Net_818;
wire Net_816;
wire Net_1006;
wire Net_1005;
wire Net_1004;
wire Net_1003;
wire Net_1001;
wire Net_1000;
wire Net_1053;
wire Net_1052;
wire Net_1051;
wire Net_1050;
wire Net_1048;
wire Net_1047;
wire Net_355;
wire Net_476;
wire Net_475;
wire Net_474;
wire Net_846;
wire Net_845;
wire Net_844;
wire Net_1054;
wire Net_862;
wire Net_574;
wire Net_977;
wire Net_566;
wire Net_858;
wire Net_961;
wire Net_863;
wire Net_104;
wire Net_840;
wire Net_838;
wire Net_129;
wire Net_105;
wire Net_122;
CharLCD_v2_10_0 LCD ();
cy_isr_v1_0
#(.int_type(2'b00))
startTimer_ISR
(.int_signal(Net_840));
Debouncer_v1_0 upPositionPin_DBNC (
.d(Net_105),
.clock(Net_129),
.q(Net_838),
.neg(Net_844),
.either(Net_845),
.pos(Net_846));
defparam upPositionPin_DBNC.EitherEdgeDetect = 0;
defparam upPositionPin_DBNC.NegEdgeDetect = 0;
defparam upPositionPin_DBNC.PosEdgeDetect = 1;
defparam upPositionPin_DBNC.SignalWidth = 1;
cy_isr_v1_0
#(.int_type(2'b00))
stopTimer_ISR
(.int_signal(Net_104));
wire [0:0] tmpOE__downPosition_PIN_net;
wire [0:0] tmpIO_0__downPosition_PIN_net;
wire [0:0] tmpINTERRUPT_0__downPosition_PIN_net;
electrical [0:0] tmpSIOVREF__downPosition_PIN_net;
cy_psoc3_pins_v1_10
#(.id("ff71b630-d4fb-4bb5-bd46-fea7933ec6ec"),
.drive_mode(3'b011),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
downPosition_PIN
(.oe(tmpOE__downPosition_PIN_net),
.y({1'b0}),
.fb({Net_122}),
.io({tmpIO_0__downPosition_PIN_net[0:0]}),
.siovref(tmpSIOVREF__downPosition_PIN_net),
.interrupt({tmpINTERRUPT_0__downPosition_PIN_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__downPosition_PIN_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__upPosition_PIN_net;
wire [0:0] tmpIO_0__upPosition_PIN_net;
wire [0:0] tmpINTERRUPT_0__upPosition_PIN_net;
electrical [0:0] tmpSIOVREF__upPosition_PIN_net;
cy_psoc3_pins_v1_10
#(.id("8d318d8b-cf7b-4b6b-b02c-ab1c5c49d0ba"),
.drive_mode(3'b011),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
upPosition_PIN
(.oe(tmpOE__upPosition_PIN_net),
.y({1'b0}),
.fb({Net_105}),
.io({tmpIO_0__upPosition_PIN_net[0:0]}),
.siovref(tmpSIOVREF__upPosition_PIN_net),
.interrupt({tmpINTERRUPT_0__upPosition_PIN_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__upPosition_PIN_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
Debouncer_v1_0 downPositionPin_DBNC (
.d(Net_122),
.clock(Net_129),
.q(Net_104),
.neg(Net_474),
.either(Net_475),
.pos(Net_476));
defparam downPositionPin_DBNC.EitherEdgeDetect = 0;
defparam downPositionPin_DBNC.NegEdgeDetect = 0;
defparam downPositionPin_DBNC.PosEdgeDetect = 1;
defparam downPositionPin_DBNC.SignalWidth = 1;
cy_clock_v1_0
#(.id("433a9115-2609-4ad7-bf43-81b377bd4494"),
.source_clock_id(""),
.divisor(0),
.period("20000000000000"),
.is_direct(0),
.is_digital(1))
dbnc_CLK
(.clock_out(Net_129));
Counter_v2_40_1 sec_CNTR (
.reset(Net_838),
.tc(Net_574),
.comp(Net_1047),
.clock(Net_961),
.interrupt(Net_1048),
.enable(Net_977),
.capture(1'b0),
.upCnt(1'b0),
.downCnt(1'b0),
.up_ndown(1'b1),
.count(Net_1054));
defparam sec_CNTR.CaptureMode = 0;
defparam sec_CNTR.ClockMode = 0;
defparam sec_CNTR.CompareMode = 0;
defparam sec_CNTR.CompareStatusEdgeSense = 1;
defparam sec_CNTR.EnableMode = 1;
defparam sec_CNTR.ReloadOnCapture = 0;
defparam sec_CNTR.ReloadOnCompare = 0;
defparam sec_CNTR.ReloadOnOverUnder = 1;
defparam sec_CNTR.ReloadOnReset = 1;
defparam sec_CNTR.Resolution = 8;
defparam sec_CNTR.RunMode = 0;
defparam sec_CNTR.UseInterrupt = 1;
assign Net_840 = ~Net_838;
cy_isr_v1_0
#(.int_type(2'b00))
readyTimer_ISR
(.int_signal(Net_838));
Counter_v2_40_2 min_CNTR (
.reset(Net_838),
.tc(Net_566),
.comp(Net_1000),
.clock(Net_961),
.interrupt(Net_1001),
.enable(Net_977),
.capture(1'b0),
.upCnt(1'b0),
.downCnt(1'b0),
.up_ndown(1'b1),
.count(Net_574));
defparam min_CNTR.CaptureMode = 0;
defparam min_CNTR.ClockMode = 0;
defparam min_CNTR.CompareMode = 0;
defparam min_CNTR.CompareStatusEdgeSense = 1;
defparam min_CNTR.EnableMode = 1;
defparam min_CNTR.ReloadOnCapture = 0;
defparam min_CNTR.ReloadOnCompare = 0;
defparam min_CNTR.ReloadOnOverUnder = 1;
defparam min_CNTR.ReloadOnReset = 1;
defparam min_CNTR.Resolution = 8;
defparam min_CNTR.RunMode = 0;
defparam min_CNTR.UseInterrupt = 1;
Timer_v2_70_3 Timer (
.reset(Net_838),
.interrupt(Net_816),
.enable(Net_863),
.trigger(1'b1),
.capture(1'b0),
.capture_out(Net_820),
.tc(Net_858),
.clock(Net_961));
defparam Timer.CaptureCount = 2;
defparam Timer.CaptureCounterEnabled = 0;
defparam Timer.DeviceFamily = "PSoC3";
defparam Timer.InterruptOnCapture = 0;
defparam Timer.InterruptOnTC = 0;
defparam Timer.Resolution = 8;
defparam Timer.SiliconRevision = "3";
Counter_v2_40_4 tenthSec_CNTR (
.reset(Net_838),
.tc(Net_1054),
.comp(Net_1056),
.clock(Net_961),
.interrupt(Net_1057),
.enable(Net_977),
.capture(1'b0),
.upCnt(1'b0),
.downCnt(1'b0),
.up_ndown(1'b1),
.count(Net_862));
defparam tenthSec_CNTR.CaptureMode = 0;
defparam tenthSec_CNTR.ClockMode = 0;
defparam tenthSec_CNTR.CompareMode = 5;
defparam tenthSec_CNTR.CompareStatusEdgeSense = 1;
defparam tenthSec_CNTR.EnableMode = 1;
defparam tenthSec_CNTR.ReloadOnCapture = 0;
defparam tenthSec_CNTR.ReloadOnCompare = 0;
defparam tenthSec_CNTR.ReloadOnOverUnder = 1;
defparam tenthSec_CNTR.ReloadOnReset = 1;
defparam tenthSec_CNTR.Resolution = 8;
defparam tenthSec_CNTR.RunMode = 0;
defparam tenthSec_CNTR.UseInterrupt = 1;
cy_clock_v1_0
#(.id("dec4c689-42b4-4657-b0cd-a62772aa3b3f"),
.source_clock_id(""),
.divisor(0),
.period("1000000000000"),
.is_direct(0),
.is_digital(1))
timer_CLK
(.clock_out(Net_961));
Counter_v2_40_5 hr_CNTR (
.reset(Net_838),
.tc(Net_973),
.comp(Net_974),
.clock(Net_961),
.interrupt(Net_976),
.enable(Net_977),
.capture(1'b0),
.upCnt(1'b0),
.downCnt(1'b0),
.up_ndown(1'b1),
.count(Net_566));
defparam hr_CNTR.CaptureMode = 0;
defparam hr_CNTR.ClockMode = 0;
defparam hr_CNTR.CompareMode = 0;
defparam hr_CNTR.CompareStatusEdgeSense = 1;
defparam hr_CNTR.EnableMode = 1;
defparam hr_CNTR.ReloadOnCapture = 0;
defparam hr_CNTR.ReloadOnCompare = 0;
defparam hr_CNTR.ReloadOnOverUnder = 1;
defparam hr_CNTR.ReloadOnReset = 1;
defparam hr_CNTR.Resolution = 8;
defparam hr_CNTR.RunMode = 0;
defparam hr_CNTR.UseInterrupt = 1;
assign Net_977 = 1'h1;
assign Net_863 = 1'h1;
cy_sync_v1_0 SYNC (
.s_in(Net_858),
.clock(Net_961),
.s_out(Net_862));
defparam SYNC.SignalWidth = 1;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9434_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio);
// 4 wire
input [ 1:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3B_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR3B_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor3b (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3B_BLACKBOX_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: mc_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mc_pll (
inclk0,
c0);
input inclk0;
output c0;
wire [6:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 40000,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=mc_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 7;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "mc_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mc_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mc_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mc_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mc_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mc_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mc_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mc_pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SoC_nios2_qsys_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
// Copyright (c) 2014, Segiusz 'q3k' Bazanski <[email protected]>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
module qm_fetch(
/// datapath
// input PC to assume
input wire [31:0] di_PC,
// output instruction register
output reg [31:0] do_IR,
// output to next PC
output reg [31:0] do_NextPC,
// icache connectivity
output wire [31:0] icache_address,
input wire icache_hit,
input wire icache_should_stall,
input wire [31:0] icache_data
);
assign icache_address = di_PC;
always @(*) begin
if (icache_should_stall && !icache_hit) begin
do_NextPC = di_PC;
do_IR = 0;
end else begin
do_NextPC = di_PC + 4;
do_IR = icache_data;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31AI_4_V
`define SKY130_FD_SC_LP__O31AI_4_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31ai_4 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31AI_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:45:39 10/10/2014
// Design Name:
// Module Name: analog_input
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module analog_input(
input clk,
input rst,
output [3:0] channel,
input new_sample,
input [9:0] sample,
input [3:0] sample_channel,
output [9:0] out
);
assign channel = 4'd0; // only read A0
reg [9:0] sample_d, sample_q;
assign out = sample_q;
//assign out = {8{pwm}}; // duplicate the PWM signal to each LED
always @(*) begin
sample_d = sample_q;
if (new_sample && sample_channel == 4'd0) // valid sample
sample_d = sample;
end
always @(posedge clk) begin
if (rst) begin
sample_q <= 10'd0;
end else begin
sample_q <= sample_d;
end
end
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/01/2009
This block is responsible for communicating with the host processor/
descriptor prefetching master block. It uses FIFOs to buffer descriptors
to keep the read and write masters operating without intervention from a
host processor. This block is comprised of three main blocks:
1) Descriptor buffer
2) CSR
3) Response
The descriptor buffer recieves descriptors from a host/prefetcher and
registers the incoming byte lanes. When the descriptor 'go' bit has been
written, the descriptor is committed to the read/write descriptor buffers.
From there the descriptors are exposed to the read and write masters without
intervention from the host. The descriptor port is either 128 or 256 bits
wide depending on whether or not the enhanced features setting has been enabled.
Since the port is write only minimial logic will be created in the fabric
to adapt the byte enables for narrow masters connecting to this port. This
port contains a single address so address bits are exposed to the fabric.
The CSR (control-status register) block is used to provide information
back to the host as well as allow the SGDMA to be controlled on a
non-descriptor basis. The host driver should be written to mostly interact
with this port as interrupts and status information is accessible from this
block.
The optional response block is used to feed information on a per descriptor
basis back to the host or prefetching descriptor master. In most cases the
port will be used for sharing infomation about ST->MM transfers.
Communication between this block and the masters is performed using pairs
of Avalon-ST port connections. When the SGDMA is setup for MM->ST then the
write master port connections are removed and visa vera for ST->MM and the
read master. For more detailed information refer to "SGDMA_dispatcher_ug.pdf"
for more details.
Author: JCJB
Date: 08/13/2010
1.0 - Initial release
1.1 - Changed the stopped and resetting logic to correctly reflect the state
of the hardware (this block and the masters).
1.2 - Added stop descriptors logic
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module dispatcher (
clk,
reset,
// 128/256 bit write only port for feeding the dispatcher descriptors, no address since it's only one word wide, blocking when too many descriptors are buffered
descriptor_writedata,
descriptor_byteenable,
descriptor_write,
descriptor_waitrequest,
// control and status port, 32 bits wide with a read latency of 2 and non-blocking
csr_writedata,
csr_byteenable,
csr_write,
csr_readdata,
csr_read,
csr_address, // 4 addresses when ENHANCED_FEATURES is off (zero) otherwise 8 addresses are available
csr_irq, // only available if the response port is not an ST source (in that case the SGDMA pre-fetching block will issue interrupts)
// response slave port (when "RESPONSE_PORT" is set to 0), 32 bits wide, read only, and a read latency of 3 cycles
mm_response_readdata,
mm_response_read,
mm_response_address, // only two addresses
mm_response_byteenable, // last byte read pops the response FIFO
mm_response_waitrequest,
// response source port (when "RESPONSE_PORT" is set to 1),
src_response_data,
src_response_valid,
src_response_ready,
// write master source port (sends commands to write master)
src_write_master_data,
src_write_master_valid,
src_write_master_ready,
// write master sink port (recieves response from write master)
snk_write_master_data,
snk_write_master_valid,
snk_write_master_ready,
// read master source port (sends commands to read master)
src_read_master_data,
src_read_master_valid,
src_read_master_ready,
// read master sink port (recieves response from the read master)
snk_read_master_data,
snk_read_master_valid,
snk_read_master_ready
);
// y = log2(x)
function integer log2;
input integer x;
begin
x = x-1;
for(log2=0; x>0; log2=log2+1)
x = x>>1;
end
endfunction
parameter MODE = 0; // 0 for MM->MM, 1 for MM->ST, 2 for ST->MM
parameter RESPONSE_PORT = 0; // 0 for MM, 1 for ST, 2 for Disabled // normally disabled for all but ST->MM transfers
parameter DESCRIPTOR_FIFO_DEPTH = 128; // 16-1024 in powers of 2
parameter ENHANCED_FEATURES = 1; // 1 for Enabled, 0 for Disabled
parameter DESCRIPTOR_WIDTH = 256; // 256 when enhanced mode is on, 128 for off (needs to be controlled by callback since it influences data width)
parameter DESCRIPTOR_BYTEENABLE_WIDTH = 32; // 32 when enhanced mode is on, 16 for off (needs to be controlled by callback since it influences byte enable width)
parameter CSR_ADDRESS_WIDTH = 3; // always 3 bits wide
localparam RESPONSE_FIFO_DEPTH = 2 * DESCRIPTOR_FIFO_DEPTH;
localparam DESCRIPTOR_FIFO_DEPTH_LOG2 = log2(DESCRIPTOR_FIFO_DEPTH);
localparam RESPONSE_FIFO_DEPTH_LOG2 = log2(RESPONSE_FIFO_DEPTH);
input clk;
input reset;
input [DESCRIPTOR_WIDTH-1:0] descriptor_writedata;
input [DESCRIPTOR_BYTEENABLE_WIDTH-1:0] descriptor_byteenable;
input descriptor_write;
output wire descriptor_waitrequest;
input [31:0] csr_writedata;
input [3:0] csr_byteenable;
input csr_write;
output wire [31:0] csr_readdata;
input csr_read;
input [CSR_ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
// Used by a host with a master (like Nios II)
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address;
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
// Used by a pre-fetching master
output wire [255:0] src_response_data; // making wide in case we need to jam more signals in here, unnecessary bits will be grounded/optimized away
output wire src_response_valid;
input src_response_ready;
output wire [255:0] src_write_master_data; // don't know how many bits the master will use, unnecessary bits will be grounded/optimized away
output wire src_write_master_valid;
input src_write_master_ready;
input [255:0] snk_write_master_data; // might need to jam more bits in......
input snk_write_master_valid;
output wire snk_write_master_ready;
output wire [255:0] src_read_master_data; // don't know how many bits the master will use, unnecessary bits will be grounded/optimized away
output wire src_read_master_valid;
input src_read_master_ready;
input [255:0] snk_read_master_data; // might need to jam more bits in......
input snk_read_master_valid;
output wire snk_read_master_ready;
/* Internal wires and registers */
// descriptor information
wire read_command_valid;
wire read_command_ready;
wire [255:0] read_command_data;
wire read_command_empty;
wire read_command_full;
wire [DESCRIPTOR_FIFO_DEPTH_LOG2:0] read_command_used; // true used signal so extra MSB is included
wire write_command_valid;
wire write_command_ready;
wire [255:0] write_command_data;
wire write_command_empty;
wire write_command_full;
wire [DESCRIPTOR_FIFO_DEPTH_LOG2:0] write_command_used; // true used signal so extra MSB is included
wire [31:0] sequence_number;
wire transfer_complete_IRQ_mask;
wire early_termination_IRQ_mask;
wire [7:0] error_IRQ_mask;
wire descriptor_buffer_empty;
wire descriptor_buffer_full;
wire [15:0] write_descriptor_watermark;
wire [15:0] read_descriptor_watermark;
wire [31:0] descriptor_watermark;
wire busy;
wire done;
wire done_strobe;
wire stop_issuing_commands;
wire stop;
wire sw_reset;
wire stop_on_error;
wire stop_on_early_termination;
wire stop_descriptors;
wire reset_stalled;
wire master_stop_state;
wire descriptors_stop_state;
wire stop_state;
wire stopped_on_error;
wire stopped_on_early_termination;
wire response_fifo_full;
wire response_fifo_empty;
wire [15:0] response_watermark;
wire [7:0] response_error;
wire response_early_termination;
wire [31:0] response_actual_bytes_transferred;
/************************************************ REGISTERS *******************************************************/
/********************************************** END REGISTERS *****************************************************/
/******************************************* MODULE DECLERATIONS **************************************************/
// the descriptor buffers block instantiates the descriptor FIFOs and handshaking logic with the master command ports
descriptor_buffers the_descriptor_buffers (
.clk (clk),
.reset (reset),
.writedata (descriptor_writedata),
.write (descriptor_write),
.byteenable (descriptor_byteenable),
.waitrequest (descriptor_waitrequest),
.read_command_valid (read_command_valid),
.read_command_ready (read_command_ready),
.read_command_data (read_command_data),
.read_command_empty (read_command_empty),
.read_command_full (read_command_full),
.read_command_used (read_command_used),
.write_command_valid (write_command_valid),
.write_command_ready (write_command_ready),
.write_command_data (write_command_data),
.write_command_empty (write_command_empty),
.write_command_full (write_command_full),
.write_command_used (write_command_used),
.stop_issuing_commands (stop_issuing_commands),
.stop (stop),
.sw_reset (sw_reset),
.sequence_number (sequence_number),
.transfer_complete_IRQ_mask (transfer_complete_IRQ_mask),
.early_termination_IRQ_mask (early_termination_IRQ_mask),
.error_IRQ_mask (error_IRQ_mask)
);
defparam the_descriptor_buffers.MODE = MODE;
defparam the_descriptor_buffers.DATA_WIDTH = DESCRIPTOR_WIDTH;
defparam the_descriptor_buffers.BYTE_ENABLE_WIDTH = DESCRIPTOR_WIDTH/8;
defparam the_descriptor_buffers.FIFO_DEPTH = DESCRIPTOR_FIFO_DEPTH;
defparam the_descriptor_buffers.FIFO_DEPTH_LOG2 = DESCRIPTOR_FIFO_DEPTH_LOG2;
// Control and status registers (and interrupts when a host connects directly to this block)
csr_block the_csr_block (
.clk (clk),
.reset (reset),
.csr_writedata (csr_writedata),
.csr_write (csr_write),
.csr_byteenable (csr_byteenable),
.csr_readdata (csr_readdata),
.csr_read (csr_read),
.csr_address (csr_address),
.csr_irq (csr_irq),
.done_strobe (done_strobe),
.busy (busy),
.descriptor_buffer_empty (descriptor_buffer_empty),
.descriptor_buffer_full (descriptor_buffer_full),
.stop_state (stop_state),
.stopped_on_error (stopped_on_error),
.stopped_on_early_termination (stopped_on_early_termination),
.stop_descriptors (stop_descriptors),
.reset_stalled (reset_stalled), // from the master(s) to tell the CSR block that it's still resetting
.stop (stop),
.sw_reset (sw_reset),
.stop_on_error (stop_on_error),
.stop_on_early_termination (stop_on_early_termination),
.sequence_number (sequence_number),
.descriptor_watermark (descriptor_watermark),
.response_watermark (response_watermark),
.response_buffer_empty (response_fifo_empty),
.response_buffer_full (response_fifo_full),
.transfer_complete_IRQ_mask (transfer_complete_IRQ_mask),
.error_IRQ_mask (error_IRQ_mask),
.early_termination_IRQ_mask (early_termination_IRQ_mask),
.error (response_error),
.early_termination (response_early_termination)
);
defparam the_csr_block.ADDRESS_WIDTH = CSR_ADDRESS_WIDTH;
// Optional response port. When using a directly connected host it'll be a slave port and using a pre-fetching descriptor master it will be a streaming source port.
response_block the_response_block (
.clk (clk),
.reset (reset),
.mm_response_readdata (mm_response_readdata),
.mm_response_read (mm_response_read),
.mm_response_address (mm_response_address),
.mm_response_byteenable (mm_response_byteenable),
.mm_response_waitrequest (mm_response_waitrequest),
.src_response_data (src_response_data),
.src_response_valid (src_response_valid),
.src_response_ready (src_response_ready),
.sw_reset (sw_reset),
.response_watermark (response_watermark),
.response_fifo_full (response_fifo_full),
.response_fifo_empty (response_fifo_empty),
.done_strobe (done_strobe),
.actual_bytes_transferred (response_actual_bytes_transferred),
.error (response_error),
.early_termination (response_early_termination),
.transfer_complete_IRQ_mask (transfer_complete_IRQ_mask),
.error_IRQ_mask (error_IRQ_mask),
.early_termination_IRQ_mask (early_termination_IRQ_mask),
.descriptor_buffer_full (descriptor_buffer_full)
);
defparam the_response_block.RESPONSE_PORT = RESPONSE_PORT;
defparam the_response_block.FIFO_DEPTH = RESPONSE_FIFO_DEPTH;
defparam the_response_block.FIFO_DEPTH_LOG2 = RESPONSE_FIFO_DEPTH_LOG2;
/***************************************** END MODULE DECLERATIONS ************************************************/
/****************************************** COMBINATIONAL SIGNALS *************************************************/
// this block issues the commands so it's always ready for a response. The response FIFO fill level will be used to
// make sure additional ST-->MM commands are not issued if there is no room to catch the response.
assign snk_write_master_ready = 1'b1;
assign snk_read_master_ready = 1'b1;
assign done = (MODE == 1)? snk_read_master_ready : snk_write_master_ready;
assign done_strobe = (MODE == 1)? (snk_read_master_ready & snk_read_master_valid) : (snk_write_master_ready & snk_write_master_valid);
assign stop_issuing_commands = (response_fifo_full == 1) | (stop_descriptors == 1);
assign src_write_master_valid = write_command_valid;
assign write_command_ready = src_write_master_ready;
assign src_write_master_data = write_command_data;
assign src_read_master_valid = read_command_valid;
assign read_command_ready = src_read_master_ready;
assign src_read_master_data = read_command_data;
assign busy = (read_command_empty == 0) | (write_command_empty == 0) | // still have descriptors buffered in the FIFOs
(done == 0); // current transfer is still occuring
assign descriptor_buffer_empty = (read_command_empty == 1) & (write_command_empty == 1);
assign descriptor_buffer_full = (read_command_full == 1) | (write_command_full == 1);
assign write_descriptor_watermark = 16'h0000 | write_command_used; // zero padding the upper unused bits
assign read_descriptor_watermark = 16'h0000 | read_command_used; // zero padding the upper unused bits
assign descriptor_watermark = {write_descriptor_watermark, read_descriptor_watermark};
assign reset_stalled = snk_read_master_data[0] | snk_write_master_data[32];
assign master_stop_state = ((MODE == 0)? (snk_read_master_data[1] & snk_write_master_data[33]) :
(MODE == 1)? snk_read_master_data[1] : snk_write_master_data[33]);
assign descriptors_stop_state = (stop_descriptors == 1) & ((MODE == 0)? ((src_read_master_ready == 1) & (src_write_master_ready == 1)) :
(MODE == 1)? (src_read_master_ready == 1) : (src_write_master_ready == 1));
assign stop_state = (master_stop_state == 1) | (descriptors_stop_state == 1);
assign response_actual_bytes_transferred = snk_write_master_data[31:0];
assign response_error = snk_write_master_data[41:34];
assign response_early_termination = snk_write_master_data[42];
/**************************************** END COMBINATIONAL SIGNALS ***********************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_SYMBOL_V
`define SKY130_FD_SC_LP__O221AI_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o221ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_BEHAVIORAL_V
`define SKY130_FD_SC_HS__BUFBUF_BEHAVIORAL_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__bufbuf (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXBP_BEHAVIORAL_V |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file BRAM.v when simulating
// the core, BRAM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module BRAM(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
input clka;
input [0 : 0] wea;
input [6 : 0] addra;
input [31 : 0] dina;
input clkb;
input [6 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(7),
.C_ADDRB_WIDTH(7),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex5"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(128),
.C_READ_DEPTH_B(128),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(128),
.C_WRITE_DEPTH_B(128),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("virtex5"))
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
endmodule
|
`include "defines.v"
module pc(
input wire clk,
input wire rst,
//Branch
input wire branchEnable_i,
input wire[31:0] branchAddr_i,
//Control
input wire bubble_i,
input wire pauseControl_i,
input wire flush_i,
input wire[31:0] excAddr_i,
//Addr
output reg[31:0] insAddr_o
);
wire[31:0] nextInsAddr = insAddr_o + 32'h4;
wire[31:0] insAddr = insAddr_o;
always @(posedge clk) begin
if (rst == `Enable) begin
//insAddr_o <= 32'hbfc00000 - 4;
insAddr_o <= 32'h80000000 - 4;
end else if (pauseControl_i == `PAUSE_CONTROLED) begin
insAddr_o <= insAddr;
end else if (flush_i == `Enable) begin
insAddr_o <= excAddr_i;
end else if (bubble_i == `Enable) begin
insAddr_o <= insAddr;
end else if (branchEnable_i == `Enable) begin
insAddr_o <= branchAddr_i;
end else begin
insAddr_o <= nextInsAddr;
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
module registers
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_NUM_CHNL = 12,
parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
parameter C_VENDOR = "ALTERA",
parameter C_NUM_VECTORS = 2,
parameter C_VECTOR_WIDTH = 32,
parameter C_FPGA_NAME = "FPGA",
parameter C_PIPELINE_OUTPUT= 1,
parameter C_PIPELINE_INPUT= 1)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: RXR Engine
input [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
input RXR_DATA_VALID,
input RXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
input [`SIG_FBE_W-1:0] RXR_META_FDWBE,
input RXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
input [`SIG_LBE_W-1:0] RXR_META_LDWBE,
input [`SIG_TC_W-1:0] RXR_META_TC,
input [`SIG_ATTR_W-1:0] RXR_META_ATTR,
input [`SIG_TAG_W-1:0] RXR_META_TAG,
input [`SIG_TYPE_W-1:0] RXR_META_TYPE,
input [`SIG_ADDR_W-1:0] RXR_META_ADDR,
input [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
input [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
input [`SIG_LEN_W-1:0] RXR_META_LENGTH,
// Interface: TXC Engine
output TXC_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
output TXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
output TXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
input TXC_DATA_READY,
output TXC_META_VALID,
output [`SIG_FBE_W-1:0] TXC_META_FDWBE,
output [`SIG_LBE_W-1:0] TXC_META_LDWBE,
output [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
output [`SIG_TYPE_W-1:0] TXC_META_TYPE,
output [`SIG_LEN_W-1:0] TXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
output [`SIG_TAG_W-1:0] TXC_META_TAG,
output [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
output [`SIG_TC_W-1:0] TXC_META_TC,
output [`SIG_ATTR_W-1:0] TXC_META_ATTR,
output TXC_META_EP,
input TXC_META_READY,
// Interface: Channel - WR
output [31:0] CHNL_REQ_DATA,
output [C_NUM_CHNL-1:0] CHNL_SGRX_LEN_VALID,
output [C_NUM_CHNL-1:0] CHNL_SGRX_ADDRLO_VALID,
output [C_NUM_CHNL-1:0] CHNL_SGRX_ADDRHI_VALID,
output [C_NUM_CHNL-1:0] CHNL_SGTX_LEN_VALID,
output [C_NUM_CHNL-1:0] CHNL_SGTX_ADDRLO_VALID,
output [C_NUM_CHNL-1:0] CHNL_SGTX_ADDRHI_VALID,
output [C_NUM_CHNL-1:0] CHNL_RX_LEN_VALID,
output [C_NUM_CHNL-1:0] CHNL_RX_OFFLAST_VALID,
// Interface: Channel - RD
input [(`SIG_TXRLEN_W*C_NUM_CHNL)-1:0] CHNL_TX_REQLEN,
input [(`SIG_OFFLAST_W*C_NUM_CHNL)-1:0] CHNL_TX_OFFLAST,
input [(`SIG_TXDONELEN_W*C_NUM_CHNL)-1:0] CHNL_TX_DONELEN,
input [(`SIG_RXDONELEN_W*C_NUM_CHNL)-1:0] CHNL_RX_DONELEN,
input [`SIG_CORESETTINGS_W-1:0] CORE_SETTINGS,
output [C_NUM_CHNL-1:0] CHNL_TX_LEN_READY,
output [C_NUM_CHNL-1:0] CHNL_TX_OFFLAST_READY,
output CORE_SETTINGS_READY,
output [C_NUM_VECTORS-1:0] INTR_VECTOR_READY,
output [C_NUM_CHNL-1:0] CHNL_TX_DONE_READY,
output [C_NUM_CHNL-1:0] CHNL_RX_DONE_READY,
output CHNL_NAME_READY,
// Interface: Interrupt Vectors
input [C_NUM_VECTORS*C_VECTOR_WIDTH-1:0] INTR_VECTOR
);
`include "functions.vh"
localparam C_ADDR_RANGE = 256;
localparam C_ARRAY_LENGTH = (32*C_ADDR_RANGE)/C_PCI_DATA_WIDTH;
localparam C_NAME_WIDTH = 32;
localparam C_FIELDS_WIDTH = 4;
localparam C_OUTPUT_STAGES = C_PIPELINE_OUTPUT > 0 ? 1:0;
localparam C_INPUT_STAGES = C_PIPELINE_INPUT > 0 ? 1:0;
localparam C_TXC_REGISTER_WIDTH = C_PCI_DATA_WIDTH + 2*(1 + clog2(C_PCI_DATA_WIDTH/32) + `SIG_FBE_W) + `SIG_LOWADDR_W + `SIG_TYPE_W + `SIG_LEN_W + `SIG_BYTECNT_W + `SIG_TAG_W + `SIG_REQID_W + `SIG_TC_W + `SIG_ATTR_W + 1;
localparam C_RXR_REGISTER_WIDTH = C_PCI_DATA_WIDTH + 2*(1 + clog2(C_PCI_DATA_WIDTH/32) + `SIG_FBE_W) + `SIG_ADDR_W + `SIG_TYPE_W + `SIG_LEN_W + `SIG_TAG_W + `SIG_REQID_W + `SIG_TC_W + `SIG_ATTR_W;
// The Mem/IO read/write address space should be at least 8 bits wide. This
// means we'll need at least 10 bits of BAR 0, at least 1024 bytes. The bottom
// two bits must always be zero (i.e. all addresses are 4 byte word aligned).
// The Mem/IO read/write address space is partitioned as illustrated below.
// {CHANNEL_NUM} {DATA_OFFSETS} {ZERO}
// ------4-------------4-----------2--
// The lower 2 bits are always zero. The middle 4 bits are used according to
// the listing below. The top 4 bits differentiate between channels for values
// defined in the table below.
// 0000 = Length of SG buffer for RX transaction (Write only)
// 0001 = PC low address of SG buffer for RX transaction (Write only)
// 0010 = PC high address of SG buffer for RX transaction (Write only)
// 0011 = Transfer length for RX transaction (Write only)
// 0100 = Offset/Last for RX transaction (Write only)
// 0101 = Length of SG buffer for TX transaction (Write only)
// 0110 = PC low address of SG buffer for TX transaction (Write only)
// 0111 = PC high address of SG buffer for TX transaction (Write only)
// 1000 = Transfer length for TX transaction (Read only) (ACK'd on read)
// 1001 = Offset/Last for TX transaction (Read only)
// 1010 = Link rate, link width, bus master enabled, number of channels (Read only)
// 1011 = Interrupt vector 1 (Read only) (Reset on read)
// 1100 = Interrupt vector 2 (Read only) (Reset on read)
// 1101 = Transferred length for RX transaction (Read only) (ACK'd on read)
// 1110 = Transferred length for TX transaction (Read only) (ACK'd on read)
// 1111 = Name of FPGA (Read only)
wire [31:0] __wRdMemory[C_ADDR_RANGE-1:0];
wire [32*C_ADDR_RANGE-1:0] _wRdMemory;
wire [C_PCI_DATA_WIDTH-1:0] wRdMemory[C_ARRAY_LENGTH-1:0];
wire [C_PCI_DATA_WIDTH-1:0] wRxrData;
wire wRxrDataValid;
wire wRxrDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataStartOffset;
wire [`SIG_FBE_W-1:0] wRxrMetaFdwbe;
wire wRxrDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataEndOffset;
wire [`SIG_LBE_W-1:0] wRxrMetaLdwbe;
wire [`SIG_TC_W-1:0] wRxrMetaTc;
wire [`SIG_ATTR_W-1:0] wRxrMetaAttr;
wire [`SIG_TAG_W-1:0] wRxrMetaTag;
wire [`SIG_TYPE_W-1:0] wRxrMetaType;
wire [`SIG_ADDR_W-1:0] wRxrMetaAddr;
wire [`SIG_REQID_W-1:0] wRxrMetaRequesterId;
wire [`SIG_LEN_W-1:0] wRxrMetaLength;
wire [C_PCI_DATA_WIDTH-1:0] wTxcData;
wire wTxcDataValid;
wire wTxcDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcDataStartOffset;
wire [`SIG_FBE_W-1:0] wTxcMetaFdwbe;
wire wTxcDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcDataEndOffset;
wire [`SIG_LBE_W-1:0] wTxcMetaLdwbe;
wire [`SIG_LOWADDR_W-1:0] wTxcMetaAddr;
wire [`SIG_TYPE_W-1:0] wTxcMetaType;
wire [`SIG_LEN_W-1:0] wTxcMetaLength;
wire [`SIG_BYTECNT_W-1:0] wTxcMetaByteCount;
wire [`SIG_TAG_W-1:0] wTxcMetaTag;
wire [`SIG_REQID_W-1:0] wTxcMetaRequesterId;
wire [`SIG_TC_W-1:0] wTxcMetaTc;
wire [`SIG_ATTR_W-1:0] wTxcMetaAttr;
wire wTxcMetaEp;
wire wTxcDataReady;
wire [clog2s(C_NUM_CHNL)-1:0] wReqChnl;
wire [C_FIELDS_WIDTH-1:0] wReqField;
wire [(1<<C_FIELDS_WIDTH)-1:0] wReqFieldDemux;
wire [C_NUM_CHNL-1:0] wChnlSgrxLenValid;
wire [C_NUM_CHNL-1:0] wChnlSgrxAddrLowValid;
wire [C_NUM_CHNL-1:0] wChnlSgrxAddrHiValid;
wire [C_NUM_CHNL-1:0] wChnlSgtxLenValid;
wire [C_NUM_CHNL-1:0] wChnlSgtxAddrLowValid;
wire [C_NUM_CHNL-1:0] wChnlSgtxAddrHiValid;
wire [C_NUM_CHNL-1:0] wChnlRxLenValid;
wire [C_NUM_CHNL-1:0] wChnlRxOfflastValid;
wire [C_NUM_CHNL-1:0] wChnlTxLenReady;
wire [C_NUM_CHNL-1:0] wChnlTxOfflastReady;
wire [`SIG_CORESETTINGS_W-1:0] wCoreSettings;
wire wCoreSettingsReady;
wire [C_NUM_VECTORS - 1 : 0] wInterVectorReady;
wire [C_NUM_CHNL-1:0] wChnlTxDoneReady;
wire [C_NUM_CHNL-1:0] wChnlRxDoneReady;
wire wChnlNameReady;
wire [31:0] wChnlReqData;
genvar addr;
genvar channel;
genvar vector;
assign wReqChnl = wRxrMetaAddr[(C_FIELDS_WIDTH + 2) +:clog2s(C_NUM_CHNL)];
assign wReqField = wRxrMetaAddr[2 +: C_FIELDS_WIDTH];
assign wChnlReqData[31:0] = wRxrData[32*wRxrDataStartOffset +: 32];
/* verilator lint_off WIDTH */
assign __wRdMemory[`ADDR_CORESETTINGS] = CORE_SETTINGS;
assign __wRdMemory[`ADDR_INTR_VECTOR_0] = INTR_VECTOR[C_VECTOR_WIDTH*0 +: C_VECTOR_WIDTH];
assign __wRdMemory[`ADDR_INTR_VECTOR_1] = INTR_VECTOR[C_VECTOR_WIDTH*1 +: C_VECTOR_WIDTH];
assign __wRdMemory[`ADDR_FPGA_NAME] = {" ",C_FPGA_NAME};
/* verilator lint_on WIDTH */
assign wTxcData = {{(C_PCI_DATA_WIDTH-32){1'b0}},__wRdMemory[{wReqChnl,wReqField}]};
assign wTxcDataValid = wRxrDataValid & wRxrMetaType == `TRLS_REQ_RD;
assign wTxcDataStartFlag = 1;
assign wTxcDataStartOffset = 0;
assign wTxcMetaFdwbe = 4'b1111;
assign wTxcDataEndFlag = 1;
assign wTxcDataEndOffset = 0;
assign wTxcMetaLdwbe = 4'b0000;
assign wTxcMetaAddr = wRxrMetaAddr[`SIG_LOWADDR_W-1:0];
assign wTxcMetaType = `TRLS_CPL_WD;
assign wTxcMetaLength = 1;
assign wTxcMetaByteCount = 4;
assign wTxcMetaTag = wRxrMetaTag;
assign wTxcMetaRequesterId = wRxrMetaRequesterId;
assign wTxcMetaTc = wRxrMetaTc;
assign wTxcMetaAttr = wRxrMetaAttr;
assign wTxcMetaEp = 0;
generate
for(channel = 0; channel < C_NUM_CHNL ; channel = channel + 1) begin : gen__wRdMemory
assign __wRdMemory[{channel[27:0] , `ADDR_TX_LEN}] = CHNL_TX_REQLEN[32*channel +: 32];
assign __wRdMemory[{channel[27:0] , `ADDR_TX_OFFLAST}] = CHNL_TX_OFFLAST[32*channel +: 32];
assign __wRdMemory[{channel[27:0] , `ADDR_RX_LEN_XFERD}] = CHNL_RX_DONELEN[32*channel +: 32];
assign __wRdMemory[{channel[27:0] , `ADDR_TX_LEN_XFERD}] = CHNL_TX_DONELEN[32*channel +: 32];
end
for(addr = 0 ; addr < C_ADDR_RANGE ; addr = addr + 1) begin : gen_wRdMemory
assign _wRdMemory[(addr*32) +: 32] = __wRdMemory[addr];
end
for(addr = 0 ; addr < C_ARRAY_LENGTH ; addr = addr + 1) begin : genwRdMemory
assign wRdMemory[addr] = _wRdMemory[(addr*C_PCI_DATA_WIDTH) +: C_PCI_DATA_WIDTH];
end
endgenerate
assign wChnlNameReady = wReqFieldDemux[`ADDR_FPGA_NAME];
assign wCoreSettingsReady = wReqFieldDemux[`ADDR_CORESETTINGS];
assign wInterVectorReady[0] = wReqFieldDemux[`ADDR_INTR_VECTOR_0];
assign wInterVectorReady[1] = wReqFieldDemux[`ADDR_INTR_VECTOR_1];
assign TXC_META_VALID = TXC_DATA_VALID;
pipeline
#(
// Parameters
.C_DEPTH (C_INPUT_STAGES),
.C_WIDTH (C_RXR_REGISTER_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
rxr_input_register
(// Outputs
.WR_DATA_READY (),// Unconnected
.RD_DATA ({wRxrData,
wRxrDataStartFlag, wRxrDataStartOffset, wRxrMetaFdwbe,
wRxrDataEndFlag, wRxrDataEndOffset, wRxrMetaLdwbe,
wRxrMetaAddr, wRxrMetaType, wRxrMetaLength,
wRxrMetaTag, wRxrMetaRequesterId, wRxrMetaTc, wRxrMetaAttr}),
.RD_DATA_VALID (wRxrDataValid),
// Inputs
.WR_DATA ({RXR_DATA,
RXR_DATA_START_FLAG, RXR_DATA_START_OFFSET, RXR_META_FDWBE,
RXR_DATA_END_FLAG, RXR_DATA_END_OFFSET, RXR_META_LDWBE,
RXR_META_ADDR, RXR_META_TYPE, RXR_META_LENGTH,
RXR_META_TAG, RXR_META_REQUESTER_ID, RXR_META_TC, RXR_META_ATTR}),
.WR_DATA_VALID (RXR_DATA_VALID),
.RD_DATA_READY (1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
demux
#(
// Parameters
.C_OUTPUTS (1<<C_FIELDS_WIDTH),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
field_demux
(
// Outputs
.RD_DATA (wReqFieldDemux),
// Inputs
.WR_DATA (wRxrDataValid),
.WR_SEL (wReqField)
/*AUTOINST*/);
demux
#(
// Parameters
.C_OUTPUTS (C_NUM_CHNL),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
tx_len_ready_demux
(
// Outputs
.RD_DATA (wChnlTxLenReady),
// Inputs
.WR_DATA (wReqFieldDemux[`ADDR_TX_LEN]),
.WR_SEL (wReqChnl)
/*AUTOINST*/);
demux
#(
// Parameters
.C_OUTPUTS (C_NUM_CHNL),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
tx_offlast_ready_demux
(
// Outputs
.RD_DATA (wChnlTxOfflastReady),
// Inputs
.WR_DATA (wReqFieldDemux[`ADDR_TX_OFFLAST]),
.WR_SEL (wReqChnl)
/*AUTOINST*/);
demux
#(
// Parameters
.C_OUTPUTS (C_NUM_CHNL),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
rxdone_demux
(
// Outputs
.RD_DATA (wChnlRxDoneReady),
// Inputs
.WR_DATA (wReqFieldDemux[`ADDR_RX_LEN_XFERD]),
.WR_SEL (wReqChnl)
/*AUTOINST*/);
demux
#(
// Parameters
.C_OUTPUTS (C_NUM_CHNL),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
txdone_demux
(
// Outputs
.RD_DATA (wChnlTxDoneReady),
// Inputs
.WR_DATA (wReqFieldDemux[`ADDR_TX_LEN_XFERD]),
.WR_SEL (wReqChnl)
/*AUTOINST*/);
demux
#(
// Parameters
.C_OUTPUTS (C_NUM_CHNL),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
rx_len_demux
(
// Outputs
.RD_DATA (wChnlRxLenValid),
// Inputs
.WR_DATA (wReqFieldDemux[`ADDR_RX_LEN]),
.WR_SEL (wReqChnl)
/*AUTOINST*/);
demux
#(
// Parameters
.C_OUTPUTS (C_NUM_CHNL),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
rx_offlast_demux
(
// Outputs
.RD_DATA (wChnlRxOfflastValid),
// Inputs
.WR_DATA (wReqFieldDemux[`ADDR_RX_OFFLAST]),
.WR_SEL (wReqChnl)
/*AUTOINST*/);
demux
#(
// Parameters
.C_OUTPUTS (C_NUM_CHNL),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
sgtx_addrhi_demux
(
// Outputs
.RD_DATA (wChnlSgtxAddrHiValid),
// Inputs
.WR_DATA (wReqFieldDemux[`ADDR_SGTX_ADDRHI]),
.WR_SEL (wReqChnl)
/*AUTOINST*/);
demux
#(
// Parameters
.C_OUTPUTS (C_NUM_CHNL),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
sgtx_addrlo_demux
(
// Outputs
.RD_DATA (wChnlSgtxAddrLowValid),
// Inputs
.WR_DATA (wReqFieldDemux[`ADDR_SGTX_ADDRLO]),
.WR_SEL (wReqChnl)
/*AUTOINST*/);
demux
#(
// Parameters
.C_OUTPUTS (C_NUM_CHNL),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
sgtxlen_demux
(
// Outputs
.RD_DATA (wChnlSgtxLenValid),
// Inputs
.WR_DATA (wReqFieldDemux[`ADDR_SGTX_LEN]),
.WR_SEL (wReqChnl)
/*AUTOINST*/);
demux
#(
// Parameters
.C_OUTPUTS (C_NUM_CHNL),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
sgrx_addrhi_demux
(
// Outputs
.RD_DATA (wChnlSgrxAddrHiValid),
// Inputs
.WR_DATA (wReqFieldDemux[`ADDR_SGRX_ADDRHI]),
.WR_SEL (wReqChnl)
/*AUTOINST*/);
demux
#(
// Parameters
.C_OUTPUTS (C_NUM_CHNL),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
sgrx_addrlo_demux
(
// Outputs
.RD_DATA (wChnlSgrxAddrLowValid),
// Inputs
.WR_DATA (wReqFieldDemux[`ADDR_SGRX_ADDRLO]),
.WR_SEL (wReqChnl)
/*AUTOINST*/);
demux
#(
// Parameters
.C_OUTPUTS (C_NUM_CHNL),
.C_WIDTH (1)
/*AUTOINSTPARAM*/)
sgrxlen_demux
(
// Outputs
.RD_DATA (wChnlSgrxLenValid),
// Inputs
.WR_DATA (wReqFieldDemux[`ADDR_SGRX_LEN]),
.WR_SEL (wReqChnl)
/*AUTOINST*/);
pipeline
#(
// Parameters
.C_DEPTH (C_OUTPUT_STAGES),
.C_WIDTH (12*C_NUM_CHNL + C_NUM_VECTORS + 2 + 32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
chnl_output_register
(
// Outputs
.WR_DATA_READY (),// Unconnected
.RD_DATA ({CHNL_TX_LEN_READY, CHNL_TX_OFFLAST_READY, CORE_SETTINGS_READY,
INTR_VECTOR_READY, CHNL_TX_DONE_READY, CHNL_RX_DONE_READY,
CHNL_NAME_READY,CHNL_SGRX_LEN_VALID, CHNL_SGRX_ADDRLO_VALID, CHNL_SGRX_ADDRHI_VALID,
CHNL_SGTX_LEN_VALID, CHNL_SGTX_ADDRLO_VALID, CHNL_SGTX_ADDRHI_VALID,
CHNL_RX_LEN_VALID, CHNL_RX_OFFLAST_VALID,
CHNL_REQ_DATA}),
.RD_DATA_VALID (),
// Inputs
.WR_DATA ({wChnlTxLenReady, wChnlTxOfflastReady, wCoreSettingsReady,
wInterVectorReady, wChnlTxDoneReady, wChnlRxDoneReady,
wChnlNameReady,wChnlSgrxLenValid,wChnlSgrxAddrLowValid,wChnlSgrxAddrHiValid,
wChnlSgtxLenValid,wChnlSgtxAddrLowValid,wChnlSgtxAddrHiValid,
wChnlRxLenValid,wChnlRxOfflastValid,
wChnlReqData}),
.WR_DATA_VALID (1),
.RD_DATA_READY (1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_OUTPUT_STAGES),
.C_WIDTH (C_TXC_REGISTER_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
txc_output_register
(
// Outputs
.WR_DATA_READY (),// Unconnected
.RD_DATA ({TXC_DATA,
TXC_DATA_START_FLAG, TXC_DATA_START_OFFSET, TXC_META_FDWBE,
TXC_DATA_END_FLAG, TXC_DATA_END_OFFSET, TXC_META_LDWBE,
TXC_META_ADDR, TXC_META_TYPE, TXC_META_LENGTH, TXC_META_BYTE_COUNT,
TXC_META_TAG, TXC_META_REQUESTER_ID, TXC_META_TC, TXC_META_ATTR,
TXC_META_EP}),
.RD_DATA_VALID (TXC_DATA_VALID),
// Inputs
.WR_DATA ({wTxcData,
wTxcDataStartFlag, wTxcDataStartOffset, wTxcMetaFdwbe,
wTxcDataEndFlag, wTxcDataEndOffset, wTxcMetaLdwbe,
wTxcMetaAddr, wTxcMetaType, wTxcMetaLength, wTxcMetaByteCount,
wTxcMetaTag, wTxcMetaRequesterId, wTxcMetaTc, wTxcMetaAttr,
wTxcMetaEp}),
.WR_DATA_VALID (wTxcDataValid),
.RD_DATA_READY (TXC_DATA_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../common/")
// End:
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then pretty much all you need to understand about it is
how it maps inputs to outputs -- that is, you can think of it as
just a concrete method for computing a mathematical function.
This is one sense of the word "functional" in "functional
programming." The direct connection between programs and simple
mathematical objects supports both formal proofs of correctness
and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful and powerful idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code. To illustrate this, we will explicitly
recapitulate all the definitions we need in this course, rather
than just getting them implicitly from the library.
To see how this mechanism works, let's start with a very simple
example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
some _type inference_ -- but we'll always include them to make
reading easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, this would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. More
information can also be found in the Coq'Art book by Bertot and
Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] automatically performs
simplification.) *)
(** _A note on notation_: In .v files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool := negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool := andb b1 (andb b2 b3).
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S n' => mult n (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Advanced Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool := andb (ble_nat n m) (negb (beq_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** We could try to prove a similar theorem about [plus] *)
Theorem plus_n_O : forall n, n + 0 = n.
(** However, unlike the previous proof, [simpl] doesn't do anything in
this case *)
Proof.
simpl. (* Doesn't do anything! *)
Abort.
(** (Can you explain why this happens? Step through both proofs with
Coq and notice how the goal and context change.) *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof. intros. rewrite H. rewrite H0. reflexivity. Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros. rewrite H. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof. intros. destruct n. reflexivity. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof. intros. rewrite H. rewrite H. reflexivity. Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros.
destruct b.
destruct c.
reflexivity.
inversion H.
simpl in H. apply H.
Qed.
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * More on Notation (Advanced) *)
(** In general, sections marked Advanced are not needed to follow the
rest of the book, except possibly other Advanced sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** * [Fixpoint] and Structural Recursion (Advanced) *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_data_fifo:1.1
// IP Revision: 8
(* X_CORE_INFO = "axis_data_fifo_v1_1_8_axis_data_fifo,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_SWandHW_standalone_axis_data_fifo_0_0,axis_data_fifo_v1_1_8_axis_data_fifo,{}" *)
(* CORE_GENERATION_INFO = "design_SWandHW_standalone_axis_data_fifo_0_0,axis_data_fifo_v1_1_8_axis_data_fifo,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_data_fifo,x_ipVersion=1.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000011011,C_FIFO_DEPTH=1024,C_FIFO_MODE=1,C_IS_ACLK_ASYNC=0,C_SYNCHRONIZER_STAGE=2,C_ACLKEN_CONV_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_SWandHW_standalone_axis_data_fifo_0_0 (
s_axis_aresetn,
s_axis_aclk,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tkeep,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tlast,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire s_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
input wire [3 : 0] s_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
output wire [3 : 0] m_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
output wire [31 : 0] axis_data_count;
output wire [31 : 0] axis_wr_data_count;
output wire [31 : 0] axis_rd_data_count;
axis_data_fifo_v1_1_8_axis_data_fifo #(
.C_FAMILY("zynq"),
.C_AXIS_TDATA_WIDTH(32),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET('B00000000000000000000000000011011),
.C_FIFO_DEPTH(1024),
.C_FIFO_MODE(1),
.C_IS_ACLK_ASYNC(0),
.C_SYNCHRONIZER_STAGE(2),
.C_ACLKEN_CONV_MODE(0)
) inst (
.s_axis_aresetn(s_axis_aresetn),
.m_axis_aresetn(1'H0),
.s_axis_aclk(s_axis_aclk),
.s_axis_aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(4'HF),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_aclk(1'H0),
.m_axis_aclken(1'H1),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axis_data_count(axis_data_count),
.axis_wr_data_count(axis_wr_data_count),
.axis_rd_data_count(axis_rd_data_count)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_BEHAVIORAL_V
`define SKY130_FD_SC_HS__MUX2I_BEHAVIORAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`include "../u_mux_2_1_inv/sky130_fd_sc_hs__u_mux_2_1_inv.v"
`celldefine
module sky130_fd_sc_hs__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
// Module ports
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
// Local signals
wire u_mux_2_1_inv0_out_Y;
wire u_vpwr_vgnd0_out_Y ;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1_inv u_mux_2_1_inv0 (u_mux_2_1_inv0_out_Y, A0, A1, S );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y , u_mux_2_1_inv0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_BEHAVIORAL_V |
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module tx_fct_counter(
input pclk_tx,
input send_null_tx,
input enable_tx,
input gotfct_tx,
input char_sent,
output reg [5:0] fct_counter_p
);
reg [2:0] state_fct_receive/* synthesis dont_replicate */;
reg [2:0] next_state_fct_receive/* synthesis dont_replicate */;
reg [2:0] state_fct_p/* synthesis dont_replicate */;
reg [2:0] next_state_fct_p/* synthesis dont_replicate */;
reg [5:0] fct_counter_receive;
reg clear_reg;
reg internal_reset;
reg get_got_fct;
always@(posedge gotfct_tx or negedge internal_reset)
begin
if(!internal_reset)
begin
get_got_fct <= 1'b0;
end
else if(send_null_tx)
begin
get_got_fct <= 1'b1;
end
end
always@(*)
begin
next_state_fct_receive = state_fct_receive;
case(state_fct_receive)
3'd0:
begin
if(get_got_fct)
begin
next_state_fct_receive = 3'd1;
end
else if(clear_reg)
begin
next_state_fct_receive = 3'd3;
end
else
next_state_fct_receive = 3'd0;
end
3'd1:
begin
next_state_fct_receive = 3'd2;
end
3'd2:
begin
if(get_got_fct)
begin
next_state_fct_receive = 3'd2;
end
else
begin
next_state_fct_receive = 3'd0;
end
end
3'd3:
begin
next_state_fct_receive = 3'd4;
end
3'd4:
begin
if(clear_reg)
begin
next_state_fct_receive = 3'd4;
end
else
begin
next_state_fct_receive = 3'd0;
end
end
default:
begin
next_state_fct_receive = 3'd0;
end
endcase
end
always@(posedge pclk_tx or negedge enable_tx)
begin
if(!enable_tx)
begin
fct_counter_receive<= 6'd0;
state_fct_receive <= 3'd0;
internal_reset <= 1'b0;
end
else if(send_null_tx)
begin
state_fct_receive <= next_state_fct_receive;
case(state_fct_receive)
3'd0:
begin
fct_counter_receive <= fct_counter_receive;
internal_reset <= 1'b1;
end
3'd1:
begin
fct_counter_receive <= fct_counter_receive + 6'd8;
internal_reset <= 1'b0;
end
3'd2:
begin
fct_counter_receive <= fct_counter_receive;
internal_reset <= 1'b0;
end
3'd3:
begin
fct_counter_receive <= fct_counter_receive;
internal_reset <= 1'b0;
end
3'd4:
begin
internal_reset <= 1'b1;
fct_counter_receive <= 6'd0;
end
default:
begin
fct_counter_receive <= fct_counter_receive;
end
endcase
end
end
always@(*)
begin
next_state_fct_p = state_fct_p;
case(state_fct_p)
3'd0:
begin
if(fct_counter_receive == 6'd56)
begin
next_state_fct_p = 3'd1;
end
else
next_state_fct_p = 3'd0;
end
3'd1:
begin
next_state_fct_p = 3'd2;
end
3'd2:
begin
if(fct_counter_receive == 6'd0)
next_state_fct_p = 3'd3;
else
next_state_fct_p = 3'd2;
end
3'd3:
begin
if(char_sent)
next_state_fct_p = 3'd4;
else
next_state_fct_p = 3'd3;
end
3'd4:
begin
if(!char_sent)
next_state_fct_p = 3'd5;
else
next_state_fct_p = 3'd4;
end
3'd5:
begin
if(fct_counter_p == 6'd0)
next_state_fct_p = 3'd0;
else if(fct_counter_p > 6'd0)
next_state_fct_p = 3'd3;
else
next_state_fct_p = 3'd5;
end
default:
begin
next_state_fct_p = 3'd0;
end
endcase
end
always@(posedge pclk_tx or negedge enable_tx)
begin
if(!enable_tx)
begin
fct_counter_p<= 6'd0;
state_fct_p <= 3'd0;
clear_reg <= 1'b0;
end
else if(send_null_tx)
begin
state_fct_p <= next_state_fct_p;
case(state_fct_p)
3'd0:
begin
clear_reg <= 1'b0;
fct_counter_p <= fct_counter_p;
end
3'd1:
begin
fct_counter_p <= fct_counter_receive;
clear_reg <= 1'b0;
end
3'd2:
begin
if(fct_counter_receive == 6'd0)
clear_reg <= 1'b0;
else
clear_reg <= 1'b1;
fct_counter_p <= fct_counter_p;
end
3'd3:
begin
clear_reg <= 1'b0;
if(char_sent)
begin
if(fct_counter_p == 6'd0)
fct_counter_p <= fct_counter_p;
else
fct_counter_p <= fct_counter_p - 6'd1;
end
else
fct_counter_p <= fct_counter_p;
end
3'd4:
begin
clear_reg <= 1'b0;
fct_counter_p <= fct_counter_p;
end
3'd5:
begin
clear_reg <= 1'b0;
fct_counter_p <= fct_counter_p;
end
default:
begin
fct_counter_p <= fct_counter_p;
end
endcase
end
end
endmodule
|
module shiftRegister(clk, peripheralClkEdge, parallelLoad, parallelDataIn, serialDataIn, parallelDataOut, serialDataOut,peripheralClk8Edge);
parameter width = 8;
input clk;
input peripheralClkEdge;
input peripheralClk8Edge;
input parallelLoad;
output[width-1:0] parallelDataOut;
output serialDataOut;
input[width-1:0] parallelDataIn;
input serialDataIn;
reg[width-1:0] shiftRegisterMem;
assign serialDataOut=shiftRegisterMem[width-1];
assign parallelDataOut=shiftRegisterMem;
always @(posedge peripheralClkEdge) begin
shiftRegisterMem <= {shiftRegisterMem[width-2:0],serialDataIn};
#20
if(parallelLoad) shiftRegisterMem <= parallelDataIn;
end
endmodule
module testShiftRegister;
parameter width = 8;
reg clk;
reg peripheralClkEdge;
reg parallelLoad;
wire[width-1:0] parallelDataOut;
wire serialDataOut;
reg[width-1:0] parallelDataIn;
reg serialDataIn;
reg [4:0] sclk_temp;
shiftregister #(width) sr(clk, peripheralClkEdge, parallelLoad, parallelDataIn, serialDataIn, parallelDataOut, serialDataOut);
initial begin clk=0; sclk_temp=0; end
always #10 clk=!clk;
initial parallelDataIn=16'hA5;
// serial clock
always #10 begin
sclk_temp=sclk_temp+1;
sclk_temp=sclk_temp % 10;
if (sclk_temp==1) peripheralClkEdge=1;
else peripheralClkEdge=0;
end
initial begin
parallelLoad=0;
serialDataIn=1; #200
serialDataIn=0; #200
serialDataIn=1; #200
serialDataIn=0; #200
serialDataIn=1; #200
serialDataIn=0; #200
serialDataIn=1; #200
serialDataIn=0; #200
serialDataIn=1;
parallelLoad=1; #20
parallelLoad=0; #180
serialDataIn=0; #200
serialDataIn=1; #200
serialDataIn=0; #200
serialDataIn=1; #200
serialDataIn=0; #200
serialDataIn=1;
//parallelLoad=0;
//$display("%b", parallelDataOut);
//serialDataIn=1;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//$display("%b", parallelDataOut);
//serialDataIn=1;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//$display("%b", parallelDataOut);
//serialDataIn=0;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//$display("%b", parallelDataOut);
//serialDataIn=1;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//$display("%b", parallelDataOut);
//serialDataIn=1;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//$display("%b", parallelDataOut);
//serialDataIn=0;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//$display("%b", parallelDataOut);
//parallelLoad=1;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//parallelLoad=0;
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0; #90
//peripheralClkEdge=1; #10
//peripheralClkEdge=0;
//$display("%b", parallelDataOut);
end
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Dave McCoy ([email protected])
* Description:
* Simulation of the PCIE Interface, used primarily to test out
* HDL Core
* Changes:
*/
module sim_pcie_axi_bridge #(
parameter USR_CLK_DIVIDE = 4
)(
// PCI Express Fabric Interface
output pci_exp_txp,
output pci_exp_txn,
input pci_exp_rxp,
input pci_exp_rxn,
// Transaction (TRN) Interface
output reg user_lnk_up,
// Tx
output reg s_axis_tx_tready,
input [31:0] s_axis_tx_tdata,
input [3:0] s_axis_tx_tkeep,
input [3:0] s_axis_tx_tuser,
input s_axis_tx_tlast,
input s_axis_tx_tvalid,
output reg [5:0] tx_buf_av,
output reg tx_err_drop,
input tx_cfg_gnt,
output reg tx_cfg_req,
// Rx
output reg [31:0] m_axis_rx_tdata,
output reg [3:0] m_axis_rx_tkeep,
output reg m_axis_rx_tlast,
output reg m_axis_rx_tvalid,
input m_axis_rx_tready,
output reg [21:0] m_axis_rx_tuser,
input rx_np_ok,
// Flow Control
input [2:0] fc_sel,
output [7:0] fc_nph,
output [11:0] fc_npd,
output [7:0] fc_ph,
output [11:0] fc_pd,
output [7:0] fc_cplh,
output [11:0] fc_cpld,
// Host (CFG) Interface
output [31:0] cfg_do,
output cfg_rd_wr_done,
input [9:0] cfg_dwaddr,
input cfg_rd_en,
// Configuration: Error
input cfg_err_ur,
input cfg_err_cor,
input cfg_err_ecrc,
input cfg_err_cpl_timeout,
input cfg_err_cpl_abort,
input cfg_err_posted,
input cfg_err_locked,
input [47:0] cfg_err_tlp_cpl_header,
output cfg_err_cpl_rdy,
// Conifguration: Interrupt
input cfg_interrupt,
output cfg_interrupt_rdy,
input cfg_interrupt_assert,
output [7:0] cfg_interrupt_do,
input [7:0] cfg_interrupt_di,
output [2:0] cfg_interrupt_mmenable,
output cfg_interrupt_msienable,
// Configuration: Power Management
input cfg_turnoff_ok,
output cfg_to_turnoff,
input cfg_pm_wake,
// Configuration: System/Status
output [2:0] cfg_pcie_link_state,
input cfg_trn_pending,
input [63:0] cfg_dsn,
output [7:0] cfg_bus_number,
output [4:0] cfg_device_number,
output reg [2:0] cfg_function_number,
output [15:0] cfg_status,
output [15:0] cfg_command,
output [15:0] cfg_dstatus,
output [15:0] cfg_dcommand,
output [15:0] cfg_lstatus,
output [15:0] cfg_lcommand,
// System Interface
input sys_clk_p,
input sys_clk_n,
input sys_reset,
output user_clk_out,
output user_reset_out,
output received_hot_reset
);
//Local Parameters
localparam RESET_OUT_TIMEOUT = 32'h00000010;
localparam LINKUP_TIMEOUT = 32'h00000010;
localparam CONTROL_PACKET_SIZE = 128;
localparam DATA_PACKET_SIZE = 512;
localparam F2_PACKET_SIZE = 0;
localparam F3_PACKET_SIZE = 0;
localparam F4_PACKET_SIZE = 0;
localparam F5_PACKET_SIZE = 0;
localparam F6_PACKET_SIZE = 0;
localparam F7_PACKET_SIZE = 0;
localparam CONTROL_FUNCTION_ID = 0;
localparam DATA_FUNCTION_ID = 1;
localparam F2_ID = 2;
localparam F3_ID = 3;
localparam F4_ID = 4;
localparam F5_ID = 5;
localparam F6_ID = 6;
localparam F7_ID = 7;
//Registers/Wires
reg clk = 0;
reg [23:0] r_usr_clk_count;
reg rst = 0;
reg [23:0] r_usr_rst_count;
reg [23:0] r_linkup_timeout;
reg [23:0] r_mcount;
reg [23:0] r_scount;
wire [23:0] w_func_size_map [0:7];
//Submodules
//Asynchronous Logic
assign pcie_exp_txp = 0;
assign pcie_exp_txn = 0;
assign user_clk_out = clk;
assign user_reset_out = rst;
assign w_func_size_map[CONTROL_FUNCTION_ID ] = CONTROL_PACKET_SIZE;
assign w_func_size_map[DATA_FUNCTION_ID ] = DATA_PACKET_SIZE;
assign w_func_size_map[F2_ID ] = F2_PACKET_SIZE;
assign w_func_size_map[F3_ID ] = F3_PACKET_SIZE;
assign w_func_size_map[F4_ID ] = F4_PACKET_SIZE;
assign w_func_size_map[F5_ID ] = F5_PACKET_SIZE;
assign w_func_size_map[F6_ID ] = F6_PACKET_SIZE;
assign w_func_size_map[F7_ID ] = F7_PACKET_SIZE;
//TODO
assign received_hot_reset = 0;
assign fc_nph = 0;
assign fc_npd = 0;
assign fc_ph = 0;
assign fc_pd = 0;
assign fc_cplh = 0;
assign fc_cpld = 0;
assign cfg_do = 0;
assign cfg_rd_wr_done = 0;
assign cfg_err_cpl_rdy = 0;
assign cfg_interrupt_rdy = 0;
assign cfg_interrupt_do = 0;
assign cfg_interrupt_mmenable = 0;
assign cfg_interrupt_msienable = 0;
assign cfg_to_turnoff = 0;
assign cfg_pcie_link_state = 0;
assign cfg_bus_number = 0;
assign cfg_device_number = 0;
assign cfg_status = 0;
assign cfg_command = 0;
assign cfg_dstatus = 0;
assign cfg_dcommand = 0;
assign cfg_lstatus = 0;
assign cfg_lcommand = 0;
//Synchronous Logic
//Generate clock
always @ (posedge sys_clk_p) begin
if (sys_reset) begin
clk <= 0;
r_usr_clk_count <= 0;
end
else begin
if (r_usr_clk_count < USR_CLK_DIVIDE) begin
r_usr_clk_count <= r_usr_clk_count + 1;
end
else begin
clk <= ~clk;
end
end
end
//Generate Reset Pulse
always @ (posedge sys_clk_p or posedge sys_reset) begin
if (sys_reset) begin
rst <= 1;
r_usr_rst_count <= 0;
end
else begin
if (r_usr_rst_count < RESET_OUT_TIMEOUT) begin
r_usr_rst_count <= r_usr_rst_count + 1;
end
else begin
rst <= 0;
end
end
end
//Send user a linkup signal
always @ (posedge clk) begin
if (rst) begin
r_linkup_timeout <= 0;
user_lnk_up <= 0;
end
else begin
if (r_linkup_timeout < LINKUP_TIMEOUT) begin
r_linkup_timeout <= r_linkup_timeout + 1;
end
else begin
user_lnk_up <= 1;
end
end
end
//Leave the cfg_function_number available for cocotb to modify in python
always @ (posedge clk) begin
if (rst) begin
cfg_function_number <= 0;
end
else begin
end
end
//Data From PCIE to Core Ggenerator
reg [3:0] dm_state;
localparam IDLE = 0;
localparam READY = 1;
localparam WRITE = 2;
localparam READ = 3;
always @ (posedge clk) begin
m_axis_rx_tlast <= 0;
m_axis_rx_tvalid <= 0;
if (rst) begin
m_axis_rx_tdata <= 0;
dm_state <= IDLE;
m_axis_rx_tkeep <= 4'b1111;
m_axis_rx_tuser <= 0;
r_mcount <= 0;
end
else begin
//m_axis_rx_tready
//rx_np_ok
case (dm_state)
IDLE: begin
r_mcount <= 0;
dm_state <= READY;
m_axis_rx_tdata <= 0;
end
READY: begin
if (m_axis_rx_tready) begin
dm_state <= WRITE;
end
end
WRITE: begin
if (m_axis_rx_tvalid) begin
m_axis_rx_tdata <= m_axis_rx_tdata + 1;
end
if (m_axis_rx_tready && (r_mcount < w_func_size_map[cfg_function_number])) begin
m_axis_rx_tvalid <= 1;
if (r_mcount >= w_func_size_map[cfg_function_number] - 1) begin
m_axis_rx_tlast <= 1;
end
r_mcount <= r_mcount + 1;
end
else begin
dm_state <= IDLE;
end
end
default: begin
end
endcase
end
end
//Data From Core to PCIE Reader
reg [3:0] ds_state;
always @ (posedge clk) begin
s_axis_tx_tready <= 0;
if (rst) begin
//s_axis_tx_tdata
//s_axis_tx_tkeep
//s_axis_tx_tuser
//s_axis_tx_tlast
//s_axis_tx_tvalid
tx_buf_av <= 0;
tx_err_drop <= 0;
//tx_cfg_gnt <= 0;
tx_cfg_req <= 0;
ds_state <= IDLE;
r_scount <= 0;
end
else begin
case (ds_state)
IDLE: begin
r_scount <= 0;
ds_state <= READ;
end
READ: begin
if (s_axis_tx_tvalid && (r_scount < w_func_size_map[cfg_function_number])) begin
s_axis_tx_tready <= 1;
end
else begin
ds_state <= IDLE;
end
end
default: begin
end
endcase
end
end
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_odd_parity (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_ODD_PARITY";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_odd_parity_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_odd_parity_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_odd_parity_psl_logic.v"
`else
`endmodule // ovl_odd_parity
`endif
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bg (
address,
clock,
q);
input [9:0] address;
input clock;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({24{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "mifs/bg.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "mifs/bg.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "24"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "mifs/bg.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_a 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO1N_LP2_V
`define SKY130_FD_SC_LP__ISO1N_LP2_V
/**
* iso1n: ????.
*
* Verilog wrapper for iso1n with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__iso1n.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso1n_lp2 (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__iso1n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.KAGND(KAGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso1n_lp2 (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR ;
supply0 KAGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__iso1n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO1N_LP2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__TAPVGND2_BEHAVIORAL_PP_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND2_BEHAVIORAL_PP_V |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 7
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_7_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
//====================================================================
module CmpEng (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
// ****************************************************************
/*AUTOREG*/
/*AUTOWIRE*/
// ********* Prefetch FSM definitions ****************************
reg [3:0] m_cac_state_r;
reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
reg m_wid1_r;
reg [2:0] m_wid3_r;
reg [5:2] m_wid4_r_l;
logic [4:1] logic_four;
logic [PARAM-1:0] paramed;
`define M 2
`define L 1
parameter MS = 2;
parameter LS = 1;
reg [MS:LS] m_param_r;
reg [`M:`L] m_def2_r;
always @ (posedge clk) begin
if (~reset_l) begin
m_cac_state_r <= CAC_IDLE;
m_cac_sel_r <= CSEL_PF;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
logic_four <= 4'h0;
m_def2_r <= {(1+(`M)-(`L)){1'b0}};
m_param_r <= {(1+(MS)-(LS)){1'b0}};
m_wid1_r <= 1'h0;
m_wid3_r <= 3'h0;
m_wid4_r_l <= ~4'h0;
paramed <= {PARAM{1'b0}};
// End of automatics
end
else begin
m_wid1_r <= 0;
m_wid3_r <= 0;
m_wid4_r_l <= 0;
m_param_r <= 0;
m_def2_r <= 0;
logic_four <= 4;
paramed <= 1;
end
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// verilog-auto-sense-defines-constant: t
// verilog-auto-reset-widths: t
// verilog-active-low-regexp: "_l$"
// End:
|
module soc_system (
clk_clk,
hps_0_f2h_sdram0_data_address,
hps_0_f2h_sdram0_data_burstcount,
hps_0_f2h_sdram0_data_waitrequest,
hps_0_f2h_sdram0_data_readdata,
hps_0_f2h_sdram0_data_readdatavalid,
hps_0_f2h_sdram0_data_read,
hps_0_f2h_sdram1_data_address,
hps_0_f2h_sdram1_data_burstcount,
hps_0_f2h_sdram1_data_waitrequest,
hps_0_f2h_sdram1_data_readdata,
hps_0_f2h_sdram1_data_readdatavalid,
hps_0_f2h_sdram1_data_read,
hps_0_f2h_sdram2_data_address,
hps_0_f2h_sdram2_data_burstcount,
hps_0_f2h_sdram2_data_waitrequest,
hps_0_f2h_sdram2_data_readdata,
hps_0_f2h_sdram2_data_readdatavalid,
hps_0_f2h_sdram2_data_read,
hps_0_f2h_sdram3_data_address,
hps_0_f2h_sdram3_data_burstcount,
hps_0_f2h_sdram3_data_waitrequest,
hps_0_f2h_sdram3_data_writedata,
hps_0_f2h_sdram3_data_byteenable,
hps_0_f2h_sdram3_data_write,
hps_0_f2h_sdram4_data_address,
hps_0_f2h_sdram4_data_burstcount,
hps_0_f2h_sdram4_data_waitrequest,
hps_0_f2h_sdram4_data_writedata,
hps_0_f2h_sdram4_data_byteenable,
hps_0_f2h_sdram4_data_write,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n,
hps_0_i2c1_scl_in_clk,
hps_0_i2c1_clk_clk,
hps_0_i2c1_out_data,
hps_0_i2c1_sda);
input clk_clk;
input [28:0] hps_0_f2h_sdram0_data_address;
input [7:0] hps_0_f2h_sdram0_data_burstcount;
output hps_0_f2h_sdram0_data_waitrequest;
output [63:0] hps_0_f2h_sdram0_data_readdata;
output hps_0_f2h_sdram0_data_readdatavalid;
input hps_0_f2h_sdram0_data_read;
input [28:0] hps_0_f2h_sdram1_data_address;
input [7:0] hps_0_f2h_sdram1_data_burstcount;
output hps_0_f2h_sdram1_data_waitrequest;
output [63:0] hps_0_f2h_sdram1_data_readdata;
output hps_0_f2h_sdram1_data_readdatavalid;
input hps_0_f2h_sdram1_data_read;
input [28:0] hps_0_f2h_sdram2_data_address;
input [7:0] hps_0_f2h_sdram2_data_burstcount;
output hps_0_f2h_sdram2_data_waitrequest;
output [63:0] hps_0_f2h_sdram2_data_readdata;
output hps_0_f2h_sdram2_data_readdatavalid;
input hps_0_f2h_sdram2_data_read;
input [28:0] hps_0_f2h_sdram3_data_address;
input [7:0] hps_0_f2h_sdram3_data_burstcount;
output hps_0_f2h_sdram3_data_waitrequest;
input [63:0] hps_0_f2h_sdram3_data_writedata;
input [7:0] hps_0_f2h_sdram3_data_byteenable;
input hps_0_f2h_sdram3_data_write;
input [28:0] hps_0_f2h_sdram4_data_address;
input [7:0] hps_0_f2h_sdram4_data_burstcount;
output hps_0_f2h_sdram4_data_waitrequest;
input [63:0] hps_0_f2h_sdram4_data_writedata;
input [7:0] hps_0_f2h_sdram4_data_byteenable;
input hps_0_f2h_sdram4_data_write;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
input hps_0_i2c1_scl_in_clk;
output hps_0_i2c1_clk_clk;
output hps_0_i2c1_out_data;
input hps_0_i2c1_sda;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:08:31 04/18/2014
// Design Name:
// Module Name: CPU_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CPU_top(
input wire stp,rst,clk,
input wire [1:0] dptype,
input wire [4:0] regselect,
output wire exec,
output wire [5:0] initype,
output wire [3:0] node,
output wire [7:0] segment
);
wire stp_out,rst_out,zf;
wire [31:0] i_pc;
wire [31:0] dpdata;
wire [31:0] o_pc;
wire [31:0] o_ins;
wire [31:0] o_sign,aluinputb;
wire [4:0] w1;
wire [31:0] pc_add4,add_branch,not_jump;
wire [31:0]Wdata,Adat,Bdat,mem_data,alu_res;
wire RegDst,ALUsrcB,MemToReg,WriteReg,MemWrite,Branch,ALUop1,ALUop0,JMP;
wire [2:0] aluoper;
reg [15:0] digit,count=0;
pbdebounce p0(clk,stp,stp_out);
always @(posedge stp_out) count=count+1;
pbdebounce p1(clk,rst,rst_out);
single_pc PC0(stp_out,rst_out,i_pc,o_pc);
Ins_Mem ins (o_pc[11:2],o_ins);
RegFile regfile(stp_out,o_ins[25:21], o_ins[20:16],regselect, w1, Wdata, WriteReg, Adat, Bdat, dpdata);
Data_Mem data_mem (alu_res[7:2], Bdat,stp_out,MemWrite,mem_data);
cpu_ctr cpuctr(o_ins[31:26],RegDst,ALUsrcB,MemToReg,WriteReg,MemWrite,Branch,ALUop1,ALUop0,JMP );
aluc alucontrol ({ALUop1,ALUop0}, o_ins[3:0], aluoper);
alu alut(Adat, aluinputb, aluoper, zf, alu_res);
sign_extend sign(o_ins[15:0],o_sign);
display dp(clk,digit,node,segment);
add a1(o_pc,32'h4,pc_add4);
add a2(pc_add4,{o_sign[29:0],2'b00},add_branch);
assign w1=(RegDst==1)?o_ins[15:11]:o_ins[20:16];
assign not_jump=(Branch & zf)?add_branch:pc_add4;
assign i_pc=(JMP==1)?{pc_add4[31:29],o_ins[25:0],2'b00}:not_jump;
assign aluinputb=(ALUsrcB==1)?o_sign:Bdat;
assign Wdata=(MemToReg==1)?mem_data:alu_res;
always @* begin
case (dptype)
2'b00:digit<=dpdata[15:0];
2'b01:digit<=dpdata[31:16];
2'b10:digit<=o_pc[15:0];
2'b11:digit<=count;
endcase
end
assign exec=stp_out;
assign initype=o_ins[31:26];
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
parameter NC0 = (necessary_condition == `OVL_TRIGGER_ON_MOST_PIPE);
parameter NC1 = (necessary_condition == `OVL_TRIGGER_ON_FIRST_PIPE);
parameter NC2 = (necessary_condition == `OVL_TRIGGER_ON_FIRST_NOPIPE);
// Guarded parameters for num_cks < 2 (which is bad usage - see warning in top-level file)
parameter NUM_CKS_1 = (num_cks > 0) ? (num_cks - 1) : 0;
parameter NUM_CKS_2 = (num_cks > 1) ? (num_cks - 2) : 0;
parameter LSB_1 = (num_cks > 1) ? 1 : 0;
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
reg [NUM_CKS_1:0] seq_queue; // REVISIT: bit [0] is redundant (Mantis #1812)
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
seq_queue <= {num_cks{1'b0}};
end
else begin
seq_queue[NUM_CKS_2:0] <= seq_queue[NUM_CKS_1:1] & event_sequence[NUM_CKS_2:0];
seq_queue[NUM_CKS_1] <= NC2 ? event_sequence[NUM_CKS_1] && (~(|seq_queue[NUM_CKS_1:1]))
: event_sequence[NUM_CKS_1];
end
end
`endif // OVL_SHARED_CODE
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1, fire_2state_2;
reg fire_2state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_2state <= 1'b0;
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"First event occured but it is not followed by the rest of the events in sequence");
end
if (fire_2state_2) begin
ovl_error_t(`OVL_FIRE_2STATE,"First num_cks-1 events occured but they are not followed by the last event in sequence");
end
if (fire_2state_1 || fire_2state_2) begin
fire_2state <= ovl_fire_2state_f(property_type);
end
else begin
fire_2state <= 1'b0;
end
end
end
assign fire_2state_1 = ((NC1 || NC2) && (&((seq_queue[NUM_CKS_1:LSB_1] & event_sequence[NUM_CKS_2:0]) | ~(seq_queue[NUM_CKS_1:LSB_1])) == 1'b0));
assign fire_2state_2 = ( NC0 && ((!seq_queue[1] || ((seq_queue[1] && event_sequence[0]))) == 1'b0));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1, fire_xcheck_2, fire_xcheck_3, fire_xcheck_4, fire_xcheck_5, fire_xcheck_6;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"First event in the sequence contains X or Z");
end
if (fire_xcheck_2) begin
ovl_error_t(`OVL_FIRE_XCHECK,"First event in the sequence contains X or Z");
end
if (fire_xcheck_3) begin
ovl_error_t(`OVL_FIRE_XCHECK,"Subsequent events in the sequence contain X or Z");
end
if (fire_xcheck_4) begin
ovl_error_t(`OVL_FIRE_XCHECK,"First num_cks-1 events in the sequence contain X or Z");
end
if (fire_xcheck_5) begin
ovl_error_t(`OVL_FIRE_XCHECK,"Last event in the sequence contains X or Z");
end
if (fire_xcheck_6) begin
ovl_error_t(`OVL_FIRE_XCHECK,"First num_cks-1 events in the sequence contain X or Z");
end
if (fire_xcheck_1 || fire_xcheck_2 || fire_xcheck_3 || fire_xcheck_4 || fire_xcheck_5 || fire_xcheck_6) begin
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
wire valid_first_event = ~( event_sequence[NUM_CKS_1] ^
event_sequence[NUM_CKS_1] );
wire valid_sequence = (~((^(seq_queue[NUM_CKS_1:LSB_1] &
event_sequence[NUM_CKS_2:0] &
{{(NUM_CKS_2){1'b1}},{~(|NC0)}})) ^
(^(seq_queue[NUM_CKS_1:LSB_1] &
event_sequence[NUM_CKS_2:0] &
{{(NUM_CKS_2){1'b1}},{~(|NC0)}}))));
wire valid_last_event = ~((seq_queue[1] && event_sequence[0]) ^
(seq_queue[1] && event_sequence[0]));
always @ (valid_first_event or seq_queue) begin
if (valid_first_event) begin
fire_xcheck_1 = 1'b0;
fire_xcheck_2 = 1'b0;
end
else begin
fire_xcheck_1 = (NC0 || NC1);
fire_xcheck_2 = (NC2 && ~(|seq_queue[NUM_CKS_1:1]));
end
end
always @ (valid_sequence) begin
if (valid_sequence) begin
fire_xcheck_3 = 1'b0;
fire_xcheck_4 = 1'b0;
end
else begin
fire_xcheck_3 = (NC1 || NC2);
fire_xcheck_4 = (NC0);
end
end
always @ (valid_last_event or seq_queue) begin
if (valid_last_event) begin
fire_xcheck_5 = 1'b0;
fire_xcheck_6 = 1'b0;
end
else begin
fire_xcheck_5 = (NC0 && seq_queue[1]);
fire_xcheck_6 = (NC0 && ~seq_queue[1]);
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
wire fire_cover_1, fire_cover_2;
reg fire_cover;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_cover <= 1'b0;
end
else begin
if (fire_cover_1) begin
ovl_cover_t("sequence_trigger covered"); // basic
end
if (fire_cover_2) begin
ovl_cover_t("sequence_trigger covered"); // basic
end
if (fire_cover_1 || fire_cover_2) begin
fire_cover <= 1'b1;
end
else begin
fire_cover <= 1'b0;
end
end
end
assign fire_cover_1 = ((OVL_COVER_BASIC_ON > 0) && (NC1 || NC2) && event_sequence[NUM_CKS_1]);
assign fire_cover_2 = ((OVL_COVER_BASIC_ON > 0) && NC0 && (&seq_queue[1])); // REVISIT: Reduction-AND is redundant
`else
wire fire_cover = 1'b0;
`endif // OVL_COVER_ON
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Logic Core: PCI/Avalon Bridge Megacore Function
// Company: Altera Corporation.
// www.altera.com
// Author: IPBU SIO Group
//
// Description: Avalon to PCI Variable Address Translation Table
//
// Copyright (c) 2004 Altera Corporation. All rights reserved. This source code
// is highly confidential and proprietary information of Altera and is being
// provided in accordance with and subject to the protections of a
// Non-Disclosure Agreement which governs its use and disclosure. Altera
// products and services are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws. Altera
// assumes no responsibility or liability arising out of the application or use
// of this source code.
//
// For Best Viewing Set tab stops to 4 spaces.
//
// $Id: //acds/main/ip/pci_express/src/rtl/lib/avalon/altpciexpav_a2p_vartrans.v#5 $
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
module altpciexpav_stif_a2p_vartrans
#(
parameter CB_A2P_ADDR_MAP_NUM_ENTRIES = 16 ,
parameter CB_A2P_ADDR_MAP_PASS_THRU_BITS = 12 ,
parameter CG_AVALON_S_ADDR_WIDTH = 32 ,
parameter CG_PCI_ADDR_WIDTH = 32 ,
parameter INTENDED_DEVICE_FAMILY = "Stratix" ,
parameter A2P_ADDR_TRANS_TR_OUTREG = 1,
parameter A2P_ADDR_TRANS_RA_OUTREG = 1
)
(
input PbaClk_i, // Clock for a2p Trans
input PbaRstn_i, // Reset signal
input [CG_AVALON_S_ADDR_WIDTH-1:0] PbaAddress_i, // Byte specific address
input PbaAddrVld_i, // Valid indication in
output reg [CG_PCI_ADDR_WIDTH-1:0] PciAddr_o, // Byte specific address
output reg [1:0] PciAddrSpace_o, // DAC Needed
output reg PciAddrVld_o, // Valid indication out
input CraClk_i, // Clock for access port
input CraRstn_i, // Reset signal
input [11:2] AdTrAddress_i, // DWORD specific address
input [3:0] AdTrByteEnable_i,// Register Byte Enables
input AdTrWriteVld_i, // Valid Write Cycle in
input [31:0] AdTrWriteData_i, // Write Data in
input AdTrReadVld_i, // Read Valid in
output reg [31:0] AdTrReadData_o, // Read Data out
output reg AdTrReadVld_o // Read Valid out (piped)
) ;
// Address space definitions
localparam [1:0] ADSP_CONFIG = 2'b11 ;
localparam [1:0] ADSP_IO = 2'b10 ;
localparam [1:0] ADSP_MEM64 = 2'b01 ;
localparam [1:0] ADSP_MEM32 = 2'b00 ;
//define the clogb2 constant function
function integer clogb2;
input [31:0] depth;
begin
depth = depth - 1 ;
for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1)
depth = depth >> 1 ;
end
endfunction // clogb2
localparam TABLE_ADDR_WIDTH = clogb2(CB_A2P_ADDR_MAP_NUM_ENTRIES) ;
// Quartus can't handle the range specification on parameters SPR160299
// so we need to leave that off for now.
// localparam [(13*8)-1:0] OUTREG_A_CLK = A2P_ADDR_TRANS_TR_OUTREG == 1 ?
localparam OUTREG_A_CLK = A2P_ADDR_TRANS_TR_OUTREG == 1 ?
"CLOCK0" : "UNREGISTERED" ;
// localparam [(13*8)-1:0] OUTREG_B_CLK = A2P_ADDR_TRANS_RA_OUTREG == 1 ?
localparam OUTREG_B_CLK = A2P_ADDR_TRANS_RA_OUTREG == 1 ?
"CLOCK1" : "UNREGISTERED" ;
// The following parameter is used to avoid a fatal modelsim error on code
// that won't actually get executed when CG_PCI_ADDR_WIDTH is 32.
//
localparam UPPER_PCI_ADDR_BIT_WIDTH
= CG_PCI_ADDR_WIDTH > 32 ? CG_PCI_ADDR_WIDTH : 64 ;
reg [(TABLE_ADDR_WIDTH-1):0] table_trans_index ;
reg [63:0] table_write_data ;
reg [7:0] table_write_byteena ;
reg [(TABLE_ADDR_WIDTH-1):0] table_cra_addr ;
wire [63:0] table_trans_data ;
wire [63:0] table_read_data ;
reg AdTrReadVld_q1 ;
reg AdTrReadVld_q2 ;
reg AdTrAddr2_q1 ;
reg AdTrAddr2_q2 ;
reg PbaAddrVld_q1 ;
reg PbaAddrVld_q2 ;
reg [CB_A2P_ADDR_MAP_PASS_THRU_BITS-1:0] PbaAddress_q1 ;
reg [CB_A2P_ADDR_MAP_PASS_THRU_BITS-1:0] PbaAddress_q2 ;
// Calculate the index into the table from the incoming address
always @(PbaAddress_i)
begin
table_trans_index = PbaAddress_i[CG_AVALON_S_ADDR_WIDTH-1:
CB_A2P_ADDR_MAP_PASS_THRU_BITS] %
CB_A2P_ADDR_MAP_NUM_ENTRIES ;
end
// Calculate the Write Port Parameters
always @(AdTrAddress_i or AdTrByteEnable_i or AdTrWriteData_i)
begin
table_write_data = 64'h0000000000000000 ;
table_cra_addr = AdTrAddress_i[TABLE_ADDR_WIDTH+2:3] ;
if (AdTrAddress_i[2] == 1'b1)
begin
table_write_byteena = {AdTrByteEnable_i,4'b0000} ;
if (CG_PCI_ADDR_WIDTH > 32)
// Need a special value here even when CG_PCI_ADDR_WIDTH = 32
table_write_data[UPPER_PCI_ADDR_BIT_WIDTH-1:32]
= AdTrWriteData_i[UPPER_PCI_ADDR_BIT_WIDTH-33:0] ;
end
else
begin
table_write_byteena = {4'b0000,AdTrByteEnable_i} ;
table_write_data[31:CB_A2P_ADDR_MAP_PASS_THRU_BITS]
= AdTrWriteData_i[31:CB_A2P_ADDR_MAP_PASS_THRU_BITS] ;
if ( (CG_PCI_ADDR_WIDTH < 33) && (AdTrWriteData_i[1:0] == ADSP_MEM64) )
begin
// synthesis translate_off
if ( (AdTrByteEnable_i[0] == 1'b1) && (AdTrWriteVld_i == 1'b1) )
$display("WARNING: Attempt to write 64-bit Memory space in 32-bit mode, 32-bit forced.") ;
// synthesis translate_on
table_write_data[1:0] = ADSP_MEM32 ;
end
else
begin
table_write_data[1:0] = AdTrWriteData_i[1:0] ;
end
end // else: !if(AdTrAddress_i[2] == 1'b1)
end // always @ (AdTrAddress_i or AdTrByteEnable_i)
// Pipeline the Valid signal and the DWORD select bit
always @(posedge CraClk_i or negedge CraRstn_i)
begin
if (CraRstn_i == 1'b0)
begin
AdTrReadVld_q1 <= 1'b0 ;
AdTrReadVld_q2 <= 1'b0 ;
AdTrAddr2_q1 <= 1'b0 ;
AdTrAddr2_q2 <= 1'b0 ;
end
else
begin
AdTrReadVld_q2 <= AdTrReadVld_q1 ;
AdTrReadVld_q1 <= AdTrReadVld_i ;
AdTrAddr2_q2 <= AdTrAddr2_q1 ;
AdTrAddr2_q1 <= AdTrAddress_i[2] ;
end // else: !if(CraRstn_i == 1'b0)
end // always @ (posedge CraClk_i or negedge CraRstn_i)
// Pipeline the Translation Address Valid signal
always @(posedge PbaClk_i or negedge PbaRstn_i)
begin
if (PbaRstn_i == 1'b0)
begin
PbaAddrVld_q1 <= 1'b0 ;
PbaAddrVld_q2 <= 1'b0 ;
PbaAddress_q1 <= 0 ;
PbaAddress_q2 <= 0 ;
end
else
begin
PbaAddrVld_q2 <= PbaAddrVld_q1 ;
PbaAddrVld_q1 <= PbaAddrVld_i ;
PbaAddress_q2 <= PbaAddress_q1 ;
PbaAddress_q1 <= PbaAddress_i[CB_A2P_ADDR_MAP_PASS_THRU_BITS-1:0] ;
end
end
// Calculate the final PCI Address and the valid signal
always @(PbaAddress_q2 or PbaAddress_q1 or table_trans_data or PbaAddrVld_q1 or PbaAddrVld_q2)
begin
if (A2P_ADDR_TRANS_TR_OUTREG == 1)
begin
PciAddrVld_o = PbaAddrVld_q2 ;
PciAddr_o = {table_trans_data[63:CB_A2P_ADDR_MAP_PASS_THRU_BITS],
PbaAddress_q2[CB_A2P_ADDR_MAP_PASS_THRU_BITS-1:0]} ;
end
else
begin
PciAddrVld_o = PbaAddrVld_q1 ;
PciAddr_o = {table_trans_data[63:CB_A2P_ADDR_MAP_PASS_THRU_BITS],
PbaAddress_q1[CB_A2P_ADDR_MAP_PASS_THRU_BITS-1:0]} ;
end // else: !if(A2P_ADDR_TRANS_TR_OUTREG == 1)
PciAddrSpace_o = table_trans_data[1:0] ;
end
// Calculate the Final Register Read Data and the valid signal
always @(AdTrAddr2_q1 or AdTrAddr2_q2 or AdTrReadVld_q1 or AdTrReadVld_q2 or table_read_data)
begin
if (A2P_ADDR_TRANS_RA_OUTREG == 1)
begin
AdTrReadVld_o = AdTrReadVld_q2 ;
if (AdTrAddr2_q2 == 1'b0)
AdTrReadData_o = table_read_data[31:0] ;
else
AdTrReadData_o = table_read_data[63:32] ;
end
else
begin
AdTrReadVld_o = AdTrReadVld_q1 ;
if (AdTrAddr2_q1 == 1'b0)
AdTrReadData_o = table_read_data[31:0] ;
else
AdTrReadData_o = table_read_data[63:32] ;
end
end
// The actual translation table
altsyncram
#(
.intended_device_family(INTENDED_DEVICE_FAMILY),
.operation_mode("BIDIR_DUAL_PORT"),
.width_a(64),
.widthad_a(TABLE_ADDR_WIDTH),
.numwords_a(CB_A2P_ADDR_MAP_NUM_ENTRIES),
.width_b(64),
.widthad_b(TABLE_ADDR_WIDTH),
.numwords_b(CB_A2P_ADDR_MAP_NUM_ENTRIES),
.lpm_type("altsyncram"),
.width_byteena_a(1),
.width_byteena_b(8),
.byte_size(8),
.indata_aclr_a("CLEAR0"),
.wrcontrol_aclr_a("CLEAR0"),
.address_aclr_a("CLEAR0"),
.indata_reg_b("CLOCK1"),
.address_reg_b("CLOCK1"),
.wrcontrol_wraddress_reg_b("CLOCK1"),
.indata_aclr_b("CLEAR1"),
.wrcontrol_aclr_b("CLEAR1"),
.address_aclr_b("CLEAR1"),
.byteena_reg_b("CLOCK1"),
.byteena_aclr_b("CLEAR1"),
.outdata_reg_a(OUTREG_A_CLK),
// .outdata_aclr_a("CLEAR0"),
.outdata_reg_b(OUTREG_B_CLK)
// .outdata_aclr_b("CLEAR1")
)
altsyncram_component
(
.wren_a (1'b0),
.clock0 (PbaClk_i),
.wren_b (AdTrWriteVld_i),
.clock1 (CraClk_i),
.byteena_b (table_write_byteena),
.address_a (table_trans_index),
.address_b (table_cra_addr),
.data_a (64'h0000000000000000),
.data_b (table_write_data),
.q_a (table_trans_data),
.q_b (table_read_data)
// synopsys translate_off
,
.byteena_a (),
.rden_b (),
.clocken0 (),
.clocken1 (),
.addressstall_a (),
.addressstall_b ()
// synopsys translate_on
);
endmodule // altpa_a2p_vartrans
|
module spdif_tx(
input wire clk, // 24.576Mhz
input wire rst,
input wire [1:0] ack_i,
input [47:0] data_i,
output wire [1:0] pop_o,
input wire [191:0] udata_i,
input wire [191:0] cdata_i,
output wire spdif_o
);
reg halfbit_ff;
always @(posedge clk) begin
if (rst)
halfbit_ff <= 1'b0;
else
halfbit_ff <= ~halfbit_ff;
end
wire halfbit = halfbit_ff;
reg [47:0] data_latch;
always @(posedge clk) begin
if (ack_i[0])
data_latch[23:0] <= data_i[23:0];
if (ack_i[1])
data_latch[47:24] <= data_i[47:24];
end
parameter SYNCCODE_B0 = 8'b00010111;
parameter SYNCCODE_W0 = 8'b00011011;
parameter SYNCCODE_M0 = 8'b00011101;
parameter SYNCCODE_B1 = ~SYNCCODE_B0;
parameter SYNCCODE_W1 = ~SYNCCODE_W0;
parameter SYNCCODE_M1 = ~SYNCCODE_M0;
reg [4:0] subframe_pos_counter_ff;
always @(posedge clk) begin
if (rst) begin
subframe_pos_counter_ff <= 5'd0;
end else if (halfbit) begin
subframe_pos_counter_ff <= subframe_pos_counter_ff + 5'd1;
end
end
wire send_synccode = subframe_pos_counter_ff < 5'd4;
wire send_parity = subframe_pos_counter_ff == 5'd31;
wire prepare_subframe = halfbit & (subframe_pos_counter_ff == 5'd3);
wire prepare_synccode_type = ~halfbit & (subframe_pos_counter_ff == 5'd31);
wire prepare_synccode = halfbit & (subframe_pos_counter_ff == 5'd31);
wire prev_subframe_end;
reg [2:0] synccode_type_ff;
parameter SYNCCODE_TYPE_B = 0;
parameter SYNCCODE_TYPE_W = 1;
parameter SYNCCODE_TYPE_M = 2;
reg [7:0] frame_counter_ff;
wire end_of_frame = frame_counter_ff == 8'd191;
always @(posedge clk) begin
if (rst) begin
synccode_type_ff <= SYNCCODE_TYPE_B;
frame_counter_ff <= 8'd191;
end else if (prepare_synccode_type) begin
case (synccode_type_ff)
SYNCCODE_TYPE_B:
synccode_type_ff <= SYNCCODE_TYPE_W;
SYNCCODE_TYPE_W:
synccode_type_ff <= end_of_frame ? SYNCCODE_TYPE_B : SYNCCODE_TYPE_M;
SYNCCODE_TYPE_M:
synccode_type_ff <= SYNCCODE_TYPE_W;
endcase
if (end_of_frame)
frame_counter_ff <= 8'd0;
else
frame_counter_ff <= frame_counter_ff + 1;
end
end
assign pop_ch = (synccode_type_ff == SYNCCODE_TYPE_W) ? 1'b1 : 1'b0;
reg [7:0] synccode_shiftreg;
always @(posedge clk) begin
if (prepare_synccode) begin
case (synccode_type_ff)
SYNCCODE_TYPE_B:
synccode_shiftreg <= prev_subframe_end ? SYNCCODE_B0 : SYNCCODE_B1;
SYNCCODE_TYPE_W:
synccode_shiftreg <= prev_subframe_end ? SYNCCODE_W0 : SYNCCODE_W1;
SYNCCODE_TYPE_M:
synccode_shiftreg <= prev_subframe_end ? SYNCCODE_M0 : SYNCCODE_M1;
endcase
end else
synccode_shiftreg <= {synccode_shiftreg[6:0], 1'b0};
end
// FIXME
wire [23:0] data_active = pop_ch ? data_latch[47:24] : data_latch[23:0];
// {User,Control} data
reg [191:0] udata_shiftreg;
reg [191:0] cdata_shiftreg;
always @(posedge clk) begin
if (end_of_frame)
udata_shiftreg <= udata_i;
else if (prepare_subframe)
udata_shiftreg <= {udata_shiftreg[190:0], 1'b0};
if (end_of_frame)
cdata_shiftreg <= cdata_i;
else if (prepare_subframe)
cdata_shiftreg <= {cdata_shiftreg[190:0], 1'b0};
end
reg [26:0] subframe_shiftreg;
always @(posedge clk) begin
if (prepare_subframe) begin
subframe_shiftreg <= {data_active, 1'b1, udata_shiftreg[191], cdata_shiftreg[191]};
end else if (halfbit)
subframe_shiftreg <= {subframe_shiftreg[25:0], 1'b0};
end
wire subframe_bit = subframe_shiftreg[26];
reg parity_ff;
always @(posedge clk) begin
if (prepare_subframe)
parity_ff <= 0;
else if (halfbit)
parity_ff <= parity_ff ^ subframe_bit;
end
wire parity = parity_ff;
wire subframe_or_parity_bit = send_parity ? parity : subframe_shiftreg[26];
reg encoded_subframe_ff;
always @(posedge clk) begin
if (rst)
encoded_subframe_ff <= 0;
else
encoded_subframe_ff <= (subframe_or_parity_bit | halfbit) ^ encoded_subframe_ff;
end
wire spdif_tbo = send_synccode ? synccode_shiftreg[7] : encoded_subframe_ff;
assign prev_subframe_end = encoded_subframe_ff;
reg spdif_out_ff;
always @(posedge clk)
spdif_out_ff <= spdif_tbo;
assign spdif_o = spdif_out_ff;
assign pop_o = prepare_subframe ? {pop_ch, ~pop_ch} : 2'b0;
endmodule
|
// fpgaTop_kc705.v - the top-level Verilog for the Xilinx KC705 board
// Copyright (c) 2011-2012 Atomic Rules LLC - ALL RIGHTS RESERVED
//
module fpgaTop (
input wire sys0_clkp, // sys0 Clock +
input wire sys0_clkn, // sys0 Clock -
input wire sys0_rst, // sys0 Reset (active high)
input wire sys1_clkp, // sys1 Clock +
input wire sys1_clkn, // sys1 Clock -
input wire pci0_clkp, // PCIe Clock +
input wire pci0_clkn, // PCIe Clock -
input wire pci0_reset_n, // PCIe Reset
output wire [3:0] pci_exp_txp, // PCIe lanes...
output wire [3:0] pci_exp_txn,
input wire [3:0] pci_exp_rxp,
input wire [3:0] pci_exp_rxn,
//input wire ppsExtIn, // PPS in
//output wire ppsOut, // PPS out
//
input wire [ 7:0] usr_sw, // dip-switches
output wire [ 7:0] led, // leds
output wire [ 3:0] lcd_db, // LCD databus
output wire lcd_e, // LCD enable
output wire lcd_rs, // LCD register-select
output wire lcd_rw, // LCD read-not-write
output wire [15:0] debug, // debug
output wire gmii_rstn, // Alaska GMII...
output wire gmii_gtx_clk,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
input wire gmii_rx_clk,
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire mdio_mdc, // Alaska MDIO...
inout wire mdio_mdd
//output wire [23:0] flash_addr,
//inout wire [15:0] flash_io_dq,
//input wire flash_wait,
//output wire flash_we_n,
//output wire flash_oe_n,
//output wire flash_ce_n
//inout wire [63:0] ddr3_dq, // DDR3 DRAM...
//output wire [12:0] ddr3_addr,
//output wire [2:0] ddr3_ba,
//output wire ddr3_ras_n,
//output wire ddr3_cas_n,
//output wire ddr3_we_n,
//output wire ddr3_reset_n,
//output wire [0:0] ddr3_cs_n,
//output wire [0:0] ddr3_odt,
//output wire [0:0] ddr3_cke,
//output wire [7:0] ddr3_dm,
//inout wire [7:0] ddr3_dqs_p,
//inout wire [7:0] ddr3_dqs_n,
//output wire [0:0] ddr3_ck_p,
//output wire [0:0] ddr3_ck_n
//output wire flp_com_sclk, // FMC150 in LPC Slot...
//output wire flp_com_sdc2m,
//input wire flp_cdc_sdm2c,
//input wire flp_mon_sdm2c,
//input wire flp_adc_sdm2c,
//input wire flp_dac_sdm2c,
//output wire flp_cdc_sen_n,
//output wire flp_mon_sen_n,
//output wire flp_adc_sen_n,
//output wire flp_dac_sen_n,
//output wire flp_cdc_rstn,
//output wire flp_cdc_pdn,
//output wire flp_mon_rstn,
//output wire flp_mon_intn,
//output wire flp_adc_rstn
);
// Instance and connect mkFTop...
mkFTop_kc705 ftop(
.sys0_clkp (sys0_clkp),
.sys0_clkn (sys0_clkn),
.sys0_rstn (!sys0_rst), // Invert to make active-low
.sys1_clkp (sys1_clkp),
.sys1_clkn (sys1_clkn),
.pci0_clkp (pci0_clkp),
.pci0_clkn (pci0_clkn),
.pci0_rstn (pci0_reset_n),
.pcie_rxp_i (pci_exp_rxp),
.pcie_rxn_i (pci_exp_rxn),
.pcie_txp (pci_exp_txp),
.pcie_txn (pci_exp_txn),
.led (led),
.lcd_db (lcd_db),
.lcd_e (lcd_e),
.lcd_rs (lcd_rs),
.lcd_rw (lcd_rw),
//.gps_ppsSyncIn_x (ppsExtIn),
//.gps_ppsSyncOut (ppsOut),
.usr_sw_i (usr_sw),
.debug (debug),
.gmii_rstn (gmii_rstn),
.gmii_tx_txd (gmii_txd),
.gmii_tx_tx_en (gmii_tx_en),
.gmii_tx_tx_er (gmii_tx_er),
.gmii_rx_rxd_i (gmii_rxd),
.gmii_rx_rx_dv_i (gmii_rx_dv),
.gmii_rx_rx_er_i (gmii_rx_er),
.gmii_tx_tx_clk (gmii_gtx_clk),
.gmii_rx_clk (gmii_rx_clk),
.mdio_mdc (mdio_mdc),
.mdio_mdd (mdio_mdd)
//.flash_addr (flash_addr),
//.flash_io_dq (flash_io_dq),
//.flash_fwait_i (flash_wait),
//.flash_we_n (flash_we_n),
//.flash_oe_n (flash_oe_n),
//.flash_ce_n (flash_ce_n)
//.dram_io_dq (ddr3_dq),
//.dram_addr (ddr3_addr),
//.dram_ba (ddr3_ba),
//.dram_ras_n (ddr3_ras_n),
//.dram_cas_n (ddr3_cas_n),
//.dram_we_n (ddr3_we_n),
//.dram_reset_n (ddr3_reset_n),
//.dram_cs_n (ddr3_cs_n),
//.dram_odt (ddr3_odt),
//.dram_cke (ddr3_cke),
//.dram_dm (ddr3_dm),
//.dram_io_dqs_p (ddr3_dqs_p),
//.dram_io_dqs_n (ddr3_dqs_n),
//.dram_ck_p (ddr3_ck_p),
//.dram_ck_n (ddr3_ck_n)
//.flp_com_sclk (flp_com_sclk),
//.flp_com_sdc2m (flp_com_sdc2m),
//.flp_cdc_sdm2c (flp_cdc_sdm2c),
//.flp_mon_sdm2c (flp_mon_sdm2c),
//.flp_adc_sdm2c (flp_adc_sdm2c),
//.flp_dac_sdm2c (flp_dac_sdm2c),
//.flp_cdc_sen_n (flp_cdc_sen_n),
//.flp_mon_sen_n (flp_mon_sen_n),
//.flp_adc_sen_n (flp_adc_sen_n),
//.flp_dac_sen_n (flp_dac_sen_n),
//.flp_cdc_rstn (flp_cdc_rstn),
//.flp_cdc_pdn (flp_cdc_pdn),
//.flp_mon_rstn (flp_mon_rstn),
//.flp_mon_intn (flp_mon_intn),
//.flp_adc_rstn (flp_adc_rstn)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Thomas Kappenman
//
// Create Date: 03/03/2015 09:08:33 PM
// Design Name:
// Module Name: seg7decimal
// Project Name: Nexys4DDR Keyboard Demo
// Target Devices: Nexys4DDR
// Tool Versions:
// Description: 7 segment display driver
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seg7decimal(
input [31:0] x,
input clk,
output reg [6:0] seg,
output reg [7:0] an,
output wire dp
);
wire [2:0] s;
reg [3:0] digit;
wire [7:0] aen;
reg [19:0] clkdiv;
assign dp = 1;
assign s = clkdiv[19:17];
assign aen = 8'b11111111; // all turned off initially
// quad 4to1 MUX.
always @(posedge clk)// or posedge clr)
case(s)
0:digit = x[3:0]; // s is 00 -->0 ; digit gets assigned 4 bit value assigned to x[3:0]
1:digit = x[7:4]; // s is 01 -->1 ; digit gets assigned 4 bit value assigned to x[7:4]
2:digit = x[11:8]; // s is 10 -->2 ; digit gets assigned 4 bit value assigned to x[11:8
3:digit = x[15:12]; // s is 11 -->3 ; digit gets assigned 4 bit value assigned to x[15:12]
4:digit = x[19:16]; // s is 00 -->0 ; digit gets assigned 4 bit value assigned to x[3:0]
5:digit = x[23:20]; // s is 01 -->1 ; digit gets assigned 4 bit value assigned to x[7:4]
6:digit = x[27:24]; // s is 10 -->2 ; digit gets assigned 4 bit value assigned to x[11:8
7:digit = x[31:28]; // s is 11 -->3 ; digit gets assigned 4 bit value assigned to x[15:12]
default:digit = x[3:0];
endcase
//decoder or truth-table for 7seg display values
always @(*)
case(digit)
//////////<---MSB-LSB<---
//////////////gfedcba//////////////////////////////////////////// a
0:seg = 7'b1000000;////0000 __
1:seg = 7'b1111001;////0001 f/ /b
2:seg = 7'b0100100;////0010 g
// __
3:seg = 7'b0110000;////0011 e / /c
4:seg = 7'b0011001;////0100 __
5:seg = 7'b0010010;////0101 d
6:seg = 7'b0000010;////0110
7:seg = 7'b1111000;////0111
8:seg = 7'b0000000;////1000
9:seg = 7'b0010000;////1001
'hA:seg = 7'b0001000;
'hB:seg = 7'b0000011;
'hC:seg = 7'b1000110;
'hD:seg = 7'b0100001;
'hE:seg = 7'b0000110;
'hF:seg = 7'b0001110;
default: seg = 7'b0000000; // U
endcase
always @(*)begin
an=8'b11111111;
if(aen[s] == 1)
an[s] = 0;
end
//clkdiv
always @(posedge clk) begin
clkdiv <= clkdiv+1;
end
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/nes_top.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Top level module for an fpga-based Nintendo Entertainment System emulator.
***************************************************************************************************/
`timescale 1 ns/1 ps
module nes_top (
input clk, // 100MHz system clock signal
input rst, // reset push button
input i_console_reset, // console reset
input [3:0] i_mute_control, // switches
output [9:0] o_image_width, // width of the generated image
output [9:0] o_image_height, // height of the generated image
output o_hsync, // vga hsync signal
output o_vsync, // vga vsync signal
output [2:0] o_red, // vga red signal
output [2:0] o_green, // vga green signal
output [1:0] o_blue, // vga blue signal
// Joypad signals.
input [7:0] i_jp1_state, //State of joypad 1
input [7:0] i_jp2_state, //State of joypad 2
output o_audio, // pwm output audio channel
input i_hci_reset,
input [7:0] i_hci_opcode,
input i_hci_opcode_strobe,
output [15:0] o_hci_opcode_status,
output o_hci_opcode_ack,
input [15:0] i_hci_address,
input [31:0] i_hci_count,
input i_hci_data_strobe,
output o_hci_sm_ready,
input [7:0] i_hci_data,
output o_hci_data_strobe,
input i_hci_host_ready,
output [7:0] o_hci_data
);
//
// System Memory Buses
//
wire [ 7:0] cpumc_din;
wire [15:0] cpumc_a;
wire cpumc_r_nw;
wire [ 7:0] ppumc_din;
wire [13:0] ppumc_a;
wire ppumc_wr;
//
// RP2A03: Main processing chip including CPU, APU, joypad control, and sprite DMA control.
//
wire rp2a03_rdy;
wire [ 7:0] rp2a03_din;
wire rp2a03_nnmi;
wire [ 7:0] rp2a03_dout;
wire [15:0] rp2a03_a;
wire rp2a03_r_nw;
wire rp2a03_brk;
wire [ 3:0] rp2a03_dbgreg_sel;
wire [ 7:0] rp2a03_dbgreg_din;
wire rp2a03_dbgreg_wr;
wire [ 7:0] rp2a03_dbgreg_dout;
rp2a03 rp2a03_blk(
.clk_in (clk ),
.rst_in (rst ),
.rdy_in (rp2a03_rdy ),
.nres_in (~i_console_reset ),
.nnmi_in (rp2a03_nnmi ),
.r_nw_out (rp2a03_r_nw ),
.a_out (rp2a03_a ),
.d_in (rp2a03_din ),
.d_out (rp2a03_dout ),
.brk_out (rp2a03_brk ),
.i_jp1_state (i_jp1_state ),
.i_jp2_state (i_jp2_state ),
.mute_in (i_mute_control ),
.audio_out (o_audio ),
.dbgreg_sel_in (rp2a03_dbgreg_sel ),
.dbgreg_d_in (rp2a03_dbgreg_din ),
.dbgreg_wr_in (rp2a03_dbgreg_wr ),
.dbgreg_d_out (rp2a03_dbgreg_dout )
);
//
// CART: cartridge emulator
//
wire cart_prg_nce;
wire [ 7:0] cart_prg_dout;
wire [ 7:0] cart_chr_dout;
wire cart_ciram_nce;
wire cart_ciram_a10;
wire [39:0] cart_cfg;
wire cart_cfg_upd;
cart cart_blk(
.clk_in (clk ),
.cfg_in (cart_cfg ),
.cfg_upd_in (cart_cfg_upd ),
.prg_nce_in (cart_prg_nce ),
.prg_a_in (cpumc_a[14:0] ),
.prg_r_nw_in (cpumc_r_nw ),
.prg_d_in (cpumc_din ),
.prg_d_out (cart_prg_dout ),
.chr_a_in (ppumc_a ),
.chr_r_nw_in (~ppumc_wr ),
.chr_d_in (ppumc_din ),
.chr_d_out (cart_chr_dout ),
.ciram_nce_out (cart_ciram_nce ),
.ciram_a10_out (cart_ciram_a10 )
);
assign cart_prg_nce = ~cpumc_a[15];
//
// WRAM: internal work ram
//
wire wram_en;
wire [7:0] wram_dout;
wram wram_blk(
.clk_in (clk ),
.en_in (wram_en ),
.r_nw_in (cpumc_r_nw ),
.a_in (cpumc_a[10:0] ),
.d_in (cpumc_din ),
.d_out (wram_dout )
);
assign wram_en = (cpumc_a[15:13] == 0);
//
// VRAM: internal video ram
//
wire [10:0] vram_a;
wire [ 7:0] vram_dout;
vram vram_blk(
.clk_in (clk ),
.en_in (~cart_ciram_nce ),
.r_nw_in (~ppumc_wr ),
.a_in (vram_a ),
.d_in (ppumc_din ),
.d_out (vram_dout )
);
//
// PPU: picture processing unit block.
//
wire [ 2:0] ppu_ri_sel; // ppu register interface reg select
wire ppu_ri_ncs; // ppu register interface enable
wire ppu_ri_r_nw; // ppu register interface read/write select
wire [ 7:0] ppu_ri_din; // ppu register interface data input
wire [ 7:0] ppu_ri_dout; // ppu register interface data output
wire [13:0] ppu_vram_a; // ppu video ram address bus
wire ppu_vram_wr; // ppu video ram read/write select
wire [ 7:0] ppu_vram_din; // ppu video ram data bus (input)
wire [ 7:0] ppu_vram_dout; // ppu video ram data bus (output)
wire ppu_nvbl; // ppu /VBL signal.
// PPU snoops the CPU address bus for register reads/writes. Addresses 0x2000-0x2007
// are mapped to the PPU register space, with every 8 bytes mirrored through 0x3FFF.
assign ppu_ri_sel = cpumc_a[2:0];
assign ppu_ri_ncs = (cpumc_a[15:13] == 3'b001) ? 1'b0 : 1'b1;
assign ppu_ri_r_nw = cpumc_r_nw;
assign ppu_ri_din = cpumc_din;
ppu ppu_blk(
.clk_in (clk ),
.rst_in (rst ),
.ri_sel_in (ppu_ri_sel ),
.ri_ncs_in (ppu_ri_ncs ),
.ri_r_nw_in (ppu_ri_r_nw ),
.ri_d_in (ppu_ri_din ),
//VGA
.o_image_width (o_image_width), // width of the generated image
.o_image_height (o_image_height),// height of the generated image
.vram_d_in (ppu_vram_din ),
.hsync_out (o_hsync ),
.vsync_out (o_vsync ),
.r_out (o_red ),
.g_out (o_green ),
.b_out (o_blue ),
//VRAM
.ri_d_out (ppu_ri_dout ),
.nvbl_out (ppu_nvbl ),
.vram_a_out (ppu_vram_a ),
.vram_d_out (ppu_vram_dout ),
.vram_wr_out (ppu_vram_wr )
);
assign vram_a = { cart_ciram_a10, ppumc_a[9:0] };
//
// HCI: host communication interface block. Interacts with NesDbg software through serial port.
//
wire hci_active;
wire [ 7:0] hci_cpu_din;
wire [ 7:0] hci_cpu_dout;
wire [15:0] hci_cpu_a;
wire hci_cpu_r_nw;
wire [ 7:0] hci_ppu_vram_din;
wire [ 7:0] hci_ppu_vram_dout;
wire [15:0] hci_ppu_vram_a;
wire hci_ppu_vram_wr;
nes_hci hci_blk(
.clk (clk ),
.rst (rst ),
//Host Interface
.i_reset_sm (i_hci_reset ),
.i_opcode (i_hci_opcode ),
.i_opcode_strobe (i_hci_opcode_strobe ),
.o_opcode_status (o_hci_opcode_status ),
.o_opcode_ack (o_hci_opcode_ack ),
.i_address (i_hci_address ),
.i_count (i_hci_count ),
.i_data_strobe (i_hci_data_strobe ),
.o_hci_ready (o_hci_sm_ready ),
.i_data (i_hci_data ),
.o_data_strobe (o_hci_data_strobe ),
.i_host_ready (i_hci_host_ready ),
.o_data (o_hci_data ),
//NES Interface
.i_cpu_break (rp2a03_brk ),
.o_cpu_r_nw (hci_cpu_r_nw ), //CPU Read/!Write Pin
.o_cpu_address (hci_cpu_a ),
.i_cpu_din (hci_cpu_din ),
.o_cpu_dout (hci_cpu_dout ),
.o_dbg_active (hci_active ),
.o_cpu_dbg_reg_wr (rp2a03_dbgreg_wr ),
.o_cpu_dbg_reg_sel (rp2a03_dbgreg_sel ),
.i_cpu_dbg_reg_din (rp2a03_dbgreg_dout ),
.o_cpu_dbg_reg_dout (rp2a03_dbgreg_din ),
.o_ppu_vram_wr (hci_ppu_vram_wr ),
.o_ppu_vram_address (hci_ppu_vram_a ),
.i_ppu_vram_din (hci_ppu_vram_din ),
.o_ppu_vram_dout (hci_ppu_vram_dout ),
.o_cart_cfg (cart_cfg ),
.o_cart_cfg_update (cart_cfg_upd )
);
/*
Moved this hear for testing
wire [7:0] jp_dout;
jp jp_blk(
.clk (clk ),
.rst (rst ),
.i_wr (~cpumc_r_nw ),
.i_addr (cpumc_a ),
.i_din (cpumc_din[0] ),
.o_dout (jp_dout ),
.i_jp1_state (i_jp1_state ),
.i_jp2_state (i_jp2_state )
);
*/
/*
hci hci_blk(
.clk (clk ),
.rst (rst ),
.rx (RXD ),
.tx (TXD ),
.active (hci_active ),
.cpu_din (hci_cpu_din ),
.cpu_r_nw (hci_cpu_r_nw ),
.cpu_a (hci_cpu_a ),
.cpu_dout (hci_cpu_dout ),
.brk (rp2a03_brk ),
.cpu_dbgreg_sel (rp2a03_dbgreg_sel ),
.cpu_dbgreg_out (rp2a03_dbgreg_din ),
.cpu_dbgreg_wr (rp2a03_dbgreg_wr ),
.cpu_dbgreg_in (rp2a03_dbgreg_dout ),
.ppu_vram_din (hci_ppu_vram_din ),
.ppu_vram_wr (hci_ppu_vram_wr ),
.ppu_vram_a (hci_ppu_vram_a ),
.ppu_vram_dout (hci_ppu_vram_dout ),
.cart_cfg (cart_cfg ),
.cart_cfg_upd (cart_cfg_upd )
);
*/
// Mux cpumc signals from rp2a03 or hci blk, depending on debug break state (hci_active).
assign rp2a03_rdy = (hci_active) ? 1'b0 : 1'b1;
assign cpumc_a = (hci_active) ? hci_cpu_a : rp2a03_a;
assign cpumc_r_nw = (hci_active) ? hci_cpu_r_nw : rp2a03_r_nw;
assign cpumc_din = (hci_active) ? hci_cpu_dout : rp2a03_dout;
assign rp2a03_din = cart_prg_dout | wram_dout | ppu_ri_dout;
assign hci_cpu_din = cart_prg_dout | wram_dout | ppu_ri_dout;
// Mux ppumc signals from ppu or hci blk, depending on debug break state (hci_active).
assign ppumc_a = (hci_active) ? hci_ppu_vram_a[13:0] : ppu_vram_a;
assign ppumc_wr = (hci_active) ? hci_ppu_vram_wr : ppu_vram_wr;
assign ppumc_din = (hci_active) ? hci_ppu_vram_dout : ppu_vram_dout;
assign ppu_vram_din = cart_chr_dout | vram_dout;
assign hci_ppu_vram_din = cart_chr_dout | vram_dout;
// Issue NMI interupt on PPU vertical blank.
assign rp2a03_nnmi = ppu_nvbl;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_out_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// FPU output datapath.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_out_dp (
dest_rdy,
req_thread,
div_exc_out,
d8stg_fdivd,
d8stg_fdivs,
div_sign_out,
div_exp_out,
div_frac_out,
mul_exc_out,
m6stg_fmul_dbl_dst,
m6stg_fmuls,
mul_sign_out,
mul_exp_out,
mul_frac_out,
add_exc_out,
a6stg_fcmpop,
add_cc_out,
add_fcc_out,
a6stg_dbl_dst,
a6stg_sng_dst,
a6stg_long_dst,
a6stg_int_dst,
add_sign_out,
add_exp_out,
add_frac_out,
rclk,
fp_cpx_data_ca,
se,
si,
so
);
input [2:0] dest_rdy; // pipe with result request this cycle
input [1:0] req_thread; // thread ID of result req this cycle
input [4:0] div_exc_out; // divide pipe result- exception flags
input d8stg_fdivd; // divide double- divide stage 8
input d8stg_fdivs; // divide single- divide stage 8
input div_sign_out; // divide sign output
input [10:0] div_exp_out; // divide exponent output
input [51:0] div_frac_out; // divide fraction output
input [4:0] mul_exc_out; // multiply pipe result- exception flags
input m6stg_fmul_dbl_dst; // double precision multiply result
input m6stg_fmuls; // fmuls- multiply 6 stage
input mul_sign_out; // multiply sign output
input [10:0] mul_exp_out; // multiply exponent output
input [51:0] mul_frac_out; // multiply fraction output
input [4:0] add_exc_out; // add pipe result- exception flags
input a6stg_fcmpop; // compare- add 6 stage
input [1:0] add_cc_out; // add pipe result- condition
input [1:0] add_fcc_out; // add pipe input fcc passed through
input a6stg_dbl_dst; // float double result- add 6 stage
input a6stg_sng_dst; // float single result- add 6 stage
input a6stg_long_dst; // 64bit integer result- add 6 stage
input a6stg_int_dst; // 32bit integer result- add 6 stage
input add_sign_out; // add sign output
input [10:0] add_exp_out; // add exponent output
input [63:0] add_frac_out; // add fraction output
input rclk; // global clock
output [144:0] fp_cpx_data_ca; // FPU result to CPX
input se; // scan_enable
input si; // scan in
output so; // scan out
wire [63:0] add_out;
wire [63:0] mul_out;
wire [63:0] div_out;
wire [7:0] fp_cpx_data_ca_84_77_in;
wire [76:0] fp_cpx_data_ca_76_0_in;
wire [7:0] fp_cpx_data_ca_84_77;
wire [76:0] fp_cpx_data_ca_76_0;
wire [144:0] fp_cpx_data_ca;
wire se_l;
assign se_l = ~se;
clken_buf ckbuf_out_dp (
.clk(clk),
.rclk(rclk),
.enb_l(1'b0),
.tmb_l(se_l)
);
///////////////////////////////////////////////////////////////////////////////
//
// Add pipe output.
//
///////////////////////////////////////////////////////////////////////////////
assign add_out[63:0]= ({64{a6stg_dbl_dst}}
& {add_sign_out, add_exp_out[10:0],
add_frac_out[62:11]})
| ({64{a6stg_sng_dst}}
& {add_sign_out, add_exp_out[7:0],
add_frac_out[62:40], 32'b0})
| ({64{a6stg_long_dst}}
& add_frac_out[63:0])
| ({64{a6stg_int_dst}}
& {add_frac_out[63:32], 32'b0});
///////////////////////////////////////////////////////////////////////////////
//
// Multiply output.
//
///////////////////////////////////////////////////////////////////////////////
assign mul_out[63:0]= ({64{m6stg_fmul_dbl_dst}}
& {mul_sign_out, mul_exp_out[10:0],
mul_frac_out[51:0]})
| ({64{m6stg_fmuls}}
& {mul_sign_out, mul_exp_out[7:0],
mul_frac_out[51:29], 32'b0});
///////////////////////////////////////////////////////////////////////////////
//
// Divide output.
//
///////////////////////////////////////////////////////////////////////////////
assign div_out[63:0]= ({64{d8stg_fdivd}}
& {div_sign_out, div_exp_out[10:0],
div_frac_out[51:0]})
| ({64{d8stg_fdivs}}
& {div_sign_out, div_exp_out[7:0],
div_frac_out[51:29], 32'b0});
///////////////////////////////////////////////////////////////////////////////
//
// Choose the output data.
//
// Input to the CPX data (CA) stage.
//
///////////////////////////////////////////////////////////////////////////////
assign fp_cpx_data_ca_84_77_in[7:0]= ({8{(|dest_rdy)}}
& {1'b1, 4'b1000, 1'b0, req_thread[1:0]});
assign fp_cpx_data_ca_76_0_in[76:0]= ({77{dest_rdy[2]}}
& {div_exc_out[4:0], 8'b0, div_out[63:0]})
| ({77{dest_rdy[1]}}
& {mul_exc_out[4:0], 8'b0, mul_out[63:0]})
| ({77{dest_rdy[0]}}
& {add_exc_out[4:0], 2'b0, a6stg_fcmpop,
add_cc_out[1:0], add_fcc_out[1:0], 1'b0,
add_out[63:0]});
dff_s #(8) i_fp_cpx_data_ca_84_77 (
.din (fp_cpx_data_ca_84_77_in[7:0]),
.clk (clk),
.q (fp_cpx_data_ca_84_77[7:0]),
.se (se),
.si (),
.so ()
);
dff_s #(77) i_fp_cpx_data_ca_76_0 (
.din (fp_cpx_data_ca_76_0_in[76:0]),
.clk (clk),
.q (fp_cpx_data_ca_76_0[76:0]),
.se (se),
.si (),
.so ()
);
assign fp_cpx_data_ca[144:0]= {fp_cpx_data_ca_84_77[7:3],
3'b0,
fp_cpx_data_ca_84_77[2:0],
57'b0,
fp_cpx_data_ca_76_0[76:0]};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_FUNCTIONAL_V
`define SKY130_FD_SC_HS__OR3B_FUNCTIONAL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or3b (
VPWR,
VGND,
X ,
A ,
B ,
C_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C_N ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_FUNCTIONAL_V |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign led = led_reg;
assign phy_reset_n = !rst;
assign uart_txd = 0;
assign uart_rts = 0;
eth_mac_1g_gmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rx_clk(phy_rx_clk),
.gmii_rxd(phy_rxd),
.gmii_rx_dv(phy_rx_dv),
.gmii_rx_er(phy_rx_er),
.gmii_tx_clk(phy_gtx_clk),
.mii_tx_clk(phy_tx_clk),
.gmii_txd(phy_txd),
.gmii_tx_en(phy_tx_en),
.gmii_tx_er(phy_tx_er),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// A one bit data synchronization module, where data is synchronized
// by passing through 2 registers of the destination clock
module SyncBit (
sCLK,
sRST_N,
dCLK,
sEN,
sD_IN,
dD_OUT
);
parameter init = 1'b0; // initial value for all registers
// Signals on source clock (sCLK)
input sCLK;
input sRST_N;
input sEN;
input sD_IN;
// Signals on destination clock (dCLK)
input dCLK;
output dD_OUT;
reg sSyncReg;
reg dSyncReg1, dSyncReg2;
assign dD_OUT = dSyncReg2 ;
always @(posedge sCLK or negedge sRST_N)
begin
if (sRST_N ==0)
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST_N ==0)
else
begin
if ( sEN )
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY (sD_IN == 1'b1) ? 1'b1 : 1'b0 ;
end // if ( sEN )
end // else: !if(sRST_N ==0)
end // always @ (posedge sCLK or negedge sRST_N)
always @(posedge dCLK or negedge sRST_N)
begin
if (sRST_N ==0)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init ;
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init ;
end // if (sRST_N ==0)
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sSyncReg ; // clock domain crossing
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
end // else: !if(sRST_N ==0)
end // always @ (posedge dCLK or negedge sRST_N)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
sSyncReg = init ;
dSyncReg1 = init ;
dSyncReg2 = init ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // BitSync
|
/**
* bsg_cache_non_blocking.v
*
* Non-blocking cache.
*
* @author tommy
*
* For design doc, follow this link.
* https://docs.google.com/document/d/1hf4WgCuf4CGjPMZXH5AplK7k9wtcAN2uw2moZhroryU/edit
*/
`include "bsg_defines.v"
module bsg_cache_non_blocking
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(ways_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(miss_fifo_els_p)
, parameter cache_pkt_width_lp=`bsg_cache_non_blocking_pkt_width(id_width_p,addr_width_p,data_width_p)
, parameter dma_pkt_width_lp=`bsg_cache_non_blocking_dma_pkt_width(addr_width_p)
)
(
input clk_i
, input reset_i
, input v_i
, input [cache_pkt_width_lp-1:0] cache_pkt_i
, output logic ready_o
, output logic v_o
, output logic [id_width_p-1:0] id_o
, output logic [data_width_p-1:0] data_o
, input yumi_i
, output logic [dma_pkt_width_lp-1:0] dma_pkt_o
, output logic dma_pkt_v_o
, input dma_pkt_yumi_i
, input [data_width_p-1:0] dma_data_i
, input dma_data_v_i
, output logic dma_data_ready_o
, output logic [data_width_p-1:0] dma_data_o
, output logic dma_data_v_o
, input dma_data_yumi_i
);
// localparam
//
localparam lg_ways_lp = `BSG_SAFE_CLOG2(ways_p);
localparam lg_sets_lp = `BSG_SAFE_CLOG2(sets_p);
localparam lg_block_size_in_words_lp = `BSG_SAFE_CLOG2(block_size_in_words_p);
localparam byte_sel_width_lp = `BSG_SAFE_CLOG2(data_width_p>>3);
localparam tag_width_lp = (addr_width_p-lg_sets_lp-lg_block_size_in_words_lp-byte_sel_width_lp);
// declare structs
//
`declare_bsg_cache_non_blocking_data_mem_pkt_s(ways_p,sets_p,block_size_in_words_p,data_width_p);
`declare_bsg_cache_non_blocking_stat_mem_pkt_s(ways_p,sets_p);
`declare_bsg_cache_non_blocking_tag_mem_pkt_s(ways_p,sets_p,data_width_p,tag_width_lp);
`declare_bsg_cache_non_blocking_miss_fifo_entry_s(id_width_p,addr_width_p,data_width_p);
`declare_bsg_cache_non_blocking_dma_cmd_s(ways_p,sets_p,tag_width_lp);
// stall signal
// When the pipeline is stalled, DMA can still operate, and move data in and
// output of data_mem. TL stage is not able to access data_mem, but it can
// still enqueue missed requests into miss_fifo. MHU cannot dequeue or invalidate
// an entry from miss FIFO.
wire stall = v_o & ~yumi_i;
// cache pkt
//
`declare_bsg_cache_non_blocking_pkt_s(id_width_p,addr_width_p,data_width_p);
bsg_cache_non_blocking_pkt_s cache_pkt;
assign cache_pkt = cache_pkt_i;
// decode
//
bsg_cache_non_blocking_decode_s decode;
bsg_cache_non_blocking_decode decode0 (
.opcode_i(cache_pkt.opcode)
,.decode_o(decode)
);
// TL stage
//
bsg_cache_non_blocking_data_mem_pkt_s tl_data_mem_pkt_lo;
logic tl_data_mem_pkt_v_lo;
logic tl_data_mem_pkt_ready_li;
logic tl_block_loading;
bsg_cache_non_blocking_stat_mem_pkt_s tl_stat_mem_pkt_lo;
logic tl_stat_mem_pkt_v_lo;
logic tl_stat_mem_pkt_ready_li;
bsg_cache_non_blocking_miss_fifo_entry_s tl_miss_fifo_entry_lo;
logic tl_miss_fifo_v_lo;
logic tl_miss_fifo_ready_li;
logic mgmt_v_lo;
logic [ways_p-1:0] valid_tl_lo;
logic [ways_p-1:0] lock_tl_lo;
logic [ways_p-1:0][tag_width_lp-1:0] tag_tl_lo;
bsg_cache_non_blocking_decode_s decode_tl_lo;
logic [addr_width_p-1:0] addr_tl_lo;
logic [id_width_p-1:0] id_tl_lo;
logic [data_width_p-1:0] data_tl_lo;
logic [lg_ways_lp-1:0] tag_hit_way_lo;
logic tag_hit_found_lo;
logic mgmt_yumi_li;
bsg_cache_non_blocking_tag_mem_pkt_s mhu_tag_mem_pkt_lo;
logic mhu_tag_mem_pkt_v_lo;
logic mhu_idle;
logic mhu_recover;
logic [lg_ways_lp-1:0] curr_mhu_way_id;
logic [lg_sets_lp-1:0] curr_mhu_index;
logic curr_mhu_v;
logic [lg_ways_lp-1:0] curr_dma_way_id;
logic [lg_sets_lp-1:0] curr_dma_index;
logic curr_dma_v;
bsg_cache_non_blocking_tl_stage #(
.id_width_p(id_width_p)
,.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.ways_p(ways_p)
,.sets_p(sets_p)
,.block_size_in_words_p(block_size_in_words_p)
) tl0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.id_i(cache_pkt.id)
,.addr_i(cache_pkt.addr)
,.data_i(cache_pkt.data)
,.mask_i(cache_pkt.mask)
,.decode_i(decode)
,.ready_o(ready_o)
,.data_mem_pkt_v_o(tl_data_mem_pkt_v_lo)
,.data_mem_pkt_o(tl_data_mem_pkt_lo)
,.data_mem_pkt_ready_i(tl_data_mem_pkt_ready_li)
,.block_loading_o(tl_block_loading)
,.stat_mem_pkt_v_o(tl_stat_mem_pkt_v_lo)
,.stat_mem_pkt_o(tl_stat_mem_pkt_lo)
,.stat_mem_pkt_ready_i(tl_stat_mem_pkt_ready_li)
,.miss_fifo_v_o(tl_miss_fifo_v_lo)
,.miss_fifo_entry_o(tl_miss_fifo_entry_lo)
,.miss_fifo_ready_i(tl_miss_fifo_ready_li)
,.mgmt_v_o(mgmt_v_lo)
,.valid_tl_o(valid_tl_lo)
,.lock_tl_o(lock_tl_lo)
,.tag_tl_o(tag_tl_lo)
,.decode_tl_o(decode_tl_lo)
,.addr_tl_o(addr_tl_lo)
,.id_tl_o(id_tl_lo)
,.data_tl_o(data_tl_lo)
,.tag_hit_way_o(tag_hit_way_lo)
,.tag_hit_found_o(tag_hit_found_lo)
,.mgmt_yumi_i(mgmt_yumi_li)
,.mhu_tag_mem_pkt_v_i(mhu_tag_mem_pkt_v_lo)
,.mhu_tag_mem_pkt_i(mhu_tag_mem_pkt_lo)
,.mhu_idle_i(mhu_idle)
,.recover_i(mhu_recover)
,.curr_dma_way_id_i(curr_dma_way_id)
,.curr_dma_index_i(curr_dma_index)
,.curr_dma_v_i(curr_dma_v)
,.curr_mhu_way_id_i(curr_mhu_way_id)
,.curr_mhu_index_i(curr_mhu_index)
,.curr_mhu_v_i(curr_mhu_v)
);
// miss FIFO
//
bsg_cache_non_blocking_miss_fifo_entry_s miss_fifo_data_li;
logic miss_fifo_v_li;
logic miss_fifo_ready_lo;
bsg_cache_non_blocking_miss_fifo_entry_s miss_fifo_data_lo;
logic miss_fifo_v_lo;
logic miss_fifo_yumi_li;
logic miss_fifo_scan_not_dq_li;
bsg_cache_non_blocking_miss_fifo_op_e miss_fifo_yumi_op_li;
logic miss_fifo_rollback_li;
logic miss_fifo_empty_lo;
bsg_cache_non_blocking_miss_fifo #(
.width_p($bits(bsg_cache_non_blocking_miss_fifo_entry_s))
,.els_p(miss_fifo_els_p)
) miss_fifo0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(miss_fifo_v_li)
,.data_i(miss_fifo_data_li)
,.ready_o(miss_fifo_ready_lo)
,.v_o(miss_fifo_v_lo)
,.data_o(miss_fifo_data_lo)
,.yumi_i(miss_fifo_yumi_li)
,.yumi_op_i(miss_fifo_yumi_op_li)
,.scan_not_dq_i(miss_fifo_scan_not_dq_li)
,.rollback_i(miss_fifo_rollback_li)
,.empty_o(miss_fifo_empty_lo)
);
assign miss_fifo_v_li = tl_miss_fifo_v_lo;
assign miss_fifo_data_li = tl_miss_fifo_entry_lo;
assign tl_miss_fifo_ready_li = miss_fifo_ready_lo;
// data_mem
//
bsg_cache_non_blocking_data_mem_pkt_s data_mem_pkt_li;
logic data_mem_v_li;
logic [data_width_p-1:0] data_mem_data_lo;
bsg_cache_non_blocking_data_mem #(
.data_width_p(data_width_p)
,.ways_p(ways_p)
,.sets_p(sets_p)
,.block_size_in_words_p(block_size_in_words_p)
) data_mem0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(data_mem_v_li)
,.data_mem_pkt_i(data_mem_pkt_li)
,.data_o(data_mem_data_lo)
);
// DMA read data buffer
// When the DMA engine reads the data_mem for eviction, the output
// is buffered here, in case dma_data_o is stalled.
logic dma_read_en;
logic dma_read_en_r;
logic [data_width_p-1:0] dma_read_data_r;
bsg_dff_reset #(
.width_p(1)
) dma_read_en_dff (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(dma_read_en)
,.data_o(dma_read_en_r)
);
bsg_dff_en_bypass #(
.width_p(data_width_p)
) dma_read_buffer (
.clk_i(clk_i)
,.en_i(dma_read_en_r)
,.data_i(data_mem_data_lo)
,.data_o(dma_read_data_r)
);
// Load data buffer
// When the TL stage or MHU does load, the output is buffered here.
logic load_read_en;
logic load_read_en_r;
logic [data_width_p-1:0] load_read_data_r;
bsg_dff_reset #(
.width_p(1)
) load_read_en_eff (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(load_read_en)
,.data_o(load_read_en_r)
);
bsg_dff_en_bypass #(
.width_p(data_width_p)
) load_read_buffer (
.clk_i(clk_i)
,.en_i(load_read_en_r)
,.data_i(data_mem_data_lo)
,.data_o(load_read_data_r)
);
// stat_mem
//
bsg_cache_non_blocking_stat_mem_pkt_s stat_mem_pkt_li;
logic stat_mem_v_li;
logic [ways_p-1:0] dirty_lo;
logic [ways_p-2:0] lru_bits_lo;
bsg_cache_non_blocking_stat_mem #(
.ways_p(ways_p)
,.sets_p(sets_p)
) stat_mem0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(stat_mem_v_li)
,.stat_mem_pkt_i(stat_mem_pkt_li)
,.dirty_o(dirty_lo)
,.lru_bits_o(lru_bits_lo)
);
// MHU
//
bsg_cache_non_blocking_data_mem_pkt_s mhu_data_mem_pkt_lo;
logic [id_width_p-1:0] mhu_data_mem_pkt_id_lo;
logic mhu_data_mem_pkt_v_lo;
logic mhu_data_mem_pkt_yumi_li;
bsg_cache_non_blocking_stat_mem_pkt_s mhu_stat_mem_pkt_lo;
logic mhu_stat_mem_pkt_v_lo;
bsg_cache_non_blocking_dma_cmd_s dma_cmd_lo;
logic dma_cmd_v_lo;
bsg_cache_non_blocking_dma_cmd_s dma_cmd_return_li;
logic dma_done_li;
logic dma_pending_li;
logic dma_ack_lo;
logic mgmt_data_v_lo;
logic [data_width_p-1:0] mgmt_data_lo;
logic [id_width_p-1:0] mgmt_id_lo;
logic mgmt_data_yumi_li;
bsg_cache_non_blocking_mhu #(
.id_width_p(id_width_p)
,.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.ways_p(ways_p)
,.sets_p(sets_p)
,.block_size_in_words_p(block_size_in_words_p)
) mhu0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.mgmt_v_i(mgmt_v_lo)
,.mgmt_yumi_o(mgmt_yumi_li)
,.mgmt_data_v_o(mgmt_data_v_lo)
,.mgmt_data_o(mgmt_data_lo)
,.mgmt_id_o(mgmt_id_lo)
,.mgmt_data_yumi_i(mgmt_data_yumi_li)
,.decode_tl_i(decode_tl_lo)
,.addr_tl_i(addr_tl_lo)
,.id_tl_i(id_tl_lo)
,.idle_o(mhu_idle)
,.recover_o(mhu_recover)
,.tl_block_loading_i(tl_block_loading)
,.data_mem_pkt_v_o(mhu_data_mem_pkt_v_lo)
,.data_mem_pkt_o(mhu_data_mem_pkt_lo)
,.data_mem_pkt_yumi_i(mhu_data_mem_pkt_yumi_li)
,.data_mem_pkt_id_o(mhu_data_mem_pkt_id_lo)
,.stat_mem_pkt_v_o(mhu_stat_mem_pkt_v_lo)
,.stat_mem_pkt_o(mhu_stat_mem_pkt_lo)
,.dirty_i(dirty_lo)
,.lru_bits_i(lru_bits_lo)
,.tag_mem_pkt_v_o(mhu_tag_mem_pkt_v_lo)
,.tag_mem_pkt_o(mhu_tag_mem_pkt_lo)
,.valid_tl_i(valid_tl_lo)
,.lock_tl_i(lock_tl_lo)
,.tag_tl_i(tag_tl_lo)
,.tag_hit_way_i(tag_hit_way_lo)
,.tag_hit_found_i(tag_hit_found_lo)
,.curr_mhu_way_id_o(curr_mhu_way_id)
,.curr_mhu_index_o(curr_mhu_index)
,.curr_mhu_v_o(curr_mhu_v)
,.miss_fifo_v_i(miss_fifo_v_lo)
,.miss_fifo_entry_i(miss_fifo_data_lo)
,.miss_fifo_yumi_o(miss_fifo_yumi_li)
,.miss_fifo_yumi_op_o(miss_fifo_yumi_op_li)
,.miss_fifo_scan_not_dq_o(miss_fifo_scan_not_dq_li)
,.miss_fifo_rollback_o(miss_fifo_rollback_li)
,.miss_fifo_empty_i(miss_fifo_empty_lo)
,.dma_cmd_o(dma_cmd_lo)
,.dma_cmd_v_o(dma_cmd_v_lo)
,.dma_cmd_return_i(dma_cmd_return_li)
,.dma_done_i(dma_done_li)
,.dma_pending_i(dma_pending_li)
,.dma_ack_o(dma_ack_lo)
);
// DMA engine
//
logic dma_data_mem_pkt_v_lo;
bsg_cache_non_blocking_data_mem_pkt_s dma_data_mem_pkt_lo;
bsg_cache_non_blocking_dma #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
) dma0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.dma_cmd_i(dma_cmd_lo)
,.dma_cmd_v_i(dma_cmd_v_lo)
,.dma_cmd_return_o(dma_cmd_return_li)
,.done_o(dma_done_li)
,.pending_o(dma_pending_li)
,.ack_i(dma_ack_lo)
,.curr_dma_way_id_o(curr_dma_way_id)
,.curr_dma_index_o(curr_dma_index)
,.curr_dma_v_o(curr_dma_v)
,.data_mem_pkt_v_o(dma_data_mem_pkt_v_lo)
,.data_mem_pkt_o(dma_data_mem_pkt_lo)
,.data_mem_data_i(dma_read_data_r)
,.dma_pkt_o(dma_pkt_o)
,.dma_pkt_v_o(dma_pkt_v_o)
,.dma_pkt_yumi_i(dma_pkt_yumi_i)
,.dma_data_i(dma_data_i)
,.dma_data_v_i(dma_data_v_i)
,.dma_data_ready_o(dma_data_ready_o)
,.dma_data_o(dma_data_o)
,.dma_data_v_o(dma_data_v_o)
,.dma_data_yumi_i(dma_data_yumi_i)
);
/// ///
/// CTRL LOGIC ///
/// ///
// data_mem ctrl logic
//
// Access priority in descending order.
// 1) DMA engine
// 2) MHU
// 3) TL stage (hit). When neither DMA nor MHU is accessing the data_mem,
// ready signal to TL stage goes high.
always_comb begin
data_mem_v_li = 1'b0;
data_mem_pkt_li = dma_data_mem_pkt_lo;
mhu_data_mem_pkt_yumi_li = 1'b0;
tl_data_mem_pkt_ready_li = 1'b0;
dma_read_en = 1'b0;
load_read_en = 1'b0;
if (dma_data_mem_pkt_v_lo) begin
data_mem_pkt_li = dma_data_mem_pkt_lo;
data_mem_v_li = 1'b1;
dma_read_en = ~dma_data_mem_pkt_lo.write_not_read;
end
else if (mhu_data_mem_pkt_v_lo) begin
data_mem_pkt_li = mhu_data_mem_pkt_lo;
data_mem_v_li = ~stall;
mhu_data_mem_pkt_yumi_li = ~stall;
load_read_en = ~mhu_data_mem_pkt_lo.write_not_read & ~stall;
end
else begin
data_mem_pkt_li = tl_data_mem_pkt_lo;
data_mem_v_li = tl_data_mem_pkt_v_lo & ~stall;
tl_data_mem_pkt_ready_li = ~stall;
load_read_en = ~tl_data_mem_pkt_lo.write_not_read & tl_data_mem_pkt_v_lo & ~stall;
end
end
// stat_mem ctrl logic
//
// MHU has higher priority over TL stage.
// MHU accesses tag_mem and stat_mem together.
always_comb begin
stat_mem_v_li = 1'b0;
stat_mem_pkt_li = mhu_stat_mem_pkt_lo;
tl_stat_mem_pkt_ready_li = 1'b0;
if (mhu_stat_mem_pkt_v_lo) begin
stat_mem_v_li = 1'b1;
stat_mem_pkt_li = mhu_stat_mem_pkt_lo;
end
else begin
tl_stat_mem_pkt_ready_li = ~stall;
stat_mem_pkt_li = tl_stat_mem_pkt_lo;
stat_mem_v_li = tl_stat_mem_pkt_v_lo & ~stall;
end
end
// Output Logic
//
// Output valid signal lasts for only one cycle. The consumer needs to be
// ready to accept the data whenever it becomes ready.
// When the pipeline is stalled, these register values stay the same.
// But the pipeline can only stall, when the output is valid.
logic [data_width_p-1:0] mgmt_data_r, mgmt_data_n;
logic [id_width_p-1:0] out_id_r, out_id_n;
logic mgmt_data_v_r, mgmt_data_v_n;
logic store_v_r, store_v_n;
logic load_v_r, load_v_n;
always_comb begin
if (stall) begin
out_id_n = out_id_r;
mgmt_data_n = mgmt_data_r;
store_v_n = store_v_r;
load_v_n = load_v_r;
mgmt_data_v_n = mgmt_data_v_r;
mgmt_data_yumi_li = 1'b0;
end
else begin
out_id_n = out_id_r;
mgmt_data_n = mgmt_data_r;
store_v_n = 1'b0;
load_v_n = 1'b0;
mgmt_data_v_n = 1'b0;
mgmt_data_yumi_li = 1'b0;
if (mgmt_data_v_lo) begin
mgmt_data_n = mgmt_data_lo;
out_id_n = mgmt_id_lo;
mgmt_data_v_n = mgmt_data_v_lo;
mgmt_data_yumi_li = mgmt_data_v_lo;
end
else if (mhu_data_mem_pkt_yumi_li) begin
out_id_n = mhu_data_mem_pkt_id_lo;
store_v_n = mhu_data_mem_pkt_lo.write_not_read;
load_v_n = ~mhu_data_mem_pkt_lo.write_not_read;
end
else if (tl_data_mem_pkt_ready_li & tl_data_mem_pkt_v_lo) begin
out_id_n = id_tl_lo;
store_v_n = tl_data_mem_pkt_lo.write_not_read;
load_v_n = ~tl_data_mem_pkt_lo.write_not_read;
end
end
if (mgmt_data_v_r)
data_o = mgmt_data_r;
else if (load_v_r)
data_o = load_read_data_r;
else
data_o = '0;
id_o = out_id_r;
v_o = mgmt_data_v_r | store_v_r | load_v_r;
end
// synopsys sync_set_reset "reset_i"
always_ff @ (posedge clk_i) begin
if (reset_i) begin
mgmt_data_r <= '0;
out_id_r <= '0;
mgmt_data_v_r <= 1'b0;
store_v_r <= 1'b0;
load_v_r <= 1'b0;
end
else begin
mgmt_data_r <= mgmt_data_n;
out_id_r <= out_id_n;
mgmt_data_v_r <= mgmt_data_v_n;
store_v_r <= store_v_n;
load_v_r <= load_v_n;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_non_blocking)
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <[email protected]>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "config.vh"
`include "bch_defs.vh"
/*
* Tradition chien search, for each cycle, check if the
* value of all the sumuations is zero, if so, this location
* is a bit error.
*/
module bch_error_tmec #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter REG_RATIO = BITS > 8 ? 8 : BITS,
parameter PIPELINE_STAGES = 0,
parameter ACCUM = PIPELINE_STAGES > 1 ? `CONFIG_LUT_SZ : 1
) (
input clk,
input start, /* Latch inputs, start calculating */
input [`BCH_SIGMA_SZ(P)-1:0] sigma,
output first, /* First valid output data */
output [BITS-1:0] err
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
/*
* We have to sum all the chien outputs. Split up the outputs and sum
* them into accumulators. For instance, if REGS == 13, and ACCUM == 3
* then we group together the chien outputs into 5 regs, 4 regs, and
* 4 regs. We then sum together those accumulators.
*/
localparam REGS = `BCH_T(P) + 1;
localparam W_A = (REGS + ACCUM - 1) / ACCUM;
localparam W_B = REGS / ACCUM;
localparam ACCUM_A = REGS - W_B * ACCUM;
localparam ACCUM_B = ACCUM - ACCUM_A;
wire [BITS*`BCH_CHIEN_SZ(P)-1:0] chien;
wire [ACCUM*BITS*M-1:0] accum;
wire [ACCUM*BITS*M-1:0] accum_pipelined;
wire [BITS*M-1:0] sum;
wire [BITS*M-1:0] sum_pipelined;
wire [BITS-1:0] err_raw;
wire first_raw;
genvar i, j;
if (`BCH_T(P) == 1)
tmec_does_not_support_sec u_tdnss();
if (PIPELINE_STAGES > 3)
tmec_only_supports_3_pipeline_stages u_tos2ps();
if (ACCUM > REGS)
tmec_accum_must_be_less_than_or_equal_to_regs u_tambltoretr();
if (ACCUM > 1 && PIPELINE_STAGES < 2)
tmec_accum_requires_2_or_more_pipeline_stages u_tar2omps();
bch_chien #(P, BITS, REG_RATIO) u_chien(
.clk(clk),
.start(start),
.sigma(sigma),
.chien(chien),
.first(first_raw)
);
pipeline #(PIPELINE_STAGES) u_out_pipeline (
.clk(clk),
.i(first_raw),
.o(first)
);
for (i = 0; i < BITS; i = i + 1) begin : BITS_BLOCK
for (j = 0; j < ACCUM_A; j = j + 1) begin : ACCUM_A_BLOCK
finite_parallel_adder #(M, W_A) u_adder(
.in(chien[i*`BCH_CHIEN_SZ(P)+j*W_A*M+:W_A*M]),
.out(accum[(i*ACCUM+j)*M+:M])
);
end
for (j = 0; j < ACCUM_B; j = j + 1) begin : ACCUM_B_BLOCK
finite_parallel_adder #(M, W_B) u_adder(
.in(chien[i*`BCH_CHIEN_SZ(P)+(ACCUM_A*W_A+j*W_B)*M+:W_B*M]),
.out(accum[(i*ACCUM+ACCUM_A+j)*M+:M])
);
end
end
pipeline #(PIPELINE_STAGES > 1) u_accum_pipeline [ACCUM*BITS*M-1:0] (clk, accum, accum_pipelined);
finite_parallel_adder #(M, ACCUM) u_adder [BITS-1:0] (accum_pipelined, sum);
pipeline #(PIPELINE_STAGES > 2) u_sum_pipeline [BITS*M-1:0] (clk, sum, sum_pipelined);
zero_cla #(M, PIPELINE_STAGES > 2 ? 1 : ACCUM) u_zero [BITS-1:0] (sum_pipelined, err_raw);
pipeline #(PIPELINE_STAGES > 0) u_err_pipeline1 [BITS-1:0] (
.clk(clk),
.i(err_raw[BITS-1:0]),
.o(err[BITS-1:0])
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: PWr
// Engineer: Kacper Witkowski
//
// Create Date: 20:31:56 05/12/2016
// Design Name: serdes
// Module Name: CRC_test
// Project Name: CRC16
//
// Verilog Test Fixture created by ISE for module: serdes
////////////////////////////////////////////////////////////////////////////////
module CRC_test_fixture;
// Inputs
reg [7:0] we;
reg clk;
reg reset;
// Outputs
wire [7:0] wy;
// Instantiate the Unit Under Test (UUT)
serdes uut (
.we(we),
.clk(clk),
.reset(reset),
.wy(wy)
);
// internal signals
reg [2:0] cnt;
reg [1:0] output_delay1;
reg [1:0] output_delay2;
integer input_file, output_file;
initial begin
// Initialize Inputs
we = 8'b00000000;
clk = 1'b0;
reset = 1'b0;
repeat(2) @(posedge clk)
reset = 1'b1;
//forever #10 clk = ~clk;
end
always #10 clk=~clk;
initial begin
input_file = $fopen("input_data.txt", "r");
output_file = $fopen("output_data.txt", "w");
end
always @(posedge clk or !reset)
begin
if ( !reset )
begin
cnt = 0;
output_delay1 = 0;
output_delay2 = 1;
end
else
cnt = cnt + 1;
if (cnt == 7)
begin
if (output_delay1 < 3)
begin
output_delay1 = output_delay1 + 1;
$fscanf(input_file, "%h\n", we[7:0]);
end
else if ((output_delay1 == 3) && !$feof(input_file))
begin
$fscanf(input_file, "%h\n", we[7:0]);
$fwrite(output_file, "%h\n", wy[7:0]);
end
else if (output_delay2 > 0)
begin
$fwrite(output_file, "%h\n", wy[7:0]);
output_delay2 = output_delay2 - 1;
end
else
begin
$fclose(output_file);
$fclose(input_file);
$finish;
end
end
end
endmodule |
module demo_sound2(
input clock,
output [7:0]key_code,
input k_tr
);
reg [15:0]tmp;
wire [15:0]tmpa;
reg tr;
reg [15:0]step;
wire [15:0]step_r;
reg [7:0]TT;
reg[5:0]st;
reg go_end;
////////Music Processing////////
always @(negedge k_tr or posedge clock) begin
if (!k_tr) begin
step=0;
st=0;
tr=0;
end
else
if (step<step_r) begin
case (st)
0: st=st+1;
1: begin tr=0; st=st+1;end
2: begin tr=1;st=st+1;end
3: if(go_end) st=st+1;
4: begin st=0;step=step+1;end
endcase
end
end
/////////////// pitch //////////////////
wire [7:0]key_code1=(
(TT[3:0]==1)?8'h2b:(//1
(TT[3:0]==2)?8'h34:(//2
(TT[3:0]==3)?8'h33:(//3
(TT[3:0]==4)?8'h3b:(//4
(TT[3:0]==5)?8'h42:(//5
(TT[3:0]==6)?8'h4b:(//6
(TT[3:0]==7)?8'h4c:(//7
(TT[3:0]==8)?8'h4a:(//1
(TT[3:0]==9)?8'h4d:(//2
(TT[3:0]==10)?8'h4e:(//3
(TT[3:0]==11)?8'h4f:(//4
(TT[3:0]==12)?8'h50:(//5
(TT[3:0]==13)?8'h51:(//6
(TT[3:0]==14)?8'h52:(//7
//(TT[3:0]==10)?8'h52:(//1
(TT[3:0]==15)?8'hf0:8'hf0
))))))))))))))
);
/////////////// paddle ///////////////////
assign tmpa[15:0]=(
(TT[7:4]==15)?16'h10:(
(TT[7:4]==8)? 16'h20:(
(TT[7:4]==10)?16'h28:( // waiting 8 - 9
(TT[7:4]==9)? 16'h30:(
(TT[7:4]==1)? 16'h40:(
(TT[7:4]==3)? 16'h60:(
(TT[7:4]==2)? 16'h80:(
(TT[7:4]==11)? 16'hc8:( // waiting 2+
(TT[7:4]==4)? 16'h100:0
))))))))
);
/////////// note list ///////////
always @(step) begin
case (step)
0:TT=8'h85;
1:TT=8'hf6;
2:TT=8'h84;
3:TT=8'hb5;
4:TT=8'h89;
5:TT=8'hf6;
6:TT=8'h84;
7:TT=8'hb5;
8:TT=8'h1f;//end
endcase
end
assign step_r=8;///Total note
/////////////KEY release & code-out ////////////////
always @(negedge tr or posedge clock)begin
if(!tr) begin tmp=0;go_end=0 ;end
else if (tmp>tmpa)go_end=1;
else tmp=tmp+1;
end
assign key_code=(tmp<(tmpa-1))?key_code1:8'hf0;//KEY release//
endmodule
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
//`define VERBOSE
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
wire sd_clk;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
wire phy_sd_cmd;
wire [3:0] phy_sd_data;
wire pll_locked;
wire dev_sd_cmd_dir;
wire dev_sd_cmd_in;
wire dev_sd_cmd_out;
wire dev_sd_data_dir;
wire [7:0] dev_sd_data_in;
wire [7:0] dev_sd_data_out;
// Function Interface From CIA
wire fbr1_csa_en;
wire [3:0] fbr1_pwr_mode;
wire [15:0] fbr1_block_size;
wire fbr2_csa_en;
wire [3:0] fbr2_pwr_mode;
wire [15:0] fbr2_block_size;
wire fbr3_csa_en;
wire [3:0] fbr3_pwr_mode;
wire [15:0] fbr3_block_size;
wire fbr4_csa_en;
wire [3:0] fbr4_pwr_mode;
wire [15:0] fbr4_block_size;
wire fbr5_csa_en;
wire [3:0] fbr5_pwr_mode;
wire [15:0] fbr5_block_size;
wire fbr6_csa_en;
wire [3:0] fbr6_pwr_mode;
wire [15:0] fbr6_block_size;
wire fbr7_csa_en;
wire [3:0] fbr7_pwr_mode;
wire [15:0] fbr7_block_size;
wire [7:0] function_enable;
wire [7:0] function_ready;
wire [2:0] function_abort_stb;
wire [7:0] function_exec_status;
wire [7:0] function_ready_for_data;
wire function_inc_addr;
wire function_bock_mode;
wire func_wr_stb [0:8];
wire [7:0] func_wr_data [0:8];
wire func_rd_stb [0:8];
wire [7:0] func_rd_data [0:8];
wire func_hst_rdy [0:8];
wire func_com_rdy [0:8];
wire func_activate [0:8];
wire [7:0] function_interrupt;
wire func_inc_addr;
wire [3:0] func_num;
wire func_write_flag;
wire func_rd_after_wr;
wire [17:0] func_addr;
wire [12:0] func_data_count;
wire func_block_mode;
wire i_func_num;
wire o_read_wait;
wire o_interrupt;
wire demo_func_ready;
wire demo_func_int_pend;
wire demo_func_busy;
wire demo_func_exec_sts;
//wishbone signals
wire w_wbp_we;
wire w_wbp_cyc;
wire w_wbp_stb;
wire [3:0] w_wbp_sel;
wire [31:0] w_wbp_adr;
wire [31:0] w_wbp_dat_o;
wire [31:0] w_wbp_dat_i;
wire w_wbp_ack;
wire w_wbp_int;
//mem slave 0
wire w_sm0_i_wbs_we;
wire w_sm0_i_wbs_cyc;
wire [31:0] w_sm0_i_wbs_dat;
wire [31:0] w_sm0_o_wbs_dat;
wire [31:0] w_sm0_i_wbs_adr;
wire w_sm0_i_wbs_stb;
wire [3:0] w_sm0_i_wbs_sel;
wire w_sm0_o_wbs_ack;
wire w_sm0_o_wbs_int;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Memory Interface
wire w_mem_we_o;
wire w_mem_cyc_o;
wire w_mem_stb_o;
wire [3:0] w_mem_sel_o;
wire [31:0] w_mem_adr_o;
wire [31:0] w_mem_dat_i;
wire [31:0] w_mem_dat_o;
wire w_mem_ack_i;
wire w_mem_int_i;
wire w_arb0_i_wbs_stb;
wire w_arb0_i_wbs_cyc;
wire w_arb0_i_wbs_we;
wire [3:0] w_arb0_i_wbs_sel;
wire [31:0] w_arb0_i_wbs_dat;
wire [31:0] w_arb0_o_wbs_dat;
wire [31:0] w_arb0_i_wbs_adr;
wire w_arb0_o_wbs_ack;
wire w_arb0_o_wbs_int;
wire mem_o_we;
wire mem_o_stb;
wire mem_o_cyc;
wire [3:0] mem_o_sel;
wire [31:0] mem_o_adr;
wire [31:0] mem_o_dat;
wire [31:0] mem_i_dat;
wire mem_i_ack;
wire mem_i_int;
assign device_interrupt = w_wbm_int;
assign w_wbs0_int = 1'b0;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
wire start;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbp_we ),
.o_per_adr (w_wbp_adr ),
.o_per_dat (w_wbp_dat_i ),
.i_per_dat (w_wbp_dat_o ),
.o_per_stb (w_wbp_stb ),
.o_per_cyc (w_wbp_cyc ),
.o_per_msk (w_wbp_msk ),
.o_per_sel (w_wbp_sel ),
.i_per_ack (w_wbp_ack ),
.i_per_int (w_wbp_int ),
//memory interconnect signals
.o_mem_we (w_mem_we_o ),
.o_mem_adr (w_mem_adr_o ),
.o_mem_dat (w_mem_dat_o ),
.i_mem_dat (w_mem_dat_i ),
.o_mem_stb (w_mem_stb_o ),
.o_mem_cyc (w_mem_cyc_o ),
.o_mem_sel (w_mem_sel_o ),
.i_mem_ack (w_mem_ack_i ),
.i_mem_int (w_mem_int_i )
);
wishbone_mem_interconnect wmi (
.clk (clk ),
.rst (rst ),
//master
.i_m_we (w_mem_we_o ),
.i_m_cyc (w_mem_cyc_o ),
.i_m_stb (w_mem_stb_o ),
.i_m_sel (w_mem_sel_o ),
.o_m_ack (w_mem_ack_i ),
.i_m_dat (w_mem_dat_o ),
.o_m_dat (w_mem_dat_i ),
.i_m_adr (w_mem_adr_o ),
.o_m_int (w_mem_int_i ),
//slave 0
.o_s0_we (w_sm0_i_wbs_we ),
.o_s0_cyc (w_sm0_i_wbs_cyc ),
.o_s0_stb (w_sm0_i_wbs_stb ),
.o_s0_sel (w_sm0_i_wbs_sel ),
.i_s0_ack (w_sm0_o_wbs_ack ),
.o_s0_dat (w_sm0_i_wbs_dat ),
.i_s0_dat (w_sm0_o_wbs_dat ),
.o_s0_adr (w_sm0_i_wbs_adr ),
.i_s0_int (w_sm0_o_wbs_int )
);
//slave 1
wb_sd_host s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_sel (4'b1111 ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int ),
.mem_o_we (mem_o_we ),
.mem_o_stb (mem_o_stb ),
.mem_o_cyc (mem_o_cyc ),
.mem_o_sel (mem_o_sel ),
.mem_o_adr (mem_o_adr ),
.mem_o_dat (mem_o_dat ),
.mem_i_dat (mem_i_dat ),
.mem_i_ack (mem_i_ack ),
.mem_i_int (mem_i_int ),
.o_sd_clk (sd_clk ),
.io_sd_cmd (phy_sd_cmd ),
.io_sd_data (phy_sd_data )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbp_we ),
.i_m_cyc (w_wbp_cyc ),
.i_m_stb (w_wbp_stb ),
.o_m_ack (w_wbp_ack ),
.i_m_dat (w_wbp_dat_i ),
.o_m_dat (w_wbp_dat_o ),
.i_m_adr (w_wbp_adr ),
.o_m_int (w_wbp_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
arbiter_2_masters arb0 (
.clk (clk ),
.rst (rst ),
//masters
.i_m1_we (mem_o_we ),
.i_m1_stb (mem_o_stb ),
.i_m1_cyc (mem_o_cyc ),
.i_m1_sel (mem_o_sel ),
.i_m1_dat (mem_o_dat ),
.i_m1_adr (mem_o_adr ),
.o_m1_dat (mem_i_dat ),
.o_m1_ack (mem_i_ack ),
.o_m1_int (mem_i_int ),
.i_m0_we (w_sm0_i_wbs_we ),
.i_m0_stb (w_sm0_i_wbs_stb ),
.i_m0_cyc (w_sm0_i_wbs_cyc ), //Artificially block
.i_m0_sel (w_sm0_i_wbs_sel ),
.i_m0_dat (w_sm0_i_wbs_dat ),
.i_m0_adr (w_sm0_i_wbs_adr ),
.o_m0_dat (w_sm0_o_wbs_dat ),
.o_m0_ack (w_sm0_o_wbs_ack ),
.o_m0_int (w_sm0_o_wbs_int ),
//slave
.o_s_we (w_arb0_i_wbs_we ),
.o_s_stb (w_arb0_i_wbs_stb ),
.o_s_cyc (w_arb0_i_wbs_cyc ),
.o_s_sel (w_arb0_i_wbs_sel ),
.o_s_dat (w_arb0_i_wbs_dat ),
.o_s_adr (w_arb0_i_wbs_adr ),
.i_s_dat (w_arb0_o_wbs_dat ),
.i_s_ack (w_arb0_o_wbs_ack ),
.i_s_int (w_arb0_o_wbs_int )
);
wb_bram #(
.DATA_WIDTH (32 ),
.ADDR_WIDTH (10 )
)bram(
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_arb0_i_wbs_we ),
.i_wbs_sel (w_arb0_i_wbs_sel ),
.i_wbs_cyc (w_arb0_i_wbs_cyc ),
.i_wbs_dat (w_arb0_i_wbs_dat ),
.i_wbs_stb (w_arb0_i_wbs_stb ),
.i_wbs_adr (w_arb0_i_wbs_adr ),
.o_wbs_dat (w_arb0_o_wbs_dat ),
.o_wbs_ack (w_arb0_o_wbs_ack ),
.o_wbs_int (w_arb0_o_wbs_int )
);
sd_dev_platform_spartan6 #(
.OUTPUT_DELAY (0 ),
.INPUT_DELAY (0 )
)sdio_dev_plat (
.clk (clk ),
.rst (rst ),
.o_locked (pll_locked ),
.o_sd_clk (dev_sd_clk ),
.i_sd_cmd_dir (dev_sd_cmd_dir ),
.o_sd_cmd_in (dev_sd_cmd_in ),
.i_sd_cmd_out (dev_sd_cmd_out ),
.i_sd_data_dir (dev_sd_data_dir ),
.o_sd_data_in (dev_sd_data_in ),
.i_sd_data_out (dev_sd_data_out ),
.i_phy_clk (sd_clk ),
.io_phy_sd_cmd (phy_sd_cmd ),
.io_phy_sd_data (phy_sd_data )
);
pullup (phy_sd_cmd );
pullup (phy_sd_data[0]);
pullup (phy_sd_data[1]);
pullup (phy_sd_data[2]);
pullup (phy_sd_data[3]);
//TODO ADAPT sdio_device to use the platform based phy_sd_cmd and phy_sd_data
sdio_device_stack sdio_device (
.sdio_clk (dev_sd_clk ),
.rst (rst || !pll_locked ),
// Function Interfacee From CIA
.o_fbr1_csa_en (fbr1_csa_en ),
.o_fbr1_pwr_mode (fbr1_pwr_mode ),
.o_fbr1_block_size (fbr1_block_size ),
.o_fbr2_csa_en (fbr2_csa_en ),
.o_fbr2_pwr_mode (fbr2_pwr_mode ),
.o_fbr2_block_size (fbr2_block_size ),
.o_fbr3_csa_en (fbr3_csa_en ),
.o_fbr3_pwr_mode (fbr3_pwr_mode ),
.o_fbr3_block_size (fbr3_block_size ),
.o_fbr4_csa_en (fbr4_csa_en ),
.o_fbr4_pwr_mode (fbr4_pwr_mode ),
.o_fbr4_block_size (fbr4_block_size ),
.o_fbr5_csa_en (fbr5_csa_en ),
.o_fbr5_pwr_mode (fbr5_pwr_mode ),
.o_fbr5_block_size (fbr5_block_size ),
.o_fbr6_csa_en (fbr6_csa_en ),
.o_fbr6_pwr_mode (fbr6_pwr_mode ),
.o_fbr6_block_size (fbr6_block_size ),
.o_fbr7_csa_en (fbr7_csa_en ),
.o_fbr7_pwr_mode (fbr7_pwr_mode ),
.o_fbr7_block_size (fbr7_block_size ),
//Data Interface
//Function 1 Interface
.o_func1_wr_stb (func_wr_stb[1] ),
.o_func1_wr_data (func_wr_data[1] ),
.i_func1_rd_stb (func_rd_stb[1] ),
.i_func1_rd_data (func_rd_data[1] ),
.o_func1_hst_rdy (func_hst_rdy[1] ),
.i_func1_com_rdy (func_com_rdy[1] ),
.o_func1_activate (func_activate[1] ),
//Function 2 Interface
.o_func2_wr_stb (func_wr_stb[2] ),
.o_func2_wr_data (func_wr_data[2] ),
.i_func2_rd_stb (func_rd_stb[2] ),
.i_func2_rd_data (func_rd_data[2] ),
.o_func2_hst_rdy (func_hst_rdy[2] ),
.i_func2_com_rdy (func_com_rdy[2] ),
.o_func2_activate (func_activate[2] ),
//Function 3 Interface
.o_func3_wr_stb (func_wr_stb[3] ),
.o_func3_wr_data (func_wr_data[3] ),
.i_func3_rd_stb (func_rd_stb[3] ),
.i_func3_rd_data (func_rd_data[3] ),
.o_func3_hst_rdy (func_hst_rdy[3] ),
.i_func3_com_rdy (func_com_rdy[3] ),
.o_func3_activate (func_activate[3] ),
//Function 4 Interface
.o_func4_wr_stb (func_wr_stb[4] ),
.o_func4_wr_data (func_wr_data[4] ),
.i_func4_rd_stb (func_rd_stb[4] ),
.i_func4_rd_data (func_rd_data[4] ),
.o_func4_hst_rdy (func_hst_rdy[4] ),
.i_func4_com_rdy (func_com_rdy[4] ),
.o_func4_activate (func_activate[4] ),
//Function 5 Interface
.o_func5_wr_stb (func_wr_stb[5] ),
.o_func5_wr_data (func_wr_data[5] ),
.i_func5_rd_stb (func_rd_stb[5] ),
.i_func5_rd_data (func_rd_data[5] ),
.o_func5_hst_rdy (func_hst_rdy[5] ),
.i_func5_com_rdy (func_com_rdy[5] ),
.o_func5_activate (func_activate[5] ),
//Function 6 Interface
.o_func6_wr_stb (func_wr_stb[6] ),
.o_func6_wr_data (func_wr_data[6] ),
.i_func6_rd_stb (func_rd_stb[6] ),
.i_func6_rd_data (func_rd_data[6] ),
.o_func6_hst_rdy (func_hst_rdy[6] ),
.i_func6_com_rdy (func_com_rdy[6] ),
.o_func6_activate (func_activate[6] ),
//Function 7 Interface
.o_func7_wr_stb (func_wr_stb[7] ),
.o_func7_wr_data (func_wr_data[7] ),
.i_func7_rd_stb (func_rd_stb[7] ),
.i_func7_rd_data (func_rd_data[7] ),
.o_func7_hst_rdy (func_hst_rdy[7] ),
.i_func7_com_rdy (func_com_rdy[7] ),
.o_func7_activate (func_activate[7] ),
//Memory Interface
.o_mem_wr_stb (func_wr_stb[8] ),
.o_mem_wr_data (func_wr_data[8] ),
.i_mem_rd_stb (func_rd_stb[8] ),
.i_mem_rd_data (func_rd_data[8] ),
.o_mem_hst_rdy (func_hst_rdy[8] ),
.i_mem_com_rdy (func_com_rdy[8] ),
.o_mem_activate (func_activate[8] ),
.o_func_enable (function_enable ),
.i_func_ready (function_ready ),
.o_func_abort_stb (function_abort_stb ),
.i_func_exec_status (function_exec_status ),
.i_func_ready_for_data(function_ready_for_data ),
.o_func_inc_addr (func_inc_addr ),
.o_func_block_mode (func_block_mode ),
.o_func_write_flag (func_write_flag ),
.o_func_num (func_num ),
.o_func_rd_after_wr (func_rd_after_wr ),
.o_func_addr (func_addr ),
.o_func_data_count (func_data_count ),
.i_interrupt (function_interrupt ),
.o_sd_cmd_dir (dev_sd_cmd_dir ),
.i_sd_cmd_in (dev_sd_cmd_in ),
.o_sd_cmd_out (dev_sd_cmd_out ),
.o_sd_data_dir (dev_sd_data_dir ),
.o_sd_data_out (dev_sd_data_out ),
.i_sd_data_in (dev_sd_data_in )
);
demo_function demo (
.clk (clk ),
.sdio_clk (dev_sd_clk ),
.rst (rst || !pll_locked),
.i_csa_en (fbr1_csa_en ),
.i_pwr_mode (fbr1_pwr_mode ),
.i_block_size (fbr1_block_size ),
.i_enable (function_enable[1] ),
.o_ready (demo_func_ready ),
.i_abort (function_abort_stb[1]),
.o_busy (demo_func_busy ),
.o_execution_status (demo_func_exec_sts ),
.o_ready_for_data (demo_func_ready_for_data),
.i_activate (func_activate[1] ),
.o_finished (demo_func_finished ),
.i_inc_addr (func_inc_addr ),
.i_block_mode (func_block_mode ),
.i_write_flag (func_write_flag ),
.i_rd_after_wr (func_rd_after_wr ),
.i_addr (func_addr ),
.i_write_data (func_wr_data[1] ),
.o_read_data (func_rd_data[1] ),
.o_data_rdy (func_com_rdy[1] ),
.i_data_stb (func_wr_stb[1] ),
.i_host_rdy (func_hst_rdy[1] ),
.i_data_count (func_data_count ),
.o_data_stb (func_rd_stb[1] ),
// .o_read_wait (demo_func_read_wait ),
.o_interrupt (demo_func_interrupt ),
// .i_request_read_wait (r_request_read_wait ),
.i_request_interrupt (r_request_interrupt )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
assign function_ready = {6'b000000, demo_func_ready, 1'b0};
assign function_exec_status = {6'b000000, demo_func_exec_sts, 1'b0};
assign function_ready_for_data = {6'b000000, demo_func_ready_for_data, 1'b0};
assign function_interrupt = {6'b000000, demo_func_interrupt, 1'b0};
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
`ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_144x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_144x256 (
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input clock;
input [143:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [143:0] q;
output [7:0] usedw;
wire sub_wire0;
wire [7:0] sub_wire1;
wire sub_wire2;
wire [143:0] sub_wire3;
wire sub_wire4;
wire almost_full = sub_wire0;
wire [7:0] usedw = sub_wire1[7:0];
wire empty = sub_wire2;
wire [143:0] q = sub_wire3[143:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
.usedw (sub_wire1),
.empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_full_value = 250,
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 144,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "250"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "144"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "144"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "250"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "144"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 144 0 INPUT NODEFVAL data[143..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 144 0 OUTPUT NODEFVAL q[143..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 144 0 data 0 0 144 0
// Retrieval info: CONNECT: q 0 0 144 0 @q 0 0 144 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
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