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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7091r (
// physical interface
adc_sdo_i,
adc_sclk_o,
adc_cnv_o,
adc_cs_n_o,
ref_clk,
rx_clk,
// master-slave interface
adc_start_out,
dma_start_out,
adc_start_in,
dma_start_in,
// dma interface
s_axis_s2mm_clk,
s_axis_s2mm_tvalid,
s_axis_s2mm_tdata,
s_axis_s2mm_tkeep,
s_axis_s2mm_tlast,
s_axis_s2mm_tready,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
// debug signals
adc_clk,
adc_mon_valid,
adc_mon_data);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
input ref_clk;
input rx_clk;
input adc_sdo_i;
output adc_sclk_o;
output adc_cnv_o;
output adc_cs_n_o;
// master-slave interface
output adc_start_out;
output dma_start_out;
input adc_start_in;
input dma_start_in;
// dma interface
input s_axis_s2mm_clk;
output s_axis_s2mm_tvalid;
output [31:0] s_axis_s2mm_tdata;
output [ 3:0] s_axis_s2mm_tkeep;
output s_axis_s2mm_tlast;
input s_axis_s2mm_tready;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// debug signals
output adc_clk;
output adc_mon_valid;
output [31:0] adc_mon_data;
// internal registers
reg adc_start_out = 'd0;
reg adc_valid = 'd0;
reg [31:0] adc_data = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
// internal clocks & resets
wire adc_rst;
wire dma_clk;
wire dma_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire adc_start_s;
wire dma_start_s;
wire [15:0] adc_data_s;
wire [15:0] adc_dcfilter_data_a_s;
wire [15:0] adc_dcfilter_data_b_s;
wire adc_enable_s;
wire adc_status_s;
wire dma_valid_s;
wire dma_last_s;
wire [31:0] dma_data_s;
wire dma_ready_s;
wire dma_stream_s;
wire [31:0] dma_count_s;
wire dma_ovf_s;
wire dma_unf_s;
wire dma_status_s;
wire [31:0] dma_bw_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
wire [31:0] pid_s;
wire adc_data_valid;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign dma_clk = s_axis_s2mm_clk;
assign dma_ready_s = s_axis_s2mm_tready;
assign s_axis_s2mm_tvalid = dma_valid_s;
assign s_axis_s2mm_tdata = dma_data_s;
assign s_axis_s2mm_tlast = dma_last_s;
assign s_axis_s2mm_tkeep = 4'hf;
// monitor signals
assign adc_mon_valid = data_rd_ready_s;
assign adc_mon_data[15: 0] = adc_data_s;
assign adc_mon_data[31:16] = 16'h0;
// multiple instances synchronization
assign pid_s = 32'd0;
assign adc_start_s = (pid_s == 32'd0) ? adc_start_out : adc_start_in;
assign dma_start_s = (pid_s == 32'd0) ? dma_start_out : dma_start_in;
assign adc_clk = s_axi_aclk;
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_start_out <= 1'b0;
end else begin
adc_start_out <= 1'b1;
end
end
// adc channels - dma interface
always @(posedge adc_clk)
begin
adc_valid <= data_rd_ready_s;
adc_data <= { 16'h0, adc_data_s };
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_rdata <= up_adc_common_rdata_s;
up_ack <= up_adc_common_ack_s;
end
end
// main (device interface)
axi_ad7091r_dev_if i_if (
.fpga_clk_i (ref_clk),
.adc_clk_i (rx_clk),
.reset_i(adc_rst),
.data_o (adc_data_s),
.data_rd_ready_o (data_rd_ready_s),
.adc_sdo_i (adc_sdo_i),
.adc_cs_n_o (adc_cs_n_o),
.adc_sclk_o (adc_sclk_o),
.adc_convst_n_o (adc_cnv_o),
.adc_status_o (adc_status_s)
);
// dma transfer
dma_core #(.DATA_WIDTH(32)) i_dma_core (
.dma_clk (dma_clk),
.dma_rst (dma_rst),
.dma_valid (dma_valid_s),
.dma_last (dma_last_s),
.dma_data (dma_data_s),
.dma_ready (dma_ready_s),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dma_status (dma_status_s),
.dma_bw (dma_bw_s),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid),
.adc_data (adc_data),
.dma_start (dma_start_s),
.dma_stream (dma_stream_s),
.dma_count (dma_count_s));
// common processor control
up_adc_common i_up_adc_common (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_clk_ratio (32'd1),
.delay_clk (1'b0),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (5'd0),
.delay_ack_t (1'b0),
.delay_locked (1'b0),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_rwn (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ack_t (1'd0),
.dma_clk (dma_clk),
.dma_rst (dma_rst),
.dma_start (dma_start_out),
.dma_stream (dma_stream_s),
.dma_count (dma_count_s),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dma_status (dma_status_s),
.dma_bw (dma_bw_s),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_common_rdata_s),
.up_ack (up_adc_common_ack_s)
);
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*******************************************************************************
* Copyright (c) 2015 Elphel, Inc.
* Dual port memory wrapper, with variable width write and variable width read
* using "SDP" or "TDP" mode of RAMB18E1 (half of RAMB18E1)
* Uses parity bits to extend total data width (minimal width should be >=8).
* ram18p_var_w_var_r.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ram18p_var_w_var_r.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*******************************************************************************/
`include "system_defines.vh"
/*
Address/data widths
Connect unused data to 1b0, unused addresses - to 1'b1
RAMB18E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[13:0] | D[0] | --- |
| 2 | A[13:1] | D[1:0] | --- |
| 4 | A[13:2] | D[3:0[ | --- |
| 9 | A[13:3] | D[7:0] | DP[0] |
| 18 | A[13:4] | D[15:0] | DP[1:0] |
+-----------+---------+---------+---------+
RAMB18E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 32/36 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 32/ 1 | A[13:0] | D[0] | --- |
| 32/ 2 | A[13:1] | D[1:0] | --- |
| 32/ 4 | A[13:2] | D[3:0[ | --- |
| 36/ 9 | A[13:3] | D[7:0] | DP[0] |
| 36/ 18 | A[13:4] | D[15:0] | DP[1:0] |
| 36/ 36 | A[13:5] | D[31:0] | DP[3:0] |
+------------+---------+---------+---------+
RAMB36E1 in True Dual Port (TDP) Mode - each port individually
+-----------+---------+---------+---------+
|Data Width | Address | Data | Parity |
+-----------+---------+---------+---------+
| 1 | A[14:0] | D[0] | --- |
| 2 | A[14:1] | D[1:0] | --- |
| 4 | A[14:2] | D[3:0[ | --- |
| 9 | A[14:3] | D[7:0] | DP[0] |
| 18 | A[14:4] | D[15:0] | DP[1:0] |
| 36 | A[14:5] | D[31:0] | DP[3:0] |
|1(Cascade) | A[15:0] | D[0] | --- |
+-----------+---------+---------+---------+
RAMB36E1 in Simple Dual Port (SDP) Mode
one of the ports (r or w) - 64/72 bits, other - variable
+------------+---------+---------+---------+
|Data Widths | Address | Data | Parity |
+------------+---------+---------+---------+
| 64/ 1 | A[14:0] | D[0] | --- |
| 64/ 2 | A[14:1] | D[1:0] | --- |
| 64/ 4 | A[14:2] | D[3:0[ | --- |
| 64/ 9 | A[14:3] | D[7:0] | DP[0] |
| 64/ 18 | A[14:4] | D[15:0] | DP[1:0] |
| 64/ 36 | A[14:5] | D[31:0] | DP[3:0] |
| 64/ 72 | A[14:6] | D[63:0] | DP[7:0] |
+------------+---------+---------+---------+
*/
module ram18p_var_w_var_r
#(
parameter integer REGISTERS = 0, // 1 - registered output
parameter integer LOG2WIDTH_WR = 5, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter integer LOG2WIDTH_RD = 5, // WIDTH= 9 << (LOG2WIDTH - 3)
parameter DUMMY = 0
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
// input [ 9:0] raddr, // read address
input [13-LOG2WIDTH_RD:0] raddr, // read address
input ren, // read port enable
input regen, // output register enable
output [(9 << (LOG2WIDTH_RD-3))-1:0] data_out, // data out
input wclk, // clock for read port
input [13-LOG2WIDTH_WR:0] waddr, // write address
input we, // write port enable
input [ 3:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
generate
if (DUMMY)
ram18p_dummy #(
.LOG2WIDTH_RD(LOG2WIDTH_RD)
) ram18p_dummy_i (
.data_out(data_out)
);
else if ((LOG2WIDTH_WR == 5) && (LOG2WIDTH_RD == 5))
ram18p_32w_32r #(
.REGISTERS (REGISTERS)
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[8:0]
.ren (ren), // input
.regen (regen), // input
.data_out (data_out), // output[35:0]
.wclk (wclk), // input
.waddr (waddr), // input[8:0]
.we (we), // input
.web (web), // input[3:0]
.data_in (data_in) // input[35:0]
);
else if ((LOG2WIDTH_WR == 5) && (LOG2WIDTH_RD < 5))
ram18p_32w_lt32r #(
.REGISTERS (REGISTERS),
.LOG2WIDTH_RD (LOG2WIDTH_RD)
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[(>8):0]
.ren (ren), // input
.regen (regen), // input
.data_out (data_out), // output[(<35):0]
.wclk (wclk), // input
.waddr (waddr), // input[8:0]
.we (we), // input
.web (web), // input[3:0]
.data_in (data_in) // input[35:0]
);
else if ((LOG2WIDTH_WR < 5) && (LOG2WIDTH_RD == 5))
ram18p_lt32w_32r #(
.REGISTERS (REGISTERS),
.LOG2WIDTH_WR (LOG2WIDTH_WR)
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[8:0]
.ren (ren), // input
.regen (regen), // input
.data_out (data_out), // output[35:0]
.wclk (wclk), // input
.waddr (waddr), // input[(>8):0]
.we (we), // input
.web (web), // input[3:0]
.data_in (data_in) // input[(<35):0]
);
else if ((LOG2WIDTH_WR < 5) && (LOG2WIDTH_RD < 5))
ram18p_lt32w_lt32r #(
.REGISTERS (REGISTERS),
.LOG2WIDTH_WR (LOG2WIDTH_WR),
.LOG2WIDTH_RD (LOG2WIDTH_RD)
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) ram_i (
.rclk (rclk), // input
.raddr (raddr), // input[(>8):0]
.ren (ren), // input
.regen (regen), // input
.data_out (data_out), // output[(<35):0]
.wclk (wclk), // input
.waddr (waddr), // input[(>8):0]
.we (we), // input
.web (web), // input[7:0]
.data_in (data_in) // input[(<35):0]
);
endgenerate
endmodule
// Both ports with 32 bit widths
module ram18p_32w_32r
#(
parameter integer REGISTERS = 0 // 1 - registered output
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
input [8:0] raddr, // read address
input ren, // read port enable
input regen, // output register enable
output [35:0] data_out, // data out
input wclk, // clock for read port
input [ 8:0] waddr, // write address
input we, // write port enable
input [ 3:0] web, // write byte enable
input [35:0] data_in // data out
);
localparam PWIDTH_WR=36;
localparam PWIDTH_RD=36;
RAMB18E1
#(
.RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.DOA_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.DOB_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.READ_WIDTH_A (PWIDTH_RD), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.READ_WIDTH_B (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_A (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_B (PWIDTH_WR), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.RAM_MODE ("SDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
.WRITE_MODE_A ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.WRITE_MODE_B ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
.DOADO (data_out[15:0]), // Port A data/LSB data[15:0], output
.DOPADOP (data_out[17:16]),// Port A parity/LSB parity[2:0], output
.DIADI (data_in[15:0]), // Port A data/LSB data[15:0], input
.DIPADIP (data_in[17:16]), // Port A parity/LSB parity[2:0], input
.ADDRARDADDR ({raddr[8:0],5'b11111}), // Port A (read port in SDP) address [13:0], unused should be high, input
.CLKARDCLK (rclk), // Port A (read port in SDP) clock, input
.ENARDEN (ren), // Port A (read port in SDP) Enable, input
.REGCEAREGCE (regen), // Port A (read port in SDP) register enable, input
.RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
.RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
.WEA (2'b0), // Port A (read port in SDP) Write Enable[2:0], input
// Port B
.DOBDO (data_out[33:18]),// Port B data/MSB data[15:0], output
.DOPBDOP (data_out[35:34]),// Port B parity/MSB parity[2:0], output
.DIBDI (data_in[33:18]), // Port B data/MSB data[31:0], input
.DIPBDIP (data_in[35:34]), // Port B parity/MSB parity[1:0], input
.ADDRBWRADDR ({waddr[8:0],5'b11111}), // Port B (write port in SDP) address [13:0], unused should be high, input
.CLKBWRCLK (wclk), // Port B (write port in SDP) clock, input
.ENBWREN (we), // Port B (write port in SDP) Enable, input
.REGCEB (1'b0), // Port B (write port in SDP) register enable, input
.RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
.RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
.WEBWE (web) // Port B (write port in SDP) Write Enable[7:0], input
);
endmodule
// Both ports with less than 32 bit widths
module ram18p_lt32w_lt32r
#(
parameter integer REGISTERS = 0, // 1 - registered output
parameter integer LOG2WIDTH_WR = 4, // WIDTH= 1 << LOG2WIDTH
parameter integer LOG2WIDTH_RD = 4 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
input [13-LOG2WIDTH_RD:0] raddr, // read address
input ren, // read port enable
input regen, // output register enable
output [(9 << (LOG2WIDTH_RD-3))-1:0] data_out, // data out
input wclk, // clock for read port
input [13-LOG2WIDTH_WR:0] waddr, // write address
input we, // write port enable
input [ 3:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
localparam WIDTH_WRP = 1 << (LOG2WIDTH_WR-3);
localparam WIDTH_RD = 1 << LOG2WIDTH_RD;
localparam WIDTH_RDP = 1 << (LOG2WIDTH_RD-3);
wire [15:0] data_out16;
wire [ 1:0] datap_out2;
assign data_out={datap_out2[WIDTH_RDP-1:0], data_out16[WIDTH_RD-1:0]};
wire [WIDTH_WR+15:0] data_in_ext = {16'b0,data_in[WIDTH_WR-1:0]};
wire [15:0] data_in16=data_in_ext[15:0];
wire [WIDTH_WRP+1:0] datap_in_ext = {2'b0,data_in[WIDTH_WR+:WIDTH_WRP]};
wire [1:0] datap_in2= datap_in_ext[1:0];
RAMB18E1
#(
.RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.DOA_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.DOB_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.READ_WIDTH_A (PWIDTH_RD), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.READ_WIDTH_B (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_A (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_B (PWIDTH_WR), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.RAM_MODE ("TDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
.WRITE_MODE_A ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.WRITE_MODE_B ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
.DOADO (data_out16), // Port A data/LSB data[15:0], output
.DOPADOP (datap_out2), // Port A parity/LSB parity[1:0], output
.DIADI (16'h0), // Port A data/LSB data[15:0], input
.DIPADIP (2'h0), // Port A parity/LSB parity[1:0], input
.ADDRARDADDR ({raddr,{LOG2WIDTH_RD{1'b1}}}), // Port A (read port in SDP) address [13:0], unused should be high, input
.CLKARDCLK (rclk), // Port A (read port in SDP) clock, input
.ENARDEN (ren), // Port A (read port in SDP) Enable, input
.REGCEAREGCE (regen), // Port A (read port in SDP) register enable, input
.RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
.RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
.WEA (2'b0), // Port A (read port in SDP) Write Enable[3:0], input
// Port B
.DOBDO (), // Port B data/MSB data[31:0], output
.DOPBDOP (), // Port B parity/MSB parity[3:0], output
.DIBDI (data_in16), // Port B data/MSB data[31:0], input
.DIPBDIP (datap_in2), // Port B parity/MSB parity[3:0], input
.ADDRBWRADDR ({waddr,{LOG2WIDTH_WR{1'b1}}}), // Port B (write port in SDP) address [13:0], unused should be high, input
.CLKBWRCLK (wclk), // Port B (write port in SDP) clock, input
.ENBWREN (we), // Port B (write port in SDP) Enable, input
.REGCEB (1'b0), // Port B (write port in SDP) register enable, input
.RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
.RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
.WEBWE (web[3:0]) // Port B (write port in SDP) Write Enable[3:0], input
);
endmodule
// Write port less than 32bits, read port 32 bit widths
module ram18p_lt32w_32r
#(
parameter integer REGISTERS = 0, // 1 - registered output
parameter integer LOG2WIDTH_WR = 4 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
input [8:0] raddr, // read address
input ren, // read port enable
input regen, // output register enable
output [35:0] data_out, // data out
input wclk, // clock for read port
input [13-LOG2WIDTH_WR:0] waddr, // write address
input we, // write port enable
input [ 3:0] web, // write byte enable
input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
);
localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
localparam PWIDTH_RD = 36;
localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
localparam WIDTH_WRP = 1 << (LOG2WIDTH_WR-3);
wire [WIDTH_WR+15:0] data_in_ext = {16'b0,data_in[WIDTH_WR-1:0]};
wire [15:0] data_in16=data_in_ext[15:0];
wire [WIDTH_WRP+1:0] datap_in_ext = {2'b0,data_in[WIDTH_WR+:WIDTH_WRP]};
wire [1:0] datap_in2= datap_in_ext[1:0];
RAMB18E1
#(
.RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.DOA_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.DOB_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.READ_WIDTH_A (PWIDTH_RD), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.READ_WIDTH_B (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_A (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_B (PWIDTH_WR), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.RAM_MODE ("SDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
.WRITE_MODE_A ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.WRITE_MODE_B ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
.DOADO (data_out[15:0]), // Port A data/LSB data[15:0], output
.DOPADOP (data_out[17:16]),// Port A parity/LSB parity[3:0], output
.DIADI (16'h0), // Port A data/LSB data[31:0], input
.DIPADIP (2'h0), // Port A parity/LSB parity[3:0], input
.ADDRARDADDR ({raddr[8:0],5'b11111}), // Port A (read port in SDP) address [15:0]. used from [14] down, unused should be high, input
.CLKARDCLK (rclk), // Port A (read port in SDP) clock, input
.ENARDEN (ren), // Port A (read port in SDP) Enable, input
.REGCEAREGCE (regen), // Port A (read port in SDP) register enable, input
.RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
.RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
.WEA (2'b0), // Port A (read port in SDP) Write Enable[3:0], input
// Port B
.DOBDO (data_out[33:18]),// Port B data/MSB data[31:0], output
.DOPBDOP (data_out[35:34]),// Port B parity/MSB parity[3:0], output
.DIBDI (data_in16), // Port B data/MSB data[31:0], input
.DIPBDIP (datap_in2), // Port B parity/MSB parity[3:0], input
.ADDRBWRADDR ({waddr,{LOG2WIDTH_WR{1'b1}}}), // Port B (write port in SDP) address [15:0]. used from [14] down, unused should be high, input
.CLKBWRCLK (wclk), // Port B (write port in SDP) clock, input
.ENBWREN (we), // Port B (write port in SDP) Enable, input
.REGCEB (1'b0), // Port B (write port in SDP) register enable, input
.RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
.RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
.WEBWE (web[3:0]) // Port B (write port in SDP) Write Enable[7:0], input
);
endmodule
// Write port 64 bita, read port - less than 64 bits
module ram18p_32w_lt32r
#(
parameter integer REGISTERS = 0, // 1 - registered output
// parameter integer LOG2WIDTH_WR = 4, // WIDTH= 1 << LOG2WIDTH
parameter integer LOG2WIDTH_RD = 4 // WIDTH= 1 << LOG2WIDTH
`ifdef PRELOAD_BRAMS
,
`include "includes/ram18_declare_init.vh"
`endif
)
(
input rclk, // clock for read port
input [13-LOG2WIDTH_RD:0] raddr, // read address
input ren, // read port enable
input regen, // output register enable
output [(9 << (LOG2WIDTH_RD-3))-1:0] data_out, // data out
input wclk, // clock for read port
input [8:0] waddr, // write address
input we, // write port enable
input [ 3:0] web, // write byte enable
input [35:0] data_in // data out
);
localparam PWIDTH_WR = 36;
localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
localparam WIDTH_RD = 1 << LOG2WIDTH_RD;
localparam WIDTH_RDP = 1 << (LOG2WIDTH_RD-3);
wire [15:0] data_out16;
wire [ 1:0] datap_out2;
assign data_out={datap_out2[WIDTH_RDP-1:0], data_out16[WIDTH_RD-1:0]};
RAMB18E1
#(
.RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
.DOA_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.DOB_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
.READ_WIDTH_A (PWIDTH_RD), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.READ_WIDTH_B (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_A (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.WRITE_WIDTH_B (PWIDTH_WR), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
.RAM_MODE ("SDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
.WRITE_MODE_A ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.WRITE_MODE_B ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
.SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
.INIT_FILE ("NONE"), // "NONE" or filename with initialization data
.SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
`ifdef PRELOAD_BRAMS
`include "includes/ram18_pass_init.vh"
`endif
) RAMB36E1_i
(
// Port A (Read port in SDP mode):
.DOADO (data_out16), // Port A data/LSB data[15:0], output
.DOPADOP (datap_out2), // Port A parity/LSB parity[1:0], output
.DIADI (data_in[15:0]), // Port A data/LSB data[15:0], input
.DIPADIP (data_in[17:16]), // Port A parity/LSB parity[1:0], input
.ADDRARDADDR ({raddr,{LOG2WIDTH_RD{1'b1}}}), // Port A (read port in SDP) address [13:0], unused should be high, input
.CLKARDCLK (rclk), // Port A (read port in SDP) clock, input
.ENARDEN (ren), // Port A (read port in SDP) Enable, input
.REGCEAREGCE (regen), // Port A (read port in SDP) register enable, input
.RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
.RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
.WEA (2'b0), // Port A (read port in SDP) Write Enable[1:0], input
// Port B
.DOBDO (), // Port B data/MSB data[15:0], output
.DOPBDOP (), // Port B parity/MSB parity[1:0], output
.DIBDI (data_in[33:18]), // Port B data/MSB data[15:0], input
.DIPBDIP (data_in[35:34]), // Port B parity/MSB parity[1:0], input
.ADDRBWRADDR({waddr[8:0],5'b11111}), // Port B (write port in SDP) address [13:0], unused should be high, input
.CLKBWRCLK (wclk), // Port B (write port in SDP) clock, input
.ENBWREN (we), // Port B (write port in SDP) Enable, input
.REGCEB (1'b0), // Port B (write port in SDP) register enable, input
.RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
.RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
.WEBWE (web[3:0]) // Port B (write port in SDP) Write Enable[7:0], input
);
endmodule
module ram18p_dummy
#(
parameter integer LOG2WIDTH_RD = 4 // WIDTH= 1 << LOG2WIDTH
)
(
output [(9 << (LOG2WIDTH_RD-3))-1:0] data_out // data out
);
assign data_out=0;
endmodule
|
module var19_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
`include "bsg_mem_1rw_sync_mask_write_byte_macros.vh"
module bsg_mem_1rw_sync_mask_write_byte #( parameter `BSG_INV_PARAM(els_p )
, parameter `BSG_INV_PARAM(data_width_p )
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter write_mask_width_lp = data_width_p>>3
, parameter harden_p = 1
, parameter latch_last_read_p = 1
)
( input clk_i
, input reset_i
, input v_i
, input w_i
, input [addr_width_lp-1:0] addr_i
, input [data_width_p-1:0] data_i
, input [write_mask_width_lp-1:0] write_mask_i
, output logic [data_width_p-1:0] data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_1rw_sync_mask_write_byte_macro(512,64,2) else
`bsg_mem_1rw_sync_mask_write_byte_macro(1024,32,4) else
`bsg_mem_1rw_sync_mask_write_byte_macro(2048,64,4) else
`bsg_mem_1rw_sync_mask_write_byte_macro(4096,64,4) else
`bsg_mem_1rw_sync_mask_write_byte_macro(1024,32,4) else
`bsg_mem_1rw_sync_mask_write_byte_banked_macro(1024,256,8,1) else
// no hardened version found
begin : notmacro
bsg_mem_1rw_sync_mask_write_byte_synth #(.data_width_p(data_width_p), .els_p(els_p), .latch_last_read_p(latch_last_read_p))
synth
(.*);
end // block: notmacro
// synopsys translate_off
always_comb
begin
assert (data_width_p % 8 == 0)
else $error("data width should be a multiple of 8 for byte masking");
end
initial
begin
$display("## bsg_mem_1rw_sync_mask_write_byte: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte)
|
module Datapath(input clock,
input clear);
// PC register
wire[31:0] pc_in;
wire[31:0] pc_out;
PcRegister pc_register(
clock,
clear,
pc_in,
pc_out);
// Instruction memory
wire[31:0] instruction_memory_address;
wire[31:0] instruction_memory_instr;
InstructionMemory instruction_memory(
clock,
clear,
instruction_memory_address,
instruction_memory_instr);
// Connections for instruction memory
assign instruction_memory_address = pc_out;
// Adder4
wire[31:0] adder4_in;
wire[31:0] adder4_out;
Adder4 adder4(adder4_in,
adder4_out);
// Connections for Adder4
assign adder4_in = pc_out;
// PC MUX
wire[31:0] pc_mux_in0;
wire[31:0] pc_mux_in1;
wire[31:0] pc_mux_out;
wire pc_mux_sel;
Mux32Bit2To1 pc_mux(pc_mux_in0,
pc_mux_in1,
pc_mux_sel,
pc_mux_out);
// Connections for PC MUX
assign pc_in = pc_mux_out;
assign pc_mux_in0 = adder4_out;
// Register file MUX
wire[4:0] register_file_mux_in0;
wire[4:0] register_file_mux_in1;
wire[4:0] register_file_mux_out;
wire register_file_mux_sel;
Mux5Bit2To1 register_file_mux(
register_file_mux_in0,
register_file_mux_in1,
register_file_mux_sel,
register_file_mux_out);
// Connections for register file MUX
assign register_file_mux_in0 = instruction_memory_instr[20:16];
assign register_file_mux_in1 = instruction_memory_instr[15:11];
// Register file
wire[4:0] register_file_read_index1;
wire[31:0] register_file_read_data1;
wire[4:0] register_file_read_index2;
wire[31:0] register_file_read_data2;
wire register_file_write;
wire[4:0] register_file_write_index;
reg[31:0] register_file_write_data;
RegisterFile register_file(
clock,
clear,
register_file_read_index1,
register_file_read_data1,
register_file_read_index2,
register_file_read_data2,
register_file_write,
register_file_write_index,
register_file_write_data);
// Connections for register file
assign register_file_read_index1 = instruction_memory_instr[25:21];
assign register_file_read_index2 = instruction_memory_instr[20:16];
assign register_file_write_index = register_file_mux_out;
// ALU MUX
wire[31:0] alu_mux_in0;
wire[31:0] alu_mux_in1;
wire[31:0] alu_mux_in2;
wire[31:0] alu_mux_in3;
wire[31:0] alu_mux_out;
wire[1:0] alu_mux_sel;
Mux32Bit4To1 alu_mux(
alu_mux_in0,
alu_mux_in1,
alu_mux_in2,
alu_mux_in3,
alu_mux_sel,
alu_mux_out);
// Connections for ALU MUX
assign alu_mux_in0 = register_file_read_data2;
// ALU
wire[31:0] alu_op1;
wire[31:0] alu_op2;
wire[3:0] alu_f;
wire[31:0] alu_result;
wire alu_zero;
Alu alu(alu_op1,
alu_op2,
alu_f,
alu_result,
alu_zero);
// MULT/DIV ALU Module
wire mult_alu_en;
wire[31:0] alu_result_hi;
wire[31:0] alu_result_lo;
Mult_Div_Alu mult_div_alu(alu_op1,
alu_op2,
alu_f,
mult_alu_en,
alu_result_hi,
alu_result_lo);
// Connections for ALU(s)
assign alu_op1 = register_file_read_data1;
assign alu_op2 = alu_mux_out;
// Data memory
wire[31:0] data_memory_address;
wire data_memory_write;
wire[31:0] data_memory_write_data;
wire[31:0] data_memory_read_data;
DataMemory data_memory(
clock,
clear,
data_memory_address,
data_memory_write,
data_memory_write_data,
data_memory_read_data);
// Connections for data memory
assign data_memory_address = alu_result;
assign data_memory_write_data = register_file_read_data2;
// Data memory MUX
wire[31:0] data_memory_mux_in0;
wire[31:0] data_memory_mux_in1;
wire data_memory_mux_sel;
wire[31:0] data_memory_mux_out;
Mux32Bit2To1 data_memory_mux(
data_memory_mux_in0,
data_memory_mux_in1,
data_memory_mux_sel,
data_memory_mux_out);
// Connections for data memory MUX
assign data_memory_mux_in0 = alu_result;
assign data_memory_mux_in1 = data_memory_read_data;
//assign register_file_write_data = data_memory_mux_out;
// SignExtend
wire[15:0] sign_extend_in;
wire[31:0] sign_extend_out;
SignExtend sign_extend(
sign_extend_in,
sign_extend_out);
// Connections for SignExtend
assign sign_extend_in = instruction_memory_instr[15:0];
// ZeroExtend
wire[15:0] zero_extend_in;
wire[31:0] zero_extend_out;
ZeroExtend zero_extend(
zero_extend_in,
zero_extend_out);
// Connections for ZeroExtend
assign zero_extend_in = instruction_memory_instr[15:0];
// Zero_Sign_Ext MUX
wire[31:0] zero_sign_ext_mux_in0;
wire[31:0] zero_sign_ext_mux_in1;
wire zero_sign_ext_mux_sel;
wire[31:0] zero_sign_ext_mux_out;
Mux32Bit2To1 zero_sign_ext_mux(
zero_sign_ext_mux_in0,
zero_sign_ext_mux_in1,
zero_sign_ext_mux_sel,
zero_sign_ext_mux_out);
// Connections for Zero_Sign_Ext MUX
assign zero_sign_ext_mux_in0 = sign_extend_out;
assign zero_sign_ext_mux_in1 = zero_extend_out;
assign alu_mux_in1 = zero_sign_ext_mux_out;
// ShiftLeft
wire[31:0] shift_left_in;
wire[31:0] shift_left_out;
ShiftLeft shift_left(
shift_left_in,
shift_left_out);
// Connections for ShiftLeft
assign shift_left_in = sign_extend_out;
// Adder
wire[31:0] adder_op1;
wire[31:0] adder_op2;
wire[31:0] adder_result;
Adder adder(adder_op1,
adder_op2,
adder_result);
// Connections for adder
assign adder_op1 = shift_left_out;
assign adder_op2 = adder4_out;
assign pc_mux_in1 = adder_result;
// And gate
wire and_gate_in1;
wire and_gate_in2;
wire and_gate_out;
and and_gate(and_gate_out,
and_gate_in1,
and_gate_in2);
// Connections for and gate
assign and_gate_in2 = alu_zero;
assign pc_mux_sel = and_gate_out;
// ZeroExtendShamt
wire[4:0] zero_ext_shamt_in;
wire[31:0] zero_ext_shamt_out;
ZeroExtendShamt zero_ext_shamt(
zero_ext_shamt_in,
zero_ext_shamt_out);
// Connections for ZeroExtendShamt
assign zero_ext_shamt_in = instruction_memory_instr[10:6];
assign alu_mux_in2 = zero_ext_shamt_out;
// Control unit
wire[5:0] control_unit_opcode;
wire[5:0] control_unit_funct;
wire control_unit_reg_dst;
wire control_unit_reg_write;
wire[1:0] control_unit_alu_src;
wire[3:0] control_unit_alu_op;
wire control_unit_branch;
wire control_unit_mem_write;
wire control_unit_mem_to_reg;
wire control_unit_zero_sign_ext;
wire control_unit_mult_op;
wire control_unit_mfhi;
wire control_unit_mflo;
ControlUnit control_unit(
control_unit_opcode,
control_unit_funct,
control_unit_reg_dst,
control_unit_reg_write,
control_unit_alu_src,
control_unit_alu_op,
control_unit_branch,
control_unit_mem_write,
control_unit_mem_to_reg,
control_unit_zero_sign_ext,
control_unit_mult_op,
control_unit_mfhi,
control_unit_mflo);
// Connections for control unit
assign control_unit_opcode = instruction_memory_instr[31:26];
assign control_unit_funct = instruction_memory_instr[5:0];
assign register_file_mux_sel = control_unit_reg_dst;
assign register_file_write = control_unit_reg_write;
assign alu_mux_sel = control_unit_alu_src;
assign alu_f = control_unit_alu_op;
assign and_gate_in1 = control_unit_branch;
assign data_memory_write = control_unit_mem_write;
assign data_memory_mux_sel = control_unit_mem_to_reg;
assign mult_alu_en = control_unit_mult_op;
// NOTE: it's not possible for mflo and mfhi to both be enabled so this
// won't result in a race condition
always@(control_unit_mflo, control_unit_mfhi) begin
case({control_unit_mflo, control_unit_mfhi})
2'b10: register_file_write_data = alu_result_lo;
2'b01: register_file_write_data = alu_result_hi;
default: register_file_write_data = data_memory_mux_out;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCON_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__FAHCON_BEHAVIORAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
// Local signals
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire u_vpwr_vgnd1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , u_vpwr_vgnd1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCON_BEHAVIORAL_PP_V |
module r5_decoder
(// INSTRUCTION TO DECODE
input [31:0] instr,
// TYPES
output de_rv32i,
output de_rv64i,
output de_rv32m,
output de_rv64m,
output de_rv32a,
output de_rv64a,
output de_rv32f,
output de_rv32d,
output de_rv64d,
// IMMEDIATES
output [31:0] de_imm_data,
output de_imm_sel,
// IALU
output de_and,
output de_sub, // subtract
output de_asr, // arithmetic shift right
output de_lsl, // logical shift left
output de_lsr, // logical shift right
output de_orr, // logical or
output de_eor, // logical xor
output de_sltu, // set if less than (unsigned)
output de_slt, // set if less than (signed)
output de_rs1_read,
output [4:0] de_rs1_addr,
output de_rs2_read,
output [4:0] de_rs2_addr,
output de_rd_write,
output [4:0] de_rd_addr,
// FPU
output de_fadd,
output de_fsub,
output de_fmul,
output de_fmadd,
output de_fnmadd,
output de_fmsub,
output de_fnmsub,
output de_fdiv,
output de_fmin,
output de_fmax,
output de_fsqrt,
output de_fix,
output de_float,
output de_fabs,
output de_fmin,
output de_fmax,
output de_feq, // floating point equal comparison
output de_flt, // floating point less than comparison
output de_fle, // floating point less than or equal comparison
output de_fmv_float2int, // move from float reg to int reg file
output de_fmv_int2float, // move from int reg to float reg file
output de_flcass, // classifies floating point number
output de_fnegate, //negative floating point value
output de_fcopysign, // RD = RS1[30:0] | RS2[31]
output de_finvertsign,// RD = RS1[30:0] | ~RS2[31]
output de_fxorsign,// RD = RS1[31:0] | RS2[31]
output de_frs1_read,
output [4:0] de_frs1_addr,
output de_frs2_read,
output [4:0] de_frs2_addr,
output de_frs3_read,
output [4:0] de_frs3_addr,
output de_frd_write,
output [4:0] de_frd_addr,
output [2:0] de_frounding_mode,
// BRANCHING
output de_branch,
output de_link,
output [3:0] de_branch_code,
output de_jump_reg
output de_aupic, // RD=PC+IMM20
// LOAD/STORE
output de_load, //load operation
output de_store, // store operation
output [1:0] de_datamode,//00=byte,01=half,10=word,11=double
output de_load_signed, // load signed data
output de_movi, // load immediate, ADDI RD, R0,IMM
output de_movi_hi, // load immediate, RD=RS | IMM <<12
// ATOMICS
output de_fence, //memory fence operation
output de_atomic_lr,//atomic load conditional
output de_atomic_sc, //atomic store conditional
output de_atomic_swap, //atomic swap
output de_atomic_add, //atomic add
output de_atomic_xor, //atomic xor
output de_atomic_or,// atomic or
output de_atomic_and, //atomic and
output de_atomic_min,//signed atomic min operation
output de_atomic_max,//signed atomic max operation
output de_atomic_minu,//unsigned atomic min operation
output de_atomic_maxu//unsigned atomic max operation
);
endmodule // r5_decoder
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:41:22 09/24/2013
// Design Name: Clock_Divider
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab3/laboratorio3/test_divisor.v
// Project Name: laboratorio3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Clock_Divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_divisor;
// Inputs
reg clock;
reg reset;
// Outputs
wire clock_out;
// Instantiate the Unit Under Test (UUT)
Clock_Divider uut (
.clock(clock),
.reset(reset),
.clock_out(clock_out)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111A_4_V
`define SKY130_FD_SC_HS__O2111A_4_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2111a_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2111a_4 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111A_4_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:23:08 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, r_mode,
ready_cordic, overflow_flag, underflow_flag, data_output );
input [31:0] data_in;
input [1:0] shift_region_flag;
input [1:0] r_mode;
output [31:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag;
wire d_ff1_operation_out, sel_mux_1_reg, d_ff3_sign_out, sel_mux_3_reg,
data_output2_31_, cordic_FSM_state_next_1_,
add_subt_module_sign_final_result, add_subt_module_intAS,
add_subt_module_add_overflow_flag, add_subt_module_FSM_selector_C,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1016,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067,
n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077,
n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, DP_OP_92J114_122_1254_n20,
DP_OP_92J114_122_1254_n19, DP_OP_92J114_122_1254_n18,
DP_OP_92J114_122_1254_n17, DP_OP_92J114_122_1254_n16,
DP_OP_92J114_122_1254_n15, DP_OP_92J114_122_1254_n14,
DP_OP_92J114_122_1254_n13, DP_OP_92J114_122_1254_n8,
DP_OP_92J114_122_1254_n7, DP_OP_92J114_122_1254_n6,
DP_OP_92J114_122_1254_n5, DP_OP_92J114_122_1254_n4,
DP_OP_92J114_122_1254_n3, DP_OP_92J114_122_1254_n2,
DP_OP_92J114_122_1254_n1, DP_OP_95J114_125_203_n56,
DP_OP_95J114_125_203_n55, DP_OP_95J114_125_203_n54,
DP_OP_95J114_125_203_n53, DP_OP_95J114_125_203_n52,
DP_OP_95J114_125_203_n51, DP_OP_95J114_125_203_n50,
DP_OP_95J114_125_203_n49, DP_OP_95J114_125_203_n48,
DP_OP_95J114_125_203_n47, DP_OP_95J114_125_203_n46,
DP_OP_95J114_125_203_n45, DP_OP_95J114_125_203_n44,
DP_OP_95J114_125_203_n43, DP_OP_95J114_125_203_n42,
DP_OP_95J114_125_203_n41, DP_OP_95J114_125_203_n40,
DP_OP_95J114_125_203_n39, DP_OP_95J114_125_203_n38,
DP_OP_95J114_125_203_n37, DP_OP_95J114_125_203_n36,
DP_OP_95J114_125_203_n35, DP_OP_95J114_125_203_n34,
DP_OP_95J114_125_203_n33, DP_OP_95J114_125_203_n32,
DP_OP_95J114_125_203_n31, DP_OP_95J114_125_203_n26,
DP_OP_95J114_125_203_n25, DP_OP_95J114_125_203_n24,
DP_OP_95J114_125_203_n23, DP_OP_95J114_125_203_n22,
DP_OP_95J114_125_203_n21, DP_OP_95J114_125_203_n20,
DP_OP_95J114_125_203_n19, DP_OP_95J114_125_203_n18,
DP_OP_95J114_125_203_n17, DP_OP_95J114_125_203_n16,
DP_OP_95J114_125_203_n15, DP_OP_95J114_125_203_n14,
DP_OP_95J114_125_203_n13, DP_OP_95J114_125_203_n12,
DP_OP_95J114_125_203_n11, DP_OP_95J114_125_203_n10,
DP_OP_95J114_125_203_n9, DP_OP_95J114_125_203_n8,
DP_OP_95J114_125_203_n7, DP_OP_95J114_125_203_n6,
DP_OP_95J114_125_203_n5, DP_OP_95J114_125_203_n4,
DP_OP_95J114_125_203_n3, DP_OP_95J114_125_203_n2,
DP_OP_95J114_125_203_n1, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2011, n2012, n2013, n2014, n2015, n2016,
n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026,
n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036,
n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046,
n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056,
n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066,
n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076,
n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086,
n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096,
n2097, n2098, n2099, n2100, n2101, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357,
n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367,
n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387,
n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397,
n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407,
n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417,
n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477,
n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487,
n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497,
n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507,
n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517,
n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527,
n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537,
n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547,
n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557,
n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567,
n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577,
n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587,
n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597,
n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607,
n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617,
n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627,
n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637,
n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647,
n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657,
n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667,
n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677,
n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687,
n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697,
n2698, n2699, n2700, n2702;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:1] cont_iter_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] d_ff_Yn;
wire [31:0] d_ff_Zn;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [31:0] result_add_subt;
wire [30:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
wire [25:0] add_subt_module_S_A_S_Oper_A;
wire [25:0] add_subt_module_Sgf_normalized_result;
wire [25:0] add_subt_module_Add_Subt_result;
wire [4:0] add_subt_module_LZA_output;
wire [7:0] add_subt_module_S_Oper_A_exp;
wire [7:0] add_subt_module_exp_oper_result;
wire [30:0] add_subt_module_DmP;
wire [30:0] add_subt_module_DMP;
wire [31:0] add_subt_module_intDY;
wire [31:0] add_subt_module_intDX;
wire [1:0] add_subt_module_FSM_selector_B;
wire [3:0] add_subt_module_FS_Module_state_reg;
wire [7:0] add_subt_module_Exp_Operation_Module_Data_S;
wire [25:0] add_subt_module_Add_Subt_Sgf_module_S_to_D;
wire [51:0] add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n1498), .CK(clk), .RN(n2699), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n1497), .CK(clk), .RN(n2698), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n1496), .CK(clk), .RN(n1610), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n1495), .CK(clk), .RN(n2684), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n1494), .CK(clk), .RN(n2700), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n1493), .CK(clk), .RN(n2684), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n1492), .CK(clk), .RN(n2698), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n1491), .CK(clk), .RN(n2680), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n1490), .CK(clk), .RN(n2700), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n1489), .CK(clk), .RN(n1610), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n1488), .CK(clk), .RN(n2697), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n1487), .CK(clk), .RN(n2686), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n1486), .CK(clk), .RN(n2681), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n1485), .CK(clk), .RN(n2698), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n1484), .CK(clk), .RN(n2697), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n1483), .CK(clk), .RN(n2697), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n1482), .CK(clk), .RN(n2698), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n1481), .CK(clk), .RN(n2698), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n1480), .CK(clk), .RN(n2697), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n1479), .CK(clk), .RN(n2697), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n1478), .CK(clk), .RN(n2698), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n1477), .CK(clk), .RN(n2697), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n1476), .CK(clk), .RN(n2698), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n1475), .CK(clk), .RN(n2697), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n1474), .CK(clk), .RN(n2698), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n1473), .CK(clk), .RN(n2697), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n1472), .CK(clk), .RN(n2698), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n1471), .CK(clk), .RN(n2697), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n1470), .CK(clk), .RN(n2698), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n1469), .CK(clk), .RN(n2697), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n1468), .CK(clk), .RN(n2698), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n1467), .CK(clk), .RN(n2697), .Q(d_ff1_Z[31])
);
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(n1463), .CK(clk), .RN(n2698), .Q(
d_ff3_LUT_out[27]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n1462), .CK(clk), .RN(n2697), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n1461), .CK(clk), .RN(n2698), .Q(
d_ff3_LUT_out[25]), .QN(n2659) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n1460), .CK(clk), .RN(n2697), .Q(
d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n1459), .CK(clk), .RN(n2698), .Q(
d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n1458), .CK(clk), .RN(n2696), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n1457), .CK(clk), .RN(n2695), .Q(
d_ff3_LUT_out[21]), .QN(n2657) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n1456), .CK(clk), .RN(n2694), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n1455), .CK(clk), .RN(n2695), .Q(
d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n1454), .CK(clk), .RN(n2696), .Q(
d_ff3_LUT_out[18]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n1453), .CK(clk), .RN(n2694), .Q(
d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n1452), .CK(clk), .RN(n2695), .Q(
d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n1451), .CK(clk), .RN(n2696), .Q(
d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n1450), .CK(clk), .RN(n2694), .Q(
d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n1449), .CK(clk), .RN(n2695), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n1448), .CK(clk), .RN(n2696), .Q(
d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_11_ ( .D(n1447), .CK(clk), .RN(n2694), .Q(
d_ff3_LUT_out[11]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n1446), .CK(clk), .RN(n1530), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n1444), .CK(clk), .RN(n2683), .Q(
d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n1443), .CK(clk), .RN(n1530), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n1442), .CK(clk), .RN(n2693), .Q(
d_ff3_LUT_out[6]), .QN(n2658) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n1441), .CK(clk), .RN(n2683), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n1440), .CK(clk), .RN(n1530), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n1439), .CK(clk), .RN(n2693), .Q(
d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n1438), .CK(clk), .RN(n2683), .Q(
d_ff3_LUT_out[2]), .QN(n2660) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n1437), .CK(clk), .RN(n1530), .Q(
d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n1436), .CK(clk), .RN(n2693), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n1084), .CK(clk), .RN(n2683), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n1085), .CK(clk), .RN(n2686), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n1086), .CK(clk), .RN(n2700), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n1087), .CK(clk), .RN(n2684), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n1088), .CK(clk), .RN(n1610), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n1089), .CK(clk), .RN(n2683), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n1090), .CK(clk), .RN(n2697), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n1419), .CK(clk), .RN(n1610), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n1420), .CK(clk), .RN(n2689), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n1421), .CK(clk), .RN(n1560), .Q(
d_ff3_sh_x_out[28]), .QN(n2661) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n1422), .CK(clk), .RN(n2681), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n1423), .CK(clk), .RN(n2692), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n1424), .CK(clk), .RN(n2694), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n1425), .CK(clk), .RN(n2681), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n1426), .CK(clk), .RN(n2679), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n1373), .CK(clk), .RN(n2679), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ (
.D(n1331), .CK(clk), .RN(n1562), .Q(add_subt_module_LZA_output[0]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n1435), .CK(clk), .RN(n2695), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(n1371), .CK(clk), .RN(n2696), .Q(
d_ff_Yn[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n1082), .CK(clk), .RN(n2694), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff5_Q_reg_31_ ( .D(n1018), .CK(clk), .RN(n2695), .Q(
data_output2_31_) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n1016), .CK(clk), .RN(n2696), .Q(
data_output[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n1370), .CK(clk), .RN(n2694), .Q(
d_ff_Zn[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n1300), .CK(clk), .RN(n2695), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n1299), .CK(clk), .RN(n2694), .Q(
d_ff_Yn[30]), .QN(n1556) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(n1020), .CK(clk), .RN(n1560), .Q(
sign_inv_out[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n1019), .CK(clk), .RN(n1560), .Q(
data_output[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n1296), .CK(clk), .RN(n1560), .Q(
d_ff_Zn[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n1295), .CK(clk), .RN(n1560), .Q(
d_ff_Yn[29]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(n1022), .CK(clk), .RN(n1560), .Q(
sign_inv_out[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n1021), .CK(clk), .RN(n2679), .Q(
data_output[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n1292), .CK(clk), .RN(n2696), .Q(
d_ff_Zn[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n1291), .CK(clk), .RN(n2688), .Q(
d_ff_Yn[28]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(n1024), .CK(clk), .RN(n2679), .Q(
sign_inv_out[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n1023), .CK(clk), .RN(n2690), .Q(
data_output[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n1288), .CK(clk), .RN(n2679), .Q(
d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1152), .CK(clk), .RN(n2688),
.Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n1287), .CK(clk), .RN(n2679), .Q(
d_ff_Yn[27]), .QN(n1557) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_27_ ( .D(n1095), .CK(clk), .RN(n1530),
.QN(n1541) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_27_ ( .D(n1431), .CK(clk), .RN(n1530),
.QN(n1540) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n1026), .CK(clk), .RN(n1530), .Q(
sign_inv_out[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n1025), .CK(clk), .RN(n1530), .Q(
data_output[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n1284), .CK(clk), .RN(n1530), .Q(
d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1153), .CK(clk), .RN(n1530),
.Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n1283), .CK(clk), .RN(n1530), .Q(
d_ff_Yn[26]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(n1028), .CK(clk), .RN(n2693), .Q(
sign_inv_out[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n1027), .CK(clk), .RN(n2696), .Q(
data_output[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n1280), .CK(clk), .RN(n2694), .Q(
d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1154), .CK(clk), .RN(n2694),
.Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n1279), .CK(clk), .RN(n2695), .Q(
d_ff_Yn[25]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_25_ ( .D(n1097), .CK(clk), .RN(n2696),
.QN(n1539) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_25_ ( .D(n1429), .CK(clk), .RN(n2695),
.QN(n1538) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(n1030), .CK(clk), .RN(n2696), .Q(
sign_inv_out[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n1029), .CK(clk), .RN(n2694), .Q(
data_output[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n1276), .CK(clk), .RN(n2695), .Q(
d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1155), .CK(clk), .RN(n2696),
.Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n1275), .CK(clk), .RN(n2694), .Q(
d_ff_Yn[24]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(n1032), .CK(clk), .RN(n2683), .Q(
sign_inv_out[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n1031), .CK(clk), .RN(n2693), .Q(
data_output[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n1272), .CK(clk), .RN(n1530), .Q(
d_ff_Zn[23]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n1271), .CK(clk), .RN(n2693), .Q(
d_ff_Yn[23]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n1034), .CK(clk), .RN(n1530), .Q(
sign_inv_out[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n1033), .CK(clk), .RN(n1530), .Q(
data_output[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n1180), .CK(clk), .RN(n2693), .Q(d_ff_Zn[0])
);
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n1146), .CK(clk), .RN(n2693), .Q(d_ff_Yn[0])
);
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]),
.CK(clk), .RN(n2665), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n1268), .CK(clk), .RN(n1530), .Q(
d_ff_Zn[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n1267), .CK(clk), .RN(n2693), .Q(
d_ff_Yn[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n1100), .CK(clk), .RN(n1530), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n1417), .CK(clk), .RN(n2692), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n1204), .CK(clk), .RN(n2692), .Q(d_ff_Zn[6])
);
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n1203), .CK(clk), .RN(n2692), .Q(d_ff_Yn[6])
);
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n1132), .CK(clk), .RN(n2692), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n1385), .CK(clk), .RN(n2692), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n1192), .CK(clk), .RN(n2692), .Q(d_ff_Zn[3])
);
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n1191), .CK(clk), .RN(n2692), .Q(d_ff_Yn[3])
);
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n1138), .CK(clk), .RN(n2689), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n1379), .CK(clk), .RN(n2689), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n1256), .CK(clk), .RN(n2687), .Q(
d_ff_Zn[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n1255), .CK(clk), .RN(n2687), .Q(
d_ff_Yn[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n1106), .CK(clk), .RN(n2689), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n1411), .CK(clk), .RN(n2691), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(n1042), .CK(clk), .RN(n1610), .Q(
sign_inv_out[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n1041), .CK(clk), .RN(n2690), .Q(
data_output[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n1188), .CK(clk), .RN(n2690), .Q(d_ff_Zn[2])
);
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n1187), .CK(clk), .RN(n2690), .Q(d_ff_Yn[2])
);
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n1140), .CK(clk), .RN(n1610), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n1377), .CK(clk), .RN(n2690), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n1264), .CK(clk), .RN(n2687), .Q(
d_ff_Zn[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n1263), .CK(clk), .RN(n2688), .Q(
d_ff_Yn[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n1102), .CK(clk), .RN(n1530), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n1415), .CK(clk), .RN(n2691), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n1252), .CK(clk), .RN(n2687), .Q(
d_ff_Zn[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n1251), .CK(clk), .RN(n2687), .Q(
d_ff_Yn[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n1108), .CK(clk), .RN(n2688), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n1409), .CK(clk), .RN(n1530), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(n1044), .CK(clk), .RN(n2687), .Q(
sign_inv_out[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n1043), .CK(clk), .RN(n2691), .Q(
data_output[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n1240), .CK(clk), .RN(n2688), .Q(
d_ff_Zn[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n1239), .CK(clk), .RN(n1610), .Q(
d_ff_Yn[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n1114), .CK(clk), .RN(n2691), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n1403), .CK(clk), .RN(n2690), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n1212), .CK(clk), .RN(n2689), .Q(d_ff_Zn[8])
);
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n1211), .CK(clk), .RN(n2683), .Q(d_ff_Yn[8])
);
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n1128), .CK(clk), .RN(n2688), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n1389), .CK(clk), .RN(n2687), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n1184), .CK(clk), .RN(n1610), .Q(d_ff_Zn[1])
);
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n1183), .CK(clk), .RN(n1530), .Q(d_ff_Yn[1])
);
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n1142), .CK(clk), .RN(n2690), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n1375), .CK(clk), .RN(n2689), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n1260), .CK(clk), .RN(n2689), .Q(
d_ff_Zn[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n1259), .CK(clk), .RN(n2688), .Q(
d_ff_Yn[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n1104), .CK(clk), .RN(n2691), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n1413), .CK(clk), .RN(n2683), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(n1040), .CK(clk), .RN(n2689), .Q(
sign_inv_out[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n1039), .CK(clk), .RN(n2691), .Q(
data_output[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n1232), .CK(clk), .RN(n2690), .Q(
d_ff_Zn[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n1231), .CK(clk), .RN(n1610), .Q(
d_ff_Yn[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n1118), .CK(clk), .RN(n2687), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n1399), .CK(clk), .RN(n1610), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(n1054), .CK(clk), .RN(n2693), .Q(
sign_inv_out[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n1053), .CK(clk), .RN(n2686), .Q(
data_output[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n1200), .CK(clk), .RN(n2686), .Q(d_ff_Zn[5])
);
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n1199), .CK(clk), .RN(n2686), .Q(d_ff_Yn[5])
);
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n1134), .CK(clk), .RN(n2686), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n1383), .CK(clk), .RN(n2686), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n1248), .CK(clk), .RN(n2686), .Q(
d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1162), .CK(clk), .RN(n2686),
.Q(d_ff2_Z[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n1247), .CK(clk), .RN(n2686), .Q(
d_ff_Yn[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n1110), .CK(clk), .RN(n2685), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n1407), .CK(clk), .RN(n2685), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(n1046), .CK(clk), .RN(n2685), .Q(
sign_inv_out[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n1045), .CK(clk), .RN(n2685), .Q(
data_output[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n1196), .CK(clk), .RN(n2685), .Q(d_ff_Zn[4])
);
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n1195), .CK(clk), .RN(n2685), .Q(d_ff_Yn[4])
);
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n1136), .CK(clk), .RN(n2685), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n1381), .CK(clk), .RN(n2684), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n1244), .CK(clk), .RN(n2684), .Q(
d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1163), .CK(clk), .RN(n2684),
.Q(d_ff2_Z[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n1243), .CK(clk), .RN(n2684), .Q(
d_ff_Yn[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n1112), .CK(clk), .RN(n2684), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n1405), .CK(clk), .RN(n2684), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(n1048), .CK(clk), .RN(n2684), .Q(
sign_inv_out[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n1047), .CK(clk), .RN(n2700), .Q(
data_output[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n1220), .CK(clk), .RN(n2683), .Q(
d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1169), .CK(clk), .RN(n2700),
.Q(d_ff2_Z[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n1219), .CK(clk), .RN(n2683), .Q(
d_ff_Yn[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n1124), .CK(clk), .RN(n2700), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n1393), .CK(clk), .RN(n2683), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n1236), .CK(clk), .RN(n2700), .Q(
d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1165), .CK(clk), .RN(n2683),
.Q(d_ff2_Z[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n1235), .CK(clk), .RN(n2700), .Q(
d_ff_Yn[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n1116), .CK(clk), .RN(n2682), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n1401), .CK(clk), .RN(n2682), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(n1052), .CK(clk), .RN(n2682), .Q(
sign_inv_out[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n1051), .CK(clk), .RN(n2682), .Q(
data_output[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n1208), .CK(clk), .RN(n2682), .Q(d_ff_Zn[7])
);
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n1207), .CK(clk), .RN(n2682), .Q(d_ff_Yn[7])
);
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n1130), .CK(clk), .RN(n1610), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n1387), .CK(clk), .RN(n2691), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n1224), .CK(clk), .RN(n2687), .Q(
d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1168), .CK(clk), .RN(n2689),
.Q(d_ff2_Z[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n1223), .CK(clk), .RN(n2691), .Q(
d_ff_Yn[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n1122), .CK(clk), .RN(n2685), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n1395), .CK(clk), .RN(n2685), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n1228), .CK(clk), .RN(n2680), .Q(
d_ff_Zn[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n1227), .CK(clk), .RN(n2681), .Q(
d_ff_Yn[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n1120), .CK(clk), .RN(n2681), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n1397), .CK(clk), .RN(n2681), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(n1056), .CK(clk), .RN(n2681), .Q(
sign_inv_out[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n1055), .CK(clk), .RN(n1610), .Q(
data_output[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n1216), .CK(clk), .RN(n2681), .Q(d_ff_Zn[9])
);
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n1215), .CK(clk), .RN(n2681), .Q(d_ff_Yn[9])
);
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n1126), .CK(clk), .RN(n2680), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n1391), .CK(clk), .RN(n2680), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(n1062), .CK(clk), .RN(n2680), .Q(
sign_inv_out[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n1061), .CK(clk), .RN(n2680), .Q(
data_output[9]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(n1058), .CK(clk), .RN(n2680), .Q(
sign_inv_out[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n1057), .CK(clk), .RN(n2680), .Q(
data_output[11]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(n1066), .CK(clk), .RN(n2680), .Q(
sign_inv_out[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n1065), .CK(clk), .RN(n2680), .Q(
data_output[7]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(n1060), .CK(clk), .RN(n2680), .Q(
sign_inv_out[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n1059), .CK(clk), .RN(n2695), .Q(
data_output[10]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(n1072), .CK(clk), .RN(n2679), .Q(
sign_inv_out[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n1071), .CK(clk), .RN(n2692), .Q(
data_output[4]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(n1070), .CK(clk), .RN(n2679), .Q(
sign_inv_out[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n1069), .CK(clk), .RN(n2692), .Q(
data_output[5]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(n1078), .CK(clk), .RN(n2679), .Q(
sign_inv_out[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n1077), .CK(clk), .RN(n2696), .Q(
data_output[1]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(n1064), .CK(clk), .RN(n2679), .Q(
sign_inv_out[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n1063), .CK(clk), .RN(n2695), .Q(
data_output[8]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(n1050), .CK(clk), .RN(n2679), .Q(
sign_inv_out[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n1049), .CK(clk), .RN(n2692), .Q(
data_output[15]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(n1038), .CK(clk), .RN(n2679), .Q(
sign_inv_out[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n1037), .CK(clk), .RN(n2683), .Q(
data_output[21]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(n1076), .CK(clk), .RN(n2686), .Q(
sign_inv_out[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n1075), .CK(clk), .RN(n1560), .Q(
data_output[2]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(n1074), .CK(clk), .RN(n2700), .Q(
sign_inv_out[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n1073), .CK(clk), .RN(n2680), .Q(
data_output[3]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(n1068), .CK(clk), .RN(n1560), .Q(
sign_inv_out[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n1067), .CK(clk), .RN(n2683), .Q(
data_output[6]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(n1036), .CK(clk), .RN(n2698), .Q(
sign_inv_out[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n1035), .CK(clk), .RN(n1560), .Q(
data_output[22]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]),
.CK(clk), .RN(n2667), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n1144), .CK(clk), .RN(n2700), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(n1080), .CK(clk), .RN(n1560), .Q(
sign_inv_out[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n1079), .CK(clk), .RN(n1560), .Q(
data_output[0]) );
DFFRXLTS add_subt_module_YRegister_Q_reg_31_ ( .D(n1004), .CK(clk), .RN(
n2671), .Q(add_subt_module_intDY[31]) );
DFFRXLTS add_subt_module_ASRegister_Q_reg_0_ ( .D(n1002), .CK(clk), .RN(
n1561), .Q(add_subt_module_intAS) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n999),
.CK(clk), .RN(n2674), .Q(add_subt_module_DmP[30]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n998),
.CK(clk), .RN(n2675), .Q(add_subt_module_DMP[30]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n996),
.CK(clk), .RN(n2668), .Q(add_subt_module_DmP[29]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n995),
.CK(clk), .RN(n2673), .Q(add_subt_module_DMP[29]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n993),
.CK(clk), .RN(n2675), .Q(add_subt_module_DmP[28]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n992),
.CK(clk), .RN(n1532), .Q(add_subt_module_DMP[28]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n990),
.CK(clk), .RN(n2673), .Q(add_subt_module_DmP[27]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n989),
.CK(clk), .RN(n2674), .Q(add_subt_module_DMP[27]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n987),
.CK(clk), .RN(n2668), .Q(add_subt_module_DmP[26]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n986),
.CK(clk), .RN(n1532), .Q(add_subt_module_DMP[26]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n984),
.CK(clk), .RN(n2675), .Q(add_subt_module_DmP[25]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n983),
.CK(clk), .RN(n2674), .Q(add_subt_module_DMP[25]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n981),
.CK(clk), .RN(n2673), .Q(add_subt_module_DmP[24]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n980),
.CK(clk), .RN(n1532), .Q(add_subt_module_DMP[24]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n978),
.CK(clk), .RN(n2668), .Q(add_subt_module_DmP[23]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n977),
.CK(clk), .RN(n1532), .Q(add_subt_module_DMP[23]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n963),
.CK(clk), .RN(n2669), .Q(add_subt_module_DmP[19]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n962),
.CK(clk), .RN(n2677), .Q(add_subt_module_DMP[19]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n953),
.CK(clk), .RN(n2669), .Q(add_subt_module_DmP[18]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n952),
.CK(clk), .RN(n1532), .Q(add_subt_module_DMP[18]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n939),
.CK(clk), .RN(n2677), .Q(add_subt_module_DMP[20]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n935),
.CK(clk), .RN(n2674), .Q(add_subt_module_DMP[13]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n928),
.CK(clk), .RN(n2674), .Q(add_subt_module_DMP[17]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n921),
.CK(clk), .RN(n1532), .Q(add_subt_module_DMP[16]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n914),
.CK(clk), .RN(n1532), .Q(add_subt_module_DMP[14]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n911),
.CK(clk), .RN(n1562), .QN(n1542) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n908),
.CK(clk), .RN(n1562), .Q(add_subt_module_DmP[11]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n905),
.CK(clk), .RN(n2666), .QN(n1543) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n896),
.CK(clk), .RN(n2676), .Q(add_subt_module_DMP[4]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n895),
.CK(clk), .RN(n2676), .Q(add_subt_module_DMP[5]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n894),
.CK(clk), .RN(n2676), .Q(add_subt_module_DMP[1]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n892),
.CK(clk), .RN(n2674), .Q(add_subt_module_DMP[15]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n891),
.CK(clk), .RN(n2677), .Q(add_subt_module_DMP[21]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n890),
.CK(clk), .RN(n2676), .Q(add_subt_module_DMP[2]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n889),
.CK(clk), .RN(n2676), .Q(add_subt_module_DMP[3]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n888),
.CK(clk), .RN(n2676), .Q(add_subt_module_DMP[6]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n887),
.CK(clk), .RN(n2677), .Q(add_subt_module_DMP[22]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n886),
.CK(clk), .RN(n2668), .Q(add_subt_module_DMP[0]) );
CMPR32X2TS DP_OP_92J114_122_1254_U9 ( .A(add_subt_module_S_Oper_A_exp[0]),
.B(n2110), .C(DP_OP_92J114_122_1254_n20), .CO(DP_OP_92J114_122_1254_n8), .S(add_subt_module_Exp_Operation_Module_Data_S[0]) );
CMPR32X2TS DP_OP_92J114_122_1254_U8 ( .A(DP_OP_92J114_122_1254_n19), .B(
add_subt_module_S_Oper_A_exp[1]), .C(DP_OP_92J114_122_1254_n8), .CO(
DP_OP_92J114_122_1254_n7), .S(
add_subt_module_Exp_Operation_Module_Data_S[1]) );
CMPR32X2TS DP_OP_92J114_122_1254_U7 ( .A(DP_OP_92J114_122_1254_n18), .B(
add_subt_module_S_Oper_A_exp[2]), .C(DP_OP_92J114_122_1254_n7), .CO(
DP_OP_92J114_122_1254_n6), .S(
add_subt_module_Exp_Operation_Module_Data_S[2]) );
CMPR32X2TS DP_OP_92J114_122_1254_U6 ( .A(DP_OP_92J114_122_1254_n17), .B(
add_subt_module_S_Oper_A_exp[3]), .C(DP_OP_92J114_122_1254_n6), .CO(
DP_OP_92J114_122_1254_n5), .S(
add_subt_module_Exp_Operation_Module_Data_S[3]) );
CMPR32X2TS DP_OP_92J114_122_1254_U5 ( .A(DP_OP_92J114_122_1254_n16), .B(
add_subt_module_S_Oper_A_exp[4]), .C(DP_OP_92J114_122_1254_n5), .CO(
DP_OP_92J114_122_1254_n4), .S(
add_subt_module_Exp_Operation_Module_Data_S[4]) );
CMPR32X2TS DP_OP_92J114_122_1254_U4 ( .A(DP_OP_92J114_122_1254_n15), .B(
add_subt_module_S_Oper_A_exp[5]), .C(DP_OP_92J114_122_1254_n4), .CO(
DP_OP_92J114_122_1254_n3), .S(
add_subt_module_Exp_Operation_Module_Data_S[5]) );
CMPR32X2TS DP_OP_92J114_122_1254_U3 ( .A(DP_OP_92J114_122_1254_n14), .B(
add_subt_module_S_Oper_A_exp[6]), .C(DP_OP_92J114_122_1254_n3), .CO(
DP_OP_92J114_122_1254_n2), .S(
add_subt_module_Exp_Operation_Module_Data_S[6]) );
CMPR32X2TS DP_OP_92J114_122_1254_U2 ( .A(DP_OP_92J114_122_1254_n13), .B(
add_subt_module_S_Oper_A_exp[7]), .C(DP_OP_92J114_122_1254_n2), .CO(
DP_OP_92J114_122_1254_n1), .S(
add_subt_module_Exp_Operation_Module_Data_S[7]) );
CMPR32X2TS DP_OP_95J114_125_203_U26 ( .A(DP_OP_95J114_125_203_n55), .B(
add_subt_module_S_A_S_Oper_A[1]), .C(DP_OP_95J114_125_203_n26), .CO(
DP_OP_95J114_125_203_n25), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[1]) );
CMPR32X2TS DP_OP_95J114_125_203_U25 ( .A(DP_OP_95J114_125_203_n54), .B(
add_subt_module_S_A_S_Oper_A[2]), .C(DP_OP_95J114_125_203_n25), .CO(
DP_OP_95J114_125_203_n24), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[2]) );
CMPR32X2TS DP_OP_95J114_125_203_U24 ( .A(DP_OP_95J114_125_203_n53), .B(
add_subt_module_S_A_S_Oper_A[3]), .C(DP_OP_95J114_125_203_n24), .CO(
DP_OP_95J114_125_203_n23), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[3]) );
CMPR32X2TS DP_OP_95J114_125_203_U23 ( .A(DP_OP_95J114_125_203_n52), .B(
add_subt_module_S_A_S_Oper_A[4]), .C(DP_OP_95J114_125_203_n23), .CO(
DP_OP_95J114_125_203_n22), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[4]) );
CMPR32X2TS DP_OP_95J114_125_203_U22 ( .A(DP_OP_95J114_125_203_n51), .B(
add_subt_module_S_A_S_Oper_A[5]), .C(DP_OP_95J114_125_203_n22), .CO(
DP_OP_95J114_125_203_n21), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[5]) );
CMPR32X2TS DP_OP_95J114_125_203_U21 ( .A(DP_OP_95J114_125_203_n50), .B(
add_subt_module_S_A_S_Oper_A[6]), .C(DP_OP_95J114_125_203_n21), .CO(
DP_OP_95J114_125_203_n20), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[6]) );
CMPR32X2TS DP_OP_95J114_125_203_U20 ( .A(DP_OP_95J114_125_203_n49), .B(
add_subt_module_S_A_S_Oper_A[7]), .C(DP_OP_95J114_125_203_n20), .CO(
DP_OP_95J114_125_203_n19), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[7]) );
CMPR32X2TS DP_OP_95J114_125_203_U19 ( .A(DP_OP_95J114_125_203_n48), .B(
add_subt_module_S_A_S_Oper_A[8]), .C(DP_OP_95J114_125_203_n19), .CO(
DP_OP_95J114_125_203_n18), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[8]) );
CMPR32X2TS DP_OP_95J114_125_203_U18 ( .A(DP_OP_95J114_125_203_n47), .B(
add_subt_module_S_A_S_Oper_A[9]), .C(DP_OP_95J114_125_203_n18), .CO(
DP_OP_95J114_125_203_n17), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[9]) );
CMPR32X2TS DP_OP_95J114_125_203_U17 ( .A(DP_OP_95J114_125_203_n46), .B(
add_subt_module_S_A_S_Oper_A[10]), .C(DP_OP_95J114_125_203_n17), .CO(
DP_OP_95J114_125_203_n16), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[10]) );
CMPR32X2TS DP_OP_95J114_125_203_U16 ( .A(DP_OP_95J114_125_203_n45), .B(
add_subt_module_S_A_S_Oper_A[11]), .C(DP_OP_95J114_125_203_n16), .CO(
DP_OP_95J114_125_203_n15), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[11]) );
CMPR32X2TS DP_OP_95J114_125_203_U15 ( .A(DP_OP_95J114_125_203_n44), .B(
add_subt_module_S_A_S_Oper_A[12]), .C(DP_OP_95J114_125_203_n15), .CO(
DP_OP_95J114_125_203_n14), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[12]) );
CMPR32X2TS DP_OP_95J114_125_203_U14 ( .A(DP_OP_95J114_125_203_n43), .B(
add_subt_module_S_A_S_Oper_A[13]), .C(DP_OP_95J114_125_203_n14), .CO(
DP_OP_95J114_125_203_n13), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[13]) );
CMPR32X2TS DP_OP_95J114_125_203_U13 ( .A(DP_OP_95J114_125_203_n42), .B(
add_subt_module_S_A_S_Oper_A[14]), .C(DP_OP_95J114_125_203_n13), .CO(
DP_OP_95J114_125_203_n12), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[14]) );
CMPR32X2TS DP_OP_95J114_125_203_U12 ( .A(DP_OP_95J114_125_203_n41), .B(
add_subt_module_S_A_S_Oper_A[15]), .C(DP_OP_95J114_125_203_n12), .CO(
DP_OP_95J114_125_203_n11), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[15]) );
CMPR32X2TS DP_OP_95J114_125_203_U11 ( .A(DP_OP_95J114_125_203_n40), .B(
add_subt_module_S_A_S_Oper_A[16]), .C(DP_OP_95J114_125_203_n11), .CO(
DP_OP_95J114_125_203_n10), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[16]) );
CMPR32X2TS DP_OP_95J114_125_203_U10 ( .A(DP_OP_95J114_125_203_n39), .B(
add_subt_module_S_A_S_Oper_A[17]), .C(DP_OP_95J114_125_203_n10), .CO(
DP_OP_95J114_125_203_n9), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[17]) );
CMPR32X2TS DP_OP_95J114_125_203_U9 ( .A(DP_OP_95J114_125_203_n38), .B(
add_subt_module_S_A_S_Oper_A[18]), .C(DP_OP_95J114_125_203_n9), .CO(
DP_OP_95J114_125_203_n8), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[18]) );
CMPR32X2TS DP_OP_95J114_125_203_U8 ( .A(DP_OP_95J114_125_203_n37), .B(
add_subt_module_S_A_S_Oper_A[19]), .C(DP_OP_95J114_125_203_n8), .CO(
DP_OP_95J114_125_203_n7), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[19]) );
CMPR32X2TS DP_OP_95J114_125_203_U7 ( .A(DP_OP_95J114_125_203_n36), .B(
add_subt_module_S_A_S_Oper_A[20]), .C(DP_OP_95J114_125_203_n7), .CO(
DP_OP_95J114_125_203_n6), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[20]) );
CMPR32X2TS DP_OP_95J114_125_203_U6 ( .A(DP_OP_95J114_125_203_n35), .B(
add_subt_module_S_A_S_Oper_A[21]), .C(DP_OP_95J114_125_203_n6), .CO(
DP_OP_95J114_125_203_n5), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[21]) );
CMPR32X2TS DP_OP_95J114_125_203_U5 ( .A(DP_OP_95J114_125_203_n34), .B(
add_subt_module_S_A_S_Oper_A[22]), .C(DP_OP_95J114_125_203_n5), .CO(
DP_OP_95J114_125_203_n4), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[22]) );
CMPR32X2TS DP_OP_95J114_125_203_U4 ( .A(DP_OP_95J114_125_203_n33), .B(
add_subt_module_S_A_S_Oper_A[23]), .C(DP_OP_95J114_125_203_n4), .CO(
DP_OP_95J114_125_203_n3), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[23]) );
CMPR32X2TS DP_OP_95J114_125_203_U3 ( .A(DP_OP_95J114_125_203_n32), .B(
add_subt_module_S_A_S_Oper_A[24]), .C(DP_OP_95J114_125_203_n3), .CO(
DP_OP_95J114_125_203_n2), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[24]) );
CMPR32X2TS DP_OP_95J114_125_203_U2 ( .A(DP_OP_95J114_125_203_n31), .B(
add_subt_module_S_A_S_Oper_A[25]), .C(DP_OP_95J114_125_203_n2), .CO(
DP_OP_95J114_125_203_n1), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[25]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n1515),
.CK(clk), .RN(n1532), .Q(underflow_flag), .QN(n2656) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n1094), .CK(clk), .RN(n2695),
.Q(d_ff2_Y[28]), .QN(n2654) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]),
.CK(clk), .RN(n2666), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]), .QN(
n2653) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]),
.CK(clk), .RN(n2665), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]), .QN(
n2652) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(
n1326), .CK(clk), .RN(n2677), .Q(
add_subt_module_Sgf_normalized_result[24]), .QN(n2651) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(
n1354), .CK(clk), .RN(n2672), .Q(add_subt_module_Add_Subt_result[21]),
.QN(n2650) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n1501), .CK(clk), .RN(n2699), .Q(
d_ff1_operation_out), .QN(n2649) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(
n1350), .CK(clk), .RN(n2674), .Q(add_subt_module_Add_Subt_result[17]),
.QN(n2648) );
DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n1465), .CK(clk), .RN(n2697), .Q(
sel_mux_2_reg[0]), .QN(n2647) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(
n1324), .CK(clk), .RN(n2677), .Q(
add_subt_module_Sgf_normalized_result[22]), .QN(n2646) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(
n1325), .CK(clk), .RN(n2677), .Q(
add_subt_module_Sgf_normalized_result[23]), .QN(n2645) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(
n1352), .CK(clk), .RN(n2672), .Q(add_subt_module_Add_Subt_result[19]),
.QN(n2644) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(
n1340), .CK(clk), .RN(n2672), .Q(add_subt_module_Add_Subt_result[7]),
.QN(n2643) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(
n1344), .CK(clk), .RN(n2674), .Q(add_subt_module_Add_Subt_result[11]),
.QN(n2642) );
DFFRX1TS add_subt_module_Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(
n1001), .CK(clk), .RN(n1533), .Q(add_subt_module_sign_final_result),
.QN(n2641) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(
n1323), .CK(clk), .RN(n2677), .Q(
add_subt_module_Sgf_normalized_result[21]), .QN(n2640) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(
n1338), .CK(clk), .RN(n2672), .Q(add_subt_module_Add_Subt_result[5]),
.QN(n2639) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(
n1357), .CK(clk), .RN(n2672), .Q(add_subt_module_Add_Subt_result[24]),
.QN(n2638) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(
n1335), .CK(clk), .RN(n2672), .Q(add_subt_module_Add_Subt_result[2]),
.QN(n2637) );
DFFRX2TS add_subt_module_YRegister_Q_reg_23_ ( .D(n1005), .CK(clk), .RN(
n1562), .Q(add_subt_module_intDY[23]), .QN(n2636) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n1428), .CK(clk), .RN(n2693),
.Q(d_ff2_X[24]), .QN(n2635) );
DFFRX1TS cont_var_count_reg_0_ ( .D(n1507), .CK(clk), .RN(n2699), .Q(
cont_var_out[0]), .QN(n2633) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n1098), .CK(clk), .RN(n1530),
.Q(d_ff2_Y[24]), .QN(n2632) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(
n1322), .CK(clk), .RN(n2674), .Q(
add_subt_module_Sgf_normalized_result[20]), .QN(n2630) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(
n1336), .CK(clk), .RN(n2672), .Q(add_subt_module_Add_Subt_result[3]),
.QN(n2629) );
DFFRX2TS add_subt_module_XRegister_Q_reg_23_ ( .D(n979), .CK(clk), .RN(n2673), .Q(add_subt_module_intDX[23]), .QN(n2628) );
DFFRX2TS add_subt_module_XRegister_Q_reg_16_ ( .D(n924), .CK(clk), .RN(n2670), .Q(add_subt_module_intDX[16]), .QN(n2626) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(
n1319), .CK(clk), .RN(n2674), .Q(
add_subt_module_Sgf_normalized_result[17]), .QN(n2625) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(
n1320), .CK(clk), .RN(n2674), .Q(
add_subt_module_Sgf_normalized_result[18]), .QN(n2624) );
DFFRX2TS add_subt_module_YRegister_Q_reg_25_ ( .D(n1007), .CK(clk), .RN(
n2674), .Q(add_subt_module_intDY[25]), .QN(n2623) );
DFFRX2TS add_subt_module_YRegister_Q_reg_26_ ( .D(n1008), .CK(clk), .RN(
n2667), .Q(add_subt_module_intDY[26]), .QN(n2622) );
DFFRX2TS add_subt_module_XRegister_Q_reg_6_ ( .D(n971), .CK(clk), .RN(n2675),
.Q(add_subt_module_intDX[6]), .QN(n2621) );
DFFRX1TS add_subt_module_XRegister_Q_reg_2_ ( .D(n961), .CK(clk), .RN(n2670),
.Q(add_subt_module_intDX[2]), .QN(n2620) );
DFFRX2TS add_subt_module_XRegister_Q_reg_4_ ( .D(n927), .CK(clk), .RN(n1532),
.Q(add_subt_module_intDX[4]), .QN(n2619) );
DFFRX1TS add_subt_module_XRegister_Q_reg_11_ ( .D(n910), .CK(clk), .RN(n1561), .Q(add_subt_module_intDX[11]), .QN(n2618) );
DFFRX2TS add_subt_module_YRegister_Q_reg_12_ ( .D(n906), .CK(clk), .RN(n1562), .Q(add_subt_module_intDY[12]), .QN(n2617) );
DFFRX1TS add_subt_module_XRegister_Q_reg_14_ ( .D(n917), .CK(clk), .RN(n2670), .Q(add_subt_module_intDX[14]), .QN(n2616) );
DFFRX1TS add_subt_module_XRegister_Q_reg_19_ ( .D(n965), .CK(clk), .RN(n2672), .Q(add_subt_module_intDX[19]), .QN(n2615) );
DFFRX1TS add_subt_module_YRegister_Q_reg_24_ ( .D(n1006), .CK(clk), .RN(
n2671), .Q(add_subt_module_intDY[24]), .QN(n2614) );
DFFRX1TS add_subt_module_YRegister_Q_reg_0_ ( .D(n1013), .CK(clk), .RN(n2667), .Q(add_subt_module_intDY[0]), .QN(n2613) );
DFFRX1TS add_subt_module_XRegister_Q_reg_22_ ( .D(n974), .CK(clk), .RN(n2675), .Q(add_subt_module_intDX[22]), .QN(n2612) );
DFFRX1TS add_subt_module_XRegister_Q_reg_8_ ( .D(n948), .CK(clk), .RN(n2669),
.Q(add_subt_module_intDX[8]), .QN(n2611) );
DFFRX2TS add_subt_module_XRegister_Q_reg_10_ ( .D(n920), .CK(clk), .RN(n2670), .Q(add_subt_module_intDX[10]), .QN(n2610) );
DFFRX1TS add_subt_module_XRegister_Q_reg_17_ ( .D(n931), .CK(clk), .RN(n2672), .Q(add_subt_module_intDX[17]), .QN(n2609) );
DFFRX1TS add_subt_module_XRegister_Q_reg_20_ ( .D(n942), .CK(clk), .RN(n2669), .Q(add_subt_module_intDX[20]), .QN(n2608) );
DFFRX1TS add_subt_module_XRegister_Q_reg_18_ ( .D(n955), .CK(clk), .RN(n2665), .Q(add_subt_module_intDX[18]), .QN(n2607) );
DFFRX2TS add_subt_module_YRegister_Q_reg_28_ ( .D(n1010), .CK(clk), .RN(
n2667), .Q(add_subt_module_intDY[28]), .QN(n2606) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(
n1317), .CK(clk), .RN(n1532), .Q(
add_subt_module_Sgf_normalized_result[15]), .QN(n2605) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(
n1318), .CK(clk), .RN(n1532), .Q(
add_subt_module_Sgf_normalized_result[16]), .QN(n2604) );
DFFRX2TS add_subt_module_YRegister_Q_reg_18_ ( .D(n954), .CK(clk), .RN(n2669), .Q(add_subt_module_intDY[18]), .QN(n2603) );
DFFRX2TS add_subt_module_YRegister_Q_reg_21_ ( .D(n957), .CK(clk), .RN(n2673), .Q(add_subt_module_intDY[21]), .QN(n2602) );
DFFRX1TS add_subt_module_XRegister_Q_reg_13_ ( .D(n938), .CK(clk), .RN(n2670), .Q(add_subt_module_intDX[13]), .QN(n2601) );
DFFRX1TS add_subt_module_XRegister_Q_reg_3_ ( .D(n968), .CK(clk), .RN(n2673),
.Q(add_subt_module_intDX[3]), .QN(n2600) );
DFFRX2TS add_subt_module_Sel_B_Q_reg_0_ ( .D(n1369), .CK(clk), .RN(n1014),
.Q(add_subt_module_FSM_selector_B[0]), .QN(n2599) );
DFFRX2TS add_subt_module_YRegister_Q_reg_11_ ( .D(n909), .CK(clk), .RN(n2666), .Q(add_subt_module_intDY[11]), .QN(n2597) );
DFFRX2TS add_subt_module_YRegister_Q_reg_8_ ( .D(n947), .CK(clk), .RN(n2669),
.Q(add_subt_module_intDY[8]), .QN(n2596) );
DFFRX2TS add_subt_module_YRegister_Q_reg_17_ ( .D(n930), .CK(clk), .RN(n2667), .Q(add_subt_module_intDY[17]), .QN(n2595) );
DFFRX2TS add_subt_module_YRegister_Q_reg_13_ ( .D(n937), .CK(clk), .RN(n2665), .Q(add_subt_module_intDY[13]), .QN(n2594) );
DFFRX2TS add_subt_module_XRegister_Q_reg_28_ ( .D(n994), .CK(clk), .RN(n1533), .Q(add_subt_module_intDX[28]), .QN(n2593) );
DFFRX2TS add_subt_module_YRegister_Q_reg_20_ ( .D(n941), .CK(clk), .RN(n2670), .Q(add_subt_module_intDY[20]), .QN(n2592) );
DFFRX2TS add_subt_module_YRegister_Q_reg_1_ ( .D(n944), .CK(clk), .RN(n2669),
.Q(add_subt_module_intDY[1]), .QN(n2591) );
DFFRX2TS add_subt_module_YRegister_Q_reg_14_ ( .D(n916), .CK(clk), .RN(n2670), .Q(add_subt_module_intDY[14]), .QN(n2590) );
DFFRX2TS add_subt_module_YRegister_Q_reg_3_ ( .D(n967), .CK(clk), .RN(n2668),
.Q(add_subt_module_intDY[3]), .QN(n2589) );
DFFRX1TS add_subt_module_FS_Module_state_reg_reg_0_ ( .D(n1510), .CK(clk),
.RN(n1561), .Q(add_subt_module_FS_Module_state_reg[0]), .QN(n2587) );
DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n1520), .CK(clk), .RN(n1533), .Q(
cordic_FSM_state_reg[2]), .QN(n2586) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(
n1304), .CK(clk), .RN(n2673), .Q(
add_subt_module_Sgf_normalized_result[2]), .QN(n2585) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n1099), .CK(clk), .RN(n2683),
.Q(d_ff2_Y[23]), .QN(n2584) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(
n1348), .CK(clk), .RN(n1532), .Q(add_subt_module_Add_Subt_result[15]),
.QN(n2583) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n1500), .CK(clk), .RN(n2699), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n2582) );
DFFRX2TS cont_var_count_reg_1_ ( .D(n1506), .CK(clk), .RN(n2699), .Q(
cont_var_out[1]), .QN(n2581) );
DFFRX1TS add_subt_module_XRegister_Q_reg_1_ ( .D(n945), .CK(clk), .RN(n2669),
.Q(add_subt_module_intDX[1]), .QN(n2579) );
DFFRX1TS add_subt_module_XRegister_Q_reg_9_ ( .D(n903), .CK(clk), .RN(n2666),
.Q(add_subt_module_intDX[9]), .QN(n2578) );
DFFRX2TS add_subt_module_XRegister_Q_reg_5_ ( .D(n934), .CK(clk), .RN(n2676),
.Q(add_subt_module_intDX[5]), .QN(n2577) );
DFFRX2TS add_subt_module_XRegister_Q_reg_7_ ( .D(n913), .CK(clk), .RN(n2670),
.Q(add_subt_module_intDX[7]), .QN(n2576) );
DFFRX2TS add_subt_module_YRegister_Q_reg_19_ ( .D(n964), .CK(clk), .RN(n2675), .Q(add_subt_module_intDY[19]), .QN(n2574) );
DFFRX1TS add_subt_module_XRegister_Q_reg_21_ ( .D(n958), .CK(clk), .RN(n2669), .Q(add_subt_module_intDX[21]), .QN(n2573) );
DFFRX1TS add_subt_module_XRegister_Q_reg_15_ ( .D(n951), .CK(clk), .RN(n2669), .Q(add_subt_module_intDX[15]), .QN(n2572) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(
n1315), .CK(clk), .RN(n2677), .Q(
add_subt_module_Sgf_normalized_result[13]), .QN(n2571) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(
n1316), .CK(clk), .RN(n2677), .Q(
add_subt_module_Sgf_normalized_result[14]), .QN(n2570) );
DFFRX2TS add_subt_module_YRegister_Q_reg_22_ ( .D(n973), .CK(clk), .RN(n2668), .Q(add_subt_module_intDY[22]), .QN(n2569) );
DFFRX1TS add_subt_module_Sel_C_Q_reg_0_ ( .D(n1358), .CK(clk), .RN(n1014),
.Q(add_subt_module_FSM_selector_C), .QN(n2634) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(
n1314), .CK(clk), .RN(n2676), .Q(
add_subt_module_Sgf_normalized_result[12]), .QN(n2568) );
DFFRX2TS add_subt_module_YRegister_Q_reg_15_ ( .D(n950), .CK(clk), .RN(n2669), .Q(add_subt_module_intDY[15]), .QN(n2567) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(
n1312), .CK(clk), .RN(n2672), .Q(
add_subt_module_Sgf_normalized_result[10]), .QN(n2565) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(
n1313), .CK(clk), .RN(n2669), .Q(
add_subt_module_Sgf_normalized_result[11]), .QN(n2564) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(
n1310), .CK(clk), .RN(n2676), .Q(
add_subt_module_Sgf_normalized_result[8]), .QN(n2563) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(
n1311), .CK(clk), .RN(n2677), .Q(
add_subt_module_Sgf_normalized_result[9]), .QN(n2562) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(
n1308), .CK(clk), .RN(n2676), .Q(
add_subt_module_Sgf_normalized_result[6]), .QN(n2561) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(
n1309), .CK(clk), .RN(n2676), .Q(
add_subt_module_Sgf_normalized_result[7]), .QN(n2560) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(
n1306), .CK(clk), .RN(n2676), .Q(
add_subt_module_Sgf_normalized_result[4]), .QN(n2559) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(
n1307), .CK(clk), .RN(n2676), .Q(
add_subt_module_Sgf_normalized_result[5]), .QN(n2558) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_1_ ( .D(n1509), .CK(clk),
.RN(n1562), .Q(add_subt_module_FS_Module_state_reg[1]), .QN(n2557) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(
n1305), .CK(clk), .RN(n2676), .Q(
add_subt_module_Sgf_normalized_result[3]), .QN(n2555) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(
n1302), .CK(clk), .RN(n2675), .Q(
add_subt_module_Sgf_normalized_result[0]), .QN(n2554) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n1499), .CK(clk), .RN(n2699), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n2552) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(
n1303), .CK(clk), .RN(n2668), .Q(
add_subt_module_Sgf_normalized_result[1]), .QN(n2550) );
DFFRX2TS add_subt_module_YRegister_Q_reg_27_ ( .D(n1009), .CK(clk), .RN(
n2675), .Q(add_subt_module_intDY[27]), .QN(n2549) );
DFFRX4TS cont_iter_count_reg_0_ ( .D(n1504), .CK(clk), .RN(n2699), .Q(n2663),
.QN(n2702) );
DFFRX2TS add_subt_module_YRegister_Q_reg_30_ ( .D(n1012), .CK(clk), .RN(
n2668), .QN(n2627) );
DFFRX2TS add_subt_module_YRegister_Q_reg_29_ ( .D(n1011), .CK(clk), .RN(
n2673), .QN(n2580) );
DFFRX4TS add_subt_module_Sel_D_Q_reg_0_ ( .D(n1368), .CK(clk), .RN(n1014),
.Q(n2678), .QN(n2553) );
DFFRX4TS cont_iter_count_reg_2_ ( .D(n1502), .CK(clk), .RN(n2699), .Q(n2662),
.QN(n1536) );
DFFRX2TS add_subt_module_YRegister_Q_reg_5_ ( .D(n933), .CK(clk), .RN(n2667),
.Q(add_subt_module_intDY[5]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_7_ ( .D(n912), .CK(clk), .RN(n1561),
.Q(add_subt_module_intDY[7]) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_3_ ( .D(n1511), .CK(clk),
.RN(n2665), .Q(add_subt_module_FS_Module_state_reg[3]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(
n1332), .CK(clk), .RN(n2673), .Q(add_subt_module_Add_Subt_result[25])
);
DFFRX2TS add_subt_module_XRegister_Q_reg_25_ ( .D(n985), .CK(clk), .RN(n2675), .Q(add_subt_module_intDX[25]) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_2_ ( .D(n1508), .CK(clk),
.RN(n2677), .Q(add_subt_module_FS_Module_state_reg[2]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(
n1349), .CK(clk), .RN(n1532), .Q(add_subt_module_Add_Subt_result[16])
);
DFFRX2TS add_subt_module_XRegister_Q_reg_12_ ( .D(n907), .CK(clk), .RN(n1533), .Q(add_subt_module_intDX[12]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_26_ ( .D(n988), .CK(clk), .RN(n1562), .Q(add_subt_module_intDX[26]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_30_ ( .D(n1000), .CK(clk), .RN(
n2666), .Q(add_subt_module_intDX[30]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_10_ ( .D(n919), .CK(clk), .RN(n2670), .Q(add_subt_module_intDY[10]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_16_ ( .D(n923), .CK(clk), .RN(n2670), .Q(add_subt_module_intDY[16]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_27_ ( .D(n991), .CK(clk), .RN(n1561), .Q(add_subt_module_intDX[27]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_9_ ( .D(n902), .CK(clk), .RN(n2671),
.Q(add_subt_module_intDY[9]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(
n1343), .CK(clk), .RN(n1532), .Q(add_subt_module_Add_Subt_result[10])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(
n1355), .CK(clk), .RN(n2672), .Q(add_subt_module_Add_Subt_result[22])
);
DFFRX2TS add_subt_module_XRegister_Q_reg_0_ ( .D(n976), .CK(clk), .RN(n2668),
.Q(add_subt_module_intDX[0]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(
n1339), .CK(clk), .RN(n2672), .Q(add_subt_module_Add_Subt_result[6])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(
n1351), .CK(clk), .RN(n1532), .Q(add_subt_module_Add_Subt_result[18])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(
n1334), .CK(clk), .RN(n2668), .Q(add_subt_module_Add_Subt_result[1])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(
n1346), .CK(clk), .RN(n1532), .Q(add_subt_module_Add_Subt_result[13])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(
n1342), .CK(clk), .RN(n1532), .Q(add_subt_module_Add_Subt_result[9])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(
n1345), .CK(clk), .RN(n1532), .Q(add_subt_module_Add_Subt_result[12])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(
n1337), .CK(clk), .RN(n2672), .Q(add_subt_module_Add_Subt_result[4])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(
n1347), .CK(clk), .RN(n1532), .Q(add_subt_module_Add_Subt_result[14])
);
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]),
.CK(clk), .RN(n2666), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]),
.CK(clk), .RN(n1562), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]),
.CK(clk), .RN(n2665), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]),
.CK(clk), .RN(n2666), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]),
.CK(clk), .RN(n2665), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]),
.CK(clk), .RN(n1562), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]),
.CK(clk), .RN(n1533), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n1365), .CK(clk), .RN(n1532), .Q(add_subt_module_exp_oper_result[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n1433), .CK(clk), .RN(n1560),
.Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n1427), .CK(clk), .RN(n2683),
.Q(d_ff2_X[23]) );
DFFRX1TS add_subt_module_Sel_B_Q_reg_1_ ( .D(n1516), .CK(clk), .RN(n1014),
.Q(add_subt_module_FSM_selector_B[1]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n1361), .CK(clk), .RN(n2674), .Q(add_subt_module_exp_oper_result[0]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n1362), .CK(clk), .RN(n2674), .Q(add_subt_module_exp_oper_result[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n2679),
.Q(d_ff2_X[28]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ (
.D(n1281), .CK(clk), .RN(n2665), .Q(result_add_subt[25]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ (
.D(n1293), .CK(clk), .RN(n2665), .Q(result_add_subt[28]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ (
.D(n1297), .CK(clk), .RN(n2671), .Q(result_add_subt[29]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ (
.D(n1301), .CK(clk), .RN(n1533), .Q(result_add_subt[30]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ (
.D(n1197), .CK(clk), .RN(n1562), .Q(result_add_subt[4]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ (
.D(n1201), .CK(clk), .RN(n1562), .Q(result_add_subt[5]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ (
.D(n1261), .CK(clk), .RN(n1561), .Q(result_add_subt[20]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ (
.D(n1185), .CK(clk), .RN(n2671), .Q(result_add_subt[1]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ (
.D(n1265), .CK(clk), .RN(n2671), .Q(result_add_subt[21]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ (
.D(n1189), .CK(clk), .RN(n1561), .Q(result_add_subt[2]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ (
.D(n1193), .CK(clk), .RN(n1533), .Q(result_add_subt[3]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ (
.D(n1269), .CK(clk), .RN(n2665), .Q(result_add_subt[22]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ (
.D(n1181), .CK(clk), .RN(n2665), .Q(result_add_subt[0]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ (
.D(n1514), .CK(clk), .RN(n1533), .Q(result_add_subt[31]) );
DFFRX4TS cont_iter_count_reg_1_ ( .D(n1503), .CK(clk), .RN(n2699), .Q(
cont_iter_out[1]), .QN(n2566) );
DFFRX1TS add_subt_module_XRegister_Q_reg_31_ ( .D(n1003), .CK(clk), .RN(
n1562), .Q(add_subt_module_intDX[31]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]),
.CK(clk), .RN(n1562), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n1282), .CK(clk), .RN(n1530), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n1286), .CK(clk), .RN(n1530), .Q(
d_ff_Xn[27]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ (
.D(n1330), .CK(clk), .RN(n2668), .Q(add_subt_module_LZA_output[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n1388), .CK(clk), .RN(n2679), .Q(
d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n1402), .CK(clk), .RN(n2682),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n1394), .CK(clk), .RN(n2683),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n1406), .CK(clk), .RN(n2684),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n1408), .CK(clk), .RN(n2685),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n1384), .CK(clk), .RN(n2686), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n1400), .CK(clk), .RN(n2690),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n1414), .CK(clk), .RN(n2687),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n1412), .CK(clk), .RN(n2691),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n1386), .CK(clk), .RN(n2692), .Q(
d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n1392), .CK(clk), .RN(n2680), .Q(
d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n1396), .CK(clk), .RN(n2690),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n1382), .CK(clk), .RN(n2684), .Q(
d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n1390), .CK(clk), .RN(n2690), .Q(
d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n1404), .CK(clk), .RN(n1610),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n1410), .CK(clk), .RN(n2689),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n1416), .CK(clk), .RN(n1610),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n1418), .CK(clk), .RN(n2683),
.Q(d_ff2_X[22]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(
n1518), .CK(clk), .RN(n2677), .Q(
add_subt_module_Sgf_normalized_result[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n1115), .CK(clk), .RN(n2689),
.Q(d_ff2_Y[15]) );
DFFRX4TS cordic_FSM_state_reg_reg_3_ ( .D(n1521), .CK(clk), .RN(n1562), .Q(
cordic_FSM_state_reg[3]), .QN(n2551) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n1274), .CK(clk), .RN(n2693), .Q(
d_ff_Xn[24]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]),
.CK(clk), .RN(n2667), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]) );
DFFRX1TS reg_shift_y_Q_reg_23_ ( .D(n1091), .CK(clk), .RN(n1560), .Q(
d_ff3_sh_y_out[23]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_6_ ( .D(n970), .CK(clk), .RN(n2673),
.Q(add_subt_module_intDY[6]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_4_ ( .D(n926), .CK(clk), .RN(n2670),
.Q(add_subt_module_intDY[4]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_29_ ( .D(n997), .CK(clk), .RN(n2671), .Q(add_subt_module_intDX[29]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_24_ ( .D(n982), .CK(clk), .RN(n2675), .Q(add_subt_module_intDX[24]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_2_ ( .D(n960), .CK(clk), .RN(n2676),
.Q(add_subt_module_intDY[2]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(
n1356), .CK(clk), .RN(n2672), .Q(add_subt_module_Add_Subt_result[23])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(
n1353), .CK(clk), .RN(n2672), .Q(add_subt_module_Add_Subt_result[20])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(
n1333), .CK(clk), .RN(n2675), .Q(add_subt_module_Add_Subt_result[0])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(
n1341), .CK(clk), .RN(n1532), .Q(add_subt_module_Add_Subt_result[8])
);
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]),
.CK(clk), .RN(n1562), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n1093), .CK(clk), .RN(n1560),
.Q(d_ff2_Y[29]) );
DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n1464), .CK(clk), .RN(n2698), .Q(
sel_mux_2_reg[1]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n1363), .CK(clk), .RN(n2673), .Q(add_subt_module_exp_oper_result[2]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ (
.D(n1289), .CK(clk), .RN(n2665), .Q(result_add_subt[27]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ (
.D(n1285), .CK(clk), .RN(n2665), .Q(result_add_subt[26]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ (
.D(n1277), .CK(clk), .RN(n2665), .Q(result_add_subt[24]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ (
.D(n1273), .CK(clk), .RN(n2665), .Q(result_add_subt[23]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ (
.D(n1205), .CK(clk), .RN(n1562), .Q(result_add_subt[6]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ (
.D(n1257), .CK(clk), .RN(n1562), .Q(result_add_subt[19]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ (
.D(n1253), .CK(clk), .RN(n2673), .Q(result_add_subt[18]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ (
.D(n1241), .CK(clk), .RN(n1561), .Q(result_add_subt[15]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ (
.D(n1213), .CK(clk), .RN(n1561), .Q(result_add_subt[8]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ (
.D(n1233), .CK(clk), .RN(n1561), .Q(result_add_subt[13]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ (
.D(n1249), .CK(clk), .RN(n2666), .Q(result_add_subt[17]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ (
.D(n1245), .CK(clk), .RN(n1561), .Q(result_add_subt[16]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ (
.D(n1221), .CK(clk), .RN(n2671), .Q(result_add_subt[10]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ (
.D(n1237), .CK(clk), .RN(n1533), .Q(result_add_subt[14]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ (
.D(n1209), .CK(clk), .RN(n1533), .Q(result_add_subt[7]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ (
.D(n1225), .CK(clk), .RN(n2675), .Q(result_add_subt[11]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ (
.D(n1229), .CK(clk), .RN(n2667), .Q(result_add_subt[12]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ (
.D(n1217), .CK(clk), .RN(n2667), .Q(result_add_subt[9]) );
DFFRX4TS cont_iter_count_reg_3_ ( .D(n1505), .CK(clk), .RN(n2699), .Q(
cont_iter_out[3]), .QN(n2575) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n1430), .CK(clk), .RN(n1530),
.Q(d_ff2_X[26]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ (
.D(n1327), .CK(clk), .RN(n2675), .Q(add_subt_module_LZA_output[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n1096), .CK(clk), .RN(n1530),
.Q(d_ff2_Y[26]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ (
.D(n1328), .CK(clk), .RN(n2668), .Q(add_subt_module_LZA_output[3]) );
DFFRX4TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n1562), .Q(cordic_FSM_state_reg[1]), .QN(n2556) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]),
.CK(clk), .RN(n1562), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]),
.CK(clk), .RN(n2667), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1148), .CK(clk), .RN(n2695),
.Q(d_ff2_Z[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n1092), .CK(clk), .RN(n1560),
.Q(d_ff2_Y[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n1434), .CK(clk), .RN(n2696),
.Q(d_ff2_X[30]) );
DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n1372), .CK(clk), .RN(n2681), .Q(
sel_mux_3_reg) );
DFFRX1TS reg_ch_mux_1_Q_reg_0_ ( .D(n1466), .CK(clk), .RN(n2695), .Q(
sel_mux_1_reg) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n1294), .CK(clk), .RN(n1560), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n1290), .CK(clk), .RN(n2696), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n1278), .CK(clk), .RN(n2695), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n1202), .CK(clk), .RN(n2692), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n1190), .CK(clk), .RN(n2691), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n1254), .CK(clk), .RN(n2689), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n1186), .CK(clk), .RN(n1610), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n1182), .CK(clk), .RN(n1610), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n1258), .CK(clk), .RN(n2688), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n1230), .CK(clk), .RN(n2690), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n1198), .CK(clk), .RN(n2686), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n1246), .CK(clk), .RN(n2685), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n1242), .CK(clk), .RN(n2684), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n1218), .CK(clk), .RN(n2700), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n1234), .CK(clk), .RN(n2682), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n1206), .CK(clk), .RN(n2694), .Q(d_ff_Xn[7])
);
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n1226), .CK(clk), .RN(n2681), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n1081), .CK(clk), .RN(n2700), .Q(d_ff_Xn[0])
);
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n1513), .CK(clk), .RN(n2683), .Q(
d_ff_Xn[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n1298), .CK(clk), .RN(n2681), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n1270), .CK(clk), .RN(n1530), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n1266), .CK(clk), .RN(n2693), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n1262), .CK(clk), .RN(n1610), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n1250), .CK(clk), .RN(n2690), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n1238), .CK(clk), .RN(n2691), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n1210), .CK(clk), .RN(n2691), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n1194), .CK(clk), .RN(n2684), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n1222), .CK(clk), .RN(n2694), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n1214), .CK(clk), .RN(n2680), .Q(d_ff_Xn[9])
);
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ (
.D(n1329), .CK(clk), .RN(n2675), .Q(add_subt_module_LZA_output[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n1380), .CK(clk), .RN(n2689), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n1378), .CK(clk), .RN(n2688), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n1376), .CK(clk), .RN(n2691), .Q(
d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n1398), .CK(clk), .RN(n2681),
.Q(d_ff2_X[12]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n1367), .CK(clk), .RN(n2668), .Q(add_subt_module_exp_oper_result[6]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n1366), .CK(clk), .RN(n2674), .Q(add_subt_module_exp_oper_result[5]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n1360), .CK(clk), .RN(n2673), .Q(add_subt_module_exp_oper_result[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n1374), .CK(clk), .RN(n2679), .Q(
d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n1512), .CK(clk), .RN(n1610),
.Q(d_ff2_X[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n1083), .CK(clk), .RN(n2696),
.Q(d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n1145), .CK(clk), .RN(n2693), .Q(
d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n1101), .CK(clk), .RN(n2693),
.Q(d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n1133), .CK(clk), .RN(n2692), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n1139), .CK(clk), .RN(n2688), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n1107), .CK(clk), .RN(n1610),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n1141), .CK(clk), .RN(n2688), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n1103), .CK(clk), .RN(n2690),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n1109), .CK(clk), .RN(n2689),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n1129), .CK(clk), .RN(n2691), .Q(
d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n1143), .CK(clk), .RN(n2688), .Q(
d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n1105), .CK(clk), .RN(n2688),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n1119), .CK(clk), .RN(n2687),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n1135), .CK(clk), .RN(n2686), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n1111), .CK(clk), .RN(n2685),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n1137), .CK(clk), .RN(n2685), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n1113), .CK(clk), .RN(n2684),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n1125), .CK(clk), .RN(n2683),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n1117), .CK(clk), .RN(n2682),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n1131), .CK(clk), .RN(n2682), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n1123), .CK(clk), .RN(n2700),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n1121), .CK(clk), .RN(n1610),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n1127), .CK(clk), .RN(n2680), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n1147), .CK(clk), .RN(n2694), .Q(
d_ff3_sign_out) );
DFFRX4TS cordic_FSM_state_reg_reg_0_ ( .D(n1519), .CK(clk), .RN(n1533), .Q(
cordic_FSM_state_reg[0]), .QN(n2588) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n975),
.CK(clk), .RN(n2675), .Q(add_subt_module_DmP[0]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n972),
.CK(clk), .RN(n2673), .Q(add_subt_module_DmP[22]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n969),
.CK(clk), .RN(n2668), .Q(add_subt_module_DmP[6]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n925),
.CK(clk), .RN(n2670), .Q(add_subt_module_DmP[4]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n922),
.CK(clk), .RN(n2670), .Q(add_subt_module_DmP[16]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n918),
.CK(clk), .RN(n2670), .Q(add_subt_module_DmP[10]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n915),
.CK(clk), .RN(n2670), .Q(add_subt_module_DmP[14]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n940),
.CK(clk), .RN(n2668), .Q(add_subt_module_DmP[20]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n936),
.CK(clk), .RN(n2673), .Q(add_subt_module_DmP[13]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n932),
.CK(clk), .RN(n2675), .Q(add_subt_module_DmP[5]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n929),
.CK(clk), .RN(n2669), .Q(add_subt_module_DmP[17]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n946),
.CK(clk), .RN(n2669), .Q(add_subt_module_DmP[8]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n943),
.CK(clk), .RN(n2669), .Q(add_subt_module_DmP[1]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n959),
.CK(clk), .RN(n2677), .Q(add_subt_module_DmP[2]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n956),
.CK(clk), .RN(n2676), .Q(add_subt_module_DmP[21]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]),
.CK(clk), .RN(n1533), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]),
.CK(clk), .RN(n1533), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]),
.CK(clk), .RN(n2671), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n904),
.CK(clk), .RN(n2665), .Q(add_subt_module_DMP[12]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n899),
.CK(clk), .RN(n2677), .Q(add_subt_module_DMP[11]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n897),
.CK(clk), .RN(n1533), .Q(add_subt_module_DMP[10]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n900),
.CK(clk), .RN(n1561), .Q(add_subt_module_DMP[9]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n893),
.CK(clk), .RN(n1562), .Q(add_subt_module_DMP[8]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n898),
.CK(clk), .RN(n2666), .Q(add_subt_module_DMP[7]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ (
.D(n1517), .CK(clk), .RN(n2673), .Q(add_subt_module_add_overflow_flag),
.QN(n2598) );
DFFRX2TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n1364), .CK(clk), .RN(n2674), .Q(add_subt_module_exp_oper_result[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1156), .CK(clk), .RN(n2683),
.Q(d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1179), .CK(clk), .RN(n2683), .Q(
d_ff2_Z[0]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1157), .CK(clk), .RN(n2683),
.Q(d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1173), .CK(clk), .RN(n2692), .Q(
d_ff2_Z[6]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1176), .CK(clk), .RN(n2692), .Q(
d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1160), .CK(clk), .RN(n2688),
.Q(d_ff2_Z[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1177), .CK(clk), .RN(n2688), .Q(
d_ff2_Z[2]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1158), .CK(clk), .RN(n2691),
.Q(d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1161), .CK(clk), .RN(n2691),
.Q(d_ff2_Z[18]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1164), .CK(clk), .RN(n2688),
.Q(d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1171), .CK(clk), .RN(n2689), .Q(
d_ff2_Z[8]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1178), .CK(clk), .RN(n2689), .Q(
d_ff2_Z[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1159), .CK(clk), .RN(n2690),
.Q(d_ff2_Z[20]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1166), .CK(clk), .RN(n2690),
.Q(d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1174), .CK(clk), .RN(n2686), .Q(
d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1175), .CK(clk), .RN(n2685), .Q(
d_ff2_Z[4]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1172), .CK(clk), .RN(n2682), .Q(
d_ff2_Z[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1167), .CK(clk), .RN(n2681),
.Q(d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1170), .CK(clk), .RN(n1610), .Q(
d_ff2_Z[9]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1149), .CK(clk), .RN(n2696),
.Q(d_ff2_Z[30]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1150), .CK(clk), .RN(n1560),
.Q(d_ff2_Z[29]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1151), .CK(clk), .RN(n2679),
.Q(d_ff2_Z[28]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n901),
.CK(clk), .RN(n1533), .Q(add_subt_module_DmP[9]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]),
.CK(clk), .RN(n2671), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]),
.CK(clk), .RN(n1561), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]),
.CK(clk), .RN(n1533), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]) );
DFFRX1TS reg_LUT_Q_reg_9_ ( .D(n1445), .CK(clk), .RN(n2693), .Q(
d_ff3_LUT_out[9]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]),
.CK(clk), .RN(n2667), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]),
.CK(clk), .RN(n1533), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]),
.CK(clk), .RN(n2668), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]),
.CK(clk), .RN(n1562), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n966),
.CK(clk), .RN(n2677), .Q(add_subt_module_DmP[3]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n949),
.CK(clk), .RN(n2669), .Q(add_subt_module_DmP[15]) );
DFFRXLTS add_subt_module_Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n1359),
.CK(clk), .RN(n1533), .Q(overflow_flag), .QN(n2655) );
ADDFX1TS DP_OP_95J114_125_203_U27 ( .A(add_subt_module_S_A_S_Oper_A[0]), .B(
n2664), .CI(DP_OP_95J114_125_203_n56), .CO(DP_OP_95J114_125_203_n26),
.S(add_subt_module_Add_Subt_Sgf_module_S_to_D[0]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(
n1321), .CK(clk), .RN(n1532), .Q(
add_subt_module_Sgf_normalized_result[19]), .QN(n2631) );
CLKINVX6TS U1619 ( .A(n2165), .Y(n1560) );
AOI32X1TS U1620 ( .A0(d_ff2_X[23]), .A1(n2436), .A2(n2702), .B0(
d_ff3_sh_x_out[23]), .B1(n2425), .Y(n2328) );
AOI32X1TS U1621 ( .A0(n1643), .A1(n2436), .A2(n2702), .B0(d_ff3_LUT_out[23]),
.B1(n2425), .Y(n1644) );
AOI222X1TS U1622 ( .A0(n1700), .A1(d_ff2_Z[25]), .B0(n1702), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n2418), .Y(n1667) );
AOI222X1TS U1623 ( .A0(n1700), .A1(d_ff2_Z[26]), .B0(n1702), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n2418), .Y(n1668) );
AOI222X1TS U1624 ( .A0(n1700), .A1(d_ff2_Z[27]), .B0(n1702), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n2418), .Y(n1669) );
AOI222X1TS U1625 ( .A0(n1700), .A1(d_ff2_Z[14]), .B0(n1702), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n2418), .Y(n1673) );
AOI222X1TS U1626 ( .A0(n2402), .A1(d_ff2_Z[24]), .B0(n1702), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n2414), .Y(n1683) );
AOI222X1TS U1627 ( .A0(n1700), .A1(d_ff2_Z[17]), .B0(n1702), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n2414), .Y(n1678) );
AOI222X1TS U1628 ( .A0(n1700), .A1(d_ff2_Z[16]), .B0(n1702), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n2414), .Y(n1679) );
AOI222X1TS U1629 ( .A0(n2402), .A1(d_ff2_Z[10]), .B0(n1702), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n2347), .Y(n1697) );
AOI222X1TS U1630 ( .A0(n2402), .A1(d_ff2_Z[11]), .B0(n1702), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n2347), .Y(n1703) );
NAND2X6TS U1631 ( .A(n1836), .B(n2288), .Y(n1840) );
CMPR32X2TS U1632 ( .A(d_ff2_Y[26]), .B(n2575), .C(n2427), .CO(n2430), .S(
n2426) );
CMPR32X2TS U1633 ( .A(d_ff2_X[26]), .B(n2575), .C(n2336), .CO(n2339), .S(
n2335) );
NAND2X4TS U1634 ( .A(n1980), .B(n2170), .Y(n1979) );
XOR2XLTS U1635 ( .A(DP_OP_95J114_125_203_n1), .B(n2664), .Y(n2210) );
BUFX6TS U1636 ( .A(n2686), .Y(n2683) );
OR2X4TS U1637 ( .A(n1835), .B(n1836), .Y(n2022) );
NAND3BXLTS U1638 ( .AN(ack_cordic), .B(n2556), .C(n2447), .Y(n2278) );
NAND2X6TS U1639 ( .A(n2448), .B(n2447), .Y(n2449) );
CLKINVX6TS U1640 ( .A(rst), .Y(n1561) );
BUFX6TS U1641 ( .A(n2683), .Y(n1530) );
INVX4TS U1642 ( .A(n2169), .Y(n1982) );
BUFX6TS U1643 ( .A(n2694), .Y(n1610) );
NAND2BX4TS U1644 ( .AN(n2109), .B(n2108), .Y(n2110) );
CLKINVX6TS U1645 ( .A(n1831), .Y(n1880) );
OR3X4TS U1646 ( .A(underflow_flag), .B(n1552), .C(overflow_flag), .Y(n2367)
);
CLKINVX6TS U1647 ( .A(n2002), .Y(n1876) );
INVX4TS U1648 ( .A(n2054), .Y(n2055) );
NAND2X2TS U1649 ( .A(n1872), .B(n1875), .Y(n1831) );
BUFX4TS U1650 ( .A(n2369), .Y(n1552) );
NAND2BX4TS U1651 ( .AN(n1657), .B(sel_mux_3_reg), .Y(n1612) );
BUFX6TS U1652 ( .A(n2285), .Y(n2368) );
NOR2X4TS U1653 ( .A(sel_mux_3_reg), .B(n1657), .Y(n1613) );
OR2X2TS U1654 ( .A(n2082), .B(n2267), .Y(n2041) );
BUFX3TS U1655 ( .A(n2375), .Y(n2377) );
NOR2X4TS U1656 ( .A(n2348), .B(n2351), .Y(n2374) );
NOR2X1TS U1657 ( .A(sel_mux_1_reg), .B(n2402), .Y(n1666) );
AND2X4TS U1658 ( .A(n2416), .B(sel_mux_1_reg), .Y(n2418) );
BUFX6TS U1659 ( .A(n2209), .Y(n2249) );
BUFX4TS U1660 ( .A(n1665), .Y(n2416) );
NAND3X2TS U1661 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.C(n1620), .Y(n1634) );
CLKINVX3TS U1662 ( .A(n1565), .Y(n1711) );
OAI32X2TS U1663 ( .A0(n2228), .A1(n2141), .A2(n2143), .B0(n2287), .B1(n2228),
.Y(n2151) );
OR3X4TS U1664 ( .A(n2588), .B(n2273), .C(cordic_FSM_state_reg[1]), .Y(n1558)
);
OA21X4TS U1665 ( .A0(n2228), .A1(n2227), .B0(n2226), .Y(n2229) );
BUFX6TS U1666 ( .A(n2296), .Y(n1531) );
NOR2X4TS U1667 ( .A(n2228), .B(n2103), .Y(n2104) );
NOR2X4TS U1668 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n2147), .Y(
n2209) );
BUFX6TS U1669 ( .A(n2666), .Y(n1532) );
BUFX6TS U1670 ( .A(n1561), .Y(n1533) );
NAND2BXLTS U1671 ( .AN(add_subt_module_intDY[9]), .B(
add_subt_module_intDX[9]), .Y(n1742) );
NAND2BXLTS U1672 ( .AN(add_subt_module_intDX[27]), .B(
add_subt_module_intDY[27]), .Y(n1715) );
AOI222X4TS U1673 ( .A0(n2141), .A1(n1545), .B0(
add_subt_module_Add_Subt_result[9]), .B1(n1922), .C0(
add_subt_module_Add_Subt_result[16]), .C1(n1917), .Y(n1893) );
AOI222X4TS U1674 ( .A0(n2634), .A1(add_subt_module_DmP[10]), .B0(
add_subt_module_Add_Subt_result[12]), .B1(n1922), .C0(
add_subt_module_Add_Subt_result[13]), .C1(n1917), .Y(n1929) );
AOI222X4TS U1675 ( .A0(n2141), .A1(n1544), .B0(
add_subt_module_Add_Subt_result[11]), .B1(n1917), .C0(
add_subt_module_Add_Subt_result[14]), .C1(n1922), .Y(n1916) );
AOI222X4TS U1676 ( .A0(n2141), .A1(add_subt_module_DmP[14]), .B0(
add_subt_module_Add_Subt_result[9]), .B1(n1917), .C0(
add_subt_module_Add_Subt_result[16]), .C1(n1922), .Y(n1928) );
AOI222X4TS U1677 ( .A0(n2141), .A1(add_subt_module_DmP[15]), .B0(
add_subt_module_Add_Subt_result[8]), .B1(n1917), .C0(
add_subt_module_Add_Subt_result[17]), .C1(n1922), .Y(n1930) );
NAND2BXLTS U1678 ( .AN(add_subt_module_intDX[24]), .B(
add_subt_module_intDY[24]), .Y(n1771) );
AOI222X4TS U1679 ( .A0(n2634), .A1(add_subt_module_DmP[6]), .B0(
add_subt_module_Add_Subt_result[8]), .B1(n1922), .C0(
add_subt_module_Add_Subt_result[17]), .C1(n1917), .Y(n1891) );
NAND2BXLTS U1680 ( .AN(add_subt_module_Add_Subt_result[12]), .B(n2359), .Y(
n2247) );
OAI211X1TS U1681 ( .A0(add_subt_module_FS_Module_state_reg[3]), .A1(n2141),
.B0(add_subt_module_FS_Module_state_reg[0]), .C0(n2140), .Y(n2291) );
AOI222X1TS U1682 ( .A0(n2141), .A1(add_subt_module_DmP[2]), .B0(
add_subt_module_Add_Subt_result[4]), .B1(n1922), .C0(
add_subt_module_Add_Subt_result[21]), .C1(n1917), .Y(n1885) );
AO22XLTS U1683 ( .A0(n1903), .A1(n1885), .B0(n1891), .B1(n2266), .Y(n1535)
);
AO22XLTS U1684 ( .A0(n1903), .A1(n1870), .B0(n1890), .B1(n2266), .Y(n1534)
);
OAI31X1TS U1685 ( .A0(n2662), .A1(n2575), .A2(n2315), .B0(n2327), .Y(n2319)
);
OAI32X1TS U1686 ( .A0(cordic_FSM_state_reg[2]), .A1(n2276), .A2(n2275), .B0(
n2448), .B1(n2586), .Y(n2277) );
AO22XLTS U1687 ( .A0(n2223), .A1(n2366), .B0(n2364), .B1(
add_subt_module_LZA_output[2]), .Y(n1329) );
AO22XLTS U1688 ( .A0(d_ff_Yn[30]), .A1(n2418), .B0(n2440), .B1(d_ff2_Y[30]),
.Y(n1092) );
OAI222X1TS U1689 ( .A0(n2294), .A1(n2314), .B0(n2310), .B1(n2299), .C0(n2575), .C1(n2293), .Y(n1505) );
AO22XLTS U1690 ( .A0(n2248), .A1(n2366), .B0(n2364), .B1(
add_subt_module_LZA_output[1]), .Y(n1330) );
AOI222X1TS U1691 ( .A0(n2263), .A1(n2262), .B0(n2260), .B1(n2264), .C0(n2261), .C1(n1876), .Y(n1977) );
AOI211XLTS U1692 ( .A0(add_subt_module_FS_Module_state_reg[1]), .A1(n2289),
.B0(n2145), .C0(n2144), .Y(n2146) );
AO22XLTS U1693 ( .A0(d_ff_Yn[27]), .A1(n2414), .B0(n2440), .B1(n1553), .Y(
n1095) );
BUFX3TS U1694 ( .A(n1613), .Y(n1645) );
OR2X1TS U1695 ( .A(n1820), .B(n1819), .Y(n1537) );
INVX2TS U1696 ( .A(n1543), .Y(n1544) );
INVX2TS U1697 ( .A(n1542), .Y(n1545) );
INVX3TS U1698 ( .A(n2390), .Y(n2436) );
BUFX6TS U1699 ( .A(n1558), .Y(n2390) );
BUFX6TS U1700 ( .A(n2634), .Y(n2141) );
CLKINVX3TS U1701 ( .A(n2056), .Y(n2080) );
BUFX6TS U1702 ( .A(n2543), .Y(n2532) );
BUFX6TS U1703 ( .A(n2535), .Y(n2545) );
AOI211X1TS U1704 ( .A0(n2354), .A1(add_subt_module_Add_Subt_result[18]),
.B0(n2214), .C0(n2213), .Y(n2363) );
NOR2X2TS U1705 ( .A(add_subt_module_Add_Subt_result[19]), .B(n2239), .Y(
n2354) );
AOI31X2TS U1706 ( .A0(cont_iter_out[1]), .A1(n1536), .A2(n2575), .B0(n2309),
.Y(n2324) );
BUFX6TS U1707 ( .A(n2057), .Y(n2134) );
NOR2X2TS U1708 ( .A(n2566), .B(n2313), .Y(n2304) );
NAND2X2TS U1709 ( .A(n2663), .B(n2575), .Y(n2313) );
INVX2TS U1710 ( .A(n1537), .Y(n1546) );
BUFX4TS U1711 ( .A(n2700), .Y(n2692) );
BUFX4TS U1712 ( .A(n2700), .Y(n2696) );
BUFX4TS U1713 ( .A(n2700), .Y(n2695) );
BUFX4TS U1714 ( .A(n2700), .Y(n2694) );
BUFX4TS U1715 ( .A(n2685), .Y(n2686) );
BUFX4TS U1716 ( .A(n2685), .Y(n2680) );
BUFX4TS U1717 ( .A(n2697), .Y(n2681) );
BUFX4TS U1718 ( .A(n1610), .Y(n2685) );
BUFX4TS U1719 ( .A(n2699), .Y(n2679) );
BUFX4TS U1720 ( .A(n2684), .Y(n2700) );
AOI32X1TS U1721 ( .A0(n1992), .A1(n2264), .A2(n2263), .B0(n2006), .B1(n2264),
.Y(n1993) );
NOR2X2TS U1722 ( .A(n1992), .B(n2267), .Y(n2006) );
BUFX4TS U1723 ( .A(n2699), .Y(n2684) );
BUFX4TS U1724 ( .A(n2699), .Y(n2697) );
BUFX4TS U1725 ( .A(n2699), .Y(n2698) );
CLKINVX6TS U1726 ( .A(n2416), .Y(n2412) );
BUFX4TS U1727 ( .A(n2681), .Y(n2690) );
BUFX4TS U1728 ( .A(n1610), .Y(n2689) );
BUFX4TS U1729 ( .A(n2681), .Y(n2688) );
BUFX4TS U1730 ( .A(n1610), .Y(n2691) );
BUFX4TS U1731 ( .A(n2671), .Y(n2665) );
NOR2X2TS U1732 ( .A(n2287), .B(n1833), .Y(n2145) );
NOR2X2TS U1733 ( .A(d_ff2_Y[23]), .B(n2702), .Y(n2422) );
BUFX4TS U1734 ( .A(n1533), .Y(n2669) );
OAI221X2TS U1735 ( .A0(add_subt_module_sign_final_result), .A1(r_mode[1]),
.B0(n2641), .B1(r_mode[0]), .C0(n2139), .Y(n2148) );
BUFX4TS U1736 ( .A(n1533), .Y(n2670) );
BUFX4TS U1737 ( .A(n1562), .Y(n2668) );
AOI32X2TS U1738 ( .A0(n1879), .A1(n1903), .A2(n1878), .B0(n1892), .B1(n2266),
.Y(n1906) );
BUFX4TS U1739 ( .A(n1634), .Y(n1657) );
INVX2TS U1740 ( .A(n2041), .Y(n1547) );
AO21X2TS U1741 ( .A0(n2320), .A1(n2575), .B0(n2309), .Y(n2312) );
BUFX6TS U1742 ( .A(n1826), .Y(n1922) );
NOR2XLTS U1743 ( .A(n2141), .B(n1980), .Y(n1826) );
BUFX4TS U1744 ( .A(n1877), .Y(n1903) );
INVX6TS U1745 ( .A(n2553), .Y(n2230) );
OAI211XLTS U1746 ( .A0(n2287), .A1(add_subt_module_FS_Module_state_reg[1]),
.B0(n2286), .C0(n2229), .Y(n2292) );
NAND2BX2TS U1747 ( .AN(n2103), .B(n1818), .Y(n2286) );
OAI22X2TS U1748 ( .A0(n1833), .A1(n2103), .B0(n1832), .B1(n2227), .Y(n2115)
);
BUFX4TS U1749 ( .A(n2374), .Y(n2372) );
BUFX4TS U1750 ( .A(n2374), .Y(n2380) );
BUFX4TS U1751 ( .A(n2374), .Y(n2379) );
NOR2X2TS U1752 ( .A(n2586), .B(n2551), .Y(n2447) );
NOR2X4TS U1753 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.Y(n2448) );
NOR3X1TS U1754 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[3]),
.C(beg_fsm_cordic), .Y(n2275) );
OAI32X1TS U1755 ( .A0(n2662), .A1(n2305), .A2(n2294), .B0(n2293), .B1(n1536),
.Y(n1502) );
NAND3X2TS U1756 ( .A(n2350), .B(n1824), .C(n2349), .Y(n2294) );
AOI22X4TS U1757 ( .A0(add_subt_module_LZA_output[3]), .A1(n2205), .B0(n2204),
.B1(add_subt_module_exp_oper_result[3]), .Y(n2083) );
INVX2TS U1758 ( .A(n1539), .Y(n1548) );
INVX2TS U1759 ( .A(n1538), .Y(n1549) );
INVX2TS U1760 ( .A(n1534), .Y(n1550) );
AOI22X2TS U1761 ( .A0(n1992), .A1(n1921), .B0(n2261), .B1(n1976), .Y(n2003)
);
BUFX4TS U1762 ( .A(n2367), .Y(n2370) );
AOI22X2TS U1763 ( .A0(n1992), .A1(n1930), .B0(n1974), .B1(n1976), .Y(n1998)
);
AOI22X2TS U1764 ( .A0(n1992), .A1(n1974), .B0(n2255), .B1(n2266), .Y(n2005)
);
OAI22X2TS U1765 ( .A0(n1824), .A1(n2282), .B0(n1823), .B1(n1014), .Y(n2289)
);
INVX2TS U1766 ( .A(n1535), .Y(n1551) );
BUFX6TS U1767 ( .A(n1871), .Y(n2264) );
NOR2X2TS U1768 ( .A(n1536), .B(n2575), .Y(n1643) );
NAND3X2TS U1769 ( .A(n2320), .B(n2702), .C(n2575), .Y(n2321) );
BUFX4TS U1770 ( .A(n1666), .Y(n1702) );
BUFX4TS U1771 ( .A(n1666), .Y(n1691) );
BUFX6TS U1772 ( .A(n2142), .Y(n2033) );
BUFX4TS U1773 ( .A(n1835), .Y(n2142) );
INVX3TS U1774 ( .A(n1924), .Y(n1980) );
NOR2X4TS U1775 ( .A(n2129), .B(n1980), .Y(n2054) );
OAI21X2TS U1776 ( .A0(n2637), .A1(n1924), .B0(n1920), .Y(n2261) );
CLKINVX6TS U1777 ( .A(n1711), .Y(n2544) );
INVX6TS U1778 ( .A(n1711), .Y(n2520) );
INVX4TS U1779 ( .A(n1711), .Y(n2529) );
NOR2X1TS U1780 ( .A(add_subt_module_Add_Subt_result[9]), .B(
add_subt_module_Add_Subt_result[8]), .Y(n2154) );
INVX2TS U1781 ( .A(n1541), .Y(n1553) );
OAI22X2TS U1782 ( .A0(add_subt_module_Add_Subt_result[0]), .A1(n1924), .B0(
add_subt_module_Add_Subt_result[25]), .B1(n1973), .Y(n2255) );
AOI222X4TS U1783 ( .A0(n2141), .A1(add_subt_module_DmP[3]), .B0(
add_subt_module_Add_Subt_result[5]), .B1(n1922), .C0(
add_subt_module_Add_Subt_result[20]), .C1(n1917), .Y(n1886) );
AOI222X4TS U1784 ( .A0(n2141), .A1(add_subt_module_DmP[18]), .B0(
add_subt_module_Add_Subt_result[5]), .B1(n1917), .C0(
add_subt_module_Add_Subt_result[20]), .C1(n1922), .Y(n1991) );
INVX2TS U1785 ( .A(n1540), .Y(n1554) );
OAI32X1TS U1786 ( .A0(add_subt_module_Add_Subt_result[25]), .A1(
add_subt_module_Add_Subt_result[23]), .A2(n2352), .B0(n2638), .B1(
add_subt_module_Add_Subt_result[25]), .Y(n2353) );
NOR4X2TS U1787 ( .A(add_subt_module_Add_Subt_result[24]), .B(
add_subt_module_Add_Subt_result[25]), .C(
add_subt_module_Add_Subt_result[22]), .D(
add_subt_module_Add_Subt_result[23]), .Y(n2217) );
OAI221X1TS U1788 ( .A0(n2610), .A1(add_subt_module_intDY[10]), .B0(n2620),
.B1(add_subt_module_intDY[2]), .C0(n1781), .Y(n1784) );
OAI221XLTS U1789 ( .A0(n2623), .A1(add_subt_module_intDX[25]), .B0(n2614),
.B1(add_subt_module_intDX[24]), .C0(n1798), .Y(n1799) );
AOI221X4TS U1790 ( .A0(add_subt_module_intDX[30]), .A1(n2627), .B0(
add_subt_module_intDX[29]), .B1(n2580), .C0(n1720), .Y(n1722) );
OAI221XLTS U1791 ( .A0(n2607), .A1(add_subt_module_intDY[18]), .B0(n2580),
.B1(add_subt_module_intDX[29]), .C0(n1796), .Y(n1801) );
AOI222X1TS U1792 ( .A0(add_subt_module_intDY[4]), .A1(n2619), .B0(n1731),
.B1(n1730), .C0(add_subt_module_intDY[5]), .C1(n2577), .Y(n1733) );
OAI221XLTS U1793 ( .A0(n2577), .A1(add_subt_module_intDY[5]), .B0(n2619),
.B1(add_subt_module_intDY[4]), .C0(n1788), .Y(n1793) );
OAI221X1TS U1794 ( .A0(n2606), .A1(add_subt_module_intDX[28]), .B0(n2621),
.B1(add_subt_module_intDY[6]), .C0(n1795), .Y(n1802) );
AOI222X4TS U1795 ( .A0(n2520), .A1(add_subt_module_intDY[31]), .B0(n2487),
.B1(d_ff3_sh_x_out[31]), .C0(n2473), .C1(d_ff3_sh_y_out[31]), .Y(n1713) );
BUFX4TS U1796 ( .A(n2683), .Y(n2693) );
NOR2X2TS U1797 ( .A(n2586), .B(cordic_FSM_state_reg[3]), .Y(n1822) );
AOI211XLTS U1798 ( .A0(add_subt_module_intDY[16]), .A1(n2626), .B0(n1764),
.C0(n1765), .Y(n1756) );
OAI211X2TS U1799 ( .A0(add_subt_module_intDX[20]), .A1(n2592), .B0(n1770),
.C0(n1755), .Y(n1764) );
NOR2X4TS U1800 ( .A(n2116), .B(n2055), .Y(n2135) );
BUFX4TS U1801 ( .A(n1533), .Y(n2676) );
BUFX4TS U1802 ( .A(n1562), .Y(n2675) );
BUFX4TS U1803 ( .A(n1562), .Y(n2673) );
BUFX4TS U1804 ( .A(n2666), .Y(n2674) );
BUFX4TS U1805 ( .A(n1533), .Y(n2672) );
BUFX4TS U1806 ( .A(n1533), .Y(n2677) );
BUFX6TS U1807 ( .A(n1561), .Y(n1562) );
BUFX4TS U1808 ( .A(n1612), .Y(n1664) );
BUFX4TS U1809 ( .A(n1645), .Y(n1662) );
CLKINVX6TS U1810 ( .A(n1840), .Y(n2034) );
BUFX6TS U1811 ( .A(n1873), .Y(n2262) );
CLKINVX6TS U1812 ( .A(n1531), .Y(n2299) );
AOI22X2TS U1813 ( .A0(add_subt_module_LZA_output[1]), .A1(n2205), .B0(n2204),
.B1(add_subt_module_exp_oper_result[1]), .Y(n1872) );
AOI21X2TS U1814 ( .A0(add_subt_module_exp_oper_result[0]), .A1(n2599), .B0(
n2207), .Y(n1875) );
NOR2X2TS U1815 ( .A(d_ff2_X[23]), .B(n2702), .Y(n2332) );
AOI22X2TS U1816 ( .A0(n1992), .A1(n1915), .B0(n1921), .B1(n2266), .Y(n1956)
);
AOI22X2TS U1817 ( .A0(n1903), .A1(n1901), .B0(n1915), .B1(n2266), .Y(n1940)
);
AOI22X2TS U1818 ( .A0(n1903), .A1(n1890), .B0(n1901), .B1(n2266), .Y(n1949)
);
AOI22X2TS U1819 ( .A0(n1992), .A1(n1916), .B0(n1925), .B1(n1976), .Y(n1952)
);
AOI22X2TS U1820 ( .A0(n1903), .A1(n1902), .B0(n1916), .B1(n2266), .Y(n1946)
);
AOI22X2TS U1821 ( .A0(n1903), .A1(n1892), .B0(n1902), .B1(n1976), .Y(n1911)
);
AOI22X2TS U1822 ( .A0(n1992), .A1(n1931), .B0(n1930), .B1(n2266), .Y(n1951)
);
AOI22X2TS U1823 ( .A0(n1903), .A1(n1893), .B0(n1931), .B1(n1976), .Y(n1944)
);
AOI22X2TS U1824 ( .A0(n1903), .A1(n1886), .B0(n1893), .B1(n1976), .Y(n1910)
);
AOI22X2TS U1825 ( .A0(n1992), .A1(n1929), .B0(n1928), .B1(n1976), .Y(n1950)
);
AOI22X2TS U1826 ( .A0(n1992), .A1(n1928), .B0(n1991), .B1(n2266), .Y(n1941)
);
AOI22X2TS U1827 ( .A0(n1903), .A1(n1891), .B0(n1929), .B1(n2266), .Y(n1945)
);
BUFX4TS U1828 ( .A(n1903), .Y(n1992) );
INVX6TS U1829 ( .A(n1903), .Y(n2266) );
INVX3TS U1830 ( .A(n2449), .Y(n2454) );
INVX3TS U1831 ( .A(n2368), .Y(n2373) );
CLKINVX6TS U1832 ( .A(n2418), .Y(n2441) );
NOR3X4TS U1833 ( .A(n2129), .B(n2267), .C(n2080), .Y(n2099) );
OAI21X4TS U1834 ( .A0(n2115), .A1(n2151), .B0(
add_subt_module_add_overflow_flag), .Y(n2267) );
BUFX6TS U1835 ( .A(n2133), .Y(n2129) );
INVX3TS U1836 ( .A(n1924), .Y(n1917) );
CLKINVX6TS U1837 ( .A(n1558), .Y(n2444) );
CLKINVX6TS U1838 ( .A(n2416), .Y(n1700) );
BUFX6TS U1839 ( .A(n2191), .Y(n2664) );
AOI222X4TS U1840 ( .A0(n2141), .A1(add_subt_module_DmP[19]), .B0(
add_subt_module_Add_Subt_result[4]), .B1(n1980), .C0(
add_subt_module_Add_Subt_result[21]), .C1(n1922), .Y(n1974) );
AOI222X4TS U1841 ( .A0(n2141), .A1(add_subt_module_DmP[11]), .B0(
add_subt_module_Add_Subt_result[12]), .B1(n1917), .C0(
add_subt_module_Add_Subt_result[13]), .C1(n1922), .Y(n1931) );
AOI32X1TS U1842 ( .A0(add_subt_module_Add_Subt_result[10]), .A1(n2359), .A2(
n2642), .B0(add_subt_module_Add_Subt_result[12]), .B1(n2359), .Y(n2232) );
BUFX6TS U1843 ( .A(n2540), .Y(n2546) );
AOI211XLTS U1844 ( .A0(add_subt_module_Add_Subt_result[1]), .A1(n2234), .B0(
n2233), .C0(n2356), .Y(n2235) );
AOI222X4TS U1845 ( .A0(n2141), .A1(add_subt_module_DmP[16]), .B0(
add_subt_module_Add_Subt_result[7]), .B1(n1917), .C0(
add_subt_module_Add_Subt_result[18]), .C1(n1922), .Y(n1925) );
AOI222X4TS U1846 ( .A0(n2141), .A1(add_subt_module_DmP[4]), .B0(
add_subt_module_Add_Subt_result[6]), .B1(n1922), .C0(
add_subt_module_Add_Subt_result[19]), .C1(n1917), .Y(n1892) );
OAI221XLTS U1847 ( .A0(n2579), .A1(add_subt_module_intDY[1]), .B0(n2613),
.B1(add_subt_module_intDX[0]), .C0(n1790), .Y(n1791) );
AOI222X4TS U1848 ( .A0(n2141), .A1(add_subt_module_DmP[8]), .B0(
add_subt_module_Add_Subt_result[10]), .B1(n1922), .C0(
add_subt_module_Add_Subt_result[15]), .C1(n1917), .Y(n1902) );
OAI221XLTS U1849 ( .A0(n2578), .A1(add_subt_module_intDY[9]), .B0(n2618),
.B1(add_subt_module_intDY[11]), .C0(n1782), .Y(n1783) );
OAI221X1TS U1850 ( .A0(n2549), .A1(add_subt_module_intDX[27]), .B0(n2615),
.B1(add_subt_module_intDY[19]), .C0(n1797), .Y(n1800) );
OAI221X1TS U1851 ( .A0(n2609), .A1(add_subt_module_intDY[17]), .B0(n2626),
.B1(add_subt_module_intDY[16]), .C0(n1805), .Y(n1808) );
OAI221X1TS U1852 ( .A0(n2608), .A1(add_subt_module_intDY[20]), .B0(n2627),
.B1(add_subt_module_intDX[30]), .C0(n1803), .Y(n1810) );
OAI221X1TS U1853 ( .A0(n2600), .A1(add_subt_module_intDY[3]), .B0(n2622),
.B1(add_subt_module_intDX[26]), .C0(n1789), .Y(n1792) );
OAI211X2TS U1854 ( .A0(add_subt_module_intDX[12]), .A1(n2617), .B0(n1750),
.C0(n1736), .Y(n1752) );
OAI221XLTS U1855 ( .A0(n2612), .A1(add_subt_module_intDY[22]), .B0(n2617),
.B1(add_subt_module_intDX[12]), .C0(n1806), .Y(n1807) );
NOR4X2TS U1856 ( .A(add_subt_module_Add_Subt_result[16]), .B(
add_subt_module_Add_Subt_result[15]), .C(
add_subt_module_Add_Subt_result[17]), .D(n2236), .Y(n2231) );
NAND2X2TS U1857 ( .A(n2557), .B(add_subt_module_FS_Module_state_reg[2]), .Y(
n2228) );
NOR2X2TS U1858 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(
add_subt_module_FS_Module_state_reg[2]), .Y(n1818) );
NOR2X2TS U1859 ( .A(n2287), .B(add_subt_module_FS_Module_state_reg[2]), .Y(
n2224) );
NAND2X2TS U1860 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(
add_subt_module_FS_Module_state_reg[2]), .Y(n2147) );
NOR2X2TS U1861 ( .A(n2557), .B(add_subt_module_FS_Module_state_reg[2]), .Y(
n2225) );
NAND2X2TS U1862 ( .A(n2587), .B(add_subt_module_FS_Module_state_reg[3]), .Y(
n2287) );
NOR2X2TS U1863 ( .A(n2587), .B(add_subt_module_FS_Module_state_reg[3]), .Y(
n2107) );
OR3X2TS U1864 ( .A(n1832), .B(add_subt_module_FS_Module_state_reg[3]), .C(
add_subt_module_add_overflow_flag), .Y(n1924) );
OAI221X1TS U1865 ( .A0(n2576), .A1(add_subt_module_intDY[7]), .B0(n2616),
.B1(add_subt_module_intDY[14]), .C0(n1787), .Y(n1794) );
NOR2X2TS U1866 ( .A(n2662), .B(cont_iter_out[1]), .Y(n2320) );
CLKINVX6TS U1867 ( .A(n2553), .Y(n1555) );
OAI21XLTS U1868 ( .A0(add_subt_module_intDX[1]), .A1(n2591), .B0(
add_subt_module_intDX[0]), .Y(n1726) );
OAI21XLTS U1869 ( .A0(add_subt_module_intDX[15]), .A1(n2567), .B0(
add_subt_module_intDX[14]), .Y(n1746) );
NOR2XLTS U1870 ( .A(n1759), .B(add_subt_module_intDY[16]), .Y(n1760) );
OAI21XLTS U1871 ( .A0(add_subt_module_intDX[21]), .A1(n2602), .B0(
add_subt_module_intDX[20]), .Y(n1758) );
NOR2XLTS U1872 ( .A(n2605), .B(n2678), .Y(n2181) );
NOR2XLTS U1873 ( .A(n2651), .B(n1555), .Y(n2172) );
NOR2XLTS U1874 ( .A(n2625), .B(n1555), .Y(n2179) );
NOR2XLTS U1875 ( .A(add_subt_module_Add_Subt_result[3]), .B(
add_subt_module_Add_Subt_result[2]), .Y(n2156) );
OAI211XLTS U1876 ( .A0(n2147), .A1(n2143), .B0(n2142), .C0(n2544), .Y(n2144)
);
AOI31XLTS U1877 ( .A0(add_subt_module_Add_Subt_result[6]), .A1(n2357), .A2(
n2643), .B0(n2356), .Y(n2361) );
NOR2XLTS U1878 ( .A(n2266), .B(n2254), .Y(n2257) );
AOI31XLTS U1879 ( .A0(n2310), .A1(n1569), .A2(n2321), .B0(n2425), .Y(n1563)
);
OAI211XLTS U1880 ( .A0(n2132), .A1(n2055), .B0(n2131), .C0(n2130), .Y(n1309)
);
AOI221XLTS U1881 ( .A0(cont_var_out[1]), .A1(n1632), .B0(n2581), .B1(n1631),
.C0(n2436), .Y(n1506) );
OAI211XLTS U1882 ( .A0(n2079), .A1(n1979), .B0(n1990), .C0(n1989), .Y(n1317)
);
OAI211XLTS U1883 ( .A0(n2132), .A1(n1979), .B0(n2101), .C0(n2100), .Y(n1320)
);
OAI21XLTS U1884 ( .A0(n2616), .A1(n2036), .B0(n2015), .Y(n914) );
OAI21XLTS U1885 ( .A0(n2601), .A1(n2036), .B0(n2020), .Y(n935) );
OAI21XLTS U1886 ( .A0(n2615), .A1(n2022), .B0(n2012), .Y(n962) );
OAI21XLTS U1887 ( .A0(n2623), .A1(n2022), .B0(n2027), .Y(n984) );
OAI21XLTS U1888 ( .A0(n2627), .A1(n2022), .B0(n2025), .Y(n999) );
OAI21XLTS U1889 ( .A0(n2398), .A1(n1664), .B0(n1663), .Y(n1052) );
OAI211XLTS U1890 ( .A0(n1831), .A1(n1550), .B0(n1899), .C0(n1898), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]) );
OAI21XLTS U1891 ( .A0(n2410), .A1(n1664), .B0(n1659), .Y(n1032) );
XOR2X1TS U1892 ( .A(add_subt_module_intAS), .B(add_subt_module_intDY[31]),
.Y(n1779) );
XNOR2X1TS U1893 ( .A(n1779), .B(add_subt_module_intDX[31]), .Y(n1819) );
NOR2X2TS U1894 ( .A(n1819), .B(n2678), .Y(n2191) );
NOR2X1TS U1895 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(
add_subt_module_FS_Module_state_reg[3]), .Y(n1559) );
INVX2TS U1896 ( .A(n1559), .Y(n2227) );
OAI21XLTS U1897 ( .A0(n2147), .A1(n2227), .B0(n2141), .Y(n1358) );
NAND2X2TS U1898 ( .A(n1559), .B(n1818), .Y(n1014) );
INVX2TS U1899 ( .A(n2448), .Y(n2270) );
NOR3X1TS U1900 ( .A(n2270), .B(cordic_FSM_state_reg[2]), .C(
cordic_FSM_state_reg[3]), .Y(n2165) );
BUFX4TS U1901 ( .A(n1560), .Y(n2699) );
BUFX3TS U1902 ( .A(n2680), .Y(n2682) );
BUFX3TS U1903 ( .A(n1561), .Y(n2666) );
BUFX3TS U1904 ( .A(n1562), .Y(n2667) );
BUFX3TS U1905 ( .A(n1561), .Y(n2671) );
INVX2TS U1906 ( .A(n1822), .Y(n2273) );
NAND2X1TS U1907 ( .A(cont_iter_out[3]), .B(n1536), .Y(n2310) );
NAND2X1TS U1908 ( .A(n2575), .B(n2662), .Y(n1569) );
BUFX4TS U1909 ( .A(n2390), .Y(n2425) );
AO21XLTS U1910 ( .A0(d_ff3_LUT_out[1]), .A1(n2390), .B0(n1563), .Y(n1437) );
NAND2X1TS U1911 ( .A(cont_iter_out[1]), .B(n2702), .Y(n2315) );
INVX2TS U1912 ( .A(n1569), .Y(n2306) );
NAND2X1TS U1913 ( .A(cont_iter_out[1]), .B(n2663), .Y(n2305) );
NOR2XLTS U1914 ( .A(n2662), .B(n2305), .Y(n1564) );
AOI31X1TS U1915 ( .A0(n2306), .A1(n2566), .A2(n2702), .B0(n1564), .Y(n2327)
);
OAI21X1TS U1916 ( .A0(n2566), .A1(n2702), .B0(n1536), .Y(n2308) );
INVX4TS U1917 ( .A(n2390), .Y(n2439) );
OAI21X1TS U1918 ( .A0(cont_iter_out[3]), .A1(n2308), .B0(n2439), .Y(n2303)
);
OA22X1TS U1919 ( .A0(n2319), .A1(n2303), .B0(n2439), .B1(d_ff3_LUT_out[4]),
.Y(n1440) );
NAND2X1TS U1920 ( .A(n2107), .B(n1818), .Y(n1565) );
AOI2BB2XLTS U1921 ( .B0(d_ff3_sign_out), .B1(n2633), .A0N(n2633), .A1N(
d_ff3_sign_out), .Y(n1566) );
AO22XLTS U1922 ( .A0(n1711), .A1(n1566), .B0(n2520), .B1(
add_subt_module_intAS), .Y(n1002) );
INVX4TS U1923 ( .A(n2394), .Y(n2434) );
OAI21XLTS U1924 ( .A0(n1536), .A1(n2575), .B0(n2663), .Y(n1567) );
XOR2XLTS U1925 ( .A(cont_iter_out[1]), .B(n1567), .Y(n1568) );
AO22XLTS U1926 ( .A0(n2434), .A1(n1568), .B0(n2425), .B1(d_ff3_LUT_out[24]),
.Y(n1460) );
NOR2XLTS U1927 ( .A(n2566), .B(n1569), .Y(n1570) );
NAND4BXLTS U1928 ( .AN(n2304), .B(n2436), .C(n2310), .D(n2321), .Y(n2318) );
OA22X1TS U1929 ( .A0(n1570), .A1(n2318), .B0(n2439), .B1(d_ff3_LUT_out[0]),
.Y(n1436) );
OR2X2TS U1930 ( .A(n1643), .B(n2390), .Y(n2309) );
OAI21X1TS U1931 ( .A0(n2321), .A1(n2425), .B0(n2312), .Y(n1571) );
AO21XLTS U1932 ( .A0(d_ff3_LUT_out[7]), .A1(n2390), .B0(n1571), .Y(n1443) );
AO21XLTS U1933 ( .A0(d_ff3_LUT_out[11]), .A1(n2390), .B0(n1571), .Y(n1447)
);
NOR3X1TS U1934 ( .A(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .C(n2544), .Y(
n1704) );
BUFX4TS U1935 ( .A(n1704), .Y(n2543) );
AOI22X1TS U1936 ( .A0(add_subt_module_intDX[17]), .A1(n1565), .B0(n2532),
.B1(d_ff2_X[17]), .Y(n1573) );
AND3X1TS U1937 ( .A(sel_mux_2_reg[1]), .B(n2647), .C(n1711), .Y(n1706) );
BUFX4TS U1938 ( .A(n1706), .Y(n2540) );
BUFX4TS U1939 ( .A(n2540), .Y(n2536) );
NOR3X1TS U1940 ( .A(sel_mux_2_reg[1]), .B(n2647), .C(n2544), .Y(n1712) );
BUFX4TS U1941 ( .A(n1712), .Y(n2535) );
AOI22X1TS U1942 ( .A0(n2536), .A1(d_ff2_Z[17]), .B0(n2545), .B1(d_ff2_Y[17]),
.Y(n1572) );
NAND2X1TS U1943 ( .A(n1573), .B(n1572), .Y(n931) );
AOI22X1TS U1944 ( .A0(add_subt_module_intDX[20]), .A1(n2544), .B0(n2532),
.B1(d_ff2_X[20]), .Y(n1575) );
AOI22X1TS U1945 ( .A0(n2546), .A1(d_ff2_Z[20]), .B0(n2545), .B1(d_ff2_Y[20]),
.Y(n1574) );
NAND2X1TS U1946 ( .A(n1575), .B(n1574), .Y(n942) );
AOI22X1TS U1947 ( .A0(add_subt_module_intDX[13]), .A1(n2544), .B0(n2532),
.B1(d_ff2_X[13]), .Y(n1577) );
AOI22X1TS U1948 ( .A0(n2546), .A1(d_ff2_Z[13]), .B0(n2545), .B1(d_ff2_Y[13]),
.Y(n1576) );
NAND2X1TS U1949 ( .A(n1577), .B(n1576), .Y(n938) );
AOI22X1TS U1950 ( .A0(add_subt_module_intDX[1]), .A1(n1565), .B0(n2532),
.B1(d_ff2_X[1]), .Y(n1579) );
AOI22X1TS U1951 ( .A0(n2536), .A1(d_ff2_Z[1]), .B0(n2545), .B1(d_ff2_Y[1]),
.Y(n1578) );
NAND2X1TS U1952 ( .A(n1579), .B(n1578), .Y(n945) );
AOI22X1TS U1953 ( .A0(add_subt_module_intDX[5]), .A1(n2529), .B0(n2532),
.B1(d_ff2_X[5]), .Y(n1581) );
AOI22X1TS U1954 ( .A0(n2536), .A1(d_ff2_Z[5]), .B0(n2545), .B1(d_ff2_Y[5]),
.Y(n1580) );
NAND2X1TS U1955 ( .A(n1581), .B(n1580), .Y(n934) );
AOI22X1TS U1956 ( .A0(add_subt_module_intDY[1]), .A1(n2529), .B0(n2532),
.B1(d_ff3_sh_y_out[1]), .Y(n1583) );
AOI22X1TS U1957 ( .A0(n1706), .A1(d_ff3_LUT_out[1]), .B0(n2545), .B1(
d_ff3_sh_x_out[1]), .Y(n1582) );
NAND2X1TS U1958 ( .A(n1583), .B(n1582), .Y(n944) );
AOI22X1TS U1959 ( .A0(add_subt_module_intDY[20]), .A1(n2529), .B0(n2532),
.B1(d_ff3_sh_y_out[20]), .Y(n1585) );
AOI22X1TS U1960 ( .A0(n1706), .A1(d_ff3_LUT_out[20]), .B0(n2545), .B1(
d_ff3_sh_x_out[20]), .Y(n1584) );
NAND2X1TS U1961 ( .A(n1585), .B(n1584), .Y(n941) );
BUFX4TS U1962 ( .A(n2543), .Y(n2539) );
AOI22X1TS U1963 ( .A0(add_subt_module_intDX[9]), .A1(n2544), .B0(n2539),
.B1(d_ff2_X[9]), .Y(n1587) );
AOI22X1TS U1964 ( .A0(n2536), .A1(d_ff2_Z[9]), .B0(n2545), .B1(d_ff2_Y[9]),
.Y(n1586) );
NAND2X1TS U1965 ( .A(n1587), .B(n1586), .Y(n903) );
AOI22X1TS U1966 ( .A0(add_subt_module_intDX[11]), .A1(n2544), .B0(n2539),
.B1(d_ff2_X[11]), .Y(n1589) );
AOI22X1TS U1967 ( .A0(n2536), .A1(d_ff2_Z[11]), .B0(n2545), .B1(d_ff2_Y[11]),
.Y(n1588) );
NAND2X1TS U1968 ( .A(n1589), .B(n1588), .Y(n910) );
AOI22X1TS U1969 ( .A0(add_subt_module_intDX[14]), .A1(n2544), .B0(n2539),
.B1(d_ff2_X[14]), .Y(n1591) );
BUFX4TS U1970 ( .A(n2535), .Y(n2474) );
AOI22X1TS U1971 ( .A0(n2536), .A1(d_ff2_Z[14]), .B0(n2474), .B1(d_ff2_Y[14]),
.Y(n1590) );
NAND2X1TS U1972 ( .A(n1591), .B(n1590), .Y(n917) );
AOI22X1TS U1973 ( .A0(add_subt_module_intDY[11]), .A1(n2529), .B0(n2539),
.B1(d_ff3_sh_y_out[11]), .Y(n1593) );
AOI22X1TS U1974 ( .A0(n2536), .A1(d_ff3_LUT_out[11]), .B0(n2474), .B1(
d_ff3_sh_x_out[11]), .Y(n1592) );
NAND2X1TS U1975 ( .A(n1593), .B(n1592), .Y(n909) );
AOI22X1TS U1976 ( .A0(add_subt_module_intDY[17]), .A1(n2529), .B0(n2532),
.B1(d_ff3_sh_y_out[17]), .Y(n1595) );
AOI22X1TS U1977 ( .A0(n2536), .A1(d_ff3_LUT_out[17]), .B0(n2474), .B1(
d_ff3_sh_x_out[17]), .Y(n1594) );
NAND2X1TS U1978 ( .A(n1595), .B(n1594), .Y(n930) );
AOI22X1TS U1979 ( .A0(add_subt_module_intDY[12]), .A1(n2529), .B0(n2539),
.B1(d_ff3_sh_y_out[12]), .Y(n1597) );
AOI22X1TS U1980 ( .A0(d_ff3_LUT_out[12]), .A1(n2546), .B0(n2474), .B1(
d_ff3_sh_x_out[12]), .Y(n1596) );
NAND2X1TS U1981 ( .A(n1597), .B(n1596), .Y(n906) );
AOI22X1TS U1982 ( .A0(add_subt_module_intDX[7]), .A1(n2529), .B0(n2539),
.B1(d_ff2_X[7]), .Y(n1599) );
AOI22X1TS U1983 ( .A0(n2536), .A1(d_ff2_Z[7]), .B0(n2474), .B1(d_ff2_Y[7]),
.Y(n1598) );
NAND2X1TS U1984 ( .A(n1599), .B(n1598), .Y(n913) );
AOI22X1TS U1985 ( .A0(add_subt_module_intDX[4]), .A1(n2529), .B0(n2532),
.B1(d_ff2_X[4]), .Y(n1601) );
AOI22X1TS U1986 ( .A0(n2536), .A1(d_ff2_Z[4]), .B0(n2474), .B1(d_ff2_Y[4]),
.Y(n1600) );
NAND2X1TS U1987 ( .A(n1601), .B(n1600), .Y(n927) );
AOI22X1TS U1988 ( .A0(add_subt_module_intDY[10]), .A1(n2529), .B0(n2539),
.B1(d_ff3_sh_y_out[10]), .Y(n1603) );
AOI22X1TS U1989 ( .A0(n2536), .A1(d_ff3_LUT_out[10]), .B0(n2545), .B1(
d_ff3_sh_x_out[10]), .Y(n1602) );
NAND2X1TS U1990 ( .A(n1603), .B(n1602), .Y(n919) );
AOI22X1TS U1991 ( .A0(add_subt_module_intDX[12]), .A1(n2529), .B0(n2539),
.B1(d_ff2_X[12]), .Y(n1605) );
AOI22X1TS U1992 ( .A0(n2536), .A1(d_ff2_Z[12]), .B0(n2474), .B1(d_ff2_Y[12]),
.Y(n1604) );
NAND2X1TS U1993 ( .A(n1605), .B(n1604), .Y(n907) );
AOI22X1TS U1994 ( .A0(add_subt_module_intDY[16]), .A1(n2520), .B0(n2539),
.B1(d_ff3_sh_y_out[16]), .Y(n1607) );
AOI22X1TS U1995 ( .A0(n2536), .A1(d_ff3_LUT_out[16]), .B0(n2474), .B1(
d_ff3_sh_x_out[16]), .Y(n1606) );
NAND2X1TS U1996 ( .A(n1607), .B(n1606), .Y(n923) );
AOI22X1TS U1997 ( .A0(add_subt_module_intDY[7]), .A1(n2520), .B0(n2539),
.B1(d_ff3_sh_y_out[7]), .Y(n1609) );
AOI22X1TS U1998 ( .A0(n2536), .A1(d_ff3_LUT_out[7]), .B0(n2474), .B1(
d_ff3_sh_x_out[7]), .Y(n1608) );
NAND2X1TS U1999 ( .A(n1609), .B(n1608), .Y(n912) );
BUFX3TS U2000 ( .A(n1610), .Y(n2687) );
INVX2TS U2001 ( .A(d_ff_Yn[10]), .Y(n2392) );
NAND2X1TS U2002 ( .A(n2586), .B(cordic_FSM_state_reg[1]), .Y(n2300) );
INVX2TS U2003 ( .A(n2300), .Y(n1620) );
BUFX4TS U2004 ( .A(n1634), .Y(n1661) );
AOI22X1TS U2005 ( .A0(d_ff_Xn[10]), .A1(n1613), .B0(sign_inv_out[10]), .B1(
n1661), .Y(n1611) );
OAI21XLTS U2006 ( .A0(n2392), .A1(n1612), .B0(n1611), .Y(n1060) );
INVX2TS U2007 ( .A(d_ff_Yn[12]), .Y(n2395) );
AOI22X1TS U2008 ( .A0(d_ff_Xn[12]), .A1(n1613), .B0(sign_inv_out[12]), .B1(
n1661), .Y(n1614) );
OAI21XLTS U2009 ( .A0(n2395), .A1(n1664), .B0(n1614), .Y(n1056) );
INVX2TS U2010 ( .A(d_ff_Yn[6]), .Y(n2387) );
AOI22X1TS U2011 ( .A0(d_ff_Xn[6]), .A1(n1613), .B0(sign_inv_out[6]), .B1(
n1657), .Y(n1615) );
OAI21XLTS U2012 ( .A0(n2387), .A1(n1612), .B0(n1615), .Y(n1068) );
INVX2TS U2013 ( .A(d_ff_Yn[7]), .Y(n2388) );
AOI22X1TS U2014 ( .A0(d_ff_Xn[7]), .A1(n1613), .B0(sign_inv_out[7]), .B1(
n1657), .Y(n1616) );
OAI21XLTS U2015 ( .A0(n2388), .A1(n1612), .B0(n1616), .Y(n1066) );
INVX2TS U2016 ( .A(d_ff_Yn[1]), .Y(n2382) );
AOI22X1TS U2017 ( .A0(d_ff_Xn[1]), .A1(n1613), .B0(sign_inv_out[1]), .B1(
n1657), .Y(n1617) );
OAI21XLTS U2018 ( .A0(n2382), .A1(n1612), .B0(n1617), .Y(n1078) );
INVX2TS U2019 ( .A(d_ff_Yn[9]), .Y(n2391) );
AOI22X1TS U2020 ( .A0(d_ff_Xn[9]), .A1(n1613), .B0(sign_inv_out[9]), .B1(
n1661), .Y(n1618) );
OAI21XLTS U2021 ( .A0(n2391), .A1(n1612), .B0(n1618), .Y(n1062) );
XOR2XLTS U2022 ( .A(n2552), .B(d_ff1_operation_out), .Y(n1619) );
XNOR2X1TS U2023 ( .A(n2582), .B(n1619), .Y(n2163) );
NAND3XLTS U2024 ( .A(cordic_FSM_state_reg[3]), .B(n1620), .C(n2588), .Y(
n1622) );
NAND3XLTS U2025 ( .A(n1622), .B(sel_mux_3_reg), .C(n2699), .Y(n1621) );
OAI21XLTS U2026 ( .A0(n2163), .A1(n1622), .B0(n1621), .Y(n1372) );
NAND3X1TS U2027 ( .A(n2588), .B(cordic_FSM_state_reg[1]), .C(n1822), .Y(
n2164) );
NAND3X2TS U2028 ( .A(cont_iter_out[1]), .B(n2663), .C(n1643), .Y(n2349) );
INVX2TS U2029 ( .A(n2349), .Y(n2281) );
INVX2TS U2030 ( .A(n2164), .Y(n2166) );
NAND2X1TS U2031 ( .A(sel_mux_2_reg[1]), .B(n2699), .Y(n1623) );
OAI32X1TS U2032 ( .A0(n2164), .A1(n2281), .A2(n2581), .B0(n2166), .B1(n1623),
.Y(n1464) );
OR3X1TS U2033 ( .A(n2300), .B(cordic_FSM_state_reg[3]), .C(
cordic_FSM_state_reg[0]), .Y(n2296) );
NOR2X2TS U2034 ( .A(cont_var_out[0]), .B(n2581), .Y(n2350) );
NAND4XLTS U2035 ( .A(n2586), .B(n2556), .C(cordic_FSM_state_reg[3]), .D(
cordic_FSM_state_reg[0]), .Y(n2046) );
INVX2TS U2036 ( .A(n2046), .Y(n1824) );
NAND2X1TS U2037 ( .A(n1531), .B(n2294), .Y(n2295) );
NAND4XLTS U2038 ( .A(n1824), .B(n2663), .C(n2350), .D(n2566), .Y(n1624) );
OAI2BB1X1TS U2039 ( .A0N(n2315), .A1N(n1624), .B0(n1531), .Y(n1625) );
OAI21XLTS U2040 ( .A0(n2295), .A1(n2566), .B0(n1625), .Y(n1503) );
INVX2TS U2041 ( .A(d_ff_Yn[5]), .Y(n2386) );
AOI22X1TS U2042 ( .A0(d_ff_Xn[5]), .A1(n1645), .B0(sign_inv_out[5]), .B1(
n1657), .Y(n1626) );
OAI21XLTS U2043 ( .A0(n2386), .A1(n1612), .B0(n1626), .Y(n1070) );
INVX2TS U2044 ( .A(d_ff_Yn[11]), .Y(n2393) );
AOI22X1TS U2045 ( .A0(d_ff_Xn[11]), .A1(n1645), .B0(sign_inv_out[11]), .B1(
n1661), .Y(n1627) );
OAI21XLTS U2046 ( .A0(n2393), .A1(n1612), .B0(n1627), .Y(n1058) );
INVX2TS U2047 ( .A(d_ff_Yn[2]), .Y(n2383) );
AOI22X1TS U2048 ( .A0(d_ff_Xn[2]), .A1(n1645), .B0(sign_inv_out[2]), .B1(
n1657), .Y(n1628) );
OAI21XLTS U2049 ( .A0(n2383), .A1(n1612), .B0(n1628), .Y(n1076) );
INVX2TS U2050 ( .A(d_ff_Yn[3]), .Y(n2384) );
AOI22X1TS U2051 ( .A0(d_ff_Xn[3]), .A1(n1645), .B0(sign_inv_out[3]), .B1(
n1657), .Y(n1629) );
OAI21XLTS U2052 ( .A0(n2384), .A1(n1612), .B0(n1629), .Y(n1074) );
NAND3XLTS U2053 ( .A(n2349), .B(cont_var_out[0]), .C(n1824), .Y(n1631) );
INVX2TS U2054 ( .A(n1631), .Y(n1632) );
AOI31XLTS U2055 ( .A0(n1824), .A1(n2581), .A2(n2349), .B0(cont_var_out[0]),
.Y(n1630) );
NOR3XLTS U2056 ( .A(n2436), .B(n1632), .C(n1630), .Y(n1507) );
AOI22X1TS U2057 ( .A0(d_ff_Xn[27]), .A1(n1662), .B0(sign_inv_out[27]), .B1(
n1634), .Y(n1633) );
OAI21XLTS U2058 ( .A0(n1557), .A1(n1664), .B0(n1633), .Y(n1026) );
AOI22X1TS U2059 ( .A0(d_ff_Xn[30]), .A1(n1662), .B0(sign_inv_out[30]), .B1(
n1634), .Y(n1635) );
OAI21XLTS U2060 ( .A0(n1556), .A1(n1612), .B0(n1635), .Y(n1020) );
INVX2TS U2061 ( .A(d_ff_Yn[31]), .Y(n2442) );
AOI22X1TS U2062 ( .A0(d_ff_Xn[31]), .A1(n1662), .B0(data_output2_31_), .B1(
n1657), .Y(n1636) );
OAI21XLTS U2063 ( .A0(n2442), .A1(n1612), .B0(n1636), .Y(n1018) );
INVX2TS U2064 ( .A(d_ff_Yn[28]), .Y(n2415) );
AOI22X1TS U2065 ( .A0(d_ff_Xn[28]), .A1(n1662), .B0(sign_inv_out[28]), .B1(
n1661), .Y(n1637) );
OAI21XLTS U2066 ( .A0(n2415), .A1(n1612), .B0(n1637), .Y(n1024) );
INVX2TS U2067 ( .A(d_ff_Yn[29]), .Y(n2417) );
AOI22X1TS U2068 ( .A0(d_ff_Xn[29]), .A1(n1662), .B0(sign_inv_out[29]), .B1(
n1657), .Y(n1638) );
OAI21XLTS U2069 ( .A0(n2417), .A1(n1664), .B0(n1638), .Y(n1022) );
INVX2TS U2070 ( .A(d_ff_Yn[0]), .Y(n2381) );
AOI22X1TS U2071 ( .A0(d_ff_Xn[0]), .A1(n1662), .B0(sign_inv_out[0]), .B1(
n1657), .Y(n1639) );
OAI21XLTS U2072 ( .A0(n2381), .A1(n1612), .B0(n1639), .Y(n1080) );
INVX2TS U2073 ( .A(d_ff_Yn[26]), .Y(n2413) );
AOI22X1TS U2074 ( .A0(d_ff_Xn[26]), .A1(n1662), .B0(sign_inv_out[26]), .B1(
n1661), .Y(n1640) );
OAI21XLTS U2075 ( .A0(n2413), .A1(n1664), .B0(n1640), .Y(n1028) );
INVX2TS U2076 ( .A(n2295), .Y(n1641) );
AOI21X1TS U2077 ( .A0(n1531), .A1(n2305), .B0(n1641), .Y(n2293) );
AOI22X1TS U2078 ( .A0(n2436), .A1(n2422), .B0(d_ff3_sh_y_out[23]), .B1(n2425), .Y(n1642) );
OAI31X1TS U2079 ( .A0(n2663), .A1(n1558), .A2(n2584), .B0(n1642), .Y(n1091)
);
OAI21XLTS U2080 ( .A0(n2702), .A1(n2309), .B0(n1644), .Y(n1459) );
OR2X1TS U2081 ( .A(d_ff3_LUT_out[27]), .B(n2434), .Y(n1463) );
INVX2TS U2082 ( .A(d_ff_Yn[16]), .Y(n2401) );
AOI22X1TS U2083 ( .A0(d_ff_Xn[16]), .A1(n1645), .B0(sign_inv_out[16]), .B1(
n1661), .Y(n1646) );
OAI21XLTS U2084 ( .A0(n2401), .A1(n1664), .B0(n1646), .Y(n1048) );
INVX2TS U2085 ( .A(d_ff_Yn[15]), .Y(n2400) );
AOI22X1TS U2086 ( .A0(d_ff_Xn[15]), .A1(n1645), .B0(sign_inv_out[15]), .B1(
n1661), .Y(n1647) );
OAI21XLTS U2087 ( .A0(n2400), .A1(n1664), .B0(n1647), .Y(n1050) );
INVX2TS U2088 ( .A(d_ff_Yn[22]), .Y(n2408) );
AOI22X1TS U2089 ( .A0(d_ff_Xn[22]), .A1(n1645), .B0(sign_inv_out[22]), .B1(
n1657), .Y(n1648) );
OAI21XLTS U2090 ( .A0(n2408), .A1(n1664), .B0(n1648), .Y(n1036) );
INVX2TS U2091 ( .A(d_ff_Yn[8]), .Y(n2389) );
AOI22X1TS U2092 ( .A0(d_ff_Xn[8]), .A1(n1645), .B0(sign_inv_out[8]), .B1(
n1661), .Y(n1649) );
OAI21XLTS U2093 ( .A0(n2389), .A1(n1664), .B0(n1649), .Y(n1064) );
INVX2TS U2094 ( .A(d_ff_Yn[19]), .Y(n2405) );
AOI22X1TS U2095 ( .A0(d_ff_Xn[19]), .A1(n1645), .B0(sign_inv_out[19]), .B1(
n1661), .Y(n1650) );
OAI21XLTS U2096 ( .A0(n2405), .A1(n1664), .B0(n1650), .Y(n1042) );
INVX2TS U2097 ( .A(d_ff_Yn[13]), .Y(n2396) );
AOI22X1TS U2098 ( .A0(d_ff_Xn[13]), .A1(n1645), .B0(sign_inv_out[13]), .B1(
n1661), .Y(n1651) );
OAI21XLTS U2099 ( .A0(n2396), .A1(n1664), .B0(n1651), .Y(n1054) );
INVX2TS U2100 ( .A(d_ff_Yn[20]), .Y(n2406) );
AOI22X1TS U2101 ( .A0(d_ff_Xn[20]), .A1(n1662), .B0(sign_inv_out[20]), .B1(
n1661), .Y(n1652) );
OAI21XLTS U2102 ( .A0(n2406), .A1(n1664), .B0(n1652), .Y(n1040) );
INVX2TS U2103 ( .A(d_ff_Yn[21]), .Y(n2407) );
AOI22X1TS U2104 ( .A0(d_ff_Xn[21]), .A1(n1662), .B0(sign_inv_out[21]), .B1(
n1657), .Y(n1653) );
OAI21XLTS U2105 ( .A0(n2407), .A1(n1664), .B0(n1653), .Y(n1038) );
INVX2TS U2106 ( .A(d_ff_Yn[23]), .Y(n2409) );
AOI22X1TS U2107 ( .A0(d_ff_Xn[23]), .A1(n1662), .B0(sign_inv_out[23]), .B1(
n1661), .Y(n1654) );
OAI21XLTS U2108 ( .A0(n2409), .A1(n1664), .B0(n1654), .Y(n1034) );
INVX2TS U2109 ( .A(d_ff_Yn[18]), .Y(n2404) );
AOI22X1TS U2110 ( .A0(d_ff_Xn[18]), .A1(n1662), .B0(sign_inv_out[18]), .B1(
n1661), .Y(n1655) );
OAI21XLTS U2111 ( .A0(n2404), .A1(n1664), .B0(n1655), .Y(n1044) );
INVX2TS U2112 ( .A(d_ff_Yn[25]), .Y(n2411) );
AOI22X1TS U2113 ( .A0(d_ff_Xn[25]), .A1(n1662), .B0(sign_inv_out[25]), .B1(
n1661), .Y(n1656) );
OAI21XLTS U2114 ( .A0(n2411), .A1(n1664), .B0(n1656), .Y(n1030) );
INVX2TS U2115 ( .A(d_ff_Yn[4]), .Y(n2385) );
AOI22X1TS U2116 ( .A0(d_ff_Xn[4]), .A1(n1662), .B0(sign_inv_out[4]), .B1(
n1657), .Y(n1658) );
OAI21XLTS U2117 ( .A0(n2385), .A1(n1664), .B0(n1658), .Y(n1072) );
INVX2TS U2118 ( .A(d_ff_Yn[24]), .Y(n2410) );
AOI22X1TS U2119 ( .A0(d_ff_Xn[24]), .A1(n1662), .B0(sign_inv_out[24]), .B1(
n1661), .Y(n1659) );
INVX2TS U2120 ( .A(d_ff_Yn[17]), .Y(n2403) );
AOI22X1TS U2121 ( .A0(d_ff_Xn[17]), .A1(n1662), .B0(sign_inv_out[17]), .B1(
n1661), .Y(n1660) );
OAI21XLTS U2122 ( .A0(n2403), .A1(n1664), .B0(n1660), .Y(n1046) );
INVX2TS U2123 ( .A(d_ff_Yn[14]), .Y(n2398) );
AOI22X1TS U2124 ( .A0(d_ff_Xn[14]), .A1(n1662), .B0(sign_inv_out[14]), .B1(
n1661), .Y(n1663) );
NOR2X1TS U2125 ( .A(n2273), .B(n2270), .Y(n1665) );
INVX4TS U2126 ( .A(n1665), .Y(n2402) );
INVX2TS U2127 ( .A(n1667), .Y(n1154) );
INVX2TS U2128 ( .A(n1668), .Y(n1153) );
INVX2TS U2129 ( .A(n1669), .Y(n1152) );
AOI222X1TS U2130 ( .A0(n2402), .A1(d_ff2_Z[31]), .B0(n1691), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n2418), .Y(n1670) );
INVX2TS U2131 ( .A(n1670), .Y(n1148) );
AOI222X1TS U2132 ( .A0(n2402), .A1(d_ff2_Z[13]), .B0(n1691), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n2418), .Y(n1671) );
INVX2TS U2133 ( .A(n1671), .Y(n1166) );
AOI222X1TS U2134 ( .A0(n2402), .A1(d_ff2_Z[28]), .B0(n1702), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n2418), .Y(n1672) );
INVX2TS U2135 ( .A(n1672), .Y(n1151) );
INVX2TS U2136 ( .A(n1673), .Y(n1165) );
AOI222X1TS U2137 ( .A0(n2402), .A1(d_ff2_Z[30]), .B0(n1702), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n2418), .Y(n1674) );
INVX2TS U2138 ( .A(n1674), .Y(n1149) );
AOI222X1TS U2139 ( .A0(n2402), .A1(d_ff2_Z[29]), .B0(n1691), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n2418), .Y(n1675) );
INVX2TS U2140 ( .A(n1675), .Y(n1150) );
NAND2X2TS U2141 ( .A(n2557), .B(n2224), .Y(n2364) );
INVX2TS U2142 ( .A(n2224), .Y(n2105) );
INVX2TS U2143 ( .A(n2225), .Y(n1833) );
AOI21X1TS U2144 ( .A0(add_subt_module_FSM_selector_B[1]), .A1(n2105), .B0(
n2145), .Y(n1676) );
OAI21XLTS U2145 ( .A0(n2364), .A1(n2598), .B0(n1676), .Y(n1516) );
AOI21X1TS U2146 ( .A0(d_ff3_LUT_out[9]), .A1(n2425), .B0(n2324), .Y(n1677)
);
OAI31X1TS U2147 ( .A0(n2662), .A1(n2390), .A2(n2315), .B0(n1677), .Y(n1445)
);
BUFX4TS U2148 ( .A(n2418), .Y(n2414) );
INVX2TS U2149 ( .A(n1678), .Y(n1162) );
INVX2TS U2150 ( .A(n1679), .Y(n1163) );
AOI222X1TS U2151 ( .A0(n1700), .A1(d_ff2_Z[19]), .B0(n1691), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n2414), .Y(n1680) );
INVX2TS U2152 ( .A(n1680), .Y(n1160) );
AOI222X1TS U2153 ( .A0(n1700), .A1(d_ff2_Z[15]), .B0(n1691), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n2414), .Y(n1681) );
INVX2TS U2154 ( .A(n1681), .Y(n1164) );
AOI222X1TS U2155 ( .A0(n1700), .A1(d_ff2_Z[5]), .B0(n1702), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n2414), .Y(n1682) );
INVX2TS U2156 ( .A(n1682), .Y(n1174) );
INVX2TS U2157 ( .A(n1683), .Y(n1155) );
AOI222X1TS U2158 ( .A0(n2402), .A1(d_ff2_Z[22]), .B0(n1691), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n2414), .Y(n1684) );
INVX2TS U2159 ( .A(n1684), .Y(n1157) );
AOI222X1TS U2160 ( .A0(n1700), .A1(d_ff2_Z[18]), .B0(n1691), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n2414), .Y(n1685) );
INVX2TS U2161 ( .A(n1685), .Y(n1161) );
AOI222X1TS U2162 ( .A0(n2402), .A1(d_ff2_Z[23]), .B0(n1691), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n2414), .Y(n1686) );
INVX2TS U2163 ( .A(n1686), .Y(n1156) );
AOI222X1TS U2164 ( .A0(n1700), .A1(d_ff2_Z[7]), .B0(n1702), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n2414), .Y(n1687) );
INVX2TS U2165 ( .A(n1687), .Y(n1172) );
AOI222X1TS U2166 ( .A0(n1700), .A1(d_ff2_Z[9]), .B0(n1702), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n2414), .Y(n1688) );
INVX2TS U2167 ( .A(n1688), .Y(n1170) );
AOI222X1TS U2168 ( .A0(n1700), .A1(d_ff2_Z[20]), .B0(n1691), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n2414), .Y(n1689) );
INVX2TS U2169 ( .A(n1689), .Y(n1159) );
AOI222X1TS U2170 ( .A0(n1700), .A1(d_ff2_Z[6]), .B0(n1702), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n2414), .Y(n1690) );
INVX2TS U2171 ( .A(n1690), .Y(n1173) );
AOI222X1TS U2172 ( .A0(n1700), .A1(d_ff2_Z[21]), .B0(n1691), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n2414), .Y(n1692) );
INVX2TS U2173 ( .A(n1692), .Y(n1158) );
BUFX4TS U2174 ( .A(n2418), .Y(n2347) );
AOI222X1TS U2175 ( .A0(n2402), .A1(d_ff2_Z[8]), .B0(n1702), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n2347), .Y(n1693) );
INVX2TS U2176 ( .A(n1693), .Y(n1171) );
AOI222X1TS U2177 ( .A0(n1700), .A1(d_ff2_Z[1]), .B0(n1691), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n2347), .Y(n1694) );
INVX2TS U2178 ( .A(n1694), .Y(n1178) );
AOI222X1TS U2179 ( .A0(n1700), .A1(d_ff2_Z[3]), .B0(n1691), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n2347), .Y(n1695) );
INVX2TS U2180 ( .A(n1695), .Y(n1176) );
AOI222X1TS U2181 ( .A0(n1700), .A1(d_ff2_Z[12]), .B0(n1691), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n2347), .Y(n1696) );
INVX2TS U2182 ( .A(n1696), .Y(n1167) );
INVX2TS U2183 ( .A(n1697), .Y(n1169) );
AOI222X1TS U2184 ( .A0(n1700), .A1(d_ff2_Z[4]), .B0(n1691), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n2347), .Y(n1698) );
INVX2TS U2185 ( .A(n1698), .Y(n1175) );
AOI222X1TS U2186 ( .A0(n1700), .A1(d_ff2_Z[0]), .B0(n1691), .B1(d_ff1_Z[0]),
.C0(d_ff_Zn[0]), .C1(n2347), .Y(n1699) );
INVX2TS U2187 ( .A(n1699), .Y(n1179) );
AOI222X1TS U2188 ( .A0(n1700), .A1(d_ff2_Z[2]), .B0(n1691), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n2347), .Y(n1701) );
INVX2TS U2189 ( .A(n1701), .Y(n1177) );
INVX2TS U2190 ( .A(n1703), .Y(n1168) );
BUFX3TS U2191 ( .A(n1704), .Y(n2473) );
AOI22X1TS U2192 ( .A0(d_ff3_sh_x_out[30]), .A1(n2474), .B0(
d_ff3_sh_y_out[30]), .B1(n2473), .Y(n1705) );
OAI21XLTS U2193 ( .A0(n1711), .A1(n2627), .B0(n1705), .Y(n1012) );
AOI22X1TS U2194 ( .A0(n2474), .A1(d_ff3_sh_x_out[27]), .B0(n2473), .B1(
d_ff3_sh_y_out[27]), .Y(n1707) );
NAND2X1TS U2195 ( .A(n1706), .B(d_ff3_LUT_out[27]), .Y(n1709) );
OAI211XLTS U2196 ( .A0(n1711), .A1(n2549), .B0(n1707), .C0(n1709), .Y(n1009)
);
AOI22X1TS U2197 ( .A0(n2474), .A1(d_ff3_sh_x_out[29]), .B0(n2473), .B1(
d_ff3_sh_y_out[29]), .Y(n1708) );
OAI211XLTS U2198 ( .A0(n1711), .A1(n2580), .B0(n1708), .C0(n1709), .Y(n1011)
);
AOI22X1TS U2199 ( .A0(n2474), .A1(d_ff3_sh_x_out[28]), .B0(n2473), .B1(
d_ff3_sh_y_out[28]), .Y(n1710) );
OAI211XLTS U2200 ( .A0(n1711), .A1(n2606), .B0(n1710), .C0(n1709), .Y(n1010)
);
BUFX3TS U2201 ( .A(n1712), .Y(n2487) );
INVX2TS U2202 ( .A(n1713), .Y(n1004) );
NOR2X2TS U2203 ( .A(n2227), .B(n1833), .Y(n2288) );
INVX2TS U2204 ( .A(n2288), .Y(n1835) );
NOR2X1TS U2205 ( .A(n2623), .B(add_subt_module_intDX[25]), .Y(n1773) );
NOR2XLTS U2206 ( .A(n1773), .B(add_subt_module_intDY[24]), .Y(n1714) );
AOI22X1TS U2207 ( .A0(add_subt_module_intDX[25]), .A1(n2623), .B0(
add_subt_module_intDX[24]), .B1(n1714), .Y(n1718) );
OAI21X1TS U2208 ( .A0(add_subt_module_intDX[26]), .A1(n2622), .B0(n1715),
.Y(n1774) );
NAND3XLTS U2209 ( .A(n2622), .B(n1715), .C(add_subt_module_intDX[26]), .Y(
n1717) );
NAND2BXLTS U2210 ( .AN(add_subt_module_intDY[27]), .B(
add_subt_module_intDX[27]), .Y(n1716) );
OAI211XLTS U2211 ( .A0(n1718), .A1(n1774), .B0(n1717), .C0(n1716), .Y(n1723)
);
NOR2X1TS U2212 ( .A(n2627), .B(add_subt_module_intDX[30]), .Y(n1721) );
NOR2X1TS U2213 ( .A(n2580), .B(add_subt_module_intDX[29]), .Y(n1719) );
AOI211X1TS U2214 ( .A0(add_subt_module_intDY[28]), .A1(n2593), .B0(n1721),
.C0(n1719), .Y(n1772) );
NOR3XLTS U2215 ( .A(n2593), .B(n1719), .C(add_subt_module_intDY[28]), .Y(
n1720) );
AOI2BB2X1TS U2216 ( .B0(n1723), .B1(n1772), .A0N(n1722), .A1N(n1721), .Y(
n1778) );
NOR2X1TS U2217 ( .A(n2595), .B(add_subt_module_intDX[17]), .Y(n1759) );
NAND2BXLTS U2218 ( .AN(add_subt_module_intDX[9]), .B(
add_subt_module_intDY[9]), .Y(n1740) );
NOR2X1TS U2219 ( .A(n2597), .B(add_subt_module_intDX[11]), .Y(n1738) );
AOI21X1TS U2220 ( .A0(add_subt_module_intDY[10]), .A1(n2610), .B0(n1738),
.Y(n1743) );
OAI211XLTS U2221 ( .A0(add_subt_module_intDX[8]), .A1(n2596), .B0(n1740),
.C0(n1743), .Y(n1754) );
OAI2BB1X1TS U2222 ( .A0N(n2577), .A1N(add_subt_module_intDY[5]), .B0(
add_subt_module_intDX[4]), .Y(n1724) );
OAI22X1TS U2223 ( .A0(add_subt_module_intDY[4]), .A1(n1724), .B0(n2577),
.B1(add_subt_module_intDY[5]), .Y(n1735) );
OAI2BB1X1TS U2224 ( .A0N(n2576), .A1N(add_subt_module_intDY[7]), .B0(
add_subt_module_intDX[6]), .Y(n1725) );
OAI22X1TS U2225 ( .A0(add_subt_module_intDY[6]), .A1(n1725), .B0(n2576),
.B1(add_subt_module_intDY[7]), .Y(n1734) );
OAI2BB2XLTS U2226 ( .B0(add_subt_module_intDY[0]), .B1(n1726), .A0N(
add_subt_module_intDX[1]), .A1N(n2591), .Y(n1728) );
NAND2BXLTS U2227 ( .AN(add_subt_module_intDX[2]), .B(
add_subt_module_intDY[2]), .Y(n1727) );
OAI211XLTS U2228 ( .A0(n2589), .A1(add_subt_module_intDX[3]), .B0(n1728),
.C0(n1727), .Y(n1731) );
OAI21XLTS U2229 ( .A0(add_subt_module_intDX[3]), .A1(n2589), .B0(
add_subt_module_intDX[2]), .Y(n1729) );
AOI2BB2XLTS U2230 ( .B0(add_subt_module_intDX[3]), .B1(n2589), .A0N(
add_subt_module_intDY[2]), .A1N(n1729), .Y(n1730) );
AOI22X1TS U2231 ( .A0(add_subt_module_intDY[7]), .A1(n2576), .B0(
add_subt_module_intDY[6]), .B1(n2621), .Y(n1732) );
OAI32X1TS U2232 ( .A0(n1735), .A1(n1734), .A2(n1733), .B0(n1732), .B1(n1734),
.Y(n1753) );
OA22X1TS U2233 ( .A0(n2590), .A1(add_subt_module_intDX[14]), .B0(n2567),
.B1(add_subt_module_intDX[15]), .Y(n1750) );
NAND2BXLTS U2234 ( .AN(add_subt_module_intDX[13]), .B(
add_subt_module_intDY[13]), .Y(n1736) );
OAI21XLTS U2235 ( .A0(add_subt_module_intDX[13]), .A1(n2594), .B0(
add_subt_module_intDX[12]), .Y(n1737) );
OAI2BB2XLTS U2236 ( .B0(add_subt_module_intDY[12]), .B1(n1737), .A0N(
add_subt_module_intDX[13]), .A1N(n2594), .Y(n1749) );
NOR2XLTS U2237 ( .A(n1738), .B(add_subt_module_intDY[10]), .Y(n1739) );
AOI22X1TS U2238 ( .A0(add_subt_module_intDX[11]), .A1(n2597), .B0(
add_subt_module_intDX[10]), .B1(n1739), .Y(n1745) );
NAND3XLTS U2239 ( .A(n2596), .B(n1740), .C(add_subt_module_intDX[8]), .Y(
n1741) );
AOI21X1TS U2240 ( .A0(n1742), .A1(n1741), .B0(n1752), .Y(n1744) );
OAI2BB2XLTS U2241 ( .B0(n1745), .B1(n1752), .A0N(n1744), .A1N(n1743), .Y(
n1748) );
OAI2BB2XLTS U2242 ( .B0(add_subt_module_intDY[14]), .B1(n1746), .A0N(
add_subt_module_intDX[15]), .A1N(n2567), .Y(n1747) );
AOI211X1TS U2243 ( .A0(n1750), .A1(n1749), .B0(n1748), .C0(n1747), .Y(n1751)
);
OAI31X1TS U2244 ( .A0(n1754), .A1(n1753), .A2(n1752), .B0(n1751), .Y(n1757)
);
OA22X1TS U2245 ( .A0(n2569), .A1(add_subt_module_intDX[22]), .B0(n2636),
.B1(add_subt_module_intDX[23]), .Y(n1770) );
NAND2BXLTS U2246 ( .AN(add_subt_module_intDX[21]), .B(
add_subt_module_intDY[21]), .Y(n1755) );
NAND2BXLTS U2247 ( .AN(add_subt_module_intDX[19]), .B(
add_subt_module_intDY[19]), .Y(n1761) );
OAI21X1TS U2248 ( .A0(add_subt_module_intDX[18]), .A1(n2603), .B0(n1761),
.Y(n1765) );
NAND3BXLTS U2249 ( .AN(n1759), .B(n1757), .C(n1756), .Y(n1777) );
OAI2BB2XLTS U2250 ( .B0(add_subt_module_intDY[20]), .B1(n1758), .A0N(
add_subt_module_intDX[21]), .A1N(n2602), .Y(n1769) );
AOI22X1TS U2251 ( .A0(add_subt_module_intDX[17]), .A1(n2595), .B0(
add_subt_module_intDX[16]), .B1(n1760), .Y(n1763) );
AOI32X1TS U2252 ( .A0(n2603), .A1(n1761), .A2(add_subt_module_intDX[18]),
.B0(add_subt_module_intDX[19]), .B1(n2574), .Y(n1762) );
OAI32X1TS U2253 ( .A0(n1765), .A1(n1764), .A2(n1763), .B0(n1762), .B1(n1764),
.Y(n1768) );
OAI21XLTS U2254 ( .A0(add_subt_module_intDX[23]), .A1(n2636), .B0(
add_subt_module_intDX[22]), .Y(n1766) );
OAI2BB2XLTS U2255 ( .B0(add_subt_module_intDY[22]), .B1(n1766), .A0N(
add_subt_module_intDX[23]), .A1N(n2636), .Y(n1767) );
AOI211X1TS U2256 ( .A0(n1770), .A1(n1769), .B0(n1768), .C0(n1767), .Y(n1776)
);
NAND4BBX1TS U2257 ( .AN(n1774), .BN(n1773), .C(n1772), .D(n1771), .Y(n1775)
);
AOI32X1TS U2258 ( .A0(n1778), .A1(n1777), .A2(n1776), .B0(n1775), .B1(n1778),
.Y(n1815) );
NOR2XLTS U2259 ( .A(n1779), .B(n1815), .Y(n1817) );
AOI22X1TS U2260 ( .A0(add_subt_module_intDY[23]), .A1(
add_subt_module_intDX[23]), .B0(n2628), .B1(n2636), .Y(n1786) );
AOI22X1TS U2261 ( .A0(n2572), .A1(add_subt_module_intDY[15]), .B0(n2601),
.B1(add_subt_module_intDY[13]), .Y(n1780) );
OAI221XLTS U2262 ( .A0(n2572), .A1(add_subt_module_intDY[15]), .B0(n2601),
.B1(add_subt_module_intDY[13]), .C0(n1780), .Y(n1785) );
AOI22X1TS U2263 ( .A0(n2610), .A1(add_subt_module_intDY[10]), .B0(n2620),
.B1(add_subt_module_intDY[2]), .Y(n1781) );
AOI22X1TS U2264 ( .A0(n2578), .A1(add_subt_module_intDY[9]), .B0(n2618),
.B1(add_subt_module_intDY[11]), .Y(n1782) );
NOR4X1TS U2265 ( .A(n1786), .B(n1785), .C(n1784), .D(n1783), .Y(n1814) );
AOI22X1TS U2266 ( .A0(n2576), .A1(add_subt_module_intDY[7]), .B0(n2616),
.B1(add_subt_module_intDY[14]), .Y(n1787) );
AOI22X1TS U2267 ( .A0(n2577), .A1(add_subt_module_intDY[5]), .B0(n2619),
.B1(add_subt_module_intDY[4]), .Y(n1788) );
AOI22X1TS U2268 ( .A0(n2600), .A1(add_subt_module_intDY[3]), .B0(n2622),
.B1(add_subt_module_intDX[26]), .Y(n1789) );
AOI22X1TS U2269 ( .A0(n2579), .A1(add_subt_module_intDY[1]), .B0(n2613),
.B1(add_subt_module_intDX[0]), .Y(n1790) );
NOR4X1TS U2270 ( .A(n1794), .B(n1793), .C(n1792), .D(n1791), .Y(n1813) );
AOI22X1TS U2271 ( .A0(n2606), .A1(add_subt_module_intDX[28]), .B0(n2621),
.B1(add_subt_module_intDY[6]), .Y(n1795) );
AOI22X1TS U2272 ( .A0(n2607), .A1(add_subt_module_intDY[18]), .B0(n2580),
.B1(add_subt_module_intDX[29]), .Y(n1796) );
AOI22X1TS U2273 ( .A0(n2549), .A1(add_subt_module_intDX[27]), .B0(n2615),
.B1(add_subt_module_intDY[19]), .Y(n1797) );
AOI22X1TS U2274 ( .A0(n2623), .A1(add_subt_module_intDX[25]), .B0(n2614),
.B1(add_subt_module_intDX[24]), .Y(n1798) );
NOR4X1TS U2275 ( .A(n1802), .B(n1801), .C(n1800), .D(n1799), .Y(n1812) );
AOI22X1TS U2276 ( .A0(n2608), .A1(add_subt_module_intDY[20]), .B0(n2627),
.B1(add_subt_module_intDX[30]), .Y(n1803) );
AOI22X1TS U2277 ( .A0(n2611), .A1(add_subt_module_intDY[8]), .B0(n2573),
.B1(add_subt_module_intDY[21]), .Y(n1804) );
OAI221XLTS U2278 ( .A0(n2611), .A1(add_subt_module_intDY[8]), .B0(n2573),
.B1(add_subt_module_intDY[21]), .C0(n1804), .Y(n1809) );
AOI22X1TS U2279 ( .A0(n2609), .A1(add_subt_module_intDY[17]), .B0(n2626),
.B1(add_subt_module_intDY[16]), .Y(n1805) );
AOI22X1TS U2280 ( .A0(n2612), .A1(add_subt_module_intDY[22]), .B0(n2617),
.B1(add_subt_module_intDX[12]), .Y(n1806) );
NOR4X1TS U2281 ( .A(n1810), .B(n1809), .C(n1808), .D(n1807), .Y(n1811) );
NAND4XLTS U2282 ( .A(n1814), .B(n1813), .C(n1812), .D(n1811), .Y(n1820) );
INVX2TS U2283 ( .A(n1815), .Y(n1836) );
AOI21X1TS U2284 ( .A0(n1820), .A1(n1836), .B0(add_subt_module_intDX[31]),
.Y(n1816) );
OAI32X1TS U2285 ( .A0(n2142), .A1(n1817), .A2(n1816), .B0(n2288), .B1(n2641),
.Y(n1001) );
NAND2X1TS U2286 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(
add_subt_module_FS_Module_state_reg[3]), .Y(n2103) );
INVX2TS U2287 ( .A(n2286), .Y(n2149) );
INVX2TS U2288 ( .A(n2107), .Y(n2143) );
OAI22X1TS U2289 ( .A0(add_subt_module_FS_Module_state_reg[1]), .A1(n2227),
.B0(n1546), .B1(n2033), .Y(n1821) );
NOR4X1TS U2290 ( .A(n2145), .B(n2149), .C(n2151), .D(n1821), .Y(n1825) );
OR2X1TS U2291 ( .A(n2147), .B(n2287), .Y(n2282) );
NAND3XLTS U2292 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.C(n1822), .Y(n2049) );
INVX2TS U2293 ( .A(n2049), .Y(n1823) );
NOR2XLTS U2294 ( .A(n1825), .B(n2289), .Y(n1510) );
INVX2TS U2295 ( .A(n2228), .Y(n2140) );
NAND2X1TS U2296 ( .A(n2140), .B(add_subt_module_FSM_selector_C), .Y(n1832)
);
INVX2TS U2297 ( .A(n1922), .Y(n1973) );
NOR2XLTS U2298 ( .A(add_subt_module_FSM_selector_B[1]), .B(n2599), .Y(n1827)
);
CLKBUFX3TS U2299 ( .A(n1827), .Y(n2205) );
NOR2XLTS U2300 ( .A(add_subt_module_FSM_selector_B[1]), .B(
add_subt_module_FSM_selector_B[0]), .Y(n1828) );
BUFX3TS U2301 ( .A(n1828), .Y(n2204) );
AOI22X1TS U2302 ( .A0(add_subt_module_LZA_output[2]), .A1(n2205), .B0(
add_subt_module_exp_oper_result[2]), .B1(n2204), .Y(n1877) );
NAND2X1TS U2303 ( .A(n2205), .B(add_subt_module_LZA_output[0]), .Y(n1830) );
NAND2X1TS U2304 ( .A(n2599), .B(add_subt_module_FSM_selector_B[1]), .Y(n1829) );
NAND2X1TS U2305 ( .A(n1830), .B(n1829), .Y(n2207) );
NOR2XLTS U2306 ( .A(n2266), .B(n1831), .Y(n1834) );
OAI32X1TS U2307 ( .A0(n2255), .A1(n2266), .A2(n1831), .B0(n1834), .B1(n2267),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]) );
INVX2TS U2308 ( .A(n1840), .Y(n1866) );
BUFX4TS U2309 ( .A(n2142), .Y(n2029) );
AOI22X1TS U2310 ( .A0(n1866), .A1(add_subt_module_intDX[28]), .B0(
add_subt_module_DmP[28]), .B1(n2029), .Y(n1837) );
OAI21XLTS U2311 ( .A0(n2606), .A1(n2022), .B0(n1837), .Y(n993) );
AOI22X1TS U2312 ( .A0(n1866), .A1(add_subt_module_intDX[26]), .B0(
add_subt_module_DmP[26]), .B1(n2029), .Y(n1838) );
OAI21XLTS U2313 ( .A0(n2622), .A1(n2022), .B0(n1838), .Y(n987) );
AOI22X1TS U2314 ( .A0(add_subt_module_DmP[0]), .A1(n2142), .B0(
add_subt_module_intDX[0]), .B1(n1866), .Y(n1839) );
OAI21XLTS U2315 ( .A0(n2613), .A1(n2022), .B0(n1839), .Y(n975) );
INVX4TS U2316 ( .A(n2022), .Y(n1859) );
AOI22X1TS U2317 ( .A0(add_subt_module_DmP[3]), .A1(n2033), .B0(
add_subt_module_intDY[3]), .B1(n1859), .Y(n1841) );
OAI21XLTS U2318 ( .A0(n2600), .A1(n1840), .B0(n1841), .Y(n966) );
AOI22X1TS U2319 ( .A0(add_subt_module_DmP[8]), .A1(n2142), .B0(
add_subt_module_intDY[8]), .B1(n1859), .Y(n1842) );
OAI21XLTS U2320 ( .A0(n2611), .A1(n1840), .B0(n1842), .Y(n946) );
AOI22X1TS U2321 ( .A0(add_subt_module_DmP[20]), .A1(n1835), .B0(
add_subt_module_intDY[20]), .B1(n1859), .Y(n1843) );
OAI21XLTS U2322 ( .A0(n2608), .A1(n1840), .B0(n1843), .Y(n940) );
INVX4TS U2323 ( .A(n2022), .Y(n1969) );
AOI22X1TS U2324 ( .A0(n2142), .A1(add_subt_module_DmP[18]), .B0(
add_subt_module_intDY[18]), .B1(n1969), .Y(n1844) );
OAI21XLTS U2325 ( .A0(n2607), .A1(n1840), .B0(n1844), .Y(n953) );
AOI22X1TS U2326 ( .A0(n2142), .A1(add_subt_module_DmP[11]), .B0(
add_subt_module_intDY[11]), .B1(n1859), .Y(n1845) );
OAI21XLTS U2327 ( .A0(n2618), .A1(n1840), .B0(n1845), .Y(n908) );
AOI22X1TS U2328 ( .A0(n1969), .A1(add_subt_module_intDX[12]), .B0(
add_subt_module_DMP[12]), .B1(n2033), .Y(n1846) );
OAI21XLTS U2329 ( .A0(n2617), .A1(n1840), .B0(n1846), .Y(n904) );
AOI22X1TS U2330 ( .A0(add_subt_module_DmP[17]), .A1(n1835), .B0(
add_subt_module_intDY[17]), .B1(n1859), .Y(n1847) );
OAI21XLTS U2331 ( .A0(n2609), .A1(n1840), .B0(n1847), .Y(n929) );
AOI22X1TS U2332 ( .A0(add_subt_module_DmP[1]), .A1(n1835), .B0(
add_subt_module_intDY[1]), .B1(n1859), .Y(n1848) );
OAI21XLTS U2333 ( .A0(n2579), .A1(n1840), .B0(n1848), .Y(n943) );
AOI22X1TS U2334 ( .A0(add_subt_module_DmP[15]), .A1(n1835), .B0(
add_subt_module_intDY[15]), .B1(n1859), .Y(n1849) );
OAI21XLTS U2335 ( .A0(n2572), .A1(n1840), .B0(n1849), .Y(n949) );
AOI22X1TS U2336 ( .A0(add_subt_module_DmP[13]), .A1(n2142), .B0(
add_subt_module_intDY[13]), .B1(n1859), .Y(n1850) );
OAI21XLTS U2337 ( .A0(n2601), .A1(n1840), .B0(n1850), .Y(n936) );
AOI22X1TS U2338 ( .A0(add_subt_module_DmP[21]), .A1(n2142), .B0(
add_subt_module_intDY[21]), .B1(n1859), .Y(n1851) );
OAI21XLTS U2339 ( .A0(n2573), .A1(n1840), .B0(n1851), .Y(n956) );
AOI22X1TS U2340 ( .A0(add_subt_module_DmP[14]), .A1(n1835), .B0(
add_subt_module_intDY[14]), .B1(n1859), .Y(n1852) );
OAI21XLTS U2341 ( .A0(n2616), .A1(n1840), .B0(n1852), .Y(n915) );
AOI22X1TS U2342 ( .A0(add_subt_module_DmP[4]), .A1(n2142), .B0(
add_subt_module_intDY[4]), .B1(n1859), .Y(n1853) );
OAI21XLTS U2343 ( .A0(n2619), .A1(n1840), .B0(n1853), .Y(n925) );
AOI22X1TS U2344 ( .A0(add_subt_module_DmP[16]), .A1(n2142), .B0(
add_subt_module_intDY[16]), .B1(n1859), .Y(n1854) );
OAI21XLTS U2345 ( .A0(n2626), .A1(n1840), .B0(n1854), .Y(n922) );
AOI22X1TS U2346 ( .A0(add_subt_module_DmP[10]), .A1(n2033), .B0(
add_subt_module_intDY[10]), .B1(n1859), .Y(n1855) );
OAI21XLTS U2347 ( .A0(n2610), .A1(n1840), .B0(n1855), .Y(n918) );
AOI22X1TS U2348 ( .A0(add_subt_module_DmP[2]), .A1(n2033), .B0(
add_subt_module_intDY[2]), .B1(n1859), .Y(n1856) );
OAI21XLTS U2349 ( .A0(n2620), .A1(n1840), .B0(n1856), .Y(n959) );
AOI22X1TS U2350 ( .A0(add_subt_module_DmP[9]), .A1(n2142), .B0(
add_subt_module_intDY[9]), .B1(n1969), .Y(n1857) );
OAI21XLTS U2351 ( .A0(n2578), .A1(n1840), .B0(n1857), .Y(n901) );
AOI22X1TS U2352 ( .A0(add_subt_module_DmP[5]), .A1(n2142), .B0(
add_subt_module_intDY[5]), .B1(n1859), .Y(n1858) );
OAI21XLTS U2353 ( .A0(n2577), .A1(n1840), .B0(n1858), .Y(n932) );
AOI22X1TS U2354 ( .A0(n1545), .A1(n2033), .B0(add_subt_module_intDY[7]),
.B1(n1859), .Y(n1860) );
OAI21XLTS U2355 ( .A0(n2576), .A1(n1840), .B0(n1860), .Y(n911) );
BUFX4TS U2356 ( .A(n2022), .Y(n2036) );
AOI22X1TS U2357 ( .A0(n1866), .A1(add_subt_module_intDY[21]), .B0(
add_subt_module_DMP[21]), .B1(n2033), .Y(n1861) );
OAI21XLTS U2358 ( .A0(n2573), .A1(n2036), .B0(n1861), .Y(n891) );
AOI22X1TS U2359 ( .A0(n1544), .A1(n1835), .B0(add_subt_module_intDX[12]),
.B1(n1866), .Y(n1862) );
OAI21XLTS U2360 ( .A0(n2617), .A1(n2036), .B0(n1862), .Y(n905) );
AOI22X1TS U2361 ( .A0(n1866), .A1(add_subt_module_intDY[5]), .B0(
add_subt_module_DMP[5]), .B1(n2033), .Y(n1863) );
OAI21XLTS U2362 ( .A0(n2577), .A1(n2036), .B0(n1863), .Y(n895) );
AOI22X1TS U2363 ( .A0(n1866), .A1(add_subt_module_intDY[11]), .B0(
add_subt_module_DMP[11]), .B1(n2033), .Y(n1864) );
OAI21XLTS U2364 ( .A0(n2618), .A1(n2036), .B0(n1864), .Y(n899) );
AOI22X1TS U2365 ( .A0(n1866), .A1(add_subt_module_intDY[7]), .B0(
add_subt_module_DMP[7]), .B1(n2033), .Y(n1865) );
OAI21XLTS U2366 ( .A0(n2576), .A1(n2036), .B0(n1865), .Y(n898) );
AOI22X1TS U2367 ( .A0(n1866), .A1(add_subt_module_intDY[3]), .B0(
add_subt_module_DMP[3]), .B1(n2033), .Y(n1867) );
OAI21XLTS U2368 ( .A0(n2600), .A1(n2036), .B0(n1867), .Y(n889) );
AOI22X1TS U2369 ( .A0(add_subt_module_Add_Subt_result[22]), .A1(n1980), .B0(
add_subt_module_DmP[1]), .B1(n2141), .Y(n1868) );
OAI21XLTS U2370 ( .A0(n2629), .A1(n1973), .B0(n1868), .Y(n1870) );
AOI22X1TS U2371 ( .A0(add_subt_module_Add_Subt_result[18]), .A1(n1980), .B0(
add_subt_module_DmP[5]), .B1(n2141), .Y(n1869) );
OAI21X1TS U2372 ( .A0(n2643), .A1(n1973), .B0(n1869), .Y(n1890) );
NOR2XLTS U2373 ( .A(n1872), .B(n1875), .Y(n1871) );
INVX2TS U2374 ( .A(n2264), .Y(n1955) );
INVX2TS U2375 ( .A(n1872), .Y(n2254) );
NOR2XLTS U2376 ( .A(n1875), .B(n2254), .Y(n1873) );
AOI22X1TS U2377 ( .A0(add_subt_module_Add_Subt_result[24]), .A1(n1980), .B0(
add_subt_module_Add_Subt_result[1]), .B1(n1922), .Y(n1874) );
AOI22X1TS U2378 ( .A0(n1903), .A1(n1874), .B0(n1886), .B1(n2266), .Y(n1907)
);
NAND2X2TS U2379 ( .A(n2254), .B(n1875), .Y(n2002) );
AOI22X1TS U2380 ( .A0(add_subt_module_Add_Subt_result[23]), .A1(n1980), .B0(
add_subt_module_DmP[0]), .B1(n2141), .Y(n1879) );
NAND2X1TS U2381 ( .A(add_subt_module_Add_Subt_result[2]), .B(n1922), .Y(
n1878) );
AOI22X1TS U2382 ( .A0(n2262), .A1(n1907), .B0(n1876), .B1(n1906), .Y(n1884)
);
AOI22X1TS U2383 ( .A0(add_subt_module_Add_Subt_result[25]), .A1(n1980), .B0(
add_subt_module_Add_Subt_result[0]), .B1(n1922), .Y(n1881) );
AOI22X1TS U2384 ( .A0(n1992), .A1(n1881), .B0(n1885), .B1(n2266), .Y(n1882)
);
NAND2X1TS U2385 ( .A(n1880), .B(n1882), .Y(n1883) );
OAI211XLTS U2386 ( .A0(n1550), .A1(n1955), .B0(n1884), .C0(n1883), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]) );
INVX2TS U2387 ( .A(n2262), .Y(n1997) );
AOI22X1TS U2388 ( .A0(n1876), .A1(n1551), .B0(n1880), .B1(n1906), .Y(n1888)
);
NAND2X1TS U2389 ( .A(n2264), .B(n1910), .Y(n1887) );
OAI211XLTS U2390 ( .A0(n1550), .A1(n1997), .B0(n1888), .C0(n1887), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AOI22X1TS U2391 ( .A0(add_subt_module_Add_Subt_result[14]), .A1(n1980), .B0(
add_subt_module_DmP[9]), .B1(n2141), .Y(n1889) );
OAI21X1TS U2392 ( .A0(n2642), .A1(n1973), .B0(n1889), .Y(n1901) );
AOI22X1TS U2393 ( .A0(n1876), .A1(n1945), .B0(n1880), .B1(n1911), .Y(n1895)
);
NAND2X1TS U2394 ( .A(n2264), .B(n1944), .Y(n1894) );
OAI211XLTS U2395 ( .A0(n1949), .A1(n1997), .B0(n1895), .C0(n1894), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]) );
AOI22X1TS U2396 ( .A0(n2262), .A1(n1911), .B0(n1880), .B1(n1910), .Y(n1897)
);
NAND2X1TS U2397 ( .A(n2264), .B(n1945), .Y(n1896) );
OAI211XLTS U2398 ( .A0(n1949), .A1(n2002), .B0(n1897), .C0(n1896), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]) );
AOI22X1TS U2399 ( .A0(n2262), .A1(n1551), .B0(n1876), .B1(n1910), .Y(n1899)
);
NAND2X1TS U2400 ( .A(n2264), .B(n1911), .Y(n1898) );
AOI22X1TS U2401 ( .A0(add_subt_module_Add_Subt_result[10]), .A1(n1980), .B0(
add_subt_module_DmP[13]), .B1(n2141), .Y(n1900) );
OAI21X1TS U2402 ( .A0(n2583), .A1(n1973), .B0(n1900), .Y(n1915) );
AOI22X1TS U2403 ( .A0(n2262), .A1(n1944), .B0(n1880), .B1(n1945), .Y(n1905)
);
NAND2X1TS U2404 ( .A(n1876), .B(n1946), .Y(n1904) );
OAI211XLTS U2405 ( .A0(n1940), .A1(n1955), .B0(n1905), .C0(n1904), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI22X1TS U2406 ( .A0(n2262), .A1(n1906), .B0(n2264), .B1(n1551), .Y(n1909)
);
NAND2X1TS U2407 ( .A(n1880), .B(n1907), .Y(n1908) );
OAI211XLTS U2408 ( .A0(n1550), .A1(n2002), .B0(n1909), .C0(n1908), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]) );
AOI22X1TS U2409 ( .A0(n2262), .A1(n1910), .B0(n1880), .B1(n1551), .Y(n1913)
);
NAND2X1TS U2410 ( .A(n1876), .B(n1911), .Y(n1912) );
OAI211XLTS U2411 ( .A0(n1949), .A1(n1955), .B0(n1913), .C0(n1912), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]) );
AOI22X1TS U2412 ( .A0(add_subt_module_Add_Subt_result[6]), .A1(n1980), .B0(
add_subt_module_DmP[17]), .B1(n2141), .Y(n1914) );
OAI21X1TS U2413 ( .A0(n2644), .A1(n1973), .B0(n1914), .Y(n1921) );
AOI22X1TS U2414 ( .A0(n1876), .A1(n1941), .B0(n1880), .B1(n1952), .Y(n1919)
);
INVX2TS U2415 ( .A(n1992), .Y(n1976) );
NAND2X1TS U2416 ( .A(n2264), .B(n1998), .Y(n1918) );
OAI211XLTS U2417 ( .A0(n1956), .A1(n1997), .B0(n1919), .C0(n1918), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]) );
AOI22X1TS U2418 ( .A0(add_subt_module_Add_Subt_result[23]), .A1(n1922), .B0(
add_subt_module_DmP[21]), .B1(n2141), .Y(n1920) );
AOI22X1TS U2419 ( .A0(n2262), .A1(n1998), .B0(n1880), .B1(n1941), .Y(n1927)
);
AOI22X1TS U2420 ( .A0(add_subt_module_Add_Subt_result[22]), .A1(n1922), .B0(
add_subt_module_DmP[20]), .B1(n2141), .Y(n1923) );
OAI21X2TS U2421 ( .A0(n2629), .A1(n1924), .B0(n1923), .Y(n2263) );
AOI2BB2X2TS U2422 ( .B0(n1903), .B1(n1925), .A0N(n2263), .A1N(n1992), .Y(
n1999) );
NAND2X1TS U2423 ( .A(n1876), .B(n1999), .Y(n1926) );
OAI211XLTS U2424 ( .A0(n2003), .A1(n1955), .B0(n1927), .C0(n1926), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]) );
AOI22X1TS U2425 ( .A0(n1876), .A1(n1950), .B0(n1880), .B1(n1946), .Y(n1933)
);
NAND2X1TS U2426 ( .A(n2264), .B(n1951), .Y(n1932) );
OAI211XLTS U2427 ( .A0(n1940), .A1(n1997), .B0(n1933), .C0(n1932), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]) );
AOI22X1TS U2428 ( .A0(n2262), .A1(n1946), .B0(n1880), .B1(n1944), .Y(n1935)
);
NAND2X1TS U2429 ( .A(n2264), .B(n1950), .Y(n1934) );
OAI211XLTS U2430 ( .A0(n1940), .A1(n2002), .B0(n1935), .C0(n1934), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI22X1TS U2431 ( .A0(n2262), .A1(n1952), .B0(n1880), .B1(n1951), .Y(n1937)
);
NAND2X1TS U2432 ( .A(n2264), .B(n1941), .Y(n1936) );
OAI211XLTS U2433 ( .A0(n1956), .A1(n2002), .B0(n1937), .C0(n1936), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]) );
AOI22X1TS U2434 ( .A0(n2262), .A1(n1950), .B0(n1876), .B1(n1951), .Y(n1939)
);
NAND2X1TS U2435 ( .A(n2264), .B(n1952), .Y(n1938) );
OAI211XLTS U2436 ( .A0(n1831), .A1(n1940), .B0(n1939), .C0(n1938), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]) );
AOI22X1TS U2437 ( .A0(n2262), .A1(n1941), .B0(n1876), .B1(n1998), .Y(n1943)
);
NAND2X1TS U2438 ( .A(n2264), .B(n1999), .Y(n1942) );
OAI211XLTS U2439 ( .A0(n1831), .A1(n1956), .B0(n1943), .C0(n1942), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]) );
AOI22X1TS U2440 ( .A0(n2262), .A1(n1945), .B0(n1876), .B1(n1944), .Y(n1948)
);
NAND2X1TS U2441 ( .A(n2264), .B(n1946), .Y(n1947) );
OAI211XLTS U2442 ( .A0(n1831), .A1(n1949), .B0(n1948), .C0(n1947), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]) );
AOI22X1TS U2443 ( .A0(n2262), .A1(n1951), .B0(n1880), .B1(n1950), .Y(n1954)
);
NAND2X1TS U2444 ( .A(n1876), .B(n1952), .Y(n1953) );
OAI211XLTS U2445 ( .A0(n1956), .A1(n1955), .B0(n1954), .C0(n1953), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]) );
BUFX3TS U2446 ( .A(n1840), .Y(n1971) );
AOI22X1TS U2447 ( .A0(n1969), .A1(add_subt_module_intDX[0]), .B0(
add_subt_module_DMP[0]), .B1(n2029), .Y(n1957) );
OAI21XLTS U2448 ( .A0(n2613), .A1(n1971), .B0(n1957), .Y(n886) );
AOI22X1TS U2449 ( .A0(add_subt_module_DmP[22]), .A1(n2142), .B0(
add_subt_module_intDY[22]), .B1(n1969), .Y(n1958) );
OAI21XLTS U2450 ( .A0(n2612), .A1(n1971), .B0(n1958), .Y(n972) );
AOI22X1TS U2451 ( .A0(n1969), .A1(add_subt_module_intDX[26]), .B0(
add_subt_module_DMP[26]), .B1(n2029), .Y(n1959) );
OAI21XLTS U2452 ( .A0(n2622), .A1(n1971), .B0(n1959), .Y(n986) );
AOI22X1TS U2453 ( .A0(n1969), .A1(add_subt_module_intDX[25]), .B0(
add_subt_module_DMP[25]), .B1(n2029), .Y(n1960) );
OAI21XLTS U2454 ( .A0(n2623), .A1(n1971), .B0(n1960), .Y(n983) );
AOI22X1TS U2455 ( .A0(n2142), .A1(add_subt_module_DmP[19]), .B0(
add_subt_module_intDY[19]), .B1(n1969), .Y(n1961) );
OAI21XLTS U2456 ( .A0(n2615), .A1(n1971), .B0(n1961), .Y(n963) );
AOI22X1TS U2457 ( .A0(n1969), .A1(add_subt_module_intDX[30]), .B0(
add_subt_module_DMP[30]), .B1(n2029), .Y(n1962) );
OAI21XLTS U2458 ( .A0(n2627), .A1(n1971), .B0(n1962), .Y(n998) );
AOI22X1TS U2459 ( .A0(n1969), .A1(add_subt_module_intDX[23]), .B0(
add_subt_module_DMP[23]), .B1(n2142), .Y(n1963) );
OAI21XLTS U2460 ( .A0(n2636), .A1(n1971), .B0(n1963), .Y(n977) );
AOI22X1TS U2461 ( .A0(n1969), .A1(add_subt_module_intDX[28]), .B0(
add_subt_module_DMP[28]), .B1(n2029), .Y(n1964) );
OAI21XLTS U2462 ( .A0(n2606), .A1(n1971), .B0(n1964), .Y(n992) );
AOI22X1TS U2463 ( .A0(n1969), .A1(add_subt_module_intDX[27]), .B0(
add_subt_module_DMP[27]), .B1(n2029), .Y(n1965) );
OAI21XLTS U2464 ( .A0(n2549), .A1(n1971), .B0(n1965), .Y(n989) );
AOI22X1TS U2465 ( .A0(n1969), .A1(add_subt_module_intDY[23]), .B0(
add_subt_module_DmP[23]), .B1(n2029), .Y(n1966) );
OAI21XLTS U2466 ( .A0(n2628), .A1(n1971), .B0(n1966), .Y(n978) );
AOI22X1TS U2467 ( .A0(n1969), .A1(add_subt_module_intDX[24]), .B0(
add_subt_module_DMP[24]), .B1(n2029), .Y(n1967) );
OAI21XLTS U2468 ( .A0(n2614), .A1(n1971), .B0(n1967), .Y(n980) );
AOI22X1TS U2469 ( .A0(add_subt_module_DmP[6]), .A1(n2142), .B0(
add_subt_module_intDY[6]), .B1(n1969), .Y(n1968) );
OAI21XLTS U2470 ( .A0(n2621), .A1(n1971), .B0(n1968), .Y(n969) );
AOI22X1TS U2471 ( .A0(n1969), .A1(add_subt_module_intDX[29]), .B0(
add_subt_module_DMP[29]), .B1(n2029), .Y(n1970) );
OAI21XLTS U2472 ( .A0(n2580), .A1(n1971), .B0(n1970), .Y(n995) );
AOI22X1TS U2473 ( .A0(add_subt_module_Add_Subt_result[1]), .A1(n1980), .B0(
add_subt_module_DmP[22]), .B1(n2141), .Y(n1972) );
OAI21X2TS U2474 ( .A0(n2638), .A1(n1973), .B0(n1972), .Y(n2260) );
AOI22X1TS U2475 ( .A0(n1880), .A1(n2005), .B0(n2006), .B1(n1831), .Y(n1975)
);
OAI21XLTS U2476 ( .A0(n1977), .A1(n1976), .B0(n1975), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]) );
AOI22X2TS U2477 ( .A0(add_subt_module_LZA_output[4]), .A1(n2205), .B0(n2204),
.B1(add_subt_module_exp_oper_result[4]), .Y(n2082) );
INVX2TS U2478 ( .A(n2082), .Y(n2037) );
NOR2XLTS U2479 ( .A(n2083), .B(n2037), .Y(n1978) );
BUFX4TS U2480 ( .A(n1978), .Y(n2097) );
AOI21X1TS U2481 ( .A0(n2097), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(
n1547), .Y(n2074) );
AOI21X2TS U2482 ( .A0(n2287), .A1(n2143), .B0(n2228), .Y(n2170) );
INVX2TS U2483 ( .A(n2170), .Y(n2133) );
NAND2X1TS U2484 ( .A(n2083), .B(n2082), .Y(n2056) );
AOI22X1TS U2485 ( .A0(n2080), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(
n2097), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .Y(
n1981) );
NAND2X1TS U2486 ( .A(n1981), .B(n2041), .Y(n2071) );
AOI22X1TS U2487 ( .A0(n2054), .A1(n2071), .B0(
add_subt_module_Sgf_normalized_result[14]), .B1(n2129), .Y(n1984) );
INVX2TS U2488 ( .A(n1979), .Y(n2076) );
NAND2X1TS U2489 ( .A(n2076), .B(n2080), .Y(n2169) );
NAND2X1TS U2490 ( .A(n1982), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(
n1983) );
OAI211XLTS U2491 ( .A0(n2074), .A1(n1979), .B0(n1984), .C0(n1983), .Y(n1316)
);
AOI21X1TS U2492 ( .A0(n2097), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(
n1547), .Y(n2070) );
AOI22X1TS U2493 ( .A0(n2080), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]), .B0(
n2097), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(
n1985) );
NAND2X1TS U2494 ( .A(n1985), .B(n2041), .Y(n2067) );
AOI22X1TS U2495 ( .A0(n2054), .A1(n2067), .B0(
add_subt_module_Sgf_normalized_result[13]), .B1(n2129), .Y(n1987) );
NAND2X1TS U2496 ( .A(n1982), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(
n1986) );
OAI211XLTS U2497 ( .A0(n2070), .A1(n1979), .B0(n1987), .C0(n1986), .Y(n1315)
);
AOI21X1TS U2498 ( .A0(n2097), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(
n1547), .Y(n2079) );
AOI22X1TS U2499 ( .A0(n2080), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(
n2097), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]), .Y(
n1988) );
NAND2X1TS U2500 ( .A(n1988), .B(n2041), .Y(n2075) );
AOI22X1TS U2501 ( .A0(n2054), .A1(n2075), .B0(
add_subt_module_Sgf_normalized_result[15]), .B1(n2129), .Y(n1990) );
NAND2X1TS U2502 ( .A(n1982), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(
n1989) );
AOI2BB2X2TS U2503 ( .B0(n1903), .B1(n1991), .A0N(n2260), .A1N(n1992), .Y(
n2004) );
AOI22X1TS U2504 ( .A0(n2262), .A1(n2004), .B0(n1876), .B1(n2005), .Y(n1994)
);
OAI211XLTS U2505 ( .A0(n1831), .A1(n2003), .B0(n1994), .C0(n1993), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]) );
AOI22X1TS U2506 ( .A0(n1876), .A1(n2004), .B0(n1880), .B1(n1999), .Y(n1996)
);
NAND2X1TS U2507 ( .A(n2264), .B(n2005), .Y(n1995) );
OAI211XLTS U2508 ( .A0(n2003), .A1(n1997), .B0(n1996), .C0(n1995), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]) );
AOI22X1TS U2509 ( .A0(n2262), .A1(n1999), .B0(n1880), .B1(n1998), .Y(n2001)
);
NAND2X1TS U2510 ( .A(n2264), .B(n2004), .Y(n2000) );
OAI211XLTS U2511 ( .A0(n2003), .A1(n2002), .B0(n2001), .C0(n2000), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]) );
AOI22X1TS U2512 ( .A0(n1876), .A1(n2263), .B0(n2264), .B1(n2261), .Y(n2009)
);
AOI22X1TS U2513 ( .A0(n2262), .A1(n2005), .B0(n1880), .B1(n2004), .Y(n2008)
);
NAND2X1TS U2514 ( .A(n2006), .B(n2254), .Y(n2007) );
OAI211XLTS U2515 ( .A0(n2009), .A1(n2266), .B0(n2008), .C0(n2007), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]) );
AOI22X1TS U2516 ( .A0(n2034), .A1(add_subt_module_intDY[18]), .B0(
add_subt_module_DMP[18]), .B1(n2029), .Y(n2011) );
OAI21XLTS U2517 ( .A0(n2607), .A1(n2022), .B0(n2011), .Y(n952) );
AOI22X1TS U2518 ( .A0(n2034), .A1(add_subt_module_intDY[19]), .B0(
add_subt_module_DMP[19]), .B1(n2033), .Y(n2012) );
AOI22X1TS U2519 ( .A0(n2034), .A1(add_subt_module_intDY[17]), .B0(
add_subt_module_DMP[17]), .B1(n2033), .Y(n2013) );
OAI21XLTS U2520 ( .A0(n2609), .A1(n2022), .B0(n2013), .Y(n928) );
AOI22X1TS U2521 ( .A0(n2034), .A1(add_subt_module_intDY[1]), .B0(
add_subt_module_DMP[1]), .B1(n2033), .Y(n2014) );
OAI21XLTS U2522 ( .A0(n2579), .A1(n2036), .B0(n2014), .Y(n894) );
AOI22X1TS U2523 ( .A0(n2034), .A1(add_subt_module_intDY[14]), .B0(
add_subt_module_DMP[14]), .B1(n2029), .Y(n2015) );
AOI22X1TS U2524 ( .A0(n2034), .A1(add_subt_module_intDY[15]), .B0(
add_subt_module_DMP[15]), .B1(n2033), .Y(n2016) );
OAI21XLTS U2525 ( .A0(n2572), .A1(n2036), .B0(n2016), .Y(n892) );
AOI22X1TS U2526 ( .A0(n2034), .A1(add_subt_module_intDY[20]), .B0(
add_subt_module_DMP[20]), .B1(n2033), .Y(n2017) );
OAI21XLTS U2527 ( .A0(n2608), .A1(n2036), .B0(n2017), .Y(n939) );
AOI22X1TS U2528 ( .A0(n2034), .A1(add_subt_module_intDY[22]), .B0(
add_subt_module_DMP[22]), .B1(n2029), .Y(n2018) );
OAI21XLTS U2529 ( .A0(n2612), .A1(n2036), .B0(n2018), .Y(n887) );
AOI22X1TS U2530 ( .A0(n2034), .A1(add_subt_module_intDY[8]), .B0(
add_subt_module_DMP[8]), .B1(n2033), .Y(n2019) );
OAI21XLTS U2531 ( .A0(n2611), .A1(n2036), .B0(n2019), .Y(n893) );
AOI22X1TS U2532 ( .A0(n2034), .A1(add_subt_module_intDY[13]), .B0(
add_subt_module_DMP[13]), .B1(n2033), .Y(n2020) );
AOI22X1TS U2533 ( .A0(n2034), .A1(add_subt_module_intDY[16]), .B0(
add_subt_module_DMP[16]), .B1(n2033), .Y(n2021) );
OAI21XLTS U2534 ( .A0(n2626), .A1(n2022), .B0(n2021), .Y(n921) );
AOI22X1TS U2535 ( .A0(n2034), .A1(add_subt_module_intDX[27]), .B0(
add_subt_module_DmP[27]), .B1(n2029), .Y(n2023) );
OAI21XLTS U2536 ( .A0(n2549), .A1(n2022), .B0(n2023), .Y(n990) );
AOI22X1TS U2537 ( .A0(n2034), .A1(add_subt_module_intDX[24]), .B0(
add_subt_module_DmP[24]), .B1(n2029), .Y(n2024) );
OAI21XLTS U2538 ( .A0(n2614), .A1(n2022), .B0(n2024), .Y(n981) );
AOI22X1TS U2539 ( .A0(n2034), .A1(add_subt_module_intDX[30]), .B0(
add_subt_module_DmP[30]), .B1(n2033), .Y(n2025) );
AOI22X1TS U2540 ( .A0(n2034), .A1(add_subt_module_intDY[2]), .B0(
add_subt_module_DMP[2]), .B1(n2033), .Y(n2026) );
OAI21XLTS U2541 ( .A0(n2620), .A1(n2036), .B0(n2026), .Y(n890) );
AOI22X1TS U2542 ( .A0(n2034), .A1(add_subt_module_intDX[25]), .B0(
add_subt_module_DmP[25]), .B1(n2029), .Y(n2027) );
AOI22X1TS U2543 ( .A0(n2034), .A1(add_subt_module_intDY[9]), .B0(
add_subt_module_DMP[9]), .B1(n2033), .Y(n2028) );
OAI21XLTS U2544 ( .A0(n2578), .A1(n2036), .B0(n2028), .Y(n900) );
AOI22X1TS U2545 ( .A0(n2034), .A1(add_subt_module_intDX[29]), .B0(
add_subt_module_DmP[29]), .B1(n2029), .Y(n2030) );
OAI21XLTS U2546 ( .A0(n2580), .A1(n2022), .B0(n2030), .Y(n996) );
AOI22X1TS U2547 ( .A0(n2034), .A1(add_subt_module_intDY[6]), .B0(
add_subt_module_DMP[6]), .B1(n2033), .Y(n2031) );
OAI21XLTS U2548 ( .A0(n2621), .A1(n2036), .B0(n2031), .Y(n888) );
AOI22X1TS U2549 ( .A0(n2034), .A1(add_subt_module_intDY[10]), .B0(
add_subt_module_DMP[10]), .B1(n2033), .Y(n2032) );
OAI21XLTS U2550 ( .A0(n2610), .A1(n2036), .B0(n2032), .Y(n897) );
AOI22X1TS U2551 ( .A0(n2034), .A1(add_subt_module_intDY[4]), .B0(
add_subt_module_DMP[4]), .B1(n2033), .Y(n2035) );
OAI21XLTS U2552 ( .A0(n2619), .A1(n2036), .B0(n2035), .Y(n896) );
AOI21X1TS U2553 ( .A0(n2097), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]), .B0(
n1547), .Y(n2066) );
AOI22X1TS U2554 ( .A0(n1982), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .B0(
add_subt_module_Sgf_normalized_result[8]), .B1(n2129), .Y(n2040) );
NAND2X1TS U2555 ( .A(n2083), .B(n2037), .Y(n2051) );
AOI22X1TS U2556 ( .A0(n2080), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(
n2097), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(
n2038) );
OR2X1TS U2557 ( .A(n2083), .B(n2041), .Y(n2116) );
OAI211X1TS U2558 ( .A0(n2652), .A1(n2051), .B0(n2038), .C0(n2116), .Y(n2063)
);
NAND2X1TS U2559 ( .A(n2054), .B(n2063), .Y(n2039) );
OAI211XLTS U2560 ( .A0(n2066), .A1(n1979), .B0(n2040), .C0(n2039), .Y(n1310)
);
AOI21X1TS U2561 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]), .A1(
n2097), .B0(n1547), .Y(n2062) );
AOI22X1TS U2562 ( .A0(n1982), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .B0(
add_subt_module_Sgf_normalized_result[9]), .B1(n2129), .Y(n2044) );
AOI22X1TS U2563 ( .A0(n2080), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(
n2097), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(
n2042) );
OAI211X1TS U2564 ( .A0(n2051), .A1(n2653), .B0(n2042), .C0(n2116), .Y(n2059)
);
NAND2X1TS U2565 ( .A(n2054), .B(n2059), .Y(n2043) );
OAI211XLTS U2566 ( .A0(n2062), .A1(n1979), .B0(n2044), .C0(n2043), .Y(n1311)
);
NAND2X1TS U2567 ( .A(cordic_FSM_state_reg[1]), .B(n2588), .Y(n2048) );
NOR2XLTS U2568 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[3]),
.Y(n2045) );
AOI31XLTS U2569 ( .A0(cordic_FSM_state_reg[0]), .A1(beg_fsm_cordic), .A2(
n2045), .B0(n2439), .Y(n2047) );
OAI211XLTS U2570 ( .A0(n2447), .A1(n2048), .B0(n2047), .C0(n2046), .Y(
cordic_FSM_state_next_1_) );
OAI32X1TS U2571 ( .A0(n2448), .A1(cordic_FSM_state_reg[1]), .A2(n2281), .B0(
n2586), .B1(n2448), .Y(n2050) );
OAI211XLTS U2572 ( .A0(n2050), .A1(n2551), .B0(n2278), .C0(n2049), .Y(n1521)
);
INVX2TS U2573 ( .A(n2051), .Y(n2098) );
AOI22X1TS U2574 ( .A0(n2080), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]), .B0(
n2098), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(
n2052) );
OAI31X1TS U2575 ( .A0(n2083), .A1(n2082), .A2(n2653), .B0(n2052), .Y(n2053)
);
AOI21X1TS U2576 ( .A0(n2097), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(
n2053), .Y(n2168) );
NOR2XLTS U2577 ( .A(n2056), .B(n2055), .Y(n2057) );
AOI22X1TS U2578 ( .A0(n2134), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(
add_subt_module_Sgf_normalized_result[24]), .B1(n2133), .Y(n2058) );
INVX2TS U2579 ( .A(n2099), .Y(n2085) );
OAI211XLTS U2580 ( .A0(n2168), .A1(n1979), .B0(n2058), .C0(n2085), .Y(n1326)
);
AOI22X1TS U2581 ( .A0(n2134), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .B0(
add_subt_module_Sgf_normalized_result[16]), .B1(n2133), .Y(n2061) );
NAND2X1TS U2582 ( .A(n2076), .B(n2059), .Y(n2060) );
OAI211XLTS U2583 ( .A0(n2062), .A1(n2055), .B0(n2061), .C0(n2060), .Y(n1318)
);
AOI22X1TS U2584 ( .A0(n2134), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .B0(
add_subt_module_Sgf_normalized_result[17]), .B1(n2133), .Y(n2065) );
NAND2X1TS U2585 ( .A(n2076), .B(n2063), .Y(n2064) );
OAI211XLTS U2586 ( .A0(n2066), .A1(n2055), .B0(n2065), .C0(n2064), .Y(n1319)
);
AOI22X1TS U2587 ( .A0(n2076), .A1(n2067), .B0(
add_subt_module_Sgf_normalized_result[12]), .B1(n2129), .Y(n2069) );
NAND2X1TS U2588 ( .A(n2134), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(
n2068) );
OAI211XLTS U2589 ( .A0(n2070), .A1(n2055), .B0(n2069), .C0(n2068), .Y(n1314)
);
AOI22X1TS U2590 ( .A0(n2076), .A1(n2071), .B0(
add_subt_module_Sgf_normalized_result[11]), .B1(n2129), .Y(n2073) );
NAND2X1TS U2591 ( .A(n2134), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(
n2072) );
OAI211XLTS U2592 ( .A0(n2074), .A1(n2055), .B0(n2073), .C0(n2072), .Y(n1313)
);
AOI22X1TS U2593 ( .A0(n2076), .A1(n2075), .B0(
add_subt_module_Sgf_normalized_result[10]), .B1(n2129), .Y(n2078) );
NAND2X1TS U2594 ( .A(n2134), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(
n2077) );
OAI211XLTS U2595 ( .A0(n2079), .A1(n2055), .B0(n2078), .C0(n2077), .Y(n1312)
);
AOI22X1TS U2596 ( .A0(n2080), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]), .B0(
n2098), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(
n2081) );
OAI31X1TS U2597 ( .A0(n2083), .A1(n2082), .A2(n2652), .B0(n2081), .Y(n2084)
);
AOI21X1TS U2598 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]), .A1(
n2097), .B0(n2084), .Y(n2167) );
AOI22X1TS U2599 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]), .A1(
n2134), .B0(add_subt_module_Sgf_normalized_result[25]), .B1(n2129),
.Y(n2086) );
OAI211XLTS U2600 ( .A0(n2167), .A1(n1979), .B0(n2086), .C0(n2085), .Y(n1518)
);
AOI22X1TS U2601 ( .A0(n2098), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(
n2097), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(
n2119) );
AOI22X1TS U2602 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n2134), .B0(add_subt_module_Sgf_normalized_result[19]), .B1(n2133),
.Y(n2088) );
AOI21X1TS U2603 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]), .A1(
n1982), .B0(n2099), .Y(n2087) );
OAI211XLTS U2604 ( .A0(n2119), .A1(n1979), .B0(n2088), .C0(n2087), .Y(n1321)
);
AOI22X1TS U2605 ( .A0(n2098), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(
n2097), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(
n2128) );
AOI22X1TS U2606 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1(
n2134), .B0(add_subt_module_Sgf_normalized_result[21]), .B1(n2129),
.Y(n2090) );
AOI21X1TS U2607 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]), .A1(
n1982), .B0(n2099), .Y(n2089) );
OAI211XLTS U2608 ( .A0(n2128), .A1(n1979), .B0(n2090), .C0(n2089), .Y(n1323)
);
AOI22X1TS U2609 ( .A0(n2098), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(
n2097), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(
n2125) );
AOI22X1TS U2610 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .A1(
n2134), .B0(add_subt_module_Sgf_normalized_result[22]), .B1(n2129),
.Y(n2092) );
AOI21X1TS U2611 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]), .A1(
n1982), .B0(n2099), .Y(n2091) );
OAI211XLTS U2612 ( .A0(n2125), .A1(n1979), .B0(n2092), .C0(n2091), .Y(n1324)
);
AOI22X1TS U2613 ( .A0(n2098), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(
n2097), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(
n2138) );
AOI22X1TS U2614 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]), .A1(
n2134), .B0(add_subt_module_Sgf_normalized_result[23]), .B1(n2129),
.Y(n2094) );
AOI21X1TS U2615 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]), .A1(
n1982), .B0(n2099), .Y(n2093) );
OAI211XLTS U2616 ( .A0(n2138), .A1(n1979), .B0(n2094), .C0(n2093), .Y(n1325)
);
AOI22X1TS U2617 ( .A0(n2098), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(
n2097), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(
n2122) );
AOI22X1TS U2618 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n2134), .B0(add_subt_module_Sgf_normalized_result[20]), .B1(n2133),
.Y(n2096) );
AOI21X1TS U2619 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]), .A1(
n1982), .B0(n2099), .Y(n2095) );
OAI211XLTS U2620 ( .A0(n2122), .A1(n1979), .B0(n2096), .C0(n2095), .Y(n1322)
);
AOI22X1TS U2621 ( .A0(n2098), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(
n2097), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(
n2132) );
AOI22X1TS U2622 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]), .A1(
n1982), .B0(add_subt_module_Sgf_normalized_result[18]), .B1(n2133),
.Y(n2101) );
AOI21X1TS U2623 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n2134), .B0(n2099), .Y(n2100) );
INVX2TS U2624 ( .A(n2104), .Y(n2369) );
NAND4XLTS U2625 ( .A(n2105), .B(n2147), .C(n2286), .D(n1552), .Y(n2109) );
AOI21X1TS U2626 ( .A0(add_subt_module_FS_Module_state_reg[2]), .A1(
add_subt_module_FSM_selector_C), .B0(n2227), .Y(n2106) );
NOR4X1TS U2627 ( .A(n2170), .B(n2107), .C(n2106), .D(n2598), .Y(n2108) );
XOR2X1TS U2628 ( .A(DP_OP_92J114_122_1254_n1), .B(n2110), .Y(n2251) );
INVX2TS U2629 ( .A(n2115), .Y(n2111) );
OR4X2TS U2630 ( .A(add_subt_module_Exp_Operation_Module_Data_S[2]), .B(
add_subt_module_Exp_Operation_Module_Data_S[0]), .C(
add_subt_module_Exp_Operation_Module_Data_S[1]), .D(n2111), .Y(n2112)
);
OR4X2TS U2631 ( .A(add_subt_module_Exp_Operation_Module_Data_S[5]), .B(
add_subt_module_Exp_Operation_Module_Data_S[4]), .C(
add_subt_module_Exp_Operation_Module_Data_S[3]), .D(n2112), .Y(n2113)
);
OR4X2TS U2632 ( .A(n2251), .B(add_subt_module_Exp_Operation_Module_Data_S[7]), .C(add_subt_module_Exp_Operation_Module_Data_S[6]), .D(n2113), .Y(n2114) );
OAI21XLTS U2633 ( .A0(n2115), .A1(n2656), .B0(n2114), .Y(n1515) );
AOI22X1TS U2634 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]), .A1(
n2134), .B0(add_subt_module_Sgf_normalized_result[6]), .B1(n2129), .Y(
n2118) );
AOI21X1TS U2635 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n1982), .B0(n2135), .Y(n2117) );
OAI211XLTS U2636 ( .A0(n2119), .A1(n2055), .B0(n2118), .C0(n2117), .Y(n1308)
);
AOI22X1TS U2637 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]), .A1(
n2134), .B0(add_subt_module_Sgf_normalized_result[5]), .B1(n2129), .Y(
n2121) );
AOI21X1TS U2638 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n1982), .B0(n2135), .Y(n2120) );
OAI211XLTS U2639 ( .A0(n2122), .A1(n2055), .B0(n2121), .C0(n2120), .Y(n1307)
);
AOI22X1TS U2640 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]), .A1(
n2134), .B0(add_subt_module_Sgf_normalized_result[3]), .B1(n2129), .Y(
n2124) );
AOI21X1TS U2641 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .A1(
n1982), .B0(n2135), .Y(n2123) );
OAI211XLTS U2642 ( .A0(n2125), .A1(n2055), .B0(n2124), .C0(n2123), .Y(n1305)
);
AOI22X1TS U2643 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]), .A1(
n2134), .B0(add_subt_module_Sgf_normalized_result[4]), .B1(n2129), .Y(
n2127) );
AOI21X1TS U2644 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1(
n1982), .B0(n2135), .Y(n2126) );
OAI211XLTS U2645 ( .A0(n2128), .A1(n2055), .B0(n2127), .C0(n2126), .Y(n1306)
);
AOI22X1TS U2646 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]), .A1(
n2134), .B0(add_subt_module_Sgf_normalized_result[7]), .B1(n2129), .Y(
n2131) );
AOI21X1TS U2647 ( .A0(n1982), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(
n2135), .Y(n2130) );
AOI22X1TS U2648 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]), .A1(
n2134), .B0(add_subt_module_Sgf_normalized_result[2]), .B1(n2133), .Y(
n2137) );
AOI21X1TS U2649 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]), .A1(
n1982), .B0(n2135), .Y(n2136) );
OAI211XLTS U2650 ( .A0(n2138), .A1(n2055), .B0(n2137), .C0(n2136), .Y(n1304)
);
AOI22X1TS U2651 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n2550), .B1(n2554),
.Y(n2139) );
OAI211XLTS U2652 ( .A0(n2286), .A1(n2148), .B0(n2291), .C0(n2146), .Y(n1509)
);
OAI21XLTS U2653 ( .A0(n2286), .A1(n2148), .B0(n2553), .Y(n1368) );
AO22XLTS U2654 ( .A0(n2288), .A1(n1546), .B0(n2149), .B1(n2148), .Y(n2150)
);
OR4X2TS U2655 ( .A(n2249), .B(n2104), .C(n2151), .D(n2150), .Y(n2152) );
OAI32X1TS U2656 ( .A0(n2289), .A1(n2152), .A2(n2225), .B0(
add_subt_module_FS_Module_state_reg[3]), .B1(n2152), .Y(n2153) );
INVX2TS U2657 ( .A(n2153), .Y(n1511) );
NOR2X1TS U2658 ( .A(add_subt_module_Add_Subt_result[20]), .B(
add_subt_module_Add_Subt_result[21]), .Y(n2215) );
NAND2X1TS U2659 ( .A(n2215), .B(n2217), .Y(n2239) );
NAND2BXLTS U2660 ( .AN(add_subt_module_Add_Subt_result[18]), .B(n2354), .Y(
n2236) );
NAND2BXLTS U2661 ( .AN(add_subt_module_Add_Subt_result[14]), .B(n2231), .Y(
n2216) );
NOR2X2TS U2662 ( .A(add_subt_module_Add_Subt_result[13]), .B(n2216), .Y(
n2359) );
NOR3X1TS U2663 ( .A(add_subt_module_Add_Subt_result[11]), .B(
add_subt_module_Add_Subt_result[10]), .C(n2247), .Y(n2159) );
NAND2X1TS U2664 ( .A(n2154), .B(n2639), .Y(n2158) );
NAND2X1TS U2665 ( .A(n2154), .B(n2159), .Y(n2355) );
NOR3X1TS U2666 ( .A(add_subt_module_Add_Subt_result[7]), .B(
add_subt_module_Add_Subt_result[6]), .C(n2355), .Y(n2220) );
NAND2X1TS U2667 ( .A(n2220), .B(n2639), .Y(n2155) );
NOR2BX1TS U2668 ( .AN(add_subt_module_Add_Subt_result[4]), .B(n2155), .Y(
n2214) );
NOR2XLTS U2669 ( .A(add_subt_module_Add_Subt_result[7]), .B(
add_subt_module_Add_Subt_result[6]), .Y(n2157) );
NOR2X1TS U2670 ( .A(n2155), .B(add_subt_module_Add_Subt_result[4]), .Y(n2219) );
INVX2TS U2671 ( .A(n2219), .Y(n2211) );
OAI22X1TS U2672 ( .A0(n2157), .A1(n2355), .B0(n2156), .B1(n2211), .Y(n2241)
);
AOI211XLTS U2673 ( .A0(n2159), .A1(n2158), .B0(n2214), .C0(n2241), .Y(n2162)
);
INVX2TS U2674 ( .A(n2364), .Y(n2366) );
NOR3X1TS U2675 ( .A(add_subt_module_Add_Subt_result[3]), .B(
add_subt_module_Add_Subt_result[2]), .C(n2211), .Y(n2234) );
OAI21XLTS U2676 ( .A0(add_subt_module_Add_Subt_result[1]), .A1(
add_subt_module_Add_Subt_result[0]), .B0(n2234), .Y(n2161) );
NOR2XLTS U2677 ( .A(n2366), .B(add_subt_module_LZA_output[4]), .Y(n2160) );
AOI31XLTS U2678 ( .A0(n2162), .A1(n2366), .A2(n2161), .B0(n2160), .Y(n1327)
);
NOR2X1TS U2679 ( .A(n2163), .B(n2349), .Y(n2284) );
AOI21X1TS U2680 ( .A0(cont_var_out[0]), .A1(n2349), .B0(n2284), .Y(n2348) );
OAI32X1TS U2681 ( .A0(n2166), .A1(n2165), .A2(n2647), .B0(n2348), .B1(n2164),
.Y(n1465) );
OAI222X1TS U2682 ( .A0(n2554), .A1(n2170), .B0(n2169), .B1(n2653), .C0(n2167), .C1(n2055), .Y(n1302) );
OAI222X1TS U2683 ( .A0(n2550), .A1(n2170), .B0(n2169), .B1(n2652), .C0(n2168), .C1(n2055), .Y(n1303) );
NOR2BX1TS U2684 ( .AN(add_subt_module_Sgf_normalized_result[25]), .B(n1555),
.Y(n2171) );
XOR2X1TS U2685 ( .A(n2664), .B(n2171), .Y(DP_OP_95J114_125_203_n31) );
XOR2X1TS U2686 ( .A(n2664), .B(n2172), .Y(DP_OP_95J114_125_203_n32) );
NOR2XLTS U2687 ( .A(n2645), .B(n1555), .Y(n2173) );
XOR2X1TS U2688 ( .A(n2664), .B(n2173), .Y(DP_OP_95J114_125_203_n33) );
NOR2XLTS U2689 ( .A(n2646), .B(n1555), .Y(n2174) );
XOR2X1TS U2690 ( .A(n2664), .B(n2174), .Y(DP_OP_95J114_125_203_n34) );
NOR2XLTS U2691 ( .A(n2640), .B(n1555), .Y(n2175) );
XOR2X1TS U2692 ( .A(n2664), .B(n2175), .Y(DP_OP_95J114_125_203_n35) );
NOR2XLTS U2693 ( .A(n2630), .B(n1555), .Y(n2176) );
XOR2X1TS U2694 ( .A(n2664), .B(n2176), .Y(DP_OP_95J114_125_203_n36) );
NOR2XLTS U2695 ( .A(n2631), .B(n1555), .Y(n2177) );
XOR2X1TS U2696 ( .A(n2664), .B(n2177), .Y(DP_OP_95J114_125_203_n37) );
NOR2XLTS U2697 ( .A(n2624), .B(n1555), .Y(n2178) );
XOR2X1TS U2698 ( .A(n2664), .B(n2178), .Y(DP_OP_95J114_125_203_n38) );
XOR2X1TS U2699 ( .A(n2664), .B(n2179), .Y(DP_OP_95J114_125_203_n39) );
NOR2XLTS U2700 ( .A(n2604), .B(n1555), .Y(n2180) );
XOR2X1TS U2701 ( .A(n2664), .B(n2180), .Y(DP_OP_95J114_125_203_n40) );
XOR2X1TS U2702 ( .A(n2664), .B(n2181), .Y(DP_OP_95J114_125_203_n41) );
NOR2XLTS U2703 ( .A(n2570), .B(n2678), .Y(n2182) );
XOR2X1TS U2704 ( .A(n2664), .B(n2182), .Y(DP_OP_95J114_125_203_n42) );
NOR2XLTS U2705 ( .A(n2571), .B(n2678), .Y(n2183) );
XOR2X1TS U2706 ( .A(n2664), .B(n2183), .Y(DP_OP_95J114_125_203_n43) );
NOR2XLTS U2707 ( .A(n2568), .B(n2678), .Y(n2184) );
XOR2X1TS U2708 ( .A(n2664), .B(n2184), .Y(DP_OP_95J114_125_203_n44) );
NOR2XLTS U2709 ( .A(n2564), .B(n2678), .Y(n2185) );
XOR2X1TS U2710 ( .A(n2664), .B(n2185), .Y(DP_OP_95J114_125_203_n45) );
NOR2XLTS U2711 ( .A(n2565), .B(n2678), .Y(n2186) );
XOR2X1TS U2712 ( .A(n2664), .B(n2186), .Y(DP_OP_95J114_125_203_n46) );
NOR2XLTS U2713 ( .A(n2562), .B(n2678), .Y(n2187) );
XOR2X1TS U2714 ( .A(n2191), .B(n2187), .Y(DP_OP_95J114_125_203_n47) );
NOR2XLTS U2715 ( .A(n2563), .B(n2678), .Y(n2188) );
XOR2X1TS U2716 ( .A(n2191), .B(n2188), .Y(DP_OP_95J114_125_203_n48) );
NOR2XLTS U2717 ( .A(n2560), .B(n2678), .Y(n2189) );
XOR2X1TS U2718 ( .A(n2191), .B(n2189), .Y(DP_OP_95J114_125_203_n49) );
NOR2XLTS U2719 ( .A(n2561), .B(n2678), .Y(n2190) );
XOR2X1TS U2720 ( .A(n2191), .B(n2190), .Y(DP_OP_95J114_125_203_n50) );
NOR2XLTS U2721 ( .A(n2558), .B(n2678), .Y(n2192) );
XOR2X1TS U2722 ( .A(n2664), .B(n2192), .Y(DP_OP_95J114_125_203_n51) );
NOR2XLTS U2723 ( .A(n2559), .B(n2678), .Y(n2193) );
XOR2X1TS U2724 ( .A(n2664), .B(n2193), .Y(DP_OP_95J114_125_203_n52) );
NOR2XLTS U2725 ( .A(n2555), .B(n2678), .Y(n2194) );
XOR2X1TS U2726 ( .A(n2664), .B(n2194), .Y(DP_OP_95J114_125_203_n53) );
NAND2X1TS U2727 ( .A(n2585), .B(n2553), .Y(n2195) );
XOR2X1TS U2728 ( .A(n2664), .B(n2195), .Y(DP_OP_95J114_125_203_n54) );
NOR2XLTS U2729 ( .A(n2678), .B(n2550), .Y(n2196) );
XOR2X1TS U2730 ( .A(n2664), .B(n2196), .Y(DP_OP_95J114_125_203_n55) );
NOR2XLTS U2731 ( .A(n2678), .B(n2554), .Y(n2197) );
XOR2X1TS U2732 ( .A(n2664), .B(n2197), .Y(DP_OP_95J114_125_203_n56) );
CLKAND2X2TS U2733 ( .A(n2204), .B(add_subt_module_DmP[30]), .Y(n2198) );
XOR2X1TS U2734 ( .A(n2110), .B(n2198), .Y(DP_OP_92J114_122_1254_n13) );
CLKAND2X2TS U2735 ( .A(n2204), .B(add_subt_module_DmP[29]), .Y(n2199) );
XOR2X1TS U2736 ( .A(n2110), .B(n2199), .Y(DP_OP_92J114_122_1254_n14) );
CLKAND2X2TS U2737 ( .A(n2204), .B(add_subt_module_DmP[28]), .Y(n2200) );
XOR2X1TS U2738 ( .A(n2110), .B(n2200), .Y(DP_OP_92J114_122_1254_n15) );
AO22XLTS U2739 ( .A0(add_subt_module_LZA_output[4]), .A1(n2205), .B0(n2204),
.B1(add_subt_module_DmP[27]), .Y(n2201) );
XOR2X1TS U2740 ( .A(n2110), .B(n2201), .Y(DP_OP_92J114_122_1254_n16) );
AO22XLTS U2741 ( .A0(add_subt_module_LZA_output[3]), .A1(n2205), .B0(n2204),
.B1(add_subt_module_DmP[26]), .Y(n2202) );
XOR2X1TS U2742 ( .A(n2110), .B(n2202), .Y(DP_OP_92J114_122_1254_n17) );
AO22XLTS U2743 ( .A0(add_subt_module_LZA_output[2]), .A1(n2205), .B0(n2204),
.B1(add_subt_module_DmP[25]), .Y(n2203) );
XOR2X1TS U2744 ( .A(n2110), .B(n2203), .Y(DP_OP_92J114_122_1254_n18) );
AO22XLTS U2745 ( .A0(add_subt_module_LZA_output[1]), .A1(n2205), .B0(n2204),
.B1(add_subt_module_DmP[24]), .Y(n2206) );
XOR2X1TS U2746 ( .A(n2110), .B(n2206), .Y(DP_OP_92J114_122_1254_n19) );
AO21XLTS U2747 ( .A0(add_subt_module_DmP[23]), .A1(n2599), .B0(n2207), .Y(
n2208) );
XOR2X1TS U2748 ( .A(n2110), .B(n2208), .Y(DP_OP_92J114_122_1254_n20) );
NAND2BXLTS U2749 ( .AN(add_subt_module_Sgf_normalized_result[25]), .B(n1555),
.Y(add_subt_module_S_A_S_Oper_A[25]) );
MX2X1TS U2750 ( .A(add_subt_module_DMP[22]), .B(
add_subt_module_Sgf_normalized_result[24]), .S0(n2230), .Y(
add_subt_module_S_A_S_Oper_A[24]) );
MX2X1TS U2751 ( .A(add_subt_module_DMP[21]), .B(
add_subt_module_Sgf_normalized_result[23]), .S0(n1555), .Y(
add_subt_module_S_A_S_Oper_A[23]) );
MX2X1TS U2752 ( .A(add_subt_module_DMP[20]), .B(
add_subt_module_Sgf_normalized_result[22]), .S0(n1555), .Y(
add_subt_module_S_A_S_Oper_A[22]) );
MX2X1TS U2753 ( .A(add_subt_module_DMP[19]), .B(
add_subt_module_Sgf_normalized_result[21]), .S0(n1555), .Y(
add_subt_module_S_A_S_Oper_A[21]) );
MX2X1TS U2754 ( .A(add_subt_module_DMP[18]), .B(
add_subt_module_Sgf_normalized_result[20]), .S0(n1555), .Y(
add_subt_module_S_A_S_Oper_A[20]) );
MX2X1TS U2755 ( .A(add_subt_module_DMP[17]), .B(
add_subt_module_Sgf_normalized_result[19]), .S0(n1555), .Y(
add_subt_module_S_A_S_Oper_A[19]) );
MX2X1TS U2756 ( .A(add_subt_module_DMP[16]), .B(
add_subt_module_Sgf_normalized_result[18]), .S0(n1555), .Y(
add_subt_module_S_A_S_Oper_A[18]) );
MX2X1TS U2757 ( .A(add_subt_module_DMP[15]), .B(
add_subt_module_Sgf_normalized_result[17]), .S0(n1555), .Y(
add_subt_module_S_A_S_Oper_A[17]) );
MX2X1TS U2758 ( .A(add_subt_module_DMP[14]), .B(
add_subt_module_Sgf_normalized_result[16]), .S0(n1555), .Y(
add_subt_module_S_A_S_Oper_A[16]) );
MX2X1TS U2759 ( .A(add_subt_module_DMP[13]), .B(
add_subt_module_Sgf_normalized_result[15]), .S0(n1555), .Y(
add_subt_module_S_A_S_Oper_A[15]) );
MX2X1TS U2760 ( .A(add_subt_module_DMP[12]), .B(
add_subt_module_Sgf_normalized_result[14]), .S0(n1555), .Y(
add_subt_module_S_A_S_Oper_A[14]) );
MX2X1TS U2761 ( .A(add_subt_module_DMP[11]), .B(
add_subt_module_Sgf_normalized_result[13]), .S0(n2678), .Y(
add_subt_module_S_A_S_Oper_A[13]) );
MX2X1TS U2762 ( .A(add_subt_module_DMP[10]), .B(
add_subt_module_Sgf_normalized_result[12]), .S0(n2230), .Y(
add_subt_module_S_A_S_Oper_A[12]) );
MX2X1TS U2763 ( .A(add_subt_module_DMP[9]), .B(
add_subt_module_Sgf_normalized_result[11]), .S0(n2230), .Y(
add_subt_module_S_A_S_Oper_A[11]) );
MX2X1TS U2764 ( .A(add_subt_module_DMP[8]), .B(
add_subt_module_Sgf_normalized_result[10]), .S0(n2230), .Y(
add_subt_module_S_A_S_Oper_A[10]) );
MX2X1TS U2765 ( .A(add_subt_module_DMP[7]), .B(
add_subt_module_Sgf_normalized_result[9]), .S0(n2230), .Y(
add_subt_module_S_A_S_Oper_A[9]) );
MX2X1TS U2766 ( .A(add_subt_module_DMP[6]), .B(
add_subt_module_Sgf_normalized_result[8]), .S0(n2230), .Y(
add_subt_module_S_A_S_Oper_A[8]) );
MX2X1TS U2767 ( .A(add_subt_module_DMP[5]), .B(
add_subt_module_Sgf_normalized_result[7]), .S0(n2230), .Y(
add_subt_module_S_A_S_Oper_A[7]) );
MX2X1TS U2768 ( .A(add_subt_module_DMP[4]), .B(
add_subt_module_Sgf_normalized_result[6]), .S0(n2230), .Y(
add_subt_module_S_A_S_Oper_A[6]) );
MX2X1TS U2769 ( .A(add_subt_module_DMP[3]), .B(
add_subt_module_Sgf_normalized_result[5]), .S0(n2230), .Y(
add_subt_module_S_A_S_Oper_A[5]) );
MX2X1TS U2770 ( .A(add_subt_module_DMP[2]), .B(
add_subt_module_Sgf_normalized_result[4]), .S0(n2230), .Y(
add_subt_module_S_A_S_Oper_A[4]) );
MX2X1TS U2771 ( .A(add_subt_module_DMP[1]), .B(
add_subt_module_Sgf_normalized_result[3]), .S0(n2230), .Y(
add_subt_module_S_A_S_Oper_A[3]) );
MX2X1TS U2772 ( .A(add_subt_module_DMP[0]), .B(
add_subt_module_Sgf_normalized_result[2]), .S0(n2230), .Y(
add_subt_module_S_A_S_Oper_A[2]) );
CLKAND2X2TS U2773 ( .A(n2230), .B(add_subt_module_Sgf_normalized_result[1]),
.Y(add_subt_module_S_A_S_Oper_A[1]) );
CLKAND2X2TS U2774 ( .A(n2230), .B(add_subt_module_Sgf_normalized_result[0]),
.Y(add_subt_module_S_A_S_Oper_A[0]) );
MX2X1TS U2775 ( .A(add_subt_module_add_overflow_flag), .B(n2210), .S0(n2209),
.Y(n1517) );
MX2X1TS U2776 ( .A(add_subt_module_Add_Subt_result[0]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[0]), .S0(n2209), .Y(n1333)
);
MX2X1TS U2777 ( .A(add_subt_module_Add_Subt_result[25]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[25]), .S0(n2249), .Y(n1332)
);
NAND2BXLTS U2778 ( .AN(add_subt_module_Add_Subt_result[1]), .B(
add_subt_module_Add_Subt_result[0]), .Y(n2212) );
AOI211X1TS U2779 ( .A0(n2637), .A1(n2212), .B0(
add_subt_module_Add_Subt_result[3]), .C0(n2211), .Y(n2213) );
INVX2TS U2780 ( .A(n2215), .Y(n2218) );
AOI2BB1X1TS U2781 ( .A0N(add_subt_module_Add_Subt_result[13]), .A1N(
add_subt_module_Add_Subt_result[11]), .B0(n2216), .Y(n2233) );
OAI31X1TS U2782 ( .A0(n2218), .A1(n2233), .A2(
add_subt_module_Add_Subt_result[19]), .B0(n2217), .Y(n2222) );
AOI22X1TS U2783 ( .A0(add_subt_module_Add_Subt_result[5]), .A1(n2220), .B0(
add_subt_module_Add_Subt_result[3]), .B1(n2219), .Y(n2221) );
NAND4XLTS U2784 ( .A(n2363), .B(n2222), .C(n2221), .D(n2232), .Y(n2223) );
MXI2X1TS U2785 ( .A(n2599), .B(add_subt_module_add_overflow_flag), .S0(n2224), .Y(n1369) );
NAND2X1TS U2786 ( .A(n2225), .B(add_subt_module_FS_Module_state_reg[0]), .Y(
n2226) );
MX2X1TS U2787 ( .A(add_subt_module_Exp_Operation_Module_Data_S[7]), .B(
add_subt_module_exp_oper_result[7]), .S0(n2229), .Y(n1360) );
MX2X1TS U2788 ( .A(add_subt_module_DMP[30]), .B(
add_subt_module_exp_oper_result[7]), .S0(n2230), .Y(
add_subt_module_S_Oper_A_exp[7]) );
MX2X1TS U2789 ( .A(add_subt_module_Exp_Operation_Module_Data_S[6]), .B(
add_subt_module_exp_oper_result[6]), .S0(n2229), .Y(n1367) );
MX2X1TS U2790 ( .A(add_subt_module_DMP[29]), .B(
add_subt_module_exp_oper_result[6]), .S0(n2230), .Y(
add_subt_module_S_Oper_A_exp[6]) );
MX2X1TS U2791 ( .A(add_subt_module_Exp_Operation_Module_Data_S[5]), .B(
add_subt_module_exp_oper_result[5]), .S0(n2229), .Y(n1366) );
MX2X1TS U2792 ( .A(add_subt_module_DMP[28]), .B(
add_subt_module_exp_oper_result[5]), .S0(n2230), .Y(
add_subt_module_S_Oper_A_exp[5]) );
MX2X1TS U2793 ( .A(add_subt_module_Exp_Operation_Module_Data_S[4]), .B(
add_subt_module_exp_oper_result[4]), .S0(n2229), .Y(n1365) );
MX2X1TS U2794 ( .A(add_subt_module_DMP[27]), .B(
add_subt_module_exp_oper_result[4]), .S0(n2230), .Y(
add_subt_module_S_Oper_A_exp[4]) );
MX2X1TS U2795 ( .A(add_subt_module_Exp_Operation_Module_Data_S[3]), .B(
add_subt_module_exp_oper_result[3]), .S0(n2229), .Y(n1364) );
MX2X1TS U2796 ( .A(add_subt_module_DMP[26]), .B(
add_subt_module_exp_oper_result[3]), .S0(n2230), .Y(
add_subt_module_S_Oper_A_exp[3]) );
MX2X1TS U2797 ( .A(add_subt_module_DMP[25]), .B(
add_subt_module_exp_oper_result[2]), .S0(n2230), .Y(
add_subt_module_S_Oper_A_exp[2]) );
MX2X1TS U2798 ( .A(add_subt_module_Exp_Operation_Module_Data_S[1]), .B(
add_subt_module_exp_oper_result[1]), .S0(n2229), .Y(n1362) );
MX2X1TS U2799 ( .A(add_subt_module_DMP[24]), .B(
add_subt_module_exp_oper_result[1]), .S0(n2230), .Y(
add_subt_module_S_Oper_A_exp[1]) );
MX2X1TS U2800 ( .A(add_subt_module_Exp_Operation_Module_Data_S[0]), .B(
add_subt_module_exp_oper_result[0]), .S0(n2229), .Y(n1361) );
MX2X1TS U2801 ( .A(add_subt_module_DMP[23]), .B(
add_subt_module_exp_oper_result[0]), .S0(n2230), .Y(
add_subt_module_S_Oper_A_exp[0]) );
NOR3XLTS U2802 ( .A(add_subt_module_Add_Subt_result[15]), .B(
add_subt_module_Add_Subt_result[16]), .C(
add_subt_module_Add_Subt_result[17]), .Y(n2237) );
NAND2X1TS U2803 ( .A(add_subt_module_Add_Subt_result[14]), .B(n2231), .Y(
n2245) );
NAND2X1TS U2804 ( .A(n2245), .B(n2232), .Y(n2356) );
OAI21XLTS U2805 ( .A0(n2237), .A1(n2236), .B0(n2235), .Y(n2238) );
AO22XLTS U2806 ( .A0(n2238), .A1(n2366), .B0(add_subt_module_LZA_output[3]),
.B1(n2364), .Y(n1328) );
NOR2X1TS U2807 ( .A(add_subt_module_Add_Subt_result[11]), .B(
add_subt_module_Add_Subt_result[10]), .Y(n2358) );
NOR2XLTS U2808 ( .A(add_subt_module_Add_Subt_result[24]), .B(
add_subt_module_Add_Subt_result[25]), .Y(n2244) );
OR2X1TS U2809 ( .A(add_subt_module_Add_Subt_result[22]), .B(
add_subt_module_Add_Subt_result[23]), .Y(n2243) );
OAI31X1TS U2810 ( .A0(n2583), .A1(add_subt_module_Add_Subt_result[16]), .A2(
add_subt_module_Add_Subt_result[17]), .B0(n2644), .Y(n2240) );
AOI2BB1XLTS U2811 ( .A0N(n2240), .A1N(add_subt_module_Add_Subt_result[18]),
.B0(n2239), .Y(n2242) );
AOI211X1TS U2812 ( .A0(n2244), .A1(n2243), .B0(n2242), .C0(n2241), .Y(n2246)
);
OAI211XLTS U2813 ( .A0(n2358), .A1(n2247), .B0(n2246), .C0(n2245), .Y(n2248)
);
MX2X1TS U2814 ( .A(add_subt_module_Exp_Operation_Module_Data_S[2]), .B(
add_subt_module_exp_oper_result[2]), .S0(n2229), .Y(n1363) );
MX2X1TS U2815 ( .A(add_subt_module_Add_Subt_result[1]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[1]), .S0(n2249), .Y(n1334)
);
MX2X1TS U2816 ( .A(add_subt_module_Add_Subt_result[24]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[24]), .S0(n2249), .Y(n1357)
);
MX2X1TS U2817 ( .A(add_subt_module_Add_Subt_result[23]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[23]), .S0(n2209), .Y(n1356)
);
MX2X1TS U2818 ( .A(add_subt_module_Add_Subt_result[2]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[2]), .S0(n2249), .Y(n1335)
);
MX2X1TS U2819 ( .A(add_subt_module_Add_Subt_result[22]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[22]), .S0(n2209), .Y(n1355)
);
MX2X1TS U2820 ( .A(add_subt_module_Add_Subt_result[3]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[3]), .S0(n2249), .Y(n1336)
);
MX2X1TS U2821 ( .A(add_subt_module_Add_Subt_result[4]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[4]), .S0(n2209), .Y(n1337)
);
MX2X1TS U2822 ( .A(add_subt_module_Add_Subt_result[21]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[21]), .S0(n2249), .Y(n1354)
);
MX2X1TS U2823 ( .A(add_subt_module_Add_Subt_result[5]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[5]), .S0(n2249), .Y(n1338)
);
MX2X1TS U2824 ( .A(add_subt_module_Add_Subt_result[20]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[20]), .S0(n2209), .Y(n1353)
);
MX2X1TS U2825 ( .A(add_subt_module_Add_Subt_result[6]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[6]), .S0(n2249), .Y(n1339)
);
MX2X1TS U2826 ( .A(add_subt_module_Add_Subt_result[19]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[19]), .S0(n2249), .Y(n1352)
);
MX2X1TS U2827 ( .A(add_subt_module_Add_Subt_result[7]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[7]), .S0(n2249), .Y(n1340)
);
MX2X1TS U2828 ( .A(add_subt_module_Add_Subt_result[18]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[18]), .S0(n2249), .Y(n1351)
);
MX2X1TS U2829 ( .A(add_subt_module_Add_Subt_result[8]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[8]), .S0(n2249), .Y(n1341)
);
MX2X1TS U2830 ( .A(add_subt_module_Add_Subt_result[17]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[17]), .S0(n2249), .Y(n1350)
);
MX2X1TS U2831 ( .A(add_subt_module_Add_Subt_result[9]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[9]), .S0(n2249), .Y(n1342)
);
MX2X1TS U2832 ( .A(add_subt_module_Add_Subt_result[16]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[16]), .S0(n2249), .Y(n1349)
);
MX2X1TS U2833 ( .A(add_subt_module_Add_Subt_result[10]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[10]), .S0(n2249), .Y(n1343)
);
MX2X1TS U2834 ( .A(add_subt_module_Add_Subt_result[15]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[15]), .S0(n2249), .Y(n1348)
);
MX2X1TS U2835 ( .A(add_subt_module_Add_Subt_result[11]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[11]), .S0(n2249), .Y(n1344)
);
MX2X1TS U2836 ( .A(add_subt_module_Add_Subt_result[14]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[14]), .S0(n2249), .Y(n1347)
);
MX2X1TS U2837 ( .A(add_subt_module_Add_Subt_result[12]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[12]), .S0(n2249), .Y(n1345)
);
MX2X1TS U2838 ( .A(add_subt_module_Add_Subt_result[13]), .B(
add_subt_module_Add_Subt_Sgf_module_S_to_D[13]), .S0(n2249), .Y(n1346)
);
AND4X1TS U2839 ( .A(add_subt_module_Exp_Operation_Module_Data_S[3]), .B(
add_subt_module_Exp_Operation_Module_Data_S[2]), .C(
add_subt_module_Exp_Operation_Module_Data_S[0]), .D(
add_subt_module_Exp_Operation_Module_Data_S[1]), .Y(n2250) );
AND4X1TS U2840 ( .A(add_subt_module_Exp_Operation_Module_Data_S[6]), .B(
add_subt_module_Exp_Operation_Module_Data_S[5]), .C(
add_subt_module_Exp_Operation_Module_Data_S[4]), .D(n2250), .Y(n2252)
);
AOI21X1TS U2841 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[7]), .A1(
n2252), .B0(n2251), .Y(n2253) );
MXI2X1TS U2842 ( .A(n2253), .B(n2655), .S0(n2229), .Y(n1359) );
INVX2TS U2843 ( .A(n2255), .Y(n2265) );
AOI22X1TS U2844 ( .A0(n2262), .A1(n2265), .B0(n1880), .B1(n2260), .Y(n2256)
);
OAI22X1TS U2845 ( .A0(n2267), .A1(n2257), .B0(n2256), .B1(n2266), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]) );
NOR2XLTS U2846 ( .A(n2266), .B(n2264), .Y(n2259) );
AOI222X1TS U2847 ( .A0(n2260), .A1(n2262), .B0(n2265), .B1(n1876), .C0(n2261), .C1(n1880), .Y(n2258) );
OAI22X1TS U2848 ( .A0(n2267), .A1(n2259), .B0(n2258), .B1(n2266), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI22X1TS U2849 ( .A0(n2262), .A1(n2261), .B0(n1876), .B1(n2260), .Y(n2269)
);
AOI22X1TS U2850 ( .A0(n2265), .A1(n2264), .B0(n1880), .B1(n2263), .Y(n2268)
);
AOI32X1TS U2851 ( .A0(n2269), .A1(n1877), .A2(n2268), .B0(n2267), .B1(n2266),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]) );
AND3X1TS U2852 ( .A(n2447), .B(n2556), .C(cordic_FSM_state_reg[0]), .Y(
ready_cordic) );
OAI211X1TS U2853 ( .A0(cordic_FSM_state_reg[1]), .A1(ack_cordic), .B0(
cordic_FSM_state_reg[2]), .C0(n2270), .Y(n2272) );
OAI31X1TS U2854 ( .A0(n2350), .A1(n2281), .A2(n2551), .B0(n2556), .Y(n2271)
);
AOI32X1TS U2855 ( .A0(cordic_FSM_state_reg[0]), .A1(n2272), .A2(n2271), .B0(
cordic_FSM_state_reg[2]), .B1(n2272), .Y(n2274) );
AOI32X1TS U2856 ( .A0(cordic_FSM_state_reg[0]), .A1(n2274), .A2(
cordic_FSM_state_reg[1]), .B0(n2273), .B1(n2274), .Y(n1520) );
NAND2X1TS U2857 ( .A(n2551), .B(n2588), .Y(n2279) );
AOI21X1TS U2858 ( .A0(n2282), .A1(n2556), .B0(cordic_FSM_state_reg[0]), .Y(
n2276) );
NAND4XLTS U2859 ( .A(n2279), .B(n2294), .C(n2278), .D(n2277), .Y(n1519) );
OAI211XLTS U2860 ( .A0(add_subt_module_sign_final_result), .A1(
underflow_flag), .B0(n2104), .C0(n2655), .Y(n2280) );
OAI2BB1X1TS U2861 ( .A0N(n2369), .A1N(result_add_subt[31]), .B0(n2280), .Y(
n1514) );
AOI21X1TS U2862 ( .A0(n2633), .A1(n2581), .B0(n2281), .Y(n2283) );
NAND4BX1TS U2863 ( .AN(n2282), .B(n2586), .C(cordic_FSM_state_reg[3]), .D(
n2448), .Y(n2351) );
OR3X1TS U2864 ( .A(n2284), .B(n2283), .C(n2351), .Y(n2285) );
INVX4TS U2865 ( .A(n2285), .Y(n2446) );
CLKBUFX3TS U2866 ( .A(n2368), .Y(n2445) );
AO22XLTS U2867 ( .A0(n2446), .A1(result_add_subt[31]), .B0(n2445), .B1(
d_ff_Xn[31]), .Y(n1513) );
INVX4TS U2868 ( .A(n2416), .Y(n2440) );
AO22XLTS U2869 ( .A0(d_ff_Xn[31]), .A1(n2347), .B0(d_ff2_X[31]), .B1(n2440),
.Y(n1512) );
AOI22X1TS U2870 ( .A0(add_subt_module_FS_Module_state_reg[2]), .A1(n2289),
.B0(n2288), .B1(n1546), .Y(n2290) );
NAND3BXLTS U2871 ( .AN(n2292), .B(n2291), .C(n2290), .Y(n1508) );
NAND2X1TS U2872 ( .A(n2662), .B(n2304), .Y(n2314) );
AOI22X1TS U2873 ( .A0(n2663), .A1(n2295), .B0(n2294), .B1(n2702), .Y(n1504)
);
INVX4TS U2874 ( .A(n1531), .Y(n2298) );
OAI2BB2XLTS U2875 ( .B0(n2299), .B1(n2649), .A0N(n2298), .A1N(operation),
.Y(n1501) );
OAI2BB2XLTS U2876 ( .B0(n2299), .B1(n2582), .A0N(n2298), .A1N(
shift_region_flag[0]), .Y(n1500) );
OAI2BB2XLTS U2877 ( .B0(n2299), .B1(n2552), .A0N(n2298), .A1N(
shift_region_flag[1]), .Y(n1499) );
AO22XLTS U2878 ( .A0(n2298), .A1(data_in[30]), .B0(n2296), .B1(d_ff1_Z[30]),
.Y(n1498) );
AO22XLTS U2879 ( .A0(n2298), .A1(data_in[29]), .B0(n1531), .B1(d_ff1_Z[29]),
.Y(n1497) );
AO22XLTS U2880 ( .A0(n2298), .A1(data_in[28]), .B0(n1531), .B1(d_ff1_Z[28]),
.Y(n1496) );
BUFX3TS U2881 ( .A(n1531), .Y(n2297) );
AO22XLTS U2882 ( .A0(n2298), .A1(data_in[27]), .B0(n2297), .B1(d_ff1_Z[27]),
.Y(n1495) );
AO22XLTS U2883 ( .A0(n2298), .A1(data_in[26]), .B0(n2297), .B1(d_ff1_Z[26]),
.Y(n1494) );
AO22XLTS U2884 ( .A0(n2298), .A1(data_in[25]), .B0(n2297), .B1(d_ff1_Z[25]),
.Y(n1493) );
AO22XLTS U2885 ( .A0(n2298), .A1(data_in[24]), .B0(n2297), .B1(d_ff1_Z[24]),
.Y(n1492) );
AO22XLTS U2886 ( .A0(n2298), .A1(data_in[23]), .B0(n2297), .B1(d_ff1_Z[23]),
.Y(n1491) );
AO22XLTS U2887 ( .A0(n2298), .A1(data_in[22]), .B0(n2297), .B1(d_ff1_Z[22]),
.Y(n1490) );
AO22XLTS U2888 ( .A0(n2298), .A1(data_in[21]), .B0(n2297), .B1(d_ff1_Z[21]),
.Y(n1489) );
AO22XLTS U2889 ( .A0(n2298), .A1(data_in[20]), .B0(n2297), .B1(d_ff1_Z[20]),
.Y(n1488) );
AO22XLTS U2890 ( .A0(n2298), .A1(data_in[19]), .B0(n2297), .B1(d_ff1_Z[19]),
.Y(n1487) );
AO22XLTS U2891 ( .A0(n2298), .A1(data_in[18]), .B0(n2297), .B1(d_ff1_Z[18]),
.Y(n1486) );
AO22XLTS U2892 ( .A0(n2298), .A1(data_in[17]), .B0(n2297), .B1(d_ff1_Z[17]),
.Y(n1485) );
AO22XLTS U2893 ( .A0(n2299), .A1(data_in[16]), .B0(n2297), .B1(d_ff1_Z[16]),
.Y(n1484) );
AO22XLTS U2894 ( .A0(n2298), .A1(data_in[15]), .B0(n1531), .B1(d_ff1_Z[15]),
.Y(n1483) );
AO22XLTS U2895 ( .A0(n2299), .A1(data_in[14]), .B0(n1531), .B1(d_ff1_Z[14]),
.Y(n1482) );
AO22XLTS U2896 ( .A0(n2299), .A1(data_in[13]), .B0(n1531), .B1(d_ff1_Z[13]),
.Y(n1481) );
AO22XLTS U2897 ( .A0(n2299), .A1(data_in[12]), .B0(n1531), .B1(d_ff1_Z[12]),
.Y(n1480) );
AO22XLTS U2898 ( .A0(n2299), .A1(data_in[11]), .B0(n1531), .B1(d_ff1_Z[11]),
.Y(n1479) );
AO22XLTS U2899 ( .A0(n2299), .A1(data_in[10]), .B0(n1531), .B1(d_ff1_Z[10]),
.Y(n1478) );
AO22XLTS U2900 ( .A0(n2299), .A1(data_in[9]), .B0(n1531), .B1(d_ff1_Z[9]),
.Y(n1477) );
AO22XLTS U2901 ( .A0(n2299), .A1(data_in[8]), .B0(n1531), .B1(d_ff1_Z[8]),
.Y(n1476) );
AO22XLTS U2902 ( .A0(n2299), .A1(data_in[7]), .B0(n1531), .B1(d_ff1_Z[7]),
.Y(n1475) );
AO22XLTS U2903 ( .A0(n2299), .A1(data_in[6]), .B0(n1531), .B1(d_ff1_Z[6]),
.Y(n1474) );
AO22XLTS U2904 ( .A0(n2299), .A1(data_in[5]), .B0(n1531), .B1(d_ff1_Z[5]),
.Y(n1473) );
AO22XLTS U2905 ( .A0(n2299), .A1(data_in[4]), .B0(n1531), .B1(d_ff1_Z[4]),
.Y(n1472) );
AO22XLTS U2906 ( .A0(n2299), .A1(data_in[3]), .B0(n1531), .B1(d_ff1_Z[3]),
.Y(n1471) );
AO22XLTS U2907 ( .A0(n2299), .A1(data_in[2]), .B0(n1531), .B1(d_ff1_Z[2]),
.Y(n1470) );
AO22XLTS U2908 ( .A0(n2299), .A1(data_in[1]), .B0(n1531), .B1(d_ff1_Z[1]),
.Y(n1469) );
AO22XLTS U2909 ( .A0(n2299), .A1(data_in[0]), .B0(n1531), .B1(d_ff1_Z[0]),
.Y(n1468) );
AO22XLTS U2910 ( .A0(n2299), .A1(data_in[31]), .B0(n1531), .B1(d_ff1_Z[31]),
.Y(n1467) );
NOR3X1TS U2911 ( .A(cordic_FSM_state_reg[3]), .B(n2588), .C(n2300), .Y(n2302) );
NAND2X1TS U2912 ( .A(sel_mux_1_reg), .B(n2699), .Y(n2301) );
OAI2BB2XLTS U2913 ( .B0(n2302), .B1(n2301), .A0N(n2302), .A1N(n2321), .Y(
n1466) );
INVX2TS U2914 ( .A(n2303), .Y(n2307) );
AOI22X1TS U2915 ( .A0(n2306), .A1(n2305), .B0(n2304), .B1(n1536), .Y(n2311)
);
AOI2BB2XLTS U2916 ( .B0(n2307), .B1(n2311), .A0N(n2439), .A1N(
d_ff3_LUT_out[26]), .Y(n1462) );
AOI32X1TS U2917 ( .A0(n2308), .A1(n2436), .A2(n2314), .B0(n2659), .B1(n1558),
.Y(n1461) );
OAI2BB1X1TS U2918 ( .A0N(d_ff3_LUT_out[22]), .A1N(n1558), .B0(n2309), .Y(
n1458) );
OAI221XLTS U2919 ( .A0(n2439), .A1(n2657), .B0(n2425), .B1(n2313), .C0(n2312), .Y(n1457) );
OAI2BB1X1TS U2920 ( .A0N(d_ff3_LUT_out[20]), .A1N(n2390), .B0(n2312), .Y(
n1456) );
OAI2BB1X1TS U2921 ( .A0N(d_ff3_LUT_out[19]), .A1N(n1558), .B0(n2309), .Y(
n1455) );
AOI31X1TS U2922 ( .A0(n2311), .A1(n2313), .A2(n2310), .B0(n2397), .Y(n2316)
);
AO21XLTS U2923 ( .A0(d_ff3_LUT_out[18]), .A1(n2390), .B0(n2316), .Y(n1454)
);
OAI2BB1X1TS U2924 ( .A0N(d_ff3_LUT_out[17]), .A1N(n2390), .B0(n2312), .Y(
n1453) );
AO21XLTS U2925 ( .A0(d_ff3_LUT_out[16]), .A1(n2390), .B0(n2324), .Y(n1452)
);
OAI2BB1X1TS U2926 ( .A0N(d_ff3_LUT_out[15]), .A1N(n2390), .B0(n2312), .Y(
n1451) );
NOR2X1TS U2927 ( .A(cont_iter_out[1]), .B(n2313), .Y(n2325) );
OAI221X1TS U2928 ( .A0(cont_iter_out[3]), .A1(n2315), .B0(n2575), .B1(n2662),
.C0(n2314), .Y(n2317) );
OAI21X1TS U2929 ( .A0(n2325), .A1(n2317), .B0(n2439), .Y(n2323) );
OAI2BB1X1TS U2930 ( .A0N(d_ff3_LUT_out[14]), .A1N(n2390), .B0(n2323), .Y(
n1450) );
AO21XLTS U2931 ( .A0(d_ff3_LUT_out[13]), .A1(n2390), .B0(n2316), .Y(n1449)
);
AO22XLTS U2932 ( .A0(n2434), .A1(n2317), .B0(n2390), .B1(d_ff3_LUT_out[12]),
.Y(n1448) );
OA21XLTS U2933 ( .A0(n2434), .A1(d_ff3_LUT_out[10]), .B0(n2318), .Y(n1446)
);
OAI2BB2XLTS U2934 ( .B0(n2425), .B1(n2662), .A0N(n2390), .A1N(
d_ff3_LUT_out[8]), .Y(n1444) );
AOI31XLTS U2935 ( .A0(n2663), .A1(cont_iter_out[3]), .A2(n2320), .B0(n2319),
.Y(n2322) );
AOI32X1TS U2936 ( .A0(n2322), .A1(n2436), .A2(n2321), .B0(n2658), .B1(n1558),
.Y(n1442) );
OAI2BB1X1TS U2937 ( .A0N(d_ff3_LUT_out[5]), .A1N(n2390), .B0(n2323), .Y(
n1441) );
AO21XLTS U2938 ( .A0(d_ff3_LUT_out[3]), .A1(n2390), .B0(n2324), .Y(n1439) );
NAND2X1TS U2939 ( .A(n2662), .B(n2325), .Y(n2326) );
AOI32X1TS U2940 ( .A0(n2327), .A1(n2436), .A2(n2326), .B0(n2660), .B1(n1558),
.Y(n1438) );
BUFX3TS U2941 ( .A(n2390), .Y(n2394) );
AO22XLTS U2942 ( .A0(n2434), .A1(d_ff2_X[31]), .B0(n2394), .B1(
d_ff3_sh_x_out[31]), .Y(n1435) );
AO22XLTS U2943 ( .A0(d_ff_Xn[30]), .A1(n2347), .B0(d_ff2_X[30]), .B1(n2440),
.Y(n1434) );
INVX2TS U2944 ( .A(n2418), .Y(n2345) );
OA22X1TS U2945 ( .A0(d_ff2_X[29]), .A1(n2416), .B0(d_ff_Xn[29]), .B1(n2345),
.Y(n1433) );
BUFX3TS U2946 ( .A(n2416), .Y(n2346) );
OA22X1TS U2947 ( .A0(d_ff2_X[28]), .A1(n2346), .B0(d_ff_Xn[28]), .B1(n2345),
.Y(n1432) );
OA22X1TS U2948 ( .A0(n1554), .A1(n2346), .B0(d_ff_Xn[27]), .B1(n2345), .Y(
n1431) );
OA22X1TS U2949 ( .A0(d_ff2_X[26]), .A1(n2346), .B0(d_ff_Xn[26]), .B1(n2345),
.Y(n1430) );
OA22X1TS U2950 ( .A0(n1549), .A1(n2346), .B0(d_ff_Xn[25]), .B1(n2345), .Y(
n1429) );
OA22X1TS U2951 ( .A0(d_ff2_X[24]), .A1(n2346), .B0(d_ff_Xn[24]), .B1(n2345),
.Y(n1428) );
AO22XLTS U2952 ( .A0(d_ff_Xn[23]), .A1(n2347), .B0(d_ff2_X[23]), .B1(n2412),
.Y(n1427) );
INVX4TS U2953 ( .A(n2443), .Y(n2428) );
OAI2BB1X1TS U2954 ( .A0N(n2428), .A1N(n2332), .B0(n2328), .Y(n1426) );
AOI22X1TS U2955 ( .A0(cont_iter_out[1]), .A1(n2635), .B0(d_ff2_X[24]), .B1(
n2566), .Y(n2329) );
XNOR2X1TS U2956 ( .A(n2332), .B(n2329), .Y(n2330) );
AO22XLTS U2957 ( .A0(n2434), .A1(n2330), .B0(n2394), .B1(d_ff3_sh_x_out[24]),
.Y(n1425) );
NAND2X1TS U2958 ( .A(d_ff2_X[24]), .B(n2566), .Y(n2331) );
AOI22X1TS U2959 ( .A0(cont_iter_out[1]), .A1(n2635), .B0(n2332), .B1(n2331),
.Y(n2334) );
AO22XLTS U2960 ( .A0(n2434), .A1(n2333), .B0(n2394), .B1(d_ff3_sh_x_out[25]),
.Y(n1424) );
CMPR32X2TS U2961 ( .A(n1549), .B(n1536), .C(n2334), .CO(n2336), .S(n2333) );
AO22XLTS U2962 ( .A0(n2434), .A1(n2335), .B0(n2394), .B1(d_ff3_sh_x_out[26]),
.Y(n1423) );
NOR2XLTS U2963 ( .A(n1554), .B(n2339), .Y(n2337) );
AOI21X1TS U2964 ( .A0(n2339), .A1(n1554), .B0(n2337), .Y(n2338) );
AOI2BB2XLTS U2965 ( .B0(n2436), .B1(n2338), .A0N(d_ff3_sh_x_out[27]), .A1N(
n2434), .Y(n1422) );
OR3X1TS U2966 ( .A(d_ff2_X[28]), .B(n1554), .C(n2339), .Y(n2341) );
OAI21XLTS U2967 ( .A0(n1554), .A1(n2339), .B0(d_ff2_X[28]), .Y(n2340) );
AOI32X1TS U2968 ( .A0(n2341), .A1(n2436), .A2(n2340), .B0(n2661), .B1(n2425),
.Y(n1421) );
NOR2X1TS U2969 ( .A(d_ff2_X[29]), .B(n2341), .Y(n2343) );
AOI21X1TS U2970 ( .A0(d_ff2_X[29]), .A1(n2341), .B0(n2343), .Y(n2342) );
AOI2BB2XLTS U2971 ( .B0(n2439), .B1(n2342), .A0N(d_ff3_sh_x_out[29]), .A1N(
n2434), .Y(n1420) );
XOR2XLTS U2972 ( .A(d_ff2_X[30]), .B(n2343), .Y(n2344) );
AO22XLTS U2973 ( .A0(n2434), .A1(n2344), .B0(n2394), .B1(d_ff3_sh_x_out[30]),
.Y(n1419) );
AO22XLTS U2974 ( .A0(d_ff_Xn[22]), .A1(n2347), .B0(d_ff2_X[22]), .B1(n2412),
.Y(n1418) );
AO22XLTS U2975 ( .A0(n2434), .A1(d_ff2_X[22]), .B0(n2394), .B1(
d_ff3_sh_x_out[22]), .Y(n1417) );
AO22XLTS U2976 ( .A0(d_ff_Xn[21]), .A1(n2414), .B0(d_ff2_X[21]), .B1(n2412),
.Y(n1416) );
AO22XLTS U2977 ( .A0(n2434), .A1(d_ff2_X[21]), .B0(n2394), .B1(
d_ff3_sh_x_out[21]), .Y(n1415) );
OA22X1TS U2978 ( .A0(d_ff2_X[20]), .A1(n2346), .B0(d_ff_Xn[20]), .B1(n2345),
.Y(n1414) );
AO22XLTS U2979 ( .A0(n2434), .A1(d_ff2_X[20]), .B0(n2394), .B1(
d_ff3_sh_x_out[20]), .Y(n1413) );
OA22X1TS U2980 ( .A0(d_ff2_X[19]), .A1(n2346), .B0(d_ff_Xn[19]), .B1(n2345),
.Y(n1412) );
AO22XLTS U2981 ( .A0(n2434), .A1(d_ff2_X[19]), .B0(n2394), .B1(
d_ff3_sh_x_out[19]), .Y(n1411) );
AO22XLTS U2982 ( .A0(d_ff_Xn[18]), .A1(n2414), .B0(d_ff2_X[18]), .B1(n2440),
.Y(n1410) );
AO22XLTS U2983 ( .A0(n2434), .A1(d_ff2_X[18]), .B0(n2394), .B1(
d_ff3_sh_x_out[18]), .Y(n1409) );
OA22X1TS U2984 ( .A0(d_ff2_X[17]), .A1(n2346), .B0(d_ff_Xn[17]), .B1(n2345),
.Y(n1408) );
AO22XLTS U2985 ( .A0(n2428), .A1(d_ff2_X[17]), .B0(n2394), .B1(
d_ff3_sh_x_out[17]), .Y(n1407) );
OA22X1TS U2986 ( .A0(d_ff2_X[16]), .A1(n2346), .B0(d_ff_Xn[16]), .B1(n2345),
.Y(n1406) );
BUFX3TS U2987 ( .A(n2390), .Y(n2443) );
AO22XLTS U2988 ( .A0(n2428), .A1(d_ff2_X[16]), .B0(n2443), .B1(
d_ff3_sh_x_out[16]), .Y(n1405) );
AO22XLTS U2989 ( .A0(d_ff_Xn[15]), .A1(n2347), .B0(d_ff2_X[15]), .B1(n2440),
.Y(n1404) );
AO22XLTS U2990 ( .A0(n2428), .A1(d_ff2_X[15]), .B0(n2443), .B1(
d_ff3_sh_x_out[15]), .Y(n1403) );
INVX4TS U2991 ( .A(n2418), .Y(n2399) );
OA22X1TS U2992 ( .A0(d_ff2_X[14]), .A1(n2346), .B0(d_ff_Xn[14]), .B1(n2399),
.Y(n1402) );
AO22XLTS U2993 ( .A0(n2428), .A1(d_ff2_X[14]), .B0(n2443), .B1(
d_ff3_sh_x_out[14]), .Y(n1401) );
OA22X1TS U2994 ( .A0(d_ff2_X[13]), .A1(n2346), .B0(d_ff_Xn[13]), .B1(n2399),
.Y(n1400) );
AO22XLTS U2995 ( .A0(n2428), .A1(d_ff2_X[13]), .B0(n2443), .B1(
d_ff3_sh_x_out[13]), .Y(n1399) );
OA22X1TS U2996 ( .A0(d_ff2_X[12]), .A1(n2416), .B0(d_ff_Xn[12]), .B1(n2399),
.Y(n1398) );
AO22XLTS U2997 ( .A0(n2428), .A1(d_ff2_X[12]), .B0(n2443), .B1(
d_ff3_sh_x_out[12]), .Y(n1397) );
AO22XLTS U2998 ( .A0(d_ff_Xn[11]), .A1(n2347), .B0(d_ff2_X[11]), .B1(n2440),
.Y(n1396) );
AO22XLTS U2999 ( .A0(n2428), .A1(d_ff2_X[11]), .B0(n2443), .B1(
d_ff3_sh_x_out[11]), .Y(n1395) );
OA22X1TS U3000 ( .A0(d_ff2_X[10]), .A1(n2416), .B0(d_ff_Xn[10]), .B1(n2399),
.Y(n1394) );
AO22XLTS U3001 ( .A0(n2428), .A1(d_ff2_X[10]), .B0(n2443), .B1(
d_ff3_sh_x_out[10]), .Y(n1393) );
AO22XLTS U3002 ( .A0(d_ff_Xn[9]), .A1(n2347), .B0(d_ff2_X[9]), .B1(n2412),
.Y(n1392) );
AO22XLTS U3003 ( .A0(n2428), .A1(d_ff2_X[9]), .B0(n2443), .B1(
d_ff3_sh_x_out[9]), .Y(n1391) );
AO22XLTS U3004 ( .A0(d_ff_Xn[8]), .A1(n2347), .B0(d_ff2_X[8]), .B1(n2412),
.Y(n1390) );
AO22XLTS U3005 ( .A0(n2428), .A1(d_ff2_X[8]), .B0(n2443), .B1(
d_ff3_sh_x_out[8]), .Y(n1389) );
OA22X1TS U3006 ( .A0(d_ff2_X[7]), .A1(n2416), .B0(d_ff_Xn[7]), .B1(n2399),
.Y(n1388) );
AO22XLTS U3007 ( .A0(n2428), .A1(d_ff2_X[7]), .B0(n2443), .B1(
d_ff3_sh_x_out[7]), .Y(n1387) );
OA22X1TS U3008 ( .A0(d_ff2_X[6]), .A1(n2416), .B0(d_ff_Xn[6]), .B1(n2399),
.Y(n1386) );
BUFX3TS U3009 ( .A(n2390), .Y(n2397) );
AO22XLTS U3010 ( .A0(n2428), .A1(d_ff2_X[6]), .B0(n2397), .B1(
d_ff3_sh_x_out[6]), .Y(n1385) );
OA22X1TS U3011 ( .A0(d_ff2_X[5]), .A1(n2346), .B0(d_ff_Xn[5]), .B1(n2399),
.Y(n1384) );
AO22XLTS U3012 ( .A0(n2428), .A1(d_ff2_X[5]), .B0(n2397), .B1(
d_ff3_sh_x_out[5]), .Y(n1383) );
AO22XLTS U3013 ( .A0(d_ff_Xn[4]), .A1(n2347), .B0(d_ff2_X[4]), .B1(n2440),
.Y(n1382) );
AO22XLTS U3014 ( .A0(n2428), .A1(d_ff2_X[4]), .B0(n2397), .B1(
d_ff3_sh_x_out[4]), .Y(n1381) );
OA22X1TS U3015 ( .A0(d_ff2_X[3]), .A1(n2416), .B0(d_ff_Xn[3]), .B1(n2399),
.Y(n1380) );
AO22XLTS U3016 ( .A0(n2444), .A1(d_ff2_X[3]), .B0(n2397), .B1(
d_ff3_sh_x_out[3]), .Y(n1379) );
OA22X1TS U3017 ( .A0(d_ff2_X[2]), .A1(n2416), .B0(d_ff_Xn[2]), .B1(n2399),
.Y(n1378) );
AO22XLTS U3018 ( .A0(n2444), .A1(d_ff2_X[2]), .B0(n2397), .B1(
d_ff3_sh_x_out[2]), .Y(n1377) );
OA22X1TS U3019 ( .A0(d_ff2_X[1]), .A1(n2346), .B0(d_ff_Xn[1]), .B1(n2399),
.Y(n1376) );
AO22XLTS U3020 ( .A0(n2444), .A1(d_ff2_X[1]), .B0(n2397), .B1(
d_ff3_sh_x_out[1]), .Y(n1375) );
AO22XLTS U3021 ( .A0(d_ff_Xn[0]), .A1(n2347), .B0(d_ff2_X[0]), .B1(n2412),
.Y(n1374) );
AO22XLTS U3022 ( .A0(n2444), .A1(d_ff2_X[0]), .B0(n2397), .B1(
d_ff3_sh_x_out[0]), .Y(n1373) );
OAI2BB2XLTS U3023 ( .B0(n2380), .B1(n2442), .A0N(n2380), .A1N(
result_add_subt[31]), .Y(n1371) );
NAND3BX1TS U3024 ( .AN(n2351), .B(n2350), .C(n2349), .Y(n2375) );
INVX4TS U3025 ( .A(n2377), .Y(n2378) );
AO22XLTS U3026 ( .A0(n2378), .A1(result_add_subt[31]), .B0(n2377), .B1(
d_ff_Zn[31]), .Y(n1370) );
AOI21X1TS U3027 ( .A0(add_subt_module_Add_Subt_result[20]), .A1(n2650), .B0(
add_subt_module_Add_Subt_result[22]), .Y(n2352) );
AOI31XLTS U3028 ( .A0(add_subt_module_Add_Subt_result[16]), .A1(n2354), .A2(
n2648), .B0(n2353), .Y(n2362) );
INVX2TS U3029 ( .A(n2355), .Y(n2357) );
NAND4BXLTS U3030 ( .AN(add_subt_module_Add_Subt_result[9]), .B(n2359), .C(
add_subt_module_Add_Subt_result[8]), .D(n2358), .Y(n2360) );
NAND4XLTS U3031 ( .A(n2363), .B(n2362), .C(n2361), .D(n2360), .Y(n2365) );
AO22XLTS U3032 ( .A0(n2366), .A1(n2365), .B0(n2364), .B1(
add_subt_module_LZA_output[0]), .Y(n1331) );
OA22X1TS U3033 ( .A0(n2104), .A1(result_add_subt[30]), .B0(
add_subt_module_exp_oper_result[7]), .B1(n2370), .Y(n1301) );
BUFX4TS U3034 ( .A(n2377), .Y(n2371) );
AO22XLTS U3035 ( .A0(n2378), .A1(result_add_subt[30]), .B0(n2371), .B1(
d_ff_Zn[30]), .Y(n1300) );
OAI2BB2XLTS U3036 ( .B0(n2379), .B1(n1556), .A0N(n2380), .A1N(
result_add_subt[30]), .Y(n1299) );
AO22XLTS U3037 ( .A0(n2446), .A1(result_add_subt[30]), .B0(n2368), .B1(
d_ff_Xn[30]), .Y(n1298) );
OA22X1TS U3038 ( .A0(n2104), .A1(result_add_subt[29]), .B0(
add_subt_module_exp_oper_result[6]), .B1(n2370), .Y(n1297) );
AO22XLTS U3039 ( .A0(n2378), .A1(result_add_subt[29]), .B0(n2371), .B1(
d_ff_Zn[29]), .Y(n1296) );
OAI2BB2XLTS U3040 ( .B0(n2372), .B1(n2417), .A0N(n2379), .A1N(
result_add_subt[29]), .Y(n1295) );
AO22XLTS U3041 ( .A0(n2446), .A1(result_add_subt[29]), .B0(n2368), .B1(
d_ff_Xn[29]), .Y(n1294) );
OA22X1TS U3042 ( .A0(n2104), .A1(result_add_subt[28]), .B0(
add_subt_module_exp_oper_result[5]), .B1(n2370), .Y(n1293) );
AO22XLTS U3043 ( .A0(n2378), .A1(result_add_subt[28]), .B0(n2371), .B1(
d_ff_Zn[28]), .Y(n1292) );
OAI2BB2XLTS U3044 ( .B0(n2380), .B1(n2415), .A0N(n2372), .A1N(
result_add_subt[28]), .Y(n1291) );
AO22XLTS U3045 ( .A0(n2446), .A1(result_add_subt[28]), .B0(n2368), .B1(
d_ff_Xn[28]), .Y(n1290) );
OA22X1TS U3046 ( .A0(n2104), .A1(result_add_subt[27]), .B0(
add_subt_module_exp_oper_result[4]), .B1(n2370), .Y(n1289) );
AO22XLTS U3047 ( .A0(n2378), .A1(result_add_subt[27]), .B0(n2371), .B1(
d_ff_Zn[27]), .Y(n1288) );
OAI2BB2XLTS U3048 ( .B0(n2379), .B1(n1557), .A0N(n2380), .A1N(
result_add_subt[27]), .Y(n1287) );
AO22XLTS U3049 ( .A0(n2446), .A1(result_add_subt[27]), .B0(n2368), .B1(
d_ff_Xn[27]), .Y(n1286) );
OA22X1TS U3050 ( .A0(n2104), .A1(result_add_subt[26]), .B0(
add_subt_module_exp_oper_result[3]), .B1(n2370), .Y(n1285) );
AO22XLTS U3051 ( .A0(n2378), .A1(result_add_subt[26]), .B0(n2371), .B1(
d_ff_Zn[26]), .Y(n1284) );
OAI2BB2XLTS U3052 ( .B0(n2379), .B1(n2413), .A0N(n2372), .A1N(
result_add_subt[26]), .Y(n1283) );
AO22XLTS U3053 ( .A0(n2446), .A1(result_add_subt[26]), .B0(n2368), .B1(
d_ff_Xn[26]), .Y(n1282) );
OA22X1TS U3054 ( .A0(n2104), .A1(result_add_subt[25]), .B0(
add_subt_module_exp_oper_result[2]), .B1(n2370), .Y(n1281) );
AO22XLTS U3055 ( .A0(n2378), .A1(result_add_subt[25]), .B0(n2371), .B1(
d_ff_Zn[25]), .Y(n1280) );
OAI2BB2XLTS U3056 ( .B0(n2372), .B1(n2411), .A0N(n2372), .A1N(
result_add_subt[25]), .Y(n1279) );
AO22XLTS U3057 ( .A0(n2446), .A1(result_add_subt[25]), .B0(n2368), .B1(
d_ff_Xn[25]), .Y(n1278) );
OA22X1TS U3058 ( .A0(n2104), .A1(result_add_subt[24]), .B0(
add_subt_module_exp_oper_result[1]), .B1(n2370), .Y(n1277) );
AO22XLTS U3059 ( .A0(n2378), .A1(result_add_subt[24]), .B0(n2371), .B1(
d_ff_Zn[24]), .Y(n1276) );
OAI2BB2XLTS U3060 ( .B0(n2372), .B1(n2410), .A0N(n2374), .A1N(
result_add_subt[24]), .Y(n1275) );
AO22XLTS U3061 ( .A0(n2446), .A1(result_add_subt[24]), .B0(n2368), .B1(
d_ff_Xn[24]), .Y(n1274) );
OA22X1TS U3062 ( .A0(n2104), .A1(result_add_subt[23]), .B0(
add_subt_module_exp_oper_result[0]), .B1(n2370), .Y(n1273) );
AO22XLTS U3063 ( .A0(n2378), .A1(result_add_subt[23]), .B0(n2371), .B1(
d_ff_Zn[23]), .Y(n1272) );
OAI2BB2XLTS U3064 ( .B0(n2372), .B1(n2409), .A0N(n2380), .A1N(
result_add_subt[23]), .Y(n1271) );
AO22XLTS U3065 ( .A0(n2446), .A1(result_add_subt[23]), .B0(n2368), .B1(
d_ff_Xn[23]), .Y(n1270) );
OAI2BB2XLTS U3066 ( .B0(n2651), .B1(n2367), .A0N(result_add_subt[22]), .A1N(
n2369), .Y(n1269) );
AO22XLTS U3067 ( .A0(n2378), .A1(result_add_subt[22]), .B0(n2371), .B1(
d_ff_Zn[22]), .Y(n1268) );
OAI2BB2XLTS U3068 ( .B0(n2380), .B1(n2408), .A0N(n2379), .A1N(
result_add_subt[22]), .Y(n1267) );
AO22XLTS U3069 ( .A0(n2446), .A1(result_add_subt[22]), .B0(n2368), .B1(
d_ff_Xn[22]), .Y(n1266) );
OAI2BB2XLTS U3070 ( .B0(n2645), .B1(n2367), .A0N(result_add_subt[21]), .A1N(
n2369), .Y(n1265) );
AO22XLTS U3071 ( .A0(n2378), .A1(result_add_subt[21]), .B0(n2371), .B1(
d_ff_Zn[21]), .Y(n1264) );
OAI2BB2XLTS U3072 ( .B0(n2379), .B1(n2407), .A0N(n2379), .A1N(
result_add_subt[21]), .Y(n1263) );
AO22XLTS U3073 ( .A0(n2446), .A1(result_add_subt[21]), .B0(n2368), .B1(
d_ff_Xn[21]), .Y(n1262) );
OAI2BB2XLTS U3074 ( .B0(n2646), .B1(n2367), .A0N(result_add_subt[20]), .A1N(
n2369), .Y(n1261) );
AO22XLTS U3075 ( .A0(n2378), .A1(result_add_subt[20]), .B0(n2371), .B1(
d_ff_Zn[20]), .Y(n1260) );
OAI2BB2XLTS U3076 ( .B0(n2372), .B1(n2406), .A0N(n2372), .A1N(
result_add_subt[20]), .Y(n1259) );
AO22XLTS U3077 ( .A0(n2446), .A1(result_add_subt[20]), .B0(n2368), .B1(
d_ff_Xn[20]), .Y(n1258) );
OAI2BB2XLTS U3078 ( .B0(n2640), .B1(n2370), .A0N(result_add_subt[19]), .A1N(
n2369), .Y(n1257) );
INVX4TS U3079 ( .A(n2377), .Y(n2376) );
AO22XLTS U3080 ( .A0(n2376), .A1(result_add_subt[19]), .B0(n2371), .B1(
d_ff_Zn[19]), .Y(n1256) );
OAI2BB2XLTS U3081 ( .B0(n2379), .B1(n2405), .A0N(n2372), .A1N(
result_add_subt[19]), .Y(n1255) );
AO22XLTS U3082 ( .A0(n2373), .A1(result_add_subt[19]), .B0(n2368), .B1(
d_ff_Xn[19]), .Y(n1254) );
OAI2BB2XLTS U3083 ( .B0(n2630), .B1(n2370), .A0N(result_add_subt[18]), .A1N(
n2369), .Y(n1253) );
AO22XLTS U3084 ( .A0(n2376), .A1(result_add_subt[18]), .B0(n2377), .B1(
d_ff_Zn[18]), .Y(n1252) );
OAI2BB2XLTS U3085 ( .B0(n2380), .B1(n2404), .A0N(n2380), .A1N(
result_add_subt[18]), .Y(n1251) );
AO22XLTS U3086 ( .A0(n2373), .A1(result_add_subt[18]), .B0(n2368), .B1(
d_ff_Xn[18]), .Y(n1250) );
OAI2BB2XLTS U3087 ( .B0(n2631), .B1(n2370), .A0N(result_add_subt[17]), .A1N(
n2369), .Y(n1249) );
AO22XLTS U3088 ( .A0(n2376), .A1(result_add_subt[17]), .B0(n2371), .B1(
d_ff_Zn[17]), .Y(n1248) );
OAI2BB2XLTS U3089 ( .B0(n2379), .B1(n2403), .A0N(n2379), .A1N(
result_add_subt[17]), .Y(n1247) );
AO22XLTS U3090 ( .A0(n2373), .A1(result_add_subt[17]), .B0(n2368), .B1(
d_ff_Xn[17]), .Y(n1246) );
OAI2BB2XLTS U3091 ( .B0(n2624), .B1(n2370), .A0N(result_add_subt[16]), .A1N(
n2369), .Y(n1245) );
AO22XLTS U3092 ( .A0(n2376), .A1(result_add_subt[16]), .B0(n2371), .B1(
d_ff_Zn[16]), .Y(n1244) );
OAI2BB2XLTS U3093 ( .B0(n2372), .B1(n2401), .A0N(n2380), .A1N(
result_add_subt[16]), .Y(n1243) );
AO22XLTS U3094 ( .A0(n2373), .A1(result_add_subt[16]), .B0(n2368), .B1(
d_ff_Xn[16]), .Y(n1242) );
OAI2BB2XLTS U3095 ( .B0(n2625), .B1(n2370), .A0N(result_add_subt[15]), .A1N(
n2369), .Y(n1241) );
AO22XLTS U3096 ( .A0(n2376), .A1(result_add_subt[15]), .B0(n2377), .B1(
d_ff_Zn[15]), .Y(n1240) );
OAI2BB2XLTS U3097 ( .B0(n2380), .B1(n2400), .A0N(n2372), .A1N(
result_add_subt[15]), .Y(n1239) );
AO22XLTS U3098 ( .A0(n2373), .A1(result_add_subt[15]), .B0(n2368), .B1(
d_ff_Xn[15]), .Y(n1238) );
OAI2BB2XLTS U3099 ( .B0(n2604), .B1(n2370), .A0N(result_add_subt[14]), .A1N(
n1552), .Y(n1237) );
AO22XLTS U3100 ( .A0(n2376), .A1(result_add_subt[14]), .B0(n2371), .B1(
d_ff_Zn[14]), .Y(n1236) );
OAI2BB2XLTS U3101 ( .B0(n2379), .B1(n2398), .A0N(n2380), .A1N(
result_add_subt[14]), .Y(n1235) );
AO22XLTS U3102 ( .A0(n2373), .A1(result_add_subt[14]), .B0(n2368), .B1(
d_ff_Xn[14]), .Y(n1234) );
OAI2BB2XLTS U3103 ( .B0(n2605), .B1(n2370), .A0N(result_add_subt[13]), .A1N(
n1552), .Y(n1233) );
AO22XLTS U3104 ( .A0(n2376), .A1(result_add_subt[13]), .B0(n2371), .B1(
d_ff_Zn[13]), .Y(n1232) );
OAI2BB2XLTS U3105 ( .B0(n2372), .B1(n2396), .A0N(n2379), .A1N(
result_add_subt[13]), .Y(n1231) );
AO22XLTS U3106 ( .A0(n2373), .A1(result_add_subt[13]), .B0(n2368), .B1(
d_ff_Xn[13]), .Y(n1230) );
OAI2BB2XLTS U3107 ( .B0(n2570), .B1(n2370), .A0N(result_add_subt[12]), .A1N(
n1552), .Y(n1229) );
AO22XLTS U3108 ( .A0(n2376), .A1(result_add_subt[12]), .B0(n2371), .B1(
d_ff_Zn[12]), .Y(n1228) );
OAI2BB2XLTS U3109 ( .B0(n2380), .B1(n2395), .A0N(n2380), .A1N(
result_add_subt[12]), .Y(n1227) );
AO22XLTS U3110 ( .A0(n2373), .A1(result_add_subt[12]), .B0(n2368), .B1(
d_ff_Xn[12]), .Y(n1226) );
OAI2BB2XLTS U3111 ( .B0(n2571), .B1(n2367), .A0N(result_add_subt[11]), .A1N(
n1552), .Y(n1225) );
AO22XLTS U3112 ( .A0(n2376), .A1(result_add_subt[11]), .B0(n2371), .B1(
d_ff_Zn[11]), .Y(n1224) );
OAI2BB2XLTS U3113 ( .B0(n2372), .B1(n2393), .A0N(n2372), .A1N(
result_add_subt[11]), .Y(n1223) );
AO22XLTS U3114 ( .A0(n2373), .A1(result_add_subt[11]), .B0(n2368), .B1(
d_ff_Xn[11]), .Y(n1222) );
OAI2BB2XLTS U3115 ( .B0(n2568), .B1(n2367), .A0N(result_add_subt[10]), .A1N(
n1552), .Y(n1221) );
AO22XLTS U3116 ( .A0(n2376), .A1(result_add_subt[10]), .B0(n2371), .B1(
d_ff_Zn[10]), .Y(n1220) );
OAI2BB2XLTS U3117 ( .B0(n2380), .B1(n2392), .A0N(n2379), .A1N(
result_add_subt[10]), .Y(n1219) );
AO22XLTS U3118 ( .A0(n2373), .A1(result_add_subt[10]), .B0(n2368), .B1(
d_ff_Xn[10]), .Y(n1218) );
OAI2BB2XLTS U3119 ( .B0(n2564), .B1(n2367), .A0N(result_add_subt[9]), .A1N(
n1552), .Y(n1217) );
AO22XLTS U3120 ( .A0(n2376), .A1(result_add_subt[9]), .B0(n2371), .B1(
d_ff_Zn[9]), .Y(n1216) );
OAI2BB2XLTS U3121 ( .B0(n2380), .B1(n2391), .A0N(n2379), .A1N(
result_add_subt[9]), .Y(n1215) );
AO22XLTS U3122 ( .A0(n2373), .A1(result_add_subt[9]), .B0(n2368), .B1(
d_ff_Xn[9]), .Y(n1214) );
OAI2BB2XLTS U3123 ( .B0(n2565), .B1(n2367), .A0N(result_add_subt[8]), .A1N(
n1552), .Y(n1213) );
AO22XLTS U3124 ( .A0(n2376), .A1(result_add_subt[8]), .B0(n2377), .B1(
d_ff_Zn[8]), .Y(n1212) );
OAI2BB2XLTS U3125 ( .B0(n2379), .B1(n2389), .A0N(n2379), .A1N(
result_add_subt[8]), .Y(n1211) );
AO22XLTS U3126 ( .A0(n2373), .A1(result_add_subt[8]), .B0(n2445), .B1(
d_ff_Xn[8]), .Y(n1210) );
OAI2BB2XLTS U3127 ( .B0(n2562), .B1(n2367), .A0N(result_add_subt[7]), .A1N(
n1552), .Y(n1209) );
AO22XLTS U3128 ( .A0(n2376), .A1(result_add_subt[7]), .B0(n2377), .B1(
d_ff_Zn[7]), .Y(n1208) );
OAI2BB2XLTS U3129 ( .B0(n2380), .B1(n2388), .A0N(n2372), .A1N(
result_add_subt[7]), .Y(n1207) );
AO22XLTS U3130 ( .A0(n2373), .A1(result_add_subt[7]), .B0(n2445), .B1(
d_ff_Xn[7]), .Y(n1206) );
OAI2BB2XLTS U3131 ( .B0(n2563), .B1(n2367), .A0N(result_add_subt[6]), .A1N(
n1552), .Y(n1205) );
AO22XLTS U3132 ( .A0(n2378), .A1(result_add_subt[6]), .B0(n2377), .B1(
d_ff_Zn[6]), .Y(n1204) );
OAI2BB2XLTS U3133 ( .B0(n2379), .B1(n2387), .A0N(n2380), .A1N(
result_add_subt[6]), .Y(n1203) );
AO22XLTS U3134 ( .A0(n2373), .A1(result_add_subt[6]), .B0(n2445), .B1(
d_ff_Xn[6]), .Y(n1202) );
OAI2BB2XLTS U3135 ( .B0(n2560), .B1(n2367), .A0N(result_add_subt[5]), .A1N(
n1552), .Y(n1201) );
AO22XLTS U3136 ( .A0(n2376), .A1(result_add_subt[5]), .B0(n2377), .B1(
d_ff_Zn[5]), .Y(n1200) );
OAI2BB2XLTS U3137 ( .B0(n2374), .B1(n2386), .A0N(n2379), .A1N(
result_add_subt[5]), .Y(n1199) );
AO22XLTS U3138 ( .A0(n2446), .A1(result_add_subt[5]), .B0(n2445), .B1(
d_ff_Xn[5]), .Y(n1198) );
OAI2BB2XLTS U3139 ( .B0(n2561), .B1(n2367), .A0N(result_add_subt[4]), .A1N(
n1552), .Y(n1197) );
AO22XLTS U3140 ( .A0(n2378), .A1(result_add_subt[4]), .B0(n2377), .B1(
d_ff_Zn[4]), .Y(n1196) );
OAI2BB2XLTS U3141 ( .B0(n2374), .B1(n2385), .A0N(n2372), .A1N(
result_add_subt[4]), .Y(n1195) );
AO22XLTS U3142 ( .A0(n2446), .A1(result_add_subt[4]), .B0(n2445), .B1(
d_ff_Xn[4]), .Y(n1194) );
OAI2BB2XLTS U3143 ( .B0(n2558), .B1(n2367), .A0N(result_add_subt[3]), .A1N(
n1552), .Y(n1193) );
AO22XLTS U3144 ( .A0(n2376), .A1(result_add_subt[3]), .B0(n2375), .B1(
d_ff_Zn[3]), .Y(n1192) );
OAI2BB2XLTS U3145 ( .B0(n2374), .B1(n2384), .A0N(n2380), .A1N(
result_add_subt[3]), .Y(n1191) );
AO22XLTS U3146 ( .A0(n2446), .A1(result_add_subt[3]), .B0(n2445), .B1(
d_ff_Xn[3]), .Y(n1190) );
OAI2BB2XLTS U3147 ( .B0(n2559), .B1(n2367), .A0N(result_add_subt[2]), .A1N(
n1552), .Y(n1189) );
AO22XLTS U3148 ( .A0(n2378), .A1(result_add_subt[2]), .B0(n2375), .B1(
d_ff_Zn[2]), .Y(n1188) );
OAI2BB2XLTS U3149 ( .B0(n2372), .B1(n2383), .A0N(n2379), .A1N(
result_add_subt[2]), .Y(n1187) );
AO22XLTS U3150 ( .A0(n2446), .A1(result_add_subt[2]), .B0(n2445), .B1(
d_ff_Xn[2]), .Y(n1186) );
OAI2BB2XLTS U3151 ( .B0(n2555), .B1(n2367), .A0N(result_add_subt[1]), .A1N(
n1552), .Y(n1185) );
AO22XLTS U3152 ( .A0(n2376), .A1(result_add_subt[1]), .B0(n2375), .B1(
d_ff_Zn[1]), .Y(n1184) );
OAI2BB2XLTS U3153 ( .B0(n2372), .B1(n2382), .A0N(n2372), .A1N(
result_add_subt[1]), .Y(n1183) );
AO22XLTS U3154 ( .A0(n2446), .A1(result_add_subt[1]), .B0(n2445), .B1(
d_ff_Xn[1]), .Y(n1182) );
OAI2BB2XLTS U3155 ( .B0(n2585), .B1(n2367), .A0N(result_add_subt[0]), .A1N(
n1552), .Y(n1181) );
AO22XLTS U3156 ( .A0(n2378), .A1(result_add_subt[0]), .B0(n2377), .B1(
d_ff_Zn[0]), .Y(n1180) );
AO22XLTS U3157 ( .A0(n2444), .A1(d_ff2_Z[31]), .B0(n2397), .B1(
d_ff3_sign_out), .Y(n1147) );
OAI2BB2XLTS U3158 ( .B0(n2380), .B1(n2381), .A0N(n2379), .A1N(
result_add_subt[0]), .Y(n1146) );
OAI2BB2XLTS U3159 ( .B0(n2381), .B1(n2399), .A0N(d_ff2_Y[0]), .A1N(n2440),
.Y(n1145) );
AO22XLTS U3160 ( .A0(n2444), .A1(d_ff2_Y[0]), .B0(n2397), .B1(
d_ff3_sh_y_out[0]), .Y(n1144) );
OAI2BB2XLTS U3161 ( .B0(n2382), .B1(n2399), .A0N(d_ff2_Y[1]), .A1N(n2440),
.Y(n1143) );
AO22XLTS U3162 ( .A0(n2444), .A1(d_ff2_Y[1]), .B0(n2397), .B1(
d_ff3_sh_y_out[1]), .Y(n1142) );
OAI2BB2XLTS U3163 ( .B0(n2383), .B1(n2399), .A0N(d_ff2_Y[2]), .A1N(n2440),
.Y(n1141) );
AO22XLTS U3164 ( .A0(n2444), .A1(d_ff2_Y[2]), .B0(n2397), .B1(
d_ff3_sh_y_out[2]), .Y(n1140) );
OAI2BB2XLTS U3165 ( .B0(n2384), .B1(n2399), .A0N(d_ff2_Y[3]), .A1N(n2440),
.Y(n1139) );
AO22XLTS U3166 ( .A0(n2444), .A1(d_ff2_Y[3]), .B0(n2394), .B1(
d_ff3_sh_y_out[3]), .Y(n1138) );
OAI2BB2XLTS U3167 ( .B0(n2385), .B1(n2441), .A0N(d_ff2_Y[4]), .A1N(n2440),
.Y(n1137) );
AO22XLTS U3168 ( .A0(n2444), .A1(d_ff2_Y[4]), .B0(n2443), .B1(
d_ff3_sh_y_out[4]), .Y(n1136) );
OAI2BB2XLTS U3169 ( .B0(n2386), .B1(n2441), .A0N(d_ff2_Y[5]), .A1N(n2440),
.Y(n1135) );
AO22XLTS U3170 ( .A0(n2444), .A1(d_ff2_Y[5]), .B0(n2397), .B1(
d_ff3_sh_y_out[5]), .Y(n1134) );
OAI2BB2XLTS U3171 ( .B0(n2387), .B1(n2441), .A0N(d_ff2_Y[6]), .A1N(n2440),
.Y(n1133) );
AO22XLTS U3172 ( .A0(n2444), .A1(d_ff2_Y[6]), .B0(n1558), .B1(
d_ff3_sh_y_out[6]), .Y(n1132) );
OAI2BB2XLTS U3173 ( .B0(n2388), .B1(n2441), .A0N(d_ff2_Y[7]), .A1N(n2440),
.Y(n1131) );
AO22XLTS U3174 ( .A0(n2444), .A1(d_ff2_Y[7]), .B0(n1558), .B1(
d_ff3_sh_y_out[7]), .Y(n1130) );
OAI2BB2XLTS U3175 ( .B0(n2389), .B1(n2441), .A0N(d_ff2_Y[8]), .A1N(n2412),
.Y(n1129) );
AO22XLTS U3176 ( .A0(n2444), .A1(d_ff2_Y[8]), .B0(n2390), .B1(
d_ff3_sh_y_out[8]), .Y(n1128) );
OAI2BB2XLTS U3177 ( .B0(n2391), .B1(n2441), .A0N(d_ff2_Y[9]), .A1N(n2412),
.Y(n1127) );
AO22XLTS U3178 ( .A0(n2444), .A1(d_ff2_Y[9]), .B0(n1558), .B1(
d_ff3_sh_y_out[9]), .Y(n1126) );
OAI2BB2XLTS U3179 ( .B0(n2392), .B1(n2441), .A0N(d_ff2_Y[10]), .A1N(n2412),
.Y(n1125) );
AO22XLTS U3180 ( .A0(n2444), .A1(d_ff2_Y[10]), .B0(n1558), .B1(
d_ff3_sh_y_out[10]), .Y(n1124) );
OAI2BB2XLTS U3181 ( .B0(n2393), .B1(n2441), .A0N(d_ff2_Y[11]), .A1N(n2412),
.Y(n1123) );
AO22XLTS U3182 ( .A0(n2444), .A1(d_ff2_Y[11]), .B0(n2394), .B1(
d_ff3_sh_y_out[11]), .Y(n1122) );
OAI2BB2XLTS U3183 ( .B0(n2395), .B1(n2399), .A0N(d_ff2_Y[12]), .A1N(n2412),
.Y(n1121) );
AO22XLTS U3184 ( .A0(n2444), .A1(d_ff2_Y[12]), .B0(n2443), .B1(
d_ff3_sh_y_out[12]), .Y(n1120) );
OAI2BB2XLTS U3185 ( .B0(n2396), .B1(n2399), .A0N(d_ff2_Y[13]), .A1N(n2402),
.Y(n1119) );
AO22XLTS U3186 ( .A0(n2444), .A1(d_ff2_Y[13]), .B0(n2397), .B1(
d_ff3_sh_y_out[13]), .Y(n1118) );
OAI2BB2XLTS U3187 ( .B0(n2398), .B1(n2399), .A0N(d_ff2_Y[14]), .A1N(n2412),
.Y(n1117) );
AO22XLTS U3188 ( .A0(n2444), .A1(d_ff2_Y[14]), .B0(n2425), .B1(
d_ff3_sh_y_out[14]), .Y(n1116) );
OAI2BB2XLTS U3189 ( .B0(n2400), .B1(n2399), .A0N(d_ff2_Y[15]), .A1N(n2402),
.Y(n1115) );
AO22XLTS U3190 ( .A0(n2434), .A1(d_ff2_Y[15]), .B0(n2425), .B1(
d_ff3_sh_y_out[15]), .Y(n1114) );
OAI2BB2XLTS U3191 ( .B0(n2401), .B1(n2441), .A0N(d_ff2_Y[16]), .A1N(n2402),
.Y(n1113) );
AO22XLTS U3192 ( .A0(n2444), .A1(d_ff2_Y[16]), .B0(n1558), .B1(
d_ff3_sh_y_out[16]), .Y(n1112) );
OAI2BB2XLTS U3193 ( .B0(n2403), .B1(n2441), .A0N(d_ff2_Y[17]), .A1N(n2402),
.Y(n1111) );
AO22XLTS U3194 ( .A0(n2444), .A1(d_ff2_Y[17]), .B0(n2425), .B1(
d_ff3_sh_y_out[17]), .Y(n1110) );
OAI2BB2XLTS U3195 ( .B0(n2404), .B1(n2441), .A0N(d_ff2_Y[18]), .A1N(n2412),
.Y(n1109) );
AO22XLTS U3196 ( .A0(n2439), .A1(d_ff2_Y[18]), .B0(n2425), .B1(
d_ff3_sh_y_out[18]), .Y(n1108) );
OAI2BB2XLTS U3197 ( .B0(n2405), .B1(n2441), .A0N(d_ff2_Y[19]), .A1N(n2412),
.Y(n1107) );
AO22XLTS U3198 ( .A0(n2439), .A1(d_ff2_Y[19]), .B0(n2425), .B1(
d_ff3_sh_y_out[19]), .Y(n1106) );
OAI2BB2XLTS U3199 ( .B0(n2406), .B1(n2441), .A0N(d_ff2_Y[20]), .A1N(n2412),
.Y(n1105) );
AO22XLTS U3200 ( .A0(n2439), .A1(d_ff2_Y[20]), .B0(n2425), .B1(
d_ff3_sh_y_out[20]), .Y(n1104) );
OAI2BB2XLTS U3201 ( .B0(n2407), .B1(n2441), .A0N(d_ff2_Y[21]), .A1N(n2412),
.Y(n1103) );
AO22XLTS U3202 ( .A0(n2439), .A1(d_ff2_Y[21]), .B0(n2390), .B1(
d_ff3_sh_y_out[21]), .Y(n1102) );
OAI2BB2XLTS U3203 ( .B0(n2408), .B1(n2441), .A0N(d_ff2_Y[22]), .A1N(n2412),
.Y(n1101) );
AO22XLTS U3204 ( .A0(n2439), .A1(d_ff2_Y[22]), .B0(n2425), .B1(
d_ff3_sh_y_out[22]), .Y(n1100) );
OAI22X1TS U3205 ( .A0(n2416), .A1(n2584), .B0(n2409), .B1(n2441), .Y(n1099)
);
OAI22X1TS U3206 ( .A0(n2416), .A1(n2632), .B0(n2410), .B1(n2441), .Y(n1098)
);
OAI2BB2XLTS U3207 ( .B0(n2411), .B1(n2441), .A0N(n1548), .A1N(n2412), .Y(
n1097) );
OAI2BB2XLTS U3208 ( .B0(n2413), .B1(n2441), .A0N(d_ff2_Y[26]), .A1N(n2412),
.Y(n1096) );
OAI22X1TS U3209 ( .A0(n2416), .A1(n2654), .B0(n2415), .B1(n2441), .Y(n1094)
);
OAI2BB2XLTS U3210 ( .B0(n2417), .B1(n2441), .A0N(n2440), .A1N(d_ff2_Y[29]),
.Y(n1093) );
AOI22X1TS U3211 ( .A0(cont_iter_out[1]), .A1(n2632), .B0(d_ff2_Y[24]), .B1(
n2566), .Y(n2419) );
XNOR2X1TS U3212 ( .A(n2422), .B(n2419), .Y(n2420) );
AO22XLTS U3213 ( .A0(n2439), .A1(n2420), .B0(n2425), .B1(d_ff3_sh_y_out[24]),
.Y(n1090) );
NAND2X1TS U3214 ( .A(d_ff2_Y[24]), .B(n2566), .Y(n2421) );
AOI22X1TS U3215 ( .A0(cont_iter_out[1]), .A1(n2632), .B0(n2422), .B1(n2421),
.Y(n2424) );
AO22XLTS U3216 ( .A0(n2439), .A1(n2423), .B0(n2425), .B1(d_ff3_sh_y_out[25]),
.Y(n1089) );
CMPR32X2TS U3217 ( .A(n1548), .B(n1536), .C(n2424), .CO(n2427), .S(n2423) );
AO22XLTS U3218 ( .A0(n2439), .A1(n2426), .B0(n2425), .B1(d_ff3_sh_y_out[26]),
.Y(n1088) );
NOR2X1TS U3219 ( .A(n1553), .B(n2430), .Y(n2431) );
AOI21X1TS U3220 ( .A0(n2430), .A1(n1553), .B0(n2431), .Y(n2429) );
AOI2BB2XLTS U3221 ( .B0(n2436), .B1(n2429), .A0N(d_ff3_sh_y_out[27]), .A1N(
n2428), .Y(n1087) );
OR3X1TS U3222 ( .A(n2430), .B(d_ff2_Y[28]), .C(n1553), .Y(n2433) );
OAI21XLTS U3223 ( .A0(n2431), .A1(n2654), .B0(n2433), .Y(n2432) );
AO22XLTS U3224 ( .A0(n2439), .A1(n2432), .B0(n1558), .B1(d_ff3_sh_y_out[28]),
.Y(n1086) );
NOR2X1TS U3225 ( .A(d_ff2_Y[29]), .B(n2433), .Y(n2437) );
AOI21X1TS U3226 ( .A0(d_ff2_Y[29]), .A1(n2433), .B0(n2437), .Y(n2435) );
AOI2BB2XLTS U3227 ( .B0(n2436), .B1(n2435), .A0N(d_ff3_sh_y_out[29]), .A1N(
n2434), .Y(n1085) );
XOR2XLTS U3228 ( .A(d_ff2_Y[30]), .B(n2437), .Y(n2438) );
AO22XLTS U3229 ( .A0(n2439), .A1(n2438), .B0(n2390), .B1(d_ff3_sh_y_out[30]),
.Y(n1084) );
OAI2BB2XLTS U3230 ( .B0(n2442), .B1(n2441), .A0N(d_ff2_Y[31]), .A1N(n2440),
.Y(n1083) );
AO22XLTS U3231 ( .A0(n2444), .A1(d_ff2_Y[31]), .B0(n2443), .B1(
d_ff3_sh_y_out[31]), .Y(n1082) );
AO22XLTS U3232 ( .A0(n2446), .A1(result_add_subt[0]), .B0(n2445), .B1(
d_ff_Xn[0]), .Y(n1081) );
INVX4TS U3233 ( .A(n2449), .Y(n2450) );
CLKBUFX3TS U3234 ( .A(n2449), .Y(n2452) );
AO22XLTS U3235 ( .A0(n2450), .A1(sign_inv_out[0]), .B0(n2452), .B1(
data_output[0]), .Y(n1079) );
AO22XLTS U3236 ( .A0(n2450), .A1(sign_inv_out[1]), .B0(n2449), .B1(
data_output[1]), .Y(n1077) );
AO22XLTS U3237 ( .A0(n2450), .A1(sign_inv_out[2]), .B0(n2449), .B1(
data_output[2]), .Y(n1075) );
AO22XLTS U3238 ( .A0(n2450), .A1(sign_inv_out[3]), .B0(n2449), .B1(
data_output[3]), .Y(n1073) );
AO22XLTS U3239 ( .A0(n2450), .A1(sign_inv_out[4]), .B0(n2449), .B1(
data_output[4]), .Y(n1071) );
AO22XLTS U3240 ( .A0(n2450), .A1(sign_inv_out[5]), .B0(n2449), .B1(
data_output[5]), .Y(n1069) );
AO22XLTS U3241 ( .A0(n2450), .A1(sign_inv_out[6]), .B0(n2449), .B1(
data_output[6]), .Y(n1067) );
AO22XLTS U3242 ( .A0(n2450), .A1(sign_inv_out[7]), .B0(n2449), .B1(
data_output[7]), .Y(n1065) );
AO22XLTS U3243 ( .A0(n2450), .A1(sign_inv_out[8]), .B0(n2449), .B1(
data_output[8]), .Y(n1063) );
AO22XLTS U3244 ( .A0(n2450), .A1(sign_inv_out[9]), .B0(n2449), .B1(
data_output[9]), .Y(n1061) );
AO22XLTS U3245 ( .A0(n2450), .A1(sign_inv_out[10]), .B0(n2449), .B1(
data_output[10]), .Y(n1059) );
AO22XLTS U3246 ( .A0(n2450), .A1(sign_inv_out[11]), .B0(n2449), .B1(
data_output[11]), .Y(n1057) );
AO22XLTS U3247 ( .A0(n2454), .A1(sign_inv_out[12]), .B0(n2449), .B1(
data_output[12]), .Y(n1055) );
AO22XLTS U3248 ( .A0(n2454), .A1(sign_inv_out[13]), .B0(n2449), .B1(
data_output[13]), .Y(n1053) );
AO22XLTS U3249 ( .A0(n2454), .A1(sign_inv_out[14]), .B0(n2449), .B1(
data_output[14]), .Y(n1051) );
AO22XLTS U3250 ( .A0(n2454), .A1(sign_inv_out[15]), .B0(n2449), .B1(
data_output[15]), .Y(n1049) );
AO22XLTS U3251 ( .A0(n2454), .A1(sign_inv_out[16]), .B0(n2449), .B1(
data_output[16]), .Y(n1047) );
AO22XLTS U3252 ( .A0(n2454), .A1(sign_inv_out[17]), .B0(n2449), .B1(
data_output[17]), .Y(n1045) );
AO22XLTS U3253 ( .A0(n2454), .A1(sign_inv_out[18]), .B0(n2449), .B1(
data_output[18]), .Y(n1043) );
AO22XLTS U3254 ( .A0(n2454), .A1(sign_inv_out[19]), .B0(n2449), .B1(
data_output[19]), .Y(n1041) );
AO22XLTS U3255 ( .A0(n2454), .A1(sign_inv_out[20]), .B0(n2449), .B1(
data_output[20]), .Y(n1039) );
AO22XLTS U3256 ( .A0(n2454), .A1(sign_inv_out[21]), .B0(n2449), .B1(
data_output[21]), .Y(n1037) );
AO22XLTS U3257 ( .A0(n2454), .A1(sign_inv_out[22]), .B0(n2449), .B1(
data_output[22]), .Y(n1035) );
AO22XLTS U3258 ( .A0(n2454), .A1(sign_inv_out[23]), .B0(n2452), .B1(
data_output[23]), .Y(n1033) );
AO22XLTS U3259 ( .A0(n2450), .A1(sign_inv_out[24]), .B0(n2452), .B1(
data_output[24]), .Y(n1031) );
AO22XLTS U3260 ( .A0(n2450), .A1(sign_inv_out[25]), .B0(n2452), .B1(
data_output[25]), .Y(n1029) );
AO22XLTS U3261 ( .A0(n2450), .A1(sign_inv_out[26]), .B0(n2452), .B1(
data_output[26]), .Y(n1027) );
AO22XLTS U3262 ( .A0(n2450), .A1(sign_inv_out[27]), .B0(n2452), .B1(
data_output[27]), .Y(n1025) );
AO22XLTS U3263 ( .A0(n2450), .A1(sign_inv_out[28]), .B0(n2452), .B1(
data_output[28]), .Y(n1023) );
AO22XLTS U3264 ( .A0(n2450), .A1(sign_inv_out[29]), .B0(n2452), .B1(
data_output[29]), .Y(n1021) );
AO22XLTS U3265 ( .A0(n2454), .A1(sign_inv_out[30]), .B0(n2452), .B1(
data_output[30]), .Y(n1019) );
OAI33X1TS U3266 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n2582), .B0(n2552), .B1(n2649), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n2451) );
XOR2XLTS U3267 ( .A(data_output2_31_), .B(n2451), .Y(n2453) );
AO22XLTS U3268 ( .A0(n2454), .A1(n2453), .B0(n2452), .B1(data_output[31]),
.Y(n1016) );
AOI22X1TS U3269 ( .A0(add_subt_module_intDY[0]), .A1(n2520), .B0(n2539),
.B1(d_ff3_sh_y_out[0]), .Y(n2456) );
AOI22X1TS U3270 ( .A0(d_ff3_LUT_out[0]), .A1(n2540), .B0(n2474), .B1(
d_ff3_sh_x_out[0]), .Y(n2455) );
NAND2X1TS U3271 ( .A(n2456), .B(n2455), .Y(n1013) );
AOI22X1TS U3272 ( .A0(add_subt_module_intDY[26]), .A1(n2520), .B0(n2543),
.B1(d_ff3_sh_y_out[26]), .Y(n2458) );
AOI22X1TS U3273 ( .A0(d_ff3_LUT_out[26]), .A1(n2546), .B0(n2487), .B1(
d_ff3_sh_x_out[26]), .Y(n2457) );
NAND2X1TS U3274 ( .A(n2458), .B(n2457), .Y(n1008) );
AOI22X1TS U3275 ( .A0(add_subt_module_intDY[25]), .A1(n2520), .B0(n2473),
.B1(d_ff3_sh_y_out[25]), .Y(n2460) );
AOI22X1TS U3276 ( .A0(n2540), .A1(d_ff3_LUT_out[25]), .B0(n2487), .B1(
d_ff3_sh_x_out[25]), .Y(n2459) );
NAND2X1TS U3277 ( .A(n2460), .B(n2459), .Y(n1007) );
AOI22X1TS U3278 ( .A0(add_subt_module_intDY[24]), .A1(n2520), .B0(n2543),
.B1(d_ff3_sh_y_out[24]), .Y(n2462) );
AOI22X1TS U3279 ( .A0(d_ff3_LUT_out[24]), .A1(n2546), .B0(n2487), .B1(
d_ff3_sh_x_out[24]), .Y(n2461) );
NAND2X1TS U3280 ( .A(n2462), .B(n2461), .Y(n1006) );
AOI22X1TS U3281 ( .A0(add_subt_module_intDY[23]), .A1(n2520), .B0(n2473),
.B1(d_ff3_sh_y_out[23]), .Y(n2464) );
AOI22X1TS U3282 ( .A0(n2546), .A1(d_ff3_LUT_out[23]), .B0(n2487), .B1(
d_ff3_sh_x_out[23]), .Y(n2463) );
NAND2X1TS U3283 ( .A(n2464), .B(n2463), .Y(n1005) );
AOI22X1TS U3284 ( .A0(add_subt_module_intDX[31]), .A1(n2520), .B0(n2473),
.B1(d_ff2_X[31]), .Y(n2466) );
AOI22X1TS U3285 ( .A0(n2540), .A1(d_ff2_Z[31]), .B0(n2487), .B1(d_ff2_Y[31]),
.Y(n2465) );
NAND2X1TS U3286 ( .A(n2466), .B(n2465), .Y(n1003) );
AOI22X1TS U3287 ( .A0(add_subt_module_intDX[30]), .A1(n2520), .B0(
d_ff2_X[30]), .B1(n2473), .Y(n2468) );
AOI22X1TS U3288 ( .A0(d_ff2_Y[30]), .A1(n2474), .B0(n2546), .B1(d_ff2_Z[30]),
.Y(n2467) );
NAND2X1TS U3289 ( .A(n2468), .B(n2467), .Y(n1000) );
AOI22X1TS U3290 ( .A0(add_subt_module_intDX[29]), .A1(n2544), .B0(
d_ff2_X[29]), .B1(n2473), .Y(n2470) );
AOI22X1TS U3291 ( .A0(d_ff2_Y[29]), .A1(n2474), .B0(n2546), .B1(d_ff2_Z[29]),
.Y(n2469) );
NAND2X1TS U3292 ( .A(n2470), .B(n2469), .Y(n997) );
AOI22X1TS U3293 ( .A0(add_subt_module_intDX[28]), .A1(n2520), .B0(
d_ff2_X[28]), .B1(n2473), .Y(n2472) );
AOI22X1TS U3294 ( .A0(d_ff2_Y[28]), .A1(n2474), .B0(n2546), .B1(d_ff2_Z[28]),
.Y(n2471) );
NAND2X1TS U3295 ( .A(n2472), .B(n2471), .Y(n994) );
AOI22X1TS U3296 ( .A0(add_subt_module_intDX[27]), .A1(n2520), .B0(n1554),
.B1(n2473), .Y(n2476) );
AOI22X1TS U3297 ( .A0(n1553), .A1(n2474), .B0(n2546), .B1(d_ff2_Z[27]), .Y(
n2475) );
NAND2X1TS U3298 ( .A(n2476), .B(n2475), .Y(n991) );
AOI22X1TS U3299 ( .A0(add_subt_module_intDX[26]), .A1(n2544), .B0(n2543),
.B1(d_ff2_X[26]), .Y(n2478) );
AOI22X1TS U3300 ( .A0(n2540), .A1(d_ff2_Z[26]), .B0(n2487), .B1(d_ff2_Y[26]),
.Y(n2477) );
NAND2X1TS U3301 ( .A(n2478), .B(n2477), .Y(n988) );
AOI22X1TS U3302 ( .A0(add_subt_module_intDX[25]), .A1(n2544), .B0(n2543),
.B1(n1549), .Y(n2480) );
AOI22X1TS U3303 ( .A0(n2546), .A1(d_ff2_Z[25]), .B0(n2487), .B1(n1548), .Y(
n2479) );
NAND2X1TS U3304 ( .A(n2480), .B(n2479), .Y(n985) );
AOI22X1TS U3305 ( .A0(add_subt_module_intDX[24]), .A1(n2520), .B0(n2543),
.B1(d_ff2_X[24]), .Y(n2482) );
AOI22X1TS U3306 ( .A0(n2540), .A1(d_ff2_Z[24]), .B0(n2487), .B1(d_ff2_Y[24]),
.Y(n2481) );
NAND2X1TS U3307 ( .A(n2482), .B(n2481), .Y(n982) );
AOI22X1TS U3308 ( .A0(add_subt_module_intDX[23]), .A1(n2544), .B0(n2543),
.B1(d_ff2_X[23]), .Y(n2484) );
AOI22X1TS U3309 ( .A0(n2540), .A1(d_ff2_Z[23]), .B0(n2487), .B1(d_ff2_Y[23]),
.Y(n2483) );
NAND2X1TS U3310 ( .A(n2484), .B(n2483), .Y(n979) );
AOI22X1TS U3311 ( .A0(add_subt_module_intDX[0]), .A1(n2520), .B0(n2543),
.B1(d_ff2_X[0]), .Y(n2486) );
AOI22X1TS U3312 ( .A0(n2540), .A1(d_ff2_Z[0]), .B0(n2487), .B1(d_ff2_Y[0]),
.Y(n2485) );
NAND2X1TS U3313 ( .A(n2486), .B(n2485), .Y(n976) );
AOI22X1TS U3314 ( .A0(add_subt_module_intDX[22]), .A1(n2520), .B0(n2543),
.B1(d_ff2_X[22]), .Y(n2489) );
AOI22X1TS U3315 ( .A0(n2546), .A1(d_ff2_Z[22]), .B0(n2487), .B1(d_ff2_Y[22]),
.Y(n2488) );
NAND2X1TS U3316 ( .A(n2489), .B(n2488), .Y(n974) );
AOI22X1TS U3317 ( .A0(add_subt_module_intDY[22]), .A1(n2544), .B0(n2543),
.B1(d_ff3_sh_y_out[22]), .Y(n2491) );
AOI22X1TS U3318 ( .A0(n2546), .A1(d_ff3_LUT_out[22]), .B0(n2535), .B1(
d_ff3_sh_x_out[22]), .Y(n2490) );
NAND2X1TS U3319 ( .A(n2491), .B(n2490), .Y(n973) );
AOI22X1TS U3320 ( .A0(add_subt_module_intDX[6]), .A1(n2544), .B0(n2543),
.B1(d_ff2_X[6]), .Y(n2493) );
AOI22X1TS U3321 ( .A0(n2546), .A1(d_ff2_Z[6]), .B0(n2535), .B1(d_ff2_Y[6]),
.Y(n2492) );
NAND2X1TS U3322 ( .A(n2493), .B(n2492), .Y(n971) );
AOI22X1TS U3323 ( .A0(add_subt_module_intDY[6]), .A1(n2520), .B0(n2543),
.B1(d_ff3_sh_y_out[6]), .Y(n2495) );
AOI22X1TS U3324 ( .A0(d_ff3_LUT_out[6]), .A1(n2540), .B0(n2535), .B1(
d_ff3_sh_x_out[6]), .Y(n2494) );
NAND2X1TS U3325 ( .A(n2495), .B(n2494), .Y(n970) );
AOI22X1TS U3326 ( .A0(add_subt_module_intDX[3]), .A1(n2520), .B0(n2543),
.B1(d_ff2_X[3]), .Y(n2497) );
AOI22X1TS U3327 ( .A0(n2546), .A1(d_ff2_Z[3]), .B0(n2535), .B1(d_ff2_Y[3]),
.Y(n2496) );
NAND2X1TS U3328 ( .A(n2497), .B(n2496), .Y(n968) );
AOI22X1TS U3329 ( .A0(add_subt_module_intDY[3]), .A1(n2544), .B0(n2543),
.B1(d_ff3_sh_y_out[3]), .Y(n2499) );
AOI22X1TS U3330 ( .A0(n2546), .A1(d_ff3_LUT_out[3]), .B0(n2535), .B1(
d_ff3_sh_x_out[3]), .Y(n2498) );
NAND2X1TS U3331 ( .A(n2499), .B(n2498), .Y(n967) );
AOI22X1TS U3332 ( .A0(add_subt_module_intDX[19]), .A1(n2520), .B0(n2539),
.B1(d_ff2_X[19]), .Y(n2501) );
AOI22X1TS U3333 ( .A0(n2546), .A1(d_ff2_Z[19]), .B0(n2535), .B1(d_ff2_Y[19]),
.Y(n2500) );
NAND2X1TS U3334 ( .A(n2501), .B(n2500), .Y(n965) );
AOI22X1TS U3335 ( .A0(add_subt_module_intDY[19]), .A1(n2544), .B0(n2532),
.B1(d_ff3_sh_y_out[19]), .Y(n2503) );
AOI22X1TS U3336 ( .A0(n2546), .A1(d_ff3_LUT_out[19]), .B0(n2535), .B1(
d_ff3_sh_x_out[19]), .Y(n2502) );
NAND2X1TS U3337 ( .A(n2503), .B(n2502), .Y(n964) );
AOI22X1TS U3338 ( .A0(add_subt_module_intDX[2]), .A1(n2520), .B0(n2532),
.B1(d_ff2_X[2]), .Y(n2505) );
AOI22X1TS U3339 ( .A0(n2546), .A1(d_ff2_Z[2]), .B0(n2535), .B1(d_ff2_Y[2]),
.Y(n2504) );
NAND2X1TS U3340 ( .A(n2505), .B(n2504), .Y(n961) );
AOI22X1TS U3341 ( .A0(add_subt_module_intDY[2]), .A1(n2544), .B0(n2539),
.B1(d_ff3_sh_y_out[2]), .Y(n2507) );
AOI22X1TS U3342 ( .A0(n2546), .A1(d_ff3_LUT_out[2]), .B0(n2535), .B1(
d_ff3_sh_x_out[2]), .Y(n2506) );
NAND2X1TS U3343 ( .A(n2507), .B(n2506), .Y(n960) );
AOI22X1TS U3344 ( .A0(add_subt_module_intDX[21]), .A1(n2520), .B0(n2539),
.B1(d_ff2_X[21]), .Y(n2509) );
AOI22X1TS U3345 ( .A0(n2546), .A1(d_ff2_Z[21]), .B0(n2535), .B1(d_ff2_Y[21]),
.Y(n2508) );
NAND2X1TS U3346 ( .A(n2509), .B(n2508), .Y(n958) );
AOI22X1TS U3347 ( .A0(add_subt_module_intDY[21]), .A1(n2544), .B0(n2539),
.B1(d_ff3_sh_y_out[21]), .Y(n2511) );
AOI22X1TS U3348 ( .A0(n2546), .A1(d_ff3_LUT_out[21]), .B0(n2535), .B1(
d_ff3_sh_x_out[21]), .Y(n2510) );
NAND2X1TS U3349 ( .A(n2511), .B(n2510), .Y(n957) );
AOI22X1TS U3350 ( .A0(add_subt_module_intDX[18]), .A1(n2520), .B0(n2539),
.B1(d_ff2_X[18]), .Y(n2513) );
AOI22X1TS U3351 ( .A0(n2546), .A1(d_ff2_Z[18]), .B0(n2535), .B1(d_ff2_Y[18]),
.Y(n2512) );
NAND2X1TS U3352 ( .A(n2513), .B(n2512), .Y(n955) );
AOI22X1TS U3353 ( .A0(add_subt_module_intDY[18]), .A1(n2544), .B0(n2532),
.B1(d_ff3_sh_y_out[18]), .Y(n2515) );
AOI22X1TS U3354 ( .A0(d_ff3_LUT_out[18]), .A1(n2540), .B0(n2535), .B1(
d_ff3_sh_x_out[18]), .Y(n2514) );
NAND2X1TS U3355 ( .A(n2515), .B(n2514), .Y(n954) );
AOI22X1TS U3356 ( .A0(add_subt_module_intDX[15]), .A1(n2520), .B0(n2532),
.B1(d_ff2_X[15]), .Y(n2517) );
AOI22X1TS U3357 ( .A0(n2536), .A1(d_ff2_Z[15]), .B0(n2545), .B1(d_ff2_Y[15]),
.Y(n2516) );
NAND2X1TS U3358 ( .A(n2517), .B(n2516), .Y(n951) );
AOI22X1TS U3359 ( .A0(add_subt_module_intDY[15]), .A1(n2544), .B0(n2543),
.B1(d_ff3_sh_y_out[15]), .Y(n2519) );
AOI22X1TS U3360 ( .A0(n2540), .A1(d_ff3_LUT_out[15]), .B0(n2545), .B1(
d_ff3_sh_x_out[15]), .Y(n2518) );
NAND2X1TS U3361 ( .A(n2519), .B(n2518), .Y(n950) );
AOI22X1TS U3362 ( .A0(add_subt_module_intDX[8]), .A1(n2520), .B0(n2532),
.B1(d_ff2_X[8]), .Y(n2522) );
AOI22X1TS U3363 ( .A0(n2546), .A1(d_ff2_Z[8]), .B0(n2545), .B1(d_ff2_Y[8]),
.Y(n2521) );
NAND2X1TS U3364 ( .A(n2522), .B(n2521), .Y(n948) );
AOI22X1TS U3365 ( .A0(add_subt_module_intDY[8]), .A1(n2529), .B0(n2532),
.B1(d_ff3_sh_y_out[8]), .Y(n2524) );
AOI22X1TS U3366 ( .A0(n2540), .A1(d_ff3_LUT_out[8]), .B0(n2545), .B1(
d_ff3_sh_x_out[8]), .Y(n2523) );
NAND2X1TS U3367 ( .A(n2524), .B(n2523), .Y(n947) );
AOI22X1TS U3368 ( .A0(add_subt_module_intDY[13]), .A1(n2529), .B0(n2532),
.B1(d_ff3_sh_y_out[13]), .Y(n2526) );
AOI22X1TS U3369 ( .A0(d_ff3_LUT_out[13]), .A1(n2540), .B0(n2545), .B1(
d_ff3_sh_x_out[13]), .Y(n2525) );
NAND2X1TS U3370 ( .A(n2526), .B(n2525), .Y(n937) );
AOI22X1TS U3371 ( .A0(add_subt_module_intDY[5]), .A1(n2529), .B0(n2532),
.B1(d_ff3_sh_y_out[5]), .Y(n2528) );
AOI22X1TS U3372 ( .A0(d_ff3_LUT_out[5]), .A1(n2540), .B0(n2545), .B1(
d_ff3_sh_x_out[5]), .Y(n2527) );
NAND2X1TS U3373 ( .A(n2528), .B(n2527), .Y(n933) );
AOI22X1TS U3374 ( .A0(add_subt_module_intDY[4]), .A1(n2529), .B0(n2532),
.B1(d_ff3_sh_y_out[4]), .Y(n2531) );
AOI22X1TS U3375 ( .A0(d_ff3_LUT_out[4]), .A1(n2540), .B0(n2545), .B1(
d_ff3_sh_x_out[4]), .Y(n2530) );
NAND2X1TS U3376 ( .A(n2531), .B(n2530), .Y(n926) );
AOI22X1TS U3377 ( .A0(add_subt_module_intDX[16]), .A1(n2529), .B0(n2532),
.B1(d_ff2_X[16]), .Y(n2534) );
AOI22X1TS U3378 ( .A0(n2536), .A1(d_ff2_Z[16]), .B0(n2535), .B1(d_ff2_Y[16]),
.Y(n2533) );
NAND2X1TS U3379 ( .A(n2534), .B(n2533), .Y(n924) );
AOI22X1TS U3380 ( .A0(add_subt_module_intDX[10]), .A1(n2520), .B0(n2539),
.B1(d_ff2_X[10]), .Y(n2538) );
AOI22X1TS U3381 ( .A0(n2536), .A1(d_ff2_Z[10]), .B0(n2535), .B1(d_ff2_Y[10]),
.Y(n2537) );
NAND2X1TS U3382 ( .A(n2538), .B(n2537), .Y(n920) );
AOI22X1TS U3383 ( .A0(add_subt_module_intDY[14]), .A1(n2529), .B0(n2539),
.B1(d_ff3_sh_y_out[14]), .Y(n2542) );
AOI22X1TS U3384 ( .A0(d_ff3_LUT_out[14]), .A1(n2540), .B0(n2545), .B1(
d_ff3_sh_x_out[14]), .Y(n2541) );
NAND2X1TS U3385 ( .A(n2542), .B(n2541), .Y(n916) );
AOI22X1TS U3386 ( .A0(add_subt_module_intDY[9]), .A1(n2544), .B0(n2543),
.B1(d_ff3_sh_y_out[9]), .Y(n2548) );
AOI22X1TS U3387 ( .A0(n2546), .A1(d_ff3_LUT_out[9]), .B0(n2545), .B1(
d_ff3_sh_x_out[9]), .Y(n2547) );
NAND2X1TS U3388 ( .A(n2548), .B(n2547), .Y(n902) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk40.tcl_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD3_TB_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD3_TB_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlygate4sd3.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__dlygate4sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD3_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand4b (
Y ,
A_N,
B ,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, D, C, B, not0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__AND3B_FUNCTIONAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3B_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_0_V
`define SKY130_FD_SC_LP__NOR2_0_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_0 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_0 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_0_V
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: rx_link
*
*/
`default_nettype none
module rx_link #(
parameter LOG_FPW = 2,
parameter FPW = 4,
parameter DWIDTH = FPW*128,
parameter LOG_NUM_LANES = 3,
parameter NUM_LANES = 2**LOG_NUM_LANES,
parameter HMC_PTR_SIZE = 8,
parameter HMC_RF_RWIDTH = 64,
//Configure functionality
parameter LOG_MAX_RTC = 8,
parameter CTRL_LANE_POLARITY = 1,
parameter CTRL_LANE_REVERSAL = 1,
parameter BITSLIP_SHIFT_RIGHT= 1
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
input wire res_n,
//----------------------------------
//----TO HMC PHY
//----------------------------------
input wire [DWIDTH-1:0] phy_scrambled_data_in,
output reg [NUM_LANES-1:0] init_bit_slip, //bit slip per lane
//----------------------------------
//----TO RX HTAX FIFO
//----------------------------------
output reg [DWIDTH-1:0] d_out_fifo_data,
input wire d_out_fifo_full,
input wire d_out_fifo_a_full,
output reg d_out_fifo_shift_in,
output reg [4*FPW-1:0] d_out_fifo_ctrl,
//----------------------------------
//----TO TX Block
//----------------------------------
output reg tx_link_retry,
output reg tx_error_abort_mode,
output reg tx_error_abort_mode_cleared,
output reg [7:0] tx_hmc_frp,
output reg [7:0] tx_rrp,
output reg [7:0] tx_returned_tokens,
output reg [LOG_FPW:0] tx_hmc_tokens_to_return,
output reg [LOG_FPW:0] tx_hmc_poisoned_tokens_to_return,
//----------------------------------
//----RF
//----------------------------------
//Monitoring 1-cycle set to increment
output reg [HMC_RF_RWIDTH-1:0] rf_cnt_poisoned,
output reg [HMC_RF_RWIDTH-1:0] rf_cnt_rsp,
//Status
output reg [1:0] rf_link_status,
output reg [2:0] rf_hmc_init_status,
input wire rf_tx_sends_ts1,
input wire rf_hmc_sleep,
//Init Status
output wire [NUM_LANES-1:0] rf_descrambler_part_aligned,
output wire [NUM_LANES-1:0] rf_descrambler_aligned,
output wire rf_all_descramblers_aligned,
//Control
input wire [5:0] rf_bit_slip_time,
input wire rf_hmc_init_cont_set,
output reg [NUM_LANES-1:0] rf_lane_polarity,
input wire rf_scrambler_disable,
output reg rf_lane_reversal_detected,
output reg [NUM_LANES-1:0] rf_descramblers_locked,
input wire [4:0] rf_irtry_received_threshold
);
`include "hmc_field_functions.h"
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//------------------------------------------------------------------------------------Some general things
//Link state
localparam HMC_DOWN = 3'b000;
localparam HMC_NULL = 3'b001;
localparam HMC_TS1 = 3'b010;
localparam HMC_UP = 3'b100;
//Commands
localparam CMD_IRTRY = 3'b011;
localparam CMD_FLOW = 3'b000;
localparam CMD_RSP = 3'b111;
localparam CMD_RSP_ERROR = 6'b111110;
//Other helpful defines
localparam WIDTH_PER_LANE = (DWIDTH/NUM_LANES);
//16 bits is a ts1, so the init seq number is incremented according to the lane size
localparam INIT_SEQ_INC_PER_CYCLE = WIDTH_PER_LANE/16;
//MISC
integer i_f; //counts to FPW
integer i_l; //counts to NUM_LANES
integer i_c; //counts to CYCLES_TO_COMPLETE_FULL_PACKET
genvar f; //Counts to FPW
genvar n; //Counts to NUM_LANES
genvar w; //Counts to WIDTH_PER_LANE
//------------------------------------------------------------------------------------DESCRAMBLER AND DATA ORDERING
reg [NUM_LANES-1:0] init_descrambler_part_aligned;
reg [NUM_LANES-1:0] init_descrambler_aligned;
assign rf_descrambler_part_aligned = init_descrambler_part_aligned;
assign rf_descrambler_aligned = init_descrambler_aligned;
//DATA and REORDERING
reg [WIDTH_PER_LANE-1:0] init_data_per_lane [NUM_LANES-1:0];
wire [DWIDTH-1:0] init_d_in;
wire [128-1:0] init_d_in_flit [FPW-1:0];
wire [WIDTH_PER_LANE-1:0] descrambled_data_per_lane [NUM_LANES-1:0];
wire [DWIDTH-1:0] d_in;
wire [128-1:0] d_in_flit [FPW-1:0];
//Valid FLIT sources. A FLIT is valid when it is not NULL
wire [FPW-1:0] valid_flit_src; //bit0 = flit0, ...
wire [FPW-1:0] init_valid_flit_src; //bit0 = flit0, ...
generate
//-- Apply lane reversal if detected
for(n = 0; n < NUM_LANES; n = n + 1) begin : apply_lane_reversal
for(w = 0; w < WIDTH_PER_LANE; w = w + 1) begin : inner_apply_lane_reversal
if(CTRL_LANE_REVERSAL==1)begin
assign d_in[w*NUM_LANES+n] = rf_lane_reversal_detected ? descrambled_data_per_lane[NUM_LANES-1-n][w] : descrambled_data_per_lane[n][w];
assign init_d_in[w*NUM_LANES+n] = rf_lane_reversal_detected ? init_data_per_lane[NUM_LANES-1-n][w] : init_data_per_lane[n][w];
end else begin
assign d_in[w*NUM_LANES+n] = descrambled_data_per_lane[n][w];
assign init_d_in[w*NUM_LANES+n] = init_data_per_lane[n][w];
end
end
end
for(f = 0; f < FPW; f = f + 1) begin : reorder_input_data
//-- Reorder the descrambled data to FLITs
assign d_in_flit[f] = d_in[128-1+(f*128):f*128];
assign init_d_in_flit[f] = init_d_in[128-1+(f*128):f*128];
//-- Generate valid flit positions for the init sequence
assign valid_flit_src[f] = (|d_in_flit[f] == 1'b0) ? 1'b0 : 1'b1;
assign init_valid_flit_src[f] = (|init_d_in_flit[f] == 1'b0) ? 1'b0 : 1'b1;
end
endgenerate
//------------------------------------------------------------------------------------INIT
localparam LINK_DOWN = 2'b00;
localparam LINK_INIT = 2'b01;
localparam LINK_UP = 2'b10;
reg [5:0] init_bit_slip_cnt;
reg [4:0] init_wait_time;
wire [NUM_LANES-1:0] init_descrambler_locked; //locked from the descrambler
wire link_is_up;
reg [3:0] init_tmp_seq;
reg init_prbs_seen;
assign link_is_up = rf_link_status[1];
assign rf_all_descramblers_aligned = &init_descrambler_aligned;
//--------------TS1 recognition
localparam ts1_independent_portion = {4'hF,4'h0};
localparam ts1_lanex_portion = {4'h5};
localparam ts1_lane7or15_portion = 4'hc;
localparam ts1_lane0_portion = 4'h3;
localparam ts1_per_cycle_and_lane = DWIDTH/NUM_LANES/16;
wire [NUM_LANES-1:0] init_lane_has_correct_ts1;
wire [ts1_per_cycle_and_lane-1:0] init_lane_has_correct_ts1_vec [NUM_LANES-1:0];
genvar t;
generate
//Make sure that the lanes have valid ts1 sequences throughout the entire data stream
for(n=0;n<NUM_LANES;n=n+1) begin : lane_has_correct_ts1_gen
assign init_lane_has_correct_ts1[n] = &init_lane_has_correct_ts1_vec[n];
for(t=0;t<ts1_per_cycle_and_lane;t=t+1) begin : inner_lane_has_correct_ts1_gen
if(n==0 || n==NUM_LANES-1) begin
assign init_lane_has_correct_ts1_vec[n][t] = (init_data_per_lane[n][(t*16)+16-1:(t*16)+4] == {ts1_independent_portion,ts1_lane7or15_portion})
||
(init_data_per_lane[n][(t*16)+16-1:(t*16)+4] == {ts1_independent_portion,ts1_lane0_portion});
end else begin
assign init_lane_has_correct_ts1_vec[n][t] = (init_data_per_lane[n][(t*16)+16-1:(t*16)+4] == {ts1_independent_portion,ts1_lanex_portion});
end
end
end
endgenerate
//--------------Align the lanes, scan for the ts1 seq
reg [LOG_NUM_LANES-1:0] init_lane_cnt;
wire [3:0] init_seq_diff;
//If one of the descramblers is already partially aligned search for other lanes with their ts1 sequence number close this lane.
assign init_seq_diff = |init_descrambler_part_aligned ?
(BITSLIP_SHIFT_RIGHT==1 ? (init_data_per_lane[init_lane_cnt][3:0] - init_tmp_seq)
: init_tmp_seq - init_data_per_lane[init_lane_cnt][3:0])
: 0;
//------------------------------------------------------------------------------------Input Stage: Scan for Packets, Headers, Tails ...
reg [DWIDTH-1:0] data2crc;
reg [FPW-1:0] data2crc_hdr;
reg [FPW-1:0] data2crc_tail;
reg [FPW-1:0] data2crc_valid;
wire [(FPW*4)-1:0] data2crc_lng;
reg [3:0] data2crc_lng_per_flit [FPW-1:0];
reg [3:0] data2crc_payload_remain;
reg [FPW-1:0] data2crc_hdr_comb;
reg [FPW-1:0] data2crc_tail_comb;
reg [FPW-1:0] data2crc_valid_comb;
reg [3:0] data2crc_lng_per_flit_comb [FPW-1:0];
reg [3:0] data2crc_payload_remain_comb;
generate
for(f = 0; f < (FPW); f = f + 1) begin : INPUT_SCAN
assign data2crc_lng[(f*4)+4-1:(f*4)] = data2crc_lng_per_flit[f];
end
endgenerate
//------------------------------------------------------------------------------------CRC
wire [DWIDTH-1:0] crc_d_out_data;
wire [128-1:0] crc_d_out_flit [FPW-1:0];
wire [FPW-1:0] crc_d_out_flit_is_hdr;
wire [FPW-1:0] crc_d_out_flit_is_tail;
wire [FPW-1:0] crc_d_out_flit_is_valid;
wire [FPW-1:0] crc_d_out_flit_is_error;
wire [FPW-1:0] crc_d_out_flit_is_poisoned;
wire [FPW-1:0] crc_d_out_flit_has_rtc;
wire [FPW-1:0] crc_d_out_flit_is_flow;
generate
for(f=0;f<FPW;f=f+1) begin : reorder_crc_output
assign crc_d_out_flit[f] = crc_d_out_data[128-1+(f*128):f*128];
end
endgenerate
//------------------------------------------------------------------------------------LNG and DLN stage
reg [128-1:0] flit_after_lng_check [FPW-1:0];
reg [FPW-1:0] flit_after_lng_check_is_hdr;
reg [FPW-1:0] flit_after_lng_check_is_tail;
reg [FPW-1:0] flit_after_lng_check_is_valid;
reg [FPW-1:0] flit_after_lng_check_is_error;
reg [FPW-1:0] flit_after_lng_check_is_poisoned;
reg [FPW-1:0] flit_after_lng_check_is_flow;
reg [FPW-1:0] flit_after_lng_check_has_rtc;
//------------------------------------------------------------------------------------Start TX retry Stage
reg [128-1:0] flit_after_retry_stage [FPW-1:0];
reg [FPW-1:0] flit_after_retry_stage_is_hdr;
reg [FPW-1:0] flit_after_retry_stage_is_tail;
reg [FPW-1:0] flit_after_retry_stage_is_valid;
reg [FPW-1:0] flit_after_retry_stage_is_valid_mask_msb;
reg [FPW-1:0] flit_after_retry_stage_is_valid_mask_lsb;
reg [FPW-1:0] flit_after_retry_stage_is_error;
reg [FPW-1:0] flit_after_retry_stage_is_poisoned;
reg [FPW-1:0] flit_after_retry_stage_is_flow;
reg [FPW-1:0] flit_after_retry_stage_has_rtc;
reg [FPW-1:0] flit_after_retry_stage_is_start_retry;
reg [FPW-1:0] flit_after_retry_stage_is_start_retry_comb;
//------------------------------------------------------------------------------------SeqStage and Seqnum
reg [128-1:0] flit_after_seq_check [FPW-1:0];
reg [FPW-1:0] flit_after_seq_check_is_hdr;
reg [FPW-1:0] flit_after_seq_check_is_tail;
reg [FPW-1:0] flit_after_seq_check_is_valid;
reg [FPW-1:0] flit_after_seq_check_is_error;
reg [FPW-1:0] flit_after_seq_check_is_error_comb;
reg [FPW-1:0] flit_after_seq_check_is_poisoned;
reg [FPW-1:0] flit_after_seq_check_is_flow;
reg [FPW-1:0] flit_after_seq_check_has_rtc;
reg [FPW-1:0] flit_after_seq_check_is_start_retry;
reg [2:0] next_seqnum;
reg [2:0] next_seqnum_comb; //use param instead
reg [2:0] first_seq_after_error;
//------------------------------------------------------------------------------------Invalidation Stage
localparam CYCLES_TO_COMPLETE_FULL_PACKET = (FPW == 2) ? 5 :
(FPW == 4) ? 3 : //Assuming Max Pkt size = 9 FLITs
(FPW == 6) ? 3 :
(FPW == 8) ? 2 :
1;
//Regs to retrieve the pkt length, assign the length to correspoding tail. The packet will be invalidated then
reg [3:0] lng_per_tail [FPW-1:0] ;
reg [3:0] lng_per_tail_comb [FPW-1:0] ;
reg [3:0] lng_temp;
reg [3:0] lng_comb;
//Signal that an error was detected. Invalid all FLITs after
reg error_detected;
//Assign FLITs to word, necessary for the invalidation stage pipeline
wire [DWIDTH-1:0] flit_after_seq_check_word;
generate
for(f = 0; f < (FPW); f = f + 1) begin : reorder_flits_after_seq_to_word
assign flit_after_seq_check_word[(f*128)+128-1:(f*128)] = flit_after_seq_check[f];
end
endgenerate
reg [DWIDTH-1:0] flit_in_invalidation_data [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
reg [FPW-1:0] flit_in_invalidation_is_hdr [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
reg [FPW-1:0] flit_in_invalidation_is_tail [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
reg [FPW-1:0] flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
reg [FPW-1:0] flit_in_invalidation_mask_error;
reg [FPW-1:0] flit_in_invalidation_is_poisoned [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
reg [FPW-1:0] flit_in_invalidation0_is_poisoned_comb;
reg [FPW-1:0] flit_in_invalidation_is_flow [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
reg [FPW-1:0] flit_in_invalidation_has_rtc [CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
reg [FPW-1:0] flit_in_invalidation_is_start_retry[CYCLES_TO_COMPLETE_FULL_PACKET-1:0];
//------------------------------------------------------------------------------------Checked FLITs
wire [128-1:0] checked_flit [FPW-1:0];
wire [FPW-1:0] checked_flit_is_poisoned;
wire [FPW-1:0] checked_flit_is_valid;
wire [FPW-1:0] checked_flit_is_hdr;
wire [FPW-1:0] checked_flit_is_tail;
wire [FPW-1:0] checked_flit_has_rtc;
wire [FPW-1:0] checked_flit_is_flow;
wire [FPW-1:0] checked_flit_is_start_retry;
assign checked_flit_is_hdr = flit_in_invalidation_is_hdr [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
assign checked_flit_is_tail = flit_in_invalidation_is_tail [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
assign checked_flit_is_valid = flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1] ;
assign checked_flit_is_poisoned = flit_in_invalidation_is_poisoned [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
assign checked_flit_is_flow = flit_in_invalidation_is_flow [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
assign checked_flit_has_rtc = flit_in_invalidation_has_rtc [CYCLES_TO_COMPLETE_FULL_PACKET-1] & flit_in_invalidation_is_valid [CYCLES_TO_COMPLETE_FULL_PACKET-1];
assign checked_flit_is_start_retry = flit_in_invalidation_is_start_retry[CYCLES_TO_COMPLETE_FULL_PACKET-1];
generate
for(f = 0; f < (FPW); f = f + 1) begin : reorder_invalidation_word_back_to_flits
assign checked_flit[f] = flit_in_invalidation_data[CYCLES_TO_COMPLETE_FULL_PACKET-1][128-1+(f*128):f*128];
end
endgenerate
//------------------------------------------------------------------------------------Counter
reg [LOG_FPW:0] rf_cnt_poisoned_comb;
reg [LOG_FPW:0] rf_cnt_rsp_comb;
//------------------------------------------------------------------------------------Input Buffer
reg [LOG_FPW:0] tokens_out_of_fifo_sum_comb;
reg [LOG_FPW:0] tokens_poisoned;
reg [7:0] rtc_sum_comb; //for 8 FLIT config, maximum 8*31 tokens will be returned per cycle
reg [128-1:0] input_buffer_d_in_flit [FPW-1:0];
reg [FPW-1:0] input_buffer_valid;
reg [FPW-1:0] input_buffer_is_hdr;
reg [FPW-1:0] input_buffer_is_tail;
reg [FPW-1:0] input_buffer_is_error_rsp;
wire [DWIDTH+(4*FPW)-1:0] input_buffer_d_in;
wire [DWIDTH+(4*FPW)-1:0] input_buffer_d_out;
wire input_buffer_empty;
reg input_buffer_shift_in;
wire input_buffer_shift_out;
assign input_buffer_shift_out = ~(input_buffer_empty || d_out_fifo_a_full);
generate
for(f = 0; f < (FPW); f = f + 1) begin : assign_flits_to_input_buffer_to_a_single_reg
assign input_buffer_d_in[f*128+128-1:f*128] = input_buffer_d_in_flit[f];
assign input_buffer_d_in[DWIDTH+f] = input_buffer_valid[f];
assign input_buffer_d_in[DWIDTH+f+FPW] = input_buffer_is_hdr[f];
assign input_buffer_d_in[DWIDTH+f+(2*FPW)] = input_buffer_is_tail[f];
assign input_buffer_d_in[DWIDTH+f+(3*FPW)] = input_buffer_is_error_rsp[f];
end
endgenerate
//------------------------------------------------------------------------------------LINK RETRY
reg [5:0] irtry_start_retry_cnt;
reg [5:0] irtry_clear_error_cnt;
reg [5:0] irtry_start_retry_cnt_comb;
reg [5:0] irtry_clear_error_cnt_comb;
reg irtry_clear_trig;
reg irtry_clear_trig_comb;
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------ACTUAL LOGIC STARTS HERE--------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//========================================================================================================================================
//------------------------------------------------------------------INIT
//========================================================================================================================================
always @(posedge clk) begin
for(i_l = 0;i_l<NUM_LANES;i_l=i_l+1)begin
init_data_per_lane[i_l] <= descrambled_data_per_lane[i_l];
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
//----Misc
init_descrambler_aligned <= {NUM_LANES{1'b0}};
init_descrambler_part_aligned <= {NUM_LANES{1'b0}};
init_bit_slip <= {NUM_LANES{1'b0}};
init_bit_slip_cnt <= 6'h0;
init_wait_time <= 5'h0;
init_tmp_seq <= 4'h0;
init_lane_cnt <= {LOG_NUM_LANES{1'b0}};
init_prbs_seen <= 1'b0;
rf_hmc_init_status <= HMC_DOWN;
rf_link_status <= LINK_DOWN;
rf_lane_polarity <= {NUM_LANES{1'b0}};
rf_lane_reversal_detected <= 1'b0;
rf_descramblers_locked <= {NUM_LANES{1'b0}};
end
else begin
rf_descramblers_locked <= init_descrambler_locked;
init_bit_slip <= {NUM_LANES{1'b0}};
if(rf_hmc_sleep || !rf_hmc_init_cont_set) begin
rf_link_status <= LINK_DOWN;
end else if(rf_link_status == LINK_DOWN) begin
//Begin (Re-)Init
init_descrambler_aligned <= {NUM_LANES{1'b0}};
init_descrambler_part_aligned <= {NUM_LANES{1'b0}};
init_wait_time <= 5'h1f;
init_tmp_seq <= 4'h0;
init_lane_cnt <= {LOG_NUM_LANES{1'b0}};
init_prbs_seen <= 1'b0;
rf_hmc_init_status <= HMC_DOWN;
rf_link_status <= LINK_INIT;
rf_lane_polarity <= {NUM_LANES{1'b0}};
rf_lane_reversal_detected <= 1'b0;
rf_descramblers_locked <= {NUM_LANES{1'b0}};
end
//Detect Lane polarity when HMC is sending first NULLs
if(&rf_descramblers_locked && rf_link_status == LINK_INIT) begin
for(i_l = 0;i_l<NUM_LANES;i_l=i_l+1)begin
if(init_data_per_lane[i_l] == {WIDTH_PER_LANE{1'b1}})begin
rf_lane_polarity[i_l] <= 1'b1;
end
end
end
if(rf_hmc_init_status == HMC_DOWN) begin
if(|init_valid_flit_src) begin
init_prbs_seen <= 1'b1;
end
if(!init_valid_flit_src && init_prbs_seen && &rf_descramblers_locked) begin
rf_hmc_init_status <= HMC_NULL;
end
end
//When TX block sends ts1, start init process
if(rf_tx_sends_ts1 && &init_valid_flit_src) begin
rf_hmc_init_status <= HMC_TS1;
end
if(rf_hmc_init_status==HMC_TS1) begin
// -------------------------------------------------------------------------TS1 AND DESCRAMBLER SYNCHRONIZATION
if(!rf_all_descramblers_aligned) begin // repeat this until all descramblers are aligned !!
if(|init_wait_time == 1'b0)begin
init_tmp_seq <= init_tmp_seq + INIT_SEQ_INC_PER_CYCLE;
if(|init_bit_slip_cnt == 1'b0)begin
init_lane_cnt <= init_lane_cnt + 1;
if(!init_descrambler_part_aligned[init_lane_cnt])begin
init_bit_slip[init_lane_cnt] <= ~init_lane_has_correct_ts1[init_lane_cnt];
//if the current lane is more advanced than the current reference lane, set this lane as new reference
if(init_seq_diff < 2 && init_lane_has_correct_ts1[init_lane_cnt]) begin
init_tmp_seq <= init_data_per_lane[init_lane_cnt][3:0] + INIT_SEQ_INC_PER_CYCLE;
end
end
if(&init_descrambler_part_aligned) begin
if(|init_seq_diff==1'b0 && init_lane_has_correct_ts1[init_lane_cnt])begin
init_descrambler_aligned[init_lane_cnt] <= 1'b1;
end else begin
init_bit_slip[init_lane_cnt] <= 1'b1;
end
end else begin
init_descrambler_part_aligned[init_lane_cnt] <= init_lane_has_correct_ts1[init_lane_cnt];
end
if(init_lane_cnt == NUM_LANES-1)begin
init_bit_slip_cnt <= rf_bit_slip_time;
end
end else begin
init_bit_slip_cnt <= init_bit_slip_cnt -1;
end
end else begin
init_wait_time <= init_wait_time -1;
end
// -------------------------------------------------------------------------SECOND NULL SEQUENCE
end else begin // now that all is synchronized continue with NULL and TRET
//lane reversal detected, reverse the input stream lane by lane
if(init_data_per_lane[0][7:4] == ts1_lane7or15_portion)begin
rf_lane_reversal_detected <= 1'b1;
end
//when received NULLs again, init done (initial TRETs are treated as normal packets)
if(|init_valid_flit_src == 1'b0)begin
rf_link_status <= LINK_UP;
rf_hmc_init_status <= HMC_UP;
end
end
end
end
end
//========================================================================================================================================
//------------------------------------------------------------------Packet Processing
//========================================================================================================================================
//==================================================================================
//---------------------------------Detect HDR,Tail,Valid Flits and provide to CRC logic
//==================================================================================
always @(*) begin
//Use the remaining payload from last cycle
data2crc_payload_remain_comb = data2crc_payload_remain;
data2crc_hdr_comb = {FPW{1'b0}};
data2crc_tail_comb = {FPW{1'b0}};
data2crc_valid_comb = {FPW{1'b0}};
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
data2crc_lng_per_flit_comb[i_f] = {128{1'b0}};
if(data2crc_payload_remain_comb ==4'h1) begin
data2crc_tail_comb[i_f] = 1'b1;
end
if(data2crc_payload_remain_comb) begin
data2crc_valid_comb[i_f] = 1'b1;
data2crc_payload_remain_comb = data2crc_payload_remain_comb - 1;
end else if(valid_flit_src[i_f])begin
data2crc_hdr_comb[i_f] = 1'b1;
data2crc_valid_comb[i_f] = 1'b1;
if(lng(d_in_flit[i_f]) < 2 || lng(d_in_flit[i_f]) > 9) begin
//Treat false lng values as single FLIT packets which will force error abort mode
data2crc_tail_comb[i_f] = 1'b1;
data2crc_lng_per_flit_comb[i_f] = 1;
end else begin
data2crc_payload_remain_comb = lng(d_in_flit[i_f]) -1;
data2crc_lng_per_flit_comb[i_f] = lng(d_in_flit[i_f]);
end
end
end
end
//Register the combinational logic from previous stage
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
data2crc_hdr <= {FPW{1'b0}};
data2crc_tail <= {FPW{1'b0}};
data2crc_valid <= {FPW{1'b0}};
data2crc_payload_remain <= {4{1'b0}};
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
data2crc_lng_per_flit[i_f] <= {128{1'b0}};
end
data2crc <= {DWIDTH{1'b0}};
end else begin
if(link_is_up) begin
data2crc_hdr <= data2crc_hdr_comb;
data2crc_tail <= data2crc_tail_comb;
data2crc_valid <= data2crc_valid_comb;
end
data2crc_payload_remain <= data2crc_payload_remain_comb;
for(i_f=0;i_f<FPW;i_f=i_f+1) begin
data2crc_lng_per_flit[i_f] <= data2crc_lng_per_flit_comb[i_f];
end
data2crc <= d_in;
end
end
//==================================================================================
//---------------------------------LNG/DLN check
//==================================================================================
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
flit_after_lng_check_is_hdr <= {FPW{1'b0}};
flit_after_lng_check_is_tail <= {FPW{1'b0}};
flit_after_lng_check_is_valid <= {FPW{1'b0}};
flit_after_lng_check_is_poisoned <= {FPW{1'b0}};
flit_after_lng_check_is_flow <= {FPW{1'b0}};
flit_after_lng_check_has_rtc <= {FPW{1'b0}};
flit_after_lng_check_is_error <= {FPW{1'b0}};
for(i_f = 0; i_f < FPW; i_f = i_f + 1) begin
flit_after_lng_check[i_f] <= {128{1'b0}};
end
end else begin
flit_after_lng_check_is_hdr <= crc_d_out_flit_is_hdr;
flit_after_lng_check_is_tail <= crc_d_out_flit_is_tail;
flit_after_lng_check_is_valid <= crc_d_out_flit_is_valid;
flit_after_lng_check_is_poisoned <= crc_d_out_flit_is_poisoned;
flit_after_lng_check_is_flow <= crc_d_out_flit_is_flow;
flit_after_lng_check_has_rtc <= crc_d_out_flit_has_rtc;
flit_after_lng_check_is_error <= crc_d_out_flit_is_error;
for(i_f = 0; i_f < FPW; i_f = i_f + 1) begin
flit_after_lng_check[i_f] <= crc_d_out_flit[i_f];
end
//perform lng/dln check
for(i_f = 0; i_f < FPW; i_f = i_f + 1) begin
if(crc_d_out_flit_is_hdr[i_f] && (lng(crc_d_out_flit[i_f]) != dln(crc_d_out_flit[i_f]))) begin
flit_after_lng_check_is_error[i_f] <= 1'b1;
end
end
end
end
//====================================================================
//---------------------------------Start Retry Stage
//====================================================================
//-- Count all types of IRTRY packets
always @(*) begin
//Set the lower bit mask for the next stage: Mask out all error FLITs
flit_after_retry_stage_is_valid_mask_lsb = {FPW{1'b1}};
for(i_f = FPW-1; i_f >=0; i_f = i_f - 1) begin
if(flit_after_lng_check_is_error[i_f])begin
//Pass the tail in case it is an crc error so that the corresponding FLITs of the packet can be invalidated
//but mask out single flit packets!
flit_after_retry_stage_is_valid_mask_lsb = {FPW{1'b1}} >> (FPW-i_f-(flit_after_lng_check_is_tail[i_f] & !flit_after_lng_check_is_hdr[i_f]));
end
end
//Next up, count both types of irtry packets and set the mask accordingly for irtry start packets in error abort mode and the
//final clear abort FLIT that reaches the threshold
flit_after_retry_stage_is_start_retry_comb = {FPW{1'b0}};
if( (tx_error_abort_mode && !irtry_clear_trig) ||
|(flit_after_retry_stage_is_error) ||
|(flit_after_seq_check_is_error)
)begin
flit_after_retry_stage_is_valid_mask_msb = {FPW{1'b0}};
end else begin
flit_after_retry_stage_is_valid_mask_msb = {FPW{1'b1}};
end
irtry_clear_trig_comb = 1'b0;
irtry_clear_error_cnt_comb = irtry_clear_error_cnt;
irtry_start_retry_cnt_comb = irtry_start_retry_cnt;
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
if( flit_after_lng_check_is_flow[i_f] &&
cmd(flit_after_lng_check[i_f]) == {CMD_FLOW,CMD_IRTRY} &&
!flit_after_lng_check_is_error[i_f]
) begin
if(irtry_start_retry_flag(flit_after_lng_check[i_f])) begin
//it's a start tx retry pkt
irtry_start_retry_cnt_comb = irtry_start_retry_cnt_comb + 6'h1;
irtry_clear_error_cnt_comb = 6'h0;
end else begin
//must be clear error pkt
irtry_clear_error_cnt_comb = irtry_clear_error_cnt_comb + 6'h1;
irtry_start_retry_cnt_comb = 6'h0;
end
if(irtry_start_retry_cnt_comb == rf_irtry_received_threshold) begin
//The start retry packet that reaches the trehold is treated as valid and will trigger tx retry
flit_after_retry_stage_is_valid_mask_msb[i_f] = 1'b1;
flit_after_retry_stage_is_start_retry_comb[i_f] = 1'b1;
end
//Clear error abort when threshold reached, allow following FLITs to be valid
if(irtry_clear_error_cnt_comb == rf_irtry_received_threshold) begin
irtry_clear_trig_comb = 1'b1;
flit_after_retry_stage_is_valid_mask_msb = {FPW{1'b1}} << (i_f);
end
end else begin
//Reset both counters when received a non-irtry packet
irtry_start_retry_cnt_comb = 6'h0;
irtry_clear_error_cnt_comb = 6'h0;
end
end
end
//Save the temporary counts to be re-used in the next cycle and register the clear trigger
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
irtry_clear_trig <= 1'b0;
irtry_clear_error_cnt <= {6{1'b0}};
irtry_start_retry_cnt <= {6{1'b0}};
end else begin
irtry_clear_trig <= irtry_clear_trig_comb;
irtry_clear_error_cnt <= irtry_clear_error_cnt_comb;
irtry_start_retry_cnt <= irtry_start_retry_cnt_comb;
end
end
//Propagate data and apply the valid masks
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_f = 0;i_f<(FPW);i_f=i_f+1) begin
flit_after_retry_stage[i_f] <= {128{1'b0}};
end
flit_after_retry_stage_is_hdr <= {FPW{1'b0}};
flit_after_retry_stage_is_tail <= {FPW{1'b0}};
flit_after_retry_stage_is_poisoned <= {FPW{1'b0}};
flit_after_retry_stage_is_flow <= {FPW{1'b0}};
flit_after_retry_stage_has_rtc <= {FPW{1'b0}};
flit_after_retry_stage_is_error <= {FPW{1'b0}};
flit_after_retry_stage_is_valid <= {FPW{1'b0}};
flit_after_retry_stage_is_start_retry <= 1'b0;
end else begin
for(i_f = 0;i_f<(FPW);i_f=i_f+1) begin
flit_after_retry_stage[i_f] <= flit_after_lng_check[i_f];
end
flit_after_retry_stage_is_hdr <= flit_after_lng_check_is_hdr;
flit_after_retry_stage_is_tail <= flit_after_lng_check_is_tail;
flit_after_retry_stage_is_poisoned <= flit_after_lng_check_is_poisoned &
flit_after_retry_stage_is_valid_mask_msb &
flit_after_retry_stage_is_valid_mask_lsb;
flit_after_retry_stage_is_flow <= flit_after_lng_check_is_flow;
flit_after_retry_stage_has_rtc <= flit_after_lng_check_has_rtc;
flit_after_retry_stage_is_error <= flit_after_lng_check_is_error;
flit_after_retry_stage_is_valid <= flit_after_lng_check_is_valid &
flit_after_retry_stage_is_valid_mask_msb &
flit_after_retry_stage_is_valid_mask_lsb;
flit_after_retry_stage_is_start_retry <= flit_after_retry_stage_is_start_retry_comb;
end
end
//-------------------------------------------Error abort mode
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
//TX signaling
tx_error_abort_mode <= 1'b0;
tx_error_abort_mode_cleared <= 1'b0;
end else begin
tx_error_abort_mode_cleared <= 1'b0;
if(irtry_clear_trig) begin
tx_error_abort_mode <= 1'b0;
tx_error_abort_mode_cleared <= 1'b1;
end
//Set error abort mode again if error detected
if(|flit_after_lng_check_is_error || flit_after_seq_check_is_error)begin
tx_error_abort_mode <= 1'b1;
end
end
end
//==================================================================================
//---------------------------------SEQ check
//==================================================================================
//Check the seqnum FLIT by FLIT. Assign the last received seqnum when error abort mode is cleared
//!Lots of logic levels for 8FLIT config
always @(*) begin
next_seqnum_comb = 3'h0;
flit_after_seq_check_is_error_comb = {FPW{1'b0}};
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
if(flit_after_retry_stage_has_rtc[i_f]) begin
//All packets that have an RTC also have a valid seqnum
if(seq(flit_after_retry_stage[i_f]) == next_seqnum + next_seqnum_comb) begin
next_seqnum_comb = next_seqnum_comb + 3'h1;
end else begin
flit_after_seq_check_is_error_comb[i_f] = 1'b1;
end
end
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
//We expect the first packet to have the seqnum 1
next_seqnum <= 3'h1;
flit_after_seq_check_is_hdr <= {FPW{1'b0}};
flit_after_seq_check_is_tail <= {FPW{1'b0}};
flit_after_seq_check_is_valid <= {FPW{1'b0}};
flit_after_seq_check_is_poisoned <= {FPW{1'b0}};
flit_after_seq_check_is_flow <= {FPW{1'b0}};
flit_after_seq_check_has_rtc <= {FPW{1'b0}};
flit_after_seq_check_is_error <= {FPW{1'b0}};
flit_after_seq_check_is_start_retry <= {FPW{1'b0}};
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
flit_after_seq_check[i_f] <= {128{1'b0}};
end
end else begin
//Set the expected sequence number to the first one after error abort mode was cleared
//otherwise apply the last seqnum + combinatioanl offset
if(irtry_clear_trig_comb) begin
next_seqnum <= first_seq_after_error + next_seqnum_comb;
end else begin
next_seqnum <= next_seqnum + next_seqnum_comb;
end
//propage data to next stage and include any error bits that were detected during sequence number check
flit_after_seq_check_is_hdr <= flit_after_retry_stage_is_hdr;
flit_after_seq_check_is_tail <= flit_after_retry_stage_is_tail;
flit_after_seq_check_is_valid <= flit_after_retry_stage_is_valid;
flit_after_seq_check_is_poisoned <= flit_after_retry_stage_is_poisoned;
flit_after_seq_check_is_flow <= flit_after_retry_stage_is_flow;
flit_after_seq_check_has_rtc <= flit_after_retry_stage_has_rtc;
flit_after_seq_check_is_error <= flit_after_retry_stage_is_error |
flit_after_seq_check_is_error_comb;
flit_after_seq_check_is_start_retry <= flit_after_retry_stage_is_start_retry;
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
flit_after_seq_check[i_f] <= flit_after_retry_stage[i_f];
end
end
end
//==================================================================================
//---------------------------------Retrieve the lengths to invalide FLITs
//==================================================================================
always @(*) begin
//Retrieve the length from the header and assign it to the tail. This information will be used in the
//invalidation stage to mask out FLITs that belong to the faulty packet
lng_comb = lng_temp;
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
if(flit_after_retry_stage_is_hdr[i_f]) begin
if( lng(flit_after_retry_stage[i_f]) < 2 ||
lng(flit_after_retry_stage[i_f]) > 9
) begin
lng_comb = 1;
end else begin
lng_comb = lng(flit_after_retry_stage[i_f]);
end
end
if(flit_after_retry_stage_is_tail[i_f]) begin
lng_per_tail_comb[i_f] = lng_comb;
end else begin
lng_per_tail_comb[i_f] = {4{1'b0}};
end
end
end
//Register combinational values
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
lng_per_tail[i_f] <= 0;
end
lng_temp <= {4{1'b0}};
end else begin
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
lng_per_tail[i_f] <= lng_per_tail_comb[i_f];
end
lng_temp <= lng_comb;
end
end
//==================================================================================
//---------------------------------FLIT Invalidation Stage
//==================================================================================
//Constant propagation for some parts of the invalidation stage
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_c=0; i_c<(CYCLES_TO_COMPLETE_FULL_PACKET); i_c=i_c+1) begin
flit_in_invalidation_data[i_c] <= {DWIDTH{1'b0}};
flit_in_invalidation_is_hdr[i_c] <= {FPW{1'b0}};
flit_in_invalidation_is_tail[i_c] <= {FPW{1'b0}};
flit_in_invalidation_is_flow[i_c] <= {FPW{1'b0}};
flit_in_invalidation_has_rtc[i_c] <= {FPW{1'b0}};
flit_in_invalidation_is_start_retry[i_c] <= {FPW{1'b0}};
end
end else begin
flit_in_invalidation_data[0] <= flit_after_seq_check_word;
flit_in_invalidation_is_hdr[0] <= flit_after_seq_check_is_hdr;
flit_in_invalidation_is_tail[0] <= flit_after_seq_check_is_tail;
flit_in_invalidation_is_flow[0] <= flit_after_seq_check_is_flow;
flit_in_invalidation_has_rtc[0] <= flit_after_seq_check_has_rtc;
flit_in_invalidation_is_start_retry[0] <= flit_after_seq_check_is_start_retry;
for(i_c=0; i_c<(CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c=i_c+1) begin
flit_in_invalidation_data[i_c+1] <= flit_in_invalidation_data[i_c];
flit_in_invalidation_is_hdr[i_c+1] <= flit_in_invalidation_is_hdr[i_c];
flit_in_invalidation_is_tail[i_c+1] <= flit_in_invalidation_is_tail[i_c];
flit_in_invalidation_is_flow[i_c+1] <= flit_in_invalidation_is_flow[i_c];
flit_in_invalidation_has_rtc[i_c+1] <= flit_in_invalidation_has_rtc[i_c];
flit_in_invalidation_is_start_retry[i_c+1] <= flit_in_invalidation_is_start_retry[i_c];
end
end
end
//Mark all poisoned FLITs
always @(*) begin
flit_in_invalidation0_is_poisoned_comb = {FPW{1'b0}};
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
if(flit_after_seq_check_is_poisoned[i_f])begin
flit_in_invalidation0_is_poisoned_comb =flit_in_invalidation0_is_poisoned_comb |
(({FPW{1'b1}} >> (FPW-i_f-1)) & ~({FPW{1'b1}} >> lng_per_tail[i_f]+(FPW-i_f-1)));
end
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET); i_c = i_c + 1) begin
flit_in_invalidation_is_poisoned[i_c] <= 0;
end
end else begin
flit_in_invalidation_is_poisoned[0] <= flit_in_invalidation0_is_poisoned_comb;
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
flit_in_invalidation_is_poisoned[i_c+1] <= flit_in_invalidation_is_poisoned[i_c];
end
//If there is a poisoned packet mark all FLITs as such
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
if(flit_after_seq_check_is_poisoned[i_f]) begin
// flit_in_invalidation_is_poisoned[0] <= ({FPW{1'b1}} >> (FPW-i_f-1)) & ~({FPW{1'b1}} >> lng_per_tail[i_f]+(FPW-i_f-1));
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
if(lng_per_tail[i_f] > ((i_c)*FPW)+i_f+1) begin
flit_in_invalidation_is_poisoned[i_c+1] <= flit_in_invalidation_is_poisoned[i_c] | ~({FPW{1'b1}} >> lng_per_tail[i_f]-(i_c*FPW)-i_f-1);
end
end
end
end
end
end
//Invalidate FLITs that belong to errorenous packets
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET); i_c = i_c + 1) begin
flit_in_invalidation_is_valid[i_c] <= 0;
end
error_detected <= 0;
flit_in_invalidation_mask_error <= {FPW{1'b1}};
end else begin
//Reset the masks for invalidation stages
flit_in_invalidation_mask_error <= {FPW{1'b1}};
if(irtry_clear_trig) begin
error_detected <= 0;
end
//Propate invalidation stages but apply error and poisoned masks to the second stage
for(i_c = 1; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
flit_in_invalidation_is_valid[i_c+1] <= flit_in_invalidation_is_valid[i_c];
end
flit_in_invalidation_is_valid[1] <= flit_in_invalidation_is_valid[0] & flit_in_invalidation_mask_error;
if(error_detected) begin
//There is no valid FLIT when an error was detected
flit_in_invalidation_is_valid[0] <= {FPW{1'b0}};
end else begin
//First apply valids from previous stage
flit_in_invalidation_is_valid[0] <= flit_after_seq_check_is_valid;
//At least one FLIT contained an error in its tail. Leave all FLITs before the error untouched
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
if(flit_after_seq_check_is_error[i_f] && flit_after_seq_check_is_tail[i_f]) begin
error_detected <= 1'b1;
flit_in_invalidation_mask_error <= {FPW{1'b1}} >> (FPW-i_f-1+lng_per_tail[i_f]);
end
end
//Now use the length of the packet to invalidate FLITs that may reside in the next stages already
for(i_f = FPW-1; i_f>=0; i_f = i_f-1) begin
if(flit_after_seq_check_is_error[i_f] && flit_after_seq_check_is_tail[i_f]) begin
for(i_c = 0; i_c < (CYCLES_TO_COMPLETE_FULL_PACKET-1); i_c = i_c + 1) begin
if(lng_per_tail[i_f] > ((i_c)*FPW)+i_f+1) begin
flit_in_invalidation_is_valid[i_c+1] <= flit_in_invalidation_is_valid[i_c] &
({FPW{1'b1}} >> lng_per_tail[i_f]-(i_c*FPW)-i_f-1);
end
end
end
end
end
end
end
//====================================================================
//---------------------------------FRP/RRP/RTC
//====================================================================
//Count Tokens that were returned
always @(*) begin
rtc_sum_comb = {8{1'b0}};
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
if(checked_flit_has_rtc[i_f])begin
rtc_sum_comb = rtc_sum_comb + rtc(checked_flit[i_f]);
end
end
end
//Extract FRP/RRP + last seq (which is necessary to check packets after error_abort_mode is cleared)
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
tx_hmc_frp <= {8{1'b0}};
tx_rrp <= {8{1'b0}};
tx_returned_tokens <= {8{1'b0}};
first_seq_after_error <= 3'h1;
tx_link_retry <= 1'b0;
end else begin
//Return tokens
tx_returned_tokens <= rtc_sum_comb;
//Process FLITs and extract frp/seq/rrp if applicable
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
if(checked_flit_is_tail[i_f] || checked_flit_is_start_retry[i_f]) begin
tx_rrp <= rrp(checked_flit[i_f]);
if(checked_flit_has_rtc[i_f])begin
tx_hmc_frp <= frp(checked_flit[i_f]);
first_seq_after_error <= seq(checked_flit[i_f]) + 3'h1;
end
end
end
//-------------------------------------------TX retry
tx_link_retry <= 1'b0;
if(|checked_flit_is_start_retry)begin
tx_link_retry <= 1'b1;
end
end
end
//==================================================================================
//---------------------------------Fill the input buffer with all response packets
//==================================================================================
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
input_buffer_shift_in <= 1'b0;
input_buffer_valid <= {FPW{1'b0}};
input_buffer_is_hdr <= {FPW{1'b0}};
input_buffer_is_tail <= {FPW{1'b0}};
input_buffer_is_error_rsp <= {FPW{1'b0}};
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
input_buffer_d_in_flit[i_f] <= {128{1'b0}};
end
end else begin
input_buffer_shift_in <= 1'b0;
input_buffer_is_error_rsp <= {FPW{1'b0}};
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
input_buffer_d_in_flit[i_f] <= {128{1'b0}};
//Flow and poisoned packets are not forwarded
if(checked_flit_is_valid[i_f]) begin
if(!checked_flit_is_flow[i_f] && !checked_flit_is_poisoned[i_f])begin
input_buffer_d_in_flit[i_f] <= checked_flit[i_f];
end
if(checked_flit_is_hdr[i_f] && (cmd(checked_flit[i_f])==CMD_RSP_ERROR)) begin
input_buffer_is_error_rsp[i_f] <= 1'b1;
end
end
end
//Mask out any flow or poisoned packets
input_buffer_valid <= checked_flit_is_valid &
~checked_flit_is_flow &
~checked_flit_is_poisoned;
input_buffer_is_hdr <= checked_flit_is_hdr &
~checked_flit_is_flow &
~checked_flit_is_poisoned;
input_buffer_is_tail <= checked_flit_is_tail &
~checked_flit_is_flow &
~checked_flit_is_poisoned;
//If there is still a valid packet remaining after applying the mask
if(|(checked_flit_is_valid & ~checked_flit_is_flow & ~checked_flit_is_poisoned))begin
input_buffer_shift_in <= 1'b1;
end
end
end
always @(*) begin
tokens_poisoned = {LOG_FPW+1{1'b0}};
for(i_f=0; i_f<FPW; i_f=i_f+1) begin
tokens_poisoned = tokens_poisoned + checked_flit_is_poisoned[i_f];
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
tx_hmc_poisoned_tokens_to_return <= {LOG_FPW+1{1'b0}};
end else begin
tx_hmc_poisoned_tokens_to_return <= tokens_poisoned;
end
end
//==================================================================================
//---------------------------------Count responses and poisoned packets
//==================================================================================
always @(*) begin
rf_cnt_poisoned_comb = {LOG_FPW+1{1'b0}};
rf_cnt_rsp_comb = {LOG_FPW+1{1'b0}};
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
if(checked_flit_is_poisoned[i_f] && checked_flit_is_hdr[i_f])begin
rf_cnt_poisoned_comb = rf_cnt_poisoned_comb + {{LOG_FPW{1'b0}},1'b1};
end
if(input_buffer_is_tail[i_f] && !input_buffer_is_error_rsp[i_f])begin
//if its a tail but not error response
rf_cnt_rsp_comb = rf_cnt_rsp_comb + {{LOG_FPW{1'b0}},1'b1};
end
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
rf_cnt_poisoned <= {HMC_RF_RWIDTH{1'b0}};
rf_cnt_rsp <= {HMC_RF_RWIDTH{1'b0}};
end else begin
rf_cnt_poisoned <= rf_cnt_poisoned + {{HMC_RF_RWIDTH-LOG_FPW-1{1'b0}},rf_cnt_poisoned_comb};
rf_cnt_rsp <= rf_cnt_rsp + {{HMC_RF_RWIDTH-LOG_FPW-1{1'b0}},rf_cnt_rsp_comb};
end
end
//==================================================================================
//---------------------------------Shift response packets into the output fifo, return a token for each processed FLIT
//==================================================================================
always @(*) begin
tokens_out_of_fifo_sum_comb = {LOG_FPW+1{1'b0}};
if(input_buffer_shift_out)begin
for(i_f=0; i_f<FPW; i_f=i_f+1) begin
tokens_out_of_fifo_sum_comb = tokens_out_of_fifo_sum_comb +
(input_buffer_d_out[DWIDTH+i_f] &&
!input_buffer_d_out[DWIDTH+i_f+(3*FPW)]); //increment if there's a valid FLIT, but not an error response
end
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
tx_hmc_tokens_to_return <= {LOG_FPW+1{1'b0}};
end else begin
tx_hmc_tokens_to_return <= tokens_out_of_fifo_sum_comb;
end
end
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
if(!res_n) begin
//----FIFO
d_out_fifo_shift_in <= 1'b0;
d_out_fifo_ctrl <= {4*FPW{1'b0}};
d_out_fifo_data <= {DWIDTH{1'b0}};
end else begin
d_out_fifo_shift_in <= 1'b0;
d_out_fifo_ctrl <= {4*FPW{1'b0}};
if(input_buffer_shift_out)begin
d_out_fifo_data <= input_buffer_d_out[DWIDTH-1:0];
d_out_fifo_shift_in <= 1'b1;
d_out_fifo_ctrl <= input_buffer_d_out[DWIDTH+(4*FPW)-1:DWIDTH];
end
end
end
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
wire res_n_lanes;
assign res_n_lanes = ((rf_link_status == LINK_DOWN) || !rf_hmc_init_cont_set) ? 1'b0 : 1'b1;
//Lane Init
genvar i;
generate
for(i=0;i<NUM_LANES;i=i+1)begin : lane_gen
rx_lane_logic #(
.DWIDTH(DWIDTH),
.NUM_LANES(NUM_LANES),
.CTRL_LANE_POLARITY(CTRL_LANE_POLARITY),
.BITSLIP_SHIFT_RIGHT(BITSLIP_SHIFT_RIGHT)
) rx_lane_I (
.clk(clk),
.res_n(res_n_lanes),
.bit_slip(init_bit_slip[i]),
.descrambler_locked(init_descrambler_locked[i]),
.descrambler_disable(rf_scrambler_disable),
.lane_polarity(rf_lane_polarity[i]),
.scrambled_data_in(phy_scrambled_data_in[i*WIDTH_PER_LANE+WIDTH_PER_LANE-1:i*WIDTH_PER_LANE]),
.descrambled_data_out(descrambled_data_per_lane[i])
);
end
endgenerate
//HMC CRC Logic
rx_crc_compare #(
.DWIDTH(DWIDTH),
.FPW(FPW),
.LOG_FPW(LOG_FPW)
)
rx_crc_compare
(
.clk(clk),
.res_n(res_n),
//input
.d_in_data(data2crc),
.d_in_hdr(data2crc_hdr),
.d_in_tail(data2crc_tail),
.d_in_valid(data2crc_valid),
.d_in_lng(data2crc_lng),
//output
.d_out_data(crc_d_out_data),
.d_out_hdr(crc_d_out_flit_is_hdr),
.d_out_tail(crc_d_out_flit_is_tail),
.d_out_valid(crc_d_out_flit_is_valid),
.d_out_error(crc_d_out_flit_is_error),
.d_out_poisoned(crc_d_out_flit_is_poisoned),
.d_out_rtc(crc_d_out_flit_has_rtc),
.d_out_flow(crc_d_out_flit_is_flow)
);
//Buffer Fifo - Depth = Max Tokens
openhmc_sync_fifo #(
.DATASIZE(DWIDTH+(4*FPW)), //+4*FPW for header/tail/valid/error response information -> AXI-4 TUSER signal
.ADDRSIZE(LOG_MAX_RTC)
) input_buffer_I(
.clk(clk),
.res_n(res_n),
.d_in(input_buffer_d_in),
.shift_in(input_buffer_shift_in),
.d_out(input_buffer_d_out),
.shift_out(input_buffer_shift_out),
.next_stage_full(1'b1), // Dont touch!
.empty(input_buffer_empty)
);
endmodule
`default_nettype wire
|
(** * Stlc: The Simply Typed Lambda-Calculus *)
(** The simply typed lambda-calculus (STLC) is a tiny core
calculus embodying the key concept of _functional abstraction_,
which shows up in pretty much every real-world programming
language in some form (functions, procedures, methods, etc.).
We will follow exactly the same pattern as in the previous chapter
when formalizing this calculus (syntax, small-step semantics,
typing rules) and its main properties (progress and preservation).
The new technical challenges arise from the mechanisms of
_variable binding_ and _substitution_. It which will take some
work to deal with these. *)
Set Warnings "-notation-overridden,-parsing".
Require Import Maps.
Require Import Smallstep.
Require Import Types.
(* ################################################################# *)
(** * Overview *)
(** The STLC is built on some collection of _base types_:
booleans, numbers, strings, etc. The exact choice of base types
doesn't matter much -- the construction of the language and its
theoretical properties work out the same no matter what we
choose -- so for the sake of brevity let's take just [Bool] for
the moment. At the end of the chapter we'll see how to add more
base types, and in later chapters we'll enrich the pure STLC with
other useful constructs like pairs, records, subtyping, and
mutable state.
Starting from boolean constants and conditionals, we add three
things:
- variables
- function abstractions
- application
This gives us the following collection of abstract syntax
constructors (written out first in informal BNF notation -- we'll
formalize it below). *)
(**
t ::= x variable
| \x:T1.t2 abstraction
| t1 t2 application
| true constant true
| false constant false
| if t1 then t2 else t3 conditional
*)
(** The [\] symbol in a function abstraction [\x:T1.t2] is generally
written as a Greek letter "lambda" (hence the name of the
calculus). The variable [x] is called the _parameter_ to the
function; the term [t2] is its _body_. The annotation [:T1]
specifies the type of arguments that the function can be applied
to. *)
(** Some examples:
- [\x:Bool. x]
The identity function for booleans.
- [(\x:Bool. x) true]
The identity function for booleans, applied to the boolean [true].
- [\x:Bool. if x then false else true]
The boolean "not" function.
- [\x:Bool. true]
The constant function that takes every (boolean) argument to
[true]. *)
(**
- [\x:Bool. \y:Bool. x]
A two-argument function that takes two booleans and returns
the first one. (As in Coq, a two-argument function is really
a one-argument function whose body is also a one-argument
function.)
- [(\x:Bool. \y:Bool. x) false true]
A two-argument function that takes two booleans and returns
the first one, applied to the booleans [false] and [true].
As in Coq, application associates to the left -- i.e., this
expression is parsed as [((\x:Bool. \y:Bool. x) false) true].
- [\f:Bool->Bool. f (f true)]
A higher-order function that takes a _function_ [f] (from
booleans to booleans) as an argument, applies [f] to [true],
and applies [f] again to the result.
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)]
The same higher-order function, applied to the constantly
[false] function. *)
(** As the last several examples show, the STLC is a language of
_higher-order_ functions: we can write down functions that take
other functions as arguments and/or return other functions as
results.
The STLC doesn't provide any primitive syntax for defining _named_
functions -- all functions are "anonymous." We'll see in chapter
[MoreStlc] that it is easy to add named functions to what we've
got -- indeed, the fundamental naming and binding mechanisms are
exactly the same.
The _types_ of the STLC include [Bool], which classifies the
boolean constants [true] and [false] as well as more complex
computations that yield booleans, plus _arrow types_ that classify
functions. *)
(**
T ::= Bool
| T1 -> T2
For example:
- [\x:Bool. false] has type [Bool->Bool]
- [\x:Bool. x] has type [Bool->Bool]
- [(\x:Bool. x) true] has type [Bool]
- [\x:Bool. \y:Bool. x] has type [Bool->Bool->Bool]
(i.e., [Bool -> (Bool->Bool)])
- [(\x:Bool. \y:Bool. x) false] has type [Bool->Bool]
- [(\x:Bool. \y:Bool. x) false true] has type [Bool] *)
(* ################################################################# *)
(** * Syntax *)
(** We next formalize the syntax of the STLC. *)
Module STLC.
(* ================================================================= *)
(** ** Types *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty.
(* ================================================================= *)
(** ** Terms *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
(** Note that an abstraction [\x:T.t] (formally, [tabs x T t]) is
always annotated with the type [T] of its parameter, in contrast
to Coq (and other functional languages like ML, Haskell, etc.),
which use type inference to fill in missing annotations. We're
not considering type inference here. *)
(** Some examples... *)
Definition x := (Id "x").
Definition y := (Id "y").
Definition z := (Id "z").
Hint Unfold x.
Hint Unfold y.
Hint Unfold z.
(** [idB = \x:Bool. x] *)
Notation idB :=
(tabs x TBool (tvar x)).
(** [idBB = \x:Bool->Bool. x] *)
Notation idBB :=
(tabs x (TArrow TBool TBool) (tvar x)).
(** [idBBBB = \x:(Bool->Bool) -> (Bool->Bool). x] *)
Notation idBBBB :=
(tabs x (TArrow (TArrow TBool TBool)
(TArrow TBool TBool))
(tvar x)).
(** [k = \x:Bool. \y:Bool. x] *)
Notation k := (tabs x TBool (tabs y TBool (tvar x))).
(** [notB = \x:Bool. if x then false else true] *)
Notation notB := (tabs x TBool (tif (tvar x) tfalse ttrue)).
(** (We write these as [Notation]s rather than [Definition]s to make
things easier for [auto].) *)
(* ################################################################# *)
(** * Operational Semantics *)
(** To define the small-step semantics of STLC terms, we begin,
as always, by defining the set of values. Next, we define the
critical notions of _free variables_ and _substitution_, which are
used in the reduction rule for application expressions. And
finally we give the small-step relation itself. *)
(* ================================================================= *)
(** ** Values *)
(** To define the values of the STLC, we have a few cases to consider.
First, for the boolean part of the language, the situation is
clear: [true] and [false] are the only values. An [if]
expression is never a value. *)
(** Second, an application is clearly not a value: It represents a
function being invoked on some argument, which clearly still has
work left to do. *)
(** Third, for abstractions, we have a choice:
- We can say that [\x:T. t1] is a value only when [t1] is a
value -- i.e., only if the function's body has been
reduced (as much as it can be without knowing what argument it
is going to be applied to).
- Or we can say that [\x:T. t1] is always a value, no matter
whether [t1] is one or not -- in other words, we can say that
reduction stops at abstractions.
Our usual way of evaluating expressions in Coq makes the first
choice -- for example,
Compute (fun x:bool => 3 + 4)
yields [fun x:bool => 7].
Most real-world functional programming languages make the second
choice -- reduction of a function's body only begins when the
function is actually applied to an argument. We also make the
second choice here. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse.
Hint Constructors value.
(** Finally, we must consider what constitutes a _complete_ program.
Intuitively, a "complete program" must not refer to any undefined
variables. We'll see shortly how to define the _free_ variables
in a STLC term. A complete program is _closed_ -- that is, it
contains no free variables.
(Conversely, a term with free variables is often called an _open
term_.)
Having made the choice not to reduce under abstractions, we don't
need to worry about whether variables are values, since we'll
always be reducing programs "from the outside in," and that means
the [step] relation will always be working with closed terms. *)
(* ================================================================= *)
(** ** Substitution *)
(** Now we come to the heart of the STLC: the operation of
substituting one term for a variable in another term. This
operation is used below to define the operational semantics of
function application, where we will need to substitute the
argument term for the function parameter in the function's body.
For example, we reduce
(\x:Bool. if x then true else x) false
to
if false then true else false
by substituting [false] for the parameter [x] in the body of the
function.
In general, we need to be able to substitute some given term [s]
for occurrences of some variable [x] in another term [t]. In
informal discussions, this is usually written [ [x:=s]t ] and
pronounced "substitute [x] with [s] in [t]." *)
(** Here are some examples:
- [[x:=true] (if x then x else false)]
yields [if true then true else false]
- [[x:=true] x] yields [true]
- [[x:=true] (if x then x else y)] yields [if true then true else y]
- [[x:=true] y] yields [y]
- [[x:=true] false] yields [false] (vacuous substitution)
- [[x:=true] (\y:Bool. if y then x else false)]
yields [\y:Bool. if y then true else false]
- [[x:=true] (\y:Bool. x)] yields [\y:Bool. true]
- [[x:=true] (\y:Bool. y)] yields [\y:Bool. y]
- [[x:=true] (\x:Bool. x)] yields [\x:Bool. x]
The last example is very important: substituting [x] with [true] in
[\x:Bool. x] does _not_ yield [\x:Bool. true]! The reason for
this is that the [x] in the body of [\x:Bool. x] is _bound_ by the
abstraction: it is a new, local name that just happens to be
spelled the same as some global name [x]. *)
(** Here is the definition, informally...
[x:=s]x = s
[x:=s]y = y if x <> y
[x:=s](\x:T11. t12) = \x:T11. t12
[x:=s](\y:T11. t12) = \y:T11. [x:=s]t12 if x <> y
[x:=s](t1 t2) = ([x:=s]t1) ([x:=s]t2)
[x:=s]true = true
[x:=s]false = false
[x:=s](if t1 then t2 else t3) =
if [x:=s]t1 then [x:=s]t2 else [x:=s]t3
*)
(** ... and formally: *)
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if beq_id x x' then s else t
| tabs x' T t1 =>
tabs x' T (if beq_id x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
end
where "'[' x ':=' s ']' t" := (subst x s t).
(** _Technical note_: Substitution becomes trickier to define if we
consider the case where [s], the term being substituted for a
variable in some other term, may itself contain free variables.
Since we are only interested here in defining the [step] relation
on closed terms (i.e., terms like [\x:Bool. x] that include
binders for all of the variables they mention), we can avoid this
extra complexity here, but it must be dealt with when formalizing
richer languages. *)
(** See, for example, [Aydemir 2008] for further discussion
of this issue. *)
(** **** Exercise: 3 stars (substi) *)
(** The definition that we gave above uses Coq's [Fixpoint] facility
to define substitution as a _function_. Suppose, instead, we
wanted to define substitution as an inductive _relation_ [substi].
We've begun the definition by providing the [Inductive] header and
one of the constructors; your job is to fill in the rest of the
constructors and prove that the relation you've defined coincides
with the function given above. *)
Inductive substi (s:tm) (x:id) : tm -> tm -> Prop :=
| s_var1 :
substi s x (tvar x) s
(* FILL IN HERE *)
.
Hint Constructors substi.
Theorem substi_correct : forall s x t t',
[x:=s]t = t' <-> substi s x t t'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Reduction *)
(** The small-step reduction relation for STLC now follows the
same pattern as the ones we have seen before. Intuitively, to
reduce a function application, we first reduce its left-hand
side (the function) until it becomes an abstraction; then we
reduce its right-hand side (the argument) until it is also a
value; and finally we substitute the argument for the bound
variable in the body of the abstraction. This last rule, written
informally as
(\x:T.t12) v2 ==> [x:=v2]t12
is traditionally called "beta-reduction". *)
(**
value v2
---------------------------- (ST_AppAbs)
(\x:T.t12) v2 ==> [x:=v2]t12
t1 ==> t1'
---------------- (ST_App1)
t1 t2 ==> t1' t2
value v1
t2 ==> t2'
---------------- (ST_App2)
v1 t2 ==> v1 t2'
*)
(** ... plus the usual rules for booleans:
-------------------------------- (ST_IfTrue)
(if true then t1 else t2) ==> t1
--------------------------------- (ST_IfFalse)
(if false then t1 else t2) ==> t2
t1 ==> t1'
---------------------------------------------------- (ST_If)
(if t1 then t2 else t3) ==> (if t1' then t2 else t3)
*)
(** Formally: *)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
(* ================================================================= *)
(** ** Examples *)
(** Example:
(\x:Bool->Bool. x) (\x:Bool. x) ==>* \x:Bool. x
i.e.,
idBB idB ==>* idB
*)
Lemma step_example1 :
(tapp idBB idB) ==>* idB.
Proof.
eapply multi_step.
apply ST_AppAbs.
apply v_abs.
simpl.
apply multi_refl. Qed.
(** Example:
(\x:Bool->Bool. x) ((\x:Bool->Bool. x) (\x:Bool. x))
==>* \x:Bool. x
i.e.,
(idBB (idBB idB)) ==>* idB.
*)
Lemma step_example2 :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto.
eapply multi_step.
apply ST_AppAbs. simpl. auto.
simpl. apply multi_refl. Qed.
(** Example:
(\x:Bool->Bool. x)
(\x:Bool. if x then false else true)
true
==>* false
i.e.,
(idBB notB) ttrue ==>* tfalse.
*)
Lemma step_example3 :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App1. apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_IfTrue. apply multi_refl. Qed.
(** Example:
(\x:Bool -> Bool. x)
((\x:Bool. if x then false else true) true)
==>* false
i.e.,
idBB (notB ttrue) ==>* tfalse.
*)
Lemma step_example4 :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_App2. auto.
apply ST_IfTrue.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
apply multi_refl. Qed.
(** We can use the [normalize] tactic defined in the [Types] chapter
to simplify these proofs. *)
Lemma step_example1' :
(tapp idBB idB) ==>* idB.
Proof. normalize. Qed.
Lemma step_example2' :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof. normalize. Qed.
Lemma step_example3' :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof. normalize. Qed.
Lemma step_example4' :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof. normalize. Qed.
(** **** Exercise: 2 stars (step_example3) *)
(** Try to do this one both with and without [normalize]. *)
Lemma step_example5 :
tapp (tapp idBBBB idBB) idB
==>* idB.
Proof.
(* FILL IN HERE *) Admitted.
Lemma step_example5_with_normalize :
tapp (tapp idBBBB idBB) idB
==>* idB.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Typing *)
(** Next we consider the typing relation of the STLC. *)
(* ================================================================= *)
(** ** Contexts *)
(** _Question_: What is the type of the term "[x y]"?
_Answer_: It depends on the types of [x] and [y]!
I.e., in order to assign a type to a term, we need to know
what assumptions we should make about the types of its free
variables.
This leads us to a three-place _typing judgment_, informally
written [Gamma |- t \in T], where [Gamma] is a
"typing context" -- a mapping from variables to their types. *)
(** Informally, we'll write [Gamma, x:T] for "extend the partial
function [Gamma] to also map [x] to [T]." Formally, we use the
function [extend] to add a binding to a partial map. *)
Definition context := partial_map ty.
(* ================================================================= *)
(** ** Typing Relation *)
(**
Gamma x = T
-------------- (T_Var)
Gamma |- x \in T
Gamma , x:T11 |- t12 \in T12
---------------------------- (T_Abs)
Gamma |- \x:T11.t12 \in T11->T12
Gamma |- t1 \in T11->T12
Gamma |- t2 \in T11
---------------------- (T_App)
Gamma |- t1 t2 \in T12
-------------------- (T_True)
Gamma |- true \in Bool
--------------------- (T_False)
Gamma |- false \in Bool
Gamma |- t1 \in Bool Gamma |- t2 \in T Gamma |- t3 \in T
-------------------------------------------------------- (T_If)
Gamma |- if t1 then t2 else t3 \in T
We can read the three-place relation [Gamma |- t \in T] as:
"to the term [t] we can assign the type [T] using as types for
the free variables of [t] the ones specified in the context
[Gamma]." *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
update Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
(* ================================================================= *)
(** ** Examples *)
Example typing_example_1 :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof.
apply T_Abs. apply T_Var. reflexivity. Qed.
(** Note that since we added the [has_type] constructors to the hints
database, auto can actually solve this one immediately. *)
Example typing_example_1' :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof. auto. Qed.
(** Another example:
empty |- \x:A. \y:A->A. y (y x))
\in A -> (A->A) -> A.
*)
Example typing_example_2 :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof with auto using update_eq.
apply T_Abs.
apply T_Abs.
eapply T_App. apply T_Var...
eapply T_App. apply T_Var...
apply T_Var...
Qed.
(** **** Exercise: 2 stars, optional (typing_example_2_full) *)
(** Prove the same result without using [auto], [eauto], or
[eapply] (or [...]). *)
Example typing_example_2_full :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (typing_example_3) *)
(** Formally prove the following typing derivation holds: *)
(**
empty |- \x:Bool->B. \y:Bool->Bool. \z:Bool.
y (x z)
\in T.
*)
Example typing_example_3 :
exists T,
empty |-
(tabs x (TArrow TBool TBool)
(tabs y (TArrow TBool TBool)
(tabs z TBool
(tapp (tvar y) (tapp (tvar x) (tvar z)))))) \in
T.
Proof with auto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can also show that terms are _not_ typable. For example, let's
formally check that there is no typing derivation assigning a type
to the term [\x:Bool. \y:Bool, x y] -- i.e.,
~ exists T,
empty |- \x:Bool. \y:Bool, x y : T.
*)
Example typing_nonexample_1 :
~ exists T,
empty |-
(tabs x TBool
(tabs y TBool
(tapp (tvar x) (tvar y)))) \in
T.
Proof.
intros Hc. inversion Hc.
(* The [clear] tactic is useful here for tidying away bits of
the context that we're not going to need again. *)
inversion H. subst. clear H.
inversion H5. subst. clear H5.
inversion H4. subst. clear H4.
inversion H2. subst. clear H2.
inversion H5. subst. clear H5.
inversion H1. Qed.
(** **** Exercise: 3 stars, optional (typing_nonexample_3) *)
(** Another nonexample:
~ (exists S, exists T,
empty |- \x:S. x x \in T).
*)
Example typing_nonexample_3 :
~ (exists S, exists T,
empty |-
(tabs x S
(tapp (tvar x) (tvar x))) \in
T).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End STLC.
(** $Date: 2017-05-17 16:11:21 -0400 (Wed, 17 May 2017) $ *)
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sas_intf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
`define INTF0_WIDTH 61
`define INTF1_WIDTH 125
`define INTF2_WIDTH 192
`define INTF3_WIDTH 145
`define INTF4_WIDTH 109
`define INTF5_WIDTH 45
`define CLEAN_CYCLE 200
module sas_intf (/*AUTOARG*/
// Inputs
clk, rst_l
);
input clk;
input rst_l;
wire [`INTF0_WIDTH-1:0] i0_0_data;
wire i0_0_rdy;
wire [`INTF3_WIDTH-1:0] i3_0_data;
wire i3_0_rdy;
wire [`INTF4_WIDTH-1:0] i4_0_data;
wire i4_0_rdy;
wire [`INTF5_WIDTH-1:0] i5_0_data;
wire i5_0_rdy;
reg [1:0] i0_0_ifu_lsu_ldst_size_m;
reg [1:0] i0_0_ifu_lsu_ldst_size_g;
wire i0_0_asi_internal_g;
wire i0_0_asi_quad_g;
wire i0_0_asi_blk_g;
wire i0_0_asi_binit_g;
wire i0_0_dcache_hit_g;
wire i0_0_full_raw_g;
wire i0_0_partial_raw_g;
wire i0_0_ld_l2cache_rq;
wire i0_0_st_inst_vld_g;
wire i0_0_ld_inst_vld_g;
reg[3:0] i4_0_fprs_set_e;
reg[1:0] i4_0_new_fprs_e;
reg[3:0] i4_0_fprs_set_m;
reg[1:0] i4_0_new_fprs_m;
reg[3:0] i4_0_fprs_set_w;
reg[1:0] i4_0_new_fprs_w;
reg i4_0_rstint_w;
reg i4_0_hwint_w;
reg i4_0_sftint_w;
reg i4_0_hint_m;
reg i4_0_hint_w;
reg[3:0] i4_0_int_thr_w;
reg i4_0_ic_inv_vld_f;
reg i4_0_ic_inv_vld_s;
reg[5:0] i4_0_ic_inv_addr_f;
reg[5:0] i4_0_ic_inv_addr_s;
reg i4_0_ic_inv_word1_f;
reg i4_0_ic_inv_word1_s;
reg i4_0_ic_inv_word0_f;
reg i4_0_ic_inv_word0_s;
reg[1:0] i4_0_ic_inv_way1_f;
reg[1:0] i4_0_ic_inv_way1_s;
reg[1:0] i4_0_ic_inv_way0_f;
reg[1:0] i4_0_ic_inv_way0_s;
reg i4_0_st_wr_dcache_m;
reg i4_0_fill_dcache_m;
reg[9:0] i4_0_dcache_fill_addr_m;
reg i4_0_dva_svld_m;
reg[4:0] i4_0_dva_snp_addr_m;
reg[3:0] i4_0_dva_snp_set_vld_m;
reg[1:0] i4_0_dva_snp_wy0_m;
reg[1:0] i4_0_dva_snp_wy1_m;
reg[1:0] i4_0_dva_snp_wy2_m;
reg[1:0] i4_0_dva_snp_wy3_m;
reg i4_0_st_wr_dcache_w;
reg i4_0_fill_dcache_w;
reg[9:0] i4_0_dcache_fill_addr_w;
reg i4_0_dva_svld_w;
reg[4:0] i4_0_dva_snp_addr_w;
reg[3:0] i4_0_dva_snp_set_vld_w;
reg[1:0] i4_0_dva_snp_wy0_w;
reg[1:0] i4_0_dva_snp_wy1_w;
reg[1:0] i4_0_dva_snp_wy2_w;
reg[1:0] i4_0_dva_snp_wy3_w;
wire i4_0_spu_trap_ack_w;
wire i4_0_spu_illgl_va;
wire[3:0] i4_0_tick_match;
wire[3:0] i4_0_stick_match;
wire[3:0] i4_0_hstick_match;
wire i4_0_rstint_vld_w;
wire i4_0_hwint_vld_w;
wire i4_0_sftint_vld_w;
wire i4_0_hint_vld_w;
wire i4_0_trap;
wire[3:0] i4_0_ld_int;
wire i4_0_immu_miss;
wire i4_0_dmmu_miss;
wire[1:0] i4_0_cpx_tid;
wire i4_0_itlb_repl_vld;
wire i4_0_dtlb_repl_vld;
wire[63:0] i4_0_tlb_repl_vec;
wire[5:0] i4_0_tlb_repl_idx;
wire [`INTF0_WIDTH-1:0] i0_1_data;
wire i0_1_rdy;
wire [`INTF3_WIDTH-1:0] i3_1_data;
wire i3_1_rdy;
wire [`INTF4_WIDTH-1:0] i4_1_data;
wire i4_1_rdy;
wire [`INTF5_WIDTH-1:0] i5_1_data;
wire i5_1_rdy;
reg [1:0] i0_1_ifu_lsu_ldst_size_m;
reg [1:0] i0_1_ifu_lsu_ldst_size_g;
wire i0_1_asi_internal_g;
wire i0_1_asi_quad_g;
wire i0_1_asi_blk_g;
wire i0_1_asi_binit_g;
wire i0_1_dcache_hit_g;
wire i0_1_full_raw_g;
wire i0_1_partial_raw_g;
wire i0_1_ld_l2cache_rq;
wire i0_1_st_inst_vld_g;
wire i0_1_ld_inst_vld_g;
reg[3:0] i4_1_fprs_set_e;
reg[1:0] i4_1_new_fprs_e;
reg[3:0] i4_1_fprs_set_m;
reg[1:0] i4_1_new_fprs_m;
reg[3:0] i4_1_fprs_set_w;
reg[1:0] i4_1_new_fprs_w;
reg i4_1_rstint_w;
reg i4_1_hwint_w;
reg i4_1_sftint_w;
reg i4_1_hint_m;
reg i4_1_hint_w;
reg[3:0] i4_1_int_thr_w;
reg i4_1_ic_inv_vld_f;
reg i4_1_ic_inv_vld_s;
reg[5:0] i4_1_ic_inv_addr_f;
reg[5:0] i4_1_ic_inv_addr_s;
reg i4_1_ic_inv_word1_f;
reg i4_1_ic_inv_word1_s;
reg i4_1_ic_inv_word0_f;
reg i4_1_ic_inv_word0_s;
reg[1:0] i4_1_ic_inv_way1_f;
reg[1:0] i4_1_ic_inv_way1_s;
reg[1:0] i4_1_ic_inv_way0_f;
reg[1:0] i4_1_ic_inv_way0_s;
reg i4_1_st_wr_dcache_m;
reg i4_1_fill_dcache_m;
reg[9:0] i4_1_dcache_fill_addr_m;
reg i4_1_dva_svld_m;
reg[4:0] i4_1_dva_snp_addr_m;
reg[3:0] i4_1_dva_snp_set_vld_m;
reg[1:0] i4_1_dva_snp_wy0_m;
reg[1:0] i4_1_dva_snp_wy1_m;
reg[1:0] i4_1_dva_snp_wy2_m;
reg[1:0] i4_1_dva_snp_wy3_m;
reg i4_1_st_wr_dcache_w;
reg i4_1_fill_dcache_w;
reg[9:0] i4_1_dcache_fill_addr_w;
reg i4_1_dva_svld_w;
reg[4:0] i4_1_dva_snp_addr_w;
reg[3:0] i4_1_dva_snp_set_vld_w;
reg[1:0] i4_1_dva_snp_wy0_w;
reg[1:0] i4_1_dva_snp_wy1_w;
reg[1:0] i4_1_dva_snp_wy2_w;
reg[1:0] i4_1_dva_snp_wy3_w;
wire i4_1_spu_trap_ack_w;
wire i4_1_spu_illgl_va;
wire[3:0] i4_1_tick_match;
wire[3:0] i4_1_stick_match;
wire[3:0] i4_1_hstick_match;
wire i4_1_rstint_vld_w;
wire i4_1_hwint_vld_w;
wire i4_1_sftint_vld_w;
wire i4_1_hint_vld_w;
wire i4_1_trap;
wire[3:0] i4_1_ld_int;
wire i4_1_immu_miss;
wire i4_1_dmmu_miss;
wire[1:0] i4_1_cpx_tid;
wire i4_1_itlb_repl_vld;
wire i4_1_dtlb_repl_vld;
wire[63:0] i4_1_tlb_repl_vec;
wire[5:0] i4_1_tlb_repl_idx;
wire [`INTF0_WIDTH-1:0] i0_2_data;
wire i0_2_rdy;
wire [`INTF3_WIDTH-1:0] i3_2_data;
wire i3_2_rdy;
wire [`INTF4_WIDTH-1:0] i4_2_data;
wire i4_2_rdy;
wire [`INTF5_WIDTH-1:0] i5_2_data;
wire i5_2_rdy;
reg [1:0] i0_2_ifu_lsu_ldst_size_m;
reg [1:0] i0_2_ifu_lsu_ldst_size_g;
wire i0_2_asi_internal_g;
wire i0_2_asi_quad_g;
wire i0_2_asi_blk_g;
wire i0_2_asi_binit_g;
wire i0_2_dcache_hit_g;
wire i0_2_full_raw_g;
wire i0_2_partial_raw_g;
wire i0_2_ld_l2cache_rq;
wire i0_2_st_inst_vld_g;
wire i0_2_ld_inst_vld_g;
reg[3:0] i4_2_fprs_set_e;
reg[1:0] i4_2_new_fprs_e;
reg[3:0] i4_2_fprs_set_m;
reg[1:0] i4_2_new_fprs_m;
reg[3:0] i4_2_fprs_set_w;
reg[1:0] i4_2_new_fprs_w;
reg i4_2_rstint_w;
reg i4_2_hwint_w;
reg i4_2_sftint_w;
reg i4_2_hint_m;
reg i4_2_hint_w;
reg[3:0] i4_2_int_thr_w;
reg i4_2_ic_inv_vld_f;
reg i4_2_ic_inv_vld_s;
reg[5:0] i4_2_ic_inv_addr_f;
reg[5:0] i4_2_ic_inv_addr_s;
reg i4_2_ic_inv_word1_f;
reg i4_2_ic_inv_word1_s;
reg i4_2_ic_inv_word0_f;
reg i4_2_ic_inv_word0_s;
reg[1:0] i4_2_ic_inv_way1_f;
reg[1:0] i4_2_ic_inv_way1_s;
reg[1:0] i4_2_ic_inv_way0_f;
reg[1:0] i4_2_ic_inv_way0_s;
reg i4_2_st_wr_dcache_m;
reg i4_2_fill_dcache_m;
reg[9:0] i4_2_dcache_fill_addr_m;
reg i4_2_dva_svld_m;
reg[4:0] i4_2_dva_snp_addr_m;
reg[3:0] i4_2_dva_snp_set_vld_m;
reg[1:0] i4_2_dva_snp_wy0_m;
reg[1:0] i4_2_dva_snp_wy1_m;
reg[1:0] i4_2_dva_snp_wy2_m;
reg[1:0] i4_2_dva_snp_wy3_m;
reg i4_2_st_wr_dcache_w;
reg i4_2_fill_dcache_w;
reg[9:0] i4_2_dcache_fill_addr_w;
reg i4_2_dva_svld_w;
reg[4:0] i4_2_dva_snp_addr_w;
reg[3:0] i4_2_dva_snp_set_vld_w;
reg[1:0] i4_2_dva_snp_wy0_w;
reg[1:0] i4_2_dva_snp_wy1_w;
reg[1:0] i4_2_dva_snp_wy2_w;
reg[1:0] i4_2_dva_snp_wy3_w;
wire i4_2_spu_trap_ack_w;
wire i4_2_spu_illgl_va;
wire[3:0] i4_2_tick_match;
wire[3:0] i4_2_stick_match;
wire[3:0] i4_2_hstick_match;
wire i4_2_rstint_vld_w;
wire i4_2_hwint_vld_w;
wire i4_2_sftint_vld_w;
wire i4_2_hint_vld_w;
wire i4_2_trap;
wire[3:0] i4_2_ld_int;
wire i4_2_immu_miss;
wire i4_2_dmmu_miss;
wire[1:0] i4_2_cpx_tid;
wire i4_2_itlb_repl_vld;
wire i4_2_dtlb_repl_vld;
wire[63:0] i4_2_tlb_repl_vec;
wire[5:0] i4_2_tlb_repl_idx;
wire [`INTF0_WIDTH-1:0] i0_3_data;
wire i0_3_rdy;
wire [`INTF3_WIDTH-1:0] i3_3_data;
wire i3_3_rdy;
wire [`INTF4_WIDTH-1:0] i4_3_data;
wire i4_3_rdy;
wire [`INTF5_WIDTH-1:0] i5_3_data;
wire i5_3_rdy;
reg [1:0] i0_3_ifu_lsu_ldst_size_m;
reg [1:0] i0_3_ifu_lsu_ldst_size_g;
wire i0_3_asi_internal_g;
wire i0_3_asi_quad_g;
wire i0_3_asi_blk_g;
wire i0_3_asi_binit_g;
wire i0_3_dcache_hit_g;
wire i0_3_full_raw_g;
wire i0_3_partial_raw_g;
wire i0_3_ld_l2cache_rq;
wire i0_3_st_inst_vld_g;
wire i0_3_ld_inst_vld_g;
reg[3:0] i4_3_fprs_set_e;
reg[1:0] i4_3_new_fprs_e;
reg[3:0] i4_3_fprs_set_m;
reg[1:0] i4_3_new_fprs_m;
reg[3:0] i4_3_fprs_set_w;
reg[1:0] i4_3_new_fprs_w;
reg i4_3_rstint_w;
reg i4_3_hwint_w;
reg i4_3_sftint_w;
reg i4_3_hint_m;
reg i4_3_hint_w;
reg[3:0] i4_3_int_thr_w;
reg i4_3_ic_inv_vld_f;
reg i4_3_ic_inv_vld_s;
reg[5:0] i4_3_ic_inv_addr_f;
reg[5:0] i4_3_ic_inv_addr_s;
reg i4_3_ic_inv_word1_f;
reg i4_3_ic_inv_word1_s;
reg i4_3_ic_inv_word0_f;
reg i4_3_ic_inv_word0_s;
reg[1:0] i4_3_ic_inv_way1_f;
reg[1:0] i4_3_ic_inv_way1_s;
reg[1:0] i4_3_ic_inv_way0_f;
reg[1:0] i4_3_ic_inv_way0_s;
reg i4_3_st_wr_dcache_m;
reg i4_3_fill_dcache_m;
reg[9:0] i4_3_dcache_fill_addr_m;
reg i4_3_dva_svld_m;
reg[4:0] i4_3_dva_snp_addr_m;
reg[3:0] i4_3_dva_snp_set_vld_m;
reg[1:0] i4_3_dva_snp_wy0_m;
reg[1:0] i4_3_dva_snp_wy1_m;
reg[1:0] i4_3_dva_snp_wy2_m;
reg[1:0] i4_3_dva_snp_wy3_m;
reg i4_3_st_wr_dcache_w;
reg i4_3_fill_dcache_w;
reg[9:0] i4_3_dcache_fill_addr_w;
reg i4_3_dva_svld_w;
reg[4:0] i4_3_dva_snp_addr_w;
reg[3:0] i4_3_dva_snp_set_vld_w;
reg[1:0] i4_3_dva_snp_wy0_w;
reg[1:0] i4_3_dva_snp_wy1_w;
reg[1:0] i4_3_dva_snp_wy2_w;
reg[1:0] i4_3_dva_snp_wy3_w;
wire i4_3_spu_trap_ack_w;
wire i4_3_spu_illgl_va;
wire[3:0] i4_3_tick_match;
wire[3:0] i4_3_stick_match;
wire[3:0] i4_3_hstick_match;
wire i4_3_rstint_vld_w;
wire i4_3_hwint_vld_w;
wire i4_3_sftint_vld_w;
wire i4_3_hint_vld_w;
wire i4_3_trap;
wire[3:0] i4_3_ld_int;
wire i4_3_immu_miss;
wire i4_3_dmmu_miss;
wire[1:0] i4_3_cpx_tid;
wire i4_3_itlb_repl_vld;
wire i4_3_dtlb_repl_vld;
wire[63:0] i4_3_tlb_repl_vec;
wire[5:0] i4_3_tlb_repl_idx;
wire [`INTF0_WIDTH-1:0] i0_4_data;
wire i0_4_rdy;
wire [`INTF3_WIDTH-1:0] i3_4_data;
wire i3_4_rdy;
wire [`INTF4_WIDTH-1:0] i4_4_data;
wire i4_4_rdy;
wire [`INTF5_WIDTH-1:0] i5_4_data;
wire i5_4_rdy;
reg [1:0] i0_4_ifu_lsu_ldst_size_m;
reg [1:0] i0_4_ifu_lsu_ldst_size_g;
wire i0_4_asi_internal_g;
wire i0_4_asi_quad_g;
wire i0_4_asi_blk_g;
wire i0_4_asi_binit_g;
wire i0_4_dcache_hit_g;
wire i0_4_full_raw_g;
wire i0_4_partial_raw_g;
wire i0_4_ld_l2cache_rq;
wire i0_4_st_inst_vld_g;
wire i0_4_ld_inst_vld_g;
reg[3:0] i4_4_fprs_set_e;
reg[1:0] i4_4_new_fprs_e;
reg[3:0] i4_4_fprs_set_m;
reg[1:0] i4_4_new_fprs_m;
reg[3:0] i4_4_fprs_set_w;
reg[1:0] i4_4_new_fprs_w;
reg i4_4_rstint_w;
reg i4_4_hwint_w;
reg i4_4_sftint_w;
reg i4_4_hint_m;
reg i4_4_hint_w;
reg[3:0] i4_4_int_thr_w;
reg i4_4_ic_inv_vld_f;
reg i4_4_ic_inv_vld_s;
reg[5:0] i4_4_ic_inv_addr_f;
reg[5:0] i4_4_ic_inv_addr_s;
reg i4_4_ic_inv_word1_f;
reg i4_4_ic_inv_word1_s;
reg i4_4_ic_inv_word0_f;
reg i4_4_ic_inv_word0_s;
reg[1:0] i4_4_ic_inv_way1_f;
reg[1:0] i4_4_ic_inv_way1_s;
reg[1:0] i4_4_ic_inv_way0_f;
reg[1:0] i4_4_ic_inv_way0_s;
reg i4_4_st_wr_dcache_m;
reg i4_4_fill_dcache_m;
reg[9:0] i4_4_dcache_fill_addr_m;
reg i4_4_dva_svld_m;
reg[4:0] i4_4_dva_snp_addr_m;
reg[3:0] i4_4_dva_snp_set_vld_m;
reg[1:0] i4_4_dva_snp_wy0_m;
reg[1:0] i4_4_dva_snp_wy1_m;
reg[1:0] i4_4_dva_snp_wy2_m;
reg[1:0] i4_4_dva_snp_wy3_m;
reg i4_4_st_wr_dcache_w;
reg i4_4_fill_dcache_w;
reg[9:0] i4_4_dcache_fill_addr_w;
reg i4_4_dva_svld_w;
reg[4:0] i4_4_dva_snp_addr_w;
reg[3:0] i4_4_dva_snp_set_vld_w;
reg[1:0] i4_4_dva_snp_wy0_w;
reg[1:0] i4_4_dva_snp_wy1_w;
reg[1:0] i4_4_dva_snp_wy2_w;
reg[1:0] i4_4_dva_snp_wy3_w;
wire i4_4_spu_trap_ack_w;
wire i4_4_spu_illgl_va;
wire[3:0] i4_4_tick_match;
wire[3:0] i4_4_stick_match;
wire[3:0] i4_4_hstick_match;
wire i4_4_rstint_vld_w;
wire i4_4_hwint_vld_w;
wire i4_4_sftint_vld_w;
wire i4_4_hint_vld_w;
wire i4_4_trap;
wire[3:0] i4_4_ld_int;
wire i4_4_immu_miss;
wire i4_4_dmmu_miss;
wire[1:0] i4_4_cpx_tid;
wire i4_4_itlb_repl_vld;
wire i4_4_dtlb_repl_vld;
wire[63:0] i4_4_tlb_repl_vec;
wire[5:0] i4_4_tlb_repl_idx;
wire [`INTF0_WIDTH-1:0] i0_5_data;
wire i0_5_rdy;
wire [`INTF3_WIDTH-1:0] i3_5_data;
wire i3_5_rdy;
wire [`INTF4_WIDTH-1:0] i4_5_data;
wire i4_5_rdy;
wire [`INTF5_WIDTH-1:0] i5_5_data;
wire i5_5_rdy;
reg [1:0] i0_5_ifu_lsu_ldst_size_m;
reg [1:0] i0_5_ifu_lsu_ldst_size_g;
wire i0_5_asi_internal_g;
wire i0_5_asi_quad_g;
wire i0_5_asi_blk_g;
wire i0_5_asi_binit_g;
wire i0_5_dcache_hit_g;
wire i0_5_full_raw_g;
wire i0_5_partial_raw_g;
wire i0_5_ld_l2cache_rq;
wire i0_5_st_inst_vld_g;
wire i0_5_ld_inst_vld_g;
reg[3:0] i4_5_fprs_set_e;
reg[1:0] i4_5_new_fprs_e;
reg[3:0] i4_5_fprs_set_m;
reg[1:0] i4_5_new_fprs_m;
reg[3:0] i4_5_fprs_set_w;
reg[1:0] i4_5_new_fprs_w;
reg i4_5_rstint_w;
reg i4_5_hwint_w;
reg i4_5_sftint_w;
reg i4_5_hint_m;
reg i4_5_hint_w;
reg[3:0] i4_5_int_thr_w;
reg i4_5_ic_inv_vld_f;
reg i4_5_ic_inv_vld_s;
reg[5:0] i4_5_ic_inv_addr_f;
reg[5:0] i4_5_ic_inv_addr_s;
reg i4_5_ic_inv_word1_f;
reg i4_5_ic_inv_word1_s;
reg i4_5_ic_inv_word0_f;
reg i4_5_ic_inv_word0_s;
reg[1:0] i4_5_ic_inv_way1_f;
reg[1:0] i4_5_ic_inv_way1_s;
reg[1:0] i4_5_ic_inv_way0_f;
reg[1:0] i4_5_ic_inv_way0_s;
reg i4_5_st_wr_dcache_m;
reg i4_5_fill_dcache_m;
reg[9:0] i4_5_dcache_fill_addr_m;
reg i4_5_dva_svld_m;
reg[4:0] i4_5_dva_snp_addr_m;
reg[3:0] i4_5_dva_snp_set_vld_m;
reg[1:0] i4_5_dva_snp_wy0_m;
reg[1:0] i4_5_dva_snp_wy1_m;
reg[1:0] i4_5_dva_snp_wy2_m;
reg[1:0] i4_5_dva_snp_wy3_m;
reg i4_5_st_wr_dcache_w;
reg i4_5_fill_dcache_w;
reg[9:0] i4_5_dcache_fill_addr_w;
reg i4_5_dva_svld_w;
reg[4:0] i4_5_dva_snp_addr_w;
reg[3:0] i4_5_dva_snp_set_vld_w;
reg[1:0] i4_5_dva_snp_wy0_w;
reg[1:0] i4_5_dva_snp_wy1_w;
reg[1:0] i4_5_dva_snp_wy2_w;
reg[1:0] i4_5_dva_snp_wy3_w;
wire i4_5_spu_trap_ack_w;
wire i4_5_spu_illgl_va;
wire[3:0] i4_5_tick_match;
wire[3:0] i4_5_stick_match;
wire[3:0] i4_5_hstick_match;
wire i4_5_rstint_vld_w;
wire i4_5_hwint_vld_w;
wire i4_5_sftint_vld_w;
wire i4_5_hint_vld_w;
wire i4_5_trap;
wire[3:0] i4_5_ld_int;
wire i4_5_immu_miss;
wire i4_5_dmmu_miss;
wire[1:0] i4_5_cpx_tid;
wire i4_5_itlb_repl_vld;
wire i4_5_dtlb_repl_vld;
wire[63:0] i4_5_tlb_repl_vec;
wire[5:0] i4_5_tlb_repl_idx;
wire [`INTF0_WIDTH-1:0] i0_6_data;
wire i0_6_rdy;
wire [`INTF3_WIDTH-1:0] i3_6_data;
wire i3_6_rdy;
wire [`INTF4_WIDTH-1:0] i4_6_data;
wire i4_6_rdy;
wire [`INTF5_WIDTH-1:0] i5_6_data;
wire i5_6_rdy;
reg [1:0] i0_6_ifu_lsu_ldst_size_m;
reg [1:0] i0_6_ifu_lsu_ldst_size_g;
wire i0_6_asi_internal_g;
wire i0_6_asi_quad_g;
wire i0_6_asi_blk_g;
wire i0_6_asi_binit_g;
wire i0_6_dcache_hit_g;
wire i0_6_full_raw_g;
wire i0_6_partial_raw_g;
wire i0_6_ld_l2cache_rq;
wire i0_6_st_inst_vld_g;
wire i0_6_ld_inst_vld_g;
reg[3:0] i4_6_fprs_set_e;
reg[1:0] i4_6_new_fprs_e;
reg[3:0] i4_6_fprs_set_m;
reg[1:0] i4_6_new_fprs_m;
reg[3:0] i4_6_fprs_set_w;
reg[1:0] i4_6_new_fprs_w;
reg i4_6_rstint_w;
reg i4_6_hwint_w;
reg i4_6_sftint_w;
reg i4_6_hint_m;
reg i4_6_hint_w;
reg[3:0] i4_6_int_thr_w;
reg i4_6_ic_inv_vld_f;
reg i4_6_ic_inv_vld_s;
reg[5:0] i4_6_ic_inv_addr_f;
reg[5:0] i4_6_ic_inv_addr_s;
reg i4_6_ic_inv_word1_f;
reg i4_6_ic_inv_word1_s;
reg i4_6_ic_inv_word0_f;
reg i4_6_ic_inv_word0_s;
reg[1:0] i4_6_ic_inv_way1_f;
reg[1:0] i4_6_ic_inv_way1_s;
reg[1:0] i4_6_ic_inv_way0_f;
reg[1:0] i4_6_ic_inv_way0_s;
reg i4_6_st_wr_dcache_m;
reg i4_6_fill_dcache_m;
reg[9:0] i4_6_dcache_fill_addr_m;
reg i4_6_dva_svld_m;
reg[4:0] i4_6_dva_snp_addr_m;
reg[3:0] i4_6_dva_snp_set_vld_m;
reg[1:0] i4_6_dva_snp_wy0_m;
reg[1:0] i4_6_dva_snp_wy1_m;
reg[1:0] i4_6_dva_snp_wy2_m;
reg[1:0] i4_6_dva_snp_wy3_m;
reg i4_6_st_wr_dcache_w;
reg i4_6_fill_dcache_w;
reg[9:0] i4_6_dcache_fill_addr_w;
reg i4_6_dva_svld_w;
reg[4:0] i4_6_dva_snp_addr_w;
reg[3:0] i4_6_dva_snp_set_vld_w;
reg[1:0] i4_6_dva_snp_wy0_w;
reg[1:0] i4_6_dva_snp_wy1_w;
reg[1:0] i4_6_dva_snp_wy2_w;
reg[1:0] i4_6_dva_snp_wy3_w;
wire i4_6_spu_trap_ack_w;
wire i4_6_spu_illgl_va;
wire[3:0] i4_6_tick_match;
wire[3:0] i4_6_stick_match;
wire[3:0] i4_6_hstick_match;
wire i4_6_rstint_vld_w;
wire i4_6_hwint_vld_w;
wire i4_6_sftint_vld_w;
wire i4_6_hint_vld_w;
wire i4_6_trap;
wire[3:0] i4_6_ld_int;
wire i4_6_immu_miss;
wire i4_6_dmmu_miss;
wire[1:0] i4_6_cpx_tid;
wire i4_6_itlb_repl_vld;
wire i4_6_dtlb_repl_vld;
wire[63:0] i4_6_tlb_repl_vec;
wire[5:0] i4_6_tlb_repl_idx;
wire [`INTF0_WIDTH-1:0] i0_7_data;
wire i0_7_rdy;
wire [`INTF3_WIDTH-1:0] i3_7_data;
wire i3_7_rdy;
wire [`INTF4_WIDTH-1:0] i4_7_data;
wire i4_7_rdy;
wire [`INTF5_WIDTH-1:0] i5_7_data;
wire i5_7_rdy;
reg [1:0] i0_7_ifu_lsu_ldst_size_m;
reg [1:0] i0_7_ifu_lsu_ldst_size_g;
wire i0_7_asi_internal_g;
wire i0_7_asi_quad_g;
wire i0_7_asi_blk_g;
wire i0_7_asi_binit_g;
wire i0_7_dcache_hit_g;
wire i0_7_full_raw_g;
wire i0_7_partial_raw_g;
wire i0_7_ld_l2cache_rq;
wire i0_7_st_inst_vld_g;
wire i0_7_ld_inst_vld_g;
reg[3:0] i4_7_fprs_set_e;
reg[1:0] i4_7_new_fprs_e;
reg[3:0] i4_7_fprs_set_m;
reg[1:0] i4_7_new_fprs_m;
reg[3:0] i4_7_fprs_set_w;
reg[1:0] i4_7_new_fprs_w;
reg i4_7_rstint_w;
reg i4_7_hwint_w;
reg i4_7_sftint_w;
reg i4_7_hint_m;
reg i4_7_hint_w;
reg[3:0] i4_7_int_thr_w;
reg i4_7_ic_inv_vld_f;
reg i4_7_ic_inv_vld_s;
reg[5:0] i4_7_ic_inv_addr_f;
reg[5:0] i4_7_ic_inv_addr_s;
reg i4_7_ic_inv_word1_f;
reg i4_7_ic_inv_word1_s;
reg i4_7_ic_inv_word0_f;
reg i4_7_ic_inv_word0_s;
reg[1:0] i4_7_ic_inv_way1_f;
reg[1:0] i4_7_ic_inv_way1_s;
reg[1:0] i4_7_ic_inv_way0_f;
reg[1:0] i4_7_ic_inv_way0_s;
reg i4_7_st_wr_dcache_m;
reg i4_7_fill_dcache_m;
reg[9:0] i4_7_dcache_fill_addr_m;
reg i4_7_dva_svld_m;
reg[4:0] i4_7_dva_snp_addr_m;
reg[3:0] i4_7_dva_snp_set_vld_m;
reg[1:0] i4_7_dva_snp_wy0_m;
reg[1:0] i4_7_dva_snp_wy1_m;
reg[1:0] i4_7_dva_snp_wy2_m;
reg[1:0] i4_7_dva_snp_wy3_m;
reg i4_7_st_wr_dcache_w;
reg i4_7_fill_dcache_w;
reg[9:0] i4_7_dcache_fill_addr_w;
reg i4_7_dva_svld_w;
reg[4:0] i4_7_dva_snp_addr_w;
reg[3:0] i4_7_dva_snp_set_vld_w;
reg[1:0] i4_7_dva_snp_wy0_w;
reg[1:0] i4_7_dva_snp_wy1_w;
reg[1:0] i4_7_dva_snp_wy2_w;
reg[1:0] i4_7_dva_snp_wy3_w;
wire i4_7_spu_trap_ack_w;
wire i4_7_spu_illgl_va;
wire[3:0] i4_7_tick_match;
wire[3:0] i4_7_stick_match;
wire[3:0] i4_7_hstick_match;
wire i4_7_rstint_vld_w;
wire i4_7_hwint_vld_w;
wire i4_7_sftint_vld_w;
wire i4_7_hint_vld_w;
wire i4_7_trap;
wire[3:0] i4_7_ld_int;
wire i4_7_immu_miss;
wire i4_7_dmmu_miss;
wire[1:0] i4_7_cpx_tid;
wire i4_7_itlb_repl_vld;
wire i4_7_dtlb_repl_vld;
wire[63:0] i4_7_tlb_repl_vec;
wire[5:0] i4_7_tlb_repl_idx;
wire [`INTF1_WIDTH-1:0] i1_0_data;
wire i1_0_rdy;
wire [`INTF2_WIDTH-1:0] i2_0_data;
reg i2_0_rdy;
reg pcx_sctag0_data_rdy_px2;
reg[2:0] sctag0_cpuid_c8;
reg i2_0_hit_c4;
reg i2_0_hit_c5;
reg i2_0_hit_c6;
reg i2_0_hit_c7;
reg i2_0_hit_c8;
wire [`INTF1_WIDTH-1:0] i1_1_data;
wire i1_1_rdy;
wire [`INTF2_WIDTH-1:0] i2_1_data;
reg i2_1_rdy;
reg pcx_sctag1_data_rdy_px2;
reg[2:0] sctag1_cpuid_c8;
reg i2_1_hit_c4;
reg i2_1_hit_c5;
reg i2_1_hit_c6;
reg i2_1_hit_c7;
reg i2_1_hit_c8;
wire [`INTF1_WIDTH-1:0] i1_2_data;
wire i1_2_rdy;
wire [`INTF2_WIDTH-1:0] i2_2_data;
reg i2_2_rdy;
reg pcx_sctag2_data_rdy_px2;
reg[2:0] sctag2_cpuid_c8;
reg i2_2_hit_c4;
reg i2_2_hit_c5;
reg i2_2_hit_c6;
reg i2_2_hit_c7;
reg i2_2_hit_c8;
wire [`INTF1_WIDTH-1:0] i1_3_data;
wire i1_3_rdy;
wire [`INTF2_WIDTH-1:0] i2_3_data;
reg i2_3_rdy;
reg pcx_sctag3_data_rdy_px2;
reg[2:0] sctag3_cpuid_c8;
reg i2_3_hit_c4;
reg i2_3_hit_c5;
reg i2_3_hit_c6;
reg i2_3_hit_c7;
reg i2_3_hit_c8;
`ifdef SAS_DISABLE
`else
always @(posedge clk) begin
`ifdef RTL_SPARC0
i0_0_ifu_lsu_ldst_size_m <= #1 `TOP_DESIGN.sparc0.lsu.ifu_lsu_ldst_size_e[1:0];
i0_0_ifu_lsu_ldst_size_g <= #1 i0_0_ifu_lsu_ldst_size_m;
`endif //ifdef RTL_SPARC0
`ifdef RTL_SPARC1
i0_1_ifu_lsu_ldst_size_m <= #1 `TOP_DESIGN.sparc1.lsu.ifu_lsu_ldst_size_e[1:0];
i0_1_ifu_lsu_ldst_size_g <= #1 i0_1_ifu_lsu_ldst_size_m;
`endif //ifdef RTL_SPARC1
`ifdef RTL_SPARC2
i0_2_ifu_lsu_ldst_size_m <= #1 `TOP_DESIGN.sparc2.lsu.ifu_lsu_ldst_size_e[1:0];
i0_2_ifu_lsu_ldst_size_g <= #1 i0_2_ifu_lsu_ldst_size_m;
`endif //ifdef RTL_SPARC2
`ifdef RTL_SPARC3
i0_3_ifu_lsu_ldst_size_m <= #1 `TOP_DESIGN.sparc3.lsu.ifu_lsu_ldst_size_e[1:0];
i0_3_ifu_lsu_ldst_size_g <= #1 i0_3_ifu_lsu_ldst_size_m;
`endif //ifdef RTL_SPARC3
`ifdef RTL_SPARC4
i0_4_ifu_lsu_ldst_size_m <= #1 `TOP_DESIGN.sparc4.lsu.ifu_lsu_ldst_size_e[1:0];
i0_4_ifu_lsu_ldst_size_g <= #1 i0_4_ifu_lsu_ldst_size_m;
`endif //ifdef RTL_SPARC4
`ifdef RTL_SPARC5
i0_5_ifu_lsu_ldst_size_m <= #1 `TOP_DESIGN.sparc5.lsu.ifu_lsu_ldst_size_e[1:0];
i0_5_ifu_lsu_ldst_size_g <= #1 i0_5_ifu_lsu_ldst_size_m;
`endif //ifdef RTL_SPARC5
`ifdef RTL_SPARC6
i0_6_ifu_lsu_ldst_size_m <= #1 `TOP_DESIGN.sparc6.lsu.ifu_lsu_ldst_size_e[1:0];
i0_6_ifu_lsu_ldst_size_g <= #1 i0_6_ifu_lsu_ldst_size_m;
`endif //ifdef RTL_SPARC6
`ifdef RTL_SPARC7
i0_7_ifu_lsu_ldst_size_m <= #1 `TOP_DESIGN.sparc7.lsu.ifu_lsu_ldst_size_e[1:0];
i0_7_ifu_lsu_ldst_size_g <= #1 i0_7_ifu_lsu_ldst_size_m;
`endif //ifdef RTL_SPARC7
`ifdef ENV_SPARC1
i0_1_ifu_lsu_ldst_size_m <= #1 2'h0;
i0_1_ifu_lsu_ldst_size_g <= #1 2'h0;
`endif // !ifdef RTL_SPARC1
`ifdef ENV_SPARC2
i0_2_ifu_lsu_ldst_size_m <= #1 2'h0;
i0_2_ifu_lsu_ldst_size_g <= #1 2'h0;
`endif // !ifdef RTL_SPARC2
`ifdef ENV_SPARC3
i0_3_ifu_lsu_ldst_size_m <= #1 2'h0;
i0_3_ifu_lsu_ldst_size_g <= #1 2'h0;
`endif // !ifdef RTL_SPARC3
`ifdef ENV_SPARC4
i0_4_ifu_lsu_ldst_size_m <= #1 2'h0;
i0_4_ifu_lsu_ldst_size_g <= #1 2'h0;
`endif // !ifdef RTL_SPARC4
`ifdef ENV_SPARC5
i0_5_ifu_lsu_ldst_size_m <= #1 2'h0;
i0_5_ifu_lsu_ldst_size_g <= #1 2'h0;
`endif // !ifdef RTL_SPARC5
`ifdef ENV_SPARC6
i0_6_ifu_lsu_ldst_size_m <= #1 2'h0;
i0_6_ifu_lsu_ldst_size_g <= #1 2'h0;
`endif // !ifdef RTL_SPARC6
`ifdef ENV_SPARC7
i0_7_ifu_lsu_ldst_size_m <= #1 2'h0;
i0_7_ifu_lsu_ldst_size_g <= #1 2'h0;
`endif // !ifdef RTL_SPARC7
end // always @(posedge clk)
`ifdef RTL_SPARC0
assign i0_0_asi_internal_g = `TOP_DESIGN.sparc0.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc0.lsu.dctl.asi_internal_g;
assign i0_0_asi_quad_g = `TOP_DESIGN.sparc0.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc0.lsu.dctl.quad_asi_g;
assign i0_0_asi_blk_g = `TOP_DESIGN.sparc0.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc0.lsu.dctl.blk_asi_g;
assign i0_0_asi_binit_g = `TOP_DESIGN.sparc0.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc0.lsu.dctl.binit_quad_asi_g;
assign i0_0_dcache_hit_g= |(`TOP_DESIGN.sparc0.lsu.dtlb.cache_way_hit[3:0]);
assign i0_0_full_raw_g=
(|`TOP_DESIGN.sparc0.lsu.qctl1.stb_ld_full_raw[7:0]) &
~(`TOP_DESIGN.sparc0.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc0.lsu.qctl1.ldq_hit_g |
`TOP_DESIGN.sparc0.lsu.qctl1.io_ld);
assign i0_0_partial_raw_g=
(|`TOP_DESIGN.sparc0.lsu.qctl1.stb_ld_partial_raw[7:0]) |
`TOP_DESIGN.sparc0.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc0.lsu.qctl1.ldq_hit_g |
(`TOP_DESIGN.sparc0.lsu.qctl1.io_ld &
`TOP_DESIGN.sparc0.lsu.qctl1.stb_not_empty);
assign i0_0_ld_l2cache_rq=
(`TOP_DESIGN.sparc0.lsu.qctl1.ld0_l2cache_rq &
`TOP_DESIGN.sparc0.lsu.qctl1.thread0_g) |
(`TOP_DESIGN.sparc0.lsu.qctl1.ld1_l2cache_rq &
`TOP_DESIGN.sparc0.lsu.qctl1.thread1_g) |
(`TOP_DESIGN.sparc0.lsu.qctl1.ld2_l2cache_rq &
`TOP_DESIGN.sparc0.lsu.qctl1.thread2_g) |
(`TOP_DESIGN.sparc0.lsu.qctl1.ld3_l2cache_rq &
`TOP_DESIGN.sparc0.lsu.qctl1.thread3_g);
assign i0_0_ld_inst_vld_g =
`TOP_DESIGN.sparc0.lsu.dctl.ld_inst_vld_g &
~(|cmp_top.sas_tasks.task0.spc0_force_flush[3:0]);
assign i0_0_st_inst_vld_g =
`TOP_DESIGN.sparc0.lsu.dctl.st_inst_vld_g &
~`TOP_DESIGN.sparc0.lsu.stb_rwctl.ffu_lsu_kill_fst_w &
~(|cmp_top.sas_tasks.task0.spc0_force_flush[3:0]);
assign i0_0_data =
{1'b0,
1'b0,
1'b0,
1'b0,
i0_0_asi_internal_g,
i0_0_asi_quad_g,
i0_0_asi_blk_g,
i0_0_asi_binit_g,
`TOP_DESIGN.sparc0.lsu.dctl.ldd_force_l2access_g,
i0_0_ld_l2cache_rq,
i0_0_full_raw_g,
i0_0_partial_raw_g,
i0_0_dcache_hit_g,
i0_0_ifu_lsu_ldst_size_g[1:0],
`TOP_DESIGN.sparc0.lsu.dctl.ld_inst_vld_g,
i0_0_st_inst_vld_g,
`TOP_DESIGN.sparc0.lsu.qctl1.thread0_g,
`TOP_DESIGN.sparc0.lsu.qctl1.thread1_g,
`TOP_DESIGN.sparc0.lsu.qctl1.thread2_g,
`TOP_DESIGN.sparc0.lsu.qctl1.thread3_g,
`TOP_DESIGN.sparc0.lsu.dtlb.pgnum_g[29:0],
`TOP_DESIGN.sparc0.lsu.dctldp.ldst_va_g[9:0]};
assign i0_0_rdy =
(i0_0_ld_inst_vld_g |
i0_0_st_inst_vld_g);
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC1
assign i0_1_asi_internal_g = `TOP_DESIGN.sparc1.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc1.lsu.dctl.asi_internal_g;
assign i0_1_asi_quad_g = `TOP_DESIGN.sparc1.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc1.lsu.dctl.quad_asi_g;
assign i0_1_asi_blk_g = `TOP_DESIGN.sparc1.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc1.lsu.dctl.blk_asi_g;
assign i0_1_asi_binit_g = `TOP_DESIGN.sparc1.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc1.lsu.dctl.binit_quad_asi_g;
assign i0_1_dcache_hit_g= |(`TOP_DESIGN.sparc1.lsu.dtlb.cache_way_hit[3:0]);
assign i0_1_full_raw_g=
(|`TOP_DESIGN.sparc1.lsu.qctl1.stb_ld_full_raw[7:0]) &
~(`TOP_DESIGN.sparc1.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc1.lsu.qctl1.ldq_hit_g |
`TOP_DESIGN.sparc1.lsu.qctl1.io_ld);
assign i0_1_partial_raw_g=
(|`TOP_DESIGN.sparc1.lsu.qctl1.stb_ld_partial_raw[7:0]) |
`TOP_DESIGN.sparc1.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc1.lsu.qctl1.ldq_hit_g |
(`TOP_DESIGN.sparc1.lsu.qctl1.io_ld &
`TOP_DESIGN.sparc1.lsu.qctl1.stb_not_empty);
assign i0_1_ld_l2cache_rq=
(`TOP_DESIGN.sparc1.lsu.qctl1.ld0_l2cache_rq &
`TOP_DESIGN.sparc1.lsu.qctl1.thread0_g) |
(`TOP_DESIGN.sparc1.lsu.qctl1.ld1_l2cache_rq &
`TOP_DESIGN.sparc1.lsu.qctl1.thread1_g) |
(`TOP_DESIGN.sparc1.lsu.qctl1.ld2_l2cache_rq &
`TOP_DESIGN.sparc1.lsu.qctl1.thread2_g) |
(`TOP_DESIGN.sparc1.lsu.qctl1.ld3_l2cache_rq &
`TOP_DESIGN.sparc1.lsu.qctl1.thread3_g);
assign i0_1_ld_inst_vld_g =
`TOP_DESIGN.sparc1.lsu.dctl.ld_inst_vld_g &
~(|cmp_top.sas_tasks.task1.spc0_force_flush[3:0]);
assign i0_1_st_inst_vld_g =
`TOP_DESIGN.sparc1.lsu.dctl.st_inst_vld_g &
~`TOP_DESIGN.sparc1.lsu.stb_rwctl.ffu_lsu_kill_fst_w &
~(|cmp_top.sas_tasks.task1.spc0_force_flush[3:0]);
assign i0_1_data =
{1'b0,
1'b0,
1'b0,
1'b0,
i0_1_asi_internal_g,
i0_1_asi_quad_g,
i0_1_asi_blk_g,
i0_1_asi_binit_g,
`TOP_DESIGN.sparc1.lsu.dctl.ldd_force_l2access_g,
i0_1_ld_l2cache_rq,
i0_1_full_raw_g,
i0_1_partial_raw_g,
i0_1_dcache_hit_g,
i0_1_ifu_lsu_ldst_size_g[1:0],
`TOP_DESIGN.sparc1.lsu.dctl.ld_inst_vld_g,
i0_1_st_inst_vld_g,
`TOP_DESIGN.sparc1.lsu.qctl1.thread0_g,
`TOP_DESIGN.sparc1.lsu.qctl1.thread1_g,
`TOP_DESIGN.sparc1.lsu.qctl1.thread2_g,
`TOP_DESIGN.sparc1.lsu.qctl1.thread3_g,
`TOP_DESIGN.sparc1.lsu.dtlb.pgnum_g[29:0],
`TOP_DESIGN.sparc1.lsu.dctldp.ldst_va_g[9:0]};
assign i0_1_rdy =
(i0_1_ld_inst_vld_g |
i0_1_st_inst_vld_g);
`endif // ifdef RTL_SPARC1
`ifdef RTL_SPARC2
assign i0_2_asi_internal_g = `TOP_DESIGN.sparc2.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc2.lsu.dctl.asi_internal_g;
assign i0_2_asi_quad_g = `TOP_DESIGN.sparc2.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc2.lsu.dctl.quad_asi_g;
assign i0_2_asi_blk_g = `TOP_DESIGN.sparc2.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc2.lsu.dctl.blk_asi_g;
assign i0_2_asi_binit_g = `TOP_DESIGN.sparc2.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc2.lsu.dctl.binit_quad_asi_g;
assign i0_2_dcache_hit_g= |(`TOP_DESIGN.sparc2.lsu.dtlb.cache_way_hit[3:0]);
assign i0_2_full_raw_g=
(|`TOP_DESIGN.sparc2.lsu.qctl1.stb_ld_full_raw[7:0]) &
~(`TOP_DESIGN.sparc2.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc2.lsu.qctl1.ldq_hit_g |
`TOP_DESIGN.sparc2.lsu.qctl1.io_ld);
assign i0_2_partial_raw_g=
(|`TOP_DESIGN.sparc2.lsu.qctl1.stb_ld_partial_raw[7:0]) |
`TOP_DESIGN.sparc2.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc2.lsu.qctl1.ldq_hit_g |
(`TOP_DESIGN.sparc2.lsu.qctl1.io_ld &
`TOP_DESIGN.sparc2.lsu.qctl1.stb_not_empty);
assign i0_2_ld_l2cache_rq=
(`TOP_DESIGN.sparc2.lsu.qctl1.ld0_l2cache_rq &
`TOP_DESIGN.sparc2.lsu.qctl1.thread0_g) |
(`TOP_DESIGN.sparc2.lsu.qctl1.ld1_l2cache_rq &
`TOP_DESIGN.sparc2.lsu.qctl1.thread1_g) |
(`TOP_DESIGN.sparc2.lsu.qctl1.ld2_l2cache_rq &
`TOP_DESIGN.sparc2.lsu.qctl1.thread2_g) |
(`TOP_DESIGN.sparc2.lsu.qctl1.ld3_l2cache_rq &
`TOP_DESIGN.sparc2.lsu.qctl1.thread3_g);
assign i0_2_ld_inst_vld_g =
`TOP_DESIGN.sparc2.lsu.dctl.ld_inst_vld_g &
~(|cmp_top.sas_tasks.task2.spc0_force_flush[3:0]);
assign i0_2_st_inst_vld_g =
`TOP_DESIGN.sparc2.lsu.dctl.st_inst_vld_g &
~`TOP_DESIGN.sparc2.lsu.stb_rwctl.ffu_lsu_kill_fst_w &
~(|cmp_top.sas_tasks.task2.spc0_force_flush[3:0]);
assign i0_2_data =
{1'b0,
1'b0,
1'b0,
1'b0,
i0_2_asi_internal_g,
i0_2_asi_quad_g,
i0_2_asi_blk_g,
i0_2_asi_binit_g,
`TOP_DESIGN.sparc2.lsu.dctl.ldd_force_l2access_g,
i0_2_ld_l2cache_rq,
i0_2_full_raw_g,
i0_2_partial_raw_g,
i0_2_dcache_hit_g,
i0_2_ifu_lsu_ldst_size_g[1:0],
`TOP_DESIGN.sparc2.lsu.dctl.ld_inst_vld_g,
i0_2_st_inst_vld_g,
`TOP_DESIGN.sparc2.lsu.qctl1.thread0_g,
`TOP_DESIGN.sparc2.lsu.qctl1.thread1_g,
`TOP_DESIGN.sparc2.lsu.qctl1.thread2_g,
`TOP_DESIGN.sparc2.lsu.qctl1.thread3_g,
`TOP_DESIGN.sparc2.lsu.dtlb.pgnum_g[29:0],
`TOP_DESIGN.sparc2.lsu.dctldp.ldst_va_g[9:0]};
assign i0_2_rdy =
(i0_2_ld_inst_vld_g |
i0_2_st_inst_vld_g);
`endif // ifdef RTL_SPARC2
`ifdef RTL_SPARC3
assign i0_3_asi_internal_g = `TOP_DESIGN.sparc3.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc3.lsu.dctl.asi_internal_g;
assign i0_3_asi_quad_g = `TOP_DESIGN.sparc3.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc3.lsu.dctl.quad_asi_g;
assign i0_3_asi_blk_g = `TOP_DESIGN.sparc3.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc3.lsu.dctl.blk_asi_g;
assign i0_3_asi_binit_g = `TOP_DESIGN.sparc3.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc3.lsu.dctl.binit_quad_asi_g;
assign i0_3_dcache_hit_g= |(`TOP_DESIGN.sparc3.lsu.dtlb.cache_way_hit[3:0]);
assign i0_3_full_raw_g=
(|`TOP_DESIGN.sparc3.lsu.qctl1.stb_ld_full_raw[7:0]) &
~(`TOP_DESIGN.sparc3.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc3.lsu.qctl1.ldq_hit_g |
`TOP_DESIGN.sparc3.lsu.qctl1.io_ld);
assign i0_3_partial_raw_g=
(|`TOP_DESIGN.sparc3.lsu.qctl1.stb_ld_partial_raw[7:0]) |
`TOP_DESIGN.sparc3.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc3.lsu.qctl1.ldq_hit_g |
(`TOP_DESIGN.sparc3.lsu.qctl1.io_ld &
`TOP_DESIGN.sparc3.lsu.qctl1.stb_not_empty);
assign i0_3_ld_l2cache_rq=
(`TOP_DESIGN.sparc3.lsu.qctl1.ld0_l2cache_rq &
`TOP_DESIGN.sparc3.lsu.qctl1.thread0_g) |
(`TOP_DESIGN.sparc3.lsu.qctl1.ld1_l2cache_rq &
`TOP_DESIGN.sparc3.lsu.qctl1.thread1_g) |
(`TOP_DESIGN.sparc3.lsu.qctl1.ld2_l2cache_rq &
`TOP_DESIGN.sparc3.lsu.qctl1.thread2_g) |
(`TOP_DESIGN.sparc3.lsu.qctl1.ld3_l2cache_rq &
`TOP_DESIGN.sparc3.lsu.qctl1.thread3_g);
assign i0_3_ld_inst_vld_g =
`TOP_DESIGN.sparc3.lsu.dctl.ld_inst_vld_g &
~(|cmp_top.sas_tasks.task3.spc0_force_flush[3:0]);
assign i0_3_st_inst_vld_g =
`TOP_DESIGN.sparc3.lsu.dctl.st_inst_vld_g &
~`TOP_DESIGN.sparc3.lsu.stb_rwctl.ffu_lsu_kill_fst_w &
~(|cmp_top.sas_tasks.task3.spc0_force_flush[3:0]);
assign i0_3_data =
{1'b0,
1'b0,
1'b0,
1'b0,
i0_3_asi_internal_g,
i0_3_asi_quad_g,
i0_3_asi_blk_g,
i0_3_asi_binit_g,
`TOP_DESIGN.sparc3.lsu.dctl.ldd_force_l2access_g,
i0_3_ld_l2cache_rq,
i0_3_full_raw_g,
i0_3_partial_raw_g,
i0_3_dcache_hit_g,
i0_3_ifu_lsu_ldst_size_g[1:0],
`TOP_DESIGN.sparc3.lsu.dctl.ld_inst_vld_g,
i0_3_st_inst_vld_g,
`TOP_DESIGN.sparc3.lsu.qctl1.thread0_g,
`TOP_DESIGN.sparc3.lsu.qctl1.thread1_g,
`TOP_DESIGN.sparc3.lsu.qctl1.thread2_g,
`TOP_DESIGN.sparc3.lsu.qctl1.thread3_g,
`TOP_DESIGN.sparc3.lsu.dtlb.pgnum_g[29:0],
`TOP_DESIGN.sparc3.lsu.dctldp.ldst_va_g[9:0]};
assign i0_3_rdy =
(i0_3_ld_inst_vld_g |
i0_3_st_inst_vld_g);
`endif // ifdef RTL_SPARC3
`ifdef RTL_SPARC4
assign i0_4_asi_internal_g = `TOP_DESIGN.sparc4.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc4.lsu.dctl.asi_internal_g;
assign i0_4_asi_quad_g = `TOP_DESIGN.sparc4.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc4.lsu.dctl.quad_asi_g;
assign i0_4_asi_blk_g = `TOP_DESIGN.sparc4.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc4.lsu.dctl.blk_asi_g;
assign i0_4_asi_binit_g = `TOP_DESIGN.sparc4.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc4.lsu.dctl.binit_quad_asi_g;
assign i0_4_dcache_hit_g= |(`TOP_DESIGN.sparc4.lsu.dtlb.cache_way_hit[3:0]);
assign i0_4_full_raw_g=
(|`TOP_DESIGN.sparc4.lsu.qctl1.stb_ld_full_raw[7:0]) &
~(`TOP_DESIGN.sparc4.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc4.lsu.qctl1.ldq_hit_g |
`TOP_DESIGN.sparc4.lsu.qctl1.io_ld);
assign i0_4_partial_raw_g=
(|`TOP_DESIGN.sparc4.lsu.qctl1.stb_ld_partial_raw[7:0]) |
`TOP_DESIGN.sparc4.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc4.lsu.qctl1.ldq_hit_g |
(`TOP_DESIGN.sparc4.lsu.qctl1.io_ld &
`TOP_DESIGN.sparc4.lsu.qctl1.stb_not_empty);
assign i0_4_ld_l2cache_rq=
(`TOP_DESIGN.sparc4.lsu.qctl1.ld0_l2cache_rq &
`TOP_DESIGN.sparc4.lsu.qctl1.thread0_g) |
(`TOP_DESIGN.sparc4.lsu.qctl1.ld1_l2cache_rq &
`TOP_DESIGN.sparc4.lsu.qctl1.thread1_g) |
(`TOP_DESIGN.sparc4.lsu.qctl1.ld2_l2cache_rq &
`TOP_DESIGN.sparc4.lsu.qctl1.thread2_g) |
(`TOP_DESIGN.sparc4.lsu.qctl1.ld3_l2cache_rq &
`TOP_DESIGN.sparc4.lsu.qctl1.thread3_g);
assign i0_4_ld_inst_vld_g =
`TOP_DESIGN.sparc4.lsu.dctl.ld_inst_vld_g &
~(|cmp_top.sas_tasks.task4.spc0_force_flush[3:0]);
assign i0_4_st_inst_vld_g =
`TOP_DESIGN.sparc4.lsu.dctl.st_inst_vld_g &
~`TOP_DESIGN.sparc4.lsu.stb_rwctl.ffu_lsu_kill_fst_w &
~(|cmp_top.sas_tasks.task4.spc0_force_flush[3:0]);
assign i0_4_data =
{1'b0,
1'b0,
1'b0,
1'b0,
i0_4_asi_internal_g,
i0_4_asi_quad_g,
i0_4_asi_blk_g,
i0_4_asi_binit_g,
`TOP_DESIGN.sparc4.lsu.dctl.ldd_force_l2access_g,
i0_4_ld_l2cache_rq,
i0_4_full_raw_g,
i0_4_partial_raw_g,
i0_4_dcache_hit_g,
i0_4_ifu_lsu_ldst_size_g[1:0],
`TOP_DESIGN.sparc4.lsu.dctl.ld_inst_vld_g,
i0_4_st_inst_vld_g,
`TOP_DESIGN.sparc4.lsu.qctl1.thread0_g,
`TOP_DESIGN.sparc4.lsu.qctl1.thread1_g,
`TOP_DESIGN.sparc4.lsu.qctl1.thread2_g,
`TOP_DESIGN.sparc4.lsu.qctl1.thread3_g,
`TOP_DESIGN.sparc4.lsu.dtlb.pgnum_g[29:0],
`TOP_DESIGN.sparc4.lsu.dctldp.ldst_va_g[9:0]};
assign i0_4_rdy =
(i0_4_ld_inst_vld_g |
i0_4_st_inst_vld_g);
`endif // ifdef RTL_SPARC4
`ifdef RTL_SPARC5
assign i0_5_asi_internal_g = `TOP_DESIGN.sparc5.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc5.lsu.dctl.asi_internal_g;
assign i0_5_asi_quad_g = `TOP_DESIGN.sparc5.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc5.lsu.dctl.quad_asi_g;
assign i0_5_asi_blk_g = `TOP_DESIGN.sparc5.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc5.lsu.dctl.blk_asi_g;
assign i0_5_asi_binit_g = `TOP_DESIGN.sparc5.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc5.lsu.dctl.binit_quad_asi_g;
assign i0_5_dcache_hit_g= |(`TOP_DESIGN.sparc5.lsu.dtlb.cache_way_hit[3:0]);
assign i0_5_full_raw_g=
(|`TOP_DESIGN.sparc5.lsu.qctl1.stb_ld_full_raw[7:0]) &
~(`TOP_DESIGN.sparc5.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc5.lsu.qctl1.ldq_hit_g |
`TOP_DESIGN.sparc5.lsu.qctl1.io_ld);
assign i0_5_partial_raw_g=
(|`TOP_DESIGN.sparc5.lsu.qctl1.stb_ld_partial_raw[7:0]) |
`TOP_DESIGN.sparc5.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc5.lsu.qctl1.ldq_hit_g |
(`TOP_DESIGN.sparc5.lsu.qctl1.io_ld &
`TOP_DESIGN.sparc5.lsu.qctl1.stb_not_empty);
assign i0_5_ld_l2cache_rq=
(`TOP_DESIGN.sparc5.lsu.qctl1.ld0_l2cache_rq &
`TOP_DESIGN.sparc5.lsu.qctl1.thread0_g) |
(`TOP_DESIGN.sparc5.lsu.qctl1.ld1_l2cache_rq &
`TOP_DESIGN.sparc5.lsu.qctl1.thread1_g) |
(`TOP_DESIGN.sparc5.lsu.qctl1.ld2_l2cache_rq &
`TOP_DESIGN.sparc5.lsu.qctl1.thread2_g) |
(`TOP_DESIGN.sparc5.lsu.qctl1.ld3_l2cache_rq &
`TOP_DESIGN.sparc5.lsu.qctl1.thread3_g);
assign i0_5_ld_inst_vld_g =
`TOP_DESIGN.sparc5.lsu.dctl.ld_inst_vld_g &
~(|cmp_top.sas_tasks.task5.spc0_force_flush[3:0]);
assign i0_5_st_inst_vld_g =
`TOP_DESIGN.sparc5.lsu.dctl.st_inst_vld_g &
~`TOP_DESIGN.sparc5.lsu.stb_rwctl.ffu_lsu_kill_fst_w &
~(|cmp_top.sas_tasks.task5.spc0_force_flush[3:0]);
assign i0_5_data =
{1'b0,
1'b0,
1'b0,
1'b0,
i0_5_asi_internal_g,
i0_5_asi_quad_g,
i0_5_asi_blk_g,
i0_5_asi_binit_g,
`TOP_DESIGN.sparc5.lsu.dctl.ldd_force_l2access_g,
i0_5_ld_l2cache_rq,
i0_5_full_raw_g,
i0_5_partial_raw_g,
i0_5_dcache_hit_g,
i0_5_ifu_lsu_ldst_size_g[1:0],
`TOP_DESIGN.sparc5.lsu.dctl.ld_inst_vld_g,
i0_5_st_inst_vld_g,
`TOP_DESIGN.sparc5.lsu.qctl1.thread0_g,
`TOP_DESIGN.sparc5.lsu.qctl1.thread1_g,
`TOP_DESIGN.sparc5.lsu.qctl1.thread2_g,
`TOP_DESIGN.sparc5.lsu.qctl1.thread3_g,
`TOP_DESIGN.sparc5.lsu.dtlb.pgnum_g[29:0],
`TOP_DESIGN.sparc5.lsu.dctldp.ldst_va_g[9:0]};
assign i0_5_rdy =
(i0_5_ld_inst_vld_g |
i0_5_st_inst_vld_g);
`endif // ifdef RTL_SPARC5
`ifdef RTL_SPARC6
assign i0_6_asi_internal_g = `TOP_DESIGN.sparc6.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc6.lsu.dctl.asi_internal_g;
assign i0_6_asi_quad_g = `TOP_DESIGN.sparc6.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc6.lsu.dctl.quad_asi_g;
assign i0_6_asi_blk_g = `TOP_DESIGN.sparc6.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc6.lsu.dctl.blk_asi_g;
assign i0_6_asi_binit_g = `TOP_DESIGN.sparc6.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc6.lsu.dctl.binit_quad_asi_g;
assign i0_6_dcache_hit_g= |(`TOP_DESIGN.sparc6.lsu.dtlb.cache_way_hit[3:0]);
assign i0_6_full_raw_g=
(|`TOP_DESIGN.sparc6.lsu.qctl1.stb_ld_full_raw[7:0]) &
~(`TOP_DESIGN.sparc6.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc6.lsu.qctl1.ldq_hit_g |
`TOP_DESIGN.sparc6.lsu.qctl1.io_ld);
assign i0_6_partial_raw_g=
(|`TOP_DESIGN.sparc6.lsu.qctl1.stb_ld_partial_raw[7:0]) |
`TOP_DESIGN.sparc6.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc6.lsu.qctl1.ldq_hit_g |
(`TOP_DESIGN.sparc6.lsu.qctl1.io_ld &
`TOP_DESIGN.sparc6.lsu.qctl1.stb_not_empty);
assign i0_6_ld_l2cache_rq=
(`TOP_DESIGN.sparc6.lsu.qctl1.ld0_l2cache_rq &
`TOP_DESIGN.sparc6.lsu.qctl1.thread0_g) |
(`TOP_DESIGN.sparc6.lsu.qctl1.ld1_l2cache_rq &
`TOP_DESIGN.sparc6.lsu.qctl1.thread1_g) |
(`TOP_DESIGN.sparc6.lsu.qctl1.ld2_l2cache_rq &
`TOP_DESIGN.sparc6.lsu.qctl1.thread2_g) |
(`TOP_DESIGN.sparc6.lsu.qctl1.ld3_l2cache_rq &
`TOP_DESIGN.sparc6.lsu.qctl1.thread3_g);
assign i0_6_ld_inst_vld_g =
`TOP_DESIGN.sparc6.lsu.dctl.ld_inst_vld_g &
~(|cmp_top.sas_tasks.task6.spc0_force_flush[3:0]);
assign i0_6_st_inst_vld_g =
`TOP_DESIGN.sparc6.lsu.dctl.st_inst_vld_g &
~`TOP_DESIGN.sparc6.lsu.stb_rwctl.ffu_lsu_kill_fst_w &
~(|cmp_top.sas_tasks.task6.spc0_force_flush[3:0]);
assign i0_6_data =
{1'b0,
1'b0,
1'b0,
1'b0,
i0_6_asi_internal_g,
i0_6_asi_quad_g,
i0_6_asi_blk_g,
i0_6_asi_binit_g,
`TOP_DESIGN.sparc6.lsu.dctl.ldd_force_l2access_g,
i0_6_ld_l2cache_rq,
i0_6_full_raw_g,
i0_6_partial_raw_g,
i0_6_dcache_hit_g,
i0_6_ifu_lsu_ldst_size_g[1:0],
`TOP_DESIGN.sparc6.lsu.dctl.ld_inst_vld_g,
i0_6_st_inst_vld_g,
`TOP_DESIGN.sparc6.lsu.qctl1.thread0_g,
`TOP_DESIGN.sparc6.lsu.qctl1.thread1_g,
`TOP_DESIGN.sparc6.lsu.qctl1.thread2_g,
`TOP_DESIGN.sparc6.lsu.qctl1.thread3_g,
`TOP_DESIGN.sparc6.lsu.dtlb.pgnum_g[29:0],
`TOP_DESIGN.sparc6.lsu.dctldp.ldst_va_g[9:0]};
assign i0_6_rdy =
(i0_6_ld_inst_vld_g |
i0_6_st_inst_vld_g);
`endif // ifdef RTL_SPARC6
`ifdef RTL_SPARC7
assign i0_7_asi_internal_g = `TOP_DESIGN.sparc7.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc7.lsu.dctl.asi_internal_g;
assign i0_7_asi_quad_g = `TOP_DESIGN.sparc7.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc7.lsu.dctl.quad_asi_g;
assign i0_7_asi_blk_g = `TOP_DESIGN.sparc7.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc7.lsu.dctl.blk_asi_g;
assign i0_7_asi_binit_g = `TOP_DESIGN.sparc7.lsu.dctl.lsu_alt_space_g &
`TOP_DESIGN.sparc7.lsu.dctl.binit_quad_asi_g;
assign i0_7_dcache_hit_g= |(`TOP_DESIGN.sparc7.lsu.dtlb.cache_way_hit[3:0]);
assign i0_7_full_raw_g=
(|`TOP_DESIGN.sparc7.lsu.qctl1.stb_ld_full_raw[7:0]) &
~(`TOP_DESIGN.sparc7.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc7.lsu.qctl1.ldq_hit_g |
`TOP_DESIGN.sparc7.lsu.qctl1.io_ld);
assign i0_7_partial_raw_g=
(|`TOP_DESIGN.sparc7.lsu.qctl1.stb_ld_partial_raw[7:0]) |
`TOP_DESIGN.sparc7.lsu.qctl1.stb_cam_mhit |
`TOP_DESIGN.sparc7.lsu.qctl1.ldq_hit_g |
(`TOP_DESIGN.sparc7.lsu.qctl1.io_ld &
`TOP_DESIGN.sparc7.lsu.qctl1.stb_not_empty);
assign i0_7_ld_l2cache_rq=
(`TOP_DESIGN.sparc7.lsu.qctl1.ld0_l2cache_rq &
`TOP_DESIGN.sparc7.lsu.qctl1.thread0_g) |
(`TOP_DESIGN.sparc7.lsu.qctl1.ld1_l2cache_rq &
`TOP_DESIGN.sparc7.lsu.qctl1.thread1_g) |
(`TOP_DESIGN.sparc7.lsu.qctl1.ld2_l2cache_rq &
`TOP_DESIGN.sparc7.lsu.qctl1.thread2_g) |
(`TOP_DESIGN.sparc7.lsu.qctl1.ld3_l2cache_rq &
`TOP_DESIGN.sparc7.lsu.qctl1.thread3_g);
assign i0_7_ld_inst_vld_g =
`TOP_DESIGN.sparc7.lsu.dctl.ld_inst_vld_g &
~(|cmp_top.sas_tasks.task7.spc0_force_flush[3:0]);
assign i0_7_st_inst_vld_g =
`TOP_DESIGN.sparc7.lsu.dctl.st_inst_vld_g &
~`TOP_DESIGN.sparc7.lsu.stb_rwctl.ffu_lsu_kill_fst_w &
~(|cmp_top.sas_tasks.task7.spc0_force_flush[3:0]);
assign i0_7_data =
{1'b0,
1'b0,
1'b0,
1'b0,
i0_7_asi_internal_g,
i0_7_asi_quad_g,
i0_7_asi_blk_g,
i0_7_asi_binit_g,
`TOP_DESIGN.sparc7.lsu.dctl.ldd_force_l2access_g,
i0_7_ld_l2cache_rq,
i0_7_full_raw_g,
i0_7_partial_raw_g,
i0_7_dcache_hit_g,
i0_7_ifu_lsu_ldst_size_g[1:0],
`TOP_DESIGN.sparc7.lsu.dctl.ld_inst_vld_g,
i0_7_st_inst_vld_g,
`TOP_DESIGN.sparc7.lsu.qctl1.thread0_g,
`TOP_DESIGN.sparc7.lsu.qctl1.thread1_g,
`TOP_DESIGN.sparc7.lsu.qctl1.thread2_g,
`TOP_DESIGN.sparc7.lsu.qctl1.thread3_g,
`TOP_DESIGN.sparc7.lsu.dtlb.pgnum_g[29:0],
`TOP_DESIGN.sparc7.lsu.dctldp.ldst_va_g[9:0]};
assign i0_7_rdy =
(i0_7_ld_inst_vld_g |
i0_7_st_inst_vld_g);
`endif // ifdef RTL_SPARC7
`ifdef ENV_SPARC1
assign i0_1_data = 'h0;
assign i0_1_rdy = 'h0;
`endif // !ifdef RTL_SPARC1
`ifdef ENV_SPARC2
assign i0_2_data = 'h0;
assign i0_2_rdy = 'h0;
`endif // !ifdef RTL_SPARC2
`ifdef ENV_SPARC3
assign i0_3_data = 'h0;
assign i0_3_rdy = 'h0;
`endif // !ifdef RTL_SPARC3
`ifdef ENV_SPARC4
assign i0_4_data = 'h0;
assign i0_4_rdy = 'h0;
`endif // !ifdef RTL_SPARC4
`ifdef ENV_SPARC5
assign i0_5_data = 'h0;
assign i0_5_rdy = 'h0;
`endif // !ifdef RTL_SPARC5
`ifdef ENV_SPARC6
assign i0_6_data = 'h0;
assign i0_6_rdy = 'h0;
`endif // !ifdef RTL_SPARC6
`ifdef ENV_SPARC7
assign i0_7_data = 'h0;
assign i0_7_rdy = 'h0;
`endif // !ifdef RTL_SPARC7
`endif // ifdef SAS_DISABLE
`ifdef RTL_CCX
always @(posedge clk) begin
pcx_sctag0_data_rdy_px2 <= `TOP_MEMORY.ccx.pcx_sctag0_data_rdy_px1;
pcx_sctag1_data_rdy_px2 <= `TOP_MEMORY.ccx.pcx_sctag1_data_rdy_px1;
pcx_sctag2_data_rdy_px2 <= `TOP_MEMORY.ccx.pcx_sctag2_data_rdy_px1;
pcx_sctag3_data_rdy_px2 <= `TOP_MEMORY.ccx.pcx_sctag3_data_rdy_px1;
end
assign i1_0_data = `TOP_MEMORY.ccx.pcx_sctag0_data_px2;
assign i1_0_rdy = pcx_sctag0_data_rdy_px2;
assign i1_1_data = `TOP_MEMORY.ccx.pcx_sctag1_data_px2;
assign i1_1_rdy = pcx_sctag1_data_rdy_px2;
assign i1_2_data = `TOP_MEMORY.ccx.pcx_sctag2_data_px2;
assign i1_2_rdy = pcx_sctag2_data_rdy_px2;
assign i1_3_data = `TOP_MEMORY.ccx.pcx_sctag3_data_px2;
assign i1_3_rdy = pcx_sctag3_data_rdy_px2;
`endif // ifdef RTL_CCX
`ifdef RTL_SCTAG0
always @(posedge clk) begin
i2_0_rdy <= #1 |`TOP_MEMORY.sctag0.oqctl.req_out_c7;
i2_0_hit_c4 <= #1 `TOP_MEMORY.sctag0.arbctl.decdp_bis_inst_c3 &
(`TOP_MEMORY.sctag0.tagctl.tagctl_hit_c3 |
`TOP_MEMORY.sctag0.mbctl.fbctl_match_c3);
i2_0_hit_c5 <= #1 i2_0_hit_c4;
i2_0_hit_c6 <= #1 i2_0_hit_c5;
i2_0_hit_c7 <= #1 i2_0_hit_c6;
i2_0_hit_c8 <= #1 i2_0_hit_c7;
i2_1_rdy <= #1 |`TOP_MEMORY.sctag1.oqctl.req_out_c7;
i2_1_hit_c4 <= #1 `TOP_MEMORY.sctag1.arbctl.decdp_bis_inst_c3 &
(`TOP_MEMORY.sctag1.tagctl.tagctl_hit_c3 |
`TOP_MEMORY.sctag1.mbctl.fbctl_match_c3);
i2_1_hit_c5 <= #1 i2_1_hit_c4;
i2_1_hit_c6 <= #1 i2_1_hit_c5;
i2_1_hit_c7 <= #1 i2_1_hit_c6;
i2_1_hit_c8 <= #1 i2_1_hit_c7;
i2_2_rdy <= #1 |`TOP_MEMORY.sctag2.oqctl.req_out_c7;
i2_2_hit_c4 <= #1 `TOP_MEMORY.sctag2.arbctl.decdp_bis_inst_c3 &
(`TOP_MEMORY.sctag2.tagctl.tagctl_hit_c3 |
`TOP_MEMORY.sctag2.mbctl.fbctl_match_c3);
i2_2_hit_c5 <= #1 i2_2_hit_c4;
i2_2_hit_c6 <= #1 i2_2_hit_c5;
i2_2_hit_c7 <= #1 i2_2_hit_c6;
i2_2_hit_c8 <= #1 i2_2_hit_c7;
i2_3_rdy <= #1 |`TOP_MEMORY.sctag3.oqctl.req_out_c7;
i2_3_hit_c4 <= #1 `TOP_MEMORY.sctag3.arbctl.decdp_bis_inst_c3 &
(`TOP_MEMORY.sctag3.tagctl.tagctl_hit_c3 |
`TOP_MEMORY.sctag3.mbctl.fbctl_match_c3);
i2_3_hit_c5 <= #1 i2_3_hit_c4;
i2_3_hit_c6 <= #1 i2_3_hit_c5;
i2_3_hit_c7 <= #1 i2_3_hit_c6;
i2_3_hit_c8 <= #1 i2_3_hit_c7;
end // always @(posedge clk)
assign i2_0_data = {`TOP_MEMORY.sctag0.arbaddrdp.arbdp_addr_c8[39:0],
1'b0,
1'b0,
1'b0,
i2_0_hit_c8,
`TOP_MEMORY.sctag0.oqdp.cpuid_c8, // C8 signal
`TOP_MEMORY.sctag0.oqdp.oq_array_data_in[144:0]};
assign i2_1_data = {`TOP_MEMORY.sctag1.arbaddrdp.arbdp_addr_c8[39:0],
1'b0,
1'b0,
1'b0,
i2_1_hit_c8,
`TOP_MEMORY.sctag1.oqdp.cpuid_c8, // C8 signal
`TOP_MEMORY.sctag1.oqdp.oq_array_data_in[144:0]};
assign i2_2_data = {`TOP_MEMORY.sctag2.arbaddrdp.arbdp_addr_c8[39:0],
1'b0,
1'b0,
1'b0,
i2_2_hit_c8,
`TOP_MEMORY.sctag2.oqdp.cpuid_c8, // C8 signal
`TOP_MEMORY.sctag2.oqdp.oq_array_data_in[144:0]};
assign i2_3_data = {`TOP_MEMORY.sctag3.arbaddrdp.arbdp_addr_c8[39:0],
1'b0,
1'b0,
1'b0,
i2_3_hit_c8,
`TOP_MEMORY.sctag3.oqdp.cpuid_c8, // C8 signal
`TOP_MEMORY.sctag3.oqdp.oq_array_data_in[144:0]};
`endif // ifdef SCTAG0
`ifdef RTL_CCX
assign i3_0_data = `TOP_MEMORY.ccx.cpx_spc0_data_cx2;
assign i3_0_rdy = `TOP_MEMORY.ccx.cpx_spc0_data_cx2[144];
assign i3_1_data = `TOP_MEMORY.ccx.cpx_spc1_data_cx2;
assign i3_1_rdy = `TOP_MEMORY.ccx.cpx_spc1_data_cx2[144];
assign i3_2_data = `TOP_MEMORY.ccx.cpx_spc2_data_cx2;
assign i3_2_rdy = `TOP_MEMORY.ccx.cpx_spc2_data_cx2[144];
assign i3_3_data = `TOP_MEMORY.ccx.cpx_spc3_data_cx2;
assign i3_3_rdy = `TOP_MEMORY.ccx.cpx_spc3_data_cx2[144];
assign i3_4_data = `TOP_MEMORY.ccx.cpx_spc4_data_cx2;
assign i3_4_rdy = `TOP_MEMORY.ccx.cpx_spc4_data_cx2[144];
assign i3_5_data = `TOP_MEMORY.ccx.cpx_spc5_data_cx2;
assign i3_5_rdy = `TOP_MEMORY.ccx.cpx_spc5_data_cx2[144];
assign i3_6_data = `TOP_MEMORY.ccx.cpx_spc6_data_cx2;
assign i3_6_rdy = `TOP_MEMORY.ccx.cpx_spc6_data_cx2[144];
assign i3_7_data = `TOP_MEMORY.ccx.cpx_spc7_data_cx2;
assign i3_7_rdy = `TOP_MEMORY.ccx.cpx_spc7_data_cx2[144];
`endif // ifdef RTL_CCX
`ifdef SAS_DISABLE
`else
always @(posedge clk) begin
`ifdef RTL_SPARC0
i4_0_fprs_set_e <= #1 `TOP_DESIGN.sparc0.ifu.swl.fprs_sel_set;
i4_0_new_fprs_e <= #1 `TOP_DESIGN.sparc0.ifu.swl.new_fprs;
i4_0_fprs_set_m <= #1 i4_0_fprs_set_e;
i4_0_new_fprs_m <= #1 i4_0_new_fprs_e;
i4_0_fprs_set_w <= #1 i4_0_fprs_set_m;
i4_0_new_fprs_w <= #1 i4_0_new_fprs_m;
i4_0_rstint_w <= #1 `TOP_DESIGN.sparc0.ifu.fcl.ifu_tlu_rstint_m;
i4_0_hwint_w <= #1 `TOP_DESIGN.sparc0.ifu.fcl.ifu_tlu_hwint_m;
i4_0_sftint_w <= #1 `TOP_DESIGN.sparc0.ifu.fcl.ifu_tlu_sftint_m;
i4_0_hint_m <= #1 `TOP_DESIGN.sparc0.ifu.fcl.ttype_sel_hstk_cmp_e;
i4_0_hint_w <= #1 i4_0_hint_m & `TOP_DESIGN.sparc0.ifu.fcl.ifu_tlu_ttype_vld_m;
i4_0_int_thr_w <= #1 `TOP_DESIGN.sparc0.ifu.fcl.thr_m;
i4_0_ic_inv_vld_f <= #1 `TOP_DESIGN.sparc0.ifu.invctl.stpkt_i2 &
`TOP_DESIGN.sparc0.ifu.invctl.invalidate_i2 &
`TOP_DESIGN.sparc0.ifu.invctl.icvidx_sel_inv_i2;
i4_0_ic_inv_addr_f <= #1 `TOP_DESIGN.sparc0.ifu.invctl.inv_addr_i2[11:6];
i4_0_ic_inv_word1_f <= #1 `TOP_DESIGN.sparc0.ifu.invctl.word1_inv_i2;
i4_0_ic_inv_word0_f <= #1 `TOP_DESIGN.sparc0.ifu.invctl.word0_inv_i2;
i4_0_ic_inv_way1_f <= #1 `TOP_DESIGN.sparc0.ifu.invctl.invwd1_way_i2;
i4_0_ic_inv_way0_f <= #1 `TOP_DESIGN.sparc0.ifu.invctl.invwd0_way_i2;
i4_0_ic_inv_vld_s <= #1 i4_0_ic_inv_vld_f;
i4_0_ic_inv_addr_s <= #1 i4_0_ic_inv_addr_f;
i4_0_ic_inv_word1_s <= #1 i4_0_ic_inv_word1_f;
i4_0_ic_inv_word0_s <= #1 i4_0_ic_inv_word0_f;
i4_0_ic_inv_way1_s <= #1 i4_0_ic_inv_way1_f;
i4_0_ic_inv_way0_s <= #1 i4_0_ic_inv_way0_f;
i4_0_st_wr_dcache_m <= #1 `TOP_DESIGN.sparc0.lsu.lsu_st_wr_dcache;
i4_0_fill_dcache_m <= #1 `TOP_DESIGN.sparc0.lsu.lsu_dcache_wr_vld_e & ~`TOP_DESIGN.sparc0.lsu.lsu_st_wr_dcache;
i4_0_dcache_fill_addr_m <= #1 `TOP_DESIGN.sparc0.lsu.dctl.dcache_fill_addr_e;
i4_0_dva_svld_m <= #1 `TOP_DESIGN.sparc0.lsu.qctl2.dva_svld_e &
(`TOP_DESIGN.sparc0.lsu.qdp2.dfq_byp_ff_data[143:140]=='h4) &
~(`TOP_DESIGN.sparc0.lsu.qctl2.memref_e &
`TOP_DESIGN.sparc0.lsu.qctl2.dfq_st_vld &
`TOP_DESIGN.sparc0.lsu.qctl2.dfq_local_inv &
`TOP_DESIGN.sparc0.lsu.qctl2.lsu_cpx_pkt_atomic);
i4_0_dva_snp_addr_m <= #1 `TOP_DESIGN.sparc0.lsu.qctl2.dva_snp_addr_e;
i4_0_dva_snp_set_vld_m <= #1 `TOP_DESIGN.sparc0.lsu.qctl2.dva_snp_set_vld_e;
i4_0_dva_snp_wy0_m <= #1 `TOP_DESIGN.sparc0.lsu.qctl2.dva_snp_wy0_e;
i4_0_dva_snp_wy1_m <= #1 `TOP_DESIGN.sparc0.lsu.qctl2.dva_snp_wy1_e;
i4_0_dva_snp_wy2_m <= #1 `TOP_DESIGN.sparc0.lsu.qctl2.dva_snp_wy2_e;
i4_0_dva_snp_wy3_m <= #1 `TOP_DESIGN.sparc0.lsu.qctl2.dva_snp_wy3_e;
i4_0_st_wr_dcache_w <= #1 i4_0_st_wr_dcache_m;
i4_0_fill_dcache_w <= #1 i4_0_fill_dcache_m;
i4_0_dcache_fill_addr_w <= #1 i4_0_dcache_fill_addr_m;
i4_0_dva_svld_w <= #1 i4_0_dva_svld_m;
i4_0_dva_snp_addr_w <= #1 i4_0_dva_snp_addr_m;
i4_0_dva_snp_set_vld_w <= #1 i4_0_dva_snp_set_vld_m;
i4_0_dva_snp_wy0_w <= #1 i4_0_dva_snp_wy0_m;
i4_0_dva_snp_wy1_w <= #1 i4_0_dva_snp_wy1_m;
i4_0_dva_snp_wy2_w <= #1 i4_0_dva_snp_wy2_m;
i4_0_dva_snp_wy3_w <= #1 i4_0_dva_snp_wy3_m;
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC1
i4_1_fprs_set_e <= #1 `TOP_DESIGN.sparc1.ifu.swl.fprs_sel_set;
i4_1_new_fprs_e <= #1 `TOP_DESIGN.sparc1.ifu.swl.new_fprs;
i4_1_fprs_set_m <= #1 i4_1_fprs_set_e;
i4_1_new_fprs_m <= #1 i4_1_new_fprs_e;
i4_1_fprs_set_w <= #1 i4_1_fprs_set_m;
i4_1_new_fprs_w <= #1 i4_1_new_fprs_m;
i4_1_rstint_w <= #1 `TOP_DESIGN.sparc1.ifu.fcl.ifu_tlu_rstint_m;
i4_1_hwint_w <= #1 `TOP_DESIGN.sparc1.ifu.fcl.ifu_tlu_hwint_m;
i4_1_sftint_w <= #1 `TOP_DESIGN.sparc1.ifu.fcl.ifu_tlu_sftint_m;
i4_1_hint_m <= #1 `TOP_DESIGN.sparc1.ifu.fcl.ttype_sel_hstk_cmp_e;
i4_1_hint_w <= #1 i4_1_hint_m & `TOP_DESIGN.sparc1.ifu.fcl.ifu_tlu_ttype_vld_m;
i4_1_int_thr_w <= #1 `TOP_DESIGN.sparc1.ifu.fcl.thr_m;
i4_1_ic_inv_vld_f <= #1 `TOP_DESIGN.sparc1.ifu.invctl.stpkt_i2 &
`TOP_DESIGN.sparc1.ifu.invctl.invalidate_i2 &
`TOP_DESIGN.sparc1.ifu.invctl.icvidx_sel_inv_i2;
i4_1_ic_inv_addr_f <= #1 `TOP_DESIGN.sparc1.ifu.invctl.inv_addr_i2[11:6];
i4_1_ic_inv_word1_f <= #1 `TOP_DESIGN.sparc1.ifu.invctl.word1_inv_i2;
i4_1_ic_inv_word0_f <= #1 `TOP_DESIGN.sparc1.ifu.invctl.word0_inv_i2;
i4_1_ic_inv_way1_f <= #1 `TOP_DESIGN.sparc1.ifu.invctl.invwd1_way_i2;
i4_1_ic_inv_way0_f <= #1 `TOP_DESIGN.sparc1.ifu.invctl.invwd0_way_i2;
i4_1_ic_inv_vld_s <= #1 i4_1_ic_inv_vld_f;
i4_1_ic_inv_addr_s <= #1 i4_1_ic_inv_addr_f;
i4_1_ic_inv_word1_s <= #1 i4_1_ic_inv_word1_f;
i4_1_ic_inv_word0_s <= #1 i4_1_ic_inv_word0_f;
i4_1_ic_inv_way1_s <= #1 i4_1_ic_inv_way1_f;
i4_1_ic_inv_way0_s <= #1 i4_1_ic_inv_way0_f;
i4_1_st_wr_dcache_m <= #1 `TOP_DESIGN.sparc1.lsu.lsu_st_wr_dcache;
i4_1_fill_dcache_m <= #1 `TOP_DESIGN.sparc1.lsu.lsu_dcache_wr_vld_e & ~`TOP_DESIGN.sparc1.lsu.lsu_st_wr_dcache;
i4_1_dcache_fill_addr_m <= #1 `TOP_DESIGN.sparc1.lsu.dctl.dcache_fill_addr_e;
i4_1_dva_svld_m <= #1 `TOP_DESIGN.sparc1.lsu.qctl2.dva_svld_e &
(`TOP_DESIGN.sparc1.lsu.qdp2.dfq_byp_ff_data[143:140]=='h4) &
~(`TOP_DESIGN.sparc1.lsu.qctl2.memref_e &
`TOP_DESIGN.sparc1.lsu.qctl2.dfq_st_vld &
`TOP_DESIGN.sparc1.lsu.qctl2.dfq_local_inv &
`TOP_DESIGN.sparc1.lsu.qctl2.lsu_cpx_pkt_atomic);
i4_1_dva_snp_addr_m <= #1 `TOP_DESIGN.sparc1.lsu.qctl2.dva_snp_addr_e;
i4_1_dva_snp_set_vld_m <= #1 `TOP_DESIGN.sparc1.lsu.qctl2.dva_snp_set_vld_e;
i4_1_dva_snp_wy0_m <= #1 `TOP_DESIGN.sparc1.lsu.qctl2.dva_snp_wy0_e;
i4_1_dva_snp_wy1_m <= #1 `TOP_DESIGN.sparc1.lsu.qctl2.dva_snp_wy1_e;
i4_1_dva_snp_wy2_m <= #1 `TOP_DESIGN.sparc1.lsu.qctl2.dva_snp_wy2_e;
i4_1_dva_snp_wy3_m <= #1 `TOP_DESIGN.sparc1.lsu.qctl2.dva_snp_wy3_e;
i4_1_st_wr_dcache_w <= #1 i4_1_st_wr_dcache_m;
i4_1_fill_dcache_w <= #1 i4_1_fill_dcache_m;
i4_1_dcache_fill_addr_w <= #1 i4_1_dcache_fill_addr_m;
i4_1_dva_svld_w <= #1 i4_1_dva_svld_m;
i4_1_dva_snp_addr_w <= #1 i4_1_dva_snp_addr_m;
i4_1_dva_snp_set_vld_w <= #1 i4_1_dva_snp_set_vld_m;
i4_1_dva_snp_wy0_w <= #1 i4_1_dva_snp_wy0_m;
i4_1_dva_snp_wy1_w <= #1 i4_1_dva_snp_wy1_m;
i4_1_dva_snp_wy2_w <= #1 i4_1_dva_snp_wy2_m;
i4_1_dva_snp_wy3_w <= #1 i4_1_dva_snp_wy3_m;
`endif // ifdef RTL_SPARC1
`ifdef RTL_SPARC2
i4_2_fprs_set_e <= #1 `TOP_DESIGN.sparc2.ifu.swl.fprs_sel_set;
i4_2_new_fprs_e <= #1 `TOP_DESIGN.sparc2.ifu.swl.new_fprs;
i4_2_fprs_set_m <= #1 i4_2_fprs_set_e;
i4_2_new_fprs_m <= #1 i4_2_new_fprs_e;
i4_2_fprs_set_w <= #1 i4_2_fprs_set_m;
i4_2_new_fprs_w <= #1 i4_2_new_fprs_m;
i4_2_rstint_w <= #1 `TOP_DESIGN.sparc2.ifu.fcl.ifu_tlu_rstint_m;
i4_2_hwint_w <= #1 `TOP_DESIGN.sparc2.ifu.fcl.ifu_tlu_hwint_m;
i4_2_sftint_w <= #1 `TOP_DESIGN.sparc2.ifu.fcl.ifu_tlu_sftint_m;
i4_2_hint_m <= #1 `TOP_DESIGN.sparc2.ifu.fcl.ttype_sel_hstk_cmp_e;
i4_2_hint_w <= #1 i4_2_hint_m & `TOP_DESIGN.sparc2.ifu.fcl.ifu_tlu_ttype_vld_m;
i4_2_int_thr_w <= #1 `TOP_DESIGN.sparc2.ifu.fcl.thr_m;
i4_2_ic_inv_vld_f <= #1 `TOP_DESIGN.sparc2.ifu.invctl.stpkt_i2 &
`TOP_DESIGN.sparc2.ifu.invctl.invalidate_i2 &
`TOP_DESIGN.sparc2.ifu.invctl.icvidx_sel_inv_i2;
i4_2_ic_inv_addr_f <= #1 `TOP_DESIGN.sparc2.ifu.invctl.inv_addr_i2[11:6];
i4_2_ic_inv_word1_f <= #1 `TOP_DESIGN.sparc2.ifu.invctl.word1_inv_i2;
i4_2_ic_inv_word0_f <= #1 `TOP_DESIGN.sparc2.ifu.invctl.word0_inv_i2;
i4_2_ic_inv_way1_f <= #1 `TOP_DESIGN.sparc2.ifu.invctl.invwd1_way_i2;
i4_2_ic_inv_way0_f <= #1 `TOP_DESIGN.sparc2.ifu.invctl.invwd0_way_i2;
i4_2_ic_inv_vld_s <= #1 i4_2_ic_inv_vld_f;
i4_2_ic_inv_addr_s <= #1 i4_2_ic_inv_addr_f;
i4_2_ic_inv_word1_s <= #1 i4_2_ic_inv_word1_f;
i4_2_ic_inv_word0_s <= #1 i4_2_ic_inv_word0_f;
i4_2_ic_inv_way1_s <= #1 i4_2_ic_inv_way1_f;
i4_2_ic_inv_way0_s <= #1 i4_2_ic_inv_way0_f;
i4_2_st_wr_dcache_m <= #1 `TOP_DESIGN.sparc2.lsu.lsu_st_wr_dcache;
i4_2_fill_dcache_m <= #1 `TOP_DESIGN.sparc2.lsu.lsu_dcache_wr_vld_e & ~`TOP_DESIGN.sparc2.lsu.lsu_st_wr_dcache;
i4_2_dcache_fill_addr_m <= #1 `TOP_DESIGN.sparc2.lsu.dctl.dcache_fill_addr_e;
i4_2_dva_svld_m <= #1 `TOP_DESIGN.sparc2.lsu.qctl2.dva_svld_e &
(`TOP_DESIGN.sparc2.lsu.qdp2.dfq_byp_ff_data[143:140]=='h4) &
~(`TOP_DESIGN.sparc2.lsu.qctl2.memref_e &
`TOP_DESIGN.sparc2.lsu.qctl2.dfq_st_vld &
`TOP_DESIGN.sparc2.lsu.qctl2.dfq_local_inv &
`TOP_DESIGN.sparc2.lsu.qctl2.lsu_cpx_pkt_atomic);
i4_2_dva_snp_addr_m <= #1 `TOP_DESIGN.sparc2.lsu.qctl2.dva_snp_addr_e;
i4_2_dva_snp_set_vld_m <= #1 `TOP_DESIGN.sparc2.lsu.qctl2.dva_snp_set_vld_e;
i4_2_dva_snp_wy0_m <= #1 `TOP_DESIGN.sparc2.lsu.qctl2.dva_snp_wy0_e;
i4_2_dva_snp_wy1_m <= #1 `TOP_DESIGN.sparc2.lsu.qctl2.dva_snp_wy1_e;
i4_2_dva_snp_wy2_m <= #1 `TOP_DESIGN.sparc2.lsu.qctl2.dva_snp_wy2_e;
i4_2_dva_snp_wy3_m <= #1 `TOP_DESIGN.sparc2.lsu.qctl2.dva_snp_wy3_e;
i4_2_st_wr_dcache_w <= #1 i4_2_st_wr_dcache_m;
i4_2_fill_dcache_w <= #1 i4_2_fill_dcache_m;
i4_2_dcache_fill_addr_w <= #1 i4_2_dcache_fill_addr_m;
i4_2_dva_svld_w <= #1 i4_2_dva_svld_m;
i4_2_dva_snp_addr_w <= #1 i4_2_dva_snp_addr_m;
i4_2_dva_snp_set_vld_w <= #1 i4_2_dva_snp_set_vld_m;
i4_2_dva_snp_wy0_w <= #1 i4_2_dva_snp_wy0_m;
i4_2_dva_snp_wy1_w <= #1 i4_2_dva_snp_wy1_m;
i4_2_dva_snp_wy2_w <= #1 i4_2_dva_snp_wy2_m;
i4_2_dva_snp_wy3_w <= #1 i4_2_dva_snp_wy3_m;
`endif // ifdef RTL_SPARC2
`ifdef RTL_SPARC3
i4_3_fprs_set_e <= #1 `TOP_DESIGN.sparc3.ifu.swl.fprs_sel_set;
i4_3_new_fprs_e <= #1 `TOP_DESIGN.sparc3.ifu.swl.new_fprs;
i4_3_fprs_set_m <= #1 i4_3_fprs_set_e;
i4_3_new_fprs_m <= #1 i4_3_new_fprs_e;
i4_3_fprs_set_w <= #1 i4_3_fprs_set_m;
i4_3_new_fprs_w <= #1 i4_3_new_fprs_m;
i4_3_rstint_w <= #1 `TOP_DESIGN.sparc3.ifu.fcl.ifu_tlu_rstint_m;
i4_3_hwint_w <= #1 `TOP_DESIGN.sparc3.ifu.fcl.ifu_tlu_hwint_m;
i4_3_sftint_w <= #1 `TOP_DESIGN.sparc3.ifu.fcl.ifu_tlu_sftint_m;
i4_3_hint_m <= #1 `TOP_DESIGN.sparc3.ifu.fcl.ttype_sel_hstk_cmp_e;
i4_3_hint_w <= #1 i4_3_hint_m & `TOP_DESIGN.sparc3.ifu.fcl.ifu_tlu_ttype_vld_m;
i4_3_int_thr_w <= #1 `TOP_DESIGN.sparc3.ifu.fcl.thr_m;
i4_3_ic_inv_vld_f <= #1 `TOP_DESIGN.sparc3.ifu.invctl.stpkt_i2 &
`TOP_DESIGN.sparc3.ifu.invctl.invalidate_i2 &
`TOP_DESIGN.sparc3.ifu.invctl.icvidx_sel_inv_i2;
i4_3_ic_inv_addr_f <= #1 `TOP_DESIGN.sparc3.ifu.invctl.inv_addr_i2[11:6];
i4_3_ic_inv_word1_f <= #1 `TOP_DESIGN.sparc3.ifu.invctl.word1_inv_i2;
i4_3_ic_inv_word0_f <= #1 `TOP_DESIGN.sparc3.ifu.invctl.word0_inv_i2;
i4_3_ic_inv_way1_f <= #1 `TOP_DESIGN.sparc3.ifu.invctl.invwd1_way_i2;
i4_3_ic_inv_way0_f <= #1 `TOP_DESIGN.sparc3.ifu.invctl.invwd0_way_i2;
i4_3_ic_inv_vld_s <= #1 i4_3_ic_inv_vld_f;
i4_3_ic_inv_addr_s <= #1 i4_3_ic_inv_addr_f;
i4_3_ic_inv_word1_s <= #1 i4_3_ic_inv_word1_f;
i4_3_ic_inv_word0_s <= #1 i4_3_ic_inv_word0_f;
i4_3_ic_inv_way1_s <= #1 i4_3_ic_inv_way1_f;
i4_3_ic_inv_way0_s <= #1 i4_3_ic_inv_way0_f;
i4_3_st_wr_dcache_m <= #1 `TOP_DESIGN.sparc3.lsu.lsu_st_wr_dcache;
i4_3_fill_dcache_m <= #1 `TOP_DESIGN.sparc3.lsu.lsu_dcache_wr_vld_e & ~`TOP_DESIGN.sparc3.lsu.lsu_st_wr_dcache;
i4_3_dcache_fill_addr_m <= #1 `TOP_DESIGN.sparc3.lsu.dctl.dcache_fill_addr_e;
i4_3_dva_svld_m <= #1 `TOP_DESIGN.sparc3.lsu.qctl2.dva_svld_e &
(`TOP_DESIGN.sparc3.lsu.qdp2.dfq_byp_ff_data[143:140]=='h4) &
~(`TOP_DESIGN.sparc3.lsu.qctl2.memref_e &
`TOP_DESIGN.sparc3.lsu.qctl2.dfq_st_vld &
`TOP_DESIGN.sparc3.lsu.qctl2.dfq_local_inv &
`TOP_DESIGN.sparc3.lsu.qctl2.lsu_cpx_pkt_atomic);
i4_3_dva_snp_addr_m <= #1 `TOP_DESIGN.sparc3.lsu.qctl2.dva_snp_addr_e;
i4_3_dva_snp_set_vld_m <= #1 `TOP_DESIGN.sparc3.lsu.qctl2.dva_snp_set_vld_e;
i4_3_dva_snp_wy0_m <= #1 `TOP_DESIGN.sparc3.lsu.qctl2.dva_snp_wy0_e;
i4_3_dva_snp_wy1_m <= #1 `TOP_DESIGN.sparc3.lsu.qctl2.dva_snp_wy1_e;
i4_3_dva_snp_wy2_m <= #1 `TOP_DESIGN.sparc3.lsu.qctl2.dva_snp_wy2_e;
i4_3_dva_snp_wy3_m <= #1 `TOP_DESIGN.sparc3.lsu.qctl2.dva_snp_wy3_e;
i4_3_st_wr_dcache_w <= #1 i4_3_st_wr_dcache_m;
i4_3_fill_dcache_w <= #1 i4_3_fill_dcache_m;
i4_3_dcache_fill_addr_w <= #1 i4_3_dcache_fill_addr_m;
i4_3_dva_svld_w <= #1 i4_3_dva_svld_m;
i4_3_dva_snp_addr_w <= #1 i4_3_dva_snp_addr_m;
i4_3_dva_snp_set_vld_w <= #1 i4_3_dva_snp_set_vld_m;
i4_3_dva_snp_wy0_w <= #1 i4_3_dva_snp_wy0_m;
i4_3_dva_snp_wy1_w <= #1 i4_3_dva_snp_wy1_m;
i4_3_dva_snp_wy2_w <= #1 i4_3_dva_snp_wy2_m;
i4_3_dva_snp_wy3_w <= #1 i4_3_dva_snp_wy3_m;
`endif // ifdef RTL_SPARC3
`ifdef RTL_SPARC4
i4_4_fprs_set_e <= #1 `TOP_DESIGN.sparc4.ifu.swl.fprs_sel_set;
i4_4_new_fprs_e <= #1 `TOP_DESIGN.sparc4.ifu.swl.new_fprs;
i4_4_fprs_set_m <= #1 i4_4_fprs_set_e;
i4_4_new_fprs_m <= #1 i4_4_new_fprs_e;
i4_4_fprs_set_w <= #1 i4_4_fprs_set_m;
i4_4_new_fprs_w <= #1 i4_4_new_fprs_m;
i4_4_rstint_w <= #1 `TOP_DESIGN.sparc4.ifu.fcl.ifu_tlu_rstint_m;
i4_4_hwint_w <= #1 `TOP_DESIGN.sparc4.ifu.fcl.ifu_tlu_hwint_m;
i4_4_sftint_w <= #1 `TOP_DESIGN.sparc4.ifu.fcl.ifu_tlu_sftint_m;
i4_4_hint_m <= #1 `TOP_DESIGN.sparc4.ifu.fcl.ttype_sel_hstk_cmp_e;
i4_4_hint_w <= #1 i4_4_hint_m & `TOP_DESIGN.sparc4.ifu.fcl.ifu_tlu_ttype_vld_m;
i4_4_int_thr_w <= #1 `TOP_DESIGN.sparc4.ifu.fcl.thr_m;
i4_4_ic_inv_vld_f <= #1 `TOP_DESIGN.sparc4.ifu.invctl.stpkt_i2 &
`TOP_DESIGN.sparc4.ifu.invctl.invalidate_i2 &
`TOP_DESIGN.sparc4.ifu.invctl.icvidx_sel_inv_i2;
i4_4_ic_inv_addr_f <= #1 `TOP_DESIGN.sparc4.ifu.invctl.inv_addr_i2[11:6];
i4_4_ic_inv_word1_f <= #1 `TOP_DESIGN.sparc4.ifu.invctl.word1_inv_i2;
i4_4_ic_inv_word0_f <= #1 `TOP_DESIGN.sparc4.ifu.invctl.word0_inv_i2;
i4_4_ic_inv_way1_f <= #1 `TOP_DESIGN.sparc4.ifu.invctl.invwd1_way_i2;
i4_4_ic_inv_way0_f <= #1 `TOP_DESIGN.sparc4.ifu.invctl.invwd0_way_i2;
i4_4_ic_inv_vld_s <= #1 i4_4_ic_inv_vld_f;
i4_4_ic_inv_addr_s <= #1 i4_4_ic_inv_addr_f;
i4_4_ic_inv_word1_s <= #1 i4_4_ic_inv_word1_f;
i4_4_ic_inv_word0_s <= #1 i4_4_ic_inv_word0_f;
i4_4_ic_inv_way1_s <= #1 i4_4_ic_inv_way1_f;
i4_4_ic_inv_way0_s <= #1 i4_4_ic_inv_way0_f;
i4_4_st_wr_dcache_m <= #1 `TOP_DESIGN.sparc4.lsu.lsu_st_wr_dcache;
i4_4_fill_dcache_m <= #1 `TOP_DESIGN.sparc4.lsu.lsu_dcache_wr_vld_e & ~`TOP_DESIGN.sparc4.lsu.lsu_st_wr_dcache;
i4_4_dcache_fill_addr_m <= #1 `TOP_DESIGN.sparc4.lsu.dctl.dcache_fill_addr_e;
i4_4_dva_svld_m <= #1 `TOP_DESIGN.sparc4.lsu.qctl2.dva_svld_e &
(`TOP_DESIGN.sparc4.lsu.qdp2.dfq_byp_ff_data[143:140]=='h4) &
~(`TOP_DESIGN.sparc4.lsu.qctl2.memref_e &
`TOP_DESIGN.sparc4.lsu.qctl2.dfq_st_vld &
`TOP_DESIGN.sparc4.lsu.qctl2.dfq_local_inv &
`TOP_DESIGN.sparc4.lsu.qctl2.lsu_cpx_pkt_atomic);
i4_4_dva_snp_addr_m <= #1 `TOP_DESIGN.sparc4.lsu.qctl2.dva_snp_addr_e;
i4_4_dva_snp_set_vld_m <= #1 `TOP_DESIGN.sparc4.lsu.qctl2.dva_snp_set_vld_e;
i4_4_dva_snp_wy0_m <= #1 `TOP_DESIGN.sparc4.lsu.qctl2.dva_snp_wy0_e;
i4_4_dva_snp_wy1_m <= #1 `TOP_DESIGN.sparc4.lsu.qctl2.dva_snp_wy1_e;
i4_4_dva_snp_wy2_m <= #1 `TOP_DESIGN.sparc4.lsu.qctl2.dva_snp_wy2_e;
i4_4_dva_snp_wy3_m <= #1 `TOP_DESIGN.sparc4.lsu.qctl2.dva_snp_wy3_e;
i4_4_st_wr_dcache_w <= #1 i4_4_st_wr_dcache_m;
i4_4_fill_dcache_w <= #1 i4_4_fill_dcache_m;
i4_4_dcache_fill_addr_w <= #1 i4_4_dcache_fill_addr_m;
i4_4_dva_svld_w <= #1 i4_4_dva_svld_m;
i4_4_dva_snp_addr_w <= #1 i4_4_dva_snp_addr_m;
i4_4_dva_snp_set_vld_w <= #1 i4_4_dva_snp_set_vld_m;
i4_4_dva_snp_wy0_w <= #1 i4_4_dva_snp_wy0_m;
i4_4_dva_snp_wy1_w <= #1 i4_4_dva_snp_wy1_m;
i4_4_dva_snp_wy2_w <= #1 i4_4_dva_snp_wy2_m;
i4_4_dva_snp_wy3_w <= #1 i4_4_dva_snp_wy3_m;
`endif // ifdef RTL_SPARC4
`ifdef RTL_SPARC5
i4_5_fprs_set_e <= #1 `TOP_DESIGN.sparc5.ifu.swl.fprs_sel_set;
i4_5_new_fprs_e <= #1 `TOP_DESIGN.sparc5.ifu.swl.new_fprs;
i4_5_fprs_set_m <= #1 i4_5_fprs_set_e;
i4_5_new_fprs_m <= #1 i4_5_new_fprs_e;
i4_5_fprs_set_w <= #1 i4_5_fprs_set_m;
i4_5_new_fprs_w <= #1 i4_5_new_fprs_m;
i4_5_rstint_w <= #1 `TOP_DESIGN.sparc5.ifu.fcl.ifu_tlu_rstint_m;
i4_5_hwint_w <= #1 `TOP_DESIGN.sparc5.ifu.fcl.ifu_tlu_hwint_m;
i4_5_sftint_w <= #1 `TOP_DESIGN.sparc5.ifu.fcl.ifu_tlu_sftint_m;
i4_5_hint_m <= #1 `TOP_DESIGN.sparc5.ifu.fcl.ttype_sel_hstk_cmp_e;
i4_5_hint_w <= #1 i4_5_hint_m & `TOP_DESIGN.sparc5.ifu.fcl.ifu_tlu_ttype_vld_m;
i4_5_int_thr_w <= #1 `TOP_DESIGN.sparc5.ifu.fcl.thr_m;
i4_5_ic_inv_vld_f <= #1 `TOP_DESIGN.sparc5.ifu.invctl.stpkt_i2 &
`TOP_DESIGN.sparc5.ifu.invctl.invalidate_i2 &
`TOP_DESIGN.sparc5.ifu.invctl.icvidx_sel_inv_i2;
i4_5_ic_inv_addr_f <= #1 `TOP_DESIGN.sparc5.ifu.invctl.inv_addr_i2[11:6];
i4_5_ic_inv_word1_f <= #1 `TOP_DESIGN.sparc5.ifu.invctl.word1_inv_i2;
i4_5_ic_inv_word0_f <= #1 `TOP_DESIGN.sparc5.ifu.invctl.word0_inv_i2;
i4_5_ic_inv_way1_f <= #1 `TOP_DESIGN.sparc5.ifu.invctl.invwd1_way_i2;
i4_5_ic_inv_way0_f <= #1 `TOP_DESIGN.sparc5.ifu.invctl.invwd0_way_i2;
i4_5_ic_inv_vld_s <= #1 i4_5_ic_inv_vld_f;
i4_5_ic_inv_addr_s <= #1 i4_5_ic_inv_addr_f;
i4_5_ic_inv_word1_s <= #1 i4_5_ic_inv_word1_f;
i4_5_ic_inv_word0_s <= #1 i4_5_ic_inv_word0_f;
i4_5_ic_inv_way1_s <= #1 i4_5_ic_inv_way1_f;
i4_5_ic_inv_way0_s <= #1 i4_5_ic_inv_way0_f;
i4_5_st_wr_dcache_m <= #1 `TOP_DESIGN.sparc5.lsu.lsu_st_wr_dcache;
i4_5_fill_dcache_m <= #1 `TOP_DESIGN.sparc5.lsu.lsu_dcache_wr_vld_e & ~`TOP_DESIGN.sparc5.lsu.lsu_st_wr_dcache;
i4_5_dcache_fill_addr_m <= #1 `TOP_DESIGN.sparc5.lsu.dctl.dcache_fill_addr_e;
i4_5_dva_svld_m <= #1 `TOP_DESIGN.sparc5.lsu.qctl2.dva_svld_e &
(`TOP_DESIGN.sparc5.lsu.qdp2.dfq_byp_ff_data[143:140]=='h4) &
~(`TOP_DESIGN.sparc5.lsu.qctl2.memref_e &
`TOP_DESIGN.sparc5.lsu.qctl2.dfq_st_vld &
`TOP_DESIGN.sparc5.lsu.qctl2.dfq_local_inv &
`TOP_DESIGN.sparc5.lsu.qctl2.lsu_cpx_pkt_atomic);
i4_5_dva_snp_addr_m <= #1 `TOP_DESIGN.sparc5.lsu.qctl2.dva_snp_addr_e;
i4_5_dva_snp_set_vld_m <= #1 `TOP_DESIGN.sparc5.lsu.qctl2.dva_snp_set_vld_e;
i4_5_dva_snp_wy0_m <= #1 `TOP_DESIGN.sparc5.lsu.qctl2.dva_snp_wy0_e;
i4_5_dva_snp_wy1_m <= #1 `TOP_DESIGN.sparc5.lsu.qctl2.dva_snp_wy1_e;
i4_5_dva_snp_wy2_m <= #1 `TOP_DESIGN.sparc5.lsu.qctl2.dva_snp_wy2_e;
i4_5_dva_snp_wy3_m <= #1 `TOP_DESIGN.sparc5.lsu.qctl2.dva_snp_wy3_e;
i4_5_st_wr_dcache_w <= #1 i4_5_st_wr_dcache_m;
i4_5_fill_dcache_w <= #1 i4_5_fill_dcache_m;
i4_5_dcache_fill_addr_w <= #1 i4_5_dcache_fill_addr_m;
i4_5_dva_svld_w <= #1 i4_5_dva_svld_m;
i4_5_dva_snp_addr_w <= #1 i4_5_dva_snp_addr_m;
i4_5_dva_snp_set_vld_w <= #1 i4_5_dva_snp_set_vld_m;
i4_5_dva_snp_wy0_w <= #1 i4_5_dva_snp_wy0_m;
i4_5_dva_snp_wy1_w <= #1 i4_5_dva_snp_wy1_m;
i4_5_dva_snp_wy2_w <= #1 i4_5_dva_snp_wy2_m;
i4_5_dva_snp_wy3_w <= #1 i4_5_dva_snp_wy3_m;
`endif // ifdef RTL_SPARC5
`ifdef RTL_SPARC6
i4_6_fprs_set_e <= #1 `TOP_DESIGN.sparc6.ifu.swl.fprs_sel_set;
i4_6_new_fprs_e <= #1 `TOP_DESIGN.sparc6.ifu.swl.new_fprs;
i4_6_fprs_set_m <= #1 i4_6_fprs_set_e;
i4_6_new_fprs_m <= #1 i4_6_new_fprs_e;
i4_6_fprs_set_w <= #1 i4_6_fprs_set_m;
i4_6_new_fprs_w <= #1 i4_6_new_fprs_m;
i4_6_rstint_w <= #1 `TOP_DESIGN.sparc6.ifu.fcl.ifu_tlu_rstint_m;
i4_6_hwint_w <= #1 `TOP_DESIGN.sparc6.ifu.fcl.ifu_tlu_hwint_m;
i4_6_sftint_w <= #1 `TOP_DESIGN.sparc6.ifu.fcl.ifu_tlu_sftint_m;
i4_6_hint_m <= #1 `TOP_DESIGN.sparc6.ifu.fcl.ttype_sel_hstk_cmp_e;
i4_6_hint_w <= #1 i4_6_hint_m & `TOP_DESIGN.sparc6.ifu.fcl.ifu_tlu_ttype_vld_m;
i4_6_int_thr_w <= #1 `TOP_DESIGN.sparc6.ifu.fcl.thr_m;
i4_6_ic_inv_vld_f <= #1 `TOP_DESIGN.sparc6.ifu.invctl.stpkt_i2 &
`TOP_DESIGN.sparc6.ifu.invctl.invalidate_i2 &
`TOP_DESIGN.sparc6.ifu.invctl.icvidx_sel_inv_i2;
i4_6_ic_inv_addr_f <= #1 `TOP_DESIGN.sparc6.ifu.invctl.inv_addr_i2[11:6];
i4_6_ic_inv_word1_f <= #1 `TOP_DESIGN.sparc6.ifu.invctl.word1_inv_i2;
i4_6_ic_inv_word0_f <= #1 `TOP_DESIGN.sparc6.ifu.invctl.word0_inv_i2;
i4_6_ic_inv_way1_f <= #1 `TOP_DESIGN.sparc6.ifu.invctl.invwd1_way_i2;
i4_6_ic_inv_way0_f <= #1 `TOP_DESIGN.sparc6.ifu.invctl.invwd0_way_i2;
i4_6_ic_inv_vld_s <= #1 i4_6_ic_inv_vld_f;
i4_6_ic_inv_addr_s <= #1 i4_6_ic_inv_addr_f;
i4_6_ic_inv_word1_s <= #1 i4_6_ic_inv_word1_f;
i4_6_ic_inv_word0_s <= #1 i4_6_ic_inv_word0_f;
i4_6_ic_inv_way1_s <= #1 i4_6_ic_inv_way1_f;
i4_6_ic_inv_way0_s <= #1 i4_6_ic_inv_way0_f;
i4_6_st_wr_dcache_m <= #1 `TOP_DESIGN.sparc6.lsu.lsu_st_wr_dcache;
i4_6_fill_dcache_m <= #1 `TOP_DESIGN.sparc6.lsu.lsu_dcache_wr_vld_e & ~`TOP_DESIGN.sparc6.lsu.lsu_st_wr_dcache;
i4_6_dcache_fill_addr_m <= #1 `TOP_DESIGN.sparc6.lsu.dctl.dcache_fill_addr_e;
i4_6_dva_svld_m <= #1 `TOP_DESIGN.sparc6.lsu.qctl2.dva_svld_e &
(`TOP_DESIGN.sparc6.lsu.qdp2.dfq_byp_ff_data[143:140]=='h4) &
~(`TOP_DESIGN.sparc6.lsu.qctl2.memref_e &
`TOP_DESIGN.sparc6.lsu.qctl2.dfq_st_vld &
`TOP_DESIGN.sparc6.lsu.qctl2.dfq_local_inv &
`TOP_DESIGN.sparc6.lsu.qctl2.lsu_cpx_pkt_atomic);
i4_6_dva_snp_addr_m <= #1 `TOP_DESIGN.sparc6.lsu.qctl2.dva_snp_addr_e;
i4_6_dva_snp_set_vld_m <= #1 `TOP_DESIGN.sparc6.lsu.qctl2.dva_snp_set_vld_e;
i4_6_dva_snp_wy0_m <= #1 `TOP_DESIGN.sparc6.lsu.qctl2.dva_snp_wy0_e;
i4_6_dva_snp_wy1_m <= #1 `TOP_DESIGN.sparc6.lsu.qctl2.dva_snp_wy1_e;
i4_6_dva_snp_wy2_m <= #1 `TOP_DESIGN.sparc6.lsu.qctl2.dva_snp_wy2_e;
i4_6_dva_snp_wy3_m <= #1 `TOP_DESIGN.sparc6.lsu.qctl2.dva_snp_wy3_e;
i4_6_st_wr_dcache_w <= #1 i4_6_st_wr_dcache_m;
i4_6_fill_dcache_w <= #1 i4_6_fill_dcache_m;
i4_6_dcache_fill_addr_w <= #1 i4_6_dcache_fill_addr_m;
i4_6_dva_svld_w <= #1 i4_6_dva_svld_m;
i4_6_dva_snp_addr_w <= #1 i4_6_dva_snp_addr_m;
i4_6_dva_snp_set_vld_w <= #1 i4_6_dva_snp_set_vld_m;
i4_6_dva_snp_wy0_w <= #1 i4_6_dva_snp_wy0_m;
i4_6_dva_snp_wy1_w <= #1 i4_6_dva_snp_wy1_m;
i4_6_dva_snp_wy2_w <= #1 i4_6_dva_snp_wy2_m;
i4_6_dva_snp_wy3_w <= #1 i4_6_dva_snp_wy3_m;
`endif // ifdef RTL_SPARC6
`ifdef RTL_SPARC7
i4_7_fprs_set_e <= #1 `TOP_DESIGN.sparc7.ifu.swl.fprs_sel_set;
i4_7_new_fprs_e <= #1 `TOP_DESIGN.sparc7.ifu.swl.new_fprs;
i4_7_fprs_set_m <= #1 i4_7_fprs_set_e;
i4_7_new_fprs_m <= #1 i4_7_new_fprs_e;
i4_7_fprs_set_w <= #1 i4_7_fprs_set_m;
i4_7_new_fprs_w <= #1 i4_7_new_fprs_m;
i4_7_rstint_w <= #1 `TOP_DESIGN.sparc7.ifu.fcl.ifu_tlu_rstint_m;
i4_7_hwint_w <= #1 `TOP_DESIGN.sparc7.ifu.fcl.ifu_tlu_hwint_m;
i4_7_sftint_w <= #1 `TOP_DESIGN.sparc7.ifu.fcl.ifu_tlu_sftint_m;
i4_7_hint_m <= #1 `TOP_DESIGN.sparc7.ifu.fcl.ttype_sel_hstk_cmp_e;
i4_7_hint_w <= #1 i4_7_hint_m & `TOP_DESIGN.sparc7.ifu.fcl.ifu_tlu_ttype_vld_m;
i4_7_int_thr_w <= #1 `TOP_DESIGN.sparc7.ifu.fcl.thr_m;
i4_7_ic_inv_vld_f <= #1 `TOP_DESIGN.sparc7.ifu.invctl.stpkt_i2 &
`TOP_DESIGN.sparc7.ifu.invctl.invalidate_i2 &
`TOP_DESIGN.sparc7.ifu.invctl.icvidx_sel_inv_i2;
i4_7_ic_inv_addr_f <= #1 `TOP_DESIGN.sparc7.ifu.invctl.inv_addr_i2[11:6];
i4_7_ic_inv_word1_f <= #1 `TOP_DESIGN.sparc7.ifu.invctl.word1_inv_i2;
i4_7_ic_inv_word0_f <= #1 `TOP_DESIGN.sparc7.ifu.invctl.word0_inv_i2;
i4_7_ic_inv_way1_f <= #1 `TOP_DESIGN.sparc7.ifu.invctl.invwd1_way_i2;
i4_7_ic_inv_way0_f <= #1 `TOP_DESIGN.sparc7.ifu.invctl.invwd0_way_i2;
i4_7_ic_inv_vld_s <= #1 i4_7_ic_inv_vld_f;
i4_7_ic_inv_addr_s <= #1 i4_7_ic_inv_addr_f;
i4_7_ic_inv_word1_s <= #1 i4_7_ic_inv_word1_f;
i4_7_ic_inv_word0_s <= #1 i4_7_ic_inv_word0_f;
i4_7_ic_inv_way1_s <= #1 i4_7_ic_inv_way1_f;
i4_7_ic_inv_way0_s <= #1 i4_7_ic_inv_way0_f;
i4_7_st_wr_dcache_m <= #1 `TOP_DESIGN.sparc7.lsu.lsu_st_wr_dcache;
i4_7_fill_dcache_m <= #1 `TOP_DESIGN.sparc7.lsu.lsu_dcache_wr_vld_e & ~`TOP_DESIGN.sparc7.lsu.lsu_st_wr_dcache;
i4_7_dcache_fill_addr_m <= #1 `TOP_DESIGN.sparc7.lsu.dctl.dcache_fill_addr_e;
i4_7_dva_svld_m <= #1 `TOP_DESIGN.sparc7.lsu.qctl2.dva_svld_e &
(`TOP_DESIGN.sparc7.lsu.qdp2.dfq_byp_ff_data[143:140]=='h4) &
~(`TOP_DESIGN.sparc7.lsu.qctl2.memref_e &
`TOP_DESIGN.sparc7.lsu.qctl2.dfq_st_vld &
`TOP_DESIGN.sparc7.lsu.qctl2.dfq_local_inv &
`TOP_DESIGN.sparc7.lsu.qctl2.lsu_cpx_pkt_atomic);
i4_7_dva_snp_addr_m <= #1 `TOP_DESIGN.sparc7.lsu.qctl2.dva_snp_addr_e;
i4_7_dva_snp_set_vld_m <= #1 `TOP_DESIGN.sparc7.lsu.qctl2.dva_snp_set_vld_e;
i4_7_dva_snp_wy0_m <= #1 `TOP_DESIGN.sparc7.lsu.qctl2.dva_snp_wy0_e;
i4_7_dva_snp_wy1_m <= #1 `TOP_DESIGN.sparc7.lsu.qctl2.dva_snp_wy1_e;
i4_7_dva_snp_wy2_m <= #1 `TOP_DESIGN.sparc7.lsu.qctl2.dva_snp_wy2_e;
i4_7_dva_snp_wy3_m <= #1 `TOP_DESIGN.sparc7.lsu.qctl2.dva_snp_wy3_e;
i4_7_st_wr_dcache_w <= #1 i4_7_st_wr_dcache_m;
i4_7_fill_dcache_w <= #1 i4_7_fill_dcache_m;
i4_7_dcache_fill_addr_w <= #1 i4_7_dcache_fill_addr_m;
i4_7_dva_svld_w <= #1 i4_7_dva_svld_m;
i4_7_dva_snp_addr_w <= #1 i4_7_dva_snp_addr_m;
i4_7_dva_snp_set_vld_w <= #1 i4_7_dva_snp_set_vld_m;
i4_7_dva_snp_wy0_w <= #1 i4_7_dva_snp_wy0_m;
i4_7_dva_snp_wy1_w <= #1 i4_7_dva_snp_wy1_m;
i4_7_dva_snp_wy2_w <= #1 i4_7_dva_snp_wy2_m;
i4_7_dva_snp_wy3_w <= #1 i4_7_dva_snp_wy3_m;
`endif // ifdef RTL_SPARC7
end // always @(posedge clk)
`ifdef RTL_SPARC0
assign i4_0_trap = `TOP_DESIGN.sparc0.tlu.tcl.thrd0_traps |
`TOP_DESIGN.sparc0.tlu.tcl.thrd1_traps |
`TOP_DESIGN.sparc0.tlu.tcl.thrd2_traps |
`TOP_DESIGN.sparc0.tlu.tcl.thrd3_traps;
assign i4_0_immu_miss= i4_0_trap &
((`TOP_DESIGN.sparc0.tlu.tcl.sas_final_ttype_g[8:0]=='h64) |
(`TOP_DESIGN.sparc0.tlu.tcl.sas_final_ttype_g[8:0]=='h3e));
assign i4_0_dmmu_miss= i4_0_trap &
((`TOP_DESIGN.sparc0.tlu.tcl.sas_final_ttype_g[8:0]=='h68) |
(`TOP_DESIGN.sparc0.tlu.tcl.sas_final_ttype_g[8:0]=='h3f));
assign i4_0_spu_trap_ack_w= `TOP_DESIGN.sparc0.ifu_spu_trap_ack;
assign i4_0_spu_illgl_va= `TOP_DESIGN.sparc0.spu_lsu_ldxa_data_vld_w2 &
`TOP_DESIGN.sparc0.spu_lsu_ldxa_illgl_va_w2;
assign i4_0_rstint_vld_w= i4_0_rstint_w &
`TOP_DESIGN.sparc0.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc0.ifu.ifu_tlu_flush_w;
assign i4_0_hwint_vld_w= i4_0_hwint_w &
`TOP_DESIGN.sparc0.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc0.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc0.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc0.tlu.tcl.tlz_trap_g[3:0]));
assign i4_0_sftint_vld_w= i4_0_sftint_w &
`TOP_DESIGN.sparc0.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc0.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc0.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc0.tlu.tcl.tlz_trap_g[3:0]));
assign i4_0_hint_vld_w= i4_0_hint_w &
`TOP_DESIGN.sparc0.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc0.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc0.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc0.tlu.tcl.tlz_trap_g[3:0]));
assign i4_0_tick_match= `TOP_DESIGN.sparc0.tlu.tdp.tickcmp_int[3:0];
assign i4_0_stick_match= `TOP_DESIGN.sparc0.tlu.tdp.stickcmp_int[3:0];
assign i4_0_hstick_match= `TOP_DESIGN.sparc0.tlu.tdp.tlu_set_hintp_g[3:0];
assign i4_0_ld_int = `TOP_DESIGN.sparc0.tlu.intdp.inc_ind_ld_int_i1;
assign i4_0_cpx_tid = `TOP_DESIGN.sparc0.lsu.qdp2.cpx_spc_data_cx[`CPX_TH_HI:`CPX_TH_LO];
assign i4_0_itlb_repl_vld = `TOP_DESIGN.sparc0.ifu.itlb.wr_vld &
~`TOP_DESIGN.sparc0.ifu.itlb.rw_index_vld;
assign i4_0_dtlb_repl_vld = `TOP_DESIGN.sparc0.lsu.dtlb.wr_vld &
~`TOP_DESIGN.sparc0.lsu.dtlb.rw_index_vld;
assign i4_0_tlb_repl_vec[63:0] = i4_0_itlb_repl_vld ?
`TOP_DESIGN.sparc0.ifu.itlb.tlb_entry_replace[63:0] :
`TOP_DESIGN.sparc0.lsu.dtlb.tlb_entry_replace[63:0];
assign i4_0_tlb_repl_idx[5] = |(i4_0_tlb_repl_vec[63:32]);
assign i4_0_tlb_repl_idx[4] =
(|(i4_0_tlb_repl_vec[63:48])) | (|(i4_0_tlb_repl_vec[31:16]));
assign i4_0_tlb_repl_idx[3] =
(|(i4_0_tlb_repl_vec[63:56])) | (|(i4_0_tlb_repl_vec[47:40])) |
(|(i4_0_tlb_repl_vec[31:24])) | (|(i4_0_tlb_repl_vec[15:8]));
assign i4_0_tlb_repl_idx[2] =
(|i4_0_tlb_repl_vec[63:60]) | (|i4_0_tlb_repl_vec[55:52]) |
(|i4_0_tlb_repl_vec[47:44]) | (|i4_0_tlb_repl_vec[39:36]) |
(|i4_0_tlb_repl_vec[31:28]) | (|i4_0_tlb_repl_vec[23:20]) |
(|i4_0_tlb_repl_vec[15:12]) | (|i4_0_tlb_repl_vec[7:4]);
assign i4_0_tlb_repl_idx[1] =
(|i4_0_tlb_repl_vec[63:62]) | (|i4_0_tlb_repl_vec[59:58]) |
(|i4_0_tlb_repl_vec[55:54]) | (|i4_0_tlb_repl_vec[51:50]) |
(|i4_0_tlb_repl_vec[47:46]) | (|i4_0_tlb_repl_vec[43:42]) |
(|i4_0_tlb_repl_vec[39:38]) | (|i4_0_tlb_repl_vec[35:34]) |
(|i4_0_tlb_repl_vec[31:30]) | (|i4_0_tlb_repl_vec[27:26]) |
(|i4_0_tlb_repl_vec[23:22]) | (|i4_0_tlb_repl_vec[19:18]) |
(|i4_0_tlb_repl_vec[15:14]) | (|i4_0_tlb_repl_vec[11:10]) |
(|i4_0_tlb_repl_vec[7:6]) | (|i4_0_tlb_repl_vec[3:2]);
assign i4_0_tlb_repl_idx[0] =
i4_0_tlb_repl_vec[63] | i4_0_tlb_repl_vec[61] |
i4_0_tlb_repl_vec[59] | i4_0_tlb_repl_vec[57] |
i4_0_tlb_repl_vec[55] | i4_0_tlb_repl_vec[53] |
i4_0_tlb_repl_vec[51] | i4_0_tlb_repl_vec[49] |
i4_0_tlb_repl_vec[47] | i4_0_tlb_repl_vec[45] |
i4_0_tlb_repl_vec[43] | i4_0_tlb_repl_vec[41] |
i4_0_tlb_repl_vec[39] | i4_0_tlb_repl_vec[37] |
i4_0_tlb_repl_vec[35] | i4_0_tlb_repl_vec[33] |
i4_0_tlb_repl_vec[31] | i4_0_tlb_repl_vec[29] |
i4_0_tlb_repl_vec[27] | i4_0_tlb_repl_vec[25] |
i4_0_tlb_repl_vec[23] | i4_0_tlb_repl_vec[21] |
i4_0_tlb_repl_vec[19] | i4_0_tlb_repl_vec[17] |
i4_0_tlb_repl_vec[15] | i4_0_tlb_repl_vec[13] |
i4_0_tlb_repl_vec[11] | i4_0_tlb_repl_vec[9] |
i4_0_tlb_repl_vec[7] | i4_0_tlb_repl_vec[5] |
i4_0_tlb_repl_vec[3] | i4_0_tlb_repl_vec[1];
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC1
assign i4_1_trap = `TOP_DESIGN.sparc1.tlu.tcl.thrd0_traps |
`TOP_DESIGN.sparc1.tlu.tcl.thrd1_traps |
`TOP_DESIGN.sparc1.tlu.tcl.thrd2_traps |
`TOP_DESIGN.sparc1.tlu.tcl.thrd3_traps;
assign i4_1_immu_miss= i4_1_trap &
((`TOP_DESIGN.sparc1.tlu.tcl.sas_final_ttype_g[8:0]=='h64) |
(`TOP_DESIGN.sparc1.tlu.tcl.sas_final_ttype_g[8:0]=='h3e));
assign i4_1_dmmu_miss= i4_1_trap &
((`TOP_DESIGN.sparc1.tlu.tcl.sas_final_ttype_g[8:0]=='h68) |
(`TOP_DESIGN.sparc1.tlu.tcl.sas_final_ttype_g[8:0]=='h3f));
assign i4_1_spu_trap_ack_w= `TOP_DESIGN.sparc1.ifu_spu_trap_ack;
assign i4_1_spu_illgl_va= `TOP_DESIGN.sparc1.spu_lsu_ldxa_data_vld_w2 &
`TOP_DESIGN.sparc1.spu_lsu_ldxa_illgl_va_w2;
assign i4_1_rstint_vld_w= i4_1_rstint_w &
`TOP_DESIGN.sparc1.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc1.ifu.ifu_tlu_flush_w;
assign i4_1_hwint_vld_w= i4_1_hwint_w &
`TOP_DESIGN.sparc1.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc1.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc1.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc1.tlu.tcl.tlz_trap_g[3:0]));
assign i4_1_sftint_vld_w= i4_1_sftint_w &
`TOP_DESIGN.sparc1.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc1.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc1.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc1.tlu.tcl.tlz_trap_g[3:0]));
assign i4_1_hint_vld_w= i4_1_hint_w &
`TOP_DESIGN.sparc1.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc1.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc1.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc1.tlu.tcl.tlz_trap_g[3:0]));
assign i4_1_tick_match= `TOP_DESIGN.sparc1.tlu.tdp.tickcmp_int[3:0];
assign i4_1_stick_match= `TOP_DESIGN.sparc1.tlu.tdp.stickcmp_int[3:0];
assign i4_1_hstick_match= `TOP_DESIGN.sparc1.tlu.tdp.tlu_set_hintp_g[3:0];
assign i4_1_ld_int = `TOP_DESIGN.sparc1.tlu.intdp.inc_ind_ld_int_i1;
assign i4_1_cpx_tid = `TOP_DESIGN.sparc1.lsu.qdp2.cpx_spc_data_cx[`CPX_TH_HI:`CPX_TH_LO];
assign i4_1_itlb_repl_vld = `TOP_DESIGN.sparc1.ifu.itlb.wr_vld &
~`TOP_DESIGN.sparc1.ifu.itlb.rw_index_vld;
assign i4_1_dtlb_repl_vld = `TOP_DESIGN.sparc1.lsu.dtlb.wr_vld &
~`TOP_DESIGN.sparc1.lsu.dtlb.rw_index_vld;
assign i4_1_tlb_repl_vec[63:0] = i4_1_itlb_repl_vld ?
`TOP_DESIGN.sparc1.ifu.itlb.tlb_entry_replace[63:0] :
`TOP_DESIGN.sparc1.lsu.dtlb.tlb_entry_replace[63:0];
assign i4_1_tlb_repl_idx[5] = |(i4_1_tlb_repl_vec[63:32]);
assign i4_1_tlb_repl_idx[4] =
|(i4_1_tlb_repl_vec[63:48]) | |(i4_1_tlb_repl_vec[31:16]);
assign i4_1_tlb_repl_idx[3] =
|(i4_1_tlb_repl_vec[63:56]) | |(i4_1_tlb_repl_vec[47:40]) |
|(i4_1_tlb_repl_vec[31:24]) | |(i4_1_tlb_repl_vec[15:8]);
assign i4_1_tlb_repl_idx[2] =
|(i4_1_tlb_repl_vec[63:60]) | |(i4_1_tlb_repl_vec[55:52]) |
|(i4_1_tlb_repl_vec[47:44]) | |(i4_1_tlb_repl_vec[39:36]) |
|(i4_1_tlb_repl_vec[31:28]) | |(i4_1_tlb_repl_vec[23:20]) |
|(i4_1_tlb_repl_vec[15:12]) | |(i4_1_tlb_repl_vec[7:4]);
assign i4_1_tlb_repl_idx[1] =
|(i4_1_tlb_repl_vec[63:62]) | |(i4_1_tlb_repl_vec[59:58]) |
|(i4_1_tlb_repl_vec[55:54]) | |(i4_1_tlb_repl_vec[51:50]) |
|(i4_1_tlb_repl_vec[47:46]) | |(i4_1_tlb_repl_vec[43:42]) |
|(i4_1_tlb_repl_vec[39:38]) | |(i4_1_tlb_repl_vec[35:34]) |
|(i4_1_tlb_repl_vec[31:30]) | |(i4_1_tlb_repl_vec[27:26]) |
|(i4_1_tlb_repl_vec[23:22]) | |(i4_1_tlb_repl_vec[19:18]) |
|(i4_1_tlb_repl_vec[15:14]) | |(i4_1_tlb_repl_vec[11:10]) |
|(i4_1_tlb_repl_vec[7:6]) | |(i4_1_tlb_repl_vec[3:2]);
assign i4_1_tlb_repl_idx[0] =
i4_1_tlb_repl_vec[63] | i4_1_tlb_repl_vec[61] |
i4_1_tlb_repl_vec[59] | i4_1_tlb_repl_vec[57] |
i4_1_tlb_repl_vec[55] | i4_1_tlb_repl_vec[53] |
i4_1_tlb_repl_vec[51] | i4_1_tlb_repl_vec[49] |
i4_1_tlb_repl_vec[47] | i4_1_tlb_repl_vec[45] |
i4_1_tlb_repl_vec[43] | i4_1_tlb_repl_vec[41] |
i4_1_tlb_repl_vec[39] | i4_1_tlb_repl_vec[37] |
i4_1_tlb_repl_vec[35] | i4_1_tlb_repl_vec[33] |
i4_1_tlb_repl_vec[31] | i4_1_tlb_repl_vec[29] |
i4_1_tlb_repl_vec[27] | i4_1_tlb_repl_vec[25] |
i4_1_tlb_repl_vec[23] | i4_1_tlb_repl_vec[21] |
i4_1_tlb_repl_vec[19] | i4_1_tlb_repl_vec[17] |
i4_1_tlb_repl_vec[15] | i4_1_tlb_repl_vec[13] |
i4_1_tlb_repl_vec[11] | i4_1_tlb_repl_vec[9] |
i4_1_tlb_repl_vec[7] | i4_1_tlb_repl_vec[5] |
i4_1_tlb_repl_vec[3] | i4_1_tlb_repl_vec[1];
`endif // ifdef RTL_SPARC1
`ifdef RTL_SPARC2
assign i4_2_trap = `TOP_DESIGN.sparc2.tlu.tcl.thrd0_traps |
`TOP_DESIGN.sparc2.tlu.tcl.thrd1_traps |
`TOP_DESIGN.sparc2.tlu.tcl.thrd2_traps |
`TOP_DESIGN.sparc2.tlu.tcl.thrd3_traps;
assign i4_2_immu_miss= i4_2_trap &
((`TOP_DESIGN.sparc2.tlu.tcl.sas_final_ttype_g[8:0]=='h64) |
(`TOP_DESIGN.sparc2.tlu.tcl.sas_final_ttype_g[8:0]=='h3e));
assign i4_2_dmmu_miss= i4_2_trap &
((`TOP_DESIGN.sparc2.tlu.tcl.sas_final_ttype_g[8:0]=='h68) |
(`TOP_DESIGN.sparc2.tlu.tcl.sas_final_ttype_g[8:0]=='h3f));
assign i4_2_spu_trap_ack_w= `TOP_DESIGN.sparc2.ifu_spu_trap_ack;
assign i4_2_spu_illgl_va= `TOP_DESIGN.sparc2.spu_lsu_ldxa_data_vld_w2 &
`TOP_DESIGN.sparc2.spu_lsu_ldxa_illgl_va_w2;
assign i4_2_rstint_vld_w= i4_2_rstint_w &
`TOP_DESIGN.sparc2.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc2.ifu.ifu_tlu_flush_w;
assign i4_2_hwint_vld_w= i4_2_hwint_w &
`TOP_DESIGN.sparc2.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc2.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc2.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc2.tlu.tcl.tlz_trap_g[3:0]));
assign i4_2_sftint_vld_w= i4_2_sftint_w &
`TOP_DESIGN.sparc2.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc2.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc2.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc2.tlu.tcl.tlz_trap_g[3:0]));
assign i4_2_hint_vld_w= i4_2_hint_w &
`TOP_DESIGN.sparc2.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc2.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc2.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc2.tlu.tcl.tlz_trap_g[3:0]));
assign i4_2_tick_match= `TOP_DESIGN.sparc2.tlu.tdp.tickcmp_int[3:0];
assign i4_2_stick_match= `TOP_DESIGN.sparc2.tlu.tdp.stickcmp_int[3:0];
assign i4_2_hstick_match= `TOP_DESIGN.sparc2.tlu.tdp.tlu_set_hintp_g[3:0];
assign i4_2_ld_int = `TOP_DESIGN.sparc2.tlu.intdp.inc_ind_ld_int_i1;
assign i4_2_cpx_tid = `TOP_DESIGN.sparc2.lsu.qdp2.cpx_spc_data_cx[`CPX_TH_HI:`CPX_TH_LO];
assign i4_2_itlb_repl_vld = `TOP_DESIGN.sparc2.ifu.itlb.wr_vld &
~`TOP_DESIGN.sparc2.ifu.itlb.rw_index_vld;
assign i4_2_dtlb_repl_vld = `TOP_DESIGN.sparc2.lsu.dtlb.wr_vld &
~`TOP_DESIGN.sparc2.lsu.dtlb.rw_index_vld;
assign i4_2_tlb_repl_vec[63:0] = i4_2_itlb_repl_vld ?
`TOP_DESIGN.sparc2.ifu.itlb.tlb_entry_replace[63:0] :
`TOP_DESIGN.sparc2.lsu.dtlb.tlb_entry_replace[63:0];
assign i4_2_tlb_repl_idx[5] = |(i4_2_tlb_repl_vec[63:32]);
assign i4_2_tlb_repl_idx[4] =
|(i4_2_tlb_repl_vec[63:48]) | |(i4_2_tlb_repl_vec[31:16]);
assign i4_2_tlb_repl_idx[3] =
|(i4_2_tlb_repl_vec[63:56]) | |(i4_2_tlb_repl_vec[47:40]) |
|(i4_2_tlb_repl_vec[31:24]) | |(i4_2_tlb_repl_vec[15:8]);
assign i4_2_tlb_repl_idx[2] =
|(i4_2_tlb_repl_vec[63:60]) | |(i4_2_tlb_repl_vec[55:52]) |
|(i4_2_tlb_repl_vec[47:44]) | |(i4_2_tlb_repl_vec[39:36]) |
|(i4_2_tlb_repl_vec[31:28]) | |(i4_2_tlb_repl_vec[23:20]) |
|(i4_2_tlb_repl_vec[15:12]) | |(i4_2_tlb_repl_vec[7:4]);
assign i4_2_tlb_repl_idx[1] =
|(i4_2_tlb_repl_vec[63:62]) | |(i4_2_tlb_repl_vec[59:58]) |
|(i4_2_tlb_repl_vec[55:54]) | |(i4_2_tlb_repl_vec[51:50]) |
|(i4_2_tlb_repl_vec[47:46]) | |(i4_2_tlb_repl_vec[43:42]) |
|(i4_2_tlb_repl_vec[39:38]) | |(i4_2_tlb_repl_vec[35:34]) |
|(i4_2_tlb_repl_vec[31:30]) | |(i4_2_tlb_repl_vec[27:26]) |
|(i4_2_tlb_repl_vec[23:22]) | |(i4_2_tlb_repl_vec[19:18]) |
|(i4_2_tlb_repl_vec[15:14]) | |(i4_2_tlb_repl_vec[11:10]) |
|(i4_2_tlb_repl_vec[7:6]) | |(i4_2_tlb_repl_vec[3:2]);
assign i4_2_tlb_repl_idx[0] =
i4_2_tlb_repl_vec[63] | i4_2_tlb_repl_vec[61] |
i4_2_tlb_repl_vec[59] | i4_2_tlb_repl_vec[57] |
i4_2_tlb_repl_vec[55] | i4_2_tlb_repl_vec[53] |
i4_2_tlb_repl_vec[51] | i4_2_tlb_repl_vec[49] |
i4_2_tlb_repl_vec[47] | i4_2_tlb_repl_vec[45] |
i4_2_tlb_repl_vec[43] | i4_2_tlb_repl_vec[41] |
i4_2_tlb_repl_vec[39] | i4_2_tlb_repl_vec[37] |
i4_2_tlb_repl_vec[35] | i4_2_tlb_repl_vec[33] |
i4_2_tlb_repl_vec[31] | i4_2_tlb_repl_vec[29] |
i4_2_tlb_repl_vec[27] | i4_2_tlb_repl_vec[25] |
i4_2_tlb_repl_vec[23] | i4_2_tlb_repl_vec[21] |
i4_2_tlb_repl_vec[19] | i4_2_tlb_repl_vec[17] |
i4_2_tlb_repl_vec[15] | i4_2_tlb_repl_vec[13] |
i4_2_tlb_repl_vec[11] | i4_2_tlb_repl_vec[9] |
i4_2_tlb_repl_vec[7] | i4_2_tlb_repl_vec[5] |
i4_2_tlb_repl_vec[3] | i4_2_tlb_repl_vec[1];
`endif // ifdef RTL_SPARC2
`ifdef RTL_SPARC3
assign i4_3_trap = `TOP_DESIGN.sparc3.tlu.tcl.thrd0_traps |
`TOP_DESIGN.sparc3.tlu.tcl.thrd1_traps |
`TOP_DESIGN.sparc3.tlu.tcl.thrd2_traps |
`TOP_DESIGN.sparc3.tlu.tcl.thrd3_traps;
assign i4_3_immu_miss= i4_3_trap &
((`TOP_DESIGN.sparc3.tlu.tcl.sas_final_ttype_g[8:0]=='h64) |
(`TOP_DESIGN.sparc3.tlu.tcl.sas_final_ttype_g[8:0]=='h3e));
assign i4_3_dmmu_miss= i4_3_trap &
((`TOP_DESIGN.sparc3.tlu.tcl.sas_final_ttype_g[8:0]=='h68) |
(`TOP_DESIGN.sparc3.tlu.tcl.sas_final_ttype_g[8:0]=='h3f));
assign i4_3_spu_trap_ack_w= `TOP_DESIGN.sparc3.ifu_spu_trap_ack;
assign i4_3_spu_illgl_va= `TOP_DESIGN.sparc3.spu_lsu_ldxa_data_vld_w2 &
`TOP_DESIGN.sparc3.spu_lsu_ldxa_illgl_va_w2;
assign i4_3_rstint_vld_w= i4_3_rstint_w &
`TOP_DESIGN.sparc3.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc3.ifu.ifu_tlu_flush_w;
assign i4_3_hwint_vld_w= i4_3_hwint_w &
`TOP_DESIGN.sparc3.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc3.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc3.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc3.tlu.tcl.tlz_trap_g[3:0]));
assign i4_3_sftint_vld_w= i4_3_sftint_w &
`TOP_DESIGN.sparc3.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc3.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc3.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc3.tlu.tcl.tlz_trap_g[3:0]));
assign i4_3_hint_vld_w= i4_3_hint_w &
`TOP_DESIGN.sparc3.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc3.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc3.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc3.tlu.tcl.tlz_trap_g[3:0]));
assign i4_3_tick_match= `TOP_DESIGN.sparc3.tlu.tdp.tickcmp_int[3:0];
assign i4_3_stick_match= `TOP_DESIGN.sparc3.tlu.tdp.stickcmp_int[3:0];
assign i4_3_hstick_match= `TOP_DESIGN.sparc3.tlu.tdp.tlu_set_hintp_g[3:0];
assign i4_3_ld_int = `TOP_DESIGN.sparc3.tlu.intdp.inc_ind_ld_int_i1;
assign i4_3_cpx_tid = `TOP_DESIGN.sparc3.lsu.qdp2.cpx_spc_data_cx[`CPX_TH_HI:`CPX_TH_LO];
assign i4_3_itlb_repl_vld = `TOP_DESIGN.sparc3.ifu.itlb.wr_vld &
~`TOP_DESIGN.sparc3.ifu.itlb.rw_index_vld;
assign i4_3_dtlb_repl_vld = `TOP_DESIGN.sparc3.lsu.dtlb.wr_vld &
~`TOP_DESIGN.sparc3.lsu.dtlb.rw_index_vld;
assign i4_3_tlb_repl_vec[63:0] = i4_3_itlb_repl_vld ?
`TOP_DESIGN.sparc3.ifu.itlb.tlb_entry_replace[63:0] :
`TOP_DESIGN.sparc3.lsu.dtlb.tlb_entry_replace[63:0];
assign i4_3_tlb_repl_idx[5] = |(i4_3_tlb_repl_vec[63:32]);
assign i4_3_tlb_repl_idx[4] =
|(i4_3_tlb_repl_vec[63:48]) | |(i4_3_tlb_repl_vec[31:16]);
assign i4_3_tlb_repl_idx[3] =
|(i4_3_tlb_repl_vec[63:56]) | |(i4_3_tlb_repl_vec[47:40]) |
|(i4_3_tlb_repl_vec[31:24]) | |(i4_3_tlb_repl_vec[15:8]);
assign i4_3_tlb_repl_idx[2] =
|(i4_3_tlb_repl_vec[63:60]) | |(i4_3_tlb_repl_vec[55:52]) |
|(i4_3_tlb_repl_vec[47:44]) | |(i4_3_tlb_repl_vec[39:36]) |
|(i4_3_tlb_repl_vec[31:28]) | |(i4_3_tlb_repl_vec[23:20]) |
|(i4_3_tlb_repl_vec[15:12]) | |(i4_3_tlb_repl_vec[7:4]);
assign i4_3_tlb_repl_idx[1] =
|(i4_3_tlb_repl_vec[63:62]) | |(i4_3_tlb_repl_vec[59:58]) |
|(i4_3_tlb_repl_vec[55:54]) | |(i4_3_tlb_repl_vec[51:50]) |
|(i4_3_tlb_repl_vec[47:46]) | |(i4_3_tlb_repl_vec[43:42]) |
|(i4_3_tlb_repl_vec[39:38]) | |(i4_3_tlb_repl_vec[35:34]) |
|(i4_3_tlb_repl_vec[31:30]) | |(i4_3_tlb_repl_vec[27:26]) |
|(i4_3_tlb_repl_vec[23:22]) | |(i4_3_tlb_repl_vec[19:18]) |
|(i4_3_tlb_repl_vec[15:14]) | |(i4_3_tlb_repl_vec[11:10]) |
|(i4_3_tlb_repl_vec[7:6]) | |(i4_3_tlb_repl_vec[3:2]);
assign i4_3_tlb_repl_idx[0] =
i4_3_tlb_repl_vec[63] | i4_3_tlb_repl_vec[61] |
i4_3_tlb_repl_vec[59] | i4_3_tlb_repl_vec[57] |
i4_3_tlb_repl_vec[55] | i4_3_tlb_repl_vec[53] |
i4_3_tlb_repl_vec[51] | i4_3_tlb_repl_vec[49] |
i4_3_tlb_repl_vec[47] | i4_3_tlb_repl_vec[45] |
i4_3_tlb_repl_vec[43] | i4_3_tlb_repl_vec[41] |
i4_3_tlb_repl_vec[39] | i4_3_tlb_repl_vec[37] |
i4_3_tlb_repl_vec[35] | i4_3_tlb_repl_vec[33] |
i4_3_tlb_repl_vec[31] | i4_3_tlb_repl_vec[29] |
i4_3_tlb_repl_vec[27] | i4_3_tlb_repl_vec[25] |
i4_3_tlb_repl_vec[23] | i4_3_tlb_repl_vec[21] |
i4_3_tlb_repl_vec[19] | i4_3_tlb_repl_vec[17] |
i4_3_tlb_repl_vec[15] | i4_3_tlb_repl_vec[13] |
i4_3_tlb_repl_vec[11] | i4_3_tlb_repl_vec[9] |
i4_3_tlb_repl_vec[7] | i4_3_tlb_repl_vec[5] |
i4_3_tlb_repl_vec[3] | i4_3_tlb_repl_vec[1];
`endif // ifdef RTL_SPARC3
`ifdef RTL_SPARC4
assign i4_4_trap = `TOP_DESIGN.sparc4.tlu.tcl.thrd0_traps |
`TOP_DESIGN.sparc4.tlu.tcl.thrd1_traps |
`TOP_DESIGN.sparc4.tlu.tcl.thrd2_traps |
`TOP_DESIGN.sparc4.tlu.tcl.thrd3_traps;
assign i4_4_immu_miss= i4_4_trap &
((`TOP_DESIGN.sparc4.tlu.tcl.sas_final_ttype_g[8:0]=='h64) |
(`TOP_DESIGN.sparc4.tlu.tcl.sas_final_ttype_g[8:0]=='h3e));
assign i4_4_dmmu_miss= i4_4_trap &
((`TOP_DESIGN.sparc4.tlu.tcl.sas_final_ttype_g[8:0]=='h68) |
(`TOP_DESIGN.sparc4.tlu.tcl.sas_final_ttype_g[8:0]=='h3f));
assign i4_4_spu_trap_ack_w= `TOP_DESIGN.sparc4.ifu_spu_trap_ack;
assign i4_4_spu_illgl_va= `TOP_DESIGN.sparc4.spu_lsu_ldxa_data_vld_w2 &
`TOP_DESIGN.sparc4.spu_lsu_ldxa_illgl_va_w2;
assign i4_4_rstint_vld_w= i4_4_rstint_w &
`TOP_DESIGN.sparc4.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc4.ifu.ifu_tlu_flush_w;
assign i4_4_hwint_vld_w= i4_4_hwint_w &
`TOP_DESIGN.sparc4.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc4.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc4.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc4.tlu.tcl.tlz_trap_g[3:0]));
assign i4_4_sftint_vld_w= i4_4_sftint_w &
`TOP_DESIGN.sparc4.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc4.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc4.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc4.tlu.tcl.tlz_trap_g[3:0]));
assign i4_4_hint_vld_w= i4_4_hint_w &
`TOP_DESIGN.sparc4.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc4.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc4.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc4.tlu.tcl.tlz_trap_g[3:0]));
assign i4_4_tick_match= `TOP_DESIGN.sparc4.tlu.tdp.tickcmp_int[3:0];
assign i4_4_stick_match= `TOP_DESIGN.sparc4.tlu.tdp.stickcmp_int[3:0];
assign i4_4_hstick_match= `TOP_DESIGN.sparc4.tlu.tdp.tlu_set_hintp_g[3:0];
assign i4_4_ld_int = `TOP_DESIGN.sparc4.tlu.intdp.inc_ind_ld_int_i1;
assign i4_4_cpx_tid = `TOP_DESIGN.sparc4.lsu.qdp2.cpx_spc_data_cx[`CPX_TH_HI:`CPX_TH_LO];
assign i4_4_itlb_repl_vld = `TOP_DESIGN.sparc4.ifu.itlb.wr_vld &
~`TOP_DESIGN.sparc4.ifu.itlb.rw_index_vld;
assign i4_4_dtlb_repl_vld = `TOP_DESIGN.sparc4.lsu.dtlb.wr_vld &
~`TOP_DESIGN.sparc4.lsu.dtlb.rw_index_vld;
assign i4_4_tlb_repl_vec[63:0] = i4_4_itlb_repl_vld ?
`TOP_DESIGN.sparc4.ifu.itlb.tlb_entry_replace[63:0] :
`TOP_DESIGN.sparc4.lsu.dtlb.tlb_entry_replace[63:0];
assign i4_4_tlb_repl_idx[5] = |(i4_4_tlb_repl_vec[63:32]);
assign i4_4_tlb_repl_idx[4] =
|(i4_4_tlb_repl_vec[63:48]) | |(i4_4_tlb_repl_vec[31:16]);
assign i4_4_tlb_repl_idx[3] =
|(i4_4_tlb_repl_vec[63:56]) | |(i4_4_tlb_repl_vec[47:40]) |
|(i4_4_tlb_repl_vec[31:24]) | |(i4_4_tlb_repl_vec[15:8]);
assign i4_4_tlb_repl_idx[2] =
|(i4_4_tlb_repl_vec[63:60]) | |(i4_4_tlb_repl_vec[55:52]) |
|(i4_4_tlb_repl_vec[47:44]) | |(i4_4_tlb_repl_vec[39:36]) |
|(i4_4_tlb_repl_vec[31:28]) | |(i4_4_tlb_repl_vec[23:20]) |
|(i4_4_tlb_repl_vec[15:12]) | |(i4_4_tlb_repl_vec[7:4]);
assign i4_4_tlb_repl_idx[1] =
|(i4_4_tlb_repl_vec[63:62]) | |(i4_4_tlb_repl_vec[59:58]) |
|(i4_4_tlb_repl_vec[55:54]) | |(i4_4_tlb_repl_vec[51:50]) |
|(i4_4_tlb_repl_vec[47:46]) | |(i4_4_tlb_repl_vec[43:42]) |
|(i4_4_tlb_repl_vec[39:38]) | |(i4_4_tlb_repl_vec[35:34]) |
|(i4_4_tlb_repl_vec[31:30]) | |(i4_4_tlb_repl_vec[27:26]) |
|(i4_4_tlb_repl_vec[23:22]) | |(i4_4_tlb_repl_vec[19:18]) |
|(i4_4_tlb_repl_vec[15:14]) | |(i4_4_tlb_repl_vec[11:10]) |
|(i4_4_tlb_repl_vec[7:6]) | |(i4_4_tlb_repl_vec[3:2]);
assign i4_4_tlb_repl_idx[0] =
i4_4_tlb_repl_vec[63] | i4_4_tlb_repl_vec[61] |
i4_4_tlb_repl_vec[59] | i4_4_tlb_repl_vec[57] |
i4_4_tlb_repl_vec[55] | i4_4_tlb_repl_vec[53] |
i4_4_tlb_repl_vec[51] | i4_4_tlb_repl_vec[49] |
i4_4_tlb_repl_vec[47] | i4_4_tlb_repl_vec[45] |
i4_4_tlb_repl_vec[43] | i4_4_tlb_repl_vec[41] |
i4_4_tlb_repl_vec[39] | i4_4_tlb_repl_vec[37] |
i4_4_tlb_repl_vec[35] | i4_4_tlb_repl_vec[33] |
i4_4_tlb_repl_vec[31] | i4_4_tlb_repl_vec[29] |
i4_4_tlb_repl_vec[27] | i4_4_tlb_repl_vec[25] |
i4_4_tlb_repl_vec[23] | i4_4_tlb_repl_vec[21] |
i4_4_tlb_repl_vec[19] | i4_4_tlb_repl_vec[17] |
i4_4_tlb_repl_vec[15] | i4_4_tlb_repl_vec[13] |
i4_4_tlb_repl_vec[11] | i4_4_tlb_repl_vec[9] |
i4_4_tlb_repl_vec[7] | i4_4_tlb_repl_vec[5] |
i4_4_tlb_repl_vec[3] | i4_4_tlb_repl_vec[1];
`endif // ifdef RTL_SPARC4
`ifdef RTL_SPARC5
assign i4_5_trap = `TOP_DESIGN.sparc5.tlu.tcl.thrd0_traps |
`TOP_DESIGN.sparc5.tlu.tcl.thrd1_traps |
`TOP_DESIGN.sparc5.tlu.tcl.thrd2_traps |
`TOP_DESIGN.sparc5.tlu.tcl.thrd3_traps;
assign i4_5_immu_miss= i4_5_trap &
((`TOP_DESIGN.sparc5.tlu.tcl.sas_final_ttype_g[8:0]=='h64) |
(`TOP_DESIGN.sparc5.tlu.tcl.sas_final_ttype_g[8:0]=='h3e));
assign i4_5_dmmu_miss= i4_5_trap &
((`TOP_DESIGN.sparc5.tlu.tcl.sas_final_ttype_g[8:0]=='h68) |
(`TOP_DESIGN.sparc5.tlu.tcl.sas_final_ttype_g[8:0]=='h3f));
assign i4_5_spu_trap_ack_w= `TOP_DESIGN.sparc5.ifu_spu_trap_ack;
assign i4_5_spu_illgl_va= `TOP_DESIGN.sparc5.spu_lsu_ldxa_data_vld_w2 &
`TOP_DESIGN.sparc5.spu_lsu_ldxa_illgl_va_w2;
assign i4_5_rstint_vld_w= i4_5_rstint_w &
`TOP_DESIGN.sparc5.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc5.ifu.ifu_tlu_flush_w;
assign i4_5_hwint_vld_w= i4_5_hwint_w &
`TOP_DESIGN.sparc5.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc5.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc5.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc5.tlu.tcl.tlz_trap_g[3:0]));
assign i4_5_sftint_vld_w= i4_5_sftint_w &
`TOP_DESIGN.sparc5.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc5.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc5.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc5.tlu.tcl.tlz_trap_g[3:0]));
assign i4_5_hint_vld_w= i4_5_hint_w &
`TOP_DESIGN.sparc5.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc5.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc5.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc5.tlu.tcl.tlz_trap_g[3:0]));
assign i4_5_tick_match= `TOP_DESIGN.sparc5.tlu.tdp.tickcmp_int[3:0];
assign i4_5_stick_match= `TOP_DESIGN.sparc5.tlu.tdp.stickcmp_int[3:0];
assign i4_5_hstick_match= `TOP_DESIGN.sparc5.tlu.tdp.tlu_set_hintp_g[3:0];
assign i4_5_ld_int = `TOP_DESIGN.sparc5.tlu.intdp.inc_ind_ld_int_i1;
assign i4_5_cpx_tid = `TOP_DESIGN.sparc5.lsu.qdp2.cpx_spc_data_cx[`CPX_TH_HI:`CPX_TH_LO];
assign i4_5_itlb_repl_vld = `TOP_DESIGN.sparc5.ifu.itlb.wr_vld &
~`TOP_DESIGN.sparc5.ifu.itlb.rw_index_vld;
assign i4_5_dtlb_repl_vld = `TOP_DESIGN.sparc5.lsu.dtlb.wr_vld &
~`TOP_DESIGN.sparc5.lsu.dtlb.rw_index_vld;
assign i4_5_tlb_repl_vec[63:0] = i4_5_itlb_repl_vld ?
`TOP_DESIGN.sparc5.ifu.itlb.tlb_entry_replace[63:0] :
`TOP_DESIGN.sparc5.lsu.dtlb.tlb_entry_replace[63:0];
assign i4_5_tlb_repl_idx[5] = |(i4_5_tlb_repl_vec[63:32]);
assign i4_5_tlb_repl_idx[4] =
|(i4_5_tlb_repl_vec[63:48]) | |(i4_5_tlb_repl_vec[31:16]);
assign i4_5_tlb_repl_idx[3] =
|(i4_5_tlb_repl_vec[63:56]) | |(i4_5_tlb_repl_vec[47:40]) |
|(i4_5_tlb_repl_vec[31:24]) | |(i4_5_tlb_repl_vec[15:8]);
assign i4_5_tlb_repl_idx[2] =
|(i4_5_tlb_repl_vec[63:60]) | |(i4_5_tlb_repl_vec[55:52]) |
|(i4_5_tlb_repl_vec[47:44]) | |(i4_5_tlb_repl_vec[39:36]) |
|(i4_5_tlb_repl_vec[31:28]) | |(i4_5_tlb_repl_vec[23:20]) |
|(i4_5_tlb_repl_vec[15:12]) | |(i4_5_tlb_repl_vec[7:4]);
assign i4_5_tlb_repl_idx[1] =
|(i4_5_tlb_repl_vec[63:62]) | |(i4_5_tlb_repl_vec[59:58]) |
|(i4_5_tlb_repl_vec[55:54]) | |(i4_5_tlb_repl_vec[51:50]) |
|(i4_5_tlb_repl_vec[47:46]) | |(i4_5_tlb_repl_vec[43:42]) |
|(i4_5_tlb_repl_vec[39:38]) | |(i4_5_tlb_repl_vec[35:34]) |
|(i4_5_tlb_repl_vec[31:30]) | |(i4_5_tlb_repl_vec[27:26]) |
|(i4_5_tlb_repl_vec[23:22]) | |(i4_5_tlb_repl_vec[19:18]) |
|(i4_5_tlb_repl_vec[15:14]) | |(i4_5_tlb_repl_vec[11:10]) |
|(i4_5_tlb_repl_vec[7:6]) | |(i4_5_tlb_repl_vec[3:2]);
assign i4_5_tlb_repl_idx[0] =
i4_5_tlb_repl_vec[63] | i4_5_tlb_repl_vec[61] |
i4_5_tlb_repl_vec[59] | i4_5_tlb_repl_vec[57] |
i4_5_tlb_repl_vec[55] | i4_5_tlb_repl_vec[53] |
i4_5_tlb_repl_vec[51] | i4_5_tlb_repl_vec[49] |
i4_5_tlb_repl_vec[47] | i4_5_tlb_repl_vec[45] |
i4_5_tlb_repl_vec[43] | i4_5_tlb_repl_vec[41] |
i4_5_tlb_repl_vec[39] | i4_5_tlb_repl_vec[37] |
i4_5_tlb_repl_vec[35] | i4_5_tlb_repl_vec[33] |
i4_5_tlb_repl_vec[31] | i4_5_tlb_repl_vec[29] |
i4_5_tlb_repl_vec[27] | i4_5_tlb_repl_vec[25] |
i4_5_tlb_repl_vec[23] | i4_5_tlb_repl_vec[21] |
i4_5_tlb_repl_vec[19] | i4_5_tlb_repl_vec[17] |
i4_5_tlb_repl_vec[15] | i4_5_tlb_repl_vec[13] |
i4_5_tlb_repl_vec[11] | i4_5_tlb_repl_vec[9] |
i4_5_tlb_repl_vec[7] | i4_5_tlb_repl_vec[5] |
i4_5_tlb_repl_vec[3] | i4_5_tlb_repl_vec[1];
`endif // ifdef RTL_SPARC5
`ifdef RTL_SPARC6
assign i4_6_trap = `TOP_DESIGN.sparc6.tlu.tcl.thrd0_traps |
`TOP_DESIGN.sparc6.tlu.tcl.thrd1_traps |
`TOP_DESIGN.sparc6.tlu.tcl.thrd2_traps |
`TOP_DESIGN.sparc6.tlu.tcl.thrd3_traps;
assign i4_6_immu_miss= i4_6_trap &
((`TOP_DESIGN.sparc6.tlu.tcl.sas_final_ttype_g[8:0]=='h64) |
(`TOP_DESIGN.sparc6.tlu.tcl.sas_final_ttype_g[8:0]=='h3e));
assign i4_6_dmmu_miss= i4_6_trap &
((`TOP_DESIGN.sparc6.tlu.tcl.sas_final_ttype_g[8:0]=='h68) |
(`TOP_DESIGN.sparc6.tlu.tcl.sas_final_ttype_g[8:0]=='h3f));
assign i4_6_spu_trap_ack_w= `TOP_DESIGN.sparc6.ifu_spu_trap_ack;
assign i4_6_spu_illgl_va= `TOP_DESIGN.sparc6.spu_lsu_ldxa_data_vld_w2 &
`TOP_DESIGN.sparc6.spu_lsu_ldxa_illgl_va_w2;
assign i4_6_rstint_vld_w= i4_6_rstint_w &
`TOP_DESIGN.sparc6.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc6.ifu.ifu_tlu_flush_w;
assign i4_6_hwint_vld_w= i4_6_hwint_w &
`TOP_DESIGN.sparc6.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc6.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc6.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc6.tlu.tcl.tlz_trap_g[3:0]));
assign i4_6_sftint_vld_w= i4_6_sftint_w &
`TOP_DESIGN.sparc6.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc6.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc6.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc6.tlu.tcl.tlz_trap_g[3:0]));
assign i4_6_hint_vld_w= i4_6_hint_w &
`TOP_DESIGN.sparc6.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc6.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc6.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc6.tlu.tcl.tlz_trap_g[3:0]));
assign i4_6_tick_match= `TOP_DESIGN.sparc6.tlu.tdp.tickcmp_int[3:0];
assign i4_6_stick_match= `TOP_DESIGN.sparc6.tlu.tdp.stickcmp_int[3:0];
assign i4_6_hstick_match= `TOP_DESIGN.sparc6.tlu.tdp.tlu_set_hintp_g[3:0];
assign i4_6_ld_int = `TOP_DESIGN.sparc6.tlu.intdp.inc_ind_ld_int_i1;
assign i4_6_cpx_tid = `TOP_DESIGN.sparc6.lsu.qdp2.cpx_spc_data_cx[`CPX_TH_HI:`CPX_TH_LO];
assign i4_6_itlb_repl_vld = `TOP_DESIGN.sparc6.ifu.itlb.wr_vld &
~`TOP_DESIGN.sparc6.ifu.itlb.rw_index_vld;
assign i4_6_dtlb_repl_vld = `TOP_DESIGN.sparc6.lsu.dtlb.wr_vld &
~`TOP_DESIGN.sparc6.lsu.dtlb.rw_index_vld;
assign i4_6_tlb_repl_vec[63:0] = i4_6_itlb_repl_vld ?
`TOP_DESIGN.sparc6.ifu.itlb.tlb_entry_replace[63:0] :
`TOP_DESIGN.sparc6.lsu.dtlb.tlb_entry_replace[63:0];
assign i4_6_tlb_repl_idx[5] = |(i4_6_tlb_repl_vec[63:32]);
assign i4_6_tlb_repl_idx[4] =
|(i4_6_tlb_repl_vec[63:48]) | |(i4_6_tlb_repl_vec[31:16]);
assign i4_6_tlb_repl_idx[3] =
|(i4_6_tlb_repl_vec[63:56]) | |(i4_6_tlb_repl_vec[47:40]) |
|(i4_6_tlb_repl_vec[31:24]) | |(i4_6_tlb_repl_vec[15:8]);
assign i4_6_tlb_repl_idx[2] =
|(i4_6_tlb_repl_vec[63:60]) | |(i4_6_tlb_repl_vec[55:52]) |
|(i4_6_tlb_repl_vec[47:44]) | |(i4_6_tlb_repl_vec[39:36]) |
|(i4_6_tlb_repl_vec[31:28]) | |(i4_6_tlb_repl_vec[23:20]) |
|(i4_6_tlb_repl_vec[15:12]) | |(i4_6_tlb_repl_vec[7:4]);
assign i4_6_tlb_repl_idx[1] =
|(i4_6_tlb_repl_vec[63:62]) | |(i4_6_tlb_repl_vec[59:58]) |
|(i4_6_tlb_repl_vec[55:54]) | |(i4_6_tlb_repl_vec[51:50]) |
|(i4_6_tlb_repl_vec[47:46]) | |(i4_6_tlb_repl_vec[43:42]) |
|(i4_6_tlb_repl_vec[39:38]) | |(i4_6_tlb_repl_vec[35:34]) |
|(i4_6_tlb_repl_vec[31:30]) | |(i4_6_tlb_repl_vec[27:26]) |
|(i4_6_tlb_repl_vec[23:22]) | |(i4_6_tlb_repl_vec[19:18]) |
|(i4_6_tlb_repl_vec[15:14]) | |(i4_6_tlb_repl_vec[11:10]) |
|(i4_6_tlb_repl_vec[7:6]) | |(i4_6_tlb_repl_vec[3:2]);
assign i4_6_tlb_repl_idx[0] =
i4_6_tlb_repl_vec[63] | i4_6_tlb_repl_vec[61] |
i4_6_tlb_repl_vec[59] | i4_6_tlb_repl_vec[57] |
i4_6_tlb_repl_vec[55] | i4_6_tlb_repl_vec[53] |
i4_6_tlb_repl_vec[51] | i4_6_tlb_repl_vec[49] |
i4_6_tlb_repl_vec[47] | i4_6_tlb_repl_vec[45] |
i4_6_tlb_repl_vec[43] | i4_6_tlb_repl_vec[41] |
i4_6_tlb_repl_vec[39] | i4_6_tlb_repl_vec[37] |
i4_6_tlb_repl_vec[35] | i4_6_tlb_repl_vec[33] |
i4_6_tlb_repl_vec[31] | i4_6_tlb_repl_vec[29] |
i4_6_tlb_repl_vec[27] | i4_6_tlb_repl_vec[25] |
i4_6_tlb_repl_vec[23] | i4_6_tlb_repl_vec[21] |
i4_6_tlb_repl_vec[19] | i4_6_tlb_repl_vec[17] |
i4_6_tlb_repl_vec[15] | i4_6_tlb_repl_vec[13] |
i4_6_tlb_repl_vec[11] | i4_6_tlb_repl_vec[9] |
i4_6_tlb_repl_vec[7] | i4_6_tlb_repl_vec[5] |
i4_6_tlb_repl_vec[3] | i4_6_tlb_repl_vec[1];
`endif // ifdef RTL_SPARC6
`ifdef RTL_SPARC7
assign i4_7_trap = `TOP_DESIGN.sparc7.tlu.tcl.thrd0_traps |
`TOP_DESIGN.sparc7.tlu.tcl.thrd1_traps |
`TOP_DESIGN.sparc7.tlu.tcl.thrd2_traps |
`TOP_DESIGN.sparc7.tlu.tcl.thrd3_traps;
assign i4_7_immu_miss= i4_7_trap &
((`TOP_DESIGN.sparc7.tlu.tcl.sas_final_ttype_g[8:0]=='h64) |
(`TOP_DESIGN.sparc7.tlu.tcl.sas_final_ttype_g[8:0]=='h3e));
assign i4_7_dmmu_miss= i4_7_trap &
((`TOP_DESIGN.sparc7.tlu.tcl.sas_final_ttype_g[8:0]=='h68) |
(`TOP_DESIGN.sparc7.tlu.tcl.sas_final_ttype_g[8:0]=='h3f));
assign i4_7_spu_trap_ack_w= `TOP_DESIGN.sparc7.ifu_spu_trap_ack;
assign i4_7_spu_illgl_va= `TOP_DESIGN.sparc7.spu_lsu_ldxa_data_vld_w2 &
`TOP_DESIGN.sparc7.spu_lsu_ldxa_illgl_va_w2;
assign i4_7_rstint_vld_w= i4_7_rstint_w &
`TOP_DESIGN.sparc7.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc7.ifu.ifu_tlu_flush_w;
assign i4_7_hwint_vld_w= i4_7_hwint_w &
`TOP_DESIGN.sparc7.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc7.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc7.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc7.tlu.tcl.tlz_trap_g[3:0]));
assign i4_7_sftint_vld_w= i4_7_sftint_w &
`TOP_DESIGN.sparc7.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc7.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc7.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc7.tlu.tcl.tlz_trap_g[3:0]));
assign i4_7_hint_vld_w= i4_7_hint_w &
`TOP_DESIGN.sparc7.ifu.ifu_tlu_inst_vld_w &
~`TOP_DESIGN.sparc7.ifu.ifu_tlu_flush_w &
~`TOP_DESIGN.sparc7.tlu.lsu_tlu_defr_trp_taken_g &
~(|(`TOP_DESIGN.sparc7.tlu.tcl.tlz_trap_g[3:0]));
assign i4_7_tick_match= `TOP_DESIGN.sparc7.tlu.tdp.tickcmp_int[3:0];
assign i4_7_stick_match= `TOP_DESIGN.sparc7.tlu.tdp.stickcmp_int[3:0];
assign i4_7_hstick_match= `TOP_DESIGN.sparc7.tlu.tdp.tlu_set_hintp_g[3:0];
assign i4_7_ld_int = `TOP_DESIGN.sparc7.tlu.intdp.inc_ind_ld_int_i1;
assign i4_7_cpx_tid = `TOP_DESIGN.sparc7.lsu.qdp2.cpx_spc_data_cx[`CPX_TH_HI:`CPX_TH_LO];
assign i4_7_itlb_repl_vld = `TOP_DESIGN.sparc7.ifu.itlb.wr_vld &
~`TOP_DESIGN.sparc7.ifu.itlb.rw_index_vld;
assign i4_7_dtlb_repl_vld = `TOP_DESIGN.sparc7.lsu.dtlb.wr_vld &
~`TOP_DESIGN.sparc7.lsu.dtlb.rw_index_vld;
assign i4_7_tlb_repl_vec[63:0] = i4_7_itlb_repl_vld ?
`TOP_DESIGN.sparc7.ifu.itlb.tlb_entry_replace[63:0] :
`TOP_DESIGN.sparc7.lsu.dtlb.tlb_entry_replace[63:0];
assign i4_7_tlb_repl_idx[5] = |(i4_7_tlb_repl_vec[63:32]);
assign i4_7_tlb_repl_idx[4] =
|(i4_7_tlb_repl_vec[63:48]) | |(i4_7_tlb_repl_vec[31:16]);
assign i4_7_tlb_repl_idx[3] =
|(i4_7_tlb_repl_vec[63:56]) | |(i4_7_tlb_repl_vec[47:40]) |
|(i4_7_tlb_repl_vec[31:24]) | |(i4_7_tlb_repl_vec[15:8]);
assign i4_7_tlb_repl_idx[2] =
|(i4_7_tlb_repl_vec[63:60]) | |(i4_7_tlb_repl_vec[55:52]) |
|(i4_7_tlb_repl_vec[47:44]) | |(i4_7_tlb_repl_vec[39:36]) |
|(i4_7_tlb_repl_vec[31:28]) | |(i4_7_tlb_repl_vec[23:20]) |
|(i4_7_tlb_repl_vec[15:12]) | |(i4_7_tlb_repl_vec[7:4]);
assign i4_7_tlb_repl_idx[1] =
|(i4_7_tlb_repl_vec[63:62]) | |(i4_7_tlb_repl_vec[59:58]) |
|(i4_7_tlb_repl_vec[55:54]) | |(i4_7_tlb_repl_vec[51:50]) |
|(i4_7_tlb_repl_vec[47:46]) | |(i4_7_tlb_repl_vec[43:42]) |
|(i4_7_tlb_repl_vec[39:38]) | |(i4_7_tlb_repl_vec[35:34]) |
|(i4_7_tlb_repl_vec[31:30]) | |(i4_7_tlb_repl_vec[27:26]) |
|(i4_7_tlb_repl_vec[23:22]) | |(i4_7_tlb_repl_vec[19:18]) |
|(i4_7_tlb_repl_vec[15:14]) | |(i4_7_tlb_repl_vec[11:10]) |
|(i4_7_tlb_repl_vec[7:6]) | |(i4_7_tlb_repl_vec[3:2]);
assign i4_7_tlb_repl_idx[0] =
i4_7_tlb_repl_vec[63] | i4_7_tlb_repl_vec[61] |
i4_7_tlb_repl_vec[59] | i4_7_tlb_repl_vec[57] |
i4_7_tlb_repl_vec[55] | i4_7_tlb_repl_vec[53] |
i4_7_tlb_repl_vec[51] | i4_7_tlb_repl_vec[49] |
i4_7_tlb_repl_vec[47] | i4_7_tlb_repl_vec[45] |
i4_7_tlb_repl_vec[43] | i4_7_tlb_repl_vec[41] |
i4_7_tlb_repl_vec[39] | i4_7_tlb_repl_vec[37] |
i4_7_tlb_repl_vec[35] | i4_7_tlb_repl_vec[33] |
i4_7_tlb_repl_vec[31] | i4_7_tlb_repl_vec[29] |
i4_7_tlb_repl_vec[27] | i4_7_tlb_repl_vec[25] |
i4_7_tlb_repl_vec[23] | i4_7_tlb_repl_vec[21] |
i4_7_tlb_repl_vec[19] | i4_7_tlb_repl_vec[17] |
i4_7_tlb_repl_vec[15] | i4_7_tlb_repl_vec[13] |
i4_7_tlb_repl_vec[11] | i4_7_tlb_repl_vec[9] |
i4_7_tlb_repl_vec[7] | i4_7_tlb_repl_vec[5] |
i4_7_tlb_repl_vec[3] | i4_7_tlb_repl_vec[1];
`endif // ifdef RTL_SPARC7
`ifdef RTL_SPARC0
assign i4_0_data =
{1'b0,
1'b0,
1'b0,
`TOP_DESIGN.sparc0.spu_lsu_ldxa_tid_w2[1:0],
`TOP_DESIGN.sparc0.tlu.tcl.sftintctr[1:0],
i4_0_tlb_repl_idx[5:0],
`TOP_DESIGN.sparc0.tlu.mmu_ctl.tlb_access_tid_g[1:0],
i4_0_itlb_repl_vld,
i4_0_dtlb_repl_vld,
i4_0_spu_illgl_va,
i4_0_ld_int[3:0],
i4_0_hstick_match[3:0],
i4_0_stick_match[3:0],
i4_0_tick_match[3:0],
i4_0_hint_vld_w,
i4_0_sftint_vld_w,
i4_0_hwint_vld_w,
i4_0_rstint_vld_w,
i4_0_int_thr_w[3:0],
i4_0_spu_trap_ack_w,
i4_0_fill_dcache_w,
`TOP_DESIGN.sparc0.spu_ifu_ttype_vld_w2,
`TOP_DESIGN.sparc0.spu_ifu_ttype_w2,
`TOP_DESIGN.sparc0.spu_ifu_ttype_tid_w2[1:0],
i4_0_immu_miss,
i4_0_dmmu_miss,
`TOP_DESIGN.sparc0.tlu.tcl.trap_tid_g[1:0],
i4_0_fprs_set_w[3:0],
i4_0_new_fprs_w[1:0],
`TOP_DESIGN.sparc0.lsu.qctl2.cpx_st_ack_tid0,
`TOP_DESIGN.sparc0.lsu.qctl2.cpx_st_ack_tid1,
`TOP_DESIGN.sparc0.lsu.qctl2.cpx_st_ack_tid2,
`TOP_DESIGN.sparc0.lsu.qctl2.cpx_st_ack_tid3,
i4_0_cpx_tid[1:0],
i4_0_ic_inv_vld_s,
i4_0_ic_inv_addr_s[5:0],
i4_0_ic_inv_word1_s,
i4_0_ic_inv_word0_s,
i4_0_ic_inv_way1_s[1:0],
i4_0_ic_inv_way0_s[1:0],
`TOP_DESIGN.sparc0.lsu.qctl2.cpx_ifill_type,
`TOP_DESIGN.sparc0.lsu.qctl2.cpx_ld_type,
`TOP_DESIGN.sparc0.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc0.lsu.qctl2.cpx_strm_st_ack_type,
i4_0_st_wr_dcache_w,
i4_0_dcache_fill_addr_w[9:0],
i4_0_dva_svld_w,
i4_0_dva_snp_addr_w[4:0],
i4_0_dva_snp_set_vld_w[3:0],
i4_0_dva_snp_wy3_w[1:0],
i4_0_dva_snp_wy2_w[1:0],
i4_0_dva_snp_wy1_w[1:0],
i4_0_dva_snp_wy0_w[1:0]};
assign i4_0_rdy =
(i4_0_itlb_repl_vld |
i4_0_dtlb_repl_vld |
i4_0_fprs_set_w[0] |
i4_0_fprs_set_w[1] |
i4_0_fprs_set_w[2] |
i4_0_fprs_set_w[3] |
i4_0_tick_match[0] |
i4_0_tick_match[1] |
i4_0_tick_match[2] |
i4_0_tick_match[3] |
i4_0_stick_match[0] |
i4_0_stick_match[1] |
i4_0_stick_match[2] |
i4_0_stick_match[3] |
i4_0_hstick_match[0] |
i4_0_hstick_match[1] |
i4_0_hstick_match[2] |
i4_0_hstick_match[3] |
i4_0_ld_int[0] |
i4_0_ld_int[1] |
i4_0_ld_int[2] |
i4_0_ld_int[3] |
`TOP_DESIGN.sparc0.spu_ifu_ttype_vld_w2 |
i4_0_spu_illgl_va |
i4_0_spu_trap_ack_w |
i4_0_immu_miss | i4_0_dmmu_miss |
i4_0_rstint_vld_w | i4_0_hwint_vld_w |
i4_0_sftint_vld_w | i4_0_hint_w |
`TOP_DESIGN.sparc0.lsu.qctl2.cpx_ifill_type |
`TOP_DESIGN.sparc0.lsu.qctl2.cpx_ld_type |
`TOP_DESIGN.sparc0.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc0.lsu.qctl2.cpx_strm_st_ack_type |
i4_0_ic_inv_vld_s |
i4_0_st_wr_dcache_w |
i4_0_fill_dcache_w |
i4_0_dva_svld_w);
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC1
assign i4_1_data =
{1'b0,
1'b0,
1'b0,
`TOP_DESIGN.sparc1.spu_lsu_ldxa_tid_w2[1:0],
`TOP_DESIGN.sparc1.tlu.tcl.sftintctr[1:0],
i4_1_tlb_repl_idx[5:0],
`TOP_DESIGN.sparc1.tlu.mmu_ctl.tlb_access_tid_g[1:0],
i4_1_itlb_repl_vld,
i4_1_dtlb_repl_vld,
i4_1_spu_illgl_va,
i4_1_ld_int[3:0],
i4_1_hstick_match[3:0],
i4_1_stick_match[3:0],
i4_1_tick_match[3:0],
i4_1_hint_vld_w,
i4_1_sftint_vld_w,
i4_1_hwint_vld_w,
i4_1_rstint_vld_w,
i4_1_int_thr_w[3:0],
i4_1_spu_trap_ack_w,
i4_1_fill_dcache_w,
`TOP_DESIGN.sparc1.spu_ifu_ttype_vld_w2,
`TOP_DESIGN.sparc1.spu_ifu_ttype_w2,
`TOP_DESIGN.sparc1.spu_ifu_ttype_tid_w2[1:0],
i4_1_immu_miss,
i4_1_dmmu_miss,
`TOP_DESIGN.sparc1.tlu.tcl.trap_tid_g[1:0],
i4_1_fprs_set_w[3:0],
i4_1_new_fprs_w[1:0],
`TOP_DESIGN.sparc1.lsu.qctl2.cpx_st_ack_tid0,
`TOP_DESIGN.sparc1.lsu.qctl2.cpx_st_ack_tid1,
`TOP_DESIGN.sparc1.lsu.qctl2.cpx_st_ack_tid2,
`TOP_DESIGN.sparc1.lsu.qctl2.cpx_st_ack_tid3,
i4_1_cpx_tid[1:0],
i4_1_ic_inv_vld_s,
i4_1_ic_inv_addr_s[5:0],
i4_1_ic_inv_word1_s,
i4_1_ic_inv_word0_s,
i4_1_ic_inv_way1_s[1:0],
i4_1_ic_inv_way0_s[1:0],
`TOP_DESIGN.sparc1.lsu.qctl2.cpx_ifill_type,
`TOP_DESIGN.sparc1.lsu.qctl2.cpx_ld_type,
`TOP_DESIGN.sparc1.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc1.lsu.qctl2.cpx_strm_st_ack_type,
i4_1_st_wr_dcache_w,
i4_1_dcache_fill_addr_w[9:0],
i4_1_dva_svld_w,
i4_1_dva_snp_addr_w[4:0],
i4_1_dva_snp_set_vld_w[3:0],
i4_1_dva_snp_wy3_w[1:0],
i4_1_dva_snp_wy2_w[1:0],
i4_1_dva_snp_wy1_w[1:0],
i4_1_dva_snp_wy0_w[1:0]};
assign i4_1_rdy =
(i4_1_itlb_repl_vld |
i4_1_dtlb_repl_vld |
i4_1_fprs_set_w[0] |
i4_1_fprs_set_w[1] |
i4_1_fprs_set_w[2] |
i4_1_fprs_set_w[3] |
i4_1_tick_match[0] |
i4_1_tick_match[1] |
i4_1_tick_match[2] |
i4_1_tick_match[3] |
i4_1_stick_match[0] |
i4_1_stick_match[1] |
i4_1_stick_match[2] |
i4_1_stick_match[3] |
i4_1_hstick_match[0] |
i4_1_hstick_match[1] |
i4_1_hstick_match[2] |
i4_1_hstick_match[3] |
i4_1_ld_int[0] |
i4_1_ld_int[1] |
i4_1_ld_int[2] |
i4_1_ld_int[3] |
`TOP_DESIGN.sparc1.spu_ifu_ttype_vld_w2 |
i4_1_spu_illgl_va |
i4_1_spu_trap_ack_w |
i4_1_immu_miss | i4_1_dmmu_miss |
i4_1_rstint_vld_w | i4_1_hwint_vld_w |
i4_1_sftint_vld_w | i4_1_hint_w |
`TOP_DESIGN.sparc1.lsu.qctl2.cpx_ifill_type |
`TOP_DESIGN.sparc1.lsu.qctl2.cpx_ld_type |
`TOP_DESIGN.sparc1.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc1.lsu.qctl2.cpx_strm_st_ack_type |
i4_1_ic_inv_vld_s |
i4_1_st_wr_dcache_w |
i4_1_fill_dcache_w |
i4_1_dva_svld_w);
`endif // ifdef RTL_SPARC1
`ifdef RTL_SPARC2
assign i4_2_data =
{1'b0,
1'b0,
1'b0,
`TOP_DESIGN.sparc2.spu_lsu_ldxa_tid_w2[1:0],
`TOP_DESIGN.sparc2.tlu.tcl.sftintctr[1:0],
i4_2_tlb_repl_idx[5:0],
`TOP_DESIGN.sparc2.tlu.mmu_ctl.tlb_access_tid_g[1:0],
i4_2_itlb_repl_vld,
i4_2_dtlb_repl_vld,
i4_2_spu_illgl_va,
i4_2_ld_int[3:0],
i4_2_hstick_match[3:0],
i4_2_stick_match[3:0],
i4_2_tick_match[3:0],
i4_2_hint_vld_w,
i4_2_sftint_vld_w,
i4_2_hwint_vld_w,
i4_2_rstint_vld_w,
i4_2_int_thr_w[3:0],
i4_2_spu_trap_ack_w,
i4_2_fill_dcache_w,
`TOP_DESIGN.sparc2.spu_ifu_ttype_vld_w2,
`TOP_DESIGN.sparc2.spu_ifu_ttype_w2,
`TOP_DESIGN.sparc2.spu_ifu_ttype_tid_w2[1:0],
i4_2_immu_miss,
i4_2_dmmu_miss,
`TOP_DESIGN.sparc2.tlu.tcl.trap_tid_g[1:0],
i4_2_fprs_set_w[3:0],
i4_2_new_fprs_w[1:0],
`TOP_DESIGN.sparc2.lsu.qctl2.cpx_st_ack_tid0,
`TOP_DESIGN.sparc2.lsu.qctl2.cpx_st_ack_tid1,
`TOP_DESIGN.sparc2.lsu.qctl2.cpx_st_ack_tid2,
`TOP_DESIGN.sparc2.lsu.qctl2.cpx_st_ack_tid3,
i4_2_cpx_tid[1:0],
i4_2_ic_inv_vld_s,
i4_2_ic_inv_addr_s[5:0],
i4_2_ic_inv_word1_s,
i4_2_ic_inv_word0_s,
i4_2_ic_inv_way1_s[1:0],
i4_2_ic_inv_way0_s[1:0],
`TOP_DESIGN.sparc2.lsu.qctl2.cpx_ifill_type,
`TOP_DESIGN.sparc2.lsu.qctl2.cpx_ld_type,
`TOP_DESIGN.sparc2.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc2.lsu.qctl2.cpx_strm_st_ack_type,
i4_2_st_wr_dcache_w,
i4_2_dcache_fill_addr_w[9:0],
i4_2_dva_svld_w,
i4_2_dva_snp_addr_w[4:0],
i4_2_dva_snp_set_vld_w[3:0],
i4_2_dva_snp_wy3_w[1:0],
i4_2_dva_snp_wy2_w[1:0],
i4_2_dva_snp_wy1_w[1:0],
i4_2_dva_snp_wy0_w[1:0]};
assign i4_2_rdy =
(i4_2_itlb_repl_vld |
i4_2_dtlb_repl_vld |
i4_2_fprs_set_w[0] |
i4_2_fprs_set_w[1] |
i4_2_fprs_set_w[2] |
i4_2_fprs_set_w[3] |
i4_2_tick_match[0] |
i4_2_tick_match[1] |
i4_2_tick_match[2] |
i4_2_tick_match[3] |
i4_2_stick_match[0] |
i4_2_stick_match[1] |
i4_2_stick_match[2] |
i4_2_stick_match[3] |
i4_2_hstick_match[0] |
i4_2_hstick_match[1] |
i4_2_hstick_match[2] |
i4_2_hstick_match[3] |
i4_2_ld_int[0] |
i4_2_ld_int[1] |
i4_2_ld_int[2] |
i4_2_ld_int[3] |
`TOP_DESIGN.sparc2.spu_ifu_ttype_vld_w2 |
i4_2_spu_illgl_va |
i4_2_spu_trap_ack_w |
i4_2_immu_miss | i4_2_dmmu_miss |
i4_2_rstint_vld_w | i4_2_hwint_vld_w |
i4_2_sftint_vld_w | i4_2_hint_w |
`TOP_DESIGN.sparc2.lsu.qctl2.cpx_ifill_type |
`TOP_DESIGN.sparc2.lsu.qctl2.cpx_ld_type |
`TOP_DESIGN.sparc2.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc2.lsu.qctl2.cpx_strm_st_ack_type |
i4_2_ic_inv_vld_s |
i4_2_st_wr_dcache_w |
i4_2_fill_dcache_w |
i4_2_dva_svld_w);
`endif // ifdef RTL_SPARC2
`ifdef RTL_SPARC3
assign i4_3_data =
{1'b0,
1'b0,
1'b0,
`TOP_DESIGN.sparc3.spu_lsu_ldxa_tid_w2[1:0],
`TOP_DESIGN.sparc3.tlu.tcl.sftintctr[1:0],
i4_3_tlb_repl_idx[5:0],
`TOP_DESIGN.sparc3.tlu.mmu_ctl.tlb_access_tid_g[1:0],
i4_3_itlb_repl_vld,
i4_3_dtlb_repl_vld,
i4_3_spu_illgl_va,
i4_3_ld_int[3:0],
i4_3_hstick_match[3:0],
i4_3_stick_match[3:0],
i4_3_tick_match[3:0],
i4_3_hint_vld_w,
i4_3_sftint_vld_w,
i4_3_hwint_vld_w,
i4_3_rstint_vld_w,
i4_3_int_thr_w[3:0],
i4_3_spu_trap_ack_w,
i4_3_fill_dcache_w,
`TOP_DESIGN.sparc3.spu_ifu_ttype_vld_w2,
`TOP_DESIGN.sparc3.spu_ifu_ttype_w2,
`TOP_DESIGN.sparc3.spu_ifu_ttype_tid_w2[1:0],
i4_3_immu_miss,
i4_3_dmmu_miss,
`TOP_DESIGN.sparc3.tlu.tcl.trap_tid_g[1:0],
i4_3_fprs_set_w[3:0],
i4_3_new_fprs_w[1:0],
`TOP_DESIGN.sparc3.lsu.qctl2.cpx_st_ack_tid0,
`TOP_DESIGN.sparc3.lsu.qctl2.cpx_st_ack_tid1,
`TOP_DESIGN.sparc3.lsu.qctl2.cpx_st_ack_tid2,
`TOP_DESIGN.sparc3.lsu.qctl2.cpx_st_ack_tid3,
i4_3_cpx_tid[1:0],
i4_3_ic_inv_vld_s,
i4_3_ic_inv_addr_s[5:0],
i4_3_ic_inv_word1_s,
i4_3_ic_inv_word0_s,
i4_3_ic_inv_way1_s[1:0],
i4_3_ic_inv_way0_s[1:0],
`TOP_DESIGN.sparc3.lsu.qctl2.cpx_ifill_type,
`TOP_DESIGN.sparc3.lsu.qctl2.cpx_ld_type,
`TOP_DESIGN.sparc3.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc3.lsu.qctl2.cpx_strm_st_ack_type,
i4_3_st_wr_dcache_w,
i4_3_dcache_fill_addr_w[9:0],
i4_3_dva_svld_w,
i4_3_dva_snp_addr_w[4:0],
i4_3_dva_snp_set_vld_w[3:0],
i4_3_dva_snp_wy3_w[1:0],
i4_3_dva_snp_wy2_w[1:0],
i4_3_dva_snp_wy1_w[1:0],
i4_3_dva_snp_wy0_w[1:0]};
assign i4_3_rdy =
(i4_3_itlb_repl_vld |
i4_3_dtlb_repl_vld |
i4_3_fprs_set_w[0] |
i4_3_fprs_set_w[1] |
i4_3_fprs_set_w[2] |
i4_3_fprs_set_w[3] |
i4_3_tick_match[0] |
i4_3_tick_match[1] |
i4_3_tick_match[2] |
i4_3_tick_match[3] |
i4_3_stick_match[0] |
i4_3_stick_match[1] |
i4_3_stick_match[2] |
i4_3_stick_match[3] |
i4_3_hstick_match[0] |
i4_3_hstick_match[1] |
i4_3_hstick_match[2] |
i4_3_hstick_match[3] |
i4_3_ld_int[0] |
i4_3_ld_int[1] |
i4_3_ld_int[2] |
i4_3_ld_int[3] |
`TOP_DESIGN.sparc3.spu_ifu_ttype_vld_w2 |
i4_3_spu_illgl_va |
i4_3_spu_trap_ack_w |
i4_3_immu_miss | i4_3_dmmu_miss |
i4_3_rstint_vld_w | i4_3_hwint_vld_w |
i4_3_sftint_vld_w | i4_3_hint_w |
`TOP_DESIGN.sparc3.lsu.qctl2.cpx_ifill_type |
`TOP_DESIGN.sparc3.lsu.qctl2.cpx_ld_type |
`TOP_DESIGN.sparc3.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc3.lsu.qctl2.cpx_strm_st_ack_type |
i4_3_ic_inv_vld_s |
i4_3_st_wr_dcache_w |
i4_3_fill_dcache_w |
i4_3_dva_svld_w);
`endif // ifdef RTL_SPARC3
`ifdef RTL_SPARC4
assign i4_4_data =
{1'b0,
1'b0,
1'b0,
`TOP_DESIGN.sparc4.spu_lsu_ldxa_tid_w2[1:0],
`TOP_DESIGN.sparc4.tlu.tcl.sftintctr[1:0],
i4_4_tlb_repl_idx[5:0],
`TOP_DESIGN.sparc4.tlu.mmu_ctl.tlb_access_tid_g[1:0],
i4_4_itlb_repl_vld,
i4_4_dtlb_repl_vld,
i4_4_spu_illgl_va,
i4_4_ld_int[3:0],
i4_4_hstick_match[3:0],
i4_4_stick_match[3:0],
i4_4_tick_match[3:0],
i4_4_hint_vld_w,
i4_4_sftint_vld_w,
i4_4_hwint_vld_w,
i4_4_rstint_vld_w,
i4_4_int_thr_w[3:0],
i4_4_spu_trap_ack_w,
i4_4_fill_dcache_w,
`TOP_DESIGN.sparc4.spu_ifu_ttype_vld_w2,
`TOP_DESIGN.sparc4.spu_ifu_ttype_w2,
`TOP_DESIGN.sparc4.spu_ifu_ttype_tid_w2[1:0],
i4_4_immu_miss,
i4_4_dmmu_miss,
`TOP_DESIGN.sparc4.tlu.tcl.trap_tid_g[1:0],
i4_4_fprs_set_w[3:0],
i4_4_new_fprs_w[1:0],
`TOP_DESIGN.sparc4.lsu.qctl2.cpx_st_ack_tid0,
`TOP_DESIGN.sparc4.lsu.qctl2.cpx_st_ack_tid1,
`TOP_DESIGN.sparc4.lsu.qctl2.cpx_st_ack_tid2,
`TOP_DESIGN.sparc4.lsu.qctl2.cpx_st_ack_tid3,
i4_4_cpx_tid[1:0],
i4_4_ic_inv_vld_s,
i4_4_ic_inv_addr_s[5:0],
i4_4_ic_inv_word1_s,
i4_4_ic_inv_word0_s,
i4_4_ic_inv_way1_s[1:0],
i4_4_ic_inv_way0_s[1:0],
`TOP_DESIGN.sparc4.lsu.qctl2.cpx_ifill_type,
`TOP_DESIGN.sparc4.lsu.qctl2.cpx_ld_type,
`TOP_DESIGN.sparc4.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc4.lsu.qctl2.cpx_strm_st_ack_type,
i4_4_st_wr_dcache_w,
i4_4_dcache_fill_addr_w[9:0],
i4_4_dva_svld_w,
i4_4_dva_snp_addr_w[4:0],
i4_4_dva_snp_set_vld_w[3:0],
i4_4_dva_snp_wy3_w[1:0],
i4_4_dva_snp_wy2_w[1:0],
i4_4_dva_snp_wy1_w[1:0],
i4_4_dva_snp_wy0_w[1:0]};
assign i4_4_rdy =
(i4_4_itlb_repl_vld |
i4_4_dtlb_repl_vld |
i4_4_fprs_set_w[0] |
i4_4_fprs_set_w[1] |
i4_4_fprs_set_w[2] |
i4_4_fprs_set_w[3] |
i4_4_tick_match[0] |
i4_4_tick_match[1] |
i4_4_tick_match[2] |
i4_4_tick_match[3] |
i4_4_stick_match[0] |
i4_4_stick_match[1] |
i4_4_stick_match[2] |
i4_4_stick_match[3] |
i4_4_hstick_match[0] |
i4_4_hstick_match[1] |
i4_4_hstick_match[2] |
i4_4_hstick_match[3] |
i4_4_ld_int[0] |
i4_4_ld_int[1] |
i4_4_ld_int[2] |
i4_4_ld_int[3] |
`TOP_DESIGN.sparc4.spu_ifu_ttype_vld_w2 |
i4_4_spu_illgl_va |
i4_4_spu_trap_ack_w |
i4_4_immu_miss | i4_4_dmmu_miss |
i4_4_rstint_vld_w | i4_4_hwint_vld_w |
i4_4_sftint_vld_w | i4_4_hint_w |
`TOP_DESIGN.sparc4.lsu.qctl2.cpx_ifill_type |
`TOP_DESIGN.sparc4.lsu.qctl2.cpx_ld_type |
`TOP_DESIGN.sparc4.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc4.lsu.qctl2.cpx_strm_st_ack_type |
i4_4_ic_inv_vld_s |
i4_4_st_wr_dcache_w |
i4_4_fill_dcache_w |
i4_4_dva_svld_w);
`endif // ifdef RTL_SPARC4
`ifdef RTL_SPARC5
assign i4_5_data =
{1'b0,
1'b0,
1'b0,
`TOP_DESIGN.sparc5.spu_lsu_ldxa_tid_w2[1:0],
`TOP_DESIGN.sparc5.tlu.tcl.sftintctr[1:0],
i4_5_tlb_repl_idx[5:0],
`TOP_DESIGN.sparc5.tlu.mmu_ctl.tlb_access_tid_g[1:0],
i4_5_itlb_repl_vld,
i4_5_dtlb_repl_vld,
i4_5_spu_illgl_va,
i4_5_ld_int[3:0],
i4_5_hstick_match[3:0],
i4_5_stick_match[3:0],
i4_5_tick_match[3:0],
i4_5_hint_vld_w,
i4_5_sftint_vld_w,
i4_5_hwint_vld_w,
i4_5_rstint_vld_w,
i4_5_int_thr_w[3:0],
i4_5_spu_trap_ack_w,
i4_5_fill_dcache_w,
`TOP_DESIGN.sparc5.spu_ifu_ttype_vld_w2,
`TOP_DESIGN.sparc5.spu_ifu_ttype_w2,
`TOP_DESIGN.sparc5.spu_ifu_ttype_tid_w2[1:0],
i4_5_immu_miss,
i4_5_dmmu_miss,
`TOP_DESIGN.sparc5.tlu.tcl.trap_tid_g[1:0],
i4_5_fprs_set_w[3:0],
i4_5_new_fprs_w[1:0],
`TOP_DESIGN.sparc5.lsu.qctl2.cpx_st_ack_tid0,
`TOP_DESIGN.sparc5.lsu.qctl2.cpx_st_ack_tid1,
`TOP_DESIGN.sparc5.lsu.qctl2.cpx_st_ack_tid2,
`TOP_DESIGN.sparc5.lsu.qctl2.cpx_st_ack_tid3,
i4_5_cpx_tid[1:0],
i4_5_ic_inv_vld_s,
i4_5_ic_inv_addr_s[5:0],
i4_5_ic_inv_word1_s,
i4_5_ic_inv_word0_s,
i4_5_ic_inv_way1_s[1:0],
i4_5_ic_inv_way0_s[1:0],
`TOP_DESIGN.sparc5.lsu.qctl2.cpx_ifill_type,
`TOP_DESIGN.sparc5.lsu.qctl2.cpx_ld_type,
`TOP_DESIGN.sparc5.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc5.lsu.qctl2.cpx_strm_st_ack_type,
i4_5_st_wr_dcache_w,
i4_5_dcache_fill_addr_w[9:0],
i4_5_dva_svld_w,
i4_5_dva_snp_addr_w[4:0],
i4_5_dva_snp_set_vld_w[3:0],
i4_5_dva_snp_wy3_w[1:0],
i4_5_dva_snp_wy2_w[1:0],
i4_5_dva_snp_wy1_w[1:0],
i4_5_dva_snp_wy0_w[1:0]};
assign i4_5_rdy =
(i4_5_itlb_repl_vld |
i4_5_dtlb_repl_vld |
i4_5_fprs_set_w[0] |
i4_5_fprs_set_w[1] |
i4_5_fprs_set_w[2] |
i4_5_fprs_set_w[3] |
i4_5_tick_match[0] |
i4_5_tick_match[1] |
i4_5_tick_match[2] |
i4_5_tick_match[3] |
i4_5_stick_match[0] |
i4_5_stick_match[1] |
i4_5_stick_match[2] |
i4_5_stick_match[3] |
i4_5_hstick_match[0] |
i4_5_hstick_match[1] |
i4_5_hstick_match[2] |
i4_5_hstick_match[3] |
i4_5_ld_int[0] |
i4_5_ld_int[1] |
i4_5_ld_int[2] |
i4_5_ld_int[3] |
`TOP_DESIGN.sparc5.spu_ifu_ttype_vld_w2 |
i4_5_spu_illgl_va |
i4_5_spu_trap_ack_w |
i4_5_immu_miss | i4_5_dmmu_miss |
i4_5_rstint_vld_w | i4_5_hwint_vld_w |
i4_5_sftint_vld_w | i4_5_hint_w |
`TOP_DESIGN.sparc5.lsu.qctl2.cpx_ifill_type |
`TOP_DESIGN.sparc5.lsu.qctl2.cpx_ld_type |
`TOP_DESIGN.sparc5.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc5.lsu.qctl2.cpx_strm_st_ack_type |
i4_5_ic_inv_vld_s |
i4_5_st_wr_dcache_w |
i4_5_fill_dcache_w |
i4_5_dva_svld_w);
`endif // ifdef RTL_SPARC5
`ifdef RTL_SPARC6
assign i4_6_data =
{1'b0,
1'b0,
1'b0,
`TOP_DESIGN.sparc6.spu_lsu_ldxa_tid_w2[1:0],
`TOP_DESIGN.sparc6.tlu.tcl.sftintctr[1:0],
i4_6_tlb_repl_idx[5:0],
`TOP_DESIGN.sparc6.tlu.mmu_ctl.tlb_access_tid_g[1:0],
i4_6_itlb_repl_vld,
i4_6_dtlb_repl_vld,
i4_6_spu_illgl_va,
i4_6_ld_int[3:0],
i4_6_hstick_match[3:0],
i4_6_stick_match[3:0],
i4_6_tick_match[3:0],
i4_6_hint_vld_w,
i4_6_sftint_vld_w,
i4_6_hwint_vld_w,
i4_6_rstint_vld_w,
i4_6_int_thr_w[3:0],
i4_6_spu_trap_ack_w,
i4_6_fill_dcache_w,
`TOP_DESIGN.sparc6.spu_ifu_ttype_vld_w2,
`TOP_DESIGN.sparc6.spu_ifu_ttype_w2,
`TOP_DESIGN.sparc6.spu_ifu_ttype_tid_w2[1:0],
i4_6_immu_miss,
i4_6_dmmu_miss,
`TOP_DESIGN.sparc6.tlu.tcl.trap_tid_g[1:0],
i4_6_fprs_set_w[3:0],
i4_6_new_fprs_w[1:0],
`TOP_DESIGN.sparc6.lsu.qctl2.cpx_st_ack_tid0,
`TOP_DESIGN.sparc6.lsu.qctl2.cpx_st_ack_tid1,
`TOP_DESIGN.sparc6.lsu.qctl2.cpx_st_ack_tid2,
`TOP_DESIGN.sparc6.lsu.qctl2.cpx_st_ack_tid3,
i4_6_cpx_tid[1:0],
i4_6_ic_inv_vld_s,
i4_6_ic_inv_addr_s[5:0],
i4_6_ic_inv_word1_s,
i4_6_ic_inv_word0_s,
i4_6_ic_inv_way1_s[1:0],
i4_6_ic_inv_way0_s[1:0],
`TOP_DESIGN.sparc6.lsu.qctl2.cpx_ifill_type,
`TOP_DESIGN.sparc6.lsu.qctl2.cpx_ld_type,
`TOP_DESIGN.sparc6.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc6.lsu.qctl2.cpx_strm_st_ack_type,
i4_6_st_wr_dcache_w,
i4_6_dcache_fill_addr_w[9:0],
i4_6_dva_svld_w,
i4_6_dva_snp_addr_w[4:0],
i4_6_dva_snp_set_vld_w[3:0],
i4_6_dva_snp_wy3_w[1:0],
i4_6_dva_snp_wy2_w[1:0],
i4_6_dva_snp_wy1_w[1:0],
i4_6_dva_snp_wy0_w[1:0]};
assign i4_6_rdy =
(i4_6_itlb_repl_vld |
i4_6_dtlb_repl_vld |
i4_6_fprs_set_w[0] |
i4_6_fprs_set_w[1] |
i4_6_fprs_set_w[2] |
i4_6_fprs_set_w[3] |
i4_6_tick_match[0] |
i4_6_tick_match[1] |
i4_6_tick_match[2] |
i4_6_tick_match[3] |
i4_6_stick_match[0] |
i4_6_stick_match[1] |
i4_6_stick_match[2] |
i4_6_stick_match[3] |
i4_6_hstick_match[0] |
i4_6_hstick_match[1] |
i4_6_hstick_match[2] |
i4_6_hstick_match[3] |
i4_6_ld_int[0] |
i4_6_ld_int[1] |
i4_6_ld_int[2] |
i4_6_ld_int[3] |
`TOP_DESIGN.sparc6.spu_ifu_ttype_vld_w2 |
i4_6_spu_illgl_va |
i4_6_spu_trap_ack_w |
i4_6_immu_miss | i4_6_dmmu_miss |
i4_6_rstint_vld_w | i4_6_hwint_vld_w |
i4_6_sftint_vld_w | i4_6_hint_w |
`TOP_DESIGN.sparc6.lsu.qctl2.cpx_ifill_type |
`TOP_DESIGN.sparc6.lsu.qctl2.cpx_ld_type |
`TOP_DESIGN.sparc6.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc6.lsu.qctl2.cpx_strm_st_ack_type |
i4_6_ic_inv_vld_s |
i4_6_st_wr_dcache_w |
i4_6_fill_dcache_w |
i4_6_dva_svld_w);
`endif // ifdef RTL_SPARC6
`ifdef RTL_SPARC7
assign i4_7_data =
{1'b0,
1'b0,
1'b0,
`TOP_DESIGN.sparc7.spu_lsu_ldxa_tid_w2[1:0],
`TOP_DESIGN.sparc7.tlu.tcl.sftintctr[1:0],
i4_7_tlb_repl_idx[5:0],
`TOP_DESIGN.sparc7.tlu.mmu_ctl.tlb_access_tid_g[1:0],
i4_7_itlb_repl_vld,
i4_7_dtlb_repl_vld,
i4_7_spu_illgl_va,
i4_7_ld_int[3:0],
i4_7_hstick_match[3:0],
i4_7_stick_match[3:0],
i4_7_tick_match[3:0],
i4_7_hint_vld_w,
i4_7_sftint_vld_w,
i4_7_hwint_vld_w,
i4_7_rstint_vld_w,
i4_7_int_thr_w[3:0],
i4_7_spu_trap_ack_w,
i4_7_fill_dcache_w,
`TOP_DESIGN.sparc7.spu_ifu_ttype_vld_w2,
`TOP_DESIGN.sparc7.spu_ifu_ttype_w2,
`TOP_DESIGN.sparc7.spu_ifu_ttype_tid_w2[1:0],
i4_7_immu_miss,
i4_7_dmmu_miss,
`TOP_DESIGN.sparc7.tlu.tcl.trap_tid_g[1:0],
i4_7_fprs_set_w[3:0],
i4_7_new_fprs_w[1:0],
`TOP_DESIGN.sparc7.lsu.qctl2.cpx_st_ack_tid0,
`TOP_DESIGN.sparc7.lsu.qctl2.cpx_st_ack_tid1,
`TOP_DESIGN.sparc7.lsu.qctl2.cpx_st_ack_tid2,
`TOP_DESIGN.sparc7.lsu.qctl2.cpx_st_ack_tid3,
i4_7_cpx_tid[1:0],
i4_7_ic_inv_vld_s,
i4_7_ic_inv_addr_s[5:0],
i4_7_ic_inv_word1_s,
i4_7_ic_inv_word0_s,
i4_7_ic_inv_way1_s[1:0],
i4_7_ic_inv_way0_s[1:0],
`TOP_DESIGN.sparc7.lsu.qctl2.cpx_ifill_type,
`TOP_DESIGN.sparc7.lsu.qctl2.cpx_ld_type,
`TOP_DESIGN.sparc7.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc7.lsu.qctl2.cpx_strm_st_ack_type,
i4_7_st_wr_dcache_w,
i4_7_dcache_fill_addr_w[9:0],
i4_7_dva_svld_w,
i4_7_dva_snp_addr_w[4:0],
i4_7_dva_snp_set_vld_w[3:0],
i4_7_dva_snp_wy3_w[1:0],
i4_7_dva_snp_wy2_w[1:0],
i4_7_dva_snp_wy1_w[1:0],
i4_7_dva_snp_wy0_w[1:0]};
assign i4_7_rdy =
(i4_7_itlb_repl_vld |
i4_7_dtlb_repl_vld |
i4_7_fprs_set_w[0] |
i4_7_fprs_set_w[1] |
i4_7_fprs_set_w[2] |
i4_7_fprs_set_w[3] |
i4_7_tick_match[0] |
i4_7_tick_match[1] |
i4_7_tick_match[2] |
i4_7_tick_match[3] |
i4_7_stick_match[0] |
i4_7_stick_match[1] |
i4_7_stick_match[2] |
i4_7_stick_match[3] |
i4_7_hstick_match[0] |
i4_7_hstick_match[1] |
i4_7_hstick_match[2] |
i4_7_hstick_match[3] |
i4_7_ld_int[0] |
i4_7_ld_int[1] |
i4_7_ld_int[2] |
i4_7_ld_int[3] |
`TOP_DESIGN.sparc7.spu_ifu_ttype_vld_w2 |
i4_7_spu_illgl_va |
i4_7_spu_trap_ack_w |
i4_7_immu_miss | i4_7_dmmu_miss |
i4_7_rstint_vld_w | i4_7_hwint_vld_w |
i4_7_sftint_vld_w | i4_7_hint_w |
`TOP_DESIGN.sparc7.lsu.qctl2.cpx_ifill_type |
`TOP_DESIGN.sparc7.lsu.qctl2.cpx_ld_type |
`TOP_DESIGN.sparc7.lsu.qctl2.cpx_st_ack_type |
`TOP_DESIGN.sparc7.lsu.qctl2.cpx_strm_st_ack_type |
i4_7_ic_inv_vld_s |
i4_7_st_wr_dcache_w |
i4_7_fill_dcache_w |
i4_7_dva_svld_w);
`endif // ifdef RTL_SPARC7
`endif // ifdef SAS_DISABLE
`ifdef ENV_SPARC1
assign i4_1_data = 'h0;
assign i4_1_rdy = 'h0;
`endif // !ifdef RTL_SPARC1
`ifdef ENV_SPARC2
assign i4_2_data = 'h0;
assign i4_2_rdy = 'h0;
`endif // !ifdef RTL_SPARC2
`ifdef ENV_SPARC3
assign i4_3_data = 'h0;
assign i4_3_rdy = 'h0;
`endif // !ifdef RTL_SPARC3
`ifdef ENV_SPARC4
assign i4_4_data = 'h0;
assign i4_4_rdy = 'h0;
`endif // !ifdef RTL_SPARC4
`ifdef ENV_SPARC5
assign i4_5_data = 'h0;
assign i4_5_rdy = 'h0;
`endif // !ifdef RTL_SPARC5
`ifdef ENV_SPARC6
assign i4_6_data = 'h0;
assign i4_6_rdy = 'h0;
`endif // !ifdef RTL_SPARC6
`ifdef ENV_SPARC7
assign i4_7_data = 'h0;
assign i4_7_rdy = 'h0;
`endif // !ifdef RTL_SPARC7
`ifdef SAS_DISABLE
`else
`ifdef RTL_SPARC0
assign i5_0_data =
{1'b0,
1'b0,
`TOP_DESIGN.sparc0.ifu.fcl.fcl_ifq_icmiss_s1,
`TOP_DESIGN.sparc0.ifu.fcl.fcl_ifq_thr_s1[1:0],
`TOP_DESIGN.sparc0.ifu.ifqdp.imiss_paddr_s};
assign i5_0_rdy =
((`TOP_DESIGN.sparc0.ifu.fcl.rdreq_s1 &
`TOP_DESIGN.sparc0.ifu.fcl.inst_vld_s1 &
~`TOP_DESIGN.sparc0.ifu.fcl.tlbmiss_s1_crit)|
`TOP_DESIGN.sparc0.ifu.fcl.fcl_ifq_icmiss_s1);
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC1
assign i5_1_data =
{1'b0,
1'b0,
`TOP_DESIGN.sparc1.ifu.fcl.fcl_ifq_icmiss_s1,
`TOP_DESIGN.sparc1.ifu.fcl.fcl_ifq_thr_s1[1:0],
`TOP_DESIGN.sparc1.ifu.ifqdp.imiss_paddr_s};
assign i5_1_rdy =
((`TOP_DESIGN.sparc1.ifu.fcl.rdreq_s1 &
`TOP_DESIGN.sparc1.ifu.fcl.inst_vld_s1 &
~`TOP_DESIGN.sparc1.ifu.fcl.tlbmiss_s1_crit)|
`TOP_DESIGN.sparc1.ifu.fcl.fcl_ifq_icmiss_s1);
`endif // ifdef RTL_SPARC1
`ifdef RTL_SPARC2
assign i5_2_data =
{1'b0,
1'b0,
`TOP_DESIGN.sparc2.ifu.fcl.fcl_ifq_icmiss_s1,
`TOP_DESIGN.sparc2.ifu.fcl.fcl_ifq_thr_s1[1:0],
`TOP_DESIGN.sparc2.ifu.ifqdp.imiss_paddr_s};
assign i5_2_rdy =
((`TOP_DESIGN.sparc2.ifu.fcl.rdreq_s1 &
`TOP_DESIGN.sparc2.ifu.fcl.inst_vld_s1 &
~`TOP_DESIGN.sparc2.ifu.fcl.tlbmiss_s1_crit)|
`TOP_DESIGN.sparc2.ifu.fcl.fcl_ifq_icmiss_s1);
`endif // ifdef RTL_SPARC2
`ifdef RTL_SPARC3
assign i5_3_data =
{1'b0,
1'b0,
`TOP_DESIGN.sparc3.ifu.fcl.fcl_ifq_icmiss_s1,
`TOP_DESIGN.sparc3.ifu.fcl.fcl_ifq_thr_s1[1:0],
`TOP_DESIGN.sparc3.ifu.ifqdp.imiss_paddr_s};
assign i5_3_rdy =
((`TOP_DESIGN.sparc3.ifu.fcl.rdreq_s1 &
`TOP_DESIGN.sparc3.ifu.fcl.inst_vld_s1 &
~`TOP_DESIGN.sparc3.ifu.fcl.tlbmiss_s1_crit)|
`TOP_DESIGN.sparc3.ifu.fcl.fcl_ifq_icmiss_s1);
`endif // ifdef RTL_SPARC3
`ifdef RTL_SPARC4
assign i5_4_data =
{1'b0,
1'b0,
`TOP_DESIGN.sparc4.ifu.fcl.fcl_ifq_icmiss_s1,
`TOP_DESIGN.sparc4.ifu.fcl.fcl_ifq_thr_s1[1:0],
`TOP_DESIGN.sparc4.ifu.ifqdp.imiss_paddr_s};
assign i5_4_rdy =
((`TOP_DESIGN.sparc4.ifu.fcl.rdreq_s1 &
`TOP_DESIGN.sparc4.ifu.fcl.inst_vld_s1 &
~`TOP_DESIGN.sparc4.ifu.fcl.tlbmiss_s1_crit)|
`TOP_DESIGN.sparc4.ifu.fcl.fcl_ifq_icmiss_s1);
`endif // ifdef RTL_SPARC4
`ifdef RTL_SPARC5
assign i5_5_data =
{1'b0,
1'b0,
`TOP_DESIGN.sparc5.ifu.fcl.fcl_ifq_icmiss_s1,
`TOP_DESIGN.sparc5.ifu.fcl.fcl_ifq_thr_s1[1:0],
`TOP_DESIGN.sparc5.ifu.ifqdp.imiss_paddr_s};
assign i5_5_rdy =
((`TOP_DESIGN.sparc5.ifu.fcl.rdreq_s1 &
`TOP_DESIGN.sparc5.ifu.fcl.inst_vld_s1 &
~`TOP_DESIGN.sparc5.ifu.fcl.tlbmiss_s1_crit)|
`TOP_DESIGN.sparc5.ifu.fcl.fcl_ifq_icmiss_s1);
`endif // ifdef RTL_SPARC5
`ifdef RTL_SPARC6
assign i5_6_data =
{1'b0,
1'b0,
`TOP_DESIGN.sparc6.ifu.fcl.fcl_ifq_icmiss_s1,
`TOP_DESIGN.sparc6.ifu.fcl.fcl_ifq_thr_s1[1:0],
`TOP_DESIGN.sparc6.ifu.ifqdp.imiss_paddr_s};
assign i5_6_rdy =
((`TOP_DESIGN.sparc6.ifu.fcl.rdreq_s1 &
`TOP_DESIGN.sparc6.ifu.fcl.inst_vld_s1 &
~`TOP_DESIGN.sparc6.ifu.fcl.tlbmiss_s1_crit)|
`TOP_DESIGN.sparc6.ifu.fcl.fcl_ifq_icmiss_s1);
`endif // ifdef RTL_SPARC6
`ifdef RTL_SPARC7
assign i5_7_data =
{1'b0,
1'b0,
`TOP_DESIGN.sparc7.ifu.fcl.fcl_ifq_icmiss_s1,
`TOP_DESIGN.sparc7.ifu.fcl.fcl_ifq_thr_s1[1:0],
`TOP_DESIGN.sparc7.ifu.ifqdp.imiss_paddr_s};
assign i5_7_rdy =
((`TOP_DESIGN.sparc7.ifu.fcl.rdreq_s1 &
`TOP_DESIGN.sparc7.ifu.fcl.inst_vld_s1 &
~`TOP_DESIGN.sparc7.ifu.fcl.tlbmiss_s1_crit)|
`TOP_DESIGN.sparc7.ifu.fcl.fcl_ifq_icmiss_s1);
`endif // ifdef RTL_SPARC7
`endif // ifdef SAS_DISABLE
`ifdef ENV_SPARC1
assign i5_1_data = 'h0;
assign i5_1_rdy = 'h0;
`endif // !ifdef RTL_SPARC1
`ifdef ENV_SPARC2
assign i5_2_data = 'h0;
assign i5_2_rdy = 'h0;
`endif // !ifdef RTL_SPARC2
`ifdef ENV_SPARC3
assign i5_3_data = 'h0;
assign i5_3_rdy = 'h0;
`endif // !ifdef RTL_SPARC3
`ifdef ENV_SPARC4
assign i5_4_data = 'h0;
assign i5_4_rdy = 'h0;
`endif // !ifdef RTL_SPARC4
`ifdef ENV_SPARC5
assign i5_5_data = 'h0;
assign i5_5_rdy = 'h0;
`endif // !ifdef RTL_SPARC5
`ifdef ENV_SPARC6
assign i5_6_data = 'h0;
assign i5_6_rdy = 'h0;
`endif // !ifdef RTL_SPARC6
`ifdef ENV_SPARC7
assign i5_7_data = 'h0;
assign i5_7_rdy = 'h0;
`endif // !ifdef RTL_SPARC7
//send memory model data
wire [`INTF0_WIDTH+2:0] local_i0_0_data = {3'b000,i0_0_data};
wire local_i0_0_vld = i0_0_rdy;
wire [`INTF0_WIDTH+2:0] local_i0_1_data = {3'b001,i0_1_data};
wire local_i0_1_vld = i0_1_rdy;
wire [`INTF0_WIDTH+2:0] local_i0_2_data = {3'b010,i0_2_data};
wire local_i0_2_vld = i0_2_rdy;
wire [`INTF0_WIDTH+2:0] local_i0_3_data = {3'b011,i0_3_data};
wire local_i0_3_vld = i0_3_rdy;
wire [`INTF0_WIDTH+2:0] local_i0_4_data = {3'b100,i0_4_data};
wire local_i0_4_vld = i0_4_rdy;
wire [`INTF0_WIDTH+2:0] local_i0_5_data = {3'b101,i0_5_data};
wire local_i0_5_vld = i0_5_rdy;
wire [`INTF0_WIDTH+2:0] local_i0_6_data = {3'b110,i0_6_data};
wire local_i0_6_vld = i0_6_rdy;
wire [`INTF0_WIDTH+2:0] local_i0_7_data = {3'b111,i0_7_data};
wire local_i0_7_vld = i0_7_rdy;
wire [`INTF1_WIDTH-1:0] local_i1_0_data = i1_0_data;
wire local_i1_0_vld = i1_0_rdy;
wire [`INTF1_WIDTH-1:0] local_i1_1_data = i1_1_data;
wire local_i1_1_vld = i1_1_rdy;
wire [`INTF1_WIDTH-1:0] local_i1_2_data = i1_2_data;
wire local_i1_2_vld = i1_2_rdy;
wire [`INTF1_WIDTH-1:0] local_i1_3_data = i1_3_data;
wire local_i1_3_vld = i1_3_rdy;
wire [`INTF2_WIDTH-1:0] local_i2_0_data = i2_0_data;
wire local_i2_0_vld = i2_0_rdy;
wire [`INTF2_WIDTH-1:0] local_i2_1_data = i2_1_data;
wire local_i2_1_vld = i2_1_rdy;
wire [`INTF2_WIDTH-1:0] local_i2_2_data = i2_2_data;
wire local_i2_2_vld = i2_2_rdy;
wire [`INTF2_WIDTH-1:0] local_i2_3_data = i2_3_data;
wire local_i2_3_vld = i2_3_rdy;
wire [`INTF3_WIDTH+2:0] local_i3_0_data = {3'b000,i3_0_data};
wire local_i3_0_vld = i3_0_rdy;
wire [`INTF3_WIDTH+2:0] local_i3_1_data = {3'b001,i3_1_data};
wire local_i3_1_vld = i3_1_rdy;
wire [`INTF3_WIDTH+2:0] local_i3_2_data = {3'b010,i3_2_data};
wire local_i3_2_vld = i3_2_rdy;
wire [`INTF3_WIDTH+2:0] local_i3_3_data = {3'b011,i3_3_data};
wire local_i3_3_vld = i3_3_rdy;
wire [`INTF3_WIDTH+2:0] local_i3_4_data = {3'b100,i3_4_data};
wire local_i3_4_vld = i3_4_rdy;
wire [`INTF3_WIDTH+2:0] local_i3_5_data = {3'b101,i3_5_data};
wire local_i3_5_vld = i3_5_rdy;
wire [`INTF3_WIDTH+2:0] local_i3_6_data = {3'b110,i3_6_data};
wire local_i3_6_vld = i3_6_rdy;
wire [`INTF3_WIDTH+2:0] local_i3_7_data = {3'b111,i3_7_data};
wire local_i3_7_vld = i3_7_rdy;
wire [`INTF4_WIDTH+2:0] local_i4_0_data = {3'b000,i4_0_data};
wire local_i4_0_vld = i4_0_rdy;
wire [`INTF4_WIDTH+2:0] local_i4_1_data = {3'b001,i4_1_data};
wire local_i4_1_vld = i4_1_rdy;
wire [`INTF4_WIDTH+2:0] local_i4_2_data = {3'b010,i4_2_data};
wire local_i4_2_vld = i4_2_rdy;
wire [`INTF4_WIDTH+2:0] local_i4_3_data = {3'b011,i4_3_data};
wire local_i4_3_vld = i4_3_rdy;
wire [`INTF4_WIDTH+2:0] local_i4_4_data = {3'b100,i4_4_data};
wire local_i4_4_vld = i4_4_rdy;
wire [`INTF4_WIDTH+2:0] local_i4_5_data = {3'b101,i4_5_data};
wire local_i4_5_vld = i4_5_rdy;
wire [`INTF4_WIDTH+2:0] local_i4_6_data = {3'b110,i4_6_data};
wire local_i4_6_vld = i4_6_rdy;
wire [`INTF4_WIDTH+2:0] local_i4_7_data = {3'b111,i4_7_data};
wire local_i4_7_vld = i4_7_rdy;
wire [`INTF5_WIDTH+2:0] local_i5_0_data = {3'b000,i5_0_data};
wire local_i5_0_vld = i5_0_rdy;
wire [`INTF5_WIDTH+2:0] local_i5_1_data = {3'b001,i5_1_data};
wire local_i5_1_vld = i5_1_rdy;
wire [`INTF5_WIDTH+2:0] local_i5_2_data = {3'b010,i5_2_data};
wire local_i5_2_vld = i5_2_rdy;
wire [`INTF5_WIDTH+2:0] local_i5_3_data = {3'b011,i5_3_data};
wire local_i5_3_vld = i5_3_rdy;
wire [`INTF5_WIDTH+2:0] local_i5_4_data = {3'b100,i5_4_data};
wire local_i5_4_vld = i5_4_rdy;
wire [`INTF5_WIDTH+2:0] local_i5_5_data = {3'b101,i5_5_data};
wire local_i5_5_vld = i5_5_rdy;
wire [`INTF5_WIDTH+2:0] local_i5_6_data = {3'b110,i5_6_data};
wire local_i5_6_vld = i5_6_rdy;
wire [`INTF5_WIDTH+2:0] local_i5_7_data = {3'b111,i5_7_data};
wire local_i5_7_vld = i5_7_rdy;
//count rtl cycles
integer counter, match_count;
reg match;
initial begin
counter = 0;
match = 1;
match_count = 0;
end
`ifdef SAS_DISABLE
`else
`ifdef RTL_SPARC0
always @(posedge clk)begin//clean up buffer
if(rst_l)begin
if(`PC_CMP.active_thread[31:0] && (`PC_CMP.good[31:0] == `PC_CMP.active_thread[31:0]))match_count = match_count + 1;
if(match_count == `CLEAN_CYCLE)match = 0;
end
else begin
counter = 0;
match = 1;
match_count = 0;
end
end
//`ifdef RTL_SPARC0
task send_model;
begin
if(match || counter)//send data to simics
if(local_i0_0_vld || local_i0_1_vld || local_i0_2_vld || local_i0_3_vld ||
local_i0_4_vld || local_i0_5_vld || local_i0_6_vld || local_i0_7_vld ||
local_i1_0_vld || local_i1_1_vld || local_i1_2_vld || local_i1_3_vld ||
local_i2_0_vld || local_i2_1_vld || local_i2_2_vld || local_i2_3_vld ||
local_i3_0_vld || local_i3_1_vld || local_i3_2_vld || local_i3_3_vld ||
local_i3_4_vld || local_i3_5_vld || local_i3_6_vld || local_i3_7_vld ||
local_i4_0_vld || local_i4_1_vld || local_i4_2_vld || local_i4_3_vld ||
local_i4_4_vld || local_i4_5_vld || local_i4_6_vld || local_i4_7_vld ||
local_i5_0_vld || local_i5_1_vld || local_i5_2_vld || local_i5_3_vld ||
local_i5_4_vld || local_i5_5_vld || local_i5_6_vld || local_i5_7_vld
)
//attention total number of bits should be 32 times.
begin
if(counter)`SAS_SEND(`PLI_RTL_CYCLE, 0, 0, 0, counter, 0);
`SAS_SEND(`PLI_RTL_DATA, 0, 0, 0, 0, {
local_i0_0_data, local_i0_0_vld,
local_i0_1_data, local_i0_1_vld,
local_i0_2_data, local_i0_2_vld,
local_i0_3_data, local_i0_3_vld,
local_i0_4_data, local_i0_4_vld,
local_i0_5_data, local_i0_5_vld,
local_i0_6_data, local_i0_6_vld,
local_i0_7_data, local_i0_7_vld,
local_i1_0_data, local_i1_0_vld,
local_i1_1_data, local_i1_1_vld,
local_i1_2_data, local_i1_2_vld,
local_i1_3_data, local_i1_3_vld,
local_i2_0_data, local_i2_0_vld,
local_i2_1_data, local_i2_1_vld,
local_i2_2_data, local_i2_2_vld,
local_i2_3_data, local_i2_3_vld,
local_i3_0_data, local_i3_0_vld,
local_i3_1_data, local_i3_1_vld,
local_i3_2_data, local_i3_2_vld,
local_i3_3_data, local_i3_3_vld,
local_i3_4_data, local_i3_4_vld,
local_i3_5_data, local_i3_5_vld,
local_i3_6_data, local_i3_6_vld,
local_i3_7_data, local_i3_7_vld,
local_i4_0_data, local_i4_0_vld,
local_i4_1_data, local_i4_1_vld,
local_i4_2_data, local_i4_2_vld,
local_i4_3_data, local_i4_3_vld,
local_i4_4_data, local_i4_4_vld,
local_i4_5_data, local_i4_5_vld,
local_i4_6_data, local_i4_6_vld,
local_i4_7_data, local_i4_7_vld,
local_i5_0_data, local_i5_0_vld,
local_i5_1_data, local_i5_1_vld,
local_i5_2_data, local_i5_2_vld,
local_i5_3_data, local_i5_3_vld,
local_i5_4_data, local_i5_4_vld,
local_i5_5_data, local_i5_5_vld,
local_i5_6_data, local_i5_6_vld,
local_i5_7_data, local_i5_7_vld,
4'b0000//padding
});
counter = 0;
end // if (local_i0_0_vld || local_i0_1_vld || local_i0_2_vld || local_i0_3_vld ||...
else begin
if(counter == 1024)begin
`SAS_SEND(`PLI_RTL_CYCLE, 0, 0, 0, counter, 0);
counter = 0;
end
counter = counter + 1;
end // else: !if(local_i0_0_vld || local_i0_1_vld || local_i0_2_vld || local_i0_3_vld ||...
end
endtask // send_model
`endif
`endif // ifdef SAS_DISABLE
endmodule // sas_intf
|
/******************************************************************************
* File Name : counter.v
* Package Module Name : Elliptic Curve Cryptoprocessor for GF(2^233)
* Author : Chester Rebeiro
* Date of Creation : 3/Apr/2008
* Type of file : Verilog source code
* Synopsis : counts down from 233 to 0. When 0 is reached e is
* set to indicate count is done.
******************************************************************************/
`ifndef __COUNTER_V__
`define __COUNTER_V__
`define KEYSIZE 32
`define KEYMSB 31
/*---------------------------------------------------------------------------
* Module Name : counter
* Synopsis :
* The counter will start from 233 and go downto 0.
* Load counter with nrst low.
* Counter ends when e goes low for one clock cycle.
---------------------------------------------------------------------------*/
module counter (clk, nrst, e);
input wire clk; /* clock used for the counter */
input wire nrst; /* active low reset */
output wire e; /* set to 0 if count = 0 */
reg [7:0] count; /* ...and the register which actually decrements */
/* activate e when count reaches 0 */
assign e = |count;
always @(posedge clk or negedge nrst) begin
if(nrst == 1'b0)
count <= 8'd`KEYMSB;
else
count <= count - 1'b1;
end
endmodule
`endif
|
/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1ns / 1ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #
(
// depth of synchronizer
parameter N = 2
)
(
input wire clk,
input wire rst,
output wire out
);
(* srl_style = "register" *)
reg [N-1:0] sync_reg = {N{1'b1}};
assign out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst) begin
sync_reg <= {N{1'b1}};
end else begin
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:10:55 03/06/2016
// Design Name:
// Module Name: mult4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mult4(
input x0,
input x1,
input x2,
input x3,
input y0,
input y1,
input y2,
input y3,
output z0,
output z1,
output z2,
output z3,
output z4,
output z5,
output z6,
output z7
);
//productos
//wire p00; -> z0
wire p01;
wire p02;
wire p03;
wire p10;
wire p11;
wire p12;
wire p13;
wire p20;
wire p21;
wire p22;
wire p23;
wire p30;
wire p31;
wire p32;
wire p33;
//acarreos
wire c1;
wire c2;
wire c3;
wire c4;
wire c5;
wire c6;
wire c7;
wire c8;
wire c9;
wire c10;
wire c11;
wire c12;
wire c13;
wire c14;
wire c15;
//sumas
wire s1;
wire s2;
wire s3;
wire s4;
wire s5;
wire s6;
wire s7;
wire s8;
and(z0, x0, y0); //z0
and(p01, x0, y1);
and(p02, x0, y2);
and(p03, x0, y3);
and(p10, x1, y0);
and(p11, x1, y1);
and(p12, x1, y2);
and(p13, x1, y3);
and(p20, x2, y0);
and(p21, x2, y1);
and(p22, x2, y2);
and(p23, x2, y3);
and(p30, x3, y0);
and(p31, x3, y1);
and(p32, x3, y2);
and(p33, x3, y3);
summed HA1(p01, p10, z1, c1); //z1
summed HA2(p11, p20, s1, c2);
sumcomp FA2(p02, s1, c1, z2, c3); //z2
sumcomp FA31(p21, p30, p12, s2, c4);
summed HA3(p03, s2, s3, c5);
sumcomp FA32(c2, s3, c3, z3, c6); //z3
sumcomp FA41(p22, p31, p13, s4, c7);
summed HA4(s4, c4, s5, c8);
sumcomp FA42(c5, s5, c6, z4, c9); //z4
summed HA51(p23, p32, s6, c10);
summed HA52(s6, c7, s7, c11);
sumcomp FA5(c8, s7, c9, z5, c12); //z5
summed HA6(p33, c10, s8, c13);
sumcomp FA6(c11, s8, c12, z6, c14); //z6
summed HA7(c13, c14, z7, c15); //z7
endmodule
|
`include "../include/tune.v"
// PentEvo project (c) NedoPC 2008-2011
//
// generates horizontal sync, blank and video start strobe, horizontal window
//
// =\ /=========||...
// ==\ /==========||...
// ====--- -------===========||...
// | \ / | |
// | --- | |
// | | | | |
// 0 t1 | t3 t4
// t2
// at 0, video ends and blank begins
// t1 = 10 clocks (@7MHz), sync begins
// t2-t1 = 33 clocks
// t3-t2 = 41 clocks, then video starts
//
// repetition period = 448 clocks
module video_sync_h(
input wire clk,
input wire init, // one-pulse strobe read at cend==1, initializes phase
// this is mainly for phasing with CPU clock 3.5/7 MHz
// still not used, but this may change anytime
input wire cend, // working strobes from DRAM controller (7MHz)
input wire pre_cend,
// modes inputs
input wire mode_atm_n_pent,
input wire mode_a_text,
output reg hblank,
output reg hsync,
output reg line_start, // 1 video cycle prior to actual start of visible line
output reg hsync_start, // 1 cycle prior to beginning of hsync: used in frame sync/blank generation
// these signals coincide with cend
output reg hint_start, // horizontal position of INT start, for fine tuning
output reg scanin_start,
output reg hpix, // marks gate during which pixels are outting
// these signals turn on and turn off 'go' signal
output reg fetch_start, // 18 cycles earlier than hpix, coincide with cend
output reg fetch_end // --//--
);
localparam HBLNK_BEG = 9'd00;
localparam HSYNC_BEG = 9'd10;
localparam HSYNC_END = 9'd43;
localparam HBLNK_END = 9'd88;
// pentagon (x256)
localparam HPIX_BEG_PENT = 9'd140; // 52 cycles from line_start to pixels beginning
localparam HPIX_END_PENT = 9'd396;
// atm (x320)
localparam HPIX_BEG_ATM = 9'd108; // 52 cycles from line_start to pixels beginning
localparam HPIX_END_ATM = 9'd428;
localparam FETCH_FOREGO = 9'd18; // consistent with older go_start in older fetch.v:
// actual data starts fetching 2 dram cycles after
// 'go' goes to 1, screen output starts another
// 16 cycles after 1st data bundle is fetched
localparam SCANIN_BEG = 9'd88; // when scan-doubler starts pixel storing
localparam HINT_BEG = 9'd2;
localparam HPERIOD = 9'd448;
reg [8:0] hcount;
// for simulation only
//
initial
begin
hcount = 9'd0;
hblank = 1'b0;
hsync = 1'b0;
line_start = 1'b0;
hsync_start = 1'b0;
hpix = 1'b0;
end
always @(posedge clk) if( cend )
begin
if( init || (hcount==(HPERIOD-9'd1)) )
hcount <= 9'd0;
else
hcount <= hcount + 9'd1;
end
always @(posedge clk) if( cend )
begin
if( hcount==HBLNK_BEG )
hblank <= 1'b1;
else if( hcount==HBLNK_END )
hblank <= 1'b0;
if( hcount==HSYNC_BEG )
hsync <= 1'b1;
else if( hcount==HSYNC_END )
hsync <= 1'b0;
end
always @(posedge clk)
begin
if( pre_cend )
begin
if( hcount==HSYNC_BEG )
hsync_start <= 1'b1;
if( hcount==HBLNK_END )
line_start <= 1'b1;
if( hcount==SCANIN_BEG )
scanin_start <= 1'b1;
end
else
begin
hsync_start <= 1'b0;
line_start <= 1'b0;
scanin_start <= 1'b0;
end
end
wire fetch_start_time, fetch_start_condition;
wire fetch_end_condition;
reg [3:0] fetch_start_wait;
assign fetch_start_time = (mode_atm_n_pent ?
(HPIX_BEG_ATM -FETCH_FOREGO-9'd4) :
(HPIX_BEG_PENT-FETCH_FOREGO-9'd4) ) == hcount;
always @(posedge clk) if( cend )
fetch_start_wait[3:0] <= { fetch_start_wait[2:0], fetch_start_time };
assign fetch_start_condition = mode_a_text ? fetch_start_time : fetch_start_wait[3];
always @(posedge clk)
if( pre_cend && fetch_start_condition )
fetch_start <= 1'b1;
else
fetch_start <= 1'b0;
assign fetch_end_time = (mode_atm_n_pent ?
(HPIX_END_ATM -FETCH_FOREGO) :
(HPIX_END_PENT-FETCH_FOREGO) ) == hcount;
always @(posedge clk)
if( pre_cend && fetch_end_time )
fetch_end <= 1'b1;
else
fetch_end <= 1'b0;
always @(posedge clk)
begin
if( pre_cend && (hcount==HINT_BEG) )
hint_start <= 1'b1;
else
hint_start <= 1'b0;
end
always @(posedge clk) if( cend )
begin
if( hcount==(mode_atm_n_pent ? HPIX_BEG_ATM : HPIX_BEG_PENT) )
hpix <= 1'b1;
else if( hcount==(mode_atm_n_pent ? HPIX_END_ATM : HPIX_END_PENT) )
hpix <= 1'b0;
end
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Wed Jul 20 01:57:48 2016
// Host : jalapeno running 64-bit unknown
// Command : write_verilog -force -mode funcsim {/home/hhassan/git/GateKeeper/FPGA
// Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_pe_fifo/shd_pe_fifo_sim_netlist.v}
// Design : shd_pe_fifo
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "shd_pe_fifo,fifo_generator_v13_0_1,{}" *) (* core_generation_info = "shd_pe_fifo,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH_NEGATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "fifo_generator_v13_0_1,Vivado 2015.4" *)
(* NotValidForBitStream *)
module shd_pe_fifo
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [31:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [31:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [9:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [9:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [9:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "32" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "32" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "virtex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "0" *)
(* C_PRELOAD_REGS = "1" *)
(* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "1022" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
shd_pe_fifo_fifo_generator_v13_0_1 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[9:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[9:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module shd_pe_fifo_blk_mem_gen_generic_cstr
(D,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]D;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire [31:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_pe_fifo_blk_mem_gen_prim_width \ramloop[0].ram.r
(.D(D),
.E(E),
.Q(Q),
.din(din),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module shd_pe_fifo_blk_mem_gen_prim_width
(D,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]D;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire [31:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_pe_fifo_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.D(D),
.E(E),
.Q(Q),
.din(din),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module shd_pe_fifo_blk_mem_gen_prim_wrapper
(D,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]D;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire [31:0]D;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gic0.gc0.count_d2_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI(din),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO(D),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(E),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({E,E,E,E}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module shd_pe_fifo_blk_mem_gen_top
(D,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]D;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire [31:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_pe_fifo_blk_mem_gen_generic_cstr \valid.cstr
(.D(D),
.E(E),
.Q(Q),
.din(din),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_1" *)
module shd_pe_fifo_blk_mem_gen_v8_3_1
(D,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]D;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire [31:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_pe_fifo_blk_mem_gen_v8_3_1_synth inst_blk_mem_gen
(.D(D),
.E(E),
.Q(Q),
.din(din),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_1_synth" *)
module shd_pe_fifo_blk_mem_gen_v8_3_1_synth
(D,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]D;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire [31:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_pe_fifo_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.D(D),
.E(E),
.Q(Q),
.din(din),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module shd_pe_fifo_clk_x_pntrs
(v1_reg,
WR_PNTR_RD,
v1_reg_0,
v1_reg_1,
Q,
\gic0.gc0.count_d1_reg[9] ,
\gic0.gc0.count_reg[9] ,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [4:0]v1_reg;
output [9:0]WR_PNTR_RD;
output [4:0]v1_reg_0;
output [4:0]v1_reg_1;
input [9:0]Q;
input [9:0]\gic0.gc0.count_d1_reg[9] ;
input [9:0]\gic0.gc0.count_reg[9] ;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]Q;
wire [9:0]WR_PNTR_RD;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [9:0]\gic0.gc0.count_reg[9] ;
wire \gsync_stage[2].wr_stg_inst_n_1 ;
wire \gsync_stage[2].wr_stg_inst_n_2 ;
wire \gsync_stage[2].wr_stg_inst_n_3 ;
wire \gsync_stage[2].wr_stg_inst_n_4 ;
wire \gsync_stage[2].wr_stg_inst_n_5 ;
wire \gsync_stage[2].wr_stg_inst_n_6 ;
wire \gsync_stage[2].wr_stg_inst_n_7 ;
wire \gsync_stage[2].wr_stg_inst_n_8 ;
wire \gsync_stage[2].wr_stg_inst_n_9 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [8:0]p_0_in;
wire [8:0]p_0_in8_out;
wire [9:9]p_0_out;
wire [9:9]p_1_out;
wire [9:0]p_22_out;
wire [9:0]p_2_out;
wire [9:0]p_3_out;
wire rd_clk;
wire [9:0]rd_pntr_gc;
wire \rd_pntr_gc[0]_i_1_n_0 ;
wire \rd_pntr_gc[1]_i_1_n_0 ;
wire \rd_pntr_gc[2]_i_1_n_0 ;
wire \rd_pntr_gc[3]_i_1_n_0 ;
wire \rd_pntr_gc[4]_i_1_n_0 ;
wire \rd_pntr_gc[5]_i_1_n_0 ;
wire \rd_pntr_gc[6]_i_1_n_0 ;
wire \rd_pntr_gc[7]_i_1_n_0 ;
wire \rd_pntr_gc[8]_i_1_n_0 ;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire [4:0]v1_reg_1;
wire wr_clk;
wire [9:0]wr_pntr_gc;
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(WR_PNTR_RD[1]),
.I1(Q[1]),
.I2(WR_PNTR_RD[0]),
.I3(Q[0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(p_22_out[1]),
.I1(\gic0.gc0.count_d1_reg[9] [1]),
.I2(p_22_out[0]),
.I3(\gic0.gc0.count_d1_reg[9] [0]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(p_22_out[1]),
.I1(\gic0.gc0.count_reg[9] [1]),
.I2(p_22_out[0]),
.I3(\gic0.gc0.count_reg[9] [0]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(WR_PNTR_RD[3]),
.I1(Q[3]),
.I2(WR_PNTR_RD[2]),
.I3(Q[2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(p_22_out[3]),
.I1(\gic0.gc0.count_d1_reg[9] [3]),
.I2(p_22_out[2]),
.I3(\gic0.gc0.count_d1_reg[9] [2]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(p_22_out[3]),
.I1(\gic0.gc0.count_reg[9] [3]),
.I2(p_22_out[2]),
.I3(\gic0.gc0.count_reg[9] [2]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(WR_PNTR_RD[5]),
.I1(Q[5]),
.I2(WR_PNTR_RD[4]),
.I3(Q[4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(p_22_out[5]),
.I1(\gic0.gc0.count_d1_reg[9] [5]),
.I2(p_22_out[4]),
.I3(\gic0.gc0.count_d1_reg[9] [4]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(p_22_out[5]),
.I1(\gic0.gc0.count_reg[9] [5]),
.I2(p_22_out[4]),
.I3(\gic0.gc0.count_reg[9] [4]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(WR_PNTR_RD[7]),
.I1(Q[7]),
.I2(WR_PNTR_RD[6]),
.I3(Q[6]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(p_22_out[7]),
.I1(\gic0.gc0.count_d1_reg[9] [7]),
.I2(p_22_out[6]),
.I3(\gic0.gc0.count_d1_reg[9] [6]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(p_22_out[7]),
.I1(\gic0.gc0.count_reg[9] [7]),
.I2(p_22_out[6]),
.I3(\gic0.gc0.count_reg[9] [6]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(WR_PNTR_RD[9]),
.I1(Q[9]),
.I2(WR_PNTR_RD[8]),
.I3(Q[8]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_22_out[9]),
.I1(\gic0.gc0.count_d1_reg[9] [9]),
.I2(p_22_out[8]),
.I3(\gic0.gc0.count_d1_reg[9] [8]),
.O(v1_reg_0[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(p_22_out[9]),
.I1(\gic0.gc0.count_reg[9] [9]),
.I2(p_22_out[8]),
.I3(\gic0.gc0.count_reg[9] [8]),
.O(v1_reg_1[4]));
shd_pe_fifo_synchronizer_ff \gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.rd_clk(rd_clk));
shd_pe_fifo_synchronizer_ff_3 \gsync_stage[1].wr_stg_inst
(.D(p_2_out),
.Q(rd_pntr_gc),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.wr_clk(wr_clk));
shd_pe_fifo_synchronizer_ff_4 \gsync_stage[2].rd_stg_inst
(.D(p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(p_1_out),
.rd_clk(rd_clk),
.\wr_pntr_bin_reg[8] (p_0_in));
shd_pe_fifo_synchronizer_ff_5 \gsync_stage[2].wr_stg_inst
(.D(p_2_out),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.out(p_0_out),
.\rd_pntr_bin_reg[8] ({\gsync_stage[2].wr_stg_inst_n_1 ,\gsync_stage[2].wr_stg_inst_n_2 ,\gsync_stage[2].wr_stg_inst_n_3 ,\gsync_stage[2].wr_stg_inst_n_4 ,\gsync_stage[2].wr_stg_inst_n_5 ,\gsync_stage[2].wr_stg_inst_n_6 ,\gsync_stage[2].wr_stg_inst_n_7 ,\gsync_stage[2].wr_stg_inst_n_8 ,\gsync_stage[2].wr_stg_inst_n_9 }),
.wr_clk(wr_clk));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_9 ),
.Q(p_22_out[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_8 ),
.Q(p_22_out[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_7 ),
.Q(p_22_out[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_6 ),
.Q(p_22_out[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_5 ),
.Q(p_22_out[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_4 ),
.Q(p_22_out[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_3 ),
.Q(p_22_out[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_2 ),
.Q(p_22_out[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_1 ),
.Q(p_22_out[8]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_out),
.Q(p_22_out[9]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[0]_i_1
(.I0(\gc0.count_d1_reg[9] [0]),
.I1(\gc0.count_d1_reg[9] [1]),
.O(\rd_pntr_gc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[1]_i_1
(.I0(\gc0.count_d1_reg[9] [1]),
.I1(\gc0.count_d1_reg[9] [2]),
.O(\rd_pntr_gc[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[2]_i_1
(.I0(\gc0.count_d1_reg[9] [2]),
.I1(\gc0.count_d1_reg[9] [3]),
.O(\rd_pntr_gc[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[3]_i_1
(.I0(\gc0.count_d1_reg[9] [3]),
.I1(\gc0.count_d1_reg[9] [4]),
.O(\rd_pntr_gc[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[4]_i_1
(.I0(\gc0.count_d1_reg[9] [4]),
.I1(\gc0.count_d1_reg[9] [5]),
.O(\rd_pntr_gc[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[5]_i_1
(.I0(\gc0.count_d1_reg[9] [5]),
.I1(\gc0.count_d1_reg[9] [6]),
.O(\rd_pntr_gc[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[6]_i_1
(.I0(\gc0.count_d1_reg[9] [6]),
.I1(\gc0.count_d1_reg[9] [7]),
.O(\rd_pntr_gc[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[7]_i_1
(.I0(\gc0.count_d1_reg[9] [7]),
.I1(\gc0.count_d1_reg[9] [8]),
.O(\rd_pntr_gc[7]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[8]_i_1
(.I0(\gc0.count_d1_reg[9] [8]),
.I1(\gc0.count_d1_reg[9] [9]),
.O(\rd_pntr_gc[8]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[0]_i_1_n_0 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[1]_i_1_n_0 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[2]_i_1_n_0 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[3]_i_1_n_0 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[4]_i_1_n_0 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[5]_i_1_n_0 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[6]_i_1_n_0 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[7]_i_1_n_0 ),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[8]_i_1_n_0 ),
.Q(rd_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[9] [9]),
.Q(rd_pntr_gc[9]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[0]),
.Q(WR_PNTR_RD[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[1]),
.Q(WR_PNTR_RD[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[2]),
.Q(WR_PNTR_RD[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[3]),
.Q(WR_PNTR_RD[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[4]),
.Q(WR_PNTR_RD[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[5]),
.Q(WR_PNTR_RD[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[6]),
.Q(WR_PNTR_RD[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[7]),
.Q(WR_PNTR_RD[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[8]),
.Q(WR_PNTR_RD[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_1_out),
.Q(WR_PNTR_RD[9]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [0]),
.I1(\gic0.gc0.count_d2_reg[9] [1]),
.O(p_0_in8_out[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [1]),
.I1(\gic0.gc0.count_d2_reg[9] [2]),
.O(p_0_in8_out[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [2]),
.I1(\gic0.gc0.count_d2_reg[9] [3]),
.O(p_0_in8_out[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[3]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [3]),
.I1(\gic0.gc0.count_d2_reg[9] [4]),
.O(p_0_in8_out[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[4]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [4]),
.I1(\gic0.gc0.count_d2_reg[9] [5]),
.O(p_0_in8_out[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[5]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [5]),
.I1(\gic0.gc0.count_d2_reg[9] [6]),
.O(p_0_in8_out[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[6]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [6]),
.I1(\gic0.gc0.count_d2_reg[9] [7]),
.O(p_0_in8_out[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[7]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [7]),
.I1(\gic0.gc0.count_d2_reg[9] [8]),
.O(p_0_in8_out[7]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[8]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [8]),
.I1(\gic0.gc0.count_d2_reg[9] [9]),
.O(p_0_in8_out[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[7]),
.Q(wr_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[8]),
.Q(wr_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gic0.gc0.count_d2_reg[9] [9]),
.Q(wr_pntr_gc[9]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module shd_pe_fifo_compare
(comp1,
v1_reg);
output comp1;
input [4:0]v1_reg;
wire comp1;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [4:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module shd_pe_fifo_compare_0
(ram_full_i,
v1_reg_0,
p_0_out,
wr_en,
comp1,
rst_full_gen_i);
output ram_full_i;
input [4:0]v1_reg_0;
input p_0_out;
input wr_en;
input comp1;
input rst_full_gen_i;
wire comp1;
wire comp2;
wire \gmux.gm[3].gms.ms_n_0 ;
wire p_0_out;
wire ram_full_i;
wire rst_full_gen_i;
wire [4:0]v1_reg_0;
wire wr_en;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
LUT5 #(
.INIT(32'h0000FF20))
ram_full_i_i_1
(.I0(comp2),
.I1(p_0_out),
.I2(wr_en),
.I3(comp1),
.I4(rst_full_gen_i),
.O(ram_full_i));
endmodule
(* ORIG_REF_NAME = "compare" *)
module shd_pe_fifo_compare_1
(ram_empty_fb_i_reg,
v1_reg_0,
p_2_out,
\gpregsm1.curr_fwft_state_reg[1] ,
rd_en,
comp1);
output ram_empty_fb_i_reg;
input [4:0]v1_reg_0;
input p_2_out;
input [1:0]\gpregsm1.curr_fwft_state_reg[1] ;
input rd_en;
input comp1;
wire comp0;
wire comp1;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [1:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire p_2_out;
wire ram_empty_fb_i_reg;
wire rd_en;
wire [4:0]v1_reg_0;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
LUT6 #(
.INIT(64'hBBBBABBBAAAAAAAA))
ram_empty_fb_i_i_1
(.I0(comp0),
.I1(p_2_out),
.I2(\gpregsm1.curr_fwft_state_reg[1] [0]),
.I3(\gpregsm1.curr_fwft_state_reg[1] [1]),
.I4(rd_en),
.I5(comp1),
.O(ram_empty_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module shd_pe_fifo_compare_2
(comp1,
v1_reg);
output comp1;
input [4:0]v1_reg;
wire comp1;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [4:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module shd_pe_fifo_fifo_generator_ramfifo
(empty,
full,
dout,
wr_clk,
rd_clk,
din,
rst,
rd_en,
wr_en);
output empty;
output full;
output [31:0]dout;
input wr_clk;
input rd_clk;
input [31:0]din;
input rst;
input rd_en;
input wr_en;
wire RD_RST;
wire RST;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire [4:0]\gras.rsts/c1/v1_reg ;
wire [4:0]\gwas.wsts/c1/v1_reg ;
wire [4:0]\gwas.wsts/c2/v1_reg ;
wire [9:0]p_0_out;
wire [9:0]p_11_out;
wire [9:0]p_12_out;
wire p_17_out;
wire [9:0]p_21_out;
wire p_5_out;
wire rd_clk;
wire rd_en;
wire [9:0]rd_pntr_plus1;
wire [1:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_en;
wire [9:0]wr_pntr_plus2;
wire [0:0]wr_rst_i;
shd_pe_fifo_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.Q(rd_pntr_plus1),
.WR_PNTR_RD(p_21_out),
.\gc0.count_d1_reg[9] (p_0_out),
.\gic0.gc0.count_d1_reg[9] (p_12_out),
.\gic0.gc0.count_d2_reg[9] (p_11_out),
.\gic0.gc0.count_reg[9] (wr_pntr_plus2),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (wr_rst_i),
.rd_clk(rd_clk),
.v1_reg(\gras.rsts/c1/v1_reg ),
.v1_reg_0(\gwas.wsts/c1/v1_reg ),
.v1_reg_1(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk));
shd_pe_fifo_rd_logic \gntv_or_sync_fifo.gl0.rd
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_0_out),
.E(p_5_out),
.Q({RD_RST,rd_rst_i[0]}),
.WR_PNTR_RD(p_21_out),
.empty(empty),
.\gc0.count_d1_reg[9] (rd_pntr_plus1),
.rd_clk(rd_clk),
.rd_en(rd_en),
.tmp_ram_rd_en(tmp_ram_rd_en),
.v1_reg(\gras.rsts/c1/v1_reg ));
shd_pe_fifo_wr_logic \gntv_or_sync_fifo.gl0.wr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_11_out),
.E(p_17_out),
.Q(wr_pntr_plus2),
.full(full),
.\gic0.gc0.count_d2_reg[9] (p_12_out),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (RST),
.rst_full_ff_i(rst_full_ff_i),
.rst_full_gen_i(rst_full_gen_i),
.v1_reg(\gwas.wsts/c1/v1_reg ),
.v1_reg_0(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk),
.wr_en(wr_en));
shd_pe_fifo_memory \gntv_or_sync_fifo.mem
(.E(p_17_out),
.Q(rd_rst_i[0]),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (p_0_out),
.\gic0.gc0.count_d2_reg[9] (p_11_out),
.\gpregsm1.curr_fwft_state_reg[1] (p_5_out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
shd_pe_fifo_reset_blk_ramfifo__parameterized0 rstblk
(.Q({RST,wr_rst_i}),
.\gc0.count_reg[1] ({RD_RST,rd_rst_i}),
.rd_clk(rd_clk),
.rst(rst),
.rst_full_ff_i(rst_full_ff_i),
.rst_full_gen_i(rst_full_gen_i),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module shd_pe_fifo_fifo_generator_top
(empty,
full,
dout,
wr_clk,
rd_clk,
din,
rst,
rd_en,
wr_en);
output empty;
output full;
output [31:0]dout;
input wr_clk;
input rd_clk;
input [31:0]din;
input rst;
input rd_en;
input wr_en;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
shd_pe_fifo_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "32" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "32" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "virtex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "0" *) (* C_PRELOAD_REGS = "1" *) (* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "1022" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *) (* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *)
(* ORIG_REF_NAME = "fifo_generator_v13_0_1" *)
module shd_pe_fifo_fifo_generator_v13_0_1
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [31:0]din;
input wr_en;
input rd_en;
input [9:0]prog_empty_thresh;
input [9:0]prog_empty_thresh_assert;
input [9:0]prog_empty_thresh_negate;
input [9:0]prog_full_thresh;
input [9:0]prog_full_thresh_assert;
input [9:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [31:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [9:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [9:0]prog_empty_thresh;
wire [9:0]prog_empty_thresh_assert;
wire [9:0]prog_empty_thresh_negate;
wire [9:0]prog_full_thresh;
wire [9:0]prog_full_thresh_assert;
wire [9:0]prog_full_thresh_negate;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire wr_clk;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
shd_pe_fifo_fifo_generator_v13_0_1_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.m_aclk(m_aclk),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v13_0_1_synth" *)
module shd_pe_fifo_fifo_generator_v13_0_1_synth
(dout,
empty,
full,
rd_en,
wr_clk,
rd_clk,
din,
s_aclk,
m_aclk,
rst,
wr_en,
s_aresetn);
output [31:0]dout;
output empty;
output full;
input rd_en;
input wr_clk;
input rd_clk;
input [31:0]din;
input s_aclk;
input m_aclk;
input rst;
input wr_en;
input s_aresetn;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire m_aclk;
wire rd_clk;
wire rd_en;
wire rst;
wire s_aclk;
wire s_aresetn;
wire wr_clk;
wire wr_en;
shd_pe_fifo_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en));
shd_pe_fifo_reset_blk_ramfifo \reset_gen_ic.rstblk_cc
(.m_aclk(m_aclk),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn));
endmodule
(* ORIG_REF_NAME = "memory" *)
module shd_pe_fifo_memory
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din,
\gpregsm1.curr_fwft_state_reg[1] );
output [31:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [31:0]dout;
wire [31:0]doutb;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_pe_fifo_blk_mem_gen_v8_3_1 \gbm.gbmg.gbmga.ngecc.bmg
(.D(doutb),
.E(E),
.Q(Q),
.din(din),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[0]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[0]),
.Q(dout[0]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[10]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[10]),
.Q(dout[10]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[11]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[11]),
.Q(dout[11]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[12]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[12]),
.Q(dout[12]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[13]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[13]),
.Q(dout[13]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[14]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[14]),
.Q(dout[14]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[15]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[15]),
.Q(dout[15]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[16]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[16]),
.Q(dout[16]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[17]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[17]),
.Q(dout[17]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[18]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[18]),
.Q(dout[18]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[19]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[19]),
.Q(dout[19]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[1]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[1]),
.Q(dout[1]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[20]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[20]),
.Q(dout[20]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[21]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[21]),
.Q(dout[21]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[22]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[22]),
.Q(dout[22]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[23]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[23]),
.Q(dout[23]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[24]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[24]),
.Q(dout[24]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[25]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[25]),
.Q(dout[25]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[26]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[26]),
.Q(dout[26]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[27]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[27]),
.Q(dout[27]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[28]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[28]),
.Q(dout[28]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[29]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[29]),
.Q(dout[29]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[2]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[2]),
.Q(dout[2]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[30]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[30]),
.Q(dout[30]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[31]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[31]),
.Q(dout[31]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[3]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[3]),
.Q(dout[3]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[4]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[4]),
.Q(dout[4]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[5]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[5]),
.Q(dout[5]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[6]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[6]),
.Q(dout[6]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[7]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[7]),
.Q(dout[7]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[8]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[8]),
.Q(dout[8]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[9]
(.C(rd_clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(doutb[9]),
.Q(dout[9]),
.R(Q));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module shd_pe_fifo_rd_bin_cntr
(Q,
v1_reg,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
WR_PNTR_RD,
E,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output [9:0]Q;
output [4:0]v1_reg;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input [9:0]WR_PNTR_RD;
input [0:0]E;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [9:0]Q;
wire [9:0]WR_PNTR_RD;
wire \gc0.count[9]_i_2_n_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire [9:0]plusOp;
wire rd_clk;
wire [4:0]v1_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h6A))
\gc0.count[2]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h6AAA))
\gc0.count[3]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[5]_i_1
(.I0(Q[5]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(Q[3]),
.I5(Q[4]),
.O(plusOp[5]));
LUT3 #(
.INIT(8'h6A))
\gc0.count[6]_i_1
(.I0(Q[6]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[5]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h6AAA))
\gc0.count[7]_i_1
(.I0(Q[7]),
.I1(Q[5]),
.I2(\gc0.count[9]_i_2_n_0 ),
.I3(Q[6]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[8]_i_1
(.I0(Q[8]),
.I1(Q[6]),
.I2(\gc0.count[9]_i_2_n_0 ),
.I3(Q[5]),
.I4(Q[7]),
.O(plusOp[8]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[9]_i_1
(.I0(Q[9]),
.I1(Q[7]),
.I2(Q[5]),
.I3(\gc0.count[9]_i_2_n_0 ),
.I4(Q[6]),
.I5(Q[8]),
.O(plusOp[9]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h80000000))
\gc0.count[9]_i_2
(.I0(Q[4]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.O(\gc0.count[9]_i_2_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp[0]),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[9]),
.Q(Q[9]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I1(WR_PNTR_RD[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I3(WR_PNTR_RD[0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.I1(WR_PNTR_RD[3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.I3(WR_PNTR_RD[2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.I1(WR_PNTR_RD[5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.I3(WR_PNTR_RD[4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.I1(WR_PNTR_RD[7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.I3(WR_PNTR_RD[6]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.I1(WR_PNTR_RD[9]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.I3(WR_PNTR_RD[8]),
.O(v1_reg[4]));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module shd_pe_fifo_rd_fwft
(empty,
E,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
tmp_ram_rd_en,
\goreg_bm.dout_i_reg[31] ,
rd_clk,
Q,
p_2_out,
rd_en);
output empty;
output [0:0]E;
output [1:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output tmp_ram_rd_en;
output [0:0]\goreg_bm.dout_i_reg[31] ;
input rd_clk;
input [1:0]Q;
input p_2_out;
input rd_en;
wire [1:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [1:0]Q;
wire empty;
wire empty_fwft_fb;
wire empty_fwft_i0;
wire [0:0]\goreg_bm.dout_i_reg[31] ;
wire \gpregsm1.curr_fwft_state[0]_i_1_n_0 ;
wire \gpregsm1.curr_fwft_state[1]_i_1_n_0 ;
wire p_2_out;
wire rd_clk;
wire rd_en;
wire tmp_ram_rd_en;
LUT5 #(
.INIT(32'hAAAAEFFF))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(Q[0]),
.I1(rd_en),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I4(p_2_out),
.O(tmp_ram_rd_en));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_reg
(.C(rd_clk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(Q[1]),
.Q(empty_fwft_fb));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hBA22))
empty_fwft_i_i_1
(.I0(empty_fwft_fb),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I2(rd_en),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.O(empty_fwft_i0));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(Q[1]),
.Q(empty));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h5515))
\gc0.count_d1[9]_i_1
(.I0(p_2_out),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I3(rd_en),
.O(E));
LUT3 #(
.INIT(8'h8A))
\goreg_bm.dout_i[31]_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I1(rd_en),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.O(\goreg_bm.dout_i_reg[31] ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hBA))
\gpregsm1.curr_fwft_state[0]_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I1(rd_en),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.O(\gpregsm1.curr_fwft_state[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h08FF))
\gpregsm1.curr_fwft_state[1]_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I2(rd_en),
.I3(p_2_out),
.O(\gpregsm1.curr_fwft_state[1]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q[1]),
.D(\gpregsm1.curr_fwft_state[0]_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q[1]),
.D(\gpregsm1.curr_fwft_state[1]_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module shd_pe_fifo_rd_logic
(empty,
\gc0.count_d1_reg[9] ,
tmp_ram_rd_en,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
E,
v1_reg,
rd_clk,
Q,
rd_en,
WR_PNTR_RD);
output empty;
output [9:0]\gc0.count_d1_reg[9] ;
output tmp_ram_rd_en;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [0:0]E;
input [4:0]v1_reg;
input rd_clk;
input [1:0]Q;
input rd_en;
input [9:0]WR_PNTR_RD;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [1:0]Q;
wire [9:0]WR_PNTR_RD;
wire [4:0]\c0/v1_reg ;
wire [0:0]curr_fwft_state;
wire empty;
wire [9:0]\gc0.count_d1_reg[9] ;
wire \gr1.rfwft_n_1 ;
wire \gr1.rfwft_n_2 ;
wire p_2_out;
wire rd_clk;
wire rd_en;
wire tmp_ram_rd_en;
wire [4:0]v1_reg;
shd_pe_fifo_rd_fwft \gr1.rfwft
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ({\gr1.rfwft_n_2 ,curr_fwft_state}),
.E(\gr1.rfwft_n_1 ),
.Q(Q),
.empty(empty),
.\goreg_bm.dout_i_reg[31] (E),
.p_2_out(p_2_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.tmp_ram_rd_en(tmp_ram_rd_en));
shd_pe_fifo_rd_status_flags_as \gras.rsts
(.Q(Q[1]),
.\gpregsm1.curr_fwft_state_reg[1] ({\gr1.rfwft_n_2 ,curr_fwft_state}),
.p_2_out(p_2_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ));
shd_pe_fifo_rd_bin_cntr rpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(\gr1.rfwft_n_1 ),
.Q(\gc0.count_d1_reg[9] ),
.WR_PNTR_RD(WR_PNTR_RD),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (Q[1]),
.rd_clk(rd_clk),
.v1_reg(\c0/v1_reg ));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module shd_pe_fifo_rd_status_flags_as
(p_2_out,
v1_reg_0,
v1_reg,
rd_clk,
Q,
\gpregsm1.curr_fwft_state_reg[1] ,
rd_en);
output p_2_out;
input [4:0]v1_reg_0;
input [4:0]v1_reg;
input rd_clk;
input [0:0]Q;
input [1:0]\gpregsm1.curr_fwft_state_reg[1] ;
input rd_en;
wire [0:0]Q;
wire c0_n_0;
wire comp1;
wire [1:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire p_2_out;
wire rd_clk;
wire rd_en;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
shd_pe_fifo_compare_1 c0
(.comp1(comp1),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.p_2_out(p_2_out),
.ram_empty_fb_i_reg(c0_n_0),
.rd_en(rd_en),
.v1_reg_0(v1_reg_0));
shd_pe_fifo_compare_2 c1
(.comp1(comp1),
.v1_reg(v1_reg));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(c0_n_0),
.PRE(Q),
.Q(p_2_out));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module shd_pe_fifo_reset_blk_ramfifo
(s_aclk,
m_aclk,
s_aresetn);
input s_aclk;
input m_aclk;
input s_aresetn;
wire inverted_reset;
wire m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire s_aresetn;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(inverted_reset),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(inverted_reset),
.Q(rst_d3));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
LUT1 #(
.INIT(2'h1))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1
(.I0(s_aresetn),
.O(inverted_reset));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module shd_pe_fifo_reset_blk_ramfifo__parameterized0
(rst_full_ff_i,
rst_full_gen_i,
Q,
\gc0.count_reg[1] ,
wr_clk,
rst,
rd_clk);
output rst_full_ff_i;
output rst_full_gen_i;
output [1:0]Q;
output [2:0]\gc0.count_reg[1] ;
input wr_clk;
input rst;
input rd_clk;
wire [1:0]Q;
wire [2:0]\gc0.count_reg[1] ;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0 ;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ;
wire rd_clk;
wire rd_rst_asreg;
wire rd_rst_asreg_d2;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire wr_clk;
wire wr_rst_asreg;
wire wr_rst_asreg_d2;
assign rst_full_ff_i = rst_d2;
assign rst_full_gen_i = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst),
.Q(rst_d3));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg),
.Q(\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0 ),
.Q(rd_rst_asreg_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(rd_rst_asreg),
.I1(\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0 ),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d2),
.O(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(\gc0.count_reg[1] [0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(\gc0.count_reg[1] [1]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(\gc0.count_reg[1] [2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg),
.Q(\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0 ),
.Q(wr_rst_asreg_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(wr_rst_asreg),
.I1(\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0 ),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d2),
.O(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ),
.Q(Q[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ),
.Q(Q[1]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module shd_pe_fifo_synchronizer_ff
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [9:0]D;
input [9:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module shd_pe_fifo_synchronizer_ff_3
(D,
Q,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [9:0]D;
input [9:0]Q;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [9:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire wr_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module shd_pe_fifo_synchronizer_ff_4
(out,
\wr_pntr_bin_reg[8] ,
D,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [0:0]out;
output [8:0]\wr_pntr_bin_reg[8] ;
input [9:0]D;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
wire \wr_pntr_bin[0]_i_2_n_0 ;
wire \wr_pntr_bin[3]_i_2_n_0 ;
wire [8:0]\wr_pntr_bin_reg[8] ;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(Q_reg[2]),
.I3(\wr_pntr_bin[0]_i_2_n_0 ),
.I4(\wr_pntr_bin[3]_i_2_n_0 ),
.O(\wr_pntr_bin_reg[8] [0]));
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[0]_i_2
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[9]),
.O(\wr_pntr_bin[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[9]),
.I2(Q_reg[3]),
.I3(Q_reg[4]),
.I4(\wr_pntr_bin[3]_i_2_n_0 ),
.I5(Q_reg[1]),
.O(\wr_pntr_bin_reg[8] [1]));
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[2]_i_1
(.I0(\wr_pntr_bin[3]_i_2_n_0 ),
.I1(Q_reg[4]),
.I2(Q_reg[3]),
.I3(Q_reg[9]),
.I4(Q_reg[2]),
.O(\wr_pntr_bin_reg[8] [2]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[3]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(\wr_pntr_bin[3]_i_2_n_0 ),
.O(\wr_pntr_bin_reg[8] [3]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[3]_i_2
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[5]),
.O(\wr_pntr_bin[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[9]),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\wr_pntr_bin_reg[8] [4]));
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[5]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[9]),
.I4(Q_reg[8]),
.O(\wr_pntr_bin_reg[8] [5]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[9]),
.I3(Q_reg[8]),
.O(\wr_pntr_bin_reg[8] [6]));
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(\wr_pntr_bin_reg[8] [7]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(\wr_pntr_bin_reg[8] [8]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module shd_pe_fifo_synchronizer_ff_5
(out,
\rd_pntr_bin_reg[8] ,
D,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [0:0]out;
output [8:0]\rd_pntr_bin_reg[8] ;
input [9:0]D;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [9:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire \rd_pntr_bin[0]_i_2_n_0 ;
wire \rd_pntr_bin[3]_i_2_n_0 ;
wire [8:0]\rd_pntr_bin_reg[8] ;
wire wr_clk;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(Q_reg[2]),
.I3(\rd_pntr_bin[0]_i_2_n_0 ),
.I4(\rd_pntr_bin[3]_i_2_n_0 ),
.O(\rd_pntr_bin_reg[8] [0]));
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[0]_i_2
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[9]),
.O(\rd_pntr_bin[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[9]),
.I2(Q_reg[3]),
.I3(Q_reg[4]),
.I4(\rd_pntr_bin[3]_i_2_n_0 ),
.I5(Q_reg[1]),
.O(\rd_pntr_bin_reg[8] [1]));
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[2]_i_1
(.I0(\rd_pntr_bin[3]_i_2_n_0 ),
.I1(Q_reg[4]),
.I2(Q_reg[3]),
.I3(Q_reg[9]),
.I4(Q_reg[2]),
.O(\rd_pntr_bin_reg[8] [2]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[3]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(\rd_pntr_bin[3]_i_2_n_0 ),
.O(\rd_pntr_bin_reg[8] [3]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[3]_i_2
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[5]),
.O(\rd_pntr_bin[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[9]),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\rd_pntr_bin_reg[8] [4]));
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[5]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[9]),
.I4(Q_reg[8]),
.O(\rd_pntr_bin_reg[8] [5]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[9]),
.I3(Q_reg[8]),
.O(\rd_pntr_bin_reg[8] [6]));
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(\rd_pntr_bin_reg[8] [7]));
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(\rd_pntr_bin_reg[8] [8]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module shd_pe_fifo_wr_bin_cntr
(Q,
\gic0.gc0.count_d2_reg[9]_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
E,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output [9:0]Q;
output [9:0]\gic0.gc0.count_d2_reg[9]_0 ;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input [0:0]E;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [9:0]Q;
wire \gic0.gc0.count[9]_i_2_n_0 ;
wire [9:0]\gic0.gc0.count_d2_reg[9]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [9:0]plusOp__0;
wire wr_clk;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h6A))
\gic0.gc0.count[2]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h6AAA))
\gic0.gc0.count[3]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gic0.gc0.count[5]_i_1
(.I0(Q[5]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(Q[3]),
.I5(Q[4]),
.O(plusOp__0[5]));
LUT3 #(
.INIT(8'h6A))
\gic0.gc0.count[6]_i_1
(.I0(Q[6]),
.I1(\gic0.gc0.count[9]_i_2_n_0 ),
.I2(Q[5]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h6AAA))
\gic0.gc0.count[7]_i_1
(.I0(Q[7]),
.I1(Q[5]),
.I2(\gic0.gc0.count[9]_i_2_n_0 ),
.I3(Q[6]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gic0.gc0.count[8]_i_1
(.I0(Q[8]),
.I1(Q[6]),
.I2(\gic0.gc0.count[9]_i_2_n_0 ),
.I3(Q[5]),
.I4(Q[7]),
.O(plusOp__0[8]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gic0.gc0.count[9]_i_1
(.I0(Q[9]),
.I1(Q[7]),
.I2(Q[5]),
.I3(\gic0.gc0.count[9]_i_2_n_0 ),
.I4(Q[6]),
.I5(Q[8]),
.O(plusOp__0[9]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h80000000))
\gic0.gc0.count[9]_i_2
(.I0(Q[4]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.O(\gic0.gc0.count[9]_i_2_n_0 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.D(Q[0]),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(\gic0.gc0.count_d2_reg[9]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[4]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[5]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[6]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[7]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[8]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(Q[9]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__0[1]),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module shd_pe_fifo_wr_logic
(full,
Q,
E,
\gic0.gc0.count_d2_reg[9] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
v1_reg,
v1_reg_0,
wr_clk,
rst_full_ff_i,
wr_en,
rst_full_gen_i,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output full;
output [9:0]Q;
output [0:0]E;
output [9:0]\gic0.gc0.count_d2_reg[9] ;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input wr_clk;
input rst_full_ff_i;
input wr_en;
input rst_full_gen_i;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [9:0]Q;
wire full;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire rst_full_ff_i;
wire rst_full_gen_i;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_clk;
wire wr_en;
shd_pe_fifo_wr_status_flags_as \gwas.wsts
(.E(E),
.full(full),
.rst_full_ff_i(rst_full_ff_i),
.rst_full_gen_i(rst_full_gen_i),
.v1_reg(v1_reg),
.v1_reg_0(v1_reg_0),
.wr_clk(wr_clk),
.wr_en(wr_en));
shd_pe_fifo_wr_bin_cntr wpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(E),
.Q(Q),
.\gic0.gc0.count_d2_reg[9]_0 (\gic0.gc0.count_d2_reg[9] ),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module shd_pe_fifo_wr_status_flags_as
(full,
E,
v1_reg,
v1_reg_0,
wr_clk,
rst_full_ff_i,
wr_en,
rst_full_gen_i);
output full;
output [0:0]E;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input wr_clk;
input rst_full_ff_i;
input wr_en;
input rst_full_gen_i;
wire [0:0]E;
wire comp1;
wire full;
wire p_0_out;
wire ram_full_i;
wire rst_full_ff_i;
wire rst_full_gen_i;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_clk;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(p_0_out),
.O(E));
shd_pe_fifo_compare c1
(.comp1(comp1),
.v1_reg(v1_reg));
shd_pe_fifo_compare_0 c2
(.comp1(comp1),
.p_0_out(p_0_out),
.ram_full_i(ram_full_i),
.rst_full_gen_i(rst_full_gen_i),
.v1_reg_0(v1_reg_0),
.wr_en(wr_en));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_full_ff_i),
.Q(p_0_out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_full_ff_i),
.Q(full));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O221AI_PP_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o221ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221AI_PP_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:31:40 11/01/2013
// Design Name: i2s_out
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/proyecto-final/i2s_test.v
// Project Name: proyecto-final
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: i2s_out
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module i2s_test;
// Inputs
reg clock;
reg reset;
reg [15:0] left_data;
reg [15:0] right_data;
// Outputs
wire mclk;
wire lrck;
wire sclk;
wire sdin;
// Instantiate the Unit Under Test (UUT)
i2s_out uut (
.clock(clock),
.reset(reset),
.left_data(left_data),
.right_data(right_data),
.mclk(mclk),
.lrck(lrck),
.sclk(sclk),
.sdin(sdin)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
left_data = 16'd63351;
right_data = 16'd1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Rose-Hulman Institute of Technology
// Engineer: Adam and Mohammad
// Create Date: 20:09:31 10/24/2015
// Design Name: Phase 1 I2C controller
// Module Name: ControllerI2C
// Summary: Determines the signals to send to the Data Unit to conform to the
// I2C protocol. See the previously submitted ACM diagram.
//////////////////////////////////////////////////////////////////////////////////
module ControllerI2C(Clock,ClockI2C,Go,Reset,BaudEnable,ReadOrWrite,Select,ShiftOrHold,StartStopAck,WriteLoad);
input Clock, ClockI2C, Go, Reset;
output reg BaudEnable, ReadOrWrite, Select, ShiftOrHold, StartStopAck, WriteLoad;
parameter InitialState = 3'd0;
parameter StartState = 3'd1;
parameter LoadState = 3'd2;
parameter SendState = 3'd3;
parameter AckState = 3'd4;
parameter DelayState = 3'd5;
parameter StopState = 3'd6;
reg [2:0] State;
reg [2:0] NextState;
reg [3:0] DataCounter;
reg DelayLoopStart;
wire Timeout;
wire OneShotI2C;
wire RisingOneShotI2C;
NegClockedOneShot OneShotUnit(ClockI2C, OneShotI2C, Reset, Clock);
PosClockedOneShot RisingOneShotUnit(ClockI2C, RisingOneShotI2C, Reset, Clock);
DelayLoop Timer(DelayLoopStart,Timeout,Clock);
always @ (State)
case (State)
InitialState: begin
ReadOrWrite <= 0;
Select <= 0;
BaudEnable <= 0;
StartStopAck <= 1;
DelayLoopStart <= 1;
end
StartState: begin
BaudEnable <= 0;
StartStopAck <= 0;
DelayLoopStart <= 0;
end
LoadState: begin
DelayLoopStart <= 1;
BaudEnable <= 1;
end
SendState:
if (DataCounter == 1) begin BaudEnable <= 1; ReadOrWrite <= 1; Select <= 0; StartStopAck <= 0; DelayLoopStart <= 1; end
else begin BaudEnable <= 1; Select <= 1; end
AckState: begin
BaudEnable <= 1;
ReadOrWrite <= 1;
Select <= 0;
StartStopAck <= 0;
DelayLoopStart <= 1;
end
DelayState: begin
BaudEnable <= 0;
Select <= 0;
ReadOrWrite <= 0;
StartStopAck <= 0;
DelayLoopStart <= 0;
end
StopState: begin
BaudEnable <= 0;
ReadOrWrite <= 0;
Select <= 0;
StartStopAck <= 1;
DelayLoopStart <= 1;
end
endcase
always @ (State or Go or ClockI2C or Timeout or DataCounter)
case (State)
InitialState: NextState <= Go == 0 ? InitialState : (ClockI2C == 0 ? InitialState : StartState);
StartState: NextState <= Timeout == 0 ? StartState : LoadState;
LoadState: NextState <= DataCounter <= 4'd9 ? SendState : LoadState;
SendState: NextState <= OneShotI2C == 1 ? NextState : (DataCounter == 0 ? AckState : SendState);
AckState: NextState <= DelayState;
DelayState: NextState <= Timeout == 0 ? DelayState : StopState;
StopState: NextState <= ClockI2C == 0 ? StopState : StopState;
endcase
always @ (OneShotI2C)
if (OneShotI2C == 1) begin ShiftOrHold <= 0; WriteLoad <= 0; end
else case (State)
SendState: ShiftOrHold <= 1;
LoadState: WriteLoad <= 1;
endcase
always @ (posedge Clock or posedge Reset)
if (Reset == 1) begin DataCounter <= 4'd10; end
else
case (State)
LoadState: DataCounter <= OneShotI2C == 0 ? DataCounter - 1 : DataCounter;
SendState: DataCounter <= OneShotI2C == 0 ? DataCounter - 1 : DataCounter;
AckState: DataCounter <= OneShotI2C == 0 ? DataCounter - 1 : DataCounter;
default: DataCounter <= 4'd10;
endcase
always @ (posedge Clock or posedge Reset)
if (Reset == 1) State <= InitialState;
else if (State == AckState) State <= DelayState;
else State <= NextState;
endmodule
|
module wb_upsizer
#(parameter DW_IN = 0,
parameter SCALE = 0,
parameter AW = 32)
(input wb_clk_i,
input wb_rst_i,
input [AW-1:0] wbs_adr_i,
input [DW_IN-1:0] wbs_dat_i,
input [DW_IN/8-1:0] wbs_sel_i,
input wbs_we_i,
input wbs_cyc_i,
input wbs_stb_i,
input [2:0] wbs_cti_i,
input [1:0] wbs_bte_i,
output [DW_IN-1:0] wbs_dat_o,
output wbs_ack_o,
output wbs_err_o,
output wbs_rty_o,
//Master port
output [AW-1:0] wbm_adr_o,
output reg [DW_IN*SCALE-1:0] wbm_dat_o,
output [DW_IN*SCALE/8-1:0] wbm_sel_o,
output wbm_we_o,
output wbm_cyc_o,
output wbm_stb_o,
output [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
input [DW_IN*SCALE-1:0] wbm_dat_i,
input wbm_ack_i,
input wbm_err_i,
input wbm_rty_i);
`include "wb_common.v"
localparam SELW = DW_IN/8; //sel width
localparam DW_OUT = DW_IN*SCALE;
localparam SW_OUT = SELW*SCALE;
localparam BUFW = $clog2(DW_IN/8)-1; //Buffer width
localparam ADR_LSB = BUFW+1; //Bit position of the LSB of the buffer address. Lower bits are used for index part
localparam [1:0]
S_IDLE = 2'b00,
S_READ = 2'b01,
S_WRITE = 2'b10;
reg [1:0] state;
wire [AW-1:ADR_LSB] adr_i;
wire [BUFW-1:0] idx_i;
reg [AW-1:ADR_LSB] radr;
reg [DW_OUT-1:0] rdat;
reg rdat_vld;
wire [AW-1:0] next_adr = wb_next_adr(wbs_adr_i, wbs_cti_i, wbs_bte_i, DW_IN)>> ($clog2(SELW)+BUFW);
wire req = wbs_cyc_i & wbs_stb_i;
wire wr_req = req & wbs_we_i;
wire last = wbs_cyc_i & (wbs_cti_i == 3'b000 | wbs_cti_i == 3'b111);
wire last_in_batch = (adr_i != next_adr) | last;
wire bufhit = (adr_i == radr) & rdat_vld;
wire next_bufhit = (next_adr == radr);
reg [AW-1:0] wr_adr;
reg [DW_IN*SCALE/8-1:0] wr_sel;
reg wr_we;
reg wr_cyc;
reg wr_stb;
reg [2:0] wr_cti;
reg [1:0] wr_bte;
reg [DW_OUT-1:0] wdat;
reg [DW_OUT/8-1:0] sel;
reg write_ack;
reg first_ack;
assign {adr_i,idx_i} = wbs_adr_i>>$clog2(SELW);
reg [AW-1:0] next_radr;
reg wbm_stb_o_r;
wire rd_cyc = wbs_cyc_i & !(last & bufhit);
assign wbs_dat_o = rdat_vld ?
rdat[idx_i*DW_IN+:DW_IN] :
wbm_dat_i[idx_i*DW_IN+:DW_IN];
wire wr = (wr_req | wr_cyc);
assign wbs_ack_o = wr ? write_ack : (wbm_ack_i | bufhit);
wire [AW-1:0] rd_adr = (first_ack/*wbm_stb_o_r*/ ? next_adr : adr_i) << ($clog2(SELW) + BUFW);
assign wbm_adr_o = wr ? wr_adr : rd_adr;
assign wbm_sel_o = wr ? wr_sel : {SW_OUT{1'b1}};
assign wbm_we_o = wr ? wr_cyc : 1'b0;
assign wbm_cyc_o = wr ? wr_cyc : rd_cyc;
assign wbm_stb_o = wr ? wr_stb : rd_cyc;
assign wbm_cti_o = wr ? wr_cti : 3'b111;
assign wbm_bte_o = wr ? wr_bte : 2'b00;
always @(posedge wb_clk_i) begin
if (wbs_ack_o & !wr) begin
first_ack <= 1'b1;
if (last) first_ack <= 1'b0;
end
write_ack <= 1'b0;
wbm_stb_o_r <= wbm_stb_o & ! wbm_we_o;
if (wbm_cyc_o & wbm_ack_i & last) begin
rdat_vld <= 1'b0;
end
case (state)
S_IDLE : begin
wr_cyc <= 1'b0;
wr_stb <= 1'b0;
wr_cti <= 3'b000;
wr_bte <= 2'b00;
if (req) begin
radr <= wbm_adr_o >> ($clog2(SELW)+BUFW);
wr_adr <= adr_i << ($clog2(SELW)+BUFW);
wr_cti <= wbs_cti_i;
wr_bte <= wbs_bte_i;
if (wbs_we_i) begin
wr_cyc <= 1'b1;
wr_stb <= last_in_batch;
wbm_dat_o[idx_i*DW_IN+:DW_IN] <= wbs_dat_i;
wr_sel[idx_i*SELW+:SELW] <= wbs_sel_i;
//FIXME
wbm_dat_o[(!idx_i)*DW_IN+:DW_IN] <= {DW_IN{1'b0}};
wr_sel[(!idx_i)*SELW+:SELW] <= {SELW{1'b0}};
write_ack <= 1'b1 | (!last_in_batch) & !(last & wbs_ack_o);
state <= S_WRITE;
end else begin //Read request
if (wbs_cti_i == 3'b111)
rdat_vld <= 1'b0;
if (!next_bufhit | !first_ack/*!wbm_stb_o_r*/) begin
rdat_vld <= 1'b0;
state <= S_READ;
end
end
end
end
S_READ : begin
if (wbm_ack_i) begin
next_radr <= wb_next_adr(wbs_adr_i, wbs_cti_i, wbs_bte_i, DW_OUT)>> ($clog2(SELW)+BUFW);
//next_radr <= next_adr;
radr <= adr_i;
rdat <= wbm_dat_i;
rdat_vld <= !last;
state <= S_IDLE;
wbm_stb_o_r <= 1'b1;
end
end
S_WRITE : begin
//write_ack <= (!last_in_batch | wbm_ack_i) & !(last & wbs_ack_o);
if (!wr_stb | wbm_ack_i) begin
write_ack <= !last & (!last_in_batch | wbm_ack_i);
wr_adr <= adr_i << ($clog2(SELW)+BUFW);
wdat[idx_i*DW_IN+:DW_IN] <= wbs_dat_i;
sel[idx_i*SELW+:SELW] <= wbs_sel_i;
if (last_in_batch) begin
wbm_dat_o[idx_i*DW_IN+:DW_IN] <= wbs_dat_i;
wbm_dat_o[(!idx_i)*DW_IN+:DW_IN] <= wdat[(!idx_i)*DW_IN+:DW_IN];
wr_sel[idx_i*SELW+:SELW] <= wbs_sel_i;
wr_sel[(!idx_i)*SELW+:SELW] <= sel[(!idx_i)*SELW+:SELW];
sel <= 0;
end
wr_sel[idx_i*SELW+:SELW] <= wbs_sel_i;
wr_stb <= last_in_batch;
wr_cti <= wbs_cti_i;
wr_bte <= wbs_bte_i;
end
if ((wbm_cti_o == 3'b111) & wbm_ack_i) begin
write_ack <= 1'b0;
wr_adr <= 0;
wbm_dat_o <= 0;
wr_sel <= 0;
wr_stb <= 1'b0;
wr_cyc <= 1'b0;
state <= S_IDLE;
end
end
default : state <= S_IDLE;
endcase
if (wb_rst_i) begin
state <= S_IDLE;
rdat_vld <= 1'b0;
first_ack <= 1'b0;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.03.2014 14:42:56
// Design Name:
// Module Name: pcie_and_stats
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pcie_bridge
(
input [7:0]pcie_7x_mgt_rxn,
input [7:0]pcie_7x_mgt_rxp,
output [7:0]pcie_7x_mgt_txn,
output [7:0]pcie_7x_mgt_txp,
input pcie_clkp,
input pcie_clkn,
input pcie_reset,
output clkOut,
output user_lnk_up,
//address write
output [31: 0] pcie_axi_AWADDR,
output pcie_axi_AWVALID,
input pcie_axi_AWREADY,
//data write
output [31: 0] pcie_axi_WDATA,
output [3: 0] pcie_axi_WSTRB,
output pcie_axi_WVALID,
input pcie_axi_WREADY,
//write response (handhake)
input [1:0] pcie_axi_BRESP,
input pcie_axi_BVALID,
output pcie_axi_BREADY,
//address read
output [31: 0] pcie_axi_ARADDR,
output pcie_axi_ARVALID,
input pcie_axi_ARREADY,
//data read
input [31: 0] pcie_axi_RDATA,
input [1:0] pcie_axi_RRESP,
input pcie_axi_RVALID,
output pcie_axi_RREADY
);
wire sys_clk;
wire GND_1;
wire [11:0]axi_bram_ctrl_1_bram_porta_ADDR;
wire axi_bram_ctrl_1_bram_porta_CLK;
wire [31:0]axi_bram_ctrl_1_bram_porta_DIN;
wire [31:0]axi_bram_ctrl_1_bram_porta_DOUT;
wire axi_bram_ctrl_1_bram_porta_EN;
wire axi_bram_ctrl_1_bram_porta_RST;
wire [3:0]axi_bram_ctrl_1_bram_porta_WE;
wire [63:0]pcie3_7x_0_m_axis_cq_TDATA;
wire [1:0]pcie3_7x_0_m_axis_cq_TKEEP;
wire pcie3_7x_0_m_axis_cq_TLAST;
wire [21:0]pcie3_7x_0_m_axis_cq_TREADY;
wire [84:0]pcie3_7x_0_m_axis_cq_TUSER;
wire pcie3_7x_0_m_axis_cq_TVALID;
wire [7:0]pcie3_7x_0_pcie_7x_mgt_rxn;
wire [7:0]pcie3_7x_0_pcie_7x_mgt_rxp;
wire [7:0]pcie3_7x_0_pcie_7x_mgt_txn;
wire [7:0]pcie3_7x_0_pcie_7x_mgt_txp;
wire pcie3_7x_0_user_clk;
wire pcie3_7x_0_user_lnk_up;
wire [63:0]pcie_2_axilite_0_m_axis_cc_TDATA;
wire [1:0]pcie_2_axilite_0_m_axis_cc_TKEEP;
wire pcie_2_axilite_0_m_axis_cc_TLAST;
wire [3:0]pcie_2_axilite_0_m_axis_cc_TREADY;
wire [32:0]pcie_2_axilite_0_m_axis_cc_TUSER;
wire pcie_2_axilite_0_m_axis_cc_TVALID;
assign pcie3_7x_0_pcie_7x_mgt_rxn = pcie_7x_mgt_rxn[7:0];
assign pcie3_7x_0_pcie_7x_mgt_rxp = pcie_7x_mgt_rxp[7:0];
assign pcie_7x_mgt_txn[7:0] = pcie3_7x_0_pcie_7x_mgt_txn;
assign pcie_7x_mgt_txp[7:0] = pcie3_7x_0_pcie_7x_mgt_txp;
assign clkOut= pcie3_7x_0_user_clk;
assign user_lnk_up = pcie3_7x_0_user_lnk_up;
//assign pcie3_7x_0_m_axis_cq_TUSER = 85'b0;
//assign pcie_2_axilite_0_m_axis_cc_TUSER = 33'b0;
GND GND(.G(GND_1));
IBUFDS_GTE2 #(
.CLKCM_CFG("TRUE"), // Refer to Transceiver User Guide
.CLKRCV_TRST("TRUE"), // Refer to Transceiver User Guide
.CLKSWING_CFG(2'b11) // Refer to Transceiver User Guide
)
IBUFDS_GTE2_inst (
.O(sys_clk), // 1-bit output: Refer to Transceiver User Guide
.ODIV2(), // 1-bit output: Refer to Transceiver User Guide
.CEB(GND_1), // 1-bit input: Refer to Transceiver User Guide
.I(pcie_clkp), // 1-bit input: Refer to Transceiver User Guide
.IB(pcie_clkn) // 1-bit input: Refer to Transceiver User Guide
);
pcie2axilite_sub_pcie3_7x_0 pcie3_7x_0
(.cfg_interrupt_int({GND_1,GND_1,GND_1,GND_1}),
.cfg_interrupt_msi_attr({GND_1,GND_1,GND_1}),
.cfg_interrupt_msi_function_number({GND_1,GND_1,GND_1}),
.cfg_interrupt_msi_int({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.cfg_interrupt_msi_pending_status({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.cfg_interrupt_msi_select({GND_1,GND_1,GND_1,GND_1}),
.cfg_interrupt_msi_tph_present(GND_1),
.cfg_interrupt_msi_tph_st_tag({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.cfg_interrupt_msi_tph_type({GND_1,GND_1}),
.cfg_interrupt_pending({GND_1,GND_1}),
.int_pclk_sel_slave({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.m_axis_cq_tdata(pcie3_7x_0_m_axis_cq_TDATA),
.m_axis_cq_tkeep(pcie3_7x_0_m_axis_cq_TKEEP),
.m_axis_cq_tlast(pcie3_7x_0_m_axis_cq_TLAST),
.m_axis_cq_tready(pcie3_7x_0_m_axis_cq_TREADY),
.m_axis_cq_tuser(pcie3_7x_0_m_axis_cq_TUSER),
.m_axis_cq_tvalid(pcie3_7x_0_m_axis_cq_TVALID),
.m_axis_rc_tready({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.pci_exp_rxn(pcie3_7x_0_pcie_7x_mgt_rxn),
.pci_exp_rxp(pcie3_7x_0_pcie_7x_mgt_rxp),
.pci_exp_txn(pcie3_7x_0_pcie_7x_mgt_txn),
.pci_exp_txp(pcie3_7x_0_pcie_7x_mgt_txp),
.s_axis_cc_tdata(pcie_2_axilite_0_m_axis_cc_TDATA),
.s_axis_cc_tkeep(pcie_2_axilite_0_m_axis_cc_TKEEP),
.s_axis_cc_tlast(pcie_2_axilite_0_m_axis_cc_TLAST),
.s_axis_cc_tready(pcie_2_axilite_0_m_axis_cc_TREADY),
.s_axis_cc_tuser(pcie_2_axilite_0_m_axis_cc_TUSER),
.s_axis_cc_tvalid(pcie_2_axilite_0_m_axis_cc_TVALID),
.s_axis_rq_tdata({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axis_rq_tkeep({GND_1,GND_1}),
.s_axis_rq_tlast(GND_1),
.s_axis_rq_tuser({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axis_rq_tvalid(GND_1),
.sys_clk(sys_clk),
.sys_reset(pcie_reset),
.user_clk(pcie3_7x_0_user_clk),
.user_lnk_up(pcie3_7x_0_user_lnk_up));
pcie2axilite_sub_pcie_2_axilite_0 pcie_2_axilite_0
(.axi_aresetn(pcie3_7x_0_user_lnk_up),
.axi_clk(pcie3_7x_0_user_clk),
.m_axi_araddr(pcie_axi_ARADDR),
.m_axi_arprot(),
.m_axi_arready(pcie_axi_ARREADY),
.m_axi_arvalid(pcie_axi_ARVALID),
.m_axi_awaddr(pcie_axi_AWADDR),
.m_axi_awprot(),
.m_axi_awready(pcie_axi_AWREADY),
.m_axi_awvalid(pcie_axi_AWVALID),
.m_axi_bready(pcie_axi_BREADY),
.m_axi_bresp(pcie_axi_BRESP),
.m_axi_bvalid(pcie_axi_BVALID),
.m_axi_rdata(pcie_axi_RDATA),
.m_axi_rready(pcie_axi_RREADY),
.m_axi_rresp(pcie_axi_RRESP),
.m_axi_rvalid(pcie_axi_RVALID),
.m_axi_wdata(pcie_axi_WDATA),
.m_axi_wready(pcie_axi_WREADY),
.m_axi_wstrb(pcie_axi_WSTRB),
.m_axi_wvalid(pcie_axi_WVALID),
.m_axis_cc_tdata(pcie_2_axilite_0_m_axis_cc_TDATA),
.m_axis_cc_tkeep(pcie_2_axilite_0_m_axis_cc_TKEEP),
.m_axis_cc_tlast(pcie_2_axilite_0_m_axis_cc_TLAST),
.m_axis_cc_tready(pcie_2_axilite_0_m_axis_cc_TREADY),
.m_axis_cc_tuser(pcie_2_axilite_0_m_axis_cc_TUSER),
.m_axis_cc_tvalid(pcie_2_axilite_0_m_axis_cc_TVALID),
.s_axis_cq_tdata(pcie3_7x_0_m_axis_cq_TDATA),
.s_axis_cq_tkeep(pcie3_7x_0_m_axis_cq_TKEEP),
.s_axis_cq_tlast(pcie3_7x_0_m_axis_cq_TLAST),
.s_axis_cq_tready(pcie3_7x_0_m_axis_cq_TREADY),
.s_axis_cq_tuser(pcie3_7x_0_m_axis_cq_TUSER),
.s_axis_cq_tvalid(pcie3_7x_0_m_axis_cq_TVALID));
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_spi_slave;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg output_axis_tready = 1'b0;
reg cs = 1'b0;
reg sck = 1'b0;
reg mosi = 1'b0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire miso;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
output_axis_tready,
cs,
sck,
mosi);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
miso,
busy);
// dump file
$dumpfile("test_axis_spi_slave.lxt");
$dumpvars(0, test_axis_spi_slave);
end
axis_spi_slave #(
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
// spi interface
.cs(cs),
.sck(sck),
.mosi(mosi),
.miso(miso),
// status
.busy(busy)
);
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Thu Aug 25 17:35:55 2016
// Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/kobayashi/PCIe_test/branches/IEICE/16-way/src/ip_pcie/PCIeGen2x8If128_stub.v
// Design : PCIeGen2x8If128
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "PCIeGen2x8If128_pcie2_top,Vivado 2015.4" *)
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_16_V
`define SKY130_FD_SC_HDLL__CLKBUF_16_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkbuf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_16_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR3_4_V
`define SKY130_FD_SC_HDLL__XOR3_4_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR3_4_V
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// mv_vm_xlate O 201
// RDY_mv_vm_xlate O 1 const
// RDY_ma_insert O 1 const
// RDY_ma_flush O 1 const
// CLK I 1 clock
// RST_N I 1 unused
// mv_vm_xlate_va I 64
// mv_vm_xlate_satp I 64
// mv_vm_xlate_read_not_write I 1
// mv_vm_xlate_priv I 2
// mv_vm_xlate_sstatus_SUM I 1
// mv_vm_xlate_mstatus_MXR I 1
// ma_insert_asid I 16 reg
// ma_insert_vpn I 27
// ma_insert_pte I 64 reg
// ma_insert_level I 2
// ma_insert_pte_pa I 64 reg
// EN_ma_insert I 1
// EN_ma_flush I 1
//
// Combinational paths from inputs to outputs:
// (mv_vm_xlate_va,
// mv_vm_xlate_satp,
// mv_vm_xlate_read_not_write,
// mv_vm_xlate_priv,
// mv_vm_xlate_sstatus_SUM,
// mv_vm_xlate_mstatus_MXR) -> mv_vm_xlate
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTLB(CLK,
RST_N,
mv_vm_xlate_va,
mv_vm_xlate_satp,
mv_vm_xlate_read_not_write,
mv_vm_xlate_priv,
mv_vm_xlate_sstatus_SUM,
mv_vm_xlate_mstatus_MXR,
mv_vm_xlate,
RDY_mv_vm_xlate,
ma_insert_asid,
ma_insert_vpn,
ma_insert_pte,
ma_insert_level,
ma_insert_pte_pa,
EN_ma_insert,
RDY_ma_insert,
EN_ma_flush,
RDY_ma_flush);
parameter [0 : 0] dmem_not_imem = 1'b0;
parameter [2 : 0] verbosity = 3'b0;
input CLK;
input RST_N;
// value method mv_vm_xlate
input [63 : 0] mv_vm_xlate_va;
input [63 : 0] mv_vm_xlate_satp;
input mv_vm_xlate_read_not_write;
input [1 : 0] mv_vm_xlate_priv;
input mv_vm_xlate_sstatus_SUM;
input mv_vm_xlate_mstatus_MXR;
output [200 : 0] mv_vm_xlate;
output RDY_mv_vm_xlate;
// action method ma_insert
input [15 : 0] ma_insert_asid;
input [26 : 0] ma_insert_vpn;
input [63 : 0] ma_insert_pte;
input [1 : 0] ma_insert_level;
input [63 : 0] ma_insert_pte_pa;
input EN_ma_insert;
output RDY_ma_insert;
// action method ma_flush
input EN_ma_flush;
output RDY_ma_flush;
// signals for module outputs
wire [200 : 0] mv_vm_xlate;
wire RDY_ma_flush, RDY_ma_insert, RDY_mv_vm_xlate;
// register tlb0_valids_0
reg tlb0_valids_0;
wire tlb0_valids_0$D_IN, tlb0_valids_0$EN;
// register tlb0_valids_1
reg tlb0_valids_1;
wire tlb0_valids_1$D_IN, tlb0_valids_1$EN;
// register tlb0_valids_10
reg tlb0_valids_10;
wire tlb0_valids_10$D_IN, tlb0_valids_10$EN;
// register tlb0_valids_11
reg tlb0_valids_11;
wire tlb0_valids_11$D_IN, tlb0_valids_11$EN;
// register tlb0_valids_12
reg tlb0_valids_12;
wire tlb0_valids_12$D_IN, tlb0_valids_12$EN;
// register tlb0_valids_13
reg tlb0_valids_13;
wire tlb0_valids_13$D_IN, tlb0_valids_13$EN;
// register tlb0_valids_14
reg tlb0_valids_14;
wire tlb0_valids_14$D_IN, tlb0_valids_14$EN;
// register tlb0_valids_15
reg tlb0_valids_15;
wire tlb0_valids_15$D_IN, tlb0_valids_15$EN;
// register tlb0_valids_2
reg tlb0_valids_2;
wire tlb0_valids_2$D_IN, tlb0_valids_2$EN;
// register tlb0_valids_3
reg tlb0_valids_3;
wire tlb0_valids_3$D_IN, tlb0_valids_3$EN;
// register tlb0_valids_4
reg tlb0_valids_4;
wire tlb0_valids_4$D_IN, tlb0_valids_4$EN;
// register tlb0_valids_5
reg tlb0_valids_5;
wire tlb0_valids_5$D_IN, tlb0_valids_5$EN;
// register tlb0_valids_6
reg tlb0_valids_6;
wire tlb0_valids_6$D_IN, tlb0_valids_6$EN;
// register tlb0_valids_7
reg tlb0_valids_7;
wire tlb0_valids_7$D_IN, tlb0_valids_7$EN;
// register tlb0_valids_8
reg tlb0_valids_8;
wire tlb0_valids_8$D_IN, tlb0_valids_8$EN;
// register tlb0_valids_9
reg tlb0_valids_9;
wire tlb0_valids_9$D_IN, tlb0_valids_9$EN;
// register tlb1_valids_0
reg tlb1_valids_0;
wire tlb1_valids_0$D_IN, tlb1_valids_0$EN;
// register tlb1_valids_1
reg tlb1_valids_1;
wire tlb1_valids_1$D_IN, tlb1_valids_1$EN;
// register tlb1_valids_2
reg tlb1_valids_2;
wire tlb1_valids_2$D_IN, tlb1_valids_2$EN;
// register tlb1_valids_3
reg tlb1_valids_3;
wire tlb1_valids_3$D_IN, tlb1_valids_3$EN;
// register tlb1_valids_4
reg tlb1_valids_4;
wire tlb1_valids_4$D_IN, tlb1_valids_4$EN;
// register tlb1_valids_5
reg tlb1_valids_5;
wire tlb1_valids_5$D_IN, tlb1_valids_5$EN;
// register tlb1_valids_6
reg tlb1_valids_6;
wire tlb1_valids_6$D_IN, tlb1_valids_6$EN;
// register tlb1_valids_7
reg tlb1_valids_7;
wire tlb1_valids_7$D_IN, tlb1_valids_7$EN;
// register tlb2_valids_0
reg tlb2_valids_0;
wire tlb2_valids_0$D_IN, tlb2_valids_0$EN;
// register tlb2_valids_1
reg tlb2_valids_1;
wire tlb2_valids_1$D_IN, tlb2_valids_1$EN;
// register tlb2_valids_2
reg tlb2_valids_2;
wire tlb2_valids_2$D_IN, tlb2_valids_2$EN;
// register tlb2_valids_3
reg tlb2_valids_3;
wire tlb2_valids_3$D_IN, tlb2_valids_3$EN;
// ports of submodule tlb0_entries
wire [166 : 0] tlb0_entries$D_IN, tlb0_entries$D_OUT_1;
wire [3 : 0] tlb0_entries$ADDR_1,
tlb0_entries$ADDR_2,
tlb0_entries$ADDR_3,
tlb0_entries$ADDR_4,
tlb0_entries$ADDR_5,
tlb0_entries$ADDR_IN;
wire tlb0_entries$WE;
// ports of submodule tlb1_entries
wire [158 : 0] tlb1_entries$D_IN, tlb1_entries$D_OUT_1;
wire [2 : 0] tlb1_entries$ADDR_1,
tlb1_entries$ADDR_2,
tlb1_entries$ADDR_3,
tlb1_entries$ADDR_4,
tlb1_entries$ADDR_5,
tlb1_entries$ADDR_IN;
wire tlb1_entries$WE;
// ports of submodule tlb2_entries
wire [150 : 0] tlb2_entries$D_IN, tlb2_entries$D_OUT_1;
wire [1 : 0] tlb2_entries$ADDR_1,
tlb2_entries$ADDR_2,
tlb2_entries$ADDR_3,
tlb2_entries$ADDR_4,
tlb2_entries$ADDR_5,
tlb2_entries$ADDR_IN;
wire tlb2_entries$WE;
// rule scheduling signals
wire CAN_FIRE_RL_rl_flush,
CAN_FIRE_ma_flush,
CAN_FIRE_ma_insert,
WILL_FIRE_RL_rl_flush,
WILL_FIRE_ma_flush,
WILL_FIRE_ma_insert;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h7675;
reg [31 : 0] v__h6243;
reg [31 : 0] v__h6237;
reg [31 : 0] v__h7669;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] _theResult___fst__h7287;
reg SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28,
SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d50,
SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb2_v_ETC___d68;
wire [129 : 0] IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95,
IF_SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb_ETC___d89,
IF_SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb_ETC___d94;
wire [63 : 0] _theResult___fst__h6368,
_theResult___fst__h7006,
_theResult___snd_fst__h6370,
_theResult___snd_fst__h7008,
_theResult___snd_fst__h7512,
pa___1__h7292,
pa___1__h7341,
pa___1__h7409,
pte___1__h7561,
pte___1__h7590,
pte___2__h7285,
x__h6616,
x__h6636,
x__h7281,
x__h7596;
wire [55 : 0] x__h7295, x__h7344, x__h7412;
wire [3 : 0] exc_code___1__h7274;
wire [1 : 0] IF_mv_vm_xlate_priv_EQ_0b0_0_AND_NOT_IF_SEL_AR_ETC___d130,
IF_mv_vm_xlate_priv_ULE_0b1_AND_mv_vm_xlate_sa_ETC___d132;
wire IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d113,
NOT_dmem_not_imem_09_AND_mv_vm_xlate_read_not__ETC___d170,
NOT_mv_vm_xlate_priv_EQ_0b0_0_57_OR_IF_SEL_ARR_ETC___d184,
NOT_verbosity_ULE_1___d3,
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d35,
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d61,
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d79,
SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d56,
SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb2_v_ETC___d74,
dmem_not_imem_OR_NOT_mv_vm_xlate_read_not_writ_ETC___d121,
mv_vm_xlate_priv_EQ_0b0_0_AND_NOT_IF_SEL_ARR_t_ETC___d122,
y__h7125;
// value method mv_vm_xlate
assign mv_vm_xlate =
{ IF_mv_vm_xlate_priv_ULE_0b1_AND_mv_vm_xlate_sa_ETC___d132,
x__h7281,
exc_code___1__h7274,
mv_vm_xlate_priv <= 2'b01 && mv_vm_xlate_satp[63:60] == 4'd8 &&
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d79 &&
NOT_mv_vm_xlate_priv_EQ_0b0_0_57_OR_IF_SEL_ARR_ETC___d184,
x__h7596,
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[65:0] } ;
assign RDY_mv_vm_xlate = 1'd1 ;
// action method ma_insert
assign RDY_ma_insert = 1'd1 ;
assign CAN_FIRE_ma_insert = 1'd1 ;
assign WILL_FIRE_ma_insert = EN_ma_insert ;
// action method ma_flush
assign RDY_ma_flush = 1'd1 ;
assign CAN_FIRE_ma_flush = 1'd1 ;
assign WILL_FIRE_ma_flush = EN_ma_flush ;
// submodule tlb0_entries
RegFile #(.addr_width(32'd4),
.data_width(32'd167),
.lo(4'h0),
.hi(4'd15)) tlb0_entries(.CLK(CLK),
.ADDR_1(tlb0_entries$ADDR_1),
.ADDR_2(tlb0_entries$ADDR_2),
.ADDR_3(tlb0_entries$ADDR_3),
.ADDR_4(tlb0_entries$ADDR_4),
.ADDR_5(tlb0_entries$ADDR_5),
.ADDR_IN(tlb0_entries$ADDR_IN),
.D_IN(tlb0_entries$D_IN),
.WE(tlb0_entries$WE),
.D_OUT_1(tlb0_entries$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule tlb1_entries
RegFile #(.addr_width(32'd3),
.data_width(32'd159),
.lo(3'h0),
.hi(3'd7)) tlb1_entries(.CLK(CLK),
.ADDR_1(tlb1_entries$ADDR_1),
.ADDR_2(tlb1_entries$ADDR_2),
.ADDR_3(tlb1_entries$ADDR_3),
.ADDR_4(tlb1_entries$ADDR_4),
.ADDR_5(tlb1_entries$ADDR_5),
.ADDR_IN(tlb1_entries$ADDR_IN),
.D_IN(tlb1_entries$D_IN),
.WE(tlb1_entries$WE),
.D_OUT_1(tlb1_entries$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule tlb2_entries
RegFile #(.addr_width(32'd2),
.data_width(32'd151),
.lo(2'h0),
.hi(2'd3)) tlb2_entries(.CLK(CLK),
.ADDR_1(tlb2_entries$ADDR_1),
.ADDR_2(tlb2_entries$ADDR_2),
.ADDR_3(tlb2_entries$ADDR_3),
.ADDR_4(tlb2_entries$ADDR_4),
.ADDR_5(tlb2_entries$ADDR_5),
.ADDR_IN(tlb2_entries$ADDR_IN),
.D_IN(tlb2_entries$D_IN),
.WE(tlb2_entries$WE),
.D_OUT_1(tlb2_entries$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// rule RL_rl_flush
assign CAN_FIRE_RL_rl_flush = EN_ma_flush ;
assign WILL_FIRE_RL_rl_flush = EN_ma_flush ;
// register tlb0_valids_0
assign tlb0_valids_0$D_IN = !EN_ma_flush ;
assign tlb0_valids_0$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd0 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_1
assign tlb0_valids_1$D_IN = !EN_ma_flush ;
assign tlb0_valids_1$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd1 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_10
assign tlb0_valids_10$D_IN = !EN_ma_flush ;
assign tlb0_valids_10$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd10 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_11
assign tlb0_valids_11$D_IN = !EN_ma_flush ;
assign tlb0_valids_11$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd11 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_12
assign tlb0_valids_12$D_IN = !EN_ma_flush ;
assign tlb0_valids_12$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd12 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_13
assign tlb0_valids_13$D_IN = !EN_ma_flush ;
assign tlb0_valids_13$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd13 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_14
assign tlb0_valids_14$D_IN = !EN_ma_flush ;
assign tlb0_valids_14$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd14 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_15
assign tlb0_valids_15$D_IN = !EN_ma_flush ;
assign tlb0_valids_15$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd15 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_2
assign tlb0_valids_2$D_IN = !EN_ma_flush ;
assign tlb0_valids_2$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd2 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_3
assign tlb0_valids_3$D_IN = !EN_ma_flush ;
assign tlb0_valids_3$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd3 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_4
assign tlb0_valids_4$D_IN = !EN_ma_flush ;
assign tlb0_valids_4$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd4 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_5
assign tlb0_valids_5$D_IN = !EN_ma_flush ;
assign tlb0_valids_5$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd5 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_6
assign tlb0_valids_6$D_IN = !EN_ma_flush ;
assign tlb0_valids_6$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd6 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_7
assign tlb0_valids_7$D_IN = !EN_ma_flush ;
assign tlb0_valids_7$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd7 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_8
assign tlb0_valids_8$D_IN = !EN_ma_flush ;
assign tlb0_valids_8$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd8 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb0_valids_9
assign tlb0_valids_9$D_IN = !EN_ma_flush ;
assign tlb0_valids_9$EN =
EN_ma_insert && ma_insert_vpn[3:0] == 4'd9 &&
ma_insert_level == 2'd0 ||
EN_ma_flush ;
// register tlb1_valids_0
assign tlb1_valids_0$D_IN = !EN_ma_flush ;
assign tlb1_valids_0$EN =
EN_ma_insert && ma_insert_vpn[11:9] == 3'd0 &&
ma_insert_level == 2'd1 ||
EN_ma_flush ;
// register tlb1_valids_1
assign tlb1_valids_1$D_IN = !EN_ma_flush ;
assign tlb1_valids_1$EN =
EN_ma_insert && ma_insert_vpn[11:9] == 3'd1 &&
ma_insert_level == 2'd1 ||
EN_ma_flush ;
// register tlb1_valids_2
assign tlb1_valids_2$D_IN = !EN_ma_flush ;
assign tlb1_valids_2$EN =
EN_ma_insert && ma_insert_vpn[11:9] == 3'd2 &&
ma_insert_level == 2'd1 ||
EN_ma_flush ;
// register tlb1_valids_3
assign tlb1_valids_3$D_IN = !EN_ma_flush ;
assign tlb1_valids_3$EN =
EN_ma_insert && ma_insert_vpn[11:9] == 3'd3 &&
ma_insert_level == 2'd1 ||
EN_ma_flush ;
// register tlb1_valids_4
assign tlb1_valids_4$D_IN = !EN_ma_flush ;
assign tlb1_valids_4$EN =
EN_ma_insert && ma_insert_vpn[11:9] == 3'd4 &&
ma_insert_level == 2'd1 ||
EN_ma_flush ;
// register tlb1_valids_5
assign tlb1_valids_5$D_IN = !EN_ma_flush ;
assign tlb1_valids_5$EN =
EN_ma_insert && ma_insert_vpn[11:9] == 3'd5 &&
ma_insert_level == 2'd1 ||
EN_ma_flush ;
// register tlb1_valids_6
assign tlb1_valids_6$D_IN = !EN_ma_flush ;
assign tlb1_valids_6$EN =
EN_ma_insert && ma_insert_vpn[11:9] == 3'd6 &&
ma_insert_level == 2'd1 ||
EN_ma_flush ;
// register tlb1_valids_7
assign tlb1_valids_7$D_IN = !EN_ma_flush ;
assign tlb1_valids_7$EN =
EN_ma_insert && ma_insert_vpn[11:9] == 3'd7 &&
ma_insert_level == 2'd1 ||
EN_ma_flush ;
// register tlb2_valids_0
assign tlb2_valids_0$D_IN = !EN_ma_flush ;
assign tlb2_valids_0$EN =
EN_ma_insert && ma_insert_vpn[19:18] == 2'd0 &&
ma_insert_level != 2'd0 &&
ma_insert_level != 2'd1 ||
EN_ma_flush ;
// register tlb2_valids_1
assign tlb2_valids_1$D_IN = !EN_ma_flush ;
assign tlb2_valids_1$EN =
EN_ma_insert && ma_insert_vpn[19:18] == 2'd1 &&
ma_insert_level != 2'd0 &&
ma_insert_level != 2'd1 ||
EN_ma_flush ;
// register tlb2_valids_2
assign tlb2_valids_2$D_IN = !EN_ma_flush ;
assign tlb2_valids_2$EN =
EN_ma_insert && ma_insert_vpn[19:18] == 2'd2 &&
ma_insert_level != 2'd0 &&
ma_insert_level != 2'd1 ||
EN_ma_flush ;
// register tlb2_valids_3
assign tlb2_valids_3$D_IN = !EN_ma_flush ;
assign tlb2_valids_3$EN =
EN_ma_insert && ma_insert_vpn[19:18] == 2'd3 &&
ma_insert_level != 2'd0 &&
ma_insert_level != 2'd1 ||
EN_ma_flush ;
// submodule tlb0_entries
assign tlb0_entries$ADDR_1 = mv_vm_xlate_va[15:12] ;
assign tlb0_entries$ADDR_2 = 4'h0 ;
assign tlb0_entries$ADDR_3 = 4'h0 ;
assign tlb0_entries$ADDR_4 = 4'h0 ;
assign tlb0_entries$ADDR_5 = 4'h0 ;
assign tlb0_entries$ADDR_IN = ma_insert_vpn[3:0] ;
assign tlb0_entries$D_IN =
{ ma_insert_asid,
ma_insert_vpn[26:4],
ma_insert_pte,
ma_insert_pte_pa } ;
assign tlb0_entries$WE = EN_ma_insert && ma_insert_level == 2'd0 ;
// submodule tlb1_entries
assign tlb1_entries$ADDR_1 = mv_vm_xlate_va[23:21] ;
assign tlb1_entries$ADDR_2 = 3'h0 ;
assign tlb1_entries$ADDR_3 = 3'h0 ;
assign tlb1_entries$ADDR_4 = 3'h0 ;
assign tlb1_entries$ADDR_5 = 3'h0 ;
assign tlb1_entries$ADDR_IN = ma_insert_vpn[11:9] ;
assign tlb1_entries$D_IN =
{ ma_insert_asid,
ma_insert_vpn[26:12],
ma_insert_pte,
ma_insert_pte_pa } ;
assign tlb1_entries$WE = EN_ma_insert && ma_insert_level == 2'd1 ;
// submodule tlb2_entries
assign tlb2_entries$ADDR_1 = mv_vm_xlate_va[31:30] ;
assign tlb2_entries$ADDR_2 = 2'h0 ;
assign tlb2_entries$ADDR_3 = 2'h0 ;
assign tlb2_entries$ADDR_4 = 2'h0 ;
assign tlb2_entries$ADDR_5 = 2'h0 ;
assign tlb2_entries$ADDR_IN = ma_insert_vpn[19:18] ;
assign tlb2_entries$D_IN =
{ ma_insert_asid,
ma_insert_vpn[26:20],
ma_insert_pte,
ma_insert_pte_pa } ;
assign tlb2_entries$WE =
EN_ma_insert && ma_insert_level != 2'd0 &&
ma_insert_level != 2'd1 ;
// remaining internal signals
assign IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d113 =
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[67] |
y__h7125 ;
assign IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95 =
{ x__h6616, 2'd0, x__h6636 } |
IF_SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb_ETC___d89 |
IF_SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb_ETC___d94 ;
assign IF_SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb_ETC___d89 =
(SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d56 &&
tlb1_entries$D_OUT_1[142:128] == mv_vm_xlate_va[38:24]) ?
{ tlb1_entries$D_OUT_1[127:64],
2'd1,
tlb1_entries$D_OUT_1[63:0] } :
130'd0 ;
assign IF_SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb_ETC___d94 =
(SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb2_v_ETC___d74 &&
tlb2_entries$D_OUT_1[134:128] == mv_vm_xlate_va[38:32]) ?
{ tlb2_entries$D_OUT_1[127:64],
2'd2,
tlb2_entries$D_OUT_1[63:0] } :
130'd0 ;
assign IF_mv_vm_xlate_priv_EQ_0b0_0_AND_NOT_IF_SEL_AR_ETC___d130 =
(mv_vm_xlate_priv_EQ_0b0_0_AND_NOT_IF_SEL_ARR_t_ETC___d122 ||
!IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[72] ||
!mv_vm_xlate_read_not_write &&
!IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[73]) ?
2'd2 :
2'd0 ;
assign IF_mv_vm_xlate_priv_ULE_0b1_AND_mv_vm_xlate_sa_ETC___d132 =
(mv_vm_xlate_priv <= 2'b01 && mv_vm_xlate_satp[63:60] == 4'd8) ?
(SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d79 ?
IF_mv_vm_xlate_priv_EQ_0b0_0_AND_NOT_IF_SEL_AR_ETC___d130 :
2'd1) :
2'd0 ;
assign NOT_dmem_not_imem_09_AND_mv_vm_xlate_read_not__ETC___d170 =
!dmem_not_imem && mv_vm_xlate_read_not_write &&
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[69] ||
dmem_not_imem && mv_vm_xlate_read_not_write &&
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d113 ||
dmem_not_imem && !mv_vm_xlate_read_not_write &&
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[68] ;
assign NOT_mv_vm_xlate_priv_EQ_0b0_0_57_OR_IF_SEL_ARR_ETC___d184 =
(mv_vm_xlate_priv != 2'b0 ||
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[70]) &&
(mv_vm_xlate_priv != 2'b01 ||
!IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[70] ||
mv_vm_xlate_sstatus_SUM) &&
NOT_dmem_not_imem_09_AND_mv_vm_xlate_read_not__ETC___d170 &&
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[72] &&
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[73] &&
!pte___2__h7285[7] &&
!mv_vm_xlate_read_not_write ;
assign NOT_verbosity_ULE_1___d3 = verbosity > 3'd1 ;
assign SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d35 =
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 &&
(tlb0_entries$D_OUT_1[166:151] == mv_vm_xlate_satp[59:44] ||
tlb0_entries$D_OUT_1[69]) ;
assign SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d61 =
(SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d35 &&
tlb0_entries$D_OUT_1[150:128] == mv_vm_xlate_va[38:16]) |
(SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d56 &&
tlb1_entries$D_OUT_1[142:128] == mv_vm_xlate_va[38:24]) ;
assign SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d79 =
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d61 |
(SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb2_v_ETC___d74 &&
tlb2_entries$D_OUT_1[134:128] == mv_vm_xlate_va[38:32]) ;
assign SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d56 =
SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d50 &&
(tlb1_entries$D_OUT_1[158:143] == mv_vm_xlate_satp[59:44] ||
tlb1_entries$D_OUT_1[69]) ;
assign SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb2_v_ETC___d74 =
SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb2_v_ETC___d68 &&
(tlb2_entries$D_OUT_1[150:135] == mv_vm_xlate_satp[59:44] ||
tlb2_entries$D_OUT_1[69]) ;
assign _theResult___fst__h6368 =
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d79 ?
_theResult___fst__h7006 :
mv_vm_xlate_va ;
assign _theResult___fst__h7006 =
(mv_vm_xlate_priv_EQ_0b0_0_AND_NOT_IF_SEL_ARR_t_ETC___d122 ||
!IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[72] ||
!mv_vm_xlate_read_not_write &&
!IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[73]) ?
mv_vm_xlate_va :
_theResult___fst__h7287 ;
assign _theResult___snd_fst__h6370 =
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d79 ?
_theResult___snd_fst__h7008 :
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[129:66] ;
assign _theResult___snd_fst__h7008 =
(mv_vm_xlate_priv_EQ_0b0_0_AND_NOT_IF_SEL_ARR_t_ETC___d122 ||
!IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[72] ||
!mv_vm_xlate_read_not_write &&
!IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[73]) ?
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[129:66] :
_theResult___snd_fst__h7512 ;
assign _theResult___snd_fst__h7512 =
(!pte___2__h7285[7] && !mv_vm_xlate_read_not_write) ?
pte___1__h7590 :
pte___2__h7285 ;
assign dmem_not_imem_OR_NOT_mv_vm_xlate_read_not_writ_ETC___d121 =
(dmem_not_imem || !mv_vm_xlate_read_not_write ||
!IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[69]) &&
(!dmem_not_imem || !mv_vm_xlate_read_not_write ||
!IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d113) &&
(!dmem_not_imem || mv_vm_xlate_read_not_write ||
!IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[68]) ;
assign exc_code___1__h7274 =
dmem_not_imem ?
(mv_vm_xlate_read_not_write ? 4'd13 : 4'd15) :
4'd12 ;
assign mv_vm_xlate_priv_EQ_0b0_0_AND_NOT_IF_SEL_ARR_t_ETC___d122 =
mv_vm_xlate_priv == 2'b0 &&
!IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[70] ||
mv_vm_xlate_priv == 2'b01 &&
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[70] &&
!mv_vm_xlate_sstatus_SUM ||
dmem_not_imem_OR_NOT_mv_vm_xlate_read_not_writ_ETC___d121 ;
assign pa___1__h7292 = { 8'd0, x__h7295 } ;
assign pa___1__h7341 = { 8'd0, x__h7344 } ;
assign pa___1__h7409 = { 8'd0, x__h7412 } ;
assign pte___1__h7561 =
{ IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[129:73],
1'd1,
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[71:66] } ;
assign pte___1__h7590 =
{ pte___2__h7285[63:8], 1'd1, pte___2__h7285[6:0] } ;
assign pte___2__h7285 =
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[72] ?
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[129:66] :
pte___1__h7561 ;
assign x__h6616 =
(SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d35 &&
tlb0_entries$D_OUT_1[150:128] == mv_vm_xlate_va[38:16]) ?
tlb0_entries$D_OUT_1[127:64] :
64'd0 ;
assign x__h6636 =
(SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d35 &&
tlb0_entries$D_OUT_1[150:128] == mv_vm_xlate_va[38:16]) ?
tlb0_entries$D_OUT_1[63:0] :
64'd0 ;
assign x__h7281 =
(mv_vm_xlate_priv <= 2'b01 && mv_vm_xlate_satp[63:60] == 4'd8) ?
_theResult___fst__h6368 :
mv_vm_xlate_va ;
assign x__h7295 =
{ IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[119:76],
mv_vm_xlate_va[11:0] } ;
assign x__h7344 =
{ IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[119:85],
mv_vm_xlate_va[20:0] } ;
assign x__h7412 =
{ IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[119:94],
mv_vm_xlate_va[29:0] } ;
assign x__h7596 =
(mv_vm_xlate_priv <= 2'b01 && mv_vm_xlate_satp[63:60] == 4'd8) ?
_theResult___snd_fst__h6370 :
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[129:66] ;
assign y__h7125 =
mv_vm_xlate_mstatus_MXR &
IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[69] ;
always@(mv_vm_xlate_va or
tlb0_valids_0 or
tlb0_valids_1 or
tlb0_valids_2 or
tlb0_valids_3 or
tlb0_valids_4 or
tlb0_valids_5 or
tlb0_valids_6 or
tlb0_valids_7 or
tlb0_valids_8 or
tlb0_valids_9 or
tlb0_valids_10 or
tlb0_valids_11 or
tlb0_valids_12 or
tlb0_valids_13 or tlb0_valids_14 or tlb0_valids_15)
begin
case (mv_vm_xlate_va[15:12])
4'd0:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_0;
4'd1:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_1;
4'd2:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_2;
4'd3:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_3;
4'd4:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_4;
4'd5:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_5;
4'd6:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_6;
4'd7:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_7;
4'd8:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_8;
4'd9:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_9;
4'd10:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_10;
4'd11:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_11;
4'd12:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_12;
4'd13:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_13;
4'd14:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_14;
4'd15:
SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb0_v_ETC___d28 =
tlb0_valids_15;
endcase
end
always@(mv_vm_xlate_va or
tlb1_valids_0 or
tlb1_valids_1 or
tlb1_valids_2 or
tlb1_valids_3 or
tlb1_valids_4 or tlb1_valids_5 or tlb1_valids_6 or tlb1_valids_7)
begin
case (mv_vm_xlate_va[23:21])
3'd0:
SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d50 =
tlb1_valids_0;
3'd1:
SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d50 =
tlb1_valids_1;
3'd2:
SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d50 =
tlb1_valids_2;
3'd3:
SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d50 =
tlb1_valids_3;
3'd4:
SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d50 =
tlb1_valids_4;
3'd5:
SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d50 =
tlb1_valids_5;
3'd6:
SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d50 =
tlb1_valids_6;
3'd7:
SEL_ARR_tlb1_valids_0_0_tlb1_valids_1_1_tlb1_v_ETC___d50 =
tlb1_valids_7;
endcase
end
always@(mv_vm_xlate_va or
tlb2_valids_0 or tlb2_valids_1 or tlb2_valids_2 or tlb2_valids_3)
begin
case (mv_vm_xlate_va[31:30])
2'd0:
SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb2_v_ETC___d68 =
tlb2_valids_0;
2'd1:
SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb2_v_ETC___d68 =
tlb2_valids_1;
2'd2:
SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb2_v_ETC___d68 =
tlb2_valids_2;
2'd3:
SEL_ARR_tlb2_valids_0_2_tlb2_valids_1_3_tlb2_v_ETC___d68 =
tlb2_valids_3;
endcase
end
always@(IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95 or
mv_vm_xlate_va or pa___1__h7292 or pa___1__h7341 or pa___1__h7409)
begin
case (IF_SEL_ARR_tlb0_valids_0_0_tlb0_valids_1_1_tlb_ETC___d95[65:64])
2'd0: _theResult___fst__h7287 = pa___1__h7292;
2'd1: _theResult___fst__h7287 = pa___1__h7341;
2'd2: _theResult___fst__h7287 = pa___1__h7409;
2'd3: _theResult___fst__h7287 = mv_vm_xlate_va;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (tlb0_valids_0$EN)
tlb0_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_0$D_IN;
if (tlb0_valids_1$EN)
tlb0_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_1$D_IN;
if (tlb0_valids_10$EN)
tlb0_valids_10 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_10$D_IN;
if (tlb0_valids_11$EN)
tlb0_valids_11 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_11$D_IN;
if (tlb0_valids_12$EN)
tlb0_valids_12 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_12$D_IN;
if (tlb0_valids_13$EN)
tlb0_valids_13 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_13$D_IN;
if (tlb0_valids_14$EN)
tlb0_valids_14 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_14$D_IN;
if (tlb0_valids_15$EN)
tlb0_valids_15 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_15$D_IN;
if (tlb0_valids_2$EN)
tlb0_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_2$D_IN;
if (tlb0_valids_3$EN)
tlb0_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_3$D_IN;
if (tlb0_valids_4$EN)
tlb0_valids_4 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_4$D_IN;
if (tlb0_valids_5$EN)
tlb0_valids_5 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_5$D_IN;
if (tlb0_valids_6$EN)
tlb0_valids_6 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_6$D_IN;
if (tlb0_valids_7$EN)
tlb0_valids_7 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_7$D_IN;
if (tlb0_valids_8$EN)
tlb0_valids_8 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_8$D_IN;
if (tlb0_valids_9$EN)
tlb0_valids_9 <= `BSV_ASSIGNMENT_DELAY tlb0_valids_9$D_IN;
if (tlb1_valids_0$EN)
tlb1_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_0$D_IN;
if (tlb1_valids_1$EN)
tlb1_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_1$D_IN;
if (tlb1_valids_2$EN)
tlb1_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_2$D_IN;
if (tlb1_valids_3$EN)
tlb1_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_3$D_IN;
if (tlb1_valids_4$EN)
tlb1_valids_4 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_4$D_IN;
if (tlb1_valids_5$EN)
tlb1_valids_5 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_5$D_IN;
if (tlb1_valids_6$EN)
tlb1_valids_6 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_6$D_IN;
if (tlb1_valids_7$EN)
tlb1_valids_7 <= `BSV_ASSIGNMENT_DELAY tlb1_valids_7$D_IN;
if (tlb2_valids_0$EN)
tlb2_valids_0 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_0$D_IN;
if (tlb2_valids_1$EN)
tlb2_valids_1 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_1$D_IN;
if (tlb2_valids_2$EN)
tlb2_valids_2 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_2$D_IN;
if (tlb2_valids_3$EN)
tlb2_valids_3 <= `BSV_ASSIGNMENT_DELAY tlb2_valids_3$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
tlb0_valids_0 = 1'h0;
tlb0_valids_1 = 1'h0;
tlb0_valids_10 = 1'h0;
tlb0_valids_11 = 1'h0;
tlb0_valids_12 = 1'h0;
tlb0_valids_13 = 1'h0;
tlb0_valids_14 = 1'h0;
tlb0_valids_15 = 1'h0;
tlb0_valids_2 = 1'h0;
tlb0_valids_3 = 1'h0;
tlb0_valids_4 = 1'h0;
tlb0_valids_5 = 1'h0;
tlb0_valids_6 = 1'h0;
tlb0_valids_7 = 1'h0;
tlb0_valids_8 = 1'h0;
tlb0_valids_9 = 1'h0;
tlb1_valids_0 = 1'h0;
tlb1_valids_1 = 1'h0;
tlb1_valids_2 = 1'h0;
tlb1_valids_3 = 1'h0;
tlb1_valids_4 = 1'h0;
tlb1_valids_5 = 1'h0;
tlb1_valids_6 = 1'h0;
tlb1_valids_7 = 1'h0;
tlb2_valids_0 = 1'h0;
tlb2_valids_1 = 1'h0;
tlb2_valids_2 = 1'h0;
tlb2_valids_3 = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (EN_ma_insert && NOT_verbosity_ULE_1___d3)
begin
v__h7675 = $stime;
#0;
end
v__h7669 = v__h7675 / 32'd10;
if (EN_ma_insert && NOT_verbosity_ULE_1___d3)
$display("%0d: %m.ma_insert: asid 0x%0h vpn 0x%0h pa 0x%0h level %0d pte 0x%0h",
v__h7669,
ma_insert_asid,
ma_insert_vpn,
ma_insert_pte,
ma_insert_level,
ma_insert_pte_pa);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_flush && NOT_verbosity_ULE_1___d3)
begin
v__h6243 = $stime;
#0;
end
v__h6237 = v__h6243 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_flush && NOT_verbosity_ULE_1___d3)
$display("%0d: %m.rl_flush", v__h6237);
end
// synopsys translate_on
endmodule // mkTLB
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mpram_xor.v: Multiported-RAM based on XOR implementation //
// //
// Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) //
// Switched SRAM-based Multi-ported RAM; University of British Columbia, 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module mpram_xor
#( parameter MEMD = 16, // memory depth
parameter DATW = 32, // data width
parameter nRP = 2 , // number of reading ports
parameter nWP = 2 , // number of writing ports
parameter WAWB = 1 , // allow Write-After-Write (need to bypass feedback ram)
parameter RAWB = 1 , // new data for Read-after-Write (need to bypass output ram)
parameter RDWB = 0 , // new data for Read-During-Write
parameter FILE = "" // initialization file, optional
)( input clk , // clock
input [nWP-1:0 ] WEnb , // write enable for each writing port
input [`log2(MEMD)*nWP-1:0] WAddr, // write addresses - packed from nWP write ports
input [DATW *nWP-1:0] WData, // write data - packed from nWP read ports
input [`log2(MEMD)*nRP-1:0] RAddr, // read addresses - packed from nRP read ports
output reg [DATW *nRP-1:0] RData); // read data - packed from nRP read ports
localparam ADRW = `log2(MEMD); // address width
// Register write addresses, data and enables
reg [ADRW*nWP-1:0] WAddr_r; // registered write addresses - packed from nWP write ports
reg [DATW*nWP-1:0] WData_r; // registered write data - packed from nWP read ports
reg [ nWP-1:0] WEnb_r ; // registered write enable for each writing port
always @(posedge clk) begin
WAddr_r <= WAddr;
WData_r <= WData;
WEnb_r <= WEnb ;
end
// unpacked/pack addresses/data
reg [ADRW -1:0] WAddr2D [nWP-1:0] ; // write addresses / 2D
reg [ADRW -1:0] WAddr2D_r [nWP-1:0] ; // registered write addresses / 2D
reg [DATW -1:0] WData2D [nWP-1:0] ; // write data / 2D
reg [DATW -1:0] WData2D_r [nWP-1:0] ; // registered write data / 2D
wire [DATW* nRP -1:0] RDataOut2D [nWP-1:0] ; // read data out / 2D
reg [DATW -1:0] RDataOut3D [nWP-1:0][nRP-1:0]; // read data out / 3D
reg [ADRW*(nWP-1)-1:0] RAddrFB2D [nWP-1:0] ; // read address fb / 2D
reg [ADRW -1:0] RAddrFB3D [nWP-1:0][nWP-2:0]; // read address fb / 3D
wire [DATW*(nWP-1)-1:0] RDataFB2D [nWP-1:0] ; // read data fb / 2D
reg [DATW -1:0] RDataFB3D [nWP-1:0][nWP-2:0]; // read data fb / 3D
reg [DATW -1:0] WDataFB2D [nWP-1:0] ; // write data / 2D
reg [DATW -1:0] RData2D [nRP-1:0] ; // read data / 2D
`ARRINIT;
always @* begin
// packing/unpacking arrays into 1D/2D/3D structures; see utils.vh for definitions
`ARR1D2D(nWP, ADRW,WAddr ,WAddr2D );
`ARR1D2D(nWP, ADRW,WAddr_r ,WAddr2D_r );
`ARR1D2D(nWP, DATW,WData ,WData2D );
`ARR1D2D(nWP, DATW,WData_r ,WData2D_r );
`ARR2D1D(nRP, DATW,RData2D ,RData );
`ARR2D3D(nWP,nRP ,DATW,RDataOut2D,RDataOut3D);
`ARR3D2D(nWP,nWP-1,ADRW,RAddrFB3D ,RAddrFB2D );
`ARR2D3D(nWP,nWP-1,DATW,RDataFB2D ,RDataFB3D );
end
// generate and instantiate mulriread RAM blocks
genvar wpi;
generate
for (wpi=0 ; wpi<nWP ; wpi=wpi+1) begin: RPORTwpi
// feedback multiread ram instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATW (DATW ), // data width
.nRP (nWP-1 ), // number of reading ports
.BYPS (WAWB || RDWB || RAWB), // bypass? 0:none; 1:single-stage; 2:two-stages
.ZERO ((wpi>0)&&(FILE!="") ), // binary / Initial RAM with zeros (has priority over FILE)
.FILE (FILE )) // initialization file, optional
mrram_fdb ( .clk (clk ), // clock - in
.WEnb (WEnb_r[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D_r[wpi] ), // write address (1 port) - in : [`log2(MEMD) -1:0]
.WData (WDataFB2D[wpi] ), // write data (1 port) - in : [DATW -1:0]
.RAddr (RAddrFB2D[wpi] ), // read addresses - packed from nRP read ports - in : [`log2(MEMD)*nRP-1:0]
.RData (RDataFB2D[wpi] )); // read data - packed from nRP read ports - out: [DATW *nRP-1:0]
// output multiread ram instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATW (DATW ), // data width
.nRP (nRP ), // number of reading ports
.BYPS (RDWB ? 2 : RAWB ), // bypass? 0:none; 1:single-stage; 2:two-stages
.ZERO ((wpi>0)&&(FILE!="") ), // binary / Initial RAM with zeros (has priority over FILE)
.FILE (FILE )) // initialization file, optional
mrram_out ( .clk (clk ), // clock - in
.WEnb (WEnb_r[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D_r[wpi] ), // write address (1 port) - in : [`log2(MEMD) -1:0]
.WData (WDataFB2D[wpi] ), // write data (1 port) - in : [DATW -1:0]
.RAddr (RAddr ), // read addresses - packed from nRP read ports - in : [`log2(MEMD)*nRP-1:0]
.RData (RDataOut2D[wpi] )); // read data - packed from nRP read ports - out: [DATW *nRP-1:0]
end
endgenerate
// combinatorial logic for output and feedback functions
integer i,j,k;
always @* begin
// generate output read functions
for(i=0;i<nRP;i=i+1) begin
RData2D[i] = RDataOut3D[0][i];
for(j=1;j<nWP;j=j+1) RData2D[i] = RData2D[i] ^ RDataOut3D[j][i];
end
// generate feedback functions
for(i=0;i<nWP;i=i+1) WDataFB2D[i] = WData2D_r[i];
for(i=0;i<nWP;i=i+1) begin
k = 0;
for(j=0;j<nWP-1;j=j+1) begin
k=k+(j==i);
RAddrFB3D[i][j] = WAddr2D[k];
WDataFB2D[k] = WDataFB2D[k] ^ RDataFB3D[i][j];
k=k+1;
end
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
(* altera_attribute = "-name ALLOW_SYNCH_CTRL_USAGE ON;-name AUTO_CLOCK_ENABLE_RECOGNITION ON" *)
module ddr3_s4_uniphy_example_if0_p0_flop_mem(
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADDR_WIDTH = "";
parameter READ_DATA_WIDTH = "";
input wr_clk;
input wr_en;
input [WRITE_ADDR_WIDTH-1:0] wr_addr;
input [WRITE_DATA_WIDTH-1:0] wr_data;
input rd_reset_n;
input rd_clk;
input rd_en;
input [READ_ADDR_WIDTH-1:0] rd_addr;
output [READ_DATA_WIDTH-1:0] rd_data;
wire [WRITE_MEM_DEPTH-1:0] wr_decode;
wire [WRITE_DATA_WIDTH*WRITE_MEM_DEPTH-1:0] all_data;
wire [READ_DATA_WIDTH-1:0] mux_data_out;
// declare a memory with WRITE_MEM_DEPTH entries
// each entry contains a data size of WRITE_DATA_WIDTH
reg [WRITE_DATA_WIDTH-1:0] data_stored [0:WRITE_MEM_DEPTH-1] /* synthesis syn_preserve = 1 */;
reg [READ_DATA_WIDTH-1:0] rd_data;
always @(posedge wr_clk)
begin
if(wr_en)
data_stored[wr_addr] <= wr_data;
end
generate
genvar entry;
for (entry=0; entry < WRITE_MEM_DEPTH; entry=entry+1)
begin: mem_location
assign all_data[(WRITE_DATA_WIDTH*(entry+1)-1) : (WRITE_DATA_WIDTH*entry)] = data_stored[entry];
end
endgenerate
// mux to select the correct output data based on read address
lpm_mux uread_mux(
.sel (rd_addr),
.data (all_data),
.result (mux_data_out)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam uread_mux.lpm_size = READ_MEM_DEPTH;
defparam uread_mux.lpm_type = "LPM_MUX";
defparam uread_mux.lpm_width = READ_DATA_WIDTH;
defparam uread_mux.lpm_widths = READ_ADDR_WIDTH;
always @(posedge rd_clk)
begin
rd_data <= mux_data_out;
end
endmodule
|
// system_acl_iface_mm_interconnect_2.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.05.05.08:40:30
`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_2 (
input wire pll_outclk0_clk, // pll_outclk0.clk
input wire address_span_extender_kernel_reset_reset_bridge_in_reset_reset, // address_span_extender_kernel_reset_reset_bridge_in_reset.reset
input wire hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset, // hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset.reset
input wire [31:0] address_span_extender_kernel_expanded_master_address, // address_span_extender_kernel_expanded_master.address
output wire address_span_extender_kernel_expanded_master_waitrequest, // .waitrequest
input wire [4:0] address_span_extender_kernel_expanded_master_burstcount, // .burstcount
input wire [31:0] address_span_extender_kernel_expanded_master_byteenable, // .byteenable
input wire address_span_extender_kernel_expanded_master_read, // .read
output wire [255:0] address_span_extender_kernel_expanded_master_readdata, // .readdata
output wire address_span_extender_kernel_expanded_master_readdatavalid, // .readdatavalid
input wire address_span_extender_kernel_expanded_master_write, // .write
input wire [255:0] address_span_extender_kernel_expanded_master_writedata, // .writedata
output wire [26:0] hps_f2h_sdram0_data_address, // hps_f2h_sdram0_data.address
output wire hps_f2h_sdram0_data_write, // .write
output wire hps_f2h_sdram0_data_read, // .read
input wire [255:0] hps_f2h_sdram0_data_readdata, // .readdata
output wire [255:0] hps_f2h_sdram0_data_writedata, // .writedata
output wire [7:0] hps_f2h_sdram0_data_burstcount, // .burstcount
output wire [31:0] hps_f2h_sdram0_data_byteenable, // .byteenable
input wire hps_f2h_sdram0_data_readdatavalid, // .readdatavalid
input wire hps_f2h_sdram0_data_waitrequest // .waitrequest
);
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_waitrequest; // address_span_extender_kernel_expanded_master_agent:av_waitrequest -> address_span_extender_kernel_expanded_master_translator:uav_waitrequest
wire [9:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_burstcount; // address_span_extender_kernel_expanded_master_translator:uav_burstcount -> address_span_extender_kernel_expanded_master_agent:av_burstcount
wire [255:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_writedata; // address_span_extender_kernel_expanded_master_translator:uav_writedata -> address_span_extender_kernel_expanded_master_agent:av_writedata
wire [31:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_address; // address_span_extender_kernel_expanded_master_translator:uav_address -> address_span_extender_kernel_expanded_master_agent:av_address
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_lock; // address_span_extender_kernel_expanded_master_translator:uav_lock -> address_span_extender_kernel_expanded_master_agent:av_lock
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_write; // address_span_extender_kernel_expanded_master_translator:uav_write -> address_span_extender_kernel_expanded_master_agent:av_write
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_read; // address_span_extender_kernel_expanded_master_translator:uav_read -> address_span_extender_kernel_expanded_master_agent:av_read
wire [255:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdata; // address_span_extender_kernel_expanded_master_agent:av_readdata -> address_span_extender_kernel_expanded_master_translator:uav_readdata
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_debugaccess; // address_span_extender_kernel_expanded_master_translator:uav_debugaccess -> address_span_extender_kernel_expanded_master_agent:av_debugaccess
wire [31:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_byteenable; // address_span_extender_kernel_expanded_master_translator:uav_byteenable -> address_span_extender_kernel_expanded_master_agent:av_byteenable
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_kernel_expanded_master_agent:av_readdatavalid -> address_span_extender_kernel_expanded_master_translator:uav_readdatavalid
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> address_span_extender_kernel_expanded_master_agent:rp_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> address_span_extender_kernel_expanded_master_agent:rp_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> address_span_extender_kernel_expanded_master_agent:rp_startofpacket
wire [363:0] rsp_mux_src_data; // rsp_mux:src_data -> address_span_extender_kernel_expanded_master_agent:rp_data
wire [0:0] rsp_mux_src_channel; // rsp_mux:src_channel -> address_span_extender_kernel_expanded_master_agent:rp_channel
wire rsp_mux_src_ready; // address_span_extender_kernel_expanded_master_agent:rp_ready -> rsp_mux:src_ready
wire hps_f2h_sdram0_data_agent_m0_waitrequest; // hps_f2h_sdram0_data_translator:uav_waitrequest -> hps_f2h_sdram0_data_agent:m0_waitrequest
wire [12:0] hps_f2h_sdram0_data_agent_m0_burstcount; // hps_f2h_sdram0_data_agent:m0_burstcount -> hps_f2h_sdram0_data_translator:uav_burstcount
wire [255:0] hps_f2h_sdram0_data_agent_m0_writedata; // hps_f2h_sdram0_data_agent:m0_writedata -> hps_f2h_sdram0_data_translator:uav_writedata
wire [31:0] hps_f2h_sdram0_data_agent_m0_address; // hps_f2h_sdram0_data_agent:m0_address -> hps_f2h_sdram0_data_translator:uav_address
wire hps_f2h_sdram0_data_agent_m0_write; // hps_f2h_sdram0_data_agent:m0_write -> hps_f2h_sdram0_data_translator:uav_write
wire hps_f2h_sdram0_data_agent_m0_lock; // hps_f2h_sdram0_data_agent:m0_lock -> hps_f2h_sdram0_data_translator:uav_lock
wire hps_f2h_sdram0_data_agent_m0_read; // hps_f2h_sdram0_data_agent:m0_read -> hps_f2h_sdram0_data_translator:uav_read
wire [255:0] hps_f2h_sdram0_data_agent_m0_readdata; // hps_f2h_sdram0_data_translator:uav_readdata -> hps_f2h_sdram0_data_agent:m0_readdata
wire hps_f2h_sdram0_data_agent_m0_readdatavalid; // hps_f2h_sdram0_data_translator:uav_readdatavalid -> hps_f2h_sdram0_data_agent:m0_readdatavalid
wire hps_f2h_sdram0_data_agent_m0_debugaccess; // hps_f2h_sdram0_data_agent:m0_debugaccess -> hps_f2h_sdram0_data_translator:uav_debugaccess
wire [31:0] hps_f2h_sdram0_data_agent_m0_byteenable; // hps_f2h_sdram0_data_agent:m0_byteenable -> hps_f2h_sdram0_data_translator:uav_byteenable
wire hps_f2h_sdram0_data_agent_rf_source_endofpacket; // hps_f2h_sdram0_data_agent:rf_source_endofpacket -> hps_f2h_sdram0_data_agent_rsp_fifo:in_endofpacket
wire hps_f2h_sdram0_data_agent_rf_source_valid; // hps_f2h_sdram0_data_agent:rf_source_valid -> hps_f2h_sdram0_data_agent_rsp_fifo:in_valid
wire hps_f2h_sdram0_data_agent_rf_source_startofpacket; // hps_f2h_sdram0_data_agent:rf_source_startofpacket -> hps_f2h_sdram0_data_agent_rsp_fifo:in_startofpacket
wire [364:0] hps_f2h_sdram0_data_agent_rf_source_data; // hps_f2h_sdram0_data_agent:rf_source_data -> hps_f2h_sdram0_data_agent_rsp_fifo:in_data
wire hps_f2h_sdram0_data_agent_rf_source_ready; // hps_f2h_sdram0_data_agent_rsp_fifo:in_ready -> hps_f2h_sdram0_data_agent:rf_source_ready
wire hps_f2h_sdram0_data_agent_rsp_fifo_out_endofpacket; // hps_f2h_sdram0_data_agent_rsp_fifo:out_endofpacket -> hps_f2h_sdram0_data_agent:rf_sink_endofpacket
wire hps_f2h_sdram0_data_agent_rsp_fifo_out_valid; // hps_f2h_sdram0_data_agent_rsp_fifo:out_valid -> hps_f2h_sdram0_data_agent:rf_sink_valid
wire hps_f2h_sdram0_data_agent_rsp_fifo_out_startofpacket; // hps_f2h_sdram0_data_agent_rsp_fifo:out_startofpacket -> hps_f2h_sdram0_data_agent:rf_sink_startofpacket
wire [364:0] hps_f2h_sdram0_data_agent_rsp_fifo_out_data; // hps_f2h_sdram0_data_agent_rsp_fifo:out_data -> hps_f2h_sdram0_data_agent:rf_sink_data
wire hps_f2h_sdram0_data_agent_rsp_fifo_out_ready; // hps_f2h_sdram0_data_agent:rf_sink_ready -> hps_f2h_sdram0_data_agent_rsp_fifo:out_ready
wire hps_f2h_sdram0_data_agent_rdata_fifo_src_valid; // hps_f2h_sdram0_data_agent:rdata_fifo_src_valid -> hps_f2h_sdram0_data_agent:rdata_fifo_sink_valid
wire [257:0] hps_f2h_sdram0_data_agent_rdata_fifo_src_data; // hps_f2h_sdram0_data_agent:rdata_fifo_src_data -> hps_f2h_sdram0_data_agent:rdata_fifo_sink_data
wire hps_f2h_sdram0_data_agent_rdata_fifo_src_ready; // hps_f2h_sdram0_data_agent:rdata_fifo_sink_ready -> hps_f2h_sdram0_data_agent:rdata_fifo_src_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> hps_f2h_sdram0_data_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> hps_f2h_sdram0_data_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> hps_f2h_sdram0_data_agent:cp_startofpacket
wire [363:0] cmd_mux_src_data; // cmd_mux:src_data -> hps_f2h_sdram0_data_agent:cp_data
wire [0:0] cmd_mux_src_channel; // cmd_mux:src_channel -> hps_f2h_sdram0_data_agent:cp_channel
wire cmd_mux_src_ready; // hps_f2h_sdram0_data_agent:cp_ready -> cmd_mux:src_ready
wire address_span_extender_kernel_expanded_master_agent_cp_endofpacket; // address_span_extender_kernel_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
wire address_span_extender_kernel_expanded_master_agent_cp_valid; // address_span_extender_kernel_expanded_master_agent:cp_valid -> router:sink_valid
wire address_span_extender_kernel_expanded_master_agent_cp_startofpacket; // address_span_extender_kernel_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [363:0] address_span_extender_kernel_expanded_master_agent_cp_data; // address_span_extender_kernel_expanded_master_agent:cp_data -> router:sink_data
wire address_span_extender_kernel_expanded_master_agent_cp_ready; // router:sink_ready -> address_span_extender_kernel_expanded_master_agent:cp_ready
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire [363:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire [0:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire hps_f2h_sdram0_data_agent_rp_endofpacket; // hps_f2h_sdram0_data_agent:rp_endofpacket -> router_001:sink_endofpacket
wire hps_f2h_sdram0_data_agent_rp_valid; // hps_f2h_sdram0_data_agent:rp_valid -> router_001:sink_valid
wire hps_f2h_sdram0_data_agent_rp_startofpacket; // hps_f2h_sdram0_data_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [363:0] hps_f2h_sdram0_data_agent_rp_data; // hps_f2h_sdram0_data_agent:rp_data -> router_001:sink_data
wire hps_f2h_sdram0_data_agent_rp_ready; // router_001:sink_ready -> hps_f2h_sdram0_data_agent:rp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire [363:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire [0:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [363:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [0:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [363:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [0:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (10),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) address_span_extender_kernel_expanded_master_translator (
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_read), // .read
.uav_write (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_kernel_expanded_master_address), // avalon_anti_master_0.address
.av_waitrequest (address_span_extender_kernel_expanded_master_waitrequest), // .waitrequest
.av_burstcount (address_span_extender_kernel_expanded_master_burstcount), // .burstcount
.av_byteenable (address_span_extender_kernel_expanded_master_byteenable), // .byteenable
.av_read (address_span_extender_kernel_expanded_master_read), // .read
.av_readdata (address_span_extender_kernel_expanded_master_readdata), // .readdata
.av_readdatavalid (address_span_extender_kernel_expanded_master_readdatavalid), // .readdatavalid
.av_write (address_span_extender_kernel_expanded_master_write), // .write
.av_writedata (address_span_extender_kernel_expanded_master_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (256),
.UAV_DATA_W (256),
.AV_BURSTCOUNT_W (8),
.AV_BYTEENABLE_W (32),
.UAV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (13),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hps_f2h_sdram0_data_translator (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hps_f2h_sdram0_data_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hps_f2h_sdram0_data_agent_m0_burstcount), // .burstcount
.uav_read (hps_f2h_sdram0_data_agent_m0_read), // .read
.uav_write (hps_f2h_sdram0_data_agent_m0_write), // .write
.uav_waitrequest (hps_f2h_sdram0_data_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hps_f2h_sdram0_data_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hps_f2h_sdram0_data_agent_m0_byteenable), // .byteenable
.uav_readdata (hps_f2h_sdram0_data_agent_m0_readdata), // .readdata
.uav_writedata (hps_f2h_sdram0_data_agent_m0_writedata), // .writedata
.uav_lock (hps_f2h_sdram0_data_agent_m0_lock), // .lock
.uav_debugaccess (hps_f2h_sdram0_data_agent_m0_debugaccess), // .debugaccess
.av_address (hps_f2h_sdram0_data_address), // avalon_anti_slave_0.address
.av_write (hps_f2h_sdram0_data_write), // .write
.av_read (hps_f2h_sdram0_data_read), // .read
.av_readdata (hps_f2h_sdram0_data_readdata), // .readdata
.av_writedata (hps_f2h_sdram0_data_writedata), // .writedata
.av_burstcount (hps_f2h_sdram0_data_burstcount), // .burstcount
.av_byteenable (hps_f2h_sdram0_data_byteenable), // .byteenable
.av_readdatavalid (hps_f2h_sdram0_data_readdatavalid), // .readdatavalid
.av_waitrequest (hps_f2h_sdram0_data_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (354),
.PKT_PROTECTION_L (352),
.PKT_BEGIN_BURST (347),
.PKT_BURSTWRAP_H (339),
.PKT_BURSTWRAP_L (339),
.PKT_BURST_SIZE_H (342),
.PKT_BURST_SIZE_L (340),
.PKT_BURST_TYPE_H (344),
.PKT_BURST_TYPE_L (343),
.PKT_BYTE_CNT_H (338),
.PKT_BYTE_CNT_L (326),
.PKT_ADDR_H (319),
.PKT_ADDR_L (288),
.PKT_TRANS_COMPRESSED_READ (320),
.PKT_TRANS_POSTED (321),
.PKT_TRANS_WRITE (322),
.PKT_TRANS_READ (323),
.PKT_TRANS_LOCK (324),
.PKT_TRANS_EXCLUSIVE (325),
.PKT_DATA_H (255),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (287),
.PKT_BYTEEN_L (256),
.PKT_SRC_ID_H (349),
.PKT_SRC_ID_L (349),
.PKT_DEST_ID_H (350),
.PKT_DEST_ID_L (350),
.PKT_THREAD_ID_H (351),
.PKT_THREAD_ID_L (351),
.PKT_CACHE_H (358),
.PKT_CACHE_L (355),
.PKT_DATA_SIDEBAND_H (346),
.PKT_DATA_SIDEBAND_L (346),
.PKT_QOS_H (348),
.PKT_QOS_L (348),
.PKT_ADDR_SIDEBAND_H (345),
.PKT_ADDR_SIDEBAND_L (345),
.PKT_RESPONSE_STATUS_H (360),
.PKT_RESPONSE_STATUS_L (359),
.PKT_ORI_BURST_SIZE_L (361),
.PKT_ORI_BURST_SIZE_H (363),
.ST_DATA_W (364),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (10),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_kernel_expanded_master_agent (
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_address), // av.address
.av_write (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_write), // .write
.av_read (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (address_span_extender_kernel_expanded_master_agent_cp_valid), // cp.valid
.cp_data (address_span_extender_kernel_expanded_master_agent_cp_data), // .data
.cp_startofpacket (address_span_extender_kernel_expanded_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_kernel_expanded_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (address_span_extender_kernel_expanded_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (255),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (347),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (287),
.PKT_BYTEEN_L (256),
.PKT_ADDR_H (319),
.PKT_ADDR_L (288),
.PKT_TRANS_COMPRESSED_READ (320),
.PKT_TRANS_POSTED (321),
.PKT_TRANS_WRITE (322),
.PKT_TRANS_READ (323),
.PKT_TRANS_LOCK (324),
.PKT_SRC_ID_H (349),
.PKT_SRC_ID_L (349),
.PKT_DEST_ID_H (350),
.PKT_DEST_ID_L (350),
.PKT_BURSTWRAP_H (339),
.PKT_BURSTWRAP_L (339),
.PKT_BYTE_CNT_H (338),
.PKT_BYTE_CNT_L (326),
.PKT_PROTECTION_H (354),
.PKT_PROTECTION_L (352),
.PKT_RESPONSE_STATUS_H (360),
.PKT_RESPONSE_STATUS_L (359),
.PKT_BURST_SIZE_H (342),
.PKT_BURST_SIZE_L (340),
.PKT_ORI_BURST_SIZE_L (361),
.PKT_ORI_BURST_SIZE_H (363),
.ST_CHANNEL_W (1),
.ST_DATA_W (364),
.AVS_BURSTCOUNT_W (13),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hps_f2h_sdram0_data_agent (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hps_f2h_sdram0_data_agent_m0_address), // m0.address
.m0_burstcount (hps_f2h_sdram0_data_agent_m0_burstcount), // .burstcount
.m0_byteenable (hps_f2h_sdram0_data_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hps_f2h_sdram0_data_agent_m0_debugaccess), // .debugaccess
.m0_lock (hps_f2h_sdram0_data_agent_m0_lock), // .lock
.m0_readdata (hps_f2h_sdram0_data_agent_m0_readdata), // .readdata
.m0_readdatavalid (hps_f2h_sdram0_data_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hps_f2h_sdram0_data_agent_m0_read), // .read
.m0_waitrequest (hps_f2h_sdram0_data_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hps_f2h_sdram0_data_agent_m0_writedata), // .writedata
.m0_write (hps_f2h_sdram0_data_agent_m0_write), // .write
.rp_endofpacket (hps_f2h_sdram0_data_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hps_f2h_sdram0_data_agent_rp_ready), // .ready
.rp_valid (hps_f2h_sdram0_data_agent_rp_valid), // .valid
.rp_data (hps_f2h_sdram0_data_agent_rp_data), // .data
.rp_startofpacket (hps_f2h_sdram0_data_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (hps_f2h_sdram0_data_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hps_f2h_sdram0_data_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hps_f2h_sdram0_data_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hps_f2h_sdram0_data_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hps_f2h_sdram0_data_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hps_f2h_sdram0_data_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hps_f2h_sdram0_data_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hps_f2h_sdram0_data_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hps_f2h_sdram0_data_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hps_f2h_sdram0_data_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hps_f2h_sdram0_data_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hps_f2h_sdram0_data_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hps_f2h_sdram0_data_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hps_f2h_sdram0_data_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (365),
.FIFO_DEPTH (15),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hps_f2h_sdram0_data_agent_rsp_fifo (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hps_f2h_sdram0_data_agent_rf_source_data), // in.data
.in_valid (hps_f2h_sdram0_data_agent_rf_source_valid), // .valid
.in_ready (hps_f2h_sdram0_data_agent_rf_source_ready), // .ready
.in_startofpacket (hps_f2h_sdram0_data_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hps_f2h_sdram0_data_agent_rf_source_endofpacket), // .endofpacket
.out_data (hps_f2h_sdram0_data_agent_rsp_fifo_out_data), // out.data
.out_valid (hps_f2h_sdram0_data_agent_rsp_fifo_out_valid), // .valid
.out_ready (hps_f2h_sdram0_data_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_mm_interconnect_2_router router (
.sink_ready (address_span_extender_kernel_expanded_master_agent_cp_ready), // sink.ready
.sink_valid (address_span_extender_kernel_expanded_master_agent_cp_valid), // .valid
.sink_data (address_span_extender_kernel_expanded_master_agent_cp_data), // .data
.sink_startofpacket (address_span_extender_kernel_expanded_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_kernel_expanded_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_router_001 router_001 (
.sink_ready (hps_f2h_sdram0_data_agent_rp_ready), // sink.ready
.sink_valid (hps_f2h_sdram0_data_agent_rp_valid), // .valid
.sink_data (hps_f2h_sdram0_data_agent_rp_data), // .data
.sink_startofpacket (hps_f2h_sdram0_data_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_f2h_sdram0_data_agent_rp_endofpacket), // .endofpacket
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_cmd_demux cmd_demux (
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_cmd_mux cmd_mux (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_cmd_demux rsp_demux (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_rsp_mux rsp_mux (
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_slvram_v7.v
// Version : v1.0
// Description: RAM instantiation.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_slvram_v7 #(
parameter C_FAMILY = "virtex7" ,
parameter C_DATAWIDTH = 64 ,
parameter C_SIZE = 1024 ,
parameter C_ADDR_WIDTH= 10 ,
parameter C_INITRAM_F = "NONE"
) (
input clk_a ,
input [C_DATAWIDTH/8-1:0] we_a ,
input [C_ADDR_WIDTH-1:0] addr_a ,
input [C_DATAWIDTH-1:0] wr_data_a,
output [C_DATAWIDTH-1:0] rd_data_a,
input clk_b ,
input [C_DATAWIDTH/8-1:0] we_b ,
input [C_ADDR_WIDTH-1:0] addr_b ,
input [C_DATAWIDTH-1:0] wr_data_b,
output [C_DATAWIDTH-1:0] rd_data_b
);
//generate
//if(C_DATAWIDTH == 32) begin: ram32b
axi_traffic_gen_v2_0_inferram #(
.C_FAMILY (C_FAMILY ),
.C_RAMINIT_F(C_INITRAM_F ),
.SIZE (C_SIZE ),
.ADDR_WIDTH (C_ADDR_WIDTH ),
.NB_COL (C_DATAWIDTH/8),
.COL_WIDTH (8 ),
.INFER_TYPE (1 )
) ram0 (
.clk(clk_a),
.wea(we_a),
.web(we_b),
.addra(addr_a),
.addrb(addr_b),
.dia(wr_data_a),
.dib(wr_data_b),
.doa(rd_data_a),
.dob(rd_data_b)
);
//end // block: ram32b
//endgenerate
//generate
//if(C_DATAWIDTH == 64) begin: ram64b
//axi_traffic_gen_v2_0_inferram #(
// .C_FAMILY (C_FAMILY ),
// .C_RAMINIT_F(C_INITRAM_F),
// .NB_COL (8 ),
// .COL_WIDTH (8 ),
// .INFER_TYPE (1 )
// )
// ram0 (
// .clk(clk_a),
// .wea(we_a),
// .web(we_b),
// .addra(addr_a),
// .addrb(addr_b),
// .dia(wr_data_a),
// .dib(wr_data_b),
// .doa(rd_data_a),
// .dob(rd_data_b)
// );
//
//end // block: ram64b
//endgenerate
/*
generate
if(C_DATAWIDTH == 32) begin: ram32b
RAMB36 #(
`RAMB_INIT0
.INIT_FILE (C_INITRAM_F ),
.SIM_COLLISION_CHECK("NONE"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.READ_WIDTH_A (36 ),
.READ_WIDTH_B (36 ),
.WRITE_WIDTH_A(36 ),
.WRITE_WIDTH_B(36 ),
.INIT_A (36'h000000000),
.INIT_B (36'h000000000),
.SRVAL_A ('h0 ),
.SRVAL_B ('h0 )
)
ramb36i (
.CLKA (clk_a ),
.ADDRA ({1'b0,addr_a,5'h0}),
.ENA (1'b1 ),
.REGCEA(1'b0 ),
.WEA (we_a[3:0] ),
.SSRA (1'b0 ),
.DOA (rd_data_a[31:0] ),
.DIA (wr_data_a[31:0] ),
.DIPA (4'b0 ),
.CLKB (clk_b ),
.ADDRB ({1'b0,addr_b,5'h0}),
.ENB (1'b1 ),
.REGCEB(1'b0 ),
.WEB (we_b[3:0] ),
.SSRB (1'b0 ),
.DOB (rd_data_b[31:0] ),
.DIB (wr_data_b[31:0] ),
.DIPB (4'b0 )
);
end // block: ram32b
endgenerate
generate
if(C_DATAWIDTH == 64) begin: ram64b
RAMB36 #(
`RAMB_INIT0
.INIT_FILE (C_INITRAM_F ),
.SIM_COLLISION_CHECK("NONE"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.READ_WIDTH_A (36 ),
.READ_WIDTH_B (36 ),
.WRITE_WIDTH_A(36 ),
.WRITE_WIDTH_B(36 ),
.INIT_A (36'h000000000),
.INIT_B (36'h000000000),
.SRVAL_A ('h0 ),
.SRVAL_B ('h0 )
)
ramb36i (
.CLKA (clk_a ),
.ADDRA ({1'b0,addr_a,5'h0}),
.ENA (1'b1 ),
.REGCEA(1'b0 ),
.WEA (we_a[3:0] ),
.SSRA (1'b0 ),
.DOA (rd_data_a[31:0] ),
.DIA (wr_data_a[31:0] ),
.DIPA (4'b0 ),
.CLKB (clk_b ),
.ADDRB ({1'b0,addr_b,5'h0}),
.ENB (1'b1 ),
.REGCEB(1'b0 ),
.WEB (we_b[3:0] ),
.SSRB (1'b0 ),
.DOB (rd_data_b[31:0] ),
.DIB (wr_data_b[31:0] ),
.DIPB (4'b0 )
);
RAMB36 #(
`RAMB_INIT0
.INIT_FILE (C_INITRAM_F ),
.SIM_COLLISION_CHECK("NONE"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.READ_WIDTH_A (36 ),
.READ_WIDTH_B (36 ),
.WRITE_WIDTH_A(36 ),
.WRITE_WIDTH_B(36 ),
.INIT_A (36'h000000000),
.INIT_B (36'h000000000),
.SRVAL_A ('h0 ),
.SRVAL_B ('h0 )
)
ramb36ii (
.CLKA (clk_a ),
.ADDRA ({1'b0, addr_a,5'h0}),
.ENA (1'b1 ),
.REGCEA(1'b0 ),
.WEA (we_a[7:4] ),
.SSRA (1'b0 ),
.DOA (rd_data_a[63:32] ),
.DIA (wr_data_a[63:32] ),
.DIPA (4'b0 ),
.CLKB (clk_b ),
.ADDRB ({1'b0,addr_b,5'h0} ),
.ENB (1'b1 ),
.REGCEB(1'b0 ),
.WEB (we_b[7:4] ),
.SSRB (1'b0 ),
.DOB (rd_data_b[63:32] ),
.DIB (wr_data_b[63:32] ),
.DIPB (4'b0 )
);
end // block: ram64b
endgenerate
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBN_TB_V
`define SKY130_FD_SC_HS__DFBBN_TB_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfbbn.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 RESET_B = 1'b1;
#160 SET_B = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 RESET_B = 1'b0;
#260 SET_B = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SET_B = 1'b1;
#380 RESET_B = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SET_B = 1'bx;
#480 RESET_B = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hs__dfbbn dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBN_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_MUX_4TO2_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_MUX_4TO2_BLACKBOX_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_mux_4to2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_MUX_4TO2_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_1_V
`define SKY130_FD_SC_HVL__DFRTP_1_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_1_V
|
module wb_stream_reader_tb;
localparam FIFO_AW = 5;
localparam MAX_BURST_LEN = 32;
localparam WB_AW = 32;
localparam WB_DW = 32;
localparam WSB = WB_DW/8; //Word size in bytes
localparam MEM_SIZE = 128*WSB; //Memory size in bytes
localparam MAX_BUF_SIZE = 32*WSB; //Buffer size in bytes
localparam BURST_SIZE = 8;
//Configuration registers
localparam REG_CSR = 0*WSB;
localparam REG_START_ADDR = 1*WSB;
localparam REG_BUF_SIZE = 2*WSB;
localparam REG_BURST_SIZE = 3*WSB;
reg clk = 1'b1;
reg rst = 1'b1;
always#10 clk <= ~clk;
initial #100 rst <= 0;
vlog_tb_utils vlog_tb_utils0();
vlog_functions utils();
vlog_tap_generator #("wb_stream_reader_tb.tap", 1) tap();
//Wishbone memory interface
wire [WB_AW-1:0] wb_m2s_data_adr;
wire [WB_DW-1:0] wb_m2s_data_dat;
wire [WB_DW/8-1:0] wb_m2s_data_sel;
wire wb_m2s_data_we;
wire wb_m2s_data_cyc;
wire wb_m2s_data_stb;
wire [2:0] wb_m2s_data_cti;
wire [1:0] wb_m2s_data_bte;
wire [WB_DW-1:0] wb_s2m_data_dat;
wire wb_s2m_data_ack;
wire wb_s2m_data_err;
//Wishbone configuration interface
wire [WB_AW-1:0] wb_m2s_cfg_adr;
wire [WB_DW-1:0] wb_m2s_cfg_dat;
wire [WB_DW/8-1:0] wb_m2s_cfg_sel;
wire wb_m2s_cfg_we;
wire wb_m2s_cfg_cyc;
wire wb_m2s_cfg_stb;
wire [2:0] wb_m2s_cfg_cti;
wire [1:0] wb_m2s_cfg_bte;
wire [WB_DW-1:0] wb_s2m_cfg_dat;
wire wb_s2m_cfg_ack;
wire wb_s2m_cfg_err;
//Stream interface
wire [WB_DW-1:0] stream_data;
wire stream_valid;
wire stream_ready;
wire irq;
wb_stream_reader
#(.FIFO_AW (FIFO_AW),
.MAX_BURST_LEN (MAX_BURST_LEN))
dut
(.clk (clk),
.rst (rst),
//Stream data output
.wbm_adr_o (wb_m2s_data_adr),
.wbm_dat_o (wb_m2s_data_dat),
.wbm_sel_o (wb_m2s_data_sel),
.wbm_we_o (wb_m2s_data_we),
.wbm_cyc_o (wb_m2s_data_cyc),
.wbm_stb_o (wb_m2s_data_stb),
.wbm_cti_o (wb_m2s_data_cti),
.wbm_bte_o (wb_m2s_data_bte),
.wbm_dat_i (wb_s2m_data_dat),
.wbm_ack_i (wb_s2m_data_ack),
.wbm_err_i (wb_s2m_data_err),
//FIFO interface
.stream_s_data_i (stream_data),
.stream_s_valid_i (stream_valid),
.stream_s_ready_o (stream_ready),
.irq_o (irq),
//Control Interface
.wbs_adr_i (wb_m2s_cfg_adr[4:0]),
.wbs_dat_i (wb_m2s_cfg_dat),
.wbs_sel_i (wb_m2s_cfg_sel),
.wbs_we_i (wb_m2s_cfg_we),
.wbs_cyc_i (wb_m2s_cfg_cyc),
.wbs_stb_i (wb_m2s_cfg_stb),
.wbs_cti_i (wb_m2s_cfg_cti),
.wbs_bte_i (wb_m2s_cfg_bte),
.wbs_dat_o (wb_s2m_cfg_dat),
.wbs_ack_o (wb_s2m_cfg_ack),
.wbs_err_o (wb_s2m_cfg_err));
stream_writer
#(.WIDTH (WB_DW),
.MAX_BLOCK_SIZE (MAX_BUF_SIZE/WSB))
writer
(.clk (clk),
.stream_m_data_o (stream_data),
.stream_m_valid_o (stream_valid),
.stream_m_ready_i (stream_ready));
wb_bfm_memory
#(.mem_size_bytes(MEM_SIZE),
.rd_min_delay (0),
.rd_max_delay (5))
wb_ram0
(//Wishbone Master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i (wb_m2s_data_adr),
.wb_dat_i (wb_m2s_data_dat),
.wb_sel_i (wb_m2s_data_sel),
.wb_we_i (wb_m2s_data_we),
.wb_cyc_i (wb_m2s_data_cyc),
.wb_stb_i (wb_m2s_data_stb),
.wb_cti_i (wb_m2s_data_cti),
.wb_bte_i (wb_m2s_data_bte),
.wb_dat_o (wb_s2m_data_dat),
.wb_ack_o (wb_s2m_data_ack),
.wb_err_o (wb_s2m_data_err));
wb_bfm_master
#(.MAX_BURST_LEN (2))
wb_cfg
(.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_o (wb_m2s_cfg_adr),
.wb_dat_o (wb_m2s_cfg_dat),
.wb_sel_o (wb_m2s_cfg_sel),
.wb_we_o (wb_m2s_cfg_we),
.wb_cyc_o (wb_m2s_cfg_cyc),
.wb_stb_o (wb_m2s_cfg_stb),
.wb_cti_o (wb_m2s_cfg_cti),
.wb_bte_o (wb_m2s_cfg_bte),
.wb_dat_i (wb_s2m_cfg_dat),
.wb_ack_i (wb_s2m_cfg_ack),
.wb_err_i (wb_s2m_cfg_err),
.wb_rty_i (1'b0));
integer transaction;
integer TRANSACTIONS;
reg VERBOSE = 0;
initial begin
if(!$value$plusargs("transactions=%d", TRANSACTIONS))
TRANSACTIONS = 1000;
if($test$plusargs("verbose"))
VERBOSE = 1;
@(negedge rst);
@(posedge clk);
//FIXME: Implement wb slave config IF
writer.rate = 0.1;
for(transaction=1;transaction<=TRANSACTIONS;transaction=transaction+1) begin
test_main();
utils.progress_bar("Completed transaction", transaction, TRANSACTIONS);
end
tap.ok("All done");
$finish;
end // initial begin
reg [WB_DW-1:0] stimuli [0:MAX_BUF_SIZE/WSB-1];
task test_main;
integer start_adr;
integer buf_size;
integer burst_len;
integer idx;
integer tmp;
integer seed;
reg [WB_DW*8*WSB-1:0] data_block;
begin
//FIXME: Burst length must be > 1
burst_len = $dist_uniform(seed, 2, MAX_BURST_LEN/WSB);
//FIXME: buf_size currently needs to be a multiple of burst_size
//buf_size = $dist_uniform(seed,1,MAX_BUF_SIZE/WSB)*WSB;
buf_size = burst_len*WSB*$dist_uniform(seed, 1, MAX_BUF_SIZE/(burst_len*WSB));
start_adr = $dist_uniform(seed,0,(MEM_SIZE-buf_size)/WSB)*WSB;
//Generate stimuli
for(idx=0 ; idx<buf_size/WSB ; idx=idx+1) begin
tmp = $random(seed);
stimuli[idx] = tmp[WB_DW-1:0];
end
cfg_write(REG_START_ADDR, start_adr); //Set start address
cfg_write(REG_BUF_SIZE , buf_size);//Set buffer size
cfg_write(REG_BURST_SIZE, burst_len);//Set burst length
cfg_write(REG_CSR, 1); //Start DMA
//Start transmit and receive transactors
fifo_write(buf_size/WSB);
@(posedge irq);
verify(start_adr, buf_size);
cfg_write(REG_CSR, 2); //Clear IRQ
end
endtask
task cfg_write;
input [WB_AW-1:0] addr_i;
input [WB_DW-1:0] data_i;
reg err;
begin
wb_cfg.write(addr_i, data_i, 4'hf, err);
if(err) begin
$display("Error writing to config interface address 0x%8x", addr_i);
$finish;
end
end
endtask
task fifo_write;
input integer len;
integer idx;
begin
for(idx=0;idx < len ; idx=idx+1) begin
writer.write_word(stimuli[idx]);
end
end
endtask
task verify;
input integer start_adr;
input integer buf_size;
integer idx;
reg [WB_DW-1:0] expected;
reg [WB_DW-1:0] received;
reg err;
begin
for(idx = 0; idx < buf_size/WSB ; idx = idx + 1) begin
expected = stimuli[idx];
received = wb_ram0.mem[start_adr/WSB+idx];
if(received !== expected) begin
$display("%m : Verify failed at address 0x%8x. Expected 0x%8x : Got 0x%8x",
start_adr+idx*WSB,
expected,
received);
$finish;
end
end
end
endtask
endmodule
|
// Generated by DDR3 High Performance Controller 10.0 [Altera, IP Toolbench 1.3.0 Build 262]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2011 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module ddr3_int (
local_address,
local_write_req,
local_read_req,
local_burstbegin,
local_wdata,
local_be,
local_size,
global_reset_n,
pll_ref_clk,
soft_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
reset_request_n,
mem_odt,
mem_cs_n,
mem_cke,
mem_addr,
mem_ba,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dm,
local_refresh_ack,
local_wdata_req,
local_init_done,
reset_phy_clk_n,
mem_reset_n,
dll_reference_clk,
dqs_delay_ctrl_export,
phy_clk,
aux_full_rate_clk,
aux_half_rate_clk,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqsn);
input [24:0] local_address;
input local_write_req;
input local_read_req;
input local_burstbegin;
input [127:0] local_wdata;
input [15:0] local_be;
input [6:0] local_size;
input global_reset_n;
input pll_ref_clk;
input soft_reset_n;
output local_ready;
output [127:0] local_rdata;
output local_rdata_valid;
output reset_request_n;
output [0:0] mem_odt;
output [0:0] mem_cs_n;
output [0:0] mem_cke;
output [13:0] mem_addr;
output [2:0] mem_ba;
output mem_ras_n;
output mem_cas_n;
output mem_we_n;
output [3:0] mem_dm;
output local_refresh_ack;
output local_wdata_req;
output local_init_done;
output reset_phy_clk_n;
output mem_reset_n;
output dll_reference_clk;
output [5:0] dqs_delay_ctrl_export;
output phy_clk;
output aux_full_rate_clk;
output aux_half_rate_clk;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [31:0] mem_dq;
inout [3:0] mem_dqs;
inout [3:0] mem_dqsn;
endmodule
|
//#############################################################################
//# Function: Clock mux #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockmux #(parameter N = 1) // number of clock inputs
(
input [N-1:0] en, // one hot enable vector (needs to be stable!)
input [N-1:0] clkin,// one hot clock inputs (only one is active!)
output clkout
);
`ifdef CFG_ASIC
generate
if((N==2))
begin : asic
asic_clockmux2 imux (.clkin(clkin[N-1:0]),
.en(en[N-1:0]),
.clkout(clkout));
end
else if((N==4))
begin : asic
asic_clockmux4 imux (.clkin(clkin[N-1:0]),
.en(en[N-1:0]),
.clkout(clkout));
end
endgenerate
`else // !`ifdef CFG_ASIC
assign clkout = |(clkin[N-1:0] & en[N-1:0]);
`endif
endmodule // oh_clockmux
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpciexpav_lite_app
#(
parameter CB_P2A_AVALON_ADDR_B0 = 32'h00000000,
parameter CB_P2A_AVALON_ADDR_B1 = 32'h00000000,
parameter CB_P2A_AVALON_ADDR_B2 = 32'h00000000,
parameter CB_P2A_AVALON_ADDR_B3 = 32'h00000000,
parameter CB_P2A_AVALON_ADDR_B4 = 32'h00000000,
parameter CB_P2A_AVALON_ADDR_B5 = 32'h00000000,
parameter CB_P2A_AVALON_ADDR_B6 = 32'h00000000,
parameter bar0_64bit_mem_space = "true",
parameter bar0_io_space = "false",
parameter bar0_prefetchable = "true",
parameter bar0_size_mask = 32 ,
parameter bar1_64bit_mem_space = "false",
parameter bar1_io_space = "false",
parameter bar1_prefetchable = "false",
parameter bar1_size_mask = 4 ,
parameter bar2_64bit_mem_space = "false",
parameter bar2_io_space = "false",
parameter bar2_prefetchable = "false",
parameter bar2_size_mask = 4 ,
parameter bar3_64bit_mem_space = "false",
parameter bar3_io_space = "false",
parameter bar3_prefetchable = "false",
parameter bar3_size_mask = 4 ,
parameter bar4_64bit_mem_space = "false",
parameter bar4_io_space = "false",
parameter bar4_prefetchable = "false",
parameter bar4_size_mask = 4 ,
parameter bar5_64bit_mem_space = "false",
parameter bar5_io_space = "false",
parameter bar5_prefetchable = "false",
parameter bar5_size_mask = 4 ,
parameter bar_io_window_size = "NONE",
parameter bar_prefetchable = 0 ,
parameter expansion_base_address_register = 0,
parameter CB_RXM_DATA_WIDTH = 32,
parameter CG_RXM_IRQ_NUM = 16 ,
parameter deviceFamily = "Arria V"
)
(
// clock, reset inputs
input Clk_i,
input Rstn_i,
// Rx streamming interface to the HIP
input RxStEmpty_i,
output RxStMask_o,
input RxStSop_i,
input RxStEop_i,
input [63:0] RxStData_i,
input RxStValid_i,
output RxStReady_o,
input [7:0] RxStBarDec_i,
// Tx streaming interface to the HIP
input TxStReady_i,
output TxStSop_o,
output TxStEop_o,
output [63:0] TxStData_o,
output TxStValid_o,
// AvalonMM Rx Master port (32-bit)
// Avalon Rx Master interface
output RxmWrite_0_o,
output [31:0] RxmAddress_0_o,
output [CB_RXM_DATA_WIDTH-1:0] RxmWriteData_0_o,
output [3:0] RxmByteEnable_0_o,
input RxmWaitRequest_0_i,
output RxmRead_0_o,
input [CB_RXM_DATA_WIDTH-1:0] RxmReadData_0_i, // this comes from Avalon Slave to be routed to Tx completion
input RxmReadDataValid_0_i, // this comes from Avalon Slave to be routed to Tx completion
output RxmWrite_1_o,
output [31:0] RxmAddress_1_o,
output [CB_RXM_DATA_WIDTH-1:0] RxmWriteData_1_o,
output [3:0] RxmByteEnable_1_o,
input RxmWaitRequest_1_i,
output RxmRead_1_o,
input [CB_RXM_DATA_WIDTH-1:0] RxmReadData_1_i, // this comes from Avalon Slave to be routed to Tx completion
input RxmReadDataValid_1_i, // this comes from Avalon Slave to be routed to Tx completion
output RxmWrite_2_o,
output [31:0] RxmAddress_2_o,
output [CB_RXM_DATA_WIDTH-1:0] RxmWriteData_2_o,
output [3:0] RxmByteEnable_2_o,
input RxmWaitRequest_2_i,
output RxmRead_2_o,
input [CB_RXM_DATA_WIDTH-1:0] RxmReadData_2_i, // this comes from Avalon Slave to be routed to Tx completion
input RxmReadDataValid_2_i, // this comes from Avalon Slave to be routed to Tx completion
output RxmWrite_3_o,
output [31:0] RxmAddress_3_o,
output [CB_RXM_DATA_WIDTH-1:0] RxmWriteData_3_o,
output [3:0] RxmByteEnable_3_o,
input RxmWaitRequest_3_i,
output RxmRead_3_o,
input [CB_RXM_DATA_WIDTH-1:0] RxmReadData_3_i, // this comes from Avalon Slave to be routed to Tx completion
input RxmReadDataValid_3_i, // this comes from Avalon Slave to be routed to Tx completion
output RxmWrite_4_o,
output [31:0] RxmAddress_4_o,
output [CB_RXM_DATA_WIDTH-1:0] RxmWriteData_4_o,
output [3:0] RxmByteEnable_4_o,
input RxmWaitRequest_4_i,
output RxmRead_4_o,
input [CB_RXM_DATA_WIDTH-1:0] RxmReadData_4_i, // this comes from Avalon Slave to be routed to Tx completion
input RxmReadDataValid_4_i, // this comes from Avalon Slave to be routed to Tx completion
output RxmWrite_5_o,
output [31:0] RxmAddress_5_o,
output [CB_RXM_DATA_WIDTH-1:0] RxmWriteData_5_o,
output [3:0] RxmByteEnable_5_o,
input RxmWaitRequest_5_i,
output RxmRead_5_o,
input [CB_RXM_DATA_WIDTH-1:0] RxmReadData_5_i, // this comes from Avalon Slave to be routed to Tx completion
input RxmReadDataValid_5_i, // this comes from Avalon Slave to be routed to Tx completion
input [CG_RXM_IRQ_NUM-1 : 0] RxmIrq_i,
// Config interface
input CfgCtlWr_i,
input [3:0] CfgAddr_i,
input [31:0] CfgCtl_i,
// Interrupt signals
output AppIntSts_o,
output reg MsiReq_o,
input MsiAck_i,
output [2:0] MsiTc_o,
output [4:0] MsiNum_o
);
//state machine encoding
localparam RX_IDLE = 12'h000;
localparam RX_RD_HEADER1 = 12'h003;
localparam RX_LATCH_HEADER1 = 12'h005;
localparam RX_RD_HEADER2 = 12'h009;
localparam RX_LATCH_HEADER2 = 12'h011;
localparam RX_CHECK_HEADER = 12'h021;
localparam RX_RD_DATA = 12'h041;
localparam RX_LATCH_DATA = 12'h081;
localparam RX_PENDING = 12'h101;
localparam RX_CPL_REQ = 12'h201;
localparam RX_CLEAR_BUF = 12'h401;
localparam RX_WAIT_EOP = 12'h801;
localparam RXAVL_IDLE = 4'h0;
localparam RXAVL_WRITE = 4'h3;
localparam RXAVL_READ = 4'h5;
localparam RXAVL_WRITE_DONE = 4'h9;
localparam TX_IDLE = 4'h0;
localparam TX_SOP = 4'h3;
localparam TX_CPL_HDR2 = 4'h5;
localparam TX_EOP = 4'h9;
wire is_read;
wire is_write;
wire is_flush;
wire is_msg;
wire is_msg_wd;
wire is_msg_wod;
wire [3:0] rx_fbe;
wire [3:0] rx_lbe;
wire [9:0] rx_dwlen;
wire rx_3dw_header;
wire [31:0] rx_addr;
wire is_valid_read;
wire is_write_32;
wire addr_bit2;
wire is_valid_write;
wire is_flush_wr32;
wire is_flush_wr64;
wire rx_check_header;
reg [63:0] rx_header1_reg;
reg [63:0] rx_header2_reg;
reg [7:0] rx_bar_hit_reg;
reg [31:0] rx_writedata_reg;
reg [11:0] rx_state;
reg [11:0] rx_nxt_state;
reg rx_pending_reg;
reg [3:0] rxavl_state;
reg [3:0] rxavl_nxt_state;
reg [12:0] cfg_busdev;
reg msi_ena;
reg [31:0] read_data_reg;
reg [11:0] normal_byte_count;
reg [11:0] abort_byte_count;
reg [6:0] lower_addr;
wire [63:0] tx_st_header1;
wire [63:0] tx_st_header2;
wire [63:0] tx_st_data;
reg cpl_data_available;
reg [3:0] tx_state;
reg [3:0] tx_nxt_state;
wire [127:0] cpl_header;
reg irq_reg;
wire irq_edge;
wire [2:0] cpl_tc;
wire [1:0] cpl_attr;
wire [9:0] dw_len;
wire [11:0] remain_bytes;
wire [15:0] cpl_req_id;
wire [7:0] cpl_tag;
wire latch_rx_header1;
wire latch_rx_header2;
reg latch_rx_header2_reg;
wire rx_get_header1;
wire adjusted_amount_data_dw;
wire adjusted_amount_dec_dw;
wire adjusted_amount_inc_dw;
reg [10:0] adjusted_data_dw_reg;
wire [9:0] adjusted_data_qw;
reg [9:0] rx_qword_counter;
wire addr_bit2_reg;
wire rx_idle;
wire rx_get_write_data;
wire rx_latch_write_data;
wire rx_pndg;
wire tx_cpl_req;
wire clear_rxbuff;
wire rxavl_req;
wire tx_idle_st;
wire [31:0] pcie_addr;
wire [227:0] k_bar;
reg [227:0] init_k_bar;
reg [3:0] header_poll_counter;
wire [11:0] rx_byte_len;
wire rx_get_header2;
wire rxm_wait_request;
wire [31:0] avl_addr;
reg [31:0] avl_addr_reg;
wire wrena;
wire rdena;
wire rxm_read_data_valid;
reg [31:0] rxm_read_data;
wire [5:0] read_valid_vector;
wire rxm_read_data_valid_0;
wire rxm_wait_request_0;
wire [31:0] rxm_read_data_0;
wire rxm_read_data_valid_1;
wire rxm_wait_request_1;
wire [31:0] rxm_read_data_1;
wire rxm_read_data_valid_2;
wire rxm_wait_request_2;
wire [31:0] rxm_read_data_2;
wire rxm_read_data_valid_3;
wire rxm_wait_request_3;
wire [31:0] rxm_read_data_3;
wire rxm_read_data_valid_4;
wire rxm_wait_request_4;
wire [31:0] rxm_read_data_4;
wire rxm_read_data_valid_5;
wire rxm_wait_request_5;
wire [31:0] rxm_read_data_5;
reg rx_eop_reg;
// decode the Rx header to extract various information to support the state machine
assign is_read = ~rx_header1_reg[30] & (rx_header1_reg[28:26]== 3'b000) & ~rx_header1_reg[24];
assign is_write = rx_header1_reg[30] & (rx_header1_reg[28:24]==5'b00000);
assign is_msg = rx_header1_reg[29:27] == 3'b110;
assign is_msg_wd = rx_header1_reg[30] & is_msg;
assign is_msg_wod = ~rx_header1_reg[30] & is_msg;
assign is_flush = (is_read & rx_lbe == 4'h0 & rx_fbe == 4'h0); /// read with no byte enable to flush
assign rx_lbe = rx_header1_reg[39:36];
assign rx_fbe = rx_header1_reg[35:32];
assign rx_dwlen = rx_header1_reg[9:0];
assign rx_byte_len = {rx_dwlen[9:0], 2'b00};
assign rx_3dw_header = !rx_header1_reg[29];
assign rx_addr[31:0] = rx_header1_reg[29]? RxStData_i[63:32] : RxStData_i[31:0];
assign is_valid_read = is_read & (rx_dwlen == 4'h1);
assign is_write_32 = is_write & rx_3dw_header;
assign is_flush_wr32 = is_valid_write & is_write_32 & rx_fbe == 4'h0;
assign is_flush_wr64 = is_valid_write & ~is_write_32 & rx_fbe == 4'h0;
assign addr_bit2 = rx_3dw_header? RxStData_i[2]: RxStData_i[34];
assign is_valid_write = is_write & (rx_dwlen == 4'h1);
assign addr_bit2_reg = rx_3dw_header? rx_header2_reg[2] : rx_header2_reg[34];
// poll counter to look for the first header
always @(posedge Clk_i or negedge Rstn_i) // state machine registers
begin
if(~Rstn_i)
header_poll_counter <= 0;
else if(rx_idle)
header_poll_counter <= 0;
else if(rx_state[2])
header_poll_counter <= header_poll_counter + 1;
end
// Rx Control SM to the HIP ST interface
always @(posedge Clk_i or negedge Rstn_i) // state machine registers
begin
if(~Rstn_i)
rx_state <= RX_IDLE;
else
rx_state <= rx_nxt_state;
end
always @*
begin
case(rx_state)
RX_IDLE :
rx_nxt_state <= RX_RD_HEADER1;
RX_RD_HEADER1:
rx_nxt_state <= RX_LATCH_HEADER1;
RX_LATCH_HEADER1:
if(RxStValid_i)
rx_nxt_state <= RX_RD_HEADER2;
else if(header_poll_counter == 4'hF)
rx_nxt_state <= RX_IDLE;
else
rx_nxt_state <= RX_LATCH_HEADER1;
RX_RD_HEADER2:
rx_nxt_state <= RX_LATCH_HEADER2;
RX_LATCH_HEADER2:
if(RxStValid_i)
rx_nxt_state <= RX_CHECK_HEADER;
else
rx_nxt_state <= RX_LATCH_HEADER2;
RX_CHECK_HEADER:
if(is_msg_wod | is_flush_wr32 & addr_bit2)
rx_nxt_state <= RX_IDLE;
else if(rx_eop_reg & (is_valid_read & ~is_flush| is_write_32 & addr_bit2 & is_valid_write & rx_fbe != 4'h0) )
rx_nxt_state <= RX_PENDING;
else if(is_write | is_msg_wd |is_flush_wr32 | is_flush_wr64)
rx_nxt_state <= RX_RD_DATA;
else if(rx_eop_reg & (!is_valid_read | is_flush) ) // not a valid read or flush
rx_nxt_state <= RX_CPL_REQ; // completion without data
else
rx_nxt_state <= RX_CHECK_HEADER;
RX_RD_DATA:
rx_nxt_state <= RX_LATCH_DATA;
RX_LATCH_DATA:
if(RxStValid_i & RxStEop_i & (is_msg_wd & rx_dwlen <= 2 & ~addr_bit2_reg| is_flush_wr32 |is_flush_wr64) )
rx_nxt_state <= RX_IDLE;
else if(RxStValid_i & RxStEop_i & is_valid_write)
rx_nxt_state <= RX_PENDING;
else if (~is_valid_write & RxStValid_i & RxStEop_i)
rx_nxt_state <= RX_IDLE;
else if((~is_valid_write & is_write & RxStValid_i)| (is_msg_wd & rx_dwlen > 2) |(is_msg_wd & rx_dwlen == 2 & addr_bit2_reg) )
rx_nxt_state <= RX_CLEAR_BUF;
else
rx_nxt_state <= RX_LATCH_DATA;
RX_PENDING:
if((wrena & ~rxm_wait_request) | TxStEop_o)
rx_nxt_state <= RX_IDLE;
else
rx_nxt_state <= RX_PENDING;
RX_CPL_REQ:
if(TxStEop_o)
rx_nxt_state <= RX_IDLE;
else
rx_nxt_state <= RX_CPL_REQ;
RX_CLEAR_BUF:
if(rx_qword_counter == 1 | rx_qword_counter == 0)
rx_nxt_state <= RX_WAIT_EOP;
else
rx_nxt_state <= RX_CLEAR_BUF;
RX_WAIT_EOP:
if(RxStEop_i)
rx_nxt_state <= RX_IDLE;
else
rx_nxt_state <= RX_WAIT_EOP;
default:
rx_nxt_state <= RX_IDLE;
endcase
end
assign rx_idle = ~rx_state[0];
assign rx_get_header1 = rx_state[1];
assign latch_rx_header1 = rx_state[2] & RxStValid_i;
assign rx_get_header2 = rx_state[3];
assign latch_rx_header2 = rx_state[4] & RxStValid_i;
assign rx_check_header = rx_state[5];
assign rx_get_write_data = rx_state[6];
assign rx_latch_write_data = rx_state[7] & RxStValid_i;
assign rx_pndg = rx_state[8];
assign tx_cpl_req = rx_state[9];
assign clear_rxbuff = rx_state[10];
// latch the first header QWORD
always @(posedge Clk_i or negedge Rstn_i)
begin
if(~Rstn_i)
rx_header1_reg <= 64'h0;
else if(latch_rx_header1)
rx_header1_reg <= RxStData_i[63:0];
end
// Latch Second Header QWORD and the BAR decode (Bar Hit)
always @(posedge Clk_i or negedge Rstn_i)
begin
if(~Rstn_i)
begin
rx_header2_reg <= 64'h0;
rx_bar_hit_reg <= 8'h0;
end
else if(latch_rx_header2)
begin
rx_header2_reg <= RxStData_i[63:0];
rx_bar_hit_reg <= RxStBarDec_i[7:0];
end
end
// Latch RX write data
always @(posedge Clk_i or negedge Rstn_i)
begin
if(~Rstn_i)
rx_writedata_reg <= 32'h0;
else if(latch_rx_header2 | rx_latch_write_data & addr_bit2_reg)
rx_writedata_reg <= RxStData_i[63:32];
else if(rx_latch_write_data)
rx_writedata_reg <= RxStData_i[31:0];
end
// hold the eop since it might assert before the check header state
always @(posedge Clk_i or negedge Rstn_i)
begin
if(~Rstn_i)
rx_eop_reg <= 1'b0;
else if(rx_idle)
rx_eop_reg <= 1'b0;
else if(RxStEop_i & RxStValid_i)
rx_eop_reg <= 1'b1;
end
// logic to keep track the number of data word extracted from the Rx buffer
assign adjusted_amount_dec_dw = (rx_3dw_header & addr_bit2); // 3 dw header and the data is not QWORD aligned => decrement by 1 dw, otherwise no adjustment
assign adjusted_amount_inc_dw = (~rx_3dw_header & addr_bit2); // 4 dw header and the data is not QWORD aligned => increment by 1 dw, otherwise no adjustment
always @(posedge Clk_i or negedge Rstn_i)
begin
if(~Rstn_i)
begin
adjusted_data_dw_reg <= 11'h0;
latch_rx_header2_reg <= 1'b0;
end
else
begin
adjusted_data_dw_reg <= rx_dwlen - adjusted_amount_dec_dw + adjusted_amount_inc_dw;
latch_rx_header2_reg <= latch_rx_header2;
end
end
assign adjusted_data_qw = adjusted_data_dw_reg[10:1] + adjusted_data_dw_reg[0]; // divided by 2 plus the remainder DW
always @(posedge Clk_i or negedge Rstn_i)
begin
if(~Rstn_i)
rx_qword_counter <= 10'h0;
else if(latch_rx_header2_reg) // for fmax
rx_qword_counter <= adjusted_data_qw;
else if(RxStReady_o)
rx_qword_counter <= rx_qword_counter - 1;
end
// Assign Outputs signals
// To AvalonMM interface to send the request to the AvalonM target
// address translation (PCIe to Avl)
altpciexpav_stif_p2a_addrtrans
p2a_addr_trans
( .k_bar_i(k_bar),
.cb_p2a_avalon_addr_b0_i(CB_P2A_AVALON_ADDR_B0),
.cb_p2a_avalon_addr_b1_i(CB_P2A_AVALON_ADDR_B1),
.cb_p2a_avalon_addr_b2_i(CB_P2A_AVALON_ADDR_B2),
.cb_p2a_avalon_addr_b3_i(CB_P2A_AVALON_ADDR_B3),
.cb_p2a_avalon_addr_b4_i(CB_P2A_AVALON_ADDR_B4),
.cb_p2a_avalon_addr_b5_i(CB_P2A_AVALON_ADDR_B5),
.cb_p2a_avalon_addr_b6_i(CB_P2A_AVALON_ADDR_B6),
.PCIeAddr_i(pcie_addr),
.BarHit_i(rx_bar_hit_reg[6:0]),
.AvlAddr_o(avl_addr)
);
always @(posedge Clk_i or negedge Rstn_i)
begin
if(~Rstn_i)
begin
avl_addr_reg <= 32'h0;
end
else
begin
avl_addr_reg <= avl_addr;
end
end
always @(posedge Clk_i or negedge Rstn_i)
begin
if(~Rstn_i)
rx_pending_reg <= 1'b0;
else
rx_pending_reg <= rx_pndg;
end
assign RxmWrite_0_o = wrena & rx_bar_hit_reg[0];
assign RxmRead_0_o = rdena & rx_bar_hit_reg[0];
assign RxmAddress_0_o = {avl_addr_reg[31:2], 2'h0};
assign RxmWriteData_0_o = rx_writedata_reg;
assign RxmWrite_1_o = wrena & rx_bar_hit_reg[1];
assign RxmRead_1_o = rdena & rx_bar_hit_reg[1];
assign RxmAddress_1_o = {avl_addr_reg[31:2], 2'h0};
assign RxmWriteData_1_o = rx_writedata_reg;
assign RxmWrite_2_o = wrena & rx_bar_hit_reg[2];
assign RxmRead_2_o = rdena & rx_bar_hit_reg[2];
assign RxmAddress_2_o = {avl_addr_reg[31:2], 2'h0};
assign RxmWriteData_2_o = rx_writedata_reg;
assign RxmWrite_3_o = wrena & rx_bar_hit_reg[3];
assign RxmRead_3_o = rdena & rx_bar_hit_reg[3];
assign RxmAddress_3_o = {avl_addr_reg[31:2], 2'h0};
assign RxmWriteData_3_o = rx_writedata_reg;
assign RxmWrite_4_o = wrena & rx_bar_hit_reg[4];
assign RxmRead_4_o = rdena & rx_bar_hit_reg[4];
assign RxmAddress_4_o = {avl_addr_reg[31:2], 2'h0};
assign RxmWriteData_4_o = rx_writedata_reg;
assign RxmWrite_5_o = wrena & rx_bar_hit_reg[5];
assign RxmRead_5_o = rdena & rx_bar_hit_reg[5];
assign RxmAddress_5_o = {avl_addr_reg[31:2], 2'h0};
assign RxmWriteData_5_o = rx_writedata_reg;
assign rxavl_req = !rx_pending_reg & rx_pndg;
assign RxmByteEnable_0_o = rx_fbe[3:0];
assign RxmByteEnable_1_o = rx_fbe[3:0];
assign RxmByteEnable_2_o = rx_fbe[3:0];
assign RxmByteEnable_3_o = rx_fbe[3:0];
assign RxmByteEnable_4_o = rx_fbe[3:0];
assign RxmByteEnable_5_o = rx_fbe[3:0];
/// Tie off the inputs when not available
assign rxm_read_data_valid_0 = RxmReadDataValid_0_i;
assign rxm_wait_request_0 = RxmWaitRequest_0_i;
assign rxm_read_data_0 = RxmReadData_0_i;
generate if (bar1_size_mask == 0)
begin
assign rxm_read_data_valid_1 = 1'b0;
assign rxm_wait_request_1 = 1'b1;
assign rxm_read_data_1 = 64'h0;
end
else
begin
assign rxm_read_data_valid_1 = RxmReadDataValid_1_i;
assign rxm_wait_request_1 = RxmWaitRequest_1_i;
assign rxm_read_data_1 = RxmReadData_1_i;
end
endgenerate
generate if (bar2_size_mask == 0)
begin
assign rxm_read_data_valid_2 = 1'b0;
assign rxm_wait_request_2 = 1'b1;
assign rxm_read_data_2 = 64'h0;
end
else
begin
assign rxm_read_data_valid_2 = RxmReadDataValid_2_i;
assign rxm_wait_request_2 = RxmWaitRequest_2_i;
assign rxm_read_data_2 = RxmReadData_2_i;
end
endgenerate
generate if (bar3_size_mask == 0)
begin
assign rxm_read_data_valid_3 = 1'b0;
assign rxm_wait_request_3 = 1'b1;
assign rxm_read_data_3 = 64'h0;
end
else
begin
assign rxm_read_data_valid_3 = RxmReadDataValid_3_i;
assign rxm_wait_request_3 = RxmWaitRequest_3_i;
assign rxm_read_data_3 = RxmReadData_3_i;
end
endgenerate
generate if (bar4_size_mask == 0)
begin
assign rxm_read_data_valid_4 = 1'b0;
assign rxm_wait_request_4 = 1'b1;
assign rxm_read_data_4 = 64'h0;
end
else
begin
assign rxm_read_data_valid_4 = RxmReadDataValid_4_i;
assign rxm_wait_request_4 = RxmWaitRequest_4_i;
assign rxm_read_data_4 = RxmReadData_4_i;
end
endgenerate
generate if (bar5_size_mask == 0)
begin
assign rxm_read_data_valid_5 = 1'b0;
assign rxm_wait_request_5 = 1'b1;
assign rxm_read_data_5 = 64'h0;
end
else
begin
assign rxm_read_data_valid_5 = RxmReadDataValid_5_i;
assign rxm_wait_request_5 = RxmWaitRequest_5_i;
assign rxm_read_data_5 = RxmReadData_5_i;
end
endgenerate
assign rxm_read_data_valid = rxm_read_data_valid_0 | rxm_read_data_valid_1 | rxm_read_data_valid_2 | rxm_read_data_valid_3 |
rxm_read_data_valid_4 | rxm_read_data_valid_5;
assign read_valid_vector = {rxm_read_data_valid_5, rxm_read_data_valid_4, rxm_read_data_valid_3, rxm_read_data_valid_2, rxm_read_data_valid_1, rxm_read_data_valid_0};
assign rxm_wait_request = rxm_wait_request_0 & rx_bar_hit_reg[0] | rxm_wait_request_1 & rx_bar_hit_reg[1] | rxm_wait_request_2 & rx_bar_hit_reg[2] |
rxm_wait_request_3 & rx_bar_hit_reg[3] | rxm_wait_request_4 & rx_bar_hit_reg[4] | rxm_wait_request_5 & rx_bar_hit_reg[5];
always @*
begin
case (read_valid_vector)
6'b000001 : rxm_read_data = rxm_read_data_0[31:0];
6'b000010 : rxm_read_data = rxm_read_data_1[31:0];
6'b000100 : rxm_read_data = rxm_read_data_2[31:0];
6'b001000 : rxm_read_data = rxm_read_data_3[31:0];
6'b010000 : rxm_read_data = rxm_read_data_4[31:0];
6'b100000 : rxm_read_data = rxm_read_data_5[31:0];
default : rxm_read_data = 32'h0;
endcase
end
assign pcie_addr = rx_3dw_header? rx_header2_reg[31:0] : rx_header2_reg[63:32];
// Interface to the HIP streaming interface
assign RxStReady_o = rx_get_header1 | rx_get_header2 | rx_get_write_data | clear_rxbuff;
//assign RxStReady_o = !(rx_pndg | tx_cpl_req); // do not accept any rx request while one ispending
/// Control logic interfacing to AvalonMM
always @(posedge Clk_i or negedge Rstn_i) // state machine registers
begin
if(~Rstn_i)
rxavl_state <= RXAVL_IDLE;
else
rxavl_state <= rxavl_nxt_state;
end
always @(rxavl_state, rxavl_req, is_write, is_read, rxm_wait_request )
begin
case(rxavl_state)
RXAVL_IDLE :
if(rxavl_req & is_write)
rxavl_nxt_state <= RXAVL_WRITE;
else if(rxavl_req & is_read)
rxavl_nxt_state <= RXAVL_READ;
else
rxavl_nxt_state <= RXAVL_IDLE;
RXAVL_WRITE:
if(~rxm_wait_request)
rxavl_nxt_state <= RXAVL_WRITE_DONE;
else
rxavl_nxt_state <= RXAVL_WRITE;
RXAVL_READ:
if(~rxm_wait_request)
rxavl_nxt_state <= RXAVL_IDLE;
else
rxavl_nxt_state <= RXAVL_READ;
RXAVL_WRITE_DONE:
rxavl_nxt_state <= RXAVL_IDLE;
default:
rxavl_nxt_state <= RXAVL_IDLE;
endcase
end
assign wrena = rxavl_state[1];
assign rdena = rxavl_state[2];
//// Tx response logic
// Latching the response data
always @(posedge Clk_i or negedge Rstn_i)
begin
if(~Rstn_i)
read_data_reg <= 32'h0;
else if(rxm_read_data_valid)
read_data_reg <= rxm_read_data[31:0];
end
// Form an Tx Completion packet
assign cpl_tc = rx_header1_reg[22:20];
assign cpl_attr= rx_header1_reg[13:12];
assign dw_len = tx_cpl_req & ~is_flush? 10'h0 : 10'h1;
always @(rx_fbe) // only first completion uses the fbe for byte count
begin
case(rx_fbe)
4'b0001 : normal_byte_count = 12'h1;
4'b0010 : normal_byte_count = 12'h1;
4'b0100 : normal_byte_count = 12'h1;
4'b1000 : normal_byte_count = 12'h1;
4'b0011 : normal_byte_count = 12'h2;
4'b0110 : normal_byte_count = 12'h2;
4'b1100 : normal_byte_count = 12'h2;
4'b0111 : normal_byte_count = 12'h3;
4'b1110 : normal_byte_count = 12'h3;
default : normal_byte_count = 12'h4;
endcase
end
always @* // only first completion uses the fbe for byte count
begin
case({rx_fbe, rx_lbe})
8'b1000_0001 : abort_byte_count = rx_byte_len - 6;
8'b1000_0011 : abort_byte_count = rx_byte_len - 5;
8'b1000_1111 : abort_byte_count = rx_byte_len - 3;
8'b1100_0001 : abort_byte_count = rx_byte_len - 5;
8'b1100_0011 : abort_byte_count = rx_byte_len - 4;
8'b1100_1111 : abort_byte_count = rx_byte_len - 2;
8'b1111_0001 : abort_byte_count = rx_byte_len - 3;
8'b1111_0011 : abort_byte_count = rx_byte_len - 2;
default : abort_byte_count = rx_byte_len;
endcase
end
assign remain_bytes = is_flush? 12'h1 : tx_cpl_req? abort_byte_count: normal_byte_count;
assign cpl_req_id = rx_header1_reg[63:48];
assign cpl_tag = rx_header1_reg[47:40];
// calculate the 7 bit lower address of the first enable byte
// based on the first byte enable
always @(rx_fbe, is_flush, rx_addr)
begin
casex({rx_fbe, is_flush})
5'bxxx10 : lower_addr = {rx_addr[6:2], 2'b00};
5'bxx100 : lower_addr = {rx_addr[6:2], 2'b01};
5'bx1000 : lower_addr = {rx_addr[6:2], 2'b10};
5'b10000 : lower_addr = {rx_addr[6:2], 2'b11};
5'bxxxx1 : lower_addr = {rx_addr[6:2], 2'b00};
default: lower_addr = 7'b0000000;
endcase
end
///////////// Synch and Demux the BusDev from configuration signals
//Synchronise to pld side
//Configuration Demux logic
always @(posedge Clk_i or negedge Rstn_i)
begin
if (Rstn_i == 0)
begin
cfg_busdev <= 13'h0;
msi_ena <= 1'b0;
end
else
begin
cfg_busdev <= (CfgAddr_i[3:0]==4'hF) ? CfgCtl_i[12 : 0] : cfg_busdev;
msi_ena <= (CfgAddr_i[3:0]==4'hD) ? CfgCtl_i[0] : msi_ena;
end
end
assign cpl_header = {
1'b0, is_valid_read, 6'b001010, 1'b0, cpl_tc, 4'h0, 2'h0, cpl_attr, 2'b00, dw_len,
cfg_busdev,3'b000, ~is_valid_read ,3'b000, remain_bytes,
cpl_req_id, cpl_tag, 1'b0,lower_addr,
read_data_reg[31:0]
};
assign tx_st_header1[63:0] = {cpl_header[95:64], cpl_header[127:96]};
assign tx_st_header2[63:0] = {cpl_header[31:0], cpl_header[63:32]};
assign tx_st_data[63:0] = {read_data_reg[31:0], read_data_reg[31:0]};
always @(posedge Clk_i or negedge Rstn_i)
begin
if(~Rstn_i)
cpl_data_available <= 1'b0;
else if(rxm_read_data_valid)
cpl_data_available <= 1'b1;
else if(TxStEop_o)
cpl_data_available <= 1'b0;
end
/// Control logic interfacing to Tx Streaming
always @(posedge Clk_i or negedge Rstn_i) // state machine registers
begin
if(~Rstn_i)
tx_state <= TX_IDLE;
else
tx_state <= tx_nxt_state;
end
always @(tx_state, cpl_data_available, tx_cpl_req, TxStReady_i, addr_bit2_reg,
is_valid_read)
begin
case(tx_state)
TX_IDLE :
if( (cpl_data_available | tx_cpl_req)& TxStReady_i)
tx_nxt_state <= TX_SOP;
else
tx_nxt_state <= TX_IDLE;
TX_SOP:
if(addr_bit2_reg | ~is_valid_read)
tx_nxt_state <= TX_EOP;
else
tx_nxt_state <= TX_CPL_HDR2;
TX_CPL_HDR2:
tx_nxt_state <= TX_EOP;
TX_EOP:
tx_nxt_state <= TX_IDLE;
default:
tx_nxt_state <= TX_IDLE;
endcase
end
assign tx_idle_st = !tx_state[0];
assign TxStSop_o = tx_state[1];
assign TxStEop_o = tx_state[3];
assign TxStData_o = TxStSop_o? tx_st_header1[63:0] : (TxStEop_o & !addr_bit2_reg & ~tx_cpl_req)? tx_st_data[63:0] : tx_st_header2[63:0];
assign TxStValid_o = !tx_idle_st;
assign RxStMask_o = 1'b0;
// INTx Interrupt logic
assign AppIntSts_o = |RxmIrq_i;
/// generate the MSI based on the
always @(posedge Clk_i or negedge Rstn_i)
begin
if (Rstn_i == 1'b0)
irq_reg <= 1'b0;
else
irq_reg<= RxmIrq_i;
end
assign irq_edge = ~irq_reg & RxmIrq_i;
always @(posedge Clk_i or negedge Rstn_i)
begin
if (Rstn_i == 1'b0)
MsiReq_o <= 1'b0;
else if(irq_edge & msi_ena)
MsiReq_o <= 1'b1;
else if(MsiAck_i)
MsiReq_o <= 1'b0;
end
assign MsiTc_o = 3'h0;
assign MsiNum_o = 5'h0;
/// Parameters conversion to signals
initial begin
init_k_bar[0:0] = (bar0_io_space == "true" ? 1'b1 : 1'b0);
init_k_bar[2:1] = (bar0_64bit_mem_space == "true" ? 2'b10 : 2'b00);
init_k_bar[3:3] = (bar0_prefetchable == "true" ? 1'b1 : 1'b0);
if (bar0_64bit_mem_space == "true")
begin
init_k_bar[63:4] = 60'hffff_ffff_ffff_fff << (bar0_size_mask - 4);
end
else begin
init_k_bar[31:4] = 28'hffff_fff << (bar0_size_mask - 4);
init_k_bar[32:32] = (bar1_io_space == "true" ? 1'b1 : 1'b0);
init_k_bar[34:33] = (bar1_64bit_mem_space == "true" ? 2'b10 : 2'b00);
init_k_bar[35:35] = (bar1_prefetchable == "true" ? 1'b1 : 1'b0);
init_k_bar[63:36] = 28'hffff_fff << (bar1_size_mask - 4);
end
init_k_bar[64:64] = (bar2_io_space == "true" ? 1'b1 : 1'b0);
init_k_bar[66:65] = (bar2_64bit_mem_space == "true" ? 2'b10 : 2'b00);
init_k_bar[67:67] = (bar2_prefetchable == "true" ? 1'b1 : 1'b0);
if (bar2_64bit_mem_space == "true")
begin
init_k_bar[127:68] = 60'hffff_ffff_ffff_fff << (bar2_size_mask - 4);
end
else begin
init_k_bar[95:68] = 28'hffff_fff << (bar2_size_mask - 4);
init_k_bar[96:96] = (bar3_io_space == "true" ? 1'b1 : 1'b0);
init_k_bar[98:97] = (bar3_64bit_mem_space == "true" ? 2'b10 : 2'b00);
init_k_bar[99:99] = (bar3_prefetchable == "true" ? 1'b1 : 1'b0);
init_k_bar[127:100] = 28'hffff_fff << (bar3_size_mask - 4);
end
init_k_bar[128:128] = (bar4_io_space == "true" ? 1'b1 : 1'b0);
init_k_bar[130:129] = (bar4_64bit_mem_space == "true" ? 2'b10 : 2'b00);
init_k_bar[131:131] = (bar4_prefetchable == "true" ? 1'b1 : 1'b0);
if (bar4_64bit_mem_space == "true")
begin
init_k_bar[191:132] = 60'hffff_ffff_ffff_fff << (bar4_size_mask - 4);
end
else begin
init_k_bar[159:132] = 28'hffff_fff << (bar4_size_mask - 4);
init_k_bar[160:160] = (bar5_io_space == "true" ? 1'b1 : 1'b0);
init_k_bar[162:161] = (bar5_64bit_mem_space == "true" ? 2'b10 : 2'b00);
init_k_bar[163:163] = (bar5_prefetchable == "true" ? 1'b1 : 1'b0);
init_k_bar[191:164] = 28'hffff_fff << (bar5_size_mask - 4);
end
if (expansion_base_address_register > 0)
init_k_bar[223:192] = 32'hffff_ffff << expansion_base_address_register;
else
init_k_bar[223:192] = expansion_base_address_register;
init_k_bar[225:224] = (
(bar_io_window_size == "NONE" ? 2'b00 : 2'b00) |
(bar_io_window_size == "16BIT" ? 2'b01 : 2'b00) |
(bar_io_window_size == "32BIT" ? 2'b10 : 2'b00) |
2'b00);
init_k_bar[227:226] = bar_prefetchable;
end
assign k_bar = init_k_bar;
endmodule
|
`timescale 1ns/1ns
module park
#(parameter INVERSE=0)
(input c,
input in_dv,
input signed [15:0] in_0,
input signed [15:0] in_1,
input signed [15:0] sin,
input signed [15:0] cos,
output signed [15:0] out_0,
output signed [15:0] out_1,
output out_dv);
wire [2:0] pipe_cnt;
r #(3) pipe_cnt_r
(.c(c), .en(|pipe_cnt | in_dv), .rst(1'b0),
.d(pipe_cnt + 1'b1), .q(pipe_cnt));
wire signed [15:0] input_z;
gmux #(.DWIDTH(16), .SELWIDTH(1)) input_mux
(.sel(pipe_cnt[0]), .z(input_z), .d({ in_1, in_0 }));
wire [31:0] x_z_mux_d = INVERSE ? { sin, cos } : { -sin, cos };
wire signed [15:0] mult_x_z;
gmux #(.DWIDTH(16), .SELWIDTH(1)) mult_x_z_mux
(.sel(pipe_cnt[0]), .z(mult_x_z), .d(x_z_mux_d)); //{ -sin, cos }));
wire [31:0] y_z_mux_d = INVERSE ? { cos, -sin } : { cos, sin };
wire signed [15:0] mult_y_z;
gmux #(.DWIDTH(16), .SELWIDTH(1)) mult_y_z_mux
(.sel(pipe_cnt[0]), .z(mult_y_z), .d(y_z_mux_d)); //{ cos, sin }));
wire signed [31:0] out_0_prod;
lpm_mult #(.lpm_widtha(16), .lpm_widthb(16), .lpm_widthp(32),
.lpm_representation("SIGNED"),
.lpm_pipeline(2)) out_x_mult
(.clock(c), .clken(1'b1), .aclr(1'b0), .sum(1'b0),
.dataa(input_z), .datab(mult_x_z), .result(out_0_prod));
r #(16) out_0_prod_r
(.c(c), .en(pipe_cnt == 3'h2 || pipe_cnt == 3'h3),
.rst(pipe_cnt == 3'h1), .d(out_0 + out_0_prod[30:15]), .q(out_0));
wire signed [31:0] out_1_prod;
lpm_mult #(.lpm_widtha(16), .lpm_widthb(16), .lpm_widthp(32),
.lpm_representation("SIGNED"),
.lpm_pipeline(2)) out_1_mult
(.clock(c), .clken(1'b1), .aclr(1'b0), .sum(1'b0),
.dataa(input_z), .datab(mult_y_z), .result(out_1_prod));
r #(16) out_1_prod_r
(.c(c), .en(pipe_cnt == 3'h2 || pipe_cnt == 3'h3),
.rst(pipe_cnt == 3'h1), .d(out_1 + out_1_prod[30:15]), .q(out_1));
assign out_dv = pipe_cnt == 3'h4;
endmodule
|
// -*- Mode: Verilog -*-
// Filename : system_controller_altera.v
// Description : System Controller for Altera FPGA
// Author : Philip Tracton
// Created On : Sat Jan 7 21:51:18 2017
// Last Modified By: Philip Tracton
// Last Modified On: Sat Jan 7 21:51:18 2017
// Update Count : 0
// Status : Unknown, Use with caution!
module system_controller_altera (/*AUTOARG*/
// Outputs
clk_i, rst_i, nrst_i,
// Inputs
clk_sys_i, rst_sys_i
) ;
input wire clk_sys_i;
input wire rst_sys_i;
output wire clk_i;
output reg rst_i;
output wire nrst_i;
wire LOCKED;
altera_syscon_pll pll(
.areset(rst_sys_i),
.inclk0(clk_sys_i),
.c0(clk_i),
.locked(LOCKED)
);
//
// RESET Logic
//
reg [3:0] rst_count;
//
// Inverted reset signal since some 3rd party blocks use an active low reset
//
assign nrst_i = ~rst_i;
//
// If input rst_sys_i or we are NOT locked, keep rst_i high for rest of system
// Once LOCKED is asserted, count down the rst_count number of clocks to make sure all
// synchronous reset blocks get a few clocks and can reset correctly. Once the count reaches 0
// release reset and let the sytem run
//
always @(posedge clk_sys_i)
if (rst_sys_i | ~LOCKED) begin
rst_i <= 1;
rst_count <= 4'hF;
end else begin
if (LOCKED) begin
if (rst_count) begin
rst_count <= rst_count - 1;
end else begin
rst_i <= 0;
end
end
end // else: !if(rst_sys_i | ~LOCKED)
endmodule // system_controller_altera
|
`timescale 1ns / 100ps
//
// Simulation testbench stubs for Xilinx modules...
//
module BUFG(I,O);
input I;
output O;
assign #1 O=I;
endmodule
module BUFGMUX(O,I0,I1,S);
input I0,I1,S;
output O;
assign #1 O = (S) ? I1 : I0;
endmodule
module DCM(CLKIN,PSCLK,PSEN,PSINCDEC,RST,CLK2X,CLK0,CLKFB);
input CLKIN, PSCLK, PSEN, PSINCDEC, RST, CLKFB;
output CLK2X, CLK0;
assign #1 CLK0 = CLKIN;
reg CLK2X;
initial CLK2X=0;
always @(posedge CLK0)
begin
CLK2X = 1'b1;
#5;
CLK2X = 1'b0;
#5;
CLK2X = 1'b1;
#5;
CLK2X = 1'b0;
end
endmodule
module ODDR2(Q,D0,D1,C0,C1);
input D0,D1,C0,C1;
output Q;
reg Q;
initial Q=0;
always @(posedge C0) Q=D0;
always @(posedge C1) Q=D1;
endmodule
module RAMB16_S9(CLK, ADDR, DI, DIP, DO, DOP, EN, SSR, WE);
input CLK, EN, SSR, WE;
input [10:0] ADDR;
input [7:0] DI;
input DIP;
output [7:0] DO;
output DOP;
parameter WRITE_MODE = 0;
wire [10:0] #1 dly_ADDR = ADDR;
wire [8:0] #1 dly_DATA = {DIP,DI};
wire #1 dly_EN = EN;
wire #1 dly_WE = WE;
reg [8:0] mem[0:2047];
reg [7:0] DO;
reg DOP;
reg sampled_EN;
reg [8:0] rddata;
integer i;
initial
begin
for (i=0; i<2048; i=i+1) mem[i] = 9'h15A;
end
always @(posedge CLK)
begin
if (dly_EN && dly_WE) mem[dly_ADDR] = dly_DATA;
rddata = mem[dly_ADDR];
sampled_EN = dly_EN;
#1;
if (sampled_EN) {DOP,DO} = rddata;
end
endmodule
module RAM16X1S (A0,A1,A2,A3,WCLK,WE,D,O);
input A0,A1,A2,A3,WCLK,WE,D;
output O;
reg mem[0:15];
wire #1 dly_WE = WE;
wire #1 dly_D = D;
wire [3:0] addr = {A3,A2,A1,A0};
wire [3:0] #1 dly_addr = addr;
always @(posedge WCLK)
begin
if (dly_WE) mem[dly_addr] = dly_D;
end
reg [3:0] rdaddr;
reg O;
always @*
begin
rdaddr = dly_addr;
#1;
O = mem[rdaddr];
end
endmodule
module RAM16X4S (A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3,O0,O1,O2,O3);
input A0,A1,A2,A3,WCLK,WE,D0,D1,D2,D3;
output O0,O1,O2,O3;
RAM16X1S bit0 (A0,A1,A2,A3,WCLK,WE,D0,O0);
RAM16X1S bit1 (A0,A1,A2,A3,WCLK,WE,D1,O1);
RAM16X1S bit2 (A0,A1,A2,A3,WCLK,WE,D2,O2);
RAM16X1S bit3 (A0,A1,A2,A3,WCLK,WE,D3,O3);
endmodule
module SRLC16E (A0,A1,A2,A3,CLK,CE,D,Q15,Q);
input A0,A1,A2,A3,CLK,CE,D;
output Q15,Q;
reg [15:0] mem;
wire #1 dly_CE = CE;
wire #1 dly_D = D;
wire [3:0] addr = {A3,A2,A1,A0};
wire [3:0] #1 dly_addr = addr;
assign Q15 = mem[15];
always @(posedge CLK)
begin
if (dly_CE) mem = {mem,dly_D};
end
reg [3:0] rdaddr;
reg Q;
always @*
begin
rdaddr = dly_addr;
#1;
Q = mem[rdaddr];
end
endmodule
module MUXCY (S,CI,DI,O);
input S,CI,DI;
output O;
reg O;
always @* begin #0.1; O = (S) ? CI : DI; end
endmodule
|
// megafunction wizard: %CIC v11.1%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// lpf_cic
// ============================================================
// Generated by CIC 11.1 [Altera, IP Toolbench 1.3.0 Build 173]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2016 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module lpf (
clk,
clken,
reset_n,
in_data,
in_valid,
out_ready,
in_error,
out_data,
in_ready,
out_valid,
out_error);
input clk;
input clken;
input reset_n;
input [31:0] in_data;
input in_valid;
input out_ready;
input [1:0] in_error;
output [31:0] out_data;
output in_ready;
output out_valid;
output [1:0] out_error;
lpf_cic lpf_cic_inst(
.clk(clk),
.clken(clken),
.reset_n(reset_n),
.in_data(in_data),
.in_valid(in_valid),
.out_ready(out_ready),
.in_error(in_error),
.out_data(out_data),
.in_ready(in_ready),
.out_valid(out_valid),
.out_error(out_error));
endmodule
// =========================================================
// CIC Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, CIC Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="CIC" version="11.1" build="173" iptb_version="1.3.0 Build 173" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.CICModel" active_core="lpf_cic" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "filter_type" value="Decimator" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "megawizard2" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "activate_atstartup" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "window_location" value="center" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "Device Family" value="Cyclone II" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "Number of Stages" value="3" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "Rate Change Factor" value="1024" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "Differential Delay" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "Input Bit Width" value="32" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "Output Bit Width" value="32" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "Hogenauer Pruning" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "Support AST back pressure" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "Full Output Resolution" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "Map Integrator Registers Into" value="Logic Element" type="STRING" enable="0" />
// Retrieval info: <PRIVATE name = "Map Differentiator Registers Into" value="Logic Element" type="STRING" enable="0" />
// Retrieval info: <PRIVATE name = "Ram Type of Integrator Registers" value="AUTO" type="STRING" enable="0" />
// Retrieval info: <PRIVATE name = "Ram Type of Differentiator Registers" value="AUTO" type="STRING" enable="0" />
// Retrieval info: <PRIVATE name = "Number of channels per interface" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "Number of interfaces" value="1" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "Output Rounding Option" value="0" type="INTEGER" enable="1" />
// Retrieval info: <PRIVATE name = "Integrator pipeline number" value="1" type="INTEGER" enable="0" />
// Retrieval info: <PRIVATE name = "Use pipeline in integrator" value="0" type="BOOLEAN" enable="0" />
// Retrieval info: <PRIVATE name = "Variable Rate Change Factor" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "Maximum Rate Change Factor" value="3" type="INTEGER" enable="0" />
// Retrieval info: <PRIVATE name = "Minimum Rate Change Factor" value="2" type="INTEGER" enable="0" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="Verilog HDL" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "hdl_generator">
// Retrieval info: <PRIVATE name = "report" value="1" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "blackbox" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "component" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: <PRIVATE name = "symbol" value="0" type="BOOLEAN" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "filename" value="lpf.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "filename" value="lpf_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "quartus_settings">
// Retrieval info: <PRIVATE name = "DEVICE" value="EP2C5T144C7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "FAMILY" value="Cyclone II" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS>
// Retrieval info: <PORT name = "clock" direction="INPUT" connect_to="clk" default="NODEFVAL" width="1" description="" />
// Retrieval info: <PORT name = "reset" direction="INPUT" connect_to="reset" default="NODEFVAL" width="1" description="" />
// Retrieval info: </PORTS>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
|
module image_processor (
input [7:0] iR,
input [7:0] iG,
input [7:0] iB,
input iHSync,
input iVSync,
input iLineValid,
input iFrameValid,
input iClk,
input iRst,
input [23:0] iDebug,
output [7:0] oR,
output [7:0] oG,
output [7:0] oB,
output oHSync,
output oVSync,
output oLineValid,
output oFrameValid,
output [23:0] oDebug
);
/************************************************
* Debug SW[4:3]
***********************************************/
reg [23:0] rDebugFPS = 0;
reg [23:0] rFPS = 0;
reg [32:0] rTime = 0;
reg [23:0] rDebugRes = 0;
reg [23:0] rWidth = 0;
reg [23:0] rHeight = 0;
reg rLineValidL = 0;
reg rFrameValidL = 0;
always@(posedge iClk)
begin
rTime <= rTime + 1;
if({rFrameValidL,iFrameValid} == 2'b10) rFPS <= rFPS + 1;
case({rLineValidL,iLineValid})
2'b10: rDebugRes[23:12] <= rWidth[11:0];
2'b00: rWidth <= 0;
2'b01: rWidth <= 0;
2'b11: rWidth <= rWidth + 1;
endcase
rLineValidL <= iLineValid;
case({rFrameValidL,iFrameValid})
2'b10: rDebugRes[11:0] <= rHeight[11:0];
2'b00: rHeight <= 0;
2'b01: rHeight <= 0;
2'b11: if({rLineValidL,iLineValid} == 2'b10) rHeight <= rHeight + 1;
endcase
rFrameValidL <= iFrameValid;
if(rTime == 25000000)
begin
rTime <= 0;
rDebugFPS <= rFPS;
rFPS <= 0;
end
end
/************************************************
* Option mux SW[2:0]
***********************************************/
wire [7:0] wRMux [7:0];
wire [7:0] wGMux [7:0];
wire [7:0] wBMux [7:0];
wire [23:0] wDebugMux [7:0];
wire wHSync [7:0];
wire wVSync [7:0];
wire wLineValid [7:0];
wire wFrameValid [7:0];
/************************************************
* Debug mux
***********************************************/
wire [23:0] wDebugMuxSw [2:0];
//Option 0
assign wDebugMuxSw[0] = rDebugRes;
//Option 1
assign wDebugMuxSw[1] = rDebugFPS;
//Option 2
assign wDebugMuxSw[2] = wDebugMux[iDebug[2:0]];
//Option 0
assign wRMux[0] = iR;
assign wGMux[0] = iG;
assign wBMux[0] = iB;
assign wHSync[0] = iHSync;
assign wVSync[0] = iVSync;
assign wLineValid[0] = iLineValid;
assign wFrameValid[0] = iFrameValid;
assign wDebugMux[0] = 1;
//Option 1
assign wRMux[1] = iR;
assign wGMux[1] = iG;
assign wBMux[1] = iB;
assign wHSync[1] = iHSync;
assign wVSync[1] = iVSync;
assign wLineValid[1] = iLineValid;
assign wFrameValid[1] = iFrameValid;
assign wDebugMux[1] = 1;
//Option 2
assign wRMux[2] = iR;
assign wGMux[2] = iG;
assign wBMux[2] = iB;
assign wHSync[2] = iHSync;
assign wVSync[2] = iVSync;
assign wLineValid[2] = iLineValid;
assign wFrameValid[2] = iFrameValid;
assign wDebugMux[2] = 2;
//Option 3
assign wRMux[3] = iR;
assign wGMux[3] = iG;
assign wBMux[3] = iB;
assign wHSync[3] = iHSync;
assign wVSync[3] = iVSync;
assign wLineValid[3] = iLineValid;
assign wFrameValid[3] = iFrameValid;
assign wDebugMux[3] = 3;
//Option 4
assign wRMux[4] = iR;
assign wGMux[4] = iG;
assign wBMux[4] = iB;
assign wHSync[4] = iHSync;
assign wVSync[4] = iVSync;
assign wLineValid[4] = iLineValid;
assign wFrameValid[4] = iFrameValid;
assign wDebugMux[4] = 4;
//Option 5
assign wRMux[5] = iR;
assign wGMux[5] = iG;
assign wBMux[5] = iB;
assign wHSync[5] = iHSync;
assign wVSync[5] = iVSync;
assign wLineValid[5] = iLineValid;
assign wFrameValid[5] = iFrameValid;
assign wDebugMux[5] = 5;
//Option 6
assign wRMux[6] = iR;
assign wGMux[6] = iG;
assign wBMux[6] = iB;
assign wHSync[6] = iHSync;
assign wVSync[6] = iVSync;
assign wLineValid[6] = iLineValid;
assign wFrameValid[6] = iFrameValid;
assign wDebugMux[6] = 6;
//Option 7
assign wRMux[7] = 0;
assign wGMux[7] = 0;
assign wBMux[7] = 0;
assign wHSync[7] = iHSync;
assign wVSync[7] = iVSync;
assign wLineValid[7] = iLineValid;
assign wFrameValid[7] = iFrameValid;
assign wDebugMux[7] = 7;
//Mux connect
assign oR = wRMux[iDebug[2:0]];
assign oG = wGMux[iDebug[2:0]];
assign oB = wBMux[iDebug[2:0]];
assign oDebug = wDebugMuxSw[iDebug[4:3]];
assign oHSync = wHSync[iDebug[2:0]];
assign oVSync = wVSync[iDebug[2:0]];
assign oLineValid = wLineValid[iDebug[2:0]];
assign oFrameValid = wFrameValid[iDebug[2:0]];
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S50_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLYGATE4S50_FUNCTIONAL_PP_V
/**
* dlygate4s50: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlygate4s50 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S50_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_BLACKBOX_V
`define SKY130_FD_SC_LP__A311O_BLACKBOX_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_BLACKBOX_V
|
// (c) NedoPC 2013
//
// SD data sender to test SD and MP3 dmas
`timescale 1ns/100ps
module sd
(
input wire clk,
input wire sdi,
output wire sdo
);
reg [7:0] byteout;
reg [7:0] bytein;
int bitcntout;
int bitcntin;
int state;
int count;
reg [7:0] tmp;
localparam _FF = 'd0;
localparam _FE = 'd1;
localparam _DATA = 'd2;
localparam _CRC = 'd3;
initial byteout = 8'hFF;
initial bitcntout = 8;
initial bitcntin = 7;
initial state = _FF;
initial count = 5;
assign sdo = byteout[7];
always @(negedge clk)
begin
byteout <= {byteout[6:0],1'b1};
bitcntout = bitcntout - 1;
if( bitcntout<0 )
begin
bitcntout = 7;
case( state )
_FF:begin
count = count - 1;
if( count <= 0 )
state <= _FE;
byteout <= 8'hFF;
end
_FE:begin
state <= _DATA;
byteout <= 8'hFE;
count = 512;
end
_DATA:begin
count = count - 1;
if( count <= 0 )
begin
state <= _CRC;
count <= 2;
end
tmp = $random>>24;
byteout <= tmp;
tb.sdmp3_chk.push_back(tmp);
end
_CRC:begin
count = count - 1;
if( count <= 0 )
begin
state <= _FF;
count <= 1+($random&63);
end
byteout <= $random>>24;
end
endcase
end
end
always @(posedge clk)
begin
bytein = {bytein[6:0], sdi};
bitcntin = bitcntin - 1;
if( bitcntin<0 )
begin
bitcntin = 7;
if( bytein!==8'hFF )
begin
$display("sd: received not FF!");
$stop;
end
end
end
endmodule
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module generic_cntr_regs
#(
parameter UDP_REG_SRC_WIDTH = 2,
parameter TAG = 0, // Tag to match against
parameter REG_ADDR_WIDTH = 5, // Width of block addresses
parameter NUM_REGS_USED = 8, // How many registers
parameter REG_START_ADDR = 0, // Address of the first counter
parameter INPUT_WIDTH = 1, // Width of each update request
parameter MIN_UPDATE_INTERVAL = 8, // Clocks between successive inputs
parameter REG_WIDTH = `CPCI_NF2_DATA_WIDTH, // How wide should each counter be?
parameter RESET_ON_READ = 0,
// Don't modify the parameters below. They are used to calculate the
// widths of the various register inputs/outputs.
parameter REG_END_ADDR = REG_START_ADDR + NUM_REGS_USED, // address of last counter + 1
parameter UPDATES_START = REG_START_ADDR * INPUT_WIDTH, // first bit of the updates vector
parameter UPDATES_END = REG_END_ADDR * INPUT_WIDTH // bit after last bit of the updates vector
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- update interface
input [UPDATES_END - 1:UPDATES_START] updates,
input [REG_END_ADDR-1:REG_START_ADDR] decrement, // if 1 then subtract the update, else add.
input clk,
input reset
);
`LOG2_FUNC
`CEILDIV_FUNC
// ------------- Internal parameters --------------
localparam MIN_CYCLE_TIME = NUM_REGS_USED + 1;
// Calculate the number of updates we can see in a single cycle through the
// RAM.
//
// This should be:
// ceil(MIN_CYCLE_TIME / MIN_UPDATE_INTERVAL)
localparam UPDATES_PER_CYCLE = ceildiv(MIN_CYCLE_TIME, MIN_UPDATE_INTERVAL);
localparam LOG_UPDATES_PER_CYCLE = log2(UPDATES_PER_CYCLE);
// Calculate how much storage to allocate for each delta
//
// A single update requires INPUT_WIDTH bits of storage
// In the worst case we would add the updates and get a total of
// (2^INPUT_WIDTH - 1) * UPDATES_PER_CYCLE
// This can be represented in:
// log2( (2^INPUT_WIDTH - 1) * UPDATES_PER_CYCLE )
// = INPUT_WIDTH + log2(UPDATES_PER_CYCLE)
// we add one for sign extension.
localparam DELTA_WIDTH = INPUT_WIDTH + LOG_UPDATES_PER_CYCLE + 1;
localparam RESET = 0,
NORMAL = 1;
// ------------- Wires/reg ------------------
reg [REG_WIDTH-1:0] reg_file [REG_START_ADDR:REG_END_ADDR-1];
wire [REG_ADDR_WIDTH-1:0] addr, addr_d1;
wire [`UDP_REG_ADDR_WIDTH-REG_ADDR_WIDTH-1:0] tag_addr;
reg [REG_ADDR_WIDTH-1:0] reg_cnt;
wire [REG_ADDR_WIDTH-1:0] reg_cnt_nxt;
wire [REG_ADDR_WIDTH-1:0] reg_file_rd_addr;
reg [REG_ADDR_WIDTH-1:0] reg_file_rd_addr_ram;
wire [REG_ADDR_WIDTH-1:0] reg_file_wr_addr;
reg [DELTA_WIDTH-1:0] deltas[REG_START_ADDR:REG_END_ADDR-1];
wire [DELTA_WIDTH-1:0] delta;
wire [DELTA_WIDTH-1:0] update[REG_START_ADDR:REG_END_ADDR-1];
wire [REG_WIDTH-1:0] reg_file_out;
reg [REG_WIDTH-1:0] reg_file_in;
reg reg_file_wr_en;
reg [REG_ADDR_WIDTH-1:0] reg_cnt_d1;
reg reg_rd_req_good_d1, reg_wr_req_good_d1;
reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in_d1;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in_d1;
reg reg_req_in_d1;
reg reg_ack_in_d1;
reg reg_rd_wr_L_in_d1;
reg [UDP_REG_SRC_WIDTH-1:0] reg_src_in_d1;
integer i;
reg state;
// -------------- Logic --------------------
assign addr = reg_addr_in[REG_ADDR_WIDTH-1:0];
assign addr_d1 = reg_addr_in_d1[REG_ADDR_WIDTH-1:0];
assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:REG_ADDR_WIDTH];
assign addr_good = addr < REG_END_ADDR && addr >= REG_START_ADDR;
assign tag_hit = tag_addr == TAG;
assign reg_rd_req_good = (tag_hit && addr_good && reg_req_in && reg_rd_wr_L_in);
assign reg_wr_req_good = (tag_hit && addr_good && reg_req_in && ~reg_rd_wr_L_in);
assign reg_cnt_nxt = (reg_cnt==REG_END_ADDR-1'b1) ? REG_START_ADDR : reg_cnt + 1'b1;
assign delta = deltas[reg_cnt_d1];
assign reg_file_rd_addr = reg_rd_req_good ? addr : reg_cnt;
assign reg_file_wr_addr = (state == RESET
? reg_cnt
: (reg_wr_req_good_d1 || reg_rd_req_good_d1)
? addr_d1 : reg_cnt_d1);
// choose when and what to write in the ram
always @(*) begin
reg_file_in = reg_file_out + {{(REG_WIDTH - DELTA_WIDTH){delta[DELTA_WIDTH-1]}}, delta};
reg_file_wr_en = 0;
if(state == RESET || (reg_rd_req_good_d1 && RESET_ON_READ)) begin
reg_file_wr_en = 1;
reg_file_in = 0;
end
else if(!reg_wr_req_good_d1 && !reg_rd_req_good_d1) begin
reg_file_wr_en = 1;
end
else if(reg_wr_req_good_d1) begin
reg_file_in = reg_data_in_d1;
reg_file_wr_en = 1;
end
end // always @ (*)
// Generate the individual update lines from the updates vector
//
// Note: I have the ugly bit selection because ModelSim doesn't seem to
// like parameters used in :+ selects! :-(
generate
genvar j;
for (j = REG_START_ADDR; j < REG_END_ADDR; j = j + 1) begin : update_gen
assign update[j] = {{(DELTA_WIDTH - INPUT_WIDTH){1'b0}}, updates[(j + 1) * INPUT_WIDTH - 1 : j * INPUT_WIDTH]};
end
endgenerate
/*********** RAM *************/
always @(posedge clk) begin
// write to the register file
if(reg_file_wr_en) begin
reg_file[reg_file_wr_addr] <= reg_file_in;
end
reg_file_rd_addr_ram <= reg_file_rd_addr;
end
assign reg_file_out = reg_file[reg_file_rd_addr_ram];
/****************************/
// State machine that handles register access from the CPU
always @(posedge clk) begin
if(reset) begin
reg_cnt <= REG_START_ADDR;
reg_rd_req_good_d1 <= 0;
reg_wr_req_good_d1 <= 0;
reg_req_in_d1 <= 0;
reg_ack_out <= 0;
reg_req_out <= 0;
state <= RESET;
for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1) begin
deltas[i] <= 0;
end
end // if (reset)
else begin
reg_cnt_d1 <= reg_cnt;
if(state == RESET) begin
reg_cnt <= reg_cnt_nxt;
if(reg_cnt == REG_END_ADDR-1'b1) begin
state <= NORMAL;
end
end
else begin
/*********************************************************************
* first stage - read bram, latch reg req signals
*/
reg_cnt <= (reg_rd_req_good || reg_wr_req_good) ? reg_cnt : reg_cnt_nxt;
reg_rd_req_good_d1 <= reg_rd_req_good;
reg_wr_req_good_d1 <= reg_wr_req_good;
reg_addr_in_d1 <= reg_addr_in;
reg_data_in_d1 <= reg_data_in;
reg_req_in_d1 <= reg_req_in;
reg_ack_in_d1 <= reg_ack_in;
reg_rd_wr_L_in_d1 <= reg_rd_wr_L_in;
reg_src_in_d1 <= reg_src_in;
// synthesis translate_off
if(reg_ack_in && (reg_rd_req_good || reg_wr_req_good)) begin
$display("%t %m ERROR: Register request already ack even though", $time);
$display("it should be destined to this module. This can happen");
$display("if two modules have aliased register addresses.");
$stop;
end
// synthesis translate_on
/********************************************************************
* second stage - output rd req or do write req or delta update
*/
reg_ack_out <= reg_rd_req_good_d1 || reg_wr_req_good_d1 || reg_ack_in_d1;
reg_data_out <= reg_rd_req_good_d1 ? reg_file_out : reg_data_in_d1;
reg_addr_out <= reg_addr_in_d1;
reg_req_out <= reg_req_in_d1;
reg_rd_wr_L_out <= reg_rd_wr_L_in_d1;
reg_src_out <= reg_src_in_d1;
/*******************************************************************
* update the deltas
*/
for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1) begin
// if we just update the register corresponding to this delta then
// clear it.
if ((i==reg_cnt_d1) // this delta was committed to reg_file
&& !reg_wr_req_good_d1 // we didn't write in this cycle
&& !(reg_rd_req_good_d1 && RESET_ON_READ) // we didn't read and reset
) begin
deltas[i] <= decrement[i] ? -update[i] : update[i];
end
else begin
deltas[i] <= decrement[i] ? deltas[i] - update[i] : deltas[i] + update[i];
end
end // for (i = REG_START_ADDR; i < REG_END_ADDR; i = i + 1)
end // else: !if(state == RESET)
end // else: !if(reset)
end // always @ (posedge clk)
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__CLKBUF_PP_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_SYMBOL_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_SYMBOL_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_SYMBOL_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe (probe_input),
.source ()
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
iss_probe_inst.enable_metastability = "NO",
iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH,
iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0,
iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised
// by a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement
// from Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================
// FILE DETAILS
// Project : pci_exp_x1
// File : tb_top.v
// Title :
// Dependencies : pci_exp_params.v pci_exp_ddefines.v testcase.v
// Description : Top level for testbench of pci_exp IP with Serdes PCS PIPE
//
// =============================================================================
// REVISION HISTORY
// Version : 1.0
// Mod. Date : Oct 02, 2007
// Changes Made : Initial Creation
// =============================================================================
`timescale 100 ps/100 ps
module tb_top;
// DUT User defines
`include "pci_exp_params.v"
// =============================================================================
// Regs for BFM & Test case
// =============================================================================
//---- Regs
reg clk_100;
reg error;
reg rst_n;
reg no_pcie_train; // This signal disables the training process
reg ecrc_gen_enb ;
reg ecrc_chk_enb ;
reg [1:0] tx_dllp_val;
reg [2:0] tx_pmtype; // Power Management Type
reg [23:0] tx_vsd_data;
reg rx_tlp_discard;
wire [23:0] tbtx_vc;
wire [23:0] tbrx_vc;
reg disable_mlfmd_check;
reg DISABLE_SKIP_CHECK;
wire [1:0] power_down_init;
wire [14:0] init_15_00;
wire [14:0] init_15_11;
wire [15:0] init_16_11;
reg enb_log;
//---- Wires
wire [2:0] rxdp_pmd_type;
wire [23:0] rxdp_vsd_data;
wire rxdp_vsd_val;
wire [1:0] rxdp_dllp_val;
wire dl_up;
wire sys_clk_125;
wire sys_clk_125_tmp;
wire tx_dllp_sent;
wire [63:0] INIT_PH_FC; //Initial P HdrFC value
wire [63:0] INIT_NPH_FC; // For NPH
wire [95:0] INIT_PD_FC; // Initial P DataFC value
wire [95:0] INIT_NPD_FC; // For NPD
wire [71:0] tx_ca_ph;
wire [103:0] tx_ca_pd;
wire [71:0] tx_ca_nph;
wire [103:0] tx_ca_npd;
wire [71:0] tx_ca_cplh;
wire [103:0] tx_ca_cpld;
reg [7:0] tbrx_cmd_prsnt;
wire [7:0] tbrx_cmd_prsnt_int;
wire [7:0] ph_buf_status; // Indicate the Full/alm.Full status of the PH buffers
wire [7:0] pd_buf_status; // Indicate PD Buffer has got space less than Max Pkt size
wire [7:0] nph_buf_status; // For NPH
wire [7:0] npd_buf_status; // For NPD
wire [7:0] ph_processed; // TL has processed one TLP Header - PH Type
wire [7:0] pd_processed; // TL has processed one TLP Data - PD TYPE
wire [7:0] nph_processed; // For NPH
wire [7:0] npd_processed; // For NPD
wire [8*8-1:0] pd_num;
wire [8*8-1:0] npd_num;
//---------Outputs From Core------------
wire [7:0] tx_rdy;
wire [127:0] rx_data;
wire [7:0] rx_st;
wire [7:0] rx_end;
wire [7:0] rx_ecrc_err;
wire [7:0] rx_us_req;
wire [7:0] rx_malf_tlp;
wire [3:0] phy_ltssm_state;
wire [7:0] tx_req;
wire [2:0] rx_status;
wire [1:0] power_down;
wire tx_detect_rx;
wire tx_elec_idle;
wire tx_compliance;
wire rx_polarity;
//wire reset_n;
wire [15:0] rx_valid;
wire [15:0] rx_elec_idle;
wire [15:0] phy_status;
wire rx_valid0; //For Debug
wire rx_elec_idle0;
wire phy_status0;
wire phy_realign_req;
//---- Integer
integer i;
wire [(`NUM_VC*16)-1:0] tx_data;
wire [`NUM_VC-1:0] tx_st;
wire [`NUM_VC-1:0] tx_end;
wire [`NUM_VC-1:0] tx_nlfy;
wire [`NUM_VC-1:0] tb_sys_clk;
`ifdef WISHBONE
reg RST_I ;
reg CLK_I ;
reg [12:0] ADR_I ;
reg [31:0] DAT_I ;
reg [3:0] SEL_I ;
reg WE_I ;
reg STB_I ;
reg CYC_I ;
wire [31:0] CHAIN_RDAT_in = 32'd0 ;
wire CHAIN_ACK_in = 1'd0;
wire [31:0] DAT_O ;
wire ACK_O ;
wire IRQ_O ;
`endif
parameter DLY1 = 1 ;
parameter DLY2 = 1 ;
// =============================================================================
// Include Testbench params files
// DUT Design params file
`include "pci_exp_ddefines.v"
// Include the test case
`include "testcase.v"
// =============================================================================
//-------- For Flow Control Tasks
parameter P = 2'b00;
parameter NP = 2'b01;
parameter CPLX = 2'b10; //CPL is already used in some other paramter
parameter PH = 3'b000;
parameter PD = 3'b001;
parameter NPH = 3'b010;
parameter NPD = 3'b011;
parameter CPLH = 3'b100;
parameter CPLD = 3'b101;
//---- Wires
wire hdoutp_0 ;
wire hdoutn_0 ;
reg hdoutp_0_d ;
reg hdoutn_0_d ;
wire refclkp;
wire refclkn;
pullup (hdoutp_0);
pullup (hdoutn_0);
always @* begin
if (!rst_n)
#DLY1 hdoutp_0_d <= hdoutp_0 ;
else if (hdoutp_0 == 1'b1)
#DLY1 hdoutp_0_d <= 1'b1 ;
else if (hdoutp_0 == 1'b0)
#DLY1 hdoutp_0_d <= 1'b0 ;
else if (hdoutp_0 === 1'bz)
#DLY1 hdoutp_0_d <= 1'b1 ;
else
#DLY1 hdoutp_0_d <= hdoutp_0_d ;
if (!rst_n)
#DLY1 hdoutn_0_d <= hdoutn_0 ;
else if (hdoutn_0 == 1'b1)
#DLY1 hdoutn_0_d <= 1'b1 ;
else if (hdoutn_0 == 1'b0)
#DLY1 hdoutn_0_d <= 1'b0 ;
else if (hdoutn_0 === 1'bz)
#DLY1 hdoutp_0_d <= 1'b1 ;
else
#DLY1 hdoutn_0_d <= hdoutn_0_d ;
end
// =============================================================================
// PIPE_SIGNALS For Debug -- For X1
// =============================================================================
assign rx_valid0 = rx_valid[0];
assign rx_elec_idle0 = rx_elec_idle[0];
assign phy_status0 = phy_status[0];
// =============================================================================
// Generate tbrx_cmd_prsnt
// =============================================================================
always@(sys_clk_125) begin
tbrx_cmd_prsnt[7] <= (tbrx_cmd_prsnt_int[7] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[6] <= (tbrx_cmd_prsnt_int[6] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[5] <= (tbrx_cmd_prsnt_int[5] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[4] <= (tbrx_cmd_prsnt_int[4] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[3] <= (tbrx_cmd_prsnt_int[3] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[2] <= (tbrx_cmd_prsnt_int[2] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[1] <= (tbrx_cmd_prsnt_int[1] === 1'b1) ? 1'b1 : 1'b0;
tbrx_cmd_prsnt[0] <= (tbrx_cmd_prsnt_int[0] === 1'b1) ? 1'b1 : 1'b0;
end
`ifdef VC8
assign tbrx_vc = {3'd7, 3'd6, 3'd5, 3'd4, 3'd3, 3'd2, 3'd1, 3'd0};
assign tbtx_vc = {3'd7, 3'd6, 3'd5, 3'd4, 3'd3, 3'd2, 3'd1, 3'd0};
`endif
`ifdef VC7
assign tbrx_vc = {3'd6, 3'd5, 3'd4, 3'd3, 3'd2, 3'd1, 3'd0};
assign tbtx_vc = {3'd6, 3'd5, 3'd4, 3'd3, 3'd2, 3'd1, 3'd0};
`endif
`ifdef VC6
assign tbrx_vc = {3'd5, 3'd4, 3'd3, 3'd2, 3'd1, 3'd0};
assign tbtx_vc = {3'd5, 3'd4, 3'd3, 3'd2, 3'd1, 3'd0};
`endif
`ifdef VC5
assign tbrx_vc = {3'd4, 3'd3, 3'd2, 3'd1, 3'd0};
assign tbtx_vc = {3'd4, 3'd3, 3'd2, 3'd1, 3'd0};
`endif
`ifdef VC4
assign tbrx_vc = {3'd3, 3'd2, 3'd1, 3'd0};
assign tbtx_vc = {3'd3, 3'd2, 3'd1, 3'd0};
`endif
`ifdef VC3
assign tbrx_vc = {3'd2, 3'd1, 3'd0};
assign tbtx_vc = {3'd2, 3'd1, 3'd0};
`endif
`ifdef VC2
assign tbrx_vc = {3'd1, 3'd0};
assign tbtx_vc = {3'd1, 3'd0};
`endif
`ifdef VC1
assign tbrx_vc = 3'd0;
assign tbtx_vc = 3'd0;
`endif
assign power_down_init = 2'b10;
assign init_15_00 = 15'b0000_0000_0000_000;
assign init_15_11 = 15'b1111_1111_1111_111;
assign init_16_11 = 16'b1111_1111_1111_1111;
// =============================================================================
// TBTX (User Logic on TX side) Instantiations
// =============================================================================
tbtx u_tbtx [`NUM_VC-1:0] (
//----- Inputs
.sys_clk (sys_clk_125),
.rst_n (rst_n),
.tx_tc (tbtx_vc[(`NUM_VC*3)-1:0]),
.tx_ca_ph (tx_ca_ph[(9*`NUM_VC)-1:0]),
.tx_ca_pd (tx_ca_pd[(13*`NUM_VC)-1:0]),
.tx_ca_nph (tx_ca_nph[(9*`NUM_VC)-1:0]),
.tx_ca_npd (tx_ca_npd[(13*`NUM_VC)-1:0]),
.tx_ca_cplh (tx_ca_cplh[(9*`NUM_VC)-1:0]),
.tx_ca_cpld (tx_ca_cpld[(13*`NUM_VC)-1:0]),
.tx_ca_p_recheck (tx_ca_p_recheck_vc0),
.tx_ca_cpl_recheck (tx_ca_cpl_recheck_vc0),
.tx_rdy (tx_rdy[`NUM_VC-1:0]),
//------- Outputs
.tx_req (tx_req[`NUM_VC-1:0]),
.tx_data (tx_data),
.tx_st (tx_st),
.tx_end (tx_end),
.tx_nlfy (tx_nlfy)
);
// =============================================================================
// TBRX (User Logic on RX side) Instantiations
// =============================================================================
tbrx u_tbrx [`NUM_VC-1:0] (
//----- Inputs
.sys_clk (sys_clk_125),
.rst_n (rst_n),
.rx_tc (tbrx_vc[(`NUM_VC*3)-1:0]),
.rx_data ( rx_data[(`NUM_VC*16)-1:0]),
.rx_st ( rx_st[`NUM_VC -1:0]),
.rx_end ( rx_end[`NUM_VC -1:0]),
`ifdef ECRC
.rx_ecrc_err ( rx_ecrc_err[`NUM_VC -1:0] ),
`endif
.rx_us_req ( rx_us_req[`NUM_VC -1:0] ),
.rx_malf_tlp ( rx_malf_tlp[`NUM_VC -1:0] ),
//------- Outputs
.tbrx_cmd_prsnt (tbrx_cmd_prsnt_int[`NUM_VC-1:0]),
.ph_buf_status (ph_buf_status[`NUM_VC-1:0]),
.pd_buf_status (pd_buf_status[`NUM_VC-1:0]),
.nph_buf_status (nph_buf_status[`NUM_VC-1:0]),
.npd_buf_status (npd_buf_status[`NUM_VC-1:0]),
.cplh_buf_status ( ),
.cpld_buf_status ( ),
.ph_processed (ph_processed[`NUM_VC-1:0]),
.pd_processed (pd_processed[`NUM_VC-1:0]),
.nph_processed (nph_processed[`NUM_VC-1:0]),
.npd_processed (npd_processed[`NUM_VC-1:0]),
.cplh_processed ( ),
.cpld_processed ( ),
.pd_num (pd_num[(8*`NUM_VC) -1:0]),
.npd_num (npd_num[(8*`NUM_VC) -1:0]),
.cpld_num ( ),
.INIT_PH_FC (INIT_PH_FC[(8*`NUM_VC)-1:0]),
.INIT_NPH_FC (INIT_NPH_FC[(8*`NUM_VC)-1:0]),
.INIT_CPLH_FC ( ),
.INIT_PD_FC (INIT_PD_FC[(12*`NUM_VC)-1:0]),
.INIT_NPD_FC (INIT_NPD_FC[(12*`NUM_VC)-1:0]),
.INIT_CPLD_FC ( )
);
// =============================================================================
// DUT
// =============================================================================
`USERNAME_EVAL_TOP u1_top(
//------- Clock and Reset
.refclkp ( clk_100),
.refclkn ( ~clk_100),
.rst_n ( rst_n ),
`ifdef Channel_0
.hdinp0 ( hdoutp_0_d ),
.hdinn0 ( hdoutn_0_d ),
.hdoutp0 ( hdoutp_0 ),
.hdoutn0 ( hdoutn_0 ),
`endif
`ifdef Channel_1
.hdinp1 ( hdoutp_0_d ),
.hdinn1 ( hdoutn_0_d ),
.hdoutp1 ( hdoutp_0 ),
.hdoutn1 ( hdoutn_0 ),
`endif
`ifdef Channel_2
.hdinp2 ( hdoutp_0_d ),
.hdinn2 ( hdoutn_0_d ),
.hdoutp2 ( hdoutp_0 ),
.hdoutn2 ( hdoutn_0 ),
`endif
`ifdef Channel_3
.hdinp3 ( hdoutp_0_d ),
.hdinn3 ( hdoutn_0_d ),
.hdoutp3 ( hdoutp_0 ),
.hdoutn3 ( hdoutn_0 ),
`endif
`ifdef WISHBONE
// Wishbone input Signals
.RST_I ( RST_I ),
.CLK_I ( CLK_I ),
.ADR_I ( ADR_I ),
.DAT_I ( DAT_I ),
.SEL_I ( SEL_I ),
.WE_I ( WE_I ),
.STB_I ( STB_I ),
.CYC_I ( CYC_I ),
.CHAIN_RDAT_in ( CHAIN_RDAT_in ),
.CHAIN_ACK_in ( CHAIN_ACK_in ),
`else
.no_pcie_train ( no_pcie_train ),
`endif
`ifdef EN_VC0
// To RXFC
// Following are Advertised during Initialization
.tx_req_vc0 (tx_req[0]),
.tx_data_vc0 (tx_data[16*1-1:0]),
.tx_st_vc0 (tx_st[0]),
.tx_end_vc0 (tx_end[0]),
.tx_nlfy_vc0 (tx_nlfy[0]),
.ph_buf_status_vc0 (ph_buf_status[0]),
.pd_buf_status_vc0 (pd_buf_status[0]),
.nph_buf_status_vc0 (nph_buf_status[0]),
.npd_buf_status_vc0 (npd_buf_status[0]),
.ph_processed_vc0 (ph_processed[0]),
.pd_processed_vc0 (pd_processed[0]),
.nph_processed_vc0 (nph_processed[0]),
.npd_processed_vc0 (npd_processed[0]),
`endif
`ifdef EN_VC1
// To RXFC
// Following are Advertised during Initialization
.tx_req_vc1 (tx_req[1]),
.tx_data_vc1 (tx_data[16*2-1:16]),
.tx_st_vc1 (tx_st[1]),
.tx_end_vc1 (tx_end[1]),
.tx_nlfy_vc1 (tx_nlfy[1]),
.ph_buf_status_vc1 (ph_buf_status[1]),
.pd_buf_status_vc1 (pd_buf_status[1]),
.nph_buf_status_vc1 (nph_buf_status[1]),
.npd_buf_status_vc1 (npd_buf_status[1]),
.ph_processed_vc1 (ph_processed[1]),
.pd_processed_vc1 (pd_processed[1]),
.nph_processed_vc1 (nph_processed[1]),
.npd_processed_vc1 (npd_processed[1]),
`endif
`ifdef EN_VC2
// To RXFC
// Following are Advertised during Initialization
.tx_req_vc2 (tx_req[2]),
.tx_data_vc2 (tx_data[16*3-1:16*2]),
.tx_st_vc2 (tx_st[2]),
.tx_end_vc2 (tx_end[2]),
.tx_nlfy_vc2 (tx_nlfy[2]),
.ph_buf_status_vc2 (ph_buf_status[2]),
.pd_buf_status_vc2 (pd_buf_status[2]),
.nph_buf_status_vc2 (nph_buf_status[2]),
.npd_buf_status_vc2 (npd_buf_status[2]),
.ph_processed_vc2 (ph_processed[2]),
.pd_processed_vc2 (pd_processed[2]),
.nph_processed_vc2 (nph_processed[2]),
.npd_processed_vc2 (npd_processed[2]),
`endif
`ifdef EN_VC3
// To RXFC
// Following are Advertised during Initialization
.tx_req_vc3 (tx_req[3]),
.tx_data_vc3 (tx_data[16*4-1:16*3]),
.tx_st_vc3 (tx_st[3]),
.tx_end_vc3 (tx_end[3]),
.tx_nlfy_vc3 (tx_nlfy[3]),
.ph_buf_status_vc3 (ph_buf_status[3]),
.pd_buf_status_vc3 (pd_buf_status[3]),
.nph_buf_status_vc3 (nph_buf_status[3]),
.npd_buf_status_vc3 (npd_buf_status[3]),
.ph_processed_vc3 (ph_processed[3]),
.pd_processed_vc3 (pd_processed[3]),
.nph_processed_vc3 (nph_processed[3]),
.npd_processed_vc3 (npd_processed[3]),
`endif
`ifdef EN_VC4
// To RXFC
// Following are Advertised during Initialization
.tx_req_vc4 (tx_req[4]),
.tx_data_vc4 (tx_data[16*5-1:16*4]),
.tx_st_vc4 (tx_st[4]),
.tx_end_vc4 (tx_end[4]),
.tx_nlfy_vc4 (tx_nlfy[4]),
.ph_buf_status_vc4 (ph_buf_status[4]),
.pd_buf_status_vc4 (pd_buf_status[4]),
.nph_buf_status_vc4 (nph_buf_status[4]),
.npd_buf_status_vc4 (npd_buf_status[4]),
.ph_processed_vc4 (ph_processed[4]),
.pd_processed_vc4 (pd_processed[4]),
.nph_processed_vc4 (nph_processed[4]),
.npd_processed_vc4 (npd_processed[4]),
`endif
`ifdef EN_VC5
// To RXFC
// Following are Advertised during Initialization
.tx_req_vc5 (tx_req[5]),
.tx_data_vc5 (tx_data[16*6-1:16*5]),
.tx_st_vc5 (tx_st[5]),
.tx_end_vc5 (tx_end[5]),
.tx_nlfy_vc5 (tx_nlfy[5]),
.ph_buf_status_vc5 (ph_buf_status[5]),
.pd_buf_status_vc5 (pd_buf_status[5]),
.nph_buf_status_vc5 (nph_buf_status[5]),
.npd_buf_status_vc5 (npd_buf_status[5]),
.ph_processed_vc5 (ph_processed[5]),
.pd_processed_vc5 (pd_processed[5]),
.nph_processed_vc5 (nph_processed[5]),
.npd_processed_vc5 (npd_processed[5]),
`endif
`ifdef EN_VC6
// To RXFC
// Following are Advertised during Initialization
.tx_req_vc6 (tx_req[6]),
.tx_data_vc6 (tx_data[16*7-1:16*6]),
.tx_st_vc6 (tx_st[6]),
.tx_end_vc6 (tx_end[6]),
.tx_nlfy_vc6 (tx_nlfy[6]),
.ph_buf_status_vc6 (ph_buf_status[6]),
.pd_buf_status_vc6 (pd_buf_status[6]),
.nph_buf_status_vc6 (nph_buf_status[6]),
.npd_buf_status_vc6 (npd_buf_status[6]),
.ph_processed_vc6 (ph_processed[6]),
.pd_processed_vc6 (pd_processed[6]),
.nph_processed_vc6 (nph_processed[6]),
.npd_processed_vc6 (npd_processed[6]),
`endif
`ifdef EN_VC7
// To RXFC
// Following are Advertised during Initialization
.tx_req_vc7 (tx_req[7]),
.tx_data_vc7 (tx_data[16*8-1:16*7]),
.tx_st_vc7 (tx_st[7]),
.tx_end_vc7 (tx_end[7]),
.tx_nlfy_vc7 (tx_nlfy[7]),
.ph_buf_status_vc7 (ph_buf_status[7]),
.pd_buf_status_vc7 (pd_buf_status[7]),
.nph_buf_status_vc7 (nph_buf_status[7]),
.npd_buf_status_vc7 (npd_buf_status[7]),
.ph_processed_vc7 (ph_processed[7]),
.pd_processed_vc7 (pd_processed[7]),
.nph_processed_vc7 (nph_processed[7]),
.npd_processed_vc7 (npd_processed[7]),
`endif
`ifdef ECRC
`ifdef AER
.ecrc_gen_enb ( ) ,
.ecrc_chk_enb ( ) ,
`else
.ecrc_gen_enb ( ecrc_gen_enb ) ,
.ecrc_chk_enb ( ecrc_chk_enb ) ,
`endif
`endif
`ifdef WISHBONE
// Wishbone output Signals
.DAT_O ( DAT_O),
.ACK_O ( ACK_O),
.IRQ_O ( IRQ_O),
`endif
`ifdef EN_VC0
// To TX User
`ifdef EN_VC1
.tcvc_map_vc0 ( ),
`endif
.tx_rdy_vc0 (tx_rdy[0]),
.tx_ca_ph_vc0 (tx_ca_ph[(9*1)-1:0]),
.tx_ca_pd_vc0 (tx_ca_pd[(13*1)-1:0]),
.tx_ca_nph_vc0 (tx_ca_nph[(9*1)-1:0]),
.tx_ca_npd_vc0 (tx_ca_npd[(13*1)-1:0]),
.tx_ca_cplh_vc0 (tx_ca_cplh[(9*1)-1:0]),
.tx_ca_cpld_vc0 (tx_ca_cpld[(13*1)-1:0]),
.tx_ca_p_recheck_vc0 ( tx_ca_p_recheck_vc0 ),
.tx_ca_cpl_recheck_vc0 ( tx_ca_cpl_recheck_vc0 ),
// Inputs/Outputs per VC
.rx_data_vc0 ( rx_data[(16*1)-1:0]),
.rx_st_vc0 ( rx_st[0]),
.rx_end_vc0 ( rx_end[0]),
`ifdef ECRC
.rx_ecrc_err_vc0 ( rx_ecrc_err[0] ),
`endif
.rx_us_req_vc0 ( rx_us_req[0] ),
.rx_malf_tlp_vc0 ( rx_malf_tlp[0] ),
`endif
`ifdef EN_VC1
// To TX User
.tcvc_map_vc1 ( ),
.tx_rdy_vc1 (tx_rdy[1]),
.tx_ca_ph_vc1 (tx_ca_ph[(9*2)-1:9]),
.tx_ca_pd_vc1 (tx_ca_pd[(13*2)-1:13]),
.tx_ca_nph_vc1 (tx_ca_nph[(9*2)-1:9]),
.tx_ca_npd_vc1 (tx_ca_npd[(13*2)-1:13]),
.tx_ca_cplh_vc1 (tx_ca_cplh[(9*2)-1:9]),
.tx_ca_cpld_vc1 (tx_ca_cpld[(13*2)-1:13]),
// Inputs/Outputs per VC
.rx_data_vc1 ( rx_data[(16*2)-1:16]),
.rx_st_vc1 ( rx_st[1]),
.rx_end_vc1 ( rx_end[1]),
`ifdef ECRC
.rx_ecrc_err_vc1 ( rx_ecrc_err[1] ),
`endif
.rx_us_req_vc1 ( rx_us_req[1] ),
.rx_malf_tlp_vc1 ( rx_malf_tlp[1] ),
`endif
`ifdef EN_VC2
// To TX User
.tcvc_map_vc2 ( ),
.tx_rdy_vc2 (tx_rdy[2]),
.tx_ca_ph_vc2 (tx_ca_ph[(9*3)-1:9*2]),
.tx_ca_pd_vc2 (tx_ca_pd[(13*3)-1:13*2]),
.tx_ca_nph_vc2 (tx_ca_nph[(9*3)-1:9*2]),
.tx_ca_npd_vc2 (tx_ca_npd[(13*3)-1:13*2]),
.tx_ca_cplh_vc2 (tx_ca_cplh[(9*3)-1:9*2]),
.tx_ca_cpld_vc2 (tx_ca_cpld[(13*3)-1:13*2]),
// Inputs/Outputs per VC
.rx_data_vc2 ( rx_data[(16*3)-1:16*2]),
.rx_st_vc2 ( rx_st[2]),
.rx_end_vc2 ( rx_end[2]),
`ifdef ECRC
.rx_ecrc_err_vc2 ( rx_ecrc_err[2] ),
`endif
.rx_us_req_vc2 ( rx_us_req[2] ),
.rx_malf_tlp_vc2 ( rx_malf_tlp[2] ),
`endif
`ifdef EN_VC3
// To TX User
.tcvc_map_vc3 ( ),
.tx_rdy_vc3 (tx_rdy[3]),
.tx_ca_ph_vc3 (tx_ca_ph[(9*4)-1:9*3]),
.tx_ca_pd_vc3 (tx_ca_pd[(13*4)-1:13*3]),
.tx_ca_nph_vc3 (tx_ca_nph[(9*4)-1:9*3]),
.tx_ca_npd_vc3 (tx_ca_npd[(13*4)-1:13*3]),
.tx_ca_cplh_vc3 (tx_ca_cplh[(9*4)-1:9*3]),
.tx_ca_cpld_vc3 (tx_ca_cpld[(13*4)-1:13*3]),
// Inputs/Outputs per VC
.rx_data_vc3 ( rx_data[(16*4)-1:16*3]),
.rx_st_vc3 ( rx_st[3]),
.rx_end_vc3 ( rx_end[3]),
`ifdef ECRC
.rx_ecrc_err_vc3 ( rx_ecrc_err[3] ),
`endif
.rx_us_req_vc3 ( rx_us_req[3] ),
.rx_malf_tlp_vc3 ( rx_malf_tlp[3] ),
`endif
`ifdef EN_VC4
// To TX User
.tcvc_map_vc4 ( ),
.tx_rdy_vc4 (tx_rdy[4]),
.tx_ca_ph_vc4 (tx_ca_ph[(9*5)-1:9*4]),
.tx_ca_pd_vc4 (tx_ca_pd[(13*5)-1:13*4]),
.tx_ca_nph_vc4 (tx_ca_nph[(9*5)-1:9*4]),
.tx_ca_npd_vc4 (tx_ca_npd[(13*5)-1:13*4]),
.tx_ca_cplh_vc4 (tx_ca_cplh[(9*5)-1:9*4]),
.tx_ca_cpld_vc4 (tx_ca_cpld[(13*5)-1:13*4]),
// Inputs/Outputs per VC
.rx_data_vc4 ( rx_data[(16*5)-1:16*4]),
.rx_st_vc4 ( rx_st[4]),
.rx_end_vc4 ( rx_end[4]),
`ifdef ECRC
.rx_ecrc_err_vc4 ( rx_ecrc_err[4] ),
`endif
.rx_us_req_vc4 ( rx_us_req[4] ),
.rx_malf_tlp_vc4 ( rx_malf_tlp[4] ),
`endif
`ifdef EN_VC5
// To TX User
.tcvc_map_vc5 ( ),
.tx_rdy_vc5 (tx_rdy[5]),
.tx_ca_ph_vc5 (tx_ca_ph[(9*6)-1:9*5]),
.tx_ca_pd_vc5 (tx_ca_pd[(13*6)-1:13*5]),
.tx_ca_nph_vc5 (tx_ca_nph[(9*6)-1:9*5]),
.tx_ca_npd_vc5 (tx_ca_npd[(13*6)-1:13*5]),
.tx_ca_cplh_vc5 (tx_ca_cplh[(9*6)-1:9*5]),
.tx_ca_cpld_vc5 (tx_ca_cpld[(13*6)-1:13*5]),
// Inputs/Outputs per VC
.rx_data_vc5 ( rx_data[(16*6)-1:16*5]),
.rx_st_vc5 ( rx_st[5]),
.rx_end_vc5 ( rx_end[5]),
`ifdef ECRC
.rx_ecrc_err_vc5 ( rx_ecrc_err[5] ),
`endif
.rx_us_req_vc5 ( rx_us_req[5] ),
.rx_malf_tlp_vc5 ( rx_malf_tlp[5] ),
`endif
`ifdef EN_VC6
// To TX User
.tcvc_map_vc6 ( ),
.tx_rdy_vc6 (tx_rdy[6]),
.tx_ca_ph_vc6 (tx_ca_ph[(9*7)-1:9*6]),
.tx_ca_pd_vc6 (tx_ca_pd[(13*7)-1:13*6]),
.tx_ca_nph_vc6 (tx_ca_nph[(9*7)-1:9*6]),
.tx_ca_npd_vc6 (tx_ca_npd[(13*7)-1:13*6]),
.tx_ca_cplh_vc6 (tx_ca_cplh[(9*7)-1:9*6]),
.tx_ca_cpld_vc6 (tx_ca_cpld[(13*7)-1:13*6]),
// Inputs/Outputs per VC
.rx_data_vc6 ( rx_data[(16*7)-1:16*6]),
.rx_st_vc6 ( rx_st[6]),
.rx_end_vc6 ( rx_end[6]),
`ifdef ECRC
.rx_ecrc_err_vc6 ( rx_ecrc_err[6] ),
`endif
.rx_us_req_vc6 ( rx_us_req[6] ),
.rx_malf_tlp_vc6 ( rx_malf_tlp[6] ),
`endif
`ifdef EN_VC7
// To TX User
.tcvc_map_vc7 ( ),
.tx_rdy_vc7 (tx_rdy[7]),
.tx_ca_ph_vc7 (tx_ca_ph[(9*8)-1:9*7]),
.tx_ca_pd_vc7 (tx_ca_pd[(13*8)-1:13*7]),
.tx_ca_nph_vc7 (tx_ca_nph[(9*8)-1:9*7]),
.tx_ca_npd_vc7 (tx_ca_npd[(13*8)-1:13*7]),
.tx_ca_cplh_vc7 (tx_ca_cplh[(9*8)-1:9*7]),
.tx_ca_cpld_vc7 (tx_ca_cpld[(13*8)-1:13*7]),
// Inputs/Outputs per VC
.rx_data_vc7 ( rx_data[(16*8)-1:16*7]),
.rx_st_vc7 ( rx_st[7]),
.rx_end_vc7 ( rx_end[7]),
`ifdef ECRC
.rx_ecrc_err_vc7 ( rx_ecrc_err[7] ),
`endif
.rx_us_req_vc7 ( rx_us_req[7] ),
.rx_malf_tlp_vc7 ( rx_malf_tlp[7] ),
`endif
// Datal Link Control SM Status
.dl_up ( dl_up ),
.sys_clk_125 ( sys_clk_125_temp )
);
// ====================================================================
// Initilize the design
// ====================================================================
initial begin
error = 1'b0;
rst_n = 1'b0;
clk_100 = 1'b0;
rx_tlp_discard = 0;
ecrc_gen_enb = 1'b0 ;
ecrc_chk_enb = 1'b0 ;
enb_log = 1'b0 ;
no_pcie_train = 1'b0;
end
// =============================================================================
// Timeout generation to finish hung test cases.
// =============================================================================
parameter TIMEOUT_NUM = 150000;
initial begin
repeat (TIMEOUT_NUM) @(posedge sys_clk_125);
$display(" ERROR : Simulation Time Out, Test case Terminated at time : %0t", $time) ;
$finish ;
end
// =============================================================================
// Simulation Time Display for long test cases
initial begin
forever begin
#100000; //every 10k (add extra zero - timescale) ns just display Time value - useful for SDF sim
$display(" Displaying Sim. Time : %0t", $time) ;
end
end
// =============================================================================
// Clocks generation
// =============================================================================
// 100 Mhz clock input to PLL to generate 125MHz for PCS
always #50 clk_100 <= ~clk_100 ;
`ifdef SDF_SIM
assign tb_sys_clk = tb_top.u1_top.pclk;
`else
assign tb_sys_clk = tb_top.u1_top.u1_pcs_pipe.PCLK;
`endif
`ifdef SDF_SIM
assign sys_clk_125 = u1_top.sys_clk_125;
`else
assign sys_clk_125 = sys_clk_125_temp;
`endif
// =============================================================================
// =============================================================================
//initial begin
// `ifdef SDF_SIM
// $sdf_annotate("../../../../par/ecp2m/config1/synplicity/top/verilog/pci_exp_x1_top.sdf", u1_top,, "pci_exp_x1_top_sdf.log");
// `endif
//end
// =============================================================================
// WISHBONE TASKS
// =============================================================================
`ifdef WISHBONE
initial begin
RST_I = 'd0 ;
CLK_I = 'd0 ;
ADR_I = 'd0 ;
DAT_I = 'd0 ;
SEL_I = 'd0 ;
WE_I = 'd0 ;
STB_I = 'd0 ;
CYC_I = 'd0 ;
end
always #40 CLK_I <= ~CLK_I ;
// =============================================================================
// Wishbone write task
// =============================================================================
task wb_write;
input [12:0] addr;
input [31:0] wr_data;
integer j;
begin
repeat (1) @(posedge CLK_I) ;
ADR_I <= addr ;
DAT_I <= wr_data ;
STB_I <= 1'b1 ;
CYC_I <= 1'b1 ;
WE_I <= 1'b1 ;
for (j=0; j<=20; j=j+1) begin
if (ACK_O) begin
$display("---INFO : Wishbone Write to Addr:%h, Data:%h at %0t", addr, wr_data, $time ) ;
STB_I <= 1'b0 ;
CYC_I <= 1'b0 ;
WE_I <= 1'b0 ;
j <= 100;
end
else if (j==20) begin
STB_I <= 1'b0 ;
CYC_I <= 1'b0 ;
WE_I <= 1'b0 ;
$display("---ERROR : Wishbone slave NOT responding at %0t", $time ) ;
end
repeat (1) @(posedge CLK_I) ;
end
end
endtask
// =============================================================================
// Wishbone read task
// =============================================================================
task wb_read;
input [12:0] addr;
output [31:0] rd_data;
integer i;
begin
repeat (1) @(posedge CLK_I) ;
ADR_I <= addr ;
STB_I <= 1'b1 ;
CYC_I <= 1'b1 ;
WE_I <= 1'b0 ;
for (i=0; i<=20; i=i+1) begin
if (ACK_O) begin
rd_data <= DAT_O ;
$display("---INFO : Wishbone Read to Addr:%h, Data:%h at %0t", addr, DAT_O, $time ) ;
STB_I <= 1'b0 ;
CYC_I <= 1'b0 ;
WE_I <= 1'b0 ;
i <= 100;
end
else if (i==20) begin
$display("---ERROR : Wishbone slave NOT responding at %0t", $time ) ;
STB_I <= 1'b0 ;
CYC_I <= 1'b0 ;
WE_I <= 1'b0 ;
end
repeat (1) @(posedge CLK_I) ;
end
end
endtask
`endif
// =============================================================================
// Reset Task
// =============================================================================
task RST_DUT;
begin
repeat(2) @(negedge clk_100);
#40000;
rst_n = 1'b1;
repeat (50) @ (posedge clk_100) ;
`ifdef SDF_SIM
force u1_top.core_rst_n = 1'b1; // de-assert delayed reset to core
`else
force u1_top.u1_dut.rst_n = 1'b1; // de-assert delayed reset to core
`endif
repeat(10) @(negedge clk_100);
`ifdef WISHBONE
wb_write (13'h1010, {2'd0, `ACKNAK_LAT_TIME, 6'd0, `SKP_INS_CNT}) ;
wb_write (13'h1014, {14'd0,`UPDATE_FREQ_PH, `UPDATE_FREQ_PD});
wb_write (13'h1018, {14'd0,`UPDATE_FREQ_NPH, `UPDATE_FREQ_NPD});
wb_write (13'h1020, {20'd0,`UPDATE_TIMER}) ;
`endif
end
endtask
// =============================================================================
// Reset Task
// =============================================================================
task DEFAULT_CREDITS;
reg [2:0] tmp_vcid;
begin
for(i=0; i<= `NUM_VC-1; i=i+1) begin
tmp_vcid = i;
case(tmp_vcid)
`ifdef EN_VC0
0 : begin
u_tbrx[0].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[0].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[0].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC1
1 : begin
u_tbrx[1].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[1].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[1].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC2
2 : begin
u_tbrx[2].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[2].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[2].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC3
3 : begin
u_tbrx[3].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[3].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[3].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC5
4 : begin
u_tbrx[4].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[4].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[4].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC5
5 : begin
u_tbrx[5].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[5].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[5].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC6
6 : begin
u_tbrx[6].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[6].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[6].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
`ifdef EN_VC7
7 : begin
u_tbrx[7].FC_INIT(P, 8'd127, 12'd2047);
u_tbrx[7].FC_INIT(NP, 8'd127, 12'd2047);
u_tbrx[7].FC_INIT(CPLX, 8'd127, 12'd2047);
end
`endif
endcase
end
end
endtask
// =============================================================================
// Check on error signal & stop simulation if error = 1
// =============================================================================
always @(posedge sys_clk_125) begin
if (error) begin
repeat (200) @(posedge sys_clk_125);
$finish;
end
end
// =============================================================================
// TBTX TASKS
// =============================================================================
// HEADER FORMAT FOR MEM READ
// (Fmt & Type decides what kind of Request)
// ================================================
// R Fmt Type R TC R R R R TD EP ATTR R Length
// Requester ID -- TAG -- Last DW BE -- First DW BE
// ---------- Address [63:32] -------------------
// --------- Address [31:2] ----------------- R
// ================================================
// Fixed values :
// Fmt[1] = 0
// First DW BE = 4'b0000
// Last DW BE = 4'b0000
// ATTR is always 2'b00 {Ordering, Snoop} = {0,0} -> {Strong Order, Snoop}
// Arguments :
// TC/VC, Address[31:2], Fmt[0]/hdr_Type, Length
// Registers that are used :
// TBTX_TD, TBTX_EP, First_DW_BE, TBTX_UPPER32_ADDR
// For hdr_type 4 DW TBTX_UPPER32_ADDR is used (and Fmt[0] = 1)
//
// NOTE : Length is not the LENGTH of this MEM_RD Pkt
// =============================================================================
task tbtx_mem_rd;
input [2:0] vcid;
input [31:0] addr;
input [9:0] length;
input hdr_type; //0: 3 DW Header --- 1: 4 DW (with TBTX_UPPER32_ADDR)
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_mem_rd(addr,length,hdr_type);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_mem_rd(addr,length,hdr_type);
`endif
endcase
end
endtask
// =============================================================================
// HEADER FORMAT FOR MEM WRITE
// (Fmt & Type decides what kind of Request)
// ================================================
// R Fmt Type R TC R R R R TD EP ATTR R Length
// Requester ID -- TAG -- Last DW BE -- First DW BE
// ---------- Address [63:32] -------------------
// --------- Address [31:2] ----------------- R
// ================================================
// Arguments :
// TC/VC, Address[31:2], Fmt[0]/hdr_Type
// Registers that are used :
// TBTX_TD, TBTX_EP, First_DW_BE, Last_DW_BE, TBTX_UPPER32_ADDR
// For hdr_type 4 DW TBTX_UPPER32_ADDR is used (and Fmt[0] = 1)
// =============================================================================
task tbtx_mem_wr;
input [2:0] vcid;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [9:0] nul_len;
input nullify;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_mem_wr(addr, length,hdr_type, nul_len, nullify);
`endif
endcase
end
endtask
// =============================================================================
task tbtx_msg;
input [2:0] vcid;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_msg;
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_msg;
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_msg;
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_msg;
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_msg;
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_msg;
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_msg;
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_msg;
`endif
endcase
end
endtask
// =============================================================================
task tbtx_msg_d;
input [2:0] vcid;
input [9:0] length;
input [9:0] nul_len;
input nullify;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_msg_d(length, nul_len, nullify);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_msg_d(length, nul_len, nullify);
`endif
endcase
end
endtask
// =============================================================================
task tbtx_cfg_rd;
input cfg; //0: cfg0, 1: cfg1
input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00}
begin
u_tbtx[0].tbtx_cfg_rd(cfg, addr);
end
endtask
// =============================================================================
task tbtx_cfg_wr;
input cfg; //0: cfg0, 1: cfg1
input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00}
begin
u_tbtx[0].tbtx_cfg_wr(cfg, addr);
end
endtask
// =============================================================================
task tbtx_io_rd;
input [31:0] addr;
begin
u_tbtx[0].tbtx_io_rd(addr);
end
endtask
// =============================================================================
task tbtx_io_wr;
input [31:0] addr;
begin
u_tbtx[0].tbtx_io_wr(addr);
end
endtask
// =============================================================================
task tbtx_cpl;
input [2:0] vcid;
input [11:0] byte_cnt;
input [6:0] lower_addr;
input [2:0] status;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_cpl(byte_cnt, lower_addr,status);
`endif
endcase
end
endtask
// =============================================================================
task tbtx_cpl_d;
input [2:0] vcid;
input [11:0] byte_cnt;
input [6:0] lower_addr;
input [2:0] status;
input [9:0] length;
input [9:0] nul_len;
input nullify;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbtx[0].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC1
1 : u_tbtx[1].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC2
2 : u_tbtx[2].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC3
3 : u_tbtx[3].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC4
4 : u_tbtx[4].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC5
5 : u_tbtx[5].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC6
6 : u_tbtx[6].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
`ifdef EN_VC7
7 : u_tbtx[7].tbtx_cpl_d(byte_cnt, lower_addr,status, length, nul_len, nullify);
`endif
endcase
end
endtask
// =============================================================================
// TBRX TASKS
// =============================================================================
// Error Types
// NO_TLP_ERR = 4'b0000;
// ECRC_ERR = 4'b0001;
// UNSUP_ERR = 4'b0010;
// MALF_ERR = 4'b0011;
// FMT_TYPE_ERR = 4'b1111;
// =============================================================================
// tbrx_tlp:
// This task is used when User wants create TLP manually
// For fmt_type error this should be used, no other tasks supports this error.
// =============================================================================
task tbrx_tlp; //When Giving Malformed TLP (Only fmt & Type error)
input [2:0] vcid;
input [3:0] Error_Type;
input hdr_type; //3 DW or 4 DW
input [31:0] h1_msb;
input [31:0] h1_lsb;
input [31:0] h2_msb;
input [31:0] h2_lsb;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_tlp(Error_Type, hdr_type, h1_msb, h1_lsb, h2_msb, h2_lsb);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_mem_rd;
input [2:0] vcid;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_mem_rd(addr,length,hdr_type,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_mem_wr;
input [2:0] vcid;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_mem_wr(addr,length,hdr_type,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_msg;
input [2:0] vcid;
input [9:0] length;
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_msg(length,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_msg(length,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_msg_d;
input [2:0] vcid;
input [9:0] length;
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_msg_d(length, Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_msg_d(length, Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_cfg_rd;
input cfg; //0: cfg0, 1: cfg1
input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00}
input [9:0] length;
input [3:0] Error_Type;
begin
u_tbrx[0].tbrx_cfg_rd(cfg, addr,length, Error_Type);
end
endtask
// =============================================================================
task tbrx_cfg_wr;
input cfg; //0: cfg0, 1: cfg1
input [31:0] addr; //{Bus No, Dev. No, Function No, 4'h0, Ext Reg No, Reg No, 2'b00}
input [9:0] length;
input [3:0] Error_Type;
begin
u_tbrx[0].tbrx_cfg_wr(cfg, addr,length, Error_Type);
end
endtask
// =============================================================================
task tbrx_io_rd;
input [31:0] addr;
input [9:0] length;
input [3:0] Error_Type;
begin
u_tbrx[0].tbrx_io_rd(addr,length, Error_Type);
end
endtask
// =============================================================================
task tbrx_io_wr;
input [31:0] addr;
input [9:0] length;
input [3:0] Error_Type;
begin
u_tbrx[0].tbrx_io_wr(addr,length, Error_Type);
end
endtask
// =============================================================================
task tbrx_cpl;
input [2:0] vcid;
input [11:0] byte_cnt;
input [6:0] lower_addr;
input [2:0] status;
input [9:0] length;
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_cpl(byte_cnt, lower_addr,status,length, Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_cpl_d;
input [2:0] vcid;
input [11:0] byte_cnt;
input [6:0] lower_addr;
input [2:0] status;
input [9:0] length;
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_cpl_d(byte_cnt, lower_addr,status, length,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
// TASKS WITH TC INPUT
// =============================================================================
task tbrx_mem_rd_tc;
input [2:0] vcid;
input [2:0] tc;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_mem_rd_tc(tc, addr,length,hdr_type,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
task tbrx_mem_wr_tc;
input [2:0] vcid;
input [2:0] tc;
input [31:0] addr;
input [9:0] length;
input hdr_type; //3 DW or 4 DW
input [3:0] Error_Type;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].tbrx_mem_wr_tc(tc, addr,length,hdr_type,Error_Type);
`endif
endcase
end
endtask
// =============================================================================
// FLOW CONTROL TASKS
// =============================================================================
// Setting INIT values
// =============================================================================
task FC_INIT;
input [2:0] vcid;
input [1:0] type; // p/np/cpl
input [7:0] hdr;
input [11:0] data;
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].FC_INIT(type, hdr, data);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].FC_INIT(type, hdr, data);
`endif
endcase
end
endtask
// =============================================================================
// Asserion/Deassertion of buf_status signals
// =============================================================================
task FC_BUF_STATUS;
input [2:0] vcid;
input [2:0] type; // ph/pd/nph/npd/cpl/cpld
input set; // Set=1: Assert the signal , Set=0, De-assert the signal
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].FC_BUF_STATUS(type, set);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].FC_BUF_STATUS(type, set);
`endif
endcase
end
endtask
// =============================================================================
// Asserion/Deassertion of Processed signals
// Onle pulse
// =============================================================================
task FC_PROCESSED;
input [2:0] vcid;
input [2:0] type; // ph/pd/nph/npd/cpl/cpld
input set; // Set=1: Assert the signal , Set=0, De-assert the signal
begin
case(vcid)
`ifdef EN_VC0
0 : u_tbrx[0].FC_PROCESSED(type);
`endif
`ifdef EN_VC1
1 : u_tbrx[1].FC_PROCESSED(type);
`endif
`ifdef EN_VC2
2 : u_tbrx[2].FC_PROCESSED(type);
`endif
`ifdef EN_VC3
3 : u_tbrx[3].FC_PROCESSED(type);
`endif
`ifdef EN_VC4
4 : u_tbrx[4].FC_PROCESSED(type);
`endif
`ifdef EN_VC5
5 : u_tbrx[5].FC_PROCESSED(type);
`endif
`ifdef EN_VC6
6 : u_tbrx[6].FC_PROCESSED(type);
`endif
`ifdef EN_VC7
7 : u_tbrx[7].FC_PROCESSED(type);
`endif
endcase
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3_TB_V
`define SKY130_FD_SC_LS__NAND3_TB_V
/**
* nand3: 3-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ls__nand3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3_TB_V
|
/* Generated by Yosys 0.7 (git sha1 61f6811, gcc 5.4.0-6ubuntu1~16.04.4 -O2 -fstack-protector-strong -fPIC -Os) */
(* top = 1 *)
(* src = "var25_multi.v:2" *)
module var25_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, valid);
wire _0000_;
wire _0001_;
wire _0002_;
wire _0003_;
wire _0004_;
wire _0005_;
wire _0006_;
wire _0007_;
wire _0008_;
wire _0009_;
wire _0010_;
wire _0011_;
wire _0012_;
wire _0013_;
wire _0014_;
wire _0015_;
wire _0016_;
wire _0017_;
wire _0018_;
wire _0019_;
wire _0020_;
wire _0021_;
wire _0022_;
wire _0023_;
wire _0024_;
wire _0025_;
wire _0026_;
wire _0027_;
wire _0028_;
wire _0029_;
wire _0030_;
wire _0031_;
wire _0032_;
wire _0033_;
wire _0034_;
wire _0035_;
wire _0036_;
wire _0037_;
wire _0038_;
wire _0039_;
wire _0040_;
wire _0041_;
wire _0042_;
wire _0043_;
wire _0044_;
wire _0045_;
wire _0046_;
wire _0047_;
wire _0048_;
wire _0049_;
wire _0050_;
wire _0051_;
wire _0052_;
wire _0053_;
wire _0054_;
wire _0055_;
wire _0056_;
wire _0057_;
wire _0058_;
wire _0059_;
wire _0060_;
wire _0061_;
wire _0062_;
wire _0063_;
wire _0064_;
wire _0065_;
wire _0066_;
wire _0067_;
wire _0068_;
wire _0069_;
wire _0070_;
wire _0071_;
wire _0072_;
wire _0073_;
wire _0074_;
wire _0075_;
wire _0076_;
wire _0077_;
wire _0078_;
wire _0079_;
wire _0080_;
wire _0081_;
wire _0082_;
wire _0083_;
wire _0084_;
wire _0085_;
wire _0086_;
wire _0087_;
wire _0088_;
wire _0089_;
wire _0090_;
wire _0091_;
wire _0092_;
wire _0093_;
wire _0094_;
wire _0095_;
wire _0096_;
wire _0097_;
wire _0098_;
wire _0099_;
wire _0100_;
wire _0101_;
wire _0102_;
wire _0103_;
wire _0104_;
wire _0105_;
wire _0106_;
wire _0107_;
wire _0108_;
wire _0109_;
wire _0110_;
wire _0111_;
wire _0112_;
wire _0113_;
wire _0114_;
wire _0115_;
wire _0116_;
wire _0117_;
wire _0118_;
wire _0119_;
wire _0120_;
wire _0121_;
wire _0122_;
wire _0123_;
wire _0124_;
wire _0125_;
wire _0126_;
wire _0127_;
wire _0128_;
wire _0129_;
wire _0130_;
wire _0131_;
wire _0132_;
wire _0133_;
wire _0134_;
wire _0135_;
wire _0136_;
wire _0137_;
wire _0138_;
wire _0139_;
wire _0140_;
wire _0141_;
wire _0142_;
wire _0143_;
wire _0144_;
wire _0145_;
wire _0146_;
wire _0147_;
wire _0148_;
wire _0149_;
wire _0150_;
wire _0151_;
wire _0152_;
wire _0153_;
wire _0154_;
wire _0155_;
wire _0156_;
wire _0157_;
wire _0158_;
wire _0159_;
wire _0160_;
wire _0161_;
wire _0162_;
wire _0163_;
wire _0164_;
wire _0165_;
wire _0166_;
wire _0167_;
wire _0168_;
wire _0169_;
wire _0170_;
wire _0171_;
wire _0172_;
wire _0173_;
wire _0174_;
wire _0175_;
wire _0176_;
wire _0177_;
wire _0178_;
wire _0179_;
wire _0180_;
wire _0181_;
wire _0182_;
wire _0183_;
wire _0184_;
wire _0185_;
wire _0186_;
wire _0187_;
wire _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire _0193_;
wire _0194_;
wire _0195_;
wire _0196_;
wire _0197_;
wire _0198_;
wire _0199_;
wire _0200_;
wire _0201_;
wire _0202_;
wire _0203_;
wire _0204_;
wire _0205_;
wire _0206_;
wire _0207_;
wire _0208_;
wire _0209_;
wire _0210_;
wire _0211_;
wire _0212_;
wire _0213_;
wire _0214_;
wire _0215_;
wire _0216_;
wire _0217_;
wire _0218_;
wire _0219_;
wire _0220_;
wire _0221_;
wire _0222_;
wire _0223_;
wire _0224_;
wire _0225_;
wire _0226_;
wire _0227_;
wire _0228_;
wire _0229_;
wire _0230_;
wire _0231_;
wire _0232_;
wire _0233_;
wire _0234_;
wire _0235_;
wire _0236_;
wire _0237_;
wire _0238_;
wire _0239_;
wire _0240_;
wire _0241_;
wire _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire _0259_;
wire _0260_;
wire _0261_;
wire _0262_;
wire _0263_;
wire _0264_;
wire _0265_;
wire _0266_;
wire _0267_;
wire _0268_;
wire _0269_;
wire _0270_;
wire _0271_;
wire _0272_;
wire _0273_;
wire _0274_;
wire _0275_;
wire _0276_;
wire _0277_;
wire _0278_;
wire _0279_;
wire _0280_;
wire _0281_;
wire _0282_;
wire _0283_;
wire _0284_;
wire _0285_;
wire _0286_;
wire _0287_;
wire _0288_;
wire _0289_;
wire _0290_;
wire _0291_;
wire _0292_;
wire _0293_;
wire _0294_;
wire _0295_;
wire _0296_;
wire _0297_;
wire _0298_;
wire _0299_;
wire _0300_;
wire _0301_;
wire _0302_;
wire _0303_;
wire _0304_;
wire _0305_;
wire _0306_;
wire _0307_;
wire _0308_;
wire _0309_;
wire _0310_;
wire _0311_;
wire _0312_;
wire _0313_;
wire _0314_;
wire _0315_;
wire _0316_;
wire _0317_;
wire _0318_;
wire _0319_;
wire _0320_;
wire _0321_;
wire _0322_;
wire _0323_;
wire _0324_;
wire _0325_;
wire _0326_;
wire _0327_;
wire _0328_;
wire _0329_;
wire _0330_;
wire _0331_;
wire _0332_;
wire _0333_;
wire _0334_;
wire _0335_;
wire _0336_;
wire _0337_;
wire _0338_;
wire _0339_;
wire _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
wire _0377_;
wire _0378_;
wire _0379_;
wire _0380_;
wire _0381_;
wire _0382_;
wire _0383_;
wire _0384_;
wire _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire _0392_;
wire _0393_;
wire _0394_;
wire _0395_;
wire _0396_;
wire _0397_;
wire _0398_;
wire _0399_;
wire _0400_;
wire _0401_;
wire _0402_;
wire _0403_;
wire _0404_;
wire _0405_;
wire _0406_;
wire _0407_;
wire _0408_;
wire _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
wire _0417_;
wire _0418_;
wire _0419_;
wire _0420_;
wire _0421_;
wire _0422_;
wire _0423_;
wire _0424_;
wire _0425_;
wire _0426_;
wire _0427_;
wire _0428_;
wire _0429_;
wire _0430_;
wire _0431_;
wire _0432_;
wire _0433_;
wire _0434_;
wire _0435_;
wire _0436_;
wire _0437_;
wire _0438_;
wire _0439_;
wire _0440_;
wire _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
wire _0445_;
wire _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
wire _0450_;
wire _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
wire _0455_;
wire _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
wire _0460_;
wire _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
wire _0465_;
wire _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
wire _0470_;
wire _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
wire _0475_;
wire _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
wire _0480_;
wire _0481_;
wire _0482_;
wire _0483_;
wire _0484_;
wire _0485_;
wire _0486_;
wire _0487_;
wire _0488_;
wire _0489_;
wire _0490_;
wire _0491_;
wire _0492_;
wire _0493_;
wire _0494_;
wire _0495_;
wire _0496_;
wire _0497_;
wire _0498_;
wire _0499_;
wire _0500_;
wire _0501_;
wire _0502_;
wire _0503_;
wire _0504_;
wire _0505_;
wire _0506_;
wire _0507_;
wire _0508_;
wire _0509_;
wire _0510_;
wire _0511_;
wire _0512_;
wire _0513_;
wire _0514_;
wire _0515_;
wire _0516_;
wire _0517_;
wire _0518_;
wire _0519_;
wire _0520_;
wire _0521_;
wire _0522_;
wire _0523_;
wire _0524_;
wire _0525_;
wire _0526_;
wire _0527_;
wire _0528_;
wire _0529_;
wire _0530_;
wire _0531_;
wire _0532_;
wire _0533_;
wire _0534_;
wire _0535_;
wire _0536_;
wire _0537_;
wire _0538_;
wire _0539_;
wire _0540_;
wire _0541_;
wire _0542_;
wire _0543_;
wire _0544_;
wire _0545_;
wire _0546_;
wire _0547_;
wire _0548_;
wire _0549_;
wire _0550_;
wire _0551_;
wire _0552_;
wire _0553_;
wire _0554_;
wire _0555_;
wire _0556_;
wire _0557_;
wire _0558_;
wire _0559_;
wire _0560_;
wire _0561_;
wire _0562_;
wire _0563_;
wire _0564_;
wire _0565_;
wire _0566_;
wire _0567_;
wire _0568_;
wire _0569_;
wire _0570_;
wire _0571_;
wire _0572_;
wire _0573_;
wire _0574_;
wire _0575_;
wire _0576_;
wire _0577_;
wire _0578_;
wire _0579_;
wire _0580_;
wire _0581_;
wire _0582_;
wire _0583_;
wire _0584_;
wire _0585_;
wire _0586_;
wire _0587_;
wire _0588_;
wire _0589_;
wire _0590_;
wire _0591_;
wire _0592_;
wire _0593_;
wire _0594_;
wire _0595_;
wire _0596_;
wire _0597_;
wire _0598_;
wire _0599_;
wire _0600_;
wire _0601_;
wire _0602_;
wire _0603_;
wire _0604_;
wire _0605_;
wire _0606_;
wire _0607_;
wire _0608_;
wire _0609_;
wire _0610_;
wire _0611_;
wire _0612_;
wire _0613_;
wire _0614_;
wire _0615_;
wire _0616_;
wire _0617_;
wire _0618_;
wire _0619_;
wire _0620_;
wire _0621_;
wire _0622_;
wire _0623_;
wire _0624_;
wire _0625_;
wire _0626_;
wire _0627_;
wire _0628_;
wire _0629_;
wire _0630_;
wire _0631_;
wire _0632_;
wire _0633_;
wire _0634_;
wire _0635_;
wire _0636_;
wire _0637_;
wire _0638_;
wire _0639_;
wire _0640_;
wire _0641_;
wire _0642_;
wire _0643_;
wire _0644_;
wire _0645_;
wire _0646_;
wire _0647_;
wire _0648_;
wire _0649_;
wire _0650_;
wire _0651_;
wire _0652_;
wire _0653_;
wire _0654_;
wire _0655_;
wire _0656_;
wire _0657_;
wire _0658_;
wire _0659_;
wire _0660_;
wire _0661_;
wire _0662_;
wire _0663_;
wire _0664_;
wire _0665_;
wire _0666_;
wire _0667_;
wire _0668_;
wire _0669_;
wire _0670_;
wire _0671_;
wire _0672_;
wire _0673_;
wire _0674_;
wire _0675_;
wire _0676_;
wire _0677_;
wire _0678_;
wire _0679_;
wire _0680_;
wire _0681_;
wire _0682_;
wire _0683_;
wire _0684_;
wire _0685_;
wire _0686_;
wire _0687_;
wire _0688_;
wire _0689_;
wire _0690_;
wire _0691_;
wire _0692_;
wire _0693_;
wire _0694_;
wire _0695_;
wire _0696_;
wire _0697_;
wire _0698_;
wire _0699_;
wire _0700_;
wire _0701_;
wire _0702_;
wire _0703_;
wire _0704_;
wire _0705_;
wire _0706_;
wire _0707_;
wire _0708_;
wire _0709_;
wire _0710_;
wire _0711_;
wire _0712_;
wire _0713_;
wire _0714_;
wire _0715_;
wire _0716_;
wire _0717_;
wire _0718_;
wire _0719_;
wire _0720_;
wire _0721_;
wire _0722_;
wire _0723_;
wire _0724_;
wire _0725_;
wire _0726_;
wire _0727_;
wire _0728_;
wire _0729_;
wire _0730_;
wire _0731_;
wire _0732_;
wire _0733_;
wire _0734_;
wire _0735_;
wire _0736_;
wire _0737_;
wire _0738_;
wire _0739_;
wire _0740_;
wire _0741_;
wire _0742_;
wire _0743_;
wire _0744_;
wire _0745_;
wire _0746_;
wire _0747_;
wire _0748_;
wire _0749_;
wire _0750_;
wire _0751_;
wire _0752_;
wire _0753_;
wire _0754_;
wire _0755_;
wire _0756_;
wire _0757_;
wire _0758_;
wire _0759_;
wire _0760_;
wire _0761_;
wire _0762_;
wire _0763_;
wire _0764_;
wire _0765_;
wire _0766_;
wire _0767_;
wire _0768_;
wire _0769_;
wire _0770_;
wire _0771_;
wire _0772_;
wire _0773_;
wire _0774_;
wire _0775_;
wire _0776_;
wire _0777_;
wire _0778_;
wire _0779_;
wire _0780_;
wire _0781_;
wire _0782_;
wire _0783_;
wire _0784_;
wire _0785_;
wire _0786_;
wire _0787_;
wire _0788_;
wire _0789_;
wire _0790_;
wire _0791_;
wire _0792_;
wire _0793_;
wire _0794_;
wire _0795_;
wire _0796_;
wire _0797_;
wire _0798_;
wire _0799_;
wire _0800_;
wire _0801_;
wire _0802_;
wire _0803_;
wire _0804_;
wire _0805_;
wire _0806_;
wire _0807_;
wire _0808_;
wire _0809_;
wire _0810_;
wire _0811_;
wire _0812_;
wire _0813_;
wire _0814_;
wire _0815_;
wire _0816_;
wire _0817_;
wire _0818_;
wire _0819_;
wire _0820_;
wire _0821_;
wire _0822_;
wire _0823_;
wire _0824_;
wire _0825_;
wire _0826_;
wire _0827_;
wire _0828_;
wire _0829_;
wire _0830_;
wire _0831_;
wire _0832_;
wire _0833_;
wire _0834_;
wire _0835_;
wire _0836_;
wire _0837_;
wire _0838_;
wire _0839_;
wire _0840_;
wire _0841_;
(* src = "var25_multi.v:3" *)
input A;
(* src = "var25_multi.v:3" *)
input B;
(* src = "var25_multi.v:3" *)
input C;
(* src = "var25_multi.v:3" *)
input D;
(* src = "var25_multi.v:3" *)
input E;
(* src = "var25_multi.v:3" *)
input F;
(* src = "var25_multi.v:3" *)
input G;
(* src = "var25_multi.v:3" *)
input H;
(* src = "var25_multi.v:3" *)
input I;
(* src = "var25_multi.v:3" *)
input J;
(* src = "var25_multi.v:3" *)
input K;
(* src = "var25_multi.v:3" *)
input L;
(* src = "var25_multi.v:3" *)
input M;
(* src = "var25_multi.v:3" *)
input N;
(* src = "var25_multi.v:3" *)
input O;
(* src = "var25_multi.v:3" *)
input P;
(* src = "var25_multi.v:3" *)
input Q;
(* src = "var25_multi.v:3" *)
input R;
(* src = "var25_multi.v:3" *)
input S;
(* src = "var25_multi.v:3" *)
input T;
(* src = "var25_multi.v:3" *)
input U;
(* src = "var25_multi.v:3" *)
input V;
(* src = "var25_multi.v:3" *)
input W;
(* src = "var25_multi.v:3" *)
input X;
(* src = "var25_multi.v:3" *)
input Y;
(* src = "var25_multi.v:4" *)
output valid;
assign _0170_ = ~T;
assign _0181_ = ~R;
assign _0192_ = ~K;
assign _0203_ = ~J;
assign _0214_ = ~(B | A);
assign _0225_ = B & A;
assign _0236_ = ~(_0225_ | _0214_);
assign _0247_ = _0236_ ^ _0203_;
assign _0258_ = _0247_ ^ _0192_;
assign _0279_ = _0258_ ^ M;
assign _0280_ = _0258_ & M;
assign _0291_ = _0247_ | _0192_;
assign _0302_ = J ? _0225_ : _0214_;
assign _0313_ = _0302_ ^ _0291_;
assign _0324_ = _0313_ ^ L;
assign _0335_ = _0324_ ^ _0280_;
assign _0356_ = _0335_ | _0279_;
assign _0357_ = _0356_ & O;
assign _0368_ = _0324_ & _0280_;
assign _0389_ = ~I;
assign _0390_ = ~D;
assign _0401_ = ~C;
assign _0412_ = _0225_ ^ _0401_;
assign _0423_ = _0412_ ^ _0390_;
assign _0434_ = _0423_ ^ G;
assign _0445_ = _0434_ ^ H;
assign _0456_ = _0445_ ^ _0389_;
assign _0467_ = _0214_ & J;
assign _0478_ = ~(_0467_ ^ _0456_);
assign _0489_ = _0478_ ^ K;
assign _0500_ = ~(_0302_ | _0291_);
assign _0511_ = _0313_ & L;
assign _0522_ = _0511_ | _0500_;
assign _0533_ = _0522_ ^ _0489_;
assign _0544_ = _0533_ ^ _0368_;
assign _0555_ = _0544_ ^ N;
assign _0566_ = _0555_ ^ _0357_;
assign _0577_ = ~P;
assign _0588_ = ~O;
assign _0599_ = _0279_ | _0588_;
assign _0610_ = _0599_ ^ _0335_;
assign _0621_ = ~(_0610_ | _0577_);
assign _0632_ = _0621_ ^ _0566_;
assign _0643_ = ~Q;
assign _0664_ = _0610_ ^ _0577_;
assign _0665_ = ~(_0664_ | _0643_);
assign _0676_ = _0665_ ^ _0632_;
assign _0687_ = _0676_ ^ _0181_;
assign _0698_ = _0687_ ^ S;
assign _0709_ = _0698_ ^ _0170_;
assign _0720_ = _0279_ ^ _0588_;
assign _0731_ = _0720_ | _0170_;
assign _0742_ = _0664_ ^ _0643_;
assign _0753_ = _0742_ ^ _0731_;
assign _0764_ = _0753_ & U;
assign _0775_ = _0764_ & _0709_;
assign _0786_ = _0687_ & S;
assign _0797_ = _0676_ | _0181_;
assign _0808_ = ~(_0664_ & Q);
assign _0818_ = ~(_0808_ | _0566_);
assign _0829_ = _0632_ & Q;
assign _0830_ = ~(_0829_ | _0818_);
assign _0831_ = ~(_0533_ & _0368_);
assign _0832_ = ~M;
assign _0833_ = _0489_ & _0511_;
assign _0834_ = ~((_0478_ & K) | _0500_);
assign _0835_ = ~(_0467_ & _0456_);
assign _0836_ = ~(_0445_ | _0389_);
assign _0837_ = _0412_ | _0390_;
assign _0838_ = D & C;
assign _0839_ = _0838_ & _0236_;
assign _0840_ = _0225_ & _0401_;
assign _0841_ = _0840_ | _0214_;
assign _0000_ = ~((_0841_ & _0837_) | _0839_);
assign _0001_ = _0000_ ^ F;
assign _0002_ = _0423_ & G;
assign _0003_ = ~((_0434_ & H) | _0002_);
assign _0004_ = ~(_0003_ ^ _0001_);
assign _0005_ = _0004_ ^ _0836_;
assign _0006_ = _0005_ ^ _0835_;
assign _0007_ = _0006_ ^ _0834_;
assign _0008_ = _0007_ ^ _0833_;
assign _0009_ = _0008_ ^ _0832_;
assign _0010_ = _0009_ ^ _0831_;
assign _0011_ = ~(_0010_ & N);
assign _0012_ = _0011_ | _0544_;
assign _0013_ = ~(_0544_ & N);
assign _0014_ = _0008_ ^ M;
assign _0015_ = ~(_0014_ | _0013_);
assign _0016_ = ~(_0010_ | N);
assign _0017_ = ~(_0016_ | _0015_);
assign _0018_ = _0017_ & _0012_;
assign _0019_ = _0555_ & _0357_;
assign _0020_ = _0621_ & _0566_;
assign _0021_ = ~(_0020_ | _0019_);
assign _0022_ = _0021_ ^ _0018_;
assign _0023_ = _0022_ ^ _0643_;
assign _0024_ = _0023_ ^ _0830_;
assign _0025_ = _0024_ ^ _0797_;
assign _0026_ = _0025_ ^ T;
assign _0027_ = _0026_ ^ _0786_;
assign _0028_ = ~(_0698_ | _0170_);
assign _0029_ = ~(_0742_ | _0731_);
assign _0030_ = _0029_ & _0709_;
assign _0031_ = _0030_ | _0028_;
assign _0032_ = _0031_ ^ _0027_;
assign _0033_ = _0032_ & _0775_;
assign _0034_ = _0030_ & _0027_;
assign _0035_ = _0025_ & T;
assign _0036_ = _0035_ | _0028_;
assign _0037_ = _0036_ | _0034_;
assign _0038_ = ~(_0022_ & _0818_);
assign _0039_ = ~(_0022_ | _0643_);
assign _0040_ = ~(_0039_ | _0829_);
assign _0041_ = _0040_ & _0038_;
assign _0042_ = _0018_ & _0020_;
assign _0043_ = _0018_ & _0019_;
assign _0044_ = ~((_0014_ | _0013_) & _0011_);
assign _0045_ = ~(_0008_ & M);
assign _0046_ = ~((_0009_ | _0831_) & _0045_);
assign _0047_ = _0007_ & _0833_;
assign _0048_ = ~(_0006_ | _0834_);
assign _0049_ = ~((_0004_ | _0445_) & I);
assign _0050_ = ~(_0001_ & _0002_);
assign _0051_ = ~F;
assign _0052_ = _0000_ | _0051_;
assign _0053_ = ~(_0839_ | _0214_);
assign _0054_ = _0053_ ^ _0052_;
assign _0055_ = _0054_ ^ _0050_;
assign _0056_ = _0434_ & H;
assign _0057_ = ~(_0001_ & _0056_);
assign _0058_ = _0057_ & H;
assign _0059_ = _0058_ ^ _0055_;
assign _0060_ = ~(_0059_ ^ _0049_);
assign _0061_ = ~_0004_;
assign _0062_ = _0456_ & _0214_;
assign _0063_ = ~((_0062_ & _0061_) | _0203_);
assign _0064_ = _0063_ ^ _0060_;
assign _0065_ = _0064_ ^ _0048_;
assign _0066_ = _0065_ ^ _0047_;
assign _0067_ = _0066_ ^ _0046_;
assign _0068_ = _0067_ ^ N;
assign _0069_ = _0068_ ^ _0044_;
assign _0070_ = _0069_ ^ O;
assign _0071_ = _0070_ ^ _0043_;
assign _0072_ = _0071_ ^ P;
assign _0073_ = _0072_ ^ _0042_;
assign _0074_ = _0073_ ^ _0643_;
assign _0075_ = _0074_ ^ _0041_;
assign _0076_ = ~_0676_;
assign _0077_ = ~((_0024_ & _0076_) | _0181_);
assign _0078_ = ~(_0077_ ^ _0075_);
assign _0079_ = ~(_0024_ & _0786_);
assign _0080_ = _0079_ ^ _0078_;
assign _0081_ = _0080_ ^ _0037_;
assign _0082_ = _0081_ ^ U;
assign _0083_ = _0082_ ^ _0033_;
assign _0084_ = _0083_ ^ V;
assign _0085_ = _0084_ & W;
assign _0086_ = _0753_ ^ U;
assign _0087_ = _0086_ & W;
assign _0088_ = ~_0087_;
assign _0089_ = ~(_0764_ | _0029_);
assign _0090_ = _0089_ ^ _0709_;
assign _0091_ = ~(_0090_ | _0088_);
assign _0092_ = _0032_ ^ _0775_;
assign _0093_ = ~((_0092_ & W) | _0091_);
assign _0094_ = ~_0093_;
assign _0095_ = _0084_ ^ W;
assign _0096_ = _0095_ & _0094_;
assign _0097_ = _0096_ | _0085_;
assign _0098_ = _0083_ & V;
assign _0099_ = _0081_ & U;
assign _0100_ = _0082_ & _0033_;
assign _0101_ = _0100_ | _0099_;
assign _0102_ = _0080_ & _0037_;
assign _0103_ = _0077_ & _0075_;
assign _0104_ = ~(_0073_ & Q);
assign _0105_ = ~((_0074_ | _0041_) & _0104_);
assign _0106_ = _0071_ & P;
assign _0107_ = _0072_ & _0042_;
assign _0108_ = _0107_ | _0106_;
assign _0109_ = _0069_ & O;
assign _0110_ = _0070_ & _0043_;
assign _0111_ = _0110_ | _0109_;
assign _0112_ = _0067_ & N;
assign _0113_ = _0068_ & _0044_;
assign _0114_ = _0113_ | _0112_;
assign _0115_ = _0066_ & _0046_;
assign _0116_ = _0065_ & _0047_;
assign _0117_ = ~_0049_;
assign _0118_ = ~(_0059_ & _0117_);
assign _0119_ = ~(_0055_ & H);
assign _0120_ = ~(_0119_ & _0057_);
assign _0121_ = ~(_0054_ | _0050_);
assign _0122_ = _0839_ | _0225_;
assign _0123_ = _0053_ | _0000_;
assign _0124_ = _0123_ & F;
assign _0125_ = _0124_ ^ _0122_;
assign _0126_ = _0125_ ^ _0121_;
assign _0127_ = _0126_ ^ _0120_;
assign _0128_ = _0127_ ^ _0118_;
assign _0129_ = ~(_0063_ & _0060_);
assign _0130_ = ~(_0064_ & _0048_);
assign _0131_ = _0130_ & _0129_;
assign _0132_ = _0131_ ^ _0128_;
assign _0133_ = _0132_ ^ _0116_;
assign _0134_ = _0133_ ^ _0115_;
assign _0135_ = _0134_ ^ _0114_;
assign _0136_ = _0135_ ^ _0111_;
assign _0137_ = _0136_ ^ _0108_;
assign _0138_ = _0137_ ^ _0105_;
assign _0139_ = _0138_ ^ _0103_;
assign _0140_ = ~S;
assign _0141_ = _0024_ & _0687_;
assign _0142_ = ~((_0141_ & _0078_) | _0140_);
assign _0143_ = _0142_ ^ _0139_;
assign _0144_ = ~(_0143_ | _0102_);
assign _0145_ = _0143_ & _0102_;
assign _0146_ = ~(_0145_ | _0144_);
assign _0147_ = _0146_ ^ _0101_;
assign _0148_ = _0147_ ^ _0098_;
assign _0149_ = _0148_ & _0097_;
assign _0150_ = _0090_ ^ _0087_;
assign _0151_ = _0086_ ^ W;
assign _0152_ = _0720_ ^ _0170_;
assign _0153_ = ~((_0152_ | _0151_) & X);
assign _0154_ = _0153_ | _0150_;
assign _0155_ = ~W;
assign _0156_ = _0091_ | _0155_;
assign _0157_ = _0156_ ^ _0092_;
assign _0158_ = _0157_ | _0154_;
assign _0159_ = ~Y;
assign _0160_ = ~X;
assign _0161_ = ~(_0152_ | _0160_);
assign _0162_ = _0152_ & _0160_;
assign _0163_ = _0162_ | _0161_;
assign _0164_ = _0163_ & _0159_;
assign _0165_ = ~_0161_;
assign _0166_ = ~(_0162_ | _0159_);
assign _0167_ = _0151_ ? _0165_ : _0166_;
assign _0168_ = _0153_ ^ _0150_;
assign _0169_ = _0163_ | _0151_;
assign _0171_ = _0169_ & Y;
assign _0172_ = ~((_0171_ | _0168_) & (_0167_ | _0164_));
assign _0173_ = ~((_0172_ | _0157_) & _0159_);
assign _0174_ = _0157_ ^ _0154_;
assign _0175_ = ~(_0169_ & _0168_);
assign _0176_ = ~(_0175_ & _0172_);
assign _0177_ = ~((_0176_ | _0174_) & _0173_);
assign _0178_ = ~((_0177_ & _0158_) | _0149_);
assign _0179_ = _0095_ ^ _0093_;
assign _0180_ = _0177_ | _0158_;
assign _0182_ = ~(_0148_ | _0097_);
assign _0183_ = ~((_0180_ & _0179_) | _0182_);
assign _0184_ = ~(Q ^ J);
assign _0185_ = _0184_ & R;
assign _0186_ = ~H;
assign _0187_ = G ^ E;
assign _0188_ = ~(_0187_ | _0186_);
assign _0189_ = _0187_ & _0186_;
assign _0190_ = ~(_0189_ | _0188_);
assign _0191_ = _0190_ ^ I;
assign _0193_ = _0191_ ^ J;
assign _0194_ = _0193_ & K;
assign _0195_ = G & E;
assign _0196_ = ~_0195_;
assign _0197_ = ~(D | A);
assign _0198_ = D & A;
assign _0199_ = ~(_0198_ | _0197_);
assign _0200_ = _0199_ ^ _0051_;
assign _0201_ = _0200_ ^ _0196_;
assign _0202_ = ~(_0189_ | _0389_);
assign _0204_ = ~(_0202_ | _0188_);
assign _0205_ = _0204_ ^ _0201_;
assign _0206_ = ~_0205_;
assign _0207_ = _0191_ & J;
assign _0208_ = _0205_ ^ _0207_;
assign _0209_ = _0194_ ? _0206_ : _0208_;
assign _0210_ = ~_0209_;
assign _0211_ = ~N;
assign _0212_ = _0193_ ^ K;
assign _0213_ = ~(_0212_ | _0211_);
assign _0215_ = _0212_ ^ _0211_;
assign _0216_ = _0215_ & O;
assign _0217_ = ~(_0216_ | _0213_);
assign _0218_ = _0217_ ^ _0210_;
assign _0219_ = Q & _0203_;
assign _0220_ = _0215_ ^ O;
assign _0221_ = ~(_0220_ | _0577_);
assign _0222_ = ~(_0220_ & _0577_);
assign _0223_ = ~((_0222_ & _0219_) | _0221_);
assign _0224_ = _0223_ ^ _0218_;
assign _0226_ = _0220_ ^ _0577_;
assign _0227_ = ~(_0226_ & _0185_);
assign _0228_ = ~_0226_;
assign _0229_ = ~(_0224_ | _0228_);
assign _0230_ = ~((_0229_ & _0185_) | (_0227_ & _0224_));
assign _0231_ = _0184_ ^ R;
assign _0232_ = ~(_0231_ | _0140_);
assign _0233_ = ~_0232_;
assign _0234_ = _0185_ | _0219_;
assign _0235_ = _0234_ ^ _0226_;
assign _0237_ = ~(_0235_ | _0233_);
assign _0238_ = ~(_0237_ | _0140_);
assign _0239_ = _0238_ ^ _0230_;
assign _0240_ = _0235_ ^ _0233_;
assign _0241_ = _0231_ ^ _0140_;
assign _0242_ = ~(_0241_ | _0240_);
assign _0243_ = ~((_0242_ & _0239_) | _0170_);
assign _0244_ = _0238_ & _0230_;
assign _0245_ = _0226_ & _0203_;
assign _0246_ = _0245_ & _0218_;
assign _0248_ = ~(_0246_ | _0643_);
assign _0249_ = _0210_ & _0216_;
assign _0250_ = _0210_ & _0213_;
assign _0251_ = ~L;
assign _0252_ = ~_0201_;
assign _0253_ = ~((_0252_ & _0190_) | _0389_);
assign _0254_ = ~_0253_;
assign _0255_ = _0200_ | _0196_;
assign _0256_ = ~(_0199_ | _0051_);
assign _0257_ = ~E;
assign _0259_ = _0198_ ^ B;
assign _0260_ = _0259_ ^ _0257_;
assign _0261_ = _0260_ ^ _0256_;
assign _0262_ = ~(_0261_ ^ _0255_);
assign _0263_ = ~(_0201_ | _0187_);
assign _0264_ = _0263_ & _0262_;
assign _0265_ = ~((_0263_ & H) | _0262_);
assign _0266_ = ~((_0264_ & H) | _0265_);
assign _0267_ = _0266_ ^ _0254_;
assign _0268_ = ~((_0194_ | _0207_) & _0205_);
assign _0269_ = _0268_ ^ _0267_;
assign _0270_ = _0269_ ^ _0251_;
assign _0271_ = _0270_ ^ _0250_;
assign _0272_ = _0271_ ^ _0249_;
assign _0273_ = ~(_0218_ & _0221_);
assign _0274_ = _0273_ ^ _0272_;
assign _0275_ = ~(_0274_ ^ _0248_);
assign _0276_ = ~((_0229_ & _0184_) | _0181_);
assign _0277_ = _0276_ ^ _0275_;
assign _0278_ = _0277_ ^ _0244_;
assign _0281_ = ~(_0278_ & _0243_);
assign _0282_ = _0230_ ? _0237_ : S;
assign _0283_ = ~((_0277_ & S) | _0282_);
assign _0284_ = _0276_ & _0275_;
assign _0285_ = ~_0248_;
assign _0286_ = ~(_0274_ | _0285_);
assign _0287_ = _0271_ & _0249_;
assign _0288_ = _0270_ & _0250_;
assign _0289_ = ~(_0269_ | _0251_);
assign _0290_ = ~(_0266_ | _0254_);
assign _0292_ = ~(_0264_ | _0186_);
assign _0293_ = ~(_0261_ | _0255_);
assign _0294_ = ~(_0259_ & E);
assign _0295_ = E & D;
assign _0296_ = _0295_ & _0236_;
assign _0297_ = _0225_ | _0390_;
assign _0298_ = ~((_0297_ & _0294_) | _0296_);
assign _0299_ = ~_0199_;
assign _0300_ = ~((_0260_ & _0299_) | _0051_);
assign _0301_ = _0300_ ^ _0298_;
assign _0303_ = _0301_ ^ G;
assign _0304_ = _0303_ ^ _0293_;
assign _0305_ = _0304_ ^ _0292_;
assign _0306_ = _0305_ ^ _0290_;
assign _0307_ = _0205_ & _0191_;
assign _0308_ = ~_0267_;
assign _0309_ = ~((_0308_ & _0307_) | _0203_);
assign _0310_ = _0309_ ^ _0306_;
assign _0311_ = _0205_ & _0193_;
assign _0312_ = _0311_ & _0308_;
assign _0314_ = _0312_ & K;
assign _0315_ = _0314_ ^ _0310_;
assign _0316_ = _0315_ ^ _0289_;
assign _0317_ = _0316_ ^ M;
assign _0318_ = _0317_ ^ N;
assign _0319_ = _0318_ ^ _0288_;
assign _0320_ = _0319_ ^ O;
assign _0321_ = _0320_ ^ _0287_;
assign _0322_ = ~_0272_;
assign _0323_ = ~_0220_;
assign _0325_ = _0218_ & _0323_;
assign _0326_ = ~((_0325_ & _0322_) | _0577_);
assign _0327_ = _0326_ ^ _0321_;
assign _0328_ = _0327_ ^ _0286_;
assign _0329_ = _0328_ ^ _0284_;
assign _0330_ = _0329_ ^ S;
assign _0331_ = _0330_ ^ _0283_;
assign _0332_ = ~((_0331_ | _0170_) & _0281_);
assign _0333_ = ~(_0329_ & S);
assign _0334_ = ~(_0329_ | S);
assign _0336_ = ~((_0334_ | _0283_) & _0333_);
assign _0337_ = _0327_ & _0286_;
assign _0338_ = _0326_ & _0321_;
assign _0339_ = _0319_ & O;
assign _0340_ = _0320_ & _0287_;
assign _0341_ = _0340_ | _0339_;
assign _0342_ = _0317_ & N;
assign _0343_ = _0318_ & _0288_;
assign _0344_ = _0343_ | _0342_;
assign _0345_ = ~_0310_;
assign _0346_ = ~((_0312_ & _0345_) | _0192_);
assign _0347_ = _0309_ & _0306_;
assign _0348_ = _0301_ & G;
assign _0349_ = ~((_0303_ & _0293_) | _0348_);
assign _0350_ = _0225_ & D;
assign _0351_ = _0296_ | _0350_;
assign _0352_ = ~((_0300_ & _0298_) | _0351_);
assign _0353_ = ~(_0352_ ^ _0349_);
assign _0354_ = _0304_ & _0292_;
assign _0355_ = ~((_0305_ & _0290_) | _0354_);
assign _0358_ = _0355_ ^ _0353_;
assign _0359_ = _0358_ ^ _0347_;
assign _0360_ = _0359_ ^ _0346_;
assign _0361_ = _0315_ & _0289_;
assign _0362_ = _0316_ & M;
assign _0363_ = _0362_ | _0361_;
assign _0364_ = _0363_ ^ _0360_;
assign _0365_ = _0364_ ^ _0344_;
assign _0366_ = _0365_ ^ _0341_;
assign _0367_ = _0366_ ^ _0338_;
assign _0369_ = ~_0367_;
assign _0370_ = ~(_0328_ & _0284_);
assign _0371_ = ~(_0367_ ^ _0370_);
assign _0372_ = _0337_ ? _0369_ : _0371_;
assign _0373_ = _0372_ ^ _0336_;
assign _0374_ = _0373_ ^ _0332_;
assign _0375_ = _0278_ ^ _0243_;
assign _0376_ = _0281_ & T;
assign _0377_ = ~(_0376_ ^ _0331_);
assign _0378_ = _0377_ | _0375_;
assign _0379_ = _0378_ & U;
assign _0380_ = _0379_ & _0374_;
assign _0381_ = _0373_ & _0332_;
assign _0382_ = _0372_ & _0336_;
assign _0383_ = ~(_0369_ | _0370_);
assign _0384_ = _0367_ & _0337_;
assign _0385_ = _0364_ & _0344_;
assign _0386_ = _0360_ & _0362_;
assign _0387_ = _0360_ & _0361_;
assign _0388_ = _0359_ & _0346_;
assign _0391_ = ~(_0352_ | _0349_);
assign _0392_ = ~(_0355_ | _0353_);
assign _0393_ = ~(_0392_ | _0391_);
assign _0394_ = ~_0393_;
assign _0395_ = ~((_0358_ & _0347_) | _0394_);
assign _0396_ = ~(_0395_ ^ _0388_);
assign _0397_ = _0396_ ^ _0387_;
assign _0398_ = _0397_ ^ _0386_;
assign _0399_ = _0398_ ^ _0385_;
assign _0400_ = ~_0399_;
assign _0402_ = _0365_ & _0341_;
assign _0403_ = ~((_0366_ & _0338_) | _0402_);
assign _0404_ = _0403_ ^ _0400_;
assign _0405_ = _0404_ ^ _0384_;
assign _0406_ = _0405_ ^ _0383_;
assign _0407_ = _0406_ ^ _0382_;
assign _0408_ = _0407_ ^ _0381_;
assign _0409_ = _0408_ ^ _0380_;
assign _0410_ = ~(_0241_ | _0170_);
assign _0411_ = ~V;
assign _0413_ = _0241_ & _0170_;
assign _0414_ = ~(_0413_ | _0411_);
assign _0415_ = ~(_0414_ | _0410_);
assign _0416_ = _0415_ ^ _0240_;
assign _0417_ = ~(_0416_ | _0155_);
assign _0418_ = ~_0240_;
assign _0419_ = ~(_0413_ | _0410_);
assign _0420_ = ~((_0419_ & _0418_) | _0411_);
assign _0421_ = ~(_0410_ & _0418_);
assign _0422_ = _0421_ ^ _0239_;
assign _0424_ = _0422_ ^ _0420_;
assign _0425_ = ~(_0424_ & _0417_);
assign _0426_ = _0422_ & _0420_;
assign _0427_ = ~_0426_;
assign _0428_ = ~U;
assign _0429_ = _0375_ ^ _0428_;
assign _0430_ = _0429_ ^ _0427_;
assign _0431_ = ~_0430_;
assign _0432_ = _0430_ ^ _0425_;
assign _0433_ = _0419_ ^ _0411_;
assign _0435_ = _0433_ & X;
assign _0436_ = _0416_ ^ _0155_;
assign _0437_ = _0424_ | _0417_;
assign _0438_ = _0425_ & X;
assign _0439_ = ~((_0438_ & _0437_) | (_0436_ & _0435_));
assign _0440_ = _0439_ & _0432_;
assign _0441_ = ~((_0431_ | _0425_) & _0440_);
assign _0442_ = _0441_ & _0409_;
assign _0443_ = ~(_0429_ | _0427_);
assign _0444_ = ~(_0375_ | _0428_);
assign _0446_ = _0377_ ^ _0444_;
assign _0447_ = ~(_0446_ & _0443_);
assign _0448_ = ~(_0379_ ^ _0374_);
assign _0449_ = ~(_0448_ & _0447_);
assign _0450_ = _0446_ ^ _0443_;
assign _0451_ = _0450_ | W;
assign _0452_ = _0451_ & _0449_;
assign _0453_ = _0452_ & _0442_;
assign _0454_ = _0408_ & _0380_;
assign _0455_ = ~(_0448_ | _0447_);
assign _0457_ = ~((_0450_ & W) | _0455_);
assign _0458_ = ~(_0449_ & _0409_);
assign _0459_ = ~(_0404_ & _0384_);
assign _0460_ = _0403_ | _0400_;
assign _0461_ = ~(_0397_ & _0386_);
assign _0462_ = ~((_0396_ & _0387_) | (_0394_ & _0388_));
assign _0463_ = ~(_0462_ & _0461_);
assign _0464_ = ~((_0398_ & _0385_) | _0463_);
assign _0465_ = _0464_ & _0460_;
assign _0466_ = ~(_0465_ & _0459_);
assign _0468_ = ~((_0405_ & _0383_) | _0466_);
assign _0469_ = _0406_ & _0382_;
assign _0470_ = ~((_0407_ & _0381_) | _0469_);
assign _0471_ = _0470_ & _0468_;
assign _0472_ = ~((_0458_ | _0457_) & _0471_);
assign _0473_ = _0472_ | _0454_;
assign _0474_ = ~_0144_;
assign _0475_ = _0082_ | _0033_;
assign _0476_ = _0475_ & V;
assign _0477_ = ~((_0474_ | _0099_) & _0476_);
assign _0479_ = E ^ C;
assign _0480_ = _0479_ ^ H;
assign _0481_ = _0480_ ^ K;
assign _0482_ = _0481_ ^ L;
assign _0483_ = _0482_ ^ _0643_;
assign _0484_ = ~(_0483_ | _0140_);
assign _0485_ = ~(_0482_ | _0643_);
assign _0486_ = ~_0485_;
assign _0487_ = _0481_ & L;
assign _0488_ = _0480_ & K;
assign _0490_ = ~((_0479_ & H) | _0488_);
assign _0491_ = ~G;
assign _0492_ = E ^ D;
assign _0493_ = C ? _0390_ : _0492_;
assign _0494_ = _0493_ ^ _0491_;
assign _0495_ = _0494_ ^ _0490_;
assign _0496_ = _0495_ ^ _0487_;
assign _0497_ = _0496_ ^ _0211_;
assign _0498_ = _0497_ ^ _0588_;
assign _0499_ = _0498_ ^ _0486_;
assign _0501_ = _0499_ ^ _0181_;
assign _0502_ = _0501_ ^ _0484_;
assign _0503_ = _0502_ ^ _0170_;
assign _0504_ = _0503_ ^ _0428_;
assign _0505_ = _0483_ ^ _0140_;
assign _0506_ = ~(_0505_ | _0411_);
assign _0507_ = ~(_0506_ ^ _0504_);
assign _0508_ = ~_0507_;
assign _0509_ = _0505_ ^ V;
assign _0510_ = _0509_ & _0508_;
assign _0512_ = ~_0506_;
assign _0513_ = ~(_0512_ | _0504_);
assign _0514_ = ~_0513_;
assign _0515_ = ~(_0503_ | _0428_);
assign _0516_ = _0502_ | _0170_;
assign _0517_ = ~(_0498_ | _0486_);
assign _0518_ = ~(O | N);
assign _0519_ = _0518_ | _0496_;
assign _0520_ = ~((_0588_ | _0211_) & _0519_);
assign _0521_ = ~(_0495_ & _0487_);
assign _0523_ = _0521_ & L;
assign _0524_ = ~(_0479_ & H);
assign _0525_ = _0494_ | _0524_;
assign _0526_ = _0493_ | _0491_;
assign _0527_ = ~A;
assign _0528_ = ~(D & C);
assign _0529_ = _0198_ & C;
assign _0530_ = ~((_0528_ & _0527_) | _0529_);
assign _0531_ = ~((_0390_ & _0401_) | _0257_);
assign _0532_ = _0531_ ^ _0530_;
assign _0534_ = _0532_ ^ F;
assign _0535_ = _0534_ ^ _0526_;
assign _0536_ = _0535_ ^ _0525_;
assign _0537_ = _0536_ ^ I;
assign _0538_ = ~_0494_;
assign _0539_ = _0538_ & _0488_;
assign _0540_ = _0539_ | _0192_;
assign _0541_ = _0540_ ^ _0537_;
assign _0542_ = _0541_ ^ _0523_;
assign _0543_ = _0542_ ^ _0520_;
assign _0545_ = _0543_ ^ P;
assign _0546_ = _0545_ ^ _0517_;
assign _0547_ = _0499_ | _0181_;
assign _0548_ = ~(_0501_ & _0484_);
assign _0549_ = _0548_ & _0547_;
assign _0550_ = _0549_ ^ _0546_;
assign _0551_ = _0550_ ^ _0516_;
assign _0552_ = ~(_0551_ ^ _0515_);
assign _0553_ = _0552_ ^ _0514_;
assign _0554_ = ~_0553_;
assign _0556_ = ~((_0554_ | _0510_) & X);
assign _0557_ = ~(_0552_ | _0514_);
assign _0558_ = ~((_0550_ | _0502_) & T);
assign _0559_ = _0549_ | _0546_;
assign _0560_ = ~(_0498_ | _0482_);
assign _0561_ = _0545_ & _0560_;
assign _0562_ = ~(_0561_ | _0643_);
assign _0563_ = ~_0562_;
assign _0564_ = ~(_0543_ & P);
assign _0565_ = ~((_0542_ & _0497_) | _0588_);
assign _0567_ = _0541_ & _0523_;
assign _0568_ = ~((_0537_ & K) | _0539_);
assign _0569_ = ~((_0534_ | _0493_) & G);
assign _0570_ = _0532_ | _0051_;
assign _0571_ = ~(_0531_ & _0530_);
assign _0572_ = ~(_0198_ | _0401_);
assign _0573_ = ~(_0572_ ^ _0236_);
assign _0574_ = _0573_ ^ E;
assign _0575_ = _0574_ ^ _0571_;
assign _0576_ = _0575_ ^ _0570_;
assign _0578_ = _0576_ ^ _0569_;
assign _0579_ = ~(_0535_ | _0525_);
assign _0580_ = ~((_0536_ & I) | _0579_);
assign _0581_ = _0580_ ^ _0578_;
assign _0582_ = _0581_ ^ _0568_;
assign _0583_ = _0582_ ^ _0567_;
assign _0584_ = _0583_ ^ _0832_;
assign _0585_ = ~_0496_;
assign _0586_ = _0542_ & _0585_;
assign _0587_ = _0586_ & N;
assign _0589_ = _0587_ ^ _0584_;
assign _0590_ = ~(_0589_ ^ _0565_);
assign _0591_ = _0590_ ^ _0564_;
assign _0592_ = _0591_ ^ _0563_;
assign _0593_ = _0592_ ^ R;
assign _0594_ = _0593_ ^ _0559_;
assign _0595_ = ~(_0594_ ^ _0558_);
assign _0596_ = ~_0515_;
assign _0597_ = ~(_0551_ | _0596_);
assign _0598_ = ~(_0597_ | _0428_);
assign _0600_ = _0598_ ^ _0595_;
assign _0601_ = _0600_ ^ _0557_;
assign _0602_ = _0601_ | _0556_;
assign _0603_ = ~_0597_;
assign _0604_ = ~((_0595_ | _0428_) & _0603_);
assign _0605_ = ~(_0546_ | _0548_);
assign _0606_ = _0593_ & _0605_;
assign _0607_ = ~(_0546_ | _0547_);
assign _0608_ = ~((_0592_ & R) | _0607_);
assign _0609_ = ~_0543_;
assign _0611_ = ~((_0590_ | _0609_) & P);
assign _0612_ = _0583_ & M;
assign _0613_ = _0581_ | _0568_;
assign _0614_ = _0578_ & _0579_;
assign _0615_ = ~(_0576_ | _0569_);
assign _0616_ = ~(_0575_ | _0570_);
assign _0617_ = _0573_ | _0257_;
assign _0618_ = ~((_0574_ | _0571_) & _0617_);
assign _0619_ = ~((_0401_ & _0527_) | B);
assign _0620_ = C & A;
assign _0622_ = _0620_ | D;
assign _0623_ = _0619_ ? _0390_ : _0622_;
assign _0624_ = _0623_ ^ E;
assign _0625_ = _0624_ ^ _0618_;
assign _0626_ = _0625_ ^ _0616_;
assign _0627_ = _0626_ ^ _0615_;
assign _0628_ = ~(_0627_ ^ _0614_);
assign _0629_ = ~(_0578_ & _0536_);
assign _0630_ = _0629_ & I;
assign _0631_ = _0630_ ^ _0628_;
assign _0633_ = _0631_ ^ _0613_;
assign _0634_ = ~((_0541_ | _0251_) & _0521_);
assign _0635_ = ~((_0582_ & L) | _0634_);
assign _0636_ = ~(_0635_ ^ _0633_);
assign _0637_ = _0636_ ^ _0612_;
assign _0638_ = ~((_0586_ & _0584_) | _0211_);
assign _0639_ = ~(_0638_ ^ _0637_);
assign _0640_ = ~_0565_;
assign _0641_ = ~((_0589_ | _0640_) & O);
assign _0642_ = ~(_0641_ ^ _0639_);
assign _0644_ = ~(_0642_ ^ _0611_);
assign _0645_ = ~((_0591_ | _0561_) & Q);
assign _0646_ = _0645_ ^ _0644_;
assign _0647_ = _0646_ ^ _0181_;
assign _0648_ = _0647_ ^ _0608_;
assign _0649_ = ~(_0648_ ^ _0606_);
assign _0650_ = _0594_ | _0558_;
assign _0651_ = ~(_0650_ & T);
assign _0652_ = _0651_ ^ _0649_;
assign _0653_ = _0652_ ^ U;
assign _0654_ = _0653_ ^ _0604_;
assign _0655_ = _0505_ | _0504_;
assign _0656_ = ~(_0655_ | _0552_);
assign _0657_ = ~((_0600_ & _0656_) | _0411_);
assign _0658_ = _0657_ ^ _0654_;
assign _0659_ = ~(_0658_ & X);
assign _0660_ = ~(_0659_ & _0602_);
assign _0661_ = ~(_0657_ & _0654_);
assign _0662_ = _0652_ & U;
assign _0663_ = _0653_ & _0604_;
assign _0666_ = _0663_ | _0662_;
assign _0667_ = ~((_0649_ | _0170_) & _0650_);
assign _0668_ = _0648_ & _0606_;
assign _0669_ = ~(_0646_ & R);
assign _0670_ = ~((_0647_ | _0608_) & _0669_);
assign _0671_ = ~((_0644_ | _0643_) & (_0591_ | _0563_));
assign _0672_ = _0642_ | _0611_;
assign _0673_ = ~((_0639_ | _0588_) & (_0589_ | _0640_));
assign _0674_ = ~(_0627_ & _0614_);
assign _0675_ = _0626_ & _0615_;
assign _0677_ = _0532_ & F;
assign _0678_ = ~((_0575_ & F) | (_0574_ & _0677_));
assign _0679_ = ~(_0625_ & F);
assign _0680_ = _0679_ & _0678_;
assign _0681_ = _0624_ & _0618_;
assign _0682_ = ~(_0623_ & E);
assign _0683_ = ~((B | D) & (C | A));
assign _0684_ = _0620_ ? D : _0683_;
assign _0685_ = ~(_0684_ & _0682_);
assign _0686_ = ~((_0685_ | _0681_) & _0571_);
assign _0688_ = _0686_ ^ _0680_;
assign _0689_ = _0688_ ^ _0675_;
assign _0690_ = _0689_ & _0674_;
assign _0691_ = ~((_0629_ & _0628_) | _0389_);
assign _0692_ = _0691_ ^ _0690_;
assign _0693_ = ~(_0631_ | _0613_);
assign _0694_ = _0582_ & L;
assign _0695_ = _0634_ | _0694_;
assign _0696_ = ~((_0695_ & _0633_) | _0693_);
assign _0697_ = ~(_0696_ ^ _0692_);
assign _0699_ = _0636_ & _0612_;
assign _0700_ = _0638_ & _0637_;
assign _0701_ = _0700_ | _0699_;
assign _0702_ = _0701_ ^ _0697_;
assign _0703_ = ~(_0702_ ^ _0673_);
assign _0704_ = _0703_ ^ _0672_;
assign _0705_ = _0704_ ^ _0671_;
assign _0706_ = _0705_ ^ _0670_;
assign _0707_ = _0706_ ^ _0668_;
assign _0708_ = _0707_ ^ _0667_;
assign _0710_ = ~(_0708_ | _0666_);
assign _0711_ = _0708_ & _0666_;
assign _0712_ = _0711_ | _0710_;
assign _0713_ = _0712_ ^ _0661_;
assign _0714_ = ~(_0601_ ^ _0556_);
assign _0715_ = _0509_ ^ X;
assign _0716_ = _0509_ & X;
assign _0717_ = ~(_0716_ ^ _0507_);
assign _0718_ = _0717_ ^ Y;
assign _0719_ = _0717_ & Y;
assign _0721_ = ~_0719_;
assign _0722_ = ~(_0510_ | _0160_);
assign _0723_ = _0722_ ^ _0553_;
assign _0724_ = ~(_0723_ & _0721_);
assign _0725_ = ~((_0718_ | _0715_) & _0724_);
assign _0726_ = ~((_0714_ & _0159_) | _0725_);
assign _0727_ = ~((_0723_ | _0721_) & (_0714_ | _0159_));
assign _0728_ = _0727_ | _0726_;
assign _0729_ = _0602_ & X;
assign _0730_ = _0729_ ^ _0658_;
assign _0732_ = _0730_ & _0728_;
assign _0733_ = ~((_0732_ | _0713_) & _0660_);
assign _0734_ = ~(_0474_ & _0101_);
assign _0735_ = _0137_ & _0105_;
assign _0736_ = _0134_ & _0114_;
assign _0737_ = ~(_0128_ | _0130_);
assign _0738_ = ~(_0125_ & _0121_);
assign _0739_ = ~((_0126_ & _0120_) | (_0124_ & _0122_));
assign _0740_ = _0739_ & _0738_;
assign _0741_ = ~_0118_;
assign _0743_ = ~(_0128_ | _0129_);
assign _0744_ = ~((_0127_ & _0741_) | _0743_);
assign _0745_ = _0744_ ^ _0740_;
assign _0746_ = ~(_0745_ ^ _0737_);
assign _0747_ = _0132_ & _0116_;
assign _0748_ = ~((_0133_ & _0115_) | _0747_);
assign _0749_ = _0748_ ^ _0746_;
assign _0750_ = ~(_0749_ ^ _0736_);
assign _0751_ = _0135_ & _0111_;
assign _0752_ = ~((_0136_ & _0108_) | _0751_);
assign _0754_ = _0752_ ^ _0750_;
assign _0755_ = ~(_0754_ ^ _0735_);
assign _0756_ = ~(_0138_ & _0103_);
assign _0757_ = ~(_0142_ & _0139_);
assign _0758_ = _0757_ & _0756_;
assign _0759_ = _0758_ ^ _0755_;
assign _0760_ = _0707_ & _0667_;
assign _0761_ = _0706_ & _0668_;
assign _0762_ = _0705_ & _0670_;
assign _0763_ = _0704_ & _0671_;
assign _0765_ = ~(_0702_ & _0673_);
assign _0766_ = ~((_0703_ | _0672_) & _0765_);
assign _0767_ = ~((_0700_ | _0699_) & _0697_);
assign _0768_ = _0695_ & _0633_;
assign _0769_ = _0692_ & _0768_;
assign _0770_ = ~(_0692_ & _0693_);
assign _0771_ = ~(_0688_ & _0675_);
assign _0772_ = _0686_ | _0680_;
assign _0773_ = ~((_0531_ & _0530_) | _0529_);
assign _0774_ = ~(_0773_ | _0772_);
assign _0776_ = _0773_ & _0772_;
assign _0777_ = ~((_0776_ | _0774_) & _0771_);
assign _0778_ = ~(_0691_ & _0690_);
assign _0779_ = ~(_0778_ & _0674_);
assign _0780_ = ~(_0779_ ^ _0777_);
assign _0781_ = _0780_ ^ _0770_;
assign _0782_ = ~(_0781_ ^ _0769_);
assign _0783_ = _0782_ ^ _0767_;
assign _0784_ = _0783_ ^ _0766_;
assign _0785_ = _0784_ ^ _0763_;
assign _0787_ = _0785_ ^ _0762_;
assign _0788_ = _0787_ ^ _0761_;
assign _0789_ = ~(_0788_ ^ _0760_);
assign _0790_ = ~(_0744_ | _0740_);
assign _0791_ = ~((_0745_ & _0737_) | _0790_);
assign _0792_ = ~((_0748_ | _0746_) & _0791_);
assign _0793_ = ~((_0749_ & _0736_) | _0792_);
assign _0794_ = ~((_0752_ | _0750_) & _0793_);
assign _0795_ = ~((_0754_ & _0735_) | _0794_);
assign _0796_ = _0795_ & _0789_;
assign _0798_ = ~((_0755_ | _0756_) & _0796_);
assign _0799_ = _0788_ & _0760_;
assign _0800_ = _0787_ & _0761_;
assign _0801_ = _0785_ & _0762_;
assign _0802_ = _0784_ & _0763_;
assign _0803_ = ~_0765_;
assign _0804_ = ~((_0779_ & _0777_) | _0774_);
assign _0805_ = ~((_0780_ | _0770_) & _0804_);
assign _0806_ = ~((_0781_ & _0769_) | _0805_);
assign _0807_ = ~((_0782_ | _0767_) & _0806_);
assign _0809_ = ~((_0783_ & _0803_) | _0807_);
assign _0810_ = _0783_ & _0766_;
assign _0811_ = _0807_ | _0810_;
assign _0812_ = _0802_ ? _0809_ : _0811_;
assign _0813_ = _0812_ ^ _0801_;
assign _0814_ = _0813_ | _0800_;
assign _0815_ = _0814_ | _0799_;
assign _0816_ = _0815_ | _0798_;
assign _0817_ = _0816_ | _0711_;
assign _0819_ = ~((_0755_ | _0757_) & (_0710_ | _0661_));
assign _0820_ = _0819_ | _0817_;
assign _0821_ = _0820_ | _0145_;
assign _0822_ = _0821_ | _0759_;
assign _0823_ = ~((_0732_ & _0713_) | _0822_);
assign _0824_ = _0823_ & _0734_;
assign _0825_ = _0824_ & _0733_;
assign _0826_ = _0825_ & _0477_;
assign _0827_ = ~((_0473_ | _0453_) & _0826_);
assign _0828_ = _0827_ | _0149_;
assign valid = ~((_0183_ & _0178_) | _0828_);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_4_V
`define SKY130_FD_SC_HS__A311O_4_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a311o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a311o_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_4_V
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 15:49:28 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_rst_ps7_0_50M_0_sim_netlist.v
// Design : gcd_block_design_rst_ps7_0_50M_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(lpf_asr_reg,
scndry_out,
lpf_asr,
p_1_in,
p_2_in,
asr_lpf,
aux_reset_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input p_1_in;
input p_2_in;
input [0:0]asr_lpf;
input aux_reset_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(p_1_in),
.I2(p_2_in),
.I3(scndry_out),
.I4(asr_lpf),
.O(lpf_asr_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
(lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0]p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire exr_d1;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(exr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O(exr_d1));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[1]),
.I2(p_3_out[2]),
.I3(scndry_out),
.I4(p_3_out[0]),
.O(lpf_exr_reg));
endmodule
(* CHECK_LICENSE_TYPE = "gcd_block_design_rst_ps7_0_50M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2018.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "zynq" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
mb_debug_sys_rst,
ext_reset_in,
aux_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input mb_debug_sys_rst;
input ext_reset_in;
input aux_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFFD))
lpf_int0
(.I0(dcm_locked),
.I1(lpf_exr),
.I2(lpf_asr),
.I3(Q),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Bsr_out;
wire MB_out;
wire Pr_out;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\BSR_OUT_DFF[0].FDRE_BSR
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Bsr_out),
.Q(bus_struct_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
FDRE_inst
(.C(slowest_sync_clk),
.CE(1'b1),
.D(MB_out),
.Q(mb_reset),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\PR_OUT_DFF[0].FDRE_PER
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Pr_out),
.Q(peripheral_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (SEQ_n_4),
.Bsr_out(Bsr_out),
.MB_out(MB_out),
.Pr_out(Pr_out),
.lpf_int(lpf_int),
.slowest_sync_clk(slowest_sync_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
(MB_out,
Bsr_out,
Pr_out,
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ,
lpf_int,
slowest_sync_clk);
output MB_out;
output Bsr_out;
output Pr_out;
output \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ;
output \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ;
wire Bsr_out;
wire Core_i_1_n_0;
wire MB_out;
wire Pr_out;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
(.I0(Bsr_out),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
(.I0(Pr_out),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(MB_out),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b1))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(MB_out),
.S(lpf_int));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0090))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[4]),
.I2(seq_cnt[3]),
.I3(seq_cnt[5]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(Bsr_out),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b1))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(Bsr_out),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h9000))
\core_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[4]),
.I2(seq_cnt[3]),
.I3(seq_cnt[5]),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(MB_out),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0018))
pr_dec0
(.I0(seq_cnt_en),
.I1(seq_cnt[0]),
.I2(seq_cnt[2]),
.I3(seq_cnt[1]),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0480))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(Pr_out),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b1))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(Pr_out),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_144x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_144x256 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q);
input aclr;
input clock;
input [143:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [143:0] q;
wire sub_wire0;
wire sub_wire1;
wire [143:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [143:0] q = sub_wire2[143:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.almost_empty (),
.almost_full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 144,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "192"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "144"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "144"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "144"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 144 0 INPUT NODEFVAL "data[143..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 144 0 OUTPUT NODEFVAL "q[143..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 144 0 data 0 0 144 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 144 0 @q 0 0 144 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_144x256_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O221A_BEHAVIORAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_BEHAVIORAL_V |
`include "bsg_nonsynth_dramsim3.svh"
`define dram_pkg bsg_dramsim3_hbm2_8gb_x128_pkg
module testbench();
bit clk;
bit reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(1000)
) cg0 (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(10)
) rg0 (
.clk_i(clk)
,.async_reset_o(reset)
);
import `dram_pkg::*;
// trace replay
localparam write_data_width_lp = 32; // we only write 32-bit data to save space.
localparam payload_width_p = `dram_pkg::channel_addr_width_p + 1 + write_data_width_lp;
localparam rom_addr_width_p = 20;
typedef struct packed {
logic write_not_read;
logic [`dram_pkg::channel_addr_width_p-1:0] ch_addr;
logic [write_data_width_lp-1:0] data;
} trace_s;
trace_s tr_data_lo;
logic tr_v_lo;
logic tr_yumi_li;
logic [rom_addr_width_p-1:0] rom_addr;
logic [payload_width_p+4-1:0] rom_data;
logic tr_done_lo;
bsg_trace_replay #(
.payload_width_p(payload_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr0 (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(tr_done_lo)
,.error_o()
);
bsg_nonsynth_test_rom #(
.filename_p("trace.tr")
,.data_width_p(payload_width_p+4)
,.addr_width_p(rom_addr_width_p)
) trom0 (
.addr_i(rom_addr)
,.data_o(rom_data)
);
// dramsim3
//
logic [num_channels_p-1:0] dramsim3_v_li;
logic [num_channels_p-1:0][channel_addr_width_p-1:0] dramsim3_ch_addr_li;
logic [num_channels_p-1:0] dramsim3_yumi_lo;
logic [num_channels_p-1:0] dramsim3_write_not_read_li;
logic [num_channels_p-1:0] dramsim3_data_v_li;
logic [num_channels_p-1:0] dramsim3_data_yumi_lo;
logic [num_channels_p-1:0][data_width_p-1:0] dramsim3_data_li;
logic [num_channels_p-1:0] dramsim3_data_v_lo;
logic [num_channels_p-1:0][data_width_p-1:0] dramsim3_data_lo;
logic [num_channels_p-1:0][channel_addr_width_p-1:0] dramsim3_read_done_ch_addr_lo;
logic [num_channels_p-1:0] dramsim3_write_done_lo;
bsg_nonsynth_dramsim3 #(
.channel_addr_width_p(`dram_pkg::channel_addr_width_p)
,.data_width_p(`dram_pkg::data_width_p)
,.num_channels_p(`dram_pkg::num_channels_p)
,.num_columns_p(`dram_pkg::num_columns_p)
,.num_rows_p(`dram_pkg::num_rows_p)
,.num_ba_p(`dram_pkg::num_ba_p)
,.num_bg_p(`dram_pkg::num_bg_p)
,.num_ranks_p(`dram_pkg::num_ranks_p)
,.size_in_bits_p(`dram_pkg::size_in_bits_p)
,.address_mapping_p(`dram_pkg::address_mapping_p)
,.config_p(`dram_pkg::config_p)
,.masked_p(0)
,.debug_p(1)
,.init_mem_p(1)
) DUT (
.clk_i(clk)
,.reset_i(reset)
,.v_i(dramsim3_v_li)
,.write_not_read_i(dramsim3_write_not_read_li)
,.ch_addr_i(dramsim3_ch_addr_li)
,.yumi_o(dramsim3_yumi_lo)
,.data_v_i(dramsim3_data_v_li)
,.data_i(dramsim3_data_li)
,.mask_i('0)
,.data_yumi_o(dramsim3_data_yumi_lo)
,.data_v_o(dramsim3_data_v_lo)
,.data_o(dramsim3_data_lo)
,.read_done_ch_addr_o(dramsim3_read_done_ch_addr_lo)
,.write_done_o(dramsim3_write_done_lo)
,.write_done_ch_addr_o()
);
assign dramsim3_v_li[0] = tr_v_lo;
assign dramsim3_write_not_read_li[0] = tr_data_lo.write_not_read;
assign dramsim3_ch_addr_li[0] = tr_data_lo.ch_addr;
assign tr_yumi_li = dramsim3_yumi_lo[0];
assign dramsim3_data_v_li[0] = tr_v_lo & tr_data_lo.write_not_read;
assign dramsim3_data_li[0] = {{(`dram_pkg::data_width_p-write_data_width_lp){1'b0}}, tr_data_lo.data};
for (genvar i = 1; i < `dram_pkg::num_channels_p; i++) begin
assign dramsim3_v_li[i] = 1'b0;
assign dramsim3_ch_addr_li[i] = '0;
assign dramsim3_write_not_read_li[i] = 1'b0;
assign dramsim3_data_v_li[i] = 1'b0;
assign dramsim3_data_li[i] = '0;
end
// request tracker
integer sent_r;
integer recv_r;
always_ff @ (posedge clk) begin
if (reset) begin
sent_r <= 0;
recv_r <= 0;
end
else begin
if (tr_v_lo & tr_yumi_li) sent_r <= sent_r + 1;
recv_r <= recv_r + dramsim3_data_v_lo[0] + dramsim3_write_done_lo[0];
end
end
initial begin
wait(tr_done_lo & (sent_r == recv_r));
#30000;
$display("[BSG_FINISH] test successful.");
$finish();
end
// consistency checker
// num_cols_p = columns_per_row * num_banks * ba_per_bg * num_rows
localparam num_cols_p = 64*4*4*(2**15);
logic [31:0] shadow_mem [num_cols_p-1:0];
logic [`dram_pkg::channel_addr_width_p-5-1:0] col_addr;
logic [`dram_pkg::channel_addr_width_p-5-1:0] read_done_col_addr;
assign col_addr = dramsim3_ch_addr_li[0][`dram_pkg::channel_addr_width_p-1:5];
assign read_done_col_addr = dramsim3_read_done_ch_addr_lo[0][`dram_pkg::channel_addr_width_p-1:5];
always_ff @ (posedge clk) begin
if (reset) begin
for (integer i = 0; i < num_cols_p; i++)
shadow_mem[i] = '0;
end
else begin
// input record
if (dramsim3_v_li[0] & dramsim3_yumi_lo[0]) begin
if (dramsim3_write_not_read_li[0]) begin
shadow_mem[col_addr] <= dramsim3_data_li[0][0+:32];
$display("[BSG_DEBUG] t=%t writing 0x%08x to 0x%08x\n", $time, dramsim3_data_li[0][0+:32], dramsim3_ch_addr_li[0]);
end
end
// output checker
if (dramsim3_data_v_lo[0]) begin
$display("[BSG_DEBUG] t=%t read 0x%08x from 0x%08x\n",$time, dramsim3_data_lo[0][0+:32], dramsim3_read_done_ch_addr_lo[0]);
assert(shadow_mem[read_done_col_addr] == dramsim3_data_lo[0][0+:32])
//$display("[BSG_INFO] output matched. Id=%d, Expected=%x, Actual=%x", recv_id, result[recv_id], dramsim3_data_lo[0][0+:32]);
else $fatal("[BSG_FATAL] output does not match expected result for 0x%x. Expected=%x, Actual=%x",
dramsim3_read_done_ch_addr_lo[0], shadow_mem[read_done_col_addr], dramsim3_data_lo[0][0+:32]);
end
end
end
endmodule
|
//phase 6: testing B.EQ and B.NE branch
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:50];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:50], daddrbusout[0:50];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:50], databusout[0:50];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:50];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter CBNZ = 8'b10110101;
parameter CBZ = 8'b10110100;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter LDUR = 11'b11111000010;
parameter LSL = 11'b11010011011;
parameter LSR = 11'b11010011010;
parameter MOVZ = 9'b110100101;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter STUR = 11'b11111000000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter B = 6'b000101;
parameter B_EQ = 8'b01010101;
parameter B_NE = 8'b01010110;
parameter B_LT = 8'b01010111;
parameter B_GT = 8'b01011000;
//register parameters
parameter R0 = 5'b00000;
parameter R15 = 5'b01111;
parameter R16 = 5'b10000;
parameter R17 = 5'b10001;
parameter R18 = 5'b10010;
parameter R19 = 5'b10011;
parameter R20 = 5'b10100;
parameter R21 = 5'b10101;
parameter R22 = 5'b10110;
parameter R23 = 5'b10111;
parameter R24 = 5'b11000;
parameter R25 = 5'b11001;
parameter R26 = 5'b11010;
parameter R27 = 5'b11011;
parameter R28 = 5'b11100;
parameter R29 = 5'b11101;
parameter R30 = 5'b11110;
parameter R31 = 5'b11111;
//other parameterz to be used
parameter zeroSham = 6'b000000;
parameter RX = 5'b11111;
parameter oneShamt = 6'b000001;
parameter twoShamt = 6'b000010;
parameter threeShamt = 6'b000011;
parameter eightShamt = 6'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64'hx;
//phase 1: testing basic op commands
// op, rd, rn, rm
iname[0] ="ADDI, R20, R31, #AAA";//testing addi, result in R20 = 0000000000000AAA
iaddrbusout[0] = 64'h00000000;
// opcode rm/ALUImm rn rd
instrbusin[0] ={ADDI, 12'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64'bz;
databusout[0] = dontcare;
// op, rd, rn, rm
iname[1] ="ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 0000000000000000
iaddrbusout[1] = 64'h00000004;
// opcode rm/ALUImm rn rd
instrbusin[1] ={ADDI, 12'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64'bz;
databusout[1] = dontcare;
// op, rd, rn, rm
iname[2] ="ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 0000000000000002
iaddrbusout[2] = 64'h00000008;
// opcode rm/ALUImm rn rd
instrbusin[2] ={ADDI, 12'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64'bz;
databusout[2] = dontcare;
// op, rd, rn, rm
iname[3] ="ORRI, R21, R24, #001";//testing ori, result in R21 = 0000000000000001
iaddrbusout[3] = 64'h0000000C;
// opcode rm/ALUImm rn rd
instrbusin[3] ={ORRI, 12'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64'bz;
databusout[3] = dontcare;
// op, rd, rn, rm
iname[4] ="EORI, R22, R20, #000";//testing xori, result in R22 = 0000000000000AAA
iaddrbusout[4] = 64'h00000010;
// opcode rm/ALUImm rn rd
instrbusin[4] ={EORI, 12'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64'bz;
databusout[4] = dontcare;
// op, rd, rn, rm
iname[5] ="ANDI, R23, R0, #003";//testing andi, result in R23 = 0000000000000002
iaddrbusout[5] = 64'h00000014;
// opcode rm/ALUImm rn rd
instrbusin[5] ={ANDI, 12'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64'bz;
databusout[5] = dontcare;
// op, rd, rn, rm
iname[6] ="SUBI, R24, R20, #00A";//testing subi, result in R24 = 0000000000000AA0
iaddrbusout[6] = 64'h00000018;
// opcode rm/ALUImm rn rd
instrbusin[6] ={SUBI, 12'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64'bz;
databusout[6] = dontcare;
// op, rd, rn, rm
iname[7] ="ADD, R25, R20, R0";//testing add, result in R25 = 0000000000000AAC
iaddrbusout[7] = 64'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64'bz;
databusout[7] = dontcare;
// op, rd, rn, rm
iname[8] ="AND, R26, R20, R22";//testing and, result in R26 = 0000000000000AAA
iaddrbusout[8] = 64'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64'bz;
databusout[8] = dontcare;
// op, rd, rn, rm
iname[9] ="EOR, R27, R23, R21";//testing xor, result in R27 = 0000000000000003
iaddrbusout[9] = 64'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64'bz;
databusout[9] = dontcare;
// op, rd, rn, rm
iname[10] ="ORR, R28, R25, R23";//testing or, result in R28 = 0000000000000AAE
iaddrbusout[10] = 64'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64'bz;
databusout[10] = dontcare;
// op, rd, rn, rm
iname[11] ="SUB, R29, R20, R22";//testing sub, result in R29 = 0000000000000000
iaddrbusout[11] = 64'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64'bz;
databusout[11] = dontcare;
// op, rd, rn, aluImm
iname[12] ="ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 0000000000000000
iaddrbusout[12] = 64'h00000030;
// opcode rm/ALUImm rn rd
instrbusin[12] ={ADDI, 12'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64'bz;
databusout[12] = dontcare;
//phase 2: testing basic op codes with the set flags
// op, rd, rn, aluImm
iname[13] ="SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFFFFFFFFFF
iaddrbusout[13] = 64'h00000034;
// opcode rm/ALUImm rn rd
instrbusin[13] ={SUBIS, 12'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64'bz;
databusout[13] = dontcare;
// op, rd, rn, rm
iname[14] ="SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFFFFFFFFFE
iaddrbusout[14] = 64'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64'bz;
databusout[14] = dontcare;
// op, rd, rn, aluImm
iname[15] ="ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 0000000000000000
iaddrbusout[15] = 64'h0000003C;
// opcode rm/ALUImm rn rd
instrbusin[15] ={ADDIS, 12'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64'bz;
databusout[15] = dontcare;
// op, rd, rn, rm
iname[16] ="ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 0000000000000001
iaddrbusout[16] = 64'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64'bz;
databusout[16] = dontcare;
// op, rd, rn, aluImm
iname[17] ="ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 0000000000000002
iaddrbusout[17] = 64'h00000044;
// opcode rm/ALUImm rn rd
instrbusin[17] ={ANDIS, 12'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64'bz;
databusout[17] = dontcare;
// op, rd, rn, rm
iname[18] ="ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFFFFFFFFFE
iaddrbusout[18] = 64'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64'bz;
databusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64'bz;
databusout[19] = dontcare;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64'bz;
databusout[20] = dontcare;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64'bz;
databusout[21] = dontcare;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64'bz;
databusout[22] = dontcare;
// op, rd, rn, rm
iname[23] ="LSL, R20, R20, 2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64'bz;
databusout[23] = dontcare;
// op, rd, rn, rm
iname[24] ="LSR, R21, R21, 2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64'bz;
databusout[24] = dontcare;
//phase 4: testing load and store
// op, rt, rn, DT_adr
iname[25] ="LDUR, R22, R31, #1";//testing load, result in R22 = 42069 (from memory,databusin) [yes, really]
iaddrbusout[25] = 64'h00000064;
// op, DT_ADDR, ?, rn, rt
instrbusin[25] ={LDUR, 9'b000000001, 2'b00, R31, R22};
daddrbusout[25] = 64'h0000000000000001;//used for LDUR
databusin[25] = 64'h0000000000042069;//used for LDUR
databusout[25] = dontcare;
// op, rn, DT_adr, rt
iname[26] ="STUR, R23, #068, R24";//testing story, result for databusout in R24 = 0000000000000002 (to memory)
//address is calculated from imm or 68, and R23, which is currently 1
iaddrbusout[26] = 64'h00000068;
// op, DT_ADDR, ?, rn, rt
instrbusin[26] ={STUR, 9'b001101000, 2'b00, R23, R24};
daddrbusout[26] = 64'h0000000000000069;//used for STUR
databusin[26] = 64'bz;
databusout[26] = 64'h0000000000000002;//used for STUR
// op, rd, rn, rm
iname[27] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[27] = 64'h0000006C;
// op, rm, shamt, rn, rd
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64'bz;
databusout[27] = dontcare;
// op, rd, rn, rm
iname[28] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[28] = 64'h00000070;
// op, rm, shamt, rn, rd
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64'bz;
databusout[28] = dontcare;
// op, rd, rn, rm
iname[29] ="AND, R17, R31, R31";//delay, result in R17 = 0000000000000000
iaddrbusout[29] = 64'h00000074;
// op, rm, shamt, rn, rd
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64'bz;
databusout[29] = dontcare;
//phase 5: testing B branch
// op, BR_address
iname[30] ="B, #EA";//testing branch, calculated branch address should be
// (64'h0000000000000078 + 64'h000000000000003A8 = 64'h0000000000000420)
iaddrbusout[30] = 64'h00000078;
// op, BR_address
instrbusin[30] ={B, 26'b00000000000000000011101010};
daddrbusout[30] = dontcare;
databusin[30] = 64'bz;
databusout[30] = dontcare;
// op, rd, rn, rm
iname[31] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[31] = 64'h0000007C;
// op, rm, shamt, rn, rd
instrbusin[31] ={AND, R31, zeroSham, R31, R19};
daddrbusout[31] = dontcare;
databusin[31] = 64'bz;
databusout[31] = dontcare;
// op, rd, rn, rm
iname[32] ="ADD, R20, R21, R20";//testing branch address result in R20 = 0000000000000707
iaddrbusout[32] = 64'h00000420;
// op, rm, shamt, rn, rd
instrbusin[32] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[32] = dontcare;
databusin[32] = 64'bz;
databusout[32] = dontcare;
//phase 6: testing B.EQ and B.NE branch
// op, rd, rn, rm
iname[33] ="ADDI, R21, R31, #AAA";//testing addi, result in R21 = 0000000000000AAA
iaddrbusout[33] = 64'h00000424;
// opcode rm/ALUImm rn rd
instrbusin[33] ={ADDI, 12'hAAA, R31, R21};
daddrbusout[33] = dontcare;
databusin[33] = 64'bz;
databusout[33] = dontcare;
// op, rd, rn, rm
iname[34] ="ADDI, R22, R31, #AAA";//testing addi, result in R22 = 0000000000000AAA
iaddrbusout[34] = 64'h00000428;
// opcode rm/ALUImm rn rd
instrbusin[34] ={ADDI, 12'hAAA, R31, R22};
daddrbusout[34] = dontcare;
databusin[34] = 64'bz;
databusout[34] = dontcare;
//ADDIS for FAKE BRANCH
// op, rd, rn, aluImm
iname[35] ="ADDIS,R31, R31, #420";//testing fake branch, this should NOT set the Z high
iaddrbusout[35] = 64'h0000042C;
// opcode rm/ALUImm rn rd
instrbusin[35] ={ADDIS, 12'h420, R31, R31};
daddrbusout[35] = dontcare;
databusin[35] = 64'bz;
databusout[35] = dontcare;
//FAKE BRANCH
// op, COND_addr, rt
iname[36] ="B_EQ, #69420, RX";//testing to NOT take the branch, Z should be LOW
iaddrbusout[36] = 64'h00000430;
// op, COND_addr, rt
instrbusin[36] ={B_EQ, 19'b1101001010000100000, RX};
daddrbusout[36] = dontcare;
databusin[36] = 64'bz;
databusout[36] = dontcare;
iname[37] = "NOP";//nada
iaddrbusout[37] = 64'h00000434;
instrbusin[37] = 64'b0;
daddrbusout[37] = dontcare;
databusin[37] = 64'bz;
databusout[37] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[38] ="SUBS, R31, R21, R22";//set z flag for BEQ,
iaddrbusout[38] = 64'h00000438;
// op, rm, shamt, rn, rd
instrbusin[38] ={SUBS, R22, zeroSham, R21, R31};
daddrbusout[38] = dontcare;
databusin[38] = 64'bz;
databusout[38] = dontcare;
//real branch for B.EQ (I have the best branches)
// op, COND_addr, rt
iname[39] ="B_EQ, #69, RX";//take the branch to instruction count ?
iaddrbusout[39] = 64'h0000043C;
// op, COND_addr, rt
instrbusin[39] ={B_EQ, 19'b0000000000001101001, RX};
//19'b
daddrbusout[39] = dontcare;
databusin[39] = 64'bz;
databusout[39] = dontcare;
iname[40] = "NOP";//nada
iaddrbusout[40] = 64'h00000440;
instrbusin[40] = 64'b0;
daddrbusout[40] = dontcare;
databusin[40] = 64'bz;
databusout[40] = dontcare;
iname[41] = "NOP";//nada
iaddrbusout[41] = 64'h000005E0;
instrbusin[41] = 64'b0;
daddrbusout[41] = dontcare;
databusin[41] = 64'bz;
databusout[41] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[42] ="SUBS, R31, R21, R20";//set z flag of NOT for BNE
iaddrbusout[42] = 64'h000005E4;
// op, rm, shamt, rn, rd
instrbusin[42] ={SUBS, R20, zeroSham, R21, R31};
daddrbusout[42] = dontcare;
databusin[42] = 64'bz;
databusout[42] = dontcare;
//test B.NE
// op, COND_addr, rt
iname[43] ="B_NE, #96, RX";//take the branch to instruction count 840
iaddrbusout[43] = 64'h000005E8;
// op, COND_addr, rt
instrbusin[43] ={B_NE, 19'b0000000000010010110, RX};
daddrbusout[43] = dontcare;
databusin[43] = 64'bz;
databusout[43] = dontcare;
iname[44] = "NOP";//nada
iaddrbusout[44] = 64'h000005EC;
instrbusin[44] = 64'b0;
daddrbusout[44] = dontcare;
databusin[44] = 64'bz;
databusout[44] = dontcare;
iname[45] = "NOP";//nada
iaddrbusout[45] = 64'h00000840;
instrbusin[45] = 64'b0;
daddrbusout[45] = dontcare;
databusin[45] = 64'bz;
databusout[45] = dontcare;
//finishing up
iname[46] = "NOP";//nada
iaddrbusout[46] = 64'h00000844;
instrbusin[46] = 64'b0;
daddrbusout[46] = dontcare;
databusin[46] = 64'bz;
databusout[46] = dontcare;
iname[47] = "NOP";//nada
iaddrbusout[47] = 64'h00000848;
instrbusin[47] = 64'b0;
daddrbusout[47] = dontcare;
databusin[47] = 64'bz;
databusout[47] = dontcare;
iname[48] = "NOP";//nada
iaddrbusout[48] = 64'h0000084C;
instrbusin[48] = 64'b0;
daddrbusout[48] = dontcare;
databusin[48] = 64'bz;
databusout[48] = dontcare;
iname[49] = "NOP";//nada
iaddrbusout[49] = 64'h00000850;
instrbusin[49] = 64'b0;
daddrbusout[49] = dontcare;
databusin[49] = 64'bz;
databusout[49] = dontcare;
iname[50] = "NOP";//nada
iaddrbusout[50] = 64'h00000854;
instrbusin[50] = 64'b0;
daddrbusout[50] = dontcare;
databusin[50] = 64'bz;
databusout[50] = dontcare;
//remember to set k down below to ntests - 1
ntests = 51;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 64'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
databusk = 64'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 50; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_crosspoint_64_4x4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_0_axis_tdata = 0;
reg [7:0] input_0_axis_tkeep = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg [63:0] input_1_axis_tdata = 0;
reg [7:0] input_1_axis_tkeep = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg [63:0] input_2_axis_tdata = 0;
reg [7:0] input_2_axis_tkeep = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg [63:0] input_3_axis_tdata = 0;
reg [7:0] input_3_axis_tkeep = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg [1:0] output_0_select = 0;
reg [1:0] output_1_select = 0;
reg [1:0] output_2_select = 0;
reg [1:0] output_3_select = 0;
// Outputs
wire [63:0] output_0_axis_tdata;
wire [7:0] output_0_axis_tkeep;
wire output_0_axis_tvalid;
wire output_0_axis_tlast;
wire [63:0] output_1_axis_tdata;
wire [7:0] output_1_axis_tkeep;
wire output_1_axis_tvalid;
wire output_1_axis_tlast;
wire [63:0] output_2_axis_tdata;
wire [7:0] output_2_axis_tkeep;
wire output_2_axis_tvalid;
wire output_2_axis_tlast;
wire [63:0] output_3_axis_tdata;
wire [7:0] output_3_axis_tkeep;
wire output_3_axis_tvalid;
wire output_3_axis_tlast;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
output_0_select,
output_1_select,
output_2_select,
output_3_select);
$to_myhdl(output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tlast,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tlast,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tlast,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tlast);
// dump file
$dumpfile("test_axis_crosspoint_64_4x4.lxt");
$dumpvars(0, test_axis_crosspoint_64_4x4);
end
axis_crosspoint_64_4x4 #(
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tkeep(input_0_axis_tkeep),
.input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tlast(input_0_axis_tlast),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tlast(input_1_axis_tlast),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tlast(input_2_axis_tlast),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tlast(input_3_axis_tlast),
// AXI outputs
.output_0_axis_tdata(output_0_axis_tdata),
.output_0_axis_tkeep(output_0_axis_tkeep),
.output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tlast(output_0_axis_tlast),
.output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tkeep(output_1_axis_tkeep),
.output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tlast(output_1_axis_tlast),
.output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tkeep(output_2_axis_tkeep),
.output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tlast(output_2_axis_tlast),
.output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tkeep(output_3_axis_tkeep),
.output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tlast(output_3_axis_tlast),
// Control
.output_0_select(output_0_select),
.output_1_select(output_1_select),
.output_2_select(output_2_select),
.output_3_select(output_3_select)
);
endmodule
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// testbench for lf_edge_detect
`include "lf_edge_detect.v"
`define FIN "tb_tmp/data.filtered.gold"
`define FOUT_MIN "tb_tmp/data.min"
`define FOUT_MAX "tb_tmp/data.max"
`define FOUT_STATE "tb_tmp/data.state"
`define FOUT_TOGGLE "tb_tmp/data.toggle"
`define FOUT_HIGH "tb_tmp/data.high"
`define FOUT_HIGHZ "tb_tmp/data.highz"
`define FOUT_LOWZ "tb_tmp/data.lowz"
`define FOUT_LOW "tb_tmp/data.low"
module lf_edge_detect_tb;
integer fin, fout_state, fout_toggle;
integer fout_high, fout_highz, fout_lowz, fout_low, fout_min, fout_max;
integer r;
reg clk = 0;
reg [7:0] adc_d;
wire adc_clk;
wire data_rdy;
wire edge_state;
wire edge_toggle;
wire [7:0] high_threshold;
wire [7:0] highz_threshold;
wire [7:0] lowz_threshold;
wire [7:0] low_threshold;
wire [7:0] max;
wire [7:0] min;
initial
begin
clk = 0;
fin = $fopen(`FIN, "r");
if (!fin) begin
$display("ERROR: can't open the data file");
$finish;
end
fout_min = $fopen(`FOUT_MIN, "w+");
fout_max = $fopen(`FOUT_MAX, "w+");
fout_state = $fopen(`FOUT_STATE, "w+");
fout_toggle = $fopen(`FOUT_TOGGLE, "w+");
fout_high = $fopen(`FOUT_HIGH, "w+");
fout_highz = $fopen(`FOUT_HIGHZ, "w+");
fout_lowz = $fopen(`FOUT_LOWZ, "w+");
fout_low = $fopen(`FOUT_LOW, "w+");
if (!$feof(fin))
adc_d = $fgetc(fin); // read the first value
end
always
# 1 clk = !clk;
// input
initial
begin
while (!$feof(fin)) begin
@(negedge clk) adc_d <= $fgetc(fin);
end
if ($feof(fin))
begin
# 3 $fclose(fin);
$fclose(fout_state);
$fclose(fout_toggle);
$fclose(fout_high);
$fclose(fout_highz);
$fclose(fout_lowz);
$fclose(fout_low);
$fclose(fout_min);
$fclose(fout_max);
$finish;
end
end
initial
begin
// $monitor("%d\t S: %b, E: %b", $time, edge_state, edge_toggle);
end
// output
always @(negedge clk)
if ($time > 2) begin
r = $fputc(min, fout_min);
r = $fputc(max, fout_max);
r = $fputc(edge_state, fout_state);
r = $fputc(edge_toggle, fout_toggle);
r = $fputc(high_threshold, fout_high);
r = $fputc(highz_threshold, fout_highz);
r = $fputc(lowz_threshold, fout_lowz);
r = $fputc(low_threshold, fout_low);
end
// module to test
lf_edge_detect detect(clk, adc_d, 8'd127,
max, min,
high_threshold, highz_threshold,
lowz_threshold, low_threshold,
edge_state, edge_toggle);
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3 (lin64) Build 1034051 Fri Oct 3 16:31:15 MDT 2014
// Date : Sun Oct 25 15:42:23 2015
// Host : arthas-ubuntu running 64-bit Ubuntu 14.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/arthas/git/SHD/SHD.srcs/sources_1/ip/pcie_recv_fifo/pcie_recv_fifo_stub.v
// Design : pcie_recv_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.3" *)
module pcie_recv_fifo(clk, srst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,srst,din[255:0],wr_en,rd_en,dout[255:0],full,empty" */;
input clk;
input srst;
input [255:0]din;
input wr_en;
input rd_en;
output [255:0]dout;
output full;
output empty;
endmodule
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: DATENPFAD.v
// Version: 1.1 bug fix
// History: 1.0 first release of 30 Mai 2015
// Date: 7 October 2015
//
// Copyright (C) 2015 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// DATENPFAD the data path of M32632
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX,
IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE,
WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, REG_OUT, PTB_SEL, PTB_WR, ACB_ZERO,
ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG,
DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT);
input BCLK;
input BRESET;
input WREN; // write enable of the register file
input IO_READY;
input LD_DIN;
input LD_IMME;
input WR_REG; // write signal for the DP_FPU
input IC_USER;
input RWVFLAG;
input [14:0] ACC_FELD;
input [5:0] ACC_STAT;
input [31:0] DIN;
input [31:0] DISP;
input [2:0] IC_TEX;
input [31:0] IMME_Q;
input [6:0] INFO_AU;
input [1:0] LD_OUT;
input [12:0] DETOIP;
input [1:0] MMU_UPDATE;
input [10:0] OPER;
input [31:0] PC_ARCHI;
input [31:0] PC_ICACHE;
input [7:0] RDAA;
input [7:0] RDAB;
input [1:0] START;
input [1:0] WMASKE;
input [5:0] WRADR;
input DBG_HIT;
input COP_DONE;
input [23:0] COP_OP;
input [63:0] COP_IN;
output DONE;
output Y_INIT;
output WRITE_OUT;
output READ_OUT;
output ZTEST;
output RMW;
output QWATWO;
output ACC_DONE;
output REG_OUT;
output PTB_SEL;
output PTB_WR;
output reg ACB_ZERO;
output ABORT;
output SAVE_PC;
output [12:0] CFG;
output [3:0] CINV;
output [63:0] DP_Q;
output [1:0] IVAR;
output [3:0] MCR;
output [3:0] PACKET;
output [31:0] PC_NEW;
output [11:0] PSR;
output [1:0] SIZE;
output [4:0] STRING;
output [5:0] TRAPS;
output [31:0] VADR;
output [40:2] DBG_IN;
output COP_GO;
output [127:0] COP_OUT;
reg [31:0] high_dq;
reg [31:0] OUT_I;
reg [31:0] BYDIN; // the bypass register
wire [2:0] BITSEL;
wire [1:0] BWD;
wire CLR_LSB;
wire [31:0] ERGEBNIS; // the result bus
wire FL;
wire [31:0] FSR;
wire [63:0] MRESULT;
wire [7:0] OPCODE;
wire SELI_A;
wire SELI_B;
wire [2:0] SP_CMP;
wire [31:0] SRC1; // the bus for the Source 1 operand
wire [31:0] SRC2; // the bus for the Source 2 operand
wire [4:0] TT_DP;
wire TWREN; // active if FPU Trap occurs
wire UP_DP;
wire WRADR_0;
wire WREN_L,WREN_LX;
wire LD_FSR;
wire UP_SP;
wire [4:0] TT_SP;
wire [31:0] addr_i;
wire [2:0] DP_CMP;
wire [31:0] DP_OUT;
wire [31:0] SFP_DAT;
wire ld_out_l;
wire [6:0] BMCODE;
wire [31:0] OUT_A,OUT_B;
wire SP_MUX;
wire [31:0] I_OUT;
wire [31:0] FP_OUT;
wire DOWR;
wire [31:0] DEST1,DEST2;
wire ENWR;
wire [3:0] OVF_BCD;
wire [3:0] DSR;
wire acb_zero_i;
wire [31:0] BMASKE;
assign FL = OPER[10];
assign BWD = OPER[9:8];
assign OPCODE = OPER[7:0];
assign ERGEBNIS = SP_MUX ? FP_OUT : I_OUT;
assign WRADR_0 = WRADR[0] ^ CLR_LSB;
assign ENWR = WREN_L | WREN;
assign DOWR = ENWR & TWREN;
assign WREN_L = WREN_LX & ~TRAPS[0];
assign DP_Q[63:32] = high_dq;
assign PC_NEW = SRC1;
always @(posedge BCLK) if (LD_OUT[1] || WREN) ACB_ZERO <= acb_zero_i;
always @(posedge BCLK) if (LD_OUT[1] || ld_out_l) high_dq <= ERGEBNIS;
always @(posedge BCLK) if (LD_DIN) OUT_I <= LD_IMME ? IMME_Q : DIN;
always @(posedge BCLK) if (RDAA[7]) BYDIN <= ERGEBNIS;
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Register Set 1 => SRC1
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
REGISTER REG_SET_A(
.BCLK(BCLK),
.ENWR(ENWR),
.DOWR(DOWR),
.DIN(ERGEBNIS),
.BYDIN(BYDIN),
.RADR(RDAA),
.WADR({WRADR[5:1],WRADR_0}),
.WMASKE(WMASKE),
.SELI(SELI_A),
.DOUT(OUT_A));
assign SRC1 = SELI_A ? OUT_I : OUT_A;
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Register Set 2 => SRC2
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
REGISTER REG_SET_B(
.BCLK(BCLK),
.ENWR(ENWR),
.DOWR(DOWR),
.DIN(ERGEBNIS),
.BYDIN(BYDIN),
.RADR(RDAB),
.WADR({WRADR[5:1],WRADR_0}),
.WMASKE(WMASKE),
.SELI(SELI_B),
.DOUT(OUT_B));
assign SRC2 = SELI_B ? OUT_I : OUT_B;
MULFILTER M_FILTER(
.FLOAT(OPCODE[2]),
.BWD(BWD),
.SRC1(SRC1),
.SRC2(SRC2),
.DEST1(DEST1),
.DEST2(DEST2));
SIGNMUL S_MULTI( // signed multiplier 32 * 32 bits = 64 bits
.dataa(DEST1),
.datab(DEST2),
.result(MRESULT));
BITMASK BITM_U(
.AA(BMCODE),
.DOUT(BMASKE));
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// The integer data path
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
I_PFAD GANZ_U(
.FL(FL),
.BRESET(BRESET),
.BCLK(BCLK),
.WREN(WREN),
.LD_OUT(LD_OUT[1]),
.ADDR(addr_i),
.BITSEL(BITSEL),
.BMASKE(BMASKE),
.BWD(BWD),
.DP_CMP(DP_CMP),
.DP_OUT(DP_OUT),
.FSR(FSR),
.DETOIP(DETOIP[11:0]),
.MRESULT(MRESULT),
.OPCODE(OPCODE),
.RDAA(RDAA),
.SFP_DAT(SFP_DAT),
.SP_CMP(SP_CMP),
.SRC1(SRC1),
.SRC2(SRC2),
.WRADR(WRADR),
.DSR(DSR),
.OV_FLAG(TRAPS[2]),
.ACB_ZERO(acb_zero_i),
.BMCODE(BMCODE),
.I_OUT(I_OUT),
.PSR(PSR),
.STRING(STRING),
.OVF_BCD(OVF_BCD),
.DISP(DISP[4:0]),
.RWVFLAG(RWVFLAG));
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// The address unit
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
ADDR_UNIT ADDR_U(
.BCLK(BCLK),
.BRESET(BRESET),
.IO_READY(IO_READY),
.READ(ACC_FELD[11]),
.WRITE(ACC_FELD[10]),
.CLRMSW(ACC_FELD[2]),
.FULLACC(ACC_FELD[8]),
.POST(ACC_FELD[3]),
.DISP_OK(INFO_AU[0]),
.LDEA(ACC_FELD[9]),
.NEWACC(ACC_FELD[14]),
.FPU_TRAP(TRAPS[0]),
.ADIVAR(INFO_AU[2]),
.RWVAL_1(INFO_AU[3]),
.ABO_STAT({INFO_AU[1],IC_USER}),
.ACC_STAT(ACC_STAT),
.ASIZE(ACC_FELD[13:12]),
.BWD(BWD),
.DISP(DISP),
.IC_TEX(IC_TEX),
.INDEX(ACC_FELD[7:4]),
.MMU_UPDATE(MMU_UPDATE),
.PC_ARCHI(PC_ARCHI),
.PC_ICACHE(PC_ICACHE),
.SRC1(SRC1),
.SRC2(SRC2),
.SRC2SEL(ACC_FELD[1:0]),
.REG_OUT(REG_OUT),
.ACC_DONE(ACC_DONE),
.READ_OUT(READ_OUT),
.WRITE_OUT(WRITE_OUT),
.ABORT(ABORT),
.ADDR(addr_i),
.BITSEL(BITSEL),
.PACKET(PACKET),
.SIZE(SIZE),
.VADR(VADR),
.ZTEST(ZTEST),
.RMW(RMW),
.QWATWO(QWATWO),
.OP_RMW(INFO_AU[4]),
.PHASE_17(INFO_AU[5]),
.NO_TRAP(INFO_AU[6]) );
CONFIG_REGS CFG_DBG(
.BCLK(BCLK),
.BRESET(BRESET),
.WREN(WREN),
.LD_OUT(LD_OUT[1]),
.OPCODE(OPCODE),
.SRC1(SRC1),
.WRADR(WRADR),
.PTB_WR(PTB_WR),
.PTB_SEL(PTB_SEL),
.CFG(CFG),
.CINV(CINV),
.IVAR(IVAR),
.Y_INIT(Y_INIT),
.MCR(MCR),
.DBG_TRAPS(TRAPS[5:3]),
.PC_ARCHI(PC_ARCHI),
.DSR(DSR),
.USER(PSR[8]),
.PCMATCH(DETOIP[12]),
.DBG_IN(DBG_IN),
.DBG_HIT(DBG_HIT),
.READ(READ_OUT) );
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// The long operation unit
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
DP_FPU DOUBLE_U(
.BCLK(BCLK),
.FL(FL),
.BRESET(BRESET),
.LD_LDQ(LD_OUT[0]),
.WR_REG(WR_REG),
.BWD(BWD),
.FSR(FSR[8:3]),
.OPCODE(OPCODE),
.SRC1(SRC1),
.SRC2(SRC2),
.START(START),
.DONE(DONE),
.UP_DP(UP_DP),
.WREN_L(WREN_LX),
.CLR_LSB(CLR_LSB),
.LD_OUT_L(ld_out_l),
.DVZ_TRAP(TRAPS[1]),
.DP_CMP(DP_CMP),
.DP_OUT(DP_OUT),
.DP_Q(DP_Q[31:0]),
.TT_DP(TT_DP),
.CY_IN(PSR[0]),
.OVF_BCD(OVF_BCD),
.COP_DONE(COP_DONE),
.COP_OP(COP_OP),
.COP_IN(COP_IN),
.COP_GO(COP_GO),
.COP_OUT(COP_OUT));
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// The single precision floating point unit
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//SP_FPU SINGLE_U(
// .FL(FL),
// .BCLK(BCLK),
// .BWD(BWD),
// .FSR(FSR[8:3]),
// .MRESULT(MRESULT[47:0]),
// .OPCODE(OPCODE),
// .SRC1(SRC1),
// .SRC2(SRC2),
// .LD_FSR(LD_FSR),
// .SP_MUX(SP_MUX),
// .UP_SP(UP_SP),
// .FP_OUT(FP_OUT),
// .I_OUT(SFP_DAT),
// .SP_CMP(SP_CMP),
// .TT_SP(TT_SP));
assign FP_OUT = 32'b0;
assign SFP_DAT = 32'b0;
assign TT_SP = 5'b0;
assign SP_CMP = 3'b0;
assign SP_MUX = 1'b0;
assign LD_FSR = 1'b0;
assign UP_SP = 1'b0;
FP_STAT_REG FPS_REG(
.BCLK(BCLK),
.BRESET(BRESET),
.LFSR(LD_FSR),
.WREN(ENWR),
.WRADR(WRADR[5:4]),
.UP_DP(UP_DP),
.UP_SP(UP_SP & LD_OUT[1]),
.DIN(SRC1[16:0]),
.TT_DP(TT_DP),
.TT_SP(TT_SP),
.FPU_TRAP(TRAPS[0]),
.TWREN(TWREN),
.SAVE_PC(SAVE_PC),
.FSR(FSR));
endmodule
|
// AJ, Beck, and Ray
// DE1_SoCPhaseII testbench
// 5/4/15
`include "Implementation/mux2_1.sv"
`include "Implementation/mux4_1.sv"
`include "Implementation/mux8_1.sv"
`include "Implementation/mux32_1.sv"
`include "Implementation/register.sv"
`include "Implementation/registerSingle.sv"
`include "Implementation/DFlipFlop.sv"
`include "Implementation/counter.v"
`include "Implementation/decoder5_32.sv"
`include "Implementation/decoder8_256.sv"
`include "Implementation/decoder11_2048.sv"
`include "adder_subtractor.v"
`include "flag.v"
`include "adder16b.v"
`include "adder4b.v"
`include "fullAdder1b.v"
`include "lookAhead4b.v"
`include "addition.v"
`include "subtract.v"
`include "andGate.v"
`include "orGate.v"
`include "xorGate.v"
`include "setLT.v"
`include "shiftll.v"
`include "DE1_SoCPhaseII.v"
`include "InstrucDecoder.v"
`include "ALUnit.sv"
`include "SRAM2Kby16.v"
`include "registerFile.sv"
module DE1_SoCPhaseIItest();
// localize variables
wire CLOCK_50; // connect to system 50 MHz clock
wire [9:0] LEDR;
wire [9:0] SW;
wire [3:0] KEY;
// declare an instance of the module
DE1_SoCPhaseII DE1_SoCPhaseII (CLOCK_50, LEDR, SW, KEY);
// Running the GUI part of simulation
DE1_SoCPhaseIItester tester (CLOCK_50, LEDR, SW, KEY);
// file for gtkwave
initial
begin
$dumpfile("PhaseIItest.vcd");
$dumpvars(1, DE1_SoCPhaseII);
end
endmodule
module DE1_SoCPhaseIItester (CLOCK_50, LEDR, SW, KEY);
output reg CLOCK_50; // connect to system 50 MHz clock
input [9:0] LEDR;
output reg [9:0] SW;
output [3:0] KEY;
parameter d = 20;
// generate a clock
always #(d/2) CLOCK_50 = ~CLOCK_50;
initial // Response
begin
$display("CLOCK_50 \t LEDR \t SW \t\t KEY \t ");
#d;
end
initial
begin
$monitor("%b \t %b \t %b \t %b \t %b \t ", CLOCK_50, LEDR, SW, KEY, $time);
SW[9] = 1'b1; #d
SW[9] = 1'b0; #(300*d)
SW[6] = 1'b1; #(300*d)
$stop;
$finish;
end
endmodule |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_a_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_a_e.v,v 1.4 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_a_e.v,v $
// Revision 1.4 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_a_e
//
// No `defines in this module
module inst_a_e
//
// Generated Module inst_a
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_1
inst_1_e inst_1 (
);
defparam inst_1.FOO = 16;
// End of Generated Instance Port Map for inst_1
// Generated Instance Port Map for inst_10
inst_10_e inst_10 (
);
defparam inst_10.FOO = 32;
// End of Generated Instance Port Map for inst_10
// Generated Instance Port Map for inst_2
inst_2_e inst_2 (
);
defparam inst_2.FOO = 16;
// End of Generated Instance Port Map for inst_2
// Generated Instance Port Map for inst_3
inst_3_e inst_3 (
);
defparam inst_3.FOO = 16;
// End of Generated Instance Port Map for inst_3
// Generated Instance Port Map for inst_4
inst_4_e inst_4 (
);
defparam inst_4.FOO = 16;
// End of Generated Instance Port Map for inst_4
// Generated Instance Port Map for inst_5
inst_5_e inst_5 (
);
// End of Generated Instance Port Map for inst_5
// Generated Instance Port Map for inst_6
inst_6_e inst_6 (
);
// End of Generated Instance Port Map for inst_6
// Generated Instance Port Map for inst_7
inst_7_e inst_7 (
);
defparam inst_7.FOO = 32;
// End of Generated Instance Port Map for inst_7
// Generated Instance Port Map for inst_8
inst_8_e inst_8 (
);
defparam inst_8.FOO = 32;
// End of Generated Instance Port Map for inst_8
// Generated Instance Port Map for inst_9
inst_9_e inst_9 (
);
defparam inst_9.FOO = 32;
// End of Generated Instance Port Map for inst_9
// Generated Instance Port Map for inst_aa
inst_aa_e inst_aa (
);
defparam inst_aa.NO_DEFAULT = "nodefault",
inst_aa.NO_NAME = "noname",
inst_aa.WIDTH = 15;
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
inst_ab_e inst_ab (
);
defparam inst_ab.WIDTH = 31;
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
inst_ac_e inst_ac (
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
inst_ad_e inst_ad (
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
inst_ae_e inst_ae (
);
// End of Generated Instance Port Map for inst_ae
// Generated Instance Port Map for inst_m1
inst_m_e inst_m1 (
);
defparam inst_m1.FOO = 15;
// End of Generated Instance Port Map for inst_m1
// Generated Instance Port Map for inst_m10
inst_m_e inst_m10 (
);
defparam inst_m10.FOO = 30;
// End of Generated Instance Port Map for inst_m10
// Generated Instance Port Map for inst_m2
inst_m_e inst_m2 (
);
defparam inst_m2.FOO = 15;
// End of Generated Instance Port Map for inst_m2
// Generated Instance Port Map for inst_m3
inst_m_e inst_m3 (
);
defparam inst_m3.FOO = 15;
// End of Generated Instance Port Map for inst_m3
// Generated Instance Port Map for inst_m4
inst_m_e inst_m4 (
);
defparam inst_m4.FOO = 15;
// End of Generated Instance Port Map for inst_m4
// Generated Instance Port Map for inst_m5
inst_m_e inst_m5 (
);
defparam inst_m5.FOO = 15;
// End of Generated Instance Port Map for inst_m5
// Generated Instance Port Map for inst_m6
inst_m_e inst_m6 (
);
defparam inst_m6.FOO = 30;
// End of Generated Instance Port Map for inst_m6
// Generated Instance Port Map for inst_m7
inst_m_e inst_m7 (
);
defparam inst_m7.FOO = 30;
// End of Generated Instance Port Map for inst_m7
// Generated Instance Port Map for inst_m8
inst_m_e inst_m8 (
);
defparam inst_m8.FOO = 30;
// End of Generated Instance Port Map for inst_m8
// Generated Instance Port Map for inst_m9
inst_m_e inst_m9 (
);
defparam inst_m9.FOO = 30;
// End of Generated Instance Port Map for inst_m9
endmodule
//
// End of Generated Module rtl of inst_a_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1500364331 : 255;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD3_1_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD3_1_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv3sd3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkdlyinv3sd3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd3_1 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkdlyinv3sd3 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd3_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkdlyinv3sd3 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD3_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHETAP_2_V
`define SKY130_FD_SC_LS__DECAPHETAP_2_V
/**
*
* Verilog wrapper for decaphetap with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decaphetap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphetap_2 (
VPWR,
VGND,
VPB
);
input VPWR;
input VGND;
input VPB ;
sky130_fd_sc_ls__decaphetap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphetap_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
sky130_fd_sc_ls__decaphetap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHETAP_2_V
|
/*
* NAME
* ----
*
* mem_ctl - memory control
*
*
* DESCRIPTION
* -----------
*
* Module for interfacing an Alliance AS6C1008 128x8 RAM chip
* on to an 8-bit data bus and a 7-bit address bus.
*
* AUTHOR
* ------
*
* Jeremiah Mahler <[email protected]>
*
*/
module mem_ctl(
input read_n,
write_n,
ce_n,
input [6:0] address_bus,
inout [7:0] data_bus,
inout [7:0] mem_data,
output [16:0] mem_address,
output wire ceh_n,
ce2,
we_n,
oe_n);
// tie unused address bits low
assign mem_address[16:7] = 0;
assign mem_address[6:0] = address_bus;
// if read enabled, drive current data, otherwise go hi Z
// for READ
assign data_bus = (~(ce_n | read_n | ~write_n)) ? mem_data : 8'bz;
// The following line is used to test read cycle, see mem_ctl-test.v
// Comment out the one above when using it.
//assign data_bus = (~(ce_n | read_n | ~write_n)) ? 8'hee : 8'bz;
// for WRITE
assign mem_data = (~(ce_n | write_n | ~read_n)) ? data_bus : 8'bz;
// No "timing" is required for the control lines.
// This just follows the truth table given on page 3 of
// the Alliance RAM data sheet.
assign ceh_n = 1'b0;
assign ce2 = 1'b1;
// for READ
assign oe_n = (~(ce_n | read_n)) ? 1'b0 : 1'b1;
// for WRITE
assign we_n = (~(ce_n | write_n | ~read_n)) ? 1'b0 : 1'b1;
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="fir,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.912000,HLS_SYN_LAT=67,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=4,HLS_SYN_FF=561,HLS_SYN_LUT=266}" *)
module fir (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
y,
y_ap_vld,
c_address0,
c_ce0,
c_q0,
x,
x_ap_vld
);
parameter ap_ST_fsm_state1 = 7'd1;
parameter ap_ST_fsm_state2 = 7'd2;
parameter ap_ST_fsm_state3 = 7'd4;
parameter ap_ST_fsm_state4 = 7'd8;
parameter ap_ST_fsm_state5 = 7'd16;
parameter ap_ST_fsm_state6 = 7'd32;
parameter ap_ST_fsm_state7 = 7'd64;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output [31:0] y;
output y_ap_vld;
output [3:0] c_address0;
output c_ce0;
input [31:0] c_q0;
input [31:0] x;
input x_ap_vld;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg y_ap_vld;
reg c_ce0;
(* fsm_encoding = "none" *) reg [6:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg [31:0] x_preg;
reg [31:0] x_in_sig;
reg x_ap_vld_preg;
reg x_ap_vld_in_sig;
reg [3:0] shift_reg_address0;
reg shift_reg_ce0;
reg shift_reg_we0;
reg [31:0] shift_reg_d0;
wire [31:0] shift_reg_q0;
reg x_blk_n;
reg ap_block_state1;
wire signed [31:0] i_cast_fu_143_p1;
reg signed [31:0] i_cast_reg_190;
wire ap_CS_fsm_state2;
wire [0:0] tmp_1_fu_155_p2;
reg [0:0] tmp_1_reg_199;
wire [0:0] tmp_fu_147_p3;
wire ap_CS_fsm_state3;
wire [4:0] grp_fu_136_p2;
reg [4:0] i_1_reg_218;
reg signed [31:0] c_load_reg_223;
wire ap_CS_fsm_state4;
wire [31:0] grp_fu_174_p2;
reg [31:0] tmp_6_reg_228;
wire ap_CS_fsm_state6;
wire [31:0] acc_1_fu_179_p2;
wire ap_CS_fsm_state7;
reg [31:0] acc_reg_101;
wire [4:0] i_phi_fu_118_p4;
reg [4:0] i_reg_114;
reg signed [31:0] data1_reg_126;
wire [63:0] tmp_3_fu_161_p1;
wire [63:0] tmp_4_fu_166_p1;
wire [63:0] tmp_5_fu_170_p1;
reg [4:0] grp_fu_136_p0;
wire ap_CS_fsm_state5;
reg [6:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 7'd1;
#0 x_preg = 32'd0;
#0 x_ap_vld_preg = 1'b0;
end
fir_shift_reg #(
.DataWidth( 32 ),
.AddressRange( 11 ),
.AddressWidth( 4 ))
shift_reg_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(shift_reg_address0),
.ce0(shift_reg_ce0),
.we0(shift_reg_we0),
.d0(shift_reg_d0),
.q0(shift_reg_q0)
);
fir_mul_32s_32s_3bkb #(
.ID( 1 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
fir_mul_32s_32s_3bkb_U1(
.clk(ap_clk),
.reset(ap_rst),
.din0(c_load_reg_223),
.din1(data1_reg_126),
.ce(1'b1),
.dout(grp_fu_174_p2)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
x_ap_vld_preg <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd1))) begin
x_ap_vld_preg <= 1'b0;
end else if (((1'b1 == x_ap_vld) & ~((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1)))) begin
x_ap_vld_preg <= x_ap_vld;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
x_preg <= 32'd0;
end else begin
if (((1'b1 == x_ap_vld) & ~((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1)))) begin
x_preg <= x;
end
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state7)) begin
acc_reg_101 <= acc_1_fu_179_p2;
end else if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == x_ap_vld_in_sig)))) begin
acc_reg_101 <= 32'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state3) & (tmp_1_reg_199 == 1'd0))) begin
data1_reg_126 <= shift_reg_q0;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd0) & (tmp_1_fu_155_p2 == 1'd1))) begin
data1_reg_126 <= x_in_sig;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state7)) begin
i_reg_114 <= i_1_reg_218;
end else if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == x_ap_vld_in_sig)))) begin
i_reg_114 <= 5'd10;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state4)) begin
c_load_reg_223 <= c_q0;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
i_1_reg_218 <= grp_fu_136_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
i_cast_reg_190 <= i_cast_fu_143_p1;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd0))) begin
tmp_1_reg_199 <= tmp_1_fu_155_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state6)) begin
tmp_6_reg_228 <= grp_fu_174_p2;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd1))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
c_ce0 = 1'b1;
end else begin
c_ce0 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
grp_fu_136_p0 = i_reg_114;
end else if ((1'b1 == ap_CS_fsm_state2)) begin
grp_fu_136_p0 = i_phi_fu_118_p4;
end else begin
grp_fu_136_p0 = 'bx;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
shift_reg_address0 = tmp_4_fu_166_p1;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd0) & (tmp_1_fu_155_p2 == 1'd1))) begin
shift_reg_address0 = 4'd0;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd0) & (tmp_1_fu_155_p2 == 1'd0))) begin
shift_reg_address0 = tmp_3_fu_161_p1;
end else begin
shift_reg_address0 = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd0) & (tmp_1_fu_155_p2 == 1'd0)) | (1'b1 == ap_CS_fsm_state3) | ((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd0) & (tmp_1_fu_155_p2 == 1'd1)))) begin
shift_reg_ce0 = 1'b1;
end else begin
shift_reg_ce0 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
shift_reg_d0 = shift_reg_q0;
end else if (((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd0) & (tmp_1_fu_155_p2 == 1'd1))) begin
shift_reg_d0 = x_in_sig;
end else begin
shift_reg_d0 = 'bx;
end
end
always @ (*) begin
if ((((1'b1 == ap_CS_fsm_state3) & (tmp_1_reg_199 == 1'd0)) | ((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd0) & (tmp_1_fu_155_p2 == 1'd1)))) begin
shift_reg_we0 = 1'b1;
end else begin
shift_reg_we0 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == x_ap_vld)) begin
x_ap_vld_in_sig = x_ap_vld;
end else begin
x_ap_vld_in_sig = x_ap_vld_preg;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
x_blk_n = x_ap_vld;
end else begin
x_blk_n = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == x_ap_vld)) begin
x_in_sig = x;
end else begin
x_in_sig = x_preg;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd1))) begin
y_ap_vld = 1'b1;
end else begin
y_ap_vld = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == x_ap_vld_in_sig)))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if (((1'b1 == ap_CS_fsm_state2) & (tmp_fu_147_p3 == 1'd1))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_state3;
end
end
ap_ST_fsm_state3 : begin
ap_NS_fsm = ap_ST_fsm_state4;
end
ap_ST_fsm_state4 : begin
ap_NS_fsm = ap_ST_fsm_state5;
end
ap_ST_fsm_state5 : begin
ap_NS_fsm = ap_ST_fsm_state6;
end
ap_ST_fsm_state6 : begin
ap_NS_fsm = ap_ST_fsm_state7;
end
ap_ST_fsm_state7 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign acc_1_fu_179_p2 = (tmp_6_reg_228 + acc_reg_101);
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4];
assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5];
assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6];
always @ (*) begin
ap_block_state1 = ((1'b0 == ap_start) | (1'b0 == x_ap_vld_in_sig));
end
assign c_address0 = tmp_5_fu_170_p1;
assign grp_fu_136_p2 = ($signed(grp_fu_136_p0) + $signed(5'd31));
assign i_cast_fu_143_p1 = $signed(i_reg_114);
assign i_phi_fu_118_p4 = i_reg_114;
assign tmp_1_fu_155_p2 = ((i_reg_114 == 5'd0) ? 1'b1 : 1'b0);
assign tmp_3_fu_161_p1 = grp_fu_136_p2;
assign tmp_4_fu_166_p1 = $unsigned(i_cast_reg_190);
assign tmp_5_fu_170_p1 = $unsigned(i_cast_reg_190);
assign tmp_fu_147_p3 = i_reg_114[32'd4];
assign y = acc_reg_101;
endmodule //fir
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_delta_assert #(
.width(width),
.min(min),
.max(max))
assert_delta_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_delta_assume #(
.width(width),
.min(min),
.max(max))
assert_delta_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_delta_cover #(
.width(width),
.min(min),
.max(max),
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON),
.OVL_COVER_CORNER_ON(OVL_COVER_CORNER_ON))
assert_delta_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_delta.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_delta_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 1;
parameter max = 2;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_delta_assume (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 8;
parameter min = 1;
parameter max = 2;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_delta_cover (clk, reset_n, test_expr);
parameter width = 8;
parameter min = 1;
parameter max = 2;
parameter OVL_COVER_BASIC_ON = 1;
parameter OVL_COVER_CORNER_ON = 1;
input clk, reset_n;
input [width-1:0] test_expr;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31AI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O31AI_FUNCTIONAL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o31ai (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31AI_FUNCTIONAL_V |
// ======================================================================
// Bootloader.v generated from TopDesign.cysch
// 10/13/2017 at 13:27
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC5LP 2
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_PSOC5TM 3
`define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1
`define CYDEV_CHIP_REV_PSOC5TM_ES1 1
`define CYDEV_CHIP_REV_PSOC5TM_ES0 0
`define CYDEV_CHIP_DIE_TMA4 4
`define CYDEV_CHIP_REV_TMA4_PRODUCTION 17
`define CYDEV_CHIP_REV_TMA4_ES 17
`define CYDEV_CHIP_REV_TMA4_ES2 33
`define CYDEV_CHIP_DIE_PSOC4A 5
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PSOC6ABLE2 6
`define CYDEV_CHIP_REV_PSOC6ABLE2_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC6ABLE2_NO_UDB 0
`define CYDEV_CHIP_DIE_VOLANS 7
`define CYDEV_CHIP_REV_VOLANS_PRODUCTION 0
`define CYDEV_CHIP_DIE_BERRYPECKER 8
`define CYDEV_CHIP_REV_BERRYPECKER_PRODUCTION 0
`define CYDEV_CHIP_DIE_CRANE 9
`define CYDEV_CHIP_REV_CRANE_PRODUCTION 0
`define CYDEV_CHIP_DIE_FM3 10
`define CYDEV_CHIP_REV_FM3_PRODUCTION 0
`define CYDEV_CHIP_DIE_FM4 11
`define CYDEV_CHIP_REV_FM4_PRODUCTION 0
`define CYDEV_CHIP_DIE_EXPECT 2
`define CYDEV_CHIP_REV_EXPECT 0
`define CYDEV_CHIP_DIE_ACTUAL 2
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_FAMILY_PSOC6 4
`define CYDEV_CHIP_FAMILY_FM0P 5
`define CYDEV_CHIP_FAMILY_FM3 6
`define CYDEV_CHIP_FAMILY_FM4 7
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_MEMBER_5B 2
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_MEMBER_5A 3
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_4G 4
`define CYDEV_CHIP_REVISION_4G_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4G_ES 17
`define CYDEV_CHIP_REVISION_4G_ES2 33
`define CYDEV_CHIP_MEMBER_4U 5
`define CYDEV_CHIP_REVISION_4U_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4E 6
`define CYDEV_CHIP_REVISION_4E_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4O 7
`define CYDEV_CHIP_REVISION_4O_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4R 8
`define CYDEV_CHIP_REVISION_4R_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4N 9
`define CYDEV_CHIP_REVISION_4N_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4S 10
`define CYDEV_CHIP_REVISION_4S_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4Q 11
`define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4D 12
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4J 13
`define CYDEV_CHIP_REVISION_4J_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4K 14
`define CYDEV_CHIP_REVISION_4K_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4H 15
`define CYDEV_CHIP_REVISION_4H_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4A 16
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4F 17
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4P 18
`define CYDEV_CHIP_REVISION_4P_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4M 19
`define CYDEV_CHIP_REVISION_4M_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4L 20
`define CYDEV_CHIP_REVISION_4L_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4I 21
`define CYDEV_CHIP_REVISION_4I_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_6A 22
`define CYDEV_CHIP_REVISION_6A_PRODUCTION 0
`define CYDEV_CHIP_REVISION_6A_NO_UDB 0
`define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 23
`define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 24
`define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 25
`define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_FM3 26
`define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_FM4 27
`define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0
`define CYDEV_CHIP_FAMILY_USED 3
`define CYDEV_CHIP_MEMBER_USED 2
`define CYDEV_CHIP_REVISION_USED 0
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// USBFS_v3_20(AudioDescriptors=<?xml version="1.0" encoding="utf-16"?>\r\n<Tree xmlns:CustomizerVersion="3_0">\r\n <Tree_x0020_Descriptors>\r\n <DescriptorNode Key="Audio">\r\n <Nodes />\r\n </DescriptorNode>\r\n </Tree_x0020_Descriptors>\r\n</Tree>, CDCDescriptors=<?xml version="1.0" encoding="utf-16"?>\r\n<Tree xmlns:CustomizerVersion="3_0">\r\n <Tree_x0020_Descriptors>\r\n <DescriptorNode Key="CDC">\r\n <Nodes />\r\n </DescriptorNode>\r\n </Tree_x0020_Descriptors>\r\n</Tree>, DeviceDescriptors=<?xml version="1.0" encoding="utf-16"?>\r\n<Tree xmlns:CustomizerVersion="3_0">\r\n <Tree_x0020_Descriptors>\r\n <DescriptorNode Key="Device">\r\n <Nodes>\r\n <DescriptorNode Key="USBDescriptor149">\r\n <m_value d6p1:type="DeviceDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>DEVICE</bDescriptorType>\r\n <bLength>18</bLength>\r\n <iwManufacturer>147</iwManufacturer>\r\n <iwProduct>148</iwProduct>\r\n <sManufacturer>Cypress Semiconductor</sManufacturer>\r\n <sProduct>PSoC3 Bootloader</sProduct>\r\n <sSerialNumber>0001</sSerialNumber>\r\n <bDeviceClass>0</bDeviceClass>\r\n <bDeviceSubClass>0</bDeviceSubClass>\r\n <bDeviceProtocol>0</bDeviceProtocol>\r\n <bMaxPacketSize0>0</bMaxPacketSize0>\r\n <idVendor>1204</idVendor>\r\n <idProduct>46877</idProduct>\r\n <bcdDevice>12289</bcdDevice>\r\n <bcdUSB>512</bcdUSB>\r\n <iManufacturer>1</iManufacturer>\r\n <iProduct>2</iProduct>\r\n <iSerialNumber>0</iSerialNumber>\r\n <bNumConfigurations>1</bNumConfigurations>\r\n <bMemoryMgmt>0</bMemoryMgmt>\r\n <bMemoryAlloc>0</bMemoryAlloc>\r\n </m_value>\r\n <Value d6p1:type="DeviceDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>DEVICE</bDescriptorType>\r\n <bLength>18</bLength>\r\n <iwManufacturer>147</iwManufacturer>\r\n <iwProduct>148</iwProduct>\r\n <sManufacturer>Cypress Semiconductor</sManufacturer>\r\n <sProduct>PSoC3 Bootloader</sProduct>\r\n <sSerialNumber>0001</sSerialNumber>\r\n <bDeviceClass>0</bDeviceClass>\r\n <bDeviceSubClass>0</bDeviceSubClass>\r\n <bDeviceProtocol>0</bDeviceProtocol>\r\n <bMaxPacketSize0>0</bMaxPacketSize0>\r\n <idVendor>1204</idVendor>\r\n <idProduct>46877</idProduct>\r\n <bcdDevice>12289</bcdDevice>\r\n <bcdUSB>512</bcdUSB>\r\n <iManufacturer>1</iManufacturer>\r\n <iProduct>2</iProduct>\r\n <iSerialNumber>0</iSerialNumber>\r\n <bNumConfigurations>1</bNumConfigurations>\r\n <bMemoryMgmt>0</bMemoryMgmt>\r\n <bMemoryAlloc>0</bMemoryAlloc>\r\n </Value>\r\n <Nodes>\r\n <DescriptorNode Key="USBDescriptor154">\r\n <m_value d8p1:type="ConfigDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>CONFIGURATION</bDescriptorType>\r\n <bLength>9</bLength>\r\n <iwConfiguration>0</iwConfiguration>\r\n <wTotalLength>41</wTotalLength>\r\n <bNumInterfaces>1</bNumInterfaces>\r\n <bConfigurationValue>0</bConfigurationValue>\r\n <iConfiguration>0</iConfiguration>\r\n <bmAttributes>128</bmAttributes>\r\n <bMaxPower>50</bMaxPower>\r\n </m_value>\r\n <Value d8p1:type="ConfigDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>CONFIGURATION</bDescriptorType>\r\n <bLength>9</bLength>\r\n <iwConfiguration>0</iwConfiguration>\r\n <wTotalLength>41</wTotalLength>\r\n <bNumInterfaces>1</bNumInterfaces>\r\n <bConfigurationValue>0</bConfigurationValue>\r\n <iConfiguration>0</iConfiguration>\r\n <bmAttributes>128</bmAttributes>\r\n <bMaxPower>50</bMaxPower>\r\n </Value>\r\n <Nodes>\r\n <DescriptorNode Key="Interface158">\r\n <m_value d10p1:type="InterfaceGeneralDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>ALTERNATE</bDescriptorType>\r\n <bLength>0</bLength>\r\n <DisplayName />\r\n </m_value>\r\n <Value d10p1:type="InterfaceGeneralDescriptor" xmlns:d10p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>ALTERNATE</bDescriptorType>\r\n <bLength>0</bLength>\r\n <DisplayName />\r\n </Value>\r\n <Nodes>\r\n <DescriptorNode Key="USBDescriptor159">\r\n <m_value d12p1:type="InterfaceDescriptor" xmlns:d12p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>INTERFACE</bDescriptorType>\r\n <bLength>9</bLength>\r\n <iwInterface>148</iwInterface>\r\n <bInterfaceClass>3</bInterfaceClass>\r\n <bAlternateSetting>0</bAlternateSetting>\r\n <bInterfaceNumber>0</bInterfaceNumber>\r\n <bNumEndpoints>2</bNumEndpoints>\r\n <bInterfaceSubClass>0</bInterfaceSubClass>\r\n <bInterfaceProtocol>0</bInterfaceProtocol>\r\n <iInterface>2</iInterface>\r\n <sInterface>PSoC3 Bootloader</sInterface>\r\n </m_value>\r\n <Value d12p1:type="InterfaceDescriptor" xmlns:d12p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>INTERFACE</bDescriptorType>\r\n <bLength>9</bLength>\r\n <iwInterface>148</iwInterface>\r\n <bInterfaceClass>3</bInterfaceClass>\r\n <bAlternateSetting>0</bAlternateSetting>\r\n <bInterfaceNumber>0</bInterfaceNumber>\r\n <bNumEndpoints>2</bNumEndpoints>\r\n <bInterfaceSubClass>0</bInterfaceSubClass>\r\n <bInterfaceProtocol>0</bInterfaceProtocol>\r\n <iInterface>2</iInterface>\r\n <sInterface>PSoC3 Bootloader</sInterface>\r\n </Value>\r\n <Nodes>\r\n <DescriptorNode Key="USBDescriptor161">\r\n <m_value d14p1:type="EndpointDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>ENDPOINT</bDescriptorType>\r\n <bLength>7</bLength>\r\n <DoubleBuffer>false</DoubleBuffer>\r\n <bInterval>1</bInterval>\r\n <bEndpointAddress>1</bEndpointAddress>\r\n <bmAttributes>3</bmAttributes>\r\n <wMaxPacketSize>64</wMaxPacketSize>\r\n </m_value>\r\n <Value d14p1:type="EndpointDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>ENDPOINT</bDescriptorType>\r\n <bLength>7</bLength>\r\n <DoubleBuffer>false</DoubleBuffer>\r\n <bInterval>1</bInterval>\r\n <bEndpointAddress>1</bEndpointAddress>\r\n <bmAttributes>3</bmAttributes>\r\n <wMaxPacketSize>64</wMaxPacketSize>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor162">\r\n <m_value d14p1:type="HIDDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID</bDescriptorType>\r\n <bLength>9</bLength>\r\n <bReportIndex>1</bReportIndex>\r\n <wReportIndex>126</wReportIndex>\r\n <bcdHID>0</bcdHID>\r\n <bCountryCode>0</bCountryCode>\r\n <bNumDescriptors>1</bNumDescriptors>\r\n <bDescriptorType1>34</bDescriptorType1>\r\n <wDescriptorLength>36</wDescriptorLength>\r\n </m_value>\r\n <Value d14p1:type="HIDDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID</bDescriptorType>\r\n <bLength>9</bLength>\r\n <bReportIndex>1</bReportIndex>\r\n <wReportIndex>126</wReportIndex>\r\n <bcdHID>0</bcdHID>\r\n <bCountryCode>0</bCountryCode>\r\n <bNumDescriptors>1</bNumDescriptors>\r\n <bDescriptorType1>34</bDescriptorType1>\r\n <wDescriptorLength>36</wDescriptorLength>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor163">\r\n <m_value d14p1:type="EndpointDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>ENDPOINT</bDescriptorType>\r\n <bLength>7</bLength>\r\n <DoubleBuffer>false</DoubleBuffer>\r\n <bInterval>1</bInterval>\r\n <bEndpointAddress>130</bEndpointAddress>\r\n <bmAttributes>3</bmAttributes>\r\n <wMaxPacketSize>64</wMaxPacketSize>\r\n </m_value>\r\n <Value d14p1:type="EndpointDescriptor" xmlns:d14p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>ENDPOINT</bDescriptorType>\r\n <bLength>7</bLength>\r\n <DoubleBuffer>false</DoubleBuffer>\r\n <bInterval>1</bInterval>\r\n <bEndpointAddress>130</bEndpointAddress>\r\n <bmAttributes>3</bmAttributes>\r\n <wMaxPacketSize>64</wMaxPacketSize>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n </Nodes>\r\n </DescriptorNode>\r\n </Nodes>\r\n </DescriptorNode>\r\n </Nodes>\r\n </DescriptorNode>\r\n </Nodes>\r\n </DescriptorNode>\r\n </Nodes>\r\n </DescriptorNode>\r\n </Tree_x0020_Descriptors>\r\n</Tree>, DmaChannelPriority=3, DW_Hide_DmaAuto=true, DW_Hide_Usbv2Regs=true, DW_RegSize=8, DW_USB_CHGDET_CTRL=CR0, DW_USB_INTR_CAUSE_HI=CR0, DW_USB_INTR_CAUSE_LO=CR0, DW_USB_INTR_CAUSE_MED=CR0, DW_USB_INTR_LVL_SEL=CR0, DW_USB_INTR_SIE=CR0, DW_USB_INTR_SIE_MASK=CR0, DW_USB_LPM_CTRL=CR0, DW_USB_LPM_STAT=CR0, DW_USB_POWER_CTRL=CR0, EnableBatteryChargDetect=false, EnableCDCApi=true, EnableMidiApi=true, endpointMA=0, endpointMM=0, epDMAautoOptimization=false, extern_cls=false, extern_vbus=true, extern_vnd=false, extJackCount=0, Gen16bitEpAccessApi=false, HandleMscRequests=true, HIDReportDescriptors=<?xml version="1.0" encoding="utf-16"?>\r\n<Tree xmlns:CustomizerVersion="3_0">\r\n <Tree_x0020_Descriptors>\r\n <DescriptorNode Key="HIDReport">\r\n <Nodes>\r\n <DescriptorNode Key="USBDescriptor126">\r\n <m_value d6p1:type="HIDReportDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT</bDescriptorType>\r\n <bLength>2</bLength>\r\n <Name>Generic HID</Name>\r\n <wLength>36</wLength>\r\n </m_value>\r\n <Value d6p1:type="HIDReportDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT</bDescriptorType>\r\n <bLength>2</bLength>\r\n <Name>Generic HID</Name>\r\n <wLength>36</wLength>\r\n </Value>\r\n <Nodes>\r\n <DescriptorNode Key="USBDescriptor127">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="4" Type="USAGE_PAGE">\r\n <Description>(Generic Desktop Controls)</Description>\r\n <Value>\r\n <unsignedByte>5</unsignedByte>\r\n <unsignedByte>1</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="4" Type="USAGE_PAGE">\r\n <Description>(Generic Desktop Controls)</Description>\r\n <Value>\r\n <unsignedByte>5</unsignedByte>\r\n <unsignedByte>1</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor129">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="8" Type="USAGE">\r\n <Description>(Undefined)</Description>\r\n <Value>\r\n <unsignedByte>9</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="8" Type="USAGE">\r\n <Description>(Undefined)</Description>\r\n <Value>\r\n <unsignedByte>9</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor130">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="160" Type="COLLECTION">\r\n <Description>(Physical)</Description>\r\n <Value>\r\n <unsignedByte>161</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="160" Type="COLLECTION">\r\n <Description>(Physical)</Description>\r\n <Value>\r\n <unsignedByte>161</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor131">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="8" Type="USAGE">\r\n <Description>(Undefined)</Description>\r\n <Value>\r\n <unsignedByte>9</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="8" Type="USAGE">\r\n <Description>(Undefined)</Description>\r\n <Value>\r\n <unsignedByte>9</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor132">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="160" Type="COLLECTION">\r\n <Description>(Physical)</Description>\r\n <Value>\r\n <unsignedByte>161</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="160" Type="COLLECTION">\r\n <Description>(Physical)</Description>\r\n <Value>\r\n <unsignedByte>161</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor133">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="8" Type="USAGE">\r\n <Description>(Undefined)</Description>\r\n <Value>\r\n <unsignedByte>9</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="8" Type="USAGE">\r\n <Description>(Undefined)</Description>\r\n <Value>\r\n <unsignedByte>9</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor134">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="20" Type="LOGICAL_MINIMUM">\r\n <Value>\r\n <unsignedByte>21</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="20" Type="LOGICAL_MINIMUM">\r\n <Value>\r\n <unsignedByte>21</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor135">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="36" Type="LOGICAL_MAXIMUM">\r\n <Value>\r\n <unsignedByte>37</unsignedByte>\r\n <unsignedByte>255</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="36" Type="LOGICAL_MAXIMUM">\r\n <Value>\r\n <unsignedByte>37</unsignedByte>\r\n <unsignedByte>255</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor136">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="116" Type="REPORT_SIZE">\r\n <Value>\r\n <unsignedByte>117</unsignedByte>\r\n <unsignedByte>8</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="116" Type="REPORT_SIZE">\r\n <Value>\r\n <unsignedByte>117</unsignedByte>\r\n <unsignedByte>8</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor137">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="148" Type="REPORT_COUNT">\r\n <Value>\r\n <unsignedByte>149</unsignedByte>\r\n <unsignedByte>64</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="148" Type="REPORT_COUNT">\r\n <Value>\r\n <unsignedByte>149</unsignedByte>\r\n <unsignedByte>64</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor138">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="144" Type="OUTPUT">\r\n <Description>(Var)</Description>\r\n <Value>\r\n <unsignedByte>145</unsignedByte>\r\n <unsignedByte>2</unsignedByte>\r\n </Value>\r\n <Kind>Bits</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="144" Type="OUTPUT">\r\n <Description>(Var)</Description>\r\n <Value>\r\n <unsignedByte>145</unsignedByte>\r\n <unsignedByte>2</unsignedByte>\r\n </Value>\r\n <Kind>Bits</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor139">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="8" Type="USAGE">\r\n <Description>(Undefined)</Description>\r\n <Value>\r\n <unsignedByte>9</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="8" Type="USAGE">\r\n <Description>(Undefined)</Description>\r\n <Value>\r\n <unsignedByte>9</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>List</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor140">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="20" Type="LOGICAL_MINIMUM">\r\n <Value>\r\n <unsignedByte>21</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="20" Type="LOGICAL_MINIMUM">\r\n <Value>\r\n <unsignedByte>21</unsignedByte>\r\n <unsignedByte>0</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor141">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="36" Type="LOGICAL_MAXIMUM">\r\n <Value>\r\n <unsignedByte>37</unsignedByte>\r\n <unsignedByte>255</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="36" Type="LOGICAL_MAXIMUM">\r\n <Value>\r\n <unsignedByte>37</unsignedByte>\r\n <unsignedByte>255</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor142">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="116" Type="REPORT_SIZE">\r\n <Value>\r\n <unsignedByte>117</unsignedByte>\r\n <unsignedByte>8</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="116" Type="REPORT_SIZE">\r\n <Value>\r\n <unsignedByte>117</unsignedByte>\r\n <unsignedByte>8</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor143">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="148" Type="REPORT_COUNT">\r\n <Value>\r\n <unsignedByte>149</unsignedByte>\r\n <unsignedByte>64</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="148" Type="REPORT_COUNT">\r\n <Value>\r\n <unsignedByte>149</unsignedByte>\r\n <unsignedByte>64</unsignedByte>\r\n </Value>\r\n <Kind>Int</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor144">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="128" Type="INPUT">\r\n <Description>(Var)</Description>\r\n <Value>\r\n <unsignedByte>129</unsignedByte>\r\n <unsignedByte>2</unsignedByte>\r\n </Value>\r\n <Kind>Bits</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="128" Type="INPUT">\r\n <Description>(Var)</Description>\r\n <Value>\r\n <unsignedByte>129</unsignedByte>\r\n <unsignedByte>2</unsignedByte>\r\n </Value>\r\n <Kind>Bits</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor145">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="192" Type="END_COLLECTION">\r\n <Value>\r\n <unsignedByte>192</unsignedByte>\r\n </Value>\r\n <Kind>None</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="192" Type="END_COLLECTION">\r\n <Value>\r\n <unsignedByte>192</unsignedByte>\r\n </Value>\r\n <Kind>None</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor146">\r\n <m_value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="192" Type="END_COLLECTION">\r\n <Value>\r\n <unsignedByte>192</unsignedByte>\r\n </Value>\r\n <Kind>None</Kind>\r\n </Item>\r\n </m_value>\r\n <Value d8p1:type="HIDReportItemDescriptor" xmlns:d8p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>HID_REPORT_ITEM</bDescriptorType>\r\n <bLength>1</bLength>\r\n <Item Code="192" Type="END_COLLECTION">\r\n <Value>\r\n <unsignedByte>192</unsignedByte>\r\n </Value>\r\n <Kind>None</Kind>\r\n </Item>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n </Nodes>\r\n </DescriptorNode>\r\n </Nodes>\r\n </DescriptorNode>\r\n </Tree_x0020_Descriptors>\r\n</Tree>, isrGroupArbiter=0, isrGroupBusReset=2, isrGroupEp0=1, isrGroupEp1=1, isrGroupEp2=1, isrGroupEp3=1, isrGroupEp4=1, isrGroupEp5=1, isrGroupEp6=1, isrGroupEp7=1, isrGroupEp8=1, isrGroupLpm=0, isrGroupSof=2, M0S8USBDSS_BLOCK_COUNT_1=0, max_interfaces_num=1, MidiDescriptors=<?xml version="1.0" encoding="utf-16"?>\r\n<Tree xmlns:CustomizerVersion="3_0">\r\n <Tree_x0020_Descriptors>\r\n <DescriptorNode Key="Midi">\r\n <Nodes />\r\n </DescriptorNode>\r\n </Tree_x0020_Descriptors>\r\n</Tree>, Mode=false, mon_vbus=false, MscDescriptors=<?xml version="1.0" encoding="utf-16"?>\r\n<Tree xmlns:CustomizerVersion="3_0">\r\n <Tree_x0020_Descriptors>\r\n <DescriptorNode Key="MSC">\r\n <Nodes />\r\n </DescriptorNode>\r\n </Tree_x0020_Descriptors>\r\n</Tree>, MscLogicalUnitsNum=1, out_sof=false, Pid=F232, powerpad_vbus=false, PRIMITIVE_INSTANCE=USB, ProdactName=, ProdactRevision=, REG_SIZE=reg8, RemoveDmaAutoOpt=true, RemoveVbusPin=true, rm_arb_int=false, rm_dma_1=true, rm_dma_2=true, rm_dma_3=true, rm_dma_4=true, rm_dma_5=true, rm_dma_6=true, rm_dma_7=true, rm_dma_8=true, rm_dp_int=false, rm_ep_isr_0=false, rm_ep_isr_1=false, rm_ep_isr_2=false, rm_ep_isr_3=true, rm_ep_isr_4=true, rm_ep_isr_5=true, rm_ep_isr_6=true, rm_ep_isr_7=true, rm_ep_isr_8=true, rm_lpm_int=true, rm_ord_int=true, rm_sof_int=true, rm_usb_int=false, SofTermEnable=false, StringDescriptors=<?xml version="1.0" encoding="utf-16"?>\r\n<Tree xmlns:CustomizerVersion="3_0">\r\n <Tree_x0020_Descriptors>\r\n <DescriptorNode Key="String">\r\n <Nodes>\r\n <DescriptorNode Key="LANGID">\r\n <m_value d6p1:type="StringZeroDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>STRING</bDescriptorType>\r\n <bLength>4</bLength>\r\n <wLANGID>1033</wLANGID>\r\n </m_value>\r\n <Value d6p1:type="StringZeroDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>STRING</bDescriptorType>\r\n <bLength>4</bLength>\r\n <wLANGID>1033</wLANGID>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor147">\r\n <m_value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>STRING</bDescriptorType>\r\n <bLength>44</bLength>\r\n <snType>USER_ENTERED_TEXT</snType>\r\n <bString>Cypress Semiconductor</bString>\r\n <bUsed>false</bUsed>\r\n </m_value>\r\n <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>STRING</bDescriptorType>\r\n <bLength>44</bLength>\r\n <snType>USER_ENTERED_TEXT</snType>\r\n <bString>Cypress Semiconductor</bString>\r\n <bUsed>false</bUsed>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="USBDescriptor148">\r\n <m_value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>STRING</bDescriptorType>\r\n <bLength>34</bLength>\r\n <snType>USER_ENTERED_TEXT</snType>\r\n <bString>PSoC3 Bootloader</bString>\r\n <bUsed>false</bUsed>\r\n </m_value>\r\n <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>STRING</bDescriptorType>\r\n <bLength>34</bLength>\r\n <snType>USER_ENTERED_TEXT</snType>\r\n <bString>PSoC3 Bootloader</bString>\r\n <bUsed>false</bUsed>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n </Nodes>\r\n </DescriptorNode>\r\n <DescriptorNode Key="SpecialString">\r\n <Nodes>\r\n <DescriptorNode Key="Serial">\r\n <m_value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>STRING</bDescriptorType>\r\n <bLength>10</bLength>\r\n <snType>USER_ENTERED_TEXT</snType>\r\n <bString>0001</bString>\r\n <bUsed>true</bUsed>\r\n </m_value>\r\n <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>STRING</bDescriptorType>\r\n <bLength>10</bLength>\r\n <snType>USER_ENTERED_TEXT</snType>\r\n <bString>0001</bString>\r\n <bUsed>true</bUsed>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n <DescriptorNode Key="EE">\r\n <m_value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>STRING</bDescriptorType>\r\n <bLength>16</bLength>\r\n <snType>USER_ENTERED_TEXT</snType>\r\n <bString>MSFT100</bString>\r\n <bUsed>false</bUsed>\r\n </m_value>\r\n <Value d6p1:type="StringDescriptor" xmlns:d6p1="http://www.w3.org/2001/XMLSchema-instance">\r\n <bDescriptorType>STRING</bDescriptorType>\r\n <bLength>16</bLength>\r\n <snType>USER_ENTERED_TEXT</snType>\r\n <bString>MSFT100</bString>\r\n <bUsed>false</bUsed>\r\n </Value>\r\n <Nodes />\r\n </DescriptorNode>\r\n </Nodes>\r\n </DescriptorNode>\r\n </Tree_x0020_Descriptors>\r\n</Tree>, UINT_TYPE=uint8, VbusDetectTermEnable=false, VendorName=, Vid=04B4, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMMENT=, CY_COMPONENT_NAME=USBFS_v3_20, CY_CONST_CONFIG=true, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=USBFS, CY_INSTANCE_SHORT_NAME=USBFS, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=20, CY_PDL_DRIVER_NAME=, CY_PDL_DRIVER_REQ_VERSION=, CY_PDL_DRIVER_SUBGROUP=, CY_PDL_DRIVER_VARIANT=, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 4.1 Update 1, INSTANCE_NAME=USBFS, )
module USBFS_v3_20_0 (
sof,
vbusdet);
output sof;
input vbusdet;
parameter epDMAautoOptimization = 0;
wire Net_1914;
wire Net_1915;
wire Net_1916;
wire Net_1917;
wire Net_1918;
wire Net_1919;
wire [7:0] dma_request;
wire Net_1920;
wire Net_1921;
wire Net_1922;
wire [7:0] Net_2039;
wire Net_2038;
wire Net_2037;
wire EPs_1_to_7_dma_complete;
wire Net_2036;
wire Net_2035;
wire Net_2034;
wire Net_2033;
wire Net_2032;
wire Net_2031;
wire Net_2030;
wire Net_2029;
wire Net_2028;
wire Net_2027;
wire Net_2026;
wire Net_2025;
wire Net_2024;
wire [7:0] Net_1940;
wire Net_1939;
wire Net_1938;
wire Net_1937;
wire Net_1936;
wire Net_1935;
wire Net_1934;
wire Net_1933;
wire Net_1932;
wire Net_2047;
wire Net_1202;
wire dma_terminate;
wire [7:0] Net_2040;
wire Net_1010;
electrical Net_1000;
electrical Net_597;
wire Net_1495;
wire Net_1498;
wire Net_1559;
wire Net_1567;
wire Net_1576;
wire Net_1579;
wire Net_1591;
wire [7:0] dma_complete;
wire Net_1588;
wire Net_1876;
wire [8:0] ep_int;
wire Net_1889;
wire busClk;
wire Net_95;
cy_isr_v1_0
#(.int_type(2'b10))
dp_int
(.int_signal(Net_1010));
wire [0:0] tmpOE__Dm_net;
wire [0:0] tmpFB_0__Dm_net;
wire [0:0] tmpIO_0__Dm_net;
wire [0:0] tmpINTERRUPT_0__Dm_net;
electrical [0:0] tmpSIOVREF__Dm_net;
cy_psoc3_pins_v1_10
#(.id("892f6c83-d52a-406f-8c41-59e053415832/8b77a6c4-10a0-4390-971c-672353e2a49c"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("NONCONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(1),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Dm
(.oe(tmpOE__Dm_net),
.y({1'b0}),
.fb({tmpFB_0__Dm_net[0:0]}),
.analog({Net_597}),
.io({tmpIO_0__Dm_net[0:0]}),
.siovref(tmpSIOVREF__Dm_net),
.interrupt({tmpINTERRUPT_0__Dm_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Dm_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Dp_net;
wire [0:0] tmpFB_0__Dp_net;
wire [0:0] tmpIO_0__Dp_net;
electrical [0:0] tmpSIOVREF__Dp_net;
cy_psoc3_pins_v1_10
#(.id("892f6c83-d52a-406f-8c41-59e053415832/618a72fc-5ddd-4df5-958f-a3d55102db42"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b10),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Dp
(.oe(tmpOE__Dp_net),
.y({1'b0}),
.fb({tmpFB_0__Dp_net[0:0]}),
.analog({Net_1000}),
.io({tmpIO_0__Dp_net[0:0]}),
.siovref(tmpSIOVREF__Dp_net),
.interrupt({Net_1010}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Dp_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_psoc3_usb_v1_0 USB (
.dp(Net_1000),
.dm(Net_597),
.sof_int(sof),
.arb_int(Net_1889),
.usb_int(Net_1876),
.ept_int(ep_int[8:0]),
.ord_int(Net_95),
.dma_req(dma_request[7:0]),
.dma_termin(dma_terminate));
cy_isr_v1_0
#(.int_type(2'b10))
ep_2
(.int_signal(ep_int[2]));
cy_isr_v1_0
#(.int_type(2'b10))
ep_1
(.int_signal(ep_int[1]));
cy_isr_v1_0
#(.int_type(2'b10))
ep_0
(.int_signal(ep_int[0]));
cy_isr_v1_0
#(.int_type(2'b10))
bus_reset
(.int_signal(Net_1876));
cy_isr_v1_0
#(.int_type(2'b10))
arb_int
(.int_signal(Net_1889));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign dma_complete[0] = Net_1922;
ZeroTerminal ZeroTerminal_1 (
.z(Net_1922));
// VirtualMux_2 (cy_virtualmux_v1_0)
assign dma_complete[1] = Net_1921;
ZeroTerminal ZeroTerminal_2 (
.z(Net_1921));
// VirtualMux_3 (cy_virtualmux_v1_0)
assign dma_complete[2] = Net_1920;
ZeroTerminal ZeroTerminal_3 (
.z(Net_1920));
// VirtualMux_4 (cy_virtualmux_v1_0)
assign dma_complete[3] = Net_1919;
ZeroTerminal ZeroTerminal_4 (
.z(Net_1919));
// VirtualMux_5 (cy_virtualmux_v1_0)
assign dma_complete[4] = Net_1918;
// VirtualMux_6 (cy_virtualmux_v1_0)
assign dma_complete[5] = Net_1917;
ZeroTerminal ZeroTerminal_5 (
.z(Net_1918));
ZeroTerminal ZeroTerminal_6 (
.z(Net_1917));
// VirtualMux_7 (cy_virtualmux_v1_0)
assign dma_complete[6] = Net_1916;
// VirtualMux_8 (cy_virtualmux_v1_0)
assign dma_complete[7] = Net_1915;
ZeroTerminal ZeroTerminal_7 (
.z(Net_1916));
ZeroTerminal ZeroTerminal_8 (
.z(Net_1915));
endmodule
// Component: OneTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v"
`endif
// PWM_v3_30(CaptureMode=0, Clock_CheckTolerance=true, Clock_desired_freq=12, Clock_desired_freq_unit=6, Clock_divisor=1, Clock_FractDividerDenominator=0, Clock_FractDividerNumerator=0, Clock_FractDividerUsed=false, Clock_is_direct=false, Clock_is_divider=false, Clock_is_freq=true, Clock_minus_tolerance=5, Clock_ph_align_clock_id=, Clock_ph_align_clock_name=, Clock_plus_tolerance=5, Clock_source_clock_id=, Clock_source_clock_name=, Compare1_16=false, Compare1_8=false, Compare2_16=false, Compare2_8=false, CompareStatusEdgeSense=true, CompareType1=1, CompareType1Software=0, CompareType2=1, CompareType2Software=0, CompareValue1=127, CompareValue2=63, CONTROL3=1, ControlReg=false, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG8, CySetRegReplacementString=CY_SET_REG8, DeadBand=0, DeadBand2_4=0, DeadBand256=0, DeadBandUsed=0, DeadTime=1, DitherOffset=0, EnableMode=0, FF16=false, FF8=true, FixedFunction=true, FixedFunctionUsed=1, InterruptOnCMP1=false, InterruptOnCMP2=false, InterruptOnKill=false, InterruptOnTC=false, IntOnCMP1=0, IntOnCMP2=0, IntOnKill=0, IntOnTC=0, KillMode=1, KillModeMinTime=0, MinimumKillTime=1, OneCompare=true, Period=255, PWMMode=0, PWMModeCenterAligned=0, RegDefReplacementString=reg8, RegSizeReplacementString=uint8, Resolution=8, RstStatusReplacementString=sSTSReg_rstSts, RunMode=0, Status=false, TermMode_capture=0, TermMode_clock=0, TermMode_cmp_sel=0, TermMode_enable=0, TermMode_interrupt=0, TermMode_kill=0, TermMode_ph1=0, TermMode_ph2=0, TermMode_pwm=0, TermMode_pwm1=0, TermMode_pwm2=0, TermMode_reset=0, TermMode_tc=0, TermMode_trigger=0, TermVisibility_capture=false, TermVisibility_clock=true, TermVisibility_cmp_sel=false, TermVisibility_enable=false, TermVisibility_interrupt=true, TermVisibility_kill=true, TermVisibility_ph1=false, TermVisibility_ph2=false, TermVisibility_pwm=true, TermVisibility_pwm1=false, TermVisibility_pwm2=false, TermVisibility_reset=true, TermVisibility_tc=true, TermVisibility_trigger=false, TriggerMode=0, UDB16=false, UDB8=false, UseControl=true, UseInterrupt=true, UseStatus=true, VerilogSectionReplacementString=sP8, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMMENT=, CY_COMPONENT_NAME=PWM_v3_30, CY_CONST_CONFIG=true, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=PWM_1, CY_INSTANCE_SHORT_NAME=PWM_1, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=30, CY_PDL_DRIVER_NAME=, CY_PDL_DRIVER_REQ_VERSION=, CY_PDL_DRIVER_SUBGROUP=, CY_PDL_DRIVER_VARIANT=, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 4.1 Update 1, INSTANCE_NAME=PWM_1, )
module PWM_v3_30_1 (
reset,
clock,
tc,
pwm1,
pwm2,
interrupt,
capture,
kill,
enable,
trigger,
cmp_sel,
pwm,
ph1,
ph2);
input reset;
input clock;
output tc;
output pwm1;
output pwm2;
output interrupt;
input capture;
input kill;
input enable;
input trigger;
input cmp_sel;
output pwm;
output ph1;
output ph2;
parameter Resolution = 8;
wire Net_114;
wire Net_113;
wire Net_107;
wire Net_96;
wire Net_55;
wire Net_57;
wire Net_101;
wire Net_54;
wire Net_63;
cy_psoc3_timer_v1_0 PWMHW (
.timer_reset(reset),
.capture(capture),
.enable(Net_113),
.kill(Net_107),
.clock(clock),
.tc(Net_63),
.compare(Net_57),
.interrupt(Net_54));
// vmCompare (cy_virtualmux_v1_0)
assign pwm = Net_57;
// vmIRQ (cy_virtualmux_v1_0)
assign interrupt = Net_54;
// vmTC (cy_virtualmux_v1_0)
assign tc = Net_63;
OneTerminal OneTerminal_1 (
.o(Net_113));
// FFKillMux (cy_virtualmux_v1_0)
assign Net_107 = kill;
ZeroTerminal ZeroTerminal_1 (
.z(Net_114));
endmodule
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// top
module top ;
wire Net_242;
wire Net_241;
wire Net_240;
wire Net_239;
wire Net_238;
wire Net_237;
wire Net_236;
wire Net_235;
wire Net_234;
wire Net_233;
wire Net_163;
electrical Net_47;
wire Net_244;
wire Net_243;
wire Net_177;
wire Net_17;
wire Net_137;
USBFS_v3_20_0 USBFS (
.sof(Net_243),
.vbusdet(1'b0));
defparam USBFS.epDMAautoOptimization = 0;
wire [0:0] tmpOE__LED_net;
wire [0:0] tmpFB_0__LED_net;
wire [0:0] tmpIO_0__LED_net;
wire [0:0] tmpINTERRUPT_0__LED_net;
electrical [0:0] tmpSIOVREF__LED_net;
cy_psoc3_pins_v1_10
#(.id("e851a3b9-efb8-48be-bbb8-b303b216c393"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b1),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
LED
(.oe(tmpOE__LED_net),
.y({Net_17}),
.fb({tmpFB_0__LED_net[0:0]}),
.io({tmpIO_0__LED_net[0:0]}),
.siovref(tmpSIOVREF__LED_net),
.interrupt({tmpINTERRUPT_0__LED_net[0:0]}),
.annotation({Net_47}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LED_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_clock_v1_0
#(.id("8d6e1ae2-bb1d-4c4c-bdac-a9fa60af6483"),
.source_clock_id(""),
.divisor(0),
.period("1000000000000"),
.is_direct(0),
.is_digital(1))
Clock_1
(.clock_out(Net_137));
PWM_v3_30_1 PWM_1 (
.reset(Net_177),
.clock(Net_137),
.tc(Net_233),
.pwm1(Net_234),
.pwm2(Net_235),
.interrupt(Net_236),
.capture(1'b0),
.kill(Net_177),
.enable(1'b1),
.trigger(1'b0),
.cmp_sel(1'b0),
.pwm(Net_17),
.ph1(Net_241),
.ph2(Net_242));
defparam PWM_1.Resolution = 8;
assign Net_177 = 1'h0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:52:53 06/12/2014
// Design Name:
// Module Name: seg7decimal
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seg7decimal(
input [15:0] x,
input clk,
input clr,
output reg [6:0] a_to_g,
output reg [3:0] an,
output wire dp
);
wire [1:0] s;
reg [3:0] digit;
wire [3:0] aen;
reg [19:0] clkdiv;
assign dp = 1;
assign s = clkdiv[19:18];
assign aen = 4'b1111; // all turned off initially
// quad 4to1 MUX.
always @(posedge clk)// or posedge clr)
case(s)
0:digit = x[3:0]; // s is 00 -->0 ; digit gets assigned 4 bit value assigned to x[3:0]
1:digit = x[7:4]; // s is 01 -->1 ; digit gets assigned 4 bit value assigned to x[7:4]
2:digit = x[11:8]; // s is 10 -->2 ; digit gets assigned 4 bit value assigned to x[11:8
3:digit = x[15:12]; // s is 11 -->3 ; digit gets assigned 4 bit value assigned to x[15:12]
default:digit = x[3:0];
endcase
//decoder or truth-table for 7a_to_g display values
always @(*)
case(digit)
//////////<---MSB-LSB<---
//////////////gfedcba//////////////////////////////////////////// a
0:a_to_g = 7'b1000000;////0000 __
1:a_to_g = 7'b1111001;////0001 f/ /b
2:a_to_g = 7'b0100100;////0010 g
// __
3:a_to_g = 7'b0110000;////0011 e / /c
4:a_to_g = 7'b0011001;////0100 __
5:a_to_g = 7'b0010010;////0101 d
6:a_to_g = 7'b0000010;////0110
7:a_to_g = 7'b1111000;////0111
8:a_to_g = 7'b0000000;////1000
9:a_to_g = 7'b0010000;////1001
'hA:a_to_g = 7'b0111111; // dash-(g)
'hB:a_to_g = 7'b1111111; // all turned off
'hC:a_to_g = 7'b1110111;
default: a_to_g = 7'b0000000; // U
endcase
always @(*)begin
an=4'b1111;
if(aen[s] == 1)
an[s] = 0;
end
//clkdiv
always @(posedge clk or posedge clr) begin
if ( clr == 1)
clkdiv <= 0;
else
clkdiv <= clkdiv+1;
end
endmodule
|
/* Buffer module testbench */
`timescale 1ns/1ns
module buffer_test();
localparam B = 1024;
reg CLOCK_50, rst;
reg [31:0] counter;
reg new_sample_val;
wire [31:0] pitch_shift_out;
wire pitch_shift_val;
// make reset
initial begin
CLOCK_50 = 1'b0;
rst = 1'b0;
counter = 32'b0;
new_sample_val = 1'b0;
#50
rst = 1'b1;
#100
rst = 1'b0;
end
// make clock
always begin
#10
CLOCK_50 = !CLOCK_50;
end
always begin
#50
counter = counter + 1;
new_sample_val = 1'b1;
#10
new_sample_val = 1'b0;
end
buffer #(B) b1
(
//inputs
.clk(CLOCK_50),
.rst(rst),
.delta(8'b01000000), // 1 in fixed3.5
.new_sample_val(new_sample_val),
.new_sample_data(counter),
.out_sel(1'b0),
.delta_mode(1'b0),
//outputs
.pitch_shift_out(pitch_shift_out),
.pitch_shift_val(pitch_shift_val)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_dp_macb_r.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_dp_macb_r(/*AUTOARG*/
// Outputs
data_out_cx_l, scan_out, shiftenable_buf,
// Inputs
arb_cpxdp_qsel1_ca, arb_cpxdp_qsel0_ca, arb_cpxdp_grant_ca,
arb_cpxdp_shift_cx, arb_cpxdp_q0_hold_ca, src_cpx_data_ca,
data_prev_cx_l, rclk, scan_in, shiftenable
);
output [149:0] data_out_cx_l; // cpx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_cpxdp_qsel1_ca; // queue write sel
input arb_cpxdp_qsel0_ca; // queue write sel
input arb_cpxdp_grant_ca;//grant signal
input arb_cpxdp_shift_cx;//grant signal
input arb_cpxdp_q0_hold_ca;//grant signal
input [149:0] src_cpx_data_ca; // scache to cpx data
input [149:0] data_prev_cx_l;
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_cx;
wire [149:0] q0_datain_ca;
wire [149:0] q1_dataout, q0_dataout;
wire [149:0] data_cx_l;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
/*
always @ (clk or arb_cpxdp_qsel1_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq1 = arb_cpxdp_qsel1_ca ;
end // always @ (clk or arb_cpxdp_qsel1_ca or tmb)
assign clkq1 = clkenq1 & clk;
always @ (clk or arb_cpxdp_q0_hold_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq0 = !arb_cpxdp_q0_hold_ca ;
end // always @ (clk or arb_cpxdp_q0_hold_ca or tmb)
assign clkq0 = clkenq0 & clk;
*/
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_cpxdp_q0_hold_ca),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_cpxdp_qsel1_ca),
.tmb_l(se_l));
dff_s #(1) dff_cpx_grin_r(
.din (arb_cpxdp_grant_ca),
.q (grant_cx),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(150) dff_cpx_datain_q1(
.din (src_cpx_data_ca[149:0]),
.q (q1_dataout[149:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
assign q0_datain_ca[149:0] =
(arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
(arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
dff_s #(150) dff_cpx_datain_q0(
.din (q0_datain_ca[149:0]),
.q (q0_dataout[149:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_cx_l[149:0] = ~(grant_cx ? q0_dataout[149:0] : 150'd0);
assign data_out_cx_l[149:0] = data_prev_cx_l[149:0] & data_cx_l[149:0];
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
// Code start here
//
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_P_PP_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_P_PP_SN_SYMBOL_V
/**
* udp_dlatch$P_pp$sN: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$P_pp$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input NOTIFIER
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_P_PP_SN_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4_BLACKBOX_V
`define SKY130_FD_SC_HD__OR4_BLACKBOX_V
/**
* or4: 4-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
v95 v95 ();
v01 v01 ();
v05 v05 ();
s05 s05 ();
s09 s09 ();
s12 s12 ();
s17 s17 ();
a23 a23 ();
initial begin
$finish;
end
endmodule
`begin_keywords "1364-1995"
module v95;
integer signed; initial signed = 1;
endmodule
`end_keywords
`begin_keywords "1364-2001"
module v01;
integer bit; initial bit = 1;
endmodule
`end_keywords
`begin_keywords "1364-2005"
module v05;
integer final; initial final = 1;
endmodule
`end_keywords
`begin_keywords "1800-2005"
module s05;
integer global; initial global = 1;
endmodule
`end_keywords
`begin_keywords "1800-2009"
module s09;
integer soft; initial soft = 1;
endmodule
`end_keywords
`begin_keywords "1800-2012"
module s12;
final begin
$write("*-* All Finished *-*\n");
end
endmodule
`end_keywords
`begin_keywords "1800-2017"
module s17;
final begin
$write("*-* All Finished *-*\n");
end
endmodule
`end_keywords
`begin_keywords "VAMS-2.3"
module a23;
real foo; initial foo = sqrt(2.0);
endmodule
`end_keywords
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_BLACKBOX_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_BLACKBOX_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlygate4sd1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_BLACKBOX_V
|
// This is an up-down counter with initial and max values.
// Moreover, it has an parameter for extra bits to be used
// for counter, in case of using for credit counters. Also
// up and down values could be variable, having max threshold
// of max_step_p.
`include "bsg_defines.v"
module bsg_counter_up_down_variable #( parameter `BSG_INV_PARAM(max_val_p )
, parameter `BSG_INV_PARAM(init_val_p )
, parameter `BSG_INV_PARAM(max_step_p )
//localpara
, parameter step_width_lp =
`BSG_WIDTH(max_step_p)
, parameter ptr_width_lp =
`BSG_WIDTH(max_val_p)
)
( input clk_i
, input reset_i
, input [step_width_lp-1:0] up_i
, input [step_width_lp-1:0] down_i
, output logic [ptr_width_lp-1:0] count_o
);
// keeping track of number of entries and updating read and
// write poniteres, and displaying errors in case of overflow
// or underflow
always_ff @(posedge clk_i)
begin
if (reset_i)
count_o <= init_val_p;
else
// It was tested on Design Compiler that using a
// simple minus and plus operation results in smaller
// design, rather than using xor or other ideas
// between down_i and up_i
count_o <= count_o - down_i + up_i;
end
//synopsys translate_off
always_ff @ (posedge clk_i) begin
if ((count_o==max_val_p) & up_i & (reset_i===0))
$display("%m error: counter overflow at time %t", $time);
if ((count_o==0) & down_i & (reset_i===0))
$display("%m error: counter underflow at time %t", $time);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_counter_up_down_variable)
|
`timescale 1ns / 1ps
//-----------------------------------------------------
// Design Name : syn_fifo
// File Name : syn_fifo.v
// Function : Synchronous (single clock) FIFO
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module syn_fifo (
clk , // Clock input
rst , // Active high reset
wr_cs , // Write chip select
rd_cs , // Read chipe select
data_in , // Data input
rd_en , // Read enable
wr_en , // Write Enable
data_out , // Data Output
empty , // FIFO empty
full // FIFO full
);
// FIFO constants
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = (1 << ADDR_WIDTH);
// Port Declarations
input clk ;
input rst ;
input wr_cs ;
input rd_cs ;
input rd_en ;
input wr_en ;
input [DATA_WIDTH-1:0] data_in ;
output full ;
output empty ;
output [DATA_WIDTH-1:0] data_out ;
//-----------Internal variables-------------------
reg [ADDR_WIDTH-1:0] wr_pointer;
reg [ADDR_WIDTH-1:0] rd_pointer;
reg [ADDR_WIDTH :0] status_cnt;
reg [DATA_WIDTH-1:0] data_out ;
wire [DATA_WIDTH-1:0] data_ram ;
//-----------Variable assignments---------------
assign full = (status_cnt == (RAM_DEPTH-1));
assign empty = (status_cnt == 0);
//-----------Code Start---------------------------
always @ (posedge clk or posedge rst)
begin : WRITE_POINTER
if (rst) begin
wr_pointer <= 0;
end else if (wr_cs && wr_en ) begin
wr_pointer <= wr_pointer + 1;
end
end
always @ (posedge clk or posedge rst)
begin : READ_POINTER
if (rst) begin
rd_pointer <= 0;
end else if (rd_cs && rd_en ) begin
rd_pointer <= rd_pointer + 1;
end
end
always @ (posedge clk or posedge rst)
begin : READ_DATA
if (rst) begin
data_out <= 0;
end else if (rd_cs && rd_en ) begin
data_out <= data_ram;
end
end
always @ (posedge clk or posedge rst)
begin : STATUS_COUNTER
if (rst) begin
status_cnt <= 0;
// Read but no write.
end else if ((rd_cs && rd_en) && !(wr_cs && wr_en)
&& (status_cnt != 0)) begin
status_cnt <= status_cnt - 1;
// Write but no read.
end else if ((wr_cs && wr_en) && !(rd_cs && rd_en)
&& (status_cnt != RAM_DEPTH)) begin
status_cnt <= status_cnt + 1;
end
end
ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
.address_0 (wr_pointer) , // address_0 input
.data_0 (data_in) , // data_0 bi-directional
.cs_0 (wr_cs) , // chip select
.we_0 (wr_en) , // write enable
.oe_0 (1'b0) , // output enable
.address_1 (rd_pointer) , // address_q input
.data_1 (data_ram) , // data_1 bi-directional
.cs_1 (rd_cs) , // chip select
.we_1 (1'b0) , // Read enable
.oe_1 (rd_en) // output enable
);
endmodule |
`define CYCLE_TIME 50
module TestBench;
reg Clk;
reg Reset;
reg Start;
integer i, outfile, outfile2, counter;
reg flag;
reg [26:0] address;
reg [23:0] tag;
reg [4:0] index;
wire [256-1:0] mem_cpu_data;
wire mem_cpu_ack;
wire [256-1:0] cpu_mem_data;
wire [32-1:0] cpu_mem_addr;
wire cpu_mem_enable;
wire cpu_mem_write;
always #(`CYCLE_TIME/2) Clk = ~Clk;
CPU CPU(
.clk (Clk),
.rst (Reset),
.start(Start),
.MemReadData(mem_cpu_data),
.MemAck(mem_cpu_ack),
.MemWriteData(cpu_mem_data),
.MemAddr(cpu_mem_addr),
.MemEnable(cpu_mem_enable),
.MemWrite(cpu_mem_write)
);
Data_Memory Data_Memory
(
.clk_i(Clk),
.rst_i (Reset),
.addr_i(cpu_mem_addr),
.data_i(cpu_mem_data),
.enable_i(cpu_mem_enable),
.write_i(cpu_mem_write),
.ack_o(mem_cpu_ack),
.data_o(mem_cpu_data)
);
initial begin
counter = 0;
// initialize instruction memory (2KB)
for(i=0; i<512; i=i+1) begin
CPU.Instruction_Memory.memory[i] = 32'b0;
end
// initialize data memory (16KB)
for(i=0; i<512; i=i+1) begin
Data_Memory.memory[i] = 256'b0;
end
// initialize cache memory (1KB)
for(i=0; i<32; i=i+1) begin
CPU.dcache.dcache_tag_sram.memory[i] = 24'b0;
CPU.dcache.dcache_data_sram.memory[i] = 256'b0;
end
// initialize Register File
for(i=0; i<32; i=i+1) begin
CPU.Registers.register[i] = 32'b0;
end
// Load instructions into instruction memory
$readmemb("instruction.txt", CPU.Instruction_Memory.memory);
// Open output file
outfile = $fopen("output.txt") | 1;
outfile2 = $fopen("cache.txt") | 1;
// Set Input n into data memory at 0x00
Data_Memory.memory[0] = 256'h5; // n = 5 for example
Clk = 1;
Start = 0;
Reset = 0;
#(`CYCLE_TIME/2)
Start = 1;
Reset = 1;
end
always@(posedge Clk) begin
if(counter == 150) begin // store cache to memory
$fdisplay(outfile, "Flush Cache! \n");
for(i=0; i<32; i=i+1) begin
tag = CPU.dcache.dcache_tag_sram.memory[i];
index = i;
address = {tag[21:0], index};
Data_Memory.memory[address] = CPU.dcache.dcache_data_sram.memory[i];
end
end
if(counter > 150) begin // stop
$stop;
end
$fdisplay(outfile, "cycle = %d, Start = %b", counter, Start);
// print PC
$fdisplay(outfile, "PC = %d", CPU.PC.pc_o);
// print Registers
$fdisplay(outfile, "Registers");
$fdisplay(outfile, "R0(r0) = %h, R8 (t0) = %h, R16(s0) = %h, R24(t8) = %h", CPU.Registers.register[0], CPU.Registers.register[8] , CPU.Registers.register[16], CPU.Registers.register[24]);
$fdisplay(outfile, "R1(at) = %h, R9 (t1) = %h, R17(s1) = %h, R25(t9) = %h", CPU.Registers.register[1], CPU.Registers.register[9] , CPU.Registers.register[17], CPU.Registers.register[25]);
$fdisplay(outfile, "R2(v0) = %h, R10(t2) = %h, R18(s2) = %h, R26(k0) = %h", CPU.Registers.register[2], CPU.Registers.register[10], CPU.Registers.register[18], CPU.Registers.register[26]);
$fdisplay(outfile, "R3(v1) = %h, R11(t3) = %h, R19(s3) = %h, R27(k1) = %h", CPU.Registers.register[3], CPU.Registers.register[11], CPU.Registers.register[19], CPU.Registers.register[27]);
$fdisplay(outfile, "R4(a0) = %h, R12(t4) = %h, R20(s4) = %h, R28(gp) = %h", CPU.Registers.register[4], CPU.Registers.register[12], CPU.Registers.register[20], CPU.Registers.register[28]);
$fdisplay(outfile, "R5(a1) = %h, R13(t5) = %h, R21(s5) = %h, R29(sp) = %h", CPU.Registers.register[5], CPU.Registers.register[13], CPU.Registers.register[21], CPU.Registers.register[29]);
$fdisplay(outfile, "R6(a2) = %h, R14(t6) = %h, R22(s6) = %h, R30(s8) = %h", CPU.Registers.register[6], CPU.Registers.register[14], CPU.Registers.register[22], CPU.Registers.register[30]);
$fdisplay(outfile, "R7(a3) = %h, R15(t7) = %h, R23(s7) = %h, R31(ra) = %h", CPU.Registers.register[7], CPU.Registers.register[15], CPU.Registers.register[23], CPU.Registers.register[31]);
// print Data Memory
$fdisplay(outfile, "Data Memory: 0x0000 = %h", Data_Memory.memory[0]);
$fdisplay(outfile, "Data Memory: 0x0020 = %h", Data_Memory.memory[1]);
$fdisplay(outfile, "Data Memory: 0x0040 = %h", Data_Memory.memory[2]);
$fdisplay(outfile, "Data Memory: 0x0060 = %h", Data_Memory.memory[3]);
$fdisplay(outfile, "Data Memory: 0x0080 = %h", Data_Memory.memory[4]);
$fdisplay(outfile, "Data Memory: 0x00A0 = %h", Data_Memory.memory[5]);
$fdisplay(outfile, "Data Memory: 0x00C0 = %h", Data_Memory.memory[6]);
$fdisplay(outfile, "Data Memory: 0x00E0 = %h", Data_Memory.memory[7]);
$fdisplay(outfile, "Data Memory: 0x0400 = %h", Data_Memory.memory[32]);
$fdisplay(outfile, "\n");
// print Data Cache Status
if(CPU.dcache.p1_stall_o && CPU.dcache.state==0) begin
if(CPU.dcache.sram_dirty) begin
if(CPU.dcache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h (Write Back!)", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_i);
else if(CPU.dcache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h (Write Back!)", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_o);
end
else begin
if(CPU.dcache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_i);
else if(CPU.dcache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_o);
end
flag = 1'b1;
end
else if(!CPU.dcache.p1_stall_o) begin
if(!flag) begin
if(CPU.dcache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Hit , Address: %h, Write Data: %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_i);
else if(CPU.dcache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Hit , Address: %h, Read Data : %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_o);
end
flag = 1'b0;
end
counter = counter + 1;
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_hdiv(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output reg pipe_ack_o,
input signed [11:0] x,
input signed [11:0] y,
input signed [17:0] tsx,
input signed [17:0] tsy,
input diff_x_positive,
input [16:0] diff_x,
input diff_y_positive,
input [16:0] diff_y,
input [10:0] dst_squarew,
output reg pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] x_f,
output reg signed [11:0] y_f,
output reg signed [17:0] tsx_f,
output reg signed [17:0] tsy_f,
output reg diff_x_positive_f,
output [16:0] diff_x_q,
output [16:0] diff_x_r,
output reg diff_y_positive_f,
output [16:0] diff_y_q,
output [16:0] diff_y_r
);
/* Divider bank */
reg start;
wire ready;
tmu2_divider17 d_x(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_x),
.divisor({6'd0, dst_squarew}),
.ready(ready),
.quotient(diff_x_q),
.remainder(diff_x_r)
);
tmu2_divider17 d_y(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.dividend(diff_y),
.divisor({6'd0, dst_squarew}),
.ready(),
.quotient(diff_y_q),
.remainder(diff_y_r)
);
/* Forward */
always @(posedge sys_clk) begin
if(start) begin
x_f <= x;
y_f <= y;
tsx_f <= tsx;
tsy_f <= tsy;
diff_x_positive_f <= diff_x_positive;
diff_y_positive_f <= diff_y_positive;
end
end
/* Glue logic */
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter WAIT = 1'b1;
always @(posedge sys_clk) begin
if(sys_rst)
state = IDLE;
else
state = next_state;
end
assign busy = state;
always @(*) begin
next_state = state;
start = 1'b0;
pipe_stb_o = 1'b0;
pipe_ack_o = 1'b0;
case(state)
IDLE: begin
pipe_ack_o = 1'b1;
if(pipe_stb_i) begin
start = 1'b1;
next_state = WAIT;
end
end
WAIT: begin
if(ready) begin
pipe_stb_o = 1'b1;
if(pipe_ack_i)
next_state = IDLE;
end
end
endcase
end
endmodule
|
`timescale 1 ns / 1 ps
`default_nettype none
`define WIDTH 16
module SB_RAM2048x2(
output [1:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
input [10:0] WADDR,
input [1:0] MASK, WDATA
);
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
wire [15:0] rd;
SB_RAM40_4K #(
.WRITE_MODE(3),
.READ_MODE(3),
.INIT_0(INIT_0),
.INIT_1(INIT_1),
.INIT_2(INIT_2),
.INIT_3(INIT_3),
.INIT_4(INIT_4),
.INIT_5(INIT_5),
.INIT_6(INIT_6),
.INIT_7(INIT_7),
.INIT_8(INIT_8),
.INIT_9(INIT_9),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.INIT_C(INIT_C),
.INIT_D(INIT_D),
.INIT_E(INIT_E),
.INIT_F(INIT_F)
) _ram (
.RDATA(rd),
.RADDR(RADDR),
.RCLK(RCLK), .RCLKE(RCLKE), .RE(RE),
.WCLK(WCLK), .WCLKE(WCLKE), .WE(WE),
.WADDR(WADDR),
.MASK(16'h0000), .WDATA({4'b0, WDATA[1], 7'b0, WDATA[0], 3'b0}));
assign RDATA[0] = rd[3];
assign RDATA[1] = rd[11];
endmodule
module top(input oscillator,
output D1,
output D2,
output D3,
output D4,
input S1,
input S2,
input S3,
input S4,
output TXD, // UART TX
input RXD, // UART RX
output SCK, // Flash SCK
input MISO, // Flash MISO
output MOSI, // Flash MOSI
output CS, // Flash CS
inout PORTA0,
inout PORTA1,
inout PORTA2,
inout PORTA3,
inout PORTA4,
inout PORTA5,
inout PORTA6,
inout PORTA7,
output Segment1A,
output Segment1B,
output Segment1C,
output Segment1D,
output Segment1E,
output Segment1F,
output Segment1G,
output Segment2A,
output Segment2B,
output Segment2C,
output Segment2D,
output Segment2E,
output Segment2F,
output Segment2G,
output VGA_HSync,
output VGA_VSync,
output VGA_Red_0,
output VGA_Red_1,
output VGA_Red_2,
output VGA_Grn_0,
output VGA_Grn_1,
output VGA_Grn_2,
output VGA_Blu_0,
output VGA_Blu_1,
output VGA_Blu_2
);
// wire resetq = 1'b1;
wire resetq = ~S4;
wire clk = oscillator;
wire io_rd, io_wr;
wire [15:0] mem_addr;
wire mem_wr;
wire [15:0] dout;
wire [15:0] io_din;
wire [12:0] code_addr;
reg unlocked = 0;
`include "../build/ram.v"
reg interrupt = 0;
// ###### PROCESSOR #####################################
j1 _j1(
.clk(clk),
.resetq(resetq),
.io_rd(io_rd),
.io_wr(io_wr),
.mem_wr(mem_wr),
.dout(dout),
.io_din(io_din),
.mem_addr(mem_addr),
.code_addr(code_addr),
.insn_from_memory(insn),
.interrupt_request(interrupt)
);
// ###### TICKS #########################################
reg [15:0] ticks;
wire [16:0] ticks_plus_1 = ticks + 1;
always @(posedge clk)
if (io_wr & mem_addr[14])
ticks <= dout;
else
ticks <= ticks_plus_1;
always @(posedge clk) // Generate interrupt on ticks overflow
interrupt <= ticks_plus_1[16];
// ###### PMOD ##########################################
reg [7:0] pmod_dir; // 1:output, 0:input
reg [7:0] pmod_out;
wire [7:0] pmod_in;
SB_IO #(.PIN_TYPE(6'b1010_01)) io0 (.PACKAGE_PIN(PORTA0), .D_OUT_0(pmod_out[0]), .D_IN_0(pmod_in[0]), .OUTPUT_ENABLE(pmod_dir[0]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io1 (.PACKAGE_PIN(PORTA1), .D_OUT_0(pmod_out[1]), .D_IN_0(pmod_in[1]), .OUTPUT_ENABLE(pmod_dir[1]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io2 (.PACKAGE_PIN(PORTA2), .D_OUT_0(pmod_out[2]), .D_IN_0(pmod_in[2]), .OUTPUT_ENABLE(pmod_dir[2]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io3 (.PACKAGE_PIN(PORTA3), .D_OUT_0(pmod_out[3]), .D_IN_0(pmod_in[3]), .OUTPUT_ENABLE(pmod_dir[3]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io4 (.PACKAGE_PIN(PORTA4), .D_OUT_0(pmod_out[4]), .D_IN_0(pmod_in[4]), .OUTPUT_ENABLE(pmod_dir[4]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io5 (.PACKAGE_PIN(PORTA5), .D_OUT_0(pmod_out[5]), .D_IN_0(pmod_in[5]), .OUTPUT_ENABLE(pmod_dir[5]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io6 (.PACKAGE_PIN(PORTA6), .D_OUT_0(pmod_out[6]), .D_IN_0(pmod_in[6]), .OUTPUT_ENABLE(pmod_dir[6]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io7 (.PACKAGE_PIN(PORTA7), .D_OUT_0(pmod_out[7]), .D_IN_0(pmod_in[7]), .OUTPUT_ENABLE(pmod_dir[7]));
// ###### UART ##########################################
wire uart0_valid, uart0_busy;
wire [7:0] uart0_data;
wire uart0_wr = io_wr & mem_addr[12];
wire uart0_rd = io_rd & mem_addr[12];
wire UART0_RX;
buart _uart0 (
.clk(clk),
.resetq(1'b1),
.rx(RXD),
.tx(TXD),
.rd(uart0_rd),
.wr(uart0_wr),
.valid(uart0_valid),
.busy(uart0_busy),
.tx_data(dout[7:0]),
.rx_data(uart0_data));
// ###### LEDS & PIOS ###################################
reg [2:0] PIOS;
assign {SCK, MOSI, CS} = PIOS;
reg [3:0] LEDS;
assign {D4,D3,D2,D1} = LEDS;
reg [13:0] SEGMENTS;
assign {Segment2G, Segment2F, Segment2E, Segment2D, Segment2C, Segment2B, Segment2A,
Segment1G, Segment1F, Segment1E, Segment1D, Segment1C, Segment1B, Segment1A } = ~SEGMENTS;
reg [10:0] VGA;
assign { VGA_VSync, VGA_HSync,
VGA_Blu_2, VGA_Blu_1, VGA_Blu_0,
VGA_Grn_2, VGA_Grn_1, VGA_Grn_0,
VGA_Red_2, VGA_Red_1, VGA_Red_0
} = VGA;
// ###### RING OSCILLATOR ###############################
wire [1:0] buffers_in, buffers_out;
assign buffers_in = {buffers_out[0:0], ~buffers_out[1]};
SB_LUT4 #(
.LUT_INIT(16'd2)
) buffers [1:0] (
.O(buffers_out),
.I0(buffers_in),
.I1(1'b0),
.I2(1'b0),
.I3(1'b0)
);
wire random = ~buffers_out[1];
// ###### IO PORTS ######################################
/* bit READ WRITE
0001 0 PMOD in
0002 1 PMOD out PMOD out
0004 2 PMOD dir PMOD dir
0008 3 misc.out misc.out
0010 4 VGA Colours
0020 5 VGA HSYNC
0040 6 VGA VSYNC
0080 7 Segments Segments
0100 8
0200 9
0400 10
0800 11
1000 12 UART RX UART TX
2000 13 misc.in
4000 14 ticks clear ticks
8000 15
*/
assign io_din =
(mem_addr[ 0] ? { 8'd0, pmod_in} : 16'd0) |
(mem_addr[ 1] ? { 8'd0, pmod_out} : 16'd0) |
(mem_addr[ 2] ? { 8'd0, pmod_dir} : 16'd0) |
(mem_addr[ 3] ? { 9'd0, LEDS, PIOS} : 16'd0) |
(mem_addr[ 7] ? { 2'd0, SEGMENTS} : 16'd0) |
(mem_addr[12] ? { 8'd0, uart0_data} : 16'd0) |
(mem_addr[13] ? { 9'd0, S3, S2, S1, random, MISO, uart0_valid, !uart0_busy} : 16'd0) |
(mem_addr[14] ? ticks : 16'd0) ;
// Very few gates needed: Simply trigger warmboot by any IO access to $8000 / $8001 / $8002 / $8003.
// SB_WARMBOOT _sb_warmboot ( .BOOT(io_wr & mem_addr[15]), .S1(mem_addr[1]), .S0(mem_addr[0]) );
always @(posedge clk) begin
if (io_wr & mem_addr[1]) pmod_out <= dout[7:0];
if (io_wr & mem_addr[2]) pmod_dir <= dout[7:0];
if (io_wr & mem_addr[3]) {LEDS, PIOS} <= dout[6:0];
if (io_wr & mem_addr[4]) {VGA[8:0]} <= dout[8:0];
if (io_wr & mem_addr[5]) {VGA[ 9]} <= dout[ 9];
if (io_wr & mem_addr[6]) {VGA[ 10]} <= dout[ 10];
if (io_wr & mem_addr[7]) SEGMENTS <= dout[13:0];
end
// ###### MEMLOCK #######################################
// This is a workaround to protect memory contents during Reset.
// Somehow it happens sometimes that the first memory location is corrupted during startup,
// and as an IO write is one of the earliest things which are done, memory write access is unlocked
// only after the processor is up and running and sending its welcome message.
always @(negedge resetq or posedge clk)
if (!resetq) unlocked <= 0;
else unlocked <= unlocked | io_wr;
endmodule // top
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:45:44 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_lmb_bram_0/system_lmb_bram_0_stub.v
// Design : system_lmb_bram_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
module system_lmb_bram_0(clka, rsta, ena, wea, addra, dina, douta, clkb, rstb, enb,
web, addrb, dinb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,rsta,ena,wea[3:0],addra[31:0],dina[31:0],douta[31:0],clkb,rstb,enb,web[3:0],addrb[31:0],dinb[31:0],doutb[31:0]" */;
input clka;
input rsta;
input ena;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DFSTP_FUNCTIONAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_lp__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_lp__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_lp__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSTP_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O311A_BEHAVIORAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_BEHAVIORAL_PP_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcieCore_gt_top.v
// Version : 1.11
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcieCore_gt_top #
(
parameter LINK_CAP_MAX_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
parameter USER_CLK2_DIV2 = "FALSE", // "FALSE" => user_clk2 = user_clk
// "TRUE" => user_clk2 = user_clk/2, where user_clk = 500 or 250 MHz.
parameter integer USER_CLK_FREQ = 3, // 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup
parameter PCIE_EXT_CLK = "FALSE", // Use External Clocking
parameter PCIE_USE_MODE = "1.0", // 1.0 = K325T IES, 1.1 = VX485T IES, 3.0 = K325T GES
parameter PCIE_GT_DEVICE = "GTX", // Select the GT to use (GTP for Artix-7, GTX for K7/V7)
parameter PCIE_PLL_SEL = "CPLL", // Select the PLL (CPLL or QPLL)
parameter PCIE_ASYNC_EN = "FALSE", // Asynchronous Clocking Enable
parameter PCIE_TXBUF_EN = "FALSE", // Use the Tansmit Buffer
parameter PCIE_CHAN_BOND = 0
)
(
//-----------------------------------------------------------------------------------------------------------------//
// pl ltssm
input wire [5:0] pl_ltssm_state ,
// Pipe Per-Link Signals
input wire pipe_tx_rcvr_det ,
input wire pipe_tx_reset ,
input wire pipe_tx_rate ,
input wire pipe_tx_deemph ,
input wire [2:0] pipe_tx_margin ,
input wire pipe_tx_swing ,
//-----------------------------------------------------------------------------------------------------------------//
// Clock Inputs //
//-----------------------------------------------------------------------------------------------------------------//
input PIPE_PCLK_IN,
input PIPE_RXUSRCLK_IN,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_IN,
input PIPE_DCLK_IN,
input PIPE_USERCLK1_IN,
input PIPE_USERCLK2_IN,
input PIPE_OOBCLK_IN,
input PIPE_MMCM_LOCK_IN,
output PIPE_TXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_PCLK_SEL_OUT,
output PIPE_GEN3_OUT,
// Pipe Per-Lane Signals - Lane 0
output wire [ 1:0] pipe_rx0_char_is_k ,
output wire [15:0] pipe_rx0_data ,
output wire pipe_rx0_valid ,
output wire pipe_rx0_chanisaligned ,
output wire [ 2:0] pipe_rx0_status ,
output wire pipe_rx0_phy_status ,
output wire pipe_rx0_elec_idle ,
input wire pipe_rx0_polarity ,
input wire pipe_tx0_compliance ,
input wire [ 1:0] pipe_tx0_char_is_k ,
input wire [15:0] pipe_tx0_data ,
input wire pipe_tx0_elec_idle ,
input wire [ 1:0] pipe_tx0_powerdown ,
// Pipe Per-Lane Signals - Lane 1
output wire [ 1:0] pipe_rx1_char_is_k ,
output wire [15:0] pipe_rx1_data ,
output wire pipe_rx1_valid ,
output wire pipe_rx1_chanisaligned ,
output wire [ 2:0] pipe_rx1_status ,
output wire pipe_rx1_phy_status ,
output wire pipe_rx1_elec_idle ,
input wire pipe_rx1_polarity ,
input wire pipe_tx1_compliance ,
input wire [ 1:0] pipe_tx1_char_is_k ,
input wire [15:0] pipe_tx1_data ,
input wire pipe_tx1_elec_idle ,
input wire [ 1:0] pipe_tx1_powerdown ,
// Pipe Per-Lane Signals - Lane 2
output wire [ 1:0] pipe_rx2_char_is_k ,
output wire [15:0] pipe_rx2_data ,
output wire pipe_rx2_valid ,
output wire pipe_rx2_chanisaligned ,
output wire [ 2:0] pipe_rx2_status ,
output wire pipe_rx2_phy_status ,
output wire pipe_rx2_elec_idle ,
input wire pipe_rx2_polarity ,
input wire pipe_tx2_compliance ,
input wire [ 1:0] pipe_tx2_char_is_k ,
input wire [15:0] pipe_tx2_data ,
input wire pipe_tx2_elec_idle ,
input wire [ 1:0] pipe_tx2_powerdown ,
// Pipe Per-Lane Signals - Lane 3
output wire [ 1:0] pipe_rx3_char_is_k ,
output wire [15:0] pipe_rx3_data ,
output wire pipe_rx3_valid ,
output wire pipe_rx3_chanisaligned ,
output wire [ 2:0] pipe_rx3_status ,
output wire pipe_rx3_phy_status ,
output wire pipe_rx3_elec_idle ,
input wire pipe_rx3_polarity ,
input wire pipe_tx3_compliance ,
input wire [ 1:0] pipe_tx3_char_is_k ,
input wire [15:0] pipe_tx3_data ,
input wire pipe_tx3_elec_idle ,
input wire [ 1:0] pipe_tx3_powerdown ,
// Pipe Per-Lane Signals - Lane 4
output wire [ 1:0] pipe_rx4_char_is_k ,
output wire [15:0] pipe_rx4_data ,
output wire pipe_rx4_valid ,
output wire pipe_rx4_chanisaligned ,
output wire [ 2:0] pipe_rx4_status ,
output wire pipe_rx4_phy_status ,
output wire pipe_rx4_elec_idle ,
input wire pipe_rx4_polarity ,
input wire pipe_tx4_compliance ,
input wire [ 1:0] pipe_tx4_char_is_k ,
input wire [15:0] pipe_tx4_data ,
input wire pipe_tx4_elec_idle ,
input wire [ 1:0] pipe_tx4_powerdown ,
// Pipe Per-Lane Signals - Lane 5
output wire [ 1:0] pipe_rx5_char_is_k ,
output wire [15:0] pipe_rx5_data ,
output wire pipe_rx5_valid ,
output wire pipe_rx5_chanisaligned ,
output wire [ 2:0] pipe_rx5_status ,
output wire pipe_rx5_phy_status ,
output wire pipe_rx5_elec_idle ,
input wire pipe_rx5_polarity ,
input wire pipe_tx5_compliance ,
input wire [ 1:0] pipe_tx5_char_is_k ,
input wire [15:0] pipe_tx5_data ,
input wire pipe_tx5_elec_idle ,
input wire [ 1:0] pipe_tx5_powerdown ,
// Pipe Per-Lane Signals - Lane 6
output wire [ 1:0] pipe_rx6_char_is_k ,
output wire [15:0] pipe_rx6_data ,
output wire pipe_rx6_valid ,
output wire pipe_rx6_chanisaligned ,
output wire [ 2:0] pipe_rx6_status ,
output wire pipe_rx6_phy_status ,
output wire pipe_rx6_elec_idle ,
input wire pipe_rx6_polarity ,
input wire pipe_tx6_compliance ,
input wire [ 1:0] pipe_tx6_char_is_k ,
input wire [15:0] pipe_tx6_data ,
input wire pipe_tx6_elec_idle ,
input wire [ 1:0] pipe_tx6_powerdown ,
// Pipe Per-Lane Signals - Lane 7
output wire [ 1:0] pipe_rx7_char_is_k ,
output wire [15:0] pipe_rx7_data ,
output wire pipe_rx7_valid ,
output wire pipe_rx7_chanisaligned ,
output wire [ 2:0] pipe_rx7_status ,
output wire pipe_rx7_phy_status ,
output wire pipe_rx7_elec_idle ,
input wire pipe_rx7_polarity ,
input wire pipe_tx7_compliance ,
input wire [ 1:0] pipe_tx7_char_is_k ,
input wire [15:0] pipe_tx7_data ,
input wire pipe_tx7_elec_idle ,
input wire [ 1:0] pipe_tx7_powerdown ,
// PCI Express signals
output wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txn ,
output wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txp ,
input wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxn ,
input wire [ (LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxp ,
// Non PIPE signals
input wire sys_clk ,
input wire sys_rst_n ,
input wire PIPE_MMCM_RST_N ,
output wire pipe_clk ,
output wire user_clk ,
output wire user_clk2 ,
output wire phy_rdy_n
);
parameter TCQ = 1; // clock to out delay model
localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "FALSE") ? USER_CLK_FREQ :
(USER_CLK_FREQ == 4) ? 3 :
(USER_CLK_FREQ == 3) ? 2 :
USER_CLK_FREQ;
localparam PCIE_LPM_DFE = (PL_FAST_TRAIN == "TRUE") ? "DFE" : "LPM";
localparam PCIE_LINK_SPEED = (PL_FAST_TRAIN == "TRUE") ? 2 : 3;
// The parameter PCIE_OOBCLK_MODE_ENABLE value should be "0" for simulation and for synthesis it should be 1
//localparam PCIE_OOBCLK_MODE_ENABLE = (PL_FAST_TRAIN == "TRUE") ? 0 : 1;
localparam PCIE_OOBCLK_MODE_ENABLE = 1;
localparam PCIE_TX_EIDLE_ASSERT_DELAY = (PL_FAST_TRAIN == "TRUE") ? 4 : 2;
wire [ 7:0] gt_rx_phy_status_wire ;
wire [ 7:0] gt_rxchanisaligned_wire ;
wire [ 31:0] gt_rx_data_k_wire ;
wire [255:0] gt_rx_data_wire ;
wire [ 7:0] gt_rx_elec_idle_wire ;
wire [ 23:0] gt_rx_status_wire ;
wire [ 7:0] gt_rx_valid_wire ;
wire [ 7:0] gt_rx_polarity ;
wire [ 15:0] gt_power_down ;
wire [ 7:0] gt_tx_char_disp_mode ;
wire [ 31:0] gt_tx_data_k ;
wire [255:0] gt_tx_data ;
wire gt_tx_detect_rx_loopback ;
wire [ 7:0] gt_tx_elec_idle ;
wire [ 7:0] gt_rx_elec_idle_reset ;
wire [LINK_CAP_MAX_LINK_WIDTH-1:0] plllkdet ;
wire [LINK_CAP_MAX_LINK_WIDTH-1:0] phystatus_rst ;
wire clock_locked ;
wire [ 7:0] gt_rx_phy_status_wire_filter ;
wire [ 31:0] gt_rx_data_k_wire_filter ;
wire [255:0] gt_rx_data_wire_filter ;
wire [ 7:0] gt_rx_elec_idle_wire_filter ;
wire [ 23:0] gt_rx_status_wire_filter ;
wire [ 7:0] gt_rx_valid_wire_filter ;
wire pipe_clk_int;
reg phy_rdy_n_int;
reg reg_clock_locked;
wire all_phystatus_rst;
reg [5:0] pl_ltssm_state_q;
always @(posedge pipe_clk_int or negedge clock_locked) begin
if (!clock_locked)
pl_ltssm_state_q <= #TCQ 6'b0;
else
pl_ltssm_state_q <= #TCQ pl_ltssm_state;
end
assign pipe_clk = pipe_clk_int ;
wire plm_in_l0 = (pl_ltssm_state_q == 6'h16);
wire plm_in_rl = (pl_ltssm_state_q == 6'h1c);
wire plm_in_dt = (pl_ltssm_state_q == 6'h2d);
wire plm_in_rs = (pl_ltssm_state_q == 6'h1f);
//-------------RX FILTER Instantiation----------------------------------------------------------//
genvar i;
generate for (i=0; i<LINK_CAP_MAX_LINK_WIDTH; i=i+1)
begin : gt_rx_valid_filter
pcieCore_gt_rx_valid_filter_7x # (
.CLK_COR_MIN_LAT(28)
)
GT_RX_VALID_FILTER_7x_inst (
.USER_RXCHARISK ( gt_rx_data_k_wire [(2*i)+1 + (2*i):(2*i)+ (2*i)] ), //O
.USER_RXDATA ( gt_rx_data_wire [(16*i)+15+(16*i) :(16*i)+0 + (16*i)] ), //O
.USER_RXVALID ( gt_rx_valid_wire [i] ), //O
.USER_RXELECIDLE ( gt_rx_elec_idle_wire [i] ), //O
.USER_RX_STATUS ( gt_rx_status_wire [(3*i)+2:(3*i)] ), //O
.USER_RX_PHY_STATUS ( gt_rx_phy_status_wire [i] ), //O
.GT_RXCHARISK ( gt_rx_data_k_wire_filter [(2*i)+1+ (2*i):2*i+ (2*i)] ), //I
.GT_RXDATA ( gt_rx_data_wire_filter [(16*i)+15+(16*i) :(16*i)+0+(16*i)] ), //I
.GT_RXVALID ( gt_rx_valid_wire_filter [i] ), //I
.GT_RXELECIDLE ( gt_rx_elec_idle_wire_filter [i] ), //I
.GT_RX_STATUS ( gt_rx_status_wire_filter [(3*i)+2:(3*i)] ), //I
.GT_RX_PHY_STATUS ( gt_rx_phy_status_wire_filter [i] ),
.PLM_IN_L0 ( plm_in_l0 ), //I
.PLM_IN_RS ( plm_in_rs ), //I
.USER_CLK ( pipe_clk_int ), //I
.RESET ( phy_rdy_n_int ) //I
);
end
endgenerate
//---------- GT Instantiation ---------------------------------------------------------------
pcieCore_pipe_wrapper #
(
.PCIE_SIM_MODE ( PL_FAST_TRAIN ),
// synthesis translate_off
.PCIE_SIM_SPEEDUP ( "TRUE" ),
// synthesis translate_on
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_ASYNC_EN ( PCIE_ASYNC_EN ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND ),
.PCIE_PLL_SEL ( PCIE_PLL_SEL ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_LANE ( LINK_CAP_MAX_LINK_WIDTH ),
.PCIE_LPM_DFE ( PCIE_LPM_DFE ),
.PCIE_LINK_SPEED ( PCIE_LINK_SPEED ),
.PCIE_TX_EIDLE_ASSERT_DELAY ( PCIE_TX_EIDLE_ASSERT_DELAY ),
.PCIE_OOBCLK_MODE ( PCIE_OOBCLK_MODE_ENABLE ),
.PCIE_REFCLK_FREQ ( REF_CLK_FREQ ),
.PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ),
.PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 )
) pipe_wrapper_i (
//---------- PIPE Clock & Reset Ports ------------------
.PIPE_CLK ( sys_clk ),
.PIPE_RESET_N ( sys_rst_n ),
.PIPE_PCLK ( pipe_clk_int ),
//---------- PIPE TX Data Ports ------------------
.PIPE_TXDATA ( gt_tx_data[((32*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXDATAK ( gt_tx_data_k[((4*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXP ( pci_exp_txp[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXN ( pci_exp_txn[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE RX Data Ports ------------------
.PIPE_RXP ( pci_exp_rxp[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXN ( pci_exp_rxn[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXDATA ( gt_rx_data_wire_filter[((32*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXDATAK ( gt_rx_data_k_wire_filter[((4*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
//---------- PIPE Command Ports ------------------
.PIPE_TXDETECTRX ( gt_tx_detect_rx_loopback ),
.PIPE_TXELECIDLE ( gt_tx_elec_idle[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_TXCOMPLIANCE ( gt_tx_char_disp_mode[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXPOLARITY ( gt_rx_polarity[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_POWERDOWN ( gt_power_down[((2*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RATE ( {1'b0,pipe_tx_rate} ),
//---------- PIPE Electrical Command Ports ------------------
.PIPE_TXMARGIN ( pipe_tx_margin[2:0] ),
.PIPE_TXSWING ( pipe_tx_swing ),
.PIPE_TXDEEMPH ( {(LINK_CAP_MAX_LINK_WIDTH){pipe_tx_deemph}} ),
.PIPE_TXEQ_CONTROL ( {2*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_PRESET ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_PRESET_DEFAULT ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_CONTROL ( {2*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_PRESET ( {3*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_LFFS ( {6*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_TXPRESET ( {4*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_USER_EN ( {1*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_USER_TXCOEFF ( {18*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_RXEQ_USER_MODE ( {1*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_COEFF ( ),
.PIPE_TXEQ_DEEMPH ( {6*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_TXEQ_FS ( ),
.PIPE_TXEQ_LF ( ),
.PIPE_TXEQ_DONE ( ),
.PIPE_RXEQ_NEW_TXCOEFF ( ),
.PIPE_RXEQ_LFFS_SEL ( ),
.PIPE_RXEQ_ADAPT_DONE ( ),
.PIPE_RXEQ_DONE ( ),
//---------- PIPE Status Ports -------------------
.PIPE_RXVALID ( gt_rx_valid_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_PHYSTATUS ( gt_rx_phy_status_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_PHYSTATUS_RST ( phystatus_rst ),
.PIPE_RXELECIDLE ( gt_rx_elec_idle_wire_filter[((LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXSTATUS ( gt_rx_status_wire_filter[((3*LINK_CAP_MAX_LINK_WIDTH)-1):0] ),
.PIPE_RXBUFSTATUS ( ),
//---------- PIPE User Ports ---------------------------
.PIPE_MMCM_RST_N ( PIPE_MMCM_RST_N ), // Async | Async
.PIPE_RXSLIDE ( {1*LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.PIPE_CPLL_LOCK ( plllkdet ),
.PIPE_QPLL_LOCK ( ),
.PIPE_PCLK_LOCK ( clock_locked ),
.PIPE_RXCDRLOCK ( ),
.PIPE_USERCLK1 ( user_clk ),
.PIPE_USERCLK2 ( user_clk2 ),
.PIPE_RXUSRCLK ( ),
.PIPE_RXOUTCLK ( ),
.PIPE_TXSYNC_DONE ( ),
.PIPE_RXSYNC_DONE ( ),
.PIPE_GEN3_RDY ( ),
.PIPE_RXCHANISALIGNED ( gt_rxchanisaligned_wire[LINK_CAP_MAX_LINK_WIDTH-1:0] ),
.PIPE_ACTIVE_LANE ( ),
//---------- External Clock Ports ---------------------------
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_JTAG_EN ( 1'b0 ),
.PIPE_JTAG_RDY ( ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
//---------- PRBS/Loopback Ports ---------------------------
.PIPE_TXPRBSSEL ( 3'b0 ),
.PIPE_RXPRBSSEL ( 3'b0 ),
.PIPE_TXPRBSFORCEERR ( 1'b0 ),
.PIPE_RXPRBSCNTRESET ( 1'b0 ),
.PIPE_LOOPBACK ( 3'b0 ),
.PIPE_RXPRBSERR ( ),
//---------- FSM Ports ---------------------------
.PIPE_RST_FSM ( ),
.PIPE_QRST_FSM ( ),
.PIPE_RATE_FSM ( ),
.PIPE_SYNC_FSM_TX ( ),
.PIPE_SYNC_FSM_RX ( ),
.PIPE_DRP_FSM ( ),
.PIPE_TXEQ_FSM ( ),
.PIPE_RXEQ_FSM ( ),
.PIPE_QDRP_FSM ( ),
.PIPE_RST_IDLE ( ),
.PIPE_QRST_IDLE ( ),
.PIPE_RATE_IDLE ( ),
//---------- DEBUG Ports ---------------------------
.PIPE_DEBUG_0 ( ),
.PIPE_DEBUG_1 ( ),
.PIPE_DEBUG_2 ( ),
.PIPE_DEBUG_3 ( ),
.PIPE_DEBUG_4 ( ),
.PIPE_DEBUG_5 ( ),
.PIPE_DEBUG_6 ( ),
.PIPE_DEBUG_7 ( ),
.PIPE_DEBUG_8 ( ),
.PIPE_DEBUG_9 ( ),
.PIPE_DEBUG ( ),
.PIPE_DMONITOROUT ( )
);
assign pipe_rx0_phy_status = gt_rx_phy_status_wire[0] ;
assign pipe_rx1_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0;
assign pipe_rx2_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0;
assign pipe_rx3_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0;
assign pipe_rx4_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0;
assign pipe_rx5_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0;
assign pipe_rx6_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0;
assign pipe_rx7_phy_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0;
assign pipe_rx0_chanisaligned = gt_rxchanisaligned_wire[0];
assign pipe_rx1_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rxchanisaligned_wire[1] : 1'b0 ;
assign pipe_rx2_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rxchanisaligned_wire[2] : 1'b0 ;
assign pipe_rx3_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rxchanisaligned_wire[3] : 1'b0 ;
assign pipe_rx4_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[4] : 1'b0 ;
assign pipe_rx5_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[5] : 1'b0 ;
assign pipe_rx6_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[6] : 1'b0 ;
assign pipe_rx7_chanisaligned = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rxchanisaligned_wire[7] : 1'b0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]};
assign pipe_rx1_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]} : 2'b0 ;
assign pipe_rx2_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]} : 2'b0 ;
assign pipe_rx3_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]} : 2'b0 ;
assign pipe_rx4_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[17], gt_rx_data_k_wire[16]} : 2'b0 ;
assign pipe_rx5_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[21], gt_rx_data_k_wire[20]} : 2'b0 ;
assign pipe_rx6_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[25], gt_rx_data_k_wire[24]} : 2'b0 ;
assign pipe_rx7_char_is_k = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_k_wire[29], gt_rx_data_k_wire[28]} : 2'b0 ;
assign pipe_rx0_data = {gt_rx_data_wire[ 15: 8], gt_rx_data_wire[ 7: 0]};
assign pipe_rx1_data = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]} : 16'h0 ;
assign pipe_rx2_data = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]} : 16'h0 ;
assign pipe_rx3_data = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]} : 16'h0 ;
assign pipe_rx4_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[143:136], gt_rx_data_wire[135:128]} : 16'h0 ;
assign pipe_rx5_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[175:168], gt_rx_data_wire[167:160]} : 16'h0 ;
assign pipe_rx6_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[207:200], gt_rx_data_wire[199:192]} : 16'h0 ;
assign pipe_rx7_data = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? {gt_rx_data_wire[239:232], gt_rx_data_wire[231:224]} : 16'h0 ;
assign pipe_rx0_status = gt_rx_status_wire[ 2: 0];
assign pipe_rx1_status = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0 ;
assign pipe_rx2_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0 ;
assign pipe_rx3_status = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0 ;
assign pipe_rx4_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0 ;
assign pipe_rx5_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0 ;
assign pipe_rx6_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0 ;
assign pipe_rx7_status = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0];
assign pipe_rx1_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1 ;
assign pipe_rx2_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1 ;
assign pipe_rx3_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1 ;
assign pipe_rx4_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1 ;
assign pipe_rx5_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1 ;
assign pipe_rx6_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1 ;
assign pipe_rx7_elec_idle = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1 ;
assign pipe_rx0_valid = gt_rx_valid_wire[0];
assign pipe_rx1_valid = (LINK_CAP_MAX_LINK_WIDTH >= 2 ) ? gt_rx_valid_wire[1] : 1'b0 ;
assign pipe_rx2_valid = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[2] : 1'b0 ;
assign pipe_rx3_valid = (LINK_CAP_MAX_LINK_WIDTH >= 4 ) ? gt_rx_valid_wire[3] : 1'b0 ;
assign pipe_rx4_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[4] : 1'b0 ;
assign pipe_rx5_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[5] : 1'b0 ;
assign pipe_rx6_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[6] : 1'b0 ;
assign pipe_rx7_valid = (LINK_CAP_MAX_LINK_WIDTH >= 8 ) ? gt_rx_valid_wire[7] : 1'b0 ;
assign gt_rx_polarity[0] = pipe_rx0_polarity;
assign gt_rx_polarity[1] = pipe_rx1_polarity;
assign gt_rx_polarity[2] = pipe_rx2_polarity;
assign gt_rx_polarity[3] = pipe_rx3_polarity;
assign gt_rx_polarity[4] = pipe_rx4_polarity;
assign gt_rx_polarity[5] = pipe_rx5_polarity;
assign gt_rx_polarity[6] = pipe_rx6_polarity;
assign gt_rx_polarity[7] = pipe_rx7_polarity;
assign gt_power_down[ 1: 0] = pipe_tx0_powerdown;
assign gt_power_down[ 3: 2] = pipe_tx1_powerdown;
assign gt_power_down[ 5: 4] = pipe_tx2_powerdown;
assign gt_power_down[ 7: 6] = pipe_tx3_powerdown;
assign gt_power_down[ 9: 8] = pipe_tx4_powerdown;
assign gt_power_down[11:10] = pipe_tx5_powerdown;
assign gt_power_down[13:12] = pipe_tx6_powerdown;
assign gt_power_down[15:14] = pipe_tx7_powerdown;
assign gt_tx_char_disp_mode = {pipe_tx7_compliance,
pipe_tx6_compliance,
pipe_tx5_compliance,
pipe_tx4_compliance,
pipe_tx3_compliance,
pipe_tx2_compliance,
pipe_tx1_compliance,
pipe_tx0_compliance};
assign gt_tx_data_k = {2'd0,
pipe_tx7_char_is_k,
2'd0,
pipe_tx6_char_is_k,
2'd0,
pipe_tx5_char_is_k,
2'd0,
pipe_tx4_char_is_k,
2'd0,
pipe_tx3_char_is_k,
2'd0,
pipe_tx2_char_is_k,
2'd0,
pipe_tx1_char_is_k,
2'd0,
pipe_tx0_char_is_k};
assign gt_tx_data = {16'd0,
pipe_tx7_data,
16'd0,
pipe_tx6_data,
16'd0,
pipe_tx5_data,
16'd0,
pipe_tx4_data,
16'd0,
pipe_tx3_data,
16'd0,
pipe_tx2_data,
16'd0,
pipe_tx1_data,
16'd0,
pipe_tx0_data};
assign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det;
assign gt_tx_elec_idle = {pipe_tx7_elec_idle,
pipe_tx6_elec_idle,
pipe_tx5_elec_idle,
pipe_tx4_elec_idle,
pipe_tx3_elec_idle,
pipe_tx2_elec_idle,
pipe_tx1_elec_idle,
pipe_tx0_elec_idle};
always @(posedge pipe_clk_int or negedge clock_locked) begin
if (!clock_locked)
reg_clock_locked <= #TCQ 1'b0;
else
reg_clock_locked <= #TCQ 1'b1;
end
always @(posedge pipe_clk_int) begin
if (!reg_clock_locked)
phy_rdy_n_int <= #TCQ 1'b0;
else
phy_rdy_n_int <= #TCQ all_phystatus_rst;
end
assign all_phystatus_rst = (&phystatus_rst[LINK_CAP_MAX_LINK_WIDTH-1:0]);
assign phy_rdy_n = phy_rdy_n_int;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
//*****************************************************************************
// Top level memory sequencer structural block. This block
// instantiates the rank, bank, and column machines.
//*****************************************************************************
`timescale 1ps/1ps
module mc #
(
parameter TCQ = 100, // clk->out delay(sim only)
parameter ADDR_CMD_MODE = "1T", // registered or
// 1Tfered mem?
parameter BANK_WIDTH = 3, // bank address width
parameter BM_CNT_WIDTH = 2, // # BM counter width
// i.e., log2(nBANK_MACHS)
parameter BURST_MODE = "8", // Burst length
parameter CL = 5, // Read CAS latency
// (in clk cyc)
parameter CMD_PIPE_PLUS1 = "ON", // add register stage
// between MC and PHY
parameter COL_WIDTH = 12, // column address width
parameter CS_WIDTH = 4, // # of unique CS outputs
parameter CWL = 5, // Write CAS latency
// (in clk cyc)
parameter DATA_BUF_ADDR_WIDTH = 8, // User request tag (e.g.
// user src/dest buf addr)
parameter DATA_BUF_OFFSET_WIDTH = 1, // User buffer offset width
parameter DATA_WIDTH = 64, // Data bus width
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3", // Memory I/F type:
// "DDR3", "DDR2"
parameter ECC = "OFF", // ECC ON/OFF?
parameter ECC_WIDTH = 8, // # of ECC bits
parameter MAINT_PRESCALER_PERIOD= 200000, // maintenance period (ps)
parameter MC_ERR_ADDR_WIDTH = 31, // # of error address bits
parameter nBANK_MACHS = 4, // # of bank machines (BM)
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
// frequency ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs
// per rank
parameter nREFRESH_BANK = 1, // # of REF cmds to pull-in
parameter nSLOTS = 1, // # DIMM slots in system
parameter ORDERING = "NORM", // request ordering mode
parameter PAYLOAD_WIDTH = 64, // Width of data payload
// from PHY
parameter RANK_WIDTH = 2, // # of bits to count ranks
parameter RANKS = 4, // # of ranks of DRAM
parameter ROW_WIDTH = 16, // row address width
parameter RTT_NOM = "40", // Nominal ODT value
parameter RTT_WR = "120", // Write ODT value
parameter SLOT_0_CONFIG = 8'b0000_0101, // ranks allowed in slot 0
parameter SLOT_1_CONFIG = 8'b0000_1010, // ranks allowed in slot 1
parameter STARVE_LIMIT = 2, // max # of times a user
// request is allowed to
// lose arbitration when
// reordering is enabled
parameter tCK = 2500, // memory clk period(ns)
parameter tFAW = 40000, // four activate window(ns)
parameter tRAS = 37500, // ACT->PRE cmd period (ns)
parameter tRCD = 12500, // ACT->R/W delay (ns)
parameter tREFI = 7800000, // average periodic
// refresh interval(ns)
parameter tRFC = 110000, // REF->ACT/REF delay (ns)
parameter tRP = 12500, // PRE cmd period (ns)
parameter tRRD = 10000, // ACT->ACT period (ns)
parameter tRTP = 7500, // Read->PRE cmd delay (ns)
parameter tWTR = 7500, // Internal write->read
// delay (ns)
parameter tZQCS = 64, // ZQCS cmd period (CKs)
parameter tZQI = 128_000_000 // ZQCS interval (ns)
)
(
// System inputs
input clk,
input rst,
// Physical memory slot presence
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// Native Interface
input [2:0] cmd,
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,
input hi_priority,
input size,
input [BANK_WIDTH-1:0] bank,
input [COL_WIDTH-1:0] col,
input [RANK_WIDTH-1:0] rank,
input [ROW_WIDTH-1:0] row,
input use_addr,
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data,
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask,
output accept,
output accept_ns,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data,
output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr,
output rd_data_en,
output rd_data_end,
output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset,
output reg [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr,
output reg wr_data_en,
output reg [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset,
// ECC interface
input correct_en,
input [2*nCK_PER_CLK-1:0] raw_not_ecc,
output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr,
output [2*nCK_PER_CLK-1:0] ecc_single,
output [2*nCK_PER_CLK-1:0] ecc_multiple,
// User maintenance requests
input app_periodic_rd_req,
input app_ref_req,
input app_zq_req,
// MC <==> PHY Interface
output reg [nCK_PER_CLK-1:0] mc_ras_n,
output reg [nCK_PER_CLK-1:0] mc_cas_n,
output reg [nCK_PER_CLK-1:0] mc_we_n,
output reg [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output reg [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire mc_reset_n,
output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata,
output wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0]mc_wrdata_mask,
output reg mc_wrdata_en,
output wire mc_cmd_wren,
output wire mc_ctl_wren,
output reg [2:0] mc_cmd,
output reg [5:0] mc_data_offset,
output reg [3:0] mc_aux_out0,
output reg [3:0] mc_aux_out1,
output reg [1:0] mc_rank_cnt,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data,
input phy_rddata_valid,
input init_calib_complete,
input [6*RANKS-1:0] calib_rd_data_offset
);
assign mc_reset_n = 1'b1; // never reset memory
assign mc_cmd_wren = 1'b1; // always write CMD FIFO(issue DSEL when idle)
assign mc_ctl_wren = 1'b1; // always write CTL FIFO(issue nondata when idle)
// Ensure there is always at least one rank present during operation
`ifdef MC_SVA
ranks_present: assert property
(@(posedge clk) (rst || (|(slot_0_present | slot_1_present))));
`endif
//***************************************************************************
// PHY, datapath, control, bus turnaround delay configuration
//***************************************************************************
localparam nWR_EN2CNFG_RD = 4; // write-enable -> read io_config delay
localparam nWR_EN2CNFG_WR = 4; // write-enable -> write io_config delay
localparam nCNFG2RD_EN = 2; // io_config -> read-enable delay
localparam nCNFG2WR = 2; // io_config -> write delay
localparam nRD_EN2CNFG_WR = // read-enable -> write io_config delay
(DRAM_TYPE == "DDR2")? 5 : (CL <= 6) ? 7 :
((CL == 7) || (CL == 8)) ? 8 : 9;
// Reserved. Do not change.
localparam nPHY_WRLAT = 2;
// never delay write data control
localparam DELAY_WR_DATA_CNTRL = ((ECC == "ON") || (CWL < 0) )? 0 : 1;
// Ensure that write control is delayed for appropriate CWL
/*`ifdef MC_SVA
delay_wr_data_zero_CWL_le_6: assert property
(@(posedge clk) ((CWL > 6) || (DELAY_WR_DATA_CNTRL == 0)));
`endif*/
// Pre-fetch WR_DATA_ADDR early when ECC is on, for all CWL
localparam EARLY_WR_DATA_ADDR = (ECC == "ON") && (CWL < 11)
? "ON"
: "OFF";
//***************************************************************************
// Convert timing parameters from time to clock cycles
//***************************************************************************
localparam nRP = cdiv(tRP, tCK);
localparam nRCD = cdiv(tRCD, tCK);
localparam nRAS = cdiv(tRAS, tCK);
localparam nFAW = cdiv(tFAW, tCK);
localparam nRFC = cdiv(tRFC, tCK);
// Convert tWR. As per specification, write recover for autoprecharge
// cycles doesn't support values of 9 and 11. Round up 9 to 10 and 11 to 12
localparam nWR_CK = cdiv(15000, tCK) ;
localparam nWR = (nWR_CK == 9) ? 10 : (nWR_CK == 11) ? 12 : nWR_CK;
// tRRD, tWTR at tRTP have a 4 cycle floor in DDR3 and 2 cycle floor in DDR2
localparam nRRD_CK = cdiv(tRRD, tCK);
localparam nRRD = (DRAM_TYPE == "DDR3") ? (nRRD_CK < 4) ? 4 : nRRD_CK
: (nRRD_CK < 2) ? 2 : nRRD_CK;
localparam nWTR_CK = cdiv(tWTR, tCK);
localparam nWTR = (DRAM_TYPE == "DDR3") ? (nWTR_CK < 4) ? 4 : nWTR_CK
: (nWTR_CK < 2) ? 2 : nWTR_CK;
localparam nRTP_CK = cdiv(tRTP, tCK);
localparam nRTP = (DRAM_TYPE == "DDR3") ? (nRTP_CK < 4) ? 4 : nRTP_CK
: (nRTP_CK < 2) ? 2 : nRTP_CK;
//***************************************************************************
// Set up maintenance counter dividers
//***************************************************************************
// CK clock divisor to generate maintenance prescaler period (round down)
localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD / (tCK*nCK_PER_CLK);
// Maintenance prescaler divisor for refresh timer. Essentially, this is
// just (tREFI / MAINT_PRESCALER_PERIOD), but we must account for the worst
// case delay from the time we get a tick from the refresh counter to the
// time that we can actually issue the REF command. Thus, subtract tRCD, CL,
// data burst time and tRP for each implemented bank machine to ensure that
// all transactions can complete before tREFI expires
localparam REFRESH_TIMER_DIV = (tREFI-((tRCD+((CL+4)*tCK)+tRP)*nBANK_MACHS))
/ MAINT_PRESCALER_PERIOD;
// Periodic read (RESERVED - not currently required or supported in 7 series)
// tPRDI should only be set to 0
localparam tPRDI = 0; // Do NOT change.
localparam PERIODIC_RD_TIMER_DIV = tPRDI / MAINT_PRESCALER_PERIOD;
// Convert maintenance prescaler from ps to ns
localparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000;
// Maintenance prescaler divisor for ZQ calibration (ZQCS) timer
localparam ZQ_TIMER_DIV = tZQI / MAINT_PRESCALER_PERIOD_NS;
// Bus width required to broadcast a single bit rank signal among all the
// bank machines - 1 bit per rank, per bank
localparam RANK_BM_BV_WIDTH = nBANK_MACHS * RANKS;
//***************************************************************************
// Reserved feature control.
//***************************************************************************
// Open page wait mode is reserved.
// nOP_WAIT is the number of states a bank machine will park itself
// on an otherwise inactive open page before closing the page. If
// nOP_WAIT == 0, open page wait mode is disabled. If nOP_WAIT == -1,
// the bank machine will remain parked until the pool of idle bank machines
// are less than LOW_IDLE_CNT. At which point parked bank machines
// are selected to exit until the number of idle bank machines exceeds the
// LOW_IDLE_CNT.
localparam nOP_WAIT = 0; // Open page mode
localparam LOW_IDLE_CNT = 0; // Low idle bank machine threshold
//***************************************************************************
// Internal wires
//***************************************************************************
wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r;
wire [ROW_WIDTH-1:0] col_a;
wire [BANK_WIDTH-1:0] col_ba;
wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
wire col_periodic_rd;
wire [RANK_WIDTH-1:0] col_ra;
wire col_rmw;
wire col_rd_wr;
wire [ROW_WIDTH-1:0] col_row;
wire col_size;
wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
wire dq_busy_data;
wire ecc_status_valid;
wire [RANKS-1:0] inhbt_act_faw_r;
wire inhbt_rd_config;
wire [RANKS-1:0] inhbt_rd_r;
wire inhbt_wr_config;
wire insert_maint_r1;
wire [RANK_WIDTH-1:0] maint_rank_r;
wire maint_req_r;
wire maint_wip_r;
wire maint_zq_r;
wire periodic_rd_ack_r;
wire periodic_rd_r;
wire [RANK_WIDTH-1:0] periodic_rd_rank_r;
wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r;
wire rd_rmw;
wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r;
wire [nBANK_MACHS-1:0] sending_col;
wire [nBANK_MACHS-1:0] sending_row;
wire sent_col;
wire wr_ecc_buf;
wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r;
wire [RANKS-1:0] wtr_inhbt_config_r;
// MC/PHY optional pipeline stage support
wire [nCK_PER_CLK-1:0] mc_ras_n_ns;
wire [nCK_PER_CLK-1:0] mc_cas_n_ns;
wire [nCK_PER_CLK-1:0] mc_we_n_ns;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address_ns;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank_ns;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_ns;
wire [3:0] mc_aux_out0_ns;
wire [3:0] mc_aux_out1_ns;
wire [1:0] mc_rank_cnt_ns = col_ra;
wire [2:0] mc_cmd_ns;
wire [5:0] mc_data_offset_ns;
wire mc_wrdata_en_ns;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr_ns;
wire wr_data_en_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset_ns;
wire [RANK_WIDTH:0] io_config_ns;
wire io_config_strobe_ns;
integer i;
//***************************************************************************
// Function cdiv
// Description:
// This function performs ceiling division (divide and round-up)
// Inputs:
// num: integer to be divided
// div: divisor
// Outputs:
// cdiv: result of ceiling division (num/div, rounded up)
//***************************************************************************
function integer cdiv (input integer num, input integer div);
begin
// perform division, then add 1 if and only if remainder is non-zero
cdiv = (num/div) + (((num%div)>0) ? 1 : 0);
end
endfunction // cdiv
//***************************************************************************
// Optional pipeline register stage on MC/PHY interface
//***************************************************************************
generate
if (CMD_PIPE_PLUS1 == "ON") begin : cmd_pipe_plus // register interface
always @(posedge clk) begin
mc_address <= #TCQ mc_address_ns;
mc_bank <= #TCQ mc_bank_ns;
mc_cas_n <= #TCQ mc_cas_n_ns;
mc_cs_n <= #TCQ mc_cs_n_ns;
mc_aux_out0 <= #TCQ mc_aux_out0_ns;
mc_aux_out1 <= #TCQ mc_aux_out1_ns;
mc_cmd <= #TCQ mc_cmd_ns;
mc_ras_n <= #TCQ mc_ras_n_ns;
mc_we_n <= #TCQ mc_we_n_ns;
mc_data_offset <= #TCQ mc_data_offset_ns;
mc_wrdata_en <= #TCQ mc_wrdata_en_ns;
mc_rank_cnt <= #TCQ mc_rank_cnt_ns;
wr_data_addr <= #TCQ wr_data_addr_ns;
wr_data_en <= #TCQ wr_data_en_ns;
wr_data_offset <= #TCQ wr_data_offset_ns;
end // always @ (posedge clk)
end // block: cmd_pipe_plus
else begin : cmd_pipe_plus0 // don't register interface
always @( mc_address or mc_aux_out0 or mc_aux_out1 or mc_bank or
mc_cas_n or mc_cmd or mc_cs_n or mc_data_offset or
mc_rank_cnt or mc_ras_n or mc_we_n or mc_wrdata_en or
wr_data_addr or wr_data_en or wr_data_offset)
begin
mc_address = #TCQ mc_address_ns;
mc_bank = #TCQ mc_bank_ns;
mc_cas_n = #TCQ mc_cas_n_ns;
mc_cs_n = #TCQ mc_cs_n_ns;
mc_aux_out0 = #TCQ mc_aux_out0_ns;
mc_aux_out1 = #TCQ mc_aux_out1_ns;
mc_cmd = #TCQ mc_cmd_ns;
mc_ras_n = #TCQ mc_ras_n_ns;
mc_we_n = #TCQ mc_we_n_ns;
mc_data_offset = #TCQ mc_data_offset_ns;
mc_wrdata_en = #TCQ mc_wrdata_en_ns;
mc_rank_cnt = #TCQ mc_rank_cnt_ns;
wr_data_addr = #TCQ wr_data_addr_ns;
wr_data_en = #TCQ wr_data_en_ns;
wr_data_offset = #TCQ wr_data_offset_ns;
mc_wrdata_en = #TCQ mc_wrdata_en_ns;
mc_rank_cnt = #TCQ mc_rank_cnt_ns;
wr_data_addr = #TCQ wr_data_addr_ns;
wr_data_en = #TCQ wr_data_en_ns;
wr_data_offset = #TCQ wr_data_offset_ns;
end // always @ (...
end // block: cmd_pipe_plus0
endgenerate
//***************************************************************************
// Manage rank-level timing and maintanence
//***************************************************************************
rank_mach #
(
// Parameters
.BURST_MODE (BURST_MODE),
.CL (CL),
.CS_WIDTH (CS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV)
)
rank_mach0
(
// Outputs
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd_r (inhbt_rd_r[RANKS-1:0]),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.wtr_inhbt_config_r (wtr_inhbt_config_r[RANKS-1:0]),
// Inputs
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.app_ref_req (app_ref_req),
.app_zq_req (app_zq_req),
.clk (clk),
.init_calib_complete (init_calib_complete),
.insert_maint_r1 (insert_maint_r1),
.maint_wip_r (maint_wip_r),
.periodic_rd_ack_r (periodic_rd_ack_r),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.rst (rst),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0])
);
//***************************************************************************
// Manage requests, reordering and bank timing
//***************************************************************************
bank_mach#
(
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.LOW_IDLE_CNT (LOW_IDLE_CNT),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCNFG2RD_EN (nCNFG2RD_EN),
.nCNFG2WR (nCNFG2WR),
.nCS_PER_RANK (nCS_PER_RANK),
.nOP_WAIT (nOP_WAIT),
.nRAS (nRAS),
.nRCD (nRCD),
.nRFC (nRFC),
.nRP (nRP),
.nRTP (nRTP),
.nSLOTS (nSLOTS),
.nWR (nWR),
.ORDERING (ORDERING),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.STARVE_LIMIT (STARVE_LIMIT),
.tZQCS (tZQCS)
)
bank_mach0
(
// Outputs
.accept (accept),
.accept_ns (accept_ns),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank_ns),
.mc_address (mc_address_ns),
.mc_ras_n (mc_ras_n_ns),
.mc_cas_n (mc_cas_n_ns),
.mc_we_n (mc_we_n_ns),
.mc_cs_n (mc_cs_n_ns),
.mc_aux_out0 (mc_aux_out0_ns),
.mc_aux_out1 (mc_aux_out1_ns),
.mc_cmd (mc_cmd_ns),
.mc_data_offset (mc_data_offset_ns),
.insert_maint_r1 (insert_maint_r1),
.io_config (io_config_ns[RANK_WIDTH:0]),
.io_config_strobe (io_config_strobe_ns),
.maint_wip_r (maint_wip_r),
.periodic_rd_ack_r (periodic_rd_ack_r),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
// Inputs
.bank (bank[BANK_WIDTH-1:0]),
.calib_rddata_offset (calib_rd_data_offset[5:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.init_calib_complete (init_calib_complete),
.phy_rddata_valid (phy_rddata_valid),
.dq_busy_data (dq_busy_data),
.hi_priority (hi_priority),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd_config (inhbt_rd_config),
.inhbt_rd_r (inhbt_rd_r[RANKS-1:0]),
.inhbt_wr_config (inhbt_wr_config),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.rank (rank[RANK_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_rmw (rd_rmw),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.size (size),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.use_addr (use_addr),
.wtr_inhbt_config_r (wtr_inhbt_config_r[RANKS-1:0])
);
//***************************************************************************
// Manage DQ bus
//***************************************************************************
col_mach #
(
// Parameters
.TCQ (TCQ),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DELAY_WR_DATA_CNTRL (DELAY_WR_DATA_CNTRL),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.nPHY_WRLAT (nPHY_WRLAT),
.nRD_EN2CNFG_WR (nRD_EN2CNFG_WR),
.nWR_EN2CNFG_RD (nWR_EN2CNFG_RD),
.nWR_EN2CNFG_WR (nWR_EN2CNFG_WR),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH)
)
col_mach0
(
// Outputs
.mc_wrdata_en (mc_wrdata_en_ns),
.dq_busy_data (dq_busy_data),
.ecc_err_addr (ecc_err_addr[MC_ERR_ADDR_WIDTH-1:0]),
.ecc_status_valid (ecc_status_valid),
.inhbt_rd_config (inhbt_rd_config),
.inhbt_wr_config (inhbt_wr_config),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.rd_rmw (rd_rmw),
.wr_data_addr (wr_data_addr_ns),
.wr_data_en (wr_data_en_ns),
.wr_data_offset (wr_data_offset_ns),
.wr_ecc_buf (wr_ecc_buf),
// Inputs
.clk (clk),
.rst (rst),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.io_config (io_config_ns),
.sent_col (sent_col)
);
//***************************************************************************
// Implement ECC
//***************************************************************************
// Total ECC word length = ECC code width + Data width
localparam CODE_WIDTH = DATA_WIDTH + ECC_WIDTH;
generate
if (ECC == "OFF") begin : ecc_off
assign rd_data = phy_rd_data;
assign mc_wrdata = wr_data;
assign mc_wrdata_mask = wr_data_mask;
assign ecc_single = 4'b0;
assign ecc_multiple = 4'b0;
end
else begin : ecc_on
wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
// Merge and encode
ecc_merge_enc #
(
// Parameters
.TCQ (TCQ),
.CODE_WIDTH (CODE_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC_WIDTH (ECC_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_merge_enc0
(
// Outputs
.mc_wrdata (mc_wrdata),
.mc_wrdata_mask (mc_wrdata_mask),
// Inputs
.clk (clk),
.rst (rst),
.h_rows (h_rows),
.rd_merge_data (rd_merge_data),
.raw_not_ecc (raw_not_ecc),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask)
);
// Decode and fix
ecc_dec_fix #
(
// Parameters
.TCQ (TCQ),
.CODE_WIDTH (CODE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC_WIDTH (ECC_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_dec_fix0
(
// Outputs
.ecc_multiple (ecc_multiple),
.ecc_single (ecc_single),
.rd_data (rd_data),
// Inputs
.clk (clk),
.rst (rst),
.correct_en (correct_en),
.phy_rddata (phy_rd_data),
.ecc_status_valid (ecc_status_valid),
.h_rows (h_rows)
);
// ECC Buffer
ecc_buf #
(
// Parameters
.TCQ (TCQ),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_buf0
(
// Outputs
.rd_merge_data (rd_merge_data),
// Inputs
.clk (clk),
.rst (rst),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_offset (wr_data_offset),
.wr_ecc_buf (wr_ecc_buf)
);
// Generate ECC table
ecc_gen #
(
// Parameters
.CODE_WIDTH (CODE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.ECC_WIDTH (ECC_WIDTH)
)
ecc_gen0
(
// Outputs
.h_rows (h_rows)
);
`ifdef DISPLAY_H_MATRIX
integer i;
always @(negedge rst) begin
$display ("**********************************************");
$display ("H Matrix:");
for (i=0; i<ECC_WIDTH; i=i+1)
$display ("%b", h_rows[i*CODE_WIDTH+:CODE_WIDTH]);
$display ("**********************************************");
end
`endif
end
endgenerate
endmodule // mc
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_TB_V
`define SKY130_FD_SC_HS__O31AI_TB_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o31ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A1 = 1'b1;
#160 A2 = 1'b1;
#180 A3 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A1 = 1'b0;
#280 A2 = 1'b0;
#300 A3 = 1'b0;
#320 B1 = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 B1 = 1'b1;
#440 A3 = 1'b1;
#460 A2 = 1'b1;
#480 A1 = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 B1 = 1'bx;
#560 A3 = 1'bx;
#580 A2 = 1'bx;
#600 A1 = 1'bx;
end
sky130_fd_sc_hs__o31ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_TB_V
|
//
//
//
//
`define NM1 32'd466 //bB_freq
`define NM2 32'd523 //C_freq
`define NM3 32'd587 //D_freq
`define NM4 32'd622 //bE_freq
`define NM5 32'd698 //F_freq
`define NM6 32'd784 //G_freq
`define NM7 32'd880 //A_freq
`define NM0 32'd20000 //slience (over freq.)
module Music (
input [7:0] ibeatNum,
input clk,
output reg [31:0] tone
);
parameter C = 523;
parameter D = 587;
parameter E = 660;
parameter F = 698;
parameter Fs = 745;
parameter G = 784;
parameter A = 880;
parameter As = 932;
parameter B = 988;
parameter ss = 20000;
always @(posedge clk) begin
case(ibeatNum)
0:tone<=ss;
1:tone<=G;
2:tone<=Fs;
3:tone<=G;
4:tone<=A;
5:tone<=G;
6:tone<=G;
7:tone<=ss;
8:tone<=G;
9:tone<=Fs;
10:tone<=G;
11:tone<=A;
12:tone<=G;
13:tone<=G;
14:tone<=ss;
15:tone<=G;
16:tone<=G;
17:tone<=G;
18:tone<=A;
19:tone<=As;
20:tone<=B;
21:tone<=B;
22:tone<=G;
23:tone<=G;
24:tone<=ss;
25:tone<=C<<1;
26:tone<=B;
27:tone<=C<<1;
28:tone<=B;
29:tone<=C<<1;
30:tone<=C<<1;
31:tone<=B;
32:tone<=C<<1;
33:tone<=B;
34:tone<=A;
35:tone<=G;
36:tone<=A;
37:tone<=G;
38:tone<=A;
39:tone<=A;
40:tone<=G;
41:tone<=A;
42:tone<=B;
43:tone<=C<<1;
44:tone<=B;
45:tone<=C<<1;
46:tone<=B;
47:tone<=C<<1;
48:tone<=C<<1;
49:tone<=B;
50:tone<=C<<1;
51:tone<=B;
52:tone<=A;
53:tone<=G;
54:tone<=A;
55:tone<=G;
56:tone<=A;
57:tone<=A;
58:tone<=G;
59:tone<=A;
60:tone<=B;
61:tone<=C<<1;
62:tone<=B;
63:tone<=C<<1;
64:tone<=B;
65:tone<=C<<1;
66:tone<=C<<1;
67:tone<=B;
68:tone<=C<<1;
69:tone<=B;
70:tone<=A;
71:tone<=G;
72:tone<=A;
73:tone<=G;
74:tone<=A;
75:tone<=A;
76:tone<=G;
77:tone<=A;
78:tone<=B;
79:tone<=C<<1;
80:tone<=B;
81:tone<=C<<1;
82:tone<=B;
83:tone<=C<<1;
84:tone<=C<<1;
85:tone<=B;
86:tone<=C<<1;
87:tone<=B;
88:tone<=A;
89:tone<=G;
90:tone<=A;
91:tone<=G;
92:tone<=A;
93:tone<=A;
94:tone<=G;
95:tone<=A;
96:tone<=B;
97:tone<=E;
98:tone<=E;
99:tone<=F;
100:tone<=G;
101:tone<=C;
102:tone<=C<<1;
103:tone<=B;
104:tone<=A;
105:tone<=G;
106:tone<=F;
107:tone<=F;
108:tone<=F;
109:tone<=D;
110:tone<=D;
111:tone<=E;
112:tone<=F;
113:tone<=B>>1;
114:tone<=B;
115:tone<=A;
116:tone<=G;
117:tone<=A;
118:tone<=G;
119:tone<=G;
120:tone<=G;
121:tone<=E;
122:tone<=E;
123:tone<=F;
124:tone<=G;
125:tone<=C;
126:tone<=C<<1;
127:tone<=B;
128:tone<=A;
129:tone<=G;
130:tone<=F;
131:tone<=F;
132:tone<=F;
133:tone<=F;
134:tone<=G;
135:tone<=A;
136:tone<=B;
137:tone<=B;
138:tone<=G;
139:tone<=G;
140:tone<=A;
141:tone<=A;
142:tone<=B;
143:tone<=B;
144:tone<=C<<1;
145:tone<=C<<1;
146:tone<=C<<1;
147:tone<=ss;
148:tone<=C<<1;
149:tone<=B;
150:tone<=As;
151:tone<=A;
152:tone<=A;
153:tone<=C<<1;
154:tone<=C<<1;
155:tone<=D<<1;
156:tone<=D<<1;
157:tone<=C<<1;
158:tone<=C<<1;
159:tone<=G;
160:tone<=G;
161:tone<=G;
162:tone<=ss;
163:tone<=C<<1;
164:tone<=B;
165:tone<=As;
166:tone<=A;
167:tone<=A;
168:tone<=C<<1;
169:tone<=C<<1;
170:tone<=D<<1;
171:tone<=D<<1;
172:tone<=C<<1;
173:tone<=C<<1;
174:tone<=G;
175:tone<=G;
176:tone<=G;
177:tone<=ss;
178:tone<=C<<1;
179:tone<=B;
180:tone<=As;
181:tone<=A;
182:tone<=A;
183:tone<=C<<1;
184:tone<=C<<1;
185:tone<=D<<1;
186:tone<=D<<1;
187:tone<=C<<1;
188:tone<=D<<1;
189:tone<=E<<1;
190:tone<=D<<1;
191:tone<=E<<1;
192:tone<=C<<1;
193:tone<=C<<1;
194:tone<=ss;
195:tone<=C<<1;
196:tone<=D<<1;
197:tone<=E<<1;
198:tone<=F<<1;
199:tone<=F<<1;
200:tone<=G;
201:tone<=G;
202:tone<=B;
203:tone<=B;
204:tone<=D<<1;
205:tone<=D<<1;
206:tone<=C<<1;
207:tone<=C<<1;
//default:tone<=ss;
endcase
end
endmodule |
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=6 LPM_WIDTHN=64 denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:07:21:01:49:21:SJ cbx_stratixii 2016:07:21:01:48:16:SJ cbx_util_mgl 2016:07:21:01:48:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mgahk
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [5:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [5:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [5:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 6,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mgahk
//VALID FILE
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:29:02 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.v
// Design : system_vga_sync_reset_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_sync_reset_0_0,vga_sync_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_sync_reset,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_sync_reset_0_0
(clk,
rst,
active,
hsync,
vsync,
xaddr,
yaddr);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 rst RST" *) input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
wire active;
wire clk;
wire hsync;
wire rst;
wire vsync;
wire [9:0]xaddr;
wire [9:0]yaddr;
system_vga_sync_reset_0_0_vga_sync_reset U0
(.active(active),
.clk(clk),
.hsync(hsync),
.rst(rst),
.vsync(vsync),
.xaddr(xaddr),
.yaddr(yaddr));
endmodule
(* ORIG_REF_NAME = "vga_sync_reset" *)
module system_vga_sync_reset_0_0_vga_sync_reset
(xaddr,
yaddr,
active,
hsync,
vsync,
clk,
rst);
output [9:0]xaddr;
output [9:0]yaddr;
output active;
output hsync;
output vsync;
input clk;
input rst;
wire active;
wire active_i_1_n_0;
wire active_i_2_n_0;
wire clk;
wire \h_count_reg[0]_i_1_n_0 ;
wire \h_count_reg[9]_i_1_n_0 ;
wire \h_count_reg[9]_i_3_n_0 ;
wire \h_count_reg[9]_i_4_n_0 ;
wire hsync;
wire hsync_i_1_n_0;
wire hsync_i_2_n_0;
wire hsync_i_3_n_0;
wire [9:1]plusOp;
wire [9:0]plusOp__0;
wire rst;
wire \v_count_reg[9]_i_1_n_0 ;
wire \v_count_reg[9]_i_2_n_0 ;
wire \v_count_reg[9]_i_4_n_0 ;
wire \v_count_reg[9]_i_5_n_0 ;
wire \v_count_reg[9]_i_6_n_0 ;
wire vsync;
wire vsync_i_1_n_0;
wire vsync_i_2_n_0;
wire [9:0]xaddr;
wire [9:0]yaddr;
LUT6 #(
.INIT(64'h0000222A00000000))
active_i_1
(.I0(active_i_2_n_0),
.I1(xaddr[9]),
.I2(xaddr[7]),
.I3(xaddr[8]),
.I4(yaddr[9]),
.I5(rst),
.O(active_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h7FFF))
active_i_2
(.I0(yaddr[7]),
.I1(yaddr[5]),
.I2(yaddr[6]),
.I3(yaddr[8]),
.O(active_i_2_n_0));
FDRE #(
.INIT(1'b0))
active_reg
(.C(clk),
.CE(1'b1),
.D(active_i_1_n_0),
.Q(active),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\h_count_reg[0]_i_1
(.I0(xaddr[0]),
.O(\h_count_reg[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\h_count_reg[1]_i_1
(.I0(xaddr[0]),
.I1(xaddr[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h78))
\h_count_reg[2]_i_1
(.I0(xaddr[1]),
.I1(xaddr[0]),
.I2(xaddr[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\h_count_reg[3]_i_1
(.I0(xaddr[2]),
.I1(xaddr[0]),
.I2(xaddr[1]),
.I3(xaddr[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\h_count_reg[4]_i_1
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[0]),
.I3(xaddr[2]),
.I4(xaddr[4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\h_count_reg[5]_i_1
(.I0(xaddr[4]),
.I1(xaddr[2]),
.I2(xaddr[0]),
.I3(xaddr[1]),
.I4(xaddr[3]),
.I5(xaddr[5]),
.O(plusOp[5]));
LUT3 #(
.INIT(8'hD2))
\h_count_reg[6]_i_1
(.I0(xaddr[5]),
.I1(\h_count_reg[9]_i_3_n_0 ),
.I2(xaddr[6]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hBF40))
\h_count_reg[7]_i_1
(.I0(\h_count_reg[9]_i_3_n_0 ),
.I1(xaddr[5]),
.I2(xaddr[6]),
.I3(xaddr[7]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFF7F0080))
\h_count_reg[8]_i_1
(.I0(xaddr[7]),
.I1(xaddr[6]),
.I2(xaddr[5]),
.I3(\h_count_reg[9]_i_3_n_0 ),
.I4(xaddr[8]),
.O(plusOp[8]));
LUT6 #(
.INIT(64'h10000000FFFFFFFF))
\h_count_reg[9]_i_1
(.I0(\h_count_reg[9]_i_3_n_0 ),
.I1(xaddr[7]),
.I2(xaddr[8]),
.I3(xaddr[9]),
.I4(\h_count_reg[9]_i_4_n_0 ),
.I5(rst),
.O(\h_count_reg[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hDFFFFFFF20000000))
\h_count_reg[9]_i_2
(.I0(xaddr[8]),
.I1(\h_count_reg[9]_i_3_n_0 ),
.I2(xaddr[5]),
.I3(xaddr[6]),
.I4(xaddr[7]),
.I5(xaddr[9]),
.O(plusOp[9]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
\h_count_reg[9]_i_3
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[0]),
.I3(xaddr[2]),
.I4(xaddr[4]),
.O(\h_count_reg[9]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h1))
\h_count_reg[9]_i_4
(.I0(xaddr[5]),
.I1(xaddr[6]),
.O(\h_count_reg[9]_i_4_n_0 ));
FDRE \h_count_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(\h_count_reg[0]_i_1_n_0 ),
.Q(xaddr[0]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(plusOp[1]),
.Q(xaddr[1]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(plusOp[2]),
.Q(xaddr[2]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[3]
(.C(clk),
.CE(1'b1),
.D(plusOp[3]),
.Q(xaddr[3]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[4]
(.C(clk),
.CE(1'b1),
.D(plusOp[4]),
.Q(xaddr[4]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[5]
(.C(clk),
.CE(1'b1),
.D(plusOp[5]),
.Q(xaddr[5]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[6]
(.C(clk),
.CE(1'b1),
.D(plusOp[6]),
.Q(xaddr[6]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[7]
(.C(clk),
.CE(1'b1),
.D(plusOp[7]),
.Q(xaddr[7]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[8]
(.C(clk),
.CE(1'b1),
.D(plusOp[8]),
.Q(xaddr[8]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[9]
(.C(clk),
.CE(1'b1),
.D(plusOp[9]),
.Q(xaddr[9]),
.R(\h_count_reg[9]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hABEAFFFF))
hsync_i_1
(.I0(hsync_i_2_n_0),
.I1(xaddr[5]),
.I2(xaddr[6]),
.I3(hsync_i_3_n_0),
.I4(rst),
.O(hsync_i_1_n_0));
LUT3 #(
.INIT(8'hDF))
hsync_i_2
(.I0(xaddr[9]),
.I1(xaddr[8]),
.I2(xaddr[7]),
.O(hsync_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0001FFFF))
hsync_i_3
(.I0(xaddr[2]),
.I1(xaddr[3]),
.I2(xaddr[0]),
.I3(xaddr[1]),
.I4(xaddr[4]),
.O(hsync_i_3_n_0));
FDRE #(
.INIT(1'b0))
hsync_reg
(.C(clk),
.CE(1'b1),
.D(hsync_i_1_n_0),
.Q(hsync),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT1 #(
.INIT(2'h1))
\v_count_reg[0]_i_1
(.I0(yaddr[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\v_count_reg[1]_i_1
(.I0(yaddr[0]),
.I1(yaddr[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\v_count_reg[2]_i_1
(.I0(yaddr[1]),
.I1(yaddr[0]),
.I2(yaddr[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h7F80))
\v_count_reg[3]_i_1
(.I0(yaddr[2]),
.I1(yaddr[0]),
.I2(yaddr[1]),
.I3(yaddr[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h7FFF8000))
\v_count_reg[4]_i_1
(.I0(yaddr[3]),
.I1(yaddr[1]),
.I2(yaddr[0]),
.I3(yaddr[2]),
.I4(yaddr[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\v_count_reg[5]_i_1
(.I0(yaddr[4]),
.I1(yaddr[2]),
.I2(yaddr[0]),
.I3(yaddr[1]),
.I4(yaddr[3]),
.I5(yaddr[5]),
.O(plusOp__0[5]));
LUT3 #(
.INIT(8'hD2))
\v_count_reg[6]_i_1
(.I0(yaddr[5]),
.I1(\v_count_reg[9]_i_6_n_0 ),
.I2(yaddr[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hF708))
\v_count_reg[7]_i_1
(.I0(yaddr[5]),
.I1(yaddr[6]),
.I2(\v_count_reg[9]_i_6_n_0 ),
.I3(yaddr[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hBFFF4000))
\v_count_reg[8]_i_1
(.I0(\v_count_reg[9]_i_6_n_0 ),
.I1(yaddr[6]),
.I2(yaddr[5]),
.I3(yaddr[7]),
.I4(yaddr[8]),
.O(plusOp__0[8]));
LUT6 #(
.INIT(64'h00400000FFFFFFFF))
\v_count_reg[9]_i_1
(.I0(\h_count_reg[9]_i_3_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(\h_count_reg[9]_i_4_n_0 ),
.I3(yaddr[0]),
.I4(\v_count_reg[9]_i_5_n_0 ),
.I5(rst),
.O(\v_count_reg[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000001000))
\v_count_reg[9]_i_2
(.I0(xaddr[5]),
.I1(xaddr[6]),
.I2(xaddr[9]),
.I3(xaddr[8]),
.I4(xaddr[7]),
.I5(\h_count_reg[9]_i_3_n_0 ),
.O(\v_count_reg[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBFFFFFFF40000000))
\v_count_reg[9]_i_3
(.I0(\v_count_reg[9]_i_6_n_0 ),
.I1(yaddr[7]),
.I2(yaddr[5]),
.I3(yaddr[6]),
.I4(yaddr[8]),
.I5(yaddr[9]),
.O(plusOp__0[9]));
LUT6 #(
.INIT(64'h0002000000000000))
\v_count_reg[9]_i_4
(.I0(yaddr[9]),
.I1(xaddr[7]),
.I2(yaddr[7]),
.I3(yaddr[8]),
.I4(xaddr[9]),
.I5(xaddr[8]),
.O(\v_count_reg[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000020))
\v_count_reg[9]_i_5
(.I0(yaddr[3]),
.I1(yaddr[4]),
.I2(yaddr[2]),
.I3(yaddr[1]),
.I4(yaddr[6]),
.I5(yaddr[5]),
.O(\v_count_reg[9]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
\v_count_reg[9]_i_6
(.I0(yaddr[3]),
.I1(yaddr[1]),
.I2(yaddr[0]),
.I3(yaddr[2]),
.I4(yaddr[4]),
.O(\v_count_reg[9]_i_6_n_0 ));
FDRE \v_count_reg_reg[0]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[0]),
.Q(yaddr[0]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[1]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[1]),
.Q(yaddr[1]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[2]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[2]),
.Q(yaddr[2]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[3]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[3]),
.Q(yaddr[3]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[4]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[4]),
.Q(yaddr[4]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[5]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[5]),
.Q(yaddr[5]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[6]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[6]),
.Q(yaddr[6]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[7]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[7]),
.Q(yaddr[7]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[8]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[8]),
.Q(yaddr[8]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[9]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[9]),
.Q(yaddr[9]),
.R(\v_count_reg[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFBFFFFFFFF))
vsync_i_1
(.I0(vsync_i_2_n_0),
.I1(yaddr[1]),
.I2(yaddr[2]),
.I3(yaddr[9]),
.I4(yaddr[4]),
.I5(rst),
.O(vsync_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
vsync_i_2
(.I0(yaddr[8]),
.I1(yaddr[6]),
.I2(yaddr[5]),
.I3(yaddr[7]),
.I4(yaddr[3]),
.O(vsync_i_2_n_0));
FDRE #(
.INIT(1'b0))
vsync_reg
(.C(clk),
.CE(1'b1),
.D(vsync_i_1_n_0),
.Q(vsync),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module usb_gpif_ctrl(
input I_sys_clk ,
input I_usb_clk ,
input I_sys_rst ,
input I_usb_rst ,
//===================System GPIF data in/out====================
input I_usb_wfifo_aclr ,
input I_usb_wrreq ,
input [15: 0] I_usb_din ,
output O_usb_wrfull ,
output [12: 0] O_usb_wruesdw ,
input I_usb_rdreq ,
output [31: 0] O_usb_dout ,
output O_usb_rdempty ,
//==================USB3.0 IO=======================================
output O_usb_pclk ,
output O_usb_clk ,
input I_usb_flga ,
input I_usb_flgb ,
output O_usb_cs ,
output O_usb_wr ,
output O_usb_rd ,
output O_usb_oe ,
output O_usb_a0 ,
output O_usb_a1 ,
output O_usb_pkt ,
output O_usb_reset ,
inout [31:0] IO_usb_dq ,
input I_usb_dir
);
//======================================================================
wire [31: 0] S_usb_din ;
wire [31: 0] S_usb_dout ;
reg R_usb_flga ;
reg R_usb_flgb ;
reg R_usb_cs ;
reg R_usb_wr ;
reg R_usb_rd ;
reg R_usb_oe ;
reg [1 : 0] R_usb_a ;
reg R_usb_pkt ;
reg R_usb_cs_d0 ;
reg R_usb_wr_d0 ;
reg R_usb_rd_d0 ;
reg R_usb_oe_d0 ;
reg [1 : 0] R_usb_a_d0 ;
reg R_usb_pkt_d0 ;
reg R_usb_cs_d1 ;
reg R_usb_wr_d1 ;
reg R_usb_rd_d1 ;
reg R_usb_oe_d1 ;
reg [1 : 0] R_usb_a_d1 ;
reg R_usb_pkt_d1 ;
reg [3 : 0] R_usb_wr_state ;
reg [3 : 0] R_usb_rd_state ;
reg [7 : 0] R_usb_wr_cnt ;
reg [7 : 0] R_usb_rd_cnt ;
reg R_usb_rd_d2 ;
reg R_usb_rd_d3 ;
wire S_wr_fifo_rdreq ;
wire [31: 0] S_wr_fifo_dout ;
reg [31: 0] R_wr_fifo_dout ;
wire S_wr_fifo_rdempty ;
wire S_wr_fifo_rdfull ;
wire [11: 0] S_wr_fifo_rduesdw ;
reg R_rd_fifo_wrreq ;
wire S_rd_fifo_wrreq ;
reg [31: 0] R_rd_fifo_din ;
reg [31: 0] R_usb_dq ;
wire [31: 0] S_usb_dq ;
//======================================================================
usb_wr_fifo_32x512 usb_wr_fifo_inst(
.aclr (I_usb_wfifo_aclr ),
.data (I_usb_din ),
.rdclk (I_usb_clk ),
.rdreq (S_wr_fifo_rdreq&&(!S_wr_fifo_rdempty)),
.wrclk (I_sys_clk ),
.wrreq (I_usb_wrreq ),
.q (S_wr_fifo_dout ),
.rdempty (S_wr_fifo_rdempty ),
.rdfull (S_wr_fifo_rdfull ),
.rdusedw (S_wr_fifo_rduesdw ),
.wrfull (O_usb_wrfull ),
.wrusedw (O_usb_wruesdw )
);
usb_rd_fifo_32x512 usb_rd_fifo_inst(
.aclr (I_usb_rst ),
.data (R_rd_fifo_din ),
.rdclk (I_sys_clk ),
.rdreq (I_usb_rdreq ),
.wrclk (I_usb_clk ),
.wrreq (S_rd_fifo_wrreq ),
.q (O_usb_dout ),
.rdempty (O_usb_rdempty ),
.wrfull ()
);
//======================================================================
always@(posedge I_usb_clk or posedge I_usb_rst)
begin
if (I_usb_rst)
begin
R_usb_flga <= 1'b0 ;
R_usb_flgb <= 1'b0 ;
end
else
begin
R_usb_flga <= I_usb_flga;
R_usb_flgb <= I_usb_flgb;
end
end
always@(posedge I_usb_clk or posedge I_usb_rst )
begin
if(I_usb_rst)
begin
R_usb_cs <= 1'b1;
R_usb_wr <= 1'b1;
R_usb_rd <= 1'b1;
R_usb_oe <= 1'b1;
R_usb_a <= 2'b0;
R_usb_pkt <= 1'b1;
R_usb_wr_state <= 4'd0;
R_usb_rd_state <= 4'd0;
R_usb_wr_cnt <= 8'd0;
end
else if(I_usb_dir==1'b0)//DATA_DIR->0->EXT TO USB //wr
begin
R_usb_rd_state <= 4'd0;
R_usb_oe <= 1'b1;
R_usb_rd <= 1'b1;
//R_usb_rd_cnt <= 4'd0;
R_usb_a <= 2'b00;
//
case(R_usb_wr_state)
4'd0:
begin
R_usb_wr_state <= 4'd1;
end
4'd1:
begin
R_usb_wr_state <= 4'd2;
end
4'd2:
begin
R_usb_wr_state <= 4'd3;
end
4'd3:
begin
R_usb_wr_state <= 4'd4;
end
4'd4:
begin
if(((S_wr_fifo_rduesdw>=12'd256)||(S_wr_fifo_rdfull==1'b1))&&(R_usb_flgb==1'b1)) //>512
begin
R_usb_wr_state <= 4'd5;
R_usb_cs <= 1'd0;
end
else
begin
R_usb_wr_state <= 4'd4;
end
end
4'd5:
begin
if(R_usb_flgb==1'b1)
begin
R_usb_wr <= 1'b0;
//
if(R_usb_wr_cnt<8'd255)
begin
R_usb_wr_cnt <= R_usb_wr_cnt + 8'd1;
R_usb_wr_state <= 4'd5;
end
else
begin
R_usb_pkt <= 1'b0;
R_usb_wr_cnt <= 8'd0;
R_usb_wr_state <= 4'd6;
end
end
else
begin
R_usb_wr <= 1'b1;
R_usb_wr_state <= 4'd5;
end
end
4'd6:
begin
R_usb_wr <= 1'b1;
R_usb_pkt <= 1'b1;
R_usb_wr_state <= 4'd7;
end
4'd7:
begin
R_usb_cs <= 1'd1;
R_usb_wr_state <= 4'd0;
end
default: R_usb_wr_state <= 4'd0;
endcase
end
else //DATA_DIR->1->USB TO EXT //rd
begin
R_usb_wr_state <= 4'd0;
R_usb_wr <= 1'b1;
R_usb_wr_cnt <= 4'd0;
R_usb_a <= 2'b11;
//
case(R_usb_rd_state)
4'd0:
begin
if(R_usb_flga==1'b1)
begin
R_usb_rd_state <= 4'd1;
end
else
begin
R_usb_rd_state <= 4'd0;
end
end
4'd1:
begin
R_usb_cs <= 1'd0;
R_usb_rd_state <= 4'd2;
end
4'd2:
begin
R_usb_oe <= 1'd0;
R_usb_rd_state <= 4'd3;
end
4'd3:
begin
R_usb_rd <= 1'b0;
R_usb_rd_state <= 4'd4;
end
4'd4:
begin
if(R_usb_flga==1'b0)
begin
R_usb_rd <= 1'b1;
R_usb_rd_state <= 4'd5;
end
else
begin
R_usb_rd_state <= 4'd4;
end
end
4'd5:
begin
R_usb_oe <= 1'd1;
R_usb_rd_state <= 4'd6;
end
4'd6:
begin
R_usb_cs <= 1'd1;
R_usb_rd_state <= 4'd0;
end
default: R_usb_rd_state <= 4'd0;
endcase
end
end
always@(posedge I_usb_clk)
begin
R_usb_cs_d0 <= R_usb_cs ;
R_usb_wr_d0 <= R_usb_wr ;
R_usb_rd_d0 <= R_usb_rd ;
R_usb_oe_d0 <= R_usb_oe ;
R_usb_a_d0 <= R_usb_a ;
R_usb_pkt_d0 <= R_usb_pkt ;
R_usb_cs_d1 <= R_usb_cs_d0 ;
R_usb_wr_d1 <= R_usb_wr_d0 ;
R_usb_rd_d1 <= R_usb_rd_d0 ;
R_usb_oe_d1 <= R_usb_oe_d0 ;
R_usb_a_d1 <= R_usb_a_d0 ;
R_usb_pkt_d1 <= R_usb_pkt_d0;
end
always@(posedge I_usb_clk)
begin
R_usb_rd_d2 <= R_usb_rd_d1;
R_usb_rd_d3 <= R_usb_rd_d2;
end
always@(posedge I_usb_clk)
begin
if(R_usb_rd_d3==1'b0)
begin
R_rd_fifo_din <= S_usb_din;
R_rd_fifo_wrreq <= 1'b1;
end
else
begin
R_rd_fifo_din <= R_rd_fifo_din;
R_rd_fifo_wrreq <= 1'b0;
end
end
assign S_rd_fifo_wrreq = R_rd_fifo_wrreq & R_usb_flga;
assign S_wr_fifo_rdreq = ~R_usb_wr;
assign S_usb_dq = R_usb_oe_d0 ? S_usb_dout : 32'hz;
always@(posedge I_usb_clk)
begin
R_usb_dq <= S_usb_dq;
end
assign S_usb_dout = S_wr_fifo_dout;
assign IO_usb_dq = R_usb_dq;
assign S_usb_din = IO_usb_dq;
assign O_usb_reset = ~I_usb_rst;
assign O_usb_cs = R_usb_cs_d1 ;
assign O_usb_wr = R_usb_wr_d1 ;
assign O_usb_rd = R_usb_rd_d1 ;
assign O_usb_oe = R_usb_oe_d1 ;
assign O_usb_a0 = R_usb_a_d1[0] ;
assign O_usb_a1 = R_usb_a_d1[1] ;
assign O_usb_pkt = 1'b1 ;
endmodule |
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