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/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:50:08 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n463,
n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, n474,
n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485,
n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496,
n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518,
n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551,
n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562,
n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573,
n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584,
n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595,
n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, n606,
n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617,
n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628,
n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650,
n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661,
n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672,
n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683,
n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694,
n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705,
n706, n707, n708, n709, n710, n711, n712, n713, n714, n715, n716,
n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727,
n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738,
n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749,
n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760,
n761, n762, n763, n764, n765, n766, n767, n769, n770, n771, n772,
n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794,
n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816,
n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827,
n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838,
n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849,
n850, n851, n852, n853, n854, n855, n856, n857, n858, n859, n860,
n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871,
DP_OP_15J60_123_4652_n8, DP_OP_15J60_123_4652_n7,
DP_OP_15J60_123_4652_n6, DP_OP_15J60_123_4652_n5,
DP_OP_15J60_123_4652_n4, intadd_68_B_14_, intadd_68_B_13_,
intadd_68_B_12_, intadd_68_B_11_, intadd_68_B_10_, intadd_68_B_9_,
intadd_68_B_8_, intadd_68_B_7_, intadd_68_B_6_, intadd_68_B_5_,
intadd_68_B_4_, intadd_68_B_3_, intadd_68_B_2_, intadd_68_B_1_,
intadd_68_B_0_, intadd_68_CI, intadd_68_SUM_14_, intadd_68_SUM_13_,
intadd_68_SUM_12_, intadd_68_SUM_11_, intadd_68_SUM_10_,
intadd_68_SUM_9_, intadd_68_SUM_8_, intadd_68_SUM_7_,
intadd_68_SUM_6_, intadd_68_SUM_5_, intadd_68_SUM_4_,
intadd_68_SUM_3_, intadd_68_SUM_2_, intadd_68_SUM_1_,
intadd_68_SUM_0_, intadd_68_n15, intadd_68_n14, intadd_68_n13,
intadd_68_n12, intadd_68_n11, intadd_68_n10, intadd_68_n9,
intadd_68_n8, intadd_68_n7, intadd_68_n6, intadd_68_n5, intadd_68_n4,
intadd_68_n3, intadd_68_n2, intadd_68_n1, intadd_69_A_4_,
intadd_69_A_3_, intadd_69_B_4_, intadd_69_B_3_, intadd_69_B_2_,
intadd_69_B_1_, intadd_69_B_0_, intadd_69_CI, intadd_69_SUM_4_,
intadd_69_SUM_3_, intadd_69_SUM_2_, intadd_69_SUM_1_,
intadd_69_SUM_0_, intadd_69_n5, intadd_69_n4, intadd_69_n3,
intadd_69_n2, intadd_69_n1, n872, n873, n874, n875, n876, n878, n879,
n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890,
n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901,
n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912,
n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923,
n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934,
n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945,
n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956,
n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967,
n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978,
n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989,
n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000,
n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010,
n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020,
n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030,
n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1231,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292,
n1293, n1294, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303,
n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313,
n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323,
n1324, n1325, n1326, n1327, n1328, n1329, n1331, n1332, n1333, n1334,
n1336, n1337, n1338, n1339, n1340, n1341, n1345, n1346, n1347, n1348,
n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1357, n1358, n1359,
n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369,
n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379,
n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389,
n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399,
n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409,
n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419,
n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480,
n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602,
n1604, n1605, n1606;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:1] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1573), .QN(
n883) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n1574),
.QN(n880) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n1581), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1574),
.Q(ready) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1573),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n1577),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n1580),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n876), .Q(
Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n1585), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1600), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1582), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n1586), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n757), .CK(clk), .RN(n1583), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n756), .CK(clk), .RN(n1587), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n755), .CK(clk), .RN(n1590), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n1590), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n1579), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n1578), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n1585), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n1577), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n1580), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n876), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1579), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1576), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n876), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n1576), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n1573), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n1578), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n741), .CK(clk), .RN(n1581), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1574), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1575), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n1576), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n1573), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n1578), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n1581), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n1574), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n1575), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n1590), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1599), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n1587), .QN(n885)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n1583), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n1590), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n1600), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1599), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n1590), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n1590), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n1587), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n1583), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n1586), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n1582), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n1599), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n1600), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n1599), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1601), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n1589), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n1595), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1585), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1584), .Q(
DMP_SFG[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n1589), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n700), .CK(clk), .RN(n1601), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1601), .Q(
DMP_SFG[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n1589), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n697), .CK(clk), .RN(n1589), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n1588), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n1588), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n1595), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n1595), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n1601), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n1584), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n1595), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n1584), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n1583), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n1587), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n1582), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n1600), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n1586), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n1587), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1599), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1583), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1586), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1582), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n1600), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n1599), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n1590), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n1587), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n1583), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n1595), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n1588), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n1585), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n1601), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n1584), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1601), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1601), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1589), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1585), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n1595), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n1601), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1601), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n1589), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n1595), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n1584), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n1585), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n1588), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n1595), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n1585), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n1589), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n1592), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n932), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n1596), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n1576), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n931), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n931), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n1592), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n932), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n1596), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n1585), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n1586), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n933), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n1582), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n1599), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n1600), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n1599), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n1587), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n1583), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1586), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1582), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1600), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n1574), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n1583), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n1600), .QN(
n889) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n1586), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1587), .QN(
n886) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1578), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n1588), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n1584), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n1584), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1582), .QN(
n890) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n1598), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1597), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1594),
.QN(n887) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1591), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1598), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n1597), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n1592), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n932), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n576), .CK(clk), .RN(n1596), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n574), .CK(clk), .RN(n1595), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n931), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n1592),
.QN(n888) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n932), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n932), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n933), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n559), .CK(clk), .RN(n1596), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n1582), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n1601), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n1592), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n1594), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n1591), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .RN(n1598), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n1597), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1594), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n550), .CK(clk), .RN(n1591), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n1598), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n1597), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n1594), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n1591), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1598), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1600), .Q(
final_result_ieee[31]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n1585), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n511), .CK(clk), .RN(n1587), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n510), .CK(clk), .RN(n1596), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n509), .CK(clk), .RN(n1574), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n508), .CK(clk), .RN(n933), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n507), .CK(clk), .RN(n931), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n506), .CK(clk), .RN(n1592), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n505), .CK(clk), .RN(n932), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n504), .CK(clk), .RN(n1596), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n503), .CK(clk), .RN(n1578), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n1581), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n501), .CK(clk), .RN(n1597), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n500), .CK(clk), .RN(n1594), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n1591), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n498), .CK(clk), .RN(n1598), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n497), .CK(clk), .RN(n1597), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n496), .CK(clk), .RN(n1594), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n495), .CK(clk), .RN(n1591), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n1581), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n493), .CK(clk), .RN(n1598), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n492), .CK(clk), .RN(n1597), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n491), .CK(clk), .RN(n1594), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n490), .CK(clk), .RN(n1591), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n489), .CK(clk), .RN(n1573), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n1587), .Q(
DmP_mant_SFG_SWR[0]), .QN(n913) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n1598), .Q(
DmP_mant_SFG_SWR[1]), .QN(n917) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n1597), .Q(
DmP_mant_SFG_SWR[2]), .QN(n918) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n1594), .Q(
DmP_mant_SFG_SWR[3]), .QN(n919) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n1591), .Q(
DmP_mant_SFG_SWR[4]), .QN(n920) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n483), .CK(clk), .RN(n1586), .Q(
DmP_mant_SFG_SWR[5]), .QN(n921) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1598), .Q(
DmP_mant_SFG_SWR[6]), .QN(n922) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n479), .CK(clk), .RN(n1591), .Q(
DmP_mant_SFG_SWR[9]), .QN(n926) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n1599), .Q(
DmP_mant_SFG_SWR[16]), .QN(n927) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n1590), .Q(
DmP_mant_SFG_SWR[17]), .QN(n928) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n1587), .Q(
DmP_mant_SFG_SWR[18]), .QN(n924) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n1583), .Q(
DmP_mant_SFG_SWR[19]), .QN(n909) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n1586), .Q(
DmP_mant_SFG_SWR[20]), .QN(n910) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n1582), .Q(
DmP_mant_SFG_SWR[21]), .QN(n911) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n1587), .Q(
DmP_mant_SFG_SWR[23]), .QN(n914) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n1583), .Q(
DmP_mant_SFG_SWR[24]), .QN(n915) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n1586), .Q(
DmP_mant_SFG_SWR[25]), .QN(n916) );
CMPR32X2TS intadd_68_U16 ( .A(n1503), .B(intadd_68_B_0_), .C(intadd_68_CI),
.CO(intadd_68_n15), .S(intadd_68_SUM_0_) );
CMPR32X2TS intadd_68_U15 ( .A(n1510), .B(intadd_68_B_1_), .C(intadd_68_n15),
.CO(intadd_68_n14), .S(intadd_68_SUM_1_) );
CMPR32X2TS intadd_68_U14 ( .A(n1509), .B(intadd_68_B_2_), .C(intadd_68_n14),
.CO(intadd_68_n13), .S(intadd_68_SUM_2_) );
CMPR32X2TS intadd_68_U13 ( .A(n1516), .B(intadd_68_B_3_), .C(intadd_68_n13),
.CO(intadd_68_n12), .S(intadd_68_SUM_3_) );
CMPR32X2TS intadd_68_U12 ( .A(n1515), .B(intadd_68_B_4_), .C(intadd_68_n12),
.CO(intadd_68_n11), .S(intadd_68_SUM_4_) );
CMPR32X2TS intadd_68_U11 ( .A(n1521), .B(intadd_68_B_5_), .C(intadd_68_n11),
.CO(intadd_68_n10), .S(intadd_68_SUM_5_) );
CMPR32X2TS intadd_68_U10 ( .A(n1520), .B(intadd_68_B_6_), .C(intadd_68_n10),
.CO(intadd_68_n9), .S(intadd_68_SUM_6_) );
CMPR32X2TS intadd_68_U9 ( .A(n1527), .B(intadd_68_B_7_), .C(intadd_68_n9),
.CO(intadd_68_n8), .S(intadd_68_SUM_7_) );
CMPR32X2TS intadd_68_U8 ( .A(n1549), .B(intadd_68_B_8_), .C(intadd_68_n8),
.CO(intadd_68_n7), .S(intadd_68_SUM_8_) );
CMPR32X2TS intadd_68_U7 ( .A(n1548), .B(intadd_68_B_9_), .C(intadd_68_n7),
.CO(intadd_68_n6), .S(intadd_68_SUM_9_) );
CMPR32X2TS intadd_68_U6 ( .A(n1557), .B(intadd_68_B_10_), .C(intadd_68_n6),
.CO(intadd_68_n5), .S(intadd_68_SUM_10_) );
CMPR32X2TS intadd_68_U5 ( .A(n1556), .B(intadd_68_B_11_), .C(intadd_68_n5),
.CO(intadd_68_n4), .S(intadd_68_SUM_11_) );
CMPR32X2TS intadd_68_U4 ( .A(n1565), .B(intadd_68_B_12_), .C(intadd_68_n4),
.CO(intadd_68_n3), .S(intadd_68_SUM_12_) );
CMPR32X2TS intadd_68_U3 ( .A(n1564), .B(intadd_68_B_13_), .C(intadd_68_n3),
.CO(intadd_68_n2), .S(intadd_68_SUM_13_) );
CMPR32X2TS intadd_68_U2 ( .A(n1569), .B(intadd_68_B_14_), .C(intadd_68_n2),
.CO(intadd_68_n1), .S(intadd_68_SUM_14_) );
CMPR32X2TS intadd_69_U6 ( .A(n1555), .B(intadd_69_B_0_), .C(intadd_69_CI),
.CO(intadd_69_n5), .S(intadd_69_SUM_0_) );
CMPR32X2TS intadd_69_U5 ( .A(n1554), .B(intadd_69_B_1_), .C(intadd_69_n5),
.CO(intadd_69_n4), .S(intadd_69_SUM_1_) );
CMPR32X2TS intadd_69_U4 ( .A(n1552), .B(intadd_69_B_2_), .C(intadd_69_n4),
.CO(intadd_69_n3), .S(intadd_69_SUM_2_) );
CMPR32X2TS intadd_69_U3 ( .A(intadd_69_A_3_), .B(intadd_69_B_3_), .C(
intadd_69_n3), .CO(intadd_69_n2), .S(intadd_69_SUM_3_) );
CMPR32X2TS intadd_69_U2 ( .A(intadd_69_A_4_), .B(intadd_69_B_4_), .C(
intadd_69_n2), .CO(intadd_69_n1), .S(intadd_69_SUM_4_) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n1581),
.Q(intDX_EWSW[24]), .QN(n1562) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n785), .CK(clk), .RN(n1577), .Q(
Data_array_SWR[14]), .QN(n1561) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n783), .CK(clk), .RN(n1579), .Q(
Data_array_SWR[12]), .QN(n1560) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n794), .CK(clk), .RN(n1581), .Q(
Data_array_SWR[23]), .QN(n1559) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n1588), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1551) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n1580),
.Q(intDY_EWSW[18]), .QN(n1546) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n1576),
.Q(intDY_EWSW[30]), .QN(n1544) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1577),
.Q(intDY_EWSW[23]), .QN(n1543) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1587),
.Q(intDY_EWSW[26]), .QN(n1541) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n1583),
.Q(intDY_EWSW[20]), .QN(n1540) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n1576),
.Q(intDY_EWSW[14]), .QN(n1538) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n1580),
.Q(intDY_EWSW[12]), .QN(n1537) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n876), .Q(
intDY_EWSW[8]), .QN(n1534) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n1574), .Q(
intDY_EWSW[1]), .QN(n1533) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n876), .Q(
intDY_EWSW[21]), .QN(n1532) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n876), .Q(
intDY_EWSW[13]), .QN(n1531) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n1577), .Q(
intDY_EWSW[3]), .QN(n1529) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n1576), .Q(
intDX_EWSW[6]), .QN(n1514) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[16]), .QN(n1513) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n1580), .Q(
shift_value_SHT2_EWR[4]), .QN(n1511) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1574), .Q(
intDX_EWSW[5]), .QN(n1507) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n1574),
.Q(intDX_EWSW[25]), .QN(n1499) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n1574),
.Q(intDY_EWSW[29]), .QN(n1493) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n1579),
.Q(intDY_EWSW[22]), .QN(n1492) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1578), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1489) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n1573), .Q(
intDX_EWSW[7]), .QN(n1488) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n1581), .Q(
intDX_EWSW[4]), .QN(n1487) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n1601), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1475) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1577),
.Q(intDY_EWSW[25]), .QN(n1606) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n876), .Q(
intDY_EWSW[15]), .QN(n1605) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n1579),
.Q(intDY_EWSW[11]), .QN(n1604) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n931), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1553) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n1588), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1547) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n1601), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1526) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n1601), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1508) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n1595), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1558) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n1584), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1478) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n1589), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1504) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n1595), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1512) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n1595), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1482) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n532), .CK(clk), .RN(n1589), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1476) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n1589), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1477) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n1588), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1479) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n1584), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1481) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n1574), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1525) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n933), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1497) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n1592), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1486) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n932), .Q(
Raw_mant_NRM_SWR[15]), .QN(n1485) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n1596), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1474) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n1601),
.Q(intDY_EWSW[19]), .QN(n1494) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1576),
.Q(intDY_EWSW[27]), .QN(n1545) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n1577),
.Q(intDY_EWSW[24]), .QN(n1480) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n876), .Q(
intDY_EWSW[16]), .QN(n1539) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n876), .Q(
intDY_EWSW[9]), .QN(n1530) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n1580), .Q(
intDY_EWSW[6]), .QN(n1523) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n1573),
.Q(intDY_EWSW[28]), .QN(n1542) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n1576), .Q(
intDY_EWSW[0]), .QN(n1491) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n1573), .Q(
intDY_EWSW[2]), .QN(n1535) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n1579), .Q(
intDY_EWSW[4]), .QN(n1536) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n1581), .Q(
intDY_EWSW[7]), .QN(n1524) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n876), .Q(
intDY_EWSW[5]), .QN(n1490) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[26]), .QN(n1566) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n1575),
.Q(intDX_EWSW[28]), .QN(n1519) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n1574), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1502) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n1592), .Q(
DmP_EXP_EWSW[26]), .QN(n1498) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n932), .Q(
DmP_EXP_EWSW[24]), .QN(n1495) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n931), .Q(
DmP_EXP_EWSW[25]), .QN(n1563) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n1600), .Q(
DMP_EXP_EWSW[25]), .QN(n1550) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n1590), .Q(
DMP_EXP_EWSW[26]), .QN(n1500) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n1586), .Q(
DMP_EXP_EWSW[24]), .QN(n1496) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n931), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1506) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1578), .Q(
shift_value_SHT2_EWR[3]), .QN(n1505) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n931), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1501) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n933), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1472) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n1596), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1473) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n1575), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1484) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n781), .CK(clk), .RN(n1595), .Q(
Data_array_SWR[10]), .QN(n1567) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n1586), .Q(
DMP_SFG[16]), .QN(n1549) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1588), .Q(
LZD_output_NRM2_EW[2]), .QN(n1518) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n1578), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1575),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n1581),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n1575),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n1574),
.Q(intDX_EWSW[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n793), .CK(clk), .RN(n1573), .Q(
Data_array_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n796), .CK(clk), .RN(n1578), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n1576), .Q(
Data_array_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n1592), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n1576),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n1575),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n1578), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n1575), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n1581), .Q(
intDX_EWSW[9]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n770), .CK(clk), .RN(n1573), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1579), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n784), .CK(clk), .RN(n876), .Q(
Data_array_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n932), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n933), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n1573),
.Q(intDX_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[29]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n1576),
.Q(intDX_EWSW[27]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n1581), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n779), .CK(clk), .RN(n1585), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n790), .CK(clk), .RN(n1577), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n787), .CK(clk), .RN(n876), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n1595), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n931), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n777), .CK(clk), .RN(n1580), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1579), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n775), .CK(clk), .RN(n876), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n776), .CK(clk), .RN(n1586), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n1585), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n1582), .Q(
DMP_SFG[1]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1575),
.Q(intDX_EWSW[31]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n1579),
.Q(intDY_EWSW[10]), .QN(n881) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n1575), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n1598), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n1592), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n932), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n1596), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1596), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1597), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n1591), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n581), .CK(clk), .RN(n1576), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1598), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1589), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n1597), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n931), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1594), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1586), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1587), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1583), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n1599), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n478), .CK(clk), .RN(n1591), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n474), .CK(clk), .RN(n1599), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n1586), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n1587), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n477), .CK(clk), .RN(n1582), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1577),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n876), .Q(
intDY_EWSW[17]), .QN(n1572) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1590), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n1585), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n1585), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n1595), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n1588), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n1575),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n1573),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1575),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n1581),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n1574), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n1576),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n1573),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n1574),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n780), .CK(clk), .RN(n1580), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n782), .CK(clk), .RN(n1580), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n792), .CK(clk), .RN(n1575), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n789), .CK(clk), .RN(n876), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n788), .CK(clk), .RN(n1600), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n791), .CK(clk), .RN(n1573), .Q(
Data_array_SWR[20]) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n549), .CK(clk), .RN(n1594), .Q(
OP_FLAG_SFG), .QN(n930) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n1590), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1575), .Q(
intAS) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[22]), .QN(n912) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n1597), .Q(
DmP_mant_SFG_SWR[7]), .QN(n923) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n480), .CK(clk), .RN(n1594), .Q(
DmP_mant_SFG_SWR[8]), .QN(n925) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n931), .Q(
DmP_EXP_EWSW[23]), .QN(n908) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n774), .CK(clk), .RN(n1577), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1580), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n876), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n771), .CK(clk), .RN(n1579), .Q(
Data_array_SWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n931), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n1589), .Q(
DMP_SFG[22]), .QN(n1569) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1584), .Q(
DMP_SFG[21]), .QN(n1564) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n1585), .Q(
DMP_SFG[20]), .QN(n1565) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n1588), .Q(
DMP_SFG[19]), .QN(n1556) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n1583), .Q(
DMP_SFG[18]), .QN(n1557) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n1587), .Q(
DMP_SFG[17]), .QN(n1548) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1590), .Q(
DMP_SFG[15]), .QN(n1527) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1590), .Q(
DMP_SFG[14]), .QN(n1520) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n1586), .Q(
DMP_SFG[13]), .QN(n1521) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n1590), .Q(
DMP_SFG[12]), .QN(n1515) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n1583), .Q(
DMP_SFG[11]), .QN(n1516) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n1595), .Q(
DMP_SFG[10]), .QN(n1509) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n1601), .Q(
DMP_SFG[9]), .QN(n1510) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n1589), .Q(
DMP_SFG[8]), .QN(n1503) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n1601), .Q(
DMP_SFG[4]), .QN(n1552) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n1585), .Q(
DMP_SFG[3]), .QN(n1554) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n1600), .Q(
DMP_SFG[2]), .QN(n1555) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n1584), .Q(
LZD_output_NRM2_EW[3]), .QN(n1522) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1585), .Q(
LZD_output_NRM2_EW[4]), .QN(n1528) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n1589), .Q(
LZD_output_NRM2_EW[1]), .QN(n1517) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n1573), .Q(
n1483), .QN(n1568) );
ADDFX1TS DP_OP_15J60_123_4652_U8 ( .A(n1517), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J60_123_4652_n8), .CO(DP_OP_15J60_123_4652_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J60_123_4652_U7 ( .A(n1518), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J60_123_4652_n7), .CO(DP_OP_15J60_123_4652_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J60_123_4652_U6 ( .A(n1522), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J60_123_4652_n6), .CO(DP_OP_15J60_123_4652_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J60_123_4652_U5 ( .A(n1528), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J60_123_4652_n5), .CO(DP_OP_15J60_123_4652_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n1578), .Q(
Shift_reg_FLAGS_7[1]), .QN(n874) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n867), .CK(clk), .RN(n1581), .Q(
n873), .QN(n1570) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n1576), .Q(
Shift_reg_FLAGS_7_6), .QN(n878) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n1581), .Q(
Shift_reg_FLAGS_7[0]), .QN(n872) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n865), .CK(clk), .RN(n1576), .Q(
n929), .QN(n1602) );
NAND2X4TS U897 ( .A(n1169), .B(n1288), .Y(n1155) );
CLKINVX6TS U898 ( .A(rst), .Y(n931) );
AOI222X4TS U899 ( .A0(Data_array_SWR[21]), .A1(n1404), .B0(
Data_array_SWR[17]), .B1(n1403), .C0(Data_array_SWR[25]), .C1(n1389),
.Y(n1426) );
BUFX4TS U900 ( .A(n931), .Y(n932) );
NOR2X4TS U901 ( .A(n1169), .B(n1211), .Y(n1170) );
NAND2X4TS U902 ( .A(n1151), .B(n1304), .Y(n1150) );
AOI211X2TS U903 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1138), .B0(n1260), .C0(
n1137), .Y(n1152) );
INVX2TS U904 ( .A(n1143), .Y(n1145) );
OAI21XLTS U905 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1121), .Y(n1122) );
CLKINVX6TS U906 ( .A(n1298), .Y(n1167) );
INVX3TS U907 ( .A(n1290), .Y(n902) );
NAND3X1TS U908 ( .A(n1123), .B(n1254), .C(Raw_mant_NRM_SWR[1]), .Y(n1248) );
NAND3X1TS U909 ( .A(n1144), .B(n1130), .C(n1249), .Y(n1260) );
OAI211X1TS U910 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1129), .B0(n1253), .C0(
n1512), .Y(n1130) );
BUFX4TS U911 ( .A(n1037), .Y(n893) );
NOR2X4TS U912 ( .A(n1017), .B(n1066), .Y(n1025) );
INVX4TS U913 ( .A(n1277), .Y(n875) );
AND2X4TS U914 ( .A(beg_OP), .B(n1271), .Y(n1275) );
NOR2X6TS U915 ( .A(n1468), .B(n1414), .Y(n1367) );
NAND2X2TS U916 ( .A(n894), .B(n1423), .Y(n1328) );
NOR2X6TS U917 ( .A(shift_value_SHT2_EWR[4]), .B(n1383), .Y(n1366) );
NAND3X1TS U918 ( .A(n1502), .B(n1485), .C(n1474), .Y(n1246) );
BUFX6TS U919 ( .A(n932), .Y(n876) );
NAND2BXLTS U920 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n967) );
NAND2BXLTS U921 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1001) );
NAND2BXLTS U922 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n955) );
NAND2BXLTS U923 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n980) );
NAND2BXLTS U924 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n976) );
NAND2BXLTS U925 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n995) );
NAND3XLTS U926 ( .A(n1541), .B(n955), .C(intDX_EWSW[26]), .Y(n957) );
NAND3BXLTS U927 ( .AN(n999), .B(n997), .C(n996), .Y(n1015) );
AOI222X4TS U928 ( .A0(Data_array_SWR[14]), .A1(n1366), .B0(
Data_array_SWR[22]), .B1(n1430), .C0(Data_array_SWR[18]), .C1(n1429),
.Y(n1379) );
AOI222X4TS U929 ( .A0(Data_array_SWR[23]), .A1(n1430), .B0(
Data_array_SWR[19]), .B1(n1429), .C0(Data_array_SWR[15]), .C1(n1366),
.Y(n1375) );
AOI222X4TS U930 ( .A0(Data_array_SWR[24]), .A1(n1430), .B0(
Data_array_SWR[20]), .B1(n1429), .C0(Data_array_SWR[16]), .C1(n1366),
.Y(n1371) );
AOI222X4TS U931 ( .A0(Data_array_SWR[21]), .A1(n1429), .B0(
Data_array_SWR[17]), .B1(n1366), .C0(Data_array_SWR[25]), .C1(n1430),
.Y(n1372) );
NAND2BXLTS U932 ( .AN(n1262), .B(n948), .Y(n950) );
OAI21XLTS U933 ( .A0(n1512), .A1(n1290), .B0(n1193), .Y(n1194) );
AOI222X1TS U934 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n902), .B0(n906), .B1(n897),
.C0(n1287), .C1(DmP_mant_SHT1_SW[10]), .Y(n1222) );
AOI222X1TS U935 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n902), .B0(n906), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1287), .C1(n895), .Y(n1173) );
AOI222X1TS U936 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n902), .B0(n906), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1287), .C1(DmP_mant_SHT1_SW[3]), .Y(n1184)
);
AOI222X1TS U937 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n902), .B0(n906), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1287), .C1(DmP_mant_SHT1_SW[8]), .Y(n1187)
);
AOI222X1TS U938 ( .A0(n1238), .A1(DMP_SFG[1]), .B0(n1238), .B1(n891), .C0(
DMP_SFG[1]), .C1(n891), .Y(intadd_69_B_0_) );
AOI222X1TS U939 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n902), .B0(n906), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1287), .C1(DmP_mant_SHT1_SW[7]), .Y(n1208)
);
AOI222X1TS U940 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n902), .B0(n906), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1287), .C1(DmP_mant_SHT1_SW[16]), .Y(n1235) );
AOI211X1TS U941 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n874), .B0(n1213), .C0(
n1212), .Y(n1281) );
OAI211XLTS U942 ( .A0(n1258), .A1(n1257), .B0(n1256), .C0(n1255), .Y(n1259)
);
AO22XLTS U943 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n1359), .B0(n1358), .B1(n926),
.Y(n879) );
AOI2BB2XLTS U944 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n1358), .A0N(n1358), .A1N(
DmP_mant_SFG_SWR[10]), .Y(intadd_68_CI) );
NAND4XLTS U945 ( .A(n1250), .B(n1249), .C(n1248), .D(n1255), .Y(n1251) );
OAI21XLTS U946 ( .A0(n1478), .A1(n1124), .B0(n1248), .Y(n1125) );
AO22XLTS U947 ( .A0(DmP_mant_SFG_SWR[3]), .A1(n1359), .B0(n1358), .B1(n919),
.Y(n882) );
OAI21XLTS U948 ( .A0(n1497), .A1(n1290), .B0(n1289), .Y(n1291) );
OAI21XLTS U949 ( .A0(n1481), .A1(n1290), .B0(n1197), .Y(n1198) );
OAI21XLTS U950 ( .A0(n1475), .A1(n1290), .B0(n1284), .Y(n1285) );
AOI222X1TS U951 ( .A0(n1391), .A1(n1468), .B0(Data_array_SWR[8]), .B1(n1438),
.C0(n1390), .C1(n1411), .Y(n1458) );
AOI222X1TS U952 ( .A0(n1391), .A1(n1437), .B0(Data_array_SWR[8]), .B1(n1367),
.C0(n1390), .C1(n1410), .Y(n1446) );
AOI222X1TS U953 ( .A0(n1386), .A1(n1468), .B0(Data_array_SWR[9]), .B1(n1438),
.C0(n1385), .C1(n1411), .Y(n1457) );
AOI222X1TS U954 ( .A0(n1386), .A1(n1437), .B0(Data_array_SWR[9]), .B1(n1367),
.C0(n1385), .C1(n1410), .Y(n1447) );
AO22XLTS U955 ( .A0(n1339), .A1(DmP_EXP_EWSW[22]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[22]), .Y(n565) );
OAI21XLTS U956 ( .A0(n1205), .A1(n1150), .B0(n1204), .Y(n791) );
OAI211XLTS U957 ( .A0(n1235), .A1(n1150), .B0(n1234), .C0(n1233), .Y(n788)
);
OAI21XLTS U958 ( .A0(n1205), .A1(n1167), .B0(n1196), .Y(n789) );
OAI211XLTS U959 ( .A0(n1187), .A1(n1150), .B0(n1186), .C0(n1185), .Y(n780)
);
AOI2BB2XLTS U960 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1296), .A0N(n1222), .A1N(
n1167), .Y(n1185) );
AO22XLTS U961 ( .A0(n1274), .A1(Data_X[19]), .B0(n1279), .B1(intDX_EWSW[19]),
.Y(n843) );
AO22XLTS U962 ( .A0(n1275), .A1(Data_X[30]), .B0(n1272), .B1(intDX_EWSW[30]),
.Y(n832) );
AO22XLTS U963 ( .A0(n1280), .A1(Data_X[10]), .B0(n1279), .B1(intDX_EWSW[10]),
.Y(n852) );
AO22XLTS U964 ( .A0(n1280), .A1(Data_Y[31]), .B0(n875), .B1(intDY_EWSW[31]),
.Y(n797) );
AO22XLTS U965 ( .A0(n1455), .A1(DMP_SHT2_EWSW[0]), .B0(n1456), .B1(
DMP_SFG[0]), .Y(n717) );
AO22XLTS U966 ( .A0(n1483), .A1(DmP_EXP_EWSW[0]), .B0(n1340), .B1(
DmP_mant_SHT1_SW[0]), .Y(n609) );
AO22XLTS U967 ( .A0(n1483), .A1(DmP_EXP_EWSW[1]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[1]), .Y(n607) );
AO22XLTS U968 ( .A0(n1483), .A1(DmP_EXP_EWSW[2]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[2]), .Y(n605) );
AO22XLTS U969 ( .A0(n1483), .A1(DmP_EXP_EWSW[6]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[6]), .Y(n597) );
AO22XLTS U970 ( .A0(n1339), .A1(DmP_EXP_EWSW[15]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[15]), .Y(n579) );
AO22XLTS U971 ( .A0(n1339), .A1(DmP_EXP_EWSW[12]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[12]), .Y(n585) );
AO22XLTS U972 ( .A0(n1339), .A1(DmP_EXP_EWSW[18]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[18]), .Y(n573) );
AO22XLTS U973 ( .A0(n1339), .A1(DmP_EXP_EWSW[14]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[14]), .Y(n581) );
AO22XLTS U974 ( .A0(n1339), .A1(DmP_EXP_EWSW[13]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[13]), .Y(n583) );
AO22XLTS U975 ( .A0(n1483), .A1(DmP_EXP_EWSW[8]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[8]), .Y(n593) );
AO22XLTS U976 ( .A0(n1339), .A1(DmP_EXP_EWSW[21]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[21]), .Y(n567) );
AO22XLTS U977 ( .A0(n1339), .A1(DmP_EXP_EWSW[16]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[16]), .Y(n577) );
AO22XLTS U978 ( .A0(n1339), .A1(DmP_EXP_EWSW[17]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[17]), .Y(n575) );
AO22XLTS U979 ( .A0(n1339), .A1(DmP_EXP_EWSW[20]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[20]), .Y(n569) );
AO22XLTS U980 ( .A0(n1280), .A1(Data_X[31]), .B0(n1278), .B1(intDX_EWSW[31]),
.Y(n831) );
AO22XLTS U981 ( .A0(n1453), .A1(DMP_SHT2_EWSW[1]), .B0(n1328), .B1(
DMP_SFG[1]), .Y(n714) );
AO22XLTS U982 ( .A0(n1453), .A1(DMP_SHT2_EWSW[7]), .B0(n1469), .B1(
DMP_SFG[7]), .Y(n696) );
OAI211XLTS U983 ( .A0(n1184), .A1(n1150), .B0(n1162), .C0(n1161), .Y(n775)
);
OAI211XLTS U984 ( .A0(n1187), .A1(n1167), .B0(n1179), .C0(n1178), .Y(n778)
);
OAI211XLTS U985 ( .A0(n1208), .A1(n1167), .B0(n1176), .C0(n1175), .Y(n777)
);
OAI211XLTS U986 ( .A0(n1231), .A1(n1150), .B0(n1229), .C0(n1228), .Y(n790)
);
OAI21XLTS U987 ( .A0(n1294), .A1(n1167), .B0(n1210), .Y(n779) );
AO22XLTS U988 ( .A0(n1280), .A1(Data_X[27]), .B0(n875), .B1(intDX_EWSW[27]),
.Y(n835) );
AO22XLTS U989 ( .A0(n1274), .A1(Data_X[29]), .B0(n875), .B1(intDX_EWSW[29]),
.Y(n833) );
AO22XLTS U990 ( .A0(n1277), .A1(Data_X[18]), .B0(n875), .B1(intDX_EWSW[18]),
.Y(n844) );
OAI211XLTS U991 ( .A0(n1223), .A1(n1150), .B0(n1218), .C0(n1217), .Y(n786)
);
AOI32X1TS U992 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1304), .A2(n874), .B0(
shift_value_SHT2_EWR[2]), .B1(n1301), .Y(n1303) );
AO22XLTS U993 ( .A0(n1276), .A1(Data_X[1]), .B0(n875), .B1(intDX_EWSW[1]),
.Y(n861) );
OAI21XLTS U994 ( .A0(n1504), .A1(n1155), .B0(n1216), .Y(n793) );
AO22XLTS U995 ( .A0(n1269), .A1(n1354), .B0(n1270), .B1(n894), .Y(n865) );
OAI211XLTS U996 ( .A0(n1304), .A1(n1511), .B0(n1244), .C0(n1127), .Y(n767)
);
AO22XLTS U997 ( .A0(n1339), .A1(DmP_EXP_EWSW[19]), .B0(n1333), .B1(n896),
.Y(n571) );
AO22XLTS U998 ( .A0(n1339), .A1(DmP_EXP_EWSW[9]), .B0(n1331), .B1(n897), .Y(
n591) );
AO22XLTS U999 ( .A0(n1483), .A1(DmP_EXP_EWSW[5]), .B0(n1333), .B1(n899), .Y(
n599) );
AO22XLTS U1000 ( .A0(n1483), .A1(DmP_EXP_EWSW[4]), .B0(n1333), .B1(n895),
.Y(n601) );
OAI21XLTS U1001 ( .A0(n1117), .A1(n1066), .B0(n1114), .Y(n1115) );
AO22XLTS U1002 ( .A0(n1276), .A1(Data_X[0]), .B0(n1279), .B1(n907), .Y(n862)
);
AO22XLTS U1003 ( .A0(n1270), .A1(busy), .B0(n1269), .B1(n894), .Y(n866) );
OR2X1TS U1004 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n884) );
OAI211XLTS U1005 ( .A0(n1158), .A1(n1150), .B0(n1157), .C0(n1156), .Y(n772)
);
OAI211XLTS U1006 ( .A0(n1184), .A1(n1167), .B0(n1183), .C0(n1182), .Y(n773)
);
OAI211XLTS U1007 ( .A0(n1173), .A1(n1167), .B0(n1172), .C0(n1171), .Y(n774)
);
NOR2X2TS U1008 ( .A(Raw_mant_NRM_SWR[6]), .B(n1128), .Y(n1253) );
BUFX4TS U1009 ( .A(n1592), .Y(n1600) );
BUFX3TS U1010 ( .A(n1568), .Y(n1332) );
AOI31XLTS U1011 ( .A0(n1134), .A1(Raw_mant_NRM_SWR[16]), .A2(n1502), .B0(
n1133), .Y(n1135) );
NOR2BX2TS U1012 ( .AN(n1258), .B(n1257), .Y(n1134) );
OAI211XLTS U1013 ( .A0(n958), .A1(n1080), .B0(n957), .C0(n956), .Y(n963) );
OAI21X2TS U1014 ( .A0(intDX_EWSW[26]), .A1(n1541), .B0(n955), .Y(n1080) );
BUFX4TS U1015 ( .A(n932), .Y(n1583) );
BUFX4TS U1016 ( .A(n1596), .Y(n1586) );
BUFX4TS U1017 ( .A(n1573), .Y(n1587) );
BUFX4TS U1018 ( .A(n1589), .Y(n1590) );
BUFX4TS U1019 ( .A(n1578), .Y(n1595) );
BUFX4TS U1020 ( .A(n1574), .Y(n1589) );
BUFX4TS U1021 ( .A(n1583), .Y(n1585) );
BUFX4TS U1022 ( .A(n1600), .Y(n1601) );
BUFX4TS U1023 ( .A(n1600), .Y(n1575) );
BUFX4TS U1024 ( .A(n1577), .Y(n1581) );
INVX2TS U1025 ( .A(n882), .Y(n891) );
INVX2TS U1026 ( .A(n879), .Y(n892) );
NOR2X2TS U1027 ( .A(Raw_mant_NRM_SWR[13]), .B(n1247), .Y(n1143) );
BUFX4TS U1028 ( .A(n876), .Y(n1578) );
BUFX4TS U1029 ( .A(n1580), .Y(n1573) );
BUFX4TS U1030 ( .A(n1579), .Y(n1576) );
BUFX4TS U1031 ( .A(n1583), .Y(n1574) );
XNOR2X2TS U1032 ( .A(DMP_exp_NRM2_EW[7]), .B(n939), .Y(n949) );
XNOR2X2TS U1033 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J60_123_4652_n4), .Y(
n951) );
NOR2X4TS U1034 ( .A(shift_value_SHT2_EWR[4]), .B(n1468), .Y(n1411) );
BUFX6TS U1035 ( .A(left_right_SHT2), .Y(n1468) );
BUFX4TS U1036 ( .A(n1020), .Y(n1325) );
INVX2TS U1037 ( .A(n883), .Y(n894) );
INVX2TS U1038 ( .A(n889), .Y(n895) );
INVX2TS U1039 ( .A(n888), .Y(n896) );
INVX2TS U1040 ( .A(n890), .Y(n897) );
INVX2TS U1041 ( .A(n887), .Y(n898) );
CLKINVX6TS U1042 ( .A(n1456), .Y(n1453) );
INVX2TS U1043 ( .A(n886), .Y(n899) );
CLKINVX6TS U1044 ( .A(n1328), .Y(n1455) );
INVX2TS U1045 ( .A(n885), .Y(n900) );
NOR4BX2TS U1046 ( .AN(n1149), .B(n1148), .C(n1147), .D(n1146), .Y(n1169) );
INVX2TS U1047 ( .A(n1290), .Y(n901) );
BUFX4TS U1048 ( .A(n930), .Y(n1358) );
BUFX4TS U1049 ( .A(n1368), .Y(n1438) );
BUFX4TS U1050 ( .A(n1365), .Y(n1429) );
BUFX4TS U1051 ( .A(n1066), .Y(n1268) );
INVX2TS U1052 ( .A(n1150), .Y(n903) );
INVX2TS U1053 ( .A(n903), .Y(n904) );
BUFX4TS U1054 ( .A(n1456), .Y(n1459) );
BUFX4TS U1055 ( .A(n1456), .Y(n1469) );
CLKINVX6TS U1056 ( .A(n1328), .Y(n1471) );
CLKINVX3TS U1057 ( .A(n884), .Y(n905) );
INVX3TS U1058 ( .A(n884), .Y(n906) );
AOI222X4TS U1059 ( .A0(Data_array_SWR[24]), .A1(n1389), .B0(
Data_array_SWR[20]), .B1(n1404), .C0(Data_array_SWR[16]), .C1(n1403),
.Y(n1434) );
OAI211XLTS U1060 ( .A0(n1222), .A1(n904), .B0(n1221), .C0(n1220), .Y(n782)
);
AOI32X1TS U1061 ( .A0(n1546), .A1(n1001), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1494), .Y(n1002) );
AOI221X1TS U1062 ( .A0(n1546), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1494), .C0(n1087), .Y(n1092) );
AOI221X1TS U1063 ( .A0(n1544), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1572), .C0(n1086), .Y(n1093) );
AOI221X4TS U1064 ( .A0(intDX_EWSW[30]), .A1(n1544), .B0(intDX_EWSW[29]),
.B1(n1493), .C0(n960), .Y(n962) );
INVX2TS U1065 ( .A(n880), .Y(n907) );
AOI221X1TS U1066 ( .A0(n881), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]), .B1(
n1604), .C0(n1095), .Y(n1100) );
AOI221X1TS U1067 ( .A0(n1535), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1529), .C0(n1103), .Y(n1108) );
AOI221X1TS U1068 ( .A0(n1492), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1543), .C0(n1089), .Y(n1090) );
AOI221X1TS U1069 ( .A0(n1538), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1605), .C0(n1097), .Y(n1098) );
OAI211X2TS U1070 ( .A0(intDX_EWSW[20]), .A1(n1540), .B0(n1009), .C0(n995),
.Y(n1004) );
AOI221X1TS U1071 ( .A0(n1540), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1532), .C0(n1088), .Y(n1091) );
OAI211X2TS U1072 ( .A0(intDX_EWSW[12]), .A1(n1537), .B0(n990), .C0(n976),
.Y(n992) );
AOI221X1TS U1073 ( .A0(n1537), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1531), .C0(n1096), .Y(n1099) );
INVX1TS U1074 ( .A(DMP_SFG[5]), .Y(intadd_69_A_3_) );
INVX1TS U1075 ( .A(DMP_SFG[6]), .Y(intadd_69_A_4_) );
OAI31XLTS U1076 ( .A0(n1327), .A1(n1117), .A2(n1336), .B0(n1116), .Y(n720)
);
NOR2X2TS U1077 ( .A(n908), .B(DMP_EXP_EWSW[23]), .Y(n1311) );
XNOR2X2TS U1078 ( .A(DMP_exp_NRM2_EW[0]), .B(n1242), .Y(n952) );
INVX1TS U1079 ( .A(LZD_output_NRM2_EW[0]), .Y(n1242) );
XNOR2X2TS U1080 ( .A(DMP_exp_NRM2_EW[6]), .B(n936), .Y(n1262) );
CLKINVX6TS U1081 ( .A(n1073), .Y(n1050) );
NOR2X4TS U1082 ( .A(shift_value_SHT2_EWR[4]), .B(n1437), .Y(n1410) );
CLKINVX6TS U1083 ( .A(n1468), .Y(n1437) );
AOI222X1TS U1084 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n901), .B0(
DmP_mant_SHT1_SW[14]), .B1(n1287), .C0(n905), .C1(DmP_mant_SHT1_SW[13]), .Y(n1223) );
AOI222X4TS U1085 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n901), .B0(n905), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1287), .C1(DmP_mant_SHT1_SW[17]), .Y(n1199) );
AOI222X1TS U1086 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n902), .B0(n906), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1287), .C1(DmP_mant_SHT1_SW[18]), .Y(n1231) );
AOI222X4TS U1087 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n901), .B0(n906), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1287), .C1(DmP_mant_SHT1_SW[21]), .Y(n1214) );
NOR2XLTS U1088 ( .A(n978), .B(intDY_EWSW[10]), .Y(n979) );
NOR2X4TS U1089 ( .A(n1364), .B(n1363), .Y(n1384) );
OAI2BB1X2TS U1090 ( .A0N(n942), .A1N(n941), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1363) );
INVX4TS U1091 ( .A(n1275), .Y(n1278) );
CLKINVX6TS U1092 ( .A(n1570), .Y(busy) );
NAND2X2TS U1093 ( .A(n874), .B(n1570), .Y(n1304) );
AOI22X2TS U1094 ( .A0(DmP_mant_SFG_SWR[7]), .A1(n1358), .B0(n1359), .B1(n923), .Y(intadd_69_B_3_) );
AOI22X2TS U1095 ( .A0(n1355), .A1(DmP_mant_SFG_SWR[8]), .B0(n1359), .B1(n925), .Y(intadd_69_B_4_) );
CLKINVX6TS U1096 ( .A(n1358), .Y(n1359) );
AOI222X4TS U1097 ( .A0(DMP_SFG[7]), .A1(n892), .B0(DMP_SFG[7]), .B1(n1241),
.C0(n892), .C1(n1241), .Y(intadd_68_B_0_) );
AOI222X1TS U1098 ( .A0(n1405), .A1(n1437), .B0(n1367), .B1(Data_array_SWR[5]), .C0(n1406), .C1(n1410), .Y(n1443) );
AOI222X1TS U1099 ( .A0(n1405), .A1(n1468), .B0(Data_array_SWR[5]), .B1(n1438), .C0(n1406), .C1(n1411), .Y(n1462) );
AOI222X1TS U1100 ( .A0(n1413), .A1(n1437), .B0(n1367), .B1(Data_array_SWR[4]), .C0(n1412), .C1(n1410), .Y(n1442) );
AOI222X1TS U1101 ( .A0(n1413), .A1(n1468), .B0(Data_array_SWR[4]), .B1(n1438), .C0(n1412), .C1(n1411), .Y(n1463) );
AOI222X1TS U1102 ( .A0(n1395), .A1(n1437), .B0(Data_array_SWR[7]), .B1(n1367), .C0(n1394), .C1(n1410), .Y(n1445) );
AOI222X1TS U1103 ( .A0(n1395), .A1(n1468), .B0(Data_array_SWR[7]), .B1(n1438), .C0(n1394), .C1(n1411), .Y(n1460) );
AOI222X1TS U1104 ( .A0(n1400), .A1(n1437), .B0(Data_array_SWR[6]), .B1(n1367), .C0(n1399), .C1(n1410), .Y(n1444) );
AOI222X1TS U1105 ( .A0(n1400), .A1(n1468), .B0(Data_array_SWR[6]), .B1(n1438), .C0(n1399), .C1(n1411), .Y(n1461) );
INVX4TS U1106 ( .A(n1602), .Y(n1357) );
INVX3TS U1107 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1423) );
AOI222X1TS U1108 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n901), .B0(n905), .B1(n896),
.C0(n1287), .C1(DmP_mant_SHT1_SW[20]), .Y(n1227) );
OAI21XLTS U1109 ( .A0(n1286), .A1(n1150), .B0(n1201), .Y(n787) );
NOR2X2TS U1110 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1525), .Y(n1267) );
AOI221X1TS U1111 ( .A0(n1541), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]),
.B1(n1545), .C0(n1080), .Y(n1084) );
OAI21X2TS U1112 ( .A0(intDX_EWSW[18]), .A1(n1546), .B0(n1001), .Y(n1087) );
NOR3X1TS U1113 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1258) );
NOR2X2TS U1114 ( .A(Raw_mant_NRM_SWR[12]), .B(n1136), .Y(n1252) );
AOI222X1TS U1115 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n901), .B0(n905), .B1(n898), .C0(n1287), .C1(DmP_mant_SHT1_SW[12]), .Y(n1226) );
OAI211XLTS U1116 ( .A0(n1226), .A1(n904), .B0(n1225), .C0(n1224), .Y(n784)
);
NOR3X1TS U1117 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1505), .Y(n1365) );
NOR2X4TS U1118 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1403) );
NOR2XLTS U1119 ( .A(n1604), .B(intDX_EWSW[11]), .Y(n978) );
OAI21XLTS U1120 ( .A0(intDX_EWSW[15]), .A1(n1605), .B0(intDX_EWSW[14]), .Y(
n986) );
NOR2XLTS U1121 ( .A(n999), .B(intDY_EWSW[16]), .Y(n1000) );
OAI21XLTS U1122 ( .A0(intDX_EWSW[23]), .A1(n1543), .B0(intDX_EWSW[22]), .Y(
n1005) );
OAI21XLTS U1123 ( .A0(intDX_EWSW[21]), .A1(n1532), .B0(intDX_EWSW[20]), .Y(
n998) );
NOR2XLTS U1124 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1139) );
OR2X1TS U1125 ( .A(n950), .B(n949), .Y(n1236) );
OAI21XLTS U1126 ( .A0(n1486), .A1(n1211), .B0(n1206), .Y(n1207) );
OAI21XLTS U1127 ( .A0(n1558), .A1(n1211), .B0(n1189), .Y(n1190) );
OAI21XLTS U1128 ( .A0(n1534), .A1(n1050), .B0(n1045), .Y(n745) );
OAI211XLTS U1129 ( .A0(n1173), .A1(n904), .B0(n1166), .C0(n1165), .Y(n776)
);
OAI21XLTS U1130 ( .A0(n1283), .A1(n1167), .B0(n1192), .Y(n792) );
CLKBUFX2TS U1131 ( .A(n931), .Y(n933) );
BUFX3TS U1132 ( .A(n1581), .Y(n1588) );
BUFX3TS U1133 ( .A(n932), .Y(n1591) );
BUFX3TS U1134 ( .A(n932), .Y(n1592) );
BUFX3TS U1135 ( .A(n1575), .Y(n1584) );
BUFX3TS U1136 ( .A(n931), .Y(n1594) );
BUFX3TS U1137 ( .A(n931), .Y(n1580) );
BUFX3TS U1138 ( .A(n931), .Y(n1597) );
BUFX3TS U1139 ( .A(n932), .Y(n1598) );
BUFX3TS U1140 ( .A(n931), .Y(n1579) );
BUFX3TS U1141 ( .A(n931), .Y(n1596) );
BUFX3TS U1142 ( .A(n1575), .Y(n1599) );
BUFX3TS U1143 ( .A(n932), .Y(n1577) );
BUFX3TS U1144 ( .A(n1589), .Y(n1582) );
INVX2TS U1145 ( .A(DP_OP_15J60_123_4652_n4), .Y(n934) );
NAND2X1TS U1146 ( .A(n1526), .B(n934), .Y(n936) );
INVX2TS U1147 ( .A(n936), .Y(n935) );
NAND2X1TS U1148 ( .A(n1547), .B(n935), .Y(n939) );
AND4X1TS U1149 ( .A(exp_rslt_NRM2_EW1[3]), .B(n952), .C(exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n937) );
AND4X1TS U1150 ( .A(n1262), .B(n951), .C(exp_rslt_NRM2_EW1[4]), .D(n937),
.Y(n938) );
CLKAND2X2TS U1151 ( .A(n949), .B(n938), .Y(n942) );
INVX2TS U1152 ( .A(n939), .Y(n940) );
CLKAND2X2TS U1153 ( .A(n1553), .B(n940), .Y(n941) );
INVX2TS U1154 ( .A(n1363), .Y(n943) );
AO22XLTS U1155 ( .A0(n943), .A1(n949), .B0(n1423), .B1(final_result_ieee[30]), .Y(n754) );
NOR2XLTS U1156 ( .A(n952), .B(exp_rslt_NRM2_EW1[1]), .Y(n946) );
INVX2TS U1157 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n945) );
INVX2TS U1158 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n944) );
NAND4BXLTS U1159 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n946), .C(n945), .D(n944),
.Y(n947) );
NOR2XLTS U1160 ( .A(n947), .B(n951), .Y(n948) );
NAND2X2TS U1161 ( .A(n1236), .B(Shift_reg_FLAGS_7[0]), .Y(n1263) );
OA22X1TS U1162 ( .A0(n1263), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n757) );
OA22X1TS U1163 ( .A0(n1263), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n760) );
OA22X1TS U1164 ( .A0(n1263), .A1(n951), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n756) );
OA22X1TS U1165 ( .A0(n1263), .A1(n952), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n761) );
OA22X1TS U1166 ( .A0(n1263), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n758) );
OA22X1TS U1167 ( .A0(n1263), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n759) );
OAI21XLTS U1168 ( .A0(n873), .A1(n1437), .B0(n874), .Y(n829) );
AOI2BB2XLTS U1169 ( .B0(beg_OP), .B1(n1489), .A0N(n1489), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n953) );
NAND3XLTS U1170 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1489), .C(
n1525), .Y(n1264) );
OAI21XLTS U1171 ( .A0(n1267), .A1(n953), .B0(n1264), .Y(n870) );
NOR2X1TS U1172 ( .A(n1606), .B(intDX_EWSW[25]), .Y(n1012) );
NOR2XLTS U1173 ( .A(n1012), .B(intDY_EWSW[24]), .Y(n954) );
AOI22X1TS U1174 ( .A0(intDX_EWSW[25]), .A1(n1606), .B0(intDX_EWSW[24]), .B1(
n954), .Y(n958) );
NAND2BXLTS U1175 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n956) );
NOR2X1TS U1176 ( .A(n1544), .B(intDX_EWSW[30]), .Y(n961) );
NOR2X1TS U1177 ( .A(n1493), .B(intDX_EWSW[29]), .Y(n959) );
AOI211X1TS U1178 ( .A0(intDY_EWSW[28]), .A1(n1519), .B0(n961), .C0(n959),
.Y(n1011) );
NOR3XLTS U1179 ( .A(n1519), .B(n959), .C(intDY_EWSW[28]), .Y(n960) );
AOI2BB2X1TS U1180 ( .B0(n963), .B1(n1011), .A0N(n962), .A1N(n961), .Y(n1016)
);
NOR2X1TS U1181 ( .A(n1572), .B(intDX_EWSW[17]), .Y(n999) );
OAI22X1TS U1182 ( .A0(n881), .A1(intDX_EWSW[10]), .B0(n1604), .B1(
intDX_EWSW[11]), .Y(n1095) );
INVX2TS U1183 ( .A(n1095), .Y(n983) );
OAI211XLTS U1184 ( .A0(intDX_EWSW[8]), .A1(n1534), .B0(n980), .C0(n983), .Y(
n994) );
OAI2BB1X1TS U1185 ( .A0N(n1507), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n964) );
OAI22X1TS U1186 ( .A0(intDY_EWSW[4]), .A1(n964), .B0(n1507), .B1(
intDY_EWSW[5]), .Y(n975) );
OAI2BB1X1TS U1187 ( .A0N(n1488), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n965) );
OAI22X1TS U1188 ( .A0(intDY_EWSW[6]), .A1(n965), .B0(n1488), .B1(
intDY_EWSW[7]), .Y(n974) );
OAI21XLTS U1189 ( .A0(intDX_EWSW[1]), .A1(n1533), .B0(n907), .Y(n966) );
OAI2BB2XLTS U1190 ( .B0(intDY_EWSW[0]), .B1(n966), .A0N(intDX_EWSW[1]),
.A1N(n1533), .Y(n968) );
OAI211XLTS U1191 ( .A0(n1529), .A1(intDX_EWSW[3]), .B0(n968), .C0(n967), .Y(
n971) );
OAI21XLTS U1192 ( .A0(intDX_EWSW[3]), .A1(n1529), .B0(intDX_EWSW[2]), .Y(
n969) );
AOI2BB2XLTS U1193 ( .B0(intDX_EWSW[3]), .B1(n1529), .A0N(intDY_EWSW[2]),
.A1N(n969), .Y(n970) );
AOI222X1TS U1194 ( .A0(intDY_EWSW[4]), .A1(n1487), .B0(n971), .B1(n970),
.C0(intDY_EWSW[5]), .C1(n1507), .Y(n973) );
AOI22X1TS U1195 ( .A0(intDY_EWSW[7]), .A1(n1488), .B0(intDY_EWSW[6]), .B1(
n1514), .Y(n972) );
OAI32X1TS U1196 ( .A0(n975), .A1(n974), .A2(n973), .B0(n972), .B1(n974), .Y(
n993) );
OA22X1TS U1197 ( .A0(n1538), .A1(intDX_EWSW[14]), .B0(n1605), .B1(
intDX_EWSW[15]), .Y(n990) );
OAI21XLTS U1198 ( .A0(intDX_EWSW[13]), .A1(n1531), .B0(intDX_EWSW[12]), .Y(
n977) );
OAI2BB2XLTS U1199 ( .B0(intDY_EWSW[12]), .B1(n977), .A0N(intDX_EWSW[13]),
.A1N(n1531), .Y(n989) );
AOI22X1TS U1200 ( .A0(intDX_EWSW[11]), .A1(n1604), .B0(intDX_EWSW[10]), .B1(
n979), .Y(n985) );
NAND2BXLTS U1201 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n982) );
NAND3XLTS U1202 ( .A(n1534), .B(n980), .C(intDX_EWSW[8]), .Y(n981) );
AOI21X1TS U1203 ( .A0(n982), .A1(n981), .B0(n992), .Y(n984) );
OAI2BB2XLTS U1204 ( .B0(n985), .B1(n992), .A0N(n984), .A1N(n983), .Y(n988)
);
OAI2BB2XLTS U1205 ( .B0(intDY_EWSW[14]), .B1(n986), .A0N(intDX_EWSW[15]),
.A1N(n1605), .Y(n987) );
AOI211X1TS U1206 ( .A0(n990), .A1(n989), .B0(n988), .C0(n987), .Y(n991) );
OAI31X1TS U1207 ( .A0(n994), .A1(n993), .A2(n992), .B0(n991), .Y(n997) );
OA22X1TS U1208 ( .A0(n1492), .A1(intDX_EWSW[22]), .B0(n1543), .B1(
intDX_EWSW[23]), .Y(n1009) );
AOI211XLTS U1209 ( .A0(intDY_EWSW[16]), .A1(n1513), .B0(n1004), .C0(n1087),
.Y(n996) );
OAI2BB2XLTS U1210 ( .B0(intDY_EWSW[20]), .B1(n998), .A0N(intDX_EWSW[21]),
.A1N(n1532), .Y(n1008) );
AOI22X1TS U1211 ( .A0(intDX_EWSW[17]), .A1(n1572), .B0(intDX_EWSW[16]), .B1(
n1000), .Y(n1003) );
OAI32X1TS U1212 ( .A0(n1087), .A1(n1004), .A2(n1003), .B0(n1002), .B1(n1004),
.Y(n1007) );
OAI2BB2XLTS U1213 ( .B0(intDY_EWSW[22]), .B1(n1005), .A0N(intDX_EWSW[23]),
.A1N(n1543), .Y(n1006) );
AOI211X1TS U1214 ( .A0(n1009), .A1(n1008), .B0(n1007), .C0(n1006), .Y(n1014)
);
NAND2BXLTS U1215 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1010) );
NAND4BBX1TS U1216 ( .AN(n1080), .BN(n1012), .C(n1011), .D(n1010), .Y(n1013)
);
AOI32X1TS U1217 ( .A0(n1016), .A1(n1015), .A2(n1014), .B0(n1013), .B1(n1016),
.Y(n1017) );
INVX2TS U1218 ( .A(Shift_reg_FLAGS_7_6), .Y(n1020) );
INVX4TS U1219 ( .A(n1025), .Y(n1336) );
AND2X2TS U1220 ( .A(Shift_reg_FLAGS_7_6), .B(n1017), .Y(n1040) );
AOI22X1TS U1221 ( .A0(n900), .A1(n1268), .B0(intDX_EWSW[27]), .B1(n1040),
.Y(n1018) );
OAI21XLTS U1222 ( .A0(n1545), .A1(n1336), .B0(n1018), .Y(n726) );
AOI22X1TS U1223 ( .A0(intDX_EWSW[1]), .A1(n1040), .B0(DMP_EXP_EWSW[1]), .B1(
n1325), .Y(n1019) );
OAI21XLTS U1224 ( .A0(n1533), .A1(n1336), .B0(n1019), .Y(n752) );
BUFX3TS U1225 ( .A(n1040), .Y(n1037) );
BUFX4TS U1226 ( .A(n1020), .Y(n1066) );
AOI22X1TS U1227 ( .A0(intDX_EWSW[28]), .A1(n1037), .B0(DMP_EXP_EWSW[28]),
.B1(n1066), .Y(n1021) );
OAI21XLTS U1228 ( .A0(n1542), .A1(n1336), .B0(n1021), .Y(n725) );
AOI22X1TS U1229 ( .A0(intDX_EWSW[29]), .A1(n1037), .B0(DMP_EXP_EWSW[29]),
.B1(n1066), .Y(n1022) );
OAI21XLTS U1230 ( .A0(n1493), .A1(n1336), .B0(n1022), .Y(n724) );
AOI22X1TS U1231 ( .A0(intDX_EWSW[30]), .A1(n1037), .B0(DMP_EXP_EWSW[30]),
.B1(n1325), .Y(n1023) );
OAI21XLTS U1232 ( .A0(n1544), .A1(n1336), .B0(n1023), .Y(n723) );
AOI22X1TS U1233 ( .A0(DMP_EXP_EWSW[23]), .A1(n1268), .B0(intDX_EWSW[23]),
.B1(n1037), .Y(n1024) );
OAI21XLTS U1234 ( .A0(n1543), .A1(n1336), .B0(n1024), .Y(n730) );
BUFX3TS U1235 ( .A(n1025), .Y(n1073) );
AOI22X1TS U1236 ( .A0(intDX_EWSW[21]), .A1(n1037), .B0(DMP_EXP_EWSW[21]),
.B1(n1066), .Y(n1026) );
OAI21XLTS U1237 ( .A0(n1532), .A1(n1050), .B0(n1026), .Y(n732) );
AOI22X1TS U1238 ( .A0(intDX_EWSW[20]), .A1(n1037), .B0(DMP_EXP_EWSW[20]),
.B1(n1325), .Y(n1027) );
OAI21XLTS U1239 ( .A0(n1540), .A1(n1050), .B0(n1027), .Y(n733) );
AOI22X1TS U1240 ( .A0(intDX_EWSW[17]), .A1(n1037), .B0(DMP_EXP_EWSW[17]),
.B1(n1066), .Y(n1028) );
OAI21XLTS U1241 ( .A0(n1572), .A1(n1050), .B0(n1028), .Y(n736) );
AOI22X1TS U1242 ( .A0(intDX_EWSW[22]), .A1(n1037), .B0(DMP_EXP_EWSW[22]),
.B1(n1325), .Y(n1029) );
OAI21XLTS U1243 ( .A0(n1492), .A1(n1050), .B0(n1029), .Y(n731) );
AOI22X1TS U1244 ( .A0(intDX_EWSW[18]), .A1(n1037), .B0(DMP_EXP_EWSW[18]),
.B1(n1325), .Y(n1030) );
OAI21XLTS U1245 ( .A0(n1546), .A1(n1050), .B0(n1030), .Y(n735) );
AOI22X1TS U1246 ( .A0(intDX_EWSW[7]), .A1(n1040), .B0(DMP_EXP_EWSW[7]), .B1(
n1325), .Y(n1031) );
OAI21XLTS U1247 ( .A0(n1524), .A1(n1050), .B0(n1031), .Y(n746) );
AOI22X1TS U1248 ( .A0(intDX_EWSW[6]), .A1(n1040), .B0(DMP_EXP_EWSW[6]), .B1(
n1066), .Y(n1032) );
OAI21XLTS U1249 ( .A0(n1523), .A1(n1050), .B0(n1032), .Y(n747) );
AOI22X1TS U1250 ( .A0(intDX_EWSW[19]), .A1(n1037), .B0(DMP_EXP_EWSW[19]),
.B1(n1066), .Y(n1033) );
OAI21XLTS U1251 ( .A0(n1494), .A1(n1050), .B0(n1033), .Y(n734) );
AOI22X1TS U1252 ( .A0(intDX_EWSW[2]), .A1(n1040), .B0(DMP_EXP_EWSW[2]), .B1(
n1066), .Y(n1034) );
OAI21XLTS U1253 ( .A0(n1535), .A1(n1050), .B0(n1034), .Y(n751) );
AOI22X1TS U1254 ( .A0(n907), .A1(n1037), .B0(DMP_EXP_EWSW[0]), .B1(n1325),
.Y(n1035) );
OAI21XLTS U1255 ( .A0(n1491), .A1(n1050), .B0(n1035), .Y(n753) );
AOI22X1TS U1256 ( .A0(intDX_EWSW[4]), .A1(n1040), .B0(DMP_EXP_EWSW[4]), .B1(
n1066), .Y(n1036) );
OAI21XLTS U1257 ( .A0(n1536), .A1(n1050), .B0(n1036), .Y(n749) );
AOI22X1TS U1258 ( .A0(intDX_EWSW[5]), .A1(n893), .B0(DMP_EXP_EWSW[5]), .B1(
n1066), .Y(n1038) );
OAI21XLTS U1259 ( .A0(n1490), .A1(n1336), .B0(n1038), .Y(n748) );
AOI22X1TS U1260 ( .A0(intDX_EWSW[16]), .A1(n893), .B0(DMP_EXP_EWSW[16]),
.B1(n1066), .Y(n1039) );
OAI21XLTS U1261 ( .A0(n1539), .A1(n1050), .B0(n1039), .Y(n737) );
AOI222X1TS U1262 ( .A0(n1073), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1325), .C0(intDY_EWSW[23]), .C1(n1040), .Y(n1041) );
INVX2TS U1263 ( .A(n1041), .Y(n564) );
AOI22X1TS U1264 ( .A0(intDX_EWSW[10]), .A1(n893), .B0(DMP_EXP_EWSW[10]),
.B1(n1325), .Y(n1042) );
OAI21XLTS U1265 ( .A0(n881), .A1(n1050), .B0(n1042), .Y(n743) );
AOI22X1TS U1266 ( .A0(intDX_EWSW[9]), .A1(n893), .B0(DMP_EXP_EWSW[9]), .B1(
n1066), .Y(n1043) );
OAI21XLTS U1267 ( .A0(n1530), .A1(n1336), .B0(n1043), .Y(n744) );
AOI22X1TS U1268 ( .A0(intDX_EWSW[14]), .A1(n893), .B0(DMP_EXP_EWSW[14]),
.B1(n1268), .Y(n1044) );
OAI21XLTS U1269 ( .A0(n1538), .A1(n1050), .B0(n1044), .Y(n739) );
AOI22X1TS U1270 ( .A0(intDX_EWSW[8]), .A1(n893), .B0(DMP_EXP_EWSW[8]), .B1(
n1268), .Y(n1045) );
AOI22X1TS U1271 ( .A0(intDX_EWSW[12]), .A1(n893), .B0(DMP_EXP_EWSW[12]),
.B1(n1268), .Y(n1046) );
OAI21XLTS U1272 ( .A0(n1537), .A1(n1050), .B0(n1046), .Y(n741) );
AOI22X1TS U1273 ( .A0(intDX_EWSW[11]), .A1(n893), .B0(DMP_EXP_EWSW[11]),
.B1(n1066), .Y(n1047) );
OAI21XLTS U1274 ( .A0(n1604), .A1(n1050), .B0(n1047), .Y(n742) );
AOI22X1TS U1275 ( .A0(intDX_EWSW[13]), .A1(n893), .B0(DMP_EXP_EWSW[13]),
.B1(n1325), .Y(n1048) );
OAI21XLTS U1276 ( .A0(n1531), .A1(n1050), .B0(n1048), .Y(n740) );
AOI22X1TS U1277 ( .A0(intDX_EWSW[15]), .A1(n893), .B0(DMP_EXP_EWSW[15]),
.B1(n1325), .Y(n1049) );
OAI21XLTS U1278 ( .A0(n1605), .A1(n1050), .B0(n1049), .Y(n738) );
AOI22X1TS U1279 ( .A0(intDX_EWSW[3]), .A1(n893), .B0(DMP_EXP_EWSW[3]), .B1(
n1325), .Y(n1051) );
OAI21XLTS U1280 ( .A0(n1529), .A1(n1336), .B0(n1051), .Y(n750) );
INVX3TS U1281 ( .A(n893), .Y(n1114) );
AOI22X1TS U1282 ( .A0(intDX_EWSW[8]), .A1(n1073), .B0(DmP_EXP_EWSW[8]), .B1(
n1325), .Y(n1052) );
OAI21XLTS U1283 ( .A0(n1534), .A1(n1114), .B0(n1052), .Y(n594) );
CLKBUFX3TS U1284 ( .A(n1073), .Y(n1077) );
AOI22X1TS U1285 ( .A0(intDX_EWSW[13]), .A1(n1077), .B0(DmP_EXP_EWSW[13]),
.B1(n1268), .Y(n1053) );
OAI21XLTS U1286 ( .A0(n1531), .A1(n1114), .B0(n1053), .Y(n584) );
AOI22X1TS U1287 ( .A0(intDX_EWSW[12]), .A1(n1073), .B0(DmP_EXP_EWSW[12]),
.B1(n1020), .Y(n1054) );
OAI21XLTS U1288 ( .A0(n1537), .A1(n1114), .B0(n1054), .Y(n586) );
AOI22X1TS U1289 ( .A0(DmP_EXP_EWSW[27]), .A1(n1268), .B0(intDX_EWSW[27]),
.B1(n1073), .Y(n1055) );
OAI21XLTS U1290 ( .A0(n1545), .A1(n1114), .B0(n1055), .Y(n560) );
AOI22X1TS U1291 ( .A0(intDX_EWSW[14]), .A1(n1077), .B0(DmP_EXP_EWSW[14]),
.B1(n1020), .Y(n1056) );
OAI21XLTS U1292 ( .A0(n1538), .A1(n1114), .B0(n1056), .Y(n582) );
AOI22X1TS U1293 ( .A0(intDX_EWSW[15]), .A1(n1077), .B0(DmP_EXP_EWSW[15]),
.B1(n1268), .Y(n1057) );
OAI21XLTS U1294 ( .A0(n1605), .A1(n1114), .B0(n1057), .Y(n580) );
AOI22X1TS U1295 ( .A0(intDX_EWSW[4]), .A1(n1025), .B0(DmP_EXP_EWSW[4]), .B1(
n1325), .Y(n1058) );
OAI21XLTS U1296 ( .A0(n1536), .A1(n1114), .B0(n1058), .Y(n602) );
AOI22X1TS U1297 ( .A0(intDX_EWSW[5]), .A1(n1073), .B0(DmP_EXP_EWSW[5]), .B1(
n1325), .Y(n1059) );
OAI21XLTS U1298 ( .A0(n1490), .A1(n1114), .B0(n1059), .Y(n600) );
AOI22X1TS U1299 ( .A0(intDX_EWSW[9]), .A1(n1025), .B0(DmP_EXP_EWSW[9]), .B1(
n1325), .Y(n1060) );
OAI21XLTS U1300 ( .A0(n1530), .A1(n1114), .B0(n1060), .Y(n592) );
AOI22X1TS U1301 ( .A0(intDX_EWSW[7]), .A1(n1025), .B0(DmP_EXP_EWSW[7]), .B1(
n1020), .Y(n1061) );
OAI21XLTS U1302 ( .A0(n1524), .A1(n1114), .B0(n1061), .Y(n596) );
AOI22X1TS U1303 ( .A0(intDX_EWSW[6]), .A1(n1073), .B0(DmP_EXP_EWSW[6]), .B1(
n1268), .Y(n1062) );
OAI21XLTS U1304 ( .A0(n1523), .A1(n1114), .B0(n1062), .Y(n598) );
AOI22X1TS U1305 ( .A0(intDX_EWSW[11]), .A1(n1073), .B0(DmP_EXP_EWSW[11]),
.B1(n1020), .Y(n1063) );
OAI21XLTS U1306 ( .A0(n1604), .A1(n1114), .B0(n1063), .Y(n588) );
AOI22X1TS U1307 ( .A0(intDX_EWSW[10]), .A1(n1025), .B0(DmP_EXP_EWSW[10]),
.B1(n1066), .Y(n1064) );
OAI21XLTS U1308 ( .A0(n881), .A1(n1114), .B0(n1064), .Y(n590) );
INVX4TS U1309 ( .A(n893), .Y(n1334) );
AOI22X1TS U1310 ( .A0(intDX_EWSW[2]), .A1(n1073), .B0(DmP_EXP_EWSW[2]), .B1(
n1268), .Y(n1065) );
OAI21XLTS U1311 ( .A0(n1535), .A1(n1334), .B0(n1065), .Y(n606) );
AOI22X1TS U1312 ( .A0(n907), .A1(n1077), .B0(DmP_EXP_EWSW[0]), .B1(n1066),
.Y(n1067) );
OAI21XLTS U1313 ( .A0(n1491), .A1(n1334), .B0(n1067), .Y(n610) );
AOI22X1TS U1314 ( .A0(intDX_EWSW[17]), .A1(n1077), .B0(DmP_EXP_EWSW[17]),
.B1(n1268), .Y(n1068) );
OAI21XLTS U1315 ( .A0(n1572), .A1(n1334), .B0(n1068), .Y(n576) );
AOI22X1TS U1316 ( .A0(intDX_EWSW[22]), .A1(n1077), .B0(DmP_EXP_EWSW[22]),
.B1(n1268), .Y(n1069) );
OAI21XLTS U1317 ( .A0(n1492), .A1(n1334), .B0(n1069), .Y(n566) );
AOI22X1TS U1318 ( .A0(intDX_EWSW[3]), .A1(n1073), .B0(DmP_EXP_EWSW[3]), .B1(
n1020), .Y(n1070) );
OAI21XLTS U1319 ( .A0(n1529), .A1(n1334), .B0(n1070), .Y(n604) );
AOI22X1TS U1320 ( .A0(intDX_EWSW[16]), .A1(n1077), .B0(DmP_EXP_EWSW[16]),
.B1(n1268), .Y(n1071) );
OAI21XLTS U1321 ( .A0(n1539), .A1(n1334), .B0(n1071), .Y(n578) );
AOI22X1TS U1322 ( .A0(intDX_EWSW[19]), .A1(n1077), .B0(DmP_EXP_EWSW[19]),
.B1(n1268), .Y(n1072) );
OAI21XLTS U1323 ( .A0(n1494), .A1(n1334), .B0(n1072), .Y(n572) );
AOI22X1TS U1324 ( .A0(intDX_EWSW[1]), .A1(n1073), .B0(DmP_EXP_EWSW[1]), .B1(
n1066), .Y(n1074) );
OAI21XLTS U1325 ( .A0(n1533), .A1(n1334), .B0(n1074), .Y(n608) );
AOI22X1TS U1326 ( .A0(intDX_EWSW[18]), .A1(n1025), .B0(DmP_EXP_EWSW[18]),
.B1(n1268), .Y(n1075) );
OAI21XLTS U1327 ( .A0(n1546), .A1(n1334), .B0(n1075), .Y(n574) );
AOI22X1TS U1328 ( .A0(intDX_EWSW[21]), .A1(n1077), .B0(DmP_EXP_EWSW[21]),
.B1(n1268), .Y(n1076) );
OAI21XLTS U1329 ( .A0(n1532), .A1(n1334), .B0(n1076), .Y(n568) );
AOI22X1TS U1330 ( .A0(intDX_EWSW[20]), .A1(n1077), .B0(DmP_EXP_EWSW[20]),
.B1(n1268), .Y(n1078) );
OAI21XLTS U1331 ( .A0(n1540), .A1(n1334), .B0(n1078), .Y(n570) );
OAI22X1TS U1332 ( .A0(n1533), .A1(intDX_EWSW[1]), .B0(n1606), .B1(
intDX_EWSW[25]), .Y(n1079) );
AOI221X1TS U1333 ( .A0(n1533), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1606), .C0(n1079), .Y(n1085) );
OAI22X1TS U1334 ( .A0(n1542), .A1(intDX_EWSW[28]), .B0(n1493), .B1(
intDX_EWSW[29]), .Y(n1081) );
AOI221X1TS U1335 ( .A0(n1542), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1493), .C0(n1081), .Y(n1083) );
AOI2BB2XLTS U1336 ( .B0(intDX_EWSW[7]), .B1(n1524), .A0N(n1524), .A1N(
intDX_EWSW[7]), .Y(n1082) );
NAND4XLTS U1337 ( .A(n1085), .B(n1084), .C(n1083), .D(n1082), .Y(n1113) );
OAI22X1TS U1338 ( .A0(n1544), .A1(intDX_EWSW[30]), .B0(n1572), .B1(
intDX_EWSW[17]), .Y(n1086) );
OAI22X1TS U1339 ( .A0(n1540), .A1(intDX_EWSW[20]), .B0(n1532), .B1(
intDX_EWSW[21]), .Y(n1088) );
OAI22X1TS U1340 ( .A0(n1492), .A1(intDX_EWSW[22]), .B0(n1543), .B1(
intDX_EWSW[23]), .Y(n1089) );
NAND4XLTS U1341 ( .A(n1093), .B(n1092), .C(n1091), .D(n1090), .Y(n1112) );
OAI22X1TS U1342 ( .A0(n1480), .A1(intDX_EWSW[24]), .B0(n1530), .B1(
intDX_EWSW[9]), .Y(n1094) );
AOI221X1TS U1343 ( .A0(n1480), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1530), .C0(n1094), .Y(n1101) );
OAI22X1TS U1344 ( .A0(n1537), .A1(intDX_EWSW[12]), .B0(n1531), .B1(
intDX_EWSW[13]), .Y(n1096) );
OAI22X1TS U1345 ( .A0(n1538), .A1(intDX_EWSW[14]), .B0(n1605), .B1(
intDX_EWSW[15]), .Y(n1097) );
NAND4XLTS U1346 ( .A(n1101), .B(n1100), .C(n1099), .D(n1098), .Y(n1111) );
OAI22X1TS U1347 ( .A0(n1539), .A1(intDX_EWSW[16]), .B0(n1491), .B1(n907),
.Y(n1102) );
AOI221X1TS U1348 ( .A0(n1539), .A1(intDX_EWSW[16]), .B0(n907), .B1(n1491),
.C0(n1102), .Y(n1109) );
OAI22X1TS U1349 ( .A0(n1535), .A1(intDX_EWSW[2]), .B0(n1529), .B1(
intDX_EWSW[3]), .Y(n1103) );
OAI22X1TS U1350 ( .A0(n1536), .A1(intDX_EWSW[4]), .B0(n1490), .B1(
intDX_EWSW[5]), .Y(n1104) );
AOI221X1TS U1351 ( .A0(n1536), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1490), .C0(n1104), .Y(n1107) );
OAI22X1TS U1352 ( .A0(n1534), .A1(intDX_EWSW[8]), .B0(n1523), .B1(
intDX_EWSW[6]), .Y(n1105) );
AOI221X1TS U1353 ( .A0(n1534), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1523), .C0(n1105), .Y(n1106) );
NAND4XLTS U1354 ( .A(n1109), .B(n1108), .C(n1107), .D(n1106), .Y(n1110) );
NOR4X1TS U1355 ( .A(n1113), .B(n1112), .C(n1111), .D(n1110), .Y(n1327) );
CLKXOR2X2TS U1356 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1324) );
INVX2TS U1357 ( .A(n1324), .Y(n1117) );
AOI22X1TS U1358 ( .A0(intDX_EWSW[31]), .A1(n1115), .B0(SIGN_FLAG_EXP), .B1(
n878), .Y(n1116) );
NOR2XLTS U1359 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1119)
);
NAND4X1TS U1360 ( .A(n1484), .B(n1473), .C(n1472), .D(n1501), .Y(n1257) );
NOR2BX1TS U1361 ( .AN(n1134), .B(Raw_mant_NRM_SWR[18]), .Y(n1245) );
NOR2BX1TS U1362 ( .AN(n1245), .B(n1246), .Y(n1131) );
NAND2X1TS U1363 ( .A(n1131), .B(n1486), .Y(n1247) );
NAND2X1TS U1364 ( .A(n1143), .B(n1475), .Y(n1136) );
NAND2X1TS U1365 ( .A(n1252), .B(n1476), .Y(n1118) );
NOR2X1TS U1366 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1120)
);
NOR3X1TS U1367 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1118),
.Y(n1121) );
NAND2X1TS U1368 ( .A(n1121), .B(n1477), .Y(n1128) );
OAI22X1TS U1369 ( .A0(n1119), .A1(n1118), .B0(n1120), .B1(n1128), .Y(n1126)
);
NOR2X1TS U1370 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1123)
);
NAND2X1TS U1371 ( .A(n1253), .B(n1120), .Y(n1124) );
OAI21X1TS U1372 ( .A0(n1123), .A1(n1124), .B0(n1122), .Y(n1147) );
INVX2TS U1373 ( .A(n1124), .Y(n1254) );
OAI31X1TS U1374 ( .A0(n1126), .A1(n1147), .A2(n1125), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1244) );
NAND3XLTS U1375 ( .A(n873), .B(Shift_amount_SHT1_EWR[4]), .C(n874), .Y(n1127) );
INVX2TS U1376 ( .A(n1128), .Y(n1138) );
AOI22X1TS U1377 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1134), .B0(n1252), .B1(
Raw_mant_NRM_SWR[10]), .Y(n1144) );
OAI32X1TS U1378 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1478), .B0(n1504), .B1(Raw_mant_NRM_SWR[3]), .Y(n1129) );
NAND2X1TS U1379 ( .A(Raw_mant_NRM_SWR[12]), .B(n1143), .Y(n1249) );
NAND2X1TS U1380 ( .A(Raw_mant_NRM_SWR[14]), .B(n1131), .Y(n1149) );
AOI32X1TS U1381 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1472), .A2(n1506), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1472), .Y(n1132) );
AOI32X1TS U1382 ( .A0(n1473), .A1(n1149), .A2(n1132), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1149), .Y(n1133) );
OAI31X1TS U1383 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1136), .A2(n1479), .B0(
n1135), .Y(n1137) );
NAND2X2TS U1384 ( .A(Shift_reg_FLAGS_7[1]), .B(n1152), .Y(n1290) );
NOR2BX1TS U1385 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1188) );
CLKBUFX2TS U1386 ( .A(n1188), .Y(n1213) );
BUFX4TS U1387 ( .A(n1213), .Y(n1287) );
AOI22X1TS U1388 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n902), .B0(n1287), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1158) );
NOR2XLTS U1389 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1142) );
NOR2X1TS U1390 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1140) );
AOI32X1TS U1391 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1140), .A2(n1139), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1140), .Y(n1141) );
AOI211X1TS U1392 ( .A0(n1142), .A1(n1141), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1148) );
OAI31X1TS U1393 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1475), .A2(n1145), .B0(
n1144), .Y(n1146) );
NOR2X1TS U1394 ( .A(n1169), .B(n874), .Y(n1261) );
AOI21X1TS U1395 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n874), .B0(n1261), .Y(
n1151) );
INVX2TS U1396 ( .A(n1304), .Y(n1219) );
BUFX4TS U1397 ( .A(n1219), .Y(n1301) );
NOR2X2TS U1398 ( .A(n1301), .B(n1151), .Y(n1298) );
NOR2X4TS U1399 ( .A(n1152), .B(n874), .Y(n1288) );
AOI22X1TS U1400 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1288), .B0(n1213), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1154) );
AOI22X1TS U1401 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n901), .B0(n905), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1153) );
NAND2X1TS U1402 ( .A(n1154), .B(n1153), .Y(n1168) );
AOI22X1TS U1403 ( .A0(n1219), .A1(Data_array_SWR[1]), .B0(n1298), .B1(n1168),
.Y(n1157) );
INVX2TS U1404 ( .A(n1155), .Y(n1296) );
NAND2X1TS U1405 ( .A(Raw_mant_NRM_SWR[23]), .B(n1296), .Y(n1156) );
AOI22X1TS U1406 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1288), .B0(n1213), .B1(
n899), .Y(n1160) );
AOI22X1TS U1407 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n901), .B0(n905), .B1(n895),
.Y(n1159) );
NAND2X1TS U1408 ( .A(n1160), .B(n1159), .Y(n1174) );
AOI22X1TS U1409 ( .A0(n1219), .A1(Data_array_SWR[4]), .B0(n1298), .B1(n1174),
.Y(n1162) );
NAND2X1TS U1410 ( .A(Raw_mant_NRM_SWR[20]), .B(n1296), .Y(n1161) );
AOI22X1TS U1411 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1288), .B0(n1213), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1164) );
AOI22X1TS U1412 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n901), .B0(n905), .B1(n899),
.Y(n1163) );
NAND2X1TS U1413 ( .A(n1164), .B(n1163), .Y(n1177) );
AOI22X1TS U1414 ( .A0(n1301), .A1(Data_array_SWR[5]), .B0(n1298), .B1(n1177),
.Y(n1166) );
NAND2X1TS U1415 ( .A(Raw_mant_NRM_SWR[19]), .B(n1296), .Y(n1165) );
AOI22X1TS U1416 ( .A0(n1219), .A1(Data_array_SWR[3]), .B0(n903), .B1(n1168),
.Y(n1172) );
INVX2TS U1417 ( .A(n1288), .Y(n1211) );
NAND2X1TS U1418 ( .A(Raw_mant_NRM_SWR[19]), .B(n1170), .Y(n1171) );
AOI22X1TS U1419 ( .A0(n1219), .A1(Data_array_SWR[6]), .B0(n903), .B1(n1174),
.Y(n1176) );
NAND2X1TS U1420 ( .A(Raw_mant_NRM_SWR[16]), .B(n1170), .Y(n1175) );
AOI22X1TS U1421 ( .A0(n1219), .A1(Data_array_SWR[7]), .B0(n903), .B1(n1177),
.Y(n1179) );
NAND2X1TS U1422 ( .A(Raw_mant_NRM_SWR[15]), .B(n1170), .Y(n1178) );
AOI22X1TS U1423 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1288), .B0(n1287), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1181) );
AOI22X1TS U1424 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n901), .B0(n905), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1180) );
NAND2X1TS U1425 ( .A(n1181), .B(n1180), .Y(n1297) );
AOI22X1TS U1426 ( .A0(n1301), .A1(Data_array_SWR[2]), .B0(n903), .B1(n1297),
.Y(n1183) );
NAND2X1TS U1427 ( .A(Raw_mant_NRM_SWR[20]), .B(n1170), .Y(n1182) );
AOI22X1TS U1428 ( .A0(n1219), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1170), .Y(n1186) );
AOI22X1TS U1429 ( .A0(n905), .A1(DmP_mant_SHT1_SW[21]), .B0(n1188), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1189) );
AOI21X1TS U1430 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n902), .B0(n1190), .Y(n1283)
);
OAI22X1TS U1431 ( .A0(n1227), .A1(n904), .B0(n1551), .B1(n1155), .Y(n1191)
);
AOI21X1TS U1432 ( .A0(n1301), .A1(Data_array_SWR[21]), .B0(n1191), .Y(n1192)
);
AOI22X1TS U1433 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1288), .B0(n1287), .B1(n896), .Y(n1193) );
AOI21X1TS U1434 ( .A0(n906), .A1(DmP_mant_SHT1_SW[18]), .B0(n1194), .Y(n1205) );
OAI22X1TS U1435 ( .A0(n1199), .A1(n904), .B0(n1482), .B1(n1155), .Y(n1195)
);
AOI21X1TS U1436 ( .A0(n1301), .A1(Data_array_SWR[18]), .B0(n1195), .Y(n1196)
);
AOI22X1TS U1437 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1288), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1213), .Y(n1197) );
AOI21X1TS U1438 ( .A0(DmP_mant_SHT1_SW[14]), .A1(n906), .B0(n1198), .Y(n1286) );
INVX2TS U1439 ( .A(n1170), .Y(n1202) );
OAI22X1TS U1440 ( .A0(n1199), .A1(n1167), .B0(n1482), .B1(n1202), .Y(n1200)
);
AOI21X1TS U1441 ( .A0(n1301), .A1(Data_array_SWR[16]), .B0(n1200), .Y(n1201)
);
OAI22X1TS U1442 ( .A0(n1214), .A1(n1167), .B0(n1504), .B1(n1202), .Y(n1203)
);
AOI21X1TS U1443 ( .A0(n1301), .A1(Data_array_SWR[20]), .B0(n1203), .Y(n1204)
);
AOI22X1TS U1444 ( .A0(n905), .A1(DmP_mant_SHT1_SW[8]), .B0(n1287), .B1(n897),
.Y(n1206) );
AOI21X1TS U1445 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n902), .B0(n1207), .Y(n1294) );
OAI22X1TS U1446 ( .A0(n1208), .A1(n904), .B0(n1474), .B1(n1155), .Y(n1209)
);
AOI21X1TS U1447 ( .A0(n1301), .A1(Data_array_SWR[8]), .B0(n1209), .Y(n1210)
);
OAI22X1TS U1448 ( .A0(n1558), .A1(n1290), .B0(n1478), .B1(n1211), .Y(n1212)
);
OAI22X1TS U1449 ( .A0(n1281), .A1(n1167), .B0(n1214), .B1(n904), .Y(n1215)
);
AOI21X1TS U1450 ( .A0(n1301), .A1(Data_array_SWR[22]), .B0(n1215), .Y(n1216)
);
AOI22X1TS U1451 ( .A0(n1301), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1170), .Y(n1218) );
OA22X1TS U1452 ( .A0(n1481), .A1(n1155), .B0(n1235), .B1(n1167), .Y(n1217)
);
AOI22X1TS U1453 ( .A0(n1219), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1170), .Y(n1221) );
OA22X1TS U1454 ( .A0(n1497), .A1(n1155), .B0(n1226), .B1(n1167), .Y(n1220)
);
AOI22X1TS U1455 ( .A0(n1301), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1170), .Y(n1225) );
OA22X1TS U1456 ( .A0(n1475), .A1(n1155), .B0(n1223), .B1(n1167), .Y(n1224)
);
AOI22X1TS U1457 ( .A0(n1301), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1170), .Y(n1229) );
OA22X1TS U1458 ( .A0(n1512), .A1(n1155), .B0(n1227), .B1(n1167), .Y(n1228)
);
AOI22X1TS U1459 ( .A0(n1301), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1170), .Y(n1234) );
OA22X1TS U1460 ( .A0(n1477), .A1(n1155), .B0(n1231), .B1(n1167), .Y(n1233)
);
INVX2TS U1461 ( .A(n1236), .Y(n1364) );
NOR2XLTS U1462 ( .A(n1364), .B(SIGN_FLAG_SHT1SHT2), .Y(n1237) );
OAI2BB2XLTS U1463 ( .B0(n1237), .B1(n1363), .A0N(n1423), .A1N(
final_result_ieee[31]), .Y(n543) );
AOI22X1TS U1464 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n1359), .B0(n1358), .B1(n918), .Y(n1347) );
NAND2X1TS U1465 ( .A(n1347), .B(DMP_SFG[0]), .Y(n1349) );
INVX2TS U1466 ( .A(n1349), .Y(n1238) );
AOI22X1TS U1467 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n1358), .B0(n1359), .B1(n922), .Y(intadd_69_B_2_) );
BUFX3TS U1468 ( .A(n1358), .Y(n1355) );
AOI21X1TS U1469 ( .A0(intadd_69_A_3_), .A1(intadd_69_B_3_), .B0(
intadd_69_B_2_), .Y(n1239) );
AOI2BB2X1TS U1470 ( .B0(DMP_SFG[4]), .B1(n1239), .A0N(intadd_69_A_3_), .A1N(
intadd_69_B_3_), .Y(n1240) );
AOI222X1TS U1471 ( .A0(n1240), .A1(intadd_69_A_4_), .B0(n1240), .B1(
intadd_69_B_4_), .C0(intadd_69_A_4_), .C1(intadd_69_B_4_), .Y(n1241)
);
INVX2TS U1472 ( .A(n1242), .Y(n1243) );
NAND2X1TS U1473 ( .A(n1508), .B(n1243), .Y(DP_OP_15J60_123_4652_n8) );
MX2X1TS U1474 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n611) );
MX2X1TS U1475 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n616) );
MX2X1TS U1476 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n621) );
MX2X1TS U1477 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n626) );
MX2X1TS U1478 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n631) );
MX2X1TS U1479 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n636) );
MX2X1TS U1480 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n641) );
MX2X1TS U1481 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n646) );
OAI2BB1X1TS U1482 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n874), .B0(n1244), .Y(
n512) );
OAI32X1TS U1483 ( .A0(n874), .A1(Raw_mant_NRM_SWR[14]), .A2(n1246), .B0(
n1245), .B1(n874), .Y(n1250) );
AO21XLTS U1484 ( .A0(n1475), .A1(n1497), .B0(n1247), .Y(n1255) );
AOI21X1TS U1485 ( .A0(n1252), .A1(Raw_mant_NRM_SWR[10]), .B0(n1251), .Y(
n1306) );
AOI2BB1XLTS U1486 ( .A0N(Shift_reg_FLAGS_7[1]), .A1N(LZD_output_NRM2_EW[3]),
.B0(n1306), .Y(n516) );
AOI22X1TS U1487 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1254), .B0(n1253), .B1(
Raw_mant_NRM_SWR[5]), .Y(n1256) );
OAI21X1TS U1488 ( .A0(n1260), .A1(n1259), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1302) );
OAI2BB1X1TS U1489 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n874), .B0(n1302), .Y(
n514) );
AO21XLTS U1490 ( .A0(LZD_output_NRM2_EW[1]), .A1(n874), .B0(n1261), .Y(n513)
);
AO21XLTS U1491 ( .A0(LZD_output_NRM2_EW[0]), .A1(n874), .B0(n1288), .Y(n515)
);
OA22X1TS U1492 ( .A0(n1263), .A1(n1262), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n755) );
OA21XLTS U1493 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1363),
.Y(n558) );
INVX2TS U1494 ( .A(n1267), .Y(n1265) );
AOI22X1TS U1495 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1265), .B1(n1489), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1496 ( .A(n1265), .B(n1264), .Y(n871) );
NOR2XLTS U1497 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1266) );
AOI32X4TS U1498 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1266), .B1(n1525), .Y(n1270)
);
INVX2TS U1499 ( .A(n1270), .Y(n1269) );
AOI22X1TS U1500 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1267), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1489), .Y(n1271) );
AO22XLTS U1501 ( .A0(n1269), .A1(Shift_reg_FLAGS_7_6), .B0(n1270), .B1(n1271), .Y(n869) );
AOI22X1TS U1502 ( .A0(n1270), .A1(n1268), .B0(n1332), .B1(n1269), .Y(n868)
);
AOI22X1TS U1503 ( .A0(n1270), .A1(n1332), .B0(n1570), .B1(n1269), .Y(n867)
);
INVX4TS U1504 ( .A(n1602), .Y(n1354) );
AOI22X1TS U1505 ( .A0(n1270), .A1(n1602), .B0(n874), .B1(n1269), .Y(n864) );
AOI22X1TS U1506 ( .A0(n1270), .A1(n874), .B0(n1423), .B1(n1269), .Y(n863) );
BUFX4TS U1507 ( .A(n1275), .Y(n1276) );
BUFX3TS U1508 ( .A(n1275), .Y(n1277) );
BUFX3TS U1509 ( .A(n1275), .Y(n1274) );
AO22XLTS U1510 ( .A0(n1274), .A1(Data_X[2]), .B0(n875), .B1(intDX_EWSW[2]),
.Y(n860) );
BUFX3TS U1511 ( .A(n1275), .Y(n1280) );
AO22XLTS U1512 ( .A0(n1280), .A1(Data_X[3]), .B0(n875), .B1(intDX_EWSW[3]),
.Y(n859) );
AO22XLTS U1513 ( .A0(n1277), .A1(Data_X[4]), .B0(n1279), .B1(intDX_EWSW[4]),
.Y(n858) );
AO22XLTS U1514 ( .A0(n1276), .A1(Data_X[5]), .B0(n875), .B1(intDX_EWSW[5]),
.Y(n857) );
AO22XLTS U1515 ( .A0(n1276), .A1(Data_X[6]), .B0(n875), .B1(intDX_EWSW[6]),
.Y(n856) );
AO22XLTS U1516 ( .A0(n1275), .A1(Data_X[7]), .B0(n1279), .B1(intDX_EWSW[7]),
.Y(n855) );
AO22XLTS U1517 ( .A0(n1280), .A1(Data_X[8]), .B0(n875), .B1(intDX_EWSW[8]),
.Y(n854) );
AO22XLTS U1518 ( .A0(n1280), .A1(Data_X[9]), .B0(n875), .B1(intDX_EWSW[9]),
.Y(n853) );
AO22XLTS U1519 ( .A0(n1280), .A1(Data_X[11]), .B0(n1279), .B1(intDX_EWSW[11]), .Y(n851) );
AO22XLTS U1520 ( .A0(n1276), .A1(Data_X[12]), .B0(n875), .B1(intDX_EWSW[12]),
.Y(n850) );
AO22XLTS U1521 ( .A0(n1277), .A1(Data_X[13]), .B0(n875), .B1(intDX_EWSW[13]),
.Y(n849) );
AO22XLTS U1522 ( .A0(n1275), .A1(Data_X[14]), .B0(n1279), .B1(intDX_EWSW[14]), .Y(n848) );
INVX2TS U1523 ( .A(n1277), .Y(n1279) );
AO22XLTS U1524 ( .A0(n1276), .A1(Data_X[15]), .B0(n1279), .B1(intDX_EWSW[15]), .Y(n847) );
AO22XLTS U1525 ( .A0(n1274), .A1(Data_X[16]), .B0(n875), .B1(intDX_EWSW[16]),
.Y(n846) );
AO22XLTS U1526 ( .A0(n1276), .A1(Data_X[17]), .B0(n875), .B1(intDX_EWSW[17]),
.Y(n845) );
AO22XLTS U1527 ( .A0(n1275), .A1(Data_X[20]), .B0(n1279), .B1(intDX_EWSW[20]), .Y(n842) );
AO22XLTS U1528 ( .A0(n1277), .A1(Data_X[21]), .B0(n875), .B1(intDX_EWSW[21]),
.Y(n841) );
AO22XLTS U1529 ( .A0(n1277), .A1(Data_X[22]), .B0(n875), .B1(intDX_EWSW[22]),
.Y(n840) );
AO22XLTS U1530 ( .A0(n1274), .A1(Data_X[23]), .B0(n1279), .B1(intDX_EWSW[23]), .Y(n839) );
INVX2TS U1531 ( .A(n1275), .Y(n1272) );
AO22XLTS U1532 ( .A0(n1272), .A1(intDX_EWSW[24]), .B0(n1275), .B1(Data_X[24]), .Y(n838) );
AO22XLTS U1533 ( .A0(n1272), .A1(intDX_EWSW[25]), .B0(n1280), .B1(Data_X[25]), .Y(n837) );
AO22XLTS U1534 ( .A0(n1272), .A1(intDX_EWSW[26]), .B0(n1275), .B1(Data_X[26]), .Y(n836) );
AO22XLTS U1535 ( .A0(n1280), .A1(Data_X[28]), .B0(n875), .B1(intDX_EWSW[28]),
.Y(n834) );
AO22XLTS U1536 ( .A0(n1276), .A1(add_subt), .B0(n1272), .B1(intAS), .Y(n830)
);
AO22XLTS U1537 ( .A0(n1272), .A1(intDY_EWSW[0]), .B0(n1280), .B1(Data_Y[0]),
.Y(n828) );
AO22XLTS U1538 ( .A0(n1272), .A1(intDY_EWSW[1]), .B0(n1274), .B1(Data_Y[1]),
.Y(n827) );
AO22XLTS U1539 ( .A0(n1272), .A1(intDY_EWSW[2]), .B0(n1274), .B1(Data_Y[2]),
.Y(n826) );
AO22XLTS U1540 ( .A0(n1272), .A1(intDY_EWSW[3]), .B0(n1274), .B1(Data_Y[3]),
.Y(n825) );
AO22XLTS U1541 ( .A0(n1273), .A1(intDY_EWSW[4]), .B0(n1274), .B1(Data_Y[4]),
.Y(n824) );
AO22XLTS U1542 ( .A0(n1278), .A1(intDY_EWSW[5]), .B0(n1274), .B1(Data_Y[5]),
.Y(n823) );
INVX2TS U1543 ( .A(n1275), .Y(n1273) );
AO22XLTS U1544 ( .A0(n1278), .A1(intDY_EWSW[6]), .B0(n1274), .B1(Data_Y[6]),
.Y(n822) );
AO22XLTS U1545 ( .A0(n1273), .A1(intDY_EWSW[7]), .B0(n1274), .B1(Data_Y[7]),
.Y(n821) );
AO22XLTS U1546 ( .A0(n1278), .A1(intDY_EWSW[8]), .B0(n1274), .B1(Data_Y[8]),
.Y(n820) );
AO22XLTS U1547 ( .A0(n1273), .A1(intDY_EWSW[9]), .B0(n1275), .B1(Data_Y[9]),
.Y(n819) );
AO22XLTS U1548 ( .A0(n1278), .A1(intDY_EWSW[10]), .B0(n1276), .B1(Data_Y[10]), .Y(n818) );
AO22XLTS U1549 ( .A0(n1273), .A1(intDY_EWSW[11]), .B0(n1277), .B1(Data_Y[11]), .Y(n817) );
AO22XLTS U1550 ( .A0(n1278), .A1(intDY_EWSW[12]), .B0(n1276), .B1(Data_Y[12]), .Y(n816) );
AO22XLTS U1551 ( .A0(n1278), .A1(intDY_EWSW[13]), .B0(n1276), .B1(Data_Y[13]), .Y(n815) );
AO22XLTS U1552 ( .A0(n1273), .A1(intDY_EWSW[14]), .B0(n1276), .B1(Data_Y[14]), .Y(n814) );
AO22XLTS U1553 ( .A0(n1278), .A1(intDY_EWSW[15]), .B0(n1276), .B1(Data_Y[15]), .Y(n813) );
AO22XLTS U1554 ( .A0(n1278), .A1(intDY_EWSW[16]), .B0(n1276), .B1(Data_Y[16]), .Y(n812) );
AO22XLTS U1555 ( .A0(n1273), .A1(intDY_EWSW[17]), .B0(n1276), .B1(Data_Y[17]), .Y(n811) );
AO22XLTS U1556 ( .A0(n1278), .A1(intDY_EWSW[18]), .B0(n1276), .B1(Data_Y[18]), .Y(n810) );
AO22XLTS U1557 ( .A0(n1278), .A1(intDY_EWSW[19]), .B0(n1276), .B1(Data_Y[19]), .Y(n809) );
AO22XLTS U1558 ( .A0(n1273), .A1(intDY_EWSW[20]), .B0(n1276), .B1(Data_Y[20]), .Y(n808) );
AO22XLTS U1559 ( .A0(n1278), .A1(intDY_EWSW[21]), .B0(n1276), .B1(Data_Y[21]), .Y(n807) );
AO22XLTS U1560 ( .A0(n1278), .A1(intDY_EWSW[22]), .B0(n1280), .B1(Data_Y[22]), .Y(n806) );
AO22XLTS U1561 ( .A0(n1273), .A1(intDY_EWSW[23]), .B0(n1280), .B1(Data_Y[23]), .Y(n805) );
AO22XLTS U1562 ( .A0(n1273), .A1(intDY_EWSW[24]), .B0(n1280), .B1(Data_Y[24]), .Y(n804) );
AO22XLTS U1563 ( .A0(n1278), .A1(intDY_EWSW[25]), .B0(n1275), .B1(Data_Y[25]), .Y(n803) );
AO22XLTS U1564 ( .A0(n1278), .A1(intDY_EWSW[26]), .B0(n1274), .B1(Data_Y[26]), .Y(n802) );
AO22XLTS U1565 ( .A0(n1278), .A1(intDY_EWSW[27]), .B0(n1275), .B1(Data_Y[27]), .Y(n801) );
AO22XLTS U1566 ( .A0(n1278), .A1(intDY_EWSW[28]), .B0(n1275), .B1(Data_Y[28]), .Y(n800) );
AO22XLTS U1567 ( .A0(n1273), .A1(intDY_EWSW[29]), .B0(n1276), .B1(Data_Y[29]), .Y(n799) );
AO22XLTS U1568 ( .A0(n1278), .A1(intDY_EWSW[30]), .B0(n1277), .B1(Data_Y[30]), .Y(n798) );
AOI21X1TS U1569 ( .A0(n902), .A1(Raw_mant_NRM_SWR[0]), .B0(n906), .Y(n1282)
);
OAI2BB2XLTS U1570 ( .B0(n1282), .B1(n1150), .A0N(n1301), .A1N(
Data_array_SWR[25]), .Y(n796) );
OAI2BB2XLTS U1571 ( .B0(n1281), .B1(n1150), .A0N(n1301), .A1N(
Data_array_SWR[24]), .Y(n795) );
OAI222X1TS U1572 ( .A0(n1559), .A1(n1304), .B0(n1150), .B1(n1283), .C0(n1167), .C1(n1282), .Y(n794) );
AOI22X1TS U1573 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1288), .B0(n1287), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1284) );
AOI21X1TS U1574 ( .A0(n906), .A1(DmP_mant_SHT1_SW[12]), .B0(n1285), .Y(n1292) );
OAI222X1TS U1575 ( .A0(n1304), .A1(n1561), .B0(n1150), .B1(n1292), .C0(n1167), .C1(n1286), .Y(n785) );
AOI22X1TS U1576 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1288), .B0(n1287), .B1(
n898), .Y(n1289) );
AOI21X1TS U1577 ( .A0(n906), .A1(DmP_mant_SHT1_SW[10]), .B0(n1291), .Y(n1293) );
OAI222X1TS U1578 ( .A0(n1560), .A1(n1304), .B0(n1150), .B1(n1293), .C0(n1167), .C1(n1292), .Y(n783) );
OAI222X1TS U1579 ( .A0(n1567), .A1(n1304), .B0(n1150), .B1(n1294), .C0(n1167), .C1(n1293), .Y(n781) );
AOI22X1TS U1580 ( .A0(n1301), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1296), .Y(n1300) );
AOI22X1TS U1581 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n902), .B0(n1298), .B1(
n1297), .Y(n1299) );
NAND2X1TS U1582 ( .A(n1300), .B(n1299), .Y(n771) );
NAND2X1TS U1583 ( .A(n1303), .B(n1302), .Y(n770) );
AOI21X1TS U1584 ( .A0(n873), .A1(Shift_amount_SHT1_EWR[3]), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1305) );
OAI22X1TS U1585 ( .A0(n1306), .A1(n1305), .B0(n1304), .B1(n1505), .Y(n769)
);
INVX4TS U1586 ( .A(n1332), .Y(n1339) );
AOI21X1TS U1587 ( .A0(DMP_EXP_EWSW[23]), .A1(n908), .B0(n1311), .Y(n1307) );
INVX4TS U1588 ( .A(n1332), .Y(n1341) );
AOI2BB2XLTS U1589 ( .B0(n1339), .B1(n1307), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1341), .Y(n766) );
NOR2X1TS U1590 ( .A(n1495), .B(DMP_EXP_EWSW[24]), .Y(n1310) );
AOI21X1TS U1591 ( .A0(DMP_EXP_EWSW[24]), .A1(n1495), .B0(n1310), .Y(n1308)
);
XNOR2X1TS U1592 ( .A(n1311), .B(n1308), .Y(n1309) );
AO22XLTS U1593 ( .A0(n1341), .A1(n1309), .B0(n1332), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n765) );
INVX4TS U1594 ( .A(n1332), .Y(n1329) );
OAI22X1TS U1595 ( .A0(n1311), .A1(n1310), .B0(DmP_EXP_EWSW[24]), .B1(n1496),
.Y(n1314) );
NAND2X1TS U1596 ( .A(DmP_EXP_EWSW[25]), .B(n1550), .Y(n1315) );
OAI21XLTS U1597 ( .A0(DmP_EXP_EWSW[25]), .A1(n1550), .B0(n1315), .Y(n1312)
);
XNOR2X1TS U1598 ( .A(n1314), .B(n1312), .Y(n1313) );
AO22XLTS U1599 ( .A0(n1329), .A1(n1313), .B0(n1568), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n764) );
AOI22X1TS U1600 ( .A0(DMP_EXP_EWSW[25]), .A1(n1563), .B0(n1315), .B1(n1314),
.Y(n1318) );
NOR2X1TS U1601 ( .A(n1498), .B(DMP_EXP_EWSW[26]), .Y(n1319) );
AOI21X1TS U1602 ( .A0(DMP_EXP_EWSW[26]), .A1(n1498), .B0(n1319), .Y(n1316)
);
XNOR2X1TS U1603 ( .A(n1318), .B(n1316), .Y(n1317) );
AO22XLTS U1604 ( .A0(n1341), .A1(n1317), .B0(n1568), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n763) );
OAI22X1TS U1605 ( .A0(n1319), .A1(n1318), .B0(DmP_EXP_EWSW[26]), .B1(n1500),
.Y(n1321) );
XNOR2X1TS U1606 ( .A(DmP_EXP_EWSW[27]), .B(n900), .Y(n1320) );
XOR2XLTS U1607 ( .A(n1321), .B(n1320), .Y(n1322) );
BUFX3TS U1608 ( .A(n1568), .Y(n1331) );
AO22XLTS U1609 ( .A0(n1329), .A1(n1322), .B0(n1331), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n762) );
OAI222X1TS U1610 ( .A0(n1334), .A1(n1562), .B0(n1496), .B1(
Shift_reg_FLAGS_7_6), .C0(n1480), .C1(n1336), .Y(n729) );
OAI222X1TS U1611 ( .A0(n1334), .A1(n1499), .B0(n1550), .B1(
Shift_reg_FLAGS_7_6), .C0(n1606), .C1(n1336), .Y(n728) );
OAI222X1TS U1612 ( .A0(n1334), .A1(n1566), .B0(n1500), .B1(
Shift_reg_FLAGS_7_6), .C0(n1541), .C1(n1336), .Y(n727) );
OAI21XLTS U1613 ( .A0(n1324), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1323) );
AOI21X1TS U1614 ( .A0(n1324), .A1(intDX_EWSW[31]), .B0(n1323), .Y(n1326) );
AO21XLTS U1615 ( .A0(OP_FLAG_EXP), .A1(n1325), .B0(n1326), .Y(n722) );
AO22XLTS U1616 ( .A0(n1327), .A1(n1326), .B0(ZERO_FLAG_EXP), .B1(n1325), .Y(
n721) );
AO22XLTS U1617 ( .A0(n1329), .A1(DMP_EXP_EWSW[0]), .B0(n1331), .B1(
DMP_SHT1_EWSW[0]), .Y(n719) );
AO22XLTS U1618 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1570), .B1(
DMP_SHT2_EWSW[0]), .Y(n718) );
BUFX4TS U1619 ( .A(n1328), .Y(n1456) );
AO22XLTS U1620 ( .A0(n1341), .A1(DMP_EXP_EWSW[1]), .B0(n1331), .B1(
DMP_SHT1_EWSW[1]), .Y(n716) );
AO22XLTS U1621 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1570), .B1(
DMP_SHT2_EWSW[1]), .Y(n715) );
AO22XLTS U1622 ( .A0(n1329), .A1(DMP_EXP_EWSW[2]), .B0(n1331), .B1(
DMP_SHT1_EWSW[2]), .Y(n713) );
AO22XLTS U1623 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1570), .B1(
DMP_SHT2_EWSW[2]), .Y(n712) );
AO22XLTS U1624 ( .A0(n1459), .A1(DMP_SFG[2]), .B0(n1453), .B1(
DMP_SHT2_EWSW[2]), .Y(n711) );
AO22XLTS U1625 ( .A0(n1329), .A1(DMP_EXP_EWSW[3]), .B0(n1331), .B1(
DMP_SHT1_EWSW[3]), .Y(n710) );
AO22XLTS U1626 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1570), .B1(
DMP_SHT2_EWSW[3]), .Y(n709) );
AO22XLTS U1627 ( .A0(n1459), .A1(DMP_SFG[3]), .B0(n1453), .B1(
DMP_SHT2_EWSW[3]), .Y(n708) );
AO22XLTS U1628 ( .A0(n1329), .A1(DMP_EXP_EWSW[4]), .B0(n1331), .B1(
DMP_SHT1_EWSW[4]), .Y(n707) );
AO22XLTS U1629 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1570), .B1(
DMP_SHT2_EWSW[4]), .Y(n706) );
AO22XLTS U1630 ( .A0(n1459), .A1(DMP_SFG[4]), .B0(n1453), .B1(
DMP_SHT2_EWSW[4]), .Y(n705) );
AO22XLTS U1631 ( .A0(n1329), .A1(DMP_EXP_EWSW[5]), .B0(n1331), .B1(
DMP_SHT1_EWSW[5]), .Y(n704) );
AO22XLTS U1632 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1570), .B1(
DMP_SHT2_EWSW[5]), .Y(n703) );
AO22XLTS U1633 ( .A0(n1469), .A1(DMP_SFG[5]), .B0(n1453), .B1(
DMP_SHT2_EWSW[5]), .Y(n702) );
AO22XLTS U1634 ( .A0(n1329), .A1(DMP_EXP_EWSW[6]), .B0(n1331), .B1(
DMP_SHT1_EWSW[6]), .Y(n701) );
AO22XLTS U1635 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1570), .B1(
DMP_SHT2_EWSW[6]), .Y(n700) );
AO22XLTS U1636 ( .A0(n1469), .A1(DMP_SFG[6]), .B0(n1453), .B1(
DMP_SHT2_EWSW[6]), .Y(n699) );
AO22XLTS U1637 ( .A0(n1329), .A1(DMP_EXP_EWSW[7]), .B0(n1331), .B1(
DMP_SHT1_EWSW[7]), .Y(n698) );
AO22XLTS U1638 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1570), .B1(
DMP_SHT2_EWSW[7]), .Y(n697) );
AO22XLTS U1639 ( .A0(n1329), .A1(DMP_EXP_EWSW[8]), .B0(n1331), .B1(
DMP_SHT1_EWSW[8]), .Y(n695) );
AO22XLTS U1640 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1570), .B1(
DMP_SHT2_EWSW[8]), .Y(n694) );
AO22XLTS U1641 ( .A0(n1459), .A1(DMP_SFG[8]), .B0(n1455), .B1(
DMP_SHT2_EWSW[8]), .Y(n693) );
AO22XLTS U1642 ( .A0(n1329), .A1(DMP_EXP_EWSW[9]), .B0(n1331), .B1(
DMP_SHT1_EWSW[9]), .Y(n692) );
AO22XLTS U1643 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n1570), .B1(
DMP_SHT2_EWSW[9]), .Y(n691) );
AO22XLTS U1644 ( .A0(n1459), .A1(DMP_SFG[9]), .B0(n1455), .B1(
DMP_SHT2_EWSW[9]), .Y(n690) );
AO22XLTS U1645 ( .A0(n1329), .A1(DMP_EXP_EWSW[10]), .B0(n1331), .B1(
DMP_SHT1_EWSW[10]), .Y(n689) );
BUFX4TS U1646 ( .A(n1570), .Y(n1338) );
AO22XLTS U1647 ( .A0(n873), .A1(DMP_SHT1_EWSW[10]), .B0(n1338), .B1(
DMP_SHT2_EWSW[10]), .Y(n688) );
AO22XLTS U1648 ( .A0(n1459), .A1(DMP_SFG[10]), .B0(n1453), .B1(
DMP_SHT2_EWSW[10]), .Y(n687) );
BUFX4TS U1649 ( .A(n1568), .Y(n1333) );
AO22XLTS U1650 ( .A0(n1329), .A1(DMP_EXP_EWSW[11]), .B0(n1333), .B1(
DMP_SHT1_EWSW[11]), .Y(n686) );
AO22XLTS U1651 ( .A0(n873), .A1(DMP_SHT1_EWSW[11]), .B0(n1338), .B1(
DMP_SHT2_EWSW[11]), .Y(n685) );
AO22XLTS U1652 ( .A0(n1459), .A1(DMP_SFG[11]), .B0(n1455), .B1(
DMP_SHT2_EWSW[11]), .Y(n684) );
AO22XLTS U1653 ( .A0(n1329), .A1(DMP_EXP_EWSW[12]), .B0(n1568), .B1(
DMP_SHT1_EWSW[12]), .Y(n683) );
AO22XLTS U1654 ( .A0(n873), .A1(DMP_SHT1_EWSW[12]), .B0(n1338), .B1(
DMP_SHT2_EWSW[12]), .Y(n682) );
AO22XLTS U1655 ( .A0(n1459), .A1(DMP_SFG[12]), .B0(n1453), .B1(
DMP_SHT2_EWSW[12]), .Y(n681) );
BUFX3TS U1656 ( .A(n1568), .Y(n1340) );
AO22XLTS U1657 ( .A0(n1329), .A1(DMP_EXP_EWSW[13]), .B0(n1340), .B1(
DMP_SHT1_EWSW[13]), .Y(n680) );
AO22XLTS U1658 ( .A0(n873), .A1(DMP_SHT1_EWSW[13]), .B0(n1338), .B1(
DMP_SHT2_EWSW[13]), .Y(n679) );
AO22XLTS U1659 ( .A0(n1459), .A1(DMP_SFG[13]), .B0(n1453), .B1(
DMP_SHT2_EWSW[13]), .Y(n678) );
AO22XLTS U1660 ( .A0(n1329), .A1(DMP_EXP_EWSW[14]), .B0(n1333), .B1(
DMP_SHT1_EWSW[14]), .Y(n677) );
AO22XLTS U1661 ( .A0(n873), .A1(DMP_SHT1_EWSW[14]), .B0(n1338), .B1(
DMP_SHT2_EWSW[14]), .Y(n676) );
AO22XLTS U1662 ( .A0(n1459), .A1(DMP_SFG[14]), .B0(n1453), .B1(
DMP_SHT2_EWSW[14]), .Y(n675) );
AO22XLTS U1663 ( .A0(n1329), .A1(DMP_EXP_EWSW[15]), .B0(n1568), .B1(
DMP_SHT1_EWSW[15]), .Y(n674) );
AO22XLTS U1664 ( .A0(n873), .A1(DMP_SHT1_EWSW[15]), .B0(n1338), .B1(
DMP_SHT2_EWSW[15]), .Y(n673) );
AO22XLTS U1665 ( .A0(n1459), .A1(DMP_SFG[15]), .B0(n1453), .B1(
DMP_SHT2_EWSW[15]), .Y(n672) );
AO22XLTS U1666 ( .A0(n1329), .A1(DMP_EXP_EWSW[16]), .B0(n1340), .B1(
DMP_SHT1_EWSW[16]), .Y(n671) );
AO22XLTS U1667 ( .A0(busy), .A1(DMP_SHT1_EWSW[16]), .B0(n1338), .B1(
DMP_SHT2_EWSW[16]), .Y(n670) );
AO22XLTS U1668 ( .A0(n1469), .A1(DMP_SFG[16]), .B0(n1453), .B1(
DMP_SHT2_EWSW[16]), .Y(n669) );
AO22XLTS U1669 ( .A0(n1341), .A1(DMP_EXP_EWSW[17]), .B0(n1333), .B1(
DMP_SHT1_EWSW[17]), .Y(n668) );
AO22XLTS U1670 ( .A0(busy), .A1(DMP_SHT1_EWSW[17]), .B0(n1338), .B1(
DMP_SHT2_EWSW[17]), .Y(n667) );
AO22XLTS U1671 ( .A0(n1459), .A1(DMP_SFG[17]), .B0(n1455), .B1(
DMP_SHT2_EWSW[17]), .Y(n666) );
AO22XLTS U1672 ( .A0(n1341), .A1(DMP_EXP_EWSW[18]), .B0(n1332), .B1(
DMP_SHT1_EWSW[18]), .Y(n665) );
AO22XLTS U1673 ( .A0(busy), .A1(DMP_SHT1_EWSW[18]), .B0(n1338), .B1(
DMP_SHT2_EWSW[18]), .Y(n664) );
AO22XLTS U1674 ( .A0(n1459), .A1(DMP_SFG[18]), .B0(n1455), .B1(
DMP_SHT2_EWSW[18]), .Y(n663) );
AO22XLTS U1675 ( .A0(n1341), .A1(DMP_EXP_EWSW[19]), .B0(n1340), .B1(
DMP_SHT1_EWSW[19]), .Y(n662) );
AO22XLTS U1676 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1338), .B1(
DMP_SHT2_EWSW[19]), .Y(n661) );
AO22XLTS U1677 ( .A0(n1459), .A1(DMP_SFG[19]), .B0(n1455), .B1(
DMP_SHT2_EWSW[19]), .Y(n660) );
AO22XLTS U1678 ( .A0(n1341), .A1(DMP_EXP_EWSW[20]), .B0(n1333), .B1(
DMP_SHT1_EWSW[20]), .Y(n659) );
AO22XLTS U1679 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1338), .B1(
DMP_SHT2_EWSW[20]), .Y(n658) );
AO22XLTS U1680 ( .A0(n1459), .A1(DMP_SFG[20]), .B0(n1455), .B1(
DMP_SHT2_EWSW[20]), .Y(n657) );
AO22XLTS U1681 ( .A0(n1341), .A1(DMP_EXP_EWSW[21]), .B0(n1332), .B1(
DMP_SHT1_EWSW[21]), .Y(n656) );
AO22XLTS U1682 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1338), .B1(
DMP_SHT2_EWSW[21]), .Y(n655) );
AO22XLTS U1683 ( .A0(n1459), .A1(DMP_SFG[21]), .B0(n1455), .B1(
DMP_SHT2_EWSW[21]), .Y(n654) );
AO22XLTS U1684 ( .A0(n1341), .A1(DMP_EXP_EWSW[22]), .B0(n1340), .B1(
DMP_SHT1_EWSW[22]), .Y(n653) );
AO22XLTS U1685 ( .A0(busy), .A1(DMP_SHT1_EWSW[22]), .B0(n1570), .B1(
DMP_SHT2_EWSW[22]), .Y(n652) );
AO22XLTS U1686 ( .A0(n1469), .A1(DMP_SFG[22]), .B0(n1455), .B1(
DMP_SHT2_EWSW[22]), .Y(n651) );
AO22XLTS U1687 ( .A0(n1341), .A1(DMP_EXP_EWSW[23]), .B0(n1340), .B1(
DMP_SHT1_EWSW[23]), .Y(n650) );
AO22XLTS U1688 ( .A0(n873), .A1(DMP_SHT1_EWSW[23]), .B0(n1570), .B1(
DMP_SHT2_EWSW[23]), .Y(n649) );
AO22XLTS U1689 ( .A0(n1471), .A1(DMP_SHT2_EWSW[23]), .B0(n1459), .B1(
DMP_SFG[23]), .Y(n648) );
AO22XLTS U1690 ( .A0(n1354), .A1(DMP_SFG[23]), .B0(n1361), .B1(
DMP_exp_NRM_EW[0]), .Y(n647) );
AO22XLTS U1691 ( .A0(n1341), .A1(DMP_EXP_EWSW[24]), .B0(n1340), .B1(
DMP_SHT1_EWSW[24]), .Y(n645) );
AO22XLTS U1692 ( .A0(n873), .A1(DMP_SHT1_EWSW[24]), .B0(n1338), .B1(
DMP_SHT2_EWSW[24]), .Y(n644) );
AO22XLTS U1693 ( .A0(n1453), .A1(DMP_SHT2_EWSW[24]), .B0(n1469), .B1(
DMP_SFG[24]), .Y(n643) );
AO22XLTS U1694 ( .A0(n1354), .A1(DMP_SFG[24]), .B0(n1602), .B1(
DMP_exp_NRM_EW[1]), .Y(n642) );
AO22XLTS U1695 ( .A0(n1341), .A1(DMP_EXP_EWSW[25]), .B0(n1340), .B1(
DMP_SHT1_EWSW[25]), .Y(n640) );
AO22XLTS U1696 ( .A0(n873), .A1(DMP_SHT1_EWSW[25]), .B0(n1338), .B1(
DMP_SHT2_EWSW[25]), .Y(n639) );
AO22XLTS U1697 ( .A0(n1455), .A1(DMP_SHT2_EWSW[25]), .B0(n1456), .B1(
DMP_SFG[25]), .Y(n638) );
AO22XLTS U1698 ( .A0(n1354), .A1(DMP_SFG[25]), .B0(n1602), .B1(
DMP_exp_NRM_EW[2]), .Y(n637) );
AO22XLTS U1699 ( .A0(n1341), .A1(DMP_EXP_EWSW[26]), .B0(n1340), .B1(
DMP_SHT1_EWSW[26]), .Y(n635) );
AO22XLTS U1700 ( .A0(n873), .A1(DMP_SHT1_EWSW[26]), .B0(n1338), .B1(
DMP_SHT2_EWSW[26]), .Y(n634) );
AO22XLTS U1701 ( .A0(n1471), .A1(DMP_SHT2_EWSW[26]), .B0(n1459), .B1(
DMP_SFG[26]), .Y(n633) );
AO22XLTS U1702 ( .A0(n1354), .A1(DMP_SFG[26]), .B0(n1602), .B1(
DMP_exp_NRM_EW[3]), .Y(n632) );
AO22XLTS U1703 ( .A0(n1341), .A1(n900), .B0(n1340), .B1(DMP_SHT1_EWSW[27]),
.Y(n630) );
AO22XLTS U1704 ( .A0(n873), .A1(DMP_SHT1_EWSW[27]), .B0(n1338), .B1(
DMP_SHT2_EWSW[27]), .Y(n629) );
AO22XLTS U1705 ( .A0(n1455), .A1(DMP_SHT2_EWSW[27]), .B0(n1469), .B1(
DMP_SFG[27]), .Y(n628) );
AO22XLTS U1706 ( .A0(n1354), .A1(DMP_SFG[27]), .B0(n1602), .B1(
DMP_exp_NRM_EW[4]), .Y(n627) );
AO22XLTS U1707 ( .A0(n1341), .A1(DMP_EXP_EWSW[28]), .B0(n1340), .B1(
DMP_SHT1_EWSW[28]), .Y(n625) );
AO22XLTS U1708 ( .A0(n873), .A1(DMP_SHT1_EWSW[28]), .B0(n1338), .B1(
DMP_SHT2_EWSW[28]), .Y(n624) );
AO22XLTS U1709 ( .A0(n1455), .A1(DMP_SHT2_EWSW[28]), .B0(n1459), .B1(
DMP_SFG[28]), .Y(n623) );
AO22XLTS U1710 ( .A0(n1354), .A1(DMP_SFG[28]), .B0(n1602), .B1(
DMP_exp_NRM_EW[5]), .Y(n622) );
AO22XLTS U1711 ( .A0(n1341), .A1(DMP_EXP_EWSW[29]), .B0(n1340), .B1(
DMP_SHT1_EWSW[29]), .Y(n620) );
AO22XLTS U1712 ( .A0(n873), .A1(DMP_SHT1_EWSW[29]), .B0(n1338), .B1(
DMP_SHT2_EWSW[29]), .Y(n619) );
AO22XLTS U1713 ( .A0(n1455), .A1(DMP_SHT2_EWSW[29]), .B0(n1456), .B1(
DMP_SFG[29]), .Y(n618) );
BUFX4TS U1714 ( .A(n1602), .Y(n1361) );
AO22XLTS U1715 ( .A0(n1354), .A1(DMP_SFG[29]), .B0(n1361), .B1(
DMP_exp_NRM_EW[6]), .Y(n617) );
AO22XLTS U1716 ( .A0(n1483), .A1(DMP_EXP_EWSW[30]), .B0(n1340), .B1(
DMP_SHT1_EWSW[30]), .Y(n615) );
AO22XLTS U1717 ( .A0(n873), .A1(DMP_SHT1_EWSW[30]), .B0(n1338), .B1(
DMP_SHT2_EWSW[30]), .Y(n614) );
AO22XLTS U1718 ( .A0(n1455), .A1(DMP_SHT2_EWSW[30]), .B0(n1469), .B1(
DMP_SFG[30]), .Y(n613) );
AO22XLTS U1719 ( .A0(n1354), .A1(DMP_SFG[30]), .B0(n1361), .B1(
DMP_exp_NRM_EW[7]), .Y(n612) );
AO22XLTS U1720 ( .A0(n1483), .A1(DmP_EXP_EWSW[3]), .B0(n1568), .B1(
DmP_mant_SHT1_SW[3]), .Y(n603) );
AO22XLTS U1721 ( .A0(n1483), .A1(DmP_EXP_EWSW[7]), .B0(n1332), .B1(
DmP_mant_SHT1_SW[7]), .Y(n595) );
AO22XLTS U1722 ( .A0(n1339), .A1(DmP_EXP_EWSW[10]), .B0(n1332), .B1(
DmP_mant_SHT1_SW[10]), .Y(n589) );
AO22XLTS U1723 ( .A0(n1339), .A1(DmP_EXP_EWSW[11]), .B0(n1332), .B1(n898),
.Y(n587) );
OAI222X1TS U1724 ( .A0(n1336), .A1(n1562), .B0(n1495), .B1(
Shift_reg_FLAGS_7_6), .C0(n1480), .C1(n1334), .Y(n563) );
OAI222X1TS U1725 ( .A0(n1336), .A1(n1499), .B0(n1563), .B1(
Shift_reg_FLAGS_7_6), .C0(n1606), .C1(n1334), .Y(n562) );
OAI222X1TS U1726 ( .A0(n1336), .A1(n1566), .B0(n1498), .B1(
Shift_reg_FLAGS_7_6), .C0(n1541), .C1(n1334), .Y(n561) );
NAND2X1TS U1727 ( .A(n1364), .B(Shift_reg_FLAGS_7[0]), .Y(n1337) );
OAI2BB1X1TS U1728 ( .A0N(underflow_flag), .A1N(n872), .B0(n1337), .Y(n559)
);
AO22XLTS U1729 ( .A0(n1339), .A1(ZERO_FLAG_EXP), .B0(n1332), .B1(
ZERO_FLAG_SHT1), .Y(n557) );
AO22XLTS U1730 ( .A0(n873), .A1(ZERO_FLAG_SHT1), .B0(n1338), .B1(
ZERO_FLAG_SHT2), .Y(n556) );
AO22XLTS U1731 ( .A0(n1455), .A1(ZERO_FLAG_SHT2), .B0(n1456), .B1(
ZERO_FLAG_SFG), .Y(n555) );
AO22XLTS U1732 ( .A0(n1354), .A1(ZERO_FLAG_SFG), .B0(n1361), .B1(
ZERO_FLAG_NRM), .Y(n554) );
AO22XLTS U1733 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n874),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n553) );
AO22XLTS U1734 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n872), .B1(zero_flag), .Y(n552) );
AO22XLTS U1735 ( .A0(n1339), .A1(OP_FLAG_EXP), .B0(OP_FLAG_SHT1), .B1(n1568),
.Y(n551) );
AO22XLTS U1736 ( .A0(n873), .A1(OP_FLAG_SHT1), .B0(n1570), .B1(OP_FLAG_SHT2),
.Y(n550) );
AO22XLTS U1737 ( .A0(n1469), .A1(OP_FLAG_SFG), .B0(n1455), .B1(OP_FLAG_SHT2),
.Y(n549) );
AO22XLTS U1738 ( .A0(n1341), .A1(SIGN_FLAG_EXP), .B0(n1340), .B1(
SIGN_FLAG_SHT1), .Y(n548) );
AO22XLTS U1739 ( .A0(n873), .A1(SIGN_FLAG_SHT1), .B0(n1570), .B1(
SIGN_FLAG_SHT2), .Y(n547) );
AO22XLTS U1740 ( .A0(n1455), .A1(SIGN_FLAG_SHT2), .B0(n1469), .B1(
SIGN_FLAG_SFG), .Y(n546) );
AO22XLTS U1741 ( .A0(n1354), .A1(SIGN_FLAG_SFG), .B0(n1602), .B1(
SIGN_FLAG_NRM), .Y(n545) );
AO22XLTS U1742 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n874),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n544) );
AOI22X1TS U1743 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n1355), .B0(n1359), .B1(n913), .Y(n1345) );
AOI22X1TS U1744 ( .A0(n1357), .A1(n1345), .B0(n1478), .B1(n1361), .Y(n542)
);
AOI22X1TS U1745 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1355), .B0(n1359), .B1(n917), .Y(n1346) );
AOI22X1TS U1746 ( .A0(n1357), .A1(n1346), .B0(n1558), .B1(n1361), .Y(n541)
);
OAI21XLTS U1747 ( .A0(n1347), .A1(DMP_SFG[0]), .B0(n1349), .Y(n1348) );
AOI22X1TS U1748 ( .A0(n1357), .A1(n1348), .B0(n1504), .B1(n1361), .Y(n540)
);
XNOR2X1TS U1749 ( .A(DMP_SFG[1]), .B(n1349), .Y(n1350) );
XNOR2X1TS U1750 ( .A(n1350), .B(n891), .Y(n1351) );
AOI22X1TS U1751 ( .A0(n1357), .A1(n1351), .B0(n1551), .B1(n1361), .Y(n539)
);
AOI22X1TS U1752 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n1358), .B0(n1359), .B1(n920), .Y(intadd_69_CI) );
AOI2BB2XLTS U1753 ( .B0(n929), .B1(intadd_69_SUM_0_), .A0N(
Raw_mant_NRM_SWR[4]), .A1N(n1354), .Y(n538) );
AOI22X1TS U1754 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1355), .B0(n1359), .B1(n921), .Y(intadd_69_B_1_) );
AOI22X1TS U1755 ( .A0(n929), .A1(intadd_69_SUM_1_), .B0(n1512), .B1(n1361),
.Y(n537) );
AOI22X1TS U1756 ( .A0(n929), .A1(intadd_69_SUM_2_), .B0(n1482), .B1(n1361),
.Y(n536) );
AOI22X1TS U1757 ( .A0(n1357), .A1(intadd_69_SUM_3_), .B0(n1477), .B1(n1361),
.Y(n535) );
AOI22X1TS U1758 ( .A0(n1357), .A1(intadd_69_SUM_4_), .B0(n1479), .B1(n1361),
.Y(n534) );
XNOR2X1TS U1759 ( .A(DMP_SFG[7]), .B(n892), .Y(n1352) );
XNOR2X1TS U1760 ( .A(intadd_69_n1), .B(n1352), .Y(n1353) );
AOI22X1TS U1761 ( .A0(n929), .A1(n1353), .B0(n1481), .B1(n1361), .Y(n533) );
AOI22X1TS U1762 ( .A0(n929), .A1(intadd_68_SUM_0_), .B0(n1476), .B1(n1361),
.Y(n532) );
AOI2BB2XLTS U1763 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n1358), .A0N(n1358),
.A1N(DmP_mant_SFG_SWR[11]), .Y(intadd_68_B_1_) );
AOI22X1TS U1764 ( .A0(n929), .A1(intadd_68_SUM_1_), .B0(n1475), .B1(n1361),
.Y(n531) );
AOI2BB2XLTS U1765 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n1358), .A0N(n930), .A1N(
DmP_mant_SFG_SWR[12]), .Y(intadd_68_B_2_) );
AOI2BB2XLTS U1766 ( .B0(n1354), .B1(intadd_68_SUM_2_), .A0N(
Raw_mant_NRM_SWR[12]), .A1N(n1354), .Y(n530) );
AOI2BB2XLTS U1767 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n1358), .A0N(n930), .A1N(
DmP_mant_SFG_SWR[13]), .Y(intadd_68_B_3_) );
AOI22X1TS U1768 ( .A0(n1357), .A1(intadd_68_SUM_3_), .B0(n1497), .B1(n1361),
.Y(n529) );
AOI2BB2XLTS U1769 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n1358), .A0N(n1358),
.A1N(DmP_mant_SFG_SWR[14]), .Y(intadd_68_B_4_) );
AOI22X1TS U1770 ( .A0(n1357), .A1(intadd_68_SUM_4_), .B0(n1486), .B1(n1361),
.Y(n528) );
AOI2BB2XLTS U1771 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n1358), .A0N(n930), .A1N(
DmP_mant_SFG_SWR[15]), .Y(intadd_68_B_5_) );
AOI22X1TS U1772 ( .A0(n1357), .A1(intadd_68_SUM_5_), .B0(n1485), .B1(n1361),
.Y(n527) );
AOI22X1TS U1773 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n1355), .B0(n1359), .B1(
n927), .Y(intadd_68_B_6_) );
AOI22X1TS U1774 ( .A0(n1357), .A1(intadd_68_SUM_6_), .B0(n1474), .B1(n1602),
.Y(n526) );
AOI22X1TS U1775 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n1355), .B0(n1359), .B1(
n928), .Y(intadd_68_B_7_) );
AOI22X1TS U1776 ( .A0(n1357), .A1(intadd_68_SUM_7_), .B0(n1502), .B1(n1602),
.Y(n525) );
AOI22X1TS U1777 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n1355), .B0(n1359), .B1(
n924), .Y(intadd_68_B_8_) );
AOI2BB2XLTS U1778 ( .B0(n929), .B1(intadd_68_SUM_8_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1354), .Y(n524) );
AOI22X1TS U1779 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n1355), .B0(n1359), .B1(
n909), .Y(intadd_68_B_9_) );
AOI2BB2XLTS U1780 ( .B0(n1354), .B1(intadd_68_SUM_9_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1354), .Y(n523) );
AOI22X1TS U1781 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1355), .B0(n1359), .B1(
n910), .Y(intadd_68_B_10_) );
AOI2BB2XLTS U1782 ( .B0(n929), .B1(intadd_68_SUM_10_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1354), .Y(n522) );
AOI22X1TS U1783 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n1355), .B0(n1359), .B1(
n911), .Y(intadd_68_B_11_) );
AOI22X1TS U1784 ( .A0(n1357), .A1(intadd_68_SUM_11_), .B0(n1506), .B1(n1602),
.Y(n521) );
AOI22X1TS U1785 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n1355), .B0(n1359), .B1(
n912), .Y(intadd_68_B_12_) );
AOI22X1TS U1786 ( .A0(n1357), .A1(intadd_68_SUM_12_), .B0(n1501), .B1(n1602),
.Y(n520) );
AOI22X1TS U1787 ( .A0(DmP_mant_SFG_SWR[23]), .A1(n1355), .B0(n1359), .B1(
n914), .Y(intadd_68_B_13_) );
AOI22X1TS U1788 ( .A0(n1357), .A1(intadd_68_SUM_13_), .B0(n1472), .B1(n1602),
.Y(n519) );
AOI22X1TS U1789 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1355), .B0(n1359), .B1(
n915), .Y(intadd_68_B_14_) );
AOI22X1TS U1790 ( .A0(n1357), .A1(intadd_68_SUM_14_), .B0(n1473), .B1(n1602),
.Y(n518) );
AOI22X1TS U1791 ( .A0(DmP_mant_SFG_SWR[25]), .A1(n1359), .B0(n1358), .B1(
n916), .Y(n1360) );
XNOR2X1TS U1792 ( .A(intadd_68_n1), .B(n1360), .Y(n1362) );
AOI22X1TS U1793 ( .A0(n929), .A1(n1362), .B0(n1484), .B1(n1361), .Y(n517) );
AND3X4TS U1794 ( .A(shift_value_SHT2_EWR[2]), .B(n1511), .C(
shift_value_SHT2_EWR[3]), .Y(n1430) );
NAND2X1TS U1795 ( .A(shift_value_SHT2_EWR[2]), .B(n1505), .Y(n1383) );
NAND2X1TS U1796 ( .A(n1403), .B(n1511), .Y(n1414) );
NOR2XLTS U1797 ( .A(n1437), .B(n1414), .Y(n1368) );
AOI22X1TS U1798 ( .A0(Data_array_SWR[12]), .A1(n1367), .B0(
Data_array_SWR[13]), .B1(n1438), .Y(n1369) );
OAI221X1TS U1799 ( .A0(n1468), .A1(n1371), .B0(n1437), .B1(n1372), .C0(n1369), .Y(n1450) );
AO22XLTS U1800 ( .A0(final_result_ieee[10]), .A1(n872), .B0(n1384), .B1(
n1450), .Y(n511) );
AOI22X1TS U1801 ( .A0(Data_array_SWR[12]), .A1(n1438), .B0(
Data_array_SWR[13]), .B1(n1367), .Y(n1370) );
OAI221X1TS U1802 ( .A0(n1468), .A1(n1372), .B0(n1437), .B1(n1371), .C0(n1370), .Y(n1451) );
AO22XLTS U1803 ( .A0(n1384), .A1(n1451), .B0(final_result_ieee[11]), .B1(
n872), .Y(n510) );
AOI22X1TS U1804 ( .A0(Data_array_SWR[22]), .A1(n1429), .B0(
Data_array_SWR[18]), .B1(n1366), .Y(n1376) );
AOI22X1TS U1805 ( .A0(Data_array_SWR[14]), .A1(n1438), .B0(
Data_array_SWR[11]), .B1(n1367), .Y(n1373) );
OAI221X1TS U1806 ( .A0(n1468), .A1(n1375), .B0(n1437), .B1(n1376), .C0(n1373), .Y(n1449) );
AO22XLTS U1807 ( .A0(n1384), .A1(n1449), .B0(final_result_ieee[9]), .B1(n872), .Y(n509) );
AOI22X1TS U1808 ( .A0(Data_array_SWR[14]), .A1(n1367), .B0(
Data_array_SWR[11]), .B1(n1438), .Y(n1374) );
OAI221X1TS U1809 ( .A0(n1468), .A1(n1376), .B0(n1437), .B1(n1375), .C0(n1374), .Y(n1452) );
AO22XLTS U1810 ( .A0(n1384), .A1(n1452), .B0(final_result_ieee[12]), .B1(
n872), .Y(n508) );
AOI22X1TS U1811 ( .A0(Data_array_SWR[23]), .A1(n1429), .B0(
Data_array_SWR[19]), .B1(n1366), .Y(n1380) );
AOI22X1TS U1812 ( .A0(Data_array_SWR[10]), .A1(n1367), .B0(
Data_array_SWR[15]), .B1(n1438), .Y(n1377) );
OAI221X1TS U1813 ( .A0(n1468), .A1(n1379), .B0(n1437), .B1(n1380), .C0(n1377), .Y(n1448) );
AO22XLTS U1814 ( .A0(n1384), .A1(n1448), .B0(final_result_ieee[8]), .B1(n872), .Y(n507) );
AOI22X1TS U1815 ( .A0(Data_array_SWR[10]), .A1(n1438), .B0(
Data_array_SWR[15]), .B1(n1367), .Y(n1378) );
OAI221X1TS U1816 ( .A0(n1468), .A1(n1380), .B0(n1437), .B1(n1379), .C0(n1378), .Y(n1454) );
AO22XLTS U1817 ( .A0(n1384), .A1(n1454), .B0(final_result_ieee[13]), .B1(
n872), .Y(n506) );
AOI22X1TS U1818 ( .A0(Data_array_SWR[17]), .A1(n1429), .B0(
Data_array_SWR[13]), .B1(n1366), .Y(n1382) );
CLKAND2X2TS U1819 ( .A(n1403), .B(shift_value_SHT2_EWR[4]), .Y(n1396) );
AOI22X1TS U1820 ( .A0(Data_array_SWR[21]), .A1(n1430), .B0(
Data_array_SWR[25]), .B1(n1396), .Y(n1381) );
NAND2X1TS U1821 ( .A(n1382), .B(n1381), .Y(n1386) );
NOR2X1TS U1822 ( .A(shift_value_SHT2_EWR[2]), .B(n1505), .Y(n1389) );
INVX2TS U1823 ( .A(n1383), .Y(n1404) );
INVX2TS U1824 ( .A(n1434), .Y(n1385) );
INVX4TS U1825 ( .A(n1384), .Y(n1428) );
OAI2BB2XLTS U1826 ( .B0(n1447), .B1(n1428), .A0N(final_result_ieee[7]),
.A1N(n872), .Y(n505) );
OAI2BB2XLTS U1827 ( .B0(n1457), .B1(n1428), .A0N(final_result_ieee[14]),
.A1N(n872), .Y(n504) );
AOI22X1TS U1828 ( .A0(Data_array_SWR[12]), .A1(n1366), .B0(
Data_array_SWR[16]), .B1(n1429), .Y(n1388) );
AOI22X1TS U1829 ( .A0(Data_array_SWR[24]), .A1(n1396), .B0(
Data_array_SWR[20]), .B1(n1430), .Y(n1387) );
NAND2X1TS U1830 ( .A(n1388), .B(n1387), .Y(n1391) );
INVX2TS U1831 ( .A(n1426), .Y(n1390) );
OAI2BB2XLTS U1832 ( .B0(n1446), .B1(n1428), .A0N(final_result_ieee[6]),
.A1N(n872), .Y(n503) );
OAI2BB2XLTS U1833 ( .B0(n1458), .B1(n1428), .A0N(final_result_ieee[15]),
.A1N(n872), .Y(n502) );
AOI22X1TS U1834 ( .A0(Data_array_SWR[15]), .A1(n1429), .B0(
Data_array_SWR[11]), .B1(n1366), .Y(n1393) );
AOI22X1TS U1835 ( .A0(Data_array_SWR[23]), .A1(n1396), .B0(
Data_array_SWR[19]), .B1(n1430), .Y(n1392) );
NAND2X1TS U1836 ( .A(n1393), .B(n1392), .Y(n1395) );
AOI22X1TS U1837 ( .A0(Data_array_SWR[22]), .A1(n1404), .B0(
Data_array_SWR[18]), .B1(n1403), .Y(n1420) );
INVX2TS U1838 ( .A(n1420), .Y(n1394) );
OAI2BB2XLTS U1839 ( .B0(n1445), .B1(n1428), .A0N(final_result_ieee[5]),
.A1N(n872), .Y(n501) );
OAI2BB2XLTS U1840 ( .B0(n1460), .B1(n1428), .A0N(final_result_ieee[16]),
.A1N(n872), .Y(n500) );
AOI22X1TS U1841 ( .A0(Data_array_SWR[14]), .A1(n1429), .B0(
Data_array_SWR[10]), .B1(n1366), .Y(n1398) );
AOI22X1TS U1842 ( .A0(Data_array_SWR[22]), .A1(n1396), .B0(
Data_array_SWR[18]), .B1(n1430), .Y(n1397) );
NAND2X1TS U1843 ( .A(n1398), .B(n1397), .Y(n1400) );
AOI22X1TS U1844 ( .A0(Data_array_SWR[23]), .A1(n1404), .B0(
Data_array_SWR[19]), .B1(n1403), .Y(n1417) );
INVX2TS U1845 ( .A(n1417), .Y(n1399) );
OAI2BB2XLTS U1846 ( .B0(n1444), .B1(n1428), .A0N(final_result_ieee[4]),
.A1N(n1423), .Y(n499) );
OAI2BB2XLTS U1847 ( .B0(n1461), .B1(n1428), .A0N(final_result_ieee[17]),
.A1N(n1423), .Y(n498) );
AOI22X1TS U1848 ( .A0(Data_array_SWR[21]), .A1(n1403), .B0(
Data_array_SWR[25]), .B1(n1404), .Y(n1409) );
AOI22X1TS U1849 ( .A0(Data_array_SWR[13]), .A1(n1429), .B0(Data_array_SWR[9]), .B1(n1366), .Y(n1402) );
NAND2X1TS U1850 ( .A(Data_array_SWR[17]), .B(n1430), .Y(n1401) );
OAI211X1TS U1851 ( .A0(n1409), .A1(n1511), .B0(n1402), .C0(n1401), .Y(n1405)
);
AO22X1TS U1852 ( .A0(Data_array_SWR[24]), .A1(n1404), .B0(Data_array_SWR[20]), .B1(n1403), .Y(n1406) );
OAI2BB2XLTS U1853 ( .B0(n1443), .B1(n1428), .A0N(final_result_ieee[3]),
.A1N(n1423), .Y(n497) );
OAI2BB2XLTS U1854 ( .B0(n1462), .B1(n1428), .A0N(final_result_ieee[18]),
.A1N(n1423), .Y(n496) );
AOI22X1TS U1855 ( .A0(Data_array_SWR[12]), .A1(n1429), .B0(Data_array_SWR[8]), .B1(n1366), .Y(n1408) );
AOI22X1TS U1856 ( .A0(Data_array_SWR[16]), .A1(n1430), .B0(
shift_value_SHT2_EWR[4]), .B1(n1406), .Y(n1407) );
NAND2X1TS U1857 ( .A(n1408), .B(n1407), .Y(n1413) );
INVX2TS U1858 ( .A(n1409), .Y(n1412) );
OAI2BB2XLTS U1859 ( .B0(n1442), .B1(n1428), .A0N(final_result_ieee[2]),
.A1N(n1423), .Y(n495) );
OAI2BB2XLTS U1860 ( .B0(n1463), .B1(n1428), .A0N(final_result_ieee[19]),
.A1N(n1423), .Y(n494) );
AOI22X1TS U1861 ( .A0(Data_array_SWR[15]), .A1(n1430), .B0(
Data_array_SWR[11]), .B1(n1429), .Y(n1416) );
INVX2TS U1862 ( .A(n1414), .Y(n1431) );
AOI22X1TS U1863 ( .A0(Data_array_SWR[7]), .A1(n1366), .B0(Data_array_SWR[3]),
.B1(n1431), .Y(n1415) );
OAI211X1TS U1864 ( .A0(n1417), .A1(n1511), .B0(n1416), .C0(n1415), .Y(n1421)
);
AOI22X1TS U1865 ( .A0(Data_array_SWR[22]), .A1(n1438), .B0(n1437), .B1(n1421), .Y(n1441) );
OAI2BB2XLTS U1866 ( .B0(n1441), .B1(n1428), .A0N(final_result_ieee[1]),
.A1N(n1423), .Y(n493) );
AOI22X1TS U1867 ( .A0(Data_array_SWR[14]), .A1(n1430), .B0(
Data_array_SWR[10]), .B1(n1429), .Y(n1419) );
AOI22X1TS U1868 ( .A0(Data_array_SWR[6]), .A1(n1366), .B0(Data_array_SWR[2]),
.B1(n1431), .Y(n1418) );
OAI211X1TS U1869 ( .A0(n1420), .A1(n1511), .B0(n1419), .C0(n1418), .Y(n1422)
);
AOI22X1TS U1870 ( .A0(Data_array_SWR[23]), .A1(n1438), .B0(n1437), .B1(n1422), .Y(n1440) );
OAI2BB2XLTS U1871 ( .B0(n1440), .B1(n1428), .A0N(final_result_ieee[0]),
.A1N(n1423), .Y(n492) );
AOI22X1TS U1872 ( .A0(Data_array_SWR[22]), .A1(n1367), .B0(n1468), .B1(n1421), .Y(n1464) );
OAI2BB2XLTS U1873 ( .B0(n1464), .B1(n1428), .A0N(final_result_ieee[20]),
.A1N(n1423), .Y(n491) );
AOI22X1TS U1874 ( .A0(Data_array_SWR[23]), .A1(n1367), .B0(n1468), .B1(n1422), .Y(n1465) );
OAI2BB2XLTS U1875 ( .B0(n1465), .B1(n1428), .A0N(final_result_ieee[21]),
.A1N(n1423), .Y(n490) );
AOI22X1TS U1876 ( .A0(Data_array_SWR[13]), .A1(n1430), .B0(Data_array_SWR[9]), .B1(n1429), .Y(n1425) );
AOI22X1TS U1877 ( .A0(Data_array_SWR[5]), .A1(n1366), .B0(Data_array_SWR[1]),
.B1(n1431), .Y(n1424) );
OAI211X1TS U1878 ( .A0(n1426), .A1(n1511), .B0(n1425), .C0(n1424), .Y(n1436)
);
AOI22X1TS U1879 ( .A0(Data_array_SWR[24]), .A1(n1367), .B0(n1468), .B1(n1436), .Y(n1466) );
OAI2BB2XLTS U1880 ( .B0(n1466), .B1(n1428), .A0N(final_result_ieee[22]),
.A1N(n872), .Y(n489) );
AOI22X1TS U1881 ( .A0(Data_array_SWR[12]), .A1(n1430), .B0(Data_array_SWR[8]), .B1(n1429), .Y(n1433) );
AOI22X1TS U1882 ( .A0(Data_array_SWR[4]), .A1(n1366), .B0(Data_array_SWR[0]),
.B1(n1431), .Y(n1432) );
OAI211X1TS U1883 ( .A0(n1434), .A1(n1511), .B0(n1433), .C0(n1432), .Y(n1467)
);
AOI22X1TS U1884 ( .A0(Data_array_SWR[25]), .A1(n1438), .B0(n1437), .B1(n1467), .Y(n1435) );
AOI22X1TS U1885 ( .A0(n1453), .A1(n1435), .B0(n1456), .B1(n913), .Y(n488) );
AOI22X1TS U1886 ( .A0(Data_array_SWR[24]), .A1(n1438), .B0(n1437), .B1(n1436), .Y(n1439) );
AOI22X1TS U1887 ( .A0(n1471), .A1(n1439), .B0(n1456), .B1(n917), .Y(n487) );
AOI22X1TS U1888 ( .A0(n1471), .A1(n1440), .B0(n1456), .B1(n918), .Y(n486) );
AOI22X1TS U1889 ( .A0(n1455), .A1(n1441), .B0(n1469), .B1(n919), .Y(n485) );
AOI22X1TS U1890 ( .A0(n1471), .A1(n1442), .B0(n1456), .B1(n920), .Y(n484) );
AOI22X1TS U1891 ( .A0(n1471), .A1(n1443), .B0(n1469), .B1(n921), .Y(n483) );
AOI22X1TS U1892 ( .A0(n1471), .A1(n1444), .B0(n1456), .B1(n922), .Y(n482) );
AOI22X1TS U1893 ( .A0(n1471), .A1(n1445), .B0(n923), .B1(n1469), .Y(n481) );
AOI22X1TS U1894 ( .A0(n1471), .A1(n1446), .B0(n925), .B1(n1456), .Y(n480) );
AOI22X1TS U1895 ( .A0(n1471), .A1(n1447), .B0(n1469), .B1(n926), .Y(n479) );
AO22XLTS U1896 ( .A0(n1456), .A1(DmP_mant_SFG_SWR[10]), .B0(n1453), .B1(
n1448), .Y(n478) );
AO22XLTS U1897 ( .A0(n1469), .A1(DmP_mant_SFG_SWR[11]), .B0(n1453), .B1(
n1449), .Y(n477) );
AO22XLTS U1898 ( .A0(n1456), .A1(DmP_mant_SFG_SWR[12]), .B0(n1453), .B1(
n1450), .Y(n476) );
AO22XLTS U1899 ( .A0(n1456), .A1(DmP_mant_SFG_SWR[13]), .B0(n1453), .B1(
n1451), .Y(n475) );
AO22XLTS U1900 ( .A0(n1456), .A1(DmP_mant_SFG_SWR[14]), .B0(n1453), .B1(
n1452), .Y(n474) );
AO22XLTS U1901 ( .A0(n1456), .A1(DmP_mant_SFG_SWR[15]), .B0(n1455), .B1(
n1454), .Y(n473) );
AOI22X1TS U1902 ( .A0(n1471), .A1(n1457), .B0(n1459), .B1(n927), .Y(n472) );
AOI22X1TS U1903 ( .A0(n1471), .A1(n1458), .B0(n1469), .B1(n928), .Y(n471) );
AOI22X1TS U1904 ( .A0(n1471), .A1(n1460), .B0(n1469), .B1(n924), .Y(n470) );
AOI22X1TS U1905 ( .A0(n1471), .A1(n1461), .B0(n1456), .B1(n909), .Y(n469) );
AOI22X1TS U1906 ( .A0(n1471), .A1(n1462), .B0(n1469), .B1(n910), .Y(n468) );
AOI22X1TS U1907 ( .A0(n1471), .A1(n1463), .B0(n1328), .B1(n911), .Y(n467) );
AOI22X1TS U1908 ( .A0(n1471), .A1(n1464), .B0(n912), .B1(n1328), .Y(n466) );
AOI22X1TS U1909 ( .A0(n1471), .A1(n1465), .B0(n1328), .B1(n914), .Y(n465) );
AOI22X1TS U1910 ( .A0(n1471), .A1(n1466), .B0(n1328), .B1(n915), .Y(n464) );
AOI22X1TS U1911 ( .A0(Data_array_SWR[25]), .A1(n1367), .B0(n1468), .B1(n1467), .Y(n1470) );
AOI22X1TS U1912 ( .A0(n1471), .A1(n1470), .B0(n1469), .B1(n916), .Y(n463) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk30.tcl_GeArN16R6P4_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__HA_1_V
`define SKY130_FD_SC_HD__HA_1_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ha_1 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ha_1 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__HA_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR3_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3_BLACKBOX_V
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: DP_FPU.v
// Version: 1.0
// Date: 30 May 2015
//
// Copyright (C) 2015 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. PREPDATA Prepare data for the big multiplier
// 2. BCDADDER 4 bit BCD adder
// 3. DFPU_BCD Binary coded decimal (BCD) adder and subtractor
// 4. DFPU_ADDSUB Double precision floating point adder and subtractor
// 5. DFPU_MISC Double precision floating point miscellaneous operations
// 6. DFPU_MUL Double precision floating point multiplier
// 7. DIVI_PREP Prepare data for the divider
// 8. DFPU_DIV The divider for all divide opcodes : double, single and integer
// 9. DP_LOGIK Control logic and result path for different functions
// 10. DP_FPU Top level of long operations datapath
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 1. PREPDATA Prepare data for the big multiplier
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module PREPDATA ( START, MEI, DFLOAT, BWD, SRC1, SRC2,
MSD_1, MSD_2, LSD_1, LSD_2, LOAD_MSD, LOAD_LSD1, LOAD_LSD2 );
input [1:0] START;
input MEI,DFLOAT;
input [1:0] BWD;
input [31:0] SRC1,SRC2;
output [52:32] MSD_1,MSD_2;
output [31:0] LSD_1,LSD_2;
output LOAD_MSD,LOAD_LSD1,LOAD_LSD2;
reg [31:0] LSD_1,LSD_2;
assign MSD_1 = MEI ? 21'h0 : {1'b1,SRC1[19:0]};
assign MSD_2 = MEI ? 21'h0 : {1'b1,SRC2[19:0]};
always @(MEI or BWD or SRC1)
casex ({MEI,BWD})
3'b100 : LSD_1 = {24'h000000,SRC1[7:0]};
3'b101 : LSD_1 = {16'h0000,SRC1[15:0]};
default : LSD_1 = SRC1;
endcase
always @(MEI or BWD or SRC2)
casex ({MEI,BWD})
3'b100 : LSD_2 = {24'h000000,SRC2[7:0]};
3'b101 : LSD_2 = {16'h0000,SRC2[15:0]};
default : LSD_2 = SRC2;
endcase
assign LOAD_MSD = (START[0] & MEI) | (START[0] & DFLOAT); // 1. step data load at DFLOAT
assign LOAD_LSD1 = (START[0] & MEI) | (START[1] & DFLOAT); // 2. step execute at DFLOAT
assign LOAD_LSD2 = (START[1] & MEI) | (START[1] & DFLOAT); // 2. step execute at DFLOAT
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 2. BCDADDER 4 bit BCD adder
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module BCDADDER ( A_IN, B_IN, CY_IN, SUBP, OUT, CY_OUT );
input [3:0] A_IN,B_IN;
input CY_IN;
input SUBP;
output [3:0] OUT;
output CY_OUT;
wire [4:0] result;
wire over;
assign result = SUBP ? ({1'b0,A_IN} - {1'b0,B_IN} - {4'b0,CY_IN})
: ({1'b0,A_IN} + {1'b0,B_IN} + {4'b0,CY_IN});
assign over = result[4] | (result[3] & (result[2] | result[1]));
// if result<0 : -6 if result>9 : -10
assign OUT = result[3:0] - (SUBP ? {1'b0,result[4],result[4],1'b0} : {over,1'b0,over,1'b0});
assign CY_OUT = SUBP ? result[4] : over;
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 3. DFPU_BCD Binary coded decimal (BCD) adder and subtractor
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DFPU_BCD ( BCLK, BRESET, START, DO_BCD, BWD, SRC1, SRC2, CY_IN, SUBP, BCD_Q, CY_OUT, BCD_DONE );
// Byte : 3 cycles in shortest case REG-REG, Word : 4 cycles and Double : 6 cycles
input BCLK;
input BRESET;
input START; // START[1]
input DO_BCD; // BCD Opcode is valid
input [1:0] BWD;
input [31:0] SRC1,SRC2; // Source , Destination, data is stable during operation
input CY_IN; // comes from PSR
input SUBP; // SUBP = 1 : SUBP , 0 : ADDP
output reg [31:0] BCD_Q;
output reg CY_OUT; // went to PSR if DONE is valid
output BCD_DONE;
reg run_bcd;
reg [1:0] byte_cou;
reg [15:0] datain;
wire [7:0] result;
wire carry,carry_lsd,carry_msd;
// START : _/---\________________
// byte_cou : xxxxxx 0 x 1 x 2 x 3 x
// BCD_DONE : _____/---\____________ if BWD = Byte
always @(posedge BCLK or negedge BRESET)
if (!BRESET) run_bcd <= 1'b0;
else
run_bcd <= (START & DO_BCD) | (run_bcd & (BWD != byte_cou));
always @(posedge BCLK) byte_cou <= START ? 2'd0 : byte_cou + {1'b0,run_bcd};
always @(*)
casex ({START,byte_cou})
3'b1_xx : datain = {SRC1[7:0], SRC2[7:0]};
3'b0_00 : datain = {SRC1[15:8], SRC2[15:8]};
3'b0_01 : datain = {SRC1[23:16],SRC2[23:16]};
3'b0_1x : datain = {SRC1[31:24],SRC2[31:24]};
endcase
assign carry = START ? CY_IN : CY_OUT;
BCDADDER lsd_inst ( .A_IN(datain[3:0]), .B_IN(datain[11:8]), .CY_IN(carry), .SUBP(SUBP),
.OUT(result[3:0]), .CY_OUT(carry_lsd) );
BCDADDER msd_inst ( .A_IN(datain[7:4]), .B_IN(datain[15:12]), .CY_IN(carry_lsd), .SUBP(SUBP),
.OUT(result[7:4]), .CY_OUT(carry_msd) );
always @(posedge BCLK) CY_OUT <= carry_msd;
always @(posedge BCLK) if (START) BCD_Q[7:0] <= result;
always @(posedge BCLK) if (byte_cou == 2'd0) BCD_Q[15:8] <= result;
always @(posedge BCLK) if (byte_cou == 2'd1) BCD_Q[23:16] <= result;
always @(posedge BCLK) if (byte_cou[1]) BCD_Q[31:24] <= result;
assign BCD_DONE = run_bcd & (BWD == byte_cou);
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 4. DFPU_ADDSUB Double precision floating point adder and subtractor
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//module DFPU_ADDSUB ( BCLK, START, SRC1, SRC2, MAN1, MAN2, SRCFLAGS, BWD, SELECT, OUT, IOUT, CMPRES );
//
// input BCLK;
// input [1:0] START;
// input [31:0] SRC1,SRC2; // The input data
// input [20:0] MAN1,MAN2;
// input [5:0] SRCFLAGS; // NAN, ZERO and SIGN of operands
// input [1:0] BWD; // size of integer
// input [3:0] SELECT; // upper 2 bits : R.T.F. code
//
// output [69:0] OUT;
// output [31:0] IOUT; // result of ROUNDLi/TRUNCLi/FLOORLi = R.T.F.
// output [1:0] CMPRES;
//
// reg [69:0] outreg;
// reg [31:0] IOUT;
//
// // MOViL : 2 cycles
// // ROUNDLi : 3 cycles (+TRUNC & FLOOR)
// // ADD/SUB : 4 cycles
// // CMP : 2 cycles
//
// // ++++++++++++++++++++++++++++++++++
// // MOViL : 1. Pipeline stage : needs 3 cycles
//
// reg [31:8] movdat;
// reg [31:0] movif;
// reg sign_movif;
//
// always @(BWD or SRC1)
// casex({BWD,SRC1[15],SRC1[7]})
// 4'b00x0 : movdat = 24'h0000_00; // Byte
// 4'b00x1 : movdat = 24'hFFFF_FF;
// 4'b010x : movdat = {16'h0000,SRC1[15:8]}; // Word
// 4'b011x : movdat = {16'hFFFF,SRC1[15:8]};
// default : movdat = SRC1[31:8]; // Double
// endcase
//
// // This pipeline stage for better timing
// always @(posedge BCLK) movif <= movdat[31] ? (32'h0 - {movdat,SRC1[7:0]}) : {movdat,SRC1[7:0]}; // -2^31 is kept !
//
// always @(posedge BCLK) sign_movif <= movdat[31];
//
// // ROUNDLi/TRUNCLi/FLOORLi : 1. pipeline stage : can Opcode-Decoder deliver direct the 64 bit operand ? From register "yes"
//
// reg ovflag,ovflag2;
// reg rovfl;
// reg minint;
// wire [11:0] rexdiff,rexo;
// wire ganzklein; // Flag for 0
//
// assign rexdiff = 12'h41D - {1'b0,SRC1[30:20]}; // 4..0 is the right shift value : like Single FP same value space
//
// // ovflag2 at the end of rounding : Check for Overflow
// always @(posedge BCLK) rovfl <= (ovflag | ovflag2) & (SELECT[1:0] == 2'b11) & ~minint;
//
// // a large positiv difference is a very small number :
// assign ganzklein = (~rexdiff[11] & (rexdiff[10:5] != 6'b0)); // 0 is implicit via SRC1[30:20]=0
//
// // Detection of Overflow
// assign rexo = ({1'b0,SRC1[30:20]} - {11'h1FF,~BWD[1]}); // subtract B/W = 3FF , D = 3FE
//
// always @(BWD or rexo) // 0 ist in implicitly
// casex (BWD)
// 2'b00 : ovflag = (~rexo[11] & (rexo[10:3] != 8'h0)); // Exponent 0..7 because -128.4 => -128
// 2'b01 : ovflag = (~rexo[11] & (rexo[10:4] != 7'h0)); // Exponent 0..15 look above
// default : ovflag = (~rexo[11] & (rexo[10:5] != 6'h0)); // but Exponent only 0..30
// endcase
//
// always @(posedge BCLK)
// if (START[1]) minint <= (SRC1 == 32'hC1E0_0000) & (SRC2 == 32'h0) & BWD[1]; // detection of -2^31
//
// // ++++++++++++++++++++++++++++++++++++
// // ADD/SUB : 1. Pipeline Stage : which operand ist bigger ? Exchange if neccessary
// // SUB/CMP : SRC2 - SRC1
//
// reg ex_null,ma_null,ex_msb,ma_msb;
// reg [10:0] expo1,expo2;
// wire [11:0] exdiff,exdiff12;
// wire [20:0] madiff;
// wire switch,nan,sign,sign1,sign2;
// reg [5:0] shift1,shift2;
//
// // Pipeline register :
// reg [63:0] muxsrc2;
// reg [55:3] pipe1; // Nummbers for right shifter
// reg [5:0] shift;
// reg vorz,addflag;
//
// wire [52:0] muxsrc1;
// wire [32:0] lowdiff;
//
// assign nan = (SELECT[1:0] == 2'b11) ? SRCFLAGS[1] : (~SELECT[1] & (SRCFLAGS[3] | SRCFLAGS[1])); // used at the end
//
// assign exdiff = {1'b0,SRC2[30:20]} - {1'b0,SRC1[30:20]}; // Difference of Exponents
// assign madiff = {1'b0,SRC2[19:0]} - {1'b0,SRC1[19:0]}; // Difference of Mantissa
// assign exdiff12 = {1'b0,SRC1[30:20]} - {1'b0,SRC2[30:20]}; // Diff. Exponents exchanged
//
// always @(posedge BCLK)
// if (START[0])
// begin
// ex_null <= (exdiff[10:0] == 11'h0);
// ma_null <= (madiff[19:0] == 20'h0);
// ex_msb <= exdiff[11];
// ma_msb <= madiff[20];
// shift1 <= (exdiff[10:6] != 5'h0) ? 6'h3F : exdiff[5:0];
// shift2 <= (exdiff12[10:6] != 5'h0) ? 6'h3F : exdiff12[5:0];
// expo1 <= SRC1[30:20];
// expo2 <= SRC2[30:20];
// end
//
// assign lowdiff = {1'b0,SRC2} - {1'b0,SRC1}; // LSD compare
//
// assign switch = ex_msb | (ex_null & (ma_msb | (ma_null & lowdiff[32]))); // exchange ?
//
// assign muxsrc1 = switch ? {MAN2,SRC2} : {MAN1,SRC1};
//
// always @(posedge BCLK) // Pipeline Reg
// begin
// muxsrc2 <= switch ? {expo1,MAN1,SRC1} : {expo2,MAN2,SRC2}; // Incl. Exponent & "1" of mantissa
// pipe1 <= SELECT[1] ? (ganzklein ? 53'd0 : {1'b1,SRC1[19:0],SRC2}) : muxsrc1; // Feeding of R.T.F.
// shift <= SELECT[1] ? {1'b0,rexdiff[4:0]} : (switch ? shift2 : shift1);
// end
//
// // SRC2 SRC1 : switch = 0 SRC2 SRC1 : switch = 1
// // 5 + 3 : +(5 + 3) = 8 3 + 5 : +(5 + 3) = 8 SELECT[0] = 0
// // 5 + (-3) : +(5 - 3) = 2 3 + (-5) : -(5 - 3) = -2
// // (-5) + 3 : -(5 - 3) = -2 (-3) + 5 : +(5 - 3) = 2
// // (-5) + (-3) : -(5 + 3) = -8 (-3) + (-5) : -(5 + 3) = -8
// // 5 - 3 : +(5 - 3) = 2 3 - 5 : -(5 - 3) = -2 SELECT[0] = 1
// // 5 - (-3) : +(5 + 3) = 8 3 - (-5) : +(5 + 3) = 8
// // (-5) - 3 : -(5 + 3) = -8 (-3) - 5 : -(5 + 3) = -8
// // (-5) - (-3) : -(5 - 3) = -2 (-3) - (-5) : +(5 - 3) = 2
//
// assign sign1 = SRCFLAGS[4];
// assign sign2 = SRCFLAGS[5];
//
// always @(posedge BCLK) // Pipeline Reg
// begin
// vorz <= switch ? (SELECT[0] ^ sign1) : sign2;
// addflag <= ~(SELECT[0] ^ (sign1 ^ sign2));
// end
//
// // CMPF : 1. Pipeline Stage : first result : is stored one level higer in Reg
//
// assign CMPRES[1] = ~CMPRES[0] & (switch ? ~sign1 : sign2); // look table above
// assign CMPRES[0] = (ex_null & ma_null & (sign1 == sign2) & (lowdiff == 33'h0)) | (SRCFLAGS[2] & SRCFLAGS[0]);
//
// // ++++++++++++++++++++++++++++++++++
// // ADD/SUB + ROUND/TRUNC : 2. Step : Barrelshifter to the right -->
//
// wire [55:0] brshifta,brshiftb,brshiftc,brshiftd,brshifte,brshiftf;
//
// // 5..33322222222221111111111 is this picture still correct ? Took over from Single FP
// // 5..2109876543210987654321098765432-10
// // 1..VVVVVVVVVVVVVVVVVVVVVVVV0000000-00 // last 2 bit for rounding
//
// assign brshifta = shift[5] ? {32'h0, pipe1[55:33], (pipe1[32:3] != 30'h0)} : {pipe1,3'h0};
// assign brshiftb = shift[4] ? {16'h0,brshifta[55:17],(brshifta[16:0] != 17'h0)} : brshifta;
// assign brshiftc = shift[3] ? { 8'h0, brshiftb[55:9], (brshiftb[8:0] != 9'h0)} : brshiftb;
// assign brshiftd = shift[2] ? { 4'h0, brshiftc[55:5], (brshiftc[4:0] != 5'h0)} : brshiftc;
// assign brshifte = shift[1] ? { 2'h0, brshiftd[55:3], (brshiftd[2:0] != 3'h0)} : brshiftd;
// assign brshiftf = shift[0] ? { 1'b0, brshifte[55:2], (brshifte[1:0] != 2'h0)} : brshifte;
//
// // ++++++++++++++++++++++++++++++++++
// // ROUNDLi/TRUNCLi/FLOORLi : 3. Step : round to Integer
//
// reg car_ry;
// wire [1:0] inex;
// wire [30:0] compl;
// wire [31:0] iadder;
// wire restbits;
//
// assign restbits = (brshiftf[23:0] != 24'h0);
// assign inex = {brshiftf[24],restbits}; // Inexact-Flag-Data transfered to multiplexer at the end
//
// always @(SELECT or sign1 or brshiftf or restbits or inex or ganzklein)
// casex (SELECT[3:2])
// 2'b00 : car_ry = sign1 ^ (((brshiftf[25:24] == 2'b11) & ~restbits) | (inex == 2'b11)); // ROUNDLi
// 2'b1x : car_ry = sign1 ? (~ganzklein & (inex == 2'b00)) : 1'b0; // +numbers like TRUNCLi, -numbers to "-infinity" round
// default : car_ry = sign1; // TRUNCLi , simple cut off
// endcase
//
// assign compl = sign1 ? ~brshiftf[55:25] : brshiftf[55:25];
//
// assign iadder = {sign1,compl} + {31'h0,car_ry};
//
// always @(posedge BCLK) IOUT <= minint ? 32'h8000_0000 : iadder;
//
// always @(iadder or BWD or sign1) // special overflow detection i.e. -129 to -255 at Byte
// casex (BWD) // or 127.9 -> 128 = error !
// 2'b00 : ovflag2 = (iadder[8] != iadder[7]); // Byte
// 2'b01 : ovflag2 = (iadder[16] != iadder[15]); // Word
// default : ovflag2 = 1'b0;
// endcase
//
// // ++++++++++++++++++++++++++++++++++
// // ADD/SUB : 3. Step : Addition or Subtraction
//
// wire [67:0] result;
// wire [55:0] blshifti;
// wire [12:0] shiftl;
// wire shift_32;
// wire [65:0] add_q;
//
// // The central adder : the subtraction needs 3 Guard-Bits after LSB for correct rounding
// assign result = {1'b0,muxsrc2,3'b000} + (addflag ? {12'h0,brshiftf} : {12'hFFF,~brshiftf}) + {67'd0,~addflag};
//
// assign blshifti = SELECT[1] ? {movif,24'h0} : result[55:0]; // Feeding of MOViL, comes from Register
//
// assign shiftl = SELECT[1] ? 13'h041E : {1'b0,result[67:56]}; // MOViL
//
// assign shift_32 = (blshifti[55:24] == 32'h0);
//
// // In case of ADD the result bypasses the barrelshifter : LSB of exponent has changed
// assign add_q = (muxsrc2[53] != result[56]) ? {result[67:3],(result[2:0] != 3'b000)}
// : {result[67:56],result[54:2],(result[1:0] != 2'b00)} ;
//
// // ++++++++++++++++++++++++++++++++++
// // ADD/SUB : 4. Step : Barrelshifter left for SUB and MOViF :
//
// wire shift_16,shift_8,shift_4,shift_2,shift_1,zero;
// wire [1:0] lsb_bl;
// wire [55:0] blshifta,blshiftb,blshiftc,blshiftd,blshifte,blshiftf;
// wire [12:0] expol;
//
// assign blshifta = shift_32 ? {blshifti[23:0],32'h0} : blshifti;
// assign shift_16 = (blshifta[55:40] == 16'h0);
// assign blshiftb = shift_16 ? {blshifta[39:0],16'h0} : blshifta;
// assign shift_8 = (blshiftb[55:48] == 8'h00);
// assign blshiftc = shift_8 ? {blshiftb[47:0],8'h0} : blshiftb;
// assign shift_4 = (blshiftc[55:52] == 4'h0);
// assign blshiftd = shift_4 ? {blshiftc[51:0],4'h0} : blshiftc;
// assign shift_2 = (blshiftd[55:54] == 2'b00);
// assign blshifte = shift_2 ? {blshiftd[53:0],2'b0} : blshiftd;
// assign shift_1 = ~blshifte[55];
// assign blshiftf = shift_1 ? {blshifte[54:0],1'b0} : blshifte;
//
// // Overflow at ROUNDLi/TRUNCLi/FLOORLi is shown in overflow of exponent , SELECT[1] is then 1
// assign expol = shiftl - {7'h00,shift_32,shift_16,shift_8,shift_4,shift_2,shift_1};
//
// // Inexact at ROUNDLi/TRUNCLi/FLOORLi : evaluation for all one level higher
// assign lsb_bl = (SELECT == 2'b11) ? inex : {blshiftf[2],(blshiftf[1:0] != 2'b0)};
//
// assign zero = (~SELECT[1] & SRCFLAGS[2] & SRCFLAGS[0])
// | ((blshifti == 56'h0) & ((~addflag & ~SELECT[1]) | (SELECT[1:0] == 2'b10)));
//
// assign sign = SELECT[1] ? sign_movif : (vorz & ~zero); // sign for MOViL
//
// // 2. Pipeline register for ADD , SUB and MOViL
// always @(posedge BCLK)
// outreg <= (addflag & ~SELECT[1]) ? {nan,zero,sign,1'b0,add_q}
// : {nan,zero,sign,expol,blshiftf[54:3],lsb_bl};
//
// // ++++++++++++++++++++++++++++++++++
//
// assign OUT = {outreg[69:67],(rovfl ? 2'b01 : outreg[66:65]),outreg[64:0]};
//
//endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 5. DFPU_MISC Double precision floating point miscellaneous operations
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//module DFPU_MISC ( BCLK, START, SRC1, SRC2, SRCFLAG, MIMUX, MODE, OUT );
//
// input BCLK;
// input START;
// input [31:0] SRC1,SRC2;
// input SRCFLAG;
// input MIMUX;
// input [3:0] MODE;
// output [69:0] OUT;
//
// reg [69:0] OUT;
// reg [63:0] daten;
//
// wire [10:0] scalb_l;
// wire nan,zero,sign;
// wire [12:0] lexpo,sexpo;
// wire [69:0] scalb_res,logb_res,fl_lf;
//
// always @(posedge BCLK) if (START) daten <= {(MIMUX ? {daten[31],scalb_l,daten[19:0]}: SRC1),SRC2};
//
// assign nan = MODE[0] ? (daten[62:55] == 8'hFF) : (daten[62:52] == 11'h7FF);
// assign zero = MODE[0] ? (daten[62:55] == 8'h00) : (daten[62:52] == 11'h000);
// assign sign = daten[63] & ~zero;
//
// assign lexpo = {5'b0,daten[62:55]} + 13'h0380; // -7F + 3FF
//
// assign sexpo = (daten[62:52] > 11'h47E) ? 13'h0FFF
// : ((daten[62:52] < 11'h381) ? 13'h0 : {2'b0,{4{daten[62]}},daten[58:52]});
//
// assign fl_lf = MODE[0] ? {nan,zero,sign,lexpo,daten[54:32],31'h0} // MOVFL
// : {nan,zero,sign,sexpo,daten[51:29],28'h0,daten[29:28],(daten[27:0] != 28'h0)}; // MOVLF
//
// // +++++++++++++++++++++++++++ LOGBf +++++++++++++++++++++++++++++++++++
//
// wire logb_null;
// wire [9:0] sel_data,unbiased,shift_l8,shift_l4,shift_l2;
// wire [8:0] shift_l;
// wire posi_8,posi_4,posi_2,posi_1;
// wire [4:0] calc_exp;
// wire [6:0] logb_exp;
//
// assign logb_null = MODE[1] ? (daten[62:55] == 8'h7F) : (daten[62:52] == 11'h3FF);
//
// assign sel_data = MODE[1] ? {{3{~daten[62]}},daten[61:55]} : daten[61:52];
// assign unbiased = daten[62] ? (sel_data + 10'h001) : ~sel_data;
//
// // detection of leading "1"
// assign posi_8 = (unbiased[9:2] == 8'h00);
// assign shift_l8 = posi_8 ? {unbiased[1:0],8'h00} : unbiased;
// assign posi_4 = (shift_l8[9:6] == 4'h0);
// assign shift_l4 = posi_4 ? {shift_l8[5:0],4'h0} : shift_l8;
// assign posi_2 = (shift_l4[9:8] == 2'b00);
// assign shift_l2 = posi_2 ? {shift_l4[7:0],2'b0} : shift_l4;
// assign posi_1 = ~shift_l2[9];
// assign shift_l = posi_1 ? {shift_l2[7:0],1'b0} : shift_l2[8:0]; // top bit is hidden "1"
//
// assign calc_exp = 5'h08 - {1'b0,posi_8,posi_4,posi_2,posi_1}; // Minimum is "F" = for exponent +/-1 <=> 2^0
//
// // exponent is set one level higher for F and L
// assign logb_exp = MODE[1] ? {{4{~calc_exp[4]}},{3{calc_exp[4]}}} : {~calc_exp[4],{6{calc_exp[4]}}};
//
// assign logb_res = logb_null ? {70'h10_0000_0000_0000_0000} : {2'b00,~daten[62],2'b00,logb_exp,calc_exp[3:0],shift_l,45'h0};
//
// // ++++++++++++++++++++++++ SCALBf ++++++++++++++++++++++++++++++++++
//
// wire [7:0] scalb_f;
//
// assign scalb_f = SRCFLAG ? 8'h00 : (daten[39:32] + daten[30:23]);
// assign scalb_l = SRCFLAG ? 11'h000 : (daten[42:32] + daten[30:20]);
//
// assign scalb_res = MODE[1] ? // no rounding of Single Data
// {2'b00,daten[31],5'b0,scalb_f,daten[22:0],daten[28:1],3'b000}
// : {2'b00,daten[63],2'b0,daten[62:0],2'b00};
//
// // ++++++++++++++++++++++++ Output ++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// always @(posedge BCLK) OUT <= MODE[3] ? (MODE[2] ? logb_res : scalb_res) : fl_lf ; // LOGB/SCALB : MOVLF/MOVFL
//
//endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 6. DFPU_MUL Double precision floating point multiplier
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//module DFPU_MUL ( BCLK, SRC1, SRC2, START, MRESULT, SRCFLAGS, OUT );
//
// input BCLK;
// input [31:0] SRC1,SRC2;
// input START; // that is START[0]
// input [105:0] MRESULT;
// input [5:0] SRCFLAGS; // NAN and ZERO flags
// output [69:0] OUT; // The result
//
// reg [69:0] OUT;
// reg [12:0] exponent;
// wire orlow;
// wire [12:0] expoh,expol;
// wire [1:0] restlow,resthigh;
// wire zero,nan,sign;
//
// assign zero = SRCFLAGS[2] | SRCFLAGS[0]; // one is NULL -> NULL is the result
// assign nan = SRCFLAGS[3] | SRCFLAGS[1]; // one is NAN -> error
// assign sign = (SRCFLAGS[5] ^ SRCFLAGS[4]) & ~zero;
//
// assign orlow = (MRESULT[50:0] != 51'b0);
//
// assign restlow = {MRESULT[51],orlow};
// assign resthigh = {MRESULT[52],(MRESULT[51] | orlow)};
//
// always @(posedge BCLK) if (START) exponent <= {2'b00,SRC1[30:20]} + {2'b00,SRC2[30:20]};
//
// assign expoh = exponent - 13'h03FE;
// assign expol = exponent - 13'h03FF; // for MSB if MRESULT=0
//
// always @(posedge BCLK)
// OUT <= MRESULT[105] ? {nan,zero,sign,expoh,MRESULT[104:53],resthigh} // 52 Bit Mantissa
// : {nan,zero,sign,expol,MRESULT[103:52],restlow};
//
//endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 7. DIVI_PREP Prepare data for the divider
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DIVI_PREP (SRC, BWD, NOT_DEI, EXTDATA, DOUT, MSB, NULL, MINUS);
input [31:0] SRC;
input [1:0] BWD;
input NOT_DEI;
input EXTDATA;
output [31:0] DOUT;
output [4:0] MSB;
output NULL;
output MINUS;
reg [31:0] double;
wire [15:0] test_16;
wire [7:0] test_8;
wire [3:0] test_4;
wire [1:0] test_2;
wire bit_4,bit_3,bit_2,bit_1,bit_0;
wire [1:0] modus;
assign modus = (NOT_DEI | EXTDATA) ? BWD : {(BWD[1] | BWD[0]),1'b1};
always @(modus or SRC or NOT_DEI)
casex (modus)
2'b00 : double = {{24{SRC[7] & NOT_DEI}},SRC[7:0]};
2'b01 : double = {{16{SRC[15] & NOT_DEI}},SRC[15:0]};
2'b1x : double = SRC;
endcase
assign MINUS = double[31] & NOT_DEI;
assign DOUT = ({32{MINUS}} ^ double) + {31'h0,MINUS}; // assign DOUT = MINUS ? (32'd0 - double) : double;
// now find most significant set bit : FFS
assign bit_4 = (DOUT[31:16] != 16'h0);
assign test_16 = bit_4 ? DOUT[31:16] : DOUT[15:0];
assign bit_3 = (test_16[15:8] != 8'h0);
assign test_8 = bit_3 ? test_16[15:8] : test_16[7:0];
assign bit_2 = (test_8[7:4] != 4'h0);
assign test_4 = bit_2 ? test_8[7:4] : test_8[3:0];
assign bit_1 = (test_4[3:2] != 2'b0);
assign test_2 = bit_1 ? test_4[3:2] : test_4[1:0];
assign bit_0 = test_2[1];
assign NULL = (test_2 == 2'b00);
assign MSB = {bit_4,bit_3,bit_2,bit_1,bit_0};
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 8. DFPU_DIV The divider for all divide opcodes : double, single and integer
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DFPU_DIV ( BCLK, BRST, START, SRC1, SRC2, MAN1, MAN2, SRCFLAGS, FL, BWD, OPCODE, OUT, DONE, DIVI_OUT, DVZ_TRAP, DEI_OVF );
// This version needs for Double 28+1 cycles if MAN1<MAN2 otherwise 28+2.
// For Single it needs 13+1 cyckes or 13+2.
input BCLK,BRST;
input [3:0] START; // START & recognized Divider Operation
input [31:0] SRC1,SRC2; // input data
input [20:0] MAN1,MAN2;
input [5:0] SRCFLAGS; // NAN and ZERO
input FL;
input [1:0] BWD;
input [2:0] OPCODE; // for all DIVi variants
output [69:0] OUT; // the result
output reg DONE; // Pipeline-Flag
output [63:0] DIVI_OUT; // for Integer Division
output DVZ_TRAP; // Divide by Zero Trap
output [1:0] DEI_OVF; // DEI Overflow
// ++++++++++++++ for Integer Division ++++++++++++++
reg run_divi;
reg divi_pipe1,divi_pipe2,divi_pipe3,divi_pipe4;
reg neg_src1,neg_src2,nul_src2;
reg [4:0] msb_src1;
reg [5:0] msb_src2;
reg [31:0] ivalue,src2_reg,pipe_reg;
reg [4:0] divi_counter;
reg sub_case;
reg negativ;
reg [32:0] divi_result;
reg [63:0] DIVI_OUT;
reg DVZ_TRAP,dvz_pipe;
reg sel_in;
reg [62:0] din_mux;
reg dei_pipe;
reg extdata; // extended data : 2 data packets, only apply to DEI
reg [2:0] addoff;
reg next_msb2;
reg [31:0] dei_result;
reg [1:0] DEI_OVF;
wire [31:0] i_in;
wire [37:0] i_out;
wire [6:0] diff_msb;
wire [5:1] shift_r;
wire [62:0] shift_2;
wire [62:0] shift_4;
wire [62:0] shift_8;
wire [62:0] shift_16;
wire [64:0] shift_32;
wire stop_divi,neg_flag;
wire rest_null,plus_1,ist_null;
wire not_dei;
wire valdata; // Data <> 0 at DEI
// ++++++++++++++ Floating Point & calculation path ++++++++
reg [69:0] OUT;
reg [32:0] save1;
reg runflag;
reg [55:0] dreimal;
reg [56:0] divreg,divsr;
reg [31:0] divreg_ext;
reg [12:0] exponent;
wire load_src1,load_src2;
wire [56:0] sub1,sub2,sub3;
wire [32:0] src_1;
wire [20:0] man_1;
wire [12:0] expoh,expol,offset;
wire restlsb,restlow,resthigh;
wire zero,nan,sign,ende;
wire orlow_s,orlow_d;
wire short;
// +++++++++++++++++++++++++++ Integer Division, DEI +++++++++++++++++++++++++++
assign not_dei = OPCODE[2]; // 0 = DEI
always @(posedge BCLK) if (START[3]) extdata <= ~START[1]; // during START[0] for SRC1 not valid
always @(posedge BCLK or negedge BRST)
if (!BRST) run_divi <= 1'b0;
else
run_divi <= (START[3] & ~ist_null) | (~divi_pipe4 & run_divi); // Abort at DVZ Trap
always @(posedge BCLK) divi_pipe1 <= START[3] & ~ist_null; // no start if SRC1 = 0 : DVZ Trap
always @(posedge BCLK) dei_pipe <= divi_pipe1 & extdata;
always @(posedge BCLK) divi_pipe2 <= extdata ? dei_pipe : divi_pipe1;
always @(posedge BCLK) src2_reg <= SRC2;
always @(posedge BCLK) sel_in <= START[3] | divi_pipe1; // two times data for DEI
assign i_in = sel_in ? src2_reg : SRC1;
DIVI_PREP prep_inst ( .SRC(i_in), .BWD(BWD), .NOT_DEI(not_dei), .EXTDATA(extdata | START[0]),
.DOUT(i_out[31:0]), .MSB(i_out[36:32]), .NULL(ist_null), .MINUS(i_out[37]) );
always @(posedge BCLK) dvz_pipe <= START[3] & ist_null; // Pulse 1 cycle long
always @(posedge BCLK) DVZ_TRAP <= dvz_pipe; // one cycle later if DEI with extdata
always @(posedge BCLK)
if (START[3])
begin
neg_src1 <= i_out[37];
msb_src1 <= i_out[36:32];
end
always @(posedge BCLK)
if (divi_pipe1)
begin
nul_src2 <= ist_null;
neg_src2 <= i_out[37];
end
always @(posedge BCLK) ivalue <= i_out[31:0];
// The following is only for DEI :
always @(posedge BCLK) pipe_reg <= {32{extdata}} & ivalue; // Register must be 0 if not used
assign valdata = extdata & ~ist_null;
always @(BWD or valdata)
casex (BWD)
2'b00 : addoff = { 1'b0, 1'b0,valdata};
2'b01 : addoff = { 1'b0,valdata, 1'b0};
default : addoff = {valdata, 1'b0, 1'b0};
endcase
always @(posedge BCLK) next_msb2 <= extdata & ist_null & divi_pipe1; // Special case at DEI : MSD = 0
always @(posedge BCLK)
if (divi_pipe1) msb_src2 <= {addoff[2],(addoff[1:0] | i_out[36:35]),i_out[34:32]};
else
if (next_msb2) msb_src2 <= {1'b0,i_out[36:32]};
// Shifter for Source2
assign diff_msb = {1'b0,msb_src2} - {2'b0,msb_src1};
// negativ shift limited to 0 : Source2=0 calculated without special handling, result always 0
assign shift_r = diff_msb[6] ? 5'd0 : diff_msb[5:1]; // LSB does not count
always @(BWD or extdata or ivalue or pipe_reg)
casex ({BWD,extdata})
3'b0x0 : din_mux = {31'b0,ivalue}; // the normal case for all except DEI
3'b001 : din_mux = {23'b0,pipe_reg,ivalue[7:0]};
3'b011 : din_mux = {15'b0,pipe_reg,ivalue[15:0]};
default : din_mux = {pipe_reg[30:0],ivalue}; // 63 Bit wide
endcase
assign shift_2 = shift_r[1] ? din_mux : {din_mux[60:0], 2'b0};
assign shift_4 = shift_r[2] ? shift_2 : {shift_2[58:0], 4'b0};
assign shift_8 = shift_r[3] ? shift_4 : {shift_4[54:0], 8'b0};
assign shift_16 = shift_r[4] ? shift_8 : {shift_8[46:0],16'b0}; // Result is 63 Bit wide
// 65 Bit result because of DEI
assign shift_32 = shift_r[5] ? {1'b0,pipe_reg,ivalue} : {shift_16,2'b00}; // special case DEI : 32 times shift
always @(posedge BCLK or negedge BRST) // Flag for rounding, only if DEST <>0
if (!BRST) divi_pipe3 <= 1'b0;
else
divi_pipe3 <= divi_pipe2 | (divi_pipe3 & ~stop_divi);
always @(posedge BCLK)
if (divi_pipe2) divi_counter <= shift_r;
else divi_counter <= divi_counter - {4'b000,~stop_divi}; // should stop at 0
assign stop_divi = (divi_counter == 5'h0); // caclulation ready
always @(posedge BCLK) divi_pipe4 <= divi_pipe3 & stop_divi;
assign neg_flag = neg_src1 ^ neg_src2;
assign rest_null = (divreg[33:2] == 32'h0);
always @(posedge BCLK) sub_case <= neg_flag & ~nul_src2; // little help for MODi opcode
// Result preparation :
// DEST SRC QUO REM / DIV MOD
// +33 +13 : 2 7 / 2 7
// +33 -13 : -2 7 / -3 -6
// -33 +13 : -2 -7 / -3 6
// -33 -13 : 2 -7 / 2 -7
always @(*)
case (OPCODE[1:0])
2'b00 : divi_result = {neg_flag,divsr[31:0]}; // QUO
2'b01 : divi_result = {neg_src2,divreg[33:2]}; // REM
2'b10 : divi_result = {neg_src1,((sub_case & ~rest_null) ? (save1[31:0] - divreg[33:2]) : divreg[33:2])}; // MOD
2'b11 : divi_result = {neg_flag,divsr[31:0]}; // DIV
endcase
always @(posedge BCLK) negativ <= divi_result[32];
assign plus_1 = (OPCODE[1:0] == 2'b11) ? (negativ & rest_null) : negativ; // Special case Rest=0 at DIV
always @(posedge BCLK)
if (divi_pipe4) DIVI_OUT[63:32] <= not_dei ? (({32{negativ}} ^ divi_result[31:0]) + {31'd0,plus_1}) : dei_result;
always @(posedge BCLK) if (divi_pipe4) DIVI_OUT[31:0] <= divreg[33:2];
always @(extdata or BWD or divsr or divreg)
casex ({extdata,BWD})
3'b000 : dei_result = {16'hxxxx,divsr[7:0],divreg[9:2]};
3'b001 : dei_result = {divsr[15:0],divreg[17:2]};
default : dei_result = divsr[31:0];
endcase
// +++++++++++++++++++++++++++ Calculation path for Division ++++++++++++++++++++++++++++
always @(posedge BCLK or negedge BRST)
if (!BRST) runflag <= 1'b0;
else
runflag <= START[2] | (~ende & runflag);
always @(posedge BCLK) DONE <= (ende & runflag) | divi_pipe4;
assign man_1 = (FL | run_divi) ? 21'h0 : MAN1;
assign src_1 = run_divi ? {1'b0,ivalue} : ( FL ? {10'h001,SRC1[22:0]} : {SRC1,1'b0});
assign load_src1 = START[2] | divi_pipe1;
// *2 + *1
always @(posedge BCLK) if (load_src1) dreimal <= {1'b0,man_1,src_1,1'b0} + {2'b00,man_1,src_1}; // 54 Bit Reg
always @(posedge BCLK) if (load_src1) save1 <= src_1;
assign sub1 = divreg - {3'b000, man_1,save1 };
assign sub2 = divreg - {2'b00 ,man_1,save1,1'b0};
assign sub3 = divreg - {1'b0, dreimal };
assign load_src2 = START[2] | divi_pipe2;
always @(posedge BCLK)
if (load_src2) divreg <= divi_pipe2 ? {23'h0,shift_32[64:32]} : ( FL ? {34'h0_0000_0001,SRC2[22:0]} : {3'b0,MAN2,SRC2,1'b0});
else
begin
casex ({sub3[56],sub2[56],sub1[56]})
3'b0xx : divreg <= {sub3[54:0],divreg_ext[31:30]};
3'b10x : divreg <= {sub2[54:0],divreg_ext[31:30]};
3'b110 : divreg <= {sub1[54:0],divreg_ext[31:30]};
default : divreg <= {divreg[54:0],divreg_ext[31:30]};
endcase
end
always @(posedge BCLK) // Extension Register for Integer Division
if (load_src2) divreg_ext <= divi_pipe2 ? shift_32[31:0] : 32'd0;
else
divreg_ext <= {divreg_ext[29:0],2'b0};
always @(posedge BCLK)
if (load_src2) divsr <= 57'h0;
else
begin
casex ({sub3[56],sub2[56],sub1[56]})
3'b0xx : divsr <= {divsr[54:0],2'b11};
3'b10x : divsr <= {divsr[54:0],2'b10};
3'b110 : divsr <= {divsr[54:0],2'b01};
default : divsr <= {divsr[54:0],2'b00};
endcase
end
// Overflow Detection for DEI : serial calculation
always @(posedge BCLK)
if (load_src2) DEI_OVF[0] <= 1'b0;
else DEI_OVF[0] <= DEI_OVF[0] | (BWD[1] ? |divsr[33:32] : (BWD[0] ? |divsr[17:16] : |divsr[9:8]));
always @(posedge BCLK) DEI_OVF[1] <= divi_pipe4; // Timing pulse for OVF inclusiv for DIV and QUO
assign short = (SRCFLAGS[3:0] != 4'h0) & runflag;
assign ende = ((FL ? (divsr[26] | divsr[25]) : (divsr[56] | divsr[55])) & runflag) | short;
assign sign = (SRCFLAGS[4] ^ SRCFLAGS[5]) & ~zero;
assign zero = SRCFLAGS[2] & ~SRCFLAGS[0]; // SRC2 = NULL -> NULL as result
assign nan = SRCFLAGS[3] | SRCFLAGS[1] | (SRCFLAGS[2] & SRCFLAGS[0]);
// one of both NAN or both 0 -> invalid Operation
assign orlow_d = (divreg[56:27] != 29'b0) & ~zero & ~FL; // is there Rest ? [1:0] are always 0.
assign orlow_s = (divreg[26:2] != 25'b0) & ~zero;
assign restlsb = divsr[0] | orlow_s;
assign restlow = (divsr[1:0] != 2'b00) | orlow_s | orlow_d;
assign resthigh = divsr[2] | restlow;
always @(posedge BCLK) if (START[0]) exponent <= FL ? ({5'b00,SRC2[30:23]} - {5'b00,SRC1[30:23]})
: ({2'b00,SRC2[30:20]} - {2'b00,SRC1[30:20]});
assign offset = FL ? 13'h007E : 13'h03FE;
assign expoh = exponent + {offset[12:1],1'b1}; // Double = 3FF/3FE Single = 7F/7E
assign expol = exponent + offset; // in case of normalizing
always @(posedge BCLK)
if (ende && runflag)
casex ({FL,divsr[26],divsr[56]})
3'b11x : OUT <= {nan,zero,sign,expoh[9:8],expoh[7],expoh[7],expoh[7],expoh[7:0],divsr[25:3],28'b0,divsr[3:2],restlow};
3'b10x : OUT <= {nan,zero,sign,expol[9:8],expol[7],expol[7],expol[7],expol[7:0],divsr[24:2],28'b0,divsr[2:1],restlsb};
3'b0x1 : OUT <= {nan,zero,sign,expoh,divsr[55:3],resthigh};
3'b0x0 : OUT <= {nan,zero,sign,expol,divsr[54:2],restlow};
endcase
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 9. DP_LOGIK Control logic and result path for different functions
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DP_LOGIK ( BCLK, BRESET, OPCODE, SRC1, SRC2, FSR, START, MRESULT, BWD, FL, MAN1, MAN2, WR_REG, CY_IN,
COP_DONE, COP_OP, COP_IN,
DOUT, TT_DP, DP_CMP, OVF_BCD, MEI, DFLOAT, DONE, UP_DP, CLR_LSB, WREN_L, LD_OUT_L, DVZ_TRAP, COP_GO );
// Definition of output word OUT of sub-moduls : the hidden-bit of the mantissa is already gone
//
// N Z S Exponent Mantissa Round
// A E I Double : 13 Bit 52 Bit 2 Bit
// N R G Single : 10 Bit 23 Bit 2 Bit
// O N -mmmm.mmmm.mmmm.mmmm.mmmm.mmm-.-- -m.
// -F-F-F-E.EEEE.EEEE.EEEE-MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.MMMM.RR
//
// 6 6 6 6 6666 6655 5555 5555 4444 4444 4433 3333 3333 2222 2222 2211 1111 1111 0000 0000 00
// 9 8 7 6 5432 1098 7654 3210 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210 9876 5432 10
//
// Single FP delivers the exponent in a way, that it is identical for rounding :
//
// Exponent 61 - 54 => kept
// Bits 64 - 62 are filled with bit 61 , carry should come through
// Exponent 62 => Bit 65 , Overflow
// Exponent 63 => Bit 66 , Underflow
input BCLK,BRESET;
input [7:0] OPCODE;
input [31:0] SRC1,SRC2; // the input data
input [20:0] MAN1,MAN2; // the MSB of mantissa
input [8:3] FSR; // Floating Point Status Register
input [1:0] START;
input [105:0] MRESULT; // Result of multiplier
input [1:0] BWD; // Size of integer
input FL;
input WR_REG; // from DECODER
input CY_IN;
input COP_DONE; // Coprozessor Interface
input [23:0] COP_OP;
input [63:0] COP_IN;
output [63:0] DOUT;
output [4:0] TT_DP; // Trap-Info to FSR
output [2:0] DP_CMP; // CMPL result
output [3:0] OVF_BCD; // Integer Division Overflow + BCD Carry update
output MEI,DFLOAT;
output DONE,UP_DP;
output CLR_LSB,WREN_L,LD_OUT_L;
output DVZ_TRAP;
output reg COP_GO;
reg [63:0] DOUT;
reg CLR_LSB;
reg [2:0] DP_CMP;
reg [5:0] preflags;
reg [5:0] srcflags;
// reg [69:0] fpout;
wire [69:0] fpout;
reg [2:0] tt;
reg [6:0] select;
reg [4:0] wctrl;
reg [2:1] sequ;
reg misc_op;
reg misc_mux;
reg car_ry;
reg wr_part2;
reg up_flag;
reg ovf_div;
wire zexp2,zman2,zexp1,zman1,znan1;
wire make_i;
wire scalbl,go_misc;
wire op_cmp;
wire [69:0] mulout,addout,divout,miscout;
wire go_divf,go_divi,divi_ops,div_done;
wire bcd_ops,man_ops;
wire [31:0] i_out;
wire [63:0] divi_out;
wire [66:2] rund,cy_val; // Indexnumber like in xxxout
wire div_zero,overflow,underflow,inexact;
wire [1:0] cmpres;
wire [63:0] fp_out,fp_res;
wire wr_part1;
wire done_i;
wire [31:0] bcd_q;
wire bcd_done;
wire bcd_carry;
wire [1:0] dei_ovf;
wire quo_div;
wire copop;
wire copwr;
// Control of datapath : together with START the Double Unit becomes activ
always @(OPCODE or FL)
casex (OPCODE)
8'b1001_000x : select = 7'b00_01010; // 0 1 0 : MOViL
8'b1001_010x : select = 7'b10_11000; // MOVLF
8'b1001_011x : select = 7'b01_11000; // MOVFL
8'b1001_100x : select = 7'b10_01011; // 0 1 1 : ROUNDLi
8'b1001_101x : select = 7'b10_01011; // 0 1 1 : TRUNCLi
8'b1001_111x : select = 7'b10_01011; // 0 1 1 : FLOORLi
8'b1011_0000 : select = 7'bxx_01000; // 0 0 0 : ADDL
8'b1011_0010 : select = 7'bxx_01001; // 0 0 1 : CMPL
8'b1011_0100 : select = 7'bxx_01001; // 0 0 1 : SUBL
8'b1011_1000 : select = 7'b11_01100; // 1 0 1 : DIVf , Default Float for srcflags
8'b1011_1100 : select = 7'bxx_01100; // 1 0 0 : MULL
8'b1011_0110 : select = 7'b11_11000; // SCALBf , Default Float for srcflags
8'b1011_0111 : select = {~FL,FL,5'b11000}; // LOGBf
default : select = 7'b0;
endcase
assign MEI = (OPCODE == 8'h79);
assign divi_ops = (OPCODE[7:2] == 6'b0111_11) | (OPCODE == 8'h7B); // QUO/REM/MOD/DIV & DEI
assign go_divf = (OPCODE == 8'hB8) & START[1]; // because of runflag in DIV Unit
assign go_divi = divi_ops & (OPCODE[2] ? START[1] : START[0]); // DEI starts with START[0]
assign bcd_ops = (OPCODE == 8'h6F) | (OPCODE == 8'h6B); // ADDP , SUBP
assign man_ops = (OPCODE == 8'hB1) | (OPCODE == 8'hB5) | (OPCODE == 8'hB9) | (OPCODE == 8'hBD); // MOVf,NEGf,XXXf,ABSf
assign DFLOAT = (select[3] | copop) & ~FL; // all Double Floating Point Operations for PREPDATA
assign make_i = (select[2:0] == 3'b011) | divi_ops | bcd_ops; // ROUND/TRUNC/FLOOR for output multiplexer
assign op_cmp = (OPCODE == 8'hB2) & ~FL;
always @(posedge BCLK) misc_op <= select[4]; // for OUT-Multiplexer
assign copop = (OPCODE == 8'hDD);
assign copwr = (COP_OP[18:17] == 2'd0) & (COP_OP[13:11] == 3'b111) & (COP_OP[7:5] == 3'b001); // Custom Convert
// very special solution for SCALBL
assign scalbl = START[0] & ~FL & (OPCODE == 8'hB6);
assign go_misc = START[1] | scalbl;
always @(posedge BCLK) misc_mux <= scalbl; // switches at START[1] the input multiplexer
// SRCFLAGS : special handling for operands is done locally
assign zexp2 = (SRC2[30:20] == 11'd0);
assign zman2 = (SRC2[19:0] == 20'd0);
assign zexp1 = (SRC1[30:20] == 11'd0);
assign zman1 = (SRC1[19:0] == 20'd0);
assign znan1 = (SRC1[30:20] == 11'h7FF);
always @(posedge BCLK)
if (START[0])
begin
srcflags[5] <= SRC2[31];
srcflags[4] <= SRC1[31];
preflags <= {(SRC2[30:20] == 11'h7FF),zexp2,zman2,znan1,zexp1,zman1};
end
// case Definition : 00 : 0 , if START[i]=0 then there are always 2 long operands
// 01 : 1 Float Operand SCR1
// 10 : 1 Long Operand SRC1+SRC2
// 11 : 2 Float Operands SRC1 , SRC2
always @(posedge BCLK) // NaN
if (START[1])
casex ({START[0],select[6:5]})
3'b0xx : srcflags[3] <= preflags[5] | (preflags[4] & (~preflags[3] | SRC2[31] | ~zexp2 | ~zman2));
3'b111 : srcflags[3] <= (SRC2[30:23] == 8'hFF) | ((SRC2[30:23] == 8'd0) & ((SRC2[22:20] != 3'd0) | ~zman2)); // F:SRC2 = NaN
default : srcflags[3] <= 1'b0;
endcase
always @(posedge BCLK) // Zero : only exponent ! If denormalized => NaN !
if (START[0])
casex ({START[1],select[6:5]})
3'b0xx : srcflags[2] <= zexp2; // L:(SRC1,SRC2) = Zero , SRC1 = MSB
3'b111 : srcflags[2] <= (SRC2[30:23] == 8'd0); // F:SRC2 = Zero
default : srcflags[2] <= 1'b0;
endcase
always @(posedge BCLK) // NaN
if (START[1])
casex ({START[0],select[6:5]})
3'b0xx : srcflags[1] <= preflags[2] | (preflags[1] & (~preflags[0] | SRC1[31] | ~zexp1 | ~zman1));
3'b1x1 : srcflags[1] <= (SRC1[30:23] == 8'hFF) | ((SRC1[30:23] == 8'd0) & ((SRC1[22:20] != 3'd0) | ~zman1)); // F:SRC1 = NaN
3'b110 : srcflags[1] <= znan1 | (zexp1 & (~zman1 | SRC2[31] | ~zexp2 | ~zman2)); // L:(SRC1,SRC2) = NaN , SRC1 = MSB
default : srcflags[1] <= 1'b0;
endcase
always @(posedge BCLK) // Zero : only exponent ! If denormalized => NaN !
if (START[0])
casex ({START[1],select[6:5]})
3'b0xx : srcflags[0] <= zexp1; // L:(SRC1,SRC2) = Zero , SRC1 = MSB
3'b1x1 : srcflags[0] <= (SRC1[30:23] == 8'd0); // F:SRC1 = Zero
3'b110 : srcflags[0] <= zexp1; // L:(SRC1,SRC2) = Zero , SRC1 = MSB
default : srcflags[0] <= 1'b0;
endcase
// The Sub-moduls :
// DFPU_ADDSUB as_inst ( .BCLK(BCLK), .START(START), .SRC1(SRC1), .SRC2(SRC2),
// .MAN1({~srcflags[0],MAN1[19:0]}), .MAN2({~srcflags[2],MAN2[19:0]}),
// .SRCFLAGS(srcflags), .BWD(BWD), .SELECT({OPCODE[2:1],select[1:0]}),
// .OUT(addout), .IOUT(i_out), .CMPRES(cmpres) );
assign addout = 70'b0;
assign i_out = 32'b0;
assign cmpres = 2'b0;
// DFPU_MUL mul_inst ( .BCLK(BCLK), .SRC1(SRC1), .SRC2(SRC2), .START(START[0]), .MRESULT(MRESULT),
// .OUT(mulout), .SRCFLAGS(srcflags) );
assign mulout = 70'b0;
DFPU_DIV div_inst ( .BCLK(BCLK), .BRST(BRESET), .START({go_divi,go_divf,START}), .SRC1(SRC1), .SRC2(SRC2),
.MAN1(MAN1), .MAN2(MAN2), .SRCFLAGS(srcflags), .FL(FL), .OUT(divout), .DONE(div_done),
.BWD(BWD), .OPCODE(OPCODE[2:0]), .DIVI_OUT(divi_out), .DVZ_TRAP(DVZ_TRAP), .DEI_OVF(dei_ovf) );
// DFPU_MISC misc_inst ( .BCLK(BCLK), .START(go_misc), .SRC1(SRC1), .SRC2(SRC2), .SRCFLAG(srcflags[2]),
// .MIMUX(misc_mux), .MODE({OPCODE[5],OPCODE[0],FL,OPCODE[1]}), .OUT(miscout) );
assign miscout = 70'b0;
DFPU_BCD bcd_inst ( .BCLK(BCLK), .BRESET(BRESET), .START(START[1]), .DO_BCD(bcd_ops), .BWD(BWD), .SRC1(SRC1), .SRC2(SRC2),
.CY_IN(CY_IN), .SUBP(~OPCODE[2]), .BCD_Q(bcd_q), .CY_OUT(bcd_carry), .BCD_DONE(bcd_done) );
// FP - path : selection of result and rounding :
// always @(misc_op or OPCODE or mulout or addout or divout or miscout)
// casex ({misc_op,OPCODE[5],OPCODE[3:2]}) //OPCODE[5] only for Flags i.e. NAN
// 4'b1xxx : fpout = miscout; // for MOVLF,MOVFL,SCALB & LOGB
// 4'b0110 : fpout = divout;
// 4'b0111 : fpout = mulout;
// default : fpout = addout;
// endcase
assign fpout = 70'd0;
always @(FSR or fpout) // Calculation of Carry according to rounding mode, fpout[67] = sign bit
casex (FSR[8:7])
2'b00 : car_ry = ((fpout[1:0] == 2'b10) & fpout[2]) | (fpout[1:0] == 2'b11); // round to nearest
2'b10 : car_ry = ~fpout[67] & (fpout[1:0] != 2'b00); // round to positiv infinity
2'b11 : car_ry = fpout[67] & (fpout[1:0] != 2'b00); // round to negativ infinity
default : car_ry = 1'b0; // round to zero
endcase
assign cy_val = {35'h0,(FL & car_ry),28'h0,(~FL & car_ry)};
assign rund = {fpout[66:2]} + cy_val;
// Detection of Div-by-0, Overflow, Underflow and Inexact : Epxonent from [66:54] = 13 Bits
assign div_zero = (srcflags[3:0] == 4'h1) & (OPCODE == 8'hB8); // true FPU Divide by Zero
assign overflow = ~rund[66] & (rund[65] | (rund[64:54] == 11'h7FF));
assign underflow = (rund[66] | (rund[65:54] == 12'h0)) & ~fpout[68]; // Zero-Flag
assign inexact = (fpout[1:0] != 2'b00);
always @(fpout or op_cmp or div_zero or overflow or underflow or inexact or FSR)
casex ({fpout[69],op_cmp,div_zero,overflow,FSR[3],underflow,FSR[5],inexact}) // [69] = NAN
8'b1xxxxxxx : tt = 3'b101; // Invalid operation
8'b001xxxxx : tt = 3'b011; // Divide by Zero
8'b0001xxxx : tt = 3'b010; // Overflow
8'b000011xx : tt = 3'b001; // Underflow
8'b00000011 : tt = 3'b110; // Inexact Result
default : tt = 3'b000; // no error
endcase
assign TT_DP = man_ops ? 5'd0 : {(inexact & ~op_cmp),(underflow & ~op_cmp),tt}; // at ABSf/NEGf no error : different to NS32381 !
assign fp_res = FL ? {fpout[67],rund[61:31],rund[33:2]}
: {fpout[67],rund[64:2]}; // lower 32 bits identical
// Underflow special case and get ZERO
assign fp_out = (underflow | fpout[68]) ? 64'h0 : fp_res;
// 63..32 goes to memory if Word or Byte ! Also in ODD Register , 31..0 goes in EVEN Register
// DEI comes without WR_REG information
always @(make_i or copop or MEI or BWD or WR_REG or MRESULT or COP_IN or i_out or fp_out or divi_ops or divi_out or bcd_ops or bcd_q)
casex ({make_i,copop,MEI,BWD})
5'b00100 : DOUT = {MRESULT[31:8], (WR_REG ? MRESULT[15:8] : MRESULT[7:0]), MRESULT[31:0]}; // LSD always the same
5'b00101 : DOUT = {MRESULT[31:16],(WR_REG ? MRESULT[31:16] : MRESULT[15:0]),MRESULT[31:0]};
5'b0011x : DOUT = MRESULT[63:0];
5'b01xxx : DOUT = COP_IN; // true alignment in Coprocessor
5'b1xxxx : DOUT = divi_ops ? divi_out : {(bcd_ops ? bcd_q : i_out),fp_out[31:0]}; // MSD is written first
default : DOUT = fp_out;
endcase
always @(posedge BCLK) DP_CMP <= {(srcflags[3] | srcflags[1]),cmpres}; // Only valid if not NaN
// Pipeline Control + Registerfile write control
always @(posedge BCLK or negedge BRESET)
if (!BRESET) sequ <= 2'b00;
else
sequ <= {(sequ[1] & ~DONE),START[1]};
always @(FL or OPCODE or copwr)
casex ({FL,OPCODE}) // WRITE Control : [2] = clr_lsb, [1] = wr_part2, [0] = wr_part1
9'bx_1001_000x : wctrl = 5'b01_111; // MOViL
9'bx_1001_010x : wctrl = 5'b00_010; // MOVLF
9'bx_1001_011x : wctrl = 5'b01_111; // MOVFL
9'bx_1001_100x : wctrl = 5'b00_010; // ROUNDLi - DONE is one cycle earlier for this opcodes
9'bx_1001_101x : wctrl = 5'b00_010; // TRUNCLi
9'bx_1001_111x : wctrl = 5'b00_010; // FLOORLi
9'bx_1011_0000 : wctrl = 5'b01_111; // ADDL
9'bx_1011_0010 : wctrl = 5'b00_000; // CMPL - via LD one cycle later in PSR
9'bx_1011_0100 : wctrl = 5'b01_111; // SUBL
9'b1_1011_1000 : wctrl = 5'b10_001; // DIVF - measured 18 cycles Reg-Reg
9'b0_1011_1000 : wctrl = 5'b10_111; // DIVL - measured 34 cycles Reg-Reg
9'bx_1011_1100 : wctrl = 5'b01_111; // MULL
9'bx_0110_1x11 : wctrl = 5'b10_001; // ADDP,SUBP
9'bx_0111_1001 : wctrl = 5'b00_111; // MEIi
9'bx_0111_1011 : wctrl = 5'b10_111; // DEIi
9'bx_0111_11xx : wctrl = 5'b10_001; // QUOi,REMi,MODi,DIVi
9'b1_1011_011x : wctrl = 5'b00_010; // SCALBF/LOGBF
9'b0_1011_011x : wctrl = 5'b01_111; // SCALBL/LOGBL
9'bx_1101_1101 : wctrl = {4'b10_00,copwr}; // execute coprocessor opcode
default : wctrl = 5'b0;
endcase
assign done_i = wctrl[4] ? (div_done | bcd_done | COP_DONE) : ( (wctrl[3] | ~WR_REG) ? sequ[2] : sequ[1] );
assign DONE = ~START[1] & done_i; // DONE is valid for all opcodes
assign wr_part1 = DONE & WR_REG & wctrl[0];
always @(posedge BCLK) CLR_LSB <= DONE & WR_REG & wctrl[2];
always @(posedge BCLK) wr_part2 <= DONE & WR_REG & wctrl[1];
assign WREN_L = wr_part1 | wr_part2;
assign LD_OUT_L = DONE & ~WR_REG; // meaning is "Load Out-Reg from Long-Path"
always @(posedge BCLK) up_flag <= DONE & ~wctrl[0]; // DONE one cycle later
assign UP_DP = (select[3] & (wctrl[0] ? DONE : up_flag)) | man_ops; // Update FSR Trap etc. : all FPU opcodes of DP_FPU
// Overflow Trap for Division : DEI, QUO, DIV
assign quo_div = (OPCODE == 8'h7C) | (OPCODE == 8'h7F);
always @(*)
casex ({OPCODE[2],BWD})
3'b100 : ovf_div = (divi_out[39] & SRC1[7] & SRC2[7] ) & quo_div;
3'b101 : ovf_div = (divi_out[47] & SRC1[15] & SRC2[15]) & quo_div;
3'b11x : ovf_div = (divi_out[63] & SRC1[31] & SRC2[31]) & quo_div;
default : ovf_div = dei_ovf[0] & (OPCODE == 8'h7B); // DEI
endcase
assign OVF_BCD = {dei_ovf[1],ovf_div,bcd_done,bcd_carry}; // to I_PFAD
always @(posedge BCLK) COP_GO <= START[1] & copop;
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 10. DP_FPU Top level of long operations datapath
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DP_FPU( BCLK, FL, BRESET, LD_LDQ, WR_REG, BWD, FSR, OPCODE, SRC1, SRC2, START, DONE, UP_DP, WREN_L,
CLR_LSB, LD_OUT_L, DVZ_TRAP, DP_CMP, DP_OUT, DP_Q, TT_DP, CY_IN, OVF_BCD, COP_GO, COP_OP,
COP_IN, COP_DONE, COP_OUT );
input BCLK;
input FL;
input BRESET;
input LD_LDQ;
input WR_REG;
input [1:0] BWD;
input [8:3] FSR;
input [7:0] OPCODE;
input [31:0] SRC1;
input [31:0] SRC2;
input [1:0] START;
input CY_IN;
input COP_DONE;
input [23:0] COP_OP;
input [63:0] COP_IN;
output DONE;
output UP_DP;
output WREN_L;
output CLR_LSB;
output LD_OUT_L;
output DVZ_TRAP;
output [2:0] DP_CMP;
output [31:0] DP_OUT;
output [31:0] DP_Q;
output [4:0] TT_DP;
output [3:0] OVF_BCD;
output COP_GO;
output [127:0] COP_OUT;
reg [52:0] MDA;
reg [52:0] MDB;
reg [31:0] DP_Q;
reg [31:20] RCOPA,RCOPB;
wire [63:0] DOUT;
wire [105:0] MRESULT;
wire MEI;
wire DFLOAT;
wire LOAD_MSD;
wire LOAD_LSD1;
wire LOAD_LSD2;
wire [31:0] LSD_1;
wire [31:0] LSD_2;
wire [52:32] MSD_1;
wire [52:32] MSD_2;
DP_LOGIK DOUBLE_U(
.FL(FL),
.BRESET(BRESET),
.BCLK(BCLK),
.WR_REG(WR_REG),
.BWD(BWD),
.FSR(FSR),
.MAN1(MDA[52:32]),
.MAN2(MDB[52:32]),
.MRESULT(MRESULT),
.OPCODE(OPCODE),
.SRC1(SRC1),
.SRC2(SRC2),
.START(START),
.MEI(MEI),
.DFLOAT(DFLOAT),
.DONE(DONE),
.UP_DP(UP_DP),
.CLR_LSB(CLR_LSB),
.WREN_L(WREN_L),
.LD_OUT_L(LD_OUT_L),
.DVZ_TRAP(DVZ_TRAP),
.DOUT(DOUT),
.DP_CMP(DP_CMP),
.TT_DP(TT_DP),
.CY_IN(CY_IN),
.OVF_BCD(OVF_BCD),
.COP_DONE(COP_DONE),
.COP_OP(COP_OP),
.COP_IN(COP_IN),
.COP_GO(COP_GO));
PREPDATA DP_PREP(
.MEI(MEI),
.DFLOAT(DFLOAT),
.BWD(BWD),
.SRC1(SRC1),
.SRC2(SRC2),
.START(START),
.LOAD_LSD1(LOAD_LSD1),
.LOAD_LSD2(LOAD_LSD2),
.LOAD_MSD(LOAD_MSD),
.LSD_1(LSD_1),
.LSD_2(LSD_2),
.MSD_1(MSD_1),
.MSD_2(MSD_2));
assign MRESULT = {21'd0,MDA[31:0]} * {21'd0,MDB[31:0]}; // unsigned multiplier 53 * 53 bits = 106 bits
assign DP_OUT = CLR_LSB ? DP_Q : DOUT[63:32];
always@(posedge BCLK) if (LD_OUT_L || LD_LDQ || WREN_L) DP_Q <= LD_LDQ ? SRC2 : DOUT[31:0];
always@(posedge BCLK) if (LOAD_LSD1) MDA[31:0] <= LSD_1;
always@(posedge BCLK) if (LOAD_LSD2) MDB[31:0] <= LSD_2;
always@(posedge BCLK)
if (LOAD_MSD)
begin
MDA[52:32] <= MSD_1;
MDB[52:32] <= MSD_2;
RCOPA <= SRC1[31:20];
RCOPB <= SRC2[31:20];
end
assign COP_OUT = {RCOPA,MDA[51:32],SRC1,RCOPB,MDB[51:32],SRC2};
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:44:26 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_sw_0/system_axi_gpio_sw_0_stub.v
// Design : system_axi_gpio_sw_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2016.4" *)
module system_axi_gpio_sw_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i, gpio2_io_i)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[3:0],gpio2_io_i[3:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output ip2intc_irpt;
input [3:0]gpio_io_i;
input [3:0]gpio2_io_i;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__AND2B_BEHAVIORAL_PP_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2B_BEHAVIORAL_PP_V |
/*************************************************************************
* *
* Copyright (C) 2016,2017 Alves, Fredy. *
* All rights reserved. Email: [email protected] *
* *
* This design is free software; you can redistribute it and/or *
* modify it under the terms of EITHER: *
* (1) The GNU Lesser General Public License as published by the Free *
* Software Foundation; either version 2.1 of the License, or (at *
* your option) any later version. The text of the GNU Lesser *
* General Public License is included with this design in the *
* file LICENSE. *
* *
* This design is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the files *
* LICENSE.TXT and LICENSE-BSD.TXT for more details. *
* *
*************************************************************************/
module dCalcVectorLength3
(
input CLK,
input [31:0] a1,
input [31:0] a2,
input [31:0] a3,
input [31:0] b1,
input [31:0] b2,
input [31:0] b3,
input RST,
output reg [31:0] res,
output reg out_rdy
);
wire CLK2;
wire [31:0] out_mult1;
wire output_z_ack_wire;
wire done_mult1;
wire input_a_ack_wire;
wire input_b_ack_wire;
wire [31:0] out_mult2;
wire output_z_ack_wire1;
wire done_mult2;
wire input_a_ack_wire1;
wire input_b_ack_wire1;
wire [31:0] out_mult3;
wire output_z_ack_wire2;
wire done_mult3;
wire input_a_ack_wire2;
wire input_b_ack_wire2;
wire [31:0] resultadd3;
reg resetadd3 = 1'b1;
wire out_rdy_adder;
reg resetsqrt = 1'b1;
wire iddle;
wire [31:0] rootcalc;
wire out_rdy_sqrt;
assign CLK2 = (done_mult1 & done_mult2 & done_mult3) ? 1:0;
mult_comb mult1 (
.clk_en ( 1'b1 ),
.clock ( CLK ),
.dataa (a1),
.datab (b1),
.result ( out_mult1 ),
.reset(RST),
.done(done_mult1)
);
mult_comb mult2 (
.clk_en ( 1'b1 ),
.clock ( CLK ),
.dataa (a2),
.datab (b2),
.result ( out_mult2 ),
.reset(RST),
.done(done_mult2)
);
mult_comb mult3 (
.clk_en ( 1'b1 ),
.clock ( CLK ),
.dataa (a3),
.datab (b3),
.result ( out_mult3 ),
.reset(RST),
.done(done_mult3)
);
add3 adder
(
.CLK(CLK),
.a1(out_mult1),
.a2(out_mult2),
.a3(out_mult3),
.reset(resetadd3),
.result(resultadd3),
.out_rdy(out_rdy_adder)
);
approx_fp_sqrt sqrt(
.in(resultadd3),
.out(rootcalc)
);
always @(posedge CLK2 or posedge out_rdy_adder or posedge out_rdy_sqrt or negedge RST)
begin
if(RST == 1'b0)
begin
resetadd3 <= 1'b0;
resetsqrt <= 1'b0;
out_rdy <= 1'b0;
end
else
begin
if(CLK2)
begin
resetadd3 <= 1'b1;
end
if(out_rdy_adder)
begin
resetsqrt <= 1'b1;
res <= rootcalc;
out_rdy <= 1'b1;
end
end
end
endmodule
|
/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI stream to Avalon-ST
*/
module axis2avst #(
parameter DATA_WIDTH = 8,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH),
parameter BYTE_REVERSE = 0
)
(
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] axis_tdata,
input wire [KEEP_WIDTH-1:0] axis_tkeep,
input wire axis_tvalid,
output wire axis_tready,
input wire axis_tlast,
input wire axis_tuser,
input wire avst_ready,
output wire avst_valid,
output wire [DATA_WIDTH-1:0] avst_data,
output wire avst_startofpacket,
output wire avst_endofpacket,
output wire [EMPTY_WIDTH-1:0] avst_empty,
output wire avst_error
);
parameter BYTE_WIDTH = KEEP_ENABLE ? DATA_WIDTH / KEEP_WIDTH : DATA_WIDTH;
reg frame_reg = 1'b0;
generate
genvar n;
if (BYTE_REVERSE) begin : rev
for (n = 0; n < KEEP_WIDTH; n = n + 1) begin
assign avst_data[n*BYTE_WIDTH +: BYTE_WIDTH] = axis_tdata[(KEEP_WIDTH-n-1)*BYTE_WIDTH +: BYTE_WIDTH];
end
end else begin
assign avst_data = axis_tdata;
end
endgenerate
reg [EMPTY_WIDTH-1:0] empty;
assign avst_empty = empty;
integer k;
always @* begin
empty = KEEP_WIDTH-1;
for (k = 0; k < KEEP_WIDTH; k = k + 1) begin
if (axis_tkeep[k]) begin
empty = KEEP_WIDTH-1-k;
end
end
end
assign avst_valid = axis_tvalid;
assign avst_startofpacket = axis_tvalid & !frame_reg;
assign avst_endofpacket = axis_tlast;
assign avst_error = axis_tuser;
assign axis_tready = avst_ready;
always @(posedge clk) begin
if (axis_tvalid && axis_tready) begin
frame_reg <= !axis_tlast;
end
if (rst) begin
frame_reg <= 1'b0;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_app_v6.v
// Version : 2.4
//--
//-- Description: PCI Express Endpoint sample application
//-- design.
//--
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
`define PCI_EXP_EP_OUI 24'h000A35
`define PCI_EXP_EP_DSN_1 {{8'h1},`PCI_EXP_EP_OUI}
`define PCI_EXP_EP_DSN_2 32'h00000001
module pcie_app_v6#(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
)(
input user_clk,
input user_reset,
input user_lnk_up,
// Tx
input [5:0] tx_buf_av,
input tx_cfg_req,
input tx_err_drop,
output tx_cfg_gnt,
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output [3:0] s_axis_tx_tuser,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
// Rx
output rx_np_ok,
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
// Flow Control
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
// CFG
input [31:0] cfg_do,
input cfg_rd_wr_done,
output [31:0] cfg_di,
output [3:0] cfg_byte_en,
output [9:0] cfg_dwaddr,
output cfg_wr_en,
output cfg_rd_en,
output cfg_err_cor,
output cfg_err_ur,
output cfg_err_ecrc,
output cfg_err_cpl_timeout,
output cfg_err_cpl_abort,
output cfg_err_cpl_unexpect,
output cfg_err_posted,
output cfg_err_locked,
output [47:0] cfg_err_tlp_cpl_header,
input cfg_err_cpl_rdy,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_turnoff_ok,
input cfg_to_turnoff,
output cfg_trn_pending,
output cfg_pm_wake,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number,
input [15:0] cfg_status,
input [15:0] cfg_command,
input [15:0] cfg_dstatus,
input [15:0] cfg_dcommand,
input [15:0] cfg_lstatus,
input [15:0] cfg_lcommand,
input [15:0] cfg_dcommand2,
input [2:0] cfg_pcie_link_state,
output [1:0] pl_directed_link_change,
input [5:0] pl_ltssm_state,
output [1:0] pl_directed_link_width,
output pl_directed_link_speed,
output pl_directed_link_auton,
output pl_upstream_prefer_deemph,
input [1:0] pl_sel_link_width,
input pl_sel_link_rate,
input pl_link_gen2_capable,
input pl_link_partner_gen2_supported,
input [2:0] pl_initial_link_width,
input pl_link_upcfg_capable,
input [1:0] pl_lane_reversal_mode,
input pl_received_hot_rst,
output [63:0] cfg_dsn
);
//
// Core input tie-offs
//
assign fc_sel = 3'b0;
assign rx_np_ok = 1'b1;
assign s_axis_tx_tuser[0] = 1'b0; // Unused for V6
assign s_axis_tx_tuser[1] = 1'b0; // Error forward packet
assign s_axis_tx_tuser[2] = 1'b0; // Stream packet
assign tx_cfg_gnt = 1'b1;
assign cfg_err_cor = 1'b0;
assign cfg_err_ur = 1'b0;
assign cfg_err_ecrc = 1'b0;
assign cfg_err_cpl_timeout = 1'b0;
assign cfg_err_cpl_abort = 1'b0;
assign cfg_err_cpl_unexpect = 1'b0;
assign cfg_err_posted = 1'b0;
assign cfg_err_locked = 1'b0;
assign cfg_pm_wake = 1'b0;
assign cfg_trn_pending = 1'b0;
assign cfg_interrupt_assert = 1'b0;
assign cfg_interrupt = 1'b0;
assign cfg_dwaddr = 0;
assign cfg_rd_en = 0;
assign pl_directed_link_change = 0;
assign pl_directed_link_width = 0;
assign pl_directed_link_speed = 0;
assign pl_directed_link_auton = 0;
assign pl_upstream_prefer_deemph = 1'b1;
assign cfg_interrupt_di = 8'b0;
assign cfg_err_tlp_cpl_header = 48'h0;
assign cfg_di = 0;
assign cfg_byte_en = 4'h0;
assign cfg_wr_en = 0;
assign cfg_dsn = {`PCI_EXP_EP_DSN_2, `PCI_EXP_EP_DSN_1};
//
// Programmable I/O Module
//
wire [15:0] cfg_completer_id = { cfg_bus_number, cfg_device_number, cfg_function_number };
wire cfg_bus_mstr_enable = cfg_command[2];
PIO #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) PIO (
.user_clk ( user_clk ), // I
.user_reset ( user_reset ), // I
.user_lnk_up ( user_lnk_up ), // I
.s_axis_tx_tready ( s_axis_tx_tready ), // I
.s_axis_tx_tdata ( s_axis_tx_tdata ), // O
.s_axis_tx_tkeep ( s_axis_tx_tkeep ), // O
.s_axis_tx_tlast ( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid ( s_axis_tx_tvalid ), // O
.tx_src_dsc ( s_axis_tx_tuser[3] ), // O
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tkeep( m_axis_rx_tkeep ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
.cfg_to_turnoff ( cfg_to_turnoff ), // I
.cfg_turnoff_ok ( cfg_turnoff_ok ), // O
.cfg_completer_id ( cfg_completer_id ), // I [15:0]
.cfg_bus_mstr_enable (cfg_bus_mstr_enable ) // I
);
endmodule // pcie_app
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O2BB2A_PP_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__TAP_PP_SYMBOL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tap (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAP_PP_SYMBOL_V
|
// megafunction wizard: %LPM_MULT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsquare
// ============================================================
// File Name: MULT_FIRSQ.v
// Megafunction Name(s):
// altsquare
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module MULT_FIRSQ (
dataa,
result);
input [29:0] dataa;
output [59:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "0"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "30"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "60"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: DATA_WIDTH NUMERIC "30"
// Retrieval info: CONSTANT: LPM_TYPE STRING "ALTSQUARE"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
// Retrieval info: CONSTANT: REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: RESULT_WIDTH NUMERIC "60"
// Retrieval info: USED_PORT: dataa 0 0 30 0 INPUT NODEFVAL "dataa[29..0]"
// Retrieval info: USED_PORT: result 0 0 60 0 OUTPUT NODEFVAL "result[59..0]"
// Retrieval info: CONNECT: @data 0 0 30 0 dataa 0 0 30 0
// Retrieval info: CONNECT: result 0 0 60 0 @result 0 0 60 0
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_FIRSQ.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_FIRSQ.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_FIRSQ.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_FIRSQ.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_FIRSQ_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MULT_FIRSQ_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_PP_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y , nor0_out, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2OI_BEHAVIORAL_PP_V |
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* DEBUG INTERFACE */
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - CPU Control features. */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
/*===========================================================================*/
integer test_nr;
integer test_var;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
`ifdef DBG_EN
`ifdef DBG_UART
`ifdef ASIC_CLOCKING
tb_skip_finish("| (this test is not supported in ASIC mode) |");
`else
test_nr = 0;
#1 dbg_en = 0;
repeat(30) @(posedge mclk);
stimulus_done = 0;
// Make sure the CPU always starts executing when the
// debug interface is disabled during POR.
//--------------------------------------------------------
dbg_en = 0;
test_nr = 1;
repeat(300) @(posedge mclk);
if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 =====");
test_var = r14;
// Make sure that enabling the debug interface after the POR
// don't stop the cpu
//--------------------------------------------------------
dbg_en = 1;
test_nr = 2;
repeat(300) @(posedge mclk);
if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 2 =====");
// Create POR with debug enable and observe the
// behavior depending on the DBG_RST_BRK_EN define
//--------------------------------------------------------
dbg_en = 1;
test_nr = 3;
@(posedge mclk); // Generate POR
reset_n = 1'b0;
@(posedge mclk);
reset_n = 1'b1;
repeat(300) @(posedge mclk);
`ifdef DBG_RST_BRK_EN
if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 =====");
`else
if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 =====");
`endif
// Send uart synchronization frame
dbg_uart_tx(DBG_SYNC);
// Check CPU_CTL reset value
dbg_uart_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
`else
if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
`endif
// Make sure that DBG_EN resets the debug interface
//--------------------------------------------------------
test_nr = 4;
// Let the CPU run
dbg_uart_wr(CPU_CTL, 16'h0002);
repeat(300) @(posedge mclk);
dbg_uart_wr(CPU_CTL, 16'h0000);
dbg_uart_wr(MEM_DATA, 16'haa55);
dbg_uart_rd(CPU_CTL);
if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 =====");
dbg_uart_rd(MEM_DATA);
if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 =====");
test_var = r14; // Backup the current register value
@(posedge mclk); // Resets the debug interface
dbg_en = 1'b0;
repeat(2) @(posedge mclk);
dbg_en = 1'b1;
// Make sure that the register was not reseted
if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 =====");
repeat(2) @(posedge mclk);
// Send uart synchronization frame
dbg_uart_tx(DBG_SYNC);
// Check CPU_CTL reset value
dbg_uart_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`else
if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`endif
dbg_uart_rd(MEM_DATA);
if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
// Make sure that RESET_N resets the debug interface
//--------------------------------------------------------
test_nr = 5;
// Let the CPU run
dbg_uart_wr(CPU_CTL, 16'h0002);
repeat(300) @(posedge mclk);
dbg_uart_wr(CPU_CTL, 16'h0000);
dbg_uart_wr(MEM_DATA, 16'haa55);
dbg_uart_rd(CPU_CTL);
if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 =====");
dbg_uart_rd(MEM_DATA);
if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 =====");
test_nr = 6;
@(posedge mclk); // Generates POR
reset_n = 1'b0;
repeat(2) @(posedge mclk);
reset_n = 1'b1;
// Make sure that the register was reseted
if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 =====");
repeat(2) @(posedge mclk);
// Send uart synchronization frame
dbg_uart_tx(DBG_SYNC);
test_nr = 7;
// Check CPU_CTL reset value
dbg_uart_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`else
if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`endif
dbg_uart_rd(MEM_DATA);
if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
// Let the CPU run
dbg_uart_wr(CPU_CTL, 16'h0002);
test_nr = 8;
// Generate IRQ to terminate the test pattern
irq[`IRQ_NR-15] = 1'b1;
@(r13);
irq[`IRQ_NR-15] = 1'b0;
stimulus_done = 1;
`endif
`else
tb_skip_finish("| (serial debug interface UART not included) |");
`endif
`else
tb_skip_finish("| (serial debug interface not included) |");
`endif
end
|
//--------------------------------------------------------------------------------
// Auto-generated by Migen (d11565a) & LiteX (02bfda5e) on 2020-02-19 17:32:00
//--------------------------------------------------------------------------------
module top(
output reg serial_tx,
input serial_rx,
input clk100,
input cpu_reset,
output eth_ref_clk,
output [13:0] ddram_a,
output [2:0] ddram_ba,
output ddram_ras_n,
output ddram_cas_n,
output ddram_we_n,
output ddram_cs_n,
output [1:0] ddram_dm,
inout [15:0] ddram_dq,
output [1:0] ddram_dqs_p,
output [1:0] ddram_dqs_n,
output ddram_clk_p,
output ddram_clk_n,
output ddram_cke,
output ddram_odt,
output ddram_reset_n,
input eth_clocks_tx,
input eth_clocks_rx,
output eth_rst_n,
inout eth_mdio,
output eth_mdc,
input eth_rx_dv,
input eth_rx_er,
input [3:0] eth_rx_data,
output reg eth_tx_en,
output reg [3:0] eth_tx_data,
input eth_col,
input eth_crs,
output [3:0] led
);
wire [3:0] led;
assign led[0] = idelayctl_rdy;
assign led[1] = soc_pll_locked;
assign led[2] = 0;
assign led[3] = 0;
// Manually inserted OBUFs
wire [13:0] ddram_a_iob;
wire [ 2:0] ddram_ba_iob;
wire ddram_ras_n_iob;
wire ddram_cas_n_iob;
wire ddram_we_n_iob;
wire ddram_cs_n_iob;
wire [ 1:0] ddram_dm_iob;
wire ddram_cke_iob;
wire ddram_odt_iob;
wire ddram_reset_n_iob;
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a0 (.I(ddram_a_iob[ 0]), .O(ddram_a[ 0]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a1 (.I(ddram_a_iob[ 1]), .O(ddram_a[ 1]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a2 (.I(ddram_a_iob[ 2]), .O(ddram_a[ 2]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a3 (.I(ddram_a_iob[ 3]), .O(ddram_a[ 3]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a4 (.I(ddram_a_iob[ 4]), .O(ddram_a[ 4]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a5 (.I(ddram_a_iob[ 5]), .O(ddram_a[ 5]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a6 (.I(ddram_a_iob[ 6]), .O(ddram_a[ 6]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a7 (.I(ddram_a_iob[ 7]), .O(ddram_a[ 7]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a8 (.I(ddram_a_iob[ 8]), .O(ddram_a[ 8]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a9 (.I(ddram_a_iob[ 9]), .O(ddram_a[ 9]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a10 (.I(ddram_a_iob[10]), .O(ddram_a[10]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a11 (.I(ddram_a_iob[11]), .O(ddram_a[11]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a12 (.I(ddram_a_iob[12]), .O(ddram_a[12]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_a13 (.I(ddram_a_iob[13]), .O(ddram_a[13]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_ba0 (.I(ddram_ba_iob[0]), .O(ddram_ba[0]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_ba1 (.I(ddram_ba_iob[1]), .O(ddram_ba[1]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_ba2 (.I(ddram_ba_iob[2]), .O(ddram_ba[2]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_dm0 (.I(ddram_dm_iob[0]), .O(ddram_dm[0]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_dm1 (.I(ddram_dm_iob[1]), .O(ddram_dm[1]));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_ras (.I(ddram_ras_n_iob), .O(ddram_ras_n));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_cas (.I(ddram_cas_n_iob), .O(ddram_cas_n));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_we (.I(ddram_we_n_iob), .O(ddram_we_n));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_cs (.I(ddram_cs_n_iob), .O(ddram_cs_n));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_cke (.I(ddram_cke_iob), .O(ddram_cke));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_odt (.I(ddram_odt_iob), .O(ddram_odt));
OBUF #(.IOSTANDARD("SSTL135"), .SLEW("FAST")) obuf_rst (.I(ddram_reset_n_iob),.O(ddram_reset_n));
// End manually inserted OBUFs
wire idelayctl_rdy;
wire soc_netsoc_ctrl_reset_reset_re;
wire soc_netsoc_ctrl_reset_reset_r;
wire soc_netsoc_ctrl_reset_reset_we;
reg soc_netsoc_ctrl_reset_reset_w = 1'd0;
reg [31:0] soc_netsoc_ctrl_storage = 32'd305419896;
reg soc_netsoc_ctrl_re = 1'd0;
wire [31:0] soc_netsoc_ctrl_bus_errors_status;
wire soc_netsoc_ctrl_bus_errors_we;
wire soc_netsoc_ctrl_reset;
wire soc_netsoc_ctrl_bus_error;
reg [31:0] soc_netsoc_ctrl_bus_errors = 32'd0;
wire soc_netsoc_cpu_reset;
wire [29:0] soc_netsoc_cpu_ibus_adr;
wire [31:0] soc_netsoc_cpu_ibus_dat_w;
wire [31:0] soc_netsoc_cpu_ibus_dat_r;
wire [3:0] soc_netsoc_cpu_ibus_sel;
wire soc_netsoc_cpu_ibus_cyc;
wire soc_netsoc_cpu_ibus_stb;
wire soc_netsoc_cpu_ibus_ack;
wire soc_netsoc_cpu_ibus_we;
wire [2:0] soc_netsoc_cpu_ibus_cti;
wire [1:0] soc_netsoc_cpu_ibus_bte;
wire soc_netsoc_cpu_ibus_err;
wire [29:0] soc_netsoc_cpu_dbus_adr;
wire [31:0] soc_netsoc_cpu_dbus_dat_w;
wire [31:0] soc_netsoc_cpu_dbus_dat_r;
wire [3:0] soc_netsoc_cpu_dbus_sel;
wire soc_netsoc_cpu_dbus_cyc;
wire soc_netsoc_cpu_dbus_stb;
wire soc_netsoc_cpu_dbus_ack;
wire soc_netsoc_cpu_dbus_we;
wire [2:0] soc_netsoc_cpu_dbus_cti;
wire [1:0] soc_netsoc_cpu_dbus_bte;
wire soc_netsoc_cpu_dbus_err;
reg [31:0] soc_netsoc_cpu_interrupt0 = 32'd0;
wire soc_netsoc_cpu_latch_re;
wire soc_netsoc_cpu_latch_r;
wire soc_netsoc_cpu_latch_we;
reg soc_netsoc_cpu_latch_w = 1'd0;
reg [63:0] soc_netsoc_cpu_time_status = 64'd0;
wire soc_netsoc_cpu_time_we;
reg [63:0] soc_netsoc_cpu_time_cmp_storage = 64'd18446744073709551615;
reg soc_netsoc_cpu_time_cmp_re = 1'd0;
wire soc_netsoc_cpu_interrupt1;
reg [63:0] soc_netsoc_cpu_time = 64'd0;
reg [63:0] soc_netsoc_cpu_time_cmp = 64'd18446744073709551615;
wire [29:0] soc_netsoc_interface0_soc_bus_adr;
wire [31:0] soc_netsoc_interface0_soc_bus_dat_w;
wire [31:0] soc_netsoc_interface0_soc_bus_dat_r;
wire [3:0] soc_netsoc_interface0_soc_bus_sel;
wire soc_netsoc_interface0_soc_bus_cyc;
wire soc_netsoc_interface0_soc_bus_stb;
wire soc_netsoc_interface0_soc_bus_ack;
wire soc_netsoc_interface0_soc_bus_we;
wire [2:0] soc_netsoc_interface0_soc_bus_cti;
wire [1:0] soc_netsoc_interface0_soc_bus_bte;
wire soc_netsoc_interface0_soc_bus_err;
wire [29:0] soc_netsoc_interface1_soc_bus_adr;
wire [31:0] soc_netsoc_interface1_soc_bus_dat_w;
wire [31:0] soc_netsoc_interface1_soc_bus_dat_r;
wire [3:0] soc_netsoc_interface1_soc_bus_sel;
wire soc_netsoc_interface1_soc_bus_cyc;
wire soc_netsoc_interface1_soc_bus_stb;
wire soc_netsoc_interface1_soc_bus_ack;
wire soc_netsoc_interface1_soc_bus_we;
wire [2:0] soc_netsoc_interface1_soc_bus_cti;
wire [1:0] soc_netsoc_interface1_soc_bus_bte;
wire soc_netsoc_interface1_soc_bus_err;
wire [29:0] soc_netsoc_rom_bus_adr;
wire [31:0] soc_netsoc_rom_bus_dat_w;
wire [31:0] soc_netsoc_rom_bus_dat_r;
wire [3:0] soc_netsoc_rom_bus_sel;
wire soc_netsoc_rom_bus_cyc;
wire soc_netsoc_rom_bus_stb;
reg soc_netsoc_rom_bus_ack = 1'd0;
wire soc_netsoc_rom_bus_we;
wire [2:0] soc_netsoc_rom_bus_cti;
wire [1:0] soc_netsoc_rom_bus_bte;
reg soc_netsoc_rom_bus_err = 1'd0;
wire [13:0] soc_netsoc_rom_adr;
wire [31:0] soc_netsoc_rom_dat_r;
wire [29:0] soc_netsoc_sram_bus_adr;
wire [31:0] soc_netsoc_sram_bus_dat_w;
wire [31:0] soc_netsoc_sram_bus_dat_r;
wire [3:0] soc_netsoc_sram_bus_sel;
wire soc_netsoc_sram_bus_cyc;
wire soc_netsoc_sram_bus_stb;
reg soc_netsoc_sram_bus_ack = 1'd0;
wire soc_netsoc_sram_bus_we;
wire [2:0] soc_netsoc_sram_bus_cti;
wire [1:0] soc_netsoc_sram_bus_bte;
reg soc_netsoc_sram_bus_err = 1'd0;
wire [12:0] soc_netsoc_sram_adr;
wire [31:0] soc_netsoc_sram_dat_r;
reg [3:0] soc_netsoc_sram_we = 4'd0;
wire [31:0] soc_netsoc_sram_dat_w;
reg [31:0] soc_netsoc_uart_phy_storage = 32'd8246337;
reg soc_netsoc_uart_phy_re = 1'd0;
wire soc_netsoc_uart_phy_sink_valid;
reg soc_netsoc_uart_phy_sink_ready = 1'd0;
wire soc_netsoc_uart_phy_sink_first;
wire soc_netsoc_uart_phy_sink_last;
wire [7:0] soc_netsoc_uart_phy_sink_payload_data;
reg soc_netsoc_uart_phy_uart_clk_txen = 1'd0;
reg [31:0] soc_netsoc_uart_phy_phase_accumulator_tx = 32'd0;
reg [7:0] soc_netsoc_uart_phy_tx_reg = 8'd0;
reg [3:0] soc_netsoc_uart_phy_tx_bitcount = 4'd0;
reg soc_netsoc_uart_phy_tx_busy = 1'd0;
reg soc_netsoc_uart_phy_source_valid = 1'd0;
wire soc_netsoc_uart_phy_source_ready;
reg soc_netsoc_uart_phy_source_first = 1'd0;
reg soc_netsoc_uart_phy_source_last = 1'd0;
reg [7:0] soc_netsoc_uart_phy_source_payload_data = 8'd0;
reg soc_netsoc_uart_phy_uart_clk_rxen = 1'd0;
reg [31:0] soc_netsoc_uart_phy_phase_accumulator_rx = 32'd0;
wire soc_netsoc_uart_phy_rx;
reg soc_netsoc_uart_phy_rx_r = 1'd0;
reg [7:0] soc_netsoc_uart_phy_rx_reg = 8'd0;
reg [3:0] soc_netsoc_uart_phy_rx_bitcount = 4'd0;
reg soc_netsoc_uart_phy_rx_busy = 1'd0;
wire soc_netsoc_uart_rxtx_re;
wire [7:0] soc_netsoc_uart_rxtx_r;
wire soc_netsoc_uart_rxtx_we;
wire [7:0] soc_netsoc_uart_rxtx_w;
wire soc_netsoc_uart_txfull_status;
wire soc_netsoc_uart_txfull_we;
wire soc_netsoc_uart_rxempty_status;
wire soc_netsoc_uart_rxempty_we;
wire soc_netsoc_uart_irq;
wire soc_netsoc_uart_tx_status;
reg soc_netsoc_uart_tx_pending = 1'd0;
wire soc_netsoc_uart_tx_trigger;
reg soc_netsoc_uart_tx_clear = 1'd0;
reg soc_netsoc_uart_tx_old_trigger = 1'd0;
wire soc_netsoc_uart_rx_status;
reg soc_netsoc_uart_rx_pending = 1'd0;
wire soc_netsoc_uart_rx_trigger;
reg soc_netsoc_uart_rx_clear = 1'd0;
reg soc_netsoc_uart_rx_old_trigger = 1'd0;
wire soc_netsoc_uart_eventmanager_status_re;
wire [1:0] soc_netsoc_uart_eventmanager_status_r;
wire soc_netsoc_uart_eventmanager_status_we;
reg [1:0] soc_netsoc_uart_eventmanager_status_w = 2'd0;
wire soc_netsoc_uart_eventmanager_pending_re;
wire [1:0] soc_netsoc_uart_eventmanager_pending_r;
wire soc_netsoc_uart_eventmanager_pending_we;
reg [1:0] soc_netsoc_uart_eventmanager_pending_w = 2'd0;
reg [1:0] soc_netsoc_uart_eventmanager_storage = 2'd0;
reg soc_netsoc_uart_eventmanager_re = 1'd0;
wire soc_netsoc_uart_tx_fifo_sink_valid;
wire soc_netsoc_uart_tx_fifo_sink_ready;
reg soc_netsoc_uart_tx_fifo_sink_first = 1'd0;
reg soc_netsoc_uart_tx_fifo_sink_last = 1'd0;
wire [7:0] soc_netsoc_uart_tx_fifo_sink_payload_data;
wire soc_netsoc_uart_tx_fifo_source_valid;
wire soc_netsoc_uart_tx_fifo_source_ready;
wire soc_netsoc_uart_tx_fifo_source_first;
wire soc_netsoc_uart_tx_fifo_source_last;
wire [7:0] soc_netsoc_uart_tx_fifo_source_payload_data;
wire soc_netsoc_uart_tx_fifo_re;
reg soc_netsoc_uart_tx_fifo_readable = 1'd0;
wire soc_netsoc_uart_tx_fifo_syncfifo_we;
wire soc_netsoc_uart_tx_fifo_syncfifo_writable;
wire soc_netsoc_uart_tx_fifo_syncfifo_re;
wire soc_netsoc_uart_tx_fifo_syncfifo_readable;
wire [9:0] soc_netsoc_uart_tx_fifo_syncfifo_din;
wire [9:0] soc_netsoc_uart_tx_fifo_syncfifo_dout;
reg [4:0] soc_netsoc_uart_tx_fifo_level0 = 5'd0;
reg soc_netsoc_uart_tx_fifo_replace = 1'd0;
reg [3:0] soc_netsoc_uart_tx_fifo_produce = 4'd0;
reg [3:0] soc_netsoc_uart_tx_fifo_consume = 4'd0;
reg [3:0] soc_netsoc_uart_tx_fifo_wrport_adr = 4'd0;
wire [9:0] soc_netsoc_uart_tx_fifo_wrport_dat_r;
wire soc_netsoc_uart_tx_fifo_wrport_we;
wire [9:0] soc_netsoc_uart_tx_fifo_wrport_dat_w;
wire soc_netsoc_uart_tx_fifo_do_read;
wire [3:0] soc_netsoc_uart_tx_fifo_rdport_adr;
wire [9:0] soc_netsoc_uart_tx_fifo_rdport_dat_r;
wire soc_netsoc_uart_tx_fifo_rdport_re;
wire [4:0] soc_netsoc_uart_tx_fifo_level1;
wire [7:0] soc_netsoc_uart_tx_fifo_fifo_in_payload_data;
wire soc_netsoc_uart_tx_fifo_fifo_in_first;
wire soc_netsoc_uart_tx_fifo_fifo_in_last;
wire [7:0] soc_netsoc_uart_tx_fifo_fifo_out_payload_data;
wire soc_netsoc_uart_tx_fifo_fifo_out_first;
wire soc_netsoc_uart_tx_fifo_fifo_out_last;
wire soc_netsoc_uart_rx_fifo_sink_valid;
wire soc_netsoc_uart_rx_fifo_sink_ready;
wire soc_netsoc_uart_rx_fifo_sink_first;
wire soc_netsoc_uart_rx_fifo_sink_last;
wire [7:0] soc_netsoc_uart_rx_fifo_sink_payload_data;
wire soc_netsoc_uart_rx_fifo_source_valid;
wire soc_netsoc_uart_rx_fifo_source_ready;
wire soc_netsoc_uart_rx_fifo_source_first;
wire soc_netsoc_uart_rx_fifo_source_last;
wire [7:0] soc_netsoc_uart_rx_fifo_source_payload_data;
wire soc_netsoc_uart_rx_fifo_re;
reg soc_netsoc_uart_rx_fifo_readable = 1'd0;
wire soc_netsoc_uart_rx_fifo_syncfifo_we;
wire soc_netsoc_uart_rx_fifo_syncfifo_writable;
wire soc_netsoc_uart_rx_fifo_syncfifo_re;
wire soc_netsoc_uart_rx_fifo_syncfifo_readable;
wire [9:0] soc_netsoc_uart_rx_fifo_syncfifo_din;
wire [9:0] soc_netsoc_uart_rx_fifo_syncfifo_dout;
reg [4:0] soc_netsoc_uart_rx_fifo_level0 = 5'd0;
reg soc_netsoc_uart_rx_fifo_replace = 1'd0;
reg [3:0] soc_netsoc_uart_rx_fifo_produce = 4'd0;
reg [3:0] soc_netsoc_uart_rx_fifo_consume = 4'd0;
reg [3:0] soc_netsoc_uart_rx_fifo_wrport_adr = 4'd0;
wire [9:0] soc_netsoc_uart_rx_fifo_wrport_dat_r;
wire soc_netsoc_uart_rx_fifo_wrport_we;
wire [9:0] soc_netsoc_uart_rx_fifo_wrport_dat_w;
wire soc_netsoc_uart_rx_fifo_do_read;
wire [3:0] soc_netsoc_uart_rx_fifo_rdport_adr;
wire [9:0] soc_netsoc_uart_rx_fifo_rdport_dat_r;
wire soc_netsoc_uart_rx_fifo_rdport_re;
wire [4:0] soc_netsoc_uart_rx_fifo_level1;
wire [7:0] soc_netsoc_uart_rx_fifo_fifo_in_payload_data;
wire soc_netsoc_uart_rx_fifo_fifo_in_first;
wire soc_netsoc_uart_rx_fifo_fifo_in_last;
wire [7:0] soc_netsoc_uart_rx_fifo_fifo_out_payload_data;
wire soc_netsoc_uart_rx_fifo_fifo_out_first;
wire soc_netsoc_uart_rx_fifo_fifo_out_last;
reg soc_netsoc_uart_reset = 1'd0;
reg [31:0] soc_netsoc_timer0_load_storage = 32'd0;
reg soc_netsoc_timer0_load_re = 1'd0;
reg [31:0] soc_netsoc_timer0_reload_storage = 32'd0;
reg soc_netsoc_timer0_reload_re = 1'd0;
reg soc_netsoc_timer0_en_storage = 1'd0;
reg soc_netsoc_timer0_en_re = 1'd0;
reg soc_netsoc_timer0_update_value_storage = 1'd0;
reg soc_netsoc_timer0_update_value_re = 1'd0;
reg [31:0] soc_netsoc_timer0_value_status = 32'd0;
wire soc_netsoc_timer0_value_we;
wire soc_netsoc_timer0_irq;
wire soc_netsoc_timer0_zero_status;
reg soc_netsoc_timer0_zero_pending = 1'd0;
wire soc_netsoc_timer0_zero_trigger;
reg soc_netsoc_timer0_zero_clear = 1'd0;
reg soc_netsoc_timer0_zero_old_trigger = 1'd0;
wire soc_netsoc_timer0_eventmanager_status_re;
wire soc_netsoc_timer0_eventmanager_status_r;
wire soc_netsoc_timer0_eventmanager_status_we;
wire soc_netsoc_timer0_eventmanager_status_w;
wire soc_netsoc_timer0_eventmanager_pending_re;
wire soc_netsoc_timer0_eventmanager_pending_r;
wire soc_netsoc_timer0_eventmanager_pending_we;
wire soc_netsoc_timer0_eventmanager_pending_w;
reg soc_netsoc_timer0_eventmanager_storage = 1'd0;
reg soc_netsoc_timer0_eventmanager_re = 1'd0;
reg [31:0] soc_netsoc_timer0_value = 32'd0;
reg [13:0] soc_netsoc_interface_adr = 14'd0;
reg soc_netsoc_interface_we = 1'd0;
wire [7:0] soc_netsoc_interface_dat_w;
wire [7:0] soc_netsoc_interface_dat_r;
wire [29:0] soc_netsoc_bus_wishbone_adr;
wire [31:0] soc_netsoc_bus_wishbone_dat_w;
wire [31:0] soc_netsoc_bus_wishbone_dat_r;
wire [3:0] soc_netsoc_bus_wishbone_sel;
wire soc_netsoc_bus_wishbone_cyc;
wire soc_netsoc_bus_wishbone_stb;
reg soc_netsoc_bus_wishbone_ack = 1'd0;
wire soc_netsoc_bus_wishbone_we;
wire [2:0] soc_netsoc_bus_wishbone_cti;
wire [1:0] soc_netsoc_bus_wishbone_bte;
reg soc_netsoc_bus_wishbone_err = 1'd0;
wire [29:0] soc_netsoc_interface0_wb_sdram_adr;
wire [31:0] soc_netsoc_interface0_wb_sdram_dat_w;
reg [31:0] soc_netsoc_interface0_wb_sdram_dat_r = 32'd0;
wire [3:0] soc_netsoc_interface0_wb_sdram_sel;
wire soc_netsoc_interface0_wb_sdram_cyc;
wire soc_netsoc_interface0_wb_sdram_stb;
reg soc_netsoc_interface0_wb_sdram_ack = 1'd0;
wire soc_netsoc_interface0_wb_sdram_we;
wire [2:0] soc_netsoc_interface0_wb_sdram_cti;
wire [1:0] soc_netsoc_interface0_wb_sdram_bte;
reg soc_netsoc_interface0_wb_sdram_err = 1'd0;
(* dont_touch = "true" *) wire sys_clk;
wire sys_rst;
wire sys4x_clk;
wire sys4x_dqs_clk;
wire clk200_clk;
wire clk200_rst;
wire soc_clk100bg;
wire soc_pll_locked;
wire soc_pll_fb;
wire soc_pll_sys;
wire soc_pll_sys4x;
wire soc_pll_sys4x_dqs;
wire soc_pll_clk200;
wire soc_pll_clk100;
reg [3:0] soc_reset_counter = 4'd15;
reg soc_ic_reset = 1'd1;
wire [29:0] soc_emulator_ram_bus_adr;
wire [31:0] soc_emulator_ram_bus_dat_w;
wire [31:0] soc_emulator_ram_bus_dat_r;
wire [3:0] soc_emulator_ram_bus_sel;
wire soc_emulator_ram_bus_cyc;
wire soc_emulator_ram_bus_stb;
reg soc_emulator_ram_bus_ack = 1'd0;
wire soc_emulator_ram_bus_we;
wire [2:0] soc_emulator_ram_bus_cti;
wire [1:0] soc_emulator_ram_bus_bte;
reg soc_emulator_ram_bus_err = 1'd0;
wire [11:0] soc_emulator_ram_adr;
wire [31:0] soc_emulator_ram_dat_r;
reg [3:0] soc_emulator_ram_we = 4'd0;
wire [31:0] soc_emulator_ram_dat_w;
reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8;
reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0;
wire soc_a7ddrphy_cdly_rst_re;
wire soc_a7ddrphy_cdly_rst_r;
wire soc_a7ddrphy_cdly_rst_we;
reg soc_a7ddrphy_cdly_rst_w = 1'd0;
wire soc_a7ddrphy_cdly_inc_re;
wire soc_a7ddrphy_cdly_inc_r;
wire soc_a7ddrphy_cdly_inc_we;
reg soc_a7ddrphy_cdly_inc_w = 1'd0;
reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0;
reg soc_a7ddrphy_dly_sel_re = 1'd0;
wire soc_a7ddrphy_rdly_dq_rst_re;
wire soc_a7ddrphy_rdly_dq_rst_r;
wire soc_a7ddrphy_rdly_dq_rst_we;
reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0;
wire soc_a7ddrphy_rdly_dq_inc_re;
wire soc_a7ddrphy_rdly_dq_inc_r;
wire soc_a7ddrphy_rdly_dq_inc_we;
reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0;
wire soc_a7ddrphy_rdly_dq_bitslip_rst_re;
wire soc_a7ddrphy_rdly_dq_bitslip_rst_r;
wire soc_a7ddrphy_rdly_dq_bitslip_rst_we;
reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
wire soc_a7ddrphy_rdly_dq_bitslip_re;
wire soc_a7ddrphy_rdly_dq_bitslip_r;
wire soc_a7ddrphy_rdly_dq_bitslip_we;
reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
wire [13:0] soc_a7ddrphy_dfi_p0_address;
wire [2:0] soc_a7ddrphy_dfi_p0_bank;
wire soc_a7ddrphy_dfi_p0_cas_n;
wire soc_a7ddrphy_dfi_p0_cs_n;
wire soc_a7ddrphy_dfi_p0_ras_n;
wire soc_a7ddrphy_dfi_p0_we_n;
wire soc_a7ddrphy_dfi_p0_cke;
wire soc_a7ddrphy_dfi_p0_odt;
wire soc_a7ddrphy_dfi_p0_reset_n;
wire soc_a7ddrphy_dfi_p0_act_n;
wire [31:0] soc_a7ddrphy_dfi_p0_wrdata;
wire soc_a7ddrphy_dfi_p0_wrdata_en;
wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask;
wire soc_a7ddrphy_dfi_p0_rddata_en;
reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0;
reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0;
wire [13:0] soc_a7ddrphy_dfi_p1_address;
wire [2:0] soc_a7ddrphy_dfi_p1_bank;
wire soc_a7ddrphy_dfi_p1_cas_n;
wire soc_a7ddrphy_dfi_p1_cs_n;
wire soc_a7ddrphy_dfi_p1_ras_n;
wire soc_a7ddrphy_dfi_p1_we_n;
wire soc_a7ddrphy_dfi_p1_cke;
wire soc_a7ddrphy_dfi_p1_odt;
wire soc_a7ddrphy_dfi_p1_reset_n;
wire soc_a7ddrphy_dfi_p1_act_n;
wire [31:0] soc_a7ddrphy_dfi_p1_wrdata;
wire soc_a7ddrphy_dfi_p1_wrdata_en;
wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask;
wire soc_a7ddrphy_dfi_p1_rddata_en;
reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0;
reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0;
wire [13:0] soc_a7ddrphy_dfi_p2_address;
wire [2:0] soc_a7ddrphy_dfi_p2_bank;
wire soc_a7ddrphy_dfi_p2_cas_n;
wire soc_a7ddrphy_dfi_p2_cs_n;
wire soc_a7ddrphy_dfi_p2_ras_n;
wire soc_a7ddrphy_dfi_p2_we_n;
wire soc_a7ddrphy_dfi_p2_cke;
wire soc_a7ddrphy_dfi_p2_odt;
wire soc_a7ddrphy_dfi_p2_reset_n;
wire soc_a7ddrphy_dfi_p2_act_n;
wire [31:0] soc_a7ddrphy_dfi_p2_wrdata;
wire soc_a7ddrphy_dfi_p2_wrdata_en;
wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask;
wire soc_a7ddrphy_dfi_p2_rddata_en;
reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0;
reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0;
wire [13:0] soc_a7ddrphy_dfi_p3_address;
wire [2:0] soc_a7ddrphy_dfi_p3_bank;
wire soc_a7ddrphy_dfi_p3_cas_n;
wire soc_a7ddrphy_dfi_p3_cs_n;
wire soc_a7ddrphy_dfi_p3_ras_n;
wire soc_a7ddrphy_dfi_p3_we_n;
wire soc_a7ddrphy_dfi_p3_cke;
wire soc_a7ddrphy_dfi_p3_odt;
wire soc_a7ddrphy_dfi_p3_reset_n;
wire soc_a7ddrphy_dfi_p3_act_n;
wire [31:0] soc_a7ddrphy_dfi_p3_wrdata;
wire soc_a7ddrphy_dfi_p3_wrdata_en;
wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask;
wire soc_a7ddrphy_dfi_p3_rddata_en;
reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0;
reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0;
wire soc_a7ddrphy_sd_clk_se_nodelay;
reg soc_a7ddrphy_oe_dqs = 1'd0;
wire soc_a7ddrphy_dqs_preamble;
wire soc_a7ddrphy_dqs_postamble;
reg [7:0] soc_a7ddrphy_dqs_serdes_pattern = 8'd85;
wire soc_a7ddrphy_dqs_nodelay0;
wire soc_a7ddrphy_dqs_t0;
wire soc_a7ddrphy0;
wire soc_a7ddrphy_dqs_nodelay1;
wire soc_a7ddrphy_dqs_t1;
wire soc_a7ddrphy1;
reg soc_a7ddrphy_oe_dq = 1'd0;
wire soc_a7ddrphy_dq_o_nodelay0;
wire soc_a7ddrphy_dq_i_nodelay0;
wire soc_a7ddrphy_dq_i_delayed0;
wire soc_a7ddrphy_dq_t0;
wire [7:0] soc_a7ddrphy_dq_i_data0;
wire [7:0] soc_a7ddrphy_bitslip0_i;
reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip0_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip0_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay1;
wire soc_a7ddrphy_dq_i_nodelay1;
wire soc_a7ddrphy_dq_i_delayed1;
wire soc_a7ddrphy_dq_t1;
wire [7:0] soc_a7ddrphy_dq_i_data1;
wire [7:0] soc_a7ddrphy_bitslip1_i;
reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip1_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip1_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay2;
wire soc_a7ddrphy_dq_i_nodelay2;
wire soc_a7ddrphy_dq_i_delayed2;
wire soc_a7ddrphy_dq_t2;
wire [7:0] soc_a7ddrphy_dq_i_data2;
wire [7:0] soc_a7ddrphy_bitslip2_i;
reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip2_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip2_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay3;
wire soc_a7ddrphy_dq_i_nodelay3;
wire soc_a7ddrphy_dq_i_delayed3;
wire soc_a7ddrphy_dq_t3;
wire [7:0] soc_a7ddrphy_dq_i_data3;
wire [7:0] soc_a7ddrphy_bitslip3_i;
reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip3_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip3_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay4;
wire soc_a7ddrphy_dq_i_nodelay4;
wire soc_a7ddrphy_dq_i_delayed4;
wire soc_a7ddrphy_dq_t4;
wire [7:0] soc_a7ddrphy_dq_i_data4;
wire [7:0] soc_a7ddrphy_bitslip4_i;
reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip4_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip4_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay5;
wire soc_a7ddrphy_dq_i_nodelay5;
wire soc_a7ddrphy_dq_i_delayed5;
wire soc_a7ddrphy_dq_t5;
wire [7:0] soc_a7ddrphy_dq_i_data5;
wire [7:0] soc_a7ddrphy_bitslip5_i;
reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip5_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip5_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay6;
wire soc_a7ddrphy_dq_i_nodelay6;
wire soc_a7ddrphy_dq_i_delayed6;
wire soc_a7ddrphy_dq_t6;
wire [7:0] soc_a7ddrphy_dq_i_data6;
wire [7:0] soc_a7ddrphy_bitslip6_i;
reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip6_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip6_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay7;
wire soc_a7ddrphy_dq_i_nodelay7;
wire soc_a7ddrphy_dq_i_delayed7;
wire soc_a7ddrphy_dq_t7;
wire [7:0] soc_a7ddrphy_dq_i_data7;
wire [7:0] soc_a7ddrphy_bitslip7_i;
reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip7_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip7_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay8;
wire soc_a7ddrphy_dq_i_nodelay8;
wire soc_a7ddrphy_dq_i_delayed8;
wire soc_a7ddrphy_dq_t8;
wire [7:0] soc_a7ddrphy_dq_i_data8;
wire [7:0] soc_a7ddrphy_bitslip8_i;
reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip8_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip8_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay9;
wire soc_a7ddrphy_dq_i_nodelay9;
wire soc_a7ddrphy_dq_i_delayed9;
wire soc_a7ddrphy_dq_t9;
wire [7:0] soc_a7ddrphy_dq_i_data9;
wire [7:0] soc_a7ddrphy_bitslip9_i;
reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip9_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip9_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay10;
wire soc_a7ddrphy_dq_i_nodelay10;
wire soc_a7ddrphy_dq_i_delayed10;
wire soc_a7ddrphy_dq_t10;
wire [7:0] soc_a7ddrphy_dq_i_data10;
wire [7:0] soc_a7ddrphy_bitslip10_i;
reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip10_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip10_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay11;
wire soc_a7ddrphy_dq_i_nodelay11;
wire soc_a7ddrphy_dq_i_delayed11;
wire soc_a7ddrphy_dq_t11;
wire [7:0] soc_a7ddrphy_dq_i_data11;
wire [7:0] soc_a7ddrphy_bitslip11_i;
reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip11_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip11_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay12;
wire soc_a7ddrphy_dq_i_nodelay12;
wire soc_a7ddrphy_dq_i_delayed12;
wire soc_a7ddrphy_dq_t12;
wire [7:0] soc_a7ddrphy_dq_i_data12;
wire [7:0] soc_a7ddrphy_bitslip12_i;
reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip12_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip12_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay13;
wire soc_a7ddrphy_dq_i_nodelay13;
wire soc_a7ddrphy_dq_i_delayed13;
wire soc_a7ddrphy_dq_t13;
wire [7:0] soc_a7ddrphy_dq_i_data13;
wire [7:0] soc_a7ddrphy_bitslip13_i;
reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip13_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip13_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay14;
wire soc_a7ddrphy_dq_i_nodelay14;
wire soc_a7ddrphy_dq_i_delayed14;
wire soc_a7ddrphy_dq_t14;
wire [7:0] soc_a7ddrphy_dq_i_data14;
wire [7:0] soc_a7ddrphy_bitslip14_i;
reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip14_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip14_r = 16'd0;
wire soc_a7ddrphy_dq_o_nodelay15;
wire soc_a7ddrphy_dq_i_nodelay15;
wire soc_a7ddrphy_dq_i_delayed15;
wire soc_a7ddrphy_dq_t15;
wire [7:0] soc_a7ddrphy_dq_i_data15;
wire [7:0] soc_a7ddrphy_bitslip15_i;
reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0;
reg [2:0] soc_a7ddrphy_bitslip15_value = 3'd0;
reg [15:0] soc_a7ddrphy_bitslip15_r = 16'd0;
reg soc_a7ddrphy_n_rddata_en0 = 1'd0;
reg soc_a7ddrphy_n_rddata_en1 = 1'd0;
reg soc_a7ddrphy_n_rddata_en2 = 1'd0;
reg soc_a7ddrphy_n_rddata_en3 = 1'd0;
reg soc_a7ddrphy_n_rddata_en4 = 1'd0;
reg soc_a7ddrphy_n_rddata_en5 = 1'd0;
reg soc_a7ddrphy_n_rddata_en6 = 1'd0;
reg soc_a7ddrphy_n_rddata_en7 = 1'd0;
wire soc_a7ddrphy_oe;
reg [3:0] soc_a7ddrphy_last_wrdata_en = 4'd0;
wire [13:0] soc_netsoc_sdram_inti_p0_address;
wire [2:0] soc_netsoc_sdram_inti_p0_bank;
reg soc_netsoc_sdram_inti_p0_cas_n = 1'd1;
reg soc_netsoc_sdram_inti_p0_cs_n = 1'd1;
reg soc_netsoc_sdram_inti_p0_ras_n = 1'd1;
reg soc_netsoc_sdram_inti_p0_we_n = 1'd1;
wire soc_netsoc_sdram_inti_p0_cke;
wire soc_netsoc_sdram_inti_p0_odt;
wire soc_netsoc_sdram_inti_p0_reset_n;
reg soc_netsoc_sdram_inti_p0_act_n = 1'd1;
wire [31:0] soc_netsoc_sdram_inti_p0_wrdata;
wire soc_netsoc_sdram_inti_p0_wrdata_en;
wire [3:0] soc_netsoc_sdram_inti_p0_wrdata_mask;
wire soc_netsoc_sdram_inti_p0_rddata_en;
reg [31:0] soc_netsoc_sdram_inti_p0_rddata = 32'd0;
reg soc_netsoc_sdram_inti_p0_rddata_valid = 1'd0;
wire [13:0] soc_netsoc_sdram_inti_p1_address;
wire [2:0] soc_netsoc_sdram_inti_p1_bank;
reg soc_netsoc_sdram_inti_p1_cas_n = 1'd1;
reg soc_netsoc_sdram_inti_p1_cs_n = 1'd1;
reg soc_netsoc_sdram_inti_p1_ras_n = 1'd1;
reg soc_netsoc_sdram_inti_p1_we_n = 1'd1;
wire soc_netsoc_sdram_inti_p1_cke;
wire soc_netsoc_sdram_inti_p1_odt;
wire soc_netsoc_sdram_inti_p1_reset_n;
reg soc_netsoc_sdram_inti_p1_act_n = 1'd1;
wire [31:0] soc_netsoc_sdram_inti_p1_wrdata;
wire soc_netsoc_sdram_inti_p1_wrdata_en;
wire [3:0] soc_netsoc_sdram_inti_p1_wrdata_mask;
wire soc_netsoc_sdram_inti_p1_rddata_en;
reg [31:0] soc_netsoc_sdram_inti_p1_rddata = 32'd0;
reg soc_netsoc_sdram_inti_p1_rddata_valid = 1'd0;
wire [13:0] soc_netsoc_sdram_inti_p2_address;
wire [2:0] soc_netsoc_sdram_inti_p2_bank;
reg soc_netsoc_sdram_inti_p2_cas_n = 1'd1;
reg soc_netsoc_sdram_inti_p2_cs_n = 1'd1;
reg soc_netsoc_sdram_inti_p2_ras_n = 1'd1;
reg soc_netsoc_sdram_inti_p2_we_n = 1'd1;
wire soc_netsoc_sdram_inti_p2_cke;
wire soc_netsoc_sdram_inti_p2_odt;
wire soc_netsoc_sdram_inti_p2_reset_n;
reg soc_netsoc_sdram_inti_p2_act_n = 1'd1;
wire [31:0] soc_netsoc_sdram_inti_p2_wrdata;
wire soc_netsoc_sdram_inti_p2_wrdata_en;
wire [3:0] soc_netsoc_sdram_inti_p2_wrdata_mask;
wire soc_netsoc_sdram_inti_p2_rddata_en;
reg [31:0] soc_netsoc_sdram_inti_p2_rddata = 32'd0;
reg soc_netsoc_sdram_inti_p2_rddata_valid = 1'd0;
wire [13:0] soc_netsoc_sdram_inti_p3_address;
wire [2:0] soc_netsoc_sdram_inti_p3_bank;
reg soc_netsoc_sdram_inti_p3_cas_n = 1'd1;
reg soc_netsoc_sdram_inti_p3_cs_n = 1'd1;
reg soc_netsoc_sdram_inti_p3_ras_n = 1'd1;
reg soc_netsoc_sdram_inti_p3_we_n = 1'd1;
wire soc_netsoc_sdram_inti_p3_cke;
wire soc_netsoc_sdram_inti_p3_odt;
wire soc_netsoc_sdram_inti_p3_reset_n;
reg soc_netsoc_sdram_inti_p3_act_n = 1'd1;
wire [31:0] soc_netsoc_sdram_inti_p3_wrdata;
wire soc_netsoc_sdram_inti_p3_wrdata_en;
wire [3:0] soc_netsoc_sdram_inti_p3_wrdata_mask;
wire soc_netsoc_sdram_inti_p3_rddata_en;
reg [31:0] soc_netsoc_sdram_inti_p3_rddata = 32'd0;
reg soc_netsoc_sdram_inti_p3_rddata_valid = 1'd0;
wire [13:0] soc_netsoc_sdram_slave_p0_address;
wire [2:0] soc_netsoc_sdram_slave_p0_bank;
wire soc_netsoc_sdram_slave_p0_cas_n;
wire soc_netsoc_sdram_slave_p0_cs_n;
wire soc_netsoc_sdram_slave_p0_ras_n;
wire soc_netsoc_sdram_slave_p0_we_n;
wire soc_netsoc_sdram_slave_p0_cke;
wire soc_netsoc_sdram_slave_p0_odt;
wire soc_netsoc_sdram_slave_p0_reset_n;
wire soc_netsoc_sdram_slave_p0_act_n;
wire [31:0] soc_netsoc_sdram_slave_p0_wrdata;
wire soc_netsoc_sdram_slave_p0_wrdata_en;
wire [3:0] soc_netsoc_sdram_slave_p0_wrdata_mask;
wire soc_netsoc_sdram_slave_p0_rddata_en;
reg [31:0] soc_netsoc_sdram_slave_p0_rddata = 32'd0;
reg soc_netsoc_sdram_slave_p0_rddata_valid = 1'd0;
wire [13:0] soc_netsoc_sdram_slave_p1_address;
wire [2:0] soc_netsoc_sdram_slave_p1_bank;
wire soc_netsoc_sdram_slave_p1_cas_n;
wire soc_netsoc_sdram_slave_p1_cs_n;
wire soc_netsoc_sdram_slave_p1_ras_n;
wire soc_netsoc_sdram_slave_p1_we_n;
wire soc_netsoc_sdram_slave_p1_cke;
wire soc_netsoc_sdram_slave_p1_odt;
wire soc_netsoc_sdram_slave_p1_reset_n;
wire soc_netsoc_sdram_slave_p1_act_n;
wire [31:0] soc_netsoc_sdram_slave_p1_wrdata;
wire soc_netsoc_sdram_slave_p1_wrdata_en;
wire [3:0] soc_netsoc_sdram_slave_p1_wrdata_mask;
wire soc_netsoc_sdram_slave_p1_rddata_en;
reg [31:0] soc_netsoc_sdram_slave_p1_rddata = 32'd0;
reg soc_netsoc_sdram_slave_p1_rddata_valid = 1'd0;
wire [13:0] soc_netsoc_sdram_slave_p2_address;
wire [2:0] soc_netsoc_sdram_slave_p2_bank;
wire soc_netsoc_sdram_slave_p2_cas_n;
wire soc_netsoc_sdram_slave_p2_cs_n;
wire soc_netsoc_sdram_slave_p2_ras_n;
wire soc_netsoc_sdram_slave_p2_we_n;
wire soc_netsoc_sdram_slave_p2_cke;
wire soc_netsoc_sdram_slave_p2_odt;
wire soc_netsoc_sdram_slave_p2_reset_n;
wire soc_netsoc_sdram_slave_p2_act_n;
wire [31:0] soc_netsoc_sdram_slave_p2_wrdata;
wire soc_netsoc_sdram_slave_p2_wrdata_en;
wire [3:0] soc_netsoc_sdram_slave_p2_wrdata_mask;
wire soc_netsoc_sdram_slave_p2_rddata_en;
reg [31:0] soc_netsoc_sdram_slave_p2_rddata = 32'd0;
reg soc_netsoc_sdram_slave_p2_rddata_valid = 1'd0;
wire [13:0] soc_netsoc_sdram_slave_p3_address;
wire [2:0] soc_netsoc_sdram_slave_p3_bank;
wire soc_netsoc_sdram_slave_p3_cas_n;
wire soc_netsoc_sdram_slave_p3_cs_n;
wire soc_netsoc_sdram_slave_p3_ras_n;
wire soc_netsoc_sdram_slave_p3_we_n;
wire soc_netsoc_sdram_slave_p3_cke;
wire soc_netsoc_sdram_slave_p3_odt;
wire soc_netsoc_sdram_slave_p3_reset_n;
wire soc_netsoc_sdram_slave_p3_act_n;
wire [31:0] soc_netsoc_sdram_slave_p3_wrdata;
wire soc_netsoc_sdram_slave_p3_wrdata_en;
wire [3:0] soc_netsoc_sdram_slave_p3_wrdata_mask;
wire soc_netsoc_sdram_slave_p3_rddata_en;
reg [31:0] soc_netsoc_sdram_slave_p3_rddata = 32'd0;
reg soc_netsoc_sdram_slave_p3_rddata_valid = 1'd0;
reg [13:0] soc_netsoc_sdram_master_p0_address = 14'd0;
reg [2:0] soc_netsoc_sdram_master_p0_bank = 3'd0;
reg soc_netsoc_sdram_master_p0_cas_n = 1'd1;
reg soc_netsoc_sdram_master_p0_cs_n = 1'd1;
reg soc_netsoc_sdram_master_p0_ras_n = 1'd1;
reg soc_netsoc_sdram_master_p0_we_n = 1'd1;
reg soc_netsoc_sdram_master_p0_cke = 1'd0;
reg soc_netsoc_sdram_master_p0_odt = 1'd0;
reg soc_netsoc_sdram_master_p0_reset_n = 1'd0;
reg soc_netsoc_sdram_master_p0_act_n = 1'd1;
reg [31:0] soc_netsoc_sdram_master_p0_wrdata = 32'd0;
reg soc_netsoc_sdram_master_p0_wrdata_en = 1'd0;
reg [3:0] soc_netsoc_sdram_master_p0_wrdata_mask = 4'd0;
reg soc_netsoc_sdram_master_p0_rddata_en = 1'd0;
wire [31:0] soc_netsoc_sdram_master_p0_rddata;
wire soc_netsoc_sdram_master_p0_rddata_valid;
reg [13:0] soc_netsoc_sdram_master_p1_address = 14'd0;
reg [2:0] soc_netsoc_sdram_master_p1_bank = 3'd0;
reg soc_netsoc_sdram_master_p1_cas_n = 1'd1;
reg soc_netsoc_sdram_master_p1_cs_n = 1'd1;
reg soc_netsoc_sdram_master_p1_ras_n = 1'd1;
reg soc_netsoc_sdram_master_p1_we_n = 1'd1;
reg soc_netsoc_sdram_master_p1_cke = 1'd0;
reg soc_netsoc_sdram_master_p1_odt = 1'd0;
reg soc_netsoc_sdram_master_p1_reset_n = 1'd0;
reg soc_netsoc_sdram_master_p1_act_n = 1'd1;
reg [31:0] soc_netsoc_sdram_master_p1_wrdata = 32'd0;
reg soc_netsoc_sdram_master_p1_wrdata_en = 1'd0;
reg [3:0] soc_netsoc_sdram_master_p1_wrdata_mask = 4'd0;
reg soc_netsoc_sdram_master_p1_rddata_en = 1'd0;
wire [31:0] soc_netsoc_sdram_master_p1_rddata;
wire soc_netsoc_sdram_master_p1_rddata_valid;
reg [13:0] soc_netsoc_sdram_master_p2_address = 14'd0;
reg [2:0] soc_netsoc_sdram_master_p2_bank = 3'd0;
reg soc_netsoc_sdram_master_p2_cas_n = 1'd1;
reg soc_netsoc_sdram_master_p2_cs_n = 1'd1;
reg soc_netsoc_sdram_master_p2_ras_n = 1'd1;
reg soc_netsoc_sdram_master_p2_we_n = 1'd1;
reg soc_netsoc_sdram_master_p2_cke = 1'd0;
reg soc_netsoc_sdram_master_p2_odt = 1'd0;
reg soc_netsoc_sdram_master_p2_reset_n = 1'd0;
reg soc_netsoc_sdram_master_p2_act_n = 1'd1;
reg [31:0] soc_netsoc_sdram_master_p2_wrdata = 32'd0;
reg soc_netsoc_sdram_master_p2_wrdata_en = 1'd0;
reg [3:0] soc_netsoc_sdram_master_p2_wrdata_mask = 4'd0;
reg soc_netsoc_sdram_master_p2_rddata_en = 1'd0;
wire [31:0] soc_netsoc_sdram_master_p2_rddata;
wire soc_netsoc_sdram_master_p2_rddata_valid;
reg [13:0] soc_netsoc_sdram_master_p3_address = 14'd0;
reg [2:0] soc_netsoc_sdram_master_p3_bank = 3'd0;
reg soc_netsoc_sdram_master_p3_cas_n = 1'd1;
reg soc_netsoc_sdram_master_p3_cs_n = 1'd1;
reg soc_netsoc_sdram_master_p3_ras_n = 1'd1;
reg soc_netsoc_sdram_master_p3_we_n = 1'd1;
reg soc_netsoc_sdram_master_p3_cke = 1'd0;
reg soc_netsoc_sdram_master_p3_odt = 1'd0;
reg soc_netsoc_sdram_master_p3_reset_n = 1'd0;
reg soc_netsoc_sdram_master_p3_act_n = 1'd1;
reg [31:0] soc_netsoc_sdram_master_p3_wrdata = 32'd0;
reg soc_netsoc_sdram_master_p3_wrdata_en = 1'd0;
reg [3:0] soc_netsoc_sdram_master_p3_wrdata_mask = 4'd0;
reg soc_netsoc_sdram_master_p3_rddata_en = 1'd0;
wire [31:0] soc_netsoc_sdram_master_p3_rddata;
wire soc_netsoc_sdram_master_p3_rddata_valid;
reg [3:0] soc_netsoc_sdram_storage = 4'd0;
reg soc_netsoc_sdram_re = 1'd0;
reg [5:0] soc_netsoc_sdram_phaseinjector0_command_storage = 6'd0;
reg soc_netsoc_sdram_phaseinjector0_command_re = 1'd0;
wire soc_netsoc_sdram_phaseinjector0_command_issue_re;
wire soc_netsoc_sdram_phaseinjector0_command_issue_r;
wire soc_netsoc_sdram_phaseinjector0_command_issue_we;
reg soc_netsoc_sdram_phaseinjector0_command_issue_w = 1'd0;
reg [13:0] soc_netsoc_sdram_phaseinjector0_address_storage = 14'd0;
reg soc_netsoc_sdram_phaseinjector0_address_re = 1'd0;
reg [2:0] soc_netsoc_sdram_phaseinjector0_baddress_storage = 3'd0;
reg soc_netsoc_sdram_phaseinjector0_baddress_re = 1'd0;
reg [31:0] soc_netsoc_sdram_phaseinjector0_wrdata_storage = 32'd0;
reg soc_netsoc_sdram_phaseinjector0_wrdata_re = 1'd0;
reg [31:0] soc_netsoc_sdram_phaseinjector0_status = 32'd0;
wire soc_netsoc_sdram_phaseinjector0_we;
reg [5:0] soc_netsoc_sdram_phaseinjector1_command_storage = 6'd0;
reg soc_netsoc_sdram_phaseinjector1_command_re = 1'd0;
wire soc_netsoc_sdram_phaseinjector1_command_issue_re;
wire soc_netsoc_sdram_phaseinjector1_command_issue_r;
wire soc_netsoc_sdram_phaseinjector1_command_issue_we;
reg soc_netsoc_sdram_phaseinjector1_command_issue_w = 1'd0;
reg [13:0] soc_netsoc_sdram_phaseinjector1_address_storage = 14'd0;
reg soc_netsoc_sdram_phaseinjector1_address_re = 1'd0;
reg [2:0] soc_netsoc_sdram_phaseinjector1_baddress_storage = 3'd0;
reg soc_netsoc_sdram_phaseinjector1_baddress_re = 1'd0;
reg [31:0] soc_netsoc_sdram_phaseinjector1_wrdata_storage = 32'd0;
reg soc_netsoc_sdram_phaseinjector1_wrdata_re = 1'd0;
reg [31:0] soc_netsoc_sdram_phaseinjector1_status = 32'd0;
wire soc_netsoc_sdram_phaseinjector1_we;
reg [5:0] soc_netsoc_sdram_phaseinjector2_command_storage = 6'd0;
reg soc_netsoc_sdram_phaseinjector2_command_re = 1'd0;
wire soc_netsoc_sdram_phaseinjector2_command_issue_re;
wire soc_netsoc_sdram_phaseinjector2_command_issue_r;
wire soc_netsoc_sdram_phaseinjector2_command_issue_we;
reg soc_netsoc_sdram_phaseinjector2_command_issue_w = 1'd0;
reg [13:0] soc_netsoc_sdram_phaseinjector2_address_storage = 14'd0;
reg soc_netsoc_sdram_phaseinjector2_address_re = 1'd0;
reg [2:0] soc_netsoc_sdram_phaseinjector2_baddress_storage = 3'd0;
reg soc_netsoc_sdram_phaseinjector2_baddress_re = 1'd0;
reg [31:0] soc_netsoc_sdram_phaseinjector2_wrdata_storage = 32'd0;
reg soc_netsoc_sdram_phaseinjector2_wrdata_re = 1'd0;
reg [31:0] soc_netsoc_sdram_phaseinjector2_status = 32'd0;
wire soc_netsoc_sdram_phaseinjector2_we;
reg [5:0] soc_netsoc_sdram_phaseinjector3_command_storage = 6'd0;
reg soc_netsoc_sdram_phaseinjector3_command_re = 1'd0;
wire soc_netsoc_sdram_phaseinjector3_command_issue_re;
wire soc_netsoc_sdram_phaseinjector3_command_issue_r;
wire soc_netsoc_sdram_phaseinjector3_command_issue_we;
reg soc_netsoc_sdram_phaseinjector3_command_issue_w = 1'd0;
reg [13:0] soc_netsoc_sdram_phaseinjector3_address_storage = 14'd0;
reg soc_netsoc_sdram_phaseinjector3_address_re = 1'd0;
reg [2:0] soc_netsoc_sdram_phaseinjector3_baddress_storage = 3'd0;
reg soc_netsoc_sdram_phaseinjector3_baddress_re = 1'd0;
reg [31:0] soc_netsoc_sdram_phaseinjector3_wrdata_storage = 32'd0;
reg soc_netsoc_sdram_phaseinjector3_wrdata_re = 1'd0;
reg [31:0] soc_netsoc_sdram_phaseinjector3_status = 32'd0;
wire soc_netsoc_sdram_phaseinjector3_we;
wire soc_netsoc_sdram_interface_bank0_valid;
wire soc_netsoc_sdram_interface_bank0_ready;
wire soc_netsoc_sdram_interface_bank0_we;
wire [20:0] soc_netsoc_sdram_interface_bank0_addr;
wire soc_netsoc_sdram_interface_bank0_lock;
wire soc_netsoc_sdram_interface_bank0_wdata_ready;
wire soc_netsoc_sdram_interface_bank0_rdata_valid;
wire soc_netsoc_sdram_interface_bank1_valid;
wire soc_netsoc_sdram_interface_bank1_ready;
wire soc_netsoc_sdram_interface_bank1_we;
wire [20:0] soc_netsoc_sdram_interface_bank1_addr;
wire soc_netsoc_sdram_interface_bank1_lock;
wire soc_netsoc_sdram_interface_bank1_wdata_ready;
wire soc_netsoc_sdram_interface_bank1_rdata_valid;
wire soc_netsoc_sdram_interface_bank2_valid;
wire soc_netsoc_sdram_interface_bank2_ready;
wire soc_netsoc_sdram_interface_bank2_we;
wire [20:0] soc_netsoc_sdram_interface_bank2_addr;
wire soc_netsoc_sdram_interface_bank2_lock;
wire soc_netsoc_sdram_interface_bank2_wdata_ready;
wire soc_netsoc_sdram_interface_bank2_rdata_valid;
wire soc_netsoc_sdram_interface_bank3_valid;
wire soc_netsoc_sdram_interface_bank3_ready;
wire soc_netsoc_sdram_interface_bank3_we;
wire [20:0] soc_netsoc_sdram_interface_bank3_addr;
wire soc_netsoc_sdram_interface_bank3_lock;
wire soc_netsoc_sdram_interface_bank3_wdata_ready;
wire soc_netsoc_sdram_interface_bank3_rdata_valid;
wire soc_netsoc_sdram_interface_bank4_valid;
wire soc_netsoc_sdram_interface_bank4_ready;
wire soc_netsoc_sdram_interface_bank4_we;
wire [20:0] soc_netsoc_sdram_interface_bank4_addr;
wire soc_netsoc_sdram_interface_bank4_lock;
wire soc_netsoc_sdram_interface_bank4_wdata_ready;
wire soc_netsoc_sdram_interface_bank4_rdata_valid;
wire soc_netsoc_sdram_interface_bank5_valid;
wire soc_netsoc_sdram_interface_bank5_ready;
wire soc_netsoc_sdram_interface_bank5_we;
wire [20:0] soc_netsoc_sdram_interface_bank5_addr;
wire soc_netsoc_sdram_interface_bank5_lock;
wire soc_netsoc_sdram_interface_bank5_wdata_ready;
wire soc_netsoc_sdram_interface_bank5_rdata_valid;
wire soc_netsoc_sdram_interface_bank6_valid;
wire soc_netsoc_sdram_interface_bank6_ready;
wire soc_netsoc_sdram_interface_bank6_we;
wire [20:0] soc_netsoc_sdram_interface_bank6_addr;
wire soc_netsoc_sdram_interface_bank6_lock;
wire soc_netsoc_sdram_interface_bank6_wdata_ready;
wire soc_netsoc_sdram_interface_bank6_rdata_valid;
wire soc_netsoc_sdram_interface_bank7_valid;
wire soc_netsoc_sdram_interface_bank7_ready;
wire soc_netsoc_sdram_interface_bank7_we;
wire [20:0] soc_netsoc_sdram_interface_bank7_addr;
wire soc_netsoc_sdram_interface_bank7_lock;
wire soc_netsoc_sdram_interface_bank7_wdata_ready;
wire soc_netsoc_sdram_interface_bank7_rdata_valid;
reg [127:0] soc_netsoc_sdram_interface_wdata = 128'd0;
reg [15:0] soc_netsoc_sdram_interface_wdata_we = 16'd0;
wire [127:0] soc_netsoc_sdram_interface_rdata;
reg [13:0] soc_netsoc_sdram_dfi_p0_address = 14'd0;
reg [2:0] soc_netsoc_sdram_dfi_p0_bank = 3'd0;
reg soc_netsoc_sdram_dfi_p0_cas_n = 1'd1;
reg soc_netsoc_sdram_dfi_p0_cs_n = 1'd1;
reg soc_netsoc_sdram_dfi_p0_ras_n = 1'd1;
reg soc_netsoc_sdram_dfi_p0_we_n = 1'd1;
wire soc_netsoc_sdram_dfi_p0_cke;
wire soc_netsoc_sdram_dfi_p0_odt;
wire soc_netsoc_sdram_dfi_p0_reset_n;
reg soc_netsoc_sdram_dfi_p0_act_n = 1'd1;
wire [31:0] soc_netsoc_sdram_dfi_p0_wrdata;
reg soc_netsoc_sdram_dfi_p0_wrdata_en = 1'd0;
wire [3:0] soc_netsoc_sdram_dfi_p0_wrdata_mask;
reg soc_netsoc_sdram_dfi_p0_rddata_en = 1'd0;
wire [31:0] soc_netsoc_sdram_dfi_p0_rddata;
wire soc_netsoc_sdram_dfi_p0_rddata_valid;
reg [13:0] soc_netsoc_sdram_dfi_p1_address = 14'd0;
reg [2:0] soc_netsoc_sdram_dfi_p1_bank = 3'd0;
reg soc_netsoc_sdram_dfi_p1_cas_n = 1'd1;
reg soc_netsoc_sdram_dfi_p1_cs_n = 1'd1;
reg soc_netsoc_sdram_dfi_p1_ras_n = 1'd1;
reg soc_netsoc_sdram_dfi_p1_we_n = 1'd1;
wire soc_netsoc_sdram_dfi_p1_cke;
wire soc_netsoc_sdram_dfi_p1_odt;
wire soc_netsoc_sdram_dfi_p1_reset_n;
reg soc_netsoc_sdram_dfi_p1_act_n = 1'd1;
wire [31:0] soc_netsoc_sdram_dfi_p1_wrdata;
reg soc_netsoc_sdram_dfi_p1_wrdata_en = 1'd0;
wire [3:0] soc_netsoc_sdram_dfi_p1_wrdata_mask;
reg soc_netsoc_sdram_dfi_p1_rddata_en = 1'd0;
wire [31:0] soc_netsoc_sdram_dfi_p1_rddata;
wire soc_netsoc_sdram_dfi_p1_rddata_valid;
reg [13:0] soc_netsoc_sdram_dfi_p2_address = 14'd0;
reg [2:0] soc_netsoc_sdram_dfi_p2_bank = 3'd0;
reg soc_netsoc_sdram_dfi_p2_cas_n = 1'd1;
reg soc_netsoc_sdram_dfi_p2_cs_n = 1'd1;
reg soc_netsoc_sdram_dfi_p2_ras_n = 1'd1;
reg soc_netsoc_sdram_dfi_p2_we_n = 1'd1;
wire soc_netsoc_sdram_dfi_p2_cke;
wire soc_netsoc_sdram_dfi_p2_odt;
wire soc_netsoc_sdram_dfi_p2_reset_n;
reg soc_netsoc_sdram_dfi_p2_act_n = 1'd1;
wire [31:0] soc_netsoc_sdram_dfi_p2_wrdata;
reg soc_netsoc_sdram_dfi_p2_wrdata_en = 1'd0;
wire [3:0] soc_netsoc_sdram_dfi_p2_wrdata_mask;
reg soc_netsoc_sdram_dfi_p2_rddata_en = 1'd0;
wire [31:0] soc_netsoc_sdram_dfi_p2_rddata;
wire soc_netsoc_sdram_dfi_p2_rddata_valid;
reg [13:0] soc_netsoc_sdram_dfi_p3_address = 14'd0;
reg [2:0] soc_netsoc_sdram_dfi_p3_bank = 3'd0;
reg soc_netsoc_sdram_dfi_p3_cas_n = 1'd1;
reg soc_netsoc_sdram_dfi_p3_cs_n = 1'd1;
reg soc_netsoc_sdram_dfi_p3_ras_n = 1'd1;
reg soc_netsoc_sdram_dfi_p3_we_n = 1'd1;
wire soc_netsoc_sdram_dfi_p3_cke;
wire soc_netsoc_sdram_dfi_p3_odt;
wire soc_netsoc_sdram_dfi_p3_reset_n;
reg soc_netsoc_sdram_dfi_p3_act_n = 1'd1;
wire [31:0] soc_netsoc_sdram_dfi_p3_wrdata;
reg soc_netsoc_sdram_dfi_p3_wrdata_en = 1'd0;
wire [3:0] soc_netsoc_sdram_dfi_p3_wrdata_mask;
reg soc_netsoc_sdram_dfi_p3_rddata_en = 1'd0;
wire [31:0] soc_netsoc_sdram_dfi_p3_rddata;
wire soc_netsoc_sdram_dfi_p3_rddata_valid;
reg soc_netsoc_sdram_cmd_valid = 1'd0;
reg soc_netsoc_sdram_cmd_ready = 1'd0;
reg soc_netsoc_sdram_cmd_last = 1'd0;
reg [13:0] soc_netsoc_sdram_cmd_payload_a = 14'd0;
reg [2:0] soc_netsoc_sdram_cmd_payload_ba = 3'd0;
reg soc_netsoc_sdram_cmd_payload_cas = 1'd0;
reg soc_netsoc_sdram_cmd_payload_ras = 1'd0;
reg soc_netsoc_sdram_cmd_payload_we = 1'd0;
reg soc_netsoc_sdram_cmd_payload_is_read = 1'd0;
reg soc_netsoc_sdram_cmd_payload_is_write = 1'd0;
wire soc_netsoc_sdram_wants_refresh;
wire soc_netsoc_sdram_wants_zqcs;
wire soc_netsoc_sdram_timer_wait;
wire soc_netsoc_sdram_timer_done0;
wire [8:0] soc_netsoc_sdram_timer_count0;
wire soc_netsoc_sdram_timer_done1;
reg [8:0] soc_netsoc_sdram_timer_count1 = 9'd468;
wire soc_netsoc_sdram_postponer_req_i;
reg soc_netsoc_sdram_postponer_req_o = 1'd0;
reg soc_netsoc_sdram_postponer_count = 1'd0;
reg soc_netsoc_sdram_sequencer_start0 = 1'd0;
wire soc_netsoc_sdram_sequencer_done0;
wire soc_netsoc_sdram_sequencer_start1;
reg soc_netsoc_sdram_sequencer_done1 = 1'd0;
reg [5:0] soc_netsoc_sdram_sequencer_counter = 6'd0;
reg soc_netsoc_sdram_sequencer_count = 1'd0;
wire soc_netsoc_sdram_zqcs_timer_wait;
wire soc_netsoc_sdram_zqcs_timer_done0;
wire [25:0] soc_netsoc_sdram_zqcs_timer_count0;
wire soc_netsoc_sdram_zqcs_timer_done1;
reg [25:0] soc_netsoc_sdram_zqcs_timer_count1 = 26'd59999999;
reg soc_netsoc_sdram_zqcs_executer_start = 1'd0;
reg soc_netsoc_sdram_zqcs_executer_done = 1'd0;
reg [4:0] soc_netsoc_sdram_zqcs_executer_counter = 5'd0;
wire soc_netsoc_sdram_bankmachine0_req_valid;
wire soc_netsoc_sdram_bankmachine0_req_ready;
wire soc_netsoc_sdram_bankmachine0_req_we;
wire [20:0] soc_netsoc_sdram_bankmachine0_req_addr;
wire soc_netsoc_sdram_bankmachine0_req_lock;
reg soc_netsoc_sdram_bankmachine0_req_wdata_ready = 1'd0;
reg soc_netsoc_sdram_bankmachine0_req_rdata_valid = 1'd0;
wire soc_netsoc_sdram_bankmachine0_refresh_req;
reg soc_netsoc_sdram_bankmachine0_refresh_gnt = 1'd0;
reg soc_netsoc_sdram_bankmachine0_cmd_valid = 1'd0;
reg soc_netsoc_sdram_bankmachine0_cmd_ready = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine0_cmd_payload_a = 14'd0;
wire [2:0] soc_netsoc_sdram_bankmachine0_cmd_payload_ba;
reg soc_netsoc_sdram_bankmachine0_cmd_payload_cas = 1'd0;
reg soc_netsoc_sdram_bankmachine0_cmd_payload_ras = 1'd0;
reg soc_netsoc_sdram_bankmachine0_cmd_payload_we = 1'd0;
reg soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;
reg soc_netsoc_sdram_bankmachine0_cmd_payload_is_read = 1'd0;
reg soc_netsoc_sdram_bankmachine0_cmd_payload_is_write = 1'd0;
reg soc_netsoc_sdram_bankmachine0_auto_precharge = 1'd0;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
reg soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
wire [23:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
wire [23:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
reg [3:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0;
reg soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_do_read;
wire [2:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_valid;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_ready;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_first;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_last;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_source_valid;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_source_ready;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_source_first;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_source_last;
reg soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_pipe_ce;
wire soc_netsoc_sdram_bankmachine0_cmd_buffer_busy;
reg soc_netsoc_sdram_bankmachine0_cmd_buffer_valid_n = 1'd0;
reg soc_netsoc_sdram_bankmachine0_cmd_buffer_first_n = 1'd0;
reg soc_netsoc_sdram_bankmachine0_cmd_buffer_last_n = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine0_row = 14'd0;
reg soc_netsoc_sdram_bankmachine0_row_opened = 1'd0;
wire soc_netsoc_sdram_bankmachine0_row_hit;
reg soc_netsoc_sdram_bankmachine0_row_open = 1'd0;
reg soc_netsoc_sdram_bankmachine0_row_close = 1'd0;
reg soc_netsoc_sdram_bankmachine0_row_col_n_addr_sel = 1'd0;
wire soc_netsoc_sdram_bankmachine0_twtpcon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine0_twtpcon_ready = 1'd1;
reg [2:0] soc_netsoc_sdram_bankmachine0_twtpcon_count = 3'd0;
wire soc_netsoc_sdram_bankmachine0_trccon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine0_trccon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine0_trccon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine0_trascon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine0_trascon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine0_trascon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine1_req_valid;
wire soc_netsoc_sdram_bankmachine1_req_ready;
wire soc_netsoc_sdram_bankmachine1_req_we;
wire [20:0] soc_netsoc_sdram_bankmachine1_req_addr;
wire soc_netsoc_sdram_bankmachine1_req_lock;
reg soc_netsoc_sdram_bankmachine1_req_wdata_ready = 1'd0;
reg soc_netsoc_sdram_bankmachine1_req_rdata_valid = 1'd0;
wire soc_netsoc_sdram_bankmachine1_refresh_req;
reg soc_netsoc_sdram_bankmachine1_refresh_gnt = 1'd0;
reg soc_netsoc_sdram_bankmachine1_cmd_valid = 1'd0;
reg soc_netsoc_sdram_bankmachine1_cmd_ready = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine1_cmd_payload_a = 14'd0;
wire [2:0] soc_netsoc_sdram_bankmachine1_cmd_payload_ba;
reg soc_netsoc_sdram_bankmachine1_cmd_payload_cas = 1'd0;
reg soc_netsoc_sdram_bankmachine1_cmd_payload_ras = 1'd0;
reg soc_netsoc_sdram_bankmachine1_cmd_payload_we = 1'd0;
reg soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;
reg soc_netsoc_sdram_bankmachine1_cmd_payload_is_read = 1'd0;
reg soc_netsoc_sdram_bankmachine1_cmd_payload_is_write = 1'd0;
reg soc_netsoc_sdram_bankmachine1_auto_precharge = 1'd0;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
reg soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
wire [23:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
wire [23:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
reg [3:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0;
reg soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_do_read;
wire [2:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_valid;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_ready;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_first;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_last;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_source_valid;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_source_ready;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_source_first;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_source_last;
reg soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_pipe_ce;
wire soc_netsoc_sdram_bankmachine1_cmd_buffer_busy;
reg soc_netsoc_sdram_bankmachine1_cmd_buffer_valid_n = 1'd0;
reg soc_netsoc_sdram_bankmachine1_cmd_buffer_first_n = 1'd0;
reg soc_netsoc_sdram_bankmachine1_cmd_buffer_last_n = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine1_row = 14'd0;
reg soc_netsoc_sdram_bankmachine1_row_opened = 1'd0;
wire soc_netsoc_sdram_bankmachine1_row_hit;
reg soc_netsoc_sdram_bankmachine1_row_open = 1'd0;
reg soc_netsoc_sdram_bankmachine1_row_close = 1'd0;
reg soc_netsoc_sdram_bankmachine1_row_col_n_addr_sel = 1'd0;
wire soc_netsoc_sdram_bankmachine1_twtpcon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine1_twtpcon_ready = 1'd1;
reg [2:0] soc_netsoc_sdram_bankmachine1_twtpcon_count = 3'd0;
wire soc_netsoc_sdram_bankmachine1_trccon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine1_trccon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine1_trccon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine1_trascon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine1_trascon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine1_trascon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine2_req_valid;
wire soc_netsoc_sdram_bankmachine2_req_ready;
wire soc_netsoc_sdram_bankmachine2_req_we;
wire [20:0] soc_netsoc_sdram_bankmachine2_req_addr;
wire soc_netsoc_sdram_bankmachine2_req_lock;
reg soc_netsoc_sdram_bankmachine2_req_wdata_ready = 1'd0;
reg soc_netsoc_sdram_bankmachine2_req_rdata_valid = 1'd0;
wire soc_netsoc_sdram_bankmachine2_refresh_req;
reg soc_netsoc_sdram_bankmachine2_refresh_gnt = 1'd0;
reg soc_netsoc_sdram_bankmachine2_cmd_valid = 1'd0;
reg soc_netsoc_sdram_bankmachine2_cmd_ready = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine2_cmd_payload_a = 14'd0;
wire [2:0] soc_netsoc_sdram_bankmachine2_cmd_payload_ba;
reg soc_netsoc_sdram_bankmachine2_cmd_payload_cas = 1'd0;
reg soc_netsoc_sdram_bankmachine2_cmd_payload_ras = 1'd0;
reg soc_netsoc_sdram_bankmachine2_cmd_payload_we = 1'd0;
reg soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;
reg soc_netsoc_sdram_bankmachine2_cmd_payload_is_read = 1'd0;
reg soc_netsoc_sdram_bankmachine2_cmd_payload_is_write = 1'd0;
reg soc_netsoc_sdram_bankmachine2_auto_precharge = 1'd0;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
reg soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
wire [23:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
wire [23:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
reg [3:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0;
reg soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_do_read;
wire [2:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_valid;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_ready;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_first;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_last;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_source_valid;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_source_ready;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_source_first;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_source_last;
reg soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_pipe_ce;
wire soc_netsoc_sdram_bankmachine2_cmd_buffer_busy;
reg soc_netsoc_sdram_bankmachine2_cmd_buffer_valid_n = 1'd0;
reg soc_netsoc_sdram_bankmachine2_cmd_buffer_first_n = 1'd0;
reg soc_netsoc_sdram_bankmachine2_cmd_buffer_last_n = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine2_row = 14'd0;
reg soc_netsoc_sdram_bankmachine2_row_opened = 1'd0;
wire soc_netsoc_sdram_bankmachine2_row_hit;
reg soc_netsoc_sdram_bankmachine2_row_open = 1'd0;
reg soc_netsoc_sdram_bankmachine2_row_close = 1'd0;
reg soc_netsoc_sdram_bankmachine2_row_col_n_addr_sel = 1'd0;
wire soc_netsoc_sdram_bankmachine2_twtpcon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine2_twtpcon_ready = 1'd1;
reg [2:0] soc_netsoc_sdram_bankmachine2_twtpcon_count = 3'd0;
wire soc_netsoc_sdram_bankmachine2_trccon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine2_trccon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine2_trccon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine2_trascon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine2_trascon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine2_trascon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine3_req_valid;
wire soc_netsoc_sdram_bankmachine3_req_ready;
wire soc_netsoc_sdram_bankmachine3_req_we;
wire [20:0] soc_netsoc_sdram_bankmachine3_req_addr;
wire soc_netsoc_sdram_bankmachine3_req_lock;
reg soc_netsoc_sdram_bankmachine3_req_wdata_ready = 1'd0;
reg soc_netsoc_sdram_bankmachine3_req_rdata_valid = 1'd0;
wire soc_netsoc_sdram_bankmachine3_refresh_req;
reg soc_netsoc_sdram_bankmachine3_refresh_gnt = 1'd0;
reg soc_netsoc_sdram_bankmachine3_cmd_valid = 1'd0;
reg soc_netsoc_sdram_bankmachine3_cmd_ready = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine3_cmd_payload_a = 14'd0;
wire [2:0] soc_netsoc_sdram_bankmachine3_cmd_payload_ba;
reg soc_netsoc_sdram_bankmachine3_cmd_payload_cas = 1'd0;
reg soc_netsoc_sdram_bankmachine3_cmd_payload_ras = 1'd0;
reg soc_netsoc_sdram_bankmachine3_cmd_payload_we = 1'd0;
reg soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;
reg soc_netsoc_sdram_bankmachine3_cmd_payload_is_read = 1'd0;
reg soc_netsoc_sdram_bankmachine3_cmd_payload_is_write = 1'd0;
reg soc_netsoc_sdram_bankmachine3_auto_precharge = 1'd0;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
reg soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
wire [23:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
wire [23:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
reg [3:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0;
reg soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_do_read;
wire [2:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_valid;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_ready;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_first;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_last;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_source_valid;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_source_ready;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_source_first;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_source_last;
reg soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_pipe_ce;
wire soc_netsoc_sdram_bankmachine3_cmd_buffer_busy;
reg soc_netsoc_sdram_bankmachine3_cmd_buffer_valid_n = 1'd0;
reg soc_netsoc_sdram_bankmachine3_cmd_buffer_first_n = 1'd0;
reg soc_netsoc_sdram_bankmachine3_cmd_buffer_last_n = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine3_row = 14'd0;
reg soc_netsoc_sdram_bankmachine3_row_opened = 1'd0;
wire soc_netsoc_sdram_bankmachine3_row_hit;
reg soc_netsoc_sdram_bankmachine3_row_open = 1'd0;
reg soc_netsoc_sdram_bankmachine3_row_close = 1'd0;
reg soc_netsoc_sdram_bankmachine3_row_col_n_addr_sel = 1'd0;
wire soc_netsoc_sdram_bankmachine3_twtpcon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine3_twtpcon_ready = 1'd1;
reg [2:0] soc_netsoc_sdram_bankmachine3_twtpcon_count = 3'd0;
wire soc_netsoc_sdram_bankmachine3_trccon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine3_trccon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine3_trccon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine3_trascon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine3_trascon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine3_trascon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine4_req_valid;
wire soc_netsoc_sdram_bankmachine4_req_ready;
wire soc_netsoc_sdram_bankmachine4_req_we;
wire [20:0] soc_netsoc_sdram_bankmachine4_req_addr;
wire soc_netsoc_sdram_bankmachine4_req_lock;
reg soc_netsoc_sdram_bankmachine4_req_wdata_ready = 1'd0;
reg soc_netsoc_sdram_bankmachine4_req_rdata_valid = 1'd0;
wire soc_netsoc_sdram_bankmachine4_refresh_req;
reg soc_netsoc_sdram_bankmachine4_refresh_gnt = 1'd0;
reg soc_netsoc_sdram_bankmachine4_cmd_valid = 1'd0;
reg soc_netsoc_sdram_bankmachine4_cmd_ready = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine4_cmd_payload_a = 14'd0;
wire [2:0] soc_netsoc_sdram_bankmachine4_cmd_payload_ba;
reg soc_netsoc_sdram_bankmachine4_cmd_payload_cas = 1'd0;
reg soc_netsoc_sdram_bankmachine4_cmd_payload_ras = 1'd0;
reg soc_netsoc_sdram_bankmachine4_cmd_payload_we = 1'd0;
reg soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0;
reg soc_netsoc_sdram_bankmachine4_cmd_payload_is_read = 1'd0;
reg soc_netsoc_sdram_bankmachine4_cmd_payload_is_write = 1'd0;
reg soc_netsoc_sdram_bankmachine4_auto_precharge = 1'd0;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
reg soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
wire [23:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
wire [23:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
reg [3:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level = 4'd0;
reg soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_do_read;
wire [2:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_valid;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_ready;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_first;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_last;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_source_valid;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_source_ready;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_source_first;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_source_last;
reg soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_pipe_ce;
wire soc_netsoc_sdram_bankmachine4_cmd_buffer_busy;
reg soc_netsoc_sdram_bankmachine4_cmd_buffer_valid_n = 1'd0;
reg soc_netsoc_sdram_bankmachine4_cmd_buffer_first_n = 1'd0;
reg soc_netsoc_sdram_bankmachine4_cmd_buffer_last_n = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine4_row = 14'd0;
reg soc_netsoc_sdram_bankmachine4_row_opened = 1'd0;
wire soc_netsoc_sdram_bankmachine4_row_hit;
reg soc_netsoc_sdram_bankmachine4_row_open = 1'd0;
reg soc_netsoc_sdram_bankmachine4_row_close = 1'd0;
reg soc_netsoc_sdram_bankmachine4_row_col_n_addr_sel = 1'd0;
wire soc_netsoc_sdram_bankmachine4_twtpcon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine4_twtpcon_ready = 1'd1;
reg [2:0] soc_netsoc_sdram_bankmachine4_twtpcon_count = 3'd0;
wire soc_netsoc_sdram_bankmachine4_trccon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine4_trccon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine4_trccon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine4_trascon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine4_trascon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine4_trascon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine5_req_valid;
wire soc_netsoc_sdram_bankmachine5_req_ready;
wire soc_netsoc_sdram_bankmachine5_req_we;
wire [20:0] soc_netsoc_sdram_bankmachine5_req_addr;
wire soc_netsoc_sdram_bankmachine5_req_lock;
reg soc_netsoc_sdram_bankmachine5_req_wdata_ready = 1'd0;
reg soc_netsoc_sdram_bankmachine5_req_rdata_valid = 1'd0;
wire soc_netsoc_sdram_bankmachine5_refresh_req;
reg soc_netsoc_sdram_bankmachine5_refresh_gnt = 1'd0;
reg soc_netsoc_sdram_bankmachine5_cmd_valid = 1'd0;
reg soc_netsoc_sdram_bankmachine5_cmd_ready = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine5_cmd_payload_a = 14'd0;
wire [2:0] soc_netsoc_sdram_bankmachine5_cmd_payload_ba;
reg soc_netsoc_sdram_bankmachine5_cmd_payload_cas = 1'd0;
reg soc_netsoc_sdram_bankmachine5_cmd_payload_ras = 1'd0;
reg soc_netsoc_sdram_bankmachine5_cmd_payload_we = 1'd0;
reg soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0;
reg soc_netsoc_sdram_bankmachine5_cmd_payload_is_read = 1'd0;
reg soc_netsoc_sdram_bankmachine5_cmd_payload_is_write = 1'd0;
reg soc_netsoc_sdram_bankmachine5_auto_precharge = 1'd0;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
reg soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
wire [23:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
wire [23:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
reg [3:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level = 4'd0;
reg soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_do_read;
wire [2:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_valid;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_ready;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_first;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_last;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_source_valid;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_source_ready;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_source_first;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_source_last;
reg soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_pipe_ce;
wire soc_netsoc_sdram_bankmachine5_cmd_buffer_busy;
reg soc_netsoc_sdram_bankmachine5_cmd_buffer_valid_n = 1'd0;
reg soc_netsoc_sdram_bankmachine5_cmd_buffer_first_n = 1'd0;
reg soc_netsoc_sdram_bankmachine5_cmd_buffer_last_n = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine5_row = 14'd0;
reg soc_netsoc_sdram_bankmachine5_row_opened = 1'd0;
wire soc_netsoc_sdram_bankmachine5_row_hit;
reg soc_netsoc_sdram_bankmachine5_row_open = 1'd0;
reg soc_netsoc_sdram_bankmachine5_row_close = 1'd0;
reg soc_netsoc_sdram_bankmachine5_row_col_n_addr_sel = 1'd0;
wire soc_netsoc_sdram_bankmachine5_twtpcon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine5_twtpcon_ready = 1'd1;
reg [2:0] soc_netsoc_sdram_bankmachine5_twtpcon_count = 3'd0;
wire soc_netsoc_sdram_bankmachine5_trccon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine5_trccon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine5_trccon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine5_trascon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine5_trascon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine5_trascon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine6_req_valid;
wire soc_netsoc_sdram_bankmachine6_req_ready;
wire soc_netsoc_sdram_bankmachine6_req_we;
wire [20:0] soc_netsoc_sdram_bankmachine6_req_addr;
wire soc_netsoc_sdram_bankmachine6_req_lock;
reg soc_netsoc_sdram_bankmachine6_req_wdata_ready = 1'd0;
reg soc_netsoc_sdram_bankmachine6_req_rdata_valid = 1'd0;
wire soc_netsoc_sdram_bankmachine6_refresh_req;
reg soc_netsoc_sdram_bankmachine6_refresh_gnt = 1'd0;
reg soc_netsoc_sdram_bankmachine6_cmd_valid = 1'd0;
reg soc_netsoc_sdram_bankmachine6_cmd_ready = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine6_cmd_payload_a = 14'd0;
wire [2:0] soc_netsoc_sdram_bankmachine6_cmd_payload_ba;
reg soc_netsoc_sdram_bankmachine6_cmd_payload_cas = 1'd0;
reg soc_netsoc_sdram_bankmachine6_cmd_payload_ras = 1'd0;
reg soc_netsoc_sdram_bankmachine6_cmd_payload_we = 1'd0;
reg soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0;
reg soc_netsoc_sdram_bankmachine6_cmd_payload_is_read = 1'd0;
reg soc_netsoc_sdram_bankmachine6_cmd_payload_is_write = 1'd0;
reg soc_netsoc_sdram_bankmachine6_auto_precharge = 1'd0;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
reg soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
wire [23:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
wire [23:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
reg [3:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level = 4'd0;
reg soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_do_read;
wire [2:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_valid;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_ready;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_first;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_last;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_source_valid;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_source_ready;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_source_first;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_source_last;
reg soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_pipe_ce;
wire soc_netsoc_sdram_bankmachine6_cmd_buffer_busy;
reg soc_netsoc_sdram_bankmachine6_cmd_buffer_valid_n = 1'd0;
reg soc_netsoc_sdram_bankmachine6_cmd_buffer_first_n = 1'd0;
reg soc_netsoc_sdram_bankmachine6_cmd_buffer_last_n = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine6_row = 14'd0;
reg soc_netsoc_sdram_bankmachine6_row_opened = 1'd0;
wire soc_netsoc_sdram_bankmachine6_row_hit;
reg soc_netsoc_sdram_bankmachine6_row_open = 1'd0;
reg soc_netsoc_sdram_bankmachine6_row_close = 1'd0;
reg soc_netsoc_sdram_bankmachine6_row_col_n_addr_sel = 1'd0;
wire soc_netsoc_sdram_bankmachine6_twtpcon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine6_twtpcon_ready = 1'd1;
reg [2:0] soc_netsoc_sdram_bankmachine6_twtpcon_count = 3'd0;
wire soc_netsoc_sdram_bankmachine6_trccon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine6_trccon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine6_trccon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine6_trascon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine6_trascon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine6_trascon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine7_req_valid;
wire soc_netsoc_sdram_bankmachine7_req_ready;
wire soc_netsoc_sdram_bankmachine7_req_we;
wire [20:0] soc_netsoc_sdram_bankmachine7_req_addr;
wire soc_netsoc_sdram_bankmachine7_req_lock;
reg soc_netsoc_sdram_bankmachine7_req_wdata_ready = 1'd0;
reg soc_netsoc_sdram_bankmachine7_req_rdata_valid = 1'd0;
wire soc_netsoc_sdram_bankmachine7_refresh_req;
reg soc_netsoc_sdram_bankmachine7_refresh_gnt = 1'd0;
reg soc_netsoc_sdram_bankmachine7_cmd_valid = 1'd0;
reg soc_netsoc_sdram_bankmachine7_cmd_ready = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine7_cmd_payload_a = 14'd0;
wire [2:0] soc_netsoc_sdram_bankmachine7_cmd_payload_ba;
reg soc_netsoc_sdram_bankmachine7_cmd_payload_cas = 1'd0;
reg soc_netsoc_sdram_bankmachine7_cmd_payload_ras = 1'd0;
reg soc_netsoc_sdram_bankmachine7_cmd_payload_we = 1'd0;
reg soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0;
reg soc_netsoc_sdram_bankmachine7_cmd_payload_is_read = 1'd0;
reg soc_netsoc_sdram_bankmachine7_cmd_payload_is_write = 1'd0;
reg soc_netsoc_sdram_bankmachine7_auto_precharge = 1'd0;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
reg soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
reg soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
wire [23:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
wire [23:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
reg [3:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level = 4'd0;
reg soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we;
wire [23:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_do_read;
wire [2:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr;
wire [23:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_valid;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_ready;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_first;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_last;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_payload_we;
wire [20:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_source_valid;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_source_ready;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_source_first;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_source_last;
reg soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_pipe_ce;
wire soc_netsoc_sdram_bankmachine7_cmd_buffer_busy;
reg soc_netsoc_sdram_bankmachine7_cmd_buffer_valid_n = 1'd0;
reg soc_netsoc_sdram_bankmachine7_cmd_buffer_first_n = 1'd0;
reg soc_netsoc_sdram_bankmachine7_cmd_buffer_last_n = 1'd0;
reg [13:0] soc_netsoc_sdram_bankmachine7_row = 14'd0;
reg soc_netsoc_sdram_bankmachine7_row_opened = 1'd0;
wire soc_netsoc_sdram_bankmachine7_row_hit;
reg soc_netsoc_sdram_bankmachine7_row_open = 1'd0;
reg soc_netsoc_sdram_bankmachine7_row_close = 1'd0;
reg soc_netsoc_sdram_bankmachine7_row_col_n_addr_sel = 1'd0;
wire soc_netsoc_sdram_bankmachine7_twtpcon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine7_twtpcon_ready = 1'd1;
reg [2:0] soc_netsoc_sdram_bankmachine7_twtpcon_count = 3'd0;
wire soc_netsoc_sdram_bankmachine7_trccon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine7_trccon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine7_trccon_count = 2'd0;
wire soc_netsoc_sdram_bankmachine7_trascon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_bankmachine7_trascon_ready = 1'd1;
reg [1:0] soc_netsoc_sdram_bankmachine7_trascon_count = 2'd0;
wire soc_netsoc_sdram_ras_allowed;
wire soc_netsoc_sdram_cas_allowed;
reg soc_netsoc_sdram_choose_cmd_want_reads = 1'd0;
reg soc_netsoc_sdram_choose_cmd_want_writes = 1'd0;
reg soc_netsoc_sdram_choose_cmd_want_cmds = 1'd0;
reg soc_netsoc_sdram_choose_cmd_want_activates = 1'd0;
wire soc_netsoc_sdram_choose_cmd_cmd_valid;
reg soc_netsoc_sdram_choose_cmd_cmd_ready = 1'd0;
wire [13:0] soc_netsoc_sdram_choose_cmd_cmd_payload_a;
wire [2:0] soc_netsoc_sdram_choose_cmd_cmd_payload_ba;
reg soc_netsoc_sdram_choose_cmd_cmd_payload_cas = 1'd0;
reg soc_netsoc_sdram_choose_cmd_cmd_payload_ras = 1'd0;
reg soc_netsoc_sdram_choose_cmd_cmd_payload_we = 1'd0;
wire soc_netsoc_sdram_choose_cmd_cmd_payload_is_cmd;
wire soc_netsoc_sdram_choose_cmd_cmd_payload_is_read;
wire soc_netsoc_sdram_choose_cmd_cmd_payload_is_write;
reg [7:0] soc_netsoc_sdram_choose_cmd_valids = 8'd0;
wire [7:0] soc_netsoc_sdram_choose_cmd_request;
reg [2:0] soc_netsoc_sdram_choose_cmd_grant = 3'd0;
wire soc_netsoc_sdram_choose_cmd_ce;
reg soc_netsoc_sdram_choose_req_want_reads = 1'd0;
reg soc_netsoc_sdram_choose_req_want_writes = 1'd0;
reg soc_netsoc_sdram_choose_req_want_cmds = 1'd0;
reg soc_netsoc_sdram_choose_req_want_activates = 1'd0;
wire soc_netsoc_sdram_choose_req_cmd_valid;
reg soc_netsoc_sdram_choose_req_cmd_ready = 1'd0;
wire [13:0] soc_netsoc_sdram_choose_req_cmd_payload_a;
wire [2:0] soc_netsoc_sdram_choose_req_cmd_payload_ba;
reg soc_netsoc_sdram_choose_req_cmd_payload_cas = 1'd0;
reg soc_netsoc_sdram_choose_req_cmd_payload_ras = 1'd0;
reg soc_netsoc_sdram_choose_req_cmd_payload_we = 1'd0;
wire soc_netsoc_sdram_choose_req_cmd_payload_is_cmd;
wire soc_netsoc_sdram_choose_req_cmd_payload_is_read;
wire soc_netsoc_sdram_choose_req_cmd_payload_is_write;
reg [7:0] soc_netsoc_sdram_choose_req_valids = 8'd0;
wire [7:0] soc_netsoc_sdram_choose_req_request;
reg [2:0] soc_netsoc_sdram_choose_req_grant = 3'd0;
wire soc_netsoc_sdram_choose_req_ce;
reg [13:0] soc_netsoc_sdram_nop_a = 14'd0;
reg [2:0] soc_netsoc_sdram_nop_ba = 3'd0;
reg [1:0] soc_netsoc_sdram_steerer_sel0 = 2'd0;
reg [1:0] soc_netsoc_sdram_steerer_sel1 = 2'd0;
reg [1:0] soc_netsoc_sdram_steerer_sel2 = 2'd0;
reg [1:0] soc_netsoc_sdram_steerer_sel3 = 2'd0;
reg soc_netsoc_sdram_steerer0 = 1'd1;
reg soc_netsoc_sdram_steerer1 = 1'd1;
reg soc_netsoc_sdram_steerer2 = 1'd1;
reg soc_netsoc_sdram_steerer3 = 1'd1;
reg soc_netsoc_sdram_steerer4 = 1'd1;
reg soc_netsoc_sdram_steerer5 = 1'd1;
reg soc_netsoc_sdram_steerer6 = 1'd1;
reg soc_netsoc_sdram_steerer7 = 1'd1;
wire soc_netsoc_sdram_trrdcon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_trrdcon_ready = 1'd1;
reg soc_netsoc_sdram_trrdcon_count = 1'd0;
wire soc_netsoc_sdram_tfawcon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_tfawcon_ready = 1'd1;
wire [1:0] soc_netsoc_sdram_tfawcon_count;
reg [3:0] soc_netsoc_sdram_tfawcon_window = 4'd0;
wire soc_netsoc_sdram_tccdcon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_tccdcon_ready = 1'd1;
reg soc_netsoc_sdram_tccdcon_count = 1'd0;
wire soc_netsoc_sdram_twtrcon_valid;
(* dont_touch = "true" *) reg soc_netsoc_sdram_twtrcon_ready = 1'd1;
reg [2:0] soc_netsoc_sdram_twtrcon_count = 3'd0;
wire soc_netsoc_sdram_read_available;
wire soc_netsoc_sdram_write_available;
reg soc_netsoc_sdram_en0 = 1'd0;
wire soc_netsoc_sdram_max_time0;
reg [4:0] soc_netsoc_sdram_time0 = 5'd0;
reg soc_netsoc_sdram_en1 = 1'd0;
wire soc_netsoc_sdram_max_time1;
reg [3:0] soc_netsoc_sdram_time1 = 4'd0;
wire soc_netsoc_sdram_go_to_refresh;
wire soc_netsoc_sdram_bandwidth_update_re;
wire soc_netsoc_sdram_bandwidth_update_r;
wire soc_netsoc_sdram_bandwidth_update_we;
reg soc_netsoc_sdram_bandwidth_update_w = 1'd0;
reg [23:0] soc_netsoc_sdram_bandwidth_nreads_status = 24'd0;
wire soc_netsoc_sdram_bandwidth_nreads_we;
reg [23:0] soc_netsoc_sdram_bandwidth_nwrites_status = 24'd0;
wire soc_netsoc_sdram_bandwidth_nwrites_we;
reg [7:0] soc_netsoc_sdram_bandwidth_data_width_status = 8'd128;
wire soc_netsoc_sdram_bandwidth_data_width_we;
reg soc_netsoc_sdram_bandwidth_cmd_valid = 1'd0;
reg soc_netsoc_sdram_bandwidth_cmd_ready = 1'd0;
reg soc_netsoc_sdram_bandwidth_cmd_is_read = 1'd0;
reg soc_netsoc_sdram_bandwidth_cmd_is_write = 1'd0;
reg [23:0] soc_netsoc_sdram_bandwidth_counter = 24'd0;
reg soc_netsoc_sdram_bandwidth_period = 1'd0;
reg [23:0] soc_netsoc_sdram_bandwidth_nreads = 24'd0;
reg [23:0] soc_netsoc_sdram_bandwidth_nwrites = 24'd0;
reg [23:0] soc_netsoc_sdram_bandwidth_nreads_r = 24'd0;
reg [23:0] soc_netsoc_sdram_bandwidth_nwrites_r = 24'd0;
reg soc_netsoc_port_cmd_valid = 1'd0;
wire soc_netsoc_port_cmd_ready;
reg soc_netsoc_port_cmd_payload_we = 1'd0;
reg [23:0] soc_netsoc_port_cmd_payload_addr = 24'd0;
wire soc_netsoc_port_wdata_valid;
wire soc_netsoc_port_wdata_ready;
wire soc_netsoc_port_wdata_first;
wire soc_netsoc_port_wdata_last;
wire [127:0] soc_netsoc_port_wdata_payload_data;
wire [15:0] soc_netsoc_port_wdata_payload_we;
wire soc_netsoc_port_rdata_valid;
wire soc_netsoc_port_rdata_ready;
reg soc_netsoc_port_rdata_first = 1'd0;
reg soc_netsoc_port_rdata_last = 1'd0;
wire [127:0] soc_netsoc_port_rdata_payload_data;
wire [29:0] soc_netsoc_interface1_wb_sdram_adr;
wire [31:0] soc_netsoc_interface1_wb_sdram_dat_w;
wire [31:0] soc_netsoc_interface1_wb_sdram_dat_r;
wire [3:0] soc_netsoc_interface1_wb_sdram_sel;
wire soc_netsoc_interface1_wb_sdram_cyc;
wire soc_netsoc_interface1_wb_sdram_stb;
wire soc_netsoc_interface1_wb_sdram_ack;
wire soc_netsoc_interface1_wb_sdram_we;
wire [2:0] soc_netsoc_interface1_wb_sdram_cti;
wire [1:0] soc_netsoc_interface1_wb_sdram_bte;
wire soc_netsoc_interface1_wb_sdram_err;
wire [29:0] soc_netsoc_adr;
wire [127:0] soc_netsoc_dat_w;
wire [127:0] soc_netsoc_dat_r;
wire [15:0] soc_netsoc_sel;
reg soc_netsoc_cyc = 1'd0;
reg soc_netsoc_stb = 1'd0;
reg soc_netsoc_ack = 1'd0;
reg soc_netsoc_we = 1'd0;
wire [8:0] soc_netsoc_data_port_adr;
wire [127:0] soc_netsoc_data_port_dat_r;
reg [15:0] soc_netsoc_data_port_we = 16'd0;
reg [127:0] soc_netsoc_data_port_dat_w = 128'd0;
reg soc_netsoc_write_from_slave = 1'd0;
reg [1:0] soc_netsoc_adr_offset_r = 2'd0;
wire [8:0] soc_netsoc_tag_port_adr;
wire [23:0] soc_netsoc_tag_port_dat_r;
reg soc_netsoc_tag_port_we = 1'd0;
wire [23:0] soc_netsoc_tag_port_dat_w;
wire [22:0] soc_netsoc_tag_do_tag;
wire soc_netsoc_tag_do_dirty;
wire [22:0] soc_netsoc_tag_di_tag;
reg soc_netsoc_tag_di_dirty = 1'd0;
reg soc_netsoc_word_clr = 1'd0;
reg soc_netsoc_word_inc = 1'd0;
wire soc_netsoc_wdata_converter_sink_valid;
wire soc_netsoc_wdata_converter_sink_ready;
reg soc_netsoc_wdata_converter_sink_first = 1'd0;
reg soc_netsoc_wdata_converter_sink_last = 1'd0;
wire [127:0] soc_netsoc_wdata_converter_sink_payload_data;
wire [15:0] soc_netsoc_wdata_converter_sink_payload_we;
wire soc_netsoc_wdata_converter_source_valid;
wire soc_netsoc_wdata_converter_source_ready;
wire soc_netsoc_wdata_converter_source_first;
wire soc_netsoc_wdata_converter_source_last;
wire [127:0] soc_netsoc_wdata_converter_source_payload_data;
wire [15:0] soc_netsoc_wdata_converter_source_payload_we;
wire soc_netsoc_wdata_converter_converter_sink_valid;
wire soc_netsoc_wdata_converter_converter_sink_ready;
wire soc_netsoc_wdata_converter_converter_sink_first;
wire soc_netsoc_wdata_converter_converter_sink_last;
wire [143:0] soc_netsoc_wdata_converter_converter_sink_payload_data;
wire soc_netsoc_wdata_converter_converter_source_valid;
wire soc_netsoc_wdata_converter_converter_source_ready;
wire soc_netsoc_wdata_converter_converter_source_first;
wire soc_netsoc_wdata_converter_converter_source_last;
wire [143:0] soc_netsoc_wdata_converter_converter_source_payload_data;
wire soc_netsoc_wdata_converter_converter_source_payload_valid_token_count;
wire soc_netsoc_wdata_converter_source_source_valid;
wire soc_netsoc_wdata_converter_source_source_ready;
wire soc_netsoc_wdata_converter_source_source_first;
wire soc_netsoc_wdata_converter_source_source_last;
wire [143:0] soc_netsoc_wdata_converter_source_source_payload_data;
wire soc_netsoc_rdata_converter_sink_valid;
wire soc_netsoc_rdata_converter_sink_ready;
wire soc_netsoc_rdata_converter_sink_first;
wire soc_netsoc_rdata_converter_sink_last;
wire [127:0] soc_netsoc_rdata_converter_sink_payload_data;
wire soc_netsoc_rdata_converter_source_valid;
wire soc_netsoc_rdata_converter_source_ready;
wire soc_netsoc_rdata_converter_source_first;
wire soc_netsoc_rdata_converter_source_last;
wire [127:0] soc_netsoc_rdata_converter_source_payload_data;
wire soc_netsoc_rdata_converter_converter_sink_valid;
wire soc_netsoc_rdata_converter_converter_sink_ready;
wire soc_netsoc_rdata_converter_converter_sink_first;
wire soc_netsoc_rdata_converter_converter_sink_last;
wire [127:0] soc_netsoc_rdata_converter_converter_sink_payload_data;
wire soc_netsoc_rdata_converter_converter_source_valid;
wire soc_netsoc_rdata_converter_converter_source_ready;
wire soc_netsoc_rdata_converter_converter_source_first;
wire soc_netsoc_rdata_converter_converter_source_last;
wire [127:0] soc_netsoc_rdata_converter_converter_source_payload_data;
wire soc_netsoc_rdata_converter_converter_source_payload_valid_token_count;
wire soc_netsoc_rdata_converter_source_source_valid;
wire soc_netsoc_rdata_converter_source_source_ready;
wire soc_netsoc_rdata_converter_source_source_first;
wire soc_netsoc_rdata_converter_source_source_last;
wire [127:0] soc_netsoc_rdata_converter_source_source_payload_data;
reg soc_netsoc_count = 1'd0;
reg soc_reset_storage = 1'd0;
reg soc_reset_re = 1'd0;
(* dont_touch = "true" *) wire eth_rx_clk;
wire eth_rx_rst;
(* dont_touch = "true" *) wire eth_tx_clk;
wire eth_tx_rst;
wire soc_reset0;
wire soc_reset1;
reg [8:0] soc_counter = 9'd0;
wire soc_counter_done;
wire soc_counter_ce;
wire soc_liteethphymiitx_sink_sink_valid;
wire soc_liteethphymiitx_sink_sink_ready;
wire soc_liteethphymiitx_sink_sink_first;
wire soc_liteethphymiitx_sink_sink_last;
wire [7:0] soc_liteethphymiitx_sink_sink_payload_data;
wire soc_liteethphymiitx_sink_sink_payload_last_be;
wire soc_liteethphymiitx_sink_sink_payload_error;
wire soc_liteethphymiitx_converter_sink_valid;
wire soc_liteethphymiitx_converter_sink_ready;
reg soc_liteethphymiitx_converter_sink_first = 1'd0;
reg soc_liteethphymiitx_converter_sink_last = 1'd0;
wire [7:0] soc_liteethphymiitx_converter_sink_payload_data;
wire soc_liteethphymiitx_converter_source_valid;
wire soc_liteethphymiitx_converter_source_ready;
wire soc_liteethphymiitx_converter_source_first;
wire soc_liteethphymiitx_converter_source_last;
wire [3:0] soc_liteethphymiitx_converter_source_payload_data;
wire soc_liteethphymiitx_converter_converter_sink_valid;
wire soc_liteethphymiitx_converter_converter_sink_ready;
wire soc_liteethphymiitx_converter_converter_sink_first;
wire soc_liteethphymiitx_converter_converter_sink_last;
reg [7:0] soc_liteethphymiitx_converter_converter_sink_payload_data = 8'd0;
wire soc_liteethphymiitx_converter_converter_source_valid;
wire soc_liteethphymiitx_converter_converter_source_ready;
wire soc_liteethphymiitx_converter_converter_source_first;
wire soc_liteethphymiitx_converter_converter_source_last;
reg [3:0] soc_liteethphymiitx_converter_converter_source_payload_data = 4'd0;
wire soc_liteethphymiitx_converter_converter_source_payload_valid_token_count;
reg soc_liteethphymiitx_converter_converter_mux = 1'd0;
wire soc_liteethphymiitx_converter_converter_first;
wire soc_liteethphymiitx_converter_converter_last;
wire soc_liteethphymiitx_converter_source_source_valid;
wire soc_liteethphymiitx_converter_source_source_ready;
wire soc_liteethphymiitx_converter_source_source_first;
wire soc_liteethphymiitx_converter_source_source_last;
wire [3:0] soc_liteethphymiitx_converter_source_source_payload_data;
wire soc_liteethphymiirx_source_source_valid;
wire soc_liteethphymiirx_source_source_ready;
wire soc_liteethphymiirx_source_source_first;
wire soc_liteethphymiirx_source_source_last;
wire [7:0] soc_liteethphymiirx_source_source_payload_data;
reg soc_liteethphymiirx_source_source_payload_last_be = 1'd0;
reg soc_liteethphymiirx_source_source_payload_error = 1'd0;
reg soc_liteethphymiirx_converter_sink_valid = 1'd0;
wire soc_liteethphymiirx_converter_sink_ready;
reg soc_liteethphymiirx_converter_sink_first = 1'd0;
wire soc_liteethphymiirx_converter_sink_last;
reg [3:0] soc_liteethphymiirx_converter_sink_payload_data = 4'd0;
wire soc_liteethphymiirx_converter_source_valid;
wire soc_liteethphymiirx_converter_source_ready;
wire soc_liteethphymiirx_converter_source_first;
wire soc_liteethphymiirx_converter_source_last;
reg [7:0] soc_liteethphymiirx_converter_source_payload_data = 8'd0;
wire soc_liteethphymiirx_converter_converter_sink_valid;
wire soc_liteethphymiirx_converter_converter_sink_ready;
wire soc_liteethphymiirx_converter_converter_sink_first;
wire soc_liteethphymiirx_converter_converter_sink_last;
wire [3:0] soc_liteethphymiirx_converter_converter_sink_payload_data;
wire soc_liteethphymiirx_converter_converter_source_valid;
wire soc_liteethphymiirx_converter_converter_source_ready;
reg soc_liteethphymiirx_converter_converter_source_first = 1'd0;
reg soc_liteethphymiirx_converter_converter_source_last = 1'd0;
reg [7:0] soc_liteethphymiirx_converter_converter_source_payload_data = 8'd0;
reg [1:0] soc_liteethphymiirx_converter_converter_source_payload_valid_token_count = 2'd0;
reg soc_liteethphymiirx_converter_converter_demux = 1'd0;
wire soc_liteethphymiirx_converter_converter_load_part;
reg soc_liteethphymiirx_converter_converter_strobe_all = 1'd0;
wire soc_liteethphymiirx_converter_source_source_valid;
wire soc_liteethphymiirx_converter_source_source_ready;
wire soc_liteethphymiirx_converter_source_source_first;
wire soc_liteethphymiirx_converter_source_source_last;
wire [7:0] soc_liteethphymiirx_converter_source_source_payload_data;
reg soc_liteethphymiirx_converter_reset = 1'd0;
wire soc_mdc;
wire soc_oe;
wire soc_w;
reg [2:0] soc_storage = 3'd0;
reg soc_re = 1'd0;
reg soc_r = 1'd0;
reg soc_status = 1'd0;
wire soc_we;
wire soc_data_w;
wire soc_data_oe;
wire soc_data_r;
wire soc_tx_gap_inserter_sink_valid;
reg soc_tx_gap_inserter_sink_ready = 1'd0;
wire soc_tx_gap_inserter_sink_first;
wire soc_tx_gap_inserter_sink_last;
wire [7:0] soc_tx_gap_inserter_sink_payload_data;
wire soc_tx_gap_inserter_sink_payload_last_be;
wire soc_tx_gap_inserter_sink_payload_error;
reg soc_tx_gap_inserter_source_valid = 1'd0;
wire soc_tx_gap_inserter_source_ready;
reg soc_tx_gap_inserter_source_first = 1'd0;
reg soc_tx_gap_inserter_source_last = 1'd0;
reg [7:0] soc_tx_gap_inserter_source_payload_data = 8'd0;
reg soc_tx_gap_inserter_source_payload_last_be = 1'd0;
reg soc_tx_gap_inserter_source_payload_error = 1'd0;
reg [3:0] soc_tx_gap_inserter_counter = 4'd0;
reg soc_tx_gap_inserter_counter_reset = 1'd0;
reg soc_tx_gap_inserter_counter_ce = 1'd0;
reg soc_preamble_crc_status = 1'd1;
wire soc_preamble_crc_we;
reg [31:0] soc_preamble_errors_status = 32'd0;
wire soc_preamble_errors_we;
reg [31:0] soc_crc_errors_status = 32'd0;
wire soc_crc_errors_we;
wire soc_preamble_inserter_sink_valid;
reg soc_preamble_inserter_sink_ready = 1'd0;
wire soc_preamble_inserter_sink_first;
wire soc_preamble_inserter_sink_last;
wire [7:0] soc_preamble_inserter_sink_payload_data;
wire soc_preamble_inserter_sink_payload_last_be;
wire soc_preamble_inserter_sink_payload_error;
reg soc_preamble_inserter_source_valid = 1'd0;
wire soc_preamble_inserter_source_ready;
reg soc_preamble_inserter_source_first = 1'd0;
reg soc_preamble_inserter_source_last = 1'd0;
reg [7:0] soc_preamble_inserter_source_payload_data = 8'd0;
wire soc_preamble_inserter_source_payload_last_be;
reg soc_preamble_inserter_source_payload_error = 1'd0;
reg [63:0] soc_preamble_inserter_preamble = 64'd15372286728091293013;
reg [2:0] soc_preamble_inserter_cnt = 3'd0;
reg soc_preamble_inserter_clr_cnt = 1'd0;
reg soc_preamble_inserter_inc_cnt = 1'd0;
wire soc_preamble_checker_sink_valid;
reg soc_preamble_checker_sink_ready = 1'd0;
wire soc_preamble_checker_sink_first;
wire soc_preamble_checker_sink_last;
wire [7:0] soc_preamble_checker_sink_payload_data;
wire soc_preamble_checker_sink_payload_last_be;
wire soc_preamble_checker_sink_payload_error;
reg soc_preamble_checker_source_valid = 1'd0;
wire soc_preamble_checker_source_ready;
reg soc_preamble_checker_source_first = 1'd0;
reg soc_preamble_checker_source_last = 1'd0;
wire [7:0] soc_preamble_checker_source_payload_data;
wire soc_preamble_checker_source_payload_last_be;
reg soc_preamble_checker_source_payload_error = 1'd0;
reg soc_preamble_checker_error = 1'd0;
wire soc_crc32_inserter_sink_valid;
reg soc_crc32_inserter_sink_ready = 1'd0;
wire soc_crc32_inserter_sink_first;
wire soc_crc32_inserter_sink_last;
wire [7:0] soc_crc32_inserter_sink_payload_data;
wire soc_crc32_inserter_sink_payload_last_be;
wire soc_crc32_inserter_sink_payload_error;
reg soc_crc32_inserter_source_valid = 1'd0;
wire soc_crc32_inserter_source_ready;
reg soc_crc32_inserter_source_first = 1'd0;
reg soc_crc32_inserter_source_last = 1'd0;
reg [7:0] soc_crc32_inserter_source_payload_data = 8'd0;
reg soc_crc32_inserter_source_payload_last_be = 1'd0;
reg soc_crc32_inserter_source_payload_error = 1'd0;
reg [7:0] soc_crc32_inserter_data0 = 8'd0;
wire [31:0] soc_crc32_inserter_value;
wire soc_crc32_inserter_error;
wire [7:0] soc_crc32_inserter_data1;
wire [31:0] soc_crc32_inserter_last;
reg [31:0] soc_crc32_inserter_next = 32'd0;
reg [31:0] soc_crc32_inserter_reg = 32'd4294967295;
reg soc_crc32_inserter_ce = 1'd0;
reg soc_crc32_inserter_reset = 1'd0;
reg [1:0] soc_crc32_inserter_cnt = 2'd3;
wire soc_crc32_inserter_cnt_done;
reg soc_crc32_inserter_is_ongoing0 = 1'd0;
reg soc_crc32_inserter_is_ongoing1 = 1'd0;
wire soc_crc32_checker_sink_sink_valid;
reg soc_crc32_checker_sink_sink_ready = 1'd0;
wire soc_crc32_checker_sink_sink_first;
wire soc_crc32_checker_sink_sink_last;
wire [7:0] soc_crc32_checker_sink_sink_payload_data;
wire soc_crc32_checker_sink_sink_payload_last_be;
wire soc_crc32_checker_sink_sink_payload_error;
wire soc_crc32_checker_source_source_valid;
wire soc_crc32_checker_source_source_ready;
reg soc_crc32_checker_source_source_first = 1'd0;
wire soc_crc32_checker_source_source_last;
wire [7:0] soc_crc32_checker_source_source_payload_data;
wire soc_crc32_checker_source_source_payload_last_be;
reg soc_crc32_checker_source_source_payload_error = 1'd0;
wire soc_crc32_checker_error;
wire [7:0] soc_crc32_checker_crc_data0;
wire [31:0] soc_crc32_checker_crc_value;
wire soc_crc32_checker_crc_error;
wire [7:0] soc_crc32_checker_crc_data1;
wire [31:0] soc_crc32_checker_crc_last;
reg [31:0] soc_crc32_checker_crc_next = 32'd0;
reg [31:0] soc_crc32_checker_crc_reg = 32'd4294967295;
reg soc_crc32_checker_crc_ce = 1'd0;
reg soc_crc32_checker_crc_reset = 1'd0;
reg soc_crc32_checker_syncfifo_sink_valid = 1'd0;
wire soc_crc32_checker_syncfifo_sink_ready;
wire soc_crc32_checker_syncfifo_sink_first;
wire soc_crc32_checker_syncfifo_sink_last;
wire [7:0] soc_crc32_checker_syncfifo_sink_payload_data;
wire soc_crc32_checker_syncfifo_sink_payload_last_be;
wire soc_crc32_checker_syncfifo_sink_payload_error;
wire soc_crc32_checker_syncfifo_source_valid;
wire soc_crc32_checker_syncfifo_source_ready;
wire soc_crc32_checker_syncfifo_source_first;
wire soc_crc32_checker_syncfifo_source_last;
wire [7:0] soc_crc32_checker_syncfifo_source_payload_data;
wire soc_crc32_checker_syncfifo_source_payload_last_be;
wire soc_crc32_checker_syncfifo_source_payload_error;
wire soc_crc32_checker_syncfifo_syncfifo_we;
wire soc_crc32_checker_syncfifo_syncfifo_writable;
wire soc_crc32_checker_syncfifo_syncfifo_re;
wire soc_crc32_checker_syncfifo_syncfifo_readable;
wire [11:0] soc_crc32_checker_syncfifo_syncfifo_din;
wire [11:0] soc_crc32_checker_syncfifo_syncfifo_dout;
reg [2:0] soc_crc32_checker_syncfifo_level = 3'd0;
reg soc_crc32_checker_syncfifo_replace = 1'd0;
reg [2:0] soc_crc32_checker_syncfifo_produce = 3'd0;
reg [2:0] soc_crc32_checker_syncfifo_consume = 3'd0;
reg [2:0] soc_crc32_checker_syncfifo_wrport_adr = 3'd0;
wire [11:0] soc_crc32_checker_syncfifo_wrport_dat_r;
wire soc_crc32_checker_syncfifo_wrport_we;
wire [11:0] soc_crc32_checker_syncfifo_wrport_dat_w;
wire soc_crc32_checker_syncfifo_do_read;
wire [2:0] soc_crc32_checker_syncfifo_rdport_adr;
wire [11:0] soc_crc32_checker_syncfifo_rdport_dat_r;
wire [7:0] soc_crc32_checker_syncfifo_fifo_in_payload_data;
wire soc_crc32_checker_syncfifo_fifo_in_payload_last_be;
wire soc_crc32_checker_syncfifo_fifo_in_payload_error;
wire soc_crc32_checker_syncfifo_fifo_in_first;
wire soc_crc32_checker_syncfifo_fifo_in_last;
wire [7:0] soc_crc32_checker_syncfifo_fifo_out_payload_data;
wire soc_crc32_checker_syncfifo_fifo_out_payload_last_be;
wire soc_crc32_checker_syncfifo_fifo_out_payload_error;
wire soc_crc32_checker_syncfifo_fifo_out_first;
wire soc_crc32_checker_syncfifo_fifo_out_last;
reg soc_crc32_checker_fifo_reset = 1'd0;
wire soc_crc32_checker_fifo_in;
wire soc_crc32_checker_fifo_out;
wire soc_crc32_checker_fifo_full;
wire soc_ps_preamble_error_i;
wire soc_ps_preamble_error_o;
reg soc_ps_preamble_error_toggle_i = 1'd0;
wire soc_ps_preamble_error_toggle_o;
reg soc_ps_preamble_error_toggle_o_r = 1'd0;
wire soc_ps_crc_error_i;
wire soc_ps_crc_error_o;
reg soc_ps_crc_error_toggle_i = 1'd0;
wire soc_ps_crc_error_toggle_o;
reg soc_ps_crc_error_toggle_o_r = 1'd0;
wire soc_padding_inserter_sink_valid;
reg soc_padding_inserter_sink_ready = 1'd0;
wire soc_padding_inserter_sink_first;
wire soc_padding_inserter_sink_last;
wire [7:0] soc_padding_inserter_sink_payload_data;
wire soc_padding_inserter_sink_payload_last_be;
wire soc_padding_inserter_sink_payload_error;
reg soc_padding_inserter_source_valid = 1'd0;
wire soc_padding_inserter_source_ready;
reg soc_padding_inserter_source_first = 1'd0;
reg soc_padding_inserter_source_last = 1'd0;
reg [7:0] soc_padding_inserter_source_payload_data = 8'd0;
reg soc_padding_inserter_source_payload_last_be = 1'd0;
reg soc_padding_inserter_source_payload_error = 1'd0;
reg [15:0] soc_padding_inserter_counter = 16'd1;
wire soc_padding_inserter_counter_done;
reg soc_padding_inserter_counter_reset = 1'd0;
reg soc_padding_inserter_counter_ce = 1'd0;
wire soc_padding_checker_sink_valid;
wire soc_padding_checker_sink_ready;
wire soc_padding_checker_sink_first;
wire soc_padding_checker_sink_last;
wire [7:0] soc_padding_checker_sink_payload_data;
wire soc_padding_checker_sink_payload_last_be;
wire soc_padding_checker_sink_payload_error;
wire soc_padding_checker_source_valid;
wire soc_padding_checker_source_ready;
wire soc_padding_checker_source_first;
wire soc_padding_checker_source_last;
wire [7:0] soc_padding_checker_source_payload_data;
wire soc_padding_checker_source_payload_last_be;
wire soc_padding_checker_source_payload_error;
wire soc_tx_last_be_sink_valid;
wire soc_tx_last_be_sink_ready;
wire soc_tx_last_be_sink_first;
wire soc_tx_last_be_sink_last;
wire [7:0] soc_tx_last_be_sink_payload_data;
wire soc_tx_last_be_sink_payload_last_be;
wire soc_tx_last_be_sink_payload_error;
wire soc_tx_last_be_source_valid;
wire soc_tx_last_be_source_ready;
reg soc_tx_last_be_source_first = 1'd0;
wire soc_tx_last_be_source_last;
wire [7:0] soc_tx_last_be_source_payload_data;
reg soc_tx_last_be_source_payload_last_be = 1'd0;
reg soc_tx_last_be_source_payload_error = 1'd0;
reg soc_tx_last_be_ongoing = 1'd1;
wire soc_rx_last_be_sink_valid;
wire soc_rx_last_be_sink_ready;
wire soc_rx_last_be_sink_first;
wire soc_rx_last_be_sink_last;
wire [7:0] soc_rx_last_be_sink_payload_data;
wire soc_rx_last_be_sink_payload_last_be;
wire soc_rx_last_be_sink_payload_error;
wire soc_rx_last_be_source_valid;
wire soc_rx_last_be_source_ready;
wire soc_rx_last_be_source_first;
wire soc_rx_last_be_source_last;
wire [7:0] soc_rx_last_be_source_payload_data;
reg soc_rx_last_be_source_payload_last_be = 1'd0;
wire soc_rx_last_be_source_payload_error;
wire soc_tx_converter_sink_valid;
wire soc_tx_converter_sink_ready;
wire soc_tx_converter_sink_first;
wire soc_tx_converter_sink_last;
wire [31:0] soc_tx_converter_sink_payload_data;
wire [3:0] soc_tx_converter_sink_payload_last_be;
wire [3:0] soc_tx_converter_sink_payload_error;
wire soc_tx_converter_source_valid;
wire soc_tx_converter_source_ready;
wire soc_tx_converter_source_first;
wire soc_tx_converter_source_last;
wire [7:0] soc_tx_converter_source_payload_data;
wire soc_tx_converter_source_payload_last_be;
wire soc_tx_converter_source_payload_error;
wire soc_tx_converter_converter_sink_valid;
wire soc_tx_converter_converter_sink_ready;
wire soc_tx_converter_converter_sink_first;
wire soc_tx_converter_converter_sink_last;
reg [39:0] soc_tx_converter_converter_sink_payload_data = 40'd0;
wire soc_tx_converter_converter_source_valid;
wire soc_tx_converter_converter_source_ready;
wire soc_tx_converter_converter_source_first;
wire soc_tx_converter_converter_source_last;
reg [9:0] soc_tx_converter_converter_source_payload_data = 10'd0;
wire soc_tx_converter_converter_source_payload_valid_token_count;
reg [1:0] soc_tx_converter_converter_mux = 2'd0;
wire soc_tx_converter_converter_first;
wire soc_tx_converter_converter_last;
wire soc_tx_converter_source_source_valid;
wire soc_tx_converter_source_source_ready;
wire soc_tx_converter_source_source_first;
wire soc_tx_converter_source_source_last;
wire [9:0] soc_tx_converter_source_source_payload_data;
wire soc_rx_converter_sink_valid;
wire soc_rx_converter_sink_ready;
wire soc_rx_converter_sink_first;
wire soc_rx_converter_sink_last;
wire [7:0] soc_rx_converter_sink_payload_data;
wire soc_rx_converter_sink_payload_last_be;
wire soc_rx_converter_sink_payload_error;
wire soc_rx_converter_source_valid;
wire soc_rx_converter_source_ready;
wire soc_rx_converter_source_first;
wire soc_rx_converter_source_last;
reg [31:0] soc_rx_converter_source_payload_data = 32'd0;
reg [3:0] soc_rx_converter_source_payload_last_be = 4'd0;
reg [3:0] soc_rx_converter_source_payload_error = 4'd0;
wire soc_rx_converter_converter_sink_valid;
wire soc_rx_converter_converter_sink_ready;
wire soc_rx_converter_converter_sink_first;
wire soc_rx_converter_converter_sink_last;
wire [9:0] soc_rx_converter_converter_sink_payload_data;
wire soc_rx_converter_converter_source_valid;
wire soc_rx_converter_converter_source_ready;
reg soc_rx_converter_converter_source_first = 1'd0;
reg soc_rx_converter_converter_source_last = 1'd0;
reg [39:0] soc_rx_converter_converter_source_payload_data = 40'd0;
reg [2:0] soc_rx_converter_converter_source_payload_valid_token_count = 3'd0;
reg [1:0] soc_rx_converter_converter_demux = 2'd0;
wire soc_rx_converter_converter_load_part;
reg soc_rx_converter_converter_strobe_all = 1'd0;
wire soc_rx_converter_source_source_valid;
wire soc_rx_converter_source_source_ready;
wire soc_rx_converter_source_source_first;
wire soc_rx_converter_source_source_last;
wire [39:0] soc_rx_converter_source_source_payload_data;
wire soc_tx_cdc_sink_valid;
wire soc_tx_cdc_sink_ready;
wire soc_tx_cdc_sink_first;
wire soc_tx_cdc_sink_last;
wire [31:0] soc_tx_cdc_sink_payload_data;
wire [3:0] soc_tx_cdc_sink_payload_last_be;
wire [3:0] soc_tx_cdc_sink_payload_error;
wire soc_tx_cdc_source_valid;
wire soc_tx_cdc_source_ready;
wire soc_tx_cdc_source_first;
wire soc_tx_cdc_source_last;
wire [31:0] soc_tx_cdc_source_payload_data;
wire [3:0] soc_tx_cdc_source_payload_last_be;
wire [3:0] soc_tx_cdc_source_payload_error;
wire soc_tx_cdc_asyncfifo_we;
wire soc_tx_cdc_asyncfifo_writable;
wire soc_tx_cdc_asyncfifo_re;
wire soc_tx_cdc_asyncfifo_readable;
wire [41:0] soc_tx_cdc_asyncfifo_din;
wire [41:0] soc_tx_cdc_asyncfifo_dout;
wire soc_tx_cdc_graycounter0_ce;
(* dont_touch = "true" *) reg [6:0] soc_tx_cdc_graycounter0_q = 7'd0;
wire [6:0] soc_tx_cdc_graycounter0_q_next;
reg [6:0] soc_tx_cdc_graycounter0_q_binary = 7'd0;
reg [6:0] soc_tx_cdc_graycounter0_q_next_binary = 7'd0;
wire soc_tx_cdc_graycounter1_ce;
(* dont_touch = "true" *) reg [6:0] soc_tx_cdc_graycounter1_q = 7'd0;
wire [6:0] soc_tx_cdc_graycounter1_q_next;
reg [6:0] soc_tx_cdc_graycounter1_q_binary = 7'd0;
reg [6:0] soc_tx_cdc_graycounter1_q_next_binary = 7'd0;
wire [6:0] soc_tx_cdc_produce_rdomain;
wire [6:0] soc_tx_cdc_consume_wdomain;
wire [5:0] soc_tx_cdc_wrport_adr;
wire [41:0] soc_tx_cdc_wrport_dat_r;
wire soc_tx_cdc_wrport_we;
wire [41:0] soc_tx_cdc_wrport_dat_w;
wire [5:0] soc_tx_cdc_rdport_adr;
wire [41:0] soc_tx_cdc_rdport_dat_r;
wire [31:0] soc_tx_cdc_fifo_in_payload_data;
wire [3:0] soc_tx_cdc_fifo_in_payload_last_be;
wire [3:0] soc_tx_cdc_fifo_in_payload_error;
wire soc_tx_cdc_fifo_in_first;
wire soc_tx_cdc_fifo_in_last;
wire [31:0] soc_tx_cdc_fifo_out_payload_data;
wire [3:0] soc_tx_cdc_fifo_out_payload_last_be;
wire [3:0] soc_tx_cdc_fifo_out_payload_error;
wire soc_tx_cdc_fifo_out_first;
wire soc_tx_cdc_fifo_out_last;
wire soc_rx_cdc_sink_valid;
wire soc_rx_cdc_sink_ready;
wire soc_rx_cdc_sink_first;
wire soc_rx_cdc_sink_last;
wire [31:0] soc_rx_cdc_sink_payload_data;
wire [3:0] soc_rx_cdc_sink_payload_last_be;
wire [3:0] soc_rx_cdc_sink_payload_error;
wire soc_rx_cdc_source_valid;
wire soc_rx_cdc_source_ready;
wire soc_rx_cdc_source_first;
wire soc_rx_cdc_source_last;
wire [31:0] soc_rx_cdc_source_payload_data;
wire [3:0] soc_rx_cdc_source_payload_last_be;
wire [3:0] soc_rx_cdc_source_payload_error;
wire soc_rx_cdc_asyncfifo_we;
wire soc_rx_cdc_asyncfifo_writable;
wire soc_rx_cdc_asyncfifo_re;
wire soc_rx_cdc_asyncfifo_readable;
wire [41:0] soc_rx_cdc_asyncfifo_din;
wire [41:0] soc_rx_cdc_asyncfifo_dout;
wire soc_rx_cdc_graycounter0_ce;
(* dont_touch = "true" *) reg [6:0] soc_rx_cdc_graycounter0_q = 7'd0;
wire [6:0] soc_rx_cdc_graycounter0_q_next;
reg [6:0] soc_rx_cdc_graycounter0_q_binary = 7'd0;
reg [6:0] soc_rx_cdc_graycounter0_q_next_binary = 7'd0;
wire soc_rx_cdc_graycounter1_ce;
(* dont_touch = "true" *) reg [6:0] soc_rx_cdc_graycounter1_q = 7'd0;
wire [6:0] soc_rx_cdc_graycounter1_q_next;
reg [6:0] soc_rx_cdc_graycounter1_q_binary = 7'd0;
reg [6:0] soc_rx_cdc_graycounter1_q_next_binary = 7'd0;
wire [6:0] soc_rx_cdc_produce_rdomain;
wire [6:0] soc_rx_cdc_consume_wdomain;
wire [5:0] soc_rx_cdc_wrport_adr;
wire [41:0] soc_rx_cdc_wrport_dat_r;
wire soc_rx_cdc_wrport_we;
wire [41:0] soc_rx_cdc_wrport_dat_w;
wire [5:0] soc_rx_cdc_rdport_adr;
wire [41:0] soc_rx_cdc_rdport_dat_r;
wire [31:0] soc_rx_cdc_fifo_in_payload_data;
wire [3:0] soc_rx_cdc_fifo_in_payload_last_be;
wire [3:0] soc_rx_cdc_fifo_in_payload_error;
wire soc_rx_cdc_fifo_in_first;
wire soc_rx_cdc_fifo_in_last;
wire [31:0] soc_rx_cdc_fifo_out_payload_data;
wire [3:0] soc_rx_cdc_fifo_out_payload_last_be;
wire [3:0] soc_rx_cdc_fifo_out_payload_error;
wire soc_rx_cdc_fifo_out_first;
wire soc_rx_cdc_fifo_out_last;
wire soc_sink_valid;
wire soc_sink_ready;
wire soc_sink_first;
wire soc_sink_last;
wire [31:0] soc_sink_payload_data;
wire [3:0] soc_sink_payload_last_be;
wire [3:0] soc_sink_payload_error;
wire soc_source_valid;
wire soc_source_ready;
wire soc_source_first;
wire soc_source_last;
wire [31:0] soc_source_payload_data;
wire [3:0] soc_source_payload_last_be;
wire [3:0] soc_source_payload_error;
wire [29:0] soc_bus_adr;
wire [31:0] soc_bus_dat_w;
wire [31:0] soc_bus_dat_r;
wire [3:0] soc_bus_sel;
wire soc_bus_cyc;
wire soc_bus_stb;
wire soc_bus_ack;
wire soc_bus_we;
wire [2:0] soc_bus_cti;
wire [1:0] soc_bus_bte;
wire soc_bus_err;
wire soc_writer_sink_sink_valid;
reg soc_writer_sink_sink_ready = 1'd1;
wire soc_writer_sink_sink_first;
wire soc_writer_sink_sink_last;
wire [31:0] soc_writer_sink_sink_payload_data;
wire [3:0] soc_writer_sink_sink_payload_last_be;
wire [3:0] soc_writer_sink_sink_payload_error;
wire soc_writer_slot_status;
wire soc_writer_slot_we;
wire [31:0] soc_writer_length_status;
wire soc_writer_length_we;
reg [31:0] soc_writer_errors_status = 32'd0;
wire soc_writer_errors_we;
wire soc_writer_irq;
wire soc_writer_available_status;
wire soc_writer_available_pending;
wire soc_writer_available_trigger;
reg soc_writer_available_clear = 1'd0;
wire soc_writer_status_re;
wire soc_writer_status_r;
wire soc_writer_status_we;
wire soc_writer_status_w;
wire soc_writer_pending_re;
wire soc_writer_pending_r;
wire soc_writer_pending_we;
wire soc_writer_pending_w;
reg soc_writer_storage = 1'd0;
reg soc_writer_re = 1'd0;
reg [2:0] soc_writer_inc = 3'd0;
reg [31:0] soc_writer_counter = 32'd0;
reg soc_writer_counter_reset = 1'd0;
reg soc_writer_counter_ce = 1'd0;
reg soc_writer_slot = 1'd0;
reg soc_writer_slot_ce = 1'd0;
reg soc_writer_ongoing = 1'd0;
reg soc_writer_fifo_sink_valid = 1'd0;
wire soc_writer_fifo_sink_ready;
reg soc_writer_fifo_sink_first = 1'd0;
reg soc_writer_fifo_sink_last = 1'd0;
wire soc_writer_fifo_sink_payload_slot;
wire [31:0] soc_writer_fifo_sink_payload_length;
wire soc_writer_fifo_source_valid;
wire soc_writer_fifo_source_ready;
wire soc_writer_fifo_source_first;
wire soc_writer_fifo_source_last;
wire soc_writer_fifo_source_payload_slot;
wire [31:0] soc_writer_fifo_source_payload_length;
wire soc_writer_fifo_syncfifo_we;
wire soc_writer_fifo_syncfifo_writable;
wire soc_writer_fifo_syncfifo_re;
wire soc_writer_fifo_syncfifo_readable;
wire [34:0] soc_writer_fifo_syncfifo_din;
wire [34:0] soc_writer_fifo_syncfifo_dout;
reg [1:0] soc_writer_fifo_level = 2'd0;
reg soc_writer_fifo_replace = 1'd0;
reg soc_writer_fifo_produce = 1'd0;
reg soc_writer_fifo_consume = 1'd0;
reg soc_writer_fifo_wrport_adr = 1'd0;
wire [34:0] soc_writer_fifo_wrport_dat_r;
wire soc_writer_fifo_wrport_we;
wire [34:0] soc_writer_fifo_wrport_dat_w;
wire soc_writer_fifo_do_read;
wire soc_writer_fifo_rdport_adr;
wire [34:0] soc_writer_fifo_rdport_dat_r;
wire soc_writer_fifo_fifo_in_payload_slot;
wire [31:0] soc_writer_fifo_fifo_in_payload_length;
wire soc_writer_fifo_fifo_in_first;
wire soc_writer_fifo_fifo_in_last;
wire soc_writer_fifo_fifo_out_payload_slot;
wire [31:0] soc_writer_fifo_fifo_out_payload_length;
wire soc_writer_fifo_fifo_out_first;
wire soc_writer_fifo_fifo_out_last;
reg [8:0] soc_writer_memory0_adr = 9'd0;
wire [31:0] soc_writer_memory0_dat_r;
reg soc_writer_memory0_we = 1'd0;
reg [31:0] soc_writer_memory0_dat_w = 32'd0;
reg [8:0] soc_writer_memory1_adr = 9'd0;
wire [31:0] soc_writer_memory1_dat_r;
reg soc_writer_memory1_we = 1'd0;
reg [31:0] soc_writer_memory1_dat_w = 32'd0;
reg soc_reader_source_source_valid = 1'd0;
wire soc_reader_source_source_ready;
reg soc_reader_source_source_first = 1'd0;
reg soc_reader_source_source_last = 1'd0;
reg [31:0] soc_reader_source_source_payload_data = 32'd0;
reg [3:0] soc_reader_source_source_payload_last_be = 4'd0;
reg [3:0] soc_reader_source_source_payload_error = 4'd0;
wire soc_reader_start_re;
wire soc_reader_start_r;
wire soc_reader_start_we;
reg soc_reader_start_w = 1'd0;
wire soc_reader_ready_status;
wire soc_reader_ready_we;
wire [1:0] soc_reader_level_status;
wire soc_reader_level_we;
reg soc_reader_slot_storage = 1'd0;
reg soc_reader_slot_re = 1'd0;
reg [10:0] soc_reader_length_storage = 11'd0;
reg soc_reader_length_re = 1'd0;
wire soc_reader_irq;
wire soc_reader_done_status;
reg soc_reader_done_pending = 1'd0;
reg soc_reader_done_trigger = 1'd0;
reg soc_reader_done_clear = 1'd0;
wire soc_reader_eventmanager_status_re;
wire soc_reader_eventmanager_status_r;
wire soc_reader_eventmanager_status_we;
wire soc_reader_eventmanager_status_w;
wire soc_reader_eventmanager_pending_re;
wire soc_reader_eventmanager_pending_r;
wire soc_reader_eventmanager_pending_we;
wire soc_reader_eventmanager_pending_w;
reg soc_reader_eventmanager_storage = 1'd0;
reg soc_reader_eventmanager_re = 1'd0;
wire soc_reader_fifo_sink_valid;
wire soc_reader_fifo_sink_ready;
reg soc_reader_fifo_sink_first = 1'd0;
reg soc_reader_fifo_sink_last = 1'd0;
wire soc_reader_fifo_sink_payload_slot;
wire [10:0] soc_reader_fifo_sink_payload_length;
wire soc_reader_fifo_source_valid;
reg soc_reader_fifo_source_ready = 1'd0;
wire soc_reader_fifo_source_first;
wire soc_reader_fifo_source_last;
wire soc_reader_fifo_source_payload_slot;
wire [10:0] soc_reader_fifo_source_payload_length;
wire soc_reader_fifo_syncfifo_we;
wire soc_reader_fifo_syncfifo_writable;
wire soc_reader_fifo_syncfifo_re;
wire soc_reader_fifo_syncfifo_readable;
wire [13:0] soc_reader_fifo_syncfifo_din;
wire [13:0] soc_reader_fifo_syncfifo_dout;
reg [1:0] soc_reader_fifo_level = 2'd0;
reg soc_reader_fifo_replace = 1'd0;
reg soc_reader_fifo_produce = 1'd0;
reg soc_reader_fifo_consume = 1'd0;
reg soc_reader_fifo_wrport_adr = 1'd0;
wire [13:0] soc_reader_fifo_wrport_dat_r;
wire soc_reader_fifo_wrport_we;
wire [13:0] soc_reader_fifo_wrport_dat_w;
wire soc_reader_fifo_do_read;
wire soc_reader_fifo_rdport_adr;
wire [13:0] soc_reader_fifo_rdport_dat_r;
wire soc_reader_fifo_fifo_in_payload_slot;
wire [10:0] soc_reader_fifo_fifo_in_payload_length;
wire soc_reader_fifo_fifo_in_first;
wire soc_reader_fifo_fifo_in_last;
wire soc_reader_fifo_fifo_out_payload_slot;
wire [10:0] soc_reader_fifo_fifo_out_payload_length;
wire soc_reader_fifo_fifo_out_first;
wire soc_reader_fifo_fifo_out_last;
reg [10:0] soc_reader_counter = 11'd0;
reg soc_reader_counter_reset = 1'd0;
reg soc_reader_counter_ce = 1'd0;
wire soc_reader_last;
reg soc_reader_last_d = 1'd0;
wire [8:0] soc_reader_memory0_adr;
wire [31:0] soc_reader_memory0_dat_r;
wire [8:0] soc_reader_memory1_adr;
wire [31:0] soc_reader_memory1_dat_r;
wire soc_ev_irq;
wire [29:0] soc_sram0_bus_adr0;
wire [31:0] soc_sram0_bus_dat_w0;
wire [31:0] soc_sram0_bus_dat_r0;
wire [3:0] soc_sram0_bus_sel0;
wire soc_sram0_bus_cyc0;
wire soc_sram0_bus_stb0;
reg soc_sram0_bus_ack0 = 1'd0;
wire soc_sram0_bus_we0;
wire [2:0] soc_sram0_bus_cti0;
wire [1:0] soc_sram0_bus_bte0;
reg soc_sram0_bus_err0 = 1'd0;
wire [8:0] soc_sram0_adr0;
wire [31:0] soc_sram0_dat_r0;
wire [29:0] soc_sram1_bus_adr0;
wire [31:0] soc_sram1_bus_dat_w0;
wire [31:0] soc_sram1_bus_dat_r0;
wire [3:0] soc_sram1_bus_sel0;
wire soc_sram1_bus_cyc0;
wire soc_sram1_bus_stb0;
reg soc_sram1_bus_ack0 = 1'd0;
wire soc_sram1_bus_we0;
wire [2:0] soc_sram1_bus_cti0;
wire [1:0] soc_sram1_bus_bte0;
reg soc_sram1_bus_err0 = 1'd0;
wire [8:0] soc_sram1_adr0;
wire [31:0] soc_sram1_dat_r0;
wire [29:0] soc_sram0_bus_adr1;
wire [31:0] soc_sram0_bus_dat_w1;
wire [31:0] soc_sram0_bus_dat_r1;
wire [3:0] soc_sram0_bus_sel1;
wire soc_sram0_bus_cyc1;
wire soc_sram0_bus_stb1;
reg soc_sram0_bus_ack1 = 1'd0;
wire soc_sram0_bus_we1;
wire [2:0] soc_sram0_bus_cti1;
wire [1:0] soc_sram0_bus_bte1;
reg soc_sram0_bus_err1 = 1'd0;
wire [8:0] soc_sram0_adr1;
wire [31:0] soc_sram0_dat_r1;
reg [3:0] soc_sram0_we = 4'd0;
wire [31:0] soc_sram0_dat_w;
wire [29:0] soc_sram1_bus_adr1;
wire [31:0] soc_sram1_bus_dat_w1;
wire [31:0] soc_sram1_bus_dat_r1;
wire [3:0] soc_sram1_bus_sel1;
wire soc_sram1_bus_cyc1;
wire soc_sram1_bus_stb1;
reg soc_sram1_bus_ack1 = 1'd0;
wire soc_sram1_bus_we1;
wire [2:0] soc_sram1_bus_cti1;
wire [1:0] soc_sram1_bus_bte1;
reg soc_sram1_bus_err1 = 1'd0;
wire [8:0] soc_sram1_adr1;
wire [31:0] soc_sram1_dat_r1;
reg [3:0] soc_sram1_we = 4'd0;
wire [31:0] soc_sram1_dat_w;
reg [3:0] soc_slave_sel = 4'd0;
reg [3:0] soc_slave_sel_r = 4'd0;
reg vns_wb2csr_state = 1'd0;
reg vns_wb2csr_next_state = 1'd0;
reg [1:0] vns_refresher_state = 2'd0;
reg [1:0] vns_refresher_next_state = 2'd0;
reg [2:0] vns_bankmachine0_state = 3'd0;
reg [2:0] vns_bankmachine0_next_state = 3'd0;
reg [2:0] vns_bankmachine1_state = 3'd0;
reg [2:0] vns_bankmachine1_next_state = 3'd0;
reg [2:0] vns_bankmachine2_state = 3'd0;
reg [2:0] vns_bankmachine2_next_state = 3'd0;
reg [2:0] vns_bankmachine3_state = 3'd0;
reg [2:0] vns_bankmachine3_next_state = 3'd0;
reg [2:0] vns_bankmachine4_state = 3'd0;
reg [2:0] vns_bankmachine4_next_state = 3'd0;
reg [2:0] vns_bankmachine5_state = 3'd0;
reg [2:0] vns_bankmachine5_next_state = 3'd0;
reg [2:0] vns_bankmachine6_state = 3'd0;
reg [2:0] vns_bankmachine6_next_state = 3'd0;
reg [2:0] vns_bankmachine7_state = 3'd0;
reg [2:0] vns_bankmachine7_next_state = 3'd0;
reg [3:0] vns_multiplexer_state = 4'd0;
reg [3:0] vns_multiplexer_next_state = 4'd0;
wire vns_roundrobin0_request;
wire vns_roundrobin0_grant;
wire vns_roundrobin0_ce;
wire vns_roundrobin1_request;
wire vns_roundrobin1_grant;
wire vns_roundrobin1_ce;
wire vns_roundrobin2_request;
wire vns_roundrobin2_grant;
wire vns_roundrobin2_ce;
wire vns_roundrobin3_request;
wire vns_roundrobin3_grant;
wire vns_roundrobin3_ce;
wire vns_roundrobin4_request;
wire vns_roundrobin4_grant;
wire vns_roundrobin4_ce;
wire vns_roundrobin5_request;
wire vns_roundrobin5_grant;
wire vns_roundrobin5_ce;
wire vns_roundrobin6_request;
wire vns_roundrobin6_grant;
wire vns_roundrobin6_ce;
wire vns_roundrobin7_request;
wire vns_roundrobin7_grant;
wire vns_roundrobin7_ce;
reg [2:0] vns_rbank = 3'd0;
reg [2:0] vns_wbank = 3'd0;
reg vns_locked0 = 1'd0;
reg vns_locked1 = 1'd0;
reg vns_locked2 = 1'd0;
reg vns_locked3 = 1'd0;
reg vns_locked4 = 1'd0;
reg vns_locked5 = 1'd0;
reg vns_locked6 = 1'd0;
reg vns_locked7 = 1'd0;
reg vns_new_master_wdata_ready0 = 1'd0;
reg vns_new_master_wdata_ready1 = 1'd0;
reg vns_new_master_wdata_ready2 = 1'd0;
reg vns_new_master_rdata_valid0 = 1'd0;
reg vns_new_master_rdata_valid1 = 1'd0;
reg vns_new_master_rdata_valid2 = 1'd0;
reg vns_new_master_rdata_valid3 = 1'd0;
reg vns_new_master_rdata_valid4 = 1'd0;
reg vns_new_master_rdata_valid5 = 1'd0;
reg vns_new_master_rdata_valid6 = 1'd0;
reg vns_new_master_rdata_valid7 = 1'd0;
reg vns_new_master_rdata_valid8 = 1'd0;
reg vns_new_master_rdata_valid9 = 1'd0;
reg [2:0] vns_fullmemorywe_state = 3'd0;
reg [2:0] vns_fullmemorywe_next_state = 3'd0;
reg [1:0] vns_litedramwishbone2native_state = 2'd0;
reg [1:0] vns_litedramwishbone2native_next_state = 2'd0;
reg soc_netsoc_count_litedramwishbone2native_next_value = 1'd0;
reg soc_netsoc_count_litedramwishbone2native_next_value_ce = 1'd0;
reg vns_liteethmacgap_state = 1'd0;
reg vns_liteethmacgap_next_state = 1'd0;
reg [1:0] vns_liteethmacpreambleinserter_state = 2'd0;
reg [1:0] vns_liteethmacpreambleinserter_next_state = 2'd0;
reg vns_liteethmacpreamblechecker_state = 1'd0;
reg vns_liteethmacpreamblechecker_next_state = 1'd0;
reg [1:0] vns_liteethmaccrc32inserter_state = 2'd0;
reg [1:0] vns_liteethmaccrc32inserter_next_state = 2'd0;
reg [1:0] vns_liteethmaccrc32checker_state = 2'd0;
reg [1:0] vns_liteethmaccrc32checker_next_state = 2'd0;
reg vns_liteethmacpaddinginserter_state = 1'd0;
reg vns_liteethmacpaddinginserter_next_state = 1'd0;
reg [2:0] vns_liteethmacsramwriter_state = 3'd0;
reg [2:0] vns_liteethmacsramwriter_next_state = 3'd0;
reg [31:0] soc_writer_errors_status_liteethmac_next_value = 32'd0;
reg soc_writer_errors_status_liteethmac_next_value_ce = 1'd0;
reg [1:0] vns_liteethmacsramreader_state = 2'd0;
reg [1:0] vns_liteethmacsramreader_next_state = 2'd0;
wire vns_wb_sdram_con_request;
wire vns_wb_sdram_con_grant;
wire [29:0] vns_netsoc_shared_adr;
wire [31:0] vns_netsoc_shared_dat_w;
reg [31:0] vns_netsoc_shared_dat_r = 32'd0;
wire [3:0] vns_netsoc_shared_sel;
wire vns_netsoc_shared_cyc;
wire vns_netsoc_shared_stb;
reg vns_netsoc_shared_ack = 1'd0;
wire vns_netsoc_shared_we;
wire [2:0] vns_netsoc_shared_cti;
wire [1:0] vns_netsoc_shared_bte;
wire vns_netsoc_shared_err;
wire [1:0] vns_netsoc_request;
reg vns_netsoc_grant = 1'd0;
reg [5:0] vns_netsoc_slave_sel = 6'd0;
reg [5:0] vns_netsoc_slave_sel_r = 6'd0;
reg vns_netsoc_error = 1'd0;
wire vns_netsoc_wait;
wire vns_netsoc_done;
reg [19:0] vns_netsoc_count = 20'd1000000;
wire [13:0] vns_netsoc_csrbankarray_interface0_bank_bus_adr;
wire vns_netsoc_csrbankarray_interface0_bank_bus_we;
wire [7:0] vns_netsoc_csrbankarray_interface0_bank_bus_dat_w;
reg [7:0] vns_netsoc_csrbankarray_interface0_bank_bus_dat_r = 8'd0;
wire vns_netsoc_csrbankarray_csrbank0_timer_time7_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time7_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time7_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time7_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time6_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time6_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time6_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time6_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time5_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time5_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time5_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time5_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time4_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time4_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time4_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time4_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time3_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time3_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time2_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time2_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time1_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time1_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time0_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time0_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_w;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_r;
wire vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_w;
wire vns_netsoc_csrbankarray_csrbank0_sel;
wire [13:0] vns_netsoc_csrbankarray_interface1_bank_bus_adr;
wire vns_netsoc_csrbankarray_interface1_bank_bus_we;
wire [7:0] vns_netsoc_csrbankarray_interface1_bank_bus_dat_w;
reg [7:0] vns_netsoc_csrbankarray_interface1_bank_bus_dat_r = 8'd0;
wire vns_netsoc_csrbankarray_csrbank1_scratch3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch3_r;
wire vns_netsoc_csrbankarray_csrbank1_scratch3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch3_w;
wire vns_netsoc_csrbankarray_csrbank1_scratch2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch2_r;
wire vns_netsoc_csrbankarray_csrbank1_scratch2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch2_w;
wire vns_netsoc_csrbankarray_csrbank1_scratch1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch1_r;
wire vns_netsoc_csrbankarray_csrbank1_scratch1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch1_w;
wire vns_netsoc_csrbankarray_csrbank1_scratch0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch0_r;
wire vns_netsoc_csrbankarray_csrbank1_scratch0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_scratch0_w;
wire vns_netsoc_csrbankarray_csrbank1_bus_errors3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors3_r;
wire vns_netsoc_csrbankarray_csrbank1_bus_errors3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors3_w;
wire vns_netsoc_csrbankarray_csrbank1_bus_errors2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors2_r;
wire vns_netsoc_csrbankarray_csrbank1_bus_errors2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors2_w;
wire vns_netsoc_csrbankarray_csrbank1_bus_errors1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors1_r;
wire vns_netsoc_csrbankarray_csrbank1_bus_errors1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors1_w;
wire vns_netsoc_csrbankarray_csrbank1_bus_errors0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors0_r;
wire vns_netsoc_csrbankarray_csrbank1_bus_errors0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank1_bus_errors0_w;
wire vns_netsoc_csrbankarray_csrbank1_sel;
wire [13:0] vns_netsoc_csrbankarray_interface2_bank_bus_adr;
wire vns_netsoc_csrbankarray_interface2_bank_bus_we;
wire [7:0] vns_netsoc_csrbankarray_interface2_bank_bus_dat_w;
reg [7:0] vns_netsoc_csrbankarray_interface2_bank_bus_dat_r = 8'd0;
wire vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_re;
wire [4:0] vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_r;
wire vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_we;
wire [4:0] vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_w;
wire vns_netsoc_csrbankarray_csrbank2_dly_sel0_re;
wire [1:0] vns_netsoc_csrbankarray_csrbank2_dly_sel0_r;
wire vns_netsoc_csrbankarray_csrbank2_dly_sel0_we;
wire [1:0] vns_netsoc_csrbankarray_csrbank2_dly_sel0_w;
wire vns_netsoc_csrbankarray_csrbank2_sel;
wire [13:0] vns_netsoc_csrbankarray_interface3_bank_bus_adr;
wire vns_netsoc_csrbankarray_interface3_bank_bus_we;
wire [7:0] vns_netsoc_csrbankarray_interface3_bank_bus_dat_w;
reg [7:0] vns_netsoc_csrbankarray_interface3_bank_bus_dat_r = 8'd0;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_re;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_we;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_re;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_we;
wire vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_re;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_we;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_level_re;
wire [1:0] vns_netsoc_csrbankarray_csrbank3_sram_reader_level_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_level_we;
wire [1:0] vns_netsoc_csrbankarray_csrbank3_sram_reader_level_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_re;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_we;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_re;
wire [2:0] vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_we;
wire [2:0] vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_w;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_re;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_r;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_we;
wire vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_w;
wire vns_netsoc_csrbankarray_csrbank3_preamble_crc_re;
wire vns_netsoc_csrbankarray_csrbank3_preamble_crc_r;
wire vns_netsoc_csrbankarray_csrbank3_preamble_crc_we;
wire vns_netsoc_csrbankarray_csrbank3_preamble_crc_w;
wire vns_netsoc_csrbankarray_csrbank3_preamble_errors3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors3_r;
wire vns_netsoc_csrbankarray_csrbank3_preamble_errors3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors3_w;
wire vns_netsoc_csrbankarray_csrbank3_preamble_errors2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors2_r;
wire vns_netsoc_csrbankarray_csrbank3_preamble_errors2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors2_w;
wire vns_netsoc_csrbankarray_csrbank3_preamble_errors1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors1_r;
wire vns_netsoc_csrbankarray_csrbank3_preamble_errors1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors1_w;
wire vns_netsoc_csrbankarray_csrbank3_preamble_errors0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors0_r;
wire vns_netsoc_csrbankarray_csrbank3_preamble_errors0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_preamble_errors0_w;
wire vns_netsoc_csrbankarray_csrbank3_crc_errors3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors3_r;
wire vns_netsoc_csrbankarray_csrbank3_crc_errors3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors3_w;
wire vns_netsoc_csrbankarray_csrbank3_crc_errors2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors2_r;
wire vns_netsoc_csrbankarray_csrbank3_crc_errors2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors2_w;
wire vns_netsoc_csrbankarray_csrbank3_crc_errors1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors1_r;
wire vns_netsoc_csrbankarray_csrbank3_crc_errors1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors1_w;
wire vns_netsoc_csrbankarray_csrbank3_crc_errors0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors0_r;
wire vns_netsoc_csrbankarray_csrbank3_crc_errors0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank3_crc_errors0_w;
wire vns_netsoc_csrbankarray_csrbank3_sel;
wire [13:0] vns_netsoc_csrbankarray_interface4_bank_bus_adr;
wire vns_netsoc_csrbankarray_interface4_bank_bus_we;
wire [7:0] vns_netsoc_csrbankarray_interface4_bank_bus_dat_w;
reg [7:0] vns_netsoc_csrbankarray_interface4_bank_bus_dat_r = 8'd0;
wire vns_netsoc_csrbankarray_csrbank4_crg_reset0_re;
wire vns_netsoc_csrbankarray_csrbank4_crg_reset0_r;
wire vns_netsoc_csrbankarray_csrbank4_crg_reset0_we;
wire vns_netsoc_csrbankarray_csrbank4_crg_reset0_w;
wire vns_netsoc_csrbankarray_csrbank4_mdio_w0_re;
wire [2:0] vns_netsoc_csrbankarray_csrbank4_mdio_w0_r;
wire vns_netsoc_csrbankarray_csrbank4_mdio_w0_we;
wire [2:0] vns_netsoc_csrbankarray_csrbank4_mdio_w0_w;
wire vns_netsoc_csrbankarray_csrbank4_mdio_r_re;
wire vns_netsoc_csrbankarray_csrbank4_mdio_r_r;
wire vns_netsoc_csrbankarray_csrbank4_mdio_r_we;
wire vns_netsoc_csrbankarray_csrbank4_mdio_r_w;
wire vns_netsoc_csrbankarray_csrbank4_sel;
wire [13:0] vns_netsoc_csrbankarray_sram_bus_adr;
wire vns_netsoc_csrbankarray_sram_bus_we;
wire [7:0] vns_netsoc_csrbankarray_sram_bus_dat_w;
reg [7:0] vns_netsoc_csrbankarray_sram_bus_dat_r = 8'd0;
wire [2:0] vns_netsoc_csrbankarray_adr;
wire [7:0] vns_netsoc_csrbankarray_dat_r;
wire vns_netsoc_csrbankarray_sel;
reg vns_netsoc_csrbankarray_sel_r = 1'd0;
wire [13:0] vns_netsoc_csrbankarray_interface5_bank_bus_adr;
wire vns_netsoc_csrbankarray_interface5_bank_bus_we;
wire [7:0] vns_netsoc_csrbankarray_interface5_bank_bus_dat_w;
reg [7:0] vns_netsoc_csrbankarray_interface5_bank_bus_dat_r = 8'd0;
wire vns_netsoc_csrbankarray_csrbank5_dfii_control0_re;
wire [3:0] vns_netsoc_csrbankarray_csrbank5_dfii_control0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_control0_we;
wire [3:0] vns_netsoc_csrbankarray_csrbank5_dfii_control0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_re;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_we;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_re;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_we;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_re;
wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_we;
wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_re;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_we;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_re;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_we;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_re;
wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_we;
wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_re;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_we;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_re;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_we;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_re;
wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_we;
wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_re;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_we;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_re;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_we;
wire [5:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_re;
wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_we;
wire [2:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_w;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_r;
wire vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_w;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_r;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_w;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_r;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_w;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_r;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_w;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_r;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_w;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_r;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_w;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_r;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_w;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_r;
wire vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_w;
wire vns_netsoc_csrbankarray_csrbank5_sel;
wire [13:0] vns_netsoc_csrbankarray_interface6_bank_bus_adr;
wire vns_netsoc_csrbankarray_interface6_bank_bus_we;
wire [7:0] vns_netsoc_csrbankarray_interface6_bank_bus_dat_w;
reg [7:0] vns_netsoc_csrbankarray_interface6_bank_bus_dat_r = 8'd0;
wire vns_netsoc_csrbankarray_csrbank6_load3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_load3_r;
wire vns_netsoc_csrbankarray_csrbank6_load3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_load3_w;
wire vns_netsoc_csrbankarray_csrbank6_load2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_load2_r;
wire vns_netsoc_csrbankarray_csrbank6_load2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_load2_w;
wire vns_netsoc_csrbankarray_csrbank6_load1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_load1_r;
wire vns_netsoc_csrbankarray_csrbank6_load1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_load1_w;
wire vns_netsoc_csrbankarray_csrbank6_load0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_load0_r;
wire vns_netsoc_csrbankarray_csrbank6_load0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_load0_w;
wire vns_netsoc_csrbankarray_csrbank6_reload3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload3_r;
wire vns_netsoc_csrbankarray_csrbank6_reload3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload3_w;
wire vns_netsoc_csrbankarray_csrbank6_reload2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload2_r;
wire vns_netsoc_csrbankarray_csrbank6_reload2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload2_w;
wire vns_netsoc_csrbankarray_csrbank6_reload1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload1_r;
wire vns_netsoc_csrbankarray_csrbank6_reload1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload1_w;
wire vns_netsoc_csrbankarray_csrbank6_reload0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload0_r;
wire vns_netsoc_csrbankarray_csrbank6_reload0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_reload0_w;
wire vns_netsoc_csrbankarray_csrbank6_en0_re;
wire vns_netsoc_csrbankarray_csrbank6_en0_r;
wire vns_netsoc_csrbankarray_csrbank6_en0_we;
wire vns_netsoc_csrbankarray_csrbank6_en0_w;
wire vns_netsoc_csrbankarray_csrbank6_update_value0_re;
wire vns_netsoc_csrbankarray_csrbank6_update_value0_r;
wire vns_netsoc_csrbankarray_csrbank6_update_value0_we;
wire vns_netsoc_csrbankarray_csrbank6_update_value0_w;
wire vns_netsoc_csrbankarray_csrbank6_value3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_value3_r;
wire vns_netsoc_csrbankarray_csrbank6_value3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_value3_w;
wire vns_netsoc_csrbankarray_csrbank6_value2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_value2_r;
wire vns_netsoc_csrbankarray_csrbank6_value2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_value2_w;
wire vns_netsoc_csrbankarray_csrbank6_value1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_value1_r;
wire vns_netsoc_csrbankarray_csrbank6_value1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_value1_w;
wire vns_netsoc_csrbankarray_csrbank6_value0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_value0_r;
wire vns_netsoc_csrbankarray_csrbank6_value0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank6_value0_w;
wire vns_netsoc_csrbankarray_csrbank6_ev_enable0_re;
wire vns_netsoc_csrbankarray_csrbank6_ev_enable0_r;
wire vns_netsoc_csrbankarray_csrbank6_ev_enable0_we;
wire vns_netsoc_csrbankarray_csrbank6_ev_enable0_w;
wire vns_netsoc_csrbankarray_csrbank6_sel;
wire [13:0] vns_netsoc_csrbankarray_interface7_bank_bus_adr;
wire vns_netsoc_csrbankarray_interface7_bank_bus_we;
wire [7:0] vns_netsoc_csrbankarray_interface7_bank_bus_dat_w;
reg [7:0] vns_netsoc_csrbankarray_interface7_bank_bus_dat_r = 8'd0;
wire vns_netsoc_csrbankarray_csrbank7_txfull_re;
wire vns_netsoc_csrbankarray_csrbank7_txfull_r;
wire vns_netsoc_csrbankarray_csrbank7_txfull_we;
wire vns_netsoc_csrbankarray_csrbank7_txfull_w;
wire vns_netsoc_csrbankarray_csrbank7_rxempty_re;
wire vns_netsoc_csrbankarray_csrbank7_rxempty_r;
wire vns_netsoc_csrbankarray_csrbank7_rxempty_we;
wire vns_netsoc_csrbankarray_csrbank7_rxempty_w;
wire vns_netsoc_csrbankarray_csrbank7_ev_enable0_re;
wire [1:0] vns_netsoc_csrbankarray_csrbank7_ev_enable0_r;
wire vns_netsoc_csrbankarray_csrbank7_ev_enable0_we;
wire [1:0] vns_netsoc_csrbankarray_csrbank7_ev_enable0_w;
wire vns_netsoc_csrbankarray_csrbank7_sel;
wire [13:0] vns_netsoc_csrbankarray_interface8_bank_bus_adr;
wire vns_netsoc_csrbankarray_interface8_bank_bus_we;
wire [7:0] vns_netsoc_csrbankarray_interface8_bank_bus_dat_w;
reg [7:0] vns_netsoc_csrbankarray_interface8_bank_bus_dat_r = 8'd0;
wire vns_netsoc_csrbankarray_csrbank8_tuning_word3_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word3_r;
wire vns_netsoc_csrbankarray_csrbank8_tuning_word3_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word3_w;
wire vns_netsoc_csrbankarray_csrbank8_tuning_word2_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word2_r;
wire vns_netsoc_csrbankarray_csrbank8_tuning_word2_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word2_w;
wire vns_netsoc_csrbankarray_csrbank8_tuning_word1_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word1_r;
wire vns_netsoc_csrbankarray_csrbank8_tuning_word1_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word1_w;
wire vns_netsoc_csrbankarray_csrbank8_tuning_word0_re;
wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word0_r;
wire vns_netsoc_csrbankarray_csrbank8_tuning_word0_we;
wire [7:0] vns_netsoc_csrbankarray_csrbank8_tuning_word0_w;
wire vns_netsoc_csrbankarray_csrbank8_sel;
wire [13:0] vns_netsoc_csrcon_adr;
wire vns_netsoc_csrcon_we;
wire [7:0] vns_netsoc_csrcon_dat_w;
wire [7:0] vns_netsoc_csrcon_dat_r;
reg vns_rhs_array_muxed0 = 1'd0;
reg [13:0] vns_rhs_array_muxed1 = 14'd0;
reg [2:0] vns_rhs_array_muxed2 = 3'd0;
reg vns_rhs_array_muxed3 = 1'd0;
reg vns_rhs_array_muxed4 = 1'd0;
reg vns_rhs_array_muxed5 = 1'd0;
reg vns_t_array_muxed0 = 1'd0;
reg vns_t_array_muxed1 = 1'd0;
reg vns_t_array_muxed2 = 1'd0;
reg vns_rhs_array_muxed6 = 1'd0;
reg [13:0] vns_rhs_array_muxed7 = 14'd0;
reg [2:0] vns_rhs_array_muxed8 = 3'd0;
reg vns_rhs_array_muxed9 = 1'd0;
reg vns_rhs_array_muxed10 = 1'd0;
reg vns_rhs_array_muxed11 = 1'd0;
reg vns_t_array_muxed3 = 1'd0;
reg vns_t_array_muxed4 = 1'd0;
reg vns_t_array_muxed5 = 1'd0;
reg [20:0] vns_rhs_array_muxed12 = 21'd0;
reg vns_rhs_array_muxed13 = 1'd0;
reg vns_rhs_array_muxed14 = 1'd0;
reg [20:0] vns_rhs_array_muxed15 = 21'd0;
reg vns_rhs_array_muxed16 = 1'd0;
reg vns_rhs_array_muxed17 = 1'd0;
reg [20:0] vns_rhs_array_muxed18 = 21'd0;
reg vns_rhs_array_muxed19 = 1'd0;
reg vns_rhs_array_muxed20 = 1'd0;
reg [20:0] vns_rhs_array_muxed21 = 21'd0;
reg vns_rhs_array_muxed22 = 1'd0;
reg vns_rhs_array_muxed23 = 1'd0;
reg [20:0] vns_rhs_array_muxed24 = 21'd0;
reg vns_rhs_array_muxed25 = 1'd0;
reg vns_rhs_array_muxed26 = 1'd0;
reg [20:0] vns_rhs_array_muxed27 = 21'd0;
reg vns_rhs_array_muxed28 = 1'd0;
reg vns_rhs_array_muxed29 = 1'd0;
reg [20:0] vns_rhs_array_muxed30 = 21'd0;
reg vns_rhs_array_muxed31 = 1'd0;
reg vns_rhs_array_muxed32 = 1'd0;
reg [20:0] vns_rhs_array_muxed33 = 21'd0;
reg vns_rhs_array_muxed34 = 1'd0;
reg vns_rhs_array_muxed35 = 1'd0;
reg [29:0] vns_rhs_array_muxed36 = 30'd0;
reg [31:0] vns_rhs_array_muxed37 = 32'd0;
reg [3:0] vns_rhs_array_muxed38 = 4'd0;
reg vns_rhs_array_muxed39 = 1'd0;
reg vns_rhs_array_muxed40 = 1'd0;
reg vns_rhs_array_muxed41 = 1'd0;
reg [2:0] vns_rhs_array_muxed42 = 3'd0;
reg [1:0] vns_rhs_array_muxed43 = 2'd0;
reg [29:0] vns_rhs_array_muxed44 = 30'd0;
reg [31:0] vns_rhs_array_muxed45 = 32'd0;
reg [3:0] vns_rhs_array_muxed46 = 4'd0;
reg vns_rhs_array_muxed47 = 1'd0;
reg vns_rhs_array_muxed48 = 1'd0;
reg vns_rhs_array_muxed49 = 1'd0;
reg [2:0] vns_rhs_array_muxed50 = 3'd0;
reg [1:0] vns_rhs_array_muxed51 = 2'd0;
reg [2:0] vns_array_muxed0 = 3'd0;
reg [13:0] vns_array_muxed1 = 14'd0;
reg vns_array_muxed2 = 1'd0;
reg vns_array_muxed3 = 1'd0;
reg vns_array_muxed4 = 1'd0;
reg vns_array_muxed5 = 1'd0;
reg vns_array_muxed6 = 1'd0;
reg [2:0] vns_array_muxed7 = 3'd0;
reg [13:0] vns_array_muxed8 = 14'd0;
reg vns_array_muxed9 = 1'd0;
reg vns_array_muxed10 = 1'd0;
reg vns_array_muxed11 = 1'd0;
reg vns_array_muxed12 = 1'd0;
reg vns_array_muxed13 = 1'd0;
reg [2:0] vns_array_muxed14 = 3'd0;
reg [13:0] vns_array_muxed15 = 14'd0;
reg vns_array_muxed16 = 1'd0;
reg vns_array_muxed17 = 1'd0;
reg vns_array_muxed18 = 1'd0;
reg vns_array_muxed19 = 1'd0;
reg vns_array_muxed20 = 1'd0;
reg [2:0] vns_array_muxed21 = 3'd0;
reg [13:0] vns_array_muxed22 = 14'd0;
reg vns_array_muxed23 = 1'd0;
reg vns_array_muxed24 = 1'd0;
reg vns_array_muxed25 = 1'd0;
reg vns_array_muxed26 = 1'd0;
reg vns_array_muxed27 = 1'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl0_regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl0_regs1 = 1'd0;
wire vns_xilinxasyncresetsynchronizerimpl0;
wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta;
wire vns_xilinxasyncresetsynchronizerimpl1;
wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta;
wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta;
wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl1_regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl1_regs1 = 1'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl2_regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl2_regs1 = 1'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl3_regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg vns_xilinxmultiregimpl3_regs1 = 1'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl4_regs0 = 7'd0;
(* async_reg = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl4_regs1 = 7'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl5_regs0 = 7'd0;
(* async_reg = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl5_regs1 = 7'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl6_regs0 = 7'd0;
(* async_reg = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl6_regs1 = 7'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl7_regs0 = 7'd0;
(* async_reg = "true", dont_touch = "true" *) reg [6:0] vns_xilinxmultiregimpl7_regs1 = 7'd0;
assign soc_netsoc_cpu_reset = soc_netsoc_ctrl_reset;
assign soc_netsoc_ctrl_bus_error = vns_netsoc_error;
always @(*) begin
soc_netsoc_cpu_interrupt0 <= 32'd0;
soc_netsoc_cpu_interrupt0[2] <= soc_ev_irq;
soc_netsoc_cpu_interrupt0[1] <= soc_netsoc_timer0_irq;
soc_netsoc_cpu_interrupt0[0] <= soc_netsoc_uart_irq;
end
assign soc_netsoc_ctrl_reset = soc_netsoc_ctrl_reset_reset_re;
assign soc_netsoc_ctrl_bus_errors_status = soc_netsoc_ctrl_bus_errors;
assign soc_netsoc_cpu_interrupt1 = (soc_netsoc_cpu_time >= soc_netsoc_cpu_time_cmp);
assign soc_netsoc_interface0_soc_bus_adr = soc_netsoc_cpu_ibus_adr;
assign soc_netsoc_interface0_soc_bus_dat_w = soc_netsoc_cpu_ibus_dat_w;
assign soc_netsoc_cpu_ibus_dat_r = soc_netsoc_interface0_soc_bus_dat_r;
assign soc_netsoc_interface0_soc_bus_sel = soc_netsoc_cpu_ibus_sel;
assign soc_netsoc_interface0_soc_bus_cyc = soc_netsoc_cpu_ibus_cyc;
assign soc_netsoc_interface0_soc_bus_stb = soc_netsoc_cpu_ibus_stb;
assign soc_netsoc_cpu_ibus_ack = soc_netsoc_interface0_soc_bus_ack;
assign soc_netsoc_interface0_soc_bus_we = soc_netsoc_cpu_ibus_we;
assign soc_netsoc_interface0_soc_bus_cti = soc_netsoc_cpu_ibus_cti;
assign soc_netsoc_interface0_soc_bus_bte = soc_netsoc_cpu_ibus_bte;
assign soc_netsoc_cpu_ibus_err = soc_netsoc_interface0_soc_bus_err;
assign soc_netsoc_interface1_soc_bus_adr = soc_netsoc_cpu_dbus_adr;
assign soc_netsoc_interface1_soc_bus_dat_w = soc_netsoc_cpu_dbus_dat_w;
assign soc_netsoc_cpu_dbus_dat_r = soc_netsoc_interface1_soc_bus_dat_r;
assign soc_netsoc_interface1_soc_bus_sel = soc_netsoc_cpu_dbus_sel;
assign soc_netsoc_interface1_soc_bus_cyc = soc_netsoc_cpu_dbus_cyc;
assign soc_netsoc_interface1_soc_bus_stb = soc_netsoc_cpu_dbus_stb;
assign soc_netsoc_cpu_dbus_ack = soc_netsoc_interface1_soc_bus_ack;
assign soc_netsoc_interface1_soc_bus_we = soc_netsoc_cpu_dbus_we;
assign soc_netsoc_interface1_soc_bus_cti = soc_netsoc_cpu_dbus_cti;
assign soc_netsoc_interface1_soc_bus_bte = soc_netsoc_cpu_dbus_bte;
assign soc_netsoc_cpu_dbus_err = soc_netsoc_interface1_soc_bus_err;
assign soc_netsoc_rom_adr = soc_netsoc_rom_bus_adr[13:0];
assign soc_netsoc_rom_bus_dat_r = soc_netsoc_rom_dat_r;
always @(*) begin
soc_netsoc_sram_we <= 4'd0;
soc_netsoc_sram_we[0] <= (((soc_netsoc_sram_bus_cyc & soc_netsoc_sram_bus_stb) & soc_netsoc_sram_bus_we) & soc_netsoc_sram_bus_sel[0]);
soc_netsoc_sram_we[1] <= (((soc_netsoc_sram_bus_cyc & soc_netsoc_sram_bus_stb) & soc_netsoc_sram_bus_we) & soc_netsoc_sram_bus_sel[1]);
soc_netsoc_sram_we[2] <= (((soc_netsoc_sram_bus_cyc & soc_netsoc_sram_bus_stb) & soc_netsoc_sram_bus_we) & soc_netsoc_sram_bus_sel[2]);
soc_netsoc_sram_we[3] <= (((soc_netsoc_sram_bus_cyc & soc_netsoc_sram_bus_stb) & soc_netsoc_sram_bus_we) & soc_netsoc_sram_bus_sel[3]);
end
assign soc_netsoc_sram_adr = soc_netsoc_sram_bus_adr[12:0];
assign soc_netsoc_sram_bus_dat_r = soc_netsoc_sram_dat_r;
assign soc_netsoc_sram_dat_w = soc_netsoc_sram_bus_dat_w;
assign soc_netsoc_uart_tx_fifo_sink_valid = soc_netsoc_uart_rxtx_re;
assign soc_netsoc_uart_tx_fifo_sink_payload_data = soc_netsoc_uart_rxtx_r;
assign soc_netsoc_uart_txfull_status = (~soc_netsoc_uart_tx_fifo_sink_ready);
assign soc_netsoc_uart_phy_sink_valid = soc_netsoc_uart_tx_fifo_source_valid;
assign soc_netsoc_uart_tx_fifo_source_ready = soc_netsoc_uart_phy_sink_ready;
assign soc_netsoc_uart_phy_sink_first = soc_netsoc_uart_tx_fifo_source_first;
assign soc_netsoc_uart_phy_sink_last = soc_netsoc_uart_tx_fifo_source_last;
assign soc_netsoc_uart_phy_sink_payload_data = soc_netsoc_uart_tx_fifo_source_payload_data;
assign soc_netsoc_uart_tx_trigger = (~soc_netsoc_uart_tx_fifo_sink_ready);
assign soc_netsoc_uart_rx_fifo_sink_valid = soc_netsoc_uart_phy_source_valid;
assign soc_netsoc_uart_phy_source_ready = soc_netsoc_uart_rx_fifo_sink_ready;
assign soc_netsoc_uart_rx_fifo_sink_first = soc_netsoc_uart_phy_source_first;
assign soc_netsoc_uart_rx_fifo_sink_last = soc_netsoc_uart_phy_source_last;
assign soc_netsoc_uart_rx_fifo_sink_payload_data = soc_netsoc_uart_phy_source_payload_data;
assign soc_netsoc_uart_rxempty_status = (~soc_netsoc_uart_rx_fifo_source_valid);
assign soc_netsoc_uart_rxtx_w = soc_netsoc_uart_rx_fifo_source_payload_data;
assign soc_netsoc_uart_rx_fifo_source_ready = soc_netsoc_uart_rx_clear;
assign soc_netsoc_uart_rx_trigger = (~soc_netsoc_uart_rx_fifo_source_valid);
always @(*) begin
soc_netsoc_uart_tx_clear <= 1'd0;
if ((soc_netsoc_uart_eventmanager_pending_re & soc_netsoc_uart_eventmanager_pending_r[0])) begin
soc_netsoc_uart_tx_clear <= 1'd1;
end
end
always @(*) begin
soc_netsoc_uart_eventmanager_status_w <= 2'd0;
soc_netsoc_uart_eventmanager_status_w[0] <= soc_netsoc_uart_tx_status;
soc_netsoc_uart_eventmanager_status_w[1] <= soc_netsoc_uart_rx_status;
end
always @(*) begin
soc_netsoc_uart_rx_clear <= 1'd0;
if ((soc_netsoc_uart_eventmanager_pending_re & soc_netsoc_uart_eventmanager_pending_r[1])) begin
soc_netsoc_uart_rx_clear <= 1'd1;
end
end
always @(*) begin
soc_netsoc_uart_eventmanager_pending_w <= 2'd0;
soc_netsoc_uart_eventmanager_pending_w[0] <= soc_netsoc_uart_tx_pending;
soc_netsoc_uart_eventmanager_pending_w[1] <= soc_netsoc_uart_rx_pending;
end
assign soc_netsoc_uart_irq = ((soc_netsoc_uart_eventmanager_pending_w[0] & soc_netsoc_uart_eventmanager_storage[0]) | (soc_netsoc_uart_eventmanager_pending_w[1] & soc_netsoc_uart_eventmanager_storage[1]));
assign soc_netsoc_uart_tx_status = soc_netsoc_uart_tx_trigger;
assign soc_netsoc_uart_rx_status = soc_netsoc_uart_rx_trigger;
assign soc_netsoc_uart_tx_fifo_syncfifo_din = {soc_netsoc_uart_tx_fifo_fifo_in_last, soc_netsoc_uart_tx_fifo_fifo_in_first, soc_netsoc_uart_tx_fifo_fifo_in_payload_data};
assign {soc_netsoc_uart_tx_fifo_fifo_out_last, soc_netsoc_uart_tx_fifo_fifo_out_first, soc_netsoc_uart_tx_fifo_fifo_out_payload_data} = soc_netsoc_uart_tx_fifo_syncfifo_dout;
assign soc_netsoc_uart_tx_fifo_sink_ready = soc_netsoc_uart_tx_fifo_syncfifo_writable;
assign soc_netsoc_uart_tx_fifo_syncfifo_we = soc_netsoc_uart_tx_fifo_sink_valid;
assign soc_netsoc_uart_tx_fifo_fifo_in_first = soc_netsoc_uart_tx_fifo_sink_first;
assign soc_netsoc_uart_tx_fifo_fifo_in_last = soc_netsoc_uart_tx_fifo_sink_last;
assign soc_netsoc_uart_tx_fifo_fifo_in_payload_data = soc_netsoc_uart_tx_fifo_sink_payload_data;
assign soc_netsoc_uart_tx_fifo_source_valid = soc_netsoc_uart_tx_fifo_readable;
assign soc_netsoc_uart_tx_fifo_source_first = soc_netsoc_uart_tx_fifo_fifo_out_first;
assign soc_netsoc_uart_tx_fifo_source_last = soc_netsoc_uart_tx_fifo_fifo_out_last;
assign soc_netsoc_uart_tx_fifo_source_payload_data = soc_netsoc_uart_tx_fifo_fifo_out_payload_data;
assign soc_netsoc_uart_tx_fifo_re = soc_netsoc_uart_tx_fifo_source_ready;
assign soc_netsoc_uart_tx_fifo_syncfifo_re = (soc_netsoc_uart_tx_fifo_syncfifo_readable & ((~soc_netsoc_uart_tx_fifo_readable) | soc_netsoc_uart_tx_fifo_re));
assign soc_netsoc_uart_tx_fifo_level1 = (soc_netsoc_uart_tx_fifo_level0 + soc_netsoc_uart_tx_fifo_readable);
always @(*) begin
soc_netsoc_uart_tx_fifo_wrport_adr <= 4'd0;
if (soc_netsoc_uart_tx_fifo_replace) begin
soc_netsoc_uart_tx_fifo_wrport_adr <= (soc_netsoc_uart_tx_fifo_produce - 1'd1);
end else begin
soc_netsoc_uart_tx_fifo_wrport_adr <= soc_netsoc_uart_tx_fifo_produce;
end
end
assign soc_netsoc_uart_tx_fifo_wrport_dat_w = soc_netsoc_uart_tx_fifo_syncfifo_din;
assign soc_netsoc_uart_tx_fifo_wrport_we = (soc_netsoc_uart_tx_fifo_syncfifo_we & (soc_netsoc_uart_tx_fifo_syncfifo_writable | soc_netsoc_uart_tx_fifo_replace));
assign soc_netsoc_uart_tx_fifo_do_read = (soc_netsoc_uart_tx_fifo_syncfifo_readable & soc_netsoc_uart_tx_fifo_syncfifo_re);
assign soc_netsoc_uart_tx_fifo_rdport_adr = soc_netsoc_uart_tx_fifo_consume;
assign soc_netsoc_uart_tx_fifo_syncfifo_dout = soc_netsoc_uart_tx_fifo_rdport_dat_r;
assign soc_netsoc_uart_tx_fifo_rdport_re = soc_netsoc_uart_tx_fifo_do_read;
assign soc_netsoc_uart_tx_fifo_syncfifo_writable = (soc_netsoc_uart_tx_fifo_level0 != 5'd16);
assign soc_netsoc_uart_tx_fifo_syncfifo_readable = (soc_netsoc_uart_tx_fifo_level0 != 1'd0);
assign soc_netsoc_uart_rx_fifo_syncfifo_din = {soc_netsoc_uart_rx_fifo_fifo_in_last, soc_netsoc_uart_rx_fifo_fifo_in_first, soc_netsoc_uart_rx_fifo_fifo_in_payload_data};
assign {soc_netsoc_uart_rx_fifo_fifo_out_last, soc_netsoc_uart_rx_fifo_fifo_out_first, soc_netsoc_uart_rx_fifo_fifo_out_payload_data} = soc_netsoc_uart_rx_fifo_syncfifo_dout;
assign soc_netsoc_uart_rx_fifo_sink_ready = soc_netsoc_uart_rx_fifo_syncfifo_writable;
assign soc_netsoc_uart_rx_fifo_syncfifo_we = soc_netsoc_uart_rx_fifo_sink_valid;
assign soc_netsoc_uart_rx_fifo_fifo_in_first = soc_netsoc_uart_rx_fifo_sink_first;
assign soc_netsoc_uart_rx_fifo_fifo_in_last = soc_netsoc_uart_rx_fifo_sink_last;
assign soc_netsoc_uart_rx_fifo_fifo_in_payload_data = soc_netsoc_uart_rx_fifo_sink_payload_data;
assign soc_netsoc_uart_rx_fifo_source_valid = soc_netsoc_uart_rx_fifo_readable;
assign soc_netsoc_uart_rx_fifo_source_first = soc_netsoc_uart_rx_fifo_fifo_out_first;
assign soc_netsoc_uart_rx_fifo_source_last = soc_netsoc_uart_rx_fifo_fifo_out_last;
assign soc_netsoc_uart_rx_fifo_source_payload_data = soc_netsoc_uart_rx_fifo_fifo_out_payload_data;
assign soc_netsoc_uart_rx_fifo_re = soc_netsoc_uart_rx_fifo_source_ready;
assign soc_netsoc_uart_rx_fifo_syncfifo_re = (soc_netsoc_uart_rx_fifo_syncfifo_readable & ((~soc_netsoc_uart_rx_fifo_readable) | soc_netsoc_uart_rx_fifo_re));
assign soc_netsoc_uart_rx_fifo_level1 = (soc_netsoc_uart_rx_fifo_level0 + soc_netsoc_uart_rx_fifo_readable);
always @(*) begin
soc_netsoc_uart_rx_fifo_wrport_adr <= 4'd0;
if (soc_netsoc_uart_rx_fifo_replace) begin
soc_netsoc_uart_rx_fifo_wrport_adr <= (soc_netsoc_uart_rx_fifo_produce - 1'd1);
end else begin
soc_netsoc_uart_rx_fifo_wrport_adr <= soc_netsoc_uart_rx_fifo_produce;
end
end
assign soc_netsoc_uart_rx_fifo_wrport_dat_w = soc_netsoc_uart_rx_fifo_syncfifo_din;
assign soc_netsoc_uart_rx_fifo_wrport_we = (soc_netsoc_uart_rx_fifo_syncfifo_we & (soc_netsoc_uart_rx_fifo_syncfifo_writable | soc_netsoc_uart_rx_fifo_replace));
assign soc_netsoc_uart_rx_fifo_do_read = (soc_netsoc_uart_rx_fifo_syncfifo_readable & soc_netsoc_uart_rx_fifo_syncfifo_re);
assign soc_netsoc_uart_rx_fifo_rdport_adr = soc_netsoc_uart_rx_fifo_consume;
assign soc_netsoc_uart_rx_fifo_syncfifo_dout = soc_netsoc_uart_rx_fifo_rdport_dat_r;
assign soc_netsoc_uart_rx_fifo_rdport_re = soc_netsoc_uart_rx_fifo_do_read;
assign soc_netsoc_uart_rx_fifo_syncfifo_writable = (soc_netsoc_uart_rx_fifo_level0 != 5'd16);
assign soc_netsoc_uart_rx_fifo_syncfifo_readable = (soc_netsoc_uart_rx_fifo_level0 != 1'd0);
assign soc_netsoc_timer0_zero_trigger = (soc_netsoc_timer0_value != 1'd0);
assign soc_netsoc_timer0_eventmanager_status_w = soc_netsoc_timer0_zero_status;
always @(*) begin
soc_netsoc_timer0_zero_clear <= 1'd0;
if ((soc_netsoc_timer0_eventmanager_pending_re & soc_netsoc_timer0_eventmanager_pending_r)) begin
soc_netsoc_timer0_zero_clear <= 1'd1;
end
end
assign soc_netsoc_timer0_eventmanager_pending_w = soc_netsoc_timer0_zero_pending;
assign soc_netsoc_timer0_irq = (soc_netsoc_timer0_eventmanager_pending_w & soc_netsoc_timer0_eventmanager_storage);
assign soc_netsoc_timer0_zero_status = soc_netsoc_timer0_zero_trigger;
assign soc_netsoc_interface_dat_w = soc_netsoc_bus_wishbone_dat_w;
assign soc_netsoc_bus_wishbone_dat_r = soc_netsoc_interface_dat_r;
always @(*) begin
soc_netsoc_interface_adr <= 14'd0;
vns_wb2csr_next_state <= 1'd0;
soc_netsoc_interface_we <= 1'd0;
soc_netsoc_bus_wishbone_ack <= 1'd0;
vns_wb2csr_next_state <= vns_wb2csr_state;
case (vns_wb2csr_state)
1'd1: begin
soc_netsoc_bus_wishbone_ack <= 1'd1;
vns_wb2csr_next_state <= 1'd0;
end
default: begin
if ((soc_netsoc_bus_wishbone_cyc & soc_netsoc_bus_wishbone_stb)) begin
soc_netsoc_interface_adr <= soc_netsoc_bus_wishbone_adr;
soc_netsoc_interface_we <= soc_netsoc_bus_wishbone_we;
vns_wb2csr_next_state <= 1'd1;
end
end
endcase
end
always @(*) begin
soc_emulator_ram_we <= 4'd0;
soc_emulator_ram_we[0] <= (((soc_emulator_ram_bus_cyc & soc_emulator_ram_bus_stb) & soc_emulator_ram_bus_we) & soc_emulator_ram_bus_sel[0]);
soc_emulator_ram_we[1] <= (((soc_emulator_ram_bus_cyc & soc_emulator_ram_bus_stb) & soc_emulator_ram_bus_we) & soc_emulator_ram_bus_sel[1]);
soc_emulator_ram_we[2] <= (((soc_emulator_ram_bus_cyc & soc_emulator_ram_bus_stb) & soc_emulator_ram_bus_we) & soc_emulator_ram_bus_sel[2]);
soc_emulator_ram_we[3] <= (((soc_emulator_ram_bus_cyc & soc_emulator_ram_bus_stb) & soc_emulator_ram_bus_we) & soc_emulator_ram_bus_sel[3]);
end
assign soc_emulator_ram_adr = soc_emulator_ram_bus_adr[11:0];
assign soc_emulator_ram_bus_dat_r = soc_emulator_ram_dat_r;
assign soc_emulator_ram_dat_w = soc_emulator_ram_bus_dat_w;
always @(*) begin
soc_a7ddrphy_dqs_serdes_pattern <= 8'd85;
soc_a7ddrphy_dqs_serdes_pattern <= 7'd85;
if ((soc_a7ddrphy_dqs_preamble | soc_a7ddrphy_dqs_postamble)) begin
soc_a7ddrphy_dqs_serdes_pattern <= 1'd0;
end
end
assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0;
assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1;
assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2;
assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3;
assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4;
assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5;
assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6;
assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7;
assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8;
assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9;
assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10;
assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11;
assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12;
assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13;
assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14;
assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15;
always @(*) begin
soc_a7ddrphy_dfi_p0_rddata <= 32'd0;
soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0];
soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1];
soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0];
soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1];
soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0];
soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1];
soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0];
soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1];
soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0];
soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1];
soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0];
soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1];
soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0];
soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1];
soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0];
soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1];
soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0];
soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1];
soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0];
soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1];
soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0];
soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1];
soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0];
soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1];
soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0];
soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1];
soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0];
soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1];
soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0];
soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1];
soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0];
soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1];
end
always @(*) begin
soc_a7ddrphy_dfi_p1_rddata <= 32'd0;
soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2];
soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3];
soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2];
soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3];
soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2];
soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3];
soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2];
soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3];
soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2];
soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3];
soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2];
soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3];
soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2];
soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3];
soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2];
soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3];
soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2];
soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3];
soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2];
soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3];
soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2];
soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3];
soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2];
soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3];
soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2];
soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3];
soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2];
soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3];
soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2];
soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3];
soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2];
soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3];
end
always @(*) begin
soc_a7ddrphy_dfi_p2_rddata <= 32'd0;
soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4];
soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5];
soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4];
soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5];
soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4];
soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5];
soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4];
soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5];
soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4];
soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5];
soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4];
soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5];
soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4];
soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5];
soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4];
soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5];
soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4];
soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5];
soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4];
soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5];
soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4];
soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5];
soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4];
soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5];
soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4];
soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5];
soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4];
soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5];
soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4];
soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5];
soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4];
soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5];
end
always @(*) begin
soc_a7ddrphy_dfi_p3_rddata <= 32'd0;
soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6];
soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7];
soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6];
soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7];
soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6];
soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7];
soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6];
soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7];
soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6];
soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7];
soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6];
soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7];
soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6];
soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7];
soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6];
soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7];
soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6];
soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7];
soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6];
soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7];
soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6];
soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7];
soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6];
soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7];
soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6];
soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7];
soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6];
soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7];
soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6];
soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7];
soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6];
soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7];
end
assign soc_a7ddrphy_oe = ((soc_a7ddrphy_last_wrdata_en[1] | soc_a7ddrphy_last_wrdata_en[2]) | soc_a7ddrphy_last_wrdata_en[3]);
assign soc_a7ddrphy_dqs_preamble = (soc_a7ddrphy_last_wrdata_en[1] & (~soc_a7ddrphy_last_wrdata_en[2]));
assign soc_a7ddrphy_dqs_postamble = (soc_a7ddrphy_last_wrdata_en[3] & (~soc_a7ddrphy_last_wrdata_en[2]));
assign soc_a7ddrphy_dfi_p0_address = soc_netsoc_sdram_master_p0_address;
assign soc_a7ddrphy_dfi_p0_bank = soc_netsoc_sdram_master_p0_bank;
assign soc_a7ddrphy_dfi_p0_cas_n = soc_netsoc_sdram_master_p0_cas_n;
assign soc_a7ddrphy_dfi_p0_cs_n = soc_netsoc_sdram_master_p0_cs_n;
assign soc_a7ddrphy_dfi_p0_ras_n = soc_netsoc_sdram_master_p0_ras_n;
assign soc_a7ddrphy_dfi_p0_we_n = soc_netsoc_sdram_master_p0_we_n;
assign soc_a7ddrphy_dfi_p0_cke = soc_netsoc_sdram_master_p0_cke;
assign soc_a7ddrphy_dfi_p0_odt = soc_netsoc_sdram_master_p0_odt;
assign soc_a7ddrphy_dfi_p0_reset_n = soc_netsoc_sdram_master_p0_reset_n;
assign soc_a7ddrphy_dfi_p0_act_n = soc_netsoc_sdram_master_p0_act_n;
assign soc_a7ddrphy_dfi_p0_wrdata = soc_netsoc_sdram_master_p0_wrdata;
assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_netsoc_sdram_master_p0_wrdata_en;
assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_netsoc_sdram_master_p0_wrdata_mask;
assign soc_a7ddrphy_dfi_p0_rddata_en = soc_netsoc_sdram_master_p0_rddata_en;
assign soc_netsoc_sdram_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata;
assign soc_netsoc_sdram_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid;
assign soc_a7ddrphy_dfi_p1_address = soc_netsoc_sdram_master_p1_address;
assign soc_a7ddrphy_dfi_p1_bank = soc_netsoc_sdram_master_p1_bank;
assign soc_a7ddrphy_dfi_p1_cas_n = soc_netsoc_sdram_master_p1_cas_n;
assign soc_a7ddrphy_dfi_p1_cs_n = soc_netsoc_sdram_master_p1_cs_n;
assign soc_a7ddrphy_dfi_p1_ras_n = soc_netsoc_sdram_master_p1_ras_n;
assign soc_a7ddrphy_dfi_p1_we_n = soc_netsoc_sdram_master_p1_we_n;
assign soc_a7ddrphy_dfi_p1_cke = soc_netsoc_sdram_master_p1_cke;
assign soc_a7ddrphy_dfi_p1_odt = soc_netsoc_sdram_master_p1_odt;
assign soc_a7ddrphy_dfi_p1_reset_n = soc_netsoc_sdram_master_p1_reset_n;
assign soc_a7ddrphy_dfi_p1_act_n = soc_netsoc_sdram_master_p1_act_n;
assign soc_a7ddrphy_dfi_p1_wrdata = soc_netsoc_sdram_master_p1_wrdata;
assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_netsoc_sdram_master_p1_wrdata_en;
assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_netsoc_sdram_master_p1_wrdata_mask;
assign soc_a7ddrphy_dfi_p1_rddata_en = soc_netsoc_sdram_master_p1_rddata_en;
assign soc_netsoc_sdram_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata;
assign soc_netsoc_sdram_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid;
assign soc_a7ddrphy_dfi_p2_address = soc_netsoc_sdram_master_p2_address;
assign soc_a7ddrphy_dfi_p2_bank = soc_netsoc_sdram_master_p2_bank;
assign soc_a7ddrphy_dfi_p2_cas_n = soc_netsoc_sdram_master_p2_cas_n;
assign soc_a7ddrphy_dfi_p2_cs_n = soc_netsoc_sdram_master_p2_cs_n;
assign soc_a7ddrphy_dfi_p2_ras_n = soc_netsoc_sdram_master_p2_ras_n;
assign soc_a7ddrphy_dfi_p2_we_n = soc_netsoc_sdram_master_p2_we_n;
assign soc_a7ddrphy_dfi_p2_cke = soc_netsoc_sdram_master_p2_cke;
assign soc_a7ddrphy_dfi_p2_odt = soc_netsoc_sdram_master_p2_odt;
assign soc_a7ddrphy_dfi_p2_reset_n = soc_netsoc_sdram_master_p2_reset_n;
assign soc_a7ddrphy_dfi_p2_act_n = soc_netsoc_sdram_master_p2_act_n;
assign soc_a7ddrphy_dfi_p2_wrdata = soc_netsoc_sdram_master_p2_wrdata;
assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_netsoc_sdram_master_p2_wrdata_en;
assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_netsoc_sdram_master_p2_wrdata_mask;
assign soc_a7ddrphy_dfi_p2_rddata_en = soc_netsoc_sdram_master_p2_rddata_en;
assign soc_netsoc_sdram_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata;
assign soc_netsoc_sdram_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid;
assign soc_a7ddrphy_dfi_p3_address = soc_netsoc_sdram_master_p3_address;
assign soc_a7ddrphy_dfi_p3_bank = soc_netsoc_sdram_master_p3_bank;
assign soc_a7ddrphy_dfi_p3_cas_n = soc_netsoc_sdram_master_p3_cas_n;
assign soc_a7ddrphy_dfi_p3_cs_n = soc_netsoc_sdram_master_p3_cs_n;
assign soc_a7ddrphy_dfi_p3_ras_n = soc_netsoc_sdram_master_p3_ras_n;
assign soc_a7ddrphy_dfi_p3_we_n = soc_netsoc_sdram_master_p3_we_n;
assign soc_a7ddrphy_dfi_p3_cke = soc_netsoc_sdram_master_p3_cke;
assign soc_a7ddrphy_dfi_p3_odt = soc_netsoc_sdram_master_p3_odt;
assign soc_a7ddrphy_dfi_p3_reset_n = soc_netsoc_sdram_master_p3_reset_n;
assign soc_a7ddrphy_dfi_p3_act_n = soc_netsoc_sdram_master_p3_act_n;
assign soc_a7ddrphy_dfi_p3_wrdata = soc_netsoc_sdram_master_p3_wrdata;
assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_netsoc_sdram_master_p3_wrdata_en;
assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_netsoc_sdram_master_p3_wrdata_mask;
assign soc_a7ddrphy_dfi_p3_rddata_en = soc_netsoc_sdram_master_p3_rddata_en;
assign soc_netsoc_sdram_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata;
assign soc_netsoc_sdram_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid;
assign soc_netsoc_sdram_slave_p0_address = soc_netsoc_sdram_dfi_p0_address;
assign soc_netsoc_sdram_slave_p0_bank = soc_netsoc_sdram_dfi_p0_bank;
assign soc_netsoc_sdram_slave_p0_cas_n = soc_netsoc_sdram_dfi_p0_cas_n;
assign soc_netsoc_sdram_slave_p0_cs_n = soc_netsoc_sdram_dfi_p0_cs_n;
assign soc_netsoc_sdram_slave_p0_ras_n = soc_netsoc_sdram_dfi_p0_ras_n;
assign soc_netsoc_sdram_slave_p0_we_n = soc_netsoc_sdram_dfi_p0_we_n;
assign soc_netsoc_sdram_slave_p0_cke = soc_netsoc_sdram_dfi_p0_cke;
assign soc_netsoc_sdram_slave_p0_odt = soc_netsoc_sdram_dfi_p0_odt;
assign soc_netsoc_sdram_slave_p0_reset_n = soc_netsoc_sdram_dfi_p0_reset_n;
assign soc_netsoc_sdram_slave_p0_act_n = soc_netsoc_sdram_dfi_p0_act_n;
assign soc_netsoc_sdram_slave_p0_wrdata = soc_netsoc_sdram_dfi_p0_wrdata;
assign soc_netsoc_sdram_slave_p0_wrdata_en = soc_netsoc_sdram_dfi_p0_wrdata_en;
assign soc_netsoc_sdram_slave_p0_wrdata_mask = soc_netsoc_sdram_dfi_p0_wrdata_mask;
assign soc_netsoc_sdram_slave_p0_rddata_en = soc_netsoc_sdram_dfi_p0_rddata_en;
assign soc_netsoc_sdram_dfi_p0_rddata = soc_netsoc_sdram_slave_p0_rddata;
assign soc_netsoc_sdram_dfi_p0_rddata_valid = soc_netsoc_sdram_slave_p0_rddata_valid;
assign soc_netsoc_sdram_slave_p1_address = soc_netsoc_sdram_dfi_p1_address;
assign soc_netsoc_sdram_slave_p1_bank = soc_netsoc_sdram_dfi_p1_bank;
assign soc_netsoc_sdram_slave_p1_cas_n = soc_netsoc_sdram_dfi_p1_cas_n;
assign soc_netsoc_sdram_slave_p1_cs_n = soc_netsoc_sdram_dfi_p1_cs_n;
assign soc_netsoc_sdram_slave_p1_ras_n = soc_netsoc_sdram_dfi_p1_ras_n;
assign soc_netsoc_sdram_slave_p1_we_n = soc_netsoc_sdram_dfi_p1_we_n;
assign soc_netsoc_sdram_slave_p1_cke = soc_netsoc_sdram_dfi_p1_cke;
assign soc_netsoc_sdram_slave_p1_odt = soc_netsoc_sdram_dfi_p1_odt;
assign soc_netsoc_sdram_slave_p1_reset_n = soc_netsoc_sdram_dfi_p1_reset_n;
assign soc_netsoc_sdram_slave_p1_act_n = soc_netsoc_sdram_dfi_p1_act_n;
assign soc_netsoc_sdram_slave_p1_wrdata = soc_netsoc_sdram_dfi_p1_wrdata;
assign soc_netsoc_sdram_slave_p1_wrdata_en = soc_netsoc_sdram_dfi_p1_wrdata_en;
assign soc_netsoc_sdram_slave_p1_wrdata_mask = soc_netsoc_sdram_dfi_p1_wrdata_mask;
assign soc_netsoc_sdram_slave_p1_rddata_en = soc_netsoc_sdram_dfi_p1_rddata_en;
assign soc_netsoc_sdram_dfi_p1_rddata = soc_netsoc_sdram_slave_p1_rddata;
assign soc_netsoc_sdram_dfi_p1_rddata_valid = soc_netsoc_sdram_slave_p1_rddata_valid;
assign soc_netsoc_sdram_slave_p2_address = soc_netsoc_sdram_dfi_p2_address;
assign soc_netsoc_sdram_slave_p2_bank = soc_netsoc_sdram_dfi_p2_bank;
assign soc_netsoc_sdram_slave_p2_cas_n = soc_netsoc_sdram_dfi_p2_cas_n;
assign soc_netsoc_sdram_slave_p2_cs_n = soc_netsoc_sdram_dfi_p2_cs_n;
assign soc_netsoc_sdram_slave_p2_ras_n = soc_netsoc_sdram_dfi_p2_ras_n;
assign soc_netsoc_sdram_slave_p2_we_n = soc_netsoc_sdram_dfi_p2_we_n;
assign soc_netsoc_sdram_slave_p2_cke = soc_netsoc_sdram_dfi_p2_cke;
assign soc_netsoc_sdram_slave_p2_odt = soc_netsoc_sdram_dfi_p2_odt;
assign soc_netsoc_sdram_slave_p2_reset_n = soc_netsoc_sdram_dfi_p2_reset_n;
assign soc_netsoc_sdram_slave_p2_act_n = soc_netsoc_sdram_dfi_p2_act_n;
assign soc_netsoc_sdram_slave_p2_wrdata = soc_netsoc_sdram_dfi_p2_wrdata;
assign soc_netsoc_sdram_slave_p2_wrdata_en = soc_netsoc_sdram_dfi_p2_wrdata_en;
assign soc_netsoc_sdram_slave_p2_wrdata_mask = soc_netsoc_sdram_dfi_p2_wrdata_mask;
assign soc_netsoc_sdram_slave_p2_rddata_en = soc_netsoc_sdram_dfi_p2_rddata_en;
assign soc_netsoc_sdram_dfi_p2_rddata = soc_netsoc_sdram_slave_p2_rddata;
assign soc_netsoc_sdram_dfi_p2_rddata_valid = soc_netsoc_sdram_slave_p2_rddata_valid;
assign soc_netsoc_sdram_slave_p3_address = soc_netsoc_sdram_dfi_p3_address;
assign soc_netsoc_sdram_slave_p3_bank = soc_netsoc_sdram_dfi_p3_bank;
assign soc_netsoc_sdram_slave_p3_cas_n = soc_netsoc_sdram_dfi_p3_cas_n;
assign soc_netsoc_sdram_slave_p3_cs_n = soc_netsoc_sdram_dfi_p3_cs_n;
assign soc_netsoc_sdram_slave_p3_ras_n = soc_netsoc_sdram_dfi_p3_ras_n;
assign soc_netsoc_sdram_slave_p3_we_n = soc_netsoc_sdram_dfi_p3_we_n;
assign soc_netsoc_sdram_slave_p3_cke = soc_netsoc_sdram_dfi_p3_cke;
assign soc_netsoc_sdram_slave_p3_odt = soc_netsoc_sdram_dfi_p3_odt;
assign soc_netsoc_sdram_slave_p3_reset_n = soc_netsoc_sdram_dfi_p3_reset_n;
assign soc_netsoc_sdram_slave_p3_act_n = soc_netsoc_sdram_dfi_p3_act_n;
assign soc_netsoc_sdram_slave_p3_wrdata = soc_netsoc_sdram_dfi_p3_wrdata;
assign soc_netsoc_sdram_slave_p3_wrdata_en = soc_netsoc_sdram_dfi_p3_wrdata_en;
assign soc_netsoc_sdram_slave_p3_wrdata_mask = soc_netsoc_sdram_dfi_p3_wrdata_mask;
assign soc_netsoc_sdram_slave_p3_rddata_en = soc_netsoc_sdram_dfi_p3_rddata_en;
assign soc_netsoc_sdram_dfi_p3_rddata = soc_netsoc_sdram_slave_p3_rddata;
assign soc_netsoc_sdram_dfi_p3_rddata_valid = soc_netsoc_sdram_slave_p3_rddata_valid;
always @(*) begin
soc_netsoc_sdram_master_p2_we_n <= 1'd1;
soc_netsoc_sdram_master_p2_cke <= 1'd0;
soc_netsoc_sdram_master_p2_odt <= 1'd0;
soc_netsoc_sdram_master_p2_reset_n <= 1'd0;
soc_netsoc_sdram_master_p2_act_n <= 1'd1;
soc_netsoc_sdram_master_p2_wrdata <= 32'd0;
soc_netsoc_sdram_inti_p3_rddata <= 32'd0;
soc_netsoc_sdram_master_p2_wrdata_en <= 1'd0;
soc_netsoc_sdram_inti_p3_rddata_valid <= 1'd0;
soc_netsoc_sdram_master_p2_wrdata_mask <= 4'd0;
soc_netsoc_sdram_master_p2_rddata_en <= 1'd0;
soc_netsoc_sdram_master_p3_address <= 14'd0;
soc_netsoc_sdram_master_p3_bank <= 3'd0;
soc_netsoc_sdram_master_p3_cas_n <= 1'd1;
soc_netsoc_sdram_master_p3_cs_n <= 1'd1;
soc_netsoc_sdram_master_p3_ras_n <= 1'd1;
soc_netsoc_sdram_master_p3_we_n <= 1'd1;
soc_netsoc_sdram_master_p3_cke <= 1'd0;
soc_netsoc_sdram_master_p3_odt <= 1'd0;
soc_netsoc_sdram_master_p3_reset_n <= 1'd0;
soc_netsoc_sdram_master_p3_act_n <= 1'd1;
soc_netsoc_sdram_master_p3_wrdata <= 32'd0;
soc_netsoc_sdram_master_p3_wrdata_en <= 1'd0;
soc_netsoc_sdram_master_p3_wrdata_mask <= 4'd0;
soc_netsoc_sdram_master_p3_rddata_en <= 1'd0;
soc_netsoc_sdram_slave_p0_rddata <= 32'd0;
soc_netsoc_sdram_slave_p0_rddata_valid <= 1'd0;
soc_netsoc_sdram_slave_p1_rddata <= 32'd0;
soc_netsoc_sdram_slave_p1_rddata_valid <= 1'd0;
soc_netsoc_sdram_slave_p2_rddata <= 32'd0;
soc_netsoc_sdram_slave_p2_rddata_valid <= 1'd0;
soc_netsoc_sdram_slave_p3_rddata <= 32'd0;
soc_netsoc_sdram_slave_p3_rddata_valid <= 1'd0;
soc_netsoc_sdram_inti_p0_rddata <= 32'd0;
soc_netsoc_sdram_inti_p0_rddata_valid <= 1'd0;
soc_netsoc_sdram_master_p0_address <= 14'd0;
soc_netsoc_sdram_master_p0_bank <= 3'd0;
soc_netsoc_sdram_master_p0_cas_n <= 1'd1;
soc_netsoc_sdram_master_p0_cs_n <= 1'd1;
soc_netsoc_sdram_master_p0_ras_n <= 1'd1;
soc_netsoc_sdram_master_p0_we_n <= 1'd1;
soc_netsoc_sdram_master_p0_cke <= 1'd0;
soc_netsoc_sdram_master_p0_odt <= 1'd0;
soc_netsoc_sdram_master_p0_reset_n <= 1'd0;
soc_netsoc_sdram_master_p0_act_n <= 1'd1;
soc_netsoc_sdram_master_p0_wrdata <= 32'd0;
soc_netsoc_sdram_inti_p1_rddata <= 32'd0;
soc_netsoc_sdram_master_p0_wrdata_en <= 1'd0;
soc_netsoc_sdram_inti_p1_rddata_valid <= 1'd0;
soc_netsoc_sdram_master_p0_wrdata_mask <= 4'd0;
soc_netsoc_sdram_master_p0_rddata_en <= 1'd0;
soc_netsoc_sdram_master_p1_address <= 14'd0;
soc_netsoc_sdram_master_p1_bank <= 3'd0;
soc_netsoc_sdram_master_p1_cas_n <= 1'd1;
soc_netsoc_sdram_master_p1_cs_n <= 1'd1;
soc_netsoc_sdram_master_p1_ras_n <= 1'd1;
soc_netsoc_sdram_master_p1_we_n <= 1'd1;
soc_netsoc_sdram_master_p1_cke <= 1'd0;
soc_netsoc_sdram_master_p1_odt <= 1'd0;
soc_netsoc_sdram_master_p1_reset_n <= 1'd0;
soc_netsoc_sdram_master_p1_act_n <= 1'd1;
soc_netsoc_sdram_master_p1_wrdata <= 32'd0;
soc_netsoc_sdram_inti_p2_rddata <= 32'd0;
soc_netsoc_sdram_master_p1_wrdata_en <= 1'd0;
soc_netsoc_sdram_inti_p2_rddata_valid <= 1'd0;
soc_netsoc_sdram_master_p1_wrdata_mask <= 4'd0;
soc_netsoc_sdram_master_p1_rddata_en <= 1'd0;
soc_netsoc_sdram_master_p2_address <= 14'd0;
soc_netsoc_sdram_master_p2_bank <= 3'd0;
soc_netsoc_sdram_master_p2_cas_n <= 1'd1;
soc_netsoc_sdram_master_p2_cs_n <= 1'd1;
soc_netsoc_sdram_master_p2_ras_n <= 1'd1;
if (soc_netsoc_sdram_storage[0]) begin
soc_netsoc_sdram_master_p0_address <= soc_netsoc_sdram_slave_p0_address;
soc_netsoc_sdram_master_p0_bank <= soc_netsoc_sdram_slave_p0_bank;
soc_netsoc_sdram_master_p0_cas_n <= soc_netsoc_sdram_slave_p0_cas_n;
soc_netsoc_sdram_master_p0_cs_n <= soc_netsoc_sdram_slave_p0_cs_n;
soc_netsoc_sdram_master_p0_ras_n <= soc_netsoc_sdram_slave_p0_ras_n;
soc_netsoc_sdram_master_p0_we_n <= soc_netsoc_sdram_slave_p0_we_n;
soc_netsoc_sdram_master_p0_cke <= soc_netsoc_sdram_slave_p0_cke;
soc_netsoc_sdram_master_p0_odt <= soc_netsoc_sdram_slave_p0_odt;
soc_netsoc_sdram_master_p0_reset_n <= soc_netsoc_sdram_slave_p0_reset_n;
soc_netsoc_sdram_master_p0_act_n <= soc_netsoc_sdram_slave_p0_act_n;
soc_netsoc_sdram_master_p0_wrdata <= soc_netsoc_sdram_slave_p0_wrdata;
soc_netsoc_sdram_master_p0_wrdata_en <= soc_netsoc_sdram_slave_p0_wrdata_en;
soc_netsoc_sdram_master_p0_wrdata_mask <= soc_netsoc_sdram_slave_p0_wrdata_mask;
soc_netsoc_sdram_master_p0_rddata_en <= soc_netsoc_sdram_slave_p0_rddata_en;
soc_netsoc_sdram_slave_p0_rddata <= soc_netsoc_sdram_master_p0_rddata;
soc_netsoc_sdram_slave_p0_rddata_valid <= soc_netsoc_sdram_master_p0_rddata_valid;
soc_netsoc_sdram_master_p1_address <= soc_netsoc_sdram_slave_p1_address;
soc_netsoc_sdram_master_p1_bank <= soc_netsoc_sdram_slave_p1_bank;
soc_netsoc_sdram_master_p1_cas_n <= soc_netsoc_sdram_slave_p1_cas_n;
soc_netsoc_sdram_master_p1_cs_n <= soc_netsoc_sdram_slave_p1_cs_n;
soc_netsoc_sdram_master_p1_ras_n <= soc_netsoc_sdram_slave_p1_ras_n;
soc_netsoc_sdram_master_p1_we_n <= soc_netsoc_sdram_slave_p1_we_n;
soc_netsoc_sdram_master_p1_cke <= soc_netsoc_sdram_slave_p1_cke;
soc_netsoc_sdram_master_p1_odt <= soc_netsoc_sdram_slave_p1_odt;
soc_netsoc_sdram_master_p1_reset_n <= soc_netsoc_sdram_slave_p1_reset_n;
soc_netsoc_sdram_master_p1_act_n <= soc_netsoc_sdram_slave_p1_act_n;
soc_netsoc_sdram_master_p1_wrdata <= soc_netsoc_sdram_slave_p1_wrdata;
soc_netsoc_sdram_master_p1_wrdata_en <= soc_netsoc_sdram_slave_p1_wrdata_en;
soc_netsoc_sdram_master_p1_wrdata_mask <= soc_netsoc_sdram_slave_p1_wrdata_mask;
soc_netsoc_sdram_master_p1_rddata_en <= soc_netsoc_sdram_slave_p1_rddata_en;
soc_netsoc_sdram_slave_p1_rddata <= soc_netsoc_sdram_master_p1_rddata;
soc_netsoc_sdram_slave_p1_rddata_valid <= soc_netsoc_sdram_master_p1_rddata_valid;
soc_netsoc_sdram_master_p2_address <= soc_netsoc_sdram_slave_p2_address;
soc_netsoc_sdram_master_p2_bank <= soc_netsoc_sdram_slave_p2_bank;
soc_netsoc_sdram_master_p2_cas_n <= soc_netsoc_sdram_slave_p2_cas_n;
soc_netsoc_sdram_master_p2_cs_n <= soc_netsoc_sdram_slave_p2_cs_n;
soc_netsoc_sdram_master_p2_ras_n <= soc_netsoc_sdram_slave_p2_ras_n;
soc_netsoc_sdram_master_p2_we_n <= soc_netsoc_sdram_slave_p2_we_n;
soc_netsoc_sdram_master_p2_cke <= soc_netsoc_sdram_slave_p2_cke;
soc_netsoc_sdram_master_p2_odt <= soc_netsoc_sdram_slave_p2_odt;
soc_netsoc_sdram_master_p2_reset_n <= soc_netsoc_sdram_slave_p2_reset_n;
soc_netsoc_sdram_master_p2_act_n <= soc_netsoc_sdram_slave_p2_act_n;
soc_netsoc_sdram_master_p2_wrdata <= soc_netsoc_sdram_slave_p2_wrdata;
soc_netsoc_sdram_master_p2_wrdata_en <= soc_netsoc_sdram_slave_p2_wrdata_en;
soc_netsoc_sdram_master_p2_wrdata_mask <= soc_netsoc_sdram_slave_p2_wrdata_mask;
soc_netsoc_sdram_master_p2_rddata_en <= soc_netsoc_sdram_slave_p2_rddata_en;
soc_netsoc_sdram_slave_p2_rddata <= soc_netsoc_sdram_master_p2_rddata;
soc_netsoc_sdram_slave_p2_rddata_valid <= soc_netsoc_sdram_master_p2_rddata_valid;
soc_netsoc_sdram_master_p3_address <= soc_netsoc_sdram_slave_p3_address;
soc_netsoc_sdram_master_p3_bank <= soc_netsoc_sdram_slave_p3_bank;
soc_netsoc_sdram_master_p3_cas_n <= soc_netsoc_sdram_slave_p3_cas_n;
soc_netsoc_sdram_master_p3_cs_n <= soc_netsoc_sdram_slave_p3_cs_n;
soc_netsoc_sdram_master_p3_ras_n <= soc_netsoc_sdram_slave_p3_ras_n;
soc_netsoc_sdram_master_p3_we_n <= soc_netsoc_sdram_slave_p3_we_n;
soc_netsoc_sdram_master_p3_cke <= soc_netsoc_sdram_slave_p3_cke;
soc_netsoc_sdram_master_p3_odt <= soc_netsoc_sdram_slave_p3_odt;
soc_netsoc_sdram_master_p3_reset_n <= soc_netsoc_sdram_slave_p3_reset_n;
soc_netsoc_sdram_master_p3_act_n <= soc_netsoc_sdram_slave_p3_act_n;
soc_netsoc_sdram_master_p3_wrdata <= soc_netsoc_sdram_slave_p3_wrdata;
soc_netsoc_sdram_master_p3_wrdata_en <= soc_netsoc_sdram_slave_p3_wrdata_en;
soc_netsoc_sdram_master_p3_wrdata_mask <= soc_netsoc_sdram_slave_p3_wrdata_mask;
soc_netsoc_sdram_master_p3_rddata_en <= soc_netsoc_sdram_slave_p3_rddata_en;
soc_netsoc_sdram_slave_p3_rddata <= soc_netsoc_sdram_master_p3_rddata;
soc_netsoc_sdram_slave_p3_rddata_valid <= soc_netsoc_sdram_master_p3_rddata_valid;
end else begin
soc_netsoc_sdram_master_p0_address <= soc_netsoc_sdram_inti_p0_address;
soc_netsoc_sdram_master_p0_bank <= soc_netsoc_sdram_inti_p0_bank;
soc_netsoc_sdram_master_p0_cas_n <= soc_netsoc_sdram_inti_p0_cas_n;
soc_netsoc_sdram_master_p0_cs_n <= soc_netsoc_sdram_inti_p0_cs_n;
soc_netsoc_sdram_master_p0_ras_n <= soc_netsoc_sdram_inti_p0_ras_n;
soc_netsoc_sdram_master_p0_we_n <= soc_netsoc_sdram_inti_p0_we_n;
soc_netsoc_sdram_master_p0_cke <= soc_netsoc_sdram_inti_p0_cke;
soc_netsoc_sdram_master_p0_odt <= soc_netsoc_sdram_inti_p0_odt;
soc_netsoc_sdram_master_p0_reset_n <= soc_netsoc_sdram_inti_p0_reset_n;
soc_netsoc_sdram_master_p0_act_n <= soc_netsoc_sdram_inti_p0_act_n;
soc_netsoc_sdram_master_p0_wrdata <= soc_netsoc_sdram_inti_p0_wrdata;
soc_netsoc_sdram_master_p0_wrdata_en <= soc_netsoc_sdram_inti_p0_wrdata_en;
soc_netsoc_sdram_master_p0_wrdata_mask <= soc_netsoc_sdram_inti_p0_wrdata_mask;
soc_netsoc_sdram_master_p0_rddata_en <= soc_netsoc_sdram_inti_p0_rddata_en;
soc_netsoc_sdram_inti_p0_rddata <= soc_netsoc_sdram_master_p0_rddata;
soc_netsoc_sdram_inti_p0_rddata_valid <= soc_netsoc_sdram_master_p0_rddata_valid;
soc_netsoc_sdram_master_p1_address <= soc_netsoc_sdram_inti_p1_address;
soc_netsoc_sdram_master_p1_bank <= soc_netsoc_sdram_inti_p1_bank;
soc_netsoc_sdram_master_p1_cas_n <= soc_netsoc_sdram_inti_p1_cas_n;
soc_netsoc_sdram_master_p1_cs_n <= soc_netsoc_sdram_inti_p1_cs_n;
soc_netsoc_sdram_master_p1_ras_n <= soc_netsoc_sdram_inti_p1_ras_n;
soc_netsoc_sdram_master_p1_we_n <= soc_netsoc_sdram_inti_p1_we_n;
soc_netsoc_sdram_master_p1_cke <= soc_netsoc_sdram_inti_p1_cke;
soc_netsoc_sdram_master_p1_odt <= soc_netsoc_sdram_inti_p1_odt;
soc_netsoc_sdram_master_p1_reset_n <= soc_netsoc_sdram_inti_p1_reset_n;
soc_netsoc_sdram_master_p1_act_n <= soc_netsoc_sdram_inti_p1_act_n;
soc_netsoc_sdram_master_p1_wrdata <= soc_netsoc_sdram_inti_p1_wrdata;
soc_netsoc_sdram_master_p1_wrdata_en <= soc_netsoc_sdram_inti_p1_wrdata_en;
soc_netsoc_sdram_master_p1_wrdata_mask <= soc_netsoc_sdram_inti_p1_wrdata_mask;
soc_netsoc_sdram_master_p1_rddata_en <= soc_netsoc_sdram_inti_p1_rddata_en;
soc_netsoc_sdram_inti_p1_rddata <= soc_netsoc_sdram_master_p1_rddata;
soc_netsoc_sdram_inti_p1_rddata_valid <= soc_netsoc_sdram_master_p1_rddata_valid;
soc_netsoc_sdram_master_p2_address <= soc_netsoc_sdram_inti_p2_address;
soc_netsoc_sdram_master_p2_bank <= soc_netsoc_sdram_inti_p2_bank;
soc_netsoc_sdram_master_p2_cas_n <= soc_netsoc_sdram_inti_p2_cas_n;
soc_netsoc_sdram_master_p2_cs_n <= soc_netsoc_sdram_inti_p2_cs_n;
soc_netsoc_sdram_master_p2_ras_n <= soc_netsoc_sdram_inti_p2_ras_n;
soc_netsoc_sdram_master_p2_we_n <= soc_netsoc_sdram_inti_p2_we_n;
soc_netsoc_sdram_master_p2_cke <= soc_netsoc_sdram_inti_p2_cke;
soc_netsoc_sdram_master_p2_odt <= soc_netsoc_sdram_inti_p2_odt;
soc_netsoc_sdram_master_p2_reset_n <= soc_netsoc_sdram_inti_p2_reset_n;
soc_netsoc_sdram_master_p2_act_n <= soc_netsoc_sdram_inti_p2_act_n;
soc_netsoc_sdram_master_p2_wrdata <= soc_netsoc_sdram_inti_p2_wrdata;
soc_netsoc_sdram_master_p2_wrdata_en <= soc_netsoc_sdram_inti_p2_wrdata_en;
soc_netsoc_sdram_master_p2_wrdata_mask <= soc_netsoc_sdram_inti_p2_wrdata_mask;
soc_netsoc_sdram_master_p2_rddata_en <= soc_netsoc_sdram_inti_p2_rddata_en;
soc_netsoc_sdram_inti_p2_rddata <= soc_netsoc_sdram_master_p2_rddata;
soc_netsoc_sdram_inti_p2_rddata_valid <= soc_netsoc_sdram_master_p2_rddata_valid;
soc_netsoc_sdram_master_p3_address <= soc_netsoc_sdram_inti_p3_address;
soc_netsoc_sdram_master_p3_bank <= soc_netsoc_sdram_inti_p3_bank;
soc_netsoc_sdram_master_p3_cas_n <= soc_netsoc_sdram_inti_p3_cas_n;
soc_netsoc_sdram_master_p3_cs_n <= soc_netsoc_sdram_inti_p3_cs_n;
soc_netsoc_sdram_master_p3_ras_n <= soc_netsoc_sdram_inti_p3_ras_n;
soc_netsoc_sdram_master_p3_we_n <= soc_netsoc_sdram_inti_p3_we_n;
soc_netsoc_sdram_master_p3_cke <= soc_netsoc_sdram_inti_p3_cke;
soc_netsoc_sdram_master_p3_odt <= soc_netsoc_sdram_inti_p3_odt;
soc_netsoc_sdram_master_p3_reset_n <= soc_netsoc_sdram_inti_p3_reset_n;
soc_netsoc_sdram_master_p3_act_n <= soc_netsoc_sdram_inti_p3_act_n;
soc_netsoc_sdram_master_p3_wrdata <= soc_netsoc_sdram_inti_p3_wrdata;
soc_netsoc_sdram_master_p3_wrdata_en <= soc_netsoc_sdram_inti_p3_wrdata_en;
soc_netsoc_sdram_master_p3_wrdata_mask <= soc_netsoc_sdram_inti_p3_wrdata_mask;
soc_netsoc_sdram_master_p3_rddata_en <= soc_netsoc_sdram_inti_p3_rddata_en;
soc_netsoc_sdram_inti_p3_rddata <= soc_netsoc_sdram_master_p3_rddata;
soc_netsoc_sdram_inti_p3_rddata_valid <= soc_netsoc_sdram_master_p3_rddata_valid;
end
end
assign soc_netsoc_sdram_inti_p0_cke = soc_netsoc_sdram_storage[1];
assign soc_netsoc_sdram_inti_p1_cke = soc_netsoc_sdram_storage[1];
assign soc_netsoc_sdram_inti_p2_cke = soc_netsoc_sdram_storage[1];
assign soc_netsoc_sdram_inti_p3_cke = soc_netsoc_sdram_storage[1];
assign soc_netsoc_sdram_inti_p0_odt = soc_netsoc_sdram_storage[2];
assign soc_netsoc_sdram_inti_p1_odt = soc_netsoc_sdram_storage[2];
assign soc_netsoc_sdram_inti_p2_odt = soc_netsoc_sdram_storage[2];
assign soc_netsoc_sdram_inti_p3_odt = soc_netsoc_sdram_storage[2];
assign soc_netsoc_sdram_inti_p0_reset_n = soc_netsoc_sdram_storage[3];
assign soc_netsoc_sdram_inti_p1_reset_n = soc_netsoc_sdram_storage[3];
assign soc_netsoc_sdram_inti_p2_reset_n = soc_netsoc_sdram_storage[3];
assign soc_netsoc_sdram_inti_p3_reset_n = soc_netsoc_sdram_storage[3];
always @(*) begin
soc_netsoc_sdram_inti_p0_we_n <= 1'd1;
soc_netsoc_sdram_inti_p0_cas_n <= 1'd1;
soc_netsoc_sdram_inti_p0_cs_n <= 1'd1;
soc_netsoc_sdram_inti_p0_ras_n <= 1'd1;
if (soc_netsoc_sdram_phaseinjector0_command_issue_re) begin
soc_netsoc_sdram_inti_p0_cs_n <= {1{(~soc_netsoc_sdram_phaseinjector0_command_storage[0])}};
soc_netsoc_sdram_inti_p0_we_n <= (~soc_netsoc_sdram_phaseinjector0_command_storage[1]);
soc_netsoc_sdram_inti_p0_cas_n <= (~soc_netsoc_sdram_phaseinjector0_command_storage[2]);
soc_netsoc_sdram_inti_p0_ras_n <= (~soc_netsoc_sdram_phaseinjector0_command_storage[3]);
end else begin
soc_netsoc_sdram_inti_p0_cs_n <= {1{1'd1}};
soc_netsoc_sdram_inti_p0_we_n <= 1'd1;
soc_netsoc_sdram_inti_p0_cas_n <= 1'd1;
soc_netsoc_sdram_inti_p0_ras_n <= 1'd1;
end
end
assign soc_netsoc_sdram_inti_p0_address = soc_netsoc_sdram_phaseinjector0_address_storage;
assign soc_netsoc_sdram_inti_p0_bank = soc_netsoc_sdram_phaseinjector0_baddress_storage;
assign soc_netsoc_sdram_inti_p0_wrdata_en = (soc_netsoc_sdram_phaseinjector0_command_issue_re & soc_netsoc_sdram_phaseinjector0_command_storage[4]);
assign soc_netsoc_sdram_inti_p0_rddata_en = (soc_netsoc_sdram_phaseinjector0_command_issue_re & soc_netsoc_sdram_phaseinjector0_command_storage[5]);
assign soc_netsoc_sdram_inti_p0_wrdata = soc_netsoc_sdram_phaseinjector0_wrdata_storage;
assign soc_netsoc_sdram_inti_p0_wrdata_mask = 1'd0;
always @(*) begin
soc_netsoc_sdram_inti_p1_we_n <= 1'd1;
soc_netsoc_sdram_inti_p1_cas_n <= 1'd1;
soc_netsoc_sdram_inti_p1_cs_n <= 1'd1;
soc_netsoc_sdram_inti_p1_ras_n <= 1'd1;
if (soc_netsoc_sdram_phaseinjector1_command_issue_re) begin
soc_netsoc_sdram_inti_p1_cs_n <= {1{(~soc_netsoc_sdram_phaseinjector1_command_storage[0])}};
soc_netsoc_sdram_inti_p1_we_n <= (~soc_netsoc_sdram_phaseinjector1_command_storage[1]);
soc_netsoc_sdram_inti_p1_cas_n <= (~soc_netsoc_sdram_phaseinjector1_command_storage[2]);
soc_netsoc_sdram_inti_p1_ras_n <= (~soc_netsoc_sdram_phaseinjector1_command_storage[3]);
end else begin
soc_netsoc_sdram_inti_p1_cs_n <= {1{1'd1}};
soc_netsoc_sdram_inti_p1_we_n <= 1'd1;
soc_netsoc_sdram_inti_p1_cas_n <= 1'd1;
soc_netsoc_sdram_inti_p1_ras_n <= 1'd1;
end
end
assign soc_netsoc_sdram_inti_p1_address = soc_netsoc_sdram_phaseinjector1_address_storage;
assign soc_netsoc_sdram_inti_p1_bank = soc_netsoc_sdram_phaseinjector1_baddress_storage;
assign soc_netsoc_sdram_inti_p1_wrdata_en = (soc_netsoc_sdram_phaseinjector1_command_issue_re & soc_netsoc_sdram_phaseinjector1_command_storage[4]);
assign soc_netsoc_sdram_inti_p1_rddata_en = (soc_netsoc_sdram_phaseinjector1_command_issue_re & soc_netsoc_sdram_phaseinjector1_command_storage[5]);
assign soc_netsoc_sdram_inti_p1_wrdata = soc_netsoc_sdram_phaseinjector1_wrdata_storage;
assign soc_netsoc_sdram_inti_p1_wrdata_mask = 1'd0;
always @(*) begin
soc_netsoc_sdram_inti_p2_we_n <= 1'd1;
soc_netsoc_sdram_inti_p2_cas_n <= 1'd1;
soc_netsoc_sdram_inti_p2_cs_n <= 1'd1;
soc_netsoc_sdram_inti_p2_ras_n <= 1'd1;
if (soc_netsoc_sdram_phaseinjector2_command_issue_re) begin
soc_netsoc_sdram_inti_p2_cs_n <= {1{(~soc_netsoc_sdram_phaseinjector2_command_storage[0])}};
soc_netsoc_sdram_inti_p2_we_n <= (~soc_netsoc_sdram_phaseinjector2_command_storage[1]);
soc_netsoc_sdram_inti_p2_cas_n <= (~soc_netsoc_sdram_phaseinjector2_command_storage[2]);
soc_netsoc_sdram_inti_p2_ras_n <= (~soc_netsoc_sdram_phaseinjector2_command_storage[3]);
end else begin
soc_netsoc_sdram_inti_p2_cs_n <= {1{1'd1}};
soc_netsoc_sdram_inti_p2_we_n <= 1'd1;
soc_netsoc_sdram_inti_p2_cas_n <= 1'd1;
soc_netsoc_sdram_inti_p2_ras_n <= 1'd1;
end
end
assign soc_netsoc_sdram_inti_p2_address = soc_netsoc_sdram_phaseinjector2_address_storage;
assign soc_netsoc_sdram_inti_p2_bank = soc_netsoc_sdram_phaseinjector2_baddress_storage;
assign soc_netsoc_sdram_inti_p2_wrdata_en = (soc_netsoc_sdram_phaseinjector2_command_issue_re & soc_netsoc_sdram_phaseinjector2_command_storage[4]);
assign soc_netsoc_sdram_inti_p2_rddata_en = (soc_netsoc_sdram_phaseinjector2_command_issue_re & soc_netsoc_sdram_phaseinjector2_command_storage[5]);
assign soc_netsoc_sdram_inti_p2_wrdata = soc_netsoc_sdram_phaseinjector2_wrdata_storage;
assign soc_netsoc_sdram_inti_p2_wrdata_mask = 1'd0;
always @(*) begin
soc_netsoc_sdram_inti_p3_we_n <= 1'd1;
soc_netsoc_sdram_inti_p3_cas_n <= 1'd1;
soc_netsoc_sdram_inti_p3_cs_n <= 1'd1;
soc_netsoc_sdram_inti_p3_ras_n <= 1'd1;
if (soc_netsoc_sdram_phaseinjector3_command_issue_re) begin
soc_netsoc_sdram_inti_p3_cs_n <= {1{(~soc_netsoc_sdram_phaseinjector3_command_storage[0])}};
soc_netsoc_sdram_inti_p3_we_n <= (~soc_netsoc_sdram_phaseinjector3_command_storage[1]);
soc_netsoc_sdram_inti_p3_cas_n <= (~soc_netsoc_sdram_phaseinjector3_command_storage[2]);
soc_netsoc_sdram_inti_p3_ras_n <= (~soc_netsoc_sdram_phaseinjector3_command_storage[3]);
end else begin
soc_netsoc_sdram_inti_p3_cs_n <= {1{1'd1}};
soc_netsoc_sdram_inti_p3_we_n <= 1'd1;
soc_netsoc_sdram_inti_p3_cas_n <= 1'd1;
soc_netsoc_sdram_inti_p3_ras_n <= 1'd1;
end
end
assign soc_netsoc_sdram_inti_p3_address = soc_netsoc_sdram_phaseinjector3_address_storage;
assign soc_netsoc_sdram_inti_p3_bank = soc_netsoc_sdram_phaseinjector3_baddress_storage;
assign soc_netsoc_sdram_inti_p3_wrdata_en = (soc_netsoc_sdram_phaseinjector3_command_issue_re & soc_netsoc_sdram_phaseinjector3_command_storage[4]);
assign soc_netsoc_sdram_inti_p3_rddata_en = (soc_netsoc_sdram_phaseinjector3_command_issue_re & soc_netsoc_sdram_phaseinjector3_command_storage[5]);
assign soc_netsoc_sdram_inti_p3_wrdata = soc_netsoc_sdram_phaseinjector3_wrdata_storage;
assign soc_netsoc_sdram_inti_p3_wrdata_mask = 1'd0;
assign soc_netsoc_sdram_bankmachine0_req_valid = soc_netsoc_sdram_interface_bank0_valid;
assign soc_netsoc_sdram_interface_bank0_ready = soc_netsoc_sdram_bankmachine0_req_ready;
assign soc_netsoc_sdram_bankmachine0_req_we = soc_netsoc_sdram_interface_bank0_we;
assign soc_netsoc_sdram_bankmachine0_req_addr = soc_netsoc_sdram_interface_bank0_addr;
assign soc_netsoc_sdram_interface_bank0_lock = soc_netsoc_sdram_bankmachine0_req_lock;
assign soc_netsoc_sdram_interface_bank0_wdata_ready = soc_netsoc_sdram_bankmachine0_req_wdata_ready;
assign soc_netsoc_sdram_interface_bank0_rdata_valid = soc_netsoc_sdram_bankmachine0_req_rdata_valid;
assign soc_netsoc_sdram_bankmachine1_req_valid = soc_netsoc_sdram_interface_bank1_valid;
assign soc_netsoc_sdram_interface_bank1_ready = soc_netsoc_sdram_bankmachine1_req_ready;
assign soc_netsoc_sdram_bankmachine1_req_we = soc_netsoc_sdram_interface_bank1_we;
assign soc_netsoc_sdram_bankmachine1_req_addr = soc_netsoc_sdram_interface_bank1_addr;
assign soc_netsoc_sdram_interface_bank1_lock = soc_netsoc_sdram_bankmachine1_req_lock;
assign soc_netsoc_sdram_interface_bank1_wdata_ready = soc_netsoc_sdram_bankmachine1_req_wdata_ready;
assign soc_netsoc_sdram_interface_bank1_rdata_valid = soc_netsoc_sdram_bankmachine1_req_rdata_valid;
assign soc_netsoc_sdram_bankmachine2_req_valid = soc_netsoc_sdram_interface_bank2_valid;
assign soc_netsoc_sdram_interface_bank2_ready = soc_netsoc_sdram_bankmachine2_req_ready;
assign soc_netsoc_sdram_bankmachine2_req_we = soc_netsoc_sdram_interface_bank2_we;
assign soc_netsoc_sdram_bankmachine2_req_addr = soc_netsoc_sdram_interface_bank2_addr;
assign soc_netsoc_sdram_interface_bank2_lock = soc_netsoc_sdram_bankmachine2_req_lock;
assign soc_netsoc_sdram_interface_bank2_wdata_ready = soc_netsoc_sdram_bankmachine2_req_wdata_ready;
assign soc_netsoc_sdram_interface_bank2_rdata_valid = soc_netsoc_sdram_bankmachine2_req_rdata_valid;
assign soc_netsoc_sdram_bankmachine3_req_valid = soc_netsoc_sdram_interface_bank3_valid;
assign soc_netsoc_sdram_interface_bank3_ready = soc_netsoc_sdram_bankmachine3_req_ready;
assign soc_netsoc_sdram_bankmachine3_req_we = soc_netsoc_sdram_interface_bank3_we;
assign soc_netsoc_sdram_bankmachine3_req_addr = soc_netsoc_sdram_interface_bank3_addr;
assign soc_netsoc_sdram_interface_bank3_lock = soc_netsoc_sdram_bankmachine3_req_lock;
assign soc_netsoc_sdram_interface_bank3_wdata_ready = soc_netsoc_sdram_bankmachine3_req_wdata_ready;
assign soc_netsoc_sdram_interface_bank3_rdata_valid = soc_netsoc_sdram_bankmachine3_req_rdata_valid;
assign soc_netsoc_sdram_bankmachine4_req_valid = soc_netsoc_sdram_interface_bank4_valid;
assign soc_netsoc_sdram_interface_bank4_ready = soc_netsoc_sdram_bankmachine4_req_ready;
assign soc_netsoc_sdram_bankmachine4_req_we = soc_netsoc_sdram_interface_bank4_we;
assign soc_netsoc_sdram_bankmachine4_req_addr = soc_netsoc_sdram_interface_bank4_addr;
assign soc_netsoc_sdram_interface_bank4_lock = soc_netsoc_sdram_bankmachine4_req_lock;
assign soc_netsoc_sdram_interface_bank4_wdata_ready = soc_netsoc_sdram_bankmachine4_req_wdata_ready;
assign soc_netsoc_sdram_interface_bank4_rdata_valid = soc_netsoc_sdram_bankmachine4_req_rdata_valid;
assign soc_netsoc_sdram_bankmachine5_req_valid = soc_netsoc_sdram_interface_bank5_valid;
assign soc_netsoc_sdram_interface_bank5_ready = soc_netsoc_sdram_bankmachine5_req_ready;
assign soc_netsoc_sdram_bankmachine5_req_we = soc_netsoc_sdram_interface_bank5_we;
assign soc_netsoc_sdram_bankmachine5_req_addr = soc_netsoc_sdram_interface_bank5_addr;
assign soc_netsoc_sdram_interface_bank5_lock = soc_netsoc_sdram_bankmachine5_req_lock;
assign soc_netsoc_sdram_interface_bank5_wdata_ready = soc_netsoc_sdram_bankmachine5_req_wdata_ready;
assign soc_netsoc_sdram_interface_bank5_rdata_valid = soc_netsoc_sdram_bankmachine5_req_rdata_valid;
assign soc_netsoc_sdram_bankmachine6_req_valid = soc_netsoc_sdram_interface_bank6_valid;
assign soc_netsoc_sdram_interface_bank6_ready = soc_netsoc_sdram_bankmachine6_req_ready;
assign soc_netsoc_sdram_bankmachine6_req_we = soc_netsoc_sdram_interface_bank6_we;
assign soc_netsoc_sdram_bankmachine6_req_addr = soc_netsoc_sdram_interface_bank6_addr;
assign soc_netsoc_sdram_interface_bank6_lock = soc_netsoc_sdram_bankmachine6_req_lock;
assign soc_netsoc_sdram_interface_bank6_wdata_ready = soc_netsoc_sdram_bankmachine6_req_wdata_ready;
assign soc_netsoc_sdram_interface_bank6_rdata_valid = soc_netsoc_sdram_bankmachine6_req_rdata_valid;
assign soc_netsoc_sdram_bankmachine7_req_valid = soc_netsoc_sdram_interface_bank7_valid;
assign soc_netsoc_sdram_interface_bank7_ready = soc_netsoc_sdram_bankmachine7_req_ready;
assign soc_netsoc_sdram_bankmachine7_req_we = soc_netsoc_sdram_interface_bank7_we;
assign soc_netsoc_sdram_bankmachine7_req_addr = soc_netsoc_sdram_interface_bank7_addr;
assign soc_netsoc_sdram_interface_bank7_lock = soc_netsoc_sdram_bankmachine7_req_lock;
assign soc_netsoc_sdram_interface_bank7_wdata_ready = soc_netsoc_sdram_bankmachine7_req_wdata_ready;
assign soc_netsoc_sdram_interface_bank7_rdata_valid = soc_netsoc_sdram_bankmachine7_req_rdata_valid;
assign soc_netsoc_sdram_timer_wait = (~soc_netsoc_sdram_timer_done0);
assign soc_netsoc_sdram_postponer_req_i = soc_netsoc_sdram_timer_done0;
assign soc_netsoc_sdram_wants_refresh = soc_netsoc_sdram_postponer_req_o;
assign soc_netsoc_sdram_wants_zqcs = soc_netsoc_sdram_zqcs_timer_done0;
assign soc_netsoc_sdram_zqcs_timer_wait = (~soc_netsoc_sdram_zqcs_executer_done);
assign soc_netsoc_sdram_timer_done1 = (soc_netsoc_sdram_timer_count1 == 1'd0);
assign soc_netsoc_sdram_timer_done0 = soc_netsoc_sdram_timer_done1;
assign soc_netsoc_sdram_timer_count0 = soc_netsoc_sdram_timer_count1;
assign soc_netsoc_sdram_sequencer_start1 = (soc_netsoc_sdram_sequencer_start0 | (soc_netsoc_sdram_sequencer_count != 1'd0));
assign soc_netsoc_sdram_sequencer_done0 = (soc_netsoc_sdram_sequencer_done1 & (soc_netsoc_sdram_sequencer_count == 1'd0));
assign soc_netsoc_sdram_zqcs_timer_done1 = (soc_netsoc_sdram_zqcs_timer_count1 == 1'd0);
assign soc_netsoc_sdram_zqcs_timer_done0 = soc_netsoc_sdram_zqcs_timer_done1;
assign soc_netsoc_sdram_zqcs_timer_count0 = soc_netsoc_sdram_zqcs_timer_count1;
always @(*) begin
soc_netsoc_sdram_cmd_valid <= 1'd0;
soc_netsoc_sdram_zqcs_executer_start <= 1'd0;
soc_netsoc_sdram_cmd_last <= 1'd0;
soc_netsoc_sdram_sequencer_start0 <= 1'd0;
vns_refresher_next_state <= 2'd0;
vns_refresher_next_state <= vns_refresher_state;
case (vns_refresher_state)
1'd1: begin
soc_netsoc_sdram_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_cmd_ready) begin
soc_netsoc_sdram_sequencer_start0 <= 1'd1;
vns_refresher_next_state <= 2'd2;
end
end
2'd2: begin
soc_netsoc_sdram_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_sequencer_done0) begin
if (soc_netsoc_sdram_wants_zqcs) begin
soc_netsoc_sdram_zqcs_executer_start <= 1'd1;
vns_refresher_next_state <= 2'd3;
end else begin
soc_netsoc_sdram_cmd_valid <= 1'd0;
soc_netsoc_sdram_cmd_last <= 1'd1;
vns_refresher_next_state <= 1'd0;
end
end
end
2'd3: begin
soc_netsoc_sdram_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_zqcs_executer_done) begin
soc_netsoc_sdram_cmd_valid <= 1'd0;
soc_netsoc_sdram_cmd_last <= 1'd1;
vns_refresher_next_state <= 1'd0;
end
end
default: begin
if (1'd1) begin
if (soc_netsoc_sdram_wants_refresh) begin
vns_refresher_next_state <= 1'd1;
end
end
end
endcase
end
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine0_req_valid;
assign soc_netsoc_sdram_bankmachine0_req_ready = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine0_req_we;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine0_req_addr;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_ready;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine0_req_wdata_ready | soc_netsoc_sdram_bankmachine0_req_rdata_valid);
assign soc_netsoc_sdram_bankmachine0_req_lock = (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine0_cmd_buffer_source_valid);
assign soc_netsoc_sdram_bankmachine0_row_hit = (soc_netsoc_sdram_bankmachine0_row == soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
assign soc_netsoc_sdram_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
soc_netsoc_sdram_bankmachine0_cmd_payload_a <= 14'd0;
if (soc_netsoc_sdram_bankmachine0_row_col_n_addr_sel) begin
soc_netsoc_sdram_bankmachine0_cmd_payload_a <= soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_netsoc_sdram_bankmachine0_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine0_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_netsoc_sdram_bankmachine0_twtpcon_valid = ((soc_netsoc_sdram_bankmachine0_cmd_valid & soc_netsoc_sdram_bankmachine0_cmd_ready) & soc_netsoc_sdram_bankmachine0_cmd_payload_is_write);
assign soc_netsoc_sdram_bankmachine0_trccon_valid = ((soc_netsoc_sdram_bankmachine0_cmd_valid & soc_netsoc_sdram_bankmachine0_cmd_ready) & soc_netsoc_sdram_bankmachine0_row_open);
assign soc_netsoc_sdram_bankmachine0_trascon_valid = ((soc_netsoc_sdram_bankmachine0_cmd_valid & soc_netsoc_sdram_bankmachine0_cmd_ready) & soc_netsoc_sdram_bankmachine0_row_open);
always @(*) begin
soc_netsoc_sdram_bankmachine0_auto_precharge <= 1'd0;
if ((soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine0_cmd_buffer_source_valid)) begin
if ((soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
soc_netsoc_sdram_bankmachine0_auto_precharge <= (soc_netsoc_sdram_bankmachine0_row_close == 1'd0);
end
end
end
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin
soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_produce;
end
end
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_replace));
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_consume;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8);
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine0_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine0_cmd_buffer_valid_n));
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine0_cmd_buffer_pipe_ce;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine0_cmd_buffer_valid_n;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine0_cmd_buffer_valid_n);
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine0_cmd_buffer_first_n;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine0_cmd_buffer_last_n;
always @(*) begin
soc_netsoc_sdram_bankmachine0_req_wdata_ready <= 1'd0;
soc_netsoc_sdram_bankmachine0_row_open <= 1'd0;
soc_netsoc_sdram_bankmachine0_req_rdata_valid <= 1'd0;
soc_netsoc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
soc_netsoc_sdram_bankmachine0_refresh_gnt <= 1'd0;
soc_netsoc_sdram_bankmachine0_cmd_valid <= 1'd0;
soc_netsoc_sdram_bankmachine0_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_bankmachine0_cmd_payload_ras <= 1'd0;
soc_netsoc_sdram_bankmachine0_cmd_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
vns_bankmachine0_next_state <= 3'd0;
soc_netsoc_sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
soc_netsoc_sdram_bankmachine0_row_close <= 1'd0;
soc_netsoc_sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
vns_bankmachine0_next_state <= vns_bankmachine0_state;
case (vns_bankmachine0_state)
1'd1: begin
if ((soc_netsoc_sdram_bankmachine0_twtpcon_ready & soc_netsoc_sdram_bankmachine0_trascon_ready)) begin
soc_netsoc_sdram_bankmachine0_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine0_cmd_ready) begin
vns_bankmachine0_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
soc_netsoc_sdram_bankmachine0_cmd_payload_we <= 1'd1;
soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
end
soc_netsoc_sdram_bankmachine0_row_close <= 1'd1;
end
2'd2: begin
if ((soc_netsoc_sdram_bankmachine0_twtpcon_ready & soc_netsoc_sdram_bankmachine0_trascon_ready)) begin
vns_bankmachine0_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine0_row_close <= 1'd1;
end
2'd3: begin
if (soc_netsoc_sdram_bankmachine0_trccon_ready) begin
soc_netsoc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
soc_netsoc_sdram_bankmachine0_row_open <= 1'd1;
soc_netsoc_sdram_bankmachine0_cmd_valid <= 1'd1;
soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
if (soc_netsoc_sdram_bankmachine0_cmd_ready) begin
vns_bankmachine0_next_state <= 3'd6;
end
soc_netsoc_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (soc_netsoc_sdram_bankmachine0_twtpcon_ready) begin
soc_netsoc_sdram_bankmachine0_refresh_gnt <= 1'd1;
end
soc_netsoc_sdram_bankmachine0_row_close <= 1'd1;
soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
if ((~soc_netsoc_sdram_bankmachine0_refresh_req)) begin
vns_bankmachine0_next_state <= 1'd0;
end
end
3'd5: begin
vns_bankmachine0_next_state <= 2'd3;
end
3'd6: begin
vns_bankmachine0_next_state <= 1'd0;
end
default: begin
if (soc_netsoc_sdram_bankmachine0_refresh_req) begin
vns_bankmachine0_next_state <= 3'd4;
end else begin
if (soc_netsoc_sdram_bankmachine0_cmd_buffer_source_valid) begin
if (soc_netsoc_sdram_bankmachine0_row_opened) begin
if (soc_netsoc_sdram_bankmachine0_row_hit) begin
soc_netsoc_sdram_bankmachine0_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
soc_netsoc_sdram_bankmachine0_req_wdata_ready <= soc_netsoc_sdram_bankmachine0_cmd_ready;
soc_netsoc_sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
soc_netsoc_sdram_bankmachine0_cmd_payload_we <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine0_req_rdata_valid <= soc_netsoc_sdram_bankmachine0_cmd_ready;
soc_netsoc_sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
end
soc_netsoc_sdram_bankmachine0_cmd_payload_cas <= 1'd1;
if ((soc_netsoc_sdram_bankmachine0_cmd_ready & soc_netsoc_sdram_bankmachine0_auto_precharge)) begin
vns_bankmachine0_next_state <= 2'd2;
end
end else begin
vns_bankmachine0_next_state <= 1'd1;
end
end else begin
vns_bankmachine0_next_state <= 2'd3;
end
end
end
end
endcase
end
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine1_req_valid;
assign soc_netsoc_sdram_bankmachine1_req_ready = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine1_req_we;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine1_req_addr;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_ready;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine1_req_wdata_ready | soc_netsoc_sdram_bankmachine1_req_rdata_valid);
assign soc_netsoc_sdram_bankmachine1_req_lock = (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine1_cmd_buffer_source_valid);
assign soc_netsoc_sdram_bankmachine1_row_hit = (soc_netsoc_sdram_bankmachine1_row == soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
assign soc_netsoc_sdram_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
soc_netsoc_sdram_bankmachine1_cmd_payload_a <= 14'd0;
if (soc_netsoc_sdram_bankmachine1_row_col_n_addr_sel) begin
soc_netsoc_sdram_bankmachine1_cmd_payload_a <= soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_netsoc_sdram_bankmachine1_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine1_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_netsoc_sdram_bankmachine1_twtpcon_valid = ((soc_netsoc_sdram_bankmachine1_cmd_valid & soc_netsoc_sdram_bankmachine1_cmd_ready) & soc_netsoc_sdram_bankmachine1_cmd_payload_is_write);
assign soc_netsoc_sdram_bankmachine1_trccon_valid = ((soc_netsoc_sdram_bankmachine1_cmd_valid & soc_netsoc_sdram_bankmachine1_cmd_ready) & soc_netsoc_sdram_bankmachine1_row_open);
assign soc_netsoc_sdram_bankmachine1_trascon_valid = ((soc_netsoc_sdram_bankmachine1_cmd_valid & soc_netsoc_sdram_bankmachine1_cmd_ready) & soc_netsoc_sdram_bankmachine1_row_open);
always @(*) begin
soc_netsoc_sdram_bankmachine1_auto_precharge <= 1'd0;
if ((soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine1_cmd_buffer_source_valid)) begin
if ((soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
soc_netsoc_sdram_bankmachine1_auto_precharge <= (soc_netsoc_sdram_bankmachine1_row_close == 1'd0);
end
end
end
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin
soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_produce;
end
end
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_replace));
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_consume;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8);
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine1_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine1_cmd_buffer_valid_n));
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine1_cmd_buffer_pipe_ce;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine1_cmd_buffer_valid_n;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine1_cmd_buffer_valid_n);
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine1_cmd_buffer_first_n;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine1_cmd_buffer_last_n;
always @(*) begin
soc_netsoc_sdram_bankmachine1_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_bankmachine1_cmd_payload_ras <= 1'd0;
soc_netsoc_sdram_bankmachine1_cmd_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
soc_netsoc_sdram_bankmachine1_row_open <= 1'd0;
soc_netsoc_sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
soc_netsoc_sdram_bankmachine1_row_close <= 1'd0;
soc_netsoc_sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
soc_netsoc_sdram_bankmachine1_req_wdata_ready <= 1'd0;
soc_netsoc_sdram_bankmachine1_req_rdata_valid <= 1'd0;
soc_netsoc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
soc_netsoc_sdram_bankmachine1_refresh_gnt <= 1'd0;
soc_netsoc_sdram_bankmachine1_cmd_valid <= 1'd0;
vns_bankmachine1_next_state <= 3'd0;
vns_bankmachine1_next_state <= vns_bankmachine1_state;
case (vns_bankmachine1_state)
1'd1: begin
if ((soc_netsoc_sdram_bankmachine1_twtpcon_ready & soc_netsoc_sdram_bankmachine1_trascon_ready)) begin
soc_netsoc_sdram_bankmachine1_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine1_cmd_ready) begin
vns_bankmachine1_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
soc_netsoc_sdram_bankmachine1_cmd_payload_we <= 1'd1;
soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
soc_netsoc_sdram_bankmachine1_row_close <= 1'd1;
end
2'd2: begin
if ((soc_netsoc_sdram_bankmachine1_twtpcon_ready & soc_netsoc_sdram_bankmachine1_trascon_ready)) begin
vns_bankmachine1_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine1_row_close <= 1'd1;
end
2'd3: begin
if (soc_netsoc_sdram_bankmachine1_trccon_ready) begin
soc_netsoc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
soc_netsoc_sdram_bankmachine1_row_open <= 1'd1;
soc_netsoc_sdram_bankmachine1_cmd_valid <= 1'd1;
soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
if (soc_netsoc_sdram_bankmachine1_cmd_ready) begin
vns_bankmachine1_next_state <= 3'd6;
end
soc_netsoc_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (soc_netsoc_sdram_bankmachine1_twtpcon_ready) begin
soc_netsoc_sdram_bankmachine1_refresh_gnt <= 1'd1;
end
soc_netsoc_sdram_bankmachine1_row_close <= 1'd1;
soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
if ((~soc_netsoc_sdram_bankmachine1_refresh_req)) begin
vns_bankmachine1_next_state <= 1'd0;
end
end
3'd5: begin
vns_bankmachine1_next_state <= 2'd3;
end
3'd6: begin
vns_bankmachine1_next_state <= 1'd0;
end
default: begin
if (soc_netsoc_sdram_bankmachine1_refresh_req) begin
vns_bankmachine1_next_state <= 3'd4;
end else begin
if (soc_netsoc_sdram_bankmachine1_cmd_buffer_source_valid) begin
if (soc_netsoc_sdram_bankmachine1_row_opened) begin
if (soc_netsoc_sdram_bankmachine1_row_hit) begin
soc_netsoc_sdram_bankmachine1_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
soc_netsoc_sdram_bankmachine1_req_wdata_ready <= soc_netsoc_sdram_bankmachine1_cmd_ready;
soc_netsoc_sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
soc_netsoc_sdram_bankmachine1_cmd_payload_we <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine1_req_rdata_valid <= soc_netsoc_sdram_bankmachine1_cmd_ready;
soc_netsoc_sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
end
soc_netsoc_sdram_bankmachine1_cmd_payload_cas <= 1'd1;
if ((soc_netsoc_sdram_bankmachine1_cmd_ready & soc_netsoc_sdram_bankmachine1_auto_precharge)) begin
vns_bankmachine1_next_state <= 2'd2;
end
end else begin
vns_bankmachine1_next_state <= 1'd1;
end
end else begin
vns_bankmachine1_next_state <= 2'd3;
end
end
end
end
endcase
end
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine2_req_valid;
assign soc_netsoc_sdram_bankmachine2_req_ready = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine2_req_we;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine2_req_addr;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_ready;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine2_req_wdata_ready | soc_netsoc_sdram_bankmachine2_req_rdata_valid);
assign soc_netsoc_sdram_bankmachine2_req_lock = (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine2_cmd_buffer_source_valid);
assign soc_netsoc_sdram_bankmachine2_row_hit = (soc_netsoc_sdram_bankmachine2_row == soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
assign soc_netsoc_sdram_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
soc_netsoc_sdram_bankmachine2_cmd_payload_a <= 14'd0;
if (soc_netsoc_sdram_bankmachine2_row_col_n_addr_sel) begin
soc_netsoc_sdram_bankmachine2_cmd_payload_a <= soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_netsoc_sdram_bankmachine2_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine2_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_netsoc_sdram_bankmachine2_twtpcon_valid = ((soc_netsoc_sdram_bankmachine2_cmd_valid & soc_netsoc_sdram_bankmachine2_cmd_ready) & soc_netsoc_sdram_bankmachine2_cmd_payload_is_write);
assign soc_netsoc_sdram_bankmachine2_trccon_valid = ((soc_netsoc_sdram_bankmachine2_cmd_valid & soc_netsoc_sdram_bankmachine2_cmd_ready) & soc_netsoc_sdram_bankmachine2_row_open);
assign soc_netsoc_sdram_bankmachine2_trascon_valid = ((soc_netsoc_sdram_bankmachine2_cmd_valid & soc_netsoc_sdram_bankmachine2_cmd_ready) & soc_netsoc_sdram_bankmachine2_row_open);
always @(*) begin
soc_netsoc_sdram_bankmachine2_auto_precharge <= 1'd0;
if ((soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine2_cmd_buffer_source_valid)) begin
if ((soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
soc_netsoc_sdram_bankmachine2_auto_precharge <= (soc_netsoc_sdram_bankmachine2_row_close == 1'd0);
end
end
end
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin
soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_produce;
end
end
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_replace));
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_consume;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8);
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine2_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine2_cmd_buffer_valid_n));
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine2_cmd_buffer_pipe_ce;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine2_cmd_buffer_valid_n;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine2_cmd_buffer_valid_n);
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine2_cmd_buffer_first_n;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine2_cmd_buffer_last_n;
always @(*) begin
soc_netsoc_sdram_bankmachine2_cmd_valid <= 1'd0;
soc_netsoc_sdram_bankmachine2_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_bankmachine2_cmd_payload_ras <= 1'd0;
soc_netsoc_sdram_bankmachine2_cmd_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
vns_bankmachine2_next_state <= 3'd0;
soc_netsoc_sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
soc_netsoc_sdram_bankmachine2_row_close <= 1'd0;
soc_netsoc_sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
soc_netsoc_sdram_bankmachine2_row_open <= 1'd0;
soc_netsoc_sdram_bankmachine2_req_wdata_ready <= 1'd0;
soc_netsoc_sdram_bankmachine2_req_rdata_valid <= 1'd0;
soc_netsoc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
soc_netsoc_sdram_bankmachine2_refresh_gnt <= 1'd0;
vns_bankmachine2_next_state <= vns_bankmachine2_state;
case (vns_bankmachine2_state)
1'd1: begin
if ((soc_netsoc_sdram_bankmachine2_twtpcon_ready & soc_netsoc_sdram_bankmachine2_trascon_ready)) begin
soc_netsoc_sdram_bankmachine2_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine2_cmd_ready) begin
vns_bankmachine2_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
soc_netsoc_sdram_bankmachine2_cmd_payload_we <= 1'd1;
soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
end
soc_netsoc_sdram_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
if ((soc_netsoc_sdram_bankmachine2_twtpcon_ready & soc_netsoc_sdram_bankmachine2_trascon_ready)) begin
vns_bankmachine2_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
if (soc_netsoc_sdram_bankmachine2_trccon_ready) begin
soc_netsoc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
soc_netsoc_sdram_bankmachine2_row_open <= 1'd1;
soc_netsoc_sdram_bankmachine2_cmd_valid <= 1'd1;
soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
if (soc_netsoc_sdram_bankmachine2_cmd_ready) begin
vns_bankmachine2_next_state <= 3'd6;
end
soc_netsoc_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (soc_netsoc_sdram_bankmachine2_twtpcon_ready) begin
soc_netsoc_sdram_bankmachine2_refresh_gnt <= 1'd1;
end
soc_netsoc_sdram_bankmachine2_row_close <= 1'd1;
soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
if ((~soc_netsoc_sdram_bankmachine2_refresh_req)) begin
vns_bankmachine2_next_state <= 1'd0;
end
end
3'd5: begin
vns_bankmachine2_next_state <= 2'd3;
end
3'd6: begin
vns_bankmachine2_next_state <= 1'd0;
end
default: begin
if (soc_netsoc_sdram_bankmachine2_refresh_req) begin
vns_bankmachine2_next_state <= 3'd4;
end else begin
if (soc_netsoc_sdram_bankmachine2_cmd_buffer_source_valid) begin
if (soc_netsoc_sdram_bankmachine2_row_opened) begin
if (soc_netsoc_sdram_bankmachine2_row_hit) begin
soc_netsoc_sdram_bankmachine2_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
soc_netsoc_sdram_bankmachine2_req_wdata_ready <= soc_netsoc_sdram_bankmachine2_cmd_ready;
soc_netsoc_sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
soc_netsoc_sdram_bankmachine2_cmd_payload_we <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine2_req_rdata_valid <= soc_netsoc_sdram_bankmachine2_cmd_ready;
soc_netsoc_sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
end
soc_netsoc_sdram_bankmachine2_cmd_payload_cas <= 1'd1;
if ((soc_netsoc_sdram_bankmachine2_cmd_ready & soc_netsoc_sdram_bankmachine2_auto_precharge)) begin
vns_bankmachine2_next_state <= 2'd2;
end
end else begin
vns_bankmachine2_next_state <= 1'd1;
end
end else begin
vns_bankmachine2_next_state <= 2'd3;
end
end
end
end
endcase
end
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine3_req_valid;
assign soc_netsoc_sdram_bankmachine3_req_ready = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine3_req_we;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine3_req_addr;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_ready;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine3_req_wdata_ready | soc_netsoc_sdram_bankmachine3_req_rdata_valid);
assign soc_netsoc_sdram_bankmachine3_req_lock = (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine3_cmd_buffer_source_valid);
assign soc_netsoc_sdram_bankmachine3_row_hit = (soc_netsoc_sdram_bankmachine3_row == soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
assign soc_netsoc_sdram_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
soc_netsoc_sdram_bankmachine3_cmd_payload_a <= 14'd0;
if (soc_netsoc_sdram_bankmachine3_row_col_n_addr_sel) begin
soc_netsoc_sdram_bankmachine3_cmd_payload_a <= soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_netsoc_sdram_bankmachine3_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine3_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_netsoc_sdram_bankmachine3_twtpcon_valid = ((soc_netsoc_sdram_bankmachine3_cmd_valid & soc_netsoc_sdram_bankmachine3_cmd_ready) & soc_netsoc_sdram_bankmachine3_cmd_payload_is_write);
assign soc_netsoc_sdram_bankmachine3_trccon_valid = ((soc_netsoc_sdram_bankmachine3_cmd_valid & soc_netsoc_sdram_bankmachine3_cmd_ready) & soc_netsoc_sdram_bankmachine3_row_open);
assign soc_netsoc_sdram_bankmachine3_trascon_valid = ((soc_netsoc_sdram_bankmachine3_cmd_valid & soc_netsoc_sdram_bankmachine3_cmd_ready) & soc_netsoc_sdram_bankmachine3_row_open);
always @(*) begin
soc_netsoc_sdram_bankmachine3_auto_precharge <= 1'd0;
if ((soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine3_cmd_buffer_source_valid)) begin
if ((soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
soc_netsoc_sdram_bankmachine3_auto_precharge <= (soc_netsoc_sdram_bankmachine3_row_close == 1'd0);
end
end
end
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin
soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_produce;
end
end
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_replace));
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_consume;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8);
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine3_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine3_cmd_buffer_valid_n));
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine3_cmd_buffer_pipe_ce;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine3_cmd_buffer_valid_n;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine3_cmd_buffer_valid_n);
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine3_cmd_buffer_first_n;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine3_cmd_buffer_last_n;
always @(*) begin
soc_netsoc_sdram_bankmachine3_row_open <= 1'd0;
soc_netsoc_sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
soc_netsoc_sdram_bankmachine3_row_close <= 1'd0;
soc_netsoc_sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
soc_netsoc_sdram_bankmachine3_req_wdata_ready <= 1'd0;
soc_netsoc_sdram_bankmachine3_req_rdata_valid <= 1'd0;
soc_netsoc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
soc_netsoc_sdram_bankmachine3_refresh_gnt <= 1'd0;
soc_netsoc_sdram_bankmachine3_cmd_valid <= 1'd0;
vns_bankmachine3_next_state <= 3'd0;
soc_netsoc_sdram_bankmachine3_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_bankmachine3_cmd_payload_ras <= 1'd0;
soc_netsoc_sdram_bankmachine3_cmd_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
vns_bankmachine3_next_state <= vns_bankmachine3_state;
case (vns_bankmachine3_state)
1'd1: begin
if ((soc_netsoc_sdram_bankmachine3_twtpcon_ready & soc_netsoc_sdram_bankmachine3_trascon_ready)) begin
soc_netsoc_sdram_bankmachine3_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine3_cmd_ready) begin
vns_bankmachine3_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
soc_netsoc_sdram_bankmachine3_cmd_payload_we <= 1'd1;
soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
end
soc_netsoc_sdram_bankmachine3_row_close <= 1'd1;
end
2'd2: begin
if ((soc_netsoc_sdram_bankmachine3_twtpcon_ready & soc_netsoc_sdram_bankmachine3_trascon_ready)) begin
vns_bankmachine3_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine3_row_close <= 1'd1;
end
2'd3: begin
if (soc_netsoc_sdram_bankmachine3_trccon_ready) begin
soc_netsoc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
soc_netsoc_sdram_bankmachine3_row_open <= 1'd1;
soc_netsoc_sdram_bankmachine3_cmd_valid <= 1'd1;
soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
if (soc_netsoc_sdram_bankmachine3_cmd_ready) begin
vns_bankmachine3_next_state <= 3'd6;
end
soc_netsoc_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (soc_netsoc_sdram_bankmachine3_twtpcon_ready) begin
soc_netsoc_sdram_bankmachine3_refresh_gnt <= 1'd1;
end
soc_netsoc_sdram_bankmachine3_row_close <= 1'd1;
soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
if ((~soc_netsoc_sdram_bankmachine3_refresh_req)) begin
vns_bankmachine3_next_state <= 1'd0;
end
end
3'd5: begin
vns_bankmachine3_next_state <= 2'd3;
end
3'd6: begin
vns_bankmachine3_next_state <= 1'd0;
end
default: begin
if (soc_netsoc_sdram_bankmachine3_refresh_req) begin
vns_bankmachine3_next_state <= 3'd4;
end else begin
if (soc_netsoc_sdram_bankmachine3_cmd_buffer_source_valid) begin
if (soc_netsoc_sdram_bankmachine3_row_opened) begin
if (soc_netsoc_sdram_bankmachine3_row_hit) begin
soc_netsoc_sdram_bankmachine3_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
soc_netsoc_sdram_bankmachine3_req_wdata_ready <= soc_netsoc_sdram_bankmachine3_cmd_ready;
soc_netsoc_sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
soc_netsoc_sdram_bankmachine3_cmd_payload_we <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine3_req_rdata_valid <= soc_netsoc_sdram_bankmachine3_cmd_ready;
soc_netsoc_sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
end
soc_netsoc_sdram_bankmachine3_cmd_payload_cas <= 1'd1;
if ((soc_netsoc_sdram_bankmachine3_cmd_ready & soc_netsoc_sdram_bankmachine3_auto_precharge)) begin
vns_bankmachine3_next_state <= 2'd2;
end
end else begin
vns_bankmachine3_next_state <= 1'd1;
end
end else begin
vns_bankmachine3_next_state <= 2'd3;
end
end
end
end
endcase
end
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine4_req_valid;
assign soc_netsoc_sdram_bankmachine4_req_ready = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine4_req_we;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine4_req_addr;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_ready;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine4_req_wdata_ready | soc_netsoc_sdram_bankmachine4_req_rdata_valid);
assign soc_netsoc_sdram_bankmachine4_req_lock = (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine4_cmd_buffer_source_valid);
assign soc_netsoc_sdram_bankmachine4_row_hit = (soc_netsoc_sdram_bankmachine4_row == soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
assign soc_netsoc_sdram_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
soc_netsoc_sdram_bankmachine4_cmd_payload_a <= 14'd0;
if (soc_netsoc_sdram_bankmachine4_row_col_n_addr_sel) begin
soc_netsoc_sdram_bankmachine4_cmd_payload_a <= soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_netsoc_sdram_bankmachine4_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine4_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_netsoc_sdram_bankmachine4_twtpcon_valid = ((soc_netsoc_sdram_bankmachine4_cmd_valid & soc_netsoc_sdram_bankmachine4_cmd_ready) & soc_netsoc_sdram_bankmachine4_cmd_payload_is_write);
assign soc_netsoc_sdram_bankmachine4_trccon_valid = ((soc_netsoc_sdram_bankmachine4_cmd_valid & soc_netsoc_sdram_bankmachine4_cmd_ready) & soc_netsoc_sdram_bankmachine4_row_open);
assign soc_netsoc_sdram_bankmachine4_trascon_valid = ((soc_netsoc_sdram_bankmachine4_cmd_valid & soc_netsoc_sdram_bankmachine4_cmd_ready) & soc_netsoc_sdram_bankmachine4_row_open);
always @(*) begin
soc_netsoc_sdram_bankmachine4_auto_precharge <= 1'd0;
if ((soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine4_cmd_buffer_source_valid)) begin
if ((soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
soc_netsoc_sdram_bankmachine4_auto_precharge <= (soc_netsoc_sdram_bankmachine4_row_close == 1'd0);
end
end
end
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin
soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_produce;
end
end
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_replace));
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_consume;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level != 4'd8);
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine4_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine4_cmd_buffer_valid_n));
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine4_cmd_buffer_pipe_ce;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine4_cmd_buffer_valid_n;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine4_cmd_buffer_valid_n);
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine4_cmd_buffer_first_n;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine4_cmd_buffer_last_n;
always @(*) begin
soc_netsoc_sdram_bankmachine4_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_bankmachine4_cmd_payload_ras <= 1'd0;
soc_netsoc_sdram_bankmachine4_cmd_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0;
vns_bankmachine4_next_state <= 3'd0;
soc_netsoc_sdram_bankmachine4_cmd_payload_is_read <= 1'd0;
soc_netsoc_sdram_bankmachine4_row_close <= 1'd0;
soc_netsoc_sdram_bankmachine4_cmd_payload_is_write <= 1'd0;
soc_netsoc_sdram_bankmachine4_row_open <= 1'd0;
soc_netsoc_sdram_bankmachine4_req_wdata_ready <= 1'd0;
soc_netsoc_sdram_bankmachine4_req_rdata_valid <= 1'd0;
soc_netsoc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0;
soc_netsoc_sdram_bankmachine4_refresh_gnt <= 1'd0;
soc_netsoc_sdram_bankmachine4_cmd_valid <= 1'd0;
vns_bankmachine4_next_state <= vns_bankmachine4_state;
case (vns_bankmachine4_state)
1'd1: begin
if ((soc_netsoc_sdram_bankmachine4_twtpcon_ready & soc_netsoc_sdram_bankmachine4_trascon_ready)) begin
soc_netsoc_sdram_bankmachine4_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine4_cmd_ready) begin
vns_bankmachine4_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
soc_netsoc_sdram_bankmachine4_cmd_payload_we <= 1'd1;
soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
end
soc_netsoc_sdram_bankmachine4_row_close <= 1'd1;
end
2'd2: begin
if ((soc_netsoc_sdram_bankmachine4_twtpcon_ready & soc_netsoc_sdram_bankmachine4_trascon_ready)) begin
vns_bankmachine4_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine4_row_close <= 1'd1;
end
2'd3: begin
if (soc_netsoc_sdram_bankmachine4_trccon_ready) begin
soc_netsoc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1;
soc_netsoc_sdram_bankmachine4_row_open <= 1'd1;
soc_netsoc_sdram_bankmachine4_cmd_valid <= 1'd1;
soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
if (soc_netsoc_sdram_bankmachine4_cmd_ready) begin
vns_bankmachine4_next_state <= 3'd6;
end
soc_netsoc_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (soc_netsoc_sdram_bankmachine4_twtpcon_ready) begin
soc_netsoc_sdram_bankmachine4_refresh_gnt <= 1'd1;
end
soc_netsoc_sdram_bankmachine4_row_close <= 1'd1;
soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
if ((~soc_netsoc_sdram_bankmachine4_refresh_req)) begin
vns_bankmachine4_next_state <= 1'd0;
end
end
3'd5: begin
vns_bankmachine4_next_state <= 2'd3;
end
3'd6: begin
vns_bankmachine4_next_state <= 1'd0;
end
default: begin
if (soc_netsoc_sdram_bankmachine4_refresh_req) begin
vns_bankmachine4_next_state <= 3'd4;
end else begin
if (soc_netsoc_sdram_bankmachine4_cmd_buffer_source_valid) begin
if (soc_netsoc_sdram_bankmachine4_row_opened) begin
if (soc_netsoc_sdram_bankmachine4_row_hit) begin
soc_netsoc_sdram_bankmachine4_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
soc_netsoc_sdram_bankmachine4_req_wdata_ready <= soc_netsoc_sdram_bankmachine4_cmd_ready;
soc_netsoc_sdram_bankmachine4_cmd_payload_is_write <= 1'd1;
soc_netsoc_sdram_bankmachine4_cmd_payload_we <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine4_req_rdata_valid <= soc_netsoc_sdram_bankmachine4_cmd_ready;
soc_netsoc_sdram_bankmachine4_cmd_payload_is_read <= 1'd1;
end
soc_netsoc_sdram_bankmachine4_cmd_payload_cas <= 1'd1;
if ((soc_netsoc_sdram_bankmachine4_cmd_ready & soc_netsoc_sdram_bankmachine4_auto_precharge)) begin
vns_bankmachine4_next_state <= 2'd2;
end
end else begin
vns_bankmachine4_next_state <= 1'd1;
end
end else begin
vns_bankmachine4_next_state <= 2'd3;
end
end
end
end
endcase
end
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine5_req_valid;
assign soc_netsoc_sdram_bankmachine5_req_ready = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine5_req_we;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine5_req_addr;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_ready;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine5_req_wdata_ready | soc_netsoc_sdram_bankmachine5_req_rdata_valid);
assign soc_netsoc_sdram_bankmachine5_req_lock = (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine5_cmd_buffer_source_valid);
assign soc_netsoc_sdram_bankmachine5_row_hit = (soc_netsoc_sdram_bankmachine5_row == soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
assign soc_netsoc_sdram_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
soc_netsoc_sdram_bankmachine5_cmd_payload_a <= 14'd0;
if (soc_netsoc_sdram_bankmachine5_row_col_n_addr_sel) begin
soc_netsoc_sdram_bankmachine5_cmd_payload_a <= soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_netsoc_sdram_bankmachine5_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine5_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_netsoc_sdram_bankmachine5_twtpcon_valid = ((soc_netsoc_sdram_bankmachine5_cmd_valid & soc_netsoc_sdram_bankmachine5_cmd_ready) & soc_netsoc_sdram_bankmachine5_cmd_payload_is_write);
assign soc_netsoc_sdram_bankmachine5_trccon_valid = ((soc_netsoc_sdram_bankmachine5_cmd_valid & soc_netsoc_sdram_bankmachine5_cmd_ready) & soc_netsoc_sdram_bankmachine5_row_open);
assign soc_netsoc_sdram_bankmachine5_trascon_valid = ((soc_netsoc_sdram_bankmachine5_cmd_valid & soc_netsoc_sdram_bankmachine5_cmd_ready) & soc_netsoc_sdram_bankmachine5_row_open);
always @(*) begin
soc_netsoc_sdram_bankmachine5_auto_precharge <= 1'd0;
if ((soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine5_cmd_buffer_source_valid)) begin
if ((soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
soc_netsoc_sdram_bankmachine5_auto_precharge <= (soc_netsoc_sdram_bankmachine5_row_close == 1'd0);
end
end
end
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin
soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_produce;
end
end
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_replace));
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_consume;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level != 4'd8);
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine5_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine5_cmd_buffer_valid_n));
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine5_cmd_buffer_pipe_ce;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine5_cmd_buffer_valid_n;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine5_cmd_buffer_valid_n);
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine5_cmd_buffer_first_n;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine5_cmd_buffer_last_n;
always @(*) begin
soc_netsoc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0;
soc_netsoc_sdram_bankmachine5_refresh_gnt <= 1'd0;
soc_netsoc_sdram_bankmachine5_cmd_valid <= 1'd0;
vns_bankmachine5_next_state <= 3'd0;
soc_netsoc_sdram_bankmachine5_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_bankmachine5_cmd_payload_ras <= 1'd0;
soc_netsoc_sdram_bankmachine5_cmd_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0;
soc_netsoc_sdram_bankmachine5_row_open <= 1'd0;
soc_netsoc_sdram_bankmachine5_cmd_payload_is_read <= 1'd0;
soc_netsoc_sdram_bankmachine5_row_close <= 1'd0;
soc_netsoc_sdram_bankmachine5_cmd_payload_is_write <= 1'd0;
soc_netsoc_sdram_bankmachine5_req_wdata_ready <= 1'd0;
soc_netsoc_sdram_bankmachine5_req_rdata_valid <= 1'd0;
vns_bankmachine5_next_state <= vns_bankmachine5_state;
case (vns_bankmachine5_state)
1'd1: begin
if ((soc_netsoc_sdram_bankmachine5_twtpcon_ready & soc_netsoc_sdram_bankmachine5_trascon_ready)) begin
soc_netsoc_sdram_bankmachine5_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine5_cmd_ready) begin
vns_bankmachine5_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
soc_netsoc_sdram_bankmachine5_cmd_payload_we <= 1'd1;
soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
end
soc_netsoc_sdram_bankmachine5_row_close <= 1'd1;
end
2'd2: begin
if ((soc_netsoc_sdram_bankmachine5_twtpcon_ready & soc_netsoc_sdram_bankmachine5_trascon_ready)) begin
vns_bankmachine5_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine5_row_close <= 1'd1;
end
2'd3: begin
if (soc_netsoc_sdram_bankmachine5_trccon_ready) begin
soc_netsoc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1;
soc_netsoc_sdram_bankmachine5_row_open <= 1'd1;
soc_netsoc_sdram_bankmachine5_cmd_valid <= 1'd1;
soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
if (soc_netsoc_sdram_bankmachine5_cmd_ready) begin
vns_bankmachine5_next_state <= 3'd6;
end
soc_netsoc_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (soc_netsoc_sdram_bankmachine5_twtpcon_ready) begin
soc_netsoc_sdram_bankmachine5_refresh_gnt <= 1'd1;
end
soc_netsoc_sdram_bankmachine5_row_close <= 1'd1;
soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
if ((~soc_netsoc_sdram_bankmachine5_refresh_req)) begin
vns_bankmachine5_next_state <= 1'd0;
end
end
3'd5: begin
vns_bankmachine5_next_state <= 2'd3;
end
3'd6: begin
vns_bankmachine5_next_state <= 1'd0;
end
default: begin
if (soc_netsoc_sdram_bankmachine5_refresh_req) begin
vns_bankmachine5_next_state <= 3'd4;
end else begin
if (soc_netsoc_sdram_bankmachine5_cmd_buffer_source_valid) begin
if (soc_netsoc_sdram_bankmachine5_row_opened) begin
if (soc_netsoc_sdram_bankmachine5_row_hit) begin
soc_netsoc_sdram_bankmachine5_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
soc_netsoc_sdram_bankmachine5_req_wdata_ready <= soc_netsoc_sdram_bankmachine5_cmd_ready;
soc_netsoc_sdram_bankmachine5_cmd_payload_is_write <= 1'd1;
soc_netsoc_sdram_bankmachine5_cmd_payload_we <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine5_req_rdata_valid <= soc_netsoc_sdram_bankmachine5_cmd_ready;
soc_netsoc_sdram_bankmachine5_cmd_payload_is_read <= 1'd1;
end
soc_netsoc_sdram_bankmachine5_cmd_payload_cas <= 1'd1;
if ((soc_netsoc_sdram_bankmachine5_cmd_ready & soc_netsoc_sdram_bankmachine5_auto_precharge)) begin
vns_bankmachine5_next_state <= 2'd2;
end
end else begin
vns_bankmachine5_next_state <= 1'd1;
end
end else begin
vns_bankmachine5_next_state <= 2'd3;
end
end
end
end
endcase
end
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine6_req_valid;
assign soc_netsoc_sdram_bankmachine6_req_ready = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine6_req_we;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine6_req_addr;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_ready;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine6_req_wdata_ready | soc_netsoc_sdram_bankmachine6_req_rdata_valid);
assign soc_netsoc_sdram_bankmachine6_req_lock = (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine6_cmd_buffer_source_valid);
assign soc_netsoc_sdram_bankmachine6_row_hit = (soc_netsoc_sdram_bankmachine6_row == soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
assign soc_netsoc_sdram_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
soc_netsoc_sdram_bankmachine6_cmd_payload_a <= 14'd0;
if (soc_netsoc_sdram_bankmachine6_row_col_n_addr_sel) begin
soc_netsoc_sdram_bankmachine6_cmd_payload_a <= soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_netsoc_sdram_bankmachine6_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine6_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_netsoc_sdram_bankmachine6_twtpcon_valid = ((soc_netsoc_sdram_bankmachine6_cmd_valid & soc_netsoc_sdram_bankmachine6_cmd_ready) & soc_netsoc_sdram_bankmachine6_cmd_payload_is_write);
assign soc_netsoc_sdram_bankmachine6_trccon_valid = ((soc_netsoc_sdram_bankmachine6_cmd_valid & soc_netsoc_sdram_bankmachine6_cmd_ready) & soc_netsoc_sdram_bankmachine6_row_open);
assign soc_netsoc_sdram_bankmachine6_trascon_valid = ((soc_netsoc_sdram_bankmachine6_cmd_valid & soc_netsoc_sdram_bankmachine6_cmd_ready) & soc_netsoc_sdram_bankmachine6_row_open);
always @(*) begin
soc_netsoc_sdram_bankmachine6_auto_precharge <= 1'd0;
if ((soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine6_cmd_buffer_source_valid)) begin
if ((soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
soc_netsoc_sdram_bankmachine6_auto_precharge <= (soc_netsoc_sdram_bankmachine6_row_close == 1'd0);
end
end
end
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin
soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_produce;
end
end
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_replace));
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_consume;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level != 4'd8);
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine6_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine6_cmd_buffer_valid_n));
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine6_cmd_buffer_pipe_ce;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine6_cmd_buffer_valid_n;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine6_cmd_buffer_valid_n);
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine6_cmd_buffer_first_n;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine6_cmd_buffer_last_n;
always @(*) begin
soc_netsoc_sdram_bankmachine6_cmd_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0;
vns_bankmachine6_next_state <= 3'd0;
soc_netsoc_sdram_bankmachine6_cmd_payload_is_read <= 1'd0;
soc_netsoc_sdram_bankmachine6_row_close <= 1'd0;
soc_netsoc_sdram_bankmachine6_cmd_payload_is_write <= 1'd0;
soc_netsoc_sdram_bankmachine6_row_open <= 1'd0;
soc_netsoc_sdram_bankmachine6_req_wdata_ready <= 1'd0;
soc_netsoc_sdram_bankmachine6_req_rdata_valid <= 1'd0;
soc_netsoc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0;
soc_netsoc_sdram_bankmachine6_refresh_gnt <= 1'd0;
soc_netsoc_sdram_bankmachine6_cmd_valid <= 1'd0;
soc_netsoc_sdram_bankmachine6_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_bankmachine6_cmd_payload_ras <= 1'd0;
vns_bankmachine6_next_state <= vns_bankmachine6_state;
case (vns_bankmachine6_state)
1'd1: begin
if ((soc_netsoc_sdram_bankmachine6_twtpcon_ready & soc_netsoc_sdram_bankmachine6_trascon_ready)) begin
soc_netsoc_sdram_bankmachine6_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine6_cmd_ready) begin
vns_bankmachine6_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
soc_netsoc_sdram_bankmachine6_cmd_payload_we <= 1'd1;
soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
end
soc_netsoc_sdram_bankmachine6_row_close <= 1'd1;
end
2'd2: begin
if ((soc_netsoc_sdram_bankmachine6_twtpcon_ready & soc_netsoc_sdram_bankmachine6_trascon_ready)) begin
vns_bankmachine6_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine6_row_close <= 1'd1;
end
2'd3: begin
if (soc_netsoc_sdram_bankmachine6_trccon_ready) begin
soc_netsoc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1;
soc_netsoc_sdram_bankmachine6_row_open <= 1'd1;
soc_netsoc_sdram_bankmachine6_cmd_valid <= 1'd1;
soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
if (soc_netsoc_sdram_bankmachine6_cmd_ready) begin
vns_bankmachine6_next_state <= 3'd6;
end
soc_netsoc_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (soc_netsoc_sdram_bankmachine6_twtpcon_ready) begin
soc_netsoc_sdram_bankmachine6_refresh_gnt <= 1'd1;
end
soc_netsoc_sdram_bankmachine6_row_close <= 1'd1;
soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
if ((~soc_netsoc_sdram_bankmachine6_refresh_req)) begin
vns_bankmachine6_next_state <= 1'd0;
end
end
3'd5: begin
vns_bankmachine6_next_state <= 2'd3;
end
3'd6: begin
vns_bankmachine6_next_state <= 1'd0;
end
default: begin
if (soc_netsoc_sdram_bankmachine6_refresh_req) begin
vns_bankmachine6_next_state <= 3'd4;
end else begin
if (soc_netsoc_sdram_bankmachine6_cmd_buffer_source_valid) begin
if (soc_netsoc_sdram_bankmachine6_row_opened) begin
if (soc_netsoc_sdram_bankmachine6_row_hit) begin
soc_netsoc_sdram_bankmachine6_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
soc_netsoc_sdram_bankmachine6_req_wdata_ready <= soc_netsoc_sdram_bankmachine6_cmd_ready;
soc_netsoc_sdram_bankmachine6_cmd_payload_is_write <= 1'd1;
soc_netsoc_sdram_bankmachine6_cmd_payload_we <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine6_req_rdata_valid <= soc_netsoc_sdram_bankmachine6_cmd_ready;
soc_netsoc_sdram_bankmachine6_cmd_payload_is_read <= 1'd1;
end
soc_netsoc_sdram_bankmachine6_cmd_payload_cas <= 1'd1;
if ((soc_netsoc_sdram_bankmachine6_cmd_ready & soc_netsoc_sdram_bankmachine6_auto_precharge)) begin
vns_bankmachine6_next_state <= 2'd2;
end
end else begin
vns_bankmachine6_next_state <= 1'd1;
end
end else begin
vns_bankmachine6_next_state <= 2'd3;
end
end
end
end
endcase
end
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_netsoc_sdram_bankmachine7_req_valid;
assign soc_netsoc_sdram_bankmachine7_req_ready = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_netsoc_sdram_bankmachine7_req_we;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_netsoc_sdram_bankmachine7_req_addr;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_valid = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_ready;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_first = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_last = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_payload_we = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_payload_addr = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_source_ready = (soc_netsoc_sdram_bankmachine7_req_wdata_ready | soc_netsoc_sdram_bankmachine7_req_rdata_valid);
assign soc_netsoc_sdram_bankmachine7_req_lock = (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | soc_netsoc_sdram_bankmachine7_cmd_buffer_source_valid);
assign soc_netsoc_sdram_bankmachine7_row_hit = (soc_netsoc_sdram_bankmachine7_row == soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
assign soc_netsoc_sdram_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
soc_netsoc_sdram_bankmachine7_cmd_payload_a <= 14'd0;
if (soc_netsoc_sdram_bankmachine7_row_col_n_addr_sel) begin
soc_netsoc_sdram_bankmachine7_cmd_payload_a <= soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7];
end else begin
soc_netsoc_sdram_bankmachine7_cmd_payload_a <= ((soc_netsoc_sdram_bankmachine7_auto_precharge <<< 4'd10) | {soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign soc_netsoc_sdram_bankmachine7_twtpcon_valid = ((soc_netsoc_sdram_bankmachine7_cmd_valid & soc_netsoc_sdram_bankmachine7_cmd_ready) & soc_netsoc_sdram_bankmachine7_cmd_payload_is_write);
assign soc_netsoc_sdram_bankmachine7_trccon_valid = ((soc_netsoc_sdram_bankmachine7_cmd_valid & soc_netsoc_sdram_bankmachine7_cmd_ready) & soc_netsoc_sdram_bankmachine7_row_open);
assign soc_netsoc_sdram_bankmachine7_trascon_valid = ((soc_netsoc_sdram_bankmachine7_cmd_valid & soc_netsoc_sdram_bankmachine7_cmd_ready) & soc_netsoc_sdram_bankmachine7_row_open);
always @(*) begin
soc_netsoc_sdram_bankmachine7_auto_precharge <= 1'd0;
if ((soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & soc_netsoc_sdram_bankmachine7_cmd_buffer_source_valid)) begin
if ((soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
soc_netsoc_sdram_bankmachine7_auto_precharge <= (soc_netsoc_sdram_bankmachine7_row_close == 1'd0);
end
end
end
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
assign {soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_first = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_last = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
always @(*) begin
soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin
soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
end else begin
soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_produce;
end
end
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_replace));
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_consume;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level != 4'd8);
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_pipe_ce = (soc_netsoc_sdram_bankmachine7_cmd_buffer_source_ready | (~soc_netsoc_sdram_bankmachine7_cmd_buffer_valid_n));
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_ready = soc_netsoc_sdram_bankmachine7_cmd_buffer_pipe_ce;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_source_valid = soc_netsoc_sdram_bankmachine7_cmd_buffer_valid_n;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_busy = (1'd0 | soc_netsoc_sdram_bankmachine7_cmd_buffer_valid_n);
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_source_first = soc_netsoc_sdram_bankmachine7_cmd_buffer_first_n;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_source_last = soc_netsoc_sdram_bankmachine7_cmd_buffer_last_n;
always @(*) begin
vns_bankmachine7_next_state <= 3'd0;
soc_netsoc_sdram_bankmachine7_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_bankmachine7_cmd_payload_ras <= 1'd0;
soc_netsoc_sdram_bankmachine7_cmd_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0;
soc_netsoc_sdram_bankmachine7_row_open <= 1'd0;
soc_netsoc_sdram_bankmachine7_cmd_payload_is_read <= 1'd0;
soc_netsoc_sdram_bankmachine7_row_close <= 1'd0;
soc_netsoc_sdram_bankmachine7_cmd_payload_is_write <= 1'd0;
soc_netsoc_sdram_bankmachine7_req_wdata_ready <= 1'd0;
soc_netsoc_sdram_bankmachine7_req_rdata_valid <= 1'd0;
soc_netsoc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0;
soc_netsoc_sdram_bankmachine7_refresh_gnt <= 1'd0;
soc_netsoc_sdram_bankmachine7_cmd_valid <= 1'd0;
vns_bankmachine7_next_state <= vns_bankmachine7_state;
case (vns_bankmachine7_state)
1'd1: begin
if ((soc_netsoc_sdram_bankmachine7_twtpcon_ready & soc_netsoc_sdram_bankmachine7_trascon_ready)) begin
soc_netsoc_sdram_bankmachine7_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine7_cmd_ready) begin
vns_bankmachine7_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
soc_netsoc_sdram_bankmachine7_cmd_payload_we <= 1'd1;
soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
end
soc_netsoc_sdram_bankmachine7_row_close <= 1'd1;
end
2'd2: begin
if ((soc_netsoc_sdram_bankmachine7_twtpcon_ready & soc_netsoc_sdram_bankmachine7_trascon_ready)) begin
vns_bankmachine7_next_state <= 3'd5;
end
soc_netsoc_sdram_bankmachine7_row_close <= 1'd1;
end
2'd3: begin
if (soc_netsoc_sdram_bankmachine7_trccon_ready) begin
soc_netsoc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1;
soc_netsoc_sdram_bankmachine7_row_open <= 1'd1;
soc_netsoc_sdram_bankmachine7_cmd_valid <= 1'd1;
soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
if (soc_netsoc_sdram_bankmachine7_cmd_ready) begin
vns_bankmachine7_next_state <= 3'd6;
end
soc_netsoc_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (soc_netsoc_sdram_bankmachine7_twtpcon_ready) begin
soc_netsoc_sdram_bankmachine7_refresh_gnt <= 1'd1;
end
soc_netsoc_sdram_bankmachine7_row_close <= 1'd1;
soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
if ((~soc_netsoc_sdram_bankmachine7_refresh_req)) begin
vns_bankmachine7_next_state <= 1'd0;
end
end
3'd5: begin
vns_bankmachine7_next_state <= 2'd3;
end
3'd6: begin
vns_bankmachine7_next_state <= 1'd0;
end
default: begin
if (soc_netsoc_sdram_bankmachine7_refresh_req) begin
vns_bankmachine7_next_state <= 3'd4;
end else begin
if (soc_netsoc_sdram_bankmachine7_cmd_buffer_source_valid) begin
if (soc_netsoc_sdram_bankmachine7_row_opened) begin
if (soc_netsoc_sdram_bankmachine7_row_hit) begin
soc_netsoc_sdram_bankmachine7_cmd_valid <= 1'd1;
if (soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
soc_netsoc_sdram_bankmachine7_req_wdata_ready <= soc_netsoc_sdram_bankmachine7_cmd_ready;
soc_netsoc_sdram_bankmachine7_cmd_payload_is_write <= 1'd1;
soc_netsoc_sdram_bankmachine7_cmd_payload_we <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine7_req_rdata_valid <= soc_netsoc_sdram_bankmachine7_cmd_ready;
soc_netsoc_sdram_bankmachine7_cmd_payload_is_read <= 1'd1;
end
soc_netsoc_sdram_bankmachine7_cmd_payload_cas <= 1'd1;
if ((soc_netsoc_sdram_bankmachine7_cmd_ready & soc_netsoc_sdram_bankmachine7_auto_precharge)) begin
vns_bankmachine7_next_state <= 2'd2;
end
end else begin
vns_bankmachine7_next_state <= 1'd1;
end
end else begin
vns_bankmachine7_next_state <= 2'd3;
end
end
end
end
endcase
end
assign soc_netsoc_sdram_trrdcon_valid = ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & ((soc_netsoc_sdram_choose_cmd_cmd_payload_ras & (~soc_netsoc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_netsoc_sdram_choose_cmd_cmd_payload_we)));
assign soc_netsoc_sdram_tfawcon_valid = ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & ((soc_netsoc_sdram_choose_cmd_cmd_payload_ras & (~soc_netsoc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_netsoc_sdram_choose_cmd_cmd_payload_we)));
assign soc_netsoc_sdram_ras_allowed = (soc_netsoc_sdram_trrdcon_ready & soc_netsoc_sdram_tfawcon_ready);
assign soc_netsoc_sdram_tccdcon_valid = ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_cmd_payload_is_write | soc_netsoc_sdram_choose_req_cmd_payload_is_read));
assign soc_netsoc_sdram_cas_allowed = soc_netsoc_sdram_tccdcon_ready;
assign soc_netsoc_sdram_twtrcon_valid = ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_write);
assign soc_netsoc_sdram_read_available = ((((((((soc_netsoc_sdram_bankmachine0_cmd_valid & soc_netsoc_sdram_bankmachine0_cmd_payload_is_read) | (soc_netsoc_sdram_bankmachine1_cmd_valid & soc_netsoc_sdram_bankmachine1_cmd_payload_is_read)) | (soc_netsoc_sdram_bankmachine2_cmd_valid & soc_netsoc_sdram_bankmachine2_cmd_payload_is_read)) | (soc_netsoc_sdram_bankmachine3_cmd_valid & soc_netsoc_sdram_bankmachine3_cmd_payload_is_read)) | (soc_netsoc_sdram_bankmachine4_cmd_valid & soc_netsoc_sdram_bankmachine4_cmd_payload_is_read)) | (soc_netsoc_sdram_bankmachine5_cmd_valid & soc_netsoc_sdram_bankmachine5_cmd_payload_is_read)) | (soc_netsoc_sdram_bankmachine6_cmd_valid & soc_netsoc_sdram_bankmachine6_cmd_payload_is_read)) | (soc_netsoc_sdram_bankmachine7_cmd_valid & soc_netsoc_sdram_bankmachine7_cmd_payload_is_read));
assign soc_netsoc_sdram_write_available = ((((((((soc_netsoc_sdram_bankmachine0_cmd_valid & soc_netsoc_sdram_bankmachine0_cmd_payload_is_write) | (soc_netsoc_sdram_bankmachine1_cmd_valid & soc_netsoc_sdram_bankmachine1_cmd_payload_is_write)) | (soc_netsoc_sdram_bankmachine2_cmd_valid & soc_netsoc_sdram_bankmachine2_cmd_payload_is_write)) | (soc_netsoc_sdram_bankmachine3_cmd_valid & soc_netsoc_sdram_bankmachine3_cmd_payload_is_write)) | (soc_netsoc_sdram_bankmachine4_cmd_valid & soc_netsoc_sdram_bankmachine4_cmd_payload_is_write)) | (soc_netsoc_sdram_bankmachine5_cmd_valid & soc_netsoc_sdram_bankmachine5_cmd_payload_is_write)) | (soc_netsoc_sdram_bankmachine6_cmd_valid & soc_netsoc_sdram_bankmachine6_cmd_payload_is_write)) | (soc_netsoc_sdram_bankmachine7_cmd_valid & soc_netsoc_sdram_bankmachine7_cmd_payload_is_write));
assign soc_netsoc_sdram_max_time0 = (soc_netsoc_sdram_time0 == 1'd0);
assign soc_netsoc_sdram_max_time1 = (soc_netsoc_sdram_time1 == 1'd0);
assign soc_netsoc_sdram_bankmachine0_refresh_req = soc_netsoc_sdram_cmd_valid;
assign soc_netsoc_sdram_bankmachine1_refresh_req = soc_netsoc_sdram_cmd_valid;
assign soc_netsoc_sdram_bankmachine2_refresh_req = soc_netsoc_sdram_cmd_valid;
assign soc_netsoc_sdram_bankmachine3_refresh_req = soc_netsoc_sdram_cmd_valid;
assign soc_netsoc_sdram_bankmachine4_refresh_req = soc_netsoc_sdram_cmd_valid;
assign soc_netsoc_sdram_bankmachine5_refresh_req = soc_netsoc_sdram_cmd_valid;
assign soc_netsoc_sdram_bankmachine6_refresh_req = soc_netsoc_sdram_cmd_valid;
assign soc_netsoc_sdram_bankmachine7_refresh_req = soc_netsoc_sdram_cmd_valid;
assign soc_netsoc_sdram_go_to_refresh = (((((((soc_netsoc_sdram_bankmachine0_refresh_gnt & soc_netsoc_sdram_bankmachine1_refresh_gnt) & soc_netsoc_sdram_bankmachine2_refresh_gnt) & soc_netsoc_sdram_bankmachine3_refresh_gnt) & soc_netsoc_sdram_bankmachine4_refresh_gnt) & soc_netsoc_sdram_bankmachine5_refresh_gnt) & soc_netsoc_sdram_bankmachine6_refresh_gnt) & soc_netsoc_sdram_bankmachine7_refresh_gnt);
assign soc_netsoc_sdram_interface_rdata = {soc_netsoc_sdram_dfi_p3_rddata, soc_netsoc_sdram_dfi_p2_rddata, soc_netsoc_sdram_dfi_p1_rddata, soc_netsoc_sdram_dfi_p0_rddata};
assign {soc_netsoc_sdram_dfi_p3_wrdata, soc_netsoc_sdram_dfi_p2_wrdata, soc_netsoc_sdram_dfi_p1_wrdata, soc_netsoc_sdram_dfi_p0_wrdata} = soc_netsoc_sdram_interface_wdata;
assign {soc_netsoc_sdram_dfi_p3_wrdata_mask, soc_netsoc_sdram_dfi_p2_wrdata_mask, soc_netsoc_sdram_dfi_p1_wrdata_mask, soc_netsoc_sdram_dfi_p0_wrdata_mask} = (~soc_netsoc_sdram_interface_wdata_we);
always @(*) begin
soc_netsoc_sdram_choose_cmd_valids <= 8'd0;
soc_netsoc_sdram_choose_cmd_valids[0] <= (soc_netsoc_sdram_bankmachine0_cmd_valid & (((soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine0_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine0_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine0_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine0_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
soc_netsoc_sdram_choose_cmd_valids[1] <= (soc_netsoc_sdram_bankmachine1_cmd_valid & (((soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine1_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine1_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine1_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine1_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
soc_netsoc_sdram_choose_cmd_valids[2] <= (soc_netsoc_sdram_bankmachine2_cmd_valid & (((soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine2_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine2_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine2_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine2_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
soc_netsoc_sdram_choose_cmd_valids[3] <= (soc_netsoc_sdram_bankmachine3_cmd_valid & (((soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine3_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine3_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine3_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine3_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
soc_netsoc_sdram_choose_cmd_valids[4] <= (soc_netsoc_sdram_bankmachine4_cmd_valid & (((soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine4_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine4_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine4_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine4_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
soc_netsoc_sdram_choose_cmd_valids[5] <= (soc_netsoc_sdram_bankmachine5_cmd_valid & (((soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine5_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine5_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine5_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine5_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
soc_netsoc_sdram_choose_cmd_valids[6] <= (soc_netsoc_sdram_bankmachine6_cmd_valid & (((soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine6_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine6_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine6_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine6_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
soc_netsoc_sdram_choose_cmd_valids[7] <= (soc_netsoc_sdram_bankmachine7_cmd_valid & (((soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd & soc_netsoc_sdram_choose_cmd_want_cmds) & ((~((soc_netsoc_sdram_bankmachine7_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine7_cmd_payload_we))) | soc_netsoc_sdram_choose_cmd_want_activates)) | ((soc_netsoc_sdram_bankmachine7_cmd_payload_is_read == soc_netsoc_sdram_choose_cmd_want_reads) & (soc_netsoc_sdram_bankmachine7_cmd_payload_is_write == soc_netsoc_sdram_choose_cmd_want_writes))));
end
assign soc_netsoc_sdram_choose_cmd_request = soc_netsoc_sdram_choose_cmd_valids;
assign soc_netsoc_sdram_choose_cmd_cmd_valid = vns_rhs_array_muxed0;
assign soc_netsoc_sdram_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1;
assign soc_netsoc_sdram_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2;
assign soc_netsoc_sdram_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3;
assign soc_netsoc_sdram_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4;
assign soc_netsoc_sdram_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5;
always @(*) begin
soc_netsoc_sdram_choose_cmd_cmd_payload_cas <= 1'd0;
if (soc_netsoc_sdram_choose_cmd_cmd_valid) begin
soc_netsoc_sdram_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0;
end
end
always @(*) begin
soc_netsoc_sdram_choose_cmd_cmd_payload_ras <= 1'd0;
if (soc_netsoc_sdram_choose_cmd_cmd_valid) begin
soc_netsoc_sdram_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1;
end
end
always @(*) begin
soc_netsoc_sdram_choose_cmd_cmd_payload_we <= 1'd0;
if (soc_netsoc_sdram_choose_cmd_cmd_valid) begin
soc_netsoc_sdram_choose_cmd_cmd_payload_we <= vns_t_array_muxed2;
end
end
assign soc_netsoc_sdram_choose_cmd_ce = (soc_netsoc_sdram_choose_cmd_cmd_ready | (~soc_netsoc_sdram_choose_cmd_cmd_valid));
always @(*) begin
soc_netsoc_sdram_choose_req_valids <= 8'd0;
soc_netsoc_sdram_choose_req_valids[0] <= (soc_netsoc_sdram_bankmachine0_cmd_valid & (((soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine0_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine0_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine0_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine0_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
soc_netsoc_sdram_choose_req_valids[1] <= (soc_netsoc_sdram_bankmachine1_cmd_valid & (((soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine1_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine1_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine1_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine1_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
soc_netsoc_sdram_choose_req_valids[2] <= (soc_netsoc_sdram_bankmachine2_cmd_valid & (((soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine2_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine2_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine2_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine2_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
soc_netsoc_sdram_choose_req_valids[3] <= (soc_netsoc_sdram_bankmachine3_cmd_valid & (((soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine3_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine3_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine3_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine3_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
soc_netsoc_sdram_choose_req_valids[4] <= (soc_netsoc_sdram_bankmachine4_cmd_valid & (((soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine4_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine4_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine4_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine4_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
soc_netsoc_sdram_choose_req_valids[5] <= (soc_netsoc_sdram_bankmachine5_cmd_valid & (((soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine5_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine5_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine5_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine5_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
soc_netsoc_sdram_choose_req_valids[6] <= (soc_netsoc_sdram_bankmachine6_cmd_valid & (((soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine6_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine6_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine6_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine6_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
soc_netsoc_sdram_choose_req_valids[7] <= (soc_netsoc_sdram_bankmachine7_cmd_valid & (((soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd & soc_netsoc_sdram_choose_req_want_cmds) & ((~((soc_netsoc_sdram_bankmachine7_cmd_payload_ras & (~soc_netsoc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_netsoc_sdram_bankmachine7_cmd_payload_we))) | soc_netsoc_sdram_choose_req_want_activates)) | ((soc_netsoc_sdram_bankmachine7_cmd_payload_is_read == soc_netsoc_sdram_choose_req_want_reads) & (soc_netsoc_sdram_bankmachine7_cmd_payload_is_write == soc_netsoc_sdram_choose_req_want_writes))));
end
assign soc_netsoc_sdram_choose_req_request = soc_netsoc_sdram_choose_req_valids;
assign soc_netsoc_sdram_choose_req_cmd_valid = vns_rhs_array_muxed6;
assign soc_netsoc_sdram_choose_req_cmd_payload_a = vns_rhs_array_muxed7;
assign soc_netsoc_sdram_choose_req_cmd_payload_ba = vns_rhs_array_muxed8;
assign soc_netsoc_sdram_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9;
assign soc_netsoc_sdram_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10;
assign soc_netsoc_sdram_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11;
always @(*) begin
soc_netsoc_sdram_choose_req_cmd_payload_cas <= 1'd0;
if (soc_netsoc_sdram_choose_req_cmd_valid) begin
soc_netsoc_sdram_choose_req_cmd_payload_cas <= vns_t_array_muxed3;
end
end
always @(*) begin
soc_netsoc_sdram_choose_req_cmd_payload_ras <= 1'd0;
if (soc_netsoc_sdram_choose_req_cmd_valid) begin
soc_netsoc_sdram_choose_req_cmd_payload_ras <= vns_t_array_muxed4;
end
end
always @(*) begin
soc_netsoc_sdram_choose_req_cmd_payload_we <= 1'd0;
if (soc_netsoc_sdram_choose_req_cmd_valid) begin
soc_netsoc_sdram_choose_req_cmd_payload_we <= vns_t_array_muxed5;
end
end
always @(*) begin
soc_netsoc_sdram_bankmachine0_cmd_ready <= 1'd0;
if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 1'd0))) begin
soc_netsoc_sdram_bankmachine0_cmd_ready <= 1'd1;
end
if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 1'd0))) begin
soc_netsoc_sdram_bankmachine0_cmd_ready <= 1'd1;
end
end
always @(*) begin
soc_netsoc_sdram_bankmachine1_cmd_ready <= 1'd0;
if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 1'd1))) begin
soc_netsoc_sdram_bankmachine1_cmd_ready <= 1'd1;
end
if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 1'd1))) begin
soc_netsoc_sdram_bankmachine1_cmd_ready <= 1'd1;
end
end
always @(*) begin
soc_netsoc_sdram_bankmachine2_cmd_ready <= 1'd0;
if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 2'd2))) begin
soc_netsoc_sdram_bankmachine2_cmd_ready <= 1'd1;
end
if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 2'd2))) begin
soc_netsoc_sdram_bankmachine2_cmd_ready <= 1'd1;
end
end
always @(*) begin
soc_netsoc_sdram_bankmachine3_cmd_ready <= 1'd0;
if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 2'd3))) begin
soc_netsoc_sdram_bankmachine3_cmd_ready <= 1'd1;
end
if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 2'd3))) begin
soc_netsoc_sdram_bankmachine3_cmd_ready <= 1'd1;
end
end
always @(*) begin
soc_netsoc_sdram_bankmachine4_cmd_ready <= 1'd0;
if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 3'd4))) begin
soc_netsoc_sdram_bankmachine4_cmd_ready <= 1'd1;
end
if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 3'd4))) begin
soc_netsoc_sdram_bankmachine4_cmd_ready <= 1'd1;
end
end
always @(*) begin
soc_netsoc_sdram_bankmachine5_cmd_ready <= 1'd0;
if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 3'd5))) begin
soc_netsoc_sdram_bankmachine5_cmd_ready <= 1'd1;
end
if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 3'd5))) begin
soc_netsoc_sdram_bankmachine5_cmd_ready <= 1'd1;
end
end
always @(*) begin
soc_netsoc_sdram_bankmachine6_cmd_ready <= 1'd0;
if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 3'd6))) begin
soc_netsoc_sdram_bankmachine6_cmd_ready <= 1'd1;
end
if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 3'd6))) begin
soc_netsoc_sdram_bankmachine6_cmd_ready <= 1'd1;
end
end
always @(*) begin
soc_netsoc_sdram_bankmachine7_cmd_ready <= 1'd0;
if (((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & (soc_netsoc_sdram_choose_cmd_grant == 3'd7))) begin
soc_netsoc_sdram_bankmachine7_cmd_ready <= 1'd1;
end
if (((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & (soc_netsoc_sdram_choose_req_grant == 3'd7))) begin
soc_netsoc_sdram_bankmachine7_cmd_ready <= 1'd1;
end
end
assign soc_netsoc_sdram_choose_req_ce = (soc_netsoc_sdram_choose_req_cmd_ready | (~soc_netsoc_sdram_choose_req_cmd_valid));
assign soc_netsoc_sdram_dfi_p0_reset_n = 1'd1;
assign soc_netsoc_sdram_dfi_p0_cke = {1{soc_netsoc_sdram_steerer0}};
assign soc_netsoc_sdram_dfi_p0_odt = {1{soc_netsoc_sdram_steerer1}};
assign soc_netsoc_sdram_dfi_p1_reset_n = 1'd1;
assign soc_netsoc_sdram_dfi_p1_cke = {1{soc_netsoc_sdram_steerer2}};
assign soc_netsoc_sdram_dfi_p1_odt = {1{soc_netsoc_sdram_steerer3}};
assign soc_netsoc_sdram_dfi_p2_reset_n = 1'd1;
assign soc_netsoc_sdram_dfi_p2_cke = {1{soc_netsoc_sdram_steerer4}};
assign soc_netsoc_sdram_dfi_p2_odt = {1{soc_netsoc_sdram_steerer5}};
assign soc_netsoc_sdram_dfi_p3_reset_n = 1'd1;
assign soc_netsoc_sdram_dfi_p3_cke = {1{soc_netsoc_sdram_steerer6}};
assign soc_netsoc_sdram_dfi_p3_odt = {1{soc_netsoc_sdram_steerer7}};
assign soc_netsoc_sdram_tfawcon_count = (((soc_netsoc_sdram_tfawcon_window[0] + soc_netsoc_sdram_tfawcon_window[1]) + soc_netsoc_sdram_tfawcon_window[2]) + soc_netsoc_sdram_tfawcon_window[3]);
always @(*) begin
soc_netsoc_sdram_en0 <= 1'd0;
soc_netsoc_sdram_choose_cmd_want_activates <= 1'd0;
soc_netsoc_sdram_steerer_sel3 <= 2'd0;
soc_netsoc_sdram_cmd_ready <= 1'd0;
soc_netsoc_sdram_choose_cmd_cmd_ready <= 1'd0;
soc_netsoc_sdram_choose_req_want_reads <= 1'd0;
soc_netsoc_sdram_choose_req_want_writes <= 1'd0;
soc_netsoc_sdram_en1 <= 1'd0;
soc_netsoc_sdram_choose_req_cmd_ready <= 1'd0;
soc_netsoc_sdram_steerer_sel0 <= 2'd0;
vns_multiplexer_next_state <= 4'd0;
soc_netsoc_sdram_steerer_sel1 <= 2'd0;
soc_netsoc_sdram_steerer_sel2 <= 2'd0;
vns_multiplexer_next_state <= vns_multiplexer_state;
case (vns_multiplexer_state)
1'd1: begin
soc_netsoc_sdram_en1 <= 1'd1;
soc_netsoc_sdram_choose_req_want_writes <= 1'd1;
if (1'd0) begin
soc_netsoc_sdram_choose_req_cmd_ready <= (soc_netsoc_sdram_cas_allowed & ((~((soc_netsoc_sdram_choose_req_cmd_payload_ras & (~soc_netsoc_sdram_choose_req_cmd_payload_cas)) & (~soc_netsoc_sdram_choose_req_cmd_payload_we))) | soc_netsoc_sdram_ras_allowed));
end else begin
soc_netsoc_sdram_choose_cmd_want_activates <= soc_netsoc_sdram_ras_allowed;
soc_netsoc_sdram_choose_cmd_cmd_ready <= ((~((soc_netsoc_sdram_choose_cmd_cmd_payload_ras & (~soc_netsoc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_netsoc_sdram_choose_cmd_cmd_payload_we))) | soc_netsoc_sdram_ras_allowed);
soc_netsoc_sdram_choose_req_cmd_ready <= soc_netsoc_sdram_cas_allowed;
end
soc_netsoc_sdram_steerer_sel0 <= 1'd0;
soc_netsoc_sdram_steerer_sel1 <= 1'd0;
soc_netsoc_sdram_steerer_sel2 <= 1'd1;
soc_netsoc_sdram_steerer_sel3 <= 2'd2;
if (soc_netsoc_sdram_read_available) begin
if (((~soc_netsoc_sdram_write_available) | soc_netsoc_sdram_max_time1)) begin
vns_multiplexer_next_state <= 2'd3;
end
end
if (soc_netsoc_sdram_go_to_refresh) begin
vns_multiplexer_next_state <= 2'd2;
end
end
2'd2: begin
soc_netsoc_sdram_steerer_sel0 <= 2'd3;
soc_netsoc_sdram_cmd_ready <= 1'd1;
if (soc_netsoc_sdram_cmd_last) begin
vns_multiplexer_next_state <= 1'd0;
end
end
2'd3: begin
if (soc_netsoc_sdram_twtrcon_ready) begin
vns_multiplexer_next_state <= 1'd0;
end
end
3'd4: begin
vns_multiplexer_next_state <= 3'd5;
end
3'd5: begin
vns_multiplexer_next_state <= 3'd6;
end
3'd6: begin
vns_multiplexer_next_state <= 3'd7;
end
3'd7: begin
vns_multiplexer_next_state <= 4'd8;
end
4'd8: begin
vns_multiplexer_next_state <= 4'd9;
end
4'd9: begin
vns_multiplexer_next_state <= 4'd10;
end
4'd10: begin
vns_multiplexer_next_state <= 4'd11;
end
4'd11: begin
vns_multiplexer_next_state <= 1'd1;
end
default: begin
soc_netsoc_sdram_en0 <= 1'd1;
soc_netsoc_sdram_choose_req_want_reads <= 1'd1;
if (1'd0) begin
soc_netsoc_sdram_choose_req_cmd_ready <= (soc_netsoc_sdram_cas_allowed & ((~((soc_netsoc_sdram_choose_req_cmd_payload_ras & (~soc_netsoc_sdram_choose_req_cmd_payload_cas)) & (~soc_netsoc_sdram_choose_req_cmd_payload_we))) | soc_netsoc_sdram_ras_allowed));
end else begin
soc_netsoc_sdram_choose_cmd_want_activates <= soc_netsoc_sdram_ras_allowed;
soc_netsoc_sdram_choose_cmd_cmd_ready <= ((~((soc_netsoc_sdram_choose_cmd_cmd_payload_ras & (~soc_netsoc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_netsoc_sdram_choose_cmd_cmd_payload_we))) | soc_netsoc_sdram_ras_allowed);
soc_netsoc_sdram_choose_req_cmd_ready <= soc_netsoc_sdram_cas_allowed;
end
soc_netsoc_sdram_steerer_sel0 <= 1'd0;
soc_netsoc_sdram_steerer_sel1 <= 1'd1;
soc_netsoc_sdram_steerer_sel2 <= 2'd2;
soc_netsoc_sdram_steerer_sel3 <= 1'd0;
if (soc_netsoc_sdram_write_available) begin
if (((~soc_netsoc_sdram_read_available) | soc_netsoc_sdram_max_time0)) begin
vns_multiplexer_next_state <= 3'd4;
end
end
if (soc_netsoc_sdram_go_to_refresh) begin
vns_multiplexer_next_state <= 2'd2;
end
end
endcase
end
assign vns_roundrobin0_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
assign vns_roundrobin0_ce = ((~soc_netsoc_sdram_interface_bank0_valid) & (~soc_netsoc_sdram_interface_bank0_lock));
assign soc_netsoc_sdram_interface_bank0_addr = vns_rhs_array_muxed12;
assign soc_netsoc_sdram_interface_bank0_we = vns_rhs_array_muxed13;
assign soc_netsoc_sdram_interface_bank0_valid = vns_rhs_array_muxed14;
assign vns_roundrobin1_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
assign vns_roundrobin1_ce = ((~soc_netsoc_sdram_interface_bank1_valid) & (~soc_netsoc_sdram_interface_bank1_lock));
assign soc_netsoc_sdram_interface_bank1_addr = vns_rhs_array_muxed15;
assign soc_netsoc_sdram_interface_bank1_we = vns_rhs_array_muxed16;
assign soc_netsoc_sdram_interface_bank1_valid = vns_rhs_array_muxed17;
assign vns_roundrobin2_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
assign vns_roundrobin2_ce = ((~soc_netsoc_sdram_interface_bank2_valid) & (~soc_netsoc_sdram_interface_bank2_lock));
assign soc_netsoc_sdram_interface_bank2_addr = vns_rhs_array_muxed18;
assign soc_netsoc_sdram_interface_bank2_we = vns_rhs_array_muxed19;
assign soc_netsoc_sdram_interface_bank2_valid = vns_rhs_array_muxed20;
assign vns_roundrobin3_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
assign vns_roundrobin3_ce = ((~soc_netsoc_sdram_interface_bank3_valid) & (~soc_netsoc_sdram_interface_bank3_lock));
assign soc_netsoc_sdram_interface_bank3_addr = vns_rhs_array_muxed21;
assign soc_netsoc_sdram_interface_bank3_we = vns_rhs_array_muxed22;
assign soc_netsoc_sdram_interface_bank3_valid = vns_rhs_array_muxed23;
assign vns_roundrobin4_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
assign vns_roundrobin4_ce = ((~soc_netsoc_sdram_interface_bank4_valid) & (~soc_netsoc_sdram_interface_bank4_lock));
assign soc_netsoc_sdram_interface_bank4_addr = vns_rhs_array_muxed24;
assign soc_netsoc_sdram_interface_bank4_we = vns_rhs_array_muxed25;
assign soc_netsoc_sdram_interface_bank4_valid = vns_rhs_array_muxed26;
assign vns_roundrobin5_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
assign vns_roundrobin5_ce = ((~soc_netsoc_sdram_interface_bank5_valid) & (~soc_netsoc_sdram_interface_bank5_lock));
assign soc_netsoc_sdram_interface_bank5_addr = vns_rhs_array_muxed27;
assign soc_netsoc_sdram_interface_bank5_we = vns_rhs_array_muxed28;
assign soc_netsoc_sdram_interface_bank5_valid = vns_rhs_array_muxed29;
assign vns_roundrobin6_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
assign vns_roundrobin6_ce = ((~soc_netsoc_sdram_interface_bank6_valid) & (~soc_netsoc_sdram_interface_bank6_lock));
assign soc_netsoc_sdram_interface_bank6_addr = vns_rhs_array_muxed30;
assign soc_netsoc_sdram_interface_bank6_we = vns_rhs_array_muxed31;
assign soc_netsoc_sdram_interface_bank6_valid = vns_rhs_array_muxed32;
assign vns_roundrobin7_request = {(((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_netsoc_port_cmd_valid)};
assign vns_roundrobin7_ce = ((~soc_netsoc_sdram_interface_bank7_valid) & (~soc_netsoc_sdram_interface_bank7_lock));
assign soc_netsoc_sdram_interface_bank7_addr = vns_rhs_array_muxed33;
assign soc_netsoc_sdram_interface_bank7_we = vns_rhs_array_muxed34;
assign soc_netsoc_sdram_interface_bank7_valid = vns_rhs_array_muxed35;
assign soc_netsoc_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_netsoc_sdram_interface_bank7_ready));
assign soc_netsoc_port_wdata_ready = vns_new_master_wdata_ready2;
assign soc_netsoc_port_rdata_valid = vns_new_master_rdata_valid9;
always @(*) begin
soc_netsoc_sdram_interface_wdata <= 128'd0;
soc_netsoc_sdram_interface_wdata_we <= 16'd0;
case ({vns_new_master_wdata_ready2})
1'd1: begin
soc_netsoc_sdram_interface_wdata <= soc_netsoc_port_wdata_payload_data;
soc_netsoc_sdram_interface_wdata_we <= soc_netsoc_port_wdata_payload_we;
end
default: begin
soc_netsoc_sdram_interface_wdata <= 1'd0;
soc_netsoc_sdram_interface_wdata_we <= 1'd0;
end
endcase
end
assign soc_netsoc_port_rdata_payload_data = soc_netsoc_sdram_interface_rdata;
assign vns_roundrobin0_grant = 1'd0;
assign vns_roundrobin1_grant = 1'd0;
assign vns_roundrobin2_grant = 1'd0;
assign vns_roundrobin3_grant = 1'd0;
assign vns_roundrobin4_grant = 1'd0;
assign vns_roundrobin5_grant = 1'd0;
assign vns_roundrobin6_grant = 1'd0;
assign vns_roundrobin7_grant = 1'd0;
assign soc_netsoc_data_port_adr = soc_netsoc_interface0_wb_sdram_adr[10:2];
always @(*) begin
soc_netsoc_data_port_we <= 16'd0;
soc_netsoc_data_port_dat_w <= 128'd0;
if (soc_netsoc_write_from_slave) begin
soc_netsoc_data_port_dat_w <= soc_netsoc_dat_r;
soc_netsoc_data_port_we <= {16{1'd1}};
end else begin
soc_netsoc_data_port_dat_w <= {4{soc_netsoc_interface0_wb_sdram_dat_w}};
if ((((soc_netsoc_interface0_wb_sdram_cyc & soc_netsoc_interface0_wb_sdram_stb) & soc_netsoc_interface0_wb_sdram_we) & soc_netsoc_interface0_wb_sdram_ack)) begin
soc_netsoc_data_port_we <= {({4{(soc_netsoc_interface0_wb_sdram_adr[1:0] == 1'd0)}} & soc_netsoc_interface0_wb_sdram_sel), ({4{(soc_netsoc_interface0_wb_sdram_adr[1:0] == 1'd1)}} & soc_netsoc_interface0_wb_sdram_sel), ({4{(soc_netsoc_interface0_wb_sdram_adr[1:0] == 2'd2)}} & soc_netsoc_interface0_wb_sdram_sel), ({4{(soc_netsoc_interface0_wb_sdram_adr[1:0] == 2'd3)}} & soc_netsoc_interface0_wb_sdram_sel)};
end
end
end
assign soc_netsoc_dat_w = soc_netsoc_data_port_dat_r;
assign soc_netsoc_sel = 16'd65535;
always @(*) begin
soc_netsoc_interface0_wb_sdram_dat_r <= 32'd0;
case (soc_netsoc_adr_offset_r)
1'd0: begin
soc_netsoc_interface0_wb_sdram_dat_r <= soc_netsoc_data_port_dat_r[127:96];
end
1'd1: begin
soc_netsoc_interface0_wb_sdram_dat_r <= soc_netsoc_data_port_dat_r[95:64];
end
2'd2: begin
soc_netsoc_interface0_wb_sdram_dat_r <= soc_netsoc_data_port_dat_r[63:32];
end
default: begin
soc_netsoc_interface0_wb_sdram_dat_r <= soc_netsoc_data_port_dat_r[31:0];
end
endcase
end
assign {soc_netsoc_tag_do_dirty, soc_netsoc_tag_do_tag} = soc_netsoc_tag_port_dat_r;
assign soc_netsoc_tag_port_dat_w = {soc_netsoc_tag_di_dirty, soc_netsoc_tag_di_tag};
assign soc_netsoc_tag_port_adr = soc_netsoc_interface0_wb_sdram_adr[10:2];
assign soc_netsoc_tag_di_tag = soc_netsoc_interface0_wb_sdram_adr[29:11];
assign soc_netsoc_adr = {soc_netsoc_tag_do_tag, soc_netsoc_interface0_wb_sdram_adr[10:2]};
always @(*) begin
vns_fullmemorywe_next_state <= 3'd0;
soc_netsoc_tag_di_dirty <= 1'd0;
soc_netsoc_word_clr <= 1'd0;
soc_netsoc_interface0_wb_sdram_ack <= 1'd0;
soc_netsoc_word_inc <= 1'd0;
soc_netsoc_write_from_slave <= 1'd0;
soc_netsoc_cyc <= 1'd0;
soc_netsoc_stb <= 1'd0;
soc_netsoc_tag_port_we <= 1'd0;
soc_netsoc_we <= 1'd0;
vns_fullmemorywe_next_state <= vns_fullmemorywe_state;
case (vns_fullmemorywe_state)
1'd1: begin
soc_netsoc_word_clr <= 1'd1;
if ((soc_netsoc_tag_do_tag == soc_netsoc_interface0_wb_sdram_adr[29:11])) begin
soc_netsoc_interface0_wb_sdram_ack <= 1'd1;
if (soc_netsoc_interface0_wb_sdram_we) begin
soc_netsoc_tag_di_dirty <= 1'd1;
soc_netsoc_tag_port_we <= 1'd1;
end
vns_fullmemorywe_next_state <= 1'd0;
end else begin
if (soc_netsoc_tag_do_dirty) begin
vns_fullmemorywe_next_state <= 2'd2;
end else begin
vns_fullmemorywe_next_state <= 2'd3;
end
end
end
2'd2: begin
soc_netsoc_stb <= 1'd1;
soc_netsoc_cyc <= 1'd1;
soc_netsoc_we <= 1'd1;
if (soc_netsoc_ack) begin
soc_netsoc_word_inc <= 1'd1;
if (1'd1) begin
vns_fullmemorywe_next_state <= 2'd3;
end
end
end
2'd3: begin
soc_netsoc_tag_port_we <= 1'd1;
soc_netsoc_word_clr <= 1'd1;
vns_fullmemorywe_next_state <= 3'd4;
end
3'd4: begin
soc_netsoc_stb <= 1'd1;
soc_netsoc_cyc <= 1'd1;
soc_netsoc_we <= 1'd0;
if (soc_netsoc_ack) begin
soc_netsoc_write_from_slave <= 1'd1;
soc_netsoc_word_inc <= 1'd1;
if (1'd1) begin
vns_fullmemorywe_next_state <= 1'd1;
end else begin
vns_fullmemorywe_next_state <= 3'd4;
end
end
end
default: begin
if ((soc_netsoc_interface0_wb_sdram_cyc & soc_netsoc_interface0_wb_sdram_stb)) begin
vns_fullmemorywe_next_state <= 1'd1;
end
end
endcase
end
assign soc_netsoc_wdata_converter_sink_valid = ((soc_netsoc_cyc & soc_netsoc_stb) & soc_netsoc_we);
assign soc_netsoc_wdata_converter_sink_payload_data = soc_netsoc_dat_w;
assign soc_netsoc_wdata_converter_sink_payload_we = soc_netsoc_sel;
assign soc_netsoc_port_wdata_valid = soc_netsoc_wdata_converter_source_valid;
assign soc_netsoc_wdata_converter_source_ready = soc_netsoc_port_wdata_ready;
assign soc_netsoc_port_wdata_first = soc_netsoc_wdata_converter_source_first;
assign soc_netsoc_port_wdata_last = soc_netsoc_wdata_converter_source_last;
assign soc_netsoc_port_wdata_payload_data = soc_netsoc_wdata_converter_source_payload_data;
assign soc_netsoc_port_wdata_payload_we = soc_netsoc_wdata_converter_source_payload_we;
assign soc_netsoc_rdata_converter_sink_valid = soc_netsoc_port_rdata_valid;
assign soc_netsoc_port_rdata_ready = soc_netsoc_rdata_converter_sink_ready;
assign soc_netsoc_rdata_converter_sink_first = soc_netsoc_port_rdata_first;
assign soc_netsoc_rdata_converter_sink_last = soc_netsoc_port_rdata_last;
assign soc_netsoc_rdata_converter_sink_payload_data = soc_netsoc_port_rdata_payload_data;
assign soc_netsoc_rdata_converter_source_ready = 1'd1;
assign soc_netsoc_dat_r = soc_netsoc_rdata_converter_source_payload_data;
assign soc_netsoc_wdata_converter_converter_sink_valid = soc_netsoc_wdata_converter_sink_valid;
assign soc_netsoc_wdata_converter_converter_sink_first = soc_netsoc_wdata_converter_sink_first;
assign soc_netsoc_wdata_converter_converter_sink_last = soc_netsoc_wdata_converter_sink_last;
assign soc_netsoc_wdata_converter_sink_ready = soc_netsoc_wdata_converter_converter_sink_ready;
assign soc_netsoc_wdata_converter_converter_sink_payload_data = {soc_netsoc_wdata_converter_sink_payload_we, soc_netsoc_wdata_converter_sink_payload_data};
assign soc_netsoc_wdata_converter_source_valid = soc_netsoc_wdata_converter_source_source_valid;
assign soc_netsoc_wdata_converter_source_first = soc_netsoc_wdata_converter_source_source_first;
assign soc_netsoc_wdata_converter_source_last = soc_netsoc_wdata_converter_source_source_last;
assign soc_netsoc_wdata_converter_source_source_ready = soc_netsoc_wdata_converter_source_ready;
assign {soc_netsoc_wdata_converter_source_payload_we, soc_netsoc_wdata_converter_source_payload_data} = soc_netsoc_wdata_converter_source_source_payload_data;
assign soc_netsoc_wdata_converter_source_source_valid = soc_netsoc_wdata_converter_converter_source_valid;
assign soc_netsoc_wdata_converter_converter_source_ready = soc_netsoc_wdata_converter_source_source_ready;
assign soc_netsoc_wdata_converter_source_source_first = soc_netsoc_wdata_converter_converter_source_first;
assign soc_netsoc_wdata_converter_source_source_last = soc_netsoc_wdata_converter_converter_source_last;
assign soc_netsoc_wdata_converter_source_source_payload_data = soc_netsoc_wdata_converter_converter_source_payload_data;
assign soc_netsoc_wdata_converter_converter_source_valid = soc_netsoc_wdata_converter_converter_sink_valid;
assign soc_netsoc_wdata_converter_converter_sink_ready = soc_netsoc_wdata_converter_converter_source_ready;
assign soc_netsoc_wdata_converter_converter_source_first = soc_netsoc_wdata_converter_converter_sink_first;
assign soc_netsoc_wdata_converter_converter_source_last = soc_netsoc_wdata_converter_converter_sink_last;
assign soc_netsoc_wdata_converter_converter_source_payload_data = soc_netsoc_wdata_converter_converter_sink_payload_data;
assign soc_netsoc_wdata_converter_converter_source_payload_valid_token_count = 1'd1;
assign soc_netsoc_rdata_converter_converter_sink_valid = soc_netsoc_rdata_converter_sink_valid;
assign soc_netsoc_rdata_converter_converter_sink_first = soc_netsoc_rdata_converter_sink_first;
assign soc_netsoc_rdata_converter_converter_sink_last = soc_netsoc_rdata_converter_sink_last;
assign soc_netsoc_rdata_converter_sink_ready = soc_netsoc_rdata_converter_converter_sink_ready;
assign soc_netsoc_rdata_converter_converter_sink_payload_data = {soc_netsoc_rdata_converter_sink_payload_data};
assign soc_netsoc_rdata_converter_source_valid = soc_netsoc_rdata_converter_source_source_valid;
assign soc_netsoc_rdata_converter_source_first = soc_netsoc_rdata_converter_source_source_first;
assign soc_netsoc_rdata_converter_source_last = soc_netsoc_rdata_converter_source_source_last;
assign soc_netsoc_rdata_converter_source_source_ready = soc_netsoc_rdata_converter_source_ready;
assign {soc_netsoc_rdata_converter_source_payload_data} = soc_netsoc_rdata_converter_source_source_payload_data;
assign soc_netsoc_rdata_converter_source_source_valid = soc_netsoc_rdata_converter_converter_source_valid;
assign soc_netsoc_rdata_converter_converter_source_ready = soc_netsoc_rdata_converter_source_source_ready;
assign soc_netsoc_rdata_converter_source_source_first = soc_netsoc_rdata_converter_converter_source_first;
assign soc_netsoc_rdata_converter_source_source_last = soc_netsoc_rdata_converter_converter_source_last;
assign soc_netsoc_rdata_converter_source_source_payload_data = soc_netsoc_rdata_converter_converter_source_payload_data;
assign soc_netsoc_rdata_converter_converter_source_valid = soc_netsoc_rdata_converter_converter_sink_valid;
assign soc_netsoc_rdata_converter_converter_sink_ready = soc_netsoc_rdata_converter_converter_source_ready;
assign soc_netsoc_rdata_converter_converter_source_first = soc_netsoc_rdata_converter_converter_sink_first;
assign soc_netsoc_rdata_converter_converter_source_last = soc_netsoc_rdata_converter_converter_sink_last;
assign soc_netsoc_rdata_converter_converter_source_payload_data = soc_netsoc_rdata_converter_converter_sink_payload_data;
assign soc_netsoc_rdata_converter_converter_source_payload_valid_token_count = 1'd1;
always @(*) begin
soc_netsoc_count_litedramwishbone2native_next_value <= 1'd0;
soc_netsoc_port_cmd_valid <= 1'd0;
soc_netsoc_count_litedramwishbone2native_next_value_ce <= 1'd0;
soc_netsoc_ack <= 1'd0;
soc_netsoc_port_cmd_payload_we <= 1'd0;
vns_litedramwishbone2native_next_state <= 2'd0;
soc_netsoc_port_cmd_payload_addr <= 24'd0;
vns_litedramwishbone2native_next_state <= vns_litedramwishbone2native_state;
case (vns_litedramwishbone2native_state)
1'd1: begin
if (soc_netsoc_wdata_converter_sink_ready) begin
soc_netsoc_ack <= 1'd1;
vns_litedramwishbone2native_next_state <= 1'd0;
end
end
2'd2: begin
if (soc_netsoc_rdata_converter_source_valid) begin
soc_netsoc_ack <= 1'd1;
vns_litedramwishbone2native_next_state <= 1'd0;
end
end
default: begin
soc_netsoc_port_cmd_valid <= (soc_netsoc_cyc & soc_netsoc_stb);
soc_netsoc_port_cmd_payload_we <= soc_netsoc_we;
soc_netsoc_port_cmd_payload_addr <= (((soc_netsoc_adr * 1'd1) + soc_netsoc_count) - 1'd0);
if ((soc_netsoc_port_cmd_valid & soc_netsoc_port_cmd_ready)) begin
soc_netsoc_count_litedramwishbone2native_next_value <= (soc_netsoc_count + 1'd1);
soc_netsoc_count_litedramwishbone2native_next_value_ce <= 1'd1;
if ((soc_netsoc_count == 1'd0)) begin
soc_netsoc_count_litedramwishbone2native_next_value <= 1'd0;
soc_netsoc_count_litedramwishbone2native_next_value_ce <= 1'd1;
if (soc_netsoc_we) begin
vns_litedramwishbone2native_next_state <= 1'd1;
end else begin
vns_litedramwishbone2native_next_state <= 2'd2;
end
end
end
end
endcase
end
assign eth_rx_clk = eth_clocks_rx;
assign eth_tx_clk = eth_clocks_tx;
assign soc_reset0 = (soc_reset_storage | soc_reset1);
assign eth_rst_n = (~soc_reset0);
assign soc_counter_done = (soc_counter == 9'd256);
assign soc_counter_ce = (~soc_counter_done);
assign soc_reset1 = (~soc_counter_done);
assign soc_liteethphymiitx_converter_sink_valid = soc_liteethphymiitx_sink_sink_valid;
assign soc_liteethphymiitx_converter_sink_payload_data = soc_liteethphymiitx_sink_sink_payload_data;
assign soc_liteethphymiitx_sink_sink_ready = soc_liteethphymiitx_converter_sink_ready;
assign soc_liteethphymiitx_converter_source_ready = 1'd1;
assign soc_liteethphymiitx_converter_converter_sink_valid = soc_liteethphymiitx_converter_sink_valid;
assign soc_liteethphymiitx_converter_converter_sink_first = soc_liteethphymiitx_converter_sink_first;
assign soc_liteethphymiitx_converter_converter_sink_last = soc_liteethphymiitx_converter_sink_last;
assign soc_liteethphymiitx_converter_sink_ready = soc_liteethphymiitx_converter_converter_sink_ready;
always @(*) begin
soc_liteethphymiitx_converter_converter_sink_payload_data <= 8'd0;
soc_liteethphymiitx_converter_converter_sink_payload_data[3:0] <= soc_liteethphymiitx_converter_sink_payload_data[3:0];
soc_liteethphymiitx_converter_converter_sink_payload_data[7:4] <= soc_liteethphymiitx_converter_sink_payload_data[7:4];
end
assign soc_liteethphymiitx_converter_source_valid = soc_liteethphymiitx_converter_source_source_valid;
assign soc_liteethphymiitx_converter_source_first = soc_liteethphymiitx_converter_source_source_first;
assign soc_liteethphymiitx_converter_source_last = soc_liteethphymiitx_converter_source_source_last;
assign soc_liteethphymiitx_converter_source_source_ready = soc_liteethphymiitx_converter_source_ready;
assign {soc_liteethphymiitx_converter_source_payload_data} = soc_liteethphymiitx_converter_source_source_payload_data;
assign soc_liteethphymiitx_converter_source_source_valid = soc_liteethphymiitx_converter_converter_source_valid;
assign soc_liteethphymiitx_converter_converter_source_ready = soc_liteethphymiitx_converter_source_source_ready;
assign soc_liteethphymiitx_converter_source_source_first = soc_liteethphymiitx_converter_converter_source_first;
assign soc_liteethphymiitx_converter_source_source_last = soc_liteethphymiitx_converter_converter_source_last;
assign soc_liteethphymiitx_converter_source_source_payload_data = soc_liteethphymiitx_converter_converter_source_payload_data;
assign soc_liteethphymiitx_converter_converter_first = (soc_liteethphymiitx_converter_converter_mux == 1'd0);
assign soc_liteethphymiitx_converter_converter_last = (soc_liteethphymiitx_converter_converter_mux == 1'd1);
assign soc_liteethphymiitx_converter_converter_source_valid = soc_liteethphymiitx_converter_converter_sink_valid;
assign soc_liteethphymiitx_converter_converter_source_first = (soc_liteethphymiitx_converter_converter_sink_first & soc_liteethphymiitx_converter_converter_first);
assign soc_liteethphymiitx_converter_converter_source_last = (soc_liteethphymiitx_converter_converter_sink_last & soc_liteethphymiitx_converter_converter_last);
assign soc_liteethphymiitx_converter_converter_sink_ready = (soc_liteethphymiitx_converter_converter_last & soc_liteethphymiitx_converter_converter_source_ready);
always @(*) begin
soc_liteethphymiitx_converter_converter_source_payload_data <= 4'd0;
case (soc_liteethphymiitx_converter_converter_mux)
1'd0: begin
soc_liteethphymiitx_converter_converter_source_payload_data <= soc_liteethphymiitx_converter_converter_sink_payload_data[3:0];
end
default: begin
soc_liteethphymiitx_converter_converter_source_payload_data <= soc_liteethphymiitx_converter_converter_sink_payload_data[7:4];
end
endcase
end
assign soc_liteethphymiitx_converter_converter_source_payload_valid_token_count = soc_liteethphymiitx_converter_converter_last;
assign soc_liteethphymiirx_converter_sink_last = (~eth_rx_dv);
assign soc_liteethphymiirx_source_source_valid = soc_liteethphymiirx_converter_source_valid;
assign soc_liteethphymiirx_converter_source_ready = soc_liteethphymiirx_source_source_ready;
assign soc_liteethphymiirx_source_source_first = soc_liteethphymiirx_converter_source_first;
assign soc_liteethphymiirx_source_source_last = soc_liteethphymiirx_converter_source_last;
assign soc_liteethphymiirx_source_source_payload_data = soc_liteethphymiirx_converter_source_payload_data;
assign soc_liteethphymiirx_converter_converter_sink_valid = soc_liteethphymiirx_converter_sink_valid;
assign soc_liteethphymiirx_converter_converter_sink_first = soc_liteethphymiirx_converter_sink_first;
assign soc_liteethphymiirx_converter_converter_sink_last = soc_liteethphymiirx_converter_sink_last;
assign soc_liteethphymiirx_converter_sink_ready = soc_liteethphymiirx_converter_converter_sink_ready;
assign soc_liteethphymiirx_converter_converter_sink_payload_data = {soc_liteethphymiirx_converter_sink_payload_data};
assign soc_liteethphymiirx_converter_source_valid = soc_liteethphymiirx_converter_source_source_valid;
assign soc_liteethphymiirx_converter_source_first = soc_liteethphymiirx_converter_source_source_first;
assign soc_liteethphymiirx_converter_source_last = soc_liteethphymiirx_converter_source_source_last;
assign soc_liteethphymiirx_converter_source_source_ready = soc_liteethphymiirx_converter_source_ready;
always @(*) begin
soc_liteethphymiirx_converter_source_payload_data <= 8'd0;
soc_liteethphymiirx_converter_source_payload_data[3:0] <= soc_liteethphymiirx_converter_source_source_payload_data[3:0];
soc_liteethphymiirx_converter_source_payload_data[7:4] <= soc_liteethphymiirx_converter_source_source_payload_data[7:4];
end
assign soc_liteethphymiirx_converter_source_source_valid = soc_liteethphymiirx_converter_converter_source_valid;
assign soc_liteethphymiirx_converter_converter_source_ready = soc_liteethphymiirx_converter_source_source_ready;
assign soc_liteethphymiirx_converter_source_source_first = soc_liteethphymiirx_converter_converter_source_first;
assign soc_liteethphymiirx_converter_source_source_last = soc_liteethphymiirx_converter_converter_source_last;
assign soc_liteethphymiirx_converter_source_source_payload_data = soc_liteethphymiirx_converter_converter_source_payload_data;
assign soc_liteethphymiirx_converter_converter_sink_ready = ((~soc_liteethphymiirx_converter_converter_strobe_all) | soc_liteethphymiirx_converter_converter_source_ready);
assign soc_liteethphymiirx_converter_converter_source_valid = soc_liteethphymiirx_converter_converter_strobe_all;
assign soc_liteethphymiirx_converter_converter_load_part = (soc_liteethphymiirx_converter_converter_sink_valid & soc_liteethphymiirx_converter_converter_sink_ready);
assign eth_mdc = soc_storage[0];
assign soc_data_oe = soc_storage[1];
assign soc_data_w = soc_storage[2];
assign soc_tx_cdc_sink_valid = soc_source_valid;
assign soc_source_ready = soc_tx_cdc_sink_ready;
assign soc_tx_cdc_sink_first = soc_source_first;
assign soc_tx_cdc_sink_last = soc_source_last;
assign soc_tx_cdc_sink_payload_data = soc_source_payload_data;
assign soc_tx_cdc_sink_payload_last_be = soc_source_payload_last_be;
assign soc_tx_cdc_sink_payload_error = soc_source_payload_error;
assign soc_sink_valid = soc_rx_cdc_source_valid;
assign soc_rx_cdc_source_ready = soc_sink_ready;
assign soc_sink_first = soc_rx_cdc_source_first;
assign soc_sink_last = soc_rx_cdc_source_last;
assign soc_sink_payload_data = soc_rx_cdc_source_payload_data;
assign soc_sink_payload_last_be = soc_rx_cdc_source_payload_last_be;
assign soc_sink_payload_error = soc_rx_cdc_source_payload_error;
assign soc_ps_preamble_error_i = soc_preamble_checker_error;
assign soc_ps_crc_error_i = soc_crc32_checker_error;
always @(*) begin
soc_tx_gap_inserter_source_first <= 1'd0;
soc_tx_gap_inserter_source_last <= 1'd0;
soc_tx_gap_inserter_source_payload_data <= 8'd0;
soc_tx_gap_inserter_source_payload_last_be <= 1'd0;
soc_tx_gap_inserter_source_payload_error <= 1'd0;
soc_tx_gap_inserter_counter_reset <= 1'd0;
soc_tx_gap_inserter_counter_ce <= 1'd0;
soc_tx_gap_inserter_sink_ready <= 1'd0;
vns_liteethmacgap_next_state <= 1'd0;
soc_tx_gap_inserter_source_valid <= 1'd0;
vns_liteethmacgap_next_state <= vns_liteethmacgap_state;
case (vns_liteethmacgap_state)
1'd1: begin
soc_tx_gap_inserter_counter_ce <= 1'd1;
if ((soc_tx_gap_inserter_counter == 4'd11)) begin
vns_liteethmacgap_next_state <= 1'd0;
end
end
default: begin
soc_tx_gap_inserter_counter_reset <= 1'd1;
soc_tx_gap_inserter_source_valid <= soc_tx_gap_inserter_sink_valid;
soc_tx_gap_inserter_sink_ready <= soc_tx_gap_inserter_source_ready;
soc_tx_gap_inserter_source_first <= soc_tx_gap_inserter_sink_first;
soc_tx_gap_inserter_source_last <= soc_tx_gap_inserter_sink_last;
soc_tx_gap_inserter_source_payload_data <= soc_tx_gap_inserter_sink_payload_data;
soc_tx_gap_inserter_source_payload_last_be <= soc_tx_gap_inserter_sink_payload_last_be;
soc_tx_gap_inserter_source_payload_error <= soc_tx_gap_inserter_sink_payload_error;
if (((soc_tx_gap_inserter_sink_valid & soc_tx_gap_inserter_sink_last) & soc_tx_gap_inserter_sink_ready)) begin
vns_liteethmacgap_next_state <= 1'd1;
end
end
endcase
end
assign soc_preamble_inserter_source_payload_last_be = soc_preamble_inserter_sink_payload_last_be;
always @(*) begin
soc_preamble_inserter_source_payload_error <= 1'd0;
vns_liteethmacpreambleinserter_next_state <= 2'd0;
soc_preamble_inserter_clr_cnt <= 1'd0;
soc_preamble_inserter_sink_ready <= 1'd0;
soc_preamble_inserter_inc_cnt <= 1'd0;
soc_preamble_inserter_source_valid <= 1'd0;
soc_preamble_inserter_source_first <= 1'd0;
soc_preamble_inserter_source_last <= 1'd0;
soc_preamble_inserter_source_payload_data <= 8'd0;
soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_sink_payload_data;
vns_liteethmacpreambleinserter_next_state <= vns_liteethmacpreambleinserter_state;
case (vns_liteethmacpreambleinserter_state)
1'd1: begin
soc_preamble_inserter_source_valid <= 1'd1;
case (soc_preamble_inserter_cnt)
1'd0: begin
soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[7:0];
end
1'd1: begin
soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[15:8];
end
2'd2: begin
soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[23:16];
end
2'd3: begin
soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[31:24];
end
3'd4: begin
soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[39:32];
end
3'd5: begin
soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[47:40];
end
3'd6: begin
soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[55:48];
end
default: begin
soc_preamble_inserter_source_payload_data <= soc_preamble_inserter_preamble[63:56];
end
endcase
if ((soc_preamble_inserter_cnt == 3'd7)) begin
if (soc_preamble_inserter_source_ready) begin
vns_liteethmacpreambleinserter_next_state <= 2'd2;
end
end else begin
soc_preamble_inserter_inc_cnt <= soc_preamble_inserter_source_ready;
end
end
2'd2: begin
soc_preamble_inserter_source_valid <= soc_preamble_inserter_sink_valid;
soc_preamble_inserter_sink_ready <= soc_preamble_inserter_source_ready;
soc_preamble_inserter_source_first <= soc_preamble_inserter_sink_first;
soc_preamble_inserter_source_last <= soc_preamble_inserter_sink_last;
soc_preamble_inserter_source_payload_error <= soc_preamble_inserter_sink_payload_error;
if (((soc_preamble_inserter_sink_valid & soc_preamble_inserter_sink_last) & soc_preamble_inserter_source_ready)) begin
vns_liteethmacpreambleinserter_next_state <= 1'd0;
end
end
default: begin
soc_preamble_inserter_sink_ready <= 1'd1;
soc_preamble_inserter_clr_cnt <= 1'd1;
if (soc_preamble_inserter_sink_valid) begin
soc_preamble_inserter_sink_ready <= 1'd0;
vns_liteethmacpreambleinserter_next_state <= 1'd1;
end
end
endcase
end
assign soc_preamble_checker_source_payload_data = soc_preamble_checker_sink_payload_data;
assign soc_preamble_checker_source_payload_last_be = soc_preamble_checker_sink_payload_last_be;
always @(*) begin
soc_preamble_checker_source_payload_error <= 1'd0;
soc_preamble_checker_error <= 1'd0;
soc_preamble_checker_source_valid <= 1'd0;
soc_preamble_checker_source_first <= 1'd0;
soc_preamble_checker_sink_ready <= 1'd0;
soc_preamble_checker_source_last <= 1'd0;
vns_liteethmacpreamblechecker_next_state <= 1'd0;
vns_liteethmacpreamblechecker_next_state <= vns_liteethmacpreamblechecker_state;
case (vns_liteethmacpreamblechecker_state)
1'd1: begin
soc_preamble_checker_source_valid <= soc_preamble_checker_sink_valid;
soc_preamble_checker_sink_ready <= soc_preamble_checker_source_ready;
soc_preamble_checker_source_first <= soc_preamble_checker_sink_first;
soc_preamble_checker_source_last <= soc_preamble_checker_sink_last;
soc_preamble_checker_source_payload_error <= soc_preamble_checker_sink_payload_error;
if (((soc_preamble_checker_source_valid & soc_preamble_checker_source_last) & soc_preamble_checker_source_ready)) begin
vns_liteethmacpreamblechecker_next_state <= 1'd0;
end
end
default: begin
soc_preamble_checker_sink_ready <= 1'd1;
if (((soc_preamble_checker_sink_valid & (~soc_preamble_checker_sink_last)) & (soc_preamble_checker_sink_payload_data == 8'd213))) begin
vns_liteethmacpreamblechecker_next_state <= 1'd1;
end
if ((soc_preamble_checker_sink_valid & soc_preamble_checker_sink_last)) begin
soc_preamble_checker_error <= 1'd1;
end
end
endcase
end
assign soc_crc32_inserter_cnt_done = (soc_crc32_inserter_cnt == 1'd0);
assign soc_crc32_inserter_data1 = soc_crc32_inserter_data0;
assign soc_crc32_inserter_last = soc_crc32_inserter_reg;
assign soc_crc32_inserter_value = (~{soc_crc32_inserter_reg[0], soc_crc32_inserter_reg[1], soc_crc32_inserter_reg[2], soc_crc32_inserter_reg[3], soc_crc32_inserter_reg[4], soc_crc32_inserter_reg[5], soc_crc32_inserter_reg[6], soc_crc32_inserter_reg[7], soc_crc32_inserter_reg[8], soc_crc32_inserter_reg[9], soc_crc32_inserter_reg[10], soc_crc32_inserter_reg[11], soc_crc32_inserter_reg[12], soc_crc32_inserter_reg[13], soc_crc32_inserter_reg[14], soc_crc32_inserter_reg[15], soc_crc32_inserter_reg[16], soc_crc32_inserter_reg[17], soc_crc32_inserter_reg[18], soc_crc32_inserter_reg[19], soc_crc32_inserter_reg[20], soc_crc32_inserter_reg[21], soc_crc32_inserter_reg[22], soc_crc32_inserter_reg[23], soc_crc32_inserter_reg[24], soc_crc32_inserter_reg[25], soc_crc32_inserter_reg[26], soc_crc32_inserter_reg[27], soc_crc32_inserter_reg[28], soc_crc32_inserter_reg[29], soc_crc32_inserter_reg[30], soc_crc32_inserter_reg[31]});
assign soc_crc32_inserter_error = (soc_crc32_inserter_next != 32'd3338984827);
always @(*) begin
soc_crc32_inserter_next <= 32'd0;
soc_crc32_inserter_next[0] <= (((soc_crc32_inserter_last[24] ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[1] <= (((((((soc_crc32_inserter_last[25] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[2] <= (((((((((soc_crc32_inserter_last[26] ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[3] <= (((((((soc_crc32_inserter_last[27] ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]);
soc_crc32_inserter_next[4] <= (((((((((soc_crc32_inserter_last[28] ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[5] <= (((((((((((((soc_crc32_inserter_last[29] ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[6] <= (((((((((((soc_crc32_inserter_last[30] ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]);
soc_crc32_inserter_next[7] <= (((((((((soc_crc32_inserter_last[31] ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[8] <= ((((((((soc_crc32_inserter_last[0] ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[9] <= ((((((((soc_crc32_inserter_last[1] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_data1[6]);
soc_crc32_inserter_next[10] <= ((((((((soc_crc32_inserter_last[2] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[11] <= ((((((((soc_crc32_inserter_last[3] ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[12] <= ((((((((((((soc_crc32_inserter_last[4] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[13] <= ((((((((((((soc_crc32_inserter_last[5] ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]);
soc_crc32_inserter_next[14] <= ((((((((((soc_crc32_inserter_last[6] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]);
soc_crc32_inserter_next[15] <= ((((((((soc_crc32_inserter_last[7] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]);
soc_crc32_inserter_next[16] <= ((((((soc_crc32_inserter_last[8] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[17] <= ((((((soc_crc32_inserter_last[9] ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_data1[6]);
soc_crc32_inserter_next[18] <= ((((((soc_crc32_inserter_last[10] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]);
soc_crc32_inserter_next[19] <= ((((soc_crc32_inserter_last[11] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]);
soc_crc32_inserter_next[20] <= ((soc_crc32_inserter_last[12] ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]);
soc_crc32_inserter_next[21] <= ((soc_crc32_inserter_last[13] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]);
soc_crc32_inserter_next[22] <= ((soc_crc32_inserter_last[14] ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[23] <= ((((((soc_crc32_inserter_last[15] ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_data1[6]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[24] <= ((((((soc_crc32_inserter_last[16] ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]);
soc_crc32_inserter_next[25] <= ((((soc_crc32_inserter_last[17] ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]);
soc_crc32_inserter_next[26] <= ((((((((soc_crc32_inserter_last[18] ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]) ^ soc_crc32_inserter_last[24]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_data1[7]);
soc_crc32_inserter_next[27] <= ((((((((soc_crc32_inserter_last[19] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]) ^ soc_crc32_inserter_last[25]) ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_data1[6]);
soc_crc32_inserter_next[28] <= ((((((soc_crc32_inserter_last[20] ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]) ^ soc_crc32_inserter_last[26]) ^ soc_crc32_inserter_data1[5]);
soc_crc32_inserter_next[29] <= ((((((soc_crc32_inserter_last[21] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[30]) ^ soc_crc32_inserter_data1[1]) ^ soc_crc32_inserter_last[27]) ^ soc_crc32_inserter_data1[4]);
soc_crc32_inserter_next[30] <= ((((soc_crc32_inserter_last[22] ^ soc_crc32_inserter_last[31]) ^ soc_crc32_inserter_data1[0]) ^ soc_crc32_inserter_last[28]) ^ soc_crc32_inserter_data1[3]);
soc_crc32_inserter_next[31] <= ((soc_crc32_inserter_last[23] ^ soc_crc32_inserter_last[29]) ^ soc_crc32_inserter_data1[2]);
end
always @(*) begin
soc_crc32_inserter_source_first <= 1'd0;
soc_crc32_inserter_source_last <= 1'd0;
soc_crc32_inserter_source_payload_data <= 8'd0;
soc_crc32_inserter_source_payload_last_be <= 1'd0;
soc_crc32_inserter_source_payload_error <= 1'd0;
soc_crc32_inserter_data0 <= 8'd0;
vns_liteethmaccrc32inserter_next_state <= 2'd0;
soc_crc32_inserter_is_ongoing0 <= 1'd0;
soc_crc32_inserter_sink_ready <= 1'd0;
soc_crc32_inserter_is_ongoing1 <= 1'd0;
soc_crc32_inserter_ce <= 1'd0;
soc_crc32_inserter_reset <= 1'd0;
soc_crc32_inserter_source_valid <= 1'd0;
vns_liteethmaccrc32inserter_next_state <= vns_liteethmaccrc32inserter_state;
case (vns_liteethmaccrc32inserter_state)
1'd1: begin
soc_crc32_inserter_ce <= (soc_crc32_inserter_sink_valid & soc_crc32_inserter_source_ready);
soc_crc32_inserter_data0 <= soc_crc32_inserter_sink_payload_data;
soc_crc32_inserter_source_valid <= soc_crc32_inserter_sink_valid;
soc_crc32_inserter_sink_ready <= soc_crc32_inserter_source_ready;
soc_crc32_inserter_source_first <= soc_crc32_inserter_sink_first;
soc_crc32_inserter_source_last <= soc_crc32_inserter_sink_last;
soc_crc32_inserter_source_payload_data <= soc_crc32_inserter_sink_payload_data;
soc_crc32_inserter_source_payload_last_be <= soc_crc32_inserter_sink_payload_last_be;
soc_crc32_inserter_source_payload_error <= soc_crc32_inserter_sink_payload_error;
soc_crc32_inserter_source_last <= 1'd0;
if (((soc_crc32_inserter_sink_valid & soc_crc32_inserter_sink_last) & soc_crc32_inserter_source_ready)) begin
vns_liteethmaccrc32inserter_next_state <= 2'd2;
end
end
2'd2: begin
soc_crc32_inserter_source_valid <= 1'd1;
case (soc_crc32_inserter_cnt)
1'd0: begin
soc_crc32_inserter_source_payload_data <= soc_crc32_inserter_value[31:24];
end
1'd1: begin
soc_crc32_inserter_source_payload_data <= soc_crc32_inserter_value[23:16];
end
2'd2: begin
soc_crc32_inserter_source_payload_data <= soc_crc32_inserter_value[15:8];
end
default: begin
soc_crc32_inserter_source_payload_data <= soc_crc32_inserter_value[7:0];
end
endcase
if (soc_crc32_inserter_cnt_done) begin
soc_crc32_inserter_source_last <= 1'd1;
if (soc_crc32_inserter_source_ready) begin
vns_liteethmaccrc32inserter_next_state <= 1'd0;
end
end
soc_crc32_inserter_is_ongoing1 <= 1'd1;
end
default: begin
soc_crc32_inserter_reset <= 1'd1;
soc_crc32_inserter_sink_ready <= 1'd1;
if (soc_crc32_inserter_sink_valid) begin
soc_crc32_inserter_sink_ready <= 1'd0;
vns_liteethmaccrc32inserter_next_state <= 1'd1;
end
soc_crc32_inserter_is_ongoing0 <= 1'd1;
end
endcase
end
assign soc_crc32_checker_fifo_full = (soc_crc32_checker_syncfifo_level == 3'd4);
assign soc_crc32_checker_fifo_in = (soc_crc32_checker_sink_sink_valid & ((~soc_crc32_checker_fifo_full) | soc_crc32_checker_fifo_out));
assign soc_crc32_checker_fifo_out = (soc_crc32_checker_source_source_valid & soc_crc32_checker_source_source_ready);
assign soc_crc32_checker_syncfifo_sink_first = soc_crc32_checker_sink_sink_first;
assign soc_crc32_checker_syncfifo_sink_last = soc_crc32_checker_sink_sink_last;
assign soc_crc32_checker_syncfifo_sink_payload_data = soc_crc32_checker_sink_sink_payload_data;
assign soc_crc32_checker_syncfifo_sink_payload_last_be = soc_crc32_checker_sink_sink_payload_last_be;
assign soc_crc32_checker_syncfifo_sink_payload_error = soc_crc32_checker_sink_sink_payload_error;
always @(*) begin
soc_crc32_checker_syncfifo_sink_valid <= 1'd0;
soc_crc32_checker_syncfifo_sink_valid <= soc_crc32_checker_sink_sink_valid;
soc_crc32_checker_syncfifo_sink_valid <= soc_crc32_checker_fifo_in;
end
always @(*) begin
soc_crc32_checker_sink_sink_ready <= 1'd0;
soc_crc32_checker_sink_sink_ready <= soc_crc32_checker_syncfifo_sink_ready;
soc_crc32_checker_sink_sink_ready <= soc_crc32_checker_fifo_in;
end
assign soc_crc32_checker_source_source_valid = (soc_crc32_checker_sink_sink_valid & soc_crc32_checker_fifo_full);
assign soc_crc32_checker_source_source_last = soc_crc32_checker_sink_sink_last;
assign soc_crc32_checker_syncfifo_source_ready = soc_crc32_checker_fifo_out;
assign soc_crc32_checker_source_source_payload_data = soc_crc32_checker_syncfifo_source_payload_data;
assign soc_crc32_checker_source_source_payload_last_be = soc_crc32_checker_syncfifo_source_payload_last_be;
always @(*) begin
soc_crc32_checker_source_source_payload_error <= 1'd0;
soc_crc32_checker_source_source_payload_error <= soc_crc32_checker_syncfifo_source_payload_error;
soc_crc32_checker_source_source_payload_error <= (soc_crc32_checker_sink_sink_payload_error | soc_crc32_checker_crc_error);
end
assign soc_crc32_checker_error = ((soc_crc32_checker_source_source_valid & soc_crc32_checker_source_source_last) & soc_crc32_checker_crc_error);
assign soc_crc32_checker_crc_data0 = soc_crc32_checker_sink_sink_payload_data;
assign soc_crc32_checker_crc_data1 = soc_crc32_checker_crc_data0;
assign soc_crc32_checker_crc_last = soc_crc32_checker_crc_reg;
assign soc_crc32_checker_crc_value = (~{soc_crc32_checker_crc_reg[0], soc_crc32_checker_crc_reg[1], soc_crc32_checker_crc_reg[2], soc_crc32_checker_crc_reg[3], soc_crc32_checker_crc_reg[4], soc_crc32_checker_crc_reg[5], soc_crc32_checker_crc_reg[6], soc_crc32_checker_crc_reg[7], soc_crc32_checker_crc_reg[8], soc_crc32_checker_crc_reg[9], soc_crc32_checker_crc_reg[10], soc_crc32_checker_crc_reg[11], soc_crc32_checker_crc_reg[12], soc_crc32_checker_crc_reg[13], soc_crc32_checker_crc_reg[14], soc_crc32_checker_crc_reg[15], soc_crc32_checker_crc_reg[16], soc_crc32_checker_crc_reg[17], soc_crc32_checker_crc_reg[18], soc_crc32_checker_crc_reg[19], soc_crc32_checker_crc_reg[20], soc_crc32_checker_crc_reg[21], soc_crc32_checker_crc_reg[22], soc_crc32_checker_crc_reg[23], soc_crc32_checker_crc_reg[24], soc_crc32_checker_crc_reg[25], soc_crc32_checker_crc_reg[26], soc_crc32_checker_crc_reg[27], soc_crc32_checker_crc_reg[28], soc_crc32_checker_crc_reg[29], soc_crc32_checker_crc_reg[30], soc_crc32_checker_crc_reg[31]});
assign soc_crc32_checker_crc_error = (soc_crc32_checker_crc_next != 32'd3338984827);
always @(*) begin
soc_crc32_checker_crc_next <= 32'd0;
soc_crc32_checker_crc_next[0] <= (((soc_crc32_checker_crc_last[24] ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[1] <= (((((((soc_crc32_checker_crc_last[25] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[2] <= (((((((((soc_crc32_checker_crc_last[26] ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[3] <= (((((((soc_crc32_checker_crc_last[27] ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]);
soc_crc32_checker_crc_next[4] <= (((((((((soc_crc32_checker_crc_last[28] ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[5] <= (((((((((((((soc_crc32_checker_crc_last[29] ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[6] <= (((((((((((soc_crc32_checker_crc_last[30] ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]);
soc_crc32_checker_crc_next[7] <= (((((((((soc_crc32_checker_crc_last[31] ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[8] <= ((((((((soc_crc32_checker_crc_last[0] ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[9] <= ((((((((soc_crc32_checker_crc_last[1] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_data1[6]);
soc_crc32_checker_crc_next[10] <= ((((((((soc_crc32_checker_crc_last[2] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[11] <= ((((((((soc_crc32_checker_crc_last[3] ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[12] <= ((((((((((((soc_crc32_checker_crc_last[4] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[13] <= ((((((((((((soc_crc32_checker_crc_last[5] ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]);
soc_crc32_checker_crc_next[14] <= ((((((((((soc_crc32_checker_crc_last[6] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]);
soc_crc32_checker_crc_next[15] <= ((((((((soc_crc32_checker_crc_last[7] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]);
soc_crc32_checker_crc_next[16] <= ((((((soc_crc32_checker_crc_last[8] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[17] <= ((((((soc_crc32_checker_crc_last[9] ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_data1[6]);
soc_crc32_checker_crc_next[18] <= ((((((soc_crc32_checker_crc_last[10] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]);
soc_crc32_checker_crc_next[19] <= ((((soc_crc32_checker_crc_last[11] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]);
soc_crc32_checker_crc_next[20] <= ((soc_crc32_checker_crc_last[12] ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]);
soc_crc32_checker_crc_next[21] <= ((soc_crc32_checker_crc_last[13] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]);
soc_crc32_checker_crc_next[22] <= ((soc_crc32_checker_crc_last[14] ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[23] <= ((((((soc_crc32_checker_crc_last[15] ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_data1[6]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[24] <= ((((((soc_crc32_checker_crc_last[16] ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]);
soc_crc32_checker_crc_next[25] <= ((((soc_crc32_checker_crc_last[17] ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]);
soc_crc32_checker_crc_next[26] <= ((((((((soc_crc32_checker_crc_last[18] ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]) ^ soc_crc32_checker_crc_last[24]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_data1[7]);
soc_crc32_checker_crc_next[27] <= ((((((((soc_crc32_checker_crc_last[19] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]) ^ soc_crc32_checker_crc_last[25]) ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_data1[6]);
soc_crc32_checker_crc_next[28] <= ((((((soc_crc32_checker_crc_last[20] ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]) ^ soc_crc32_checker_crc_last[26]) ^ soc_crc32_checker_crc_data1[5]);
soc_crc32_checker_crc_next[29] <= ((((((soc_crc32_checker_crc_last[21] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[30]) ^ soc_crc32_checker_crc_data1[1]) ^ soc_crc32_checker_crc_last[27]) ^ soc_crc32_checker_crc_data1[4]);
soc_crc32_checker_crc_next[30] <= ((((soc_crc32_checker_crc_last[22] ^ soc_crc32_checker_crc_last[31]) ^ soc_crc32_checker_crc_data1[0]) ^ soc_crc32_checker_crc_last[28]) ^ soc_crc32_checker_crc_data1[3]);
soc_crc32_checker_crc_next[31] <= ((soc_crc32_checker_crc_last[23] ^ soc_crc32_checker_crc_last[29]) ^ soc_crc32_checker_crc_data1[2]);
end
assign soc_crc32_checker_syncfifo_syncfifo_din = {soc_crc32_checker_syncfifo_fifo_in_last, soc_crc32_checker_syncfifo_fifo_in_first, soc_crc32_checker_syncfifo_fifo_in_payload_error, soc_crc32_checker_syncfifo_fifo_in_payload_last_be, soc_crc32_checker_syncfifo_fifo_in_payload_data};
assign {soc_crc32_checker_syncfifo_fifo_out_last, soc_crc32_checker_syncfifo_fifo_out_first, soc_crc32_checker_syncfifo_fifo_out_payload_error, soc_crc32_checker_syncfifo_fifo_out_payload_last_be, soc_crc32_checker_syncfifo_fifo_out_payload_data} = soc_crc32_checker_syncfifo_syncfifo_dout;
assign soc_crc32_checker_syncfifo_sink_ready = soc_crc32_checker_syncfifo_syncfifo_writable;
assign soc_crc32_checker_syncfifo_syncfifo_we = soc_crc32_checker_syncfifo_sink_valid;
assign soc_crc32_checker_syncfifo_fifo_in_first = soc_crc32_checker_syncfifo_sink_first;
assign soc_crc32_checker_syncfifo_fifo_in_last = soc_crc32_checker_syncfifo_sink_last;
assign soc_crc32_checker_syncfifo_fifo_in_payload_data = soc_crc32_checker_syncfifo_sink_payload_data;
assign soc_crc32_checker_syncfifo_fifo_in_payload_last_be = soc_crc32_checker_syncfifo_sink_payload_last_be;
assign soc_crc32_checker_syncfifo_fifo_in_payload_error = soc_crc32_checker_syncfifo_sink_payload_error;
assign soc_crc32_checker_syncfifo_source_valid = soc_crc32_checker_syncfifo_syncfifo_readable;
assign soc_crc32_checker_syncfifo_source_first = soc_crc32_checker_syncfifo_fifo_out_first;
assign soc_crc32_checker_syncfifo_source_last = soc_crc32_checker_syncfifo_fifo_out_last;
assign soc_crc32_checker_syncfifo_source_payload_data = soc_crc32_checker_syncfifo_fifo_out_payload_data;
assign soc_crc32_checker_syncfifo_source_payload_last_be = soc_crc32_checker_syncfifo_fifo_out_payload_last_be;
assign soc_crc32_checker_syncfifo_source_payload_error = soc_crc32_checker_syncfifo_fifo_out_payload_error;
assign soc_crc32_checker_syncfifo_syncfifo_re = soc_crc32_checker_syncfifo_source_ready;
always @(*) begin
soc_crc32_checker_syncfifo_wrport_adr <= 3'd0;
if (soc_crc32_checker_syncfifo_replace) begin
soc_crc32_checker_syncfifo_wrport_adr <= (soc_crc32_checker_syncfifo_produce - 1'd1);
end else begin
soc_crc32_checker_syncfifo_wrport_adr <= soc_crc32_checker_syncfifo_produce;
end
end
assign soc_crc32_checker_syncfifo_wrport_dat_w = soc_crc32_checker_syncfifo_syncfifo_din;
assign soc_crc32_checker_syncfifo_wrport_we = (soc_crc32_checker_syncfifo_syncfifo_we & (soc_crc32_checker_syncfifo_syncfifo_writable | soc_crc32_checker_syncfifo_replace));
assign soc_crc32_checker_syncfifo_do_read = (soc_crc32_checker_syncfifo_syncfifo_readable & soc_crc32_checker_syncfifo_syncfifo_re);
assign soc_crc32_checker_syncfifo_rdport_adr = soc_crc32_checker_syncfifo_consume;
assign soc_crc32_checker_syncfifo_syncfifo_dout = soc_crc32_checker_syncfifo_rdport_dat_r;
assign soc_crc32_checker_syncfifo_syncfifo_writable = (soc_crc32_checker_syncfifo_level != 3'd5);
assign soc_crc32_checker_syncfifo_syncfifo_readable = (soc_crc32_checker_syncfifo_level != 1'd0);
always @(*) begin
soc_crc32_checker_crc_ce <= 1'd0;
vns_liteethmaccrc32checker_next_state <= 2'd0;
soc_crc32_checker_crc_reset <= 1'd0;
soc_crc32_checker_fifo_reset <= 1'd0;
vns_liteethmaccrc32checker_next_state <= vns_liteethmaccrc32checker_state;
case (vns_liteethmaccrc32checker_state)
1'd1: begin
if ((soc_crc32_checker_sink_sink_valid & soc_crc32_checker_sink_sink_ready)) begin
soc_crc32_checker_crc_ce <= 1'd1;
vns_liteethmaccrc32checker_next_state <= 2'd2;
end
end
2'd2: begin
if ((soc_crc32_checker_sink_sink_valid & soc_crc32_checker_sink_sink_ready)) begin
soc_crc32_checker_crc_ce <= 1'd1;
if (soc_crc32_checker_sink_sink_last) begin
vns_liteethmaccrc32checker_next_state <= 1'd0;
end
end
end
default: begin
soc_crc32_checker_crc_reset <= 1'd1;
soc_crc32_checker_fifo_reset <= 1'd1;
vns_liteethmaccrc32checker_next_state <= 1'd1;
end
endcase
end
assign soc_ps_preamble_error_o = (soc_ps_preamble_error_toggle_o ^ soc_ps_preamble_error_toggle_o_r);
assign soc_ps_crc_error_o = (soc_ps_crc_error_toggle_o ^ soc_ps_crc_error_toggle_o_r);
assign soc_padding_inserter_counter_done = (soc_padding_inserter_counter >= 6'd59);
always @(*) begin
soc_padding_inserter_source_valid <= 1'd0;
soc_padding_inserter_source_first <= 1'd0;
soc_padding_inserter_source_last <= 1'd0;
soc_padding_inserter_source_payload_data <= 8'd0;
soc_padding_inserter_source_payload_last_be <= 1'd0;
soc_padding_inserter_source_payload_error <= 1'd0;
vns_liteethmacpaddinginserter_next_state <= 1'd0;
soc_padding_inserter_counter_reset <= 1'd0;
soc_padding_inserter_sink_ready <= 1'd0;
soc_padding_inserter_counter_ce <= 1'd0;
vns_liteethmacpaddinginserter_next_state <= vns_liteethmacpaddinginserter_state;
case (vns_liteethmacpaddinginserter_state)
1'd1: begin
soc_padding_inserter_source_valid <= 1'd1;
soc_padding_inserter_source_last <= soc_padding_inserter_counter_done;
soc_padding_inserter_source_payload_data <= 1'd0;
if ((soc_padding_inserter_source_valid & soc_padding_inserter_source_ready)) begin
soc_padding_inserter_counter_ce <= 1'd1;
if (soc_padding_inserter_counter_done) begin
soc_padding_inserter_counter_reset <= 1'd1;
vns_liteethmacpaddinginserter_next_state <= 1'd0;
end
end
end
default: begin
soc_padding_inserter_source_valid <= soc_padding_inserter_sink_valid;
soc_padding_inserter_sink_ready <= soc_padding_inserter_source_ready;
soc_padding_inserter_source_first <= soc_padding_inserter_sink_first;
soc_padding_inserter_source_last <= soc_padding_inserter_sink_last;
soc_padding_inserter_source_payload_data <= soc_padding_inserter_sink_payload_data;
soc_padding_inserter_source_payload_last_be <= soc_padding_inserter_sink_payload_last_be;
soc_padding_inserter_source_payload_error <= soc_padding_inserter_sink_payload_error;
if ((soc_padding_inserter_source_valid & soc_padding_inserter_source_ready)) begin
soc_padding_inserter_counter_ce <= 1'd1;
if (soc_padding_inserter_sink_last) begin
if ((~soc_padding_inserter_counter_done)) begin
soc_padding_inserter_source_last <= 1'd0;
vns_liteethmacpaddinginserter_next_state <= 1'd1;
end else begin
soc_padding_inserter_counter_reset <= 1'd1;
end
end
end
end
endcase
end
assign soc_padding_checker_source_valid = soc_padding_checker_sink_valid;
assign soc_padding_checker_sink_ready = soc_padding_checker_source_ready;
assign soc_padding_checker_source_first = soc_padding_checker_sink_first;
assign soc_padding_checker_source_last = soc_padding_checker_sink_last;
assign soc_padding_checker_source_payload_data = soc_padding_checker_sink_payload_data;
assign soc_padding_checker_source_payload_last_be = soc_padding_checker_sink_payload_last_be;
assign soc_padding_checker_source_payload_error = soc_padding_checker_sink_payload_error;
assign soc_tx_last_be_source_valid = (soc_tx_last_be_sink_valid & soc_tx_last_be_ongoing);
assign soc_tx_last_be_source_last = soc_tx_last_be_sink_payload_last_be;
assign soc_tx_last_be_source_payload_data = soc_tx_last_be_sink_payload_data;
assign soc_tx_last_be_sink_ready = soc_tx_last_be_source_ready;
assign soc_rx_last_be_source_valid = soc_rx_last_be_sink_valid;
assign soc_rx_last_be_sink_ready = soc_rx_last_be_source_ready;
assign soc_rx_last_be_source_first = soc_rx_last_be_sink_first;
assign soc_rx_last_be_source_last = soc_rx_last_be_sink_last;
assign soc_rx_last_be_source_payload_data = soc_rx_last_be_sink_payload_data;
assign soc_rx_last_be_source_payload_error = soc_rx_last_be_sink_payload_error;
always @(*) begin
soc_rx_last_be_source_payload_last_be <= 1'd0;
soc_rx_last_be_source_payload_last_be <= soc_rx_last_be_sink_payload_last_be;
soc_rx_last_be_source_payload_last_be <= soc_rx_last_be_sink_last;
end
assign soc_tx_converter_converter_sink_valid = soc_tx_converter_sink_valid;
assign soc_tx_converter_converter_sink_first = soc_tx_converter_sink_first;
assign soc_tx_converter_converter_sink_last = soc_tx_converter_sink_last;
assign soc_tx_converter_sink_ready = soc_tx_converter_converter_sink_ready;
always @(*) begin
soc_tx_converter_converter_sink_payload_data <= 40'd0;
soc_tx_converter_converter_sink_payload_data[7:0] <= soc_tx_converter_sink_payload_data[7:0];
soc_tx_converter_converter_sink_payload_data[8] <= soc_tx_converter_sink_payload_last_be[0];
soc_tx_converter_converter_sink_payload_data[9] <= soc_tx_converter_sink_payload_error[0];
soc_tx_converter_converter_sink_payload_data[17:10] <= soc_tx_converter_sink_payload_data[15:8];
soc_tx_converter_converter_sink_payload_data[18] <= soc_tx_converter_sink_payload_last_be[1];
soc_tx_converter_converter_sink_payload_data[19] <= soc_tx_converter_sink_payload_error[1];
soc_tx_converter_converter_sink_payload_data[27:20] <= soc_tx_converter_sink_payload_data[23:16];
soc_tx_converter_converter_sink_payload_data[28] <= soc_tx_converter_sink_payload_last_be[2];
soc_tx_converter_converter_sink_payload_data[29] <= soc_tx_converter_sink_payload_error[2];
soc_tx_converter_converter_sink_payload_data[37:30] <= soc_tx_converter_sink_payload_data[31:24];
soc_tx_converter_converter_sink_payload_data[38] <= soc_tx_converter_sink_payload_last_be[3];
soc_tx_converter_converter_sink_payload_data[39] <= soc_tx_converter_sink_payload_error[3];
end
assign soc_tx_converter_source_valid = soc_tx_converter_source_source_valid;
assign soc_tx_converter_source_first = soc_tx_converter_source_source_first;
assign soc_tx_converter_source_last = soc_tx_converter_source_source_last;
assign soc_tx_converter_source_source_ready = soc_tx_converter_source_ready;
assign {soc_tx_converter_source_payload_error, soc_tx_converter_source_payload_last_be, soc_tx_converter_source_payload_data} = soc_tx_converter_source_source_payload_data;
assign soc_tx_converter_source_source_valid = soc_tx_converter_converter_source_valid;
assign soc_tx_converter_converter_source_ready = soc_tx_converter_source_source_ready;
assign soc_tx_converter_source_source_first = soc_tx_converter_converter_source_first;
assign soc_tx_converter_source_source_last = soc_tx_converter_converter_source_last;
assign soc_tx_converter_source_source_payload_data = soc_tx_converter_converter_source_payload_data;
assign soc_tx_converter_converter_first = (soc_tx_converter_converter_mux == 1'd0);
assign soc_tx_converter_converter_last = (soc_tx_converter_converter_mux == 2'd3);
assign soc_tx_converter_converter_source_valid = soc_tx_converter_converter_sink_valid;
assign soc_tx_converter_converter_source_first = (soc_tx_converter_converter_sink_first & soc_tx_converter_converter_first);
assign soc_tx_converter_converter_source_last = (soc_tx_converter_converter_sink_last & soc_tx_converter_converter_last);
assign soc_tx_converter_converter_sink_ready = (soc_tx_converter_converter_last & soc_tx_converter_converter_source_ready);
always @(*) begin
soc_tx_converter_converter_source_payload_data <= 10'd0;
case (soc_tx_converter_converter_mux)
1'd0: begin
soc_tx_converter_converter_source_payload_data <= soc_tx_converter_converter_sink_payload_data[9:0];
end
1'd1: begin
soc_tx_converter_converter_source_payload_data <= soc_tx_converter_converter_sink_payload_data[19:10];
end
2'd2: begin
soc_tx_converter_converter_source_payload_data <= soc_tx_converter_converter_sink_payload_data[29:20];
end
default: begin
soc_tx_converter_converter_source_payload_data <= soc_tx_converter_converter_sink_payload_data[39:30];
end
endcase
end
assign soc_tx_converter_converter_source_payload_valid_token_count = soc_tx_converter_converter_last;
assign soc_rx_converter_converter_sink_valid = soc_rx_converter_sink_valid;
assign soc_rx_converter_converter_sink_first = soc_rx_converter_sink_first;
assign soc_rx_converter_converter_sink_last = soc_rx_converter_sink_last;
assign soc_rx_converter_sink_ready = soc_rx_converter_converter_sink_ready;
assign soc_rx_converter_converter_sink_payload_data = {soc_rx_converter_sink_payload_error, soc_rx_converter_sink_payload_last_be, soc_rx_converter_sink_payload_data};
assign soc_rx_converter_source_valid = soc_rx_converter_source_source_valid;
assign soc_rx_converter_source_first = soc_rx_converter_source_source_first;
assign soc_rx_converter_source_last = soc_rx_converter_source_source_last;
assign soc_rx_converter_source_source_ready = soc_rx_converter_source_ready;
always @(*) begin
soc_rx_converter_source_payload_data <= 32'd0;
soc_rx_converter_source_payload_data[7:0] <= soc_rx_converter_source_source_payload_data[7:0];
soc_rx_converter_source_payload_data[15:8] <= soc_rx_converter_source_source_payload_data[17:10];
soc_rx_converter_source_payload_data[23:16] <= soc_rx_converter_source_source_payload_data[27:20];
soc_rx_converter_source_payload_data[31:24] <= soc_rx_converter_source_source_payload_data[37:30];
end
always @(*) begin
soc_rx_converter_source_payload_last_be <= 4'd0;
soc_rx_converter_source_payload_last_be[0] <= soc_rx_converter_source_source_payload_data[8];
soc_rx_converter_source_payload_last_be[1] <= soc_rx_converter_source_source_payload_data[18];
soc_rx_converter_source_payload_last_be[2] <= soc_rx_converter_source_source_payload_data[28];
soc_rx_converter_source_payload_last_be[3] <= soc_rx_converter_source_source_payload_data[38];
end
always @(*) begin
soc_rx_converter_source_payload_error <= 4'd0;
soc_rx_converter_source_payload_error[0] <= soc_rx_converter_source_source_payload_data[9];
soc_rx_converter_source_payload_error[1] <= soc_rx_converter_source_source_payload_data[19];
soc_rx_converter_source_payload_error[2] <= soc_rx_converter_source_source_payload_data[29];
soc_rx_converter_source_payload_error[3] <= soc_rx_converter_source_source_payload_data[39];
end
assign soc_rx_converter_source_source_valid = soc_rx_converter_converter_source_valid;
assign soc_rx_converter_converter_source_ready = soc_rx_converter_source_source_ready;
assign soc_rx_converter_source_source_first = soc_rx_converter_converter_source_first;
assign soc_rx_converter_source_source_last = soc_rx_converter_converter_source_last;
assign soc_rx_converter_source_source_payload_data = soc_rx_converter_converter_source_payload_data;
assign soc_rx_converter_converter_sink_ready = ((~soc_rx_converter_converter_strobe_all) | soc_rx_converter_converter_source_ready);
assign soc_rx_converter_converter_source_valid = soc_rx_converter_converter_strobe_all;
assign soc_rx_converter_converter_load_part = (soc_rx_converter_converter_sink_valid & soc_rx_converter_converter_sink_ready);
assign soc_tx_cdc_asyncfifo_din = {soc_tx_cdc_fifo_in_last, soc_tx_cdc_fifo_in_first, soc_tx_cdc_fifo_in_payload_error, soc_tx_cdc_fifo_in_payload_last_be, soc_tx_cdc_fifo_in_payload_data};
assign {soc_tx_cdc_fifo_out_last, soc_tx_cdc_fifo_out_first, soc_tx_cdc_fifo_out_payload_error, soc_tx_cdc_fifo_out_payload_last_be, soc_tx_cdc_fifo_out_payload_data} = soc_tx_cdc_asyncfifo_dout;
assign soc_tx_cdc_sink_ready = soc_tx_cdc_asyncfifo_writable;
assign soc_tx_cdc_asyncfifo_we = soc_tx_cdc_sink_valid;
assign soc_tx_cdc_fifo_in_first = soc_tx_cdc_sink_first;
assign soc_tx_cdc_fifo_in_last = soc_tx_cdc_sink_last;
assign soc_tx_cdc_fifo_in_payload_data = soc_tx_cdc_sink_payload_data;
assign soc_tx_cdc_fifo_in_payload_last_be = soc_tx_cdc_sink_payload_last_be;
assign soc_tx_cdc_fifo_in_payload_error = soc_tx_cdc_sink_payload_error;
assign soc_tx_cdc_source_valid = soc_tx_cdc_asyncfifo_readable;
assign soc_tx_cdc_source_first = soc_tx_cdc_fifo_out_first;
assign soc_tx_cdc_source_last = soc_tx_cdc_fifo_out_last;
assign soc_tx_cdc_source_payload_data = soc_tx_cdc_fifo_out_payload_data;
assign soc_tx_cdc_source_payload_last_be = soc_tx_cdc_fifo_out_payload_last_be;
assign soc_tx_cdc_source_payload_error = soc_tx_cdc_fifo_out_payload_error;
assign soc_tx_cdc_asyncfifo_re = soc_tx_cdc_source_ready;
assign soc_tx_cdc_graycounter0_ce = (soc_tx_cdc_asyncfifo_writable & soc_tx_cdc_asyncfifo_we);
assign soc_tx_cdc_graycounter1_ce = (soc_tx_cdc_asyncfifo_readable & soc_tx_cdc_asyncfifo_re);
assign soc_tx_cdc_asyncfifo_writable = (((soc_tx_cdc_graycounter0_q[6] == soc_tx_cdc_consume_wdomain[6]) | (soc_tx_cdc_graycounter0_q[5] == soc_tx_cdc_consume_wdomain[5])) | (soc_tx_cdc_graycounter0_q[4:0] != soc_tx_cdc_consume_wdomain[4:0]));
assign soc_tx_cdc_asyncfifo_readable = (soc_tx_cdc_graycounter1_q != soc_tx_cdc_produce_rdomain);
assign soc_tx_cdc_wrport_adr = soc_tx_cdc_graycounter0_q_binary[5:0];
assign soc_tx_cdc_wrport_dat_w = soc_tx_cdc_asyncfifo_din;
assign soc_tx_cdc_wrport_we = soc_tx_cdc_graycounter0_ce;
assign soc_tx_cdc_rdport_adr = soc_tx_cdc_graycounter1_q_next_binary[5:0];
assign soc_tx_cdc_asyncfifo_dout = soc_tx_cdc_rdport_dat_r;
always @(*) begin
soc_tx_cdc_graycounter0_q_next_binary <= 7'd0;
if (soc_tx_cdc_graycounter0_ce) begin
soc_tx_cdc_graycounter0_q_next_binary <= (soc_tx_cdc_graycounter0_q_binary + 1'd1);
end else begin
soc_tx_cdc_graycounter0_q_next_binary <= soc_tx_cdc_graycounter0_q_binary;
end
end
assign soc_tx_cdc_graycounter0_q_next = (soc_tx_cdc_graycounter0_q_next_binary ^ soc_tx_cdc_graycounter0_q_next_binary[6:1]);
always @(*) begin
soc_tx_cdc_graycounter1_q_next_binary <= 7'd0;
if (soc_tx_cdc_graycounter1_ce) begin
soc_tx_cdc_graycounter1_q_next_binary <= (soc_tx_cdc_graycounter1_q_binary + 1'd1);
end else begin
soc_tx_cdc_graycounter1_q_next_binary <= soc_tx_cdc_graycounter1_q_binary;
end
end
assign soc_tx_cdc_graycounter1_q_next = (soc_tx_cdc_graycounter1_q_next_binary ^ soc_tx_cdc_graycounter1_q_next_binary[6:1]);
assign soc_rx_cdc_asyncfifo_din = {soc_rx_cdc_fifo_in_last, soc_rx_cdc_fifo_in_first, soc_rx_cdc_fifo_in_payload_error, soc_rx_cdc_fifo_in_payload_last_be, soc_rx_cdc_fifo_in_payload_data};
assign {soc_rx_cdc_fifo_out_last, soc_rx_cdc_fifo_out_first, soc_rx_cdc_fifo_out_payload_error, soc_rx_cdc_fifo_out_payload_last_be, soc_rx_cdc_fifo_out_payload_data} = soc_rx_cdc_asyncfifo_dout;
assign soc_rx_cdc_sink_ready = soc_rx_cdc_asyncfifo_writable;
assign soc_rx_cdc_asyncfifo_we = soc_rx_cdc_sink_valid;
assign soc_rx_cdc_fifo_in_first = soc_rx_cdc_sink_first;
assign soc_rx_cdc_fifo_in_last = soc_rx_cdc_sink_last;
assign soc_rx_cdc_fifo_in_payload_data = soc_rx_cdc_sink_payload_data;
assign soc_rx_cdc_fifo_in_payload_last_be = soc_rx_cdc_sink_payload_last_be;
assign soc_rx_cdc_fifo_in_payload_error = soc_rx_cdc_sink_payload_error;
assign soc_rx_cdc_source_valid = soc_rx_cdc_asyncfifo_readable;
assign soc_rx_cdc_source_first = soc_rx_cdc_fifo_out_first;
assign soc_rx_cdc_source_last = soc_rx_cdc_fifo_out_last;
assign soc_rx_cdc_source_payload_data = soc_rx_cdc_fifo_out_payload_data;
assign soc_rx_cdc_source_payload_last_be = soc_rx_cdc_fifo_out_payload_last_be;
assign soc_rx_cdc_source_payload_error = soc_rx_cdc_fifo_out_payload_error;
assign soc_rx_cdc_asyncfifo_re = soc_rx_cdc_source_ready;
assign soc_rx_cdc_graycounter0_ce = (soc_rx_cdc_asyncfifo_writable & soc_rx_cdc_asyncfifo_we);
assign soc_rx_cdc_graycounter1_ce = (soc_rx_cdc_asyncfifo_readable & soc_rx_cdc_asyncfifo_re);
assign soc_rx_cdc_asyncfifo_writable = (((soc_rx_cdc_graycounter0_q[6] == soc_rx_cdc_consume_wdomain[6]) | (soc_rx_cdc_graycounter0_q[5] == soc_rx_cdc_consume_wdomain[5])) | (soc_rx_cdc_graycounter0_q[4:0] != soc_rx_cdc_consume_wdomain[4:0]));
assign soc_rx_cdc_asyncfifo_readable = (soc_rx_cdc_graycounter1_q != soc_rx_cdc_produce_rdomain);
assign soc_rx_cdc_wrport_adr = soc_rx_cdc_graycounter0_q_binary[5:0];
assign soc_rx_cdc_wrport_dat_w = soc_rx_cdc_asyncfifo_din;
assign soc_rx_cdc_wrport_we = soc_rx_cdc_graycounter0_ce;
assign soc_rx_cdc_rdport_adr = soc_rx_cdc_graycounter1_q_next_binary[5:0];
assign soc_rx_cdc_asyncfifo_dout = soc_rx_cdc_rdport_dat_r;
always @(*) begin
soc_rx_cdc_graycounter0_q_next_binary <= 7'd0;
if (soc_rx_cdc_graycounter0_ce) begin
soc_rx_cdc_graycounter0_q_next_binary <= (soc_rx_cdc_graycounter0_q_binary + 1'd1);
end else begin
soc_rx_cdc_graycounter0_q_next_binary <= soc_rx_cdc_graycounter0_q_binary;
end
end
assign soc_rx_cdc_graycounter0_q_next = (soc_rx_cdc_graycounter0_q_next_binary ^ soc_rx_cdc_graycounter0_q_next_binary[6:1]);
always @(*) begin
soc_rx_cdc_graycounter1_q_next_binary <= 7'd0;
if (soc_rx_cdc_graycounter1_ce) begin
soc_rx_cdc_graycounter1_q_next_binary <= (soc_rx_cdc_graycounter1_q_binary + 1'd1);
end else begin
soc_rx_cdc_graycounter1_q_next_binary <= soc_rx_cdc_graycounter1_q_binary;
end
end
assign soc_rx_cdc_graycounter1_q_next = (soc_rx_cdc_graycounter1_q_next_binary ^ soc_rx_cdc_graycounter1_q_next_binary[6:1]);
assign soc_tx_converter_sink_valid = soc_tx_cdc_source_valid;
assign soc_tx_cdc_source_ready = soc_tx_converter_sink_ready;
assign soc_tx_converter_sink_first = soc_tx_cdc_source_first;
assign soc_tx_converter_sink_last = soc_tx_cdc_source_last;
assign soc_tx_converter_sink_payload_data = soc_tx_cdc_source_payload_data;
assign soc_tx_converter_sink_payload_last_be = soc_tx_cdc_source_payload_last_be;
assign soc_tx_converter_sink_payload_error = soc_tx_cdc_source_payload_error;
assign soc_tx_last_be_sink_valid = soc_tx_converter_source_valid;
assign soc_tx_converter_source_ready = soc_tx_last_be_sink_ready;
assign soc_tx_last_be_sink_first = soc_tx_converter_source_first;
assign soc_tx_last_be_sink_last = soc_tx_converter_source_last;
assign soc_tx_last_be_sink_payload_data = soc_tx_converter_source_payload_data;
assign soc_tx_last_be_sink_payload_last_be = soc_tx_converter_source_payload_last_be;
assign soc_tx_last_be_sink_payload_error = soc_tx_converter_source_payload_error;
assign soc_padding_inserter_sink_valid = soc_tx_last_be_source_valid;
assign soc_tx_last_be_source_ready = soc_padding_inserter_sink_ready;
assign soc_padding_inserter_sink_first = soc_tx_last_be_source_first;
assign soc_padding_inserter_sink_last = soc_tx_last_be_source_last;
assign soc_padding_inserter_sink_payload_data = soc_tx_last_be_source_payload_data;
assign soc_padding_inserter_sink_payload_last_be = soc_tx_last_be_source_payload_last_be;
assign soc_padding_inserter_sink_payload_error = soc_tx_last_be_source_payload_error;
assign soc_crc32_inserter_sink_valid = soc_padding_inserter_source_valid;
assign soc_padding_inserter_source_ready = soc_crc32_inserter_sink_ready;
assign soc_crc32_inserter_sink_first = soc_padding_inserter_source_first;
assign soc_crc32_inserter_sink_last = soc_padding_inserter_source_last;
assign soc_crc32_inserter_sink_payload_data = soc_padding_inserter_source_payload_data;
assign soc_crc32_inserter_sink_payload_last_be = soc_padding_inserter_source_payload_last_be;
assign soc_crc32_inserter_sink_payload_error = soc_padding_inserter_source_payload_error;
assign soc_preamble_inserter_sink_valid = soc_crc32_inserter_source_valid;
assign soc_crc32_inserter_source_ready = soc_preamble_inserter_sink_ready;
assign soc_preamble_inserter_sink_first = soc_crc32_inserter_source_first;
assign soc_preamble_inserter_sink_last = soc_crc32_inserter_source_last;
assign soc_preamble_inserter_sink_payload_data = soc_crc32_inserter_source_payload_data;
assign soc_preamble_inserter_sink_payload_last_be = soc_crc32_inserter_source_payload_last_be;
assign soc_preamble_inserter_sink_payload_error = soc_crc32_inserter_source_payload_error;
assign soc_tx_gap_inserter_sink_valid = soc_preamble_inserter_source_valid;
assign soc_preamble_inserter_source_ready = soc_tx_gap_inserter_sink_ready;
assign soc_tx_gap_inserter_sink_first = soc_preamble_inserter_source_first;
assign soc_tx_gap_inserter_sink_last = soc_preamble_inserter_source_last;
assign soc_tx_gap_inserter_sink_payload_data = soc_preamble_inserter_source_payload_data;
assign soc_tx_gap_inserter_sink_payload_last_be = soc_preamble_inserter_source_payload_last_be;
assign soc_tx_gap_inserter_sink_payload_error = soc_preamble_inserter_source_payload_error;
assign soc_liteethphymiitx_sink_sink_valid = soc_tx_gap_inserter_source_valid;
assign soc_tx_gap_inserter_source_ready = soc_liteethphymiitx_sink_sink_ready;
assign soc_liteethphymiitx_sink_sink_first = soc_tx_gap_inserter_source_first;
assign soc_liteethphymiitx_sink_sink_last = soc_tx_gap_inserter_source_last;
assign soc_liteethphymiitx_sink_sink_payload_data = soc_tx_gap_inserter_source_payload_data;
assign soc_liteethphymiitx_sink_sink_payload_last_be = soc_tx_gap_inserter_source_payload_last_be;
assign soc_liteethphymiitx_sink_sink_payload_error = soc_tx_gap_inserter_source_payload_error;
assign soc_preamble_checker_sink_valid = soc_liteethphymiirx_source_source_valid;
assign soc_liteethphymiirx_source_source_ready = soc_preamble_checker_sink_ready;
assign soc_preamble_checker_sink_first = soc_liteethphymiirx_source_source_first;
assign soc_preamble_checker_sink_last = soc_liteethphymiirx_source_source_last;
assign soc_preamble_checker_sink_payload_data = soc_liteethphymiirx_source_source_payload_data;
assign soc_preamble_checker_sink_payload_last_be = soc_liteethphymiirx_source_source_payload_last_be;
assign soc_preamble_checker_sink_payload_error = soc_liteethphymiirx_source_source_payload_error;
assign soc_crc32_checker_sink_sink_valid = soc_preamble_checker_source_valid;
assign soc_preamble_checker_source_ready = soc_crc32_checker_sink_sink_ready;
assign soc_crc32_checker_sink_sink_first = soc_preamble_checker_source_first;
assign soc_crc32_checker_sink_sink_last = soc_preamble_checker_source_last;
assign soc_crc32_checker_sink_sink_payload_data = soc_preamble_checker_source_payload_data;
assign soc_crc32_checker_sink_sink_payload_last_be = soc_preamble_checker_source_payload_last_be;
assign soc_crc32_checker_sink_sink_payload_error = soc_preamble_checker_source_payload_error;
assign soc_padding_checker_sink_valid = soc_crc32_checker_source_source_valid;
assign soc_crc32_checker_source_source_ready = soc_padding_checker_sink_ready;
assign soc_padding_checker_sink_first = soc_crc32_checker_source_source_first;
assign soc_padding_checker_sink_last = soc_crc32_checker_source_source_last;
assign soc_padding_checker_sink_payload_data = soc_crc32_checker_source_source_payload_data;
assign soc_padding_checker_sink_payload_last_be = soc_crc32_checker_source_source_payload_last_be;
assign soc_padding_checker_sink_payload_error = soc_crc32_checker_source_source_payload_error;
assign soc_rx_last_be_sink_valid = soc_padding_checker_source_valid;
assign soc_padding_checker_source_ready = soc_rx_last_be_sink_ready;
assign soc_rx_last_be_sink_first = soc_padding_checker_source_first;
assign soc_rx_last_be_sink_last = soc_padding_checker_source_last;
assign soc_rx_last_be_sink_payload_data = soc_padding_checker_source_payload_data;
assign soc_rx_last_be_sink_payload_last_be = soc_padding_checker_source_payload_last_be;
assign soc_rx_last_be_sink_payload_error = soc_padding_checker_source_payload_error;
assign soc_rx_converter_sink_valid = soc_rx_last_be_source_valid;
assign soc_rx_last_be_source_ready = soc_rx_converter_sink_ready;
assign soc_rx_converter_sink_first = soc_rx_last_be_source_first;
assign soc_rx_converter_sink_last = soc_rx_last_be_source_last;
assign soc_rx_converter_sink_payload_data = soc_rx_last_be_source_payload_data;
assign soc_rx_converter_sink_payload_last_be = soc_rx_last_be_source_payload_last_be;
assign soc_rx_converter_sink_payload_error = soc_rx_last_be_source_payload_error;
assign soc_rx_cdc_sink_valid = soc_rx_converter_source_valid;
assign soc_rx_converter_source_ready = soc_rx_cdc_sink_ready;
assign soc_rx_cdc_sink_first = soc_rx_converter_source_first;
assign soc_rx_cdc_sink_last = soc_rx_converter_source_last;
assign soc_rx_cdc_sink_payload_data = soc_rx_converter_source_payload_data;
assign soc_rx_cdc_sink_payload_last_be = soc_rx_converter_source_payload_last_be;
assign soc_rx_cdc_sink_payload_error = soc_rx_converter_source_payload_error;
assign soc_writer_sink_sink_valid = soc_sink_valid;
assign soc_sink_ready = soc_writer_sink_sink_ready;
assign soc_writer_sink_sink_first = soc_sink_first;
assign soc_writer_sink_sink_last = soc_sink_last;
assign soc_writer_sink_sink_payload_data = soc_sink_payload_data;
assign soc_writer_sink_sink_payload_last_be = soc_sink_payload_last_be;
assign soc_writer_sink_sink_payload_error = soc_sink_payload_error;
assign soc_source_valid = soc_reader_source_source_valid;
assign soc_reader_source_source_ready = soc_source_ready;
assign soc_source_first = soc_reader_source_source_first;
assign soc_source_last = soc_reader_source_source_last;
assign soc_source_payload_data = soc_reader_source_source_payload_data;
assign soc_source_payload_last_be = soc_reader_source_source_payload_last_be;
assign soc_source_payload_error = soc_reader_source_source_payload_error;
always @(*) begin
soc_writer_inc <= 3'd0;
case (soc_writer_sink_sink_payload_last_be)
1'd1: begin
soc_writer_inc <= 1'd1;
end
2'd2: begin
soc_writer_inc <= 2'd2;
end
3'd4: begin
soc_writer_inc <= 2'd3;
end
default: begin
soc_writer_inc <= 3'd4;
end
endcase
end
assign soc_writer_fifo_sink_payload_slot = soc_writer_slot;
assign soc_writer_fifo_sink_payload_length = soc_writer_counter;
assign soc_writer_fifo_source_ready = soc_writer_available_clear;
assign soc_writer_available_trigger = soc_writer_fifo_source_valid;
assign soc_writer_slot_status = soc_writer_fifo_source_payload_slot;
assign soc_writer_length_status = soc_writer_fifo_source_payload_length;
always @(*) begin
soc_writer_memory0_adr <= 9'd0;
soc_writer_memory1_dat_w <= 32'd0;
soc_writer_memory0_we <= 1'd0;
soc_writer_memory0_dat_w <= 32'd0;
soc_writer_memory1_adr <= 9'd0;
soc_writer_memory1_we <= 1'd0;
case (soc_writer_slot)
1'd0: begin
soc_writer_memory0_adr <= soc_writer_counter[31:2];
soc_writer_memory0_dat_w <= soc_writer_sink_sink_payload_data;
if ((soc_writer_sink_sink_valid & soc_writer_ongoing)) begin
soc_writer_memory0_we <= 4'd15;
end
end
1'd1: begin
soc_writer_memory1_adr <= soc_writer_counter[31:2];
soc_writer_memory1_dat_w <= soc_writer_sink_sink_payload_data;
if ((soc_writer_sink_sink_valid & soc_writer_ongoing)) begin
soc_writer_memory1_we <= 4'd15;
end
end
endcase
end
assign soc_writer_status_w = soc_writer_available_status;
always @(*) begin
soc_writer_available_clear <= 1'd0;
if ((soc_writer_pending_re & soc_writer_pending_r)) begin
soc_writer_available_clear <= 1'd1;
end
end
assign soc_writer_pending_w = soc_writer_available_pending;
assign soc_writer_irq = (soc_writer_pending_w & soc_writer_storage);
assign soc_writer_available_status = soc_writer_available_trigger;
assign soc_writer_available_pending = soc_writer_available_trigger;
assign soc_writer_fifo_syncfifo_din = {soc_writer_fifo_fifo_in_last, soc_writer_fifo_fifo_in_first, soc_writer_fifo_fifo_in_payload_length, soc_writer_fifo_fifo_in_payload_slot};
assign {soc_writer_fifo_fifo_out_last, soc_writer_fifo_fifo_out_first, soc_writer_fifo_fifo_out_payload_length, soc_writer_fifo_fifo_out_payload_slot} = soc_writer_fifo_syncfifo_dout;
assign soc_writer_fifo_sink_ready = soc_writer_fifo_syncfifo_writable;
assign soc_writer_fifo_syncfifo_we = soc_writer_fifo_sink_valid;
assign soc_writer_fifo_fifo_in_first = soc_writer_fifo_sink_first;
assign soc_writer_fifo_fifo_in_last = soc_writer_fifo_sink_last;
assign soc_writer_fifo_fifo_in_payload_slot = soc_writer_fifo_sink_payload_slot;
assign soc_writer_fifo_fifo_in_payload_length = soc_writer_fifo_sink_payload_length;
assign soc_writer_fifo_source_valid = soc_writer_fifo_syncfifo_readable;
assign soc_writer_fifo_source_first = soc_writer_fifo_fifo_out_first;
assign soc_writer_fifo_source_last = soc_writer_fifo_fifo_out_last;
assign soc_writer_fifo_source_payload_slot = soc_writer_fifo_fifo_out_payload_slot;
assign soc_writer_fifo_source_payload_length = soc_writer_fifo_fifo_out_payload_length;
assign soc_writer_fifo_syncfifo_re = soc_writer_fifo_source_ready;
always @(*) begin
soc_writer_fifo_wrport_adr <= 1'd0;
if (soc_writer_fifo_replace) begin
soc_writer_fifo_wrport_adr <= (soc_writer_fifo_produce - 1'd1);
end else begin
soc_writer_fifo_wrport_adr <= soc_writer_fifo_produce;
end
end
assign soc_writer_fifo_wrport_dat_w = soc_writer_fifo_syncfifo_din;
assign soc_writer_fifo_wrport_we = (soc_writer_fifo_syncfifo_we & (soc_writer_fifo_syncfifo_writable | soc_writer_fifo_replace));
assign soc_writer_fifo_do_read = (soc_writer_fifo_syncfifo_readable & soc_writer_fifo_syncfifo_re);
assign soc_writer_fifo_rdport_adr = soc_writer_fifo_consume;
assign soc_writer_fifo_syncfifo_dout = soc_writer_fifo_rdport_dat_r;
assign soc_writer_fifo_syncfifo_writable = (soc_writer_fifo_level != 2'd2);
assign soc_writer_fifo_syncfifo_readable = (soc_writer_fifo_level != 1'd0);
always @(*) begin
soc_writer_slot_ce <= 1'd0;
soc_writer_errors_status_liteethmac_next_value <= 32'd0;
soc_writer_errors_status_liteethmac_next_value_ce <= 1'd0;
soc_writer_ongoing <= 1'd0;
soc_writer_fifo_sink_valid <= 1'd0;
soc_writer_counter_reset <= 1'd0;
soc_writer_counter_ce <= 1'd0;
vns_liteethmacsramwriter_next_state <= 3'd0;
vns_liteethmacsramwriter_next_state <= vns_liteethmacsramwriter_state;
case (vns_liteethmacsramwriter_state)
1'd1: begin
if (soc_writer_sink_sink_valid) begin
if ((soc_writer_counter == 11'd1530)) begin
vns_liteethmacsramwriter_next_state <= 2'd3;
end else begin
soc_writer_counter_ce <= 1'd1;
soc_writer_ongoing <= 1'd1;
end
if (soc_writer_sink_sink_last) begin
if (((soc_writer_sink_sink_payload_error & soc_writer_sink_sink_payload_last_be) != 1'd0)) begin
vns_liteethmacsramwriter_next_state <= 2'd2;
end else begin
vns_liteethmacsramwriter_next_state <= 3'd4;
end
end
end
end
2'd2: begin
soc_writer_counter_reset <= 1'd1;
vns_liteethmacsramwriter_next_state <= 1'd0;
end
2'd3: begin
if ((soc_writer_sink_sink_valid & soc_writer_sink_sink_last)) begin
vns_liteethmacsramwriter_next_state <= 3'd4;
end
end
3'd4: begin
soc_writer_counter_reset <= 1'd1;
soc_writer_slot_ce <= 1'd1;
soc_writer_fifo_sink_valid <= 1'd1;
vns_liteethmacsramwriter_next_state <= 1'd0;
end
default: begin
if (soc_writer_sink_sink_valid) begin
if (soc_writer_fifo_sink_ready) begin
soc_writer_ongoing <= 1'd1;
soc_writer_counter_ce <= 1'd1;
vns_liteethmacsramwriter_next_state <= 1'd1;
end else begin
soc_writer_errors_status_liteethmac_next_value <= (soc_writer_errors_status + 1'd1);
soc_writer_errors_status_liteethmac_next_value_ce <= 1'd1;
vns_liteethmacsramwriter_next_state <= 2'd3;
end
end
end
endcase
end
assign soc_reader_fifo_sink_valid = soc_reader_start_re;
assign soc_reader_fifo_sink_payload_slot = soc_reader_slot_storage;
assign soc_reader_fifo_sink_payload_length = soc_reader_length_storage;
assign soc_reader_ready_status = soc_reader_fifo_sink_ready;
assign soc_reader_level_status = soc_reader_fifo_level;
always @(*) begin
soc_reader_source_source_payload_last_be <= 4'd0;
if (soc_reader_last) begin
case (soc_reader_fifo_source_payload_length[1:0])
1'd0: begin
soc_reader_source_source_payload_last_be <= 4'd8;
end
1'd1: begin
soc_reader_source_source_payload_last_be <= 1'd1;
end
2'd2: begin
soc_reader_source_source_payload_last_be <= 2'd2;
end
2'd3: begin
soc_reader_source_source_payload_last_be <= 3'd4;
end
endcase
end
end
assign soc_reader_last = ((soc_reader_counter + 3'd4) >= soc_reader_fifo_source_payload_length);
assign soc_reader_memory0_adr = soc_reader_counter[10:2];
assign soc_reader_memory1_adr = soc_reader_counter[10:2];
always @(*) begin
soc_reader_source_source_payload_data <= 32'd0;
case (soc_reader_fifo_source_payload_slot)
1'd0: begin
soc_reader_source_source_payload_data <= soc_reader_memory0_dat_r;
end
1'd1: begin
soc_reader_source_source_payload_data <= soc_reader_memory1_dat_r;
end
endcase
end
assign soc_reader_eventmanager_status_w = soc_reader_done_status;
always @(*) begin
soc_reader_done_clear <= 1'd0;
if ((soc_reader_eventmanager_pending_re & soc_reader_eventmanager_pending_r)) begin
soc_reader_done_clear <= 1'd1;
end
end
assign soc_reader_eventmanager_pending_w = soc_reader_done_pending;
assign soc_reader_irq = (soc_reader_eventmanager_pending_w & soc_reader_eventmanager_storage);
assign soc_reader_done_status = 1'd0;
assign soc_reader_fifo_syncfifo_din = {soc_reader_fifo_fifo_in_last, soc_reader_fifo_fifo_in_first, soc_reader_fifo_fifo_in_payload_length, soc_reader_fifo_fifo_in_payload_slot};
assign {soc_reader_fifo_fifo_out_last, soc_reader_fifo_fifo_out_first, soc_reader_fifo_fifo_out_payload_length, soc_reader_fifo_fifo_out_payload_slot} = soc_reader_fifo_syncfifo_dout;
assign soc_reader_fifo_sink_ready = soc_reader_fifo_syncfifo_writable;
assign soc_reader_fifo_syncfifo_we = soc_reader_fifo_sink_valid;
assign soc_reader_fifo_fifo_in_first = soc_reader_fifo_sink_first;
assign soc_reader_fifo_fifo_in_last = soc_reader_fifo_sink_last;
assign soc_reader_fifo_fifo_in_payload_slot = soc_reader_fifo_sink_payload_slot;
assign soc_reader_fifo_fifo_in_payload_length = soc_reader_fifo_sink_payload_length;
assign soc_reader_fifo_source_valid = soc_reader_fifo_syncfifo_readable;
assign soc_reader_fifo_source_first = soc_reader_fifo_fifo_out_first;
assign soc_reader_fifo_source_last = soc_reader_fifo_fifo_out_last;
assign soc_reader_fifo_source_payload_slot = soc_reader_fifo_fifo_out_payload_slot;
assign soc_reader_fifo_source_payload_length = soc_reader_fifo_fifo_out_payload_length;
assign soc_reader_fifo_syncfifo_re = soc_reader_fifo_source_ready;
always @(*) begin
soc_reader_fifo_wrport_adr <= 1'd0;
if (soc_reader_fifo_replace) begin
soc_reader_fifo_wrport_adr <= (soc_reader_fifo_produce - 1'd1);
end else begin
soc_reader_fifo_wrport_adr <= soc_reader_fifo_produce;
end
end
assign soc_reader_fifo_wrport_dat_w = soc_reader_fifo_syncfifo_din;
assign soc_reader_fifo_wrport_we = (soc_reader_fifo_syncfifo_we & (soc_reader_fifo_syncfifo_writable | soc_reader_fifo_replace));
assign soc_reader_fifo_do_read = (soc_reader_fifo_syncfifo_readable & soc_reader_fifo_syncfifo_re);
assign soc_reader_fifo_rdport_adr = soc_reader_fifo_consume;
assign soc_reader_fifo_syncfifo_dout = soc_reader_fifo_rdport_dat_r;
assign soc_reader_fifo_syncfifo_writable = (soc_reader_fifo_level != 2'd2);
assign soc_reader_fifo_syncfifo_readable = (soc_reader_fifo_level != 1'd0);
always @(*) begin
soc_reader_counter_reset <= 1'd0;
soc_reader_counter_ce <= 1'd0;
soc_reader_source_source_last <= 1'd0;
soc_reader_fifo_source_ready <= 1'd0;
vns_liteethmacsramreader_next_state <= 2'd0;
soc_reader_source_source_valid <= 1'd0;
soc_reader_done_trigger <= 1'd0;
vns_liteethmacsramreader_next_state <= vns_liteethmacsramreader_state;
case (vns_liteethmacsramreader_state)
1'd1: begin
if ((~soc_reader_last_d)) begin
vns_liteethmacsramreader_next_state <= 2'd2;
end else begin
vns_liteethmacsramreader_next_state <= 2'd3;
end
end
2'd2: begin
soc_reader_source_source_valid <= 1'd1;
soc_reader_source_source_last <= soc_reader_last;
if (soc_reader_source_source_ready) begin
soc_reader_counter_ce <= (~soc_reader_last);
vns_liteethmacsramreader_next_state <= 1'd1;
end
end
2'd3: begin
soc_reader_fifo_source_ready <= 1'd1;
soc_reader_done_trigger <= 1'd1;
vns_liteethmacsramreader_next_state <= 1'd0;
end
default: begin
soc_reader_counter_reset <= 1'd1;
if (soc_reader_fifo_source_valid) begin
vns_liteethmacsramreader_next_state <= 1'd1;
end
end
endcase
end
assign soc_ev_irq = (soc_writer_irq | soc_reader_irq);
assign soc_sram0_adr0 = soc_sram0_bus_adr0[8:0];
assign soc_sram0_bus_dat_r0 = soc_sram0_dat_r0;
assign soc_sram1_adr0 = soc_sram1_bus_adr0[8:0];
assign soc_sram1_bus_dat_r0 = soc_sram1_dat_r0;
always @(*) begin
soc_sram0_we <= 4'd0;
soc_sram0_we[0] <= (((soc_sram0_bus_cyc1 & soc_sram0_bus_stb1) & soc_sram0_bus_we1) & soc_sram0_bus_sel1[0]);
soc_sram0_we[1] <= (((soc_sram0_bus_cyc1 & soc_sram0_bus_stb1) & soc_sram0_bus_we1) & soc_sram0_bus_sel1[1]);
soc_sram0_we[2] <= (((soc_sram0_bus_cyc1 & soc_sram0_bus_stb1) & soc_sram0_bus_we1) & soc_sram0_bus_sel1[2]);
soc_sram0_we[3] <= (((soc_sram0_bus_cyc1 & soc_sram0_bus_stb1) & soc_sram0_bus_we1) & soc_sram0_bus_sel1[3]);
end
assign soc_sram0_adr1 = soc_sram0_bus_adr1[8:0];
assign soc_sram0_bus_dat_r1 = soc_sram0_dat_r1;
assign soc_sram0_dat_w = soc_sram0_bus_dat_w1;
always @(*) begin
soc_sram1_we <= 4'd0;
soc_sram1_we[0] <= (((soc_sram1_bus_cyc1 & soc_sram1_bus_stb1) & soc_sram1_bus_we1) & soc_sram1_bus_sel1[0]);
soc_sram1_we[1] <= (((soc_sram1_bus_cyc1 & soc_sram1_bus_stb1) & soc_sram1_bus_we1) & soc_sram1_bus_sel1[1]);
soc_sram1_we[2] <= (((soc_sram1_bus_cyc1 & soc_sram1_bus_stb1) & soc_sram1_bus_we1) & soc_sram1_bus_sel1[2]);
soc_sram1_we[3] <= (((soc_sram1_bus_cyc1 & soc_sram1_bus_stb1) & soc_sram1_bus_we1) & soc_sram1_bus_sel1[3]);
end
assign soc_sram1_adr1 = soc_sram1_bus_adr1[8:0];
assign soc_sram1_bus_dat_r1 = soc_sram1_dat_r1;
assign soc_sram1_dat_w = soc_sram1_bus_dat_w1;
always @(*) begin
soc_slave_sel <= 4'd0;
soc_slave_sel[0] <= (soc_bus_adr[10:9] == 1'd0);
soc_slave_sel[1] <= (soc_bus_adr[10:9] == 1'd1);
soc_slave_sel[2] <= (soc_bus_adr[10:9] == 2'd2);
soc_slave_sel[3] <= (soc_bus_adr[10:9] == 2'd3);
end
assign soc_sram0_bus_adr0 = soc_bus_adr;
assign soc_sram0_bus_dat_w0 = soc_bus_dat_w;
assign soc_sram0_bus_sel0 = soc_bus_sel;
assign soc_sram0_bus_stb0 = soc_bus_stb;
assign soc_sram0_bus_we0 = soc_bus_we;
assign soc_sram0_bus_cti0 = soc_bus_cti;
assign soc_sram0_bus_bte0 = soc_bus_bte;
assign soc_sram1_bus_adr0 = soc_bus_adr;
assign soc_sram1_bus_dat_w0 = soc_bus_dat_w;
assign soc_sram1_bus_sel0 = soc_bus_sel;
assign soc_sram1_bus_stb0 = soc_bus_stb;
assign soc_sram1_bus_we0 = soc_bus_we;
assign soc_sram1_bus_cti0 = soc_bus_cti;
assign soc_sram1_bus_bte0 = soc_bus_bte;
assign soc_sram0_bus_adr1 = soc_bus_adr;
assign soc_sram0_bus_dat_w1 = soc_bus_dat_w;
assign soc_sram0_bus_sel1 = soc_bus_sel;
assign soc_sram0_bus_stb1 = soc_bus_stb;
assign soc_sram0_bus_we1 = soc_bus_we;
assign soc_sram0_bus_cti1 = soc_bus_cti;
assign soc_sram0_bus_bte1 = soc_bus_bte;
assign soc_sram1_bus_adr1 = soc_bus_adr;
assign soc_sram1_bus_dat_w1 = soc_bus_dat_w;
assign soc_sram1_bus_sel1 = soc_bus_sel;
assign soc_sram1_bus_stb1 = soc_bus_stb;
assign soc_sram1_bus_we1 = soc_bus_we;
assign soc_sram1_bus_cti1 = soc_bus_cti;
assign soc_sram1_bus_bte1 = soc_bus_bte;
assign soc_sram0_bus_cyc0 = (soc_bus_cyc & soc_slave_sel[0]);
assign soc_sram1_bus_cyc0 = (soc_bus_cyc & soc_slave_sel[1]);
assign soc_sram0_bus_cyc1 = (soc_bus_cyc & soc_slave_sel[2]);
assign soc_sram1_bus_cyc1 = (soc_bus_cyc & soc_slave_sel[3]);
assign soc_bus_ack = (((soc_sram0_bus_ack0 | soc_sram1_bus_ack0) | soc_sram0_bus_ack1) | soc_sram1_bus_ack1);
assign soc_bus_err = (((soc_sram0_bus_err0 | soc_sram1_bus_err0) | soc_sram0_bus_err1) | soc_sram1_bus_err1);
assign soc_bus_dat_r = (((({32{soc_slave_sel_r[0]}} & soc_sram0_bus_dat_r0) | ({32{soc_slave_sel_r[1]}} & soc_sram1_bus_dat_r0)) | ({32{soc_slave_sel_r[2]}} & soc_sram0_bus_dat_r1)) | ({32{soc_slave_sel_r[3]}} & soc_sram1_bus_dat_r1));
assign soc_netsoc_interface0_wb_sdram_adr = vns_rhs_array_muxed36;
assign soc_netsoc_interface0_wb_sdram_dat_w = vns_rhs_array_muxed37;
assign soc_netsoc_interface0_wb_sdram_sel = vns_rhs_array_muxed38;
assign soc_netsoc_interface0_wb_sdram_cyc = vns_rhs_array_muxed39;
assign soc_netsoc_interface0_wb_sdram_stb = vns_rhs_array_muxed40;
assign soc_netsoc_interface0_wb_sdram_we = vns_rhs_array_muxed41;
assign soc_netsoc_interface0_wb_sdram_cti = vns_rhs_array_muxed42;
assign soc_netsoc_interface0_wb_sdram_bte = vns_rhs_array_muxed43;
assign soc_netsoc_interface1_wb_sdram_dat_r = soc_netsoc_interface0_wb_sdram_dat_r;
assign soc_netsoc_interface1_wb_sdram_ack = (soc_netsoc_interface0_wb_sdram_ack & (vns_wb_sdram_con_grant == 1'd0));
assign soc_netsoc_interface1_wb_sdram_err = (soc_netsoc_interface0_wb_sdram_err & (vns_wb_sdram_con_grant == 1'd0));
assign vns_wb_sdram_con_request = {soc_netsoc_interface1_wb_sdram_cyc};
assign vns_wb_sdram_con_grant = 1'd0;
assign vns_netsoc_shared_adr = vns_rhs_array_muxed44;
assign vns_netsoc_shared_dat_w = vns_rhs_array_muxed45;
assign vns_netsoc_shared_sel = vns_rhs_array_muxed46;
assign vns_netsoc_shared_cyc = vns_rhs_array_muxed47;
assign vns_netsoc_shared_stb = vns_rhs_array_muxed48;
assign vns_netsoc_shared_we = vns_rhs_array_muxed49;
assign vns_netsoc_shared_cti = vns_rhs_array_muxed50;
assign vns_netsoc_shared_bte = vns_rhs_array_muxed51;
assign soc_netsoc_interface0_soc_bus_dat_r = vns_netsoc_shared_dat_r;
assign soc_netsoc_interface1_soc_bus_dat_r = vns_netsoc_shared_dat_r;
assign soc_netsoc_interface0_soc_bus_ack = (vns_netsoc_shared_ack & (vns_netsoc_grant == 1'd0));
assign soc_netsoc_interface1_soc_bus_ack = (vns_netsoc_shared_ack & (vns_netsoc_grant == 1'd1));
assign soc_netsoc_interface0_soc_bus_err = (vns_netsoc_shared_err & (vns_netsoc_grant == 1'd0));
assign soc_netsoc_interface1_soc_bus_err = (vns_netsoc_shared_err & (vns_netsoc_grant == 1'd1));
assign vns_netsoc_request = {soc_netsoc_interface1_soc_bus_cyc, soc_netsoc_interface0_soc_bus_cyc};
always @(*) begin
vns_netsoc_slave_sel <= 6'd0;
vns_netsoc_slave_sel[0] <= (vns_netsoc_shared_adr[28:14] == 1'd0);
vns_netsoc_slave_sel[1] <= (vns_netsoc_shared_adr[28:13] == 14'd8192);
vns_netsoc_slave_sel[2] <= (vns_netsoc_shared_adr[28:22] == 7'd112);
vns_netsoc_slave_sel[3] <= (vns_netsoc_shared_adr[28:12] == 17'd81920);
vns_netsoc_slave_sel[4] <= (vns_netsoc_shared_adr[28:26] == 3'd4);
vns_netsoc_slave_sel[5] <= (vns_netsoc_shared_adr[28:26] == 2'd3);
end
assign soc_netsoc_rom_bus_adr = vns_netsoc_shared_adr;
assign soc_netsoc_rom_bus_dat_w = vns_netsoc_shared_dat_w;
assign soc_netsoc_rom_bus_sel = vns_netsoc_shared_sel;
assign soc_netsoc_rom_bus_stb = vns_netsoc_shared_stb;
assign soc_netsoc_rom_bus_we = vns_netsoc_shared_we;
assign soc_netsoc_rom_bus_cti = vns_netsoc_shared_cti;
assign soc_netsoc_rom_bus_bte = vns_netsoc_shared_bte;
assign soc_netsoc_sram_bus_adr = vns_netsoc_shared_adr;
assign soc_netsoc_sram_bus_dat_w = vns_netsoc_shared_dat_w;
assign soc_netsoc_sram_bus_sel = vns_netsoc_shared_sel;
assign soc_netsoc_sram_bus_stb = vns_netsoc_shared_stb;
assign soc_netsoc_sram_bus_we = vns_netsoc_shared_we;
assign soc_netsoc_sram_bus_cti = vns_netsoc_shared_cti;
assign soc_netsoc_sram_bus_bte = vns_netsoc_shared_bte;
assign soc_netsoc_bus_wishbone_adr = vns_netsoc_shared_adr;
assign soc_netsoc_bus_wishbone_dat_w = vns_netsoc_shared_dat_w;
assign soc_netsoc_bus_wishbone_sel = vns_netsoc_shared_sel;
assign soc_netsoc_bus_wishbone_stb = vns_netsoc_shared_stb;
assign soc_netsoc_bus_wishbone_we = vns_netsoc_shared_we;
assign soc_netsoc_bus_wishbone_cti = vns_netsoc_shared_cti;
assign soc_netsoc_bus_wishbone_bte = vns_netsoc_shared_bte;
assign soc_emulator_ram_bus_adr = vns_netsoc_shared_adr;
assign soc_emulator_ram_bus_dat_w = vns_netsoc_shared_dat_w;
assign soc_emulator_ram_bus_sel = vns_netsoc_shared_sel;
assign soc_emulator_ram_bus_stb = vns_netsoc_shared_stb;
assign soc_emulator_ram_bus_we = vns_netsoc_shared_we;
assign soc_emulator_ram_bus_cti = vns_netsoc_shared_cti;
assign soc_emulator_ram_bus_bte = vns_netsoc_shared_bte;
assign soc_netsoc_interface1_wb_sdram_adr = vns_netsoc_shared_adr;
assign soc_netsoc_interface1_wb_sdram_dat_w = vns_netsoc_shared_dat_w;
assign soc_netsoc_interface1_wb_sdram_sel = vns_netsoc_shared_sel;
assign soc_netsoc_interface1_wb_sdram_stb = vns_netsoc_shared_stb;
assign soc_netsoc_interface1_wb_sdram_we = vns_netsoc_shared_we;
assign soc_netsoc_interface1_wb_sdram_cti = vns_netsoc_shared_cti;
assign soc_netsoc_interface1_wb_sdram_bte = vns_netsoc_shared_bte;
assign soc_bus_adr = vns_netsoc_shared_adr;
assign soc_bus_dat_w = vns_netsoc_shared_dat_w;
assign soc_bus_sel = vns_netsoc_shared_sel;
assign soc_bus_stb = vns_netsoc_shared_stb;
assign soc_bus_we = vns_netsoc_shared_we;
assign soc_bus_cti = vns_netsoc_shared_cti;
assign soc_bus_bte = vns_netsoc_shared_bte;
assign soc_netsoc_rom_bus_cyc = (vns_netsoc_shared_cyc & vns_netsoc_slave_sel[0]);
assign soc_netsoc_sram_bus_cyc = (vns_netsoc_shared_cyc & vns_netsoc_slave_sel[1]);
assign soc_netsoc_bus_wishbone_cyc = (vns_netsoc_shared_cyc & vns_netsoc_slave_sel[2]);
assign soc_emulator_ram_bus_cyc = (vns_netsoc_shared_cyc & vns_netsoc_slave_sel[3]);
assign soc_netsoc_interface1_wb_sdram_cyc = (vns_netsoc_shared_cyc & vns_netsoc_slave_sel[4]);
assign soc_bus_cyc = (vns_netsoc_shared_cyc & vns_netsoc_slave_sel[5]);
assign vns_netsoc_shared_err = (((((soc_netsoc_rom_bus_err | soc_netsoc_sram_bus_err) | soc_netsoc_bus_wishbone_err) | soc_emulator_ram_bus_err) | soc_netsoc_interface1_wb_sdram_err) | soc_bus_err);
assign vns_netsoc_wait = ((vns_netsoc_shared_stb & vns_netsoc_shared_cyc) & (~vns_netsoc_shared_ack));
always @(*) begin
vns_netsoc_error <= 1'd0;
vns_netsoc_shared_ack <= 1'd0;
vns_netsoc_shared_dat_r <= 32'd0;
vns_netsoc_shared_ack <= (((((soc_netsoc_rom_bus_ack | soc_netsoc_sram_bus_ack) | soc_netsoc_bus_wishbone_ack) | soc_emulator_ram_bus_ack) | soc_netsoc_interface1_wb_sdram_ack) | soc_bus_ack);
vns_netsoc_shared_dat_r <= (((((({32{vns_netsoc_slave_sel_r[0]}} & soc_netsoc_rom_bus_dat_r) | ({32{vns_netsoc_slave_sel_r[1]}} & soc_netsoc_sram_bus_dat_r)) | ({32{vns_netsoc_slave_sel_r[2]}} & soc_netsoc_bus_wishbone_dat_r)) | ({32{vns_netsoc_slave_sel_r[3]}} & soc_emulator_ram_bus_dat_r)) | ({32{vns_netsoc_slave_sel_r[4]}} & soc_netsoc_interface1_wb_sdram_dat_r)) | ({32{vns_netsoc_slave_sel_r[5]}} & soc_bus_dat_r));
if (vns_netsoc_done) begin
vns_netsoc_shared_dat_r <= 32'd4294967295;
vns_netsoc_shared_ack <= 1'd1;
vns_netsoc_error <= 1'd1;
end
end
assign vns_netsoc_done = (vns_netsoc_count == 1'd0);
assign vns_netsoc_csrbankarray_csrbank0_sel = (vns_netsoc_csrbankarray_interface0_bank_bus_adr[13:9] == 1'd1);
assign soc_netsoc_cpu_latch_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[0];
assign soc_netsoc_cpu_latch_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 1'd0));
assign soc_netsoc_cpu_latch_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank0_timer_time7_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time7_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank0_timer_time7_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank0_timer_time6_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time6_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank0_timer_time6_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank0_timer_time5_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time5_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank0_timer_time5_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank0_timer_time4_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time4_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd4));
assign vns_netsoc_csrbankarray_csrbank0_timer_time4_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd4));
assign vns_netsoc_csrbankarray_csrbank0_timer_time3_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time3_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd5));
assign vns_netsoc_csrbankarray_csrbank0_timer_time3_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd5));
assign vns_netsoc_csrbankarray_csrbank0_timer_time2_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time2_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd6));
assign vns_netsoc_csrbankarray_csrbank0_timer_time2_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd6));
assign vns_netsoc_csrbankarray_csrbank0_timer_time1_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time1_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd7));
assign vns_netsoc_csrbankarray_csrbank0_timer_time1_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 3'd7));
assign vns_netsoc_csrbankarray_csrbank0_timer_time0_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time0_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd8));
assign vns_netsoc_csrbankarray_csrbank0_timer_time0_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd8));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd9));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd9));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd10));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd10));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd11));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd11));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd12));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd12));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd13));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd13));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd14));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd14));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd15));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 4'd15));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_r = vns_netsoc_csrbankarray_interface0_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_re = ((vns_netsoc_csrbankarray_csrbank0_sel & vns_netsoc_csrbankarray_interface0_bank_bus_we) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 5'd16));
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_we = ((vns_netsoc_csrbankarray_csrbank0_sel & (~vns_netsoc_csrbankarray_interface0_bank_bus_we)) & (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0] == 5'd16));
assign vns_netsoc_csrbankarray_csrbank0_timer_time7_w = soc_netsoc_cpu_time_status[63:56];
assign vns_netsoc_csrbankarray_csrbank0_timer_time6_w = soc_netsoc_cpu_time_status[55:48];
assign vns_netsoc_csrbankarray_csrbank0_timer_time5_w = soc_netsoc_cpu_time_status[47:40];
assign vns_netsoc_csrbankarray_csrbank0_timer_time4_w = soc_netsoc_cpu_time_status[39:32];
assign vns_netsoc_csrbankarray_csrbank0_timer_time3_w = soc_netsoc_cpu_time_status[31:24];
assign vns_netsoc_csrbankarray_csrbank0_timer_time2_w = soc_netsoc_cpu_time_status[23:16];
assign vns_netsoc_csrbankarray_csrbank0_timer_time1_w = soc_netsoc_cpu_time_status[15:8];
assign vns_netsoc_csrbankarray_csrbank0_timer_time0_w = soc_netsoc_cpu_time_status[7:0];
assign soc_netsoc_cpu_time_we = vns_netsoc_csrbankarray_csrbank0_timer_time0_we;
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_w = soc_netsoc_cpu_time_cmp_storage[63:56];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_w = soc_netsoc_cpu_time_cmp_storage[55:48];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_w = soc_netsoc_cpu_time_cmp_storage[47:40];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_w = soc_netsoc_cpu_time_cmp_storage[39:32];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_w = soc_netsoc_cpu_time_cmp_storage[31:24];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_w = soc_netsoc_cpu_time_cmp_storage[23:16];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_w = soc_netsoc_cpu_time_cmp_storage[15:8];
assign vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_w = soc_netsoc_cpu_time_cmp_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank1_sel = (vns_netsoc_csrbankarray_interface1_bank_bus_adr[13:9] == 1'd0);
assign soc_netsoc_ctrl_reset_reset_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[0];
assign soc_netsoc_ctrl_reset_reset_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 1'd0));
assign soc_netsoc_ctrl_reset_reset_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank1_scratch3_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank1_scratch3_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank1_scratch3_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank1_scratch2_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank1_scratch2_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank1_scratch2_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank1_scratch1_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank1_scratch1_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank1_scratch1_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank1_scratch0_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank1_scratch0_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd4));
assign vns_netsoc_csrbankarray_csrbank1_scratch0_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd4));
assign vns_netsoc_csrbankarray_csrbank1_bus_errors3_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank1_bus_errors3_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd5));
assign vns_netsoc_csrbankarray_csrbank1_bus_errors3_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd5));
assign vns_netsoc_csrbankarray_csrbank1_bus_errors2_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank1_bus_errors2_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd6));
assign vns_netsoc_csrbankarray_csrbank1_bus_errors2_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd6));
assign vns_netsoc_csrbankarray_csrbank1_bus_errors1_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank1_bus_errors1_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd7));
assign vns_netsoc_csrbankarray_csrbank1_bus_errors1_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 3'd7));
assign vns_netsoc_csrbankarray_csrbank1_bus_errors0_r = vns_netsoc_csrbankarray_interface1_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank1_bus_errors0_re = ((vns_netsoc_csrbankarray_csrbank1_sel & vns_netsoc_csrbankarray_interface1_bank_bus_we) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 4'd8));
assign vns_netsoc_csrbankarray_csrbank1_bus_errors0_we = ((vns_netsoc_csrbankarray_csrbank1_sel & (~vns_netsoc_csrbankarray_interface1_bank_bus_we)) & (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0] == 4'd8));
assign vns_netsoc_csrbankarray_csrbank1_scratch3_w = soc_netsoc_ctrl_storage[31:24];
assign vns_netsoc_csrbankarray_csrbank1_scratch2_w = soc_netsoc_ctrl_storage[23:16];
assign vns_netsoc_csrbankarray_csrbank1_scratch1_w = soc_netsoc_ctrl_storage[15:8];
assign vns_netsoc_csrbankarray_csrbank1_scratch0_w = soc_netsoc_ctrl_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank1_bus_errors3_w = soc_netsoc_ctrl_bus_errors_status[31:24];
assign vns_netsoc_csrbankarray_csrbank1_bus_errors2_w = soc_netsoc_ctrl_bus_errors_status[23:16];
assign vns_netsoc_csrbankarray_csrbank1_bus_errors1_w = soc_netsoc_ctrl_bus_errors_status[15:8];
assign vns_netsoc_csrbankarray_csrbank1_bus_errors0_w = soc_netsoc_ctrl_bus_errors_status[7:0];
assign soc_netsoc_ctrl_bus_errors_we = vns_netsoc_csrbankarray_csrbank1_bus_errors0_we;
assign vns_netsoc_csrbankarray_csrbank2_sel = (vns_netsoc_csrbankarray_interface2_bank_bus_adr[13:9] == 4'd11);
assign vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[4:0];
assign vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 1'd0));
assign soc_a7ddrphy_cdly_rst_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[0];
assign soc_a7ddrphy_cdly_rst_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 1'd1));
assign soc_a7ddrphy_cdly_rst_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 1'd1));
assign soc_a7ddrphy_cdly_inc_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[0];
assign soc_a7ddrphy_cdly_inc_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 2'd2));
assign soc_a7ddrphy_cdly_inc_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank2_dly_sel0_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[1:0];
assign vns_netsoc_csrbankarray_csrbank2_dly_sel0_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank2_dly_sel0_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 2'd3));
assign soc_a7ddrphy_rdly_dq_rst_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[0];
assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd4));
assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd4));
assign soc_a7ddrphy_rdly_dq_inc_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[0];
assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd5));
assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd5));
assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[0];
assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd6));
assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd6));
assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_netsoc_csrbankarray_interface2_bank_bus_dat_w[0];
assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_netsoc_csrbankarray_csrbank2_sel & vns_netsoc_csrbankarray_interface2_bank_bus_we) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd7));
assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_netsoc_csrbankarray_csrbank2_sel & (~vns_netsoc_csrbankarray_interface2_bank_bus_we)) & (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0] == 3'd7));
assign vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0];
assign vns_netsoc_csrbankarray_csrbank2_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0];
assign vns_netsoc_csrbankarray_csrbank3_sel = (vns_netsoc_csrbankarray_interface3_bank_bus_adr[13:9] == 4'd15);
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd4));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd4));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd5));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd5));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd6));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd6));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd7));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 3'd7));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd8));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd8));
assign soc_writer_status_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
assign soc_writer_status_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd9));
assign soc_writer_status_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd9));
assign soc_writer_pending_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
assign soc_writer_pending_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd10));
assign soc_writer_pending_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd10));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd11));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd11));
assign soc_reader_start_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
assign soc_reader_start_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd12));
assign soc_reader_start_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd12));
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd13));
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd13));
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_level_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[1:0];
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_level_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd14));
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_level_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd14));
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd15));
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 4'd15));
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[2:0];
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd16));
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd16));
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd17));
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd17));
assign soc_reader_eventmanager_status_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
assign soc_reader_eventmanager_status_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd18));
assign soc_reader_eventmanager_status_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd18));
assign soc_reader_eventmanager_pending_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
assign soc_reader_eventmanager_pending_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd19));
assign soc_reader_eventmanager_pending_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd19));
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd20));
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd20));
assign vns_netsoc_csrbankarray_csrbank3_preamble_crc_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank3_preamble_crc_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd21));
assign vns_netsoc_csrbankarray_csrbank3_preamble_crc_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd21));
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors3_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors3_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd22));
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors3_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd22));
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors2_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors2_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd23));
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors2_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd23));
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors1_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors1_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd24));
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors1_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd24));
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd25));
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd25));
assign vns_netsoc_csrbankarray_csrbank3_crc_errors3_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_crc_errors3_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd26));
assign vns_netsoc_csrbankarray_csrbank3_crc_errors3_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd26));
assign vns_netsoc_csrbankarray_csrbank3_crc_errors2_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_crc_errors2_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd27));
assign vns_netsoc_csrbankarray_csrbank3_crc_errors2_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd27));
assign vns_netsoc_csrbankarray_csrbank3_crc_errors1_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_crc_errors1_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd28));
assign vns_netsoc_csrbankarray_csrbank3_crc_errors1_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd28));
assign vns_netsoc_csrbankarray_csrbank3_crc_errors0_r = vns_netsoc_csrbankarray_interface3_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank3_crc_errors0_re = ((vns_netsoc_csrbankarray_csrbank3_sel & vns_netsoc_csrbankarray_interface3_bank_bus_we) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd29));
assign vns_netsoc_csrbankarray_csrbank3_crc_errors0_we = ((vns_netsoc_csrbankarray_csrbank3_sel & (~vns_netsoc_csrbankarray_interface3_bank_bus_we)) & (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0] == 5'd29));
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_w = soc_writer_slot_status;
assign soc_writer_slot_we = vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_we;
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_w = soc_writer_length_status[31:24];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_w = soc_writer_length_status[23:16];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_w = soc_writer_length_status[15:8];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_w = soc_writer_length_status[7:0];
assign soc_writer_length_we = vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_we;
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_w = soc_writer_errors_status[31:24];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_w = soc_writer_errors_status[23:16];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_w = soc_writer_errors_status[15:8];
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_w = soc_writer_errors_status[7:0];
assign soc_writer_errors_we = vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_we;
assign vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_w = soc_writer_storage;
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_w = soc_reader_ready_status;
assign soc_reader_ready_we = vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_we;
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_level_w = soc_reader_level_status[1:0];
assign soc_reader_level_we = vns_netsoc_csrbankarray_csrbank3_sram_reader_level_we;
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_w = soc_reader_slot_storage;
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_w = soc_reader_length_storage[10:8];
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_w = soc_reader_length_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_w = soc_reader_eventmanager_storage;
assign vns_netsoc_csrbankarray_csrbank3_preamble_crc_w = soc_preamble_crc_status;
assign soc_preamble_crc_we = vns_netsoc_csrbankarray_csrbank3_preamble_crc_we;
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors3_w = soc_preamble_errors_status[31:24];
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors2_w = soc_preamble_errors_status[23:16];
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors1_w = soc_preamble_errors_status[15:8];
assign vns_netsoc_csrbankarray_csrbank3_preamble_errors0_w = soc_preamble_errors_status[7:0];
assign soc_preamble_errors_we = vns_netsoc_csrbankarray_csrbank3_preamble_errors0_we;
assign vns_netsoc_csrbankarray_csrbank3_crc_errors3_w = soc_crc_errors_status[31:24];
assign vns_netsoc_csrbankarray_csrbank3_crc_errors2_w = soc_crc_errors_status[23:16];
assign vns_netsoc_csrbankarray_csrbank3_crc_errors1_w = soc_crc_errors_status[15:8];
assign vns_netsoc_csrbankarray_csrbank3_crc_errors0_w = soc_crc_errors_status[7:0];
assign soc_crc_errors_we = vns_netsoc_csrbankarray_csrbank3_crc_errors0_we;
assign vns_netsoc_csrbankarray_csrbank4_sel = (vns_netsoc_csrbankarray_interface4_bank_bus_adr[13:9] == 4'd14);
assign vns_netsoc_csrbankarray_csrbank4_crg_reset0_r = vns_netsoc_csrbankarray_interface4_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank4_crg_reset0_re = ((vns_netsoc_csrbankarray_csrbank4_sel & vns_netsoc_csrbankarray_interface4_bank_bus_we) & (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank4_crg_reset0_we = ((vns_netsoc_csrbankarray_csrbank4_sel & (~vns_netsoc_csrbankarray_interface4_bank_bus_we)) & (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank4_mdio_w0_r = vns_netsoc_csrbankarray_interface4_bank_bus_dat_w[2:0];
assign vns_netsoc_csrbankarray_csrbank4_mdio_w0_re = ((vns_netsoc_csrbankarray_csrbank4_sel & vns_netsoc_csrbankarray_interface4_bank_bus_we) & (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank4_mdio_w0_we = ((vns_netsoc_csrbankarray_csrbank4_sel & (~vns_netsoc_csrbankarray_interface4_bank_bus_we)) & (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank4_mdio_r_r = vns_netsoc_csrbankarray_interface4_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank4_mdio_r_re = ((vns_netsoc_csrbankarray_csrbank4_sel & vns_netsoc_csrbankarray_interface4_bank_bus_we) & (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank4_mdio_r_we = ((vns_netsoc_csrbankarray_csrbank4_sel & (~vns_netsoc_csrbankarray_interface4_bank_bus_we)) & (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank4_crg_reset0_w = soc_reset_storage;
assign soc_mdc = soc_storage[0];
assign soc_oe = soc_storage[1];
assign soc_w = soc_storage[2];
assign vns_netsoc_csrbankarray_csrbank4_mdio_w0_w = soc_storage[2:0];
assign vns_netsoc_csrbankarray_csrbank4_mdio_r_w = soc_status;
assign soc_we = vns_netsoc_csrbankarray_csrbank4_mdio_r_we;
assign vns_netsoc_csrbankarray_sel = (vns_netsoc_csrbankarray_sram_bus_adr[13:9] == 3'd4);
always @(*) begin
vns_netsoc_csrbankarray_sram_bus_dat_r <= 8'd0;
if (vns_netsoc_csrbankarray_sel_r) begin
vns_netsoc_csrbankarray_sram_bus_dat_r <= vns_netsoc_csrbankarray_dat_r;
end
end
assign vns_netsoc_csrbankarray_adr = vns_netsoc_csrbankarray_sram_bus_adr[2:0];
assign vns_netsoc_csrbankarray_csrbank5_sel = (vns_netsoc_csrbankarray_interface5_bank_bus_adr[13:9] == 4'd8);
assign vns_netsoc_csrbankarray_csrbank5_dfii_control0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[3:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_control0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank5_dfii_control0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 1'd1));
assign soc_netsoc_sdram_phaseinjector0_command_issue_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[0];
assign soc_netsoc_sdram_phaseinjector0_command_issue_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 2'd2));
assign soc_netsoc_sdram_phaseinjector0_command_issue_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd4));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd4));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[2:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd5));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd5));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd6));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd6));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd7));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 3'd7));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd8));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd8));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd9));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd9));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd10));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd10));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd11));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd11));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd12));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd12));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd13));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd13));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd14));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd14));
assign soc_netsoc_sdram_phaseinjector1_command_issue_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[0];
assign soc_netsoc_sdram_phaseinjector1_command_issue_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd15));
assign soc_netsoc_sdram_phaseinjector1_command_issue_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 4'd15));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd16));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd16));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd17));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd17));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[2:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd18));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd18));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd19));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd19));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd20));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd20));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd21));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd21));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd22));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd22));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd23));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd23));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd24));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd24));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd25));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd25));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd26));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd26));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd27));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd27));
assign soc_netsoc_sdram_phaseinjector2_command_issue_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[0];
assign soc_netsoc_sdram_phaseinjector2_command_issue_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd28));
assign soc_netsoc_sdram_phaseinjector2_command_issue_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd28));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd29));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd29));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd30));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd30));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[2:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd31));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 5'd31));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd32));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd32));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd33));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd33));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd34));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd34));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd35));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd35));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd36));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd36));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd37));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd37));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd38));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd38));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd39));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd39));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd40));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd40));
assign soc_netsoc_sdram_phaseinjector3_command_issue_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[0];
assign soc_netsoc_sdram_phaseinjector3_command_issue_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd41));
assign soc_netsoc_sdram_phaseinjector3_command_issue_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd41));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[5:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd42));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd42));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd43));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd43));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[2:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd44));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd44));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd45));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd45));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd46));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd46));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd47));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd47));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd48));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd48));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd49));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd49));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd50));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd50));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd51));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd51));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd52));
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd52));
assign soc_netsoc_sdram_bandwidth_update_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[0];
assign soc_netsoc_sdram_bandwidth_update_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd53));
assign soc_netsoc_sdram_bandwidth_update_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd53));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd54));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd54));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd55));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd55));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd56));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd56));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd57));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd57));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd58));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd58));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd59));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd59));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_r = vns_netsoc_csrbankarray_interface5_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_re = ((vns_netsoc_csrbankarray_csrbank5_sel & vns_netsoc_csrbankarray_interface5_bank_bus_we) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd60));
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_we = ((vns_netsoc_csrbankarray_csrbank5_sel & (~vns_netsoc_csrbankarray_interface5_bank_bus_we)) & (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0] == 6'd60));
assign vns_netsoc_csrbankarray_csrbank5_dfii_control0_w = soc_netsoc_sdram_storage[3:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_w = soc_netsoc_sdram_phaseinjector0_command_storage[5:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_w = soc_netsoc_sdram_phaseinjector0_address_storage[13:8];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_w = soc_netsoc_sdram_phaseinjector0_address_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_w = soc_netsoc_sdram_phaseinjector0_baddress_storage[2:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_w = soc_netsoc_sdram_phaseinjector0_wrdata_storage[31:24];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_w = soc_netsoc_sdram_phaseinjector0_wrdata_storage[23:16];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_w = soc_netsoc_sdram_phaseinjector0_wrdata_storage[15:8];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_w = soc_netsoc_sdram_phaseinjector0_wrdata_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_w = soc_netsoc_sdram_phaseinjector0_status[31:24];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_w = soc_netsoc_sdram_phaseinjector0_status[23:16];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_w = soc_netsoc_sdram_phaseinjector0_status[15:8];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_w = soc_netsoc_sdram_phaseinjector0_status[7:0];
assign soc_netsoc_sdram_phaseinjector0_we = vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_we;
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_w = soc_netsoc_sdram_phaseinjector1_command_storage[5:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_w = soc_netsoc_sdram_phaseinjector1_address_storage[13:8];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_w = soc_netsoc_sdram_phaseinjector1_address_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_w = soc_netsoc_sdram_phaseinjector1_baddress_storage[2:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_w = soc_netsoc_sdram_phaseinjector1_wrdata_storage[31:24];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_w = soc_netsoc_sdram_phaseinjector1_wrdata_storage[23:16];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_w = soc_netsoc_sdram_phaseinjector1_wrdata_storage[15:8];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_w = soc_netsoc_sdram_phaseinjector1_wrdata_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_w = soc_netsoc_sdram_phaseinjector1_status[31:24];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_w = soc_netsoc_sdram_phaseinjector1_status[23:16];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_w = soc_netsoc_sdram_phaseinjector1_status[15:8];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_w = soc_netsoc_sdram_phaseinjector1_status[7:0];
assign soc_netsoc_sdram_phaseinjector1_we = vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_we;
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_w = soc_netsoc_sdram_phaseinjector2_command_storage[5:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_w = soc_netsoc_sdram_phaseinjector2_address_storage[13:8];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_w = soc_netsoc_sdram_phaseinjector2_address_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_w = soc_netsoc_sdram_phaseinjector2_baddress_storage[2:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_w = soc_netsoc_sdram_phaseinjector2_wrdata_storage[31:24];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_w = soc_netsoc_sdram_phaseinjector2_wrdata_storage[23:16];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_w = soc_netsoc_sdram_phaseinjector2_wrdata_storage[15:8];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_w = soc_netsoc_sdram_phaseinjector2_wrdata_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_w = soc_netsoc_sdram_phaseinjector2_status[31:24];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_w = soc_netsoc_sdram_phaseinjector2_status[23:16];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_w = soc_netsoc_sdram_phaseinjector2_status[15:8];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_w = soc_netsoc_sdram_phaseinjector2_status[7:0];
assign soc_netsoc_sdram_phaseinjector2_we = vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_we;
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_w = soc_netsoc_sdram_phaseinjector3_command_storage[5:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_w = soc_netsoc_sdram_phaseinjector3_address_storage[13:8];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_w = soc_netsoc_sdram_phaseinjector3_address_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_w = soc_netsoc_sdram_phaseinjector3_baddress_storage[2:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_w = soc_netsoc_sdram_phaseinjector3_wrdata_storage[31:24];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_w = soc_netsoc_sdram_phaseinjector3_wrdata_storage[23:16];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_w = soc_netsoc_sdram_phaseinjector3_wrdata_storage[15:8];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_w = soc_netsoc_sdram_phaseinjector3_wrdata_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_w = soc_netsoc_sdram_phaseinjector3_status[31:24];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_w = soc_netsoc_sdram_phaseinjector3_status[23:16];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_w = soc_netsoc_sdram_phaseinjector3_status[15:8];
assign vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_w = soc_netsoc_sdram_phaseinjector3_status[7:0];
assign soc_netsoc_sdram_phaseinjector3_we = vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_we;
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_w = soc_netsoc_sdram_bandwidth_nreads_status[23:16];
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_w = soc_netsoc_sdram_bandwidth_nreads_status[15:8];
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_w = soc_netsoc_sdram_bandwidth_nreads_status[7:0];
assign soc_netsoc_sdram_bandwidth_nreads_we = vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_we;
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_w = soc_netsoc_sdram_bandwidth_nwrites_status[23:16];
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_w = soc_netsoc_sdram_bandwidth_nwrites_status[15:8];
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_w = soc_netsoc_sdram_bandwidth_nwrites_status[7:0];
assign soc_netsoc_sdram_bandwidth_nwrites_we = vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_we;
assign vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_w = soc_netsoc_sdram_bandwidth_data_width_status[7:0];
assign soc_netsoc_sdram_bandwidth_data_width_we = vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_we;
assign vns_netsoc_csrbankarray_csrbank6_sel = (vns_netsoc_csrbankarray_interface6_bank_bus_adr[13:9] == 3'd5);
assign vns_netsoc_csrbankarray_csrbank6_load3_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank6_load3_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank6_load3_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank6_load2_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank6_load2_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank6_load2_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank6_load1_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank6_load1_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank6_load1_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank6_load0_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank6_load0_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank6_load0_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank6_reload3_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank6_reload3_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd4));
assign vns_netsoc_csrbankarray_csrbank6_reload3_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd4));
assign vns_netsoc_csrbankarray_csrbank6_reload2_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank6_reload2_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd5));
assign vns_netsoc_csrbankarray_csrbank6_reload2_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd5));
assign vns_netsoc_csrbankarray_csrbank6_reload1_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank6_reload1_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd6));
assign vns_netsoc_csrbankarray_csrbank6_reload1_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd6));
assign vns_netsoc_csrbankarray_csrbank6_reload0_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank6_reload0_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd7));
assign vns_netsoc_csrbankarray_csrbank6_reload0_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 3'd7));
assign vns_netsoc_csrbankarray_csrbank6_en0_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank6_en0_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd8));
assign vns_netsoc_csrbankarray_csrbank6_en0_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd8));
assign vns_netsoc_csrbankarray_csrbank6_update_value0_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank6_update_value0_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd9));
assign vns_netsoc_csrbankarray_csrbank6_update_value0_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd9));
assign vns_netsoc_csrbankarray_csrbank6_value3_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank6_value3_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd10));
assign vns_netsoc_csrbankarray_csrbank6_value3_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd10));
assign vns_netsoc_csrbankarray_csrbank6_value2_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank6_value2_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd11));
assign vns_netsoc_csrbankarray_csrbank6_value2_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd11));
assign vns_netsoc_csrbankarray_csrbank6_value1_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank6_value1_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd12));
assign vns_netsoc_csrbankarray_csrbank6_value1_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd12));
assign vns_netsoc_csrbankarray_csrbank6_value0_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank6_value0_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd13));
assign vns_netsoc_csrbankarray_csrbank6_value0_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd13));
assign soc_netsoc_timer0_eventmanager_status_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[0];
assign soc_netsoc_timer0_eventmanager_status_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd14));
assign soc_netsoc_timer0_eventmanager_status_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd14));
assign soc_netsoc_timer0_eventmanager_pending_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[0];
assign soc_netsoc_timer0_eventmanager_pending_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd15));
assign soc_netsoc_timer0_eventmanager_pending_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 4'd15));
assign vns_netsoc_csrbankarray_csrbank6_ev_enable0_r = vns_netsoc_csrbankarray_interface6_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank6_ev_enable0_re = ((vns_netsoc_csrbankarray_csrbank6_sel & vns_netsoc_csrbankarray_interface6_bank_bus_we) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 5'd16));
assign vns_netsoc_csrbankarray_csrbank6_ev_enable0_we = ((vns_netsoc_csrbankarray_csrbank6_sel & (~vns_netsoc_csrbankarray_interface6_bank_bus_we)) & (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0] == 5'd16));
assign vns_netsoc_csrbankarray_csrbank6_load3_w = soc_netsoc_timer0_load_storage[31:24];
assign vns_netsoc_csrbankarray_csrbank6_load2_w = soc_netsoc_timer0_load_storage[23:16];
assign vns_netsoc_csrbankarray_csrbank6_load1_w = soc_netsoc_timer0_load_storage[15:8];
assign vns_netsoc_csrbankarray_csrbank6_load0_w = soc_netsoc_timer0_load_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank6_reload3_w = soc_netsoc_timer0_reload_storage[31:24];
assign vns_netsoc_csrbankarray_csrbank6_reload2_w = soc_netsoc_timer0_reload_storage[23:16];
assign vns_netsoc_csrbankarray_csrbank6_reload1_w = soc_netsoc_timer0_reload_storage[15:8];
assign vns_netsoc_csrbankarray_csrbank6_reload0_w = soc_netsoc_timer0_reload_storage[7:0];
assign vns_netsoc_csrbankarray_csrbank6_en0_w = soc_netsoc_timer0_en_storage;
assign vns_netsoc_csrbankarray_csrbank6_update_value0_w = soc_netsoc_timer0_update_value_storage;
assign vns_netsoc_csrbankarray_csrbank6_value3_w = soc_netsoc_timer0_value_status[31:24];
assign vns_netsoc_csrbankarray_csrbank6_value2_w = soc_netsoc_timer0_value_status[23:16];
assign vns_netsoc_csrbankarray_csrbank6_value1_w = soc_netsoc_timer0_value_status[15:8];
assign vns_netsoc_csrbankarray_csrbank6_value0_w = soc_netsoc_timer0_value_status[7:0];
assign soc_netsoc_timer0_value_we = vns_netsoc_csrbankarray_csrbank6_value0_we;
assign vns_netsoc_csrbankarray_csrbank6_ev_enable0_w = soc_netsoc_timer0_eventmanager_storage;
assign vns_netsoc_csrbankarray_csrbank7_sel = (vns_netsoc_csrbankarray_interface7_bank_bus_adr[13:9] == 2'd3);
assign soc_netsoc_uart_rxtx_r = vns_netsoc_csrbankarray_interface7_bank_bus_dat_w[7:0];
assign soc_netsoc_uart_rxtx_re = ((vns_netsoc_csrbankarray_csrbank7_sel & vns_netsoc_csrbankarray_interface7_bank_bus_we) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 1'd0));
assign soc_netsoc_uart_rxtx_we = ((vns_netsoc_csrbankarray_csrbank7_sel & (~vns_netsoc_csrbankarray_interface7_bank_bus_we)) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank7_txfull_r = vns_netsoc_csrbankarray_interface7_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank7_txfull_re = ((vns_netsoc_csrbankarray_csrbank7_sel & vns_netsoc_csrbankarray_interface7_bank_bus_we) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank7_txfull_we = ((vns_netsoc_csrbankarray_csrbank7_sel & (~vns_netsoc_csrbankarray_interface7_bank_bus_we)) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank7_rxempty_r = vns_netsoc_csrbankarray_interface7_bank_bus_dat_w[0];
assign vns_netsoc_csrbankarray_csrbank7_rxempty_re = ((vns_netsoc_csrbankarray_csrbank7_sel & vns_netsoc_csrbankarray_interface7_bank_bus_we) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank7_rxempty_we = ((vns_netsoc_csrbankarray_csrbank7_sel & (~vns_netsoc_csrbankarray_interface7_bank_bus_we)) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 2'd2));
assign soc_netsoc_uart_eventmanager_status_r = vns_netsoc_csrbankarray_interface7_bank_bus_dat_w[1:0];
assign soc_netsoc_uart_eventmanager_status_re = ((vns_netsoc_csrbankarray_csrbank7_sel & vns_netsoc_csrbankarray_interface7_bank_bus_we) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 2'd3));
assign soc_netsoc_uart_eventmanager_status_we = ((vns_netsoc_csrbankarray_csrbank7_sel & (~vns_netsoc_csrbankarray_interface7_bank_bus_we)) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 2'd3));
assign soc_netsoc_uart_eventmanager_pending_r = vns_netsoc_csrbankarray_interface7_bank_bus_dat_w[1:0];
assign soc_netsoc_uart_eventmanager_pending_re = ((vns_netsoc_csrbankarray_csrbank7_sel & vns_netsoc_csrbankarray_interface7_bank_bus_we) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 3'd4));
assign soc_netsoc_uart_eventmanager_pending_we = ((vns_netsoc_csrbankarray_csrbank7_sel & (~vns_netsoc_csrbankarray_interface7_bank_bus_we)) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 3'd4));
assign vns_netsoc_csrbankarray_csrbank7_ev_enable0_r = vns_netsoc_csrbankarray_interface7_bank_bus_dat_w[1:0];
assign vns_netsoc_csrbankarray_csrbank7_ev_enable0_re = ((vns_netsoc_csrbankarray_csrbank7_sel & vns_netsoc_csrbankarray_interface7_bank_bus_we) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 3'd5));
assign vns_netsoc_csrbankarray_csrbank7_ev_enable0_we = ((vns_netsoc_csrbankarray_csrbank7_sel & (~vns_netsoc_csrbankarray_interface7_bank_bus_we)) & (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0] == 3'd5));
assign vns_netsoc_csrbankarray_csrbank7_txfull_w = soc_netsoc_uart_txfull_status;
assign soc_netsoc_uart_txfull_we = vns_netsoc_csrbankarray_csrbank7_txfull_we;
assign vns_netsoc_csrbankarray_csrbank7_rxempty_w = soc_netsoc_uart_rxempty_status;
assign soc_netsoc_uart_rxempty_we = vns_netsoc_csrbankarray_csrbank7_rxempty_we;
assign vns_netsoc_csrbankarray_csrbank7_ev_enable0_w = soc_netsoc_uart_eventmanager_storage[1:0];
assign vns_netsoc_csrbankarray_csrbank8_sel = (vns_netsoc_csrbankarray_interface8_bank_bus_adr[13:9] == 2'd2);
assign vns_netsoc_csrbankarray_csrbank8_tuning_word3_r = vns_netsoc_csrbankarray_interface8_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank8_tuning_word3_re = ((vns_netsoc_csrbankarray_csrbank8_sel & vns_netsoc_csrbankarray_interface8_bank_bus_we) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank8_tuning_word3_we = ((vns_netsoc_csrbankarray_csrbank8_sel & (~vns_netsoc_csrbankarray_interface8_bank_bus_we)) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 1'd0));
assign vns_netsoc_csrbankarray_csrbank8_tuning_word2_r = vns_netsoc_csrbankarray_interface8_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank8_tuning_word2_re = ((vns_netsoc_csrbankarray_csrbank8_sel & vns_netsoc_csrbankarray_interface8_bank_bus_we) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank8_tuning_word2_we = ((vns_netsoc_csrbankarray_csrbank8_sel & (~vns_netsoc_csrbankarray_interface8_bank_bus_we)) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 1'd1));
assign vns_netsoc_csrbankarray_csrbank8_tuning_word1_r = vns_netsoc_csrbankarray_interface8_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank8_tuning_word1_re = ((vns_netsoc_csrbankarray_csrbank8_sel & vns_netsoc_csrbankarray_interface8_bank_bus_we) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank8_tuning_word1_we = ((vns_netsoc_csrbankarray_csrbank8_sel & (~vns_netsoc_csrbankarray_interface8_bank_bus_we)) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 2'd2));
assign vns_netsoc_csrbankarray_csrbank8_tuning_word0_r = vns_netsoc_csrbankarray_interface8_bank_bus_dat_w[7:0];
assign vns_netsoc_csrbankarray_csrbank8_tuning_word0_re = ((vns_netsoc_csrbankarray_csrbank8_sel & vns_netsoc_csrbankarray_interface8_bank_bus_we) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank8_tuning_word0_we = ((vns_netsoc_csrbankarray_csrbank8_sel & (~vns_netsoc_csrbankarray_interface8_bank_bus_we)) & (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0] == 2'd3));
assign vns_netsoc_csrbankarray_csrbank8_tuning_word3_w = soc_netsoc_uart_phy_storage[31:24];
assign vns_netsoc_csrbankarray_csrbank8_tuning_word2_w = soc_netsoc_uart_phy_storage[23:16];
assign vns_netsoc_csrbankarray_csrbank8_tuning_word1_w = soc_netsoc_uart_phy_storage[15:8];
assign vns_netsoc_csrbankarray_csrbank8_tuning_word0_w = soc_netsoc_uart_phy_storage[7:0];
assign vns_netsoc_csrcon_adr = soc_netsoc_interface_adr;
assign vns_netsoc_csrcon_we = soc_netsoc_interface_we;
assign vns_netsoc_csrcon_dat_w = soc_netsoc_interface_dat_w;
assign soc_netsoc_interface_dat_r = vns_netsoc_csrcon_dat_r;
assign vns_netsoc_csrbankarray_interface0_bank_bus_adr = vns_netsoc_csrcon_adr;
assign vns_netsoc_csrbankarray_interface1_bank_bus_adr = vns_netsoc_csrcon_adr;
assign vns_netsoc_csrbankarray_interface2_bank_bus_adr = vns_netsoc_csrcon_adr;
assign vns_netsoc_csrbankarray_interface3_bank_bus_adr = vns_netsoc_csrcon_adr;
assign vns_netsoc_csrbankarray_interface4_bank_bus_adr = vns_netsoc_csrcon_adr;
assign vns_netsoc_csrbankarray_interface5_bank_bus_adr = vns_netsoc_csrcon_adr;
assign vns_netsoc_csrbankarray_interface6_bank_bus_adr = vns_netsoc_csrcon_adr;
assign vns_netsoc_csrbankarray_interface7_bank_bus_adr = vns_netsoc_csrcon_adr;
assign vns_netsoc_csrbankarray_interface8_bank_bus_adr = vns_netsoc_csrcon_adr;
assign vns_netsoc_csrbankarray_sram_bus_adr = vns_netsoc_csrcon_adr;
assign vns_netsoc_csrbankarray_interface0_bank_bus_we = vns_netsoc_csrcon_we;
assign vns_netsoc_csrbankarray_interface1_bank_bus_we = vns_netsoc_csrcon_we;
assign vns_netsoc_csrbankarray_interface2_bank_bus_we = vns_netsoc_csrcon_we;
assign vns_netsoc_csrbankarray_interface3_bank_bus_we = vns_netsoc_csrcon_we;
assign vns_netsoc_csrbankarray_interface4_bank_bus_we = vns_netsoc_csrcon_we;
assign vns_netsoc_csrbankarray_interface5_bank_bus_we = vns_netsoc_csrcon_we;
assign vns_netsoc_csrbankarray_interface6_bank_bus_we = vns_netsoc_csrcon_we;
assign vns_netsoc_csrbankarray_interface7_bank_bus_we = vns_netsoc_csrcon_we;
assign vns_netsoc_csrbankarray_interface8_bank_bus_we = vns_netsoc_csrcon_we;
assign vns_netsoc_csrbankarray_sram_bus_we = vns_netsoc_csrcon_we;
assign vns_netsoc_csrbankarray_interface0_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
assign vns_netsoc_csrbankarray_interface1_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
assign vns_netsoc_csrbankarray_interface2_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
assign vns_netsoc_csrbankarray_interface3_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
assign vns_netsoc_csrbankarray_interface4_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
assign vns_netsoc_csrbankarray_interface5_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
assign vns_netsoc_csrbankarray_interface6_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
assign vns_netsoc_csrbankarray_interface7_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
assign vns_netsoc_csrbankarray_interface8_bank_bus_dat_w = vns_netsoc_csrcon_dat_w;
assign vns_netsoc_csrbankarray_sram_bus_dat_w = vns_netsoc_csrcon_dat_w;
assign vns_netsoc_csrcon_dat_r = (((((((((vns_netsoc_csrbankarray_interface0_bank_bus_dat_r | vns_netsoc_csrbankarray_interface1_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface2_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface3_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface4_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface5_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface6_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface7_bank_bus_dat_r) | vns_netsoc_csrbankarray_interface8_bank_bus_dat_r) | vns_netsoc_csrbankarray_sram_bus_dat_r);
always @(*) begin
vns_rhs_array_muxed0 <= 1'd0;
case (soc_netsoc_sdram_choose_cmd_grant)
1'd0: begin
vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[0];
end
1'd1: begin
vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[1];
end
2'd2: begin
vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[2];
end
2'd3: begin
vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[3];
end
3'd4: begin
vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[4];
end
3'd5: begin
vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[5];
end
3'd6: begin
vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[6];
end
default: begin
vns_rhs_array_muxed0 <= soc_netsoc_sdram_choose_cmd_valids[7];
end
endcase
end
always @(*) begin
vns_rhs_array_muxed1 <= 14'd0;
case (soc_netsoc_sdram_choose_cmd_grant)
1'd0: begin
vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine0_cmd_payload_a;
end
1'd1: begin
vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine1_cmd_payload_a;
end
2'd2: begin
vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine2_cmd_payload_a;
end
2'd3: begin
vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine3_cmd_payload_a;
end
3'd4: begin
vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine4_cmd_payload_a;
end
3'd5: begin
vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine5_cmd_payload_a;
end
3'd6: begin
vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine6_cmd_payload_a;
end
default: begin
vns_rhs_array_muxed1 <= soc_netsoc_sdram_bankmachine7_cmd_payload_a;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed2 <= 3'd0;
case (soc_netsoc_sdram_choose_cmd_grant)
1'd0: begin
vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine0_cmd_payload_ba;
end
1'd1: begin
vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine1_cmd_payload_ba;
end
2'd2: begin
vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine2_cmd_payload_ba;
end
2'd3: begin
vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine3_cmd_payload_ba;
end
3'd4: begin
vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine4_cmd_payload_ba;
end
3'd5: begin
vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine5_cmd_payload_ba;
end
3'd6: begin
vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine6_cmd_payload_ba;
end
default: begin
vns_rhs_array_muxed2 <= soc_netsoc_sdram_bankmachine7_cmd_payload_ba;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed3 <= 1'd0;
case (soc_netsoc_sdram_choose_cmd_grant)
1'd0: begin
vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine6_cmd_payload_is_read;
end
default: begin
vns_rhs_array_muxed3 <= soc_netsoc_sdram_bankmachine7_cmd_payload_is_read;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed4 <= 1'd0;
case (soc_netsoc_sdram_choose_cmd_grant)
1'd0: begin
vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine6_cmd_payload_is_write;
end
default: begin
vns_rhs_array_muxed4 <= soc_netsoc_sdram_bankmachine7_cmd_payload_is_write;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed5 <= 1'd0;
case (soc_netsoc_sdram_choose_cmd_grant)
1'd0: begin
vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd;
end
default: begin
vns_rhs_array_muxed5 <= soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd;
end
endcase
end
always @(*) begin
vns_t_array_muxed0 <= 1'd0;
case (soc_netsoc_sdram_choose_cmd_grant)
1'd0: begin
vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine0_cmd_payload_cas;
end
1'd1: begin
vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine1_cmd_payload_cas;
end
2'd2: begin
vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine2_cmd_payload_cas;
end
2'd3: begin
vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine3_cmd_payload_cas;
end
3'd4: begin
vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine4_cmd_payload_cas;
end
3'd5: begin
vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine5_cmd_payload_cas;
end
3'd6: begin
vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine6_cmd_payload_cas;
end
default: begin
vns_t_array_muxed0 <= soc_netsoc_sdram_bankmachine7_cmd_payload_cas;
end
endcase
end
always @(*) begin
vns_t_array_muxed1 <= 1'd0;
case (soc_netsoc_sdram_choose_cmd_grant)
1'd0: begin
vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine0_cmd_payload_ras;
end
1'd1: begin
vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine1_cmd_payload_ras;
end
2'd2: begin
vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine2_cmd_payload_ras;
end
2'd3: begin
vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine3_cmd_payload_ras;
end
3'd4: begin
vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine4_cmd_payload_ras;
end
3'd5: begin
vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine5_cmd_payload_ras;
end
3'd6: begin
vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine6_cmd_payload_ras;
end
default: begin
vns_t_array_muxed1 <= soc_netsoc_sdram_bankmachine7_cmd_payload_ras;
end
endcase
end
always @(*) begin
vns_t_array_muxed2 <= 1'd0;
case (soc_netsoc_sdram_choose_cmd_grant)
1'd0: begin
vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine0_cmd_payload_we;
end
1'd1: begin
vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine1_cmd_payload_we;
end
2'd2: begin
vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine2_cmd_payload_we;
end
2'd3: begin
vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine3_cmd_payload_we;
end
3'd4: begin
vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine4_cmd_payload_we;
end
3'd5: begin
vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine5_cmd_payload_we;
end
3'd6: begin
vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine6_cmd_payload_we;
end
default: begin
vns_t_array_muxed2 <= soc_netsoc_sdram_bankmachine7_cmd_payload_we;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed6 <= 1'd0;
case (soc_netsoc_sdram_choose_req_grant)
1'd0: begin
vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[0];
end
1'd1: begin
vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[1];
end
2'd2: begin
vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[2];
end
2'd3: begin
vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[3];
end
3'd4: begin
vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[4];
end
3'd5: begin
vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[5];
end
3'd6: begin
vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[6];
end
default: begin
vns_rhs_array_muxed6 <= soc_netsoc_sdram_choose_req_valids[7];
end
endcase
end
always @(*) begin
vns_rhs_array_muxed7 <= 14'd0;
case (soc_netsoc_sdram_choose_req_grant)
1'd0: begin
vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine0_cmd_payload_a;
end
1'd1: begin
vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine1_cmd_payload_a;
end
2'd2: begin
vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine2_cmd_payload_a;
end
2'd3: begin
vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine3_cmd_payload_a;
end
3'd4: begin
vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine4_cmd_payload_a;
end
3'd5: begin
vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine5_cmd_payload_a;
end
3'd6: begin
vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine6_cmd_payload_a;
end
default: begin
vns_rhs_array_muxed7 <= soc_netsoc_sdram_bankmachine7_cmd_payload_a;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed8 <= 3'd0;
case (soc_netsoc_sdram_choose_req_grant)
1'd0: begin
vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine0_cmd_payload_ba;
end
1'd1: begin
vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine1_cmd_payload_ba;
end
2'd2: begin
vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine2_cmd_payload_ba;
end
2'd3: begin
vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine3_cmd_payload_ba;
end
3'd4: begin
vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine4_cmd_payload_ba;
end
3'd5: begin
vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine5_cmd_payload_ba;
end
3'd6: begin
vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine6_cmd_payload_ba;
end
default: begin
vns_rhs_array_muxed8 <= soc_netsoc_sdram_bankmachine7_cmd_payload_ba;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed9 <= 1'd0;
case (soc_netsoc_sdram_choose_req_grant)
1'd0: begin
vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine6_cmd_payload_is_read;
end
default: begin
vns_rhs_array_muxed9 <= soc_netsoc_sdram_bankmachine7_cmd_payload_is_read;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed10 <= 1'd0;
case (soc_netsoc_sdram_choose_req_grant)
1'd0: begin
vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine6_cmd_payload_is_write;
end
default: begin
vns_rhs_array_muxed10 <= soc_netsoc_sdram_bankmachine7_cmd_payload_is_write;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed11 <= 1'd0;
case (soc_netsoc_sdram_choose_req_grant)
1'd0: begin
vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine6_cmd_payload_is_cmd;
end
default: begin
vns_rhs_array_muxed11 <= soc_netsoc_sdram_bankmachine7_cmd_payload_is_cmd;
end
endcase
end
always @(*) begin
vns_t_array_muxed3 <= 1'd0;
case (soc_netsoc_sdram_choose_req_grant)
1'd0: begin
vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine0_cmd_payload_cas;
end
1'd1: begin
vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine1_cmd_payload_cas;
end
2'd2: begin
vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine2_cmd_payload_cas;
end
2'd3: begin
vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine3_cmd_payload_cas;
end
3'd4: begin
vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine4_cmd_payload_cas;
end
3'd5: begin
vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine5_cmd_payload_cas;
end
3'd6: begin
vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine6_cmd_payload_cas;
end
default: begin
vns_t_array_muxed3 <= soc_netsoc_sdram_bankmachine7_cmd_payload_cas;
end
endcase
end
always @(*) begin
vns_t_array_muxed4 <= 1'd0;
case (soc_netsoc_sdram_choose_req_grant)
1'd0: begin
vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine0_cmd_payload_ras;
end
1'd1: begin
vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine1_cmd_payload_ras;
end
2'd2: begin
vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine2_cmd_payload_ras;
end
2'd3: begin
vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine3_cmd_payload_ras;
end
3'd4: begin
vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine4_cmd_payload_ras;
end
3'd5: begin
vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine5_cmd_payload_ras;
end
3'd6: begin
vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine6_cmd_payload_ras;
end
default: begin
vns_t_array_muxed4 <= soc_netsoc_sdram_bankmachine7_cmd_payload_ras;
end
endcase
end
always @(*) begin
vns_t_array_muxed5 <= 1'd0;
case (soc_netsoc_sdram_choose_req_grant)
1'd0: begin
vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine0_cmd_payload_we;
end
1'd1: begin
vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine1_cmd_payload_we;
end
2'd2: begin
vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine2_cmd_payload_we;
end
2'd3: begin
vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine3_cmd_payload_we;
end
3'd4: begin
vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine4_cmd_payload_we;
end
3'd5: begin
vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine5_cmd_payload_we;
end
3'd6: begin
vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine6_cmd_payload_we;
end
default: begin
vns_t_array_muxed5 <= soc_netsoc_sdram_bankmachine7_cmd_payload_we;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed12 <= 21'd0;
case (vns_roundrobin0_grant)
default: begin
vns_rhs_array_muxed12 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
vns_rhs_array_muxed13 <= 1'd0;
case (vns_roundrobin0_grant)
default: begin
vns_rhs_array_muxed13 <= soc_netsoc_port_cmd_payload_we;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed14 <= 1'd0;
case (vns_roundrobin0_grant)
default: begin
vns_rhs_array_muxed14 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
end
endcase
end
always @(*) begin
vns_rhs_array_muxed15 <= 21'd0;
case (vns_roundrobin1_grant)
default: begin
vns_rhs_array_muxed15 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
vns_rhs_array_muxed16 <= 1'd0;
case (vns_roundrobin1_grant)
default: begin
vns_rhs_array_muxed16 <= soc_netsoc_port_cmd_payload_we;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed17 <= 1'd0;
case (vns_roundrobin1_grant)
default: begin
vns_rhs_array_muxed17 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked1 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
end
endcase
end
always @(*) begin
vns_rhs_array_muxed18 <= 21'd0;
case (vns_roundrobin2_grant)
default: begin
vns_rhs_array_muxed18 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
vns_rhs_array_muxed19 <= 1'd0;
case (vns_roundrobin2_grant)
default: begin
vns_rhs_array_muxed19 <= soc_netsoc_port_cmd_payload_we;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed20 <= 1'd0;
case (vns_roundrobin2_grant)
default: begin
vns_rhs_array_muxed20 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked2 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
end
endcase
end
always @(*) begin
vns_rhs_array_muxed21 <= 21'd0;
case (vns_roundrobin3_grant)
default: begin
vns_rhs_array_muxed21 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
vns_rhs_array_muxed22 <= 1'd0;
case (vns_roundrobin3_grant)
default: begin
vns_rhs_array_muxed22 <= soc_netsoc_port_cmd_payload_we;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed23 <= 1'd0;
case (vns_roundrobin3_grant)
default: begin
vns_rhs_array_muxed23 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked3 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
end
endcase
end
always @(*) begin
vns_rhs_array_muxed24 <= 21'd0;
case (vns_roundrobin4_grant)
default: begin
vns_rhs_array_muxed24 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
vns_rhs_array_muxed25 <= 1'd0;
case (vns_roundrobin4_grant)
default: begin
vns_rhs_array_muxed25 <= soc_netsoc_port_cmd_payload_we;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed26 <= 1'd0;
case (vns_roundrobin4_grant)
default: begin
vns_rhs_array_muxed26 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked4 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
end
endcase
end
always @(*) begin
vns_rhs_array_muxed27 <= 21'd0;
case (vns_roundrobin5_grant)
default: begin
vns_rhs_array_muxed27 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
vns_rhs_array_muxed28 <= 1'd0;
case (vns_roundrobin5_grant)
default: begin
vns_rhs_array_muxed28 <= soc_netsoc_port_cmd_payload_we;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed29 <= 1'd0;
case (vns_roundrobin5_grant)
default: begin
vns_rhs_array_muxed29 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked5 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
end
endcase
end
always @(*) begin
vns_rhs_array_muxed30 <= 21'd0;
case (vns_roundrobin6_grant)
default: begin
vns_rhs_array_muxed30 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
vns_rhs_array_muxed31 <= 1'd0;
case (vns_roundrobin6_grant)
default: begin
vns_rhs_array_muxed31 <= soc_netsoc_port_cmd_payload_we;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed32 <= 1'd0;
case (vns_roundrobin6_grant)
default: begin
vns_rhs_array_muxed32 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked6 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
end
endcase
end
always @(*) begin
vns_rhs_array_muxed33 <= 21'd0;
case (vns_roundrobin7_grant)
default: begin
vns_rhs_array_muxed33 <= {soc_netsoc_port_cmd_payload_addr[23:10], soc_netsoc_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
vns_rhs_array_muxed34 <= 1'd0;
case (vns_roundrobin7_grant)
default: begin
vns_rhs_array_muxed34 <= soc_netsoc_port_cmd_payload_we;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed35 <= 1'd0;
case (vns_roundrobin7_grant)
default: begin
vns_rhs_array_muxed35 <= (((soc_netsoc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked7 | (soc_netsoc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_netsoc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_netsoc_port_cmd_valid);
end
endcase
end
always @(*) begin
vns_rhs_array_muxed36 <= 30'd0;
case (vns_wb_sdram_con_grant)
default: begin
vns_rhs_array_muxed36 <= soc_netsoc_interface1_wb_sdram_adr;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed37 <= 32'd0;
case (vns_wb_sdram_con_grant)
default: begin
vns_rhs_array_muxed37 <= soc_netsoc_interface1_wb_sdram_dat_w;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed38 <= 4'd0;
case (vns_wb_sdram_con_grant)
default: begin
vns_rhs_array_muxed38 <= soc_netsoc_interface1_wb_sdram_sel;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed39 <= 1'd0;
case (vns_wb_sdram_con_grant)
default: begin
vns_rhs_array_muxed39 <= soc_netsoc_interface1_wb_sdram_cyc;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed40 <= 1'd0;
case (vns_wb_sdram_con_grant)
default: begin
vns_rhs_array_muxed40 <= soc_netsoc_interface1_wb_sdram_stb;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed41 <= 1'd0;
case (vns_wb_sdram_con_grant)
default: begin
vns_rhs_array_muxed41 <= soc_netsoc_interface1_wb_sdram_we;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed42 <= 3'd0;
case (vns_wb_sdram_con_grant)
default: begin
vns_rhs_array_muxed42 <= soc_netsoc_interface1_wb_sdram_cti;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed43 <= 2'd0;
case (vns_wb_sdram_con_grant)
default: begin
vns_rhs_array_muxed43 <= soc_netsoc_interface1_wb_sdram_bte;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed44 <= 30'd0;
case (vns_netsoc_grant)
1'd0: begin
vns_rhs_array_muxed44 <= soc_netsoc_interface0_soc_bus_adr;
end
default: begin
vns_rhs_array_muxed44 <= soc_netsoc_interface1_soc_bus_adr;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed45 <= 32'd0;
case (vns_netsoc_grant)
1'd0: begin
vns_rhs_array_muxed45 <= soc_netsoc_interface0_soc_bus_dat_w;
end
default: begin
vns_rhs_array_muxed45 <= soc_netsoc_interface1_soc_bus_dat_w;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed46 <= 4'd0;
case (vns_netsoc_grant)
1'd0: begin
vns_rhs_array_muxed46 <= soc_netsoc_interface0_soc_bus_sel;
end
default: begin
vns_rhs_array_muxed46 <= soc_netsoc_interface1_soc_bus_sel;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed47 <= 1'd0;
case (vns_netsoc_grant)
1'd0: begin
vns_rhs_array_muxed47 <= soc_netsoc_interface0_soc_bus_cyc;
end
default: begin
vns_rhs_array_muxed47 <= soc_netsoc_interface1_soc_bus_cyc;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed48 <= 1'd0;
case (vns_netsoc_grant)
1'd0: begin
vns_rhs_array_muxed48 <= soc_netsoc_interface0_soc_bus_stb;
end
default: begin
vns_rhs_array_muxed48 <= soc_netsoc_interface1_soc_bus_stb;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed49 <= 1'd0;
case (vns_netsoc_grant)
1'd0: begin
vns_rhs_array_muxed49 <= soc_netsoc_interface0_soc_bus_we;
end
default: begin
vns_rhs_array_muxed49 <= soc_netsoc_interface1_soc_bus_we;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed50 <= 3'd0;
case (vns_netsoc_grant)
1'd0: begin
vns_rhs_array_muxed50 <= soc_netsoc_interface0_soc_bus_cti;
end
default: begin
vns_rhs_array_muxed50 <= soc_netsoc_interface1_soc_bus_cti;
end
endcase
end
always @(*) begin
vns_rhs_array_muxed51 <= 2'd0;
case (vns_netsoc_grant)
1'd0: begin
vns_rhs_array_muxed51 <= soc_netsoc_interface0_soc_bus_bte;
end
default: begin
vns_rhs_array_muxed51 <= soc_netsoc_interface1_soc_bus_bte;
end
endcase
end
always @(*) begin
vns_array_muxed0 <= 3'd0;
case (soc_netsoc_sdram_steerer_sel0)
1'd0: begin
vns_array_muxed0 <= soc_netsoc_sdram_nop_ba[2:0];
end
1'd1: begin
vns_array_muxed0 <= soc_netsoc_sdram_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
vns_array_muxed0 <= soc_netsoc_sdram_choose_req_cmd_payload_ba[2:0];
end
default: begin
vns_array_muxed0 <= soc_netsoc_sdram_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
vns_array_muxed1 <= 14'd0;
case (soc_netsoc_sdram_steerer_sel0)
1'd0: begin
vns_array_muxed1 <= soc_netsoc_sdram_nop_a;
end
1'd1: begin
vns_array_muxed1 <= soc_netsoc_sdram_choose_cmd_cmd_payload_a;
end
2'd2: begin
vns_array_muxed1 <= soc_netsoc_sdram_choose_req_cmd_payload_a;
end
default: begin
vns_array_muxed1 <= soc_netsoc_sdram_cmd_payload_a;
end
endcase
end
always @(*) begin
vns_array_muxed2 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel0)
1'd0: begin
vns_array_muxed2 <= 1'd0;
end
1'd1: begin
vns_array_muxed2 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_cas);
end
2'd2: begin
vns_array_muxed2 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_cas);
end
default: begin
vns_array_muxed2 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_cas);
end
endcase
end
always @(*) begin
vns_array_muxed3 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel0)
1'd0: begin
vns_array_muxed3 <= 1'd0;
end
1'd1: begin
vns_array_muxed3 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_ras);
end
2'd2: begin
vns_array_muxed3 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_ras);
end
default: begin
vns_array_muxed3 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_ras);
end
endcase
end
always @(*) begin
vns_array_muxed4 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel0)
1'd0: begin
vns_array_muxed4 <= 1'd0;
end
1'd1: begin
vns_array_muxed4 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_we);
end
2'd2: begin
vns_array_muxed4 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_we);
end
default: begin
vns_array_muxed4 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_we);
end
endcase
end
always @(*) begin
vns_array_muxed5 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel0)
1'd0: begin
vns_array_muxed5 <= 1'd0;
end
1'd1: begin
vns_array_muxed5 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
vns_array_muxed5 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_read);
end
default: begin
vns_array_muxed5 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_read);
end
endcase
end
always @(*) begin
vns_array_muxed6 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel0)
1'd0: begin
vns_array_muxed6 <= 1'd0;
end
1'd1: begin
vns_array_muxed6 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
vns_array_muxed6 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_write);
end
default: begin
vns_array_muxed6 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_write);
end
endcase
end
always @(*) begin
vns_array_muxed7 <= 3'd0;
case (soc_netsoc_sdram_steerer_sel1)
1'd0: begin
vns_array_muxed7 <= soc_netsoc_sdram_nop_ba[2:0];
end
1'd1: begin
vns_array_muxed7 <= soc_netsoc_sdram_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
vns_array_muxed7 <= soc_netsoc_sdram_choose_req_cmd_payload_ba[2:0];
end
default: begin
vns_array_muxed7 <= soc_netsoc_sdram_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
vns_array_muxed8 <= 14'd0;
case (soc_netsoc_sdram_steerer_sel1)
1'd0: begin
vns_array_muxed8 <= soc_netsoc_sdram_nop_a;
end
1'd1: begin
vns_array_muxed8 <= soc_netsoc_sdram_choose_cmd_cmd_payload_a;
end
2'd2: begin
vns_array_muxed8 <= soc_netsoc_sdram_choose_req_cmd_payload_a;
end
default: begin
vns_array_muxed8 <= soc_netsoc_sdram_cmd_payload_a;
end
endcase
end
always @(*) begin
vns_array_muxed9 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel1)
1'd0: begin
vns_array_muxed9 <= 1'd0;
end
1'd1: begin
vns_array_muxed9 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_cas);
end
2'd2: begin
vns_array_muxed9 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_cas);
end
default: begin
vns_array_muxed9 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_cas);
end
endcase
end
always @(*) begin
vns_array_muxed10 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel1)
1'd0: begin
vns_array_muxed10 <= 1'd0;
end
1'd1: begin
vns_array_muxed10 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_ras);
end
2'd2: begin
vns_array_muxed10 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_ras);
end
default: begin
vns_array_muxed10 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_ras);
end
endcase
end
always @(*) begin
vns_array_muxed11 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel1)
1'd0: begin
vns_array_muxed11 <= 1'd0;
end
1'd1: begin
vns_array_muxed11 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_we);
end
2'd2: begin
vns_array_muxed11 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_we);
end
default: begin
vns_array_muxed11 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_we);
end
endcase
end
always @(*) begin
vns_array_muxed12 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel1)
1'd0: begin
vns_array_muxed12 <= 1'd0;
end
1'd1: begin
vns_array_muxed12 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
vns_array_muxed12 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_read);
end
default: begin
vns_array_muxed12 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_read);
end
endcase
end
always @(*) begin
vns_array_muxed13 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel1)
1'd0: begin
vns_array_muxed13 <= 1'd0;
end
1'd1: begin
vns_array_muxed13 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
vns_array_muxed13 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_write);
end
default: begin
vns_array_muxed13 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_write);
end
endcase
end
always @(*) begin
vns_array_muxed14 <= 3'd0;
case (soc_netsoc_sdram_steerer_sel2)
1'd0: begin
vns_array_muxed14 <= soc_netsoc_sdram_nop_ba[2:0];
end
1'd1: begin
vns_array_muxed14 <= soc_netsoc_sdram_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
vns_array_muxed14 <= soc_netsoc_sdram_choose_req_cmd_payload_ba[2:0];
end
default: begin
vns_array_muxed14 <= soc_netsoc_sdram_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
vns_array_muxed15 <= 14'd0;
case (soc_netsoc_sdram_steerer_sel2)
1'd0: begin
vns_array_muxed15 <= soc_netsoc_sdram_nop_a;
end
1'd1: begin
vns_array_muxed15 <= soc_netsoc_sdram_choose_cmd_cmd_payload_a;
end
2'd2: begin
vns_array_muxed15 <= soc_netsoc_sdram_choose_req_cmd_payload_a;
end
default: begin
vns_array_muxed15 <= soc_netsoc_sdram_cmd_payload_a;
end
endcase
end
always @(*) begin
vns_array_muxed16 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel2)
1'd0: begin
vns_array_muxed16 <= 1'd0;
end
1'd1: begin
vns_array_muxed16 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_cas);
end
2'd2: begin
vns_array_muxed16 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_cas);
end
default: begin
vns_array_muxed16 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_cas);
end
endcase
end
always @(*) begin
vns_array_muxed17 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel2)
1'd0: begin
vns_array_muxed17 <= 1'd0;
end
1'd1: begin
vns_array_muxed17 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_ras);
end
2'd2: begin
vns_array_muxed17 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_ras);
end
default: begin
vns_array_muxed17 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_ras);
end
endcase
end
always @(*) begin
vns_array_muxed18 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel2)
1'd0: begin
vns_array_muxed18 <= 1'd0;
end
1'd1: begin
vns_array_muxed18 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_we);
end
2'd2: begin
vns_array_muxed18 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_we);
end
default: begin
vns_array_muxed18 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_we);
end
endcase
end
always @(*) begin
vns_array_muxed19 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel2)
1'd0: begin
vns_array_muxed19 <= 1'd0;
end
1'd1: begin
vns_array_muxed19 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
vns_array_muxed19 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_read);
end
default: begin
vns_array_muxed19 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_read);
end
endcase
end
always @(*) begin
vns_array_muxed20 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel2)
1'd0: begin
vns_array_muxed20 <= 1'd0;
end
1'd1: begin
vns_array_muxed20 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
vns_array_muxed20 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_write);
end
default: begin
vns_array_muxed20 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_write);
end
endcase
end
always @(*) begin
vns_array_muxed21 <= 3'd0;
case (soc_netsoc_sdram_steerer_sel3)
1'd0: begin
vns_array_muxed21 <= soc_netsoc_sdram_nop_ba[2:0];
end
1'd1: begin
vns_array_muxed21 <= soc_netsoc_sdram_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
vns_array_muxed21 <= soc_netsoc_sdram_choose_req_cmd_payload_ba[2:0];
end
default: begin
vns_array_muxed21 <= soc_netsoc_sdram_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
vns_array_muxed22 <= 14'd0;
case (soc_netsoc_sdram_steerer_sel3)
1'd0: begin
vns_array_muxed22 <= soc_netsoc_sdram_nop_a;
end
1'd1: begin
vns_array_muxed22 <= soc_netsoc_sdram_choose_cmd_cmd_payload_a;
end
2'd2: begin
vns_array_muxed22 <= soc_netsoc_sdram_choose_req_cmd_payload_a;
end
default: begin
vns_array_muxed22 <= soc_netsoc_sdram_cmd_payload_a;
end
endcase
end
always @(*) begin
vns_array_muxed23 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel3)
1'd0: begin
vns_array_muxed23 <= 1'd0;
end
1'd1: begin
vns_array_muxed23 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_cas);
end
2'd2: begin
vns_array_muxed23 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_cas);
end
default: begin
vns_array_muxed23 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_cas);
end
endcase
end
always @(*) begin
vns_array_muxed24 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel3)
1'd0: begin
vns_array_muxed24 <= 1'd0;
end
1'd1: begin
vns_array_muxed24 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_ras);
end
2'd2: begin
vns_array_muxed24 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_ras);
end
default: begin
vns_array_muxed24 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_ras);
end
endcase
end
always @(*) begin
vns_array_muxed25 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel3)
1'd0: begin
vns_array_muxed25 <= 1'd0;
end
1'd1: begin
vns_array_muxed25 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_we);
end
2'd2: begin
vns_array_muxed25 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_we);
end
default: begin
vns_array_muxed25 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_we);
end
endcase
end
always @(*) begin
vns_array_muxed26 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel3)
1'd0: begin
vns_array_muxed26 <= 1'd0;
end
1'd1: begin
vns_array_muxed26 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
vns_array_muxed26 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_read);
end
default: begin
vns_array_muxed26 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_read);
end
endcase
end
always @(*) begin
vns_array_muxed27 <= 1'd0;
case (soc_netsoc_sdram_steerer_sel3)
1'd0: begin
vns_array_muxed27 <= 1'd0;
end
1'd1: begin
vns_array_muxed27 <= ((soc_netsoc_sdram_choose_cmd_cmd_valid & soc_netsoc_sdram_choose_cmd_cmd_ready) & soc_netsoc_sdram_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
vns_array_muxed27 <= ((soc_netsoc_sdram_choose_req_cmd_valid & soc_netsoc_sdram_choose_req_cmd_ready) & soc_netsoc_sdram_choose_req_cmd_payload_is_write);
end
default: begin
vns_array_muxed27 <= ((soc_netsoc_sdram_cmd_valid & soc_netsoc_sdram_cmd_ready) & soc_netsoc_sdram_cmd_payload_is_write);
end
endcase
end
assign soc_netsoc_uart_phy_rx = vns_xilinxmultiregimpl0_regs1;
assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_pll_locked) | (~cpu_reset));
assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_pll_locked) | (~cpu_reset));
always @(*) begin
soc_status <= 1'd0;
soc_status <= soc_r;
soc_status <= vns_xilinxmultiregimpl1_regs1;
end
assign soc_ps_preamble_error_toggle_o = vns_xilinxmultiregimpl2_regs1;
assign soc_ps_crc_error_toggle_o = vns_xilinxmultiregimpl3_regs1;
assign soc_tx_cdc_produce_rdomain = vns_xilinxmultiregimpl4_regs1;
assign soc_tx_cdc_consume_wdomain = vns_xilinxmultiregimpl5_regs1;
assign soc_rx_cdc_produce_rdomain = vns_xilinxmultiregimpl6_regs1;
assign soc_rx_cdc_consume_wdomain = vns_xilinxmultiregimpl7_regs1;
always @(posedge clk200_clk) begin
if ((soc_reset_counter != 1'd0)) begin
soc_reset_counter <= (soc_reset_counter - 1'd1);
end else begin
soc_ic_reset <= 1'd0;
end
if (clk200_rst) begin
soc_reset_counter <= 4'd15;
soc_ic_reset <= 1'd1;
end
end
always @(posedge eth_rx_clk) begin
soc_liteethphymiirx_converter_reset <= (~eth_rx_dv);
soc_liteethphymiirx_converter_sink_valid <= 1'd1;
soc_liteethphymiirx_converter_sink_payload_data <= eth_rx_data;
if (soc_liteethphymiirx_converter_converter_source_ready) begin
soc_liteethphymiirx_converter_converter_strobe_all <= 1'd0;
end
if (soc_liteethphymiirx_converter_converter_load_part) begin
if (((soc_liteethphymiirx_converter_converter_demux == 1'd1) | soc_liteethphymiirx_converter_converter_sink_last)) begin
soc_liteethphymiirx_converter_converter_demux <= 1'd0;
soc_liteethphymiirx_converter_converter_strobe_all <= 1'd1;
end else begin
soc_liteethphymiirx_converter_converter_demux <= (soc_liteethphymiirx_converter_converter_demux + 1'd1);
end
end
if ((soc_liteethphymiirx_converter_converter_source_valid & soc_liteethphymiirx_converter_converter_source_ready)) begin
if ((soc_liteethphymiirx_converter_converter_sink_valid & soc_liteethphymiirx_converter_converter_sink_ready)) begin
soc_liteethphymiirx_converter_converter_source_first <= soc_liteethphymiirx_converter_converter_sink_first;
soc_liteethphymiirx_converter_converter_source_last <= soc_liteethphymiirx_converter_converter_sink_last;
end else begin
soc_liteethphymiirx_converter_converter_source_first <= 1'd0;
soc_liteethphymiirx_converter_converter_source_last <= 1'd0;
end
end else begin
if ((soc_liteethphymiirx_converter_converter_sink_valid & soc_liteethphymiirx_converter_converter_sink_ready)) begin
soc_liteethphymiirx_converter_converter_source_first <= (soc_liteethphymiirx_converter_converter_sink_first | soc_liteethphymiirx_converter_converter_source_first);
soc_liteethphymiirx_converter_converter_source_last <= (soc_liteethphymiirx_converter_converter_sink_last | soc_liteethphymiirx_converter_converter_source_last);
end
end
if (soc_liteethphymiirx_converter_converter_load_part) begin
case (soc_liteethphymiirx_converter_converter_demux)
1'd0: begin
soc_liteethphymiirx_converter_converter_source_payload_data[3:0] <= soc_liteethphymiirx_converter_converter_sink_payload_data;
end
1'd1: begin
soc_liteethphymiirx_converter_converter_source_payload_data[7:4] <= soc_liteethphymiirx_converter_converter_sink_payload_data;
end
endcase
end
if (soc_liteethphymiirx_converter_converter_load_part) begin
soc_liteethphymiirx_converter_converter_source_payload_valid_token_count <= (soc_liteethphymiirx_converter_converter_demux + 1'd1);
end
if (soc_liteethphymiirx_converter_reset) begin
soc_liteethphymiirx_converter_converter_source_first <= 1'd0;
soc_liteethphymiirx_converter_converter_source_last <= 1'd0;
soc_liteethphymiirx_converter_converter_source_payload_data <= 8'd0;
soc_liteethphymiirx_converter_converter_source_payload_valid_token_count <= 2'd0;
soc_liteethphymiirx_converter_converter_demux <= 1'd0;
soc_liteethphymiirx_converter_converter_strobe_all <= 1'd0;
end
vns_liteethmacpreamblechecker_state <= vns_liteethmacpreamblechecker_next_state;
if (soc_crc32_checker_crc_ce) begin
soc_crc32_checker_crc_reg <= soc_crc32_checker_crc_next;
end
if (soc_crc32_checker_crc_reset) begin
soc_crc32_checker_crc_reg <= 32'd4294967295;
end
if (((soc_crc32_checker_syncfifo_syncfifo_we & soc_crc32_checker_syncfifo_syncfifo_writable) & (~soc_crc32_checker_syncfifo_replace))) begin
if ((soc_crc32_checker_syncfifo_produce == 3'd4)) begin
soc_crc32_checker_syncfifo_produce <= 1'd0;
end else begin
soc_crc32_checker_syncfifo_produce <= (soc_crc32_checker_syncfifo_produce + 1'd1);
end
end
if (soc_crc32_checker_syncfifo_do_read) begin
if ((soc_crc32_checker_syncfifo_consume == 3'd4)) begin
soc_crc32_checker_syncfifo_consume <= 1'd0;
end else begin
soc_crc32_checker_syncfifo_consume <= (soc_crc32_checker_syncfifo_consume + 1'd1);
end
end
if (((soc_crc32_checker_syncfifo_syncfifo_we & soc_crc32_checker_syncfifo_syncfifo_writable) & (~soc_crc32_checker_syncfifo_replace))) begin
if ((~soc_crc32_checker_syncfifo_do_read)) begin
soc_crc32_checker_syncfifo_level <= (soc_crc32_checker_syncfifo_level + 1'd1);
end
end else begin
if (soc_crc32_checker_syncfifo_do_read) begin
soc_crc32_checker_syncfifo_level <= (soc_crc32_checker_syncfifo_level - 1'd1);
end
end
if (soc_crc32_checker_fifo_reset) begin
soc_crc32_checker_syncfifo_level <= 3'd0;
soc_crc32_checker_syncfifo_produce <= 3'd0;
soc_crc32_checker_syncfifo_consume <= 3'd0;
end
vns_liteethmaccrc32checker_state <= vns_liteethmaccrc32checker_next_state;
if (soc_ps_preamble_error_i) begin
soc_ps_preamble_error_toggle_i <= (~soc_ps_preamble_error_toggle_i);
end
if (soc_ps_crc_error_i) begin
soc_ps_crc_error_toggle_i <= (~soc_ps_crc_error_toggle_i);
end
if (soc_rx_converter_converter_source_ready) begin
soc_rx_converter_converter_strobe_all <= 1'd0;
end
if (soc_rx_converter_converter_load_part) begin
if (((soc_rx_converter_converter_demux == 2'd3) | soc_rx_converter_converter_sink_last)) begin
soc_rx_converter_converter_demux <= 1'd0;
soc_rx_converter_converter_strobe_all <= 1'd1;
end else begin
soc_rx_converter_converter_demux <= (soc_rx_converter_converter_demux + 1'd1);
end
end
if ((soc_rx_converter_converter_source_valid & soc_rx_converter_converter_source_ready)) begin
if ((soc_rx_converter_converter_sink_valid & soc_rx_converter_converter_sink_ready)) begin
soc_rx_converter_converter_source_first <= soc_rx_converter_converter_sink_first;
soc_rx_converter_converter_source_last <= soc_rx_converter_converter_sink_last;
end else begin
soc_rx_converter_converter_source_first <= 1'd0;
soc_rx_converter_converter_source_last <= 1'd0;
end
end else begin
if ((soc_rx_converter_converter_sink_valid & soc_rx_converter_converter_sink_ready)) begin
soc_rx_converter_converter_source_first <= (soc_rx_converter_converter_sink_first | soc_rx_converter_converter_source_first);
soc_rx_converter_converter_source_last <= (soc_rx_converter_converter_sink_last | soc_rx_converter_converter_source_last);
end
end
if (soc_rx_converter_converter_load_part) begin
case (soc_rx_converter_converter_demux)
1'd0: begin
soc_rx_converter_converter_source_payload_data[9:0] <= soc_rx_converter_converter_sink_payload_data;
end
1'd1: begin
soc_rx_converter_converter_source_payload_data[19:10] <= soc_rx_converter_converter_sink_payload_data;
end
2'd2: begin
soc_rx_converter_converter_source_payload_data[29:20] <= soc_rx_converter_converter_sink_payload_data;
end
2'd3: begin
soc_rx_converter_converter_source_payload_data[39:30] <= soc_rx_converter_converter_sink_payload_data;
end
endcase
end
if (soc_rx_converter_converter_load_part) begin
soc_rx_converter_converter_source_payload_valid_token_count <= (soc_rx_converter_converter_demux + 1'd1);
end
soc_rx_cdc_graycounter0_q_binary <= soc_rx_cdc_graycounter0_q_next_binary;
soc_rx_cdc_graycounter0_q <= soc_rx_cdc_graycounter0_q_next;
if (eth_rx_rst) begin
soc_liteethphymiirx_converter_sink_valid <= 1'd0;
soc_liteethphymiirx_converter_sink_payload_data <= 4'd0;
soc_liteethphymiirx_converter_converter_source_first <= 1'd0;
soc_liteethphymiirx_converter_converter_source_last <= 1'd0;
soc_liteethphymiirx_converter_converter_source_payload_data <= 8'd0;
soc_liteethphymiirx_converter_converter_source_payload_valid_token_count <= 2'd0;
soc_liteethphymiirx_converter_converter_demux <= 1'd0;
soc_liteethphymiirx_converter_converter_strobe_all <= 1'd0;
soc_liteethphymiirx_converter_reset <= 1'd0;
soc_crc32_checker_crc_reg <= 32'd4294967295;
soc_crc32_checker_syncfifo_level <= 3'd0;
soc_crc32_checker_syncfifo_produce <= 3'd0;
soc_crc32_checker_syncfifo_consume <= 3'd0;
soc_rx_converter_converter_source_first <= 1'd0;
soc_rx_converter_converter_source_last <= 1'd0;
soc_rx_converter_converter_source_payload_data <= 40'd0;
soc_rx_converter_converter_source_payload_valid_token_count <= 3'd0;
soc_rx_converter_converter_demux <= 2'd0;
soc_rx_converter_converter_strobe_all <= 1'd0;
soc_rx_cdc_graycounter0_q <= 7'd0;
soc_rx_cdc_graycounter0_q_binary <= 7'd0;
vns_liteethmacpreamblechecker_state <= 1'd0;
vns_liteethmaccrc32checker_state <= 2'd0;
end
vns_xilinxmultiregimpl7_regs0 <= soc_rx_cdc_graycounter1_q;
vns_xilinxmultiregimpl7_regs1 <= vns_xilinxmultiregimpl7_regs0;
end
always @(posedge eth_tx_clk) begin
eth_tx_en <= soc_liteethphymiitx_converter_source_valid;
eth_tx_data <= soc_liteethphymiitx_converter_source_payload_data;
if ((soc_liteethphymiitx_converter_converter_source_valid & soc_liteethphymiitx_converter_converter_source_ready)) begin
if (soc_liteethphymiitx_converter_converter_last) begin
soc_liteethphymiitx_converter_converter_mux <= 1'd0;
end else begin
soc_liteethphymiitx_converter_converter_mux <= (soc_liteethphymiitx_converter_converter_mux + 1'd1);
end
end
if (soc_tx_gap_inserter_counter_reset) begin
soc_tx_gap_inserter_counter <= 1'd0;
end else begin
if (soc_tx_gap_inserter_counter_ce) begin
soc_tx_gap_inserter_counter <= (soc_tx_gap_inserter_counter + 1'd1);
end
end
vns_liteethmacgap_state <= vns_liteethmacgap_next_state;
if (soc_preamble_inserter_clr_cnt) begin
soc_preamble_inserter_cnt <= 1'd0;
end else begin
if (soc_preamble_inserter_inc_cnt) begin
soc_preamble_inserter_cnt <= (soc_preamble_inserter_cnt + 1'd1);
end
end
vns_liteethmacpreambleinserter_state <= vns_liteethmacpreambleinserter_next_state;
if (soc_crc32_inserter_is_ongoing0) begin
soc_crc32_inserter_cnt <= 2'd3;
end else begin
if ((soc_crc32_inserter_is_ongoing1 & (~soc_crc32_inserter_cnt_done))) begin
soc_crc32_inserter_cnt <= (soc_crc32_inserter_cnt - soc_crc32_inserter_source_ready);
end
end
if (soc_crc32_inserter_ce) begin
soc_crc32_inserter_reg <= soc_crc32_inserter_next;
end
if (soc_crc32_inserter_reset) begin
soc_crc32_inserter_reg <= 32'd4294967295;
end
vns_liteethmaccrc32inserter_state <= vns_liteethmaccrc32inserter_next_state;
if (soc_padding_inserter_counter_reset) begin
soc_padding_inserter_counter <= 1'd0;
end else begin
if (soc_padding_inserter_counter_ce) begin
soc_padding_inserter_counter <= (soc_padding_inserter_counter + 1'd1);
end
end
vns_liteethmacpaddinginserter_state <= vns_liteethmacpaddinginserter_next_state;
if ((soc_tx_last_be_sink_valid & soc_tx_last_be_sink_ready)) begin
if (soc_tx_last_be_sink_last) begin
soc_tx_last_be_ongoing <= 1'd1;
end else begin
if (soc_tx_last_be_sink_payload_last_be) begin
soc_tx_last_be_ongoing <= 1'd0;
end
end
end
if ((soc_tx_converter_converter_source_valid & soc_tx_converter_converter_source_ready)) begin
if (soc_tx_converter_converter_last) begin
soc_tx_converter_converter_mux <= 1'd0;
end else begin
soc_tx_converter_converter_mux <= (soc_tx_converter_converter_mux + 1'd1);
end
end
soc_tx_cdc_graycounter1_q_binary <= soc_tx_cdc_graycounter1_q_next_binary;
soc_tx_cdc_graycounter1_q <= soc_tx_cdc_graycounter1_q_next;
if (eth_tx_rst) begin
soc_liteethphymiitx_converter_converter_mux <= 1'd0;
soc_crc32_inserter_reg <= 32'd4294967295;
soc_crc32_inserter_cnt <= 2'd3;
soc_padding_inserter_counter <= 16'd1;
soc_tx_last_be_ongoing <= 1'd1;
soc_tx_converter_converter_mux <= 2'd0;
soc_tx_cdc_graycounter1_q <= 7'd0;
soc_tx_cdc_graycounter1_q_binary <= 7'd0;
vns_liteethmacgap_state <= 1'd0;
vns_liteethmacpreambleinserter_state <= 2'd0;
vns_liteethmaccrc32inserter_state <= 2'd0;
vns_liteethmacpaddinginserter_state <= 1'd0;
end
vns_xilinxmultiregimpl4_regs0 <= soc_tx_cdc_graycounter0_q;
vns_xilinxmultiregimpl4_regs1 <= vns_xilinxmultiregimpl4_regs0;
end
always @(posedge sys_clk) begin
if ((soc_netsoc_ctrl_bus_errors != 32'd4294967295)) begin
if (soc_netsoc_ctrl_bus_error) begin
soc_netsoc_ctrl_bus_errors <= (soc_netsoc_ctrl_bus_errors + 1'd1);
end
end
soc_netsoc_cpu_time <= (soc_netsoc_cpu_time + 1'd1);
if (soc_netsoc_cpu_latch_re) begin
soc_netsoc_cpu_time_status <= soc_netsoc_cpu_time;
end
if (soc_netsoc_cpu_latch_re) begin
soc_netsoc_cpu_time_cmp <= soc_netsoc_cpu_time_cmp_storage;
end
soc_netsoc_rom_bus_ack <= 1'd0;
if (((soc_netsoc_rom_bus_cyc & soc_netsoc_rom_bus_stb) & (~soc_netsoc_rom_bus_ack))) begin
soc_netsoc_rom_bus_ack <= 1'd1;
end
soc_netsoc_sram_bus_ack <= 1'd0;
if (((soc_netsoc_sram_bus_cyc & soc_netsoc_sram_bus_stb) & (~soc_netsoc_sram_bus_ack))) begin
soc_netsoc_sram_bus_ack <= 1'd1;
end
soc_netsoc_uart_phy_sink_ready <= 1'd0;
if (((soc_netsoc_uart_phy_sink_valid & (~soc_netsoc_uart_phy_tx_busy)) & (~soc_netsoc_uart_phy_sink_ready))) begin
soc_netsoc_uart_phy_tx_reg <= soc_netsoc_uart_phy_sink_payload_data;
soc_netsoc_uart_phy_tx_bitcount <= 1'd0;
soc_netsoc_uart_phy_tx_busy <= 1'd1;
serial_tx <= 1'd0;
end else begin
if ((soc_netsoc_uart_phy_uart_clk_txen & soc_netsoc_uart_phy_tx_busy)) begin
soc_netsoc_uart_phy_tx_bitcount <= (soc_netsoc_uart_phy_tx_bitcount + 1'd1);
if ((soc_netsoc_uart_phy_tx_bitcount == 4'd8)) begin
serial_tx <= 1'd1;
end else begin
if ((soc_netsoc_uart_phy_tx_bitcount == 4'd9)) begin
serial_tx <= 1'd1;
soc_netsoc_uart_phy_tx_busy <= 1'd0;
soc_netsoc_uart_phy_sink_ready <= 1'd1;
end else begin
serial_tx <= soc_netsoc_uart_phy_tx_reg[0];
soc_netsoc_uart_phy_tx_reg <= {1'd0, soc_netsoc_uart_phy_tx_reg[7:1]};
end
end
end
end
if (soc_netsoc_uart_phy_tx_busy) begin
{soc_netsoc_uart_phy_uart_clk_txen, soc_netsoc_uart_phy_phase_accumulator_tx} <= (soc_netsoc_uart_phy_phase_accumulator_tx + soc_netsoc_uart_phy_storage);
end else begin
{soc_netsoc_uart_phy_uart_clk_txen, soc_netsoc_uart_phy_phase_accumulator_tx} <= 1'd0;
end
soc_netsoc_uart_phy_source_valid <= 1'd0;
soc_netsoc_uart_phy_rx_r <= soc_netsoc_uart_phy_rx;
if ((~soc_netsoc_uart_phy_rx_busy)) begin
if (((~soc_netsoc_uart_phy_rx) & soc_netsoc_uart_phy_rx_r)) begin
soc_netsoc_uart_phy_rx_busy <= 1'd1;
soc_netsoc_uart_phy_rx_bitcount <= 1'd0;
end
end else begin
if (soc_netsoc_uart_phy_uart_clk_rxen) begin
soc_netsoc_uart_phy_rx_bitcount <= (soc_netsoc_uart_phy_rx_bitcount + 1'd1);
if ((soc_netsoc_uart_phy_rx_bitcount == 1'd0)) begin
if (soc_netsoc_uart_phy_rx) begin
soc_netsoc_uart_phy_rx_busy <= 1'd0;
end
end else begin
if ((soc_netsoc_uart_phy_rx_bitcount == 4'd9)) begin
soc_netsoc_uart_phy_rx_busy <= 1'd0;
if (soc_netsoc_uart_phy_rx) begin
soc_netsoc_uart_phy_source_payload_data <= soc_netsoc_uart_phy_rx_reg;
soc_netsoc_uart_phy_source_valid <= 1'd1;
end
end else begin
soc_netsoc_uart_phy_rx_reg <= {soc_netsoc_uart_phy_rx, soc_netsoc_uart_phy_rx_reg[7:1]};
end
end
end
end
if (soc_netsoc_uart_phy_rx_busy) begin
{soc_netsoc_uart_phy_uart_clk_rxen, soc_netsoc_uart_phy_phase_accumulator_rx} <= (soc_netsoc_uart_phy_phase_accumulator_rx + soc_netsoc_uart_phy_storage);
end else begin
{soc_netsoc_uart_phy_uart_clk_rxen, soc_netsoc_uart_phy_phase_accumulator_rx} <= 32'd2147483648;
end
if (soc_netsoc_uart_tx_clear) begin
soc_netsoc_uart_tx_pending <= 1'd0;
end
soc_netsoc_uart_tx_old_trigger <= soc_netsoc_uart_tx_trigger;
if (((~soc_netsoc_uart_tx_trigger) & soc_netsoc_uart_tx_old_trigger)) begin
soc_netsoc_uart_tx_pending <= 1'd1;
end
if (soc_netsoc_uart_rx_clear) begin
soc_netsoc_uart_rx_pending <= 1'd0;
end
soc_netsoc_uart_rx_old_trigger <= soc_netsoc_uart_rx_trigger;
if (((~soc_netsoc_uart_rx_trigger) & soc_netsoc_uart_rx_old_trigger)) begin
soc_netsoc_uart_rx_pending <= 1'd1;
end
if (soc_netsoc_uart_tx_fifo_syncfifo_re) begin
soc_netsoc_uart_tx_fifo_readable <= 1'd1;
end else begin
if (soc_netsoc_uart_tx_fifo_re) begin
soc_netsoc_uart_tx_fifo_readable <= 1'd0;
end
end
if (((soc_netsoc_uart_tx_fifo_syncfifo_we & soc_netsoc_uart_tx_fifo_syncfifo_writable) & (~soc_netsoc_uart_tx_fifo_replace))) begin
soc_netsoc_uart_tx_fifo_produce <= (soc_netsoc_uart_tx_fifo_produce + 1'd1);
end
if (soc_netsoc_uart_tx_fifo_do_read) begin
soc_netsoc_uart_tx_fifo_consume <= (soc_netsoc_uart_tx_fifo_consume + 1'd1);
end
if (((soc_netsoc_uart_tx_fifo_syncfifo_we & soc_netsoc_uart_tx_fifo_syncfifo_writable) & (~soc_netsoc_uart_tx_fifo_replace))) begin
if ((~soc_netsoc_uart_tx_fifo_do_read)) begin
soc_netsoc_uart_tx_fifo_level0 <= (soc_netsoc_uart_tx_fifo_level0 + 1'd1);
end
end else begin
if (soc_netsoc_uart_tx_fifo_do_read) begin
soc_netsoc_uart_tx_fifo_level0 <= (soc_netsoc_uart_tx_fifo_level0 - 1'd1);
end
end
if (soc_netsoc_uart_rx_fifo_syncfifo_re) begin
soc_netsoc_uart_rx_fifo_readable <= 1'd1;
end else begin
if (soc_netsoc_uart_rx_fifo_re) begin
soc_netsoc_uart_rx_fifo_readable <= 1'd0;
end
end
if (((soc_netsoc_uart_rx_fifo_syncfifo_we & soc_netsoc_uart_rx_fifo_syncfifo_writable) & (~soc_netsoc_uart_rx_fifo_replace))) begin
soc_netsoc_uart_rx_fifo_produce <= (soc_netsoc_uart_rx_fifo_produce + 1'd1);
end
if (soc_netsoc_uart_rx_fifo_do_read) begin
soc_netsoc_uart_rx_fifo_consume <= (soc_netsoc_uart_rx_fifo_consume + 1'd1);
end
if (((soc_netsoc_uart_rx_fifo_syncfifo_we & soc_netsoc_uart_rx_fifo_syncfifo_writable) & (~soc_netsoc_uart_rx_fifo_replace))) begin
if ((~soc_netsoc_uart_rx_fifo_do_read)) begin
soc_netsoc_uart_rx_fifo_level0 <= (soc_netsoc_uart_rx_fifo_level0 + 1'd1);
end
end else begin
if (soc_netsoc_uart_rx_fifo_do_read) begin
soc_netsoc_uart_rx_fifo_level0 <= (soc_netsoc_uart_rx_fifo_level0 - 1'd1);
end
end
if (soc_netsoc_uart_reset) begin
soc_netsoc_uart_tx_pending <= 1'd0;
soc_netsoc_uart_tx_old_trigger <= 1'd0;
soc_netsoc_uart_rx_pending <= 1'd0;
soc_netsoc_uart_rx_old_trigger <= 1'd0;
soc_netsoc_uart_tx_fifo_readable <= 1'd0;
soc_netsoc_uart_tx_fifo_level0 <= 5'd0;
soc_netsoc_uart_tx_fifo_produce <= 4'd0;
soc_netsoc_uart_tx_fifo_consume <= 4'd0;
soc_netsoc_uart_rx_fifo_readable <= 1'd0;
soc_netsoc_uart_rx_fifo_level0 <= 5'd0;
soc_netsoc_uart_rx_fifo_produce <= 4'd0;
soc_netsoc_uart_rx_fifo_consume <= 4'd0;
end
if (soc_netsoc_timer0_en_storage) begin
if ((soc_netsoc_timer0_value == 1'd0)) begin
soc_netsoc_timer0_value <= soc_netsoc_timer0_reload_storage;
end else begin
soc_netsoc_timer0_value <= (soc_netsoc_timer0_value - 1'd1);
end
end else begin
soc_netsoc_timer0_value <= soc_netsoc_timer0_load_storage;
end
if (soc_netsoc_timer0_update_value_re) begin
soc_netsoc_timer0_value_status <= soc_netsoc_timer0_value;
end
if (soc_netsoc_timer0_zero_clear) begin
soc_netsoc_timer0_zero_pending <= 1'd0;
end
soc_netsoc_timer0_zero_old_trigger <= soc_netsoc_timer0_zero_trigger;
if (((~soc_netsoc_timer0_zero_trigger) & soc_netsoc_timer0_zero_old_trigger)) begin
soc_netsoc_timer0_zero_pending <= 1'd1;
end
vns_wb2csr_state <= vns_wb2csr_next_state;
soc_emulator_ram_bus_ack <= 1'd0;
if (((soc_emulator_ram_bus_cyc & soc_emulator_ram_bus_stb) & (~soc_emulator_ram_bus_ack))) begin
soc_emulator_ram_bus_ack <= 1'd1;
end
if (soc_a7ddrphy_dly_sel_storage[0]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip0_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[0]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip1_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[0]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip2_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[0]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip3_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[0]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip4_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[0]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip5_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[0]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip6_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[0]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip7_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[1]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip8_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[1]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip9_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[1]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip10_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[1]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip11_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[1]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip12_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[1]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip13_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[1]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip14_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1);
end
end
end
if (soc_a7ddrphy_dly_sel_storage[1]) begin
if (soc_a7ddrphy_rdly_dq_bitslip_rst_re) begin
soc_a7ddrphy_bitslip15_value <= 1'd0;
end else begin
if (soc_a7ddrphy_rdly_dq_bitslip_re) begin
soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1);
end
end
end
soc_a7ddrphy_n_rddata_en0 <= soc_a7ddrphy_dfi_p2_rddata_en;
soc_a7ddrphy_n_rddata_en1 <= soc_a7ddrphy_n_rddata_en0;
soc_a7ddrphy_n_rddata_en2 <= soc_a7ddrphy_n_rddata_en1;
soc_a7ddrphy_n_rddata_en3 <= soc_a7ddrphy_n_rddata_en2;
soc_a7ddrphy_n_rddata_en4 <= soc_a7ddrphy_n_rddata_en3;
soc_a7ddrphy_n_rddata_en5 <= soc_a7ddrphy_n_rddata_en4;
soc_a7ddrphy_n_rddata_en6 <= soc_a7ddrphy_n_rddata_en5;
soc_a7ddrphy_n_rddata_en7 <= soc_a7ddrphy_n_rddata_en6;
soc_a7ddrphy_dfi_p0_rddata_valid <= soc_a7ddrphy_n_rddata_en7;
soc_a7ddrphy_dfi_p1_rddata_valid <= soc_a7ddrphy_n_rddata_en7;
soc_a7ddrphy_dfi_p2_rddata_valid <= soc_a7ddrphy_n_rddata_en7;
soc_a7ddrphy_dfi_p3_rddata_valid <= soc_a7ddrphy_n_rddata_en7;
soc_a7ddrphy_last_wrdata_en <= {soc_a7ddrphy_last_wrdata_en[2:0], soc_a7ddrphy_dfi_p3_wrdata_en};
soc_a7ddrphy_oe_dqs <= soc_a7ddrphy_oe;
soc_a7ddrphy_oe_dq <= soc_a7ddrphy_oe;
soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[15:8]};
case (soc_a7ddrphy_bitslip0_value)
1'd0: begin
soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7];
end
endcase
soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[15:8]};
case (soc_a7ddrphy_bitslip1_value)
1'd0: begin
soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7];
end
endcase
soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[15:8]};
case (soc_a7ddrphy_bitslip2_value)
1'd0: begin
soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7];
end
endcase
soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[15:8]};
case (soc_a7ddrphy_bitslip3_value)
1'd0: begin
soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7];
end
endcase
soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[15:8]};
case (soc_a7ddrphy_bitslip4_value)
1'd0: begin
soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7];
end
endcase
soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[15:8]};
case (soc_a7ddrphy_bitslip5_value)
1'd0: begin
soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7];
end
endcase
soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[15:8]};
case (soc_a7ddrphy_bitslip6_value)
1'd0: begin
soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7];
end
endcase
soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[15:8]};
case (soc_a7ddrphy_bitslip7_value)
1'd0: begin
soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7];
end
endcase
soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[15:8]};
case (soc_a7ddrphy_bitslip8_value)
1'd0: begin
soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7];
end
endcase
soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[15:8]};
case (soc_a7ddrphy_bitslip9_value)
1'd0: begin
soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7];
end
endcase
soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[15:8]};
case (soc_a7ddrphy_bitslip10_value)
1'd0: begin
soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7];
end
endcase
soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[15:8]};
case (soc_a7ddrphy_bitslip11_value)
1'd0: begin
soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7];
end
endcase
soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[15:8]};
case (soc_a7ddrphy_bitslip12_value)
1'd0: begin
soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7];
end
endcase
soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[15:8]};
case (soc_a7ddrphy_bitslip13_value)
1'd0: begin
soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7];
end
endcase
soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[15:8]};
case (soc_a7ddrphy_bitslip14_value)
1'd0: begin
soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7];
end
endcase
soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[15:8]};
case (soc_a7ddrphy_bitslip15_value)
1'd0: begin
soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0];
end
1'd1: begin
soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1];
end
2'd2: begin
soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2];
end
2'd3: begin
soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3];
end
3'd4: begin
soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4];
end
3'd5: begin
soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5];
end
3'd6: begin
soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6];
end
3'd7: begin
soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7];
end
endcase
if (soc_netsoc_sdram_inti_p0_rddata_valid) begin
soc_netsoc_sdram_phaseinjector0_status <= soc_netsoc_sdram_inti_p0_rddata;
end
if (soc_netsoc_sdram_inti_p1_rddata_valid) begin
soc_netsoc_sdram_phaseinjector1_status <= soc_netsoc_sdram_inti_p1_rddata;
end
if (soc_netsoc_sdram_inti_p2_rddata_valid) begin
soc_netsoc_sdram_phaseinjector2_status <= soc_netsoc_sdram_inti_p2_rddata;
end
if (soc_netsoc_sdram_inti_p3_rddata_valid) begin
soc_netsoc_sdram_phaseinjector3_status <= soc_netsoc_sdram_inti_p3_rddata;
end
if ((soc_netsoc_sdram_timer_wait & (~soc_netsoc_sdram_timer_done0))) begin
soc_netsoc_sdram_timer_count1 <= (soc_netsoc_sdram_timer_count1 - 1'd1);
end else begin
soc_netsoc_sdram_timer_count1 <= 9'd468;
end
soc_netsoc_sdram_postponer_req_o <= 1'd0;
if (soc_netsoc_sdram_postponer_req_i) begin
soc_netsoc_sdram_postponer_count <= (soc_netsoc_sdram_postponer_count - 1'd1);
if ((soc_netsoc_sdram_postponer_count == 1'd0)) begin
soc_netsoc_sdram_postponer_count <= 1'd0;
soc_netsoc_sdram_postponer_req_o <= 1'd1;
end
end
if (soc_netsoc_sdram_sequencer_start0) begin
soc_netsoc_sdram_sequencer_count <= 1'd0;
end else begin
if (soc_netsoc_sdram_sequencer_done1) begin
if ((soc_netsoc_sdram_sequencer_count != 1'd0)) begin
soc_netsoc_sdram_sequencer_count <= (soc_netsoc_sdram_sequencer_count - 1'd1);
end
end
end
soc_netsoc_sdram_cmd_payload_a <= 1'd0;
soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_cmd_payload_ras <= 1'd0;
soc_netsoc_sdram_cmd_payload_we <= 1'd0;
soc_netsoc_sdram_sequencer_done1 <= 1'd0;
if ((soc_netsoc_sdram_sequencer_start1 & (soc_netsoc_sdram_sequencer_counter == 1'd0))) begin
soc_netsoc_sdram_cmd_payload_a <= 11'd1024;
soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_cmd_payload_ras <= 1'd1;
soc_netsoc_sdram_cmd_payload_we <= 1'd1;
end
if ((soc_netsoc_sdram_sequencer_counter == 2'd2)) begin
soc_netsoc_sdram_cmd_payload_a <= 1'd0;
soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
soc_netsoc_sdram_cmd_payload_cas <= 1'd1;
soc_netsoc_sdram_cmd_payload_ras <= 1'd1;
soc_netsoc_sdram_cmd_payload_we <= 1'd0;
end
if ((soc_netsoc_sdram_sequencer_counter == 6'd34)) begin
soc_netsoc_sdram_cmd_payload_a <= 1'd0;
soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_cmd_payload_ras <= 1'd0;
soc_netsoc_sdram_cmd_payload_we <= 1'd0;
soc_netsoc_sdram_sequencer_done1 <= 1'd1;
end
if ((soc_netsoc_sdram_sequencer_counter == 6'd34)) begin
soc_netsoc_sdram_sequencer_counter <= 1'd0;
end else begin
if ((soc_netsoc_sdram_sequencer_counter != 1'd0)) begin
soc_netsoc_sdram_sequencer_counter <= (soc_netsoc_sdram_sequencer_counter + 1'd1);
end else begin
if (soc_netsoc_sdram_sequencer_start1) begin
soc_netsoc_sdram_sequencer_counter <= 1'd1;
end
end
end
if ((soc_netsoc_sdram_zqcs_timer_wait & (~soc_netsoc_sdram_zqcs_timer_done0))) begin
soc_netsoc_sdram_zqcs_timer_count1 <= (soc_netsoc_sdram_zqcs_timer_count1 - 1'd1);
end else begin
soc_netsoc_sdram_zqcs_timer_count1 <= 26'd59999999;
end
soc_netsoc_sdram_zqcs_executer_done <= 1'd0;
if ((soc_netsoc_sdram_zqcs_executer_start & (soc_netsoc_sdram_zqcs_executer_counter == 1'd0))) begin
soc_netsoc_sdram_cmd_payload_a <= 11'd1024;
soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_cmd_payload_ras <= 1'd1;
soc_netsoc_sdram_cmd_payload_we <= 1'd1;
end
if ((soc_netsoc_sdram_zqcs_executer_counter == 2'd2)) begin
soc_netsoc_sdram_cmd_payload_a <= 1'd0;
soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_cmd_payload_ras <= 1'd0;
soc_netsoc_sdram_cmd_payload_we <= 1'd1;
end
if ((soc_netsoc_sdram_zqcs_executer_counter == 5'd18)) begin
soc_netsoc_sdram_cmd_payload_a <= 1'd0;
soc_netsoc_sdram_cmd_payload_ba <= 1'd0;
soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_cmd_payload_ras <= 1'd0;
soc_netsoc_sdram_cmd_payload_we <= 1'd0;
soc_netsoc_sdram_zqcs_executer_done <= 1'd1;
end
if ((soc_netsoc_sdram_zqcs_executer_counter == 5'd18)) begin
soc_netsoc_sdram_zqcs_executer_counter <= 1'd0;
end else begin
if ((soc_netsoc_sdram_zqcs_executer_counter != 1'd0)) begin
soc_netsoc_sdram_zqcs_executer_counter <= (soc_netsoc_sdram_zqcs_executer_counter + 1'd1);
end else begin
if (soc_netsoc_sdram_zqcs_executer_start) begin
soc_netsoc_sdram_zqcs_executer_counter <= 1'd1;
end
end
end
vns_refresher_state <= vns_refresher_next_state;
if (soc_netsoc_sdram_bankmachine0_row_close) begin
soc_netsoc_sdram_bankmachine0_row_opened <= 1'd0;
end else begin
if (soc_netsoc_sdram_bankmachine0_row_open) begin
soc_netsoc_sdram_bankmachine0_row_opened <= 1'd1;
soc_netsoc_sdram_bankmachine0_row <= soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
if ((~soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin
soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
end
end
if (soc_netsoc_sdram_bankmachine0_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine0_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_valid;
end
if (soc_netsoc_sdram_bankmachine0_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine0_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_first);
soc_netsoc_sdram_bankmachine0_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_last);
end
if (soc_netsoc_sdram_bankmachine0_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_payload_we;
soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
end
if (soc_netsoc_sdram_bankmachine0_twtpcon_valid) begin
soc_netsoc_sdram_bankmachine0_twtpcon_count <= 3'd4;
if (1'd0) begin
soc_netsoc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine0_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine0_twtpcon_ready)) begin
soc_netsoc_sdram_bankmachine0_twtpcon_count <= (soc_netsoc_sdram_bankmachine0_twtpcon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine0_twtpcon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine0_trccon_valid) begin
soc_netsoc_sdram_bankmachine0_trccon_count <= 2'd3;
if (1'd0) begin
soc_netsoc_sdram_bankmachine0_trccon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine0_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine0_trccon_ready)) begin
soc_netsoc_sdram_bankmachine0_trccon_count <= (soc_netsoc_sdram_bankmachine0_trccon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine0_trccon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine0_trccon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine0_trascon_valid) begin
soc_netsoc_sdram_bankmachine0_trascon_count <= 2'd2;
if (1'd0) begin
soc_netsoc_sdram_bankmachine0_trascon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine0_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine0_trascon_ready)) begin
soc_netsoc_sdram_bankmachine0_trascon_count <= (soc_netsoc_sdram_bankmachine0_trascon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine0_trascon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine0_trascon_ready <= 1'd1;
end
end
end
vns_bankmachine0_state <= vns_bankmachine0_next_state;
if (soc_netsoc_sdram_bankmachine1_row_close) begin
soc_netsoc_sdram_bankmachine1_row_opened <= 1'd0;
end else begin
if (soc_netsoc_sdram_bankmachine1_row_open) begin
soc_netsoc_sdram_bankmachine1_row_opened <= 1'd1;
soc_netsoc_sdram_bankmachine1_row <= soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
if ((~soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin
soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
end
end
if (soc_netsoc_sdram_bankmachine1_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine1_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_valid;
end
if (soc_netsoc_sdram_bankmachine1_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine1_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_first);
soc_netsoc_sdram_bankmachine1_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_last);
end
if (soc_netsoc_sdram_bankmachine1_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_payload_we;
soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
end
if (soc_netsoc_sdram_bankmachine1_twtpcon_valid) begin
soc_netsoc_sdram_bankmachine1_twtpcon_count <= 3'd4;
if (1'd0) begin
soc_netsoc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine1_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine1_twtpcon_ready)) begin
soc_netsoc_sdram_bankmachine1_twtpcon_count <= (soc_netsoc_sdram_bankmachine1_twtpcon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine1_twtpcon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine1_trccon_valid) begin
soc_netsoc_sdram_bankmachine1_trccon_count <= 2'd3;
if (1'd0) begin
soc_netsoc_sdram_bankmachine1_trccon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine1_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine1_trccon_ready)) begin
soc_netsoc_sdram_bankmachine1_trccon_count <= (soc_netsoc_sdram_bankmachine1_trccon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine1_trccon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine1_trccon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine1_trascon_valid) begin
soc_netsoc_sdram_bankmachine1_trascon_count <= 2'd2;
if (1'd0) begin
soc_netsoc_sdram_bankmachine1_trascon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine1_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine1_trascon_ready)) begin
soc_netsoc_sdram_bankmachine1_trascon_count <= (soc_netsoc_sdram_bankmachine1_trascon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine1_trascon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine1_trascon_ready <= 1'd1;
end
end
end
vns_bankmachine1_state <= vns_bankmachine1_next_state;
if (soc_netsoc_sdram_bankmachine2_row_close) begin
soc_netsoc_sdram_bankmachine2_row_opened <= 1'd0;
end else begin
if (soc_netsoc_sdram_bankmachine2_row_open) begin
soc_netsoc_sdram_bankmachine2_row_opened <= 1'd1;
soc_netsoc_sdram_bankmachine2_row <= soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
if ((~soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin
soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
end
end
if (soc_netsoc_sdram_bankmachine2_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine2_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_valid;
end
if (soc_netsoc_sdram_bankmachine2_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine2_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_first);
soc_netsoc_sdram_bankmachine2_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_last);
end
if (soc_netsoc_sdram_bankmachine2_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_payload_we;
soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
end
if (soc_netsoc_sdram_bankmachine2_twtpcon_valid) begin
soc_netsoc_sdram_bankmachine2_twtpcon_count <= 3'd4;
if (1'd0) begin
soc_netsoc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine2_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine2_twtpcon_ready)) begin
soc_netsoc_sdram_bankmachine2_twtpcon_count <= (soc_netsoc_sdram_bankmachine2_twtpcon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine2_twtpcon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine2_trccon_valid) begin
soc_netsoc_sdram_bankmachine2_trccon_count <= 2'd3;
if (1'd0) begin
soc_netsoc_sdram_bankmachine2_trccon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine2_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine2_trccon_ready)) begin
soc_netsoc_sdram_bankmachine2_trccon_count <= (soc_netsoc_sdram_bankmachine2_trccon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine2_trccon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine2_trccon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine2_trascon_valid) begin
soc_netsoc_sdram_bankmachine2_trascon_count <= 2'd2;
if (1'd0) begin
soc_netsoc_sdram_bankmachine2_trascon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine2_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine2_trascon_ready)) begin
soc_netsoc_sdram_bankmachine2_trascon_count <= (soc_netsoc_sdram_bankmachine2_trascon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine2_trascon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine2_trascon_ready <= 1'd1;
end
end
end
vns_bankmachine2_state <= vns_bankmachine2_next_state;
if (soc_netsoc_sdram_bankmachine3_row_close) begin
soc_netsoc_sdram_bankmachine3_row_opened <= 1'd0;
end else begin
if (soc_netsoc_sdram_bankmachine3_row_open) begin
soc_netsoc_sdram_bankmachine3_row_opened <= 1'd1;
soc_netsoc_sdram_bankmachine3_row <= soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
if ((~soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin
soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
end
end
if (soc_netsoc_sdram_bankmachine3_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine3_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_valid;
end
if (soc_netsoc_sdram_bankmachine3_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine3_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_first);
soc_netsoc_sdram_bankmachine3_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_last);
end
if (soc_netsoc_sdram_bankmachine3_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_payload_we;
soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
end
if (soc_netsoc_sdram_bankmachine3_twtpcon_valid) begin
soc_netsoc_sdram_bankmachine3_twtpcon_count <= 3'd4;
if (1'd0) begin
soc_netsoc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine3_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine3_twtpcon_ready)) begin
soc_netsoc_sdram_bankmachine3_twtpcon_count <= (soc_netsoc_sdram_bankmachine3_twtpcon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine3_twtpcon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine3_trccon_valid) begin
soc_netsoc_sdram_bankmachine3_trccon_count <= 2'd3;
if (1'd0) begin
soc_netsoc_sdram_bankmachine3_trccon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine3_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine3_trccon_ready)) begin
soc_netsoc_sdram_bankmachine3_trccon_count <= (soc_netsoc_sdram_bankmachine3_trccon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine3_trccon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine3_trccon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine3_trascon_valid) begin
soc_netsoc_sdram_bankmachine3_trascon_count <= 2'd2;
if (1'd0) begin
soc_netsoc_sdram_bankmachine3_trascon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine3_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine3_trascon_ready)) begin
soc_netsoc_sdram_bankmachine3_trascon_count <= (soc_netsoc_sdram_bankmachine3_trascon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine3_trascon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine3_trascon_ready <= 1'd1;
end
end
end
vns_bankmachine3_state <= vns_bankmachine3_next_state;
if (soc_netsoc_sdram_bankmachine4_row_close) begin
soc_netsoc_sdram_bankmachine4_row_opened <= 1'd0;
end else begin
if (soc_netsoc_sdram_bankmachine4_row_open) begin
soc_netsoc_sdram_bankmachine4_row_opened <= 1'd1;
soc_netsoc_sdram_bankmachine4_row <= soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
if ((~soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin
soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
end
end
if (soc_netsoc_sdram_bankmachine4_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine4_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_valid;
end
if (soc_netsoc_sdram_bankmachine4_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine4_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_first);
soc_netsoc_sdram_bankmachine4_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_last);
end
if (soc_netsoc_sdram_bankmachine4_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_payload_we;
soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
end
if (soc_netsoc_sdram_bankmachine4_twtpcon_valid) begin
soc_netsoc_sdram_bankmachine4_twtpcon_count <= 3'd4;
if (1'd0) begin
soc_netsoc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine4_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine4_twtpcon_ready)) begin
soc_netsoc_sdram_bankmachine4_twtpcon_count <= (soc_netsoc_sdram_bankmachine4_twtpcon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine4_twtpcon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine4_trccon_valid) begin
soc_netsoc_sdram_bankmachine4_trccon_count <= 2'd3;
if (1'd0) begin
soc_netsoc_sdram_bankmachine4_trccon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine4_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine4_trccon_ready)) begin
soc_netsoc_sdram_bankmachine4_trccon_count <= (soc_netsoc_sdram_bankmachine4_trccon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine4_trccon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine4_trccon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine4_trascon_valid) begin
soc_netsoc_sdram_bankmachine4_trascon_count <= 2'd2;
if (1'd0) begin
soc_netsoc_sdram_bankmachine4_trascon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine4_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine4_trascon_ready)) begin
soc_netsoc_sdram_bankmachine4_trascon_count <= (soc_netsoc_sdram_bankmachine4_trascon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine4_trascon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine4_trascon_ready <= 1'd1;
end
end
end
vns_bankmachine4_state <= vns_bankmachine4_next_state;
if (soc_netsoc_sdram_bankmachine5_row_close) begin
soc_netsoc_sdram_bankmachine5_row_opened <= 1'd0;
end else begin
if (soc_netsoc_sdram_bankmachine5_row_open) begin
soc_netsoc_sdram_bankmachine5_row_opened <= 1'd1;
soc_netsoc_sdram_bankmachine5_row <= soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
if ((~soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin
soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
end
end
if (soc_netsoc_sdram_bankmachine5_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine5_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_valid;
end
if (soc_netsoc_sdram_bankmachine5_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine5_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_first);
soc_netsoc_sdram_bankmachine5_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_last);
end
if (soc_netsoc_sdram_bankmachine5_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_payload_we;
soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
end
if (soc_netsoc_sdram_bankmachine5_twtpcon_valid) begin
soc_netsoc_sdram_bankmachine5_twtpcon_count <= 3'd4;
if (1'd0) begin
soc_netsoc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine5_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine5_twtpcon_ready)) begin
soc_netsoc_sdram_bankmachine5_twtpcon_count <= (soc_netsoc_sdram_bankmachine5_twtpcon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine5_twtpcon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine5_trccon_valid) begin
soc_netsoc_sdram_bankmachine5_trccon_count <= 2'd3;
if (1'd0) begin
soc_netsoc_sdram_bankmachine5_trccon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine5_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine5_trccon_ready)) begin
soc_netsoc_sdram_bankmachine5_trccon_count <= (soc_netsoc_sdram_bankmachine5_trccon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine5_trccon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine5_trccon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine5_trascon_valid) begin
soc_netsoc_sdram_bankmachine5_trascon_count <= 2'd2;
if (1'd0) begin
soc_netsoc_sdram_bankmachine5_trascon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine5_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine5_trascon_ready)) begin
soc_netsoc_sdram_bankmachine5_trascon_count <= (soc_netsoc_sdram_bankmachine5_trascon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine5_trascon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine5_trascon_ready <= 1'd1;
end
end
end
vns_bankmachine5_state <= vns_bankmachine5_next_state;
if (soc_netsoc_sdram_bankmachine6_row_close) begin
soc_netsoc_sdram_bankmachine6_row_opened <= 1'd0;
end else begin
if (soc_netsoc_sdram_bankmachine6_row_open) begin
soc_netsoc_sdram_bankmachine6_row_opened <= 1'd1;
soc_netsoc_sdram_bankmachine6_row <= soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
if ((~soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin
soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
end
end
if (soc_netsoc_sdram_bankmachine6_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine6_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_valid;
end
if (soc_netsoc_sdram_bankmachine6_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine6_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_first);
soc_netsoc_sdram_bankmachine6_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_last);
end
if (soc_netsoc_sdram_bankmachine6_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_payload_we;
soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
end
if (soc_netsoc_sdram_bankmachine6_twtpcon_valid) begin
soc_netsoc_sdram_bankmachine6_twtpcon_count <= 3'd4;
if (1'd0) begin
soc_netsoc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine6_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine6_twtpcon_ready)) begin
soc_netsoc_sdram_bankmachine6_twtpcon_count <= (soc_netsoc_sdram_bankmachine6_twtpcon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine6_twtpcon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine6_trccon_valid) begin
soc_netsoc_sdram_bankmachine6_trccon_count <= 2'd3;
if (1'd0) begin
soc_netsoc_sdram_bankmachine6_trccon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine6_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine6_trccon_ready)) begin
soc_netsoc_sdram_bankmachine6_trccon_count <= (soc_netsoc_sdram_bankmachine6_trccon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine6_trccon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine6_trccon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine6_trascon_valid) begin
soc_netsoc_sdram_bankmachine6_trascon_count <= 2'd2;
if (1'd0) begin
soc_netsoc_sdram_bankmachine6_trascon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine6_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine6_trascon_ready)) begin
soc_netsoc_sdram_bankmachine6_trascon_count <= (soc_netsoc_sdram_bankmachine6_trascon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine6_trascon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine6_trascon_ready <= 1'd1;
end
end
end
vns_bankmachine6_state <= vns_bankmachine6_next_state;
if (soc_netsoc_sdram_bankmachine7_row_close) begin
soc_netsoc_sdram_bankmachine7_row_opened <= 1'd0;
end else begin
if (soc_netsoc_sdram_bankmachine7_row_open) begin
soc_netsoc_sdram_bankmachine7_row_opened <= 1'd1;
soc_netsoc_sdram_bankmachine7_row <= soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7];
end
end
if (((soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
end
if (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
end
if (((soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
if ((~soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin
soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
end
end
if (soc_netsoc_sdram_bankmachine7_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine7_cmd_buffer_valid_n <= soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_valid;
end
if (soc_netsoc_sdram_bankmachine7_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine7_cmd_buffer_first_n <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_first);
soc_netsoc_sdram_bankmachine7_cmd_buffer_last_n <= (soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_valid & soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_last);
end
if (soc_netsoc_sdram_bankmachine7_cmd_buffer_pipe_ce) begin
soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_we <= soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_payload_we;
soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr <= soc_netsoc_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
end
if (soc_netsoc_sdram_bankmachine7_twtpcon_valid) begin
soc_netsoc_sdram_bankmachine7_twtpcon_count <= 3'd4;
if (1'd0) begin
soc_netsoc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine7_twtpcon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine7_twtpcon_ready)) begin
soc_netsoc_sdram_bankmachine7_twtpcon_count <= (soc_netsoc_sdram_bankmachine7_twtpcon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine7_twtpcon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine7_trccon_valid) begin
soc_netsoc_sdram_bankmachine7_trccon_count <= 2'd3;
if (1'd0) begin
soc_netsoc_sdram_bankmachine7_trccon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine7_trccon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine7_trccon_ready)) begin
soc_netsoc_sdram_bankmachine7_trccon_count <= (soc_netsoc_sdram_bankmachine7_trccon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine7_trccon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine7_trccon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_bankmachine7_trascon_valid) begin
soc_netsoc_sdram_bankmachine7_trascon_count <= 2'd2;
if (1'd0) begin
soc_netsoc_sdram_bankmachine7_trascon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_bankmachine7_trascon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_bankmachine7_trascon_ready)) begin
soc_netsoc_sdram_bankmachine7_trascon_count <= (soc_netsoc_sdram_bankmachine7_trascon_count - 1'd1);
if ((soc_netsoc_sdram_bankmachine7_trascon_count == 1'd1)) begin
soc_netsoc_sdram_bankmachine7_trascon_ready <= 1'd1;
end
end
end
vns_bankmachine7_state <= vns_bankmachine7_next_state;
if ((~soc_netsoc_sdram_en0)) begin
soc_netsoc_sdram_time0 <= 5'd31;
end else begin
if ((~soc_netsoc_sdram_max_time0)) begin
soc_netsoc_sdram_time0 <= (soc_netsoc_sdram_time0 - 1'd1);
end
end
if ((~soc_netsoc_sdram_en1)) begin
soc_netsoc_sdram_time1 <= 4'd15;
end else begin
if ((~soc_netsoc_sdram_max_time1)) begin
soc_netsoc_sdram_time1 <= (soc_netsoc_sdram_time1 - 1'd1);
end
end
if (soc_netsoc_sdram_choose_cmd_ce) begin
case (soc_netsoc_sdram_choose_cmd_grant)
1'd0: begin
if (soc_netsoc_sdram_choose_cmd_request[1]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[2]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[3]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[4]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[5]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[6]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[7]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
end
end
end
end
end
end
end
end
1'd1: begin
if (soc_netsoc_sdram_choose_cmd_request[2]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[3]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[4]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[5]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[6]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[7]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[0]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
end
end
end
end
end
end
end
end
2'd2: begin
if (soc_netsoc_sdram_choose_cmd_request[3]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[4]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[5]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[6]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[7]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[0]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[1]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
end
end
end
end
end
end
end
end
2'd3: begin
if (soc_netsoc_sdram_choose_cmd_request[4]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[5]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[6]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[7]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[0]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[1]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[2]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
end
end
end
end
end
end
end
end
3'd4: begin
if (soc_netsoc_sdram_choose_cmd_request[5]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[6]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[7]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[0]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[1]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[2]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[3]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
end
end
end
end
end
end
end
end
3'd5: begin
if (soc_netsoc_sdram_choose_cmd_request[6]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[7]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[0]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[1]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[2]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[3]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[4]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
end
end
end
end
end
end
end
end
3'd6: begin
if (soc_netsoc_sdram_choose_cmd_request[7]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[0]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[1]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[2]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[3]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[4]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[5]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
end
end
end
end
end
end
end
end
3'd7: begin
if (soc_netsoc_sdram_choose_cmd_request[0]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[1]) begin
soc_netsoc_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[2]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[3]) begin
soc_netsoc_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[4]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[5]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (soc_netsoc_sdram_choose_cmd_request[6]) begin
soc_netsoc_sdram_choose_cmd_grant <= 3'd6;
end
end
end
end
end
end
end
end
endcase
end
if (soc_netsoc_sdram_choose_req_ce) begin
case (soc_netsoc_sdram_choose_req_grant)
1'd0: begin
if (soc_netsoc_sdram_choose_req_request[1]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd1;
end else begin
if (soc_netsoc_sdram_choose_req_request[2]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd2;
end else begin
if (soc_netsoc_sdram_choose_req_request[3]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd3;
end else begin
if (soc_netsoc_sdram_choose_req_request[4]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd4;
end else begin
if (soc_netsoc_sdram_choose_req_request[5]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd5;
end else begin
if (soc_netsoc_sdram_choose_req_request[6]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd6;
end else begin
if (soc_netsoc_sdram_choose_req_request[7]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd7;
end
end
end
end
end
end
end
end
1'd1: begin
if (soc_netsoc_sdram_choose_req_request[2]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd2;
end else begin
if (soc_netsoc_sdram_choose_req_request[3]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd3;
end else begin
if (soc_netsoc_sdram_choose_req_request[4]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd4;
end else begin
if (soc_netsoc_sdram_choose_req_request[5]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd5;
end else begin
if (soc_netsoc_sdram_choose_req_request[6]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd6;
end else begin
if (soc_netsoc_sdram_choose_req_request[7]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd7;
end else begin
if (soc_netsoc_sdram_choose_req_request[0]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd0;
end
end
end
end
end
end
end
end
2'd2: begin
if (soc_netsoc_sdram_choose_req_request[3]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd3;
end else begin
if (soc_netsoc_sdram_choose_req_request[4]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd4;
end else begin
if (soc_netsoc_sdram_choose_req_request[5]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd5;
end else begin
if (soc_netsoc_sdram_choose_req_request[6]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd6;
end else begin
if (soc_netsoc_sdram_choose_req_request[7]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd7;
end else begin
if (soc_netsoc_sdram_choose_req_request[0]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd0;
end else begin
if (soc_netsoc_sdram_choose_req_request[1]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd1;
end
end
end
end
end
end
end
end
2'd3: begin
if (soc_netsoc_sdram_choose_req_request[4]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd4;
end else begin
if (soc_netsoc_sdram_choose_req_request[5]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd5;
end else begin
if (soc_netsoc_sdram_choose_req_request[6]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd6;
end else begin
if (soc_netsoc_sdram_choose_req_request[7]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd7;
end else begin
if (soc_netsoc_sdram_choose_req_request[0]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd0;
end else begin
if (soc_netsoc_sdram_choose_req_request[1]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd1;
end else begin
if (soc_netsoc_sdram_choose_req_request[2]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd2;
end
end
end
end
end
end
end
end
3'd4: begin
if (soc_netsoc_sdram_choose_req_request[5]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd5;
end else begin
if (soc_netsoc_sdram_choose_req_request[6]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd6;
end else begin
if (soc_netsoc_sdram_choose_req_request[7]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd7;
end else begin
if (soc_netsoc_sdram_choose_req_request[0]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd0;
end else begin
if (soc_netsoc_sdram_choose_req_request[1]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd1;
end else begin
if (soc_netsoc_sdram_choose_req_request[2]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd2;
end else begin
if (soc_netsoc_sdram_choose_req_request[3]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd3;
end
end
end
end
end
end
end
end
3'd5: begin
if (soc_netsoc_sdram_choose_req_request[6]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd6;
end else begin
if (soc_netsoc_sdram_choose_req_request[7]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd7;
end else begin
if (soc_netsoc_sdram_choose_req_request[0]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd0;
end else begin
if (soc_netsoc_sdram_choose_req_request[1]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd1;
end else begin
if (soc_netsoc_sdram_choose_req_request[2]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd2;
end else begin
if (soc_netsoc_sdram_choose_req_request[3]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd3;
end else begin
if (soc_netsoc_sdram_choose_req_request[4]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd4;
end
end
end
end
end
end
end
end
3'd6: begin
if (soc_netsoc_sdram_choose_req_request[7]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd7;
end else begin
if (soc_netsoc_sdram_choose_req_request[0]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd0;
end else begin
if (soc_netsoc_sdram_choose_req_request[1]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd1;
end else begin
if (soc_netsoc_sdram_choose_req_request[2]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd2;
end else begin
if (soc_netsoc_sdram_choose_req_request[3]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd3;
end else begin
if (soc_netsoc_sdram_choose_req_request[4]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd4;
end else begin
if (soc_netsoc_sdram_choose_req_request[5]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd5;
end
end
end
end
end
end
end
end
3'd7: begin
if (soc_netsoc_sdram_choose_req_request[0]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd0;
end else begin
if (soc_netsoc_sdram_choose_req_request[1]) begin
soc_netsoc_sdram_choose_req_grant <= 1'd1;
end else begin
if (soc_netsoc_sdram_choose_req_request[2]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd2;
end else begin
if (soc_netsoc_sdram_choose_req_request[3]) begin
soc_netsoc_sdram_choose_req_grant <= 2'd3;
end else begin
if (soc_netsoc_sdram_choose_req_request[4]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd4;
end else begin
if (soc_netsoc_sdram_choose_req_request[5]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd5;
end else begin
if (soc_netsoc_sdram_choose_req_request[6]) begin
soc_netsoc_sdram_choose_req_grant <= 3'd6;
end
end
end
end
end
end
end
end
endcase
end
soc_netsoc_sdram_dfi_p0_cs_n <= 1'd0;
soc_netsoc_sdram_dfi_p0_bank <= vns_array_muxed0;
soc_netsoc_sdram_dfi_p0_address <= vns_array_muxed1;
soc_netsoc_sdram_dfi_p0_cas_n <= (~vns_array_muxed2);
soc_netsoc_sdram_dfi_p0_ras_n <= (~vns_array_muxed3);
soc_netsoc_sdram_dfi_p0_we_n <= (~vns_array_muxed4);
soc_netsoc_sdram_dfi_p0_rddata_en <= vns_array_muxed5;
soc_netsoc_sdram_dfi_p0_wrdata_en <= vns_array_muxed6;
soc_netsoc_sdram_dfi_p1_cs_n <= 1'd0;
soc_netsoc_sdram_dfi_p1_bank <= vns_array_muxed7;
soc_netsoc_sdram_dfi_p1_address <= vns_array_muxed8;
soc_netsoc_sdram_dfi_p1_cas_n <= (~vns_array_muxed9);
soc_netsoc_sdram_dfi_p1_ras_n <= (~vns_array_muxed10);
soc_netsoc_sdram_dfi_p1_we_n <= (~vns_array_muxed11);
soc_netsoc_sdram_dfi_p1_rddata_en <= vns_array_muxed12;
soc_netsoc_sdram_dfi_p1_wrdata_en <= vns_array_muxed13;
soc_netsoc_sdram_dfi_p2_cs_n <= 1'd0;
soc_netsoc_sdram_dfi_p2_bank <= vns_array_muxed14;
soc_netsoc_sdram_dfi_p2_address <= vns_array_muxed15;
soc_netsoc_sdram_dfi_p2_cas_n <= (~vns_array_muxed16);
soc_netsoc_sdram_dfi_p2_ras_n <= (~vns_array_muxed17);
soc_netsoc_sdram_dfi_p2_we_n <= (~vns_array_muxed18);
soc_netsoc_sdram_dfi_p2_rddata_en <= vns_array_muxed19;
soc_netsoc_sdram_dfi_p2_wrdata_en <= vns_array_muxed20;
soc_netsoc_sdram_dfi_p3_cs_n <= 1'd0;
soc_netsoc_sdram_dfi_p3_bank <= vns_array_muxed21;
soc_netsoc_sdram_dfi_p3_address <= vns_array_muxed22;
soc_netsoc_sdram_dfi_p3_cas_n <= (~vns_array_muxed23);
soc_netsoc_sdram_dfi_p3_ras_n <= (~vns_array_muxed24);
soc_netsoc_sdram_dfi_p3_we_n <= (~vns_array_muxed25);
soc_netsoc_sdram_dfi_p3_rddata_en <= vns_array_muxed26;
soc_netsoc_sdram_dfi_p3_wrdata_en <= vns_array_muxed27;
if (soc_netsoc_sdram_trrdcon_valid) begin
soc_netsoc_sdram_trrdcon_count <= 1'd1;
if (1'd0) begin
soc_netsoc_sdram_trrdcon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_trrdcon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_trrdcon_ready)) begin
soc_netsoc_sdram_trrdcon_count <= (soc_netsoc_sdram_trrdcon_count - 1'd1);
if ((soc_netsoc_sdram_trrdcon_count == 1'd1)) begin
soc_netsoc_sdram_trrdcon_ready <= 1'd1;
end
end
end
soc_netsoc_sdram_tfawcon_window <= {soc_netsoc_sdram_tfawcon_window, soc_netsoc_sdram_tfawcon_valid};
if ((soc_netsoc_sdram_tfawcon_count < 3'd4)) begin
if ((soc_netsoc_sdram_tfawcon_count == 2'd3)) begin
soc_netsoc_sdram_tfawcon_ready <= (~soc_netsoc_sdram_tfawcon_valid);
end else begin
soc_netsoc_sdram_tfawcon_ready <= 1'd1;
end
end
if (soc_netsoc_sdram_tccdcon_valid) begin
soc_netsoc_sdram_tccdcon_count <= 1'd0;
if (1'd1) begin
soc_netsoc_sdram_tccdcon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_tccdcon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_tccdcon_ready)) begin
soc_netsoc_sdram_tccdcon_count <= (soc_netsoc_sdram_tccdcon_count - 1'd1);
if ((soc_netsoc_sdram_tccdcon_count == 1'd1)) begin
soc_netsoc_sdram_tccdcon_ready <= 1'd1;
end
end
end
if (soc_netsoc_sdram_twtrcon_valid) begin
soc_netsoc_sdram_twtrcon_count <= 3'd4;
if (1'd0) begin
soc_netsoc_sdram_twtrcon_ready <= 1'd1;
end else begin
soc_netsoc_sdram_twtrcon_ready <= 1'd0;
end
end else begin
if ((~soc_netsoc_sdram_twtrcon_ready)) begin
soc_netsoc_sdram_twtrcon_count <= (soc_netsoc_sdram_twtrcon_count - 1'd1);
if ((soc_netsoc_sdram_twtrcon_count == 1'd1)) begin
soc_netsoc_sdram_twtrcon_ready <= 1'd1;
end
end
end
vns_multiplexer_state <= vns_multiplexer_next_state;
soc_netsoc_sdram_bandwidth_cmd_valid <= soc_netsoc_sdram_choose_req_cmd_valid;
soc_netsoc_sdram_bandwidth_cmd_ready <= soc_netsoc_sdram_choose_req_cmd_ready;
soc_netsoc_sdram_bandwidth_cmd_is_read <= soc_netsoc_sdram_choose_req_cmd_payload_is_read;
soc_netsoc_sdram_bandwidth_cmd_is_write <= soc_netsoc_sdram_choose_req_cmd_payload_is_write;
{soc_netsoc_sdram_bandwidth_period, soc_netsoc_sdram_bandwidth_counter} <= (soc_netsoc_sdram_bandwidth_counter + 1'd1);
if (soc_netsoc_sdram_bandwidth_period) begin
soc_netsoc_sdram_bandwidth_nreads_r <= soc_netsoc_sdram_bandwidth_nreads;
soc_netsoc_sdram_bandwidth_nwrites_r <= soc_netsoc_sdram_bandwidth_nwrites;
soc_netsoc_sdram_bandwidth_nreads <= 1'd0;
soc_netsoc_sdram_bandwidth_nwrites <= 1'd0;
end else begin
if ((soc_netsoc_sdram_bandwidth_cmd_valid & soc_netsoc_sdram_bandwidth_cmd_ready)) begin
if (soc_netsoc_sdram_bandwidth_cmd_is_read) begin
soc_netsoc_sdram_bandwidth_nreads <= (soc_netsoc_sdram_bandwidth_nreads + 1'd1);
end
if (soc_netsoc_sdram_bandwidth_cmd_is_write) begin
soc_netsoc_sdram_bandwidth_nwrites <= (soc_netsoc_sdram_bandwidth_nwrites + 1'd1);
end
end
end
if (soc_netsoc_sdram_bandwidth_update_re) begin
soc_netsoc_sdram_bandwidth_nreads_status <= soc_netsoc_sdram_bandwidth_nreads_r;
soc_netsoc_sdram_bandwidth_nwrites_status <= soc_netsoc_sdram_bandwidth_nwrites_r;
end
if (((vns_roundrobin0_grant == 1'd0) & soc_netsoc_sdram_interface_bank0_rdata_valid)) begin
vns_rbank <= 1'd0;
end
if (((vns_roundrobin0_grant == 1'd0) & soc_netsoc_sdram_interface_bank0_wdata_ready)) begin
vns_wbank <= 1'd0;
end
if (((vns_roundrobin1_grant == 1'd0) & soc_netsoc_sdram_interface_bank1_rdata_valid)) begin
vns_rbank <= 1'd1;
end
if (((vns_roundrobin1_grant == 1'd0) & soc_netsoc_sdram_interface_bank1_wdata_ready)) begin
vns_wbank <= 1'd1;
end
if (((vns_roundrobin2_grant == 1'd0) & soc_netsoc_sdram_interface_bank2_rdata_valid)) begin
vns_rbank <= 2'd2;
end
if (((vns_roundrobin2_grant == 1'd0) & soc_netsoc_sdram_interface_bank2_wdata_ready)) begin
vns_wbank <= 2'd2;
end
if (((vns_roundrobin3_grant == 1'd0) & soc_netsoc_sdram_interface_bank3_rdata_valid)) begin
vns_rbank <= 2'd3;
end
if (((vns_roundrobin3_grant == 1'd0) & soc_netsoc_sdram_interface_bank3_wdata_ready)) begin
vns_wbank <= 2'd3;
end
if (((vns_roundrobin4_grant == 1'd0) & soc_netsoc_sdram_interface_bank4_rdata_valid)) begin
vns_rbank <= 3'd4;
end
if (((vns_roundrobin4_grant == 1'd0) & soc_netsoc_sdram_interface_bank4_wdata_ready)) begin
vns_wbank <= 3'd4;
end
if (((vns_roundrobin5_grant == 1'd0) & soc_netsoc_sdram_interface_bank5_rdata_valid)) begin
vns_rbank <= 3'd5;
end
if (((vns_roundrobin5_grant == 1'd0) & soc_netsoc_sdram_interface_bank5_wdata_ready)) begin
vns_wbank <= 3'd5;
end
if (((vns_roundrobin6_grant == 1'd0) & soc_netsoc_sdram_interface_bank6_rdata_valid)) begin
vns_rbank <= 3'd6;
end
if (((vns_roundrobin6_grant == 1'd0) & soc_netsoc_sdram_interface_bank6_wdata_ready)) begin
vns_wbank <= 3'd6;
end
if (((vns_roundrobin7_grant == 1'd0) & soc_netsoc_sdram_interface_bank7_rdata_valid)) begin
vns_rbank <= 3'd7;
end
if (((vns_roundrobin7_grant == 1'd0) & soc_netsoc_sdram_interface_bank7_wdata_ready)) begin
vns_wbank <= 3'd7;
end
vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_netsoc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_netsoc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_netsoc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_netsoc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_netsoc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_netsoc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_netsoc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_netsoc_sdram_interface_bank7_wdata_ready));
vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0;
vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1;
vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_netsoc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_netsoc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_netsoc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_netsoc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_netsoc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_netsoc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_netsoc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_netsoc_sdram_interface_bank7_rdata_valid));
vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0;
vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1;
vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2;
vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3;
vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4;
vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5;
vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6;
vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7;
vns_new_master_rdata_valid9 <= vns_new_master_rdata_valid8;
soc_netsoc_adr_offset_r <= soc_netsoc_interface0_wb_sdram_adr[1:0];
vns_fullmemorywe_state <= vns_fullmemorywe_next_state;
vns_litedramwishbone2native_state <= vns_litedramwishbone2native_next_state;
if (soc_netsoc_count_litedramwishbone2native_next_value_ce) begin
soc_netsoc_count <= soc_netsoc_count_litedramwishbone2native_next_value;
end
if (soc_counter_ce) begin
soc_counter <= (soc_counter + 1'd1);
end
if (soc_ps_preamble_error_o) begin
soc_preamble_errors_status <= (soc_preamble_errors_status + 1'd1);
end
if (soc_ps_crc_error_o) begin
soc_crc_errors_status <= (soc_crc_errors_status + 1'd1);
end
soc_ps_preamble_error_toggle_o_r <= soc_ps_preamble_error_toggle_o;
soc_ps_crc_error_toggle_o_r <= soc_ps_crc_error_toggle_o;
soc_tx_cdc_graycounter0_q_binary <= soc_tx_cdc_graycounter0_q_next_binary;
soc_tx_cdc_graycounter0_q <= soc_tx_cdc_graycounter0_q_next;
soc_rx_cdc_graycounter1_q_binary <= soc_rx_cdc_graycounter1_q_next_binary;
soc_rx_cdc_graycounter1_q <= soc_rx_cdc_graycounter1_q_next;
if (soc_writer_counter_reset) begin
soc_writer_counter <= 1'd0;
end else begin
if (soc_writer_counter_ce) begin
soc_writer_counter <= (soc_writer_counter + soc_writer_inc);
end
end
if (soc_writer_slot_ce) begin
soc_writer_slot <= (soc_writer_slot + 1'd1);
end
if (((soc_writer_fifo_syncfifo_we & soc_writer_fifo_syncfifo_writable) & (~soc_writer_fifo_replace))) begin
soc_writer_fifo_produce <= (soc_writer_fifo_produce + 1'd1);
end
if (soc_writer_fifo_do_read) begin
soc_writer_fifo_consume <= (soc_writer_fifo_consume + 1'd1);
end
if (((soc_writer_fifo_syncfifo_we & soc_writer_fifo_syncfifo_writable) & (~soc_writer_fifo_replace))) begin
if ((~soc_writer_fifo_do_read)) begin
soc_writer_fifo_level <= (soc_writer_fifo_level + 1'd1);
end
end else begin
if (soc_writer_fifo_do_read) begin
soc_writer_fifo_level <= (soc_writer_fifo_level - 1'd1);
end
end
vns_liteethmacsramwriter_state <= vns_liteethmacsramwriter_next_state;
if (soc_writer_errors_status_liteethmac_next_value_ce) begin
soc_writer_errors_status <= soc_writer_errors_status_liteethmac_next_value;
end
if (soc_reader_counter_reset) begin
soc_reader_counter <= 1'd0;
end else begin
if (soc_reader_counter_ce) begin
soc_reader_counter <= (soc_reader_counter + 3'd4);
end
end
soc_reader_last_d <= soc_reader_last;
if (soc_reader_done_clear) begin
soc_reader_done_pending <= 1'd0;
end
if (soc_reader_done_trigger) begin
soc_reader_done_pending <= 1'd1;
end
if (((soc_reader_fifo_syncfifo_we & soc_reader_fifo_syncfifo_writable) & (~soc_reader_fifo_replace))) begin
soc_reader_fifo_produce <= (soc_reader_fifo_produce + 1'd1);
end
if (soc_reader_fifo_do_read) begin
soc_reader_fifo_consume <= (soc_reader_fifo_consume + 1'd1);
end
if (((soc_reader_fifo_syncfifo_we & soc_reader_fifo_syncfifo_writable) & (~soc_reader_fifo_replace))) begin
if ((~soc_reader_fifo_do_read)) begin
soc_reader_fifo_level <= (soc_reader_fifo_level + 1'd1);
end
end else begin
if (soc_reader_fifo_do_read) begin
soc_reader_fifo_level <= (soc_reader_fifo_level - 1'd1);
end
end
vns_liteethmacsramreader_state <= vns_liteethmacsramreader_next_state;
soc_sram0_bus_ack0 <= 1'd0;
if (((soc_sram0_bus_cyc0 & soc_sram0_bus_stb0) & (~soc_sram0_bus_ack0))) begin
soc_sram0_bus_ack0 <= 1'd1;
end
soc_sram1_bus_ack0 <= 1'd0;
if (((soc_sram1_bus_cyc0 & soc_sram1_bus_stb0) & (~soc_sram1_bus_ack0))) begin
soc_sram1_bus_ack0 <= 1'd1;
end
soc_sram0_bus_ack1 <= 1'd0;
if (((soc_sram0_bus_cyc1 & soc_sram0_bus_stb1) & (~soc_sram0_bus_ack1))) begin
soc_sram0_bus_ack1 <= 1'd1;
end
soc_sram1_bus_ack1 <= 1'd0;
if (((soc_sram1_bus_cyc1 & soc_sram1_bus_stb1) & (~soc_sram1_bus_ack1))) begin
soc_sram1_bus_ack1 <= 1'd1;
end
soc_slave_sel_r <= soc_slave_sel;
case (vns_netsoc_grant)
1'd0: begin
if ((~vns_netsoc_request[0])) begin
if (vns_netsoc_request[1]) begin
vns_netsoc_grant <= 1'd1;
end
end
end
1'd1: begin
if ((~vns_netsoc_request[1])) begin
if (vns_netsoc_request[0]) begin
vns_netsoc_grant <= 1'd0;
end
end
end
endcase
vns_netsoc_slave_sel_r <= vns_netsoc_slave_sel;
if (vns_netsoc_wait) begin
if ((~vns_netsoc_done)) begin
vns_netsoc_count <= (vns_netsoc_count - 1'd1);
end
end else begin
vns_netsoc_count <= 20'd1000000;
end
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= 1'd0;
if (vns_netsoc_csrbankarray_csrbank0_sel) begin
case (vns_netsoc_csrbankarray_interface0_bank_bus_adr[4:0])
1'd0: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= soc_netsoc_cpu_latch_w;
end
1'd1: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time7_w;
end
2'd2: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time6_w;
end
2'd3: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time5_w;
end
3'd4: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time4_w;
end
3'd5: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time3_w;
end
3'd6: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time2_w;
end
3'd7: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time1_w;
end
4'd8: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time0_w;
end
4'd9: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_w;
end
4'd10: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_w;
end
4'd11: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_w;
end
4'd12: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_w;
end
4'd13: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_w;
end
4'd14: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_w;
end
4'd15: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_w;
end
5'd16: begin
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_w;
end
endcase
end
if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_re) begin
soc_netsoc_cpu_time_cmp_storage[63:56] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp7_r;
end
if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_re) begin
soc_netsoc_cpu_time_cmp_storage[55:48] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp6_r;
end
if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_re) begin
soc_netsoc_cpu_time_cmp_storage[47:40] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp5_r;
end
if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_re) begin
soc_netsoc_cpu_time_cmp_storage[39:32] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp4_r;
end
if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_re) begin
soc_netsoc_cpu_time_cmp_storage[31:24] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp3_r;
end
if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_re) begin
soc_netsoc_cpu_time_cmp_storage[23:16] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp2_r;
end
if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_re) begin
soc_netsoc_cpu_time_cmp_storage[15:8] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp1_r;
end
if (vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_re) begin
soc_netsoc_cpu_time_cmp_storage[7:0] <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_r;
end
soc_netsoc_cpu_time_cmp_re <= vns_netsoc_csrbankarray_csrbank0_timer_time_cmp0_re;
vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= 1'd0;
if (vns_netsoc_csrbankarray_csrbank1_sel) begin
case (vns_netsoc_csrbankarray_interface1_bank_bus_adr[3:0])
1'd0: begin
vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= soc_netsoc_ctrl_reset_reset_w;
end
1'd1: begin
vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_scratch3_w;
end
2'd2: begin
vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_scratch2_w;
end
2'd3: begin
vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_scratch1_w;
end
3'd4: begin
vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_scratch0_w;
end
3'd5: begin
vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_bus_errors3_w;
end
3'd6: begin
vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_bus_errors2_w;
end
3'd7: begin
vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_bus_errors1_w;
end
4'd8: begin
vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank1_bus_errors0_w;
end
endcase
end
if (vns_netsoc_csrbankarray_csrbank1_scratch3_re) begin
soc_netsoc_ctrl_storage[31:24] <= vns_netsoc_csrbankarray_csrbank1_scratch3_r;
end
if (vns_netsoc_csrbankarray_csrbank1_scratch2_re) begin
soc_netsoc_ctrl_storage[23:16] <= vns_netsoc_csrbankarray_csrbank1_scratch2_r;
end
if (vns_netsoc_csrbankarray_csrbank1_scratch1_re) begin
soc_netsoc_ctrl_storage[15:8] <= vns_netsoc_csrbankarray_csrbank1_scratch1_r;
end
if (vns_netsoc_csrbankarray_csrbank1_scratch0_re) begin
soc_netsoc_ctrl_storage[7:0] <= vns_netsoc_csrbankarray_csrbank1_scratch0_r;
end
soc_netsoc_ctrl_re <= vns_netsoc_csrbankarray_csrbank1_scratch0_re;
vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= 1'd0;
if (vns_netsoc_csrbankarray_csrbank2_sel) begin
case (vns_netsoc_csrbankarray_interface2_bank_bus_adr[2:0])
1'd0: begin
vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_w;
end
1'd1: begin
vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w;
end
2'd2: begin
vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w;
end
2'd3: begin
vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank2_dly_sel0_w;
end
3'd4: begin
vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w;
end
3'd5: begin
vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w;
end
3'd6: begin
vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w;
end
3'd7: begin
vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w;
end
endcase
end
if (vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_re) begin
soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_r;
end
soc_a7ddrphy_half_sys8x_taps_re <= vns_netsoc_csrbankarray_csrbank2_half_sys8x_taps0_re;
if (vns_netsoc_csrbankarray_csrbank2_dly_sel0_re) begin
soc_a7ddrphy_dly_sel_storage[1:0] <= vns_netsoc_csrbankarray_csrbank2_dly_sel0_r;
end
soc_a7ddrphy_dly_sel_re <= vns_netsoc_csrbankarray_csrbank2_dly_sel0_re;
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= 1'd0;
if (vns_netsoc_csrbankarray_csrbank3_sel) begin
case (vns_netsoc_csrbankarray_interface3_bank_bus_adr[4:0])
1'd0: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_slot_w;
end
1'd1: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_length3_w;
end
2'd2: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_length2_w;
end
2'd3: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_length1_w;
end
3'd4: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_length0_w;
end
3'd5: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_errors3_w;
end
3'd6: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_errors2_w;
end
3'd7: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_errors1_w;
end
4'd8: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_errors0_w;
end
4'd9: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= soc_writer_status_w;
end
4'd10: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= soc_writer_pending_w;
end
4'd11: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_w;
end
4'd12: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= soc_reader_start_w;
end
4'd13: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_reader_ready_w;
end
4'd14: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_reader_level_w;
end
4'd15: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_w;
end
5'd16: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_w;
end
5'd17: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_w;
end
5'd18: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= soc_reader_eventmanager_status_w;
end
5'd19: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= soc_reader_eventmanager_pending_w;
end
5'd20: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_w;
end
5'd21: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_preamble_crc_w;
end
5'd22: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_preamble_errors3_w;
end
5'd23: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_preamble_errors2_w;
end
5'd24: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_preamble_errors1_w;
end
5'd25: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_preamble_errors0_w;
end
5'd26: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_crc_errors3_w;
end
5'd27: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_crc_errors2_w;
end
5'd28: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_crc_errors1_w;
end
5'd29: begin
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank3_crc_errors0_w;
end
endcase
end
if (vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_re) begin
soc_writer_storage <= vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_r;
end
soc_writer_re <= vns_netsoc_csrbankarray_csrbank3_sram_writer_ev_enable0_re;
if (vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_re) begin
soc_reader_slot_storage <= vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_r;
end
soc_reader_slot_re <= vns_netsoc_csrbankarray_csrbank3_sram_reader_slot0_re;
if (vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_re) begin
soc_reader_length_storage[10:8] <= vns_netsoc_csrbankarray_csrbank3_sram_reader_length1_r;
end
if (vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_re) begin
soc_reader_length_storage[7:0] <= vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_r;
end
soc_reader_length_re <= vns_netsoc_csrbankarray_csrbank3_sram_reader_length0_re;
if (vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_re) begin
soc_reader_eventmanager_storage <= vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_r;
end
soc_reader_eventmanager_re <= vns_netsoc_csrbankarray_csrbank3_sram_reader_ev_enable0_re;
vns_netsoc_csrbankarray_interface4_bank_bus_dat_r <= 1'd0;
if (vns_netsoc_csrbankarray_csrbank4_sel) begin
case (vns_netsoc_csrbankarray_interface4_bank_bus_adr[1:0])
1'd0: begin
vns_netsoc_csrbankarray_interface4_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank4_crg_reset0_w;
end
1'd1: begin
vns_netsoc_csrbankarray_interface4_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank4_mdio_w0_w;
end
2'd2: begin
vns_netsoc_csrbankarray_interface4_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank4_mdio_r_w;
end
endcase
end
if (vns_netsoc_csrbankarray_csrbank4_crg_reset0_re) begin
soc_reset_storage <= vns_netsoc_csrbankarray_csrbank4_crg_reset0_r;
end
soc_reset_re <= vns_netsoc_csrbankarray_csrbank4_crg_reset0_re;
if (vns_netsoc_csrbankarray_csrbank4_mdio_w0_re) begin
soc_storage[2:0] <= vns_netsoc_csrbankarray_csrbank4_mdio_w0_r;
end
soc_re <= vns_netsoc_csrbankarray_csrbank4_mdio_w0_re;
vns_netsoc_csrbankarray_sel_r <= vns_netsoc_csrbankarray_sel;
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= 1'd0;
if (vns_netsoc_csrbankarray_csrbank5_sel) begin
case (vns_netsoc_csrbankarray_interface5_bank_bus_adr[5:0])
1'd0: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_control0_w;
end
1'd1: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_w;
end
2'd2: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= soc_netsoc_sdram_phaseinjector0_command_issue_w;
end
2'd3: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_w;
end
3'd4: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_w;
end
3'd5: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_w;
end
3'd6: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_w;
end
3'd7: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_w;
end
4'd8: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_w;
end
4'd9: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_w;
end
4'd10: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata3_w;
end
4'd11: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata2_w;
end
4'd12: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata1_w;
end
4'd13: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_rddata0_w;
end
4'd14: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_w;
end
4'd15: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= soc_netsoc_sdram_phaseinjector1_command_issue_w;
end
5'd16: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_w;
end
5'd17: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_w;
end
5'd18: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_w;
end
5'd19: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_w;
end
5'd20: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_w;
end
5'd21: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_w;
end
5'd22: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_w;
end
5'd23: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata3_w;
end
5'd24: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata2_w;
end
5'd25: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata1_w;
end
5'd26: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_rddata0_w;
end
5'd27: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_w;
end
5'd28: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= soc_netsoc_sdram_phaseinjector2_command_issue_w;
end
5'd29: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_w;
end
5'd30: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_w;
end
5'd31: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_w;
end
6'd32: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_w;
end
6'd33: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_w;
end
6'd34: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_w;
end
6'd35: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_w;
end
6'd36: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata3_w;
end
6'd37: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata2_w;
end
6'd38: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata1_w;
end
6'd39: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_rddata0_w;
end
6'd40: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_w;
end
6'd41: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= soc_netsoc_sdram_phaseinjector3_command_issue_w;
end
6'd42: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_w;
end
6'd43: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_w;
end
6'd44: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_w;
end
6'd45: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_w;
end
6'd46: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_w;
end
6'd47: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_w;
end
6'd48: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_w;
end
6'd49: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata3_w;
end
6'd50: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata2_w;
end
6'd51: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata1_w;
end
6'd52: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_rddata0_w;
end
6'd53: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= soc_netsoc_sdram_bandwidth_update_w;
end
6'd54: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads2_w;
end
6'd55: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads1_w;
end
6'd56: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nreads0_w;
end
6'd57: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites2_w;
end
6'd58: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites1_w;
end
6'd59: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_nwrites0_w;
end
6'd60: begin
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank5_controller_bandwidth_data_width_w;
end
endcase
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_control0_re) begin
soc_netsoc_sdram_storage[3:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_control0_r;
end
soc_netsoc_sdram_re <= vns_netsoc_csrbankarray_csrbank5_dfii_control0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_re) begin
soc_netsoc_sdram_phaseinjector0_command_storage[5:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_r;
end
soc_netsoc_sdram_phaseinjector0_command_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_command0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_re) begin
soc_netsoc_sdram_phaseinjector0_address_storage[13:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address1_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_re) begin
soc_netsoc_sdram_phaseinjector0_address_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_r;
end
soc_netsoc_sdram_phaseinjector0_address_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_address0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_re) begin
soc_netsoc_sdram_phaseinjector0_baddress_storage[2:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_r;
end
soc_netsoc_sdram_phaseinjector0_baddress_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_baddress0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_re) begin
soc_netsoc_sdram_phaseinjector0_wrdata_storage[31:24] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata3_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_re) begin
soc_netsoc_sdram_phaseinjector0_wrdata_storage[23:16] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata2_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_re) begin
soc_netsoc_sdram_phaseinjector0_wrdata_storage[15:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata1_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_re) begin
soc_netsoc_sdram_phaseinjector0_wrdata_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_r;
end
soc_netsoc_sdram_phaseinjector0_wrdata_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi0_wrdata0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_re) begin
soc_netsoc_sdram_phaseinjector1_command_storage[5:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_r;
end
soc_netsoc_sdram_phaseinjector1_command_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_command0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_re) begin
soc_netsoc_sdram_phaseinjector1_address_storage[13:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address1_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_re) begin
soc_netsoc_sdram_phaseinjector1_address_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_r;
end
soc_netsoc_sdram_phaseinjector1_address_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_address0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_re) begin
soc_netsoc_sdram_phaseinjector1_baddress_storage[2:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_r;
end
soc_netsoc_sdram_phaseinjector1_baddress_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_baddress0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_re) begin
soc_netsoc_sdram_phaseinjector1_wrdata_storage[31:24] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata3_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_re) begin
soc_netsoc_sdram_phaseinjector1_wrdata_storage[23:16] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata2_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_re) begin
soc_netsoc_sdram_phaseinjector1_wrdata_storage[15:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata1_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_re) begin
soc_netsoc_sdram_phaseinjector1_wrdata_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_r;
end
soc_netsoc_sdram_phaseinjector1_wrdata_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi1_wrdata0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_re) begin
soc_netsoc_sdram_phaseinjector2_command_storage[5:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_r;
end
soc_netsoc_sdram_phaseinjector2_command_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_command0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_re) begin
soc_netsoc_sdram_phaseinjector2_address_storage[13:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address1_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_re) begin
soc_netsoc_sdram_phaseinjector2_address_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_r;
end
soc_netsoc_sdram_phaseinjector2_address_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_address0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_re) begin
soc_netsoc_sdram_phaseinjector2_baddress_storage[2:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_r;
end
soc_netsoc_sdram_phaseinjector2_baddress_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_baddress0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_re) begin
soc_netsoc_sdram_phaseinjector2_wrdata_storage[31:24] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata3_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_re) begin
soc_netsoc_sdram_phaseinjector2_wrdata_storage[23:16] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata2_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_re) begin
soc_netsoc_sdram_phaseinjector2_wrdata_storage[15:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata1_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_re) begin
soc_netsoc_sdram_phaseinjector2_wrdata_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_r;
end
soc_netsoc_sdram_phaseinjector2_wrdata_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi2_wrdata0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_re) begin
soc_netsoc_sdram_phaseinjector3_command_storage[5:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_r;
end
soc_netsoc_sdram_phaseinjector3_command_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_command0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_re) begin
soc_netsoc_sdram_phaseinjector3_address_storage[13:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address1_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_re) begin
soc_netsoc_sdram_phaseinjector3_address_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_r;
end
soc_netsoc_sdram_phaseinjector3_address_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_address0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_re) begin
soc_netsoc_sdram_phaseinjector3_baddress_storage[2:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_r;
end
soc_netsoc_sdram_phaseinjector3_baddress_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_baddress0_re;
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_re) begin
soc_netsoc_sdram_phaseinjector3_wrdata_storage[31:24] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata3_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_re) begin
soc_netsoc_sdram_phaseinjector3_wrdata_storage[23:16] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata2_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_re) begin
soc_netsoc_sdram_phaseinjector3_wrdata_storage[15:8] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata1_r;
end
if (vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_re) begin
soc_netsoc_sdram_phaseinjector3_wrdata_storage[7:0] <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_r;
end
soc_netsoc_sdram_phaseinjector3_wrdata_re <= vns_netsoc_csrbankarray_csrbank5_dfii_pi3_wrdata0_re;
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= 1'd0;
if (vns_netsoc_csrbankarray_csrbank6_sel) begin
case (vns_netsoc_csrbankarray_interface6_bank_bus_adr[4:0])
1'd0: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_load3_w;
end
1'd1: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_load2_w;
end
2'd2: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_load1_w;
end
2'd3: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_load0_w;
end
3'd4: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_reload3_w;
end
3'd5: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_reload2_w;
end
3'd6: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_reload1_w;
end
3'd7: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_reload0_w;
end
4'd8: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_en0_w;
end
4'd9: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_update_value0_w;
end
4'd10: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_value3_w;
end
4'd11: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_value2_w;
end
4'd12: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_value1_w;
end
4'd13: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_value0_w;
end
4'd14: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= soc_netsoc_timer0_eventmanager_status_w;
end
4'd15: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= soc_netsoc_timer0_eventmanager_pending_w;
end
5'd16: begin
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank6_ev_enable0_w;
end
endcase
end
if (vns_netsoc_csrbankarray_csrbank6_load3_re) begin
soc_netsoc_timer0_load_storage[31:24] <= vns_netsoc_csrbankarray_csrbank6_load3_r;
end
if (vns_netsoc_csrbankarray_csrbank6_load2_re) begin
soc_netsoc_timer0_load_storage[23:16] <= vns_netsoc_csrbankarray_csrbank6_load2_r;
end
if (vns_netsoc_csrbankarray_csrbank6_load1_re) begin
soc_netsoc_timer0_load_storage[15:8] <= vns_netsoc_csrbankarray_csrbank6_load1_r;
end
if (vns_netsoc_csrbankarray_csrbank6_load0_re) begin
soc_netsoc_timer0_load_storage[7:0] <= vns_netsoc_csrbankarray_csrbank6_load0_r;
end
soc_netsoc_timer0_load_re <= vns_netsoc_csrbankarray_csrbank6_load0_re;
if (vns_netsoc_csrbankarray_csrbank6_reload3_re) begin
soc_netsoc_timer0_reload_storage[31:24] <= vns_netsoc_csrbankarray_csrbank6_reload3_r;
end
if (vns_netsoc_csrbankarray_csrbank6_reload2_re) begin
soc_netsoc_timer0_reload_storage[23:16] <= vns_netsoc_csrbankarray_csrbank6_reload2_r;
end
if (vns_netsoc_csrbankarray_csrbank6_reload1_re) begin
soc_netsoc_timer0_reload_storage[15:8] <= vns_netsoc_csrbankarray_csrbank6_reload1_r;
end
if (vns_netsoc_csrbankarray_csrbank6_reload0_re) begin
soc_netsoc_timer0_reload_storage[7:0] <= vns_netsoc_csrbankarray_csrbank6_reload0_r;
end
soc_netsoc_timer0_reload_re <= vns_netsoc_csrbankarray_csrbank6_reload0_re;
if (vns_netsoc_csrbankarray_csrbank6_en0_re) begin
soc_netsoc_timer0_en_storage <= vns_netsoc_csrbankarray_csrbank6_en0_r;
end
soc_netsoc_timer0_en_re <= vns_netsoc_csrbankarray_csrbank6_en0_re;
if (vns_netsoc_csrbankarray_csrbank6_update_value0_re) begin
soc_netsoc_timer0_update_value_storage <= vns_netsoc_csrbankarray_csrbank6_update_value0_r;
end
soc_netsoc_timer0_update_value_re <= vns_netsoc_csrbankarray_csrbank6_update_value0_re;
if (vns_netsoc_csrbankarray_csrbank6_ev_enable0_re) begin
soc_netsoc_timer0_eventmanager_storage <= vns_netsoc_csrbankarray_csrbank6_ev_enable0_r;
end
soc_netsoc_timer0_eventmanager_re <= vns_netsoc_csrbankarray_csrbank6_ev_enable0_re;
vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= 1'd0;
if (vns_netsoc_csrbankarray_csrbank7_sel) begin
case (vns_netsoc_csrbankarray_interface7_bank_bus_adr[2:0])
1'd0: begin
vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= soc_netsoc_uart_rxtx_w;
end
1'd1: begin
vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank7_txfull_w;
end
2'd2: begin
vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank7_rxempty_w;
end
2'd3: begin
vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= soc_netsoc_uart_eventmanager_status_w;
end
3'd4: begin
vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= soc_netsoc_uart_eventmanager_pending_w;
end
3'd5: begin
vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank7_ev_enable0_w;
end
endcase
end
if (vns_netsoc_csrbankarray_csrbank7_ev_enable0_re) begin
soc_netsoc_uart_eventmanager_storage[1:0] <= vns_netsoc_csrbankarray_csrbank7_ev_enable0_r;
end
soc_netsoc_uart_eventmanager_re <= vns_netsoc_csrbankarray_csrbank7_ev_enable0_re;
vns_netsoc_csrbankarray_interface8_bank_bus_dat_r <= 1'd0;
if (vns_netsoc_csrbankarray_csrbank8_sel) begin
case (vns_netsoc_csrbankarray_interface8_bank_bus_adr[1:0])
1'd0: begin
vns_netsoc_csrbankarray_interface8_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank8_tuning_word3_w;
end
1'd1: begin
vns_netsoc_csrbankarray_interface8_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank8_tuning_word2_w;
end
2'd2: begin
vns_netsoc_csrbankarray_interface8_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank8_tuning_word1_w;
end
2'd3: begin
vns_netsoc_csrbankarray_interface8_bank_bus_dat_r <= vns_netsoc_csrbankarray_csrbank8_tuning_word0_w;
end
endcase
end
if (vns_netsoc_csrbankarray_csrbank8_tuning_word3_re) begin
soc_netsoc_uart_phy_storage[31:24] <= vns_netsoc_csrbankarray_csrbank8_tuning_word3_r;
end
if (vns_netsoc_csrbankarray_csrbank8_tuning_word2_re) begin
soc_netsoc_uart_phy_storage[23:16] <= vns_netsoc_csrbankarray_csrbank8_tuning_word2_r;
end
if (vns_netsoc_csrbankarray_csrbank8_tuning_word1_re) begin
soc_netsoc_uart_phy_storage[15:8] <= vns_netsoc_csrbankarray_csrbank8_tuning_word1_r;
end
if (vns_netsoc_csrbankarray_csrbank8_tuning_word0_re) begin
soc_netsoc_uart_phy_storage[7:0] <= vns_netsoc_csrbankarray_csrbank8_tuning_word0_r;
end
soc_netsoc_uart_phy_re <= vns_netsoc_csrbankarray_csrbank8_tuning_word0_re;
if (sys_rst) begin
soc_netsoc_ctrl_storage <= 32'd305419896;
soc_netsoc_ctrl_re <= 1'd0;
soc_netsoc_ctrl_bus_errors <= 32'd0;
soc_netsoc_cpu_time_status <= 64'd0;
soc_netsoc_cpu_time_cmp_storage <= 64'd18446744073709551615;
soc_netsoc_cpu_time_cmp_re <= 1'd0;
soc_netsoc_cpu_time <= 64'd0;
soc_netsoc_cpu_time_cmp <= 64'd18446744073709551615;
soc_netsoc_rom_bus_ack <= 1'd0;
soc_netsoc_sram_bus_ack <= 1'd0;
serial_tx <= 1'd1;
soc_netsoc_uart_phy_storage <= 32'd8246337;
soc_netsoc_uart_phy_re <= 1'd0;
soc_netsoc_uart_phy_sink_ready <= 1'd0;
soc_netsoc_uart_phy_uart_clk_txen <= 1'd0;
soc_netsoc_uart_phy_phase_accumulator_tx <= 32'd0;
soc_netsoc_uart_phy_tx_reg <= 8'd0;
soc_netsoc_uart_phy_tx_bitcount <= 4'd0;
soc_netsoc_uart_phy_tx_busy <= 1'd0;
soc_netsoc_uart_phy_source_valid <= 1'd0;
soc_netsoc_uart_phy_source_payload_data <= 8'd0;
soc_netsoc_uart_phy_uart_clk_rxen <= 1'd0;
soc_netsoc_uart_phy_phase_accumulator_rx <= 32'd0;
soc_netsoc_uart_phy_rx_r <= 1'd0;
soc_netsoc_uart_phy_rx_reg <= 8'd0;
soc_netsoc_uart_phy_rx_bitcount <= 4'd0;
soc_netsoc_uart_phy_rx_busy <= 1'd0;
soc_netsoc_uart_tx_pending <= 1'd0;
soc_netsoc_uart_tx_old_trigger <= 1'd0;
soc_netsoc_uart_rx_pending <= 1'd0;
soc_netsoc_uart_rx_old_trigger <= 1'd0;
soc_netsoc_uart_eventmanager_storage <= 2'd0;
soc_netsoc_uart_eventmanager_re <= 1'd0;
soc_netsoc_uart_tx_fifo_readable <= 1'd0;
soc_netsoc_uart_tx_fifo_level0 <= 5'd0;
soc_netsoc_uart_tx_fifo_produce <= 4'd0;
soc_netsoc_uart_tx_fifo_consume <= 4'd0;
soc_netsoc_uart_rx_fifo_readable <= 1'd0;
soc_netsoc_uart_rx_fifo_level0 <= 5'd0;
soc_netsoc_uart_rx_fifo_produce <= 4'd0;
soc_netsoc_uart_rx_fifo_consume <= 4'd0;
soc_netsoc_timer0_load_storage <= 32'd0;
soc_netsoc_timer0_load_re <= 1'd0;
soc_netsoc_timer0_reload_storage <= 32'd0;
soc_netsoc_timer0_reload_re <= 1'd0;
soc_netsoc_timer0_en_storage <= 1'd0;
soc_netsoc_timer0_en_re <= 1'd0;
soc_netsoc_timer0_update_value_storage <= 1'd0;
soc_netsoc_timer0_update_value_re <= 1'd0;
soc_netsoc_timer0_value_status <= 32'd0;
soc_netsoc_timer0_zero_pending <= 1'd0;
soc_netsoc_timer0_zero_old_trigger <= 1'd0;
soc_netsoc_timer0_eventmanager_storage <= 1'd0;
soc_netsoc_timer0_eventmanager_re <= 1'd0;
soc_netsoc_timer0_value <= 32'd0;
soc_emulator_ram_bus_ack <= 1'd0;
soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
soc_a7ddrphy_half_sys8x_taps_re <= 1'd0;
soc_a7ddrphy_dly_sel_storage <= 2'd0;
soc_a7ddrphy_dly_sel_re <= 1'd0;
soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
soc_a7ddrphy_oe_dqs <= 1'd0;
soc_a7ddrphy_oe_dq <= 1'd0;
soc_a7ddrphy_bitslip0_o <= 8'd0;
soc_a7ddrphy_bitslip0_value <= 3'd0;
soc_a7ddrphy_bitslip0_r <= 16'd0;
soc_a7ddrphy_bitslip1_o <= 8'd0;
soc_a7ddrphy_bitslip1_value <= 3'd0;
soc_a7ddrphy_bitslip1_r <= 16'd0;
soc_a7ddrphy_bitslip2_o <= 8'd0;
soc_a7ddrphy_bitslip2_value <= 3'd0;
soc_a7ddrphy_bitslip2_r <= 16'd0;
soc_a7ddrphy_bitslip3_o <= 8'd0;
soc_a7ddrphy_bitslip3_value <= 3'd0;
soc_a7ddrphy_bitslip3_r <= 16'd0;
soc_a7ddrphy_bitslip4_o <= 8'd0;
soc_a7ddrphy_bitslip4_value <= 3'd0;
soc_a7ddrphy_bitslip4_r <= 16'd0;
soc_a7ddrphy_bitslip5_o <= 8'd0;
soc_a7ddrphy_bitslip5_value <= 3'd0;
soc_a7ddrphy_bitslip5_r <= 16'd0;
soc_a7ddrphy_bitslip6_o <= 8'd0;
soc_a7ddrphy_bitslip6_value <= 3'd0;
soc_a7ddrphy_bitslip6_r <= 16'd0;
soc_a7ddrphy_bitslip7_o <= 8'd0;
soc_a7ddrphy_bitslip7_value <= 3'd0;
soc_a7ddrphy_bitslip7_r <= 16'd0;
soc_a7ddrphy_bitslip8_o <= 8'd0;
soc_a7ddrphy_bitslip8_value <= 3'd0;
soc_a7ddrphy_bitslip8_r <= 16'd0;
soc_a7ddrphy_bitslip9_o <= 8'd0;
soc_a7ddrphy_bitslip9_value <= 3'd0;
soc_a7ddrphy_bitslip9_r <= 16'd0;
soc_a7ddrphy_bitslip10_o <= 8'd0;
soc_a7ddrphy_bitslip10_value <= 3'd0;
soc_a7ddrphy_bitslip10_r <= 16'd0;
soc_a7ddrphy_bitslip11_o <= 8'd0;
soc_a7ddrphy_bitslip11_value <= 3'd0;
soc_a7ddrphy_bitslip11_r <= 16'd0;
soc_a7ddrphy_bitslip12_o <= 8'd0;
soc_a7ddrphy_bitslip12_value <= 3'd0;
soc_a7ddrphy_bitslip12_r <= 16'd0;
soc_a7ddrphy_bitslip13_o <= 8'd0;
soc_a7ddrphy_bitslip13_value <= 3'd0;
soc_a7ddrphy_bitslip13_r <= 16'd0;
soc_a7ddrphy_bitslip14_o <= 8'd0;
soc_a7ddrphy_bitslip14_value <= 3'd0;
soc_a7ddrphy_bitslip14_r <= 16'd0;
soc_a7ddrphy_bitslip15_o <= 8'd0;
soc_a7ddrphy_bitslip15_value <= 3'd0;
soc_a7ddrphy_bitslip15_r <= 16'd0;
soc_a7ddrphy_n_rddata_en0 <= 1'd0;
soc_a7ddrphy_n_rddata_en1 <= 1'd0;
soc_a7ddrphy_n_rddata_en2 <= 1'd0;
soc_a7ddrphy_n_rddata_en3 <= 1'd0;
soc_a7ddrphy_n_rddata_en4 <= 1'd0;
soc_a7ddrphy_n_rddata_en5 <= 1'd0;
soc_a7ddrphy_n_rddata_en6 <= 1'd0;
soc_a7ddrphy_n_rddata_en7 <= 1'd0;
soc_a7ddrphy_last_wrdata_en <= 4'd0;
soc_netsoc_sdram_storage <= 4'd0;
soc_netsoc_sdram_re <= 1'd0;
soc_netsoc_sdram_phaseinjector0_command_storage <= 6'd0;
soc_netsoc_sdram_phaseinjector0_command_re <= 1'd0;
soc_netsoc_sdram_phaseinjector0_address_storage <= 14'd0;
soc_netsoc_sdram_phaseinjector0_address_re <= 1'd0;
soc_netsoc_sdram_phaseinjector0_baddress_storage <= 3'd0;
soc_netsoc_sdram_phaseinjector0_baddress_re <= 1'd0;
soc_netsoc_sdram_phaseinjector0_wrdata_storage <= 32'd0;
soc_netsoc_sdram_phaseinjector0_wrdata_re <= 1'd0;
soc_netsoc_sdram_phaseinjector0_status <= 32'd0;
soc_netsoc_sdram_phaseinjector1_command_storage <= 6'd0;
soc_netsoc_sdram_phaseinjector1_command_re <= 1'd0;
soc_netsoc_sdram_phaseinjector1_address_storage <= 14'd0;
soc_netsoc_sdram_phaseinjector1_address_re <= 1'd0;
soc_netsoc_sdram_phaseinjector1_baddress_storage <= 3'd0;
soc_netsoc_sdram_phaseinjector1_baddress_re <= 1'd0;
soc_netsoc_sdram_phaseinjector1_wrdata_storage <= 32'd0;
soc_netsoc_sdram_phaseinjector1_wrdata_re <= 1'd0;
soc_netsoc_sdram_phaseinjector1_status <= 32'd0;
soc_netsoc_sdram_phaseinjector2_command_storage <= 6'd0;
soc_netsoc_sdram_phaseinjector2_command_re <= 1'd0;
soc_netsoc_sdram_phaseinjector2_address_storage <= 14'd0;
soc_netsoc_sdram_phaseinjector2_address_re <= 1'd0;
soc_netsoc_sdram_phaseinjector2_baddress_storage <= 3'd0;
soc_netsoc_sdram_phaseinjector2_baddress_re <= 1'd0;
soc_netsoc_sdram_phaseinjector2_wrdata_storage <= 32'd0;
soc_netsoc_sdram_phaseinjector2_wrdata_re <= 1'd0;
soc_netsoc_sdram_phaseinjector2_status <= 32'd0;
soc_netsoc_sdram_phaseinjector3_command_storage <= 6'd0;
soc_netsoc_sdram_phaseinjector3_command_re <= 1'd0;
soc_netsoc_sdram_phaseinjector3_address_storage <= 14'd0;
soc_netsoc_sdram_phaseinjector3_address_re <= 1'd0;
soc_netsoc_sdram_phaseinjector3_baddress_storage <= 3'd0;
soc_netsoc_sdram_phaseinjector3_baddress_re <= 1'd0;
soc_netsoc_sdram_phaseinjector3_wrdata_storage <= 32'd0;
soc_netsoc_sdram_phaseinjector3_wrdata_re <= 1'd0;
soc_netsoc_sdram_phaseinjector3_status <= 32'd0;
soc_netsoc_sdram_dfi_p0_address <= 14'd0;
soc_netsoc_sdram_dfi_p0_bank <= 3'd0;
soc_netsoc_sdram_dfi_p0_cas_n <= 1'd1;
soc_netsoc_sdram_dfi_p0_cs_n <= 1'd1;
soc_netsoc_sdram_dfi_p0_ras_n <= 1'd1;
soc_netsoc_sdram_dfi_p0_we_n <= 1'd1;
soc_netsoc_sdram_dfi_p0_wrdata_en <= 1'd0;
soc_netsoc_sdram_dfi_p0_rddata_en <= 1'd0;
soc_netsoc_sdram_dfi_p1_address <= 14'd0;
soc_netsoc_sdram_dfi_p1_bank <= 3'd0;
soc_netsoc_sdram_dfi_p1_cas_n <= 1'd1;
soc_netsoc_sdram_dfi_p1_cs_n <= 1'd1;
soc_netsoc_sdram_dfi_p1_ras_n <= 1'd1;
soc_netsoc_sdram_dfi_p1_we_n <= 1'd1;
soc_netsoc_sdram_dfi_p1_wrdata_en <= 1'd0;
soc_netsoc_sdram_dfi_p1_rddata_en <= 1'd0;
soc_netsoc_sdram_dfi_p2_address <= 14'd0;
soc_netsoc_sdram_dfi_p2_bank <= 3'd0;
soc_netsoc_sdram_dfi_p2_cas_n <= 1'd1;
soc_netsoc_sdram_dfi_p2_cs_n <= 1'd1;
soc_netsoc_sdram_dfi_p2_ras_n <= 1'd1;
soc_netsoc_sdram_dfi_p2_we_n <= 1'd1;
soc_netsoc_sdram_dfi_p2_wrdata_en <= 1'd0;
soc_netsoc_sdram_dfi_p2_rddata_en <= 1'd0;
soc_netsoc_sdram_dfi_p3_address <= 14'd0;
soc_netsoc_sdram_dfi_p3_bank <= 3'd0;
soc_netsoc_sdram_dfi_p3_cas_n <= 1'd1;
soc_netsoc_sdram_dfi_p3_cs_n <= 1'd1;
soc_netsoc_sdram_dfi_p3_ras_n <= 1'd1;
soc_netsoc_sdram_dfi_p3_we_n <= 1'd1;
soc_netsoc_sdram_dfi_p3_wrdata_en <= 1'd0;
soc_netsoc_sdram_dfi_p3_rddata_en <= 1'd0;
soc_netsoc_sdram_cmd_payload_a <= 14'd0;
soc_netsoc_sdram_cmd_payload_ba <= 3'd0;
soc_netsoc_sdram_cmd_payload_cas <= 1'd0;
soc_netsoc_sdram_cmd_payload_ras <= 1'd0;
soc_netsoc_sdram_cmd_payload_we <= 1'd0;
soc_netsoc_sdram_timer_count1 <= 9'd468;
soc_netsoc_sdram_postponer_req_o <= 1'd0;
soc_netsoc_sdram_postponer_count <= 1'd0;
soc_netsoc_sdram_sequencer_done1 <= 1'd0;
soc_netsoc_sdram_sequencer_counter <= 6'd0;
soc_netsoc_sdram_sequencer_count <= 1'd0;
soc_netsoc_sdram_zqcs_timer_count1 <= 26'd59999999;
soc_netsoc_sdram_zqcs_executer_done <= 1'd0;
soc_netsoc_sdram_zqcs_executer_counter <= 5'd0;
soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0;
soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0;
soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0;
soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0;
soc_netsoc_sdram_bankmachine0_cmd_buffer_valid_n <= 1'd0;
soc_netsoc_sdram_bankmachine0_cmd_buffer_first_n <= 1'd0;
soc_netsoc_sdram_bankmachine0_cmd_buffer_last_n <= 1'd0;
soc_netsoc_sdram_bankmachine0_row <= 14'd0;
soc_netsoc_sdram_bankmachine0_row_opened <= 1'd0;
soc_netsoc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine0_twtpcon_count <= 3'd0;
soc_netsoc_sdram_bankmachine0_trccon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine0_trccon_count <= 2'd0;
soc_netsoc_sdram_bankmachine0_trascon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine0_trascon_count <= 2'd0;
soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0;
soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0;
soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0;
soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0;
soc_netsoc_sdram_bankmachine1_cmd_buffer_valid_n <= 1'd0;
soc_netsoc_sdram_bankmachine1_cmd_buffer_first_n <= 1'd0;
soc_netsoc_sdram_bankmachine1_cmd_buffer_last_n <= 1'd0;
soc_netsoc_sdram_bankmachine1_row <= 14'd0;
soc_netsoc_sdram_bankmachine1_row_opened <= 1'd0;
soc_netsoc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine1_twtpcon_count <= 3'd0;
soc_netsoc_sdram_bankmachine1_trccon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine1_trccon_count <= 2'd0;
soc_netsoc_sdram_bankmachine1_trascon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine1_trascon_count <= 2'd0;
soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0;
soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0;
soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0;
soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0;
soc_netsoc_sdram_bankmachine2_cmd_buffer_valid_n <= 1'd0;
soc_netsoc_sdram_bankmachine2_cmd_buffer_first_n <= 1'd0;
soc_netsoc_sdram_bankmachine2_cmd_buffer_last_n <= 1'd0;
soc_netsoc_sdram_bankmachine2_row <= 14'd0;
soc_netsoc_sdram_bankmachine2_row_opened <= 1'd0;
soc_netsoc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine2_twtpcon_count <= 3'd0;
soc_netsoc_sdram_bankmachine2_trccon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine2_trccon_count <= 2'd0;
soc_netsoc_sdram_bankmachine2_trascon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine2_trascon_count <= 2'd0;
soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0;
soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0;
soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0;
soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0;
soc_netsoc_sdram_bankmachine3_cmd_buffer_valid_n <= 1'd0;
soc_netsoc_sdram_bankmachine3_cmd_buffer_first_n <= 1'd0;
soc_netsoc_sdram_bankmachine3_cmd_buffer_last_n <= 1'd0;
soc_netsoc_sdram_bankmachine3_row <= 14'd0;
soc_netsoc_sdram_bankmachine3_row_opened <= 1'd0;
soc_netsoc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine3_twtpcon_count <= 3'd0;
soc_netsoc_sdram_bankmachine3_trccon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine3_trccon_count <= 2'd0;
soc_netsoc_sdram_bankmachine3_trascon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine3_trascon_count <= 2'd0;
soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_level <= 4'd0;
soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 3'd0;
soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 3'd0;
soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0;
soc_netsoc_sdram_bankmachine4_cmd_buffer_valid_n <= 1'd0;
soc_netsoc_sdram_bankmachine4_cmd_buffer_first_n <= 1'd0;
soc_netsoc_sdram_bankmachine4_cmd_buffer_last_n <= 1'd0;
soc_netsoc_sdram_bankmachine4_row <= 14'd0;
soc_netsoc_sdram_bankmachine4_row_opened <= 1'd0;
soc_netsoc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine4_twtpcon_count <= 3'd0;
soc_netsoc_sdram_bankmachine4_trccon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine4_trccon_count <= 2'd0;
soc_netsoc_sdram_bankmachine4_trascon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine4_trascon_count <= 2'd0;
soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_level <= 4'd0;
soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 3'd0;
soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 3'd0;
soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0;
soc_netsoc_sdram_bankmachine5_cmd_buffer_valid_n <= 1'd0;
soc_netsoc_sdram_bankmachine5_cmd_buffer_first_n <= 1'd0;
soc_netsoc_sdram_bankmachine5_cmd_buffer_last_n <= 1'd0;
soc_netsoc_sdram_bankmachine5_row <= 14'd0;
soc_netsoc_sdram_bankmachine5_row_opened <= 1'd0;
soc_netsoc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine5_twtpcon_count <= 3'd0;
soc_netsoc_sdram_bankmachine5_trccon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine5_trccon_count <= 2'd0;
soc_netsoc_sdram_bankmachine5_trascon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine5_trascon_count <= 2'd0;
soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_level <= 4'd0;
soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 3'd0;
soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 3'd0;
soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0;
soc_netsoc_sdram_bankmachine6_cmd_buffer_valid_n <= 1'd0;
soc_netsoc_sdram_bankmachine6_cmd_buffer_first_n <= 1'd0;
soc_netsoc_sdram_bankmachine6_cmd_buffer_last_n <= 1'd0;
soc_netsoc_sdram_bankmachine6_row <= 14'd0;
soc_netsoc_sdram_bankmachine6_row_opened <= 1'd0;
soc_netsoc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine6_twtpcon_count <= 3'd0;
soc_netsoc_sdram_bankmachine6_trccon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine6_trccon_count <= 2'd0;
soc_netsoc_sdram_bankmachine6_trascon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine6_trascon_count <= 2'd0;
soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_level <= 4'd0;
soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 3'd0;
soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 3'd0;
soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
soc_netsoc_sdram_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0;
soc_netsoc_sdram_bankmachine7_cmd_buffer_valid_n <= 1'd0;
soc_netsoc_sdram_bankmachine7_cmd_buffer_first_n <= 1'd0;
soc_netsoc_sdram_bankmachine7_cmd_buffer_last_n <= 1'd0;
soc_netsoc_sdram_bankmachine7_row <= 14'd0;
soc_netsoc_sdram_bankmachine7_row_opened <= 1'd0;
soc_netsoc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine7_twtpcon_count <= 3'd0;
soc_netsoc_sdram_bankmachine7_trccon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine7_trccon_count <= 2'd0;
soc_netsoc_sdram_bankmachine7_trascon_ready <= 1'd1;
soc_netsoc_sdram_bankmachine7_trascon_count <= 2'd0;
soc_netsoc_sdram_choose_cmd_grant <= 3'd0;
soc_netsoc_sdram_choose_req_grant <= 3'd0;
soc_netsoc_sdram_trrdcon_ready <= 1'd1;
soc_netsoc_sdram_trrdcon_count <= 1'd0;
soc_netsoc_sdram_tfawcon_ready <= 1'd1;
soc_netsoc_sdram_tfawcon_window <= 4'd0;
soc_netsoc_sdram_tccdcon_ready <= 1'd1;
soc_netsoc_sdram_tccdcon_count <= 1'd0;
soc_netsoc_sdram_twtrcon_ready <= 1'd1;
soc_netsoc_sdram_twtrcon_count <= 3'd0;
soc_netsoc_sdram_time0 <= 5'd0;
soc_netsoc_sdram_time1 <= 4'd0;
soc_netsoc_sdram_bandwidth_nreads_status <= 24'd0;
soc_netsoc_sdram_bandwidth_nwrites_status <= 24'd0;
soc_netsoc_sdram_bandwidth_cmd_valid <= 1'd0;
soc_netsoc_sdram_bandwidth_cmd_ready <= 1'd0;
soc_netsoc_sdram_bandwidth_cmd_is_read <= 1'd0;
soc_netsoc_sdram_bandwidth_cmd_is_write <= 1'd0;
soc_netsoc_sdram_bandwidth_counter <= 24'd0;
soc_netsoc_sdram_bandwidth_period <= 1'd0;
soc_netsoc_sdram_bandwidth_nreads <= 24'd0;
soc_netsoc_sdram_bandwidth_nwrites <= 24'd0;
soc_netsoc_sdram_bandwidth_nreads_r <= 24'd0;
soc_netsoc_sdram_bandwidth_nwrites_r <= 24'd0;
soc_netsoc_adr_offset_r <= 2'd0;
soc_netsoc_count <= 1'd0;
soc_reset_storage <= 1'd0;
soc_reset_re <= 1'd0;
soc_counter <= 9'd0;
soc_storage <= 3'd0;
soc_re <= 1'd0;
soc_preamble_errors_status <= 32'd0;
soc_crc_errors_status <= 32'd0;
soc_tx_cdc_graycounter0_q <= 7'd0;
soc_tx_cdc_graycounter0_q_binary <= 7'd0;
soc_rx_cdc_graycounter1_q <= 7'd0;
soc_rx_cdc_graycounter1_q_binary <= 7'd0;
soc_writer_errors_status <= 32'd0;
soc_writer_storage <= 1'd0;
soc_writer_re <= 1'd0;
soc_writer_counter <= 32'd0;
soc_writer_slot <= 1'd0;
soc_writer_fifo_level <= 2'd0;
soc_writer_fifo_produce <= 1'd0;
soc_writer_fifo_consume <= 1'd0;
soc_reader_slot_storage <= 1'd0;
soc_reader_slot_re <= 1'd0;
soc_reader_length_storage <= 11'd0;
soc_reader_length_re <= 1'd0;
soc_reader_done_pending <= 1'd0;
soc_reader_eventmanager_storage <= 1'd0;
soc_reader_eventmanager_re <= 1'd0;
soc_reader_fifo_level <= 2'd0;
soc_reader_fifo_produce <= 1'd0;
soc_reader_fifo_consume <= 1'd0;
soc_reader_counter <= 11'd0;
soc_reader_last_d <= 1'd0;
soc_sram0_bus_ack0 <= 1'd0;
soc_sram1_bus_ack0 <= 1'd0;
soc_sram0_bus_ack1 <= 1'd0;
soc_sram1_bus_ack1 <= 1'd0;
soc_slave_sel_r <= 4'd0;
vns_wb2csr_state <= 1'd0;
vns_refresher_state <= 2'd0;
vns_bankmachine0_state <= 3'd0;
vns_bankmachine1_state <= 3'd0;
vns_bankmachine2_state <= 3'd0;
vns_bankmachine3_state <= 3'd0;
vns_bankmachine4_state <= 3'd0;
vns_bankmachine5_state <= 3'd0;
vns_bankmachine6_state <= 3'd0;
vns_bankmachine7_state <= 3'd0;
vns_multiplexer_state <= 4'd0;
vns_rbank <= 3'd0;
vns_wbank <= 3'd0;
vns_new_master_wdata_ready0 <= 1'd0;
vns_new_master_wdata_ready1 <= 1'd0;
vns_new_master_wdata_ready2 <= 1'd0;
vns_new_master_rdata_valid0 <= 1'd0;
vns_new_master_rdata_valid1 <= 1'd0;
vns_new_master_rdata_valid2 <= 1'd0;
vns_new_master_rdata_valid3 <= 1'd0;
vns_new_master_rdata_valid4 <= 1'd0;
vns_new_master_rdata_valid5 <= 1'd0;
vns_new_master_rdata_valid6 <= 1'd0;
vns_new_master_rdata_valid7 <= 1'd0;
vns_new_master_rdata_valid8 <= 1'd0;
vns_new_master_rdata_valid9 <= 1'd0;
vns_fullmemorywe_state <= 3'd0;
vns_litedramwishbone2native_state <= 2'd0;
vns_liteethmacsramwriter_state <= 3'd0;
vns_liteethmacsramreader_state <= 2'd0;
vns_netsoc_grant <= 1'd0;
vns_netsoc_slave_sel_r <= 6'd0;
vns_netsoc_count <= 20'd1000000;
vns_netsoc_csrbankarray_interface0_bank_bus_dat_r <= 8'd0;
vns_netsoc_csrbankarray_interface1_bank_bus_dat_r <= 8'd0;
vns_netsoc_csrbankarray_interface2_bank_bus_dat_r <= 8'd0;
vns_netsoc_csrbankarray_interface3_bank_bus_dat_r <= 8'd0;
vns_netsoc_csrbankarray_interface4_bank_bus_dat_r <= 8'd0;
vns_netsoc_csrbankarray_sel_r <= 1'd0;
vns_netsoc_csrbankarray_interface5_bank_bus_dat_r <= 8'd0;
vns_netsoc_csrbankarray_interface6_bank_bus_dat_r <= 8'd0;
vns_netsoc_csrbankarray_interface7_bank_bus_dat_r <= 8'd0;
vns_netsoc_csrbankarray_interface8_bank_bus_dat_r <= 8'd0;
end
vns_xilinxmultiregimpl0_regs0 <= serial_rx;
vns_xilinxmultiregimpl0_regs1 <= vns_xilinxmultiregimpl0_regs0;
vns_xilinxmultiregimpl1_regs0 <= soc_data_r;
vns_xilinxmultiregimpl1_regs1 <= vns_xilinxmultiregimpl1_regs0;
vns_xilinxmultiregimpl2_regs0 <= soc_ps_preamble_error_toggle_i;
vns_xilinxmultiregimpl2_regs1 <= vns_xilinxmultiregimpl2_regs0;
vns_xilinxmultiregimpl3_regs0 <= soc_ps_crc_error_toggle_i;
vns_xilinxmultiregimpl3_regs1 <= vns_xilinxmultiregimpl3_regs0;
vns_xilinxmultiregimpl5_regs0 <= soc_tx_cdc_graycounter1_q;
vns_xilinxmultiregimpl5_regs1 <= vns_xilinxmultiregimpl5_regs0;
vns_xilinxmultiregimpl6_regs0 <= soc_rx_cdc_graycounter0_q;
vns_xilinxmultiregimpl6_regs1 <= vns_xilinxmultiregimpl6_regs0;
end
reg [31:0] mem[0:16383];
reg [31:0] memdat;
always @(posedge sys_clk) begin
memdat <= mem[soc_netsoc_rom_adr];
end
assign soc_netsoc_rom_dat_r = memdat;
initial begin
$readmemh("mem.init", mem);
end
reg [31:0] mem_1[0:8191];
reg [12:0] memadr;
always @(posedge sys_clk) begin
if (soc_netsoc_sram_we[0])
mem_1[soc_netsoc_sram_adr][7:0] <= soc_netsoc_sram_dat_w[7:0];
if (soc_netsoc_sram_we[1])
mem_1[soc_netsoc_sram_adr][15:8] <= soc_netsoc_sram_dat_w[15:8];
if (soc_netsoc_sram_we[2])
mem_1[soc_netsoc_sram_adr][23:16] <= soc_netsoc_sram_dat_w[23:16];
if (soc_netsoc_sram_we[3])
mem_1[soc_netsoc_sram_adr][31:24] <= soc_netsoc_sram_dat_w[31:24];
memadr <= soc_netsoc_sram_adr;
end
assign soc_netsoc_sram_dat_r = mem_1[memadr];
initial begin
$readmemh("mem_1.init", mem_1);
end
reg [9:0] storage[0:15];
reg [9:0] memdat_1;
reg [9:0] memdat_2;
always @(posedge sys_clk) begin
if (soc_netsoc_uart_tx_fifo_wrport_we)
storage[soc_netsoc_uart_tx_fifo_wrport_adr] <= soc_netsoc_uart_tx_fifo_wrport_dat_w;
memdat_1 <= storage[soc_netsoc_uart_tx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (soc_netsoc_uart_tx_fifo_rdport_re)
memdat_2 <= storage[soc_netsoc_uart_tx_fifo_rdport_adr];
end
assign soc_netsoc_uart_tx_fifo_wrport_dat_r = memdat_1;
assign soc_netsoc_uart_tx_fifo_rdport_dat_r = memdat_2;
reg [9:0] storage_1[0:15];
reg [9:0] memdat_3;
reg [9:0] memdat_4;
always @(posedge sys_clk) begin
if (soc_netsoc_uart_rx_fifo_wrport_we)
storage_1[soc_netsoc_uart_rx_fifo_wrport_adr] <= soc_netsoc_uart_rx_fifo_wrport_dat_w;
memdat_3 <= storage_1[soc_netsoc_uart_rx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (soc_netsoc_uart_rx_fifo_rdport_re)
memdat_4 <= storage_1[soc_netsoc_uart_rx_fifo_rdport_adr];
end
assign soc_netsoc_uart_rx_fifo_wrport_dat_r = memdat_3;
assign soc_netsoc_uart_rx_fifo_rdport_dat_r = memdat_4;
reg [7:0] mem_2[0:6];
reg [2:0] memadr_1;
always @(posedge sys_clk) begin
memadr_1 <= vns_netsoc_csrbankarray_adr;
end
assign vns_netsoc_csrbankarray_dat_r = mem_2[memadr_1];
initial begin
$readmemh("mem_2.init", mem_2);
end
PLLE2_ADV #(
.CLKFBOUT_MULT(4'd12),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(5'd20),
.CLKOUT0_PHASE(1'd0),
.CLKOUT1_DIVIDE(3'd5),
.CLKOUT1_PHASE(1'd0),
.CLKOUT2_DIVIDE(3'd5),
.CLKOUT2_PHASE(7'd90),
.CLKOUT3_DIVIDE(3'd6),
.CLKOUT3_PHASE(1'd0),
.CLKOUT4_DIVIDE(6'd48),
.CLKOUT5_PHASE(1'd0),
.DIVCLK_DIVIDE(1'd1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(soc_pll_fb),
.CLKIN1(soc_clk100bg),
.CLKFBOUT(soc_pll_fb),
.CLKOUT0(soc_pll_sys),
.CLKOUT1(soc_pll_sys4x),
.CLKOUT2(soc_pll_sys4x_dqs),
.CLKOUT3(soc_pll_clk200),
.CLKOUT4(soc_pll_clk100),
.LOCKED(soc_pll_locked)
);
wire clk100_ibuf;
IBUF clkbuf(.I(clk100), .O(clk100_ibuf));
BUFG BUFG(
.I(clk100_ibuf),
.O(soc_clk100bg)
);
BUFG BUFG_1(
.I(soc_pll_sys),
.O(sys_clk)
);
BUFG BUFG_2(
.I(soc_pll_sys4x),
.O(sys4x_clk)
);
BUFG BUFG_3(
.I(soc_pll_sys4x_dqs),
.O(sys4x_dqs_clk)
);
BUFG BUFG_4(
.I(soc_pll_clk200),
.O(clk200_clk)
);
BUFG BUFG_5(
.I(soc_pll_clk100),
.O(eth_ref_clk_obuf)
);
wire eth_ref_clk_obuf;
OBUF clk_eth_buf(.I(eth_ref_clk_obuf), .O(eth_ref_clk));
IDELAYCTRL IDELAYCTRL(
.REFCLK(clk200_clk),
.RST(soc_ic_reset),
.RDY(idelayctl_rdy)
);
reg [31:0] mem_3[0:4095];
reg [11:0] memadr_2;
always @(posedge sys_clk) begin
if (soc_emulator_ram_we[0])
mem_3[soc_emulator_ram_adr][7:0] <= soc_emulator_ram_dat_w[7:0];
if (soc_emulator_ram_we[1])
mem_3[soc_emulator_ram_adr][15:8] <= soc_emulator_ram_dat_w[15:8];
if (soc_emulator_ram_we[2])
mem_3[soc_emulator_ram_adr][23:16] <= soc_emulator_ram_dat_w[23:16];
if (soc_emulator_ram_we[3])
mem_3[soc_emulator_ram_adr][31:24] <= soc_emulator_ram_dat_w[31:24];
memadr_2 <= soc_emulator_ram_adr;
end
assign soc_emulator_ram_dat_r = mem_3[memadr_2];
wire tq;
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(1'd0),
.D2(1'd1),
.D3(1'd0),
.D4(1'd1),
.D5(1'd0),
.D6(1'd1),
.D7(1'd0),
.D8(1'd1),
.OCE(1'd1),
.RST(sys_rst),
.OQ(soc_a7ddrphy_sd_clk_se_nodelay),
.TQ(tq),
.TCE(1'd1),
.T1(1'b0)
);
OBUFTDS OBUFTDS_0(
.I(soc_a7ddrphy_sd_clk_se_nodelay),
.O(ddram_clk_p),
.OB(ddram_clk_n),
.T(tq)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_1 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[0]),
.D2(soc_a7ddrphy_dfi_p0_address[0]),
.D3(soc_a7ddrphy_dfi_p1_address[0]),
.D4(soc_a7ddrphy_dfi_p1_address[0]),
.D5(soc_a7ddrphy_dfi_p2_address[0]),
.D6(soc_a7ddrphy_dfi_p2_address[0]),
.D7(soc_a7ddrphy_dfi_p3_address[0]),
.D8(soc_a7ddrphy_dfi_p3_address[0]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[0])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_2 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[1]),
.D2(soc_a7ddrphy_dfi_p0_address[1]),
.D3(soc_a7ddrphy_dfi_p1_address[1]),
.D4(soc_a7ddrphy_dfi_p1_address[1]),
.D5(soc_a7ddrphy_dfi_p2_address[1]),
.D6(soc_a7ddrphy_dfi_p2_address[1]),
.D7(soc_a7ddrphy_dfi_p3_address[1]),
.D8(soc_a7ddrphy_dfi_p3_address[1]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[1])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_3 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[2]),
.D2(soc_a7ddrphy_dfi_p0_address[2]),
.D3(soc_a7ddrphy_dfi_p1_address[2]),
.D4(soc_a7ddrphy_dfi_p1_address[2]),
.D5(soc_a7ddrphy_dfi_p2_address[2]),
.D6(soc_a7ddrphy_dfi_p2_address[2]),
.D7(soc_a7ddrphy_dfi_p3_address[2]),
.D8(soc_a7ddrphy_dfi_p3_address[2]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[2])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_4 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[3]),
.D2(soc_a7ddrphy_dfi_p0_address[3]),
.D3(soc_a7ddrphy_dfi_p1_address[3]),
.D4(soc_a7ddrphy_dfi_p1_address[3]),
.D5(soc_a7ddrphy_dfi_p2_address[3]),
.D6(soc_a7ddrphy_dfi_p2_address[3]),
.D7(soc_a7ddrphy_dfi_p3_address[3]),
.D8(soc_a7ddrphy_dfi_p3_address[3]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[3])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_5 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[4]),
.D2(soc_a7ddrphy_dfi_p0_address[4]),
.D3(soc_a7ddrphy_dfi_p1_address[4]),
.D4(soc_a7ddrphy_dfi_p1_address[4]),
.D5(soc_a7ddrphy_dfi_p2_address[4]),
.D6(soc_a7ddrphy_dfi_p2_address[4]),
.D7(soc_a7ddrphy_dfi_p3_address[4]),
.D8(soc_a7ddrphy_dfi_p3_address[4]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[4])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_6 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[5]),
.D2(soc_a7ddrphy_dfi_p0_address[5]),
.D3(soc_a7ddrphy_dfi_p1_address[5]),
.D4(soc_a7ddrphy_dfi_p1_address[5]),
.D5(soc_a7ddrphy_dfi_p2_address[5]),
.D6(soc_a7ddrphy_dfi_p2_address[5]),
.D7(soc_a7ddrphy_dfi_p3_address[5]),
.D8(soc_a7ddrphy_dfi_p3_address[5]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[5])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_7 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[6]),
.D2(soc_a7ddrphy_dfi_p0_address[6]),
.D3(soc_a7ddrphy_dfi_p1_address[6]),
.D4(soc_a7ddrphy_dfi_p1_address[6]),
.D5(soc_a7ddrphy_dfi_p2_address[6]),
.D6(soc_a7ddrphy_dfi_p2_address[6]),
.D7(soc_a7ddrphy_dfi_p3_address[6]),
.D8(soc_a7ddrphy_dfi_p3_address[6]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[6])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_8 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[7]),
.D2(soc_a7ddrphy_dfi_p0_address[7]),
.D3(soc_a7ddrphy_dfi_p1_address[7]),
.D4(soc_a7ddrphy_dfi_p1_address[7]),
.D5(soc_a7ddrphy_dfi_p2_address[7]),
.D6(soc_a7ddrphy_dfi_p2_address[7]),
.D7(soc_a7ddrphy_dfi_p3_address[7]),
.D8(soc_a7ddrphy_dfi_p3_address[7]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[7])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_9 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[8]),
.D2(soc_a7ddrphy_dfi_p0_address[8]),
.D3(soc_a7ddrphy_dfi_p1_address[8]),
.D4(soc_a7ddrphy_dfi_p1_address[8]),
.D5(soc_a7ddrphy_dfi_p2_address[8]),
.D6(soc_a7ddrphy_dfi_p2_address[8]),
.D7(soc_a7ddrphy_dfi_p3_address[8]),
.D8(soc_a7ddrphy_dfi_p3_address[8]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[8])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_10 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[9]),
.D2(soc_a7ddrphy_dfi_p0_address[9]),
.D3(soc_a7ddrphy_dfi_p1_address[9]),
.D4(soc_a7ddrphy_dfi_p1_address[9]),
.D5(soc_a7ddrphy_dfi_p2_address[9]),
.D6(soc_a7ddrphy_dfi_p2_address[9]),
.D7(soc_a7ddrphy_dfi_p3_address[9]),
.D8(soc_a7ddrphy_dfi_p3_address[9]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[9])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_11 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[10]),
.D2(soc_a7ddrphy_dfi_p0_address[10]),
.D3(soc_a7ddrphy_dfi_p1_address[10]),
.D4(soc_a7ddrphy_dfi_p1_address[10]),
.D5(soc_a7ddrphy_dfi_p2_address[10]),
.D6(soc_a7ddrphy_dfi_p2_address[10]),
.D7(soc_a7ddrphy_dfi_p3_address[10]),
.D8(soc_a7ddrphy_dfi_p3_address[10]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[10])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_12 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[11]),
.D2(soc_a7ddrphy_dfi_p0_address[11]),
.D3(soc_a7ddrphy_dfi_p1_address[11]),
.D4(soc_a7ddrphy_dfi_p1_address[11]),
.D5(soc_a7ddrphy_dfi_p2_address[11]),
.D6(soc_a7ddrphy_dfi_p2_address[11]),
.D7(soc_a7ddrphy_dfi_p3_address[11]),
.D8(soc_a7ddrphy_dfi_p3_address[11]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[11])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_13 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[12]),
.D2(soc_a7ddrphy_dfi_p0_address[12]),
.D3(soc_a7ddrphy_dfi_p1_address[12]),
.D4(soc_a7ddrphy_dfi_p1_address[12]),
.D5(soc_a7ddrphy_dfi_p2_address[12]),
.D6(soc_a7ddrphy_dfi_p2_address[12]),
.D7(soc_a7ddrphy_dfi_p3_address[12]),
.D8(soc_a7ddrphy_dfi_p3_address[12]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[12])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_14 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_address[13]),
.D2(soc_a7ddrphy_dfi_p0_address[13]),
.D3(soc_a7ddrphy_dfi_p1_address[13]),
.D4(soc_a7ddrphy_dfi_p1_address[13]),
.D5(soc_a7ddrphy_dfi_p2_address[13]),
.D6(soc_a7ddrphy_dfi_p2_address[13]),
.D7(soc_a7ddrphy_dfi_p3_address[13]),
.D8(soc_a7ddrphy_dfi_p3_address[13]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a_iob[13])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_15 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_bank[0]),
.D2(soc_a7ddrphy_dfi_p0_bank[0]),
.D3(soc_a7ddrphy_dfi_p1_bank[0]),
.D4(soc_a7ddrphy_dfi_p1_bank[0]),
.D5(soc_a7ddrphy_dfi_p2_bank[0]),
.D6(soc_a7ddrphy_dfi_p2_bank[0]),
.D7(soc_a7ddrphy_dfi_p3_bank[0]),
.D8(soc_a7ddrphy_dfi_p3_bank[0]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ba_iob[0])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_16 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_bank[1]),
.D2(soc_a7ddrphy_dfi_p0_bank[1]),
.D3(soc_a7ddrphy_dfi_p1_bank[1]),
.D4(soc_a7ddrphy_dfi_p1_bank[1]),
.D5(soc_a7ddrphy_dfi_p2_bank[1]),
.D6(soc_a7ddrphy_dfi_p2_bank[1]),
.D7(soc_a7ddrphy_dfi_p3_bank[1]),
.D8(soc_a7ddrphy_dfi_p3_bank[1]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ba_iob[1])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_17 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_bank[2]),
.D2(soc_a7ddrphy_dfi_p0_bank[2]),
.D3(soc_a7ddrphy_dfi_p1_bank[2]),
.D4(soc_a7ddrphy_dfi_p1_bank[2]),
.D5(soc_a7ddrphy_dfi_p2_bank[2]),
.D6(soc_a7ddrphy_dfi_p2_bank[2]),
.D7(soc_a7ddrphy_dfi_p3_bank[2]),
.D8(soc_a7ddrphy_dfi_p3_bank[2]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ba_iob[2])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_18 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_ras_n),
.D2(soc_a7ddrphy_dfi_p0_ras_n),
.D3(soc_a7ddrphy_dfi_p1_ras_n),
.D4(soc_a7ddrphy_dfi_p1_ras_n),
.D5(soc_a7ddrphy_dfi_p2_ras_n),
.D6(soc_a7ddrphy_dfi_p2_ras_n),
.D7(soc_a7ddrphy_dfi_p3_ras_n),
.D8(soc_a7ddrphy_dfi_p3_ras_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ras_n_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_19 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_cas_n),
.D2(soc_a7ddrphy_dfi_p0_cas_n),
.D3(soc_a7ddrphy_dfi_p1_cas_n),
.D4(soc_a7ddrphy_dfi_p1_cas_n),
.D5(soc_a7ddrphy_dfi_p2_cas_n),
.D6(soc_a7ddrphy_dfi_p2_cas_n),
.D7(soc_a7ddrphy_dfi_p3_cas_n),
.D8(soc_a7ddrphy_dfi_p3_cas_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_cas_n_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_20 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_we_n),
.D2(soc_a7ddrphy_dfi_p0_we_n),
.D3(soc_a7ddrphy_dfi_p1_we_n),
.D4(soc_a7ddrphy_dfi_p1_we_n),
.D5(soc_a7ddrphy_dfi_p2_we_n),
.D6(soc_a7ddrphy_dfi_p2_we_n),
.D7(soc_a7ddrphy_dfi_p3_we_n),
.D8(soc_a7ddrphy_dfi_p3_we_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_we_n_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_21 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_cke),
.D2(soc_a7ddrphy_dfi_p0_cke),
.D3(soc_a7ddrphy_dfi_p1_cke),
.D4(soc_a7ddrphy_dfi_p1_cke),
.D5(soc_a7ddrphy_dfi_p2_cke),
.D6(soc_a7ddrphy_dfi_p2_cke),
.D7(soc_a7ddrphy_dfi_p3_cke),
.D8(soc_a7ddrphy_dfi_p3_cke),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_cke_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_22 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_odt),
.D2(soc_a7ddrphy_dfi_p0_odt),
.D3(soc_a7ddrphy_dfi_p1_odt),
.D4(soc_a7ddrphy_dfi_p1_odt),
.D5(soc_a7ddrphy_dfi_p2_odt),
.D6(soc_a7ddrphy_dfi_p2_odt),
.D7(soc_a7ddrphy_dfi_p3_odt),
.D8(soc_a7ddrphy_dfi_p3_odt),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_odt_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_23 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_reset_n),
.D2(soc_a7ddrphy_dfi_p0_reset_n),
.D3(soc_a7ddrphy_dfi_p1_reset_n),
.D4(soc_a7ddrphy_dfi_p1_reset_n),
.D5(soc_a7ddrphy_dfi_p2_reset_n),
.D6(soc_a7ddrphy_dfi_p2_reset_n),
.D7(soc_a7ddrphy_dfi_p3_reset_n),
.D8(soc_a7ddrphy_dfi_p3_reset_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_reset_n_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_24 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_cs_n),
.D2(soc_a7ddrphy_dfi_p0_cs_n),
.D3(soc_a7ddrphy_dfi_p1_cs_n),
.D4(soc_a7ddrphy_dfi_p1_cs_n),
.D5(soc_a7ddrphy_dfi_p2_cs_n),
.D6(soc_a7ddrphy_dfi_p2_cs_n),
.D7(soc_a7ddrphy_dfi_p3_cs_n),
.D8(soc_a7ddrphy_dfi_p3_cs_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_cs_n_iob)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_25 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]),
.D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]),
.D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]),
.D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]),
.D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]),
.D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]),
.D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]),
.D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_dm_iob[0])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_26 (
.CLK(sys4x_dqs_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dqs_serdes_pattern[0]),
.D2(soc_a7ddrphy_dqs_serdes_pattern[1]),
.D3(soc_a7ddrphy_dqs_serdes_pattern[2]),
.D4(soc_a7ddrphy_dqs_serdes_pattern[3]),
.D5(soc_a7ddrphy_dqs_serdes_pattern[4]),
.D6(soc_a7ddrphy_dqs_serdes_pattern[5]),
.D7(soc_a7ddrphy_dqs_serdes_pattern[6]),
.D8(soc_a7ddrphy_dqs_serdes_pattern[7]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dqs)),
.TCE(1'd1),
.OFB(soc_a7ddrphy0),
.OQ(soc_a7ddrphy_dqs_nodelay0),
.TQ(soc_a7ddrphy_dqs_t0)
);
OBUFTDS OBUFTDS(
.I(soc_a7ddrphy_dqs_nodelay0),
.T(soc_a7ddrphy_dqs_t0),
.O(ddram_dqs_p[0]),
.OB(ddram_dqs_n[0])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_27 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]),
.D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]),
.D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]),
.D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]),
.D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]),
.D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]),
.D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]),
.D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_dm_iob[1])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_28 (
.CLK(sys4x_dqs_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dqs_serdes_pattern[0]),
.D2(soc_a7ddrphy_dqs_serdes_pattern[1]),
.D3(soc_a7ddrphy_dqs_serdes_pattern[2]),
.D4(soc_a7ddrphy_dqs_serdes_pattern[3]),
.D5(soc_a7ddrphy_dqs_serdes_pattern[4]),
.D6(soc_a7ddrphy_dqs_serdes_pattern[5]),
.D7(soc_a7ddrphy_dqs_serdes_pattern[6]),
.D8(soc_a7ddrphy_dqs_serdes_pattern[7]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dqs)),
.TCE(1'd1),
.OFB(soc_a7ddrphy1),
.OQ(soc_a7ddrphy_dqs_nodelay1),
.TQ(soc_a7ddrphy_dqs_t1)
);
OBUFTDS OBUFTDS_1(
.I(soc_a7ddrphy_dqs_nodelay1),
.T(soc_a7ddrphy_dqs_t1),
.O(ddram_dqs_p[1]),
.OB(ddram_dqs_n[1])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_29 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[0]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[16]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[0]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[16]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[0]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[16]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[0]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[16]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay0),
.TQ(soc_a7ddrphy_dq_t0)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed0),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data0[7]),
.Q2(soc_a7ddrphy_dq_i_data0[6]),
.Q3(soc_a7ddrphy_dq_i_data0[5]),
.Q4(soc_a7ddrphy_dq_i_data0[4]),
.Q5(soc_a7ddrphy_dq_i_data0[3]),
.Q6(soc_a7ddrphy_dq_i_data0[2]),
.Q7(soc_a7ddrphy_dq_i_data0[1]),
.Q8(soc_a7ddrphy_dq_i_data0[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay0),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed0)
);
IOBUF IOBUF(
.I(soc_a7ddrphy_dq_o_nodelay0),
.T(soc_a7ddrphy_dq_t0),
.IO(ddram_dq[0]),
.O(soc_a7ddrphy_dq_i_nodelay0)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_30 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[1]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[17]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[1]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[17]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[1]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[17]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[1]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[17]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay1),
.TQ(soc_a7ddrphy_dq_t1)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_1 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed1),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data1[7]),
.Q2(soc_a7ddrphy_dq_i_data1[6]),
.Q3(soc_a7ddrphy_dq_i_data1[5]),
.Q4(soc_a7ddrphy_dq_i_data1[4]),
.Q5(soc_a7ddrphy_dq_i_data1[3]),
.Q6(soc_a7ddrphy_dq_i_data1[2]),
.Q7(soc_a7ddrphy_dq_i_data1[1]),
.Q8(soc_a7ddrphy_dq_i_data1[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_1 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay1),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed1)
);
IOBUF IOBUF_1(
.I(soc_a7ddrphy_dq_o_nodelay1),
.T(soc_a7ddrphy_dq_t1),
.IO(ddram_dq[1]),
.O(soc_a7ddrphy_dq_i_nodelay1)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_31 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[2]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[18]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[2]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[18]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[2]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[18]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[2]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[18]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay2),
.TQ(soc_a7ddrphy_dq_t2)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_2 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed2),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data2[7]),
.Q2(soc_a7ddrphy_dq_i_data2[6]),
.Q3(soc_a7ddrphy_dq_i_data2[5]),
.Q4(soc_a7ddrphy_dq_i_data2[4]),
.Q5(soc_a7ddrphy_dq_i_data2[3]),
.Q6(soc_a7ddrphy_dq_i_data2[2]),
.Q7(soc_a7ddrphy_dq_i_data2[1]),
.Q8(soc_a7ddrphy_dq_i_data2[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_2 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay2),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed2)
);
IOBUF IOBUF_2(
.I(soc_a7ddrphy_dq_o_nodelay2),
.T(soc_a7ddrphy_dq_t2),
.IO(ddram_dq[2]),
.O(soc_a7ddrphy_dq_i_nodelay2)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_32 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[3]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[19]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[3]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[19]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[3]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[19]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[3]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[19]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay3),
.TQ(soc_a7ddrphy_dq_t3)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_3 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed3),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data3[7]),
.Q2(soc_a7ddrphy_dq_i_data3[6]),
.Q3(soc_a7ddrphy_dq_i_data3[5]),
.Q4(soc_a7ddrphy_dq_i_data3[4]),
.Q5(soc_a7ddrphy_dq_i_data3[3]),
.Q6(soc_a7ddrphy_dq_i_data3[2]),
.Q7(soc_a7ddrphy_dq_i_data3[1]),
.Q8(soc_a7ddrphy_dq_i_data3[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_3 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay3),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed3)
);
IOBUF IOBUF_3(
.I(soc_a7ddrphy_dq_o_nodelay3),
.T(soc_a7ddrphy_dq_t3),
.IO(ddram_dq[3]),
.O(soc_a7ddrphy_dq_i_nodelay3)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_33 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[4]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[20]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[4]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[20]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[4]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[20]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[4]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[20]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay4),
.TQ(soc_a7ddrphy_dq_t4)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_4 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed4),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data4[7]),
.Q2(soc_a7ddrphy_dq_i_data4[6]),
.Q3(soc_a7ddrphy_dq_i_data4[5]),
.Q4(soc_a7ddrphy_dq_i_data4[4]),
.Q5(soc_a7ddrphy_dq_i_data4[3]),
.Q6(soc_a7ddrphy_dq_i_data4[2]),
.Q7(soc_a7ddrphy_dq_i_data4[1]),
.Q8(soc_a7ddrphy_dq_i_data4[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_4 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay4),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed4)
);
IOBUF IOBUF_4(
.I(soc_a7ddrphy_dq_o_nodelay4),
.T(soc_a7ddrphy_dq_t4),
.IO(ddram_dq[4]),
.O(soc_a7ddrphy_dq_i_nodelay4)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_34 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[5]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[21]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[5]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[21]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[5]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[21]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[5]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[21]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay5),
.TQ(soc_a7ddrphy_dq_t5)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_5 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed5),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data5[7]),
.Q2(soc_a7ddrphy_dq_i_data5[6]),
.Q3(soc_a7ddrphy_dq_i_data5[5]),
.Q4(soc_a7ddrphy_dq_i_data5[4]),
.Q5(soc_a7ddrphy_dq_i_data5[3]),
.Q6(soc_a7ddrphy_dq_i_data5[2]),
.Q7(soc_a7ddrphy_dq_i_data5[1]),
.Q8(soc_a7ddrphy_dq_i_data5[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_5 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay5),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed5)
);
IOBUF IOBUF_5(
.I(soc_a7ddrphy_dq_o_nodelay5),
.T(soc_a7ddrphy_dq_t5),
.IO(ddram_dq[5]),
.O(soc_a7ddrphy_dq_i_nodelay5)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_35 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[6]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[22]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[6]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[22]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[6]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[22]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[6]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[22]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay6),
.TQ(soc_a7ddrphy_dq_t6)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_6 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed6),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data6[7]),
.Q2(soc_a7ddrphy_dq_i_data6[6]),
.Q3(soc_a7ddrphy_dq_i_data6[5]),
.Q4(soc_a7ddrphy_dq_i_data6[4]),
.Q5(soc_a7ddrphy_dq_i_data6[3]),
.Q6(soc_a7ddrphy_dq_i_data6[2]),
.Q7(soc_a7ddrphy_dq_i_data6[1]),
.Q8(soc_a7ddrphy_dq_i_data6[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_6 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay6),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed6)
);
IOBUF IOBUF_6(
.I(soc_a7ddrphy_dq_o_nodelay6),
.T(soc_a7ddrphy_dq_t6),
.IO(ddram_dq[6]),
.O(soc_a7ddrphy_dq_i_nodelay6)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_36 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[7]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[23]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[7]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[23]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[7]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[23]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[7]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[23]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay7),
.TQ(soc_a7ddrphy_dq_t7)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_7 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed7),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data7[7]),
.Q2(soc_a7ddrphy_dq_i_data7[6]),
.Q3(soc_a7ddrphy_dq_i_data7[5]),
.Q4(soc_a7ddrphy_dq_i_data7[4]),
.Q5(soc_a7ddrphy_dq_i_data7[3]),
.Q6(soc_a7ddrphy_dq_i_data7[2]),
.Q7(soc_a7ddrphy_dq_i_data7[1]),
.Q8(soc_a7ddrphy_dq_i_data7[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_7 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay7),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed7)
);
IOBUF IOBUF_7(
.I(soc_a7ddrphy_dq_o_nodelay7),
.T(soc_a7ddrphy_dq_t7),
.IO(ddram_dq[7]),
.O(soc_a7ddrphy_dq_i_nodelay7)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_37 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[8]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[24]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[8]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[24]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[8]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[24]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[8]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[24]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay8),
.TQ(soc_a7ddrphy_dq_t8)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_8 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed8),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data8[7]),
.Q2(soc_a7ddrphy_dq_i_data8[6]),
.Q3(soc_a7ddrphy_dq_i_data8[5]),
.Q4(soc_a7ddrphy_dq_i_data8[4]),
.Q5(soc_a7ddrphy_dq_i_data8[3]),
.Q6(soc_a7ddrphy_dq_i_data8[2]),
.Q7(soc_a7ddrphy_dq_i_data8[1]),
.Q8(soc_a7ddrphy_dq_i_data8[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_8 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay8),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed8)
);
IOBUF IOBUF_8(
.I(soc_a7ddrphy_dq_o_nodelay8),
.T(soc_a7ddrphy_dq_t8),
.IO(ddram_dq[8]),
.O(soc_a7ddrphy_dq_i_nodelay8)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_38 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[9]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[25]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[9]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[25]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[9]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[25]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[9]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[25]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay9),
.TQ(soc_a7ddrphy_dq_t9)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_9 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed9),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data9[7]),
.Q2(soc_a7ddrphy_dq_i_data9[6]),
.Q3(soc_a7ddrphy_dq_i_data9[5]),
.Q4(soc_a7ddrphy_dq_i_data9[4]),
.Q5(soc_a7ddrphy_dq_i_data9[3]),
.Q6(soc_a7ddrphy_dq_i_data9[2]),
.Q7(soc_a7ddrphy_dq_i_data9[1]),
.Q8(soc_a7ddrphy_dq_i_data9[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_9 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay9),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed9)
);
IOBUF IOBUF_9(
.I(soc_a7ddrphy_dq_o_nodelay9),
.T(soc_a7ddrphy_dq_t9),
.IO(ddram_dq[9]),
.O(soc_a7ddrphy_dq_i_nodelay9)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_39 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[10]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[26]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[10]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[26]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[10]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[26]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[10]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[26]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay10),
.TQ(soc_a7ddrphy_dq_t10)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_10 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed10),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data10[7]),
.Q2(soc_a7ddrphy_dq_i_data10[6]),
.Q3(soc_a7ddrphy_dq_i_data10[5]),
.Q4(soc_a7ddrphy_dq_i_data10[4]),
.Q5(soc_a7ddrphy_dq_i_data10[3]),
.Q6(soc_a7ddrphy_dq_i_data10[2]),
.Q7(soc_a7ddrphy_dq_i_data10[1]),
.Q8(soc_a7ddrphy_dq_i_data10[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_10 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay10),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed10)
);
IOBUF IOBUF_10(
.I(soc_a7ddrphy_dq_o_nodelay10),
.T(soc_a7ddrphy_dq_t10),
.IO(ddram_dq[10]),
.O(soc_a7ddrphy_dq_i_nodelay10)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_40 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[11]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[27]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[11]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[27]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[11]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[27]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[11]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[27]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay11),
.TQ(soc_a7ddrphy_dq_t11)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_11 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed11),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data11[7]),
.Q2(soc_a7ddrphy_dq_i_data11[6]),
.Q3(soc_a7ddrphy_dq_i_data11[5]),
.Q4(soc_a7ddrphy_dq_i_data11[4]),
.Q5(soc_a7ddrphy_dq_i_data11[3]),
.Q6(soc_a7ddrphy_dq_i_data11[2]),
.Q7(soc_a7ddrphy_dq_i_data11[1]),
.Q8(soc_a7ddrphy_dq_i_data11[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_11 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay11),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed11)
);
IOBUF IOBUF_11(
.I(soc_a7ddrphy_dq_o_nodelay11),
.T(soc_a7ddrphy_dq_t11),
.IO(ddram_dq[11]),
.O(soc_a7ddrphy_dq_i_nodelay11)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_41 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[12]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[28]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[12]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[28]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[12]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[28]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[12]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[28]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay12),
.TQ(soc_a7ddrphy_dq_t12)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_12 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed12),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data12[7]),
.Q2(soc_a7ddrphy_dq_i_data12[6]),
.Q3(soc_a7ddrphy_dq_i_data12[5]),
.Q4(soc_a7ddrphy_dq_i_data12[4]),
.Q5(soc_a7ddrphy_dq_i_data12[3]),
.Q6(soc_a7ddrphy_dq_i_data12[2]),
.Q7(soc_a7ddrphy_dq_i_data12[1]),
.Q8(soc_a7ddrphy_dq_i_data12[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_12 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay12),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed12)
);
IOBUF IOBUF_12(
.I(soc_a7ddrphy_dq_o_nodelay12),
.T(soc_a7ddrphy_dq_t12),
.IO(ddram_dq[12]),
.O(soc_a7ddrphy_dq_i_nodelay12)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_42 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[13]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[29]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[13]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[29]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[13]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[29]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[13]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[29]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay13),
.TQ(soc_a7ddrphy_dq_t13)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_13 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed13),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data13[7]),
.Q2(soc_a7ddrphy_dq_i_data13[6]),
.Q3(soc_a7ddrphy_dq_i_data13[5]),
.Q4(soc_a7ddrphy_dq_i_data13[4]),
.Q5(soc_a7ddrphy_dq_i_data13[3]),
.Q6(soc_a7ddrphy_dq_i_data13[2]),
.Q7(soc_a7ddrphy_dq_i_data13[1]),
.Q8(soc_a7ddrphy_dq_i_data13[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_13 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay13),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed13)
);
IOBUF IOBUF_13(
.I(soc_a7ddrphy_dq_o_nodelay13),
.T(soc_a7ddrphy_dq_t13),
.IO(ddram_dq[13]),
.O(soc_a7ddrphy_dq_i_nodelay13)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_43 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[14]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[30]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[14]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[30]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[14]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[30]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[14]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[30]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay14),
.TQ(soc_a7ddrphy_dq_t14)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_14 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed14),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data14[7]),
.Q2(soc_a7ddrphy_dq_i_data14[6]),
.Q3(soc_a7ddrphy_dq_i_data14[5]),
.Q4(soc_a7ddrphy_dq_i_data14[4]),
.Q5(soc_a7ddrphy_dq_i_data14[3]),
.Q6(soc_a7ddrphy_dq_i_data14[2]),
.Q7(soc_a7ddrphy_dq_i_data14[1]),
.Q8(soc_a7ddrphy_dq_i_data14[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_14 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay14),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed14)
);
IOBUF IOBUF_14(
.I(soc_a7ddrphy_dq_o_nodelay14),
.T(soc_a7ddrphy_dq_t14),
.IO(ddram_dq[14]),
.O(soc_a7ddrphy_dq_i_nodelay14)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_44 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(soc_a7ddrphy_dfi_p0_wrdata[15]),
.D2(soc_a7ddrphy_dfi_p0_wrdata[31]),
.D3(soc_a7ddrphy_dfi_p1_wrdata[15]),
.D4(soc_a7ddrphy_dfi_p1_wrdata[31]),
.D5(soc_a7ddrphy_dfi_p2_wrdata[15]),
.D6(soc_a7ddrphy_dfi_p2_wrdata[31]),
.D7(soc_a7ddrphy_dfi_p3_wrdata[15]),
.D8(soc_a7ddrphy_dfi_p3_wrdata[31]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~soc_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(soc_a7ddrphy_dq_o_nodelay15),
.TQ(soc_a7ddrphy_dq_t15)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_15 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
`ifdef VIVADO
.CLKB((~sys4x_clk)),
`else
.CLKB(sys4x_clk),
`endif
.CLKDIV(sys_clk),
.DDLY(soc_a7ddrphy_dq_i_delayed15),
.RST(sys_rst),
.Q1(soc_a7ddrphy_dq_i_data15[7]),
.Q2(soc_a7ddrphy_dq_i_data15[6]),
.Q3(soc_a7ddrphy_dq_i_data15[5]),
.Q4(soc_a7ddrphy_dq_i_data15[4]),
.Q5(soc_a7ddrphy_dq_i_data15[3]),
.Q6(soc_a7ddrphy_dq_i_data15[2]),
.Q7(soc_a7ddrphy_dq_i_data15[1]),
.Q8(soc_a7ddrphy_dq_i_data15[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_15 (
.C(sys_clk),
.CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(soc_a7ddrphy_dq_i_nodelay15),
.INC(1'd1),
.LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(soc_a7ddrphy_dq_i_delayed15)
);
IOBUF IOBUF_15(
.I(soc_a7ddrphy_dq_o_nodelay15),
.T(soc_a7ddrphy_dq_t15),
.IO(ddram_dq[15]),
.O(soc_a7ddrphy_dq_i_nodelay15)
);
reg [23:0] storage_2[0:7];
reg [23:0] memdat_5;
always @(posedge sys_clk) begin
if (soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
storage_2[soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
memdat_5 <= storage_2[soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
assign soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_netsoc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_3[0:7];
reg [23:0] memdat_6;
always @(posedge sys_clk) begin
if (soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
storage_3[soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
memdat_6 <= storage_3[soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
assign soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_netsoc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_4[0:7];
reg [23:0] memdat_7;
always @(posedge sys_clk) begin
if (soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
storage_4[soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
memdat_7 <= storage_4[soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
assign soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_netsoc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_5[0:7];
reg [23:0] memdat_8;
always @(posedge sys_clk) begin
if (soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
storage_5[soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
memdat_8 <= storage_5[soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8;
assign soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_netsoc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_6[0:7];
reg [23:0] memdat_9;
always @(posedge sys_clk) begin
if (soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we)
storage_6[soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
memdat_9 <= storage_6[soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9;
assign soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_netsoc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_7[0:7];
reg [23:0] memdat_10;
always @(posedge sys_clk) begin
if (soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we)
storage_7[soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
memdat_10 <= storage_7[soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10;
assign soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_netsoc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_8[0:7];
reg [23:0] memdat_11;
always @(posedge sys_clk) begin
if (soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we)
storage_8[soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
memdat_11 <= storage_8[soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11;
assign soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[soc_netsoc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_9[0:7];
reg [23:0] memdat_12;
always @(posedge sys_clk) begin
if (soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we)
storage_9[soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
memdat_12 <= storage_9[soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12;
assign soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[soc_netsoc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr];
reg [23:0] tag_mem[0:511];
reg [8:0] memadr_3;
always @(posedge sys_clk) begin
if (soc_netsoc_tag_port_we)
tag_mem[soc_netsoc_tag_port_adr] <= soc_netsoc_tag_port_dat_w;
memadr_3 <= soc_netsoc_tag_port_adr;
end
assign soc_netsoc_tag_port_dat_r = tag_mem[memadr_3];
assign eth_mdio = soc_data_oe ? soc_data_w : 1'bz;
assign soc_data_r = eth_mdio;
reg [11:0] storage_10[0:4];
reg [11:0] memdat_13;
always @(posedge eth_rx_clk) begin
if (soc_crc32_checker_syncfifo_wrport_we)
storage_10[soc_crc32_checker_syncfifo_wrport_adr] <= soc_crc32_checker_syncfifo_wrport_dat_w;
memdat_13 <= storage_10[soc_crc32_checker_syncfifo_wrport_adr];
end
always @(posedge eth_rx_clk) begin
end
assign soc_crc32_checker_syncfifo_wrport_dat_r = memdat_13;
assign soc_crc32_checker_syncfifo_rdport_dat_r = storage_10[soc_crc32_checker_syncfifo_rdport_adr];
reg [41:0] storage_11[0:63];
reg [5:0] memadr_4;
reg [5:0] memadr_5;
always @(posedge sys_clk) begin
if (soc_tx_cdc_wrport_we)
storage_11[soc_tx_cdc_wrport_adr] <= soc_tx_cdc_wrport_dat_w;
memadr_4 <= soc_tx_cdc_wrport_adr;
end
always @(posedge eth_tx_clk) begin
memadr_5 <= soc_tx_cdc_rdport_adr;
end
assign soc_tx_cdc_wrport_dat_r = storage_11[memadr_4];
assign soc_tx_cdc_rdport_dat_r = storage_11[memadr_5];
reg [41:0] storage_12[0:63];
reg [5:0] memadr_6;
reg [5:0] memadr_7;
always @(posedge eth_rx_clk) begin
if (soc_rx_cdc_wrport_we)
storage_12[soc_rx_cdc_wrport_adr] <= soc_rx_cdc_wrport_dat_w;
memadr_6 <= soc_rx_cdc_wrport_adr;
end
always @(posedge sys_clk) begin
memadr_7 <= soc_rx_cdc_rdport_adr;
end
assign soc_rx_cdc_wrport_dat_r = storage_12[memadr_6];
assign soc_rx_cdc_rdport_dat_r = storage_12[memadr_7];
reg [34:0] storage_13[0:1];
reg [34:0] memdat_14;
always @(posedge sys_clk) begin
if (soc_writer_fifo_wrport_we)
storage_13[soc_writer_fifo_wrport_adr] <= soc_writer_fifo_wrport_dat_w;
memdat_14 <= storage_13[soc_writer_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_writer_fifo_wrport_dat_r = memdat_14;
assign soc_writer_fifo_rdport_dat_r = storage_13[soc_writer_fifo_rdport_adr];
reg [31:0] mem_4[0:381];
reg [8:0] memadr_8;
reg [31:0] memdat_15;
always @(posedge sys_clk) begin
if (soc_writer_memory0_we)
mem_4[soc_writer_memory0_adr] <= soc_writer_memory0_dat_w;
memadr_8 <= soc_writer_memory0_adr;
end
always @(posedge sys_clk) begin
memdat_15 <= mem_4[soc_sram0_adr0];
end
assign soc_writer_memory0_dat_r = mem_4[memadr_8];
assign soc_sram0_dat_r0 = memdat_15;
reg [31:0] mem_5[0:381];
reg [8:0] memadr_9;
reg [31:0] memdat_16;
always @(posedge sys_clk) begin
if (soc_writer_memory1_we)
mem_5[soc_writer_memory1_adr] <= soc_writer_memory1_dat_w;
memadr_9 <= soc_writer_memory1_adr;
end
always @(posedge sys_clk) begin
memdat_16 <= mem_5[soc_sram1_adr0];
end
assign soc_writer_memory1_dat_r = mem_5[memadr_9];
assign soc_sram1_dat_r0 = memdat_16;
reg [13:0] storage_14[0:1];
reg [13:0] memdat_17;
always @(posedge sys_clk) begin
if (soc_reader_fifo_wrport_we)
storage_14[soc_reader_fifo_wrport_adr] <= soc_reader_fifo_wrport_dat_w;
memdat_17 <= storage_14[soc_reader_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign soc_reader_fifo_wrport_dat_r = memdat_17;
assign soc_reader_fifo_rdport_dat_r = storage_14[soc_reader_fifo_rdport_adr];
reg [31:0] mem_6[0:381];
reg [8:0] memadr_10;
reg [8:0] memadr_11;
always @(posedge sys_clk) begin
memadr_10 <= soc_reader_memory0_adr;
end
always @(posedge sys_clk) begin
if (soc_sram0_we[0])
mem_6[soc_sram0_adr1][7:0] <= soc_sram0_dat_w[7:0];
if (soc_sram0_we[1])
mem_6[soc_sram0_adr1][15:8] <= soc_sram0_dat_w[15:8];
if (soc_sram0_we[2])
mem_6[soc_sram0_adr1][23:16] <= soc_sram0_dat_w[23:16];
if (soc_sram0_we[3])
mem_6[soc_sram0_adr1][31:24] <= soc_sram0_dat_w[31:24];
memadr_11 <= soc_sram0_adr1;
end
assign soc_reader_memory0_dat_r = mem_6[memadr_10];
assign soc_sram0_dat_r1 = mem_6[memadr_11];
reg [31:0] mem_7[0:381];
reg [8:0] memadr_12;
reg [8:0] memadr_13;
always @(posedge sys_clk) begin
memadr_12 <= soc_reader_memory1_adr;
end
always @(posedge sys_clk) begin
if (soc_sram1_we[0])
mem_7[soc_sram1_adr1][7:0] <= soc_sram1_dat_w[7:0];
if (soc_sram1_we[1])
mem_7[soc_sram1_adr1][15:8] <= soc_sram1_dat_w[15:8];
if (soc_sram1_we[2])
mem_7[soc_sram1_adr1][23:16] <= soc_sram1_dat_w[23:16];
if (soc_sram1_we[3])
mem_7[soc_sram1_adr1][31:24] <= soc_sram1_dat_w[31:24];
memadr_13 <= soc_sram1_adr1;
end
assign soc_reader_memory1_dat_r = mem_7[memadr_12];
assign soc_sram1_dat_r1 = mem_7[memadr_13];
VexRiscv VexRiscv(
.clk(sys_clk),
.dBusWishbone_ACK(soc_netsoc_cpu_dbus_ack),
.dBusWishbone_DAT_MISO(soc_netsoc_cpu_dbus_dat_r),
.dBusWishbone_ERR(soc_netsoc_cpu_dbus_err),
.externalInterruptArray(soc_netsoc_cpu_interrupt0),
.externalResetVector(1'd0),
.iBusWishbone_ACK(soc_netsoc_cpu_ibus_ack),
.iBusWishbone_DAT_MISO(soc_netsoc_cpu_ibus_dat_r),
.iBusWishbone_ERR(soc_netsoc_cpu_ibus_err),
.reset((sys_rst | soc_netsoc_cpu_reset)),
.softwareInterrupt(1'd0),
.timerInterrupt(soc_netsoc_cpu_interrupt1),
.dBusWishbone_ADR(soc_netsoc_cpu_dbus_adr),
.dBusWishbone_BTE(soc_netsoc_cpu_dbus_bte),
.dBusWishbone_CTI(soc_netsoc_cpu_dbus_cti),
.dBusWishbone_CYC(soc_netsoc_cpu_dbus_cyc),
.dBusWishbone_DAT_MOSI(soc_netsoc_cpu_dbus_dat_w),
.dBusWishbone_SEL(soc_netsoc_cpu_dbus_sel),
.dBusWishbone_STB(soc_netsoc_cpu_dbus_stb),
.dBusWishbone_WE(soc_netsoc_cpu_dbus_we),
.iBusWishbone_ADR(soc_netsoc_cpu_ibus_adr),
.iBusWishbone_BTE(soc_netsoc_cpu_ibus_bte),
.iBusWishbone_CTI(soc_netsoc_cpu_ibus_cti),
.iBusWishbone_CYC(soc_netsoc_cpu_ibus_cyc),
.iBusWishbone_DAT_MOSI(soc_netsoc_cpu_ibus_dat_w),
.iBusWishbone_SEL(soc_netsoc_cpu_ibus_sel),
.iBusWishbone_STB(soc_netsoc_cpu_ibus_stb),
.iBusWishbone_WE(soc_netsoc_cpu_ibus_we)
);
reg [7:0] data_mem_grain0[0:511];
reg [8:0] memadr_14;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[0])
data_mem_grain0[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[7:0];
memadr_14 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[7:0] = data_mem_grain0[memadr_14];
reg [7:0] data_mem_grain1[0:511];
reg [8:0] memadr_15;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[1])
data_mem_grain1[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[15:8];
memadr_15 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[15:8] = data_mem_grain1[memadr_15];
reg [7:0] data_mem_grain2[0:511];
reg [8:0] memadr_16;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[2])
data_mem_grain2[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[23:16];
memadr_16 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[23:16] = data_mem_grain2[memadr_16];
reg [7:0] data_mem_grain3[0:511];
reg [8:0] memadr_17;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[3])
data_mem_grain3[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[31:24];
memadr_17 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[31:24] = data_mem_grain3[memadr_17];
reg [7:0] data_mem_grain4[0:511];
reg [8:0] memadr_18;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[4])
data_mem_grain4[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[39:32];
memadr_18 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[39:32] = data_mem_grain4[memadr_18];
reg [7:0] data_mem_grain5[0:511];
reg [8:0] memadr_19;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[5])
data_mem_grain5[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[47:40];
memadr_19 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[47:40] = data_mem_grain5[memadr_19];
reg [7:0] data_mem_grain6[0:511];
reg [8:0] memadr_20;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[6])
data_mem_grain6[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[55:48];
memadr_20 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[55:48] = data_mem_grain6[memadr_20];
reg [7:0] data_mem_grain7[0:511];
reg [8:0] memadr_21;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[7])
data_mem_grain7[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[63:56];
memadr_21 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[63:56] = data_mem_grain7[memadr_21];
reg [7:0] data_mem_grain8[0:511];
reg [8:0] memadr_22;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[8])
data_mem_grain8[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[71:64];
memadr_22 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[71:64] = data_mem_grain8[memadr_22];
reg [7:0] data_mem_grain9[0:511];
reg [8:0] memadr_23;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[9])
data_mem_grain9[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[79:72];
memadr_23 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[79:72] = data_mem_grain9[memadr_23];
reg [7:0] data_mem_grain10[0:511];
reg [8:0] memadr_24;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[10])
data_mem_grain10[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[87:80];
memadr_24 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[87:80] = data_mem_grain10[memadr_24];
reg [7:0] data_mem_grain11[0:511];
reg [8:0] memadr_25;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[11])
data_mem_grain11[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[95:88];
memadr_25 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[95:88] = data_mem_grain11[memadr_25];
reg [7:0] data_mem_grain12[0:511];
reg [8:0] memadr_26;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[12])
data_mem_grain12[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[103:96];
memadr_26 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[103:96] = data_mem_grain12[memadr_26];
reg [7:0] data_mem_grain13[0:511];
reg [8:0] memadr_27;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[13])
data_mem_grain13[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[111:104];
memadr_27 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[111:104] = data_mem_grain13[memadr_27];
reg [7:0] data_mem_grain14[0:511];
reg [8:0] memadr_28;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[14])
data_mem_grain14[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[119:112];
memadr_28 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[119:112] = data_mem_grain14[memadr_28];
reg [7:0] data_mem_grain15[0:511];
reg [8:0] memadr_29;
always @(posedge sys_clk) begin
if (soc_netsoc_data_port_we[15])
data_mem_grain15[soc_netsoc_data_port_adr] <= soc_netsoc_data_port_dat_w[127:120];
memadr_29 <= soc_netsoc_data_port_adr;
end
assign soc_netsoc_data_port_dat_r[127:120] = data_mem_grain15[memadr_29];
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE (
.C(sys_clk),
.CE(1'd1),
.D(1'd0),
.PRE(vns_xilinxasyncresetsynchronizerimpl0),
.Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_1 (
.C(sys_clk),
.CE(1'd1),
.D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta),
.PRE(vns_xilinxasyncresetsynchronizerimpl0),
.Q(sys_rst)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_2 (
.C(clk200_clk),
.CE(1'd1),
.D(1'd0),
.PRE(vns_xilinxasyncresetsynchronizerimpl1),
.Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_3 (
.C(clk200_clk),
.CE(1'd1),
.D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta),
.PRE(vns_xilinxasyncresetsynchronizerimpl1),
.Q(clk200_rst)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_4 (
.C(eth_tx_clk),
.CE(1'd1),
.D(1'd0),
.PRE(soc_reset0),
.Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_5 (
.C(eth_tx_clk),
.CE(1'd1),
.D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta),
.PRE(soc_reset0),
.Q(eth_tx_rst)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_6 (
.C(eth_rx_clk),
.CE(1'd1),
.D(1'd0),
.PRE(soc_reset0),
.Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_7 (
.C(eth_rx_clk),
.CE(1'd1),
.D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta),
.PRE(soc_reset0),
.Q(eth_rx_rst)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__EDFXTP_PP_BLACKBOX_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXTP_PP_BLACKBOX_V
|
`timescale 1ns/1ps
module tb_cocotb #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter AXIS_WIDTH = 24,
parameter AXIS_STROBE_WIDTH = (AXIS_WIDTH / 8),
parameter BUFFER_SIZE = 2,
parameter VIDEO_IN_WIDTH = 1280,
parameter VIDEO_IN_HEIGHT = 720,
parameter VIDEO_IN_SIZE = VIDEO_IN_WIDTH * VIDEO_IN_HEIGHT,
parameter VIDEO_OUT_WIDTH = 1280,
parameter VIDEO_OUT_HEIGHT = 720,
parameter VIDEO_OUT_SIZE = VIDEO_OUT_WIDTH * VIDEO_OUT_HEIGHT,
parameter VIDEO_START_X = 0,
parameter VIDEO_START_Y = 0
)(
input clk,
input rst,
//Write Address Channel
input AXIML_AWVALID,
input [ADDR_WIDTH - 1: 0] AXIML_AWADDR,
output AXIML_AWREADY,
//Write Data Channel
input AXIML_WVALID,
output AXIML_WREADY,
input [STROBE_WIDTH - 1:0] AXIML_WSTRB,
input [DATA_WIDTH - 1: 0] AXIML_WDATA,
//Write Response Channel
output AXIML_BVALID,
input AXIML_BREADY,
output [1:0] AXIML_BRESP,
//Read Address Channel
input AXIML_ARVALID,
output AXIML_ARREADY,
input [ADDR_WIDTH - 1: 0] AXIML_ARADDR,
//Read Data Channel
output AXIML_RVALID,
input AXIML_RREADY,
output [1:0] AXIML_RRESP,
output [DATA_WIDTH - 1: 0] AXIML_RDATA,
//AXI Stream Incomming Channel
input [AXIS_WIDTH - 1:0] AXIMS_TDATA,
output AXIMS_TREADY,
input AXIMS_TVALID,
input AXIMS_TLAST,
input [AXIS_STROBE_WIDTH - 1: 0] AXIMS_TKEEP,
input [AXIS_STROBE_WIDTH - 1: 0] AXIMS_TSTRB,
input [3:0] AXIMS_TID,
input [31:0] AXIMS_TDEST,
input [3:0] AXIMS_TUSER,
//AXI Stream Output Channel
output [AXIS_WIDTH - 1:0] AXISS_TDATA,
input AXISS_TREADY,
output AXISS_TVALID,
output AXISS_TLAST,
output [AXIS_STROBE_WIDTH - 1: 0] AXISS_TKEEP,
output [AXIS_STROBE_WIDTH - 1: 0] AXISS_TSTRB,
output [3:0] AXISS_TID,
output [31:0] AXISS_TDEST,
output [3:0] AXISS_TUSER
);
//Local Parameters
//Registers
reg r_rst;
always @ (*) r_rst = rst;
reg [3:0] test_id = 0;
//submodules
axi_video_resizer #(
.INVERT_AXI_RESET (0 ),
.INVERT_AXIS_RESET (0 ),
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH ),
.AXIS_WIDTH (AXIS_WIDTH ),
.BUFFER_SIZE (BUFFER_SIZE ),
.VIDEO_IN_WIDTH (1280 ),
.VIDEO_IN_HEIGHT (720 ),
.VIDEO_IN_SIZE (VIDEO_IN_WIDTH * VIDEO_IN_HEIGHT ),
.VIDEO_OUT_WIDTH (1280 ),
.VIDEO_OUT_HEIGHT (720 ),
.VIDEO_OUT_SIZE (VIDEO_OUT_WIDTH * VIDEO_OUT_HEIGHT ),
.VIDEO_START_X (0 ),
.VIDEO_START_Y (0 )
) dut (
.clk (clk ),
.rst (r_rst ),
//AXI Lite Interface
.i_awvalid (AXIML_AWVALID ),
.i_awaddr (AXIML_AWADDR ),
.o_awready (AXIML_AWREADY ),
.i_wvalid (AXIML_WVALID ),
.o_wready (AXIML_WREADY ),
.i_wstrb (AXIML_WSTRB ),
.i_wdata (AXIML_WDATA ),
.o_bvalid (AXIML_BVALID ),
.i_bready (AXIML_BREADY ),
.o_bresp (AXIML_BRESP ),
.i_arvalid (AXIML_ARVALID ),
.o_arready (AXIML_ARREADY ),
.i_araddr (AXIML_ARADDR ),
.o_rvalid (AXIML_RVALID ),
.i_rready (AXIML_RREADY ),
.o_rresp (AXIML_RRESP ),
.o_rdata (AXIML_RDATA ),
.i_axis_clk (clk ),
.i_axis_rst (r_rst ),
//AXI Stream
.o_axis_video_in_ready (AXIMS_TREADY ),
.i_axis_video_in_data (AXIMS_TDATA ),
.i_axis_video_in_last (AXIMS_TLAST ),
.i_axis_video_in_valid (AXIMS_TVALID ),
//Physical Signals
.i_axis_video_out_ready (AXISS_TREADY ),
.o_axis_video_out_data (AXISS_TDATA ),
.o_axis_video_out_last (AXISS_TLAST ),
.o_axis_video_out_valid (AXISS_TVALID )
);
//asynchronus logic
//synchronous logic
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Tue Jul 4 08:52:39 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.2 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_a.v,v $
// Revision 1.2 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_a
//
// No user `defines in this module
module ent_a
//
// Generated Module inst_a
//
(
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a, // Input Port
port_o_a, // Output Port
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_i_a2, // Input Port
sig_o_a2 // Output Port
);
// Generated Module Inputs:
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output sig_o_a2;
// Generated Wires:
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
`ifdef exclude_inst_aa
// assign sig_04 = open;
assign sig_01 = some_val;
assign sig_02 = some_val;
assign sig_03 = some_val;
assign sig_05 = some_val;
assign sig_06 = some_val;
assign sig_07 = some_val;
assign sig_08 = 7'b1111111;
assign sig_13 = 5'b00000;
assign sig_14 = 7'b0000000;
`else
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_aa
`endif
`ifdef exclude_inst_ab
// assign sig_01 = open;
// assign sig_13 = open;
// assign sig_14 = open;
assign sig_02 = some_val;
`else
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_ab
`endif
`ifdef exclude_inst_ac
assign sig_02 = 1'b0;
`else
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
`endif
`ifdef exclude_inst_ad
assign sig_02 = 1'b0;
`else
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
`endif
`ifdef exclude_inst_ae
// assign sig_02 = open;
// assign sig_05 = open;
// assign sig_06 = open;
// assign sig_07 = open;
// assign sig_08 = open;
// assign sig_i_ae = open;
assign sig_o_ae = 8'b00000000;
`else
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
`endif
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DFXBP_FUNCTIONAL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ls__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXBP_FUNCTIONAL_V |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//
// Filename: tx_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TX Engine takes unformatted request and completions,
// formats these packets into "TLP's" or Transaction Layer Packets and abitrates
// their sending over the PCIe bus. These packets must meet max-request,
// max-payload, and payload termination requirements (see Read Completion
// Boundary). The TX Engine does not check these requirements during operation,
// but may do so during simulation.
//
// Valid packets are transmitted over the shared PCIe bus as determined
// by the arbiter.
//
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "tlp.vh"
module tx_engine_classic
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_PAYLOAD_DWORDS = 256,
parameter C_VENDOR = "ALTERA")
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_TXC_RST,
output DONE_TXR_RST,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TX Classic
input TX_TLP_READY,
output [C_PCI_DATA_WIDTH-1:0] TX_TLP,
output TX_TLP_VALID,
output TX_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET,
output TX_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
output TXC_SENT,
// Interface: TXR Engine
input TXR_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
input TXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
input TXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
output TXR_DATA_READY,
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY,
output TXR_SENT);
`include "functions.vh"
localparam C_MUX_TYPE = "SHIFT";
localparam C_DEPTH_PACKETS = 10;
localparam C_RST_COUNT = 10;
/*AUTOWIRE*/
/*AUTOINPUT*/
wire [C_PCI_DATA_WIDTH-1:0] _TXC_DATA;
wire [C_PCI_DATA_WIDTH-1:0] _TXR_DATA;
wire [C_PCI_DATA_WIDTH-1:0] wTxcTlp;
wire wTxcTlpEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcTlpEndOffset;
wire wTxcTlpReady;
wire wTxcTlpStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcTlpStartOffset;
wire wTxcTlpValid;
wire [C_PCI_DATA_WIDTH-1:0] wTxrTlp;
wire wTxrTlpEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrTlpEndOffset;
wire wTxrTlpReady;
wire wTxrTlpStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrTlpStartOffset;
wire wTxrTlpValid;
wire [C_PCI_DATA_WIDTH-1:0] wTxTlp;
wire wTxTlpEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxTlpEndOffset;
wire wTxTlpReady;
wire wTxTlpStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxTlpStartOffset;
wire wTxTlpValid;
wire wDoneTxcEngRst;
wire wDoneTxrEngRst;
wire wDoneRst;
wire wRstWaiting;
wire wRstRc;
wire wRstEng;
wire [C_RST_COUNT:0] wShiftRst;
reg rTxValid;
reg [`TLP_TYPE_W-1:0] rTxType;
reg rTxEndFlag;
reg rTxrSent;
reg rTxcSent;
assign DONE_TXC_RST = wDoneRst & wDoneTxcEngRst;
assign DONE_TXR_RST = wDoneRst & wDoneTxrEngRst;
assign TXC_SENT = rTxcSent;
assign TXR_SENT = rTxrSent;
assign wRstEng = wShiftRst[C_RST_COUNT-3];
assign wDoneEngRst = ~wShiftRst[C_RST_COUNT];
always @(posedge CLK) begin
if(TX_TLP_START_FLAG) begin
rTxType <= TX_TLP[`TLP_TYPE_R];
end
rTxEndFlag <= TX_TLP_END_FLAG;
rTxValid <= TX_TLP_VALID & TX_TLP_READY;
rTxcSent <= rTxEndFlag & rTxValid & (rTxType == `TLP_TYPE_CPL);
rTxrSent <= rTxEndFlag & rTxValid & (rTxType == `TLP_TYPE_REQ);
end
generate
if(C_VENDOR == "XILINX") begin : xilinx_data
if(C_PCI_DATA_WIDTH == 128) begin : x_be_swap128
assign _TXC_DATA = {TXC_DATA[103:96], TXC_DATA[111:104], TXC_DATA[119:112], TXC_DATA[127:120],
TXC_DATA[71:64], TXC_DATA[79:72], TXC_DATA[87:80], TXC_DATA[95:88],
TXC_DATA[39:32], TXC_DATA[47:40], TXC_DATA[55:48], TXC_DATA[63:56],
TXC_DATA[07:00], TXC_DATA[15:08], TXC_DATA[23:16], TXC_DATA[31:24]};
assign _TXR_DATA = {TXR_DATA[103:96], TXR_DATA[111:104], TXR_DATA[119:112], TXR_DATA[127:120],
TXR_DATA[71:64], TXR_DATA[79:72], TXR_DATA[87:80], TXR_DATA[95:88],
TXR_DATA[39:32], TXR_DATA[47:40], TXR_DATA[55:48], TXR_DATA[63:56],
TXR_DATA[07:00], TXR_DATA[15:08], TXR_DATA[23:16], TXR_DATA[31:24]};
end else if(C_PCI_DATA_WIDTH == 64) begin: x_be_swap64
assign _TXC_DATA = {TXC_DATA[39:32], TXC_DATA[47:40], TXC_DATA[55:48], TXC_DATA[63:56],
TXC_DATA[07:00], TXC_DATA[15:08], TXC_DATA[23:16], TXC_DATA[31:24]};
assign _TXR_DATA = {TXR_DATA[39:32], TXR_DATA[47:40], TXR_DATA[55:48], TXR_DATA[63:56],
TXR_DATA[07:00], TXR_DATA[15:08], TXR_DATA[23:16], TXR_DATA[31:24]};
end else if(C_PCI_DATA_WIDTH == 32) begin: x_be_swap32
assign _TXC_DATA = {TXC_DATA[07:00], TXC_DATA[15:08], TXC_DATA[23:16], TXC_DATA[31:24]};
assign _TXR_DATA = {TXR_DATA[07:00], TXR_DATA[15:08], TXR_DATA[23:16], TXR_DATA[31:24]};
end
end else begin : altera_data
assign _TXC_DATA = TXC_DATA;
assign _TXR_DATA = TXR_DATA;
end
endgenerate
txc_engine_classic
#(.C_PIPELINE_OUTPUT (0),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_VENDOR (C_VENDOR))
txc_engine_inst
(// Outputs
.TXC_TLP (wTxcTlp[C_PCI_DATA_WIDTH-1:0] ),
.TXC_TLP_VALID (wTxcTlpValid),
.TXC_TLP_START_FLAG (wTxcTlpStartFlag),
.TXC_TLP_START_OFFSET (wTxcTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_TLP_END_FLAG (wTxcTlpEndFlag),
.TXC_TLP_END_OFFSET (wTxcTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DONE_TXC_RST (wDoneTxcEngRst),
// Inputs
.TXC_TLP_READY (wTxcTlpReady),
.TXC_DATA (_TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.RST_IN (wRstEng),
/*AUTOINST*/
// Outputs
.TXC_DATA_READY (TXC_DATA_READY),
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (TXC_DATA_VALID),
.TXC_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
txr_engine_classic
#(.C_PIPELINE_OUTPUT (0),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_VENDOR (C_VENDOR))
txr_engine_inst
(// Outputs
.TXR_TLP (wTxrTlp[C_PCI_DATA_WIDTH-1:0]),
.TXR_TLP_VALID (wTxrTlpValid),
.TXR_TLP_START_FLAG (wTxrTlpStartFlag),
.TXR_TLP_START_OFFSET (wTxrTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_TLP_END_FLAG (wTxrTlpEndFlag),
.TXR_TLP_END_OFFSET (wTxrTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA (_TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.DONE_TXR_RST (wDoneTxrEngRst),
// Inputs
.TXR_TLP_READY (wTxrTlpReady),
.RST_IN (wRstEng),
/*AUTOINST*/
// Outputs
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY),
// Inputs
.CLK (CLK),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP));
tx_mux
#(.C_PIPELINE_INPUT (0),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_MUX_TYPE (C_MUX_TYPE),
.C_VENDOR (C_VENDOR))
tx_mux_inst
(// Inputs
.TXC_TLP (wTxcTlp[C_PCI_DATA_WIDTH-1:0]),
.TXC_TLP_VALID (wTxcTlpValid),
.TXC_TLP_START_FLAG (wTxcTlpStartFlag),
.TXC_TLP_START_OFFSET (wTxcTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_TLP_END_FLAG (wTxcTlpEndFlag),
.TXC_TLP_END_OFFSET (wTxcTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_TLP (wTxrTlp[C_PCI_DATA_WIDTH-1:0]),
.TXR_TLP_VALID (wTxrTlpValid),
.TXR_TLP_START_FLAG (wTxrTlpStartFlag),
.TXR_TLP_START_OFFSET (wTxrTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_TLP_END_FLAG (wTxrTlpEndFlag),
.TXR_TLP_END_OFFSET (wTxrTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RST_IN (wRstEng),
// Outputs
.TXC_TLP_READY (wTxcTlpReady),
.TXR_TLP_READY (wTxrTlpReady),
.TX_TLP (wTxTlp[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (wTxTlpValid),
.TX_TLP_START_FLAG (wTxTlpStartFlag),
.TX_TLP_START_OFFSET (wTxTlpStartOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TX_TLP_END_FLAG (wTxTlpEndFlag),
.TX_TLP_END_OFFSET (wTxTlpEndOffset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TX_TLP_READY (wTxTlpReady),
/*AUTOINST*/
// Inputs
.CLK (CLK));
shiftreg
#(// Parameters
.C_DEPTH (C_RST_COUNT),
.C_WIDTH (1),
.C_VALUE (1)
/*AUTOINSTPARAM*/)
rst_shiftreg
(// Outputs
.RD_DATA (wShiftRst),
// Inputs
.RST_IN (RST_BUS),
.WR_DATA (wRstRc),
/*AUTOINST*/
// Inputs
.CLK (CLK));
reset_controller
#(// Parameters
.C_RST_COUNT (C_RST_COUNT)
/*AUTOINSTPARAM*/)
rc_inst
(// Outputs
.DONE_RST (wDoneRst),
.WAITING_RESET (wRstWaiting),
.RST_OUT (wRstRc),
// Inputs
.RST_IN (RST_BUS),
.SIGNAL_RST (RST_LOGIC),
.WAIT_RST (TX_TLP_VALID),
.NEXT_CYC_RST (TX_TLP_END_FLAG & TX_TLP_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(// Parameters
.C_DEPTH (1),
.C_WIDTH (C_PCI_DATA_WIDTH +
2*(1 + clog2s(C_PCI_DATA_WIDTH/32))),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_reg_inst
(// Outputs
.WR_DATA_READY (wTxTlpReady),
.RD_DATA ({TX_TLP,
TX_TLP_START_FLAG, TX_TLP_START_OFFSET,
TX_TLP_END_FLAG, TX_TLP_END_OFFSET}),
.RD_DATA_VALID (TX_TLP_VALID),
// Inputs
.RST_IN (wRstRc),
.WR_DATA ({wTxTlp,
wTxTlpStartFlag, wTxTlpStartOffset,
wTxTlpEndFlag, wTxTlpEndOffset}),
.WR_DATA_VALID (wTxTlpValid & ~wRstWaiting),
.RD_DATA_READY (TX_TLP_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Put output pipeline stage here, OR, at TX Engine outputs
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/")
// End:
/*
Filename: tx_mux.v
Version: 1.0
Verilog Standard: Verilog-2001
Description: The tx_mux arbitrates access to the PCI TX interface
between the the Request and Completion engines. The top level tx_mux
module instantiates two sub-modules (also declared in this file):
tx_arbiter and tx_phi. The arbiter choses the next packet that will
be granted the TX interface, based on the priorities given to
it. Each priority is the count of how many successive, back-to-back
packets can be sent by either the TXC or TXR interface before
granting time to the other engine. The mux is a simple multiplexer
that uses the select signals from the arbiter.
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
- The pipeline stage at the start of the mux means that ready stays high for
both TXC and TXR. This the behavior we want?
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
`timescale 1ns/1ns
`include "trellis.vh"
module tx_mux
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MUX_TYPE = "SHIFT",
parameter C_VENDOR = "ALTERA")
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: TXC
input [C_PCI_DATA_WIDTH-1:0] TXC_TLP,
output TXC_TLP_READY,
input TXC_TLP_VALID,
input TXC_TLP_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_START_OFFSET,
input TXC_TLP_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_END_OFFSET,
// Interface: TXR
input [C_PCI_DATA_WIDTH-1:0] TXR_TLP,
input TXR_TLP_VALID,
input TXR_TLP_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_START_OFFSET,
input TXR_TLP_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_END_OFFSET,
output TXR_TLP_READY,
// Interface: TX Classic
input TX_TLP_READY,
output [C_PCI_DATA_WIDTH-1:0] TX_TLP,
output TX_TLP_VALID,
output TX_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET,
output TX_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET);
`include "functions.vh"
localparam C_WIDTH = (C_PCI_DATA_WIDTH + 2 * (clog2s(C_PCI_DATA_WIDTH/32) + 1));
localparam C_TXC_PRIORITY = 1;
localparam C_TXR_PRIORITY = 2;
/*AUTOWIRE*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
// Input Pipeline Stage to Mux
wire [C_PCI_DATA_WIDTH-1:0] wTxcTlp;
wire wTxcTlpReady;
wire wTxcTlpValid;
wire wTxcTlpStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcTlpStartOffset;
wire wTxcTlpEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcTlpEndOffset;
wire [C_PCI_DATA_WIDTH-1:0] wTxrTlp;
wire wTxrTlpReady;
wire wTxrTlpValid;
wire wTxrTlpStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrTlpStartOffset;
wire wTxrTlpEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxrTlpEndOffset;
// Output of Mux to
wire [C_PCI_DATA_WIDTH-1:0] wTxTlp;
wire wTxTlpReady;
wire wTxTlpValid;
wire wTxTlpStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxTlpStartOffset;
wire wTxTlpEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxTlpEndOffset;
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
txr_capture_inst
(// Outputs
.WR_DATA_READY (TXR_TLP_READY),
.RD_DATA ({wTxrTlp, wTxrTlpStartFlag, wTxrTlpStartOffset,
wTxrTlpEndFlag, wTxrTlpEndOffset}),
.RD_DATA_VALID (wTxrTlpValid),
// Inputs
.WR_DATA ({TXR_TLP,
TXR_TLP_START_FLAG, TXR_TLP_START_OFFSET,
TXR_TLP_END_FLAG, TXR_TLP_END_OFFSET}),
.WR_DATA_VALID (TXR_TLP_VALID),
.RD_DATA_READY (wTxrTlpReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
txc_capture_inst
(// Outputs
.WR_DATA_READY (TXC_TLP_READY),
.RD_DATA ({wTxcTlp, wTxcTlpStartFlag, wTxcTlpStartOffset,
wTxcTlpEndFlag, wTxcTlpEndOffset}),
.RD_DATA_VALID (wTxcTlpValid),
// Inputs
.WR_DATA ({TXC_TLP,
TXC_TLP_START_FLAG, TXC_TLP_START_OFFSET,
TXC_TLP_END_FLAG, TXC_TLP_END_OFFSET}),
.WR_DATA_VALID (TXC_TLP_VALID),
.RD_DATA_READY (wTxcTlpReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
tx_arbiter
#(/*AUTOINSTPARAM*/
// Parameters
.C_TXC_PRIORITY (C_TXC_PRIORITY),
.C_TXR_PRIORITY (C_TXR_PRIORITY))
tx_arbiter_inst
(// Outputs
.TXR_TLP_READY (wTxrTlpReady),
.TXC_TLP_READY (wTxcTlpReady),
// Inputs
.TX_TLP_READY (wTxTlpReady),
.TXC_TLP_VALID (wTxcTlpValid),
.TXC_TLP_START_FLAG (wTxcTlpStartFlag),
.TXC_TLP_END_FLAG (wTxcTlpEndFlag),
.TXR_TLP_VALID (wTxrTlpValid),
.TXR_TLP_START_FLAG (wTxrTlpStartFlag),
.TXR_TLP_END_FLAG (wTxrTlpEndFlag),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// MUX Selector
tx_phi
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MUX_TYPE (C_MUX_TYPE),
.C_WIDTH (C_WIDTH))
tx_phi_inst
(// Outputs
.TXC_TLP_READY (wTxcTlpReady),
.TXR_TLP_READY (wTxrTlpReady),
.TX_TLP (wTxTlp),
.TX_TLP_VALID (wTxTlpValid),
.TX_TLP_START_FLAG (wTxTlpStartFlag),
.TX_TLP_START_OFFSET (wTxTlpStartOffset),
.TX_TLP_END_FLAG (wTxTlpEndFlag),
.TX_TLP_END_OFFSET (wTxTlpEndOffset),
// Inputs
.TXC_TLP (wTxcTlp),
.TXC_TLP_VALID (wTxcTlpValid),
.TXC_TLP_START_FLAG (wTxcTlpStartFlag),
.TXC_TLP_START_OFFSET (wTxcTlpStartOffset),
.TXC_TLP_END_FLAG (wTxcTlpEndFlag),
.TXC_TLP_END_OFFSET (wTxcTlpEndOffset),
.TXR_TLP (wTxrTlp),
.TXR_TLP_VALID (wTxrTlpValid),
.TXR_TLP_START_FLAG (wTxrTlpStartFlag),
.TXR_TLP_START_OFFSET (wTxrTlpStartOffset),
.TXR_TLP_END_FLAG (wTxrTlpEndFlag),
.TXR_TLP_END_OFFSET (wTxrTlpEndOffset),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
tx_output_inst
(// Outputs
.WR_DATA_READY (wTxTlpReady),
.RD_DATA ({TX_TLP,
TX_TLP_START_FLAG, TX_TLP_START_OFFSET,
TX_TLP_END_FLAG, TX_TLP_END_OFFSET}),
.RD_DATA_VALID (TX_TLP_VALID),
// Inputs
.WR_DATA ({wTxTlp, wTxTlpStartFlag, wTxTlpStartOffset,
wTxTlpEndFlag, wTxTlpEndOffset}),
.WR_DATA_VALID (wTxTlpValid),
.RD_DATA_READY (TX_TLP_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/")
// End:
/*
Description: The tx_arbiter arbitrates between TXC and TXR channels. The C_TX*_PRIORITY
values are counters are the maximum number of uninterrupted TXR or TXC packets that can be
transmitted without transmitting a packet of the other type.
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
module tx_arbiter
#(parameter C_TXC_PRIORITY = 1,
parameter C_TXR_PRIORITY = 1)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: TX Classic Flow Control
input TX_TLP_READY,
// Interface: TXR Flow Control
output TXR_TLP_READY,
input TXR_TLP_VALID,
input TXR_TLP_START_FLAG,
input TXR_TLP_END_FLAG,
// Interface: TXC Flow Control
output TXC_TLP_READY,
input TXC_TLP_VALID,
input TXC_TLP_START_FLAG,
input TXC_TLP_END_FLAG);
`include "functions.vh"
localparam S_TXARB_IDLE = 0; // STATE: Idle state for the arbiter (not currently used)
localparam S_TXARB_TRANSMIT_TXR = 1; // STATE: Transmit TXR packets until the priority counter is reached
localparam S_TXARB_TRANSMIT_TXC = 2; // STATE: Transmit TXC packets until the priority counter is reached
// S_TXARB_PRIORITY is a special state that encodes the type (TXR/TXC) with
// higher priority so that the state machine (below) is general.
localparam S_TXARB_PRIORITY = (S_TXARB_TRANSMIT_TXR >= S_TXARB_TRANSMIT_TXC)? S_TXARB_TRANSMIT_TXR: S_TXARB_TRANSMIT_TXC;
localparam C_NUM_STATES = S_TXARB_TRANSMIT_TXC;
wire wTxrGrant;
wire wTxrReq;
wire wTxrDone;
wire wTxcGrant;
wire wTxcReq;
wire wTxcDone;
reg [clog2s(C_NUM_STATES):0] rArbState,_rArbState;
reg rTxrLast,_rTxrLast; // Reset on RST_IN or TXC_TLP_READY
reg rTxcLast,_rTxcLast; // Reset on RST_IN or TXR_TLP_READY
reg rTxrActive,_rTxrActive; // Reset on RST_IN or TXC_TLP_READY
reg rTxcActive,_rTxcActive; // Reset on RST_IN or TXR_TLP_READY
reg [clog2s(C_TXC_PRIORITY)-1:0] rTxcCounter,_rTxcCounter; // Reset on RST_IN or TXC_TLP_READY
reg [clog2s(C_TXR_PRIORITY)-1:0] rTxrCounter,_rTxrCounter; // Reset on RST_IN or TXR_TLP_READY
assign TXR_TLP_READY = wTxrGrant & TX_TLP_READY; // TODO: Not great
assign wTxrReq = TXR_TLP_START_FLAG & TXR_TLP_VALID;
assign wTxrDone = TXR_TLP_END_FLAG & TXR_TLP_READY;
assign wTxrGrant = (rArbState == S_TXARB_TRANSMIT_TXR);
assign TXC_TLP_READY = wTxcGrant & TX_TLP_READY; // TODO: Not great
assign wTxcReq = TXC_TLP_START_FLAG & TXC_TLP_VALID;
assign wTxcDone = TXC_TLP_END_FLAG & TXC_TLP_READY;
assign wTxcGrant = (rArbState == S_TXARB_TRANSMIT_TXC);
always @(*) begin
// Defaults
_rTxcCounter = rTxcCounter;
_rTxcActive = rTxcActive;
_rTxcLast = rTxcLast;
if(wTxrGrant) begin
_rTxcCounter = 0;
end else if(wTxcReq & wTxcGrant & ~rTxcLast) begin
_rTxcCounter = _rTxcCounter + 1;
end
if(wTxcReq & wTxcGrant) begin
_rTxcActive = 1;
end else if(wTxcDone) begin
_rTxcActive = 0;
end
if(wTxrGrant | RST_IN) begin
_rTxcLast = 0;
end else if(wTxcReq & wTxcGrant) begin
_rTxcLast = (rTxcCounter == (C_TXC_PRIORITY - 1));
end
end // always @ (*)
always @(posedge CLK) begin
if(RST_IN) begin
rTxcCounter <= #1 0;
rTxcActive <= #1 0;
rTxcLast <= #1 0;
end else begin
rTxcCounter <= #1 _rTxcCounter;
rTxcActive <= #1 _rTxcActive;
rTxcLast <= #1 _rTxcLast;
end
end
always @(*) begin
// Defaults
_rTxrCounter = rTxrCounter;
_rTxrActive = rTxrActive;
_rTxrLast = rTxrLast;
if(wTxcGrant) begin
_rTxrCounter = 0;
end else if(wTxrReq & wTxrGrant & ~rTxrLast) begin
_rTxrCounter = _rTxrCounter + 1;
end
if(wTxrReq & wTxrGrant) begin
_rTxrActive = 1;
end else if(wTxrDone) begin
_rTxrActive = 0;
end
if(wTxcGrant | RST_IN) begin
_rTxrLast = 0;
end else if(wTxrReq & wTxrGrant) begin
/* verilator lint_off WIDTH */
_rTxrLast = (rTxrCounter == (C_TXR_PRIORITY - 1));
/* verilator lint_on WIDTH */
end
end
always @(posedge CLK) begin
if(RST_IN) begin
rTxrCounter <= #1 0;
rTxrActive <= #1 0;
rTxrLast <= #1 0;
end else begin
rTxrCounter <= #1 _rTxrCounter;
rTxrActive <= #1 _rTxrActive;
rTxrLast <= #1 _rTxrLast;
end
end
// User encoded state machine
always @(*) begin
_rArbState = rArbState;
case(rArbState)
S_TXARB_TRANSMIT_TXR: begin
if((rTxrLast & wTxrDone & wTxcReq) | (~rTxrActive & ~wTxrReq & wTxcReq)) begin
_rArbState = S_TXARB_TRANSMIT_TXC;
end
end
S_TXARB_TRANSMIT_TXC: begin
if((rTxcLast & wTxcDone & wTxrReq) | (~rTxcActive & ~wTxcReq & wTxrReq)) begin
_rArbState = S_TXARB_TRANSMIT_TXR;
end
end
default: begin
// Error! This should never happen...
end
endcase
end // always @ begin
always @(posedge CLK) begin
if(RST_IN) begin
rArbState <= #1 S_TXARB_PRIORITY;
end else begin
rArbState <= #1 _rArbState;
end
end
endmodule
/*
Description: The tx_phi wraps a mux instantiation for the tx_mux. It is
controlled by the tx_arbiter
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
module tx_phi
#(parameter C_PCI_DATA_WIDTH = 10'd128,
parameter C_MUX_TYPE = "SHIFT",
parameter C_WIDTH = (C_PCI_DATA_WIDTH + 2 * (clog2s(C_PCI_DATA_WIDTH/32) + 1)))
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: TXC Flow Control
input TXC_TLP_READY,
// Interface: TXR Flow Control
input TXR_TLP_READY,
// Interface: TXC
input [C_PCI_DATA_WIDTH-1:0] TXC_TLP,
input TXC_TLP_VALID,
input TXC_TLP_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_START_OFFSET,
input TXC_TLP_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_END_OFFSET,
// Interface: TXR
input [C_PCI_DATA_WIDTH-1:0] TXR_TLP,
input TXR_TLP_VALID,
input TXR_TLP_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_START_OFFSET,
input TXR_TLP_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_END_OFFSET,
// Interface: TX Classic
output [C_PCI_DATA_WIDTH-1:0] TX_TLP,
output TX_TLP_VALID,
output TX_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET,
output TX_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET);
`include "functions.vh"
// Width = 2 * (DATA WIDTH + VALID + START FLAG + START OFFSET + END FLAG + END OFFSET)
localparam C_MUX_WIDTH = C_PCI_DATA_WIDTH + 3 + 2*clog2s(C_PCI_DATA_WIDTH/32);
wire [2*C_MUX_WIDTH-1:0] wAggregate;
assign wAggregate = {{TXR_TLP,TXR_TLP_VALID,TXR_TLP_START_FLAG,
TXR_TLP_START_OFFSET,TXR_TLP_END_FLAG,TXR_TLP_END_OFFSET},
{TXC_TLP,TXC_TLP_VALID,TXC_TLP_START_FLAG,
TXC_TLP_START_OFFSET,TXC_TLP_END_FLAG,TXC_TLP_END_OFFSET}};
mux
#(// Parameters
.C_NUM_INPUTS (2),
.C_CLOG_NUM_INPUTS (1),
.C_WIDTH (C_MUX_WIDTH),
.C_MUX_TYPE ("SELECT")
/*AUTOINSTPARAM*/)
mux_inst
(// Outputs
.MUX_OUTPUT ({TX_TLP,TX_TLP_VALID,TX_TLP_START_FLAG,
TX_TLP_START_OFFSET,TX_TLP_END_FLAG,
TX_TLP_END_OFFSET}),
// Inputs
.MUX_INPUTS (wAggregate),
.MUX_SELECT (TXR_TLP_READY)
/*AUTOINST*/);
endmodule
|
// -*- Mode: Verilog -*-
// Filename : pb_timer.v
// Description : Picoblaze Timer
// Author : Philip Tracton
// Created On : Thu May 28 22:25:06 2015
// Last Modified By: Philip Tracton
// Last Modified On: Thu May 28 22:25:06 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module pb_timer (/*AUTOARG*/
// Outputs
data_out, interrupt,
// Inputs
clk, reset, port_id, data_in, read_strobe, write_strobe, watchdog
) ;
parameter BASE_ADDRESS = 8'h00;
input clk;
input reset;
input [7:0] port_id;
input [7:0] data_in;
output [7:0] data_out;
input read_strobe;
input write_strobe;
output interrupt;
input watchdog;
/*AUTOREG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] timer_count; // From regs of timer_regs.v
wire timer_enable; // From regs of timer_regs.v
wire timer_interrupt; // From timer0 of timer.v
wire timer_interrupt_clear; // From regs of timer_regs.v
// End of automatics
//
// Registers
//
timer_regs regs (/*AUTOINST*/
// Outputs
.data_out (data_out[7:0]),
.interrupt (interrupt),
.timer_enable (timer_enable),
.timer_count (timer_count[31:0]),
.timer_interrupt_clear(timer_interrupt_clear),
// Inputs
.clk (clk),
.reset (reset),
.port_id (port_id[7:0]),
.data_in (data_in[7:0]),
.read_strobe (read_strobe),
.write_strobe (write_strobe),
.timer_interrupt (timer_interrupt));
//
// Timer
//
timer timer0(/*AUTOINST*/
// Outputs
.timer_interrupt (timer_interrupt),
// Inputs
.clk (clk),
.timer_count (timer_count[31:0]),
.timer_enable (timer_enable),
.timer_interrupt_clear (timer_interrupt_clear));
endmodule // pb_timer
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Wishbone Single-Port Synchronous RAM ////
//// Memory Model ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
//// ////
//// Description ////
//// This Wishbone controller connects to the wrapper of ////
//// the single-port synchronous memory interface. ////
//// Besides universal memory due to onchip_ram it provides a ////
//// generic way to set the depth of the memory. ////
//// ////
//// To Do: ////
//// ////
//// Author(s): ////
//// - Raul Fajardo, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revision History
//
//
// Revision 1.0 2009/08/18 15:15:00 fajardo
// Created interface and tested
//
`include "timescale.v"
module minsoc_memory_model (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o
);
//
// Parameters
//
parameter adr_width = 2;
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Internal regs and wires
//
wire we;
wire [3:0] be_i;
wire [31:0] wb_dat_o;
reg ack_we;
reg ack_re;
//
// Aliases and simple assignments
//
assign wb_ack_o = ack_re | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
//
// Write acknowledge
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_we <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
ack_we <= #1 1'b1;
else
ack_we <= #1 1'b0;
end
//
// read acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_re <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
ack_re <= #1 1'b1;
else
ack_re <= #1 1'b0;
end
minsoc_onchip_ram #
(
.aw(adr_width)
)
block_ram_0 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[adr_width+1:2]),
.di(wb_dat_i[7:0]),
.doq(wb_dat_o[7:0]),
.we(we),
.oe(1'b1),
.ce(be_i[0]));
minsoc_onchip_ram #
(
.aw(adr_width)
)
block_ram_1 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[adr_width+1:2]),
.di(wb_dat_i[15:8]),
.doq(wb_dat_o[15:8]),
.we(we),
.oe(1'b1),
.ce(be_i[1]));
minsoc_onchip_ram #
(
.aw(adr_width)
)
block_ram_2 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[adr_width+1:2]),
.di(wb_dat_i[23:16]),
.doq(wb_dat_o[23:16]),
.we(we),
.oe(1'b1),
.ce(be_i[2]));
minsoc_onchip_ram #
(
.aw(adr_width)
)
block_ram_3 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[adr_width+1:2]),
.di(wb_dat_i[31:24]),
.doq(wb_dat_o[31:24]),
.we(we),
.oe(1'b1),
.ce(be_i[3]));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:18:20 PM
// Design Name:
// Module Name: Mux_Array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// synopsys dc_script_begin
//
// synopsys dc_script_end
module Multiplexer_AC
# (parameter W = 32)
(
input wire ctrl,
input wire [W-1:0] D0,
input wire [W-1:0] D1,
output reg [W-1:0] S
);
always @(ctrl, D0, D1)
case (ctrl)
1'b0: S <= D0;
1'b1: S <= D1;
endcase
endmodule
module Rotate_Mux_Array
#(parameter SWR=26)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
output wire [SWR-1:0] Data_o
);
genvar j;//Create a variable for the loop FOR
generate for (j=0; j <= SWR-1; j=j+1) begin : MUX_ARRAY
case (j)
SWR-1-j:begin : MUX_ARRAY11
assign Data_o[j]=Data_i[SWR-1-j];
end
default:begin : MUX_ARRAY12
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (Data_i[SWR-1-j]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
endmodule
module DW_rbsh_inst #(parameter SWR = 8, parameter EWR = 3) ( Data_i, Shift_Value_i, inst_SH_TC, Data_o );
//Barrel Shifter with Preferred Right Direction
input [SWR-1 : 0] Data_i;
input [EWR-1 : 0] Shift_Value_i;
input inst_SH_TC;
output [SWR-1 : 0] Data_o;
// Instance of DW_rbsh
DW_rbsh #(SWR, EWR) U1 (
.A(Data_i),
.SH(Shift_Value_i),
.SH_TC(inst_SH_TC),
.B(Data_o) );
endmodule
module Mux_Array_DW
#(parameter SWR=26, parameter EWR=5)
(
input wire clk,
input wire rst,
input wire [SWR-1:0] Data_i,
input wire FSM_left_right_i,
input wire [EWR-1:0] Shift_Value_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
////ge
wire [SWR:0] Data_array[EWR+1:0];
assign Data_array [0] = {Data_i, bit_shift_i};
//////////////////7
genvar k;//Level
///////////////////77777
Rotate_Mux_Array #(.SWR(SWR+1)) first_rotate(
.Data_i(Data_array [0] ),
.select_i(FSM_left_right_i),
.Data_o(Data_array [1][SWR:0])
);
DW_rbsh_inst #(
.SWR(SWR+1),
.EWR(EWR)
) inst_DW_rbsh_inst (
.Data_i (Data_array [2][SWR:0]),
.Shift_Value_i (Shift_Value_i),
.inst_SH_TC (FSM_left_right_i),
.Data_o (Data_array [3][SWR:0])
);
Rotate_Mux_Array #(.SWR(SWR+1) last_rotate(
.Data_i(Data_array [4][SWR:0]),
.select_i(FSM_left_right_i),
.Data_o(Data_o)
);
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module clips video streams on the DE boards. *
* *
******************************************************************************/
//`define USE_CLIPPER_DROP
module Raster_Laser_Projector_Video_In_video_clipper_0 (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 7; // Frame's data width
parameter EW = 0; // Frame's empty width
parameter WIDTH_IN = 720; // Incoming frame's width in pixels
parameter HEIGHT_IN = 244; // Incoming frame's height in lines
parameter WW_IN = 9; // Incoming frame's width's address width
parameter HW_IN = 7; // Incoming frame's height's address width
parameter DROP_PIXELS_AT_START = 40;
parameter DROP_PIXELS_AT_END = 40;
parameter DROP_LINES_AT_START = 2;
parameter DROP_LINES_AT_END = 2;
parameter WIDTH_OUT = 640; // Final frame's width in pixels
parameter HEIGHT_OUT = 240; // Final frame's height in lines
parameter WW_OUT = 9; // Final frame's width's address width
parameter HW_OUT = 7; // Final frame's height's address width
parameter ADD_PIXELS_AT_START = 0;
parameter ADD_PIXELS_AT_END = 0;
parameter ADD_LINES_AT_START = 0;
parameter ADD_LINES_AT_END = 0;
parameter ADD_DATA = 8'd0; // Data value for added pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [DW: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire [EW: 0] internal_empty;
wire internal_valid;
wire internal_ready;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_clipper_drop Clipper_Drop (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_empty (stream_in_empty),
.stream_in_valid (stream_in_valid),
.stream_out_ready (internal_ready),
// Bidirectional
// Outputs
.stream_in_ready (stream_in_ready),
.stream_out_data (internal_data),
.stream_out_startofpacket (internal_startofpacket),
.stream_out_endofpacket (internal_endofpacket),
.stream_out_empty (internal_empty),
.stream_out_valid (internal_valid)
);
defparam
Clipper_Drop.DW = DW,
Clipper_Drop.EW = EW,
Clipper_Drop.IMAGE_WIDTH = WIDTH_IN,
Clipper_Drop.IMAGE_HEIGHT = HEIGHT_IN,
Clipper_Drop.WW = WW_IN,
Clipper_Drop.HW = HW_IN,
Clipper_Drop.DROP_PIXELS_AT_START = DROP_PIXELS_AT_START,
Clipper_Drop.DROP_PIXELS_AT_END = DROP_PIXELS_AT_END,
Clipper_Drop.DROP_LINES_AT_START = DROP_LINES_AT_START,
Clipper_Drop.DROP_LINES_AT_END = DROP_LINES_AT_END,
Clipper_Drop.ADD_DATA = ADD_DATA;
altera_up_video_clipper_add Clipper_Add (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (internal_data),
.stream_in_startofpacket (internal_startofpacket),
.stream_in_endofpacket (internal_endofpacket),
.stream_in_empty (internal_empty),
.stream_in_valid (internal_valid),
.stream_out_ready (stream_out_ready),
// Bidirectional
// Outputs
.stream_in_ready (internal_ready),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_empty (stream_out_empty),
.stream_out_valid (stream_out_valid)
);
defparam
Clipper_Add.DW = DW,
Clipper_Add.EW = EW,
Clipper_Add.IMAGE_WIDTH = WIDTH_OUT,
Clipper_Add.IMAGE_HEIGHT = HEIGHT_OUT,
Clipper_Add.WW = WW_OUT,
Clipper_Add.HW = HW_OUT,
Clipper_Add.ADD_PIXELS_AT_START = ADD_PIXELS_AT_START,
Clipper_Add.ADD_PIXELS_AT_END = ADD_PIXELS_AT_END,
Clipper_Add.ADD_LINES_AT_START = ADD_LINES_AT_START,
Clipper_Add.ADD_LINES_AT_END = ADD_LINES_AT_END,
Clipper_Add.ADD_DATA = ADD_DATA;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_BLACKBOX_V
`define SKY130_FD_SC_HD__OR3B_BLACKBOX_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_BLACKBOX_V
|
/*
*
* Copyright (c) 2013 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
/* Sorry if this code is ugly. Go have a look at the RIPEMD-160 specification
* and you'll understand my pain.
*/
module ripemd160 (
input clk,
input rx_reset,
input [255:0] rx_hash,
output reg tx_done = 1'b0,
output reg [159:0] tx_hash = 160'd0
);
//
reg [511:0] block;
reg [31:0] A, B, C, D, E, AA, BB, CC, DD, EE;
reg [6:0] round;
// K constants
wire [31:0] k0, k1;
ripemd160_k_constant k_constant_blk (
.clk (clk),
.rx_round (rx_reset ? 7'd0 : round),
.tx_k0 (k0),
.tx_k1 (k1)
);
// Rotation amounts
wire [3:0] first_rotate, second_rotate;
ripemd160_rol_s rol_s_blk (
.clk (clk),
.rx_round (rx_reset ? 7'd0 : (round + 7'd1)),
.tx_s0 (first_rotate),
.tx_s1 (second_rotate)
);
// Message word selection
wire [3:0] first_word, second_word;
ripemd160_word_sel word_sel_blk (
.clk (clk),
.rx_round (rx_reset ? 7'd0 : (round + 7'd1)),
.tx_s0 (first_word),
.tx_s1 (second_word)
);
// Non-linear functions
wire [31:0] nl_0, nl_1;
ripemd160_nonlinear nonlinear_0 (round, B, C, D, nl_0);
ripemd160_nonlinear nonlinear_1 (7'd79 - round, BB, CC, DD, nl_1);
// Select words
wire [31:0] x_0 = block >> {first_word, 5'd0};
wire [31:0] x_1 = block >> {second_word, 5'd0};
// Big calculations
wire [31:0] partial_T = A + nl_0 + x_0 + k0;
wire [31:0] partial_TT = AA + nl_1 + x_1 + k1;
// Rotations
wire [31:0] rotated_T, rotated_TT;
ripemd160_rol first_rol_blk (first_rotate, partial_T, rotated_T);
ripemd160_rol second_rol_blk (second_rotate, partial_TT, rotated_TT);
always @ (posedge clk)
begin
A <= E;
B <= rotated_T + E;
C <= B;
D <= {C[21:0], C[31:22]};
E <= D;
AA <= EE;
BB <= rotated_TT + EE;
CC <= BB;
DD <= {CC[21:0], CC[31:22]};
EE <= DD;
round <= round + 7'd1;
if (round == 80 && !tx_done)
begin
tx_done <= 1'b1;
/*{tx_hash[31:24],tx_hash[23:16],tx_hash[15:8],tx_hash[7:0]} <= 32'hEFCDAB89 + C + DD;
{tx_hash[63:56],tx_hash[55:48],tx_hash[47:40],tx_hash[39:32]} <= 32'h98BADCFE + D + EE;
{tx_hash[95:88],tx_hash[87:80],tx_hash[79:72],tx_hash[71:64]} <= 32'h10325476 + E + AA;
{tx_hash[127:120],tx_hash[119:112],tx_hash[111:104],tx_hash[103:96]} <= 32'hC3D2E1F0 + A + BB;
{tx_hash[159:152],tx_hash[151:144],tx_hash[143:136],tx_hash[135:128]} <= 32'h67452301 + B + CC;*/
{tx_hash[135:128],tx_hash[143:136],tx_hash[151:144],tx_hash[159:152]} <= 32'hEFCDAB89 + C + DD;
{tx_hash[103:96],tx_hash[111:104],tx_hash[119:112],tx_hash[127:120]} <= 32'h98BADCFE + D + EE;
{tx_hash[71:64],tx_hash[79:72],tx_hash[87:80],tx_hash[95:88]} <= 32'h10325476 + E + AA;
{tx_hash[39:32],tx_hash[47:40],tx_hash[55:48],tx_hash[63:56]} <= 32'hC3D2E1F0 + A + BB;
{tx_hash[7:0],tx_hash[15:8],tx_hash[23:16],tx_hash[31:24]} <= 32'h67452301 + B + CC;
end
if (rx_reset)
begin
{E, D, C, B, A} <= 160'hC3D2E1F01032547698BADCFEEFCDAB8967452301;
{EE, DD, CC, BB, AA} <= 160'hC3D2E1F01032547698BADCFEEFCDAB8967452301;
tx_done <= 1'b0;
round <= 0;
block[`IDX(0)] <= {rx_hash[231:224],rx_hash[239:232],rx_hash[247:240],rx_hash[255:248]};
block[`IDX(1)] <= {rx_hash[199:192],rx_hash[207:200],rx_hash[215:208],rx_hash[223:216]};
block[`IDX(2)] <= {rx_hash[167:160],rx_hash[175:168],rx_hash[183:176],rx_hash[191:184]};
block[`IDX(3)] <= {rx_hash[135:128],rx_hash[143:136],rx_hash[151:144],rx_hash[159:152]};
block[`IDX(4)] <= {rx_hash[103:96],rx_hash[111:104],rx_hash[119:112],rx_hash[127:120]};
block[`IDX(5)] <= {rx_hash[71:64],rx_hash[79:72],rx_hash[87:80],rx_hash[95:88]};
block[`IDX(6)] <= {rx_hash[39:32],rx_hash[47:40],rx_hash[55:48],rx_hash[63:56]};
block[`IDX(7)] <= {rx_hash[7:0],rx_hash[15:8],rx_hash[23:16],rx_hash[31:24]};
block[`IDX(8)] <= 32'h00000080;
block[`IDX(9)] <= 32'h00000000;
block[`IDX(10)] <= 32'h00000000;
block[`IDX(11)] <= 32'h00000000;
block[`IDX(12)] <= 32'h00000000;
block[`IDX(13)] <= 32'h00000000;
block[`IDX(14)] <= 32'h00000100; // Message length
block[`IDX(15)] <= 32'h00000000;
end
end
endmodule
module ripemd160_k_constant (
input clk,
input [6:0] rx_round,
output reg [31:0] tx_k0 = 32'h0,
output reg [31:0] tx_k1 = 32'h0
);
always @ (posedge clk)
begin
// These are less than, instead of less-than-or-equal-to,
// because we're calculating K for the next round.
if (rx_round < 15)
{tx_k1, tx_k0} <= {32'h50A28BE6, 32'h00000000};
else if (rx_round < 31)
{tx_k1, tx_k0} <= {32'h5C4DD124, 32'h5A827999};
else if (rx_round < 47)
{tx_k1, tx_k0} <= {32'h6D703EF3, 32'h6ED9EBA1};
else if (rx_round < 63)
{tx_k1, tx_k0} <= {32'h7A6D76E9, 32'h8F1BBCDC};
else
{tx_k1, tx_k0} <= {32'h00000000, 32'hA953FD4E};
end
endmodule
module ripemd160_nonlinear (
input [6:0] rx_round,
input [31:0] rx_x,
input [31:0] rx_y,
input [31:0] rx_z,
output reg [31:0] tx_f
);
always @ (*)
begin
if (rx_round <= 15)
tx_f = rx_x ^ rx_y ^ rx_z;
else if (rx_round <= 31)
tx_f = (rx_x & rx_y) | ((~rx_x) & rx_z);
else if (rx_round <= 47)
tx_f = (rx_x | (~rx_y)) ^ rx_z;
else if (rx_round <= 63)
tx_f = (rx_x & rx_z) | (rx_y & (~rx_z));
else
tx_f = rx_x ^ (rx_y | (~rx_z));
end
endmodule
module ripemd160_rol (
input [3:0] rx_s,
input [31:0] rx_x,
output [31:0] tx_x
);
assign tx_x = (rx_x << rx_s) | (rx_x >> (32 - rx_s));
endmodule
// amount for rotate left
module ripemd160_rol_s (
input clk,
input [6:0] rx_round,
output reg [3:0] tx_s0,
output reg [3:0] tx_s1
);
localparam [319:0] first_sequence = {4'd6,4'd5,4'd8,4'd11,4'd14,4'd13,4'd12,4'd5,4'd12,4'd13,4'd8,4'd6,4'd11,4'd5,4'd15,4'd9,4'd12,4'd5,4'd6,4'd8,4'd6,4'd5,4'd14,4'd9,4'd8,4'd9,4'd15,4'd14,4'd15,4'd14,4'd12,4'd11,4'd5,4'd7,4'd12,4'd5,4'd6,4'd13,4'd8,4'd14,4'd15,4'd13,4'd9,4'd14,4'd7,4'd6,4'd13,4'd11,4'd12,4'd13,4'd7,4'd11,4'd9,4'd15,4'd12,4'd7,4'd15,4'd7,4'd9,4'd11,4'd13,4'd8,4'd6,4'd7,4'd8,4'd9,4'd7,4'd6,4'd15,4'd14,4'd13,4'd11,4'd9,4'd7,4'd8,4'd5,4'd12,4'd15,4'd14,4'd11};
localparam [319:0] second_sequence = {4'd11,4'd11,4'd13,4'd15,4'd5,4'd6,4'd13,4'd8,4'd6,4'd14,4'd5,4'd12,4'd9,4'd12,4'd5,4'd8,4'd8,4'd15,4'd5,4'd12,4'd9,4'd12,4'd9,4'd6,4'd14,4'd6,4'd14,4'd14,4'd11,4'd8,4'd5,4'd15,4'd5,4'd7,4'd13,4'd13,4'd14,4'd5,4'd13,4'd12,4'd14,4'd6,4'd6,4'd8,4'd11,4'd15,4'd7,4'd9,4'd11,4'd13,4'd15,4'd6,4'd7,4'd12,4'd7,4'd7,4'd11,4'd9,4'd8,4'd12,4'd7,4'd15,4'd13,4'd9,4'd6,4'd12,4'd14,4'd14,4'd11,4'd8,4'd7,4'd7,4'd5,4'd15,4'd15,4'd13,4'd11,4'd9,4'd9,4'd8};
always @ (posedge clk)
begin
tx_s0 <= first_sequence >> {rx_round, 2'b00};
tx_s1 <= second_sequence >> {rx_round, 2'b00};
end
endmodule
module ripemd160_word_sel (
input clk,
input [6:0] rx_round,
output reg [3:0] tx_s0,
output reg [3:0] tx_s1
);
localparam [319:0] first_sequence = {4'd13,4'd15,4'd6,4'd11,4'd8,4'd3,4'd1,4'd14,4'd10,4'd2,4'd12,4'd7,4'd9,4'd5,4'd0,4'd4,4'd2,4'd6,4'd5,4'd14,4'd15,4'd7,4'd3,4'd13,4'd4,4'd12,4'd8,4'd0,4'd10,4'd11,4'd9,4'd1,4'd12,4'd5,4'd11,4'd13,4'd6,4'd0,4'd7,4'd2,4'd1,4'd8,4'd15,4'd9,4'd4,4'd14,4'd10,4'd3,4'd8,4'd11,4'd14,4'd2,4'd5,4'd9,4'd0,4'd12,4'd3,4'd15,4'd6,4'd10,4'd1,4'd13,4'd4,4'd7,4'd15,4'd14,4'd13,4'd12,4'd11,4'd10,4'd9,4'd8,4'd7,4'd6,4'd5,4'd4,4'd3,4'd2,4'd1,4'd0};
localparam [319:0] second_sequence = {4'd11,4'd9,4'd3,4'd0,4'd14,4'd13,4'd2,4'd6,4'd7,4'd8,4'd5,4'd1,4'd4,4'd10,4'd15,4'd12,4'd14,4'd10,4'd7,4'd9,4'd13,4'd2,4'd12,4'd5,4'd0,4'd15,4'd11,4'd3,4'd1,4'd4,4'd6,4'd8,4'd13,4'd4,4'd0,4'd10,4'd2,4'd12,4'd8,4'd11,4'd9,4'd6,4'd14,4'd7,4'd3,4'd1,4'd5,4'd15,4'd2,4'd1,4'd9,4'd4,4'd12,4'd8,4'd15,4'd14,4'd10,4'd5,4'd13,4'd0,4'd7,4'd3,4'd11,4'd6,4'd12,4'd3,4'd10,4'd1,4'd8,4'd15,4'd6,4'd13,4'd4,4'd11,4'd2,4'd9,4'd0,4'd7,4'd14,4'd5};
always @ (posedge clk)
begin
tx_s0 <= first_sequence >> {rx_round, 2'b00};
tx_s1 <= second_sequence >> {rx_round, 2'b00};
end
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_timeIn (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 5: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 5: 0] data_out;
wire [ 5: 0] out_port;
wire [ 5: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {6 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[5 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
`timescale 1ns / 1ps
//this code was generated by cReComp
module sensor_ctl(
input [0:0] clk,
input rst_32,
input [31:0] din_32,
input [0:0] wr_en_32,
input [0:0] rd_en_32,
output [31:0] dout_32,
output [0:0] full_32,
output [0:0] empty_32,
input [0:0] SPI_DI_g,
output [0:0] SPI_SS_g,
output [0:0] SPI_CK_g,
output [0:0] SPI_DO_g
);
parameter INIT_32 = 0,
READY_RCV_32 = 1,
RCV_DATA_32 = 2,
POSE_32 = 3,
READY_SND_32 = 4,
SND_DATA_32_x = 5,
SND_DATA_32_y = 6,
SND_DATA_32_z = 7;
// for input fifo
wire [31:0] rcv_data_32;
wire rcv_en_32;
wire data_empty_32;
// for output fifo
wire [31:0] snd_data_32;
wire snd_en_32;
wire data_full_32;
// state register
reg [3:0] state_32;
wire [15:0] gyro_x;
wire [15:0] gyro_y;
wire [15:0] gyro_z;
reg [15:0] gyro_x_reg;
reg [15:0] gyro_y_reg;
reg [15:0] gyro_z_reg;
wire arm_rd_en_g;
////fifo 32bit
fifo_32x512 input_fifo_32(
.clk(clk),
.srst(rst_32),
.din(din_32),
.wr_en(wr_en_32),
.full(full_32),
.dout(rcv_data_32),
.rd_en(rcv_en_32),
.empty(data_empty_32)
);
fifo_32x512 output_fifo_32(
.clk(clk),
.srst(rst_32),
.din(snd_data_32),
.wr_en(snd_en_32),
.full(data_full_32),
.dout(dout_32),
.rd_en(rd_en_32),
.empty(empty_32)
);
MPU_gyro_controller MPU_gyro_controller(
.clk(clk),
.reset(rst_32),
.gyro_x(gyro_x),
.gyro_y(gyro_y),
.gyro_z(gyro_z),
.SPI_SS_g(SPI_SS_g), //Sleve select
.SPI_CK_g(SPI_CK_g), //SCLK
.SPI_DO_g(SPI_DO_g), //Master out Sleve in
.SPI_DI_g(SPI_DI_g), //Master in Slave out
.arm_read_enable_g(arm_rd_en_g) //finish sensing accel_xyz
);
always @(posedge clk)begin
if(rst_32)
state_32 <= 0;
else
case (state_32)
INIT_32: state_32 <= READY_RCV_32;
READY_RCV_32: if(1) state_32 <= RCV_DATA_32;
RCV_DATA_32: state_32 <= POSE_32;
POSE_32: if(arm_rd_en_g) state_32 <= READY_SND_32;
// POSE_32: if(1) state_32 <= READY_SND_32;
READY_SND_32: if(data_full_32 == 0) state_32 <= SND_DATA_32_x;
// READY_SND_32: if(1) state_32 <= SND_DATA_32_x;
SND_DATA_32_x: state_32 <= SND_DATA_32_y;
SND_DATA_32_y: state_32 <= SND_DATA_32_z;
SND_DATA_32_z: state_32 <= READY_RCV_32;
endcase
end
assign rcv_en_32 = (state_32 == RCV_DATA_32);
assign snd_en_32 = (state_32 > READY_SND_32);
assign snd_data_32 = (state_32 == SND_DATA_32_x)? gyro_x_reg:
(state_32 == SND_DATA_32_y)? gyro_y_reg:
(state_32 == SND_DATA_32_z)? gyro_z_reg:0;
always @(posedge clk) begin
if (rst_32) begin
gyro_x_reg <= 0;
gyro_y_reg <= 0;
gyro_z_reg <= 0;
end
else
case (state_32)
INIT_32: begin
gyro_x_reg <= 0;
gyro_y_reg <= 0;
gyro_z_reg <= 0;
end
READY_RCV_32: begin
gyro_x_reg <= 0;
gyro_y_reg <= 0;
gyro_z_reg <= 0;
end
POSE_32: begin
gyro_x_reg <= gyro_x;
gyro_y_reg <= gyro_y;
gyro_z_reg <= gyro_z;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_TB_V
`define SKY130_FD_SC_LS__TAPVPWRVGND_TB_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tapvpwrvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__tapvpwrvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVPWRVGND_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_M_V
`define SKY130_FD_SC_LP__XOR2_M_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor2_m (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor2_m (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_M_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pt1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_pt1(/*AUTOARG*/
// Outputs
out0, out1, pcx_spc_grant_px, so,
// Inputs
in0, in1, pcx_spc_grant_buf_pa, rclk, si, se
);
output [4:0] out0;
output out1;
output [4:0] pcx_spc_grant_px;
output so;
input [4:0] in0;
input in1;
input [4:0] pcx_spc_grant_buf_pa;
input rclk;
input si, se;
dff_s #(5) dff_ccx_com_spc(
.din (pcx_spc_grant_buf_pa[4:0]),
.q (pcx_spc_grant_px[4:0]),
.clk (rclk),
.se (1'b0),
.si (5'd0),
.so ());
assign out0[4:0] = in0[4:0];
assign out1 = in1;
endmodule // pcx_grant_ff
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 256 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Top level of the high speed FFT core
// FUNCTION: Structural model of the high speed 256-complex point FFT
// core intended for synthesizing
// for any type FPGAs and ASIC.
// FILES: FFT256.v - root unit, this file,
// FFT256_CONFIG.inc - core configuration file
// BUFRAM256C.v - 1-st,2-nd,3-d data buffer, contains:
// RAM2x256C.v - dual ported synchronous RAM, contains:
// RAM256.v -single ported synchronous RAM
// FFT16.v- 1-st,2-nd stages implementing 16-point FFTs, contains
// MPU707.v, MPU707_2.v - multiplier to the factor 0.707.
// ROTATOR256.v - unit for rotating complex vectors, contains
// WROM256.v - ROM of twiddle factors.
// CNORM.v - normalization stages
// UNFFT256_TB.v - testbench file, includes:
// Wave_ROM256.v - ROM with input data and result reference data
// SineROM256_gen.pl - PERL script to generate the Wave_ROM256.v file
//
// PROPERTIES: 1. Fully pipelined, 1 complex data in, 1 complex result out each clock cycle
// 2. Input data, output data, coefficient widths are adjustable in range 8..16
// 3. Normalization stages trigger the data overflow and shift data right
// to prevent the overflow
// 4. Core can contain 2 or 3 data buffers. In the configuration of 2 buffers
// the results are in the shuffled order but provided with the proper address.
// 5. The core operation can be slowed down by the control of the ED input
// 6. The reset RST is synchronous one
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`timescale 1 ns / 1 ps
`include "FFT256_CONFIG.inc"
module FFT256 ( CLK ,RST ,ED ,START ,SHIFT ,DR ,DI ,RDY ,OVF1 ,OVF2 ,ADDR ,DOR ,DOI );
`FFT256paramnb //nb is the data bit width
output RDY ; // in the next cycle after RDY=1 the 0-th result is present
wire RDY ;
output OVF1 ; // 1 signals that an overflow occured in the 1-st stage
wire OVF1 ;
output OVF2 ; // 1 signals that an overflow occured in the 2-nd stage
wire OVF2 ;
output [7:0] ADDR ; //result data address/number
wire [7:0] ADDR ;
output [nb+3:0] DOR ;//Real part of the output data,
wire [nb+3:0] DOR ; // the bit width is nb+4, can be decreased when instantiating the core
output [nb+3:0] DOI ;//Imaginary part of the output data
wire [nb+3:0] DOI ;
input CLK ; //Clock signal is less than 300 MHz for the Xilinx Virtex5 FPGA
wire CLK ;
input RST ; //Reset signal, is the synchronous one with respect to CLK
wire RST ;
input ED ; //=1 enables the operation (eneabling CLK)
wire ED ;
input START ; // its falling edge starts the transform or the serie of transforms
wire START ; // and resets the overflow detectors
input [3:0] SHIFT ; // bits 1,0 -shift left code in the 1-st stage
wire [3:0] SHIFT ; // bits 3,2 -shift left code in the 2-nd stage
input [nb-1:0] DR ; // Real part of the input data, 0-th data goes just after
wire [nb-1:0] DR ; // the START signal or after 255-th data of the previous transform
input [nb-1:0] DI ; //Imaginary part of the input data
wire [nb-1:0] DI ;
wire [nb-1:0] dr1,di1;
wire [nb+1:0] dr3,di3,dr4,di4, dr5,di5 ;
wire [nb+3:0] dr2,di2;
wire [nb+5:0] dr6,di6;
wire [nb+3:0] dr7,di7,dr8,di8;
wire rdy1,rdy2,rdy3,rdy4,rdy5,rdy6,rdy7,rdy8;
reg [7:0] addri ;
// input buffer =8-bit inversion ordering
BUFRAM256C #(nb) U_BUF1(.CLK(CLK), .RST(RST), .ED(ED), .START(START),
.DR(DR), .DI(DI), .RDY(rdy1), .DOR(dr1), .DOI(di1));
//1-st stage of FFT
FFT16 #(nb) U_FFT1(.CLK(CLK), .RST(RST), .ED(ED),
.START(rdy1),.DIR(dr1),.DII(di1),
.RDY(rdy2), .DOR(dr2),. DOI(di2));
wire [1:0] shiftl= SHIFT[1:0];
CNORM #(nb) U_NORM1( .CLK(CLK), .ED(ED), //1-st normalization unit
.START(rdy2), // overflow detector reset
.DR(dr2), .DI(di2),
.SHIFT(shiftl), //shift left bit number
.OVF(OVF1),
.RDY(rdy3),
.DOR(dr3),.DOI(di3));
// rotator to the angles proportional to PI/32
ROTATOR64 #(nb+2) U_MPU (.CLK(CLK),.RST(RST),.ED(ED),
.START(rdy3),. DR(dr3),.DI(di3),
.RDY(rdy4), .DOR(dr4), .DOI(di4));
BUFRAM256C #(nb+2) U_BUF2(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering
.START(rdy4),. DR(dr4),.DI(di4),
.RDY(rdy5), .DOR(dr5), .DOI(di5));
//2-nd stage of FFT
FFT16 #(nb+2) U_FFT2(.CLK(CLK), .RST(RST), .ED(ED),
.START(rdy5),. DIR(dr5),.DII(di5),
.RDY(rdy6), .DOR(dr6), .DOI(di6));
wire [1:0] shifth= SHIFT[3:2];
//2-nd normalization unit
CNORM #(nb+2) U_NORM2 ( .CLK(CLK), .ED(ED),
.START(rdy6), // overflow detector reset
.DR(dr6), .DI(di6),
.SHIFT(shifth), //shift left bit number
.OVF(OVF2),
.RDY(rdy7),
.DOR(dr7), .DOI(di7));
BUFRAM256C #(nb+4) Ubuf3(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering
.START(rdy7),. DR(dr7),.DI(di7),
.RDY(rdy8), .DOR(dr8), .DOI(di8));
`ifdef FFT256parambuffers3 // 3-data buffer configuratiion
always @(posedge CLK) begin //POINTER to the result samples
if (RST)
addri<=8'b0000_0000;
else if (rdy8==1 )
addri<=8'b0000_0000;
else if (ED)
addri<=addri+1;
end
assign ADDR= addri ;
assign DOR=dr8;
assign DOI=di8;
assign RDY=rdy8;
`else
always @(posedge CLK) begin //POINTER to the result samples
if (RST)
addri<=8'b0000_0000;
else if (rdy7)
addri<=8'b0000_0000;
else if (ED)
addri<=addri+1;
end
assign #1 ADDR= {addri[3:0] , addri[7:4]} ;
assign #2 DOR= dr7;
assign #2 DOI= di7;
assign RDY= rdy7;
`endif
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : fme_top.v
// Author : Yufeng Bai
// Email : [email protected]
//
// $Id$
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fme_top (
clk ,
rstn ,
sysif_cmb_x_i ,
sysif_cmb_y_i ,
sysif_qp_i ,
sysif_start_i ,
sysif_done_o ,
fimeif_partition_i ,
fimeif_mv_rden_o ,
fimeif_mv_rdaddr_o ,
fimeif_mv_data_i ,
cur_rden_o ,
//cur_sel_o ,
//cur_idx_o ,
cur_4x4_idx_o ,
cur_4x4_x_o ,
cur_4x4_y_o ,
cur_pel_i ,
ref_rden_o ,
ref_idx_x_o ,
ref_idx_y_o ,
ref_pel_i ,
mcif_mv_rden_o ,
mcif_mv_rdaddr_o ,
mcif_mv_data_i ,
mcif_mv_wren_o ,
mcif_mv_wraddr_o ,
mcif_mv_data_o ,
mcif_pre_pixel_o ,
mcif_pre_wren_o ,
mcif_pre_addr_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [`PIC_X_WIDTH-1:0] sysif_cmb_x_i ; // current LCU x index
input [`PIC_X_WIDTH-1:0] sysif_cmb_y_i ; // current LCU y index
input [6-1:0] sysif_qp_i ; // qp value
input [1-1:0] sysif_start_i ; // fme start signal
output [1-1:0] sysif_done_o ; // fme done signal
input [42-1:0] fimeif_partition_i ; // ime partition info
output [1-1:0] fimeif_mv_rden_o ; // imv read enable
output [6-1:0] fimeif_mv_rdaddr_o ; // imv sram read address
input [2*`FMV_WIDTH-1:0] fimeif_mv_data_i ; // imv from fime
output [1-1:0] mcif_mv_rden_o ; // half fmv write back enable
output [6-1:0] mcif_mv_rdaddr_o ; // half fmv write back address
input [2*`FMV_WIDTH-1:0] mcif_mv_data_i ; // half fmv
output [1-1:0] cur_rden_o ; // current lcu read enable
//output [1-1:0] cur_sel_o ; // use block read mode
//output [6-1:0] cur_idx_o ; // current block read index ( raster sacn)
output [5-1:0] cur_4x4_idx_o ;
output [4-1:0] cur_4x4_x_o ;
output [4-1:0] cur_4x4_y_o ;
input [32*`PIXEL_WIDTH-1:0] cur_pel_i ; // current block pixel
output [1-1:0] ref_rden_o ; // referenced pixel read enable
output [7-1:0] ref_idx_x_o ; // referenced pixel x index
output [7-1:0] ref_idx_y_o ; // referenced pixel y index
input [64*`PIXEL_WIDTH-1:0] ref_pel_i ; // referenced pixel
output mcif_mv_wren_o ; // fmv sram write enable
output [6-1:0] mcif_mv_wraddr_o ; // fmv sram write address
output [2*`FMV_WIDTH-1:0] mcif_mv_data_o ; // fmv data
output [32*`PIXEL_WIDTH-1 :0] mcif_pre_pixel_o ;
output [4-1 :0] mcif_pre_wren_o ;
output [7-1 :0] mcif_pre_addr_o ;
// ********************************************
//
// PARAMETER DECLARATION
//
// ********************************************
localparam SATD_WIDTH = `PIXEL_WIDTH + 10;
// ********************************************
//
// Combinational Logic
//
// ********************************************
// CTRL <-> IP IF
wire ip_start_ctrl ;
wire ip_half_ctrl ;
wire [`FMV_WIDTH-1 :0] ip_mv_x_ctrl ;
wire [`FMV_WIDTH-1 :0] ip_mv_y_ctrl ;
wire [2-1 :0] ip_frac_x_ctrl ;
wire [2-1 :0] ip_frac_y_ctrl ;
wire [6-1 :0] ip_idx_ctrl ;
// REF <-> IP IF
reg refpel_valid ;
wire [`PIXEL_WIDTH-1 :0] ref_pel0 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel1 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel2 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel3 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel4 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel5 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel6 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel7 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel8 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel9 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel10 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel11 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel12 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel13 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel14 ;
wire [`PIXEL_WIDTH-1 :0] ref_pel15 ;
/*
wire [64*`PIXEL_WIDTH-1:0] ref_pixels ;
reg [9-1 :0] ref_shift ;
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
ref_shift <= 'd0;
end
else begin
ref_shift <= {ip_idx_ctrl[4], ip_idx_ctrl[2], ip_idx_ctrl[0],6'b0};
end
end
assign ref_pixels = ref_pel_i << ref_shift;
*/
assign ref_pel0 = ref_pel_i[64*`PIXEL_WIDTH-1:63*`PIXEL_WIDTH];
assign ref_pel1 = ref_pel_i[63*`PIXEL_WIDTH-1:62*`PIXEL_WIDTH];
assign ref_pel2 = ref_pel_i[62*`PIXEL_WIDTH-1:61*`PIXEL_WIDTH];
assign ref_pel3 = ref_pel_i[61*`PIXEL_WIDTH-1:60*`PIXEL_WIDTH];
assign ref_pel4 = ref_pel_i[60*`PIXEL_WIDTH-1:59*`PIXEL_WIDTH];
assign ref_pel5 = ref_pel_i[59*`PIXEL_WIDTH-1:58*`PIXEL_WIDTH];
assign ref_pel6 = ref_pel_i[58*`PIXEL_WIDTH-1:57*`PIXEL_WIDTH];
assign ref_pel7 = ref_pel_i[57*`PIXEL_WIDTH-1:56*`PIXEL_WIDTH];
assign ref_pel8 = ref_pel_i[56*`PIXEL_WIDTH-1:55*`PIXEL_WIDTH];
assign ref_pel9 = ref_pel_i[55*`PIXEL_WIDTH-1:54*`PIXEL_WIDTH];
assign ref_pel10 = ref_pel_i[54*`PIXEL_WIDTH-1:53*`PIXEL_WIDTH];
assign ref_pel11 = ref_pel_i[53*`PIXEL_WIDTH-1:52*`PIXEL_WIDTH];
assign ref_pel12 = ref_pel_i[52*`PIXEL_WIDTH-1:51*`PIXEL_WIDTH];
assign ref_pel13 = ref_pel_i[51*`PIXEL_WIDTH-1:50*`PIXEL_WIDTH];
assign ref_pel14 = ref_pel_i[50*`PIXEL_WIDTH-1:49*`PIXEL_WIDTH];
assign ref_pel15 = ref_pel_i[49*`PIXEL_WIDTH-1:48*`PIXEL_WIDTH];
// IP <-> SATD IF
wire [`FMV_WIDTH-1 :0] mv_x_ip ;
wire [`FMV_WIDTH-1 :0] mv_y_ip ;
wire [6-1 :0] blk_idx_ip ;
wire half_ip_flag_ip ;
wire ip_ready ;
wire end_ip ;
wire mc_end_ip ;
wire satd_start ;
wire candi0_valid ;
wire candi1_valid ;
wire candi2_valid ;
wire candi3_valid ;
wire candi4_valid ;
wire candi5_valid ;
wire candi6_valid ;
wire candi7_valid ;
wire candi8_valid ;
wire [8*`PIXEL_WIDTH-1 :0] candi0_pixles ;
wire [8*`PIXEL_WIDTH-1 :0] candi1_pixles ;
wire [8*`PIXEL_WIDTH-1 :0] candi2_pixles ;
wire [8*`PIXEL_WIDTH-1 :0] candi3_pixles ;
wire [8*`PIXEL_WIDTH-1 :0] candi4_pixles ;
wire [8*`PIXEL_WIDTH-1 :0] candi5_pixles ;
wire [8*`PIXEL_WIDTH-1 :0] candi6_pixles ;
wire [8*`PIXEL_WIDTH-1 :0] candi7_pixles ;
wire [8*`PIXEL_WIDTH-1 :0] candi8_pixles ;
// SATD <-> COST
wire cost_start ;
wire [`FMV_WIDTH-1 :0] mv_x_satd ;
wire [`FMV_WIDTH-1 :0] mv_y_satd ;
wire half_ip_flag_satd;
wire [6-1 :0] blk_idx_satd ;
wire [SATD_WIDTH-1 :0] satd0 ;
wire [SATD_WIDTH-1 :0] satd1 ;
wire [SATD_WIDTH-1 :0] satd2 ;
wire [SATD_WIDTH-1 :0] satd3 ;
wire [SATD_WIDTH-1 :0] satd4 ;
wire [SATD_WIDTH-1 :0] satd5 ;
wire [SATD_WIDTH-1 :0] satd6 ;
wire [SATD_WIDTH-1 :0] satd7 ;
wire [SATD_WIDTH-1 :0] satd8 ;
wire satd_valid ;
// COST <-> CTRL IF
wire [3 :0] current_state ;
wire cost_done ;
wire [4-1 :0] best_sp ;
wire [6-1 :0] best_addr ;
wire best_valid ;
wire [2*`FMV_WIDTH-1 :0] fmv_best ;
wire fmv_wren ;
wire fmv_sel ;
wire [6-1 :0] fmv_addr ;
wire signed [`FMV_WIDTH-1:0] imv_x ;
wire signed [`FMV_WIDTH-1:0] imv_y ;
wire signed [`FMV_WIDTH-1:0] fmv_x ;
wire signed [`FMV_WIDTH-1:0] fmv_y ;
wire [1-1 :0] predicted_en ;
wire [4-1 :0] pred_wren ;
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
refpel_valid <= 1'b0;
end
else begin
refpel_valid <= ref_rden_o;
end
end
fme_interpolator_8x8 ip8x8(
.clk (clk ),
.rstn (rstn ),
// CTRL -> IP IF
.blk_start_i (ip_start_ctrl ),
.half_ip_flag_i (ip_half_ctrl ),
.mv_x_i (ip_mv_x_ctrl ),
.mv_y_i (ip_mv_y_ctrl ),
.frac_x_i (ip_frac_x_ctrl ),
.frac_y_i (ip_frac_y_ctrl ),
.blk_idx_i (ip_idx_ctrl ),
// REF -> IP IF
.refpel_valid_i (refpel_valid ),
.ref_pel0_i (ref_pel0 ),
.ref_pel1_i (ref_pel1 ),
.ref_pel2_i (ref_pel2 ),
.ref_pel3_i (ref_pel3 ),
.ref_pel4_i (ref_pel4 ),
.ref_pel5_i (ref_pel5 ),
.ref_pel6_i (ref_pel6 ),
.ref_pel7_i (ref_pel7 ),
.ref_pel8_i (ref_pel8 ),
.ref_pel9_i (ref_pel9 ),
.ref_pel10_i (ref_pel10 ),
.ref_pel11_i (ref_pel11 ),
.ref_pel12_i (ref_pel12 ),
.ref_pel13_i (ref_pel13 ),
.ref_pel14_i (ref_pel14 ),
.ref_pel15_i (ref_pel15 ),
// SATD <- IP IF
.mv_x_o (mv_x_ip ),
.mv_y_o (mv_y_ip ),
.blk_idx_o (blk_idx_ip ),
.half_ip_flag_o (half_ip_flag_ip),
.ip_ready_o (ip_ready ),
.end_ip_o (end_ip ),
.mc_end_ip_o (mc_end_ip ),
.satd_start_o (satd_start ),
.candi0_valid_o (candi0_valid ),
.candi1_valid_o (candi1_valid ),
.candi2_valid_o (candi2_valid ),
.candi3_valid_o (candi3_valid ),
.candi4_valid_o (candi4_valid ),
.candi5_valid_o (candi5_valid ),
.candi6_valid_o (candi6_valid ),
.candi7_valid_o (candi7_valid ),
.candi8_valid_o (candi8_valid ),
.candi0_pixles_o (candi0_pixles ),
.candi1_pixles_o (candi1_pixles ),
.candi2_pixles_o (candi2_pixles ),
.candi3_pixles_o (candi3_pixles ),
.candi4_pixles_o (candi4_pixles ),
.candi5_pixles_o (candi5_pixles ),
.candi6_pixles_o (candi6_pixles ),
.candi7_pixles_o (candi7_pixles ),
.candi8_pixles_o (candi8_pixles )
);
fme_satd_gen satd_gen(
.clk (clk ),
.rstn (rstn ),
// IP -> SATD IF
.satd_start_i (satd_start ),
.blk_idx_i (blk_idx_ip ),
.mv_x_i (mv_x_ip ),
.mv_y_i (mv_y_ip ),
.half_ip_flag_i (half_ip_flag_ip),
.ip_ready_i (ip_ready ),
.end_ip_i (end_ip ),
.candi0_valid_i (candi0_valid ),
.candi1_valid_i (candi1_valid ),
.candi2_valid_i (candi2_valid ),
.candi3_valid_i (candi3_valid ),
.candi4_valid_i (candi4_valid ),
.candi5_valid_i (candi5_valid ),
.candi6_valid_i (candi6_valid ),
.candi7_valid_i (candi7_valid ),
.candi8_valid_i (candi8_valid ),
.candi0_pixles_i (candi0_pixles ),
.candi1_pixles_i (candi1_pixles ),
.candi2_pixles_i (candi2_pixles ),
.candi3_pixles_i (candi3_pixles ),
.candi4_pixles_i (candi4_pixles ),
.candi5_pixles_i (candi5_pixles ),
.candi6_pixles_i (candi6_pixles ),
.candi7_pixles_i (candi7_pixles ),
.candi8_pixles_i (candi8_pixles ),
// CUR <-> SATD IF
.cur_rden_o (cur_rden_o ),
//.cur_sel_o (cur_sel_o ),
//.cur_idx_o (cur_idx_o ),
.cur_4x4_x_o (cur_4x4_x_o ),
.cur_4x4_y_o (cur_4x4_y_o ),
.cur_4x4_idx_o (cur_4x4_idx_o ),
.cur_pel_i (cur_pel_i ),
// COST <- SATD IF
.cost_start_o (cost_start ),
.mv_x_o (mv_x_satd ),
.mv_y_o (mv_y_satd ),
.half_ip_flag_o (half_ip_flag_satd ),
.blk_idx_o (blk_idx_satd ),
.satd0_o (satd0 ),
.satd1_o (satd1 ),
.satd2_o (satd2 ),
.satd3_o (satd3 ),
.satd4_o (satd4 ),
.satd5_o (satd5 ),
.satd6_o (satd6 ),
.satd7_o (satd7 ),
.satd8_o (satd8 ),
.satd_valid_o (satd_valid )
);
fme_cost sp_cost(
.clk (clk ),
.rstn (rstn ),
// SYS IF
.qp_i (sysif_qp_i ),
.partition_i (fimeif_partition_i ),
// SATD -> COST IF
.cost_start_i (cost_start ),
.mv_x_i (mv_x_satd ),
.mv_y_i (mv_y_satd ),
.blk_idx_i (blk_idx_satd ),
.half_ip_flag_i (half_ip_flag_satd ),
.satd0_i (satd0 ),
.satd1_i (satd1 ),
.satd2_i (satd2 ),
.satd3_i (satd3 ),
.satd4_i (satd4 ),
.satd5_i (satd5 ),
.satd6_i (satd6 ),
.satd7_i (satd7 ),
.satd8_i (satd8 ),
.satd_valid_i (satd_valid ),
// CTRL <- COST IF
.cost_done_o (cost_done ),
.best_sp_o (best_sp ),
// MC <- COST IF
.fmv_best_o (fmv_best ),
.fmv_wren_o (fmv_wren ),
.fmv_sel_o (fmv_sel ),
.fmv_addr_o (fmv_addr )
);
fme_ctrl ctrl(
.clk (clk ),
.rstn (rstn ),
// SYS IF
.sysif_start_i (sysif_start_i ),
.sysif_done_o (sysif_done_o ),
// STATE
.current_state (current_state ),
// FIME <-> CTRL IF
.fimeif_partition_i (fimeif_partition_i ),
.fimeif_mv_rden_o (fimeif_mv_rden_o ),
.fimeif_mv_rdaddr_o (fimeif_mv_rdaddr_o ),
.fimeif_mv_data_i (fimeif_mv_data_i ),
// MC <-> CTRL IF
.mcif_mv_rden_o (mcif_mv_rden_o ),
.mcif_mv_rdaddr_o (mcif_mv_rdaddr_o ),
.mcif_mv_data_i (mcif_mv_data_i ),
// REF <- CTRL IF
.ref_rden_o (ref_rden_o ),
.ref_idx_x_o (ref_idx_x_o ),
.ref_idx_y_o (ref_idx_y_o ),
// IP <-> CTRL IF
.ip_start_o (ip_start_ctrl ),
.ip_done_i (mc_end_ip ),
.ip_mv_x_o (ip_mv_x_ctrl ),
.ip_mv_y_o (ip_mv_y_ctrl ),
.ip_frac_x_o (ip_frac_x_ctrl ),
.ip_frac_y_o (ip_frac_y_ctrl ),
.ip_half_flag_o (ip_half_ctrl ),
.ip_idx_o (ip_idx_ctrl ),
// COST -> CTRL IF
.cost_done_i (cost_done ),
.predicted_en_o (predicted_en )
);
fme_pred fme_pred (
.clk (clk ),
.rstn (rstn ),
.ip_start_i (ip_start_ctrl ),
.end_ip_i (end_ip ),
.imv_x_i (imv_x ),
.imv_y_i (imv_y ),
.fmv_x_i (fmv_x ),
.fmv_y_i (fmv_y ),
.block_idx_i (ip_idx_ctrl ),
.candi0_valid_i (candi0_valid ),
.candi1_valid_i (candi1_valid ),
.candi2_valid_i (candi2_valid ),
.candi3_valid_i (candi3_valid ),
.candi4_valid_i (candi4_valid ),
.candi5_valid_i (candi5_valid ),
.candi6_valid_i (candi6_valid ),
.candi7_valid_i (candi7_valid ),
.candi8_valid_i (candi8_valid ),
.candi0_pixles_i (candi0_pixles ),
.candi1_pixles_i (candi1_pixles ),
.candi2_pixles_i (candi2_pixles ),
.candi3_pixles_i (candi3_pixles ),
.candi4_pixles_i (candi4_pixles ),
.candi5_pixles_i (candi5_pixles ),
.candi6_pixles_i (candi6_pixles ),
.candi7_pixles_i (candi7_pixles ),
.candi8_pixles_i (candi8_pixles ),
.pred_pixel_o (mcif_pre_pixel_o ),
.pred_wren_o (pred_wren ),
.pred_addr_o (mcif_pre_addr_o )
);
assign mcif_pre_wren_o = pred_wren & {predicted_en, predicted_en, predicted_en, predicted_en};
assign mcif_mv_wren_o = fmv_wren && ( (current_state>=1)&(current_state<=6) ); // the third round, do not need to override mv buffer
assign mcif_mv_wraddr_o = fmv_addr;
assign mcif_mv_data_o = fmv_best;
assign imv_x = fimeif_mv_data_i[2*`FMV_WIDTH-1 : `FMV_WIDTH];
assign imv_y = fimeif_mv_data_i[`FMV_WIDTH-1 : 0];
assign fmv_x = mcif_mv_data_i [2*`FMV_WIDTH-1 : `FMV_WIDTH];
assign fmv_y = mcif_mv_data_i [`FMV_WIDTH-1 : 0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_BLACKBOX_V
`define SKY130_FD_SC_MS__O31AI_BLACKBOX_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o31ai (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_BEHAVIORAL_V
`define SKY130_FD_SC_MS__FILL_DIODE_BEHAVIORAL_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__fill_diode ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_BEHAVIORAL_V |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_sort_sector (
ap_clk,
ap_rst,
ph_rank_0_0_V_read,
ph_rank_0_1_V_read,
ph_rank_0_2_V_read,
ph_rank_0_3_V_read,
ph_rank_0_4_V_read,
ph_rank_0_5_V_read,
ph_rank_0_6_V_read,
ph_rank_0_7_V_read,
ph_rank_0_8_V_read,
ph_rank_0_9_V_read,
ph_rank_0_10_V_read,
ph_rank_0_11_V_read,
ph_rank_0_12_V_read,
ph_rank_0_13_V_read,
ph_rank_0_14_V_read,
ph_rank_0_15_V_read,
ph_rank_0_16_V_read,
ph_rank_0_17_V_read,
ph_rank_0_18_V_read,
ph_rank_0_19_V_read,
ph_rank_0_20_V_read,
ph_rank_0_21_V_read,
ph_rank_0_22_V_read,
ph_rank_0_23_V_read,
ph_rank_0_24_V_read,
ph_rank_0_25_V_read,
ph_rank_0_26_V_read,
ph_rank_0_27_V_read,
ph_rank_0_28_V_read,
ph_rank_0_29_V_read,
ph_rank_0_30_V_read,
ph_rank_0_31_V_read,
ph_rank_0_32_V_read,
ph_rank_0_33_V_read,
ph_rank_0_34_V_read,
ph_rank_0_35_V_read,
ph_rank_0_36_V_read,
ph_rank_0_37_V_read,
ph_rank_0_38_V_read,
ph_rank_0_39_V_read,
ph_rank_0_40_V_read,
ph_rank_0_41_V_read,
ph_rank_0_42_V_read,
ph_rank_0_43_V_read,
ph_rank_0_44_V_read,
ph_rank_0_45_V_read,
ph_rank_0_46_V_read,
ph_rank_0_47_V_read,
ph_rank_0_48_V_read,
ph_rank_0_49_V_read,
ph_rank_0_50_V_read,
ph_rank_0_51_V_read,
ph_rank_0_52_V_read,
ph_rank_0_53_V_read,
ph_rank_0_54_V_read,
ph_rank_0_55_V_read,
ph_rank_0_56_V_read,
ph_rank_0_57_V_read,
ph_rank_0_58_V_read,
ph_rank_0_59_V_read,
ph_rank_0_60_V_read,
ph_rank_0_61_V_read,
ph_rank_0_62_V_read,
ph_rank_0_63_V_read,
ph_rank_0_64_V_read,
ph_rank_0_65_V_read,
ph_rank_0_66_V_read,
ph_rank_0_67_V_read,
ph_rank_0_68_V_read,
ph_rank_0_69_V_read,
ph_rank_0_70_V_read,
ph_rank_0_71_V_read,
ph_rank_0_72_V_read,
ph_rank_0_73_V_read,
ph_rank_0_74_V_read,
ph_rank_0_75_V_read,
ph_rank_0_76_V_read,
ph_rank_0_77_V_read,
ph_rank_0_78_V_read,
ph_rank_0_79_V_read,
ph_rank_0_80_V_read,
ph_rank_0_81_V_read,
ph_rank_0_82_V_read,
ph_rank_0_83_V_read,
ph_rank_0_84_V_read,
ph_rank_0_85_V_read,
ph_rank_0_86_V_read,
ph_rank_0_87_V_read,
ph_rank_0_88_V_read,
ph_rank_0_89_V_read,
ph_rank_0_90_V_read,
ph_rank_0_91_V_read,
ph_rank_0_92_V_read,
ph_rank_0_93_V_read,
ph_rank_0_94_V_read,
ph_rank_0_95_V_read,
ph_rank_0_96_V_read,
ph_rank_0_97_V_read,
ph_rank_0_98_V_read,
ph_rank_0_99_V_read,
ph_rank_0_100_V_read,
ph_rank_0_101_V_read,
ph_rank_0_102_V_read,
ph_rank_0_103_V_read,
ph_rank_0_104_V_read,
ph_rank_0_105_V_read,
ph_rank_0_106_V_read,
ph_rank_0_107_V_read,
ph_rank_0_108_V_read,
ph_rank_0_109_V_read,
ph_rank_0_110_V_read,
ph_rank_0_111_V_read,
ph_rank_0_112_V_read,
ph_rank_0_113_V_read,
ph_rank_0_114_V_read,
ph_rank_0_115_V_read,
ph_rank_0_116_V_read,
ph_rank_0_117_V_read,
ph_rank_0_118_V_read,
ph_rank_0_119_V_read,
ph_rank_0_120_V_read,
ph_rank_0_121_V_read,
ph_rank_1_0_V_read,
ph_rank_1_1_V_read,
ph_rank_1_2_V_read,
ph_rank_1_3_V_read,
ph_rank_1_4_V_read,
ph_rank_1_5_V_read,
ph_rank_1_6_V_read,
ph_rank_1_7_V_read,
ph_rank_1_8_V_read,
ph_rank_1_9_V_read,
ph_rank_1_10_V_read,
ph_rank_1_11_V_read,
ph_rank_1_12_V_read,
ph_rank_1_13_V_read,
ph_rank_1_14_V_read,
ph_rank_1_15_V_read,
ph_rank_1_16_V_read,
ph_rank_1_17_V_read,
ph_rank_1_18_V_read,
ph_rank_1_19_V_read,
ph_rank_1_20_V_read,
ph_rank_1_21_V_read,
ph_rank_1_22_V_read,
ph_rank_1_23_V_read,
ph_rank_1_24_V_read,
ph_rank_1_25_V_read,
ph_rank_1_26_V_read,
ph_rank_1_27_V_read,
ph_rank_1_28_V_read,
ph_rank_1_29_V_read,
ph_rank_1_30_V_read,
ph_rank_1_31_V_read,
ph_rank_1_32_V_read,
ph_rank_1_33_V_read,
ph_rank_1_34_V_read,
ph_rank_1_35_V_read,
ph_rank_1_36_V_read,
ph_rank_1_37_V_read,
ph_rank_1_38_V_read,
ph_rank_1_39_V_read,
ph_rank_1_40_V_read,
ph_rank_1_41_V_read,
ph_rank_1_42_V_read,
ph_rank_1_43_V_read,
ph_rank_1_44_V_read,
ph_rank_1_45_V_read,
ph_rank_1_46_V_read,
ph_rank_1_47_V_read,
ph_rank_1_48_V_read,
ph_rank_1_49_V_read,
ph_rank_1_50_V_read,
ph_rank_1_51_V_read,
ph_rank_1_52_V_read,
ph_rank_1_53_V_read,
ph_rank_1_54_V_read,
ph_rank_1_55_V_read,
ph_rank_1_56_V_read,
ph_rank_1_57_V_read,
ph_rank_1_58_V_read,
ph_rank_1_59_V_read,
ph_rank_1_60_V_read,
ph_rank_1_61_V_read,
ph_rank_1_62_V_read,
ph_rank_1_63_V_read,
ph_rank_1_64_V_read,
ph_rank_1_65_V_read,
ph_rank_1_66_V_read,
ph_rank_1_67_V_read,
ph_rank_1_68_V_read,
ph_rank_1_69_V_read,
ph_rank_1_70_V_read,
ph_rank_1_71_V_read,
ph_rank_1_72_V_read,
ph_rank_1_73_V_read,
ph_rank_1_74_V_read,
ph_rank_1_75_V_read,
ph_rank_1_76_V_read,
ph_rank_1_77_V_read,
ph_rank_1_78_V_read,
ph_rank_1_79_V_read,
ph_rank_1_80_V_read,
ph_rank_1_81_V_read,
ph_rank_1_82_V_read,
ph_rank_1_83_V_read,
ph_rank_1_84_V_read,
ph_rank_1_85_V_read,
ph_rank_1_86_V_read,
ph_rank_1_87_V_read,
ph_rank_1_88_V_read,
ph_rank_1_89_V_read,
ph_rank_1_90_V_read,
ph_rank_1_91_V_read,
ph_rank_1_92_V_read,
ph_rank_1_93_V_read,
ph_rank_1_94_V_read,
ph_rank_1_95_V_read,
ph_rank_1_96_V_read,
ph_rank_1_97_V_read,
ph_rank_1_98_V_read,
ph_rank_1_99_V_read,
ph_rank_1_100_V_read,
ph_rank_1_101_V_read,
ph_rank_1_102_V_read,
ph_rank_1_103_V_read,
ph_rank_1_104_V_read,
ph_rank_1_105_V_read,
ph_rank_1_106_V_read,
ph_rank_1_107_V_read,
ph_rank_1_108_V_read,
ph_rank_1_109_V_read,
ph_rank_1_110_V_read,
ph_rank_1_111_V_read,
ph_rank_1_112_V_read,
ph_rank_1_113_V_read,
ph_rank_1_114_V_read,
ph_rank_1_115_V_read,
ph_rank_1_116_V_read,
ph_rank_1_117_V_read,
ph_rank_1_118_V_read,
ph_rank_1_119_V_read,
ph_rank_1_120_V_read,
ph_rank_1_121_V_read,
ph_rank_2_0_V_read,
ph_rank_2_1_V_read,
ph_rank_2_2_V_read,
ph_rank_2_3_V_read,
ph_rank_2_4_V_read,
ph_rank_2_5_V_read,
ph_rank_2_6_V_read,
ph_rank_2_7_V_read,
ph_rank_2_8_V_read,
ph_rank_2_9_V_read,
ph_rank_2_10_V_read,
ph_rank_2_11_V_read,
ph_rank_2_12_V_read,
ph_rank_2_13_V_read,
ph_rank_2_14_V_read,
ph_rank_2_15_V_read,
ph_rank_2_16_V_read,
ph_rank_2_17_V_read,
ph_rank_2_18_V_read,
ph_rank_2_19_V_read,
ph_rank_2_20_V_read,
ph_rank_2_21_V_read,
ph_rank_2_22_V_read,
ph_rank_2_23_V_read,
ph_rank_2_24_V_read,
ph_rank_2_25_V_read,
ph_rank_2_26_V_read,
ph_rank_2_27_V_read,
ph_rank_2_28_V_read,
ph_rank_2_29_V_read,
ph_rank_2_30_V_read,
ph_rank_2_31_V_read,
ph_rank_2_32_V_read,
ph_rank_2_33_V_read,
ph_rank_2_34_V_read,
ph_rank_2_35_V_read,
ph_rank_2_36_V_read,
ph_rank_2_37_V_read,
ph_rank_2_38_V_read,
ph_rank_2_39_V_read,
ph_rank_2_40_V_read,
ph_rank_2_41_V_read,
ph_rank_2_42_V_read,
ph_rank_2_43_V_read,
ph_rank_2_44_V_read,
ph_rank_2_45_V_read,
ph_rank_2_46_V_read,
ph_rank_2_47_V_read,
ph_rank_2_48_V_read,
ph_rank_2_49_V_read,
ph_rank_2_50_V_read,
ph_rank_2_51_V_read,
ph_rank_2_52_V_read,
ph_rank_2_53_V_read,
ph_rank_2_54_V_read,
ph_rank_2_55_V_read,
ph_rank_2_56_V_read,
ph_rank_2_57_V_read,
ph_rank_2_58_V_read,
ph_rank_2_59_V_read,
ph_rank_2_60_V_read,
ph_rank_2_61_V_read,
ph_rank_2_62_V_read,
ph_rank_2_63_V_read,
ph_rank_2_64_V_read,
ph_rank_2_65_V_read,
ph_rank_2_66_V_read,
ph_rank_2_67_V_read,
ph_rank_2_68_V_read,
ph_rank_2_69_V_read,
ph_rank_2_70_V_read,
ph_rank_2_71_V_read,
ph_rank_2_72_V_read,
ph_rank_2_73_V_read,
ph_rank_2_74_V_read,
ph_rank_2_75_V_read,
ph_rank_2_76_V_read,
ph_rank_2_77_V_read,
ph_rank_2_78_V_read,
ph_rank_2_79_V_read,
ph_rank_2_80_V_read,
ph_rank_2_81_V_read,
ph_rank_2_82_V_read,
ph_rank_2_83_V_read,
ph_rank_2_84_V_read,
ph_rank_2_85_V_read,
ph_rank_2_86_V_read,
ph_rank_2_87_V_read,
ph_rank_2_88_V_read,
ph_rank_2_89_V_read,
ph_rank_2_90_V_read,
ph_rank_2_91_V_read,
ph_rank_2_92_V_read,
ph_rank_2_93_V_read,
ph_rank_2_94_V_read,
ph_rank_2_95_V_read,
ph_rank_2_96_V_read,
ph_rank_2_97_V_read,
ph_rank_2_98_V_read,
ph_rank_2_99_V_read,
ph_rank_2_100_V_read,
ph_rank_2_101_V_read,
ph_rank_2_102_V_read,
ph_rank_2_103_V_read,
ph_rank_2_104_V_read,
ph_rank_2_105_V_read,
ph_rank_2_106_V_read,
ph_rank_2_107_V_read,
ph_rank_2_108_V_read,
ph_rank_2_109_V_read,
ph_rank_2_110_V_read,
ph_rank_2_111_V_read,
ph_rank_2_112_V_read,
ph_rank_2_113_V_read,
ph_rank_2_114_V_read,
ph_rank_2_115_V_read,
ph_rank_2_116_V_read,
ph_rank_2_117_V_read,
ph_rank_2_118_V_read,
ph_rank_2_119_V_read,
ph_rank_2_120_V_read,
ph_rank_2_121_V_read,
ph_rank_3_0_V_read,
ph_rank_3_1_V_read,
ph_rank_3_2_V_read,
ph_rank_3_3_V_read,
ph_rank_3_4_V_read,
ph_rank_3_5_V_read,
ph_rank_3_6_V_read,
ph_rank_3_7_V_read,
ph_rank_3_8_V_read,
ph_rank_3_9_V_read,
ph_rank_3_10_V_read,
ph_rank_3_11_V_read,
ph_rank_3_12_V_read,
ph_rank_3_13_V_read,
ph_rank_3_14_V_read,
ph_rank_3_15_V_read,
ph_rank_3_16_V_read,
ph_rank_3_17_V_read,
ph_rank_3_18_V_read,
ph_rank_3_19_V_read,
ph_rank_3_20_V_read,
ph_rank_3_21_V_read,
ph_rank_3_22_V_read,
ph_rank_3_23_V_read,
ph_rank_3_24_V_read,
ph_rank_3_25_V_read,
ph_rank_3_26_V_read,
ph_rank_3_27_V_read,
ph_rank_3_28_V_read,
ph_rank_3_29_V_read,
ph_rank_3_30_V_read,
ph_rank_3_31_V_read,
ph_rank_3_32_V_read,
ph_rank_3_33_V_read,
ph_rank_3_34_V_read,
ph_rank_3_35_V_read,
ph_rank_3_36_V_read,
ph_rank_3_37_V_read,
ph_rank_3_38_V_read,
ph_rank_3_39_V_read,
ph_rank_3_40_V_read,
ph_rank_3_41_V_read,
ph_rank_3_42_V_read,
ph_rank_3_43_V_read,
ph_rank_3_44_V_read,
ph_rank_3_45_V_read,
ph_rank_3_46_V_read,
ph_rank_3_47_V_read,
ph_rank_3_48_V_read,
ph_rank_3_49_V_read,
ph_rank_3_50_V_read,
ph_rank_3_51_V_read,
ph_rank_3_52_V_read,
ph_rank_3_53_V_read,
ph_rank_3_54_V_read,
ph_rank_3_55_V_read,
ph_rank_3_56_V_read,
ph_rank_3_57_V_read,
ph_rank_3_58_V_read,
ph_rank_3_59_V_read,
ph_rank_3_60_V_read,
ph_rank_3_61_V_read,
ph_rank_3_62_V_read,
ph_rank_3_63_V_read,
ph_rank_3_64_V_read,
ph_rank_3_65_V_read,
ph_rank_3_66_V_read,
ph_rank_3_67_V_read,
ph_rank_3_68_V_read,
ph_rank_3_69_V_read,
ph_rank_3_70_V_read,
ph_rank_3_71_V_read,
ph_rank_3_72_V_read,
ph_rank_3_73_V_read,
ph_rank_3_74_V_read,
ph_rank_3_75_V_read,
ph_rank_3_76_V_read,
ph_rank_3_77_V_read,
ph_rank_3_78_V_read,
ph_rank_3_79_V_read,
ph_rank_3_80_V_read,
ph_rank_3_81_V_read,
ph_rank_3_82_V_read,
ph_rank_3_83_V_read,
ph_rank_3_84_V_read,
ph_rank_3_85_V_read,
ph_rank_3_86_V_read,
ph_rank_3_87_V_read,
ph_rank_3_88_V_read,
ph_rank_3_89_V_read,
ph_rank_3_90_V_read,
ph_rank_3_91_V_read,
ph_rank_3_92_V_read,
ph_rank_3_93_V_read,
ph_rank_3_94_V_read,
ph_rank_3_95_V_read,
ph_rank_3_96_V_read,
ph_rank_3_97_V_read,
ph_rank_3_98_V_read,
ph_rank_3_99_V_read,
ph_rank_3_100_V_read,
ph_rank_3_101_V_read,
ph_rank_3_102_V_read,
ph_rank_3_103_V_read,
ph_rank_3_104_V_read,
ph_rank_3_105_V_read,
ph_rank_3_106_V_read,
ph_rank_3_107_V_read,
ph_rank_3_108_V_read,
ph_rank_3_109_V_read,
ph_rank_3_110_V_read,
ph_rank_3_111_V_read,
ph_rank_3_112_V_read,
ph_rank_3_113_V_read,
ph_rank_3_114_V_read,
ph_rank_3_115_V_read,
ph_rank_3_116_V_read,
ph_rank_3_117_V_read,
ph_rank_3_118_V_read,
ph_rank_3_119_V_read,
ph_rank_3_120_V_read,
ph_rank_3_121_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3,
ap_return_4,
ap_return_5,
ap_return_6,
ap_return_7,
ap_return_8,
ap_return_9,
ap_return_10,
ap_return_11,
ap_return_12,
ap_return_13,
ap_return_14,
ap_return_15,
ap_return_16,
ap_return_17,
ap_return_18,
ap_return_19,
ap_return_20,
ap_return_21,
ap_return_22,
ap_return_23
);
input ap_clk;
input ap_rst;
input [5:0] ph_rank_0_0_V_read;
input [5:0] ph_rank_0_1_V_read;
input [5:0] ph_rank_0_2_V_read;
input [5:0] ph_rank_0_3_V_read;
input [5:0] ph_rank_0_4_V_read;
input [5:0] ph_rank_0_5_V_read;
input [5:0] ph_rank_0_6_V_read;
input [5:0] ph_rank_0_7_V_read;
input [5:0] ph_rank_0_8_V_read;
input [5:0] ph_rank_0_9_V_read;
input [5:0] ph_rank_0_10_V_read;
input [5:0] ph_rank_0_11_V_read;
input [5:0] ph_rank_0_12_V_read;
input [5:0] ph_rank_0_13_V_read;
input [5:0] ph_rank_0_14_V_read;
input [5:0] ph_rank_0_15_V_read;
input [5:0] ph_rank_0_16_V_read;
input [5:0] ph_rank_0_17_V_read;
input [5:0] ph_rank_0_18_V_read;
input [5:0] ph_rank_0_19_V_read;
input [5:0] ph_rank_0_20_V_read;
input [5:0] ph_rank_0_21_V_read;
input [5:0] ph_rank_0_22_V_read;
input [5:0] ph_rank_0_23_V_read;
input [5:0] ph_rank_0_24_V_read;
input [5:0] ph_rank_0_25_V_read;
input [5:0] ph_rank_0_26_V_read;
input [5:0] ph_rank_0_27_V_read;
input [5:0] ph_rank_0_28_V_read;
input [5:0] ph_rank_0_29_V_read;
input [5:0] ph_rank_0_30_V_read;
input [5:0] ph_rank_0_31_V_read;
input [5:0] ph_rank_0_32_V_read;
input [5:0] ph_rank_0_33_V_read;
input [5:0] ph_rank_0_34_V_read;
input [5:0] ph_rank_0_35_V_read;
input [5:0] ph_rank_0_36_V_read;
input [5:0] ph_rank_0_37_V_read;
input [5:0] ph_rank_0_38_V_read;
input [5:0] ph_rank_0_39_V_read;
input [5:0] ph_rank_0_40_V_read;
input [5:0] ph_rank_0_41_V_read;
input [5:0] ph_rank_0_42_V_read;
input [5:0] ph_rank_0_43_V_read;
input [5:0] ph_rank_0_44_V_read;
input [5:0] ph_rank_0_45_V_read;
input [5:0] ph_rank_0_46_V_read;
input [5:0] ph_rank_0_47_V_read;
input [5:0] ph_rank_0_48_V_read;
input [5:0] ph_rank_0_49_V_read;
input [5:0] ph_rank_0_50_V_read;
input [5:0] ph_rank_0_51_V_read;
input [5:0] ph_rank_0_52_V_read;
input [5:0] ph_rank_0_53_V_read;
input [5:0] ph_rank_0_54_V_read;
input [5:0] ph_rank_0_55_V_read;
input [5:0] ph_rank_0_56_V_read;
input [5:0] ph_rank_0_57_V_read;
input [5:0] ph_rank_0_58_V_read;
input [5:0] ph_rank_0_59_V_read;
input [5:0] ph_rank_0_60_V_read;
input [5:0] ph_rank_0_61_V_read;
input [5:0] ph_rank_0_62_V_read;
input [5:0] ph_rank_0_63_V_read;
input [5:0] ph_rank_0_64_V_read;
input [5:0] ph_rank_0_65_V_read;
input [5:0] ph_rank_0_66_V_read;
input [5:0] ph_rank_0_67_V_read;
input [5:0] ph_rank_0_68_V_read;
input [5:0] ph_rank_0_69_V_read;
input [5:0] ph_rank_0_70_V_read;
input [5:0] ph_rank_0_71_V_read;
input [5:0] ph_rank_0_72_V_read;
input [5:0] ph_rank_0_73_V_read;
input [5:0] ph_rank_0_74_V_read;
input [5:0] ph_rank_0_75_V_read;
input [5:0] ph_rank_0_76_V_read;
input [5:0] ph_rank_0_77_V_read;
input [5:0] ph_rank_0_78_V_read;
input [5:0] ph_rank_0_79_V_read;
input [5:0] ph_rank_0_80_V_read;
input [5:0] ph_rank_0_81_V_read;
input [5:0] ph_rank_0_82_V_read;
input [5:0] ph_rank_0_83_V_read;
input [5:0] ph_rank_0_84_V_read;
input [5:0] ph_rank_0_85_V_read;
input [5:0] ph_rank_0_86_V_read;
input [5:0] ph_rank_0_87_V_read;
input [5:0] ph_rank_0_88_V_read;
input [5:0] ph_rank_0_89_V_read;
input [5:0] ph_rank_0_90_V_read;
input [5:0] ph_rank_0_91_V_read;
input [5:0] ph_rank_0_92_V_read;
input [5:0] ph_rank_0_93_V_read;
input [5:0] ph_rank_0_94_V_read;
input [5:0] ph_rank_0_95_V_read;
input [5:0] ph_rank_0_96_V_read;
input [5:0] ph_rank_0_97_V_read;
input [5:0] ph_rank_0_98_V_read;
input [5:0] ph_rank_0_99_V_read;
input [5:0] ph_rank_0_100_V_read;
input [5:0] ph_rank_0_101_V_read;
input [5:0] ph_rank_0_102_V_read;
input [5:0] ph_rank_0_103_V_read;
input [5:0] ph_rank_0_104_V_read;
input [5:0] ph_rank_0_105_V_read;
input [5:0] ph_rank_0_106_V_read;
input [5:0] ph_rank_0_107_V_read;
input [5:0] ph_rank_0_108_V_read;
input [5:0] ph_rank_0_109_V_read;
input [5:0] ph_rank_0_110_V_read;
input [5:0] ph_rank_0_111_V_read;
input [5:0] ph_rank_0_112_V_read;
input [5:0] ph_rank_0_113_V_read;
input [5:0] ph_rank_0_114_V_read;
input [5:0] ph_rank_0_115_V_read;
input [5:0] ph_rank_0_116_V_read;
input [5:0] ph_rank_0_117_V_read;
input [5:0] ph_rank_0_118_V_read;
input [5:0] ph_rank_0_119_V_read;
input [5:0] ph_rank_0_120_V_read;
input [5:0] ph_rank_0_121_V_read;
input [5:0] ph_rank_1_0_V_read;
input [5:0] ph_rank_1_1_V_read;
input [5:0] ph_rank_1_2_V_read;
input [5:0] ph_rank_1_3_V_read;
input [5:0] ph_rank_1_4_V_read;
input [5:0] ph_rank_1_5_V_read;
input [5:0] ph_rank_1_6_V_read;
input [5:0] ph_rank_1_7_V_read;
input [5:0] ph_rank_1_8_V_read;
input [5:0] ph_rank_1_9_V_read;
input [5:0] ph_rank_1_10_V_read;
input [5:0] ph_rank_1_11_V_read;
input [5:0] ph_rank_1_12_V_read;
input [5:0] ph_rank_1_13_V_read;
input [5:0] ph_rank_1_14_V_read;
input [5:0] ph_rank_1_15_V_read;
input [5:0] ph_rank_1_16_V_read;
input [5:0] ph_rank_1_17_V_read;
input [5:0] ph_rank_1_18_V_read;
input [5:0] ph_rank_1_19_V_read;
input [5:0] ph_rank_1_20_V_read;
input [5:0] ph_rank_1_21_V_read;
input [5:0] ph_rank_1_22_V_read;
input [5:0] ph_rank_1_23_V_read;
input [5:0] ph_rank_1_24_V_read;
input [5:0] ph_rank_1_25_V_read;
input [5:0] ph_rank_1_26_V_read;
input [5:0] ph_rank_1_27_V_read;
input [5:0] ph_rank_1_28_V_read;
input [5:0] ph_rank_1_29_V_read;
input [5:0] ph_rank_1_30_V_read;
input [5:0] ph_rank_1_31_V_read;
input [5:0] ph_rank_1_32_V_read;
input [5:0] ph_rank_1_33_V_read;
input [5:0] ph_rank_1_34_V_read;
input [5:0] ph_rank_1_35_V_read;
input [5:0] ph_rank_1_36_V_read;
input [5:0] ph_rank_1_37_V_read;
input [5:0] ph_rank_1_38_V_read;
input [5:0] ph_rank_1_39_V_read;
input [5:0] ph_rank_1_40_V_read;
input [5:0] ph_rank_1_41_V_read;
input [5:0] ph_rank_1_42_V_read;
input [5:0] ph_rank_1_43_V_read;
input [5:0] ph_rank_1_44_V_read;
input [5:0] ph_rank_1_45_V_read;
input [5:0] ph_rank_1_46_V_read;
input [5:0] ph_rank_1_47_V_read;
input [5:0] ph_rank_1_48_V_read;
input [5:0] ph_rank_1_49_V_read;
input [5:0] ph_rank_1_50_V_read;
input [5:0] ph_rank_1_51_V_read;
input [5:0] ph_rank_1_52_V_read;
input [5:0] ph_rank_1_53_V_read;
input [5:0] ph_rank_1_54_V_read;
input [5:0] ph_rank_1_55_V_read;
input [5:0] ph_rank_1_56_V_read;
input [5:0] ph_rank_1_57_V_read;
input [5:0] ph_rank_1_58_V_read;
input [5:0] ph_rank_1_59_V_read;
input [5:0] ph_rank_1_60_V_read;
input [5:0] ph_rank_1_61_V_read;
input [5:0] ph_rank_1_62_V_read;
input [5:0] ph_rank_1_63_V_read;
input [5:0] ph_rank_1_64_V_read;
input [5:0] ph_rank_1_65_V_read;
input [5:0] ph_rank_1_66_V_read;
input [5:0] ph_rank_1_67_V_read;
input [5:0] ph_rank_1_68_V_read;
input [5:0] ph_rank_1_69_V_read;
input [5:0] ph_rank_1_70_V_read;
input [5:0] ph_rank_1_71_V_read;
input [5:0] ph_rank_1_72_V_read;
input [5:0] ph_rank_1_73_V_read;
input [5:0] ph_rank_1_74_V_read;
input [5:0] ph_rank_1_75_V_read;
input [5:0] ph_rank_1_76_V_read;
input [5:0] ph_rank_1_77_V_read;
input [5:0] ph_rank_1_78_V_read;
input [5:0] ph_rank_1_79_V_read;
input [5:0] ph_rank_1_80_V_read;
input [5:0] ph_rank_1_81_V_read;
input [5:0] ph_rank_1_82_V_read;
input [5:0] ph_rank_1_83_V_read;
input [5:0] ph_rank_1_84_V_read;
input [5:0] ph_rank_1_85_V_read;
input [5:0] ph_rank_1_86_V_read;
input [5:0] ph_rank_1_87_V_read;
input [5:0] ph_rank_1_88_V_read;
input [5:0] ph_rank_1_89_V_read;
input [5:0] ph_rank_1_90_V_read;
input [5:0] ph_rank_1_91_V_read;
input [5:0] ph_rank_1_92_V_read;
input [5:0] ph_rank_1_93_V_read;
input [5:0] ph_rank_1_94_V_read;
input [5:0] ph_rank_1_95_V_read;
input [5:0] ph_rank_1_96_V_read;
input [5:0] ph_rank_1_97_V_read;
input [5:0] ph_rank_1_98_V_read;
input [5:0] ph_rank_1_99_V_read;
input [5:0] ph_rank_1_100_V_read;
input [5:0] ph_rank_1_101_V_read;
input [5:0] ph_rank_1_102_V_read;
input [5:0] ph_rank_1_103_V_read;
input [5:0] ph_rank_1_104_V_read;
input [5:0] ph_rank_1_105_V_read;
input [5:0] ph_rank_1_106_V_read;
input [5:0] ph_rank_1_107_V_read;
input [5:0] ph_rank_1_108_V_read;
input [5:0] ph_rank_1_109_V_read;
input [5:0] ph_rank_1_110_V_read;
input [5:0] ph_rank_1_111_V_read;
input [5:0] ph_rank_1_112_V_read;
input [5:0] ph_rank_1_113_V_read;
input [5:0] ph_rank_1_114_V_read;
input [5:0] ph_rank_1_115_V_read;
input [5:0] ph_rank_1_116_V_read;
input [5:0] ph_rank_1_117_V_read;
input [5:0] ph_rank_1_118_V_read;
input [5:0] ph_rank_1_119_V_read;
input [5:0] ph_rank_1_120_V_read;
input [5:0] ph_rank_1_121_V_read;
input [5:0] ph_rank_2_0_V_read;
input [5:0] ph_rank_2_1_V_read;
input [5:0] ph_rank_2_2_V_read;
input [5:0] ph_rank_2_3_V_read;
input [5:0] ph_rank_2_4_V_read;
input [5:0] ph_rank_2_5_V_read;
input [5:0] ph_rank_2_6_V_read;
input [5:0] ph_rank_2_7_V_read;
input [5:0] ph_rank_2_8_V_read;
input [5:0] ph_rank_2_9_V_read;
input [5:0] ph_rank_2_10_V_read;
input [5:0] ph_rank_2_11_V_read;
input [5:0] ph_rank_2_12_V_read;
input [5:0] ph_rank_2_13_V_read;
input [5:0] ph_rank_2_14_V_read;
input [5:0] ph_rank_2_15_V_read;
input [5:0] ph_rank_2_16_V_read;
input [5:0] ph_rank_2_17_V_read;
input [5:0] ph_rank_2_18_V_read;
input [5:0] ph_rank_2_19_V_read;
input [5:0] ph_rank_2_20_V_read;
input [5:0] ph_rank_2_21_V_read;
input [5:0] ph_rank_2_22_V_read;
input [5:0] ph_rank_2_23_V_read;
input [5:0] ph_rank_2_24_V_read;
input [5:0] ph_rank_2_25_V_read;
input [5:0] ph_rank_2_26_V_read;
input [5:0] ph_rank_2_27_V_read;
input [5:0] ph_rank_2_28_V_read;
input [5:0] ph_rank_2_29_V_read;
input [5:0] ph_rank_2_30_V_read;
input [5:0] ph_rank_2_31_V_read;
input [5:0] ph_rank_2_32_V_read;
input [5:0] ph_rank_2_33_V_read;
input [5:0] ph_rank_2_34_V_read;
input [5:0] ph_rank_2_35_V_read;
input [5:0] ph_rank_2_36_V_read;
input [5:0] ph_rank_2_37_V_read;
input [5:0] ph_rank_2_38_V_read;
input [5:0] ph_rank_2_39_V_read;
input [5:0] ph_rank_2_40_V_read;
input [5:0] ph_rank_2_41_V_read;
input [5:0] ph_rank_2_42_V_read;
input [5:0] ph_rank_2_43_V_read;
input [5:0] ph_rank_2_44_V_read;
input [5:0] ph_rank_2_45_V_read;
input [5:0] ph_rank_2_46_V_read;
input [5:0] ph_rank_2_47_V_read;
input [5:0] ph_rank_2_48_V_read;
input [5:0] ph_rank_2_49_V_read;
input [5:0] ph_rank_2_50_V_read;
input [5:0] ph_rank_2_51_V_read;
input [5:0] ph_rank_2_52_V_read;
input [5:0] ph_rank_2_53_V_read;
input [5:0] ph_rank_2_54_V_read;
input [5:0] ph_rank_2_55_V_read;
input [5:0] ph_rank_2_56_V_read;
input [5:0] ph_rank_2_57_V_read;
input [5:0] ph_rank_2_58_V_read;
input [5:0] ph_rank_2_59_V_read;
input [5:0] ph_rank_2_60_V_read;
input [5:0] ph_rank_2_61_V_read;
input [5:0] ph_rank_2_62_V_read;
input [5:0] ph_rank_2_63_V_read;
input [5:0] ph_rank_2_64_V_read;
input [5:0] ph_rank_2_65_V_read;
input [5:0] ph_rank_2_66_V_read;
input [5:0] ph_rank_2_67_V_read;
input [5:0] ph_rank_2_68_V_read;
input [5:0] ph_rank_2_69_V_read;
input [5:0] ph_rank_2_70_V_read;
input [5:0] ph_rank_2_71_V_read;
input [5:0] ph_rank_2_72_V_read;
input [5:0] ph_rank_2_73_V_read;
input [5:0] ph_rank_2_74_V_read;
input [5:0] ph_rank_2_75_V_read;
input [5:0] ph_rank_2_76_V_read;
input [5:0] ph_rank_2_77_V_read;
input [5:0] ph_rank_2_78_V_read;
input [5:0] ph_rank_2_79_V_read;
input [5:0] ph_rank_2_80_V_read;
input [5:0] ph_rank_2_81_V_read;
input [5:0] ph_rank_2_82_V_read;
input [5:0] ph_rank_2_83_V_read;
input [5:0] ph_rank_2_84_V_read;
input [5:0] ph_rank_2_85_V_read;
input [5:0] ph_rank_2_86_V_read;
input [5:0] ph_rank_2_87_V_read;
input [5:0] ph_rank_2_88_V_read;
input [5:0] ph_rank_2_89_V_read;
input [5:0] ph_rank_2_90_V_read;
input [5:0] ph_rank_2_91_V_read;
input [5:0] ph_rank_2_92_V_read;
input [5:0] ph_rank_2_93_V_read;
input [5:0] ph_rank_2_94_V_read;
input [5:0] ph_rank_2_95_V_read;
input [5:0] ph_rank_2_96_V_read;
input [5:0] ph_rank_2_97_V_read;
input [5:0] ph_rank_2_98_V_read;
input [5:0] ph_rank_2_99_V_read;
input [5:0] ph_rank_2_100_V_read;
input [5:0] ph_rank_2_101_V_read;
input [5:0] ph_rank_2_102_V_read;
input [5:0] ph_rank_2_103_V_read;
input [5:0] ph_rank_2_104_V_read;
input [5:0] ph_rank_2_105_V_read;
input [5:0] ph_rank_2_106_V_read;
input [5:0] ph_rank_2_107_V_read;
input [5:0] ph_rank_2_108_V_read;
input [5:0] ph_rank_2_109_V_read;
input [5:0] ph_rank_2_110_V_read;
input [5:0] ph_rank_2_111_V_read;
input [5:0] ph_rank_2_112_V_read;
input [5:0] ph_rank_2_113_V_read;
input [5:0] ph_rank_2_114_V_read;
input [5:0] ph_rank_2_115_V_read;
input [5:0] ph_rank_2_116_V_read;
input [5:0] ph_rank_2_117_V_read;
input [5:0] ph_rank_2_118_V_read;
input [5:0] ph_rank_2_119_V_read;
input [5:0] ph_rank_2_120_V_read;
input [5:0] ph_rank_2_121_V_read;
input [5:0] ph_rank_3_0_V_read;
input [5:0] ph_rank_3_1_V_read;
input [5:0] ph_rank_3_2_V_read;
input [5:0] ph_rank_3_3_V_read;
input [5:0] ph_rank_3_4_V_read;
input [5:0] ph_rank_3_5_V_read;
input [5:0] ph_rank_3_6_V_read;
input [5:0] ph_rank_3_7_V_read;
input [5:0] ph_rank_3_8_V_read;
input [5:0] ph_rank_3_9_V_read;
input [5:0] ph_rank_3_10_V_read;
input [5:0] ph_rank_3_11_V_read;
input [5:0] ph_rank_3_12_V_read;
input [5:0] ph_rank_3_13_V_read;
input [5:0] ph_rank_3_14_V_read;
input [5:0] ph_rank_3_15_V_read;
input [5:0] ph_rank_3_16_V_read;
input [5:0] ph_rank_3_17_V_read;
input [5:0] ph_rank_3_18_V_read;
input [5:0] ph_rank_3_19_V_read;
input [5:0] ph_rank_3_20_V_read;
input [5:0] ph_rank_3_21_V_read;
input [5:0] ph_rank_3_22_V_read;
input [5:0] ph_rank_3_23_V_read;
input [5:0] ph_rank_3_24_V_read;
input [5:0] ph_rank_3_25_V_read;
input [5:0] ph_rank_3_26_V_read;
input [5:0] ph_rank_3_27_V_read;
input [5:0] ph_rank_3_28_V_read;
input [5:0] ph_rank_3_29_V_read;
input [5:0] ph_rank_3_30_V_read;
input [5:0] ph_rank_3_31_V_read;
input [5:0] ph_rank_3_32_V_read;
input [5:0] ph_rank_3_33_V_read;
input [5:0] ph_rank_3_34_V_read;
input [5:0] ph_rank_3_35_V_read;
input [5:0] ph_rank_3_36_V_read;
input [5:0] ph_rank_3_37_V_read;
input [5:0] ph_rank_3_38_V_read;
input [5:0] ph_rank_3_39_V_read;
input [5:0] ph_rank_3_40_V_read;
input [5:0] ph_rank_3_41_V_read;
input [5:0] ph_rank_3_42_V_read;
input [5:0] ph_rank_3_43_V_read;
input [5:0] ph_rank_3_44_V_read;
input [5:0] ph_rank_3_45_V_read;
input [5:0] ph_rank_3_46_V_read;
input [5:0] ph_rank_3_47_V_read;
input [5:0] ph_rank_3_48_V_read;
input [5:0] ph_rank_3_49_V_read;
input [5:0] ph_rank_3_50_V_read;
input [5:0] ph_rank_3_51_V_read;
input [5:0] ph_rank_3_52_V_read;
input [5:0] ph_rank_3_53_V_read;
input [5:0] ph_rank_3_54_V_read;
input [5:0] ph_rank_3_55_V_read;
input [5:0] ph_rank_3_56_V_read;
input [5:0] ph_rank_3_57_V_read;
input [5:0] ph_rank_3_58_V_read;
input [5:0] ph_rank_3_59_V_read;
input [5:0] ph_rank_3_60_V_read;
input [5:0] ph_rank_3_61_V_read;
input [5:0] ph_rank_3_62_V_read;
input [5:0] ph_rank_3_63_V_read;
input [5:0] ph_rank_3_64_V_read;
input [5:0] ph_rank_3_65_V_read;
input [5:0] ph_rank_3_66_V_read;
input [5:0] ph_rank_3_67_V_read;
input [5:0] ph_rank_3_68_V_read;
input [5:0] ph_rank_3_69_V_read;
input [5:0] ph_rank_3_70_V_read;
input [5:0] ph_rank_3_71_V_read;
input [5:0] ph_rank_3_72_V_read;
input [5:0] ph_rank_3_73_V_read;
input [5:0] ph_rank_3_74_V_read;
input [5:0] ph_rank_3_75_V_read;
input [5:0] ph_rank_3_76_V_read;
input [5:0] ph_rank_3_77_V_read;
input [5:0] ph_rank_3_78_V_read;
input [5:0] ph_rank_3_79_V_read;
input [5:0] ph_rank_3_80_V_read;
input [5:0] ph_rank_3_81_V_read;
input [5:0] ph_rank_3_82_V_read;
input [5:0] ph_rank_3_83_V_read;
input [5:0] ph_rank_3_84_V_read;
input [5:0] ph_rank_3_85_V_read;
input [5:0] ph_rank_3_86_V_read;
input [5:0] ph_rank_3_87_V_read;
input [5:0] ph_rank_3_88_V_read;
input [5:0] ph_rank_3_89_V_read;
input [5:0] ph_rank_3_90_V_read;
input [5:0] ph_rank_3_91_V_read;
input [5:0] ph_rank_3_92_V_read;
input [5:0] ph_rank_3_93_V_read;
input [5:0] ph_rank_3_94_V_read;
input [5:0] ph_rank_3_95_V_read;
input [5:0] ph_rank_3_96_V_read;
input [5:0] ph_rank_3_97_V_read;
input [5:0] ph_rank_3_98_V_read;
input [5:0] ph_rank_3_99_V_read;
input [5:0] ph_rank_3_100_V_read;
input [5:0] ph_rank_3_101_V_read;
input [5:0] ph_rank_3_102_V_read;
input [5:0] ph_rank_3_103_V_read;
input [5:0] ph_rank_3_104_V_read;
input [5:0] ph_rank_3_105_V_read;
input [5:0] ph_rank_3_106_V_read;
input [5:0] ph_rank_3_107_V_read;
input [5:0] ph_rank_3_108_V_read;
input [5:0] ph_rank_3_109_V_read;
input [5:0] ph_rank_3_110_V_read;
input [5:0] ph_rank_3_111_V_read;
input [5:0] ph_rank_3_112_V_read;
input [5:0] ph_rank_3_113_V_read;
input [5:0] ph_rank_3_114_V_read;
input [5:0] ph_rank_3_115_V_read;
input [5:0] ph_rank_3_116_V_read;
input [5:0] ph_rank_3_117_V_read;
input [5:0] ph_rank_3_118_V_read;
input [5:0] ph_rank_3_119_V_read;
input [5:0] ph_rank_3_120_V_read;
input [5:0] ph_rank_3_121_V_read;
output [6:0] ap_return_0;
output [6:0] ap_return_1;
output [6:0] ap_return_2;
output [6:0] ap_return_3;
output [6:0] ap_return_4;
output [6:0] ap_return_5;
output [6:0] ap_return_6;
output [6:0] ap_return_7;
output [6:0] ap_return_8;
output [6:0] ap_return_9;
output [6:0] ap_return_10;
output [6:0] ap_return_11;
output [5:0] ap_return_12;
output [5:0] ap_return_13;
output [5:0] ap_return_14;
output [5:0] ap_return_15;
output [5:0] ap_return_16;
output [5:0] ap_return_17;
output [5:0] ap_return_18;
output [5:0] ap_return_19;
output [5:0] ap_return_20;
output [5:0] ap_return_21;
output [5:0] ap_return_22;
output [5:0] ap_return_23;
wire [5:0] grp_sp_best3_fu_3932_ap_return_0;
wire [5:0] grp_sp_best3_fu_3932_ap_return_1;
wire [5:0] grp_sp_best3_fu_3932_ap_return_2;
wire [6:0] grp_sp_best3_fu_3932_ap_return_3;
wire [6:0] grp_sp_best3_fu_3932_ap_return_4;
wire [6:0] grp_sp_best3_fu_3932_ap_return_5;
wire [5:0] grp_sp_best3_fu_4180_ap_return_0;
wire [5:0] grp_sp_best3_fu_4180_ap_return_1;
wire [5:0] grp_sp_best3_fu_4180_ap_return_2;
wire [6:0] grp_sp_best3_fu_4180_ap_return_3;
wire [6:0] grp_sp_best3_fu_4180_ap_return_4;
wire [6:0] grp_sp_best3_fu_4180_ap_return_5;
wire [5:0] grp_sp_best3_fu_4428_ap_return_0;
wire [5:0] grp_sp_best3_fu_4428_ap_return_1;
wire [5:0] grp_sp_best3_fu_4428_ap_return_2;
wire [6:0] grp_sp_best3_fu_4428_ap_return_3;
wire [6:0] grp_sp_best3_fu_4428_ap_return_4;
wire [6:0] grp_sp_best3_fu_4428_ap_return_5;
wire [5:0] grp_sp_best3_fu_4676_ap_return_0;
wire [5:0] grp_sp_best3_fu_4676_ap_return_1;
wire [5:0] grp_sp_best3_fu_4676_ap_return_2;
wire [6:0] grp_sp_best3_fu_4676_ap_return_3;
wire [6:0] grp_sp_best3_fu_4676_ap_return_4;
wire [6:0] grp_sp_best3_fu_4676_ap_return_5;
sp_best3 grp_sp_best3_fu_3932(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.rank_ex_0_V_read(ph_rank_0_0_V_read),
.rank_ex_1_V_read(ph_rank_0_1_V_read),
.rank_ex_2_V_read(ph_rank_0_2_V_read),
.rank_ex_3_V_read(ph_rank_0_3_V_read),
.rank_ex_4_V_read(ph_rank_0_4_V_read),
.rank_ex_5_V_read(ph_rank_0_5_V_read),
.rank_ex_6_V_read(ph_rank_0_6_V_read),
.rank_ex_7_V_read(ph_rank_0_7_V_read),
.rank_ex_8_V_read(ph_rank_0_8_V_read),
.rank_ex_9_V_read(ph_rank_0_9_V_read),
.rank_ex_10_V_read(ph_rank_0_10_V_read),
.rank_ex_11_V_read(ph_rank_0_11_V_read),
.rank_ex_12_V_read(ph_rank_0_12_V_read),
.rank_ex_13_V_read(ph_rank_0_13_V_read),
.rank_ex_14_V_read(ph_rank_0_14_V_read),
.rank_ex_15_V_read(ph_rank_0_15_V_read),
.rank_ex_16_V_read(ph_rank_0_16_V_read),
.rank_ex_17_V_read(ph_rank_0_17_V_read),
.rank_ex_18_V_read(ph_rank_0_18_V_read),
.rank_ex_19_V_read(ph_rank_0_19_V_read),
.rank_ex_20_V_read(ph_rank_0_20_V_read),
.rank_ex_21_V_read(ph_rank_0_21_V_read),
.rank_ex_22_V_read(ph_rank_0_22_V_read),
.rank_ex_23_V_read(ph_rank_0_23_V_read),
.rank_ex_24_V_read(ph_rank_0_24_V_read),
.rank_ex_25_V_read(ph_rank_0_25_V_read),
.rank_ex_26_V_read(ph_rank_0_26_V_read),
.rank_ex_27_V_read(ph_rank_0_27_V_read),
.rank_ex_28_V_read(ph_rank_0_28_V_read),
.rank_ex_29_V_read(ph_rank_0_29_V_read),
.rank_ex_30_V_read(ph_rank_0_30_V_read),
.rank_ex_31_V_read(ph_rank_0_31_V_read),
.rank_ex_32_V_read(ph_rank_0_32_V_read),
.rank_ex_33_V_read(ph_rank_0_33_V_read),
.rank_ex_34_V_read(ph_rank_0_34_V_read),
.rank_ex_35_V_read(ph_rank_0_35_V_read),
.rank_ex_36_V_read(ph_rank_0_36_V_read),
.rank_ex_37_V_read(ph_rank_0_37_V_read),
.rank_ex_38_V_read(ph_rank_0_38_V_read),
.rank_ex_39_V_read(ph_rank_0_39_V_read),
.rank_ex_40_V_read(ph_rank_0_40_V_read),
.rank_ex_41_V_read(ph_rank_0_41_V_read),
.rank_ex_42_V_read(ph_rank_0_42_V_read),
.rank_ex_43_V_read(ph_rank_0_43_V_read),
.rank_ex_44_V_read(ph_rank_0_44_V_read),
.rank_ex_45_V_read(ph_rank_0_45_V_read),
.rank_ex_46_V_read(ph_rank_0_46_V_read),
.rank_ex_47_V_read(ph_rank_0_47_V_read),
.rank_ex_48_V_read(ph_rank_0_48_V_read),
.rank_ex_49_V_read(ph_rank_0_49_V_read),
.rank_ex_50_V_read(ph_rank_0_50_V_read),
.rank_ex_51_V_read(ph_rank_0_51_V_read),
.rank_ex_52_V_read(ph_rank_0_52_V_read),
.rank_ex_53_V_read(ph_rank_0_53_V_read),
.rank_ex_54_V_read(ph_rank_0_54_V_read),
.rank_ex_55_V_read(ph_rank_0_55_V_read),
.rank_ex_56_V_read(ph_rank_0_56_V_read),
.rank_ex_57_V_read(ph_rank_0_57_V_read),
.rank_ex_58_V_read(ph_rank_0_58_V_read),
.rank_ex_59_V_read(ph_rank_0_59_V_read),
.rank_ex_60_V_read(ph_rank_0_60_V_read),
.rank_ex_61_V_read(ph_rank_0_61_V_read),
.rank_ex_62_V_read(ph_rank_0_62_V_read),
.rank_ex_63_V_read(ph_rank_0_63_V_read),
.rank_ex_64_V_read(ph_rank_0_64_V_read),
.rank_ex_65_V_read(ph_rank_0_65_V_read),
.rank_ex_66_V_read(ph_rank_0_66_V_read),
.rank_ex_67_V_read(ph_rank_0_67_V_read),
.rank_ex_68_V_read(ph_rank_0_68_V_read),
.rank_ex_69_V_read(ph_rank_0_69_V_read),
.rank_ex_70_V_read(ph_rank_0_70_V_read),
.rank_ex_71_V_read(ph_rank_0_71_V_read),
.rank_ex_72_V_read(ph_rank_0_72_V_read),
.rank_ex_73_V_read(ph_rank_0_73_V_read),
.rank_ex_74_V_read(ph_rank_0_74_V_read),
.rank_ex_75_V_read(ph_rank_0_75_V_read),
.rank_ex_76_V_read(ph_rank_0_76_V_read),
.rank_ex_77_V_read(ph_rank_0_77_V_read),
.rank_ex_78_V_read(ph_rank_0_78_V_read),
.rank_ex_79_V_read(ph_rank_0_79_V_read),
.rank_ex_80_V_read(ph_rank_0_80_V_read),
.rank_ex_81_V_read(ph_rank_0_81_V_read),
.rank_ex_82_V_read(ph_rank_0_82_V_read),
.rank_ex_83_V_read(ph_rank_0_83_V_read),
.rank_ex_84_V_read(ph_rank_0_84_V_read),
.rank_ex_85_V_read(ph_rank_0_85_V_read),
.rank_ex_86_V_read(ph_rank_0_86_V_read),
.rank_ex_87_V_read(ph_rank_0_87_V_read),
.rank_ex_88_V_read(ph_rank_0_88_V_read),
.rank_ex_89_V_read(ph_rank_0_89_V_read),
.rank_ex_90_V_read(ph_rank_0_90_V_read),
.rank_ex_91_V_read(ph_rank_0_91_V_read),
.rank_ex_92_V_read(ph_rank_0_92_V_read),
.rank_ex_93_V_read(ph_rank_0_93_V_read),
.rank_ex_94_V_read(ph_rank_0_94_V_read),
.rank_ex_95_V_read(ph_rank_0_95_V_read),
.rank_ex_96_V_read(ph_rank_0_96_V_read),
.rank_ex_97_V_read(ph_rank_0_97_V_read),
.rank_ex_98_V_read(ph_rank_0_98_V_read),
.rank_ex_99_V_read(ph_rank_0_99_V_read),
.rank_ex_100_V_read(ph_rank_0_100_V_read),
.rank_ex_101_V_read(ph_rank_0_101_V_read),
.rank_ex_102_V_read(ph_rank_0_102_V_read),
.rank_ex_103_V_read(ph_rank_0_103_V_read),
.rank_ex_104_V_read(ph_rank_0_104_V_read),
.rank_ex_105_V_read(ph_rank_0_105_V_read),
.rank_ex_106_V_read(ph_rank_0_106_V_read),
.rank_ex_107_V_read(ph_rank_0_107_V_read),
.rank_ex_108_V_read(ph_rank_0_108_V_read),
.rank_ex_109_V_read(ph_rank_0_109_V_read),
.rank_ex_110_V_read(ph_rank_0_110_V_read),
.rank_ex_111_V_read(ph_rank_0_111_V_read),
.rank_ex_112_V_read(ph_rank_0_112_V_read),
.rank_ex_113_V_read(ph_rank_0_113_V_read),
.rank_ex_114_V_read(ph_rank_0_114_V_read),
.rank_ex_115_V_read(ph_rank_0_115_V_read),
.rank_ex_116_V_read(ph_rank_0_116_V_read),
.rank_ex_117_V_read(ph_rank_0_117_V_read),
.rank_ex_118_V_read(ph_rank_0_118_V_read),
.rank_ex_119_V_read(ph_rank_0_119_V_read),
.rank_ex_120_V_read(ph_rank_0_120_V_read),
.rank_ex_121_V_read(ph_rank_0_121_V_read),
.ap_return_0(grp_sp_best3_fu_3932_ap_return_0),
.ap_return_1(grp_sp_best3_fu_3932_ap_return_1),
.ap_return_2(grp_sp_best3_fu_3932_ap_return_2),
.ap_return_3(grp_sp_best3_fu_3932_ap_return_3),
.ap_return_4(grp_sp_best3_fu_3932_ap_return_4),
.ap_return_5(grp_sp_best3_fu_3932_ap_return_5)
);
sp_best3 grp_sp_best3_fu_4180(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.rank_ex_0_V_read(ph_rank_1_0_V_read),
.rank_ex_1_V_read(ph_rank_1_1_V_read),
.rank_ex_2_V_read(ph_rank_1_2_V_read),
.rank_ex_3_V_read(ph_rank_1_3_V_read),
.rank_ex_4_V_read(ph_rank_1_4_V_read),
.rank_ex_5_V_read(ph_rank_1_5_V_read),
.rank_ex_6_V_read(ph_rank_1_6_V_read),
.rank_ex_7_V_read(ph_rank_1_7_V_read),
.rank_ex_8_V_read(ph_rank_1_8_V_read),
.rank_ex_9_V_read(ph_rank_1_9_V_read),
.rank_ex_10_V_read(ph_rank_1_10_V_read),
.rank_ex_11_V_read(ph_rank_1_11_V_read),
.rank_ex_12_V_read(ph_rank_1_12_V_read),
.rank_ex_13_V_read(ph_rank_1_13_V_read),
.rank_ex_14_V_read(ph_rank_1_14_V_read),
.rank_ex_15_V_read(ph_rank_1_15_V_read),
.rank_ex_16_V_read(ph_rank_1_16_V_read),
.rank_ex_17_V_read(ph_rank_1_17_V_read),
.rank_ex_18_V_read(ph_rank_1_18_V_read),
.rank_ex_19_V_read(ph_rank_1_19_V_read),
.rank_ex_20_V_read(ph_rank_1_20_V_read),
.rank_ex_21_V_read(ph_rank_1_21_V_read),
.rank_ex_22_V_read(ph_rank_1_22_V_read),
.rank_ex_23_V_read(ph_rank_1_23_V_read),
.rank_ex_24_V_read(ph_rank_1_24_V_read),
.rank_ex_25_V_read(ph_rank_1_25_V_read),
.rank_ex_26_V_read(ph_rank_1_26_V_read),
.rank_ex_27_V_read(ph_rank_1_27_V_read),
.rank_ex_28_V_read(ph_rank_1_28_V_read),
.rank_ex_29_V_read(ph_rank_1_29_V_read),
.rank_ex_30_V_read(ph_rank_1_30_V_read),
.rank_ex_31_V_read(ph_rank_1_31_V_read),
.rank_ex_32_V_read(ph_rank_1_32_V_read),
.rank_ex_33_V_read(ph_rank_1_33_V_read),
.rank_ex_34_V_read(ph_rank_1_34_V_read),
.rank_ex_35_V_read(ph_rank_1_35_V_read),
.rank_ex_36_V_read(ph_rank_1_36_V_read),
.rank_ex_37_V_read(ph_rank_1_37_V_read),
.rank_ex_38_V_read(ph_rank_1_38_V_read),
.rank_ex_39_V_read(ph_rank_1_39_V_read),
.rank_ex_40_V_read(ph_rank_1_40_V_read),
.rank_ex_41_V_read(ph_rank_1_41_V_read),
.rank_ex_42_V_read(ph_rank_1_42_V_read),
.rank_ex_43_V_read(ph_rank_1_43_V_read),
.rank_ex_44_V_read(ph_rank_1_44_V_read),
.rank_ex_45_V_read(ph_rank_1_45_V_read),
.rank_ex_46_V_read(ph_rank_1_46_V_read),
.rank_ex_47_V_read(ph_rank_1_47_V_read),
.rank_ex_48_V_read(ph_rank_1_48_V_read),
.rank_ex_49_V_read(ph_rank_1_49_V_read),
.rank_ex_50_V_read(ph_rank_1_50_V_read),
.rank_ex_51_V_read(ph_rank_1_51_V_read),
.rank_ex_52_V_read(ph_rank_1_52_V_read),
.rank_ex_53_V_read(ph_rank_1_53_V_read),
.rank_ex_54_V_read(ph_rank_1_54_V_read),
.rank_ex_55_V_read(ph_rank_1_55_V_read),
.rank_ex_56_V_read(ph_rank_1_56_V_read),
.rank_ex_57_V_read(ph_rank_1_57_V_read),
.rank_ex_58_V_read(ph_rank_1_58_V_read),
.rank_ex_59_V_read(ph_rank_1_59_V_read),
.rank_ex_60_V_read(ph_rank_1_60_V_read),
.rank_ex_61_V_read(ph_rank_1_61_V_read),
.rank_ex_62_V_read(ph_rank_1_62_V_read),
.rank_ex_63_V_read(ph_rank_1_63_V_read),
.rank_ex_64_V_read(ph_rank_1_64_V_read),
.rank_ex_65_V_read(ph_rank_1_65_V_read),
.rank_ex_66_V_read(ph_rank_1_66_V_read),
.rank_ex_67_V_read(ph_rank_1_67_V_read),
.rank_ex_68_V_read(ph_rank_1_68_V_read),
.rank_ex_69_V_read(ph_rank_1_69_V_read),
.rank_ex_70_V_read(ph_rank_1_70_V_read),
.rank_ex_71_V_read(ph_rank_1_71_V_read),
.rank_ex_72_V_read(ph_rank_1_72_V_read),
.rank_ex_73_V_read(ph_rank_1_73_V_read),
.rank_ex_74_V_read(ph_rank_1_74_V_read),
.rank_ex_75_V_read(ph_rank_1_75_V_read),
.rank_ex_76_V_read(ph_rank_1_76_V_read),
.rank_ex_77_V_read(ph_rank_1_77_V_read),
.rank_ex_78_V_read(ph_rank_1_78_V_read),
.rank_ex_79_V_read(ph_rank_1_79_V_read),
.rank_ex_80_V_read(ph_rank_1_80_V_read),
.rank_ex_81_V_read(ph_rank_1_81_V_read),
.rank_ex_82_V_read(ph_rank_1_82_V_read),
.rank_ex_83_V_read(ph_rank_1_83_V_read),
.rank_ex_84_V_read(ph_rank_1_84_V_read),
.rank_ex_85_V_read(ph_rank_1_85_V_read),
.rank_ex_86_V_read(ph_rank_1_86_V_read),
.rank_ex_87_V_read(ph_rank_1_87_V_read),
.rank_ex_88_V_read(ph_rank_1_88_V_read),
.rank_ex_89_V_read(ph_rank_1_89_V_read),
.rank_ex_90_V_read(ph_rank_1_90_V_read),
.rank_ex_91_V_read(ph_rank_1_91_V_read),
.rank_ex_92_V_read(ph_rank_1_92_V_read),
.rank_ex_93_V_read(ph_rank_1_93_V_read),
.rank_ex_94_V_read(ph_rank_1_94_V_read),
.rank_ex_95_V_read(ph_rank_1_95_V_read),
.rank_ex_96_V_read(ph_rank_1_96_V_read),
.rank_ex_97_V_read(ph_rank_1_97_V_read),
.rank_ex_98_V_read(ph_rank_1_98_V_read),
.rank_ex_99_V_read(ph_rank_1_99_V_read),
.rank_ex_100_V_read(ph_rank_1_100_V_read),
.rank_ex_101_V_read(ph_rank_1_101_V_read),
.rank_ex_102_V_read(ph_rank_1_102_V_read),
.rank_ex_103_V_read(ph_rank_1_103_V_read),
.rank_ex_104_V_read(ph_rank_1_104_V_read),
.rank_ex_105_V_read(ph_rank_1_105_V_read),
.rank_ex_106_V_read(ph_rank_1_106_V_read),
.rank_ex_107_V_read(ph_rank_1_107_V_read),
.rank_ex_108_V_read(ph_rank_1_108_V_read),
.rank_ex_109_V_read(ph_rank_1_109_V_read),
.rank_ex_110_V_read(ph_rank_1_110_V_read),
.rank_ex_111_V_read(ph_rank_1_111_V_read),
.rank_ex_112_V_read(ph_rank_1_112_V_read),
.rank_ex_113_V_read(ph_rank_1_113_V_read),
.rank_ex_114_V_read(ph_rank_1_114_V_read),
.rank_ex_115_V_read(ph_rank_1_115_V_read),
.rank_ex_116_V_read(ph_rank_1_116_V_read),
.rank_ex_117_V_read(ph_rank_1_117_V_read),
.rank_ex_118_V_read(ph_rank_1_118_V_read),
.rank_ex_119_V_read(ph_rank_1_119_V_read),
.rank_ex_120_V_read(ph_rank_1_120_V_read),
.rank_ex_121_V_read(ph_rank_1_121_V_read),
.ap_return_0(grp_sp_best3_fu_4180_ap_return_0),
.ap_return_1(grp_sp_best3_fu_4180_ap_return_1),
.ap_return_2(grp_sp_best3_fu_4180_ap_return_2),
.ap_return_3(grp_sp_best3_fu_4180_ap_return_3),
.ap_return_4(grp_sp_best3_fu_4180_ap_return_4),
.ap_return_5(grp_sp_best3_fu_4180_ap_return_5)
);
sp_best3 grp_sp_best3_fu_4428(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.rank_ex_0_V_read(ph_rank_2_0_V_read),
.rank_ex_1_V_read(ph_rank_2_1_V_read),
.rank_ex_2_V_read(ph_rank_2_2_V_read),
.rank_ex_3_V_read(ph_rank_2_3_V_read),
.rank_ex_4_V_read(ph_rank_2_4_V_read),
.rank_ex_5_V_read(ph_rank_2_5_V_read),
.rank_ex_6_V_read(ph_rank_2_6_V_read),
.rank_ex_7_V_read(ph_rank_2_7_V_read),
.rank_ex_8_V_read(ph_rank_2_8_V_read),
.rank_ex_9_V_read(ph_rank_2_9_V_read),
.rank_ex_10_V_read(ph_rank_2_10_V_read),
.rank_ex_11_V_read(ph_rank_2_11_V_read),
.rank_ex_12_V_read(ph_rank_2_12_V_read),
.rank_ex_13_V_read(ph_rank_2_13_V_read),
.rank_ex_14_V_read(ph_rank_2_14_V_read),
.rank_ex_15_V_read(ph_rank_2_15_V_read),
.rank_ex_16_V_read(ph_rank_2_16_V_read),
.rank_ex_17_V_read(ph_rank_2_17_V_read),
.rank_ex_18_V_read(ph_rank_2_18_V_read),
.rank_ex_19_V_read(ph_rank_2_19_V_read),
.rank_ex_20_V_read(ph_rank_2_20_V_read),
.rank_ex_21_V_read(ph_rank_2_21_V_read),
.rank_ex_22_V_read(ph_rank_2_22_V_read),
.rank_ex_23_V_read(ph_rank_2_23_V_read),
.rank_ex_24_V_read(ph_rank_2_24_V_read),
.rank_ex_25_V_read(ph_rank_2_25_V_read),
.rank_ex_26_V_read(ph_rank_2_26_V_read),
.rank_ex_27_V_read(ph_rank_2_27_V_read),
.rank_ex_28_V_read(ph_rank_2_28_V_read),
.rank_ex_29_V_read(ph_rank_2_29_V_read),
.rank_ex_30_V_read(ph_rank_2_30_V_read),
.rank_ex_31_V_read(ph_rank_2_31_V_read),
.rank_ex_32_V_read(ph_rank_2_32_V_read),
.rank_ex_33_V_read(ph_rank_2_33_V_read),
.rank_ex_34_V_read(ph_rank_2_34_V_read),
.rank_ex_35_V_read(ph_rank_2_35_V_read),
.rank_ex_36_V_read(ph_rank_2_36_V_read),
.rank_ex_37_V_read(ph_rank_2_37_V_read),
.rank_ex_38_V_read(ph_rank_2_38_V_read),
.rank_ex_39_V_read(ph_rank_2_39_V_read),
.rank_ex_40_V_read(ph_rank_2_40_V_read),
.rank_ex_41_V_read(ph_rank_2_41_V_read),
.rank_ex_42_V_read(ph_rank_2_42_V_read),
.rank_ex_43_V_read(ph_rank_2_43_V_read),
.rank_ex_44_V_read(ph_rank_2_44_V_read),
.rank_ex_45_V_read(ph_rank_2_45_V_read),
.rank_ex_46_V_read(ph_rank_2_46_V_read),
.rank_ex_47_V_read(ph_rank_2_47_V_read),
.rank_ex_48_V_read(ph_rank_2_48_V_read),
.rank_ex_49_V_read(ph_rank_2_49_V_read),
.rank_ex_50_V_read(ph_rank_2_50_V_read),
.rank_ex_51_V_read(ph_rank_2_51_V_read),
.rank_ex_52_V_read(ph_rank_2_52_V_read),
.rank_ex_53_V_read(ph_rank_2_53_V_read),
.rank_ex_54_V_read(ph_rank_2_54_V_read),
.rank_ex_55_V_read(ph_rank_2_55_V_read),
.rank_ex_56_V_read(ph_rank_2_56_V_read),
.rank_ex_57_V_read(ph_rank_2_57_V_read),
.rank_ex_58_V_read(ph_rank_2_58_V_read),
.rank_ex_59_V_read(ph_rank_2_59_V_read),
.rank_ex_60_V_read(ph_rank_2_60_V_read),
.rank_ex_61_V_read(ph_rank_2_61_V_read),
.rank_ex_62_V_read(ph_rank_2_62_V_read),
.rank_ex_63_V_read(ph_rank_2_63_V_read),
.rank_ex_64_V_read(ph_rank_2_64_V_read),
.rank_ex_65_V_read(ph_rank_2_65_V_read),
.rank_ex_66_V_read(ph_rank_2_66_V_read),
.rank_ex_67_V_read(ph_rank_2_67_V_read),
.rank_ex_68_V_read(ph_rank_2_68_V_read),
.rank_ex_69_V_read(ph_rank_2_69_V_read),
.rank_ex_70_V_read(ph_rank_2_70_V_read),
.rank_ex_71_V_read(ph_rank_2_71_V_read),
.rank_ex_72_V_read(ph_rank_2_72_V_read),
.rank_ex_73_V_read(ph_rank_2_73_V_read),
.rank_ex_74_V_read(ph_rank_2_74_V_read),
.rank_ex_75_V_read(ph_rank_2_75_V_read),
.rank_ex_76_V_read(ph_rank_2_76_V_read),
.rank_ex_77_V_read(ph_rank_2_77_V_read),
.rank_ex_78_V_read(ph_rank_2_78_V_read),
.rank_ex_79_V_read(ph_rank_2_79_V_read),
.rank_ex_80_V_read(ph_rank_2_80_V_read),
.rank_ex_81_V_read(ph_rank_2_81_V_read),
.rank_ex_82_V_read(ph_rank_2_82_V_read),
.rank_ex_83_V_read(ph_rank_2_83_V_read),
.rank_ex_84_V_read(ph_rank_2_84_V_read),
.rank_ex_85_V_read(ph_rank_2_85_V_read),
.rank_ex_86_V_read(ph_rank_2_86_V_read),
.rank_ex_87_V_read(ph_rank_2_87_V_read),
.rank_ex_88_V_read(ph_rank_2_88_V_read),
.rank_ex_89_V_read(ph_rank_2_89_V_read),
.rank_ex_90_V_read(ph_rank_2_90_V_read),
.rank_ex_91_V_read(ph_rank_2_91_V_read),
.rank_ex_92_V_read(ph_rank_2_92_V_read),
.rank_ex_93_V_read(ph_rank_2_93_V_read),
.rank_ex_94_V_read(ph_rank_2_94_V_read),
.rank_ex_95_V_read(ph_rank_2_95_V_read),
.rank_ex_96_V_read(ph_rank_2_96_V_read),
.rank_ex_97_V_read(ph_rank_2_97_V_read),
.rank_ex_98_V_read(ph_rank_2_98_V_read),
.rank_ex_99_V_read(ph_rank_2_99_V_read),
.rank_ex_100_V_read(ph_rank_2_100_V_read),
.rank_ex_101_V_read(ph_rank_2_101_V_read),
.rank_ex_102_V_read(ph_rank_2_102_V_read),
.rank_ex_103_V_read(ph_rank_2_103_V_read),
.rank_ex_104_V_read(ph_rank_2_104_V_read),
.rank_ex_105_V_read(ph_rank_2_105_V_read),
.rank_ex_106_V_read(ph_rank_2_106_V_read),
.rank_ex_107_V_read(ph_rank_2_107_V_read),
.rank_ex_108_V_read(ph_rank_2_108_V_read),
.rank_ex_109_V_read(ph_rank_2_109_V_read),
.rank_ex_110_V_read(ph_rank_2_110_V_read),
.rank_ex_111_V_read(ph_rank_2_111_V_read),
.rank_ex_112_V_read(ph_rank_2_112_V_read),
.rank_ex_113_V_read(ph_rank_2_113_V_read),
.rank_ex_114_V_read(ph_rank_2_114_V_read),
.rank_ex_115_V_read(ph_rank_2_115_V_read),
.rank_ex_116_V_read(ph_rank_2_116_V_read),
.rank_ex_117_V_read(ph_rank_2_117_V_read),
.rank_ex_118_V_read(ph_rank_2_118_V_read),
.rank_ex_119_V_read(ph_rank_2_119_V_read),
.rank_ex_120_V_read(ph_rank_2_120_V_read),
.rank_ex_121_V_read(ph_rank_2_121_V_read),
.ap_return_0(grp_sp_best3_fu_4428_ap_return_0),
.ap_return_1(grp_sp_best3_fu_4428_ap_return_1),
.ap_return_2(grp_sp_best3_fu_4428_ap_return_2),
.ap_return_3(grp_sp_best3_fu_4428_ap_return_3),
.ap_return_4(grp_sp_best3_fu_4428_ap_return_4),
.ap_return_5(grp_sp_best3_fu_4428_ap_return_5)
);
sp_best3 grp_sp_best3_fu_4676(
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.rank_ex_0_V_read(ph_rank_3_0_V_read),
.rank_ex_1_V_read(ph_rank_3_1_V_read),
.rank_ex_2_V_read(ph_rank_3_2_V_read),
.rank_ex_3_V_read(ph_rank_3_3_V_read),
.rank_ex_4_V_read(ph_rank_3_4_V_read),
.rank_ex_5_V_read(ph_rank_3_5_V_read),
.rank_ex_6_V_read(ph_rank_3_6_V_read),
.rank_ex_7_V_read(ph_rank_3_7_V_read),
.rank_ex_8_V_read(ph_rank_3_8_V_read),
.rank_ex_9_V_read(ph_rank_3_9_V_read),
.rank_ex_10_V_read(ph_rank_3_10_V_read),
.rank_ex_11_V_read(ph_rank_3_11_V_read),
.rank_ex_12_V_read(ph_rank_3_12_V_read),
.rank_ex_13_V_read(ph_rank_3_13_V_read),
.rank_ex_14_V_read(ph_rank_3_14_V_read),
.rank_ex_15_V_read(ph_rank_3_15_V_read),
.rank_ex_16_V_read(ph_rank_3_16_V_read),
.rank_ex_17_V_read(ph_rank_3_17_V_read),
.rank_ex_18_V_read(ph_rank_3_18_V_read),
.rank_ex_19_V_read(ph_rank_3_19_V_read),
.rank_ex_20_V_read(ph_rank_3_20_V_read),
.rank_ex_21_V_read(ph_rank_3_21_V_read),
.rank_ex_22_V_read(ph_rank_3_22_V_read),
.rank_ex_23_V_read(ph_rank_3_23_V_read),
.rank_ex_24_V_read(ph_rank_3_24_V_read),
.rank_ex_25_V_read(ph_rank_3_25_V_read),
.rank_ex_26_V_read(ph_rank_3_26_V_read),
.rank_ex_27_V_read(ph_rank_3_27_V_read),
.rank_ex_28_V_read(ph_rank_3_28_V_read),
.rank_ex_29_V_read(ph_rank_3_29_V_read),
.rank_ex_30_V_read(ph_rank_3_30_V_read),
.rank_ex_31_V_read(ph_rank_3_31_V_read),
.rank_ex_32_V_read(ph_rank_3_32_V_read),
.rank_ex_33_V_read(ph_rank_3_33_V_read),
.rank_ex_34_V_read(ph_rank_3_34_V_read),
.rank_ex_35_V_read(ph_rank_3_35_V_read),
.rank_ex_36_V_read(ph_rank_3_36_V_read),
.rank_ex_37_V_read(ph_rank_3_37_V_read),
.rank_ex_38_V_read(ph_rank_3_38_V_read),
.rank_ex_39_V_read(ph_rank_3_39_V_read),
.rank_ex_40_V_read(ph_rank_3_40_V_read),
.rank_ex_41_V_read(ph_rank_3_41_V_read),
.rank_ex_42_V_read(ph_rank_3_42_V_read),
.rank_ex_43_V_read(ph_rank_3_43_V_read),
.rank_ex_44_V_read(ph_rank_3_44_V_read),
.rank_ex_45_V_read(ph_rank_3_45_V_read),
.rank_ex_46_V_read(ph_rank_3_46_V_read),
.rank_ex_47_V_read(ph_rank_3_47_V_read),
.rank_ex_48_V_read(ph_rank_3_48_V_read),
.rank_ex_49_V_read(ph_rank_3_49_V_read),
.rank_ex_50_V_read(ph_rank_3_50_V_read),
.rank_ex_51_V_read(ph_rank_3_51_V_read),
.rank_ex_52_V_read(ph_rank_3_52_V_read),
.rank_ex_53_V_read(ph_rank_3_53_V_read),
.rank_ex_54_V_read(ph_rank_3_54_V_read),
.rank_ex_55_V_read(ph_rank_3_55_V_read),
.rank_ex_56_V_read(ph_rank_3_56_V_read),
.rank_ex_57_V_read(ph_rank_3_57_V_read),
.rank_ex_58_V_read(ph_rank_3_58_V_read),
.rank_ex_59_V_read(ph_rank_3_59_V_read),
.rank_ex_60_V_read(ph_rank_3_60_V_read),
.rank_ex_61_V_read(ph_rank_3_61_V_read),
.rank_ex_62_V_read(ph_rank_3_62_V_read),
.rank_ex_63_V_read(ph_rank_3_63_V_read),
.rank_ex_64_V_read(ph_rank_3_64_V_read),
.rank_ex_65_V_read(ph_rank_3_65_V_read),
.rank_ex_66_V_read(ph_rank_3_66_V_read),
.rank_ex_67_V_read(ph_rank_3_67_V_read),
.rank_ex_68_V_read(ph_rank_3_68_V_read),
.rank_ex_69_V_read(ph_rank_3_69_V_read),
.rank_ex_70_V_read(ph_rank_3_70_V_read),
.rank_ex_71_V_read(ph_rank_3_71_V_read),
.rank_ex_72_V_read(ph_rank_3_72_V_read),
.rank_ex_73_V_read(ph_rank_3_73_V_read),
.rank_ex_74_V_read(ph_rank_3_74_V_read),
.rank_ex_75_V_read(ph_rank_3_75_V_read),
.rank_ex_76_V_read(ph_rank_3_76_V_read),
.rank_ex_77_V_read(ph_rank_3_77_V_read),
.rank_ex_78_V_read(ph_rank_3_78_V_read),
.rank_ex_79_V_read(ph_rank_3_79_V_read),
.rank_ex_80_V_read(ph_rank_3_80_V_read),
.rank_ex_81_V_read(ph_rank_3_81_V_read),
.rank_ex_82_V_read(ph_rank_3_82_V_read),
.rank_ex_83_V_read(ph_rank_3_83_V_read),
.rank_ex_84_V_read(ph_rank_3_84_V_read),
.rank_ex_85_V_read(ph_rank_3_85_V_read),
.rank_ex_86_V_read(ph_rank_3_86_V_read),
.rank_ex_87_V_read(ph_rank_3_87_V_read),
.rank_ex_88_V_read(ph_rank_3_88_V_read),
.rank_ex_89_V_read(ph_rank_3_89_V_read),
.rank_ex_90_V_read(ph_rank_3_90_V_read),
.rank_ex_91_V_read(ph_rank_3_91_V_read),
.rank_ex_92_V_read(ph_rank_3_92_V_read),
.rank_ex_93_V_read(ph_rank_3_93_V_read),
.rank_ex_94_V_read(ph_rank_3_94_V_read),
.rank_ex_95_V_read(ph_rank_3_95_V_read),
.rank_ex_96_V_read(ph_rank_3_96_V_read),
.rank_ex_97_V_read(ph_rank_3_97_V_read),
.rank_ex_98_V_read(ph_rank_3_98_V_read),
.rank_ex_99_V_read(ph_rank_3_99_V_read),
.rank_ex_100_V_read(ph_rank_3_100_V_read),
.rank_ex_101_V_read(ph_rank_3_101_V_read),
.rank_ex_102_V_read(ph_rank_3_102_V_read),
.rank_ex_103_V_read(ph_rank_3_103_V_read),
.rank_ex_104_V_read(ph_rank_3_104_V_read),
.rank_ex_105_V_read(ph_rank_3_105_V_read),
.rank_ex_106_V_read(ph_rank_3_106_V_read),
.rank_ex_107_V_read(ph_rank_3_107_V_read),
.rank_ex_108_V_read(ph_rank_3_108_V_read),
.rank_ex_109_V_read(ph_rank_3_109_V_read),
.rank_ex_110_V_read(ph_rank_3_110_V_read),
.rank_ex_111_V_read(ph_rank_3_111_V_read),
.rank_ex_112_V_read(ph_rank_3_112_V_read),
.rank_ex_113_V_read(ph_rank_3_113_V_read),
.rank_ex_114_V_read(ph_rank_3_114_V_read),
.rank_ex_115_V_read(ph_rank_3_115_V_read),
.rank_ex_116_V_read(ph_rank_3_116_V_read),
.rank_ex_117_V_read(ph_rank_3_117_V_read),
.rank_ex_118_V_read(ph_rank_3_118_V_read),
.rank_ex_119_V_read(ph_rank_3_119_V_read),
.rank_ex_120_V_read(ph_rank_3_120_V_read),
.rank_ex_121_V_read(ph_rank_3_121_V_read),
.ap_return_0(grp_sp_best3_fu_4676_ap_return_0),
.ap_return_1(grp_sp_best3_fu_4676_ap_return_1),
.ap_return_2(grp_sp_best3_fu_4676_ap_return_2),
.ap_return_3(grp_sp_best3_fu_4676_ap_return_3),
.ap_return_4(grp_sp_best3_fu_4676_ap_return_4),
.ap_return_5(grp_sp_best3_fu_4676_ap_return_5)
);
assign ap_return_0 = grp_sp_best3_fu_3932_ap_return_3;
assign ap_return_1 = grp_sp_best3_fu_3932_ap_return_4;
assign ap_return_10 = grp_sp_best3_fu_4676_ap_return_4;
assign ap_return_11 = grp_sp_best3_fu_4676_ap_return_5;
assign ap_return_12 = grp_sp_best3_fu_3932_ap_return_0;
assign ap_return_13 = grp_sp_best3_fu_3932_ap_return_1;
assign ap_return_14 = grp_sp_best3_fu_3932_ap_return_2;
assign ap_return_15 = grp_sp_best3_fu_4180_ap_return_0;
assign ap_return_16 = grp_sp_best3_fu_4180_ap_return_1;
assign ap_return_17 = grp_sp_best3_fu_4180_ap_return_2;
assign ap_return_18 = grp_sp_best3_fu_4428_ap_return_0;
assign ap_return_19 = grp_sp_best3_fu_4428_ap_return_1;
assign ap_return_2 = grp_sp_best3_fu_3932_ap_return_5;
assign ap_return_20 = grp_sp_best3_fu_4428_ap_return_2;
assign ap_return_21 = grp_sp_best3_fu_4676_ap_return_0;
assign ap_return_22 = grp_sp_best3_fu_4676_ap_return_1;
assign ap_return_23 = grp_sp_best3_fu_4676_ap_return_2;
assign ap_return_3 = grp_sp_best3_fu_4180_ap_return_3;
assign ap_return_4 = grp_sp_best3_fu_4180_ap_return_4;
assign ap_return_5 = grp_sp_best3_fu_4180_ap_return_5;
assign ap_return_6 = grp_sp_best3_fu_4428_ap_return_3;
assign ap_return_7 = grp_sp_best3_fu_4428_ap_return_4;
assign ap_return_8 = grp_sp_best3_fu_4428_ap_return_5;
assign ap_return_9 = grp_sp_best3_fu_4676_ap_return_3;
endmodule //sp_sort_sector
|
//-----------------------------------------------------
// PROYECTO 1 : SD HOST
// Archivo : probador.v
// Descripcion : generador de estimulos para el bloque de datos
// Estudiante : Mario Castresana Avendaño - A41267
//-----------------------------------------------------
module probador(
//señales para DATA_control
output reg CLK,
output reg RESET_L,
output reg writeRead_Regs_DATA,
output reg [3:0] blockCount_Regs_DATA,
output reg multipleData_Regs_DATA,
output reg timeout_Enable_Regs_DATA,
output reg [15:0] timeout_Reg_Regs_DATA,
output reg new_DAT_DMA_DATA,
output reg serial_Ready_Phy_DATA,
output reg timeout_Phy_DATA,
output reg complete_Phy_DATA,
output reg ack_IN_Phy_DATA,
output reg fifo_OK_FIFO_DATA
//señales para DATA_PHYSICAL
);
// Generar CLK
always
begin
#5 CLK= ! CLK;
end
//Generar pruebas
initial begin
//dumps
$dumpfile("testDATA.vcd");
$dumpvars(0,testbench);
// Initialize Inputs
CLK = 0;
new_DAT_DMA_DATA = 0;
serial_Ready_Phy_DATA = 0;
blockCount_Regs_DATA = 4'b1111; //procesar 15 bloques
timeout_Reg_Regs_DATA = 16'd100; //ciclos para timeout
writeRead_Regs_DATA = 1; // Escritura (leer del FIFO para pasar a SD)
multipleData_Regs_DATA = 0; //no es operacion multi trama
fifo_OK_FIFO_DATA = 0; //FIFO en espera
complete_Phy_DATA = 0;
ack_IN_Phy_DATA = 0;
//pulso de RESET_L
#50
RESET_L = 1;
#10
RESET_L = 0;
#30
RESET_L = 1;
//Aqui ya pasa a IDLE
$display("Aqui ya pasa a IDLE");
//pasamos a setting outputs
#50
new_DAT_DMA_DATA = 1;
$display("Aqui ya pasa a SETTING OUTPUTS");
#100
serial_Ready_Phy_DATA = 1;
//pasamos a checkear el FIFO
$display("Aqui ya pasa a Check FIFO");
//nos quedamos 50 ciclos en Check FIFO
#50
fifo_OK_FIFO_DATA = 1;
//pasamos al estado transmit
$display("Aqui ya pasa a transmit");
#50
//esperamos 50 ciclo en transmit y pasamos a ACK
complete_Phy_DATA = 1;
//aqui terminamos la transmicion mandando un ACK out a capa física
//y esperando un ACK in
#30
ack_IN_Phy_DATA = 1;
new_DAT_DMA_DATA = 0;
$display("De vuelta a IDLE");
#200
$display("-----FIN------");
$finish(2);
end
endmodule
|
/*
* phase_shift_check_tb.v: Test bench for phase_shift_check.v
* author: Till Mahlburg
* year: 2020
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 1000
`endif
`ifndef DESIRED_SHIFT
`define DESIRED_SHIFT 45
`endif
`ifndef CLK_PERIOD
`define CLK_PERIOD 20
`endif
module phase_shift_check_tb ();
reg rst;
reg clk;
wire clk_shifted;
reg LOCKED;
wire fail;
integer shift;
integer pass_count;
integer fail_count;
/* adjust according to the number of test cases */
localparam total = 4;
phase_shift_check dut (
.desired_shift_1000(`DESIRED_SHIFT * 1000),
.clk_period_1000(`CLK_PERIOD * 1000),
.clk_shifted(clk_shifted),
.clk(clk),
.rst(rst),
.LOCKED(LOCKED),
.fail(fail));
phase_shift ps (
.PWRDWN(1'b0),
.RST(rst),
.clk(clk),
.shift(shift),
.clk_period_1000(`CLK_PERIOD * 1000),
.duty_cycle(50),
.clk_shifted(clk_shifted));
initial begin
$dumpfile("phase_shift_check_tb.vcd");
$dumpvars(0, phase_shift_check_tb);
rst = 0;
shift = `DESIRED_SHIFT;
clk = 0;
LOCKED = 0;
pass_count = 0;
fail_count = 0;
#10;
rst = 1;
#10;
if (fail == 1'b0) begin
$display("PASSED: rst");
pass_count = pass_count + 1;
end else begin
$display("FAILED: rst");
fail_count = fail_count + 1;
end
rst = 0;
#(`CLK_PERIOD * 2);
if (fail == 1'b0) begin
$display("PASSED: LOCKED");
pass_count = pass_count + 1;
end else begin
$display("FAILED: LOCKED");
fail_count = fail_count + 1;
end
LOCKED = 1;
#`WAIT_INTERVAL;
if (fail == 1'b0) begin
$display("PASSED: shifts match");
pass_count = pass_count + 1;
end else begin
$display("FAILED: shifts match");
fail_count = fail_count + 1;
end
shift = shift + 45;
#`WAIT_INTERVAL;
if (fail == 1'b1) begin
$display("PASSED: shifts don't match");
pass_count = pass_count + 1;
end else begin
$display("FAILED: shifts don't match");
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
always #(`CLK_PERIOD / 2.0) clk <= ~clk;
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2010 www.xilinx.com
//
// XAPP xxx - 1:5 Differential Data De-serializer
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : serdes_1_to_5_diff_data.v
//
// Description : This module instantiates IODELAY2 and ISERDES2 primitives
// to receive TMDS differential data in 1:5 format
//
// Note:
//
// Author : Bob Feng
//////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module serdes_1_to_5_diff_data # (
parameter DIFF_TERM = "TRUE",
parameter SIM_TAP_DELAY = 50,
parameter BITSLIP_ENABLE = "FALSE"
)(
input wire use_phase_detector, // '1' enables the phase detector logic
input wire datain_p, // Input from LVDS receiver pin
input wire datain_n, // Input from LVDS receiver pin
input wire rxioclk, // IO Clock network
input wire rxserdesstrobe, // Parallel data capture strobe
input wire reset, // Reset line
input wire gclk, // Global clock
input wire bitslip, // Bitslip control line
output wire [4:0] data_out // Output data
);
wire ddly_m;
wire ddly_s;
wire busys;
wire rx_data_in;
wire cascade;
wire pd_edge;
reg [8:0] counter;
reg [3:0] state;
reg cal_data_sint;
wire busy_data;
reg busy_data_d;
wire cal_data_slave;
reg enable;
reg cal_data_master;
reg rst_data;
reg inc_data_int;
wire inc_data;
reg ce_data;
reg valid_data_d;
reg incdec_data_d;
reg [4:0] pdcounter;
wire valid_data;
wire incdec_data;
reg flag;
reg mux;
reg ce_data_inta ;
wire [1:0] incdec_data_or;
wire incdec_data_im;
wire [1:0] valid_data_or;
wire valid_data_im;
wire [1:0] busy_data_or;
wire all_ce;
wire [1:0] debug_in = 2'b00;
assign busy_data = busys ;
assign cal_data_slave = cal_data_sint ;
/////////////////////////////////////////////////
//
// IDELAY Calibration FSM
//
/////////////////////////////////////////////////
always @ (posedge gclk or posedge reset)
begin
if (reset == 1'b1) begin
state <= 0 ;
cal_data_master <= 1'b0 ;
cal_data_sint <= 1'b0 ;
counter <= 9'h000 ;
enable <= 1'b0 ;
mux <= 1'h1 ;
end
else begin
counter <= counter + 9'h001 ;
if (counter[8] == 1'b1) begin
counter <= 9'h000 ;
end
if (counter[5] == 1'b1) begin
enable <= 1'b1 ;
end
if (state == 0 && enable == 1'b1) begin // Wait for IODELAY to be available
cal_data_master <= 1'b0 ;
cal_data_sint <= 1'b0 ;
rst_data <= 1'b0 ;
if (busy_data_d == 1'b0) begin
state <= 1 ;
end
end
else if (state == 1) begin // Issue calibrate command to both master and slave, needed for simulation, not for the silicon
cal_data_master <= 1'b1 ;
cal_data_sint <= 1'b1 ;
if (busy_data_d == 1'b1) begin // and wait for command to be accepted
state <= 2 ;
end
end
else if (state == 2) begin // Now RST master and slave IODELAYs needed for simulation, not for the silicon
cal_data_master <= 1'b0 ;
cal_data_sint <= 1'b0 ;
if (busy_data_d == 1'b0) begin
rst_data <= 1'b1 ;
state <= 3 ;
end
end
else if (state == 3) begin // Wait for IODELAY to be available
rst_data <= 1'b0 ;
if (busy_data_d == 1'b0) begin
state <= 4 ;
end
end
else if (state == 4) begin // Wait for occasional enable
if (counter[8] == 1'b1) begin
state <= 5 ;
end
end
else if (state == 5) begin // Calibrate slave only
if (busy_data_d == 1'b0) begin
cal_data_sint <= 1'b1 ;
state <= 6 ;
end
end
else if (state == 6) begin // Wait for command to be accepted
cal_data_sint <= 1'b0 ;
if (busy_data_d == 1'b1) begin
state <= 7 ;
end
end
else if (state == 7) begin // Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= 1'b0 ;
if (busy_data_d == 1'b0) begin
state <= 4 ;
end
end
end
end
always @ (posedge gclk or posedge reset) // Per-bit phase detection state machine
begin
if (reset == 1'b1) begin
pdcounter <= 5'b1000 ;
ce_data_inta <= 1'b0 ;
flag <= 1'b0 ; // flag is there to only allow one inc or dec per cal (test)
end
else begin
busy_data_d <= busy_data_or[1] ;
if (use_phase_detector == 1'b1) begin // decide whther pd is used
incdec_data_d <= incdec_data_or[1] ;
valid_data_d <= valid_data_or[1] ;
if (ce_data_inta == 1'b1) begin
ce_data = mux ;
end
else begin
ce_data = 64'h0000000000000000 ;
end
if (state == 7) begin
flag <= 1'b0 ;
end
else if (state != 4 || busy_data_d == 1'b1) begin // Reset filter if state machine issues a cal command or unit is busy
pdcounter <= 5'b10000 ;
ce_data_inta <= 1'b0 ;
end
else if (pdcounter == 5'b11111 && flag == 1'b0) begin // Filter has reached positive max - increment the tap count
ce_data_inta <= 1'b1 ;
inc_data_int <= 1'b1 ;
pdcounter <= 5'b10000 ;
flag <= 1'b1 ;
end
else if (pdcounter == 5'b00000 && flag == 1'b0) begin // Filter has reached negative max - decrement the tap count
ce_data_inta <= 1'b1 ;
inc_data_int <= 1'b0 ;
pdcounter <= 5'b10000 ;
flag <= 1'b1 ;
end
else if (valid_data_d == 1'b1) begin // increment filter
ce_data_inta <= 1'b0 ;
if (incdec_data_d == 1'b1 && pdcounter != 5'b11111) begin
pdcounter <= pdcounter + 5'b00001 ;
end
else if (incdec_data_d == 1'b0 && pdcounter != 5'b00000) begin // decrement filter
pdcounter <= pdcounter + 5'b11111 ;
end
end
else begin
ce_data_inta <= 1'b0 ;
end
end
else begin
ce_data = all_ce ;
inc_data_int <= debug_in[1] ;
end
end
end
assign inc_data = inc_data_int ;
assign incdec_data_or[0] = 1'b0 ; // Input Mux - Initialise generate loop OR gates
assign valid_data_or[0] = 1'b0 ;
assign busy_data_or[0] = 1'b0 ;
assign incdec_data_im = incdec_data & mux; // Input muxes
assign incdec_data_or[1] = incdec_data_im | incdec_data_or; // AND gates to allow just one signal through at a tome
assign valid_data_im = valid_data & mux; // followed by an OR
assign valid_data_or[1] = valid_data_im | valid_data_or; // for the three inputs from each PD
assign busy_data_or[1] = busy_data | busy_data_or; // The busy signals just need an OR gate
assign all_ce = debug_in[0] ;
IBUFDS #(
.DIFF_TERM (DIFF_TERM))
data_in (
.I (datain_p),
.IB (datain_n),
.O (rx_data_in)
);
//
// Master IDELAY
//
IODELAY2 #(
.DATA_RATE ("SDR"),
.IDELAY_VALUE (0),
.IDELAY2_VALUE (0),
.IDELAY_MODE ("NORMAL" ),
.ODELAY_VALUE (0),
.IDELAY_TYPE ("DIFF_PHASE_DETECTOR"),
.COUNTER_WRAPAROUND ("STAY_AT_LIMIT"), //("WRAPAROUND"),
.DELAY_SRC ("IDATAIN"),
.SERDES_MODE ("MASTER"),
.SIM_TAPDELAY_VALUE (SIM_TAP_DELAY)
) iodelay_m (
.IDATAIN (rx_data_in), // data from IBUFDS
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_m), // Output data 1 to ILOGIC/ISERDES2
.DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2
.IOCLK0 (rxioclk), // High speed clock for calibration
.IOCLK1 (1'b0), // High speed clock for calibration
.CLK (gclk), // Fabric clock (GCLK) for control signals
.CAL (cal_data_master), // Calibrate control signal
.INC (inc_data), // Increment counter
.CE (ce_data), // Clock Enable
.RST (rst_data), // Reset delay line
.BUSY () // output signal indicating sync circuit has finished / calibration has finished
);
//
// Slave IDELAY
//
IODELAY2 #(
.DATA_RATE ("SDR"),
.IDELAY_VALUE (0),
.IDELAY2_VALUE (0),
.IDELAY_MODE ("NORMAL" ),
.ODELAY_VALUE (0),
.IDELAY_TYPE ("DIFF_PHASE_DETECTOR"),
.COUNTER_WRAPAROUND ("WRAPAROUND"),
.DELAY_SRC ("IDATAIN"),
.SERDES_MODE ("SLAVE"),
.SIM_TAPDELAY_VALUE (SIM_TAP_DELAY)
) iodelay_s (
.IDATAIN (rx_data_in), // data from IBUFDS
.TOUT (), // tri-state signal to IOB
.DOUT (), // output data to IOB
.T (1'b1), // tri-state control from OLOGIC/OSERDES2
.ODATAIN (1'b0), // data from OLOGIC/OSERDES2
.DATAOUT (ddly_s), // Slave output data to ILOGIC/ISERDES2
.DATAOUT2 (), //
.IOCLK0 (rxioclk), // High speed IO clock for calibration
.IOCLK1 (1'b0),
.CLK (gclk), // Fabric clock (GCLK) for control signals
.CAL (cal_data_slave), // Calibrate control signal
.INC (inc_data), // Increment counter
.CE (ce_data), // Clock Enable
.RST (rst_data), // Reset delay line
.BUSY (busys) // output signal indicating sync circuit has finished / calibration has finished
);
//
// Master ISERDES
//
ISERDES2 #(
.DATA_WIDTH (5),
.DATA_RATE ("SDR"),
.BITSLIP_ENABLE (BITSLIP_ENABLE),
.SERDES_MODE ("MASTER"),
.INTERFACE_TYPE ("RETIMED"))
iserdes_m (
.D (ddly_m),
.CE0 (1'b1),
.CLK0 (rxioclk),
.CLK1 (1'b0),
.IOCE (rxserdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.SHIFTIN (pd_edge),
.BITSLIP (bitslip),
.FABRICOUT (),
.Q4 (data_out[0]),
.Q3 (data_out[1]),
.Q2 (data_out[2]),
.Q1 (data_out[3]),
.DFB (),
.CFB0 (),
.CFB1 (),
.VALID (valid_data),
.INCDEC (incdec_data),
.SHIFTOUT (cascade));
//
// Slave ISERDES
//
ISERDES2 #(
.DATA_WIDTH (5),
.DATA_RATE ("SDR"),
.BITSLIP_ENABLE (BITSLIP_ENABLE),
.SERDES_MODE ("SLAVE"),
.INTERFACE_TYPE ("RETIMED")
) iserdes_s (
.D (ddly_s),
.CE0 (1'b1),
.CLK0 (rxioclk),
.CLK1 (1'b0),
.IOCE (rxserdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.SHIFTIN (cascade),
.BITSLIP (bitslip),
.FABRICOUT (),
.Q4 (data_out[4]),
.Q3 (),
.Q2 (),
.Q1 (),
.DFB (),
.CFB0 (),
.CFB1 (),
.VALID (),
.INCDEC (),
.SHIFTOUT (pd_edge));
reg [7:0] rxpdcntr = 8'h7f;
always @ (posedge gclk or posedge reset) begin
if (reset)
rxpdcntr <= 8'h7f;
else if (ce_data)
if (inc_data)
rxpdcntr <= rxpdcntr + 1'b1;
else
rxpdcntr <= rxpdcntr - 1'b1;
end
endmodule
|
/* This file is part of jt12.
jt12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
jt12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with jt12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 25-2-2017
*/
/*
Does the LFO frequency depend on the pre-scaler for YM2608 ?
From spritesmind.net:
"That would be 7-bit LFO step counter (which is incremented on each LFO clock and reset when LFO enable bit is cleared).
LFO AM value indeed corresponds to LFO step counter bits 0:5 shifted left by one
and XORed with inversion of bit 6 (to generate an inverted triangle waveform)
LFO AM sensitivity (2 bits) indicates to EG how much LFO AM value is shifted before adding to EG output
[...]
LFO PM step (0-31), which takes bits 2:6 of LFO step counter (0-127) and goes to LFO PM calcuation unit
"
From Sauraen:
The LFO seems to have 3 sections:
[*] 7-bit linear prescaler. The test bit 0x21:1 goes into what looks like the carry-in or something similar;
it could go into the reset, I can't quite tell with more detailed analysis. The 7-bit output (plus maybe carry-out)
gets logiced together into 8 lines (evidently perform "== N" with N hardcoded for each line), and these go into a
little selector unit which is also fed by the LFO Speed and LFO Enable bits. I can't quite see the output of this,
but I do see there's some sort of feedback to the prescaler's reset. So this clearly seems like a divide-by-N prescaler.
I can try to read the eight N's for you if you want, but you should be able to reverse engineer them from knowing what the LFO speeds are.
[*] 7-bit linear counter, with an 8-bit unit after the output (possibly inverts the output after each cycle to make a triangle wave?).
Bits 1:6 of the output of this go to the EG, and stick into its pipeline at the same place where the LFO->Amplitude two bits go.
(Elsewhere the operator LFO enable flag simply forces these two bits to zero for operators not affected by the LFO.)
Some modified version of the 8-bit signal between the counter and the inverter unit thing goes to the third unit of the LFO.
[*] Highly complex unit which modifies the frequency data as it goes from the channel registers to the PG. The block bits bypass this,
but all the frequency bits get modified by it. There's a bitslice portion corresponding to bits 0:6, and then what appears to be
the same logic folded over to process bits 7:A. But the interesting part is that bits 4:A of the frequency data go into the
bitslices 0:6. That is, the bitslice unit for bit 0 has bit 0 enter at the middle and leave (to the PG) at the bottom. But it also has bit 4 enter at the top.
And so on through bit 6 having bit A enter at the top. It looks like the top portion is some sort of shifter for bits 4:A--the wires go diagonally
so that bit 4 only gets used once, bit 5 gets used in bitslice 1 and 0, bit 6 gets used in bitslices 2:0, and so on so that bit A gets used in all of them.
I'm guessing this whole unit is basically a multiplier, multiplying bits 4:A of the frequency value by bits 0:7 of the LFO state, and then adding the result
to bits 0:6 of the frequency value (with carry up to the higher bits). It looks like, between the multiplied output and the adder, there's another shifter
whose value is based on the the LFO->Frequency bits. But it looks like it's a bit more complex than I'm describing.
*/
module jt12_lfo(
input rst,
input clk,
input clk_en,
input zero,
input lfo_rst,
input lfo_en,
input [2:0] lfo_freq,
output reg [6:0] lfo_mod // 7-bit width according to spritesmind.net
);
reg [6:0] cnt, limit;
always @(*)
case( lfo_freq ) // same values as in MAME
3'd0: limit = 7'd108;
3'd1: limit = 7'd77;
3'd2: limit = 7'd71;
3'd3: limit = 7'd67;
3'd4: limit = 7'd62;
3'd5: limit = 7'd44;
3'd6: limit = 7'd8;
3'd7: limit = 7'd5;
endcase
always @(posedge clk)
if( rst || !lfo_en )
{ lfo_mod, cnt } <= 14'd0;
else if( clk_en && zero) begin
if( cnt == limit ) begin
cnt <= 7'd0;
lfo_mod <= lfo_mod + 1'b1;
end
else begin
cnt <= cnt + 1'b1;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:02:16 11/19/2013
// Design Name:
// Module Name: fsm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fsm(input clock, input reset, input pad_touched, output reg play);
//Definimos los estados de la FSM
parameter STATE_0 = 0;
parameter STATE_1 = 1;
parameter STATE_2 = 2;
parameter STATE_3 = 3;
//Estado en que se encuentra actualmente
reg [2:0] state;
initial
begin
state <= 0;
play <= 1'b0;
end
always@(posedge clock or posedge reset)
begin
if(reset)
begin
state <= STATE_0;
play <= 1'b0;
end
else
begin
case(state)
STATE_0:
begin
if(pad_touched)
state <= STATE_1;
else
state <= STATE_0;
end
STATE_1:
begin
play <= 1'b1;
state <= STATE_2;
end
STATE_2:
begin
if(pad_touched)
state <= STATE_2;
else
state <= STATE_3;
end
STATE_3:
begin
play <= 1'b0;
state <= STATE_0;
end
default:
begin
state <= STATE_0;
end
endcase
end //end del begin antes del case
end //end del always
endmodule
|
// soc_system_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1 162 at 2014.01.24.12:33:37
`timescale 1 ps / 1 ps
module soc_system_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim0_inst_CLK, // .hps_io_spim0_inst_CLK
output wire hps_io_spim0_inst_MOSI, // .hps_io_spim0_inst_MOSI
input wire hps_io_spim0_inst_MISO, // .hps_io_spim0_inst_MISO
output wire hps_io_spim0_inst_SS0, // .hps_io_spim0_inst_SS0
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO00, // .hps_io_gpio_inst_GPIO00
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO55, // .hps_io_gpio_inst_GPIO55
inout wire hps_io_gpio_inst_GPIO56, // .hps_io_gpio_inst_GPIO56
inout wire hps_io_gpio_inst_GPIO61, // .hps_io_gpio_inst_GPIO61
inout wire hps_io_gpio_inst_GPIO62 // .hps_io_gpio_inst_GPIO62
);
soc_system_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim0_inst_CLK (hps_io_spim0_inst_CLK), // .hps_io_spim0_inst_CLK
.hps_io_spim0_inst_MOSI (hps_io_spim0_inst_MOSI), // .hps_io_spim0_inst_MOSI
.hps_io_spim0_inst_MISO (hps_io_spim0_inst_MISO), // .hps_io_spim0_inst_MISO
.hps_io_spim0_inst_SS0 (hps_io_spim0_inst_SS0), // .hps_io_spim0_inst_SS0
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO00 (hps_io_gpio_inst_GPIO00), // .hps_io_gpio_inst_GPIO00
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO48 (hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO55 (hps_io_gpio_inst_GPIO55), // .hps_io_gpio_inst_GPIO55
.hps_io_gpio_inst_GPIO56 (hps_io_gpio_inst_GPIO56), // .hps_io_gpio_inst_GPIO56
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61), // .hps_io_gpio_inst_GPIO61
.hps_io_gpio_inst_GPIO62 (hps_io_gpio_inst_GPIO62) // .hps_io_gpio_inst_GPIO62
);
endmodule
|
//
// fixed for 9.1 jan 21 2010 cruben
//
`include "timescale.v"
`include "i2c_master_defines.v"
module i2c_opencores
(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, /*wb_cyc_i,*/ wb_ack_o, wb_inta_o,
sda_pad_in, sda_pad_out , sda_pad_en, scl_pad_in, scl_pad_out, scl_pad_en
);
// Common bus signals
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
// Slave signals
input [2:0] wb_adr_i; // WISHBONE address input
input [7:0] wb_dat_i; // WISHBONE data input
output [7:0] wb_dat_o; // WISHBONE data output
input wb_we_i; // WISHBONE write enable input
input wb_stb_i; // WISHBONE strobe input
//input wb_cyc_i; // WISHBONE cycle input
output wb_ack_o; // WISHBONE acknowledge output
output wb_inta_o; // WISHBONE interrupt output
// I2C signals
input sda_pad_in;
input scl_pad_in;
output sda_pad_out;
output scl_pad_out;
output sda_pad_en;
output scl_pad_en;
wire wb_cyc_i; // WISHBONE cycle input
// Wire tri-state scl/sda
wire scl_pad_i;
wire scl_pad_o;
wire scl_padoen_o;
wire sda_pad_i;
wire sda_pad_o;
wire sda_padoen_o;
assign wb_cyc_i = wb_stb_i;
assign scl_pad_i = scl_pad_in;
assign sda_pad_i = sda_pad_in;
assign sda_pad_out = sda_pad_o;
assign scl_pad_out = scl_pad_o;
assign sda_pad_en = sda_padoen_o;
assign scl_pad_en = scl_padoen_o;
// Avalon doesn't have an asynchronous reset
// set it to be inactive and just use synchronous reset
// reset level is a parameter, 0 is the default (active-low reset)
wire arst_i;
assign arst_i = 1'b1;
// Connect the top level I2C core
i2c_master_top i2c_master_top_inst
(
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .arst_i(arst_i),
.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), .wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o)
);
endmodule
|
`timescale 1ns / 1ps
//Test Multiplicador de 32 bits con signo
module TestMultiplicador;
//Inputs
reg [31:0] a;
reg [31:0] b;
//Outputs
wire [31:0] Z;
wire ovf;
//Unit under test
Multiplicador uut(
.a(a),
.b(b),
.Z(Z),
.ovf(ovf)
);
initial begin
a = 32'b0;
b = 32'b0;
#100;
a = 32'h0; b = 32'h0; //0 * 0
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h0; b = 32'h80000000; //0 * -0
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h80000000; b = 32'h0; //-0 * 0
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h400; b = 32'h400; //1 * 1
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h400; b = 32'h80000400; //1 * -1
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h80000400; b = 32'h80000400; //-1 * -1
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h200; b = 32'h400; //.1 * 1
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h508; b = 32'h989680; //1.0100001 * 10011000100101.101
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'hA8D99763; b = 32'hDE6D23E4; //-10100011011001100101.1101100011 * -101111001101101001000.11111001
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h28D99763; b = 32'h5E6D23E4; //10100011011001100101.1101100011 * 101111001101101001000.11111001
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'hB2EF5901; b = 32'h35905D0E; //-11001011101111010110.0100000001 * 11010110010000010111.010000111
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h8000AA89; b = 32'h985; //-101010.1010001001 * 10.0110000101
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h7CDC; b = 32'h11D; //11111.0011011100 * 00.0100011101
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
a = 32'h6ECABB; b = 32'hDBF; //1101110110010.1010111011 * 11.0110111111
#50;
$display("Z = %b %b.%b, ovf = %b", Z[31], Z[30:10], Z[9:0], ovf);
end
endmodule
|
// Logic to map a doorway lighting region's LED pixels to LCD pixels.
// Copyright (c) 2013 Jared Boone, ShareBrained Technology, Inc.
//
// This file is part of the Medusa project.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
module map_door (
input pixel_clk_i,
input [11:0] pixel_x_i,
input [11:0] pixel_y_i,
input pixel_valid_i,
output reg [9:0] led_strip_address_o,
output led_strip_address_valid_o
);
//parameter VSYNC_VBI_LINE_COUNT = 29; // good for 24-bit color mode?
parameter VSYNC_VBI_LINE_COUNT = 16; // good for 16-bit color mode?
parameter X_V1;
parameter X_V2;
parameter Y_V;
parameter X_H;
parameter Y_H;
parameter V_LEN = 127;
parameter H_LEN = 65;
parameter X1 = X_V1;
parameter Y1_START = Y_V + VSYNC_VBI_LINE_COUNT;
parameter Y1_END = Y1_START + V_LEN;
parameter X2_START = X_H;
parameter X2_END = X2_START + H_LEN;
parameter Y2 = Y_H + VSYNC_VBI_LINE_COUNT;
parameter X3 = X_V2;
parameter Y3_START = Y_V + VSYNC_VBI_LINE_COUNT;
parameter Y3_END = Y3_START + V_LEN;
wire zone1_enable = (pixel_x_i == X1) && (pixel_y_i >= Y1_START) && (pixel_y_i < Y1_END);
wire [9:0] zone1_address = V_LEN - (pixel_y_i - Y1_START + (0));
wire zone2_enable = (pixel_y_i == Y2) && (pixel_x_i >= X2_START) && (pixel_x_i < X2_END);
wire [9:0] zone2_address = pixel_x_i - X2_START + (V_LEN);
wire zone3_enable = (pixel_x_i == X3) && (pixel_y_i >= Y3_START) && (pixel_y_i < Y3_END);
wire [9:0] zone3_address = pixel_y_i - Y3_START + (H_LEN + V_LEN);
wire zone_enable = zone1_enable || zone2_enable || zone3_enable;
assign led_strip_address_valid_o = pixel_valid_i && zone_enable;
always @(zone1_enable or zone2_enable or zone3_enable or zone1_address or zone2_address or zone3_address) begin
if (zone3_enable) begin
led_strip_address_o = zone3_address;
end
else if (zone2_enable) begin
led_strip_address_o = zone2_address;
end
else begin
led_strip_address_o = zone1_address;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A311O_PP_BLACKBOX_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_PP_BLACKBOX_V
|
(* Copyright (c) 2009-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import DepList Cpdt.CpdtTactics.
Require Extraction.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** printing $ %({}*% #(<a/>*# *)
(** printing ^ %*{})% #*<a/>)# *)
(*
(** %\chapter{Universes and Axioms}% *)
*)
(** %\chapter{宇宙と公理}% *)
(**
(** Many traditional theorems can be proved in Coq without special knowledge of CIC, the logic behind the prover. A development just seems to be using a particular ASCII notation for standard formulas based on %\index{set theory}%set theory. Nonetheless, as we saw in Chapter 4, CIC differs from set theory in starting from fewer orthogonal primitives. It is possible to define the usual logical connectives as derived notions. The foundation of it all is a dependently typed functional programming language, based on dependent function types and inductive type families. By using the facilities of this language directly, we can accomplish some things much more easily than in mainstream math.
%\index{Gallina}%Gallina, which adds features to the more theoretical CIC%~\cite{CIC}%, is the logic implemented in Coq. It has a relatively simple foundation that can be defined rigorously in a page or two of formal proof rules. Still, there are some important subtleties that have practical ramifications. This chapter focuses on those subtleties, avoiding formal metatheory in favor of example code. *)
*)
(**
多くの伝統的な定理は CIC (Coq の背後にある論理体系) の特別な知識を用いずに Coq で証明できます。証明の開発が、%\index{集合論}%集合論に基づく標準的な論理式のための特別な ASCII 記法を用いることであるように思えるかもしれません。それでもやはり、4章で見たように、 CIC はより少ない直交するプリミティブで始まるという点で集合論とは異なります。通常の論理結合子は派生的な概念として定義できます。それらすべての基礎は依存型のついた関数型言語であり、依存関数型と帰納型の族に基づいています。これらの言語機能を直接的に用いれば、いくつかのことを主流の数学より簡単に達成できます。
%\index{Gallina}%Gallina は Coq に実装された論理体系であり、より理論的な CIC%~\cite{CIC}% に機能を追加しています。Gallina は1,2ページの形式的な証明規則で厳密に定義された比較的単純な基礎を持っています。それでも、実際的な影響を及ぼすいくつかの重要な細部があります。本章では、形式的なメタ理論は避け、コード例によりこれらの細部に焦点を合わせます。
*)
(*
(** * The [Type] Hierarchy *)
*)
(** * [Type] の階層 *)
(**
(** %\index{type hierarchy}%Every object in Gallina has a type. *)
*)
(** %\index{型階層}%Gallina におけるすべてのオブジェクトは型を持ちます。*)
Check 0.
(**
(** %\vspace{-.15in}% [[
0
: nat
]]
It is natural enough that zero be considered as a natural number. *)
*)
(** %\vspace{-.15in}% [[
0
: nat
]]
ゼロが自然数であると考えるのはごく自然なことです。 *)
Check nat.
(**
(** %\vspace{-.15in}% [[
nat
: Set
]]
From a set theory perspective, it is unsurprising to consider the natural numbers as a "set." *)
*)
(** %\vspace{-.15in}% [[
nat
: Set
]]
集合論の観点では、自然数の集まりが「集合」であるとみなすのは意外ではありません。*)
Check Set.
(**
(** %\vspace{-.15in}% [[
Set
: Type
]]
The type [Set] may be considered as the set of all sets, a concept that set theory handles in terms of%\index{class (in set theory)}% _classes_. In Coq, this more general notion is [Type]. *)
*)
(** %\vspace{-.15in}% [[
Set
: Type
]]
型 [Set] はすべての集合の集合、つまり集合論では%\index{クラス (集合論)}% _クラス_ という用語で表される概念と見なせます。 この、より一般的な概念は、 Coq においては [Type] です。 *)
Check Type.
(**
(** %\vspace{-.15in}% [[
Type
: Type
]]
Strangely enough, [Type] appears to be its own type. It is known that polymorphic languages with this property are inconsistent, via %\index{Girard's paradox}%Girard's paradox%~\cite{GirardsParadox}%. That is, using such a language to encode proofs is unwise, because it is possible to "prove" any proposition. What is really going on here?
Let us repeat some of our queries after toggling a flag related to Coq's printing behavior.%\index{Vernacular commands!Set Printing Universes}% *)
*)
(** %\vspace{-.15in}% [[
Type
: Type
]]
おかしなことに、[Type] はそれ自身の型であるようです。この性質を持つ多相的な言語は、%\index{ジラールのパラドックス}%ジラールのパラドックス%~\cite{GirardsParadox}% により矛盾することが知られています。 つまり、そのような言語で証明をエンコードするのは愚かなことです。なぜならどんな命題も「証明」できるからです。実のところ、ここでは何が起こっているのでしょう？
これらのクエリーをCoqの印字動作に関わるフラグ%\index{Vernacular commands!Set Printing Universes}%をトグルしてから再度入力してみましょう。 *)
Set Printing Universes.
Check nat.
(** %\vspace{-.15in}% [[
nat
: Set
]]
*)
Check Set.
(** %\vspace{-.15in}% [[
Set
: Type $ (0)+1 ^
]]
*)
Check Type.
(**
(** %\vspace{-.15in}% [[
Type $ Top.3 ^
: Type $ (Top.3)+1 ^
]]
Occurrences of [Type] are annotated with some additional information, inside comments. These annotations have to do with the secret behind [Type]: it really stands for an infinite hierarchy of types. The type of [Set] is [Type(0)], the type of [Type(0)] is [Type(1)], the type of [Type(1)] is [Type(2)], and so on. This is how we avoid the "[Type : Type]" paradox. As a convenience, the universe hierarchy drives Coq's one variety of subtyping. Any term whose type is [Type] at level [i] is automatically also described by [Type] at level [j] when [j > i].
In the outputs of our first [Check] query, we see that the type level of [Set]'s type is [(0)+1]. Here [0] stands for the level of [Set], and we increment it to arrive at the level that _classifies_ [Set].
In the third query's output, we see that the occurrence of [Type] that we check is assigned a fresh%\index{universe variable}% _universe variable_ [Top.3]. The output type increments [Top.3] to move up a level in the universe hierarchy. As we write code that uses definitions whose types mention universe variables, unification may refine the values of those variables. Luckily, the user rarely has to worry about the details.
Another crucial concept in CIC is%\index{predicativity}% _predicativity_. Consider these queries. *)
*)
(** %\vspace{-.15in}% [[
Type $ Top.3 ^
: Type $ (Top.3)+1 ^
]]
[Type] の出現が、コメントの中において追加の情報で注釈されています。これらの注釈は [Type] の背景にある秘密と関係があります。これは型の無限の階層を表しているのです。[Set] の型は [Type(0)]、[Type(0)] の型は [Type(1)]、[Type(1)] の型は [Type(2)] などです。このようにして "[Type : Type]" パラドックスを回避しています。利便性のため、この宇宙(universe)の階層は Coq における一種の部分型付けを利用しています。型がレベル [i] における [Type] である任意の項は、[j > i] であるレベル [j] における [Type] でも自動的に説明(FIXME:describe)されます。
最初の [Check] クエリの出力において、 [Set] の型の型レベルは [(0)+1] であるとわかります。ここで [0] は [Set] のレベルであり、これをインクリメントすると [Set] を _分類(classify)する_ レベルに到達します。
三番目のクエリの出力においては、ここで調べた [Type] の出現にはフレッシュな%\index{宇宙変数(universe variable)}% _宇宙変数(universe variable)_ [Top.3] が割り当てられています。出力された型は [Top.3] をインクリメントすることで宇宙の階層を１レベル上に移動しています。型が宇宙変数に言及する定義を用いたコードを書くときには、単一化によりこれらの変数の値が詳細化されることがあります。幸運にも、利用者はこの詳細を気にする必要はほとんどありません。
CIC におけるもう一つの重要な概念は%\index{可述性}% _可述性_ です。次のクエリについて考えてみましょう。*)
Check forall T : nat, fin T.
(** %\vspace{-.15in}% [[
forall T : nat, fin T
: Set
]]
*)
Check forall T : Set, T.
(** %\vspace{-.15in}% [[
forall T : Set, T
: Type $ max(0, (0)+1) ^
]]
*)
Check forall T : Type, T.
(**
(** %\vspace{-.15in}% [[
forall T : Type $ Top.9 ^ , T
: Type $ max(Top.9, (Top.9)+1) ^
]]
These outputs demonstrate the rule for determining which universe a [forall] type lives in. In particular, for a type [forall x : T1, T2], we take the maximum of the universes of [T1] and [T2]. In the first example query, both [T1] ([nat]) and [T2] ([fin T]) are in [Set], so the [forall] type is in [Set], too. In the second query, [T1] is [Set], which is at level [(0)+1]; and [T2] is [T], which is at level [0]. Thus, the [forall] exists at the maximum of these two levels. The third example illustrates the same outcome, where we replace [Set] with an occurrence of [Type] that is assigned universe variable [Top.9]. This universe variable appears in the places where [0] appeared in the previous query.
The behind-the-scenes manipulation of universe variables gives us predicativity. Consider this simple definition of a polymorphic identity function, where the first argument [T] will automatically be marked as implicit, since it can be inferred from the type of the second argument [x]. *)
*)
(** %\vspace{-.15in}% [[
forall T : Type $ Top.9 ^ , T
: Type $ max(Top.9, (Top.9)+1) ^
]]
これらの出力は [forall] 型がどの宇宙にあるか決定するための規則を実演しています。特に、型 [forall x : T1, T2] について、[T1] と [T2] の宇宙の最大値をを取っています。最初のクエリ例では、[T1] ([nat]) と [T2] ([fin T]) は [Set] にあるため、[forall] 型も同様に [Set] にあります。二つ目のクエリでは、[T1] は [Set] であり、レベル [(0)+1] にあります。[T2] は [T] であり、レベルは [0] です。従って、この [forall] はこれら二つのレベルの最大値のレベルに存在します。三番目の例も同様の結論を示しており、ここでは [Set] を宇宙変数 [Top.9] に割り当てられた [Type] の出現で置き換えています。この宇宙変数は以前のクエリに現れた [0] の位置に現れています。
宇宙変数の舞台裏における操作が可述性をもたらします。次の多相的な恒等関数の単純な定義を考えてみましょう。ここで最初の引数 [T] は二番目の引数 [x] の型から推論できるため、自動的に暗黙であるとマークされます。 *)
Definition id (T : Set) (x : T) : T := x.
Check id 0.
(**
(** %\vspace{-.15in}% [[
id 0
: nat
Check id Set.
]]
<<
Error: Illegal application (Type Error):
...
The 1st term has type "Type (* (Top.15)+1 *)"
which should be coercible to "Set".
>>
The parameter [T] of [id] must be instantiated with a [Set]. The type [nat] is a [Set], but [Set] is not. We can try fixing the problem by generalizing our definition of [id]. *)
*)
(** %\vspace{-.15in}% [[
id 0
: nat
Check id Set.
]]
<<
Error: Illegal application (Type Error):
...
The 1st term has type "Type ( * (Top.15)+1 * )"
which should be coercible to "Set".
>>
(FIXME: 上の (Top.15)+1 を囲むコメントのところでエラーになるので少し変えている)
[id] の 引数 [T] は [Set] で具体化されなければなりません。型 [nat] は [Set] ですが、 [Set] は違います。この問題は [id] の定義を一般化して、修正を試みることができます。 *)
Reset id.
Definition id (T : Type) (x : T) : T := x.
Check id 0.
(** %\vspace{-.15in}% [[
id 0
: nat
]]
*)
Check id Set.
(** %\vspace{-.15in}% [[
id Set
: Type $ Top.17 ^
]]
*)
Check id Type.
(** %\vspace{-.15in}% [[
id Type $ Top.18 ^
: Type $ Top.19 ^
]]
*)
(**
(** So far so good. As we apply [id] to different [T] values, the inferred index for [T]'s [Type] occurrence automatically moves higher up the type hierarchy.
[[
Check id id.
]]
<<
Error: Universe inconsistency (cannot enforce Top.16 < Top.16).
>>
%\index{universe inconsistency}%This error message reminds us that the universe variable for [T] still exists, even though it is usually hidden. To apply [id] to itself, that variable would need to be less than itself in the type hierarchy. Universe inconsistency error messages announce cases like this one where a term could only type-check by violating an implied constraint over universe variables. Such errors demonstrate that [Type] is _predicative_, where this word has a CIC meaning closely related to its usual mathematical meaning. A predicative system enforces the constraint that, when an object is defined using some sort of quantifier, none of the quantifiers may ever be instantiated with the object itself. %\index{impredicativity}%Impredicativity is associated with popular paradoxes in set theory, involving inconsistent constructions like "the set of all sets that do not contain themselves" (%\index{Russell's paradox}%Russell's paradox). Similar paradoxes would result from uncontrolled impredicativity in Coq. *)
*)
(** ここまではこれで良いようです。[id] を異なる値 [T] に適用するに従って、[T] の [Type] の出現で推論されたインデックスは自動的に型階層を高い方へと昇っています。
[[
Check id id.
]]
<<
Error: Universe inconsistency (cannot enforce Top.16 < Top.16).
>>
%\index{宇宙の矛盾(universe inconsistency)}%このエラーメッセージは [T] に関する宇宙変数が、普通は隠されているものの、依然として存在していることを思い出させます。[id] をそれ自身に適用するには、この変数が型階層においてそれ自身よりも小さくある必要があります。宇宙の矛盾(universe inconsistency) エラーはこのような、項が宇宙変数に関して導かれた制約に違反することでしか型検査が通らない場合について知らせてくれます。このようなエラーは [Type] が _可述的_ であることを示しています。ここで CIC における可述性の意味は、通常の数学での意味にごく近いです。可述性をもつ系は、あるオブジェクトがある種の限量子を用いて定義されたとき、どの限量子もそのオブジェクトそれ自体で具体化されてはならないという制約を強制します。%\index{非可述性}%非可述性は集合論においてよく知られたパラドックスと関連しており、「それ自体を含まない全ての集合の集合」のような矛盾する構成を伴います (%\index{ラッセルのパラドックス}%ラッセルのパラドックス)。 Coq においても、非可述性を制御しないと類似のパラドックスがもたらされます。 *)
(*
(** ** Inductive Definitions *)
*)
(** ** 帰納的定義 *)
(**
(** Predicativity restrictions also apply to inductive definitions. As an example, let us consider a type of expression trees that allows injection of any native Coq value. The idea is that an [exp T] stands for an encoded expression of type [T].
[[
Inductive exp : Set -> Set :=
| Const : forall T : Set, T -> exp T
| Pair : forall T1 T2, exp T1 -> exp T2 -> exp (T1 * T2)
| Eq : forall T, exp T -> exp T -> exp bool.
]]
<<
Error: Large non-propositional inductive types must be in Type.
>>
This definition is%\index{large inductive types}% _large_ in the sense that at least one of its constructors takes an argument whose type has type [Type]. Coq would be inconsistent if we allowed definitions like this one in their full generality. Instead, we must change [exp] to live in [Type]. We will go even further and move [exp]'s index to [Type] as well. *)
*)
(** 可述性の制限は帰納的定義にも適用されます。例えば、任意のネイティブな Coq の値を注入できる式木の型を考えましょう。ここでのアイデアは [exp T] 型が 型 [T] に関してエンコードされた式を表すということです。
[[
Inductive exp : Set -> Set :=
| Const : forall T : Set, T -> exp T
| Pair : forall T1 T2, exp T1 -> exp T2 -> exp (T1 * T2)
| Eq : forall T, exp T -> exp T -> exp bool.
]]
<<
Error: Large non-propositional inductive types must be in Type.
>>
この定義は%\index{巨大な帰納型(large inductive types)}% 少なくとも一つの構築子が型 [Type] を持つ型を持つ引数を取るという意味で _巨大_ です。Coq における最大限の一般性のもとでは、このような定義を認めると矛盾します。代わりに、[exp] が [Type] にあるように変更しなければなりません。さらに [exp] のインデックスも [Type] になるような例について考えます。 *)
Inductive exp : Type -> Type :=
| Const : forall T, T -> exp T
| Pair : forall T1 T2, exp T1 -> exp T2 -> exp (T1 * T2)
| Eq : forall T, exp T -> exp T -> exp bool.
(**
(** Note that before we had to include an annotation [: Set] for the variable [T] in [Const]'s type, but we need no annotation now. When the type of a variable is not known, and when that variable is used in a context where only types are allowed, Coq infers that the variable is of type [Type], the right behavior here, though it was wrong for the [Set] version of [exp].
Our new definition is accepted. We can build some sample expressions. *)
*)
(** 以前は変数 [T] に型注釈 [: Set] を含めなければなりませんでしたが、ここでは不要であることに注意してください。変数の型が分からず、その変数が型しか許されていない文脈で使われているとき、Coq はその変数が型 [Type] を持つと推論します。これはここでは正しい振る舞いですが、[Set] バージョンの [exp] では間違っていました。
新しい定義が受理されました。 いくつかのサンプルの式を構築できます。 *)
Check Const 0.
(** %\vspace{-.15in}% [[
Const 0
: exp nat
]]
*)
Check Pair (Const 0) (Const tt).
(** %\vspace{-.15in}% [[
Pair (Const 0) (Const tt)
: exp (nat * unit)
]]
*)
Check Eq (Const Set) (Const Type).
(**
(** %\vspace{-.15in}% [[
Eq (Const Set) (Const Type $ Top.59 ^ )
: exp bool
]]
We can check many expressions, including fancy expressions that include types. However, it is not hard to hit a type-checking wall.
[[
Check Const (Const O).
]]
<<
Error: Universe inconsistency (cannot enforce Top.42 < Top.42).
>>
We are unable to instantiate the parameter [T] of [Const] with an [exp] type. To see why, it is helpful to print the annotated version of [exp]'s inductive definition. *)
*)
(** %\vspace{-.15in}% [[
Eq (Const Set) (Const Type $ Top.59 ^ )
: exp bool
]]
型を伴うようなファンシーな式なども含め、多くの式をチェックできます。しかしながら、型検査の壁にぶつかるのもそう難しくはありません。
[[
Check Const (Const O).
]]
<<
Error: Universe inconsistency (cannot enforce Top.42 < Top.42).
>>
[Const] のパラメータ [T] は、 [exp] 型で具体化できません。その理由を知るには、注釈されたバージョンの [exp] の帰納的定義を印字すると良いです。
*)
(*
(** [[
Print exp.
]]
%\vspace{-.15in}%[[
Inductive exp
: Type $ Top.8 ^ ->
Type
$ max(0, (Top.11)+1, (Top.14)+1, (Top.15)+1, (Top.19)+1) ^ :=
Const : forall T : Type $ Top.11 ^ , T -> exp T
| Pair : forall (T1 : Type $ Top.14 ^ ) (T2 : Type $ Top.15 ^ ),
exp T1 -> exp T2 -> exp (T1 * T2)
| Eq : forall T : Type $ Top.19 ^ , exp T -> exp T -> exp bool
]]
We see that the index type of [exp] has been assigned to universe level [Top.8]. In addition, each of the four occurrences of [Type] in the types of the constructors gets its own universe variable. Each of these variables appears explicitly in the type of [exp]. In particular, any type [exp T] lives at a universe level found by incrementing by one the maximum of the four argument variables. Therefore, [exp] _must_ live at a higher universe level than any type which may be passed to one of its constructors. This consequence led to the universe inconsistency.
Strangely, the universe variable [Top.8] only appears in one place. Is there no restriction imposed on which types are valid arguments to [exp]? In fact, there is a restriction, but it only appears in a global set of universe constraints that are maintained "off to the side," not appearing explicitly in types. We can print the current database.%\index{Vernacular commands!Print Universes}% *)
*)
(** [[
Print exp.
]]
%\vspace{-.15in}%[[
Inductive exp
: Type $ Top.8 ^ ->
Type
$ max(0, (Top.11)+1, (Top.14)+1, (Top.15)+1, (Top.19)+1) ^ :=
Const : forall T : Type $ Top.11 ^ , T -> exp T
| Pair : forall (T1 : Type $ Top.14 ^ ) (T2 : Type $ Top.15 ^ ),
exp T1 -> exp T2 -> exp (T1 * T2)
| Eq : forall T : Type $ Top.19 ^ , exp T -> exp T -> exp bool
]]
[exp] のインデックス型に宇宙レベル [Top.8] が割り当てられたことが分かります。それに加えて、構築子の型における [Type] の4つの出現がそれぞれ宇宙変数を持っています。これらの変数それぞれは [exp] の型に陽に現れます。特に、 どの型 [exp T] も、4つの引数の最大値をひとつインクリメントした宇宙レベルにあります。このため、 [exp] は_必ず_構築子に渡されるどの型よりも高い宇宙レベルにあります。この帰結として、宇宙の矛盾 (universe inconsistency) になります。
不思議なことに、宇宙変数 [Top.8] は一ヶ所にしか現れていません。 [exp] の引数としてどの型が妥当かという制限はないのでしょうか？実際のところ制限はありますが、これは「脇に置いて」保たれている宇宙制約のグローバルな集合にのみ現れ、型には陽に現れません。現時点でのこのデータベースを印字することができます。%\index{Vernacular commands!Print Universes}% *)
Print Universes.
(*
(** %\vspace{-.15in}% [[
Top.19 < Top.9 <= Top.8
Top.15 < Top.9 <= Top.8 <= Coq.Init.Datatypes.38
Top.14 < Top.9 <= Top.8 <= Coq.Init.Datatypes.37
Top.11 < Top.9 <= Top.8
]]
The command outputs many more constraints, but we have collected only those that mention [Top] variables. We see one constraint for each universe variable associated with a constructor argument from [exp]'s definition. Universe variable [Top.19] is the type argument to [Eq]. The constraint for [Top.19] effectively says that [Top.19] must be less than [Top.8], the universe of [exp]'s indices; an intermediate variable [Top.9] appears as an artifact of the way the constraint was generated.
The next constraint, for [Top.15], is more complicated. This is the universe of the second argument to the [Pair] constructor. Not only must [Top.15] be less than [Top.8], but it also comes out that [Top.8] must be less than [Coq.Init.Datatypes.38]. What is this new universe variable? It is from the definition of the [prod] inductive family, to which types of the form [A * B] are desugared. *)
*)
(** %\vspace{-.15in}% [[
Top.19 < Top.9 <= Top.8
Top.15 < Top.9 <= Top.8 <= Coq.Init.Datatypes.38
Top.14 < Top.9 <= Top.8 <= Coq.Init.Datatypes.37
Top.11 < Top.9 <= Top.8
]]
このコマンドはもっと多くの制約を出力しますが、[Top] 変数に言及するものだけを集めました。ここで、 [exp] の定義における構築子の引数に関連づけられたひとつの宇宙変数につきひとつの制約を確認できます。宇宙変数 [Top.19] は [Eq] の型引数です。[Top.19] の制約は [Top.19] が [exp] のインデックスの宇宙である [Top.8] より小さくなければならないことを実質的に言っています。また、中間の変数である [Top.9] は制約が生成される途中でできたもののようです。
次の制約である [Top.15] はより複雑です。これは [Pair] 構築子への二つ目の引数の宇宙です。[Top.15] が [Top.8] より小さいだけでなく、[Top.8] も [Coq.Init.Datatypes.28] より小さくなくてはなりません。この新しい宇宙変数は何でしょう？これは [prod] という帰納的定義に由来し、[A * B] の形が展開 (desugar) されてこの型になります。*)
(* begin hide *)
(* begin thide *)
Inductive prod := pair.
Reset prod.
(* end thide *)
(* end hide *)
(*
(** %\vspace{-.3in}%[[
Print prod.
]]
%\vspace{-.15in}%[[
Inductive prod (A : Type $ Coq.Init.Datatypes.37 ^ )
(B : Type $ Coq.Init.Datatypes.38 ^ )
: Type $ max(Coq.Init.Datatypes.37, Coq.Init.Datatypes.38) ^ :=
pair : A -> B -> A * B
]]
We see that the constraint is enforcing that indices to [exp] must not live in a higher universe level than [B]-indices to [prod]. The next constraint above establishes a symmetric condition for [A].
Thus it is apparent that Coq maintains a tortuous set of universe variable inequalities behind the scenes. It may look like some functions are polymorphic in the universe levels of their arguments, but what is really happening is imperative updating of a system of constraints, such that all uses of a function are consistent with a global set of universe levels. When the constraint system may not be evolved soundly, we get a universe inconsistency error.
%\medskip%
The annotated definition of [prod] reveals something interesting. A type [prod A B] lives at a universe that is the maximum of the universes of [A] and [B]. From our earlier experiments, we might expect that [prod]'s universe would in fact need to be _one higher_ than the maximum. The critical difference is that, in the definition of [prod], [A] and [B] are defined as _parameters_; that is, they appear named to the left of the main colon, rather than appearing (possibly unnamed) to the right.
Parameters are not as flexible as normal inductive type arguments. The range types of all of the constructors of a parameterized type must share the same parameters. Nonetheless, when it is possible to define a polymorphic type in this way, we gain the ability to use the new type family in more ways, without triggering universe inconsistencies. For instance, nested pairs of types are perfectly legal. *)
*)
(** %\vspace{-.3in}%[[
Print prod.
]]
%\vspace{-.15in}%[[
Inductive prod (A : Type $ Coq.Init.Datatypes.37 ^ )
(B : Type $ Coq.Init.Datatypes.38 ^ )
: Type $ max(Coq.Init.Datatypes.37, Coq.Init.Datatypes.38) ^ :=
pair : A -> B -> A * B
]]
この制約は [exp] が [prod] の [B]の引数より高い宇宙のレベルにあってはならないことを強制していることが分かります。上記にあるその次の制約は対称的な条件を [A] について確立しています。
このように、 Coq は宇宙変数の集合に関する不等式の病的な集合を舞台裏で維持していることは明らかです。いくつかの関数が引数の宇宙レベルにおいて多相的であるように見えるかもしれませんが、実際には制約系の命令的な更新が発生し、関数の全ての使用について宇宙レベルの大域的な集合との一貫性を持たせています。もし制約システムが健全に進行しない場合、宇宙の矛盾エラーが発生します。
%\medskip%
ここで注釈を加えられた [prod] の定義から興味深いことが分かります。型 [prod A B] は [A] と [B] の最大値であるような宇宙にあるのです。 ここまでの実験から、 [prod] の宇宙は実際のところこの最大値よりも _１つだけ高い_ レベルである必要があるようにも思えます。 この決定的な違いは、[prod] の定義において [A] と [B] は _仮引数_ として定義されていることです。つまり、これらはメインのコロンよりも左手で名付けられて現れており、名前を持たないまま右手に現れているわけではないということです。
パラメータは帰納型の引数ほどには柔軟ではありません。パラメータ化された型のすべての構築子において型が動く範囲は同じパラメータを共有しなければなりません。そうではあるものの、この方法で多相型を定義できるとき、この型の族を、宇宙の矛盾を引き起こすことなく、より多くの方法で使うことができるようになます。例えば、型のペアのネストは完全に合法です。 *)
Check (nat, (Type, Set)).
(*
(** %\vspace{-.15in}% [[
(nat, (Type $ Top.44 ^ , Set))
: Set * (Type $ Top.45 ^ * Type $ Top.46 ^ )
]]
The same cannot be done with a counterpart to [prod] that does not use parameters. *)
*)
(** %\vspace{-.15in}% [[
(nat, (Type $ Top.44 ^ , Set))
: Set * (Type $ Top.45 ^ * Type $ Top.46 ^ )
]]
同じことはパラメータを用いない [prod] に対応する型ではできません。 *)
Inductive prod' : Type -> Type -> Type :=
| pair' : forall A B : Type, A -> B -> prod' A B.
(*
(** %\vspace{-.15in}%[[
Check (pair' nat (pair' Type Set)).
]]
<<
Error: Universe inconsistency (cannot enforce Top.51 < Top.51).
>>
The key benefit parameters bring us is the ability to avoid quantifying over types in the types of constructors. Such quantification induces less-than constraints, while parameters only introduce less-than-or-equal-to constraints.
Coq includes one more (potentially confusing) feature related to parameters. While Gallina does not support real %\index{universe polymorphism}%universe polymorphism, there is a convenience facility that mimics universe polymorphism in some cases. We can illustrate what this means with a simple example. *)
*)
(** %\vspace{-.15in}%[[
Check (pair' nat (pair' Type Set)).
]]
<<
Error: Universe inconsistency (cannot enforce Top.51 < Top.51).
>>
パラメータの利点はコンストラクタの型において量化を避けられることです。そのような量化は「より低い(less-than)」という制約をもたらしますが、パラメータは「以下 (less-than-or-equal)」という制約を導入するだけです。
Coq は パラメータに関してもう一つ (使用者が混乱しがちな) 機能があります。Gallina が真の%\index{宇宙多相}%宇宙多相をサポートしない一方で、いくつかの場合には宇宙多相をまねる便宜的な手段があります。 これが何を意味するのかは、単純な例で示すことができます。 *)
Inductive foo (A : Type) : Type :=
| Foo : A -> foo A.
(* begin hide *)
Unset Printing Universes.
(* end hide *)
Check foo nat.
(** %\vspace{-.15in}% [[
foo nat
: Set
]]
*)
Check foo Set.
(** %\vspace{-.15in}% [[
foo Set
: Type
]]
*)
Check foo True.
(*
(** %\vspace{-.15in}% [[
foo True
: Prop
]]
The basic pattern here is that Coq is willing to automatically build a "copied-and-pasted" version of an inductive definition, where some occurrences of [Type] have been replaced by [Set] or [Prop]. In each context, the type-checker tries to find the valid replacements that are lowest in the type hierarchy. Automatic cloning of definitions can be much more convenient than manual cloning. We have already taken advantage of the fact that we may re-use the same families of tuple and list types to form values in [Set] and [Type].
Imitation polymorphism can be confusing in some contexts. For instance, it is what is responsible for this weird behavior. *)
*)
(** %\vspace{-.15in}% [[
foo True
: Prop
]]
ここでの基本的なパターンは Coq が帰納的定義の「コピー＆ペーストした」バージョンを自動的に構築しようとしていることです。この定義において [Type] のいくつかの出現は [Set] か [Prop] で置き換えられています。どの文脈においても、型検査器は型の階層においてもっとも低く、かつ置き換えが妥当な型を探します。定義のクローンは手動のクローンよりもぐっと便利になり得ます。これまでにも、[Set] や [Type] における値を形成するために同じ組やリスト型を採用できるという事実から既に恩恵を得ています。
模造の多相性はいくつかの文脈では混乱させがちです。このせいで、例えば、次のような奇妙な問題があります。 *)
Inductive bar : Type := Bar : bar.
Check bar.
(*
(** %\vspace{-.15in}% [[
bar
: Prop
]]
The type that Coq comes up with may be used in strictly more contexts than the type one might have expected. *)
*)
(** %\vspace{-.15in}% [[
bar
: Prop
]]
Coq の型は期待したよりも真に多くの文脈で使われることがあるのです。 *)
(*
(** ** Deciphering Baffling Messages About Inability to Unify *)
*)
(** ** 不可解な単一化不能メッセージの謎を解く *)
(*
(** One of the most confusing sorts of Coq error messages arises from an interplay between universes, syntax notations, and %\index{implicit arguments}%implicit arguments. Consider the following innocuous lemma, which is symmetry of equality for the special case of types. *)
*)
(** Coq において最も混乱を招く種類のエラーメッセージのひとつは、宇宙間の相互作用や構文上の記法、そして%\index{暗黙の引数}%暗黙の引数(implicit arguments)に由来します。次の無害な補題について考えてみます。これは特殊な型についての等価性の対称性に関するものです。 *)
Theorem symmetry : forall A B : Type,
A = B
-> B = A.
intros ? ? H; rewrite H; reflexivity.
Qed.
(*
(** Let us attempt an admittedly silly proof of the following theorem. *)
*)
(** 次の定理について、ほとんど明白で馬鹿馬鹿しい証明を試みてみましょう。 *)
Theorem illustrative_but_silly_detour : unit = unit.
(*
(** %\vspace{-.25in}%[[
apply symmetry.
]]
<<
Error: Impossible to unify "?35 = ?34" with "unit = unit".
>>
Coq tells us that we cannot, in fact, apply our lemma [symmetry] here, but the error message seems defective. In particular, one might think that [apply] should unify [?35] and [?34] with [unit] to ensure that the unification goes through. In fact, the issue is in a part of the unification problem that is _not_ shown to us in this error message!
The following command is the secret to getting better error messages in such cases:%\index{Vernacular commands!Set Printing All}% *)
*)
(** %\vspace{-.25in}%[[
apply symmetry.
]]
<<
Error: Impossible to unify "?35 = ?34" with "unit = unit".
>>
Coq は実際のところ、この補題 [symmetry] を適用できないと言っているのですが、このエラーメッセージには欠陥があるように見えます。特に、単一化がうまくいくには [apply] において [?35] と [?34] を [unit] と単一化されるべきであるように思えるでしょう。実際のところ、課題はこのエラーメッセージで示されて_いない_部分における単一化問題にあります。
このような場合に良いエラーメッセージを得るための秘訣が、次のコマンドです。%\index{Vernacular commands!Set Printing All}% *)
Set Printing All.
(*
(** %\vspace{-.15in}%[[
apply symmetry.
]]
<<
Error: Impossible to unify "@eq Type ?46 ?45" with "@eq Set unit unit".
>>
Now we can see the problem: it is the first, _implicit_ argument to the underlying equality function [eq] that disagrees across the two terms. The universe [Set] may be both an element and a subtype of [Type], but the two are not definitionally equal. *)
*)
(** %\vspace{-.15in}%[[
apply symmetry.
]]
<<
Error: Impossible to unify "@eq Type ?46 ?45" with "@eq Set unit unit".
>>
これで問題が判明しました。隠れた等価関数 [eq] の、最初の_暗黙の_引数が、二つの項の間で異なっています。宇宙 [Set] は [Type] の要素であり部分型でもあるのですが、これら二つは定義において等価ではないのです。 *)
Abort.
(*
(** A variety of changes to the theorem statement would lead to use of [Type] as the implicit argument of [eq]. Here is one such change. *)
*)
(** 色々な修正を試せば、[eq] の暗黙の引数として [Type] を使えばよいことがわかるでしょう。これがそのような修正です。 *)
Theorem illustrative_but_silly_detour : (unit : Type) = unit.
apply symmetry; reflexivity.
Qed.
(*
(** There are many related issues that can come up with error messages, where one or both of notations and implicit arguments hide important details. The [Set Printing All] command turns off all such features and exposes underlying CIC terms.
For completeness, we mention one other class of confusing error message about inability to unify two terms that look obviously unifiable. Each unification variable has a scope; a unification variable instantiation may not mention variables that were not already defined within that scope, at the point in proof search where the unification variable was introduced. Consider this illustrative example: *)
*)
(** エラーメッセージには多くの問題が関連していることがあり、そのような場合は記法と暗黙の引数のいずれか片方、もしくは両方が重要な詳細を隠しています。
[Set Printing All] コマンドはそのような機能をすべてオフにして、隠された CIC の項を表示してくれます。
完全性のため、明らかに単一化可能であるように見える二つの項の単一化不能性に関する厄介なエラーメッセージのクラスについて紹介しておきます。それぞれの単一化変数はスコープを持ちます。単一化変数の具体化においては、証明の探索中、その単一化変数が導入された点におけるスコープで未だ定義されていない変数に言及してはなりません。次の実例について考えてみましょう。 *)
Unset Printing All.
Theorem ex_symmetry : (exists x, x = 0) -> (exists x, 0 = x).
eexists.
(** %\vspace{-.15in}%[[
H : exists x : nat, x = 0
============================
0 = ?98
]]
*)
destruct H.
(** %\vspace{-.15in}%[[
x : nat
H : x = 0
============================
0 = ?99
]]
*)
(*
(** %\vspace{-.2in}%[[
symmetry; exact H.
]]
<<
Error: In environment
x : nat
H : x = 0
The term "H" has type "x = 0" while it is expected to have type
"?99 = 0".
>>
The problem here is that variable [x] was introduced by [destruct] _after_ we introduced [?99] with [eexists], so the instantiation of [?99] may not mention [x]. A simple reordering of the proof solves the problem. *)
*)
(** %\vspace{-.2in}%[[
symmetry; exact H.
]]
<<
Error: In environment
x : nat
H : x = 0
The term "H" has type "x = 0" while it is expected to have type
"?99 = 0".
>>
ここでの問題は、 [?99] を [eexists] で導入した_後_で変数 [x] が [destruct] で導入されており、 [?99] の具体化においては [x] に言及できないことです。 証明の順序を入れ替えることでこの問題を解決できます。 *)
Restart.
destruct 1 as [x]; apply ex_intro with x; symmetry; assumption.
Qed.
(*
(** This restriction for unification variables may seem counterintuitive, but it follows from the fact that CIC contains no concept of unification variable. Rather, to construct the final proof term, at the point in a proof where the unification variable is introduced, we replace it with the instantiation we eventually find for it. It is simply syntactically illegal to refer there to variables that are not in scope. Without such a restriction, we could trivially "prove" such non-theorems as [exists n : nat, forall m : nat, n = m] by [econstructor; intro; reflexivity]. *)
*)
(** 単一化変数に関するこの制限は直感に反するように見えるかもしれませんが、これは CIC に単一化変数の概念がないことに由来しています。単一化変数を導入する地点において最終的な証明項を構築して、最終的に見つかった具体化によって置き換えて証明を終えるようにします。スコープに存在しない変数をそこから参照するのは単に間違っています。 そのような制約がないと、 [exists n : nat, forall m : nat, n = m] のような非定理を [econstructor; intro; reflexivity] によって「証明」できてしまうことでしょう。*)
(*
(** * The [Prop] Universe *)
*)
(** * [Prop] 宇宙 *)
(*
(** In Chapter 4, we saw parallel versions of useful datatypes for "programs" and "proofs." The convention was that programs live in [Set], and proofs live in [Prop]. We gave little explanation for why it is useful to maintain this distinction. There is certainly documentation value from separating programs from proofs; in practice, different concerns apply to building the two types of objects. It turns out, however, that these concerns motivate formal differences between the two universes in Coq.
Recall the types [sig] and [ex], which are the program and proof versions of existential quantification. Their definitions differ only in one place, where [sig] uses [Type] and [ex] uses [Prop]. *)
*)
(** 4章で, 「プログラム」と「証明」という並列な二つのバージョンの便利なデータ型を説明しました。プログラムは [Set] にあり、証明は [Prop] にあるというのが慣例でした。この区別をすることがなぜ便利なのかについては説明しませんでした。証明からのプログラムの分離について説明するのは確かに価値があります。実際、この二種類のオブジェクトを構築するには異なる関心事が適用されます。しかしながら、これらの関心事は Coq の二つの宇宙の形式的な違いの動機となるもののです。
型 [sig] と [ex] の違いについて思い出してみましょう。これらは存在量化のプログラムバージョンと証明バージョンです。定義の違いは [sig] が [Type] を用い、 [ex] が [Prop] を用いているという点のみです。 *)
Print sig.
(** %\vspace{-.15in}% [[
Inductive sig (A : Type) (P : A -> Prop) : Type :=
exist : forall x : A, P x -> sig P
]]
*)
Print ex.
(*
(** %\vspace{-.15in}% [[
Inductive ex (A : Type) (P : A -> Prop) : Prop :=
ex_intro : forall x : A, P x -> ex P
]]
It is natural to want a function to extract the first components of data structures like these. Doing so is easy enough for [sig]. *)
*)
(** %\vspace{-.15in}% [[
Inductive ex (A : Type) (P : A -> Prop) : Prop :=
ex_intro : forall x : A, P x -> ex P
]]
このようなデータ構造の最初の成分を抽出する機能が欲しいと思うのは自然なことです。それは [sig] については非常に簡単です。 *)
Definition projS A (P : A -> Prop) (x : sig P) : A :=
match x with
| exist v _ => v
end.
(* begin hide *)
(* begin thide *)
Definition projE := O.
(* end thide *)
(* end hide *)
(*
(** We run into trouble with a version that has been changed to work with [ex].
[[
Definition projE A (P : A -> Prop) (x : ex P) : A :=
match x with
| ex_intro v _ => v
end.
]]
<<
Error:
Incorrect elimination of "x" in the inductive type "ex":
the return type has sort "Type" while it should be "Prop".
Elimination of an inductive object of sort Prop
is not allowed on a predicate in sort Type
because proofs can be eliminated only to build proofs.
>>
In formal Coq parlance, %\index{elimination}%"elimination" means "pattern-matching." The typing rules of Gallina forbid us from pattern-matching on a discriminee whose type belongs to [Prop], whenever the result type of the [match] has a type besides [Prop]. This is a sort of "information flow" policy, where the type system ensures that the details of proofs can never have any effect on parts of a development that are not also marked as proofs.
This restriction matches informal practice. We think of programs and proofs as clearly separated, and, outside of constructive logic, the idea of computing with proofs is ill-formed. The distinction also has practical importance in Coq, where it affects the behavior of extraction.
Recall that %\index{program extraction}%extraction is Coq's facility for translating Coq developments into programs in general-purpose programming languages like OCaml. Extraction _erases_ proofs and leaves programs intact. A simple example with [sig] and [ex] demonstrates the distinction. *)
*)
(** [ex] についてこれを行うように変更したバージョンでは困ったことになります。
[[
Definition projE A (P : A -> Prop) (x : ex P) : A :=
match x with
| ex_intro v _ => v
end.
]]
<<
Error:
Incorrect elimination of "x" in the inductive type "ex":
the return type has sort "Type" while it should be "Prop".
Elimination of an inductive object of sort Prop
is not allowed on a predicate in sort Type
because proofs can be eliminated only to build proofs.
>>
Coq の形式的な専門用語において、 %\index{除去}%「除去 (elimination)」は「パターンマッチング」を意味します。Gallinaの型付け規則は、 [match] の結果の型が [Prop] 以外を持つとき、 [Prop] に属する型をもつ場合分けのパターンマッチングを禁じています。これはある種の「情報流」ポリシーであり、証明であるとマークされていない部分の開発に証明の詳細が影響を及ぼさないように型システムが保証しています。
この制限は非形式的な実践に対応しています。プログラムと証明は明確に分離されており、構成的論理の外側では、証明による計算はill-formedです。この区別は Coq において実際的な重要性を持ちます。抽出に関する振る舞いに影響するのです。
%\index{プログラム抽出}%抽出は Coq で開発したものを OCaml のような一般目的のプログラミング言語に変換する Coq の機能であることを思い出してください。抽出は証明を_消去_しますがプログラムはそのままです。[sig] と [ex] を用いた例がこの違いをよく実演しています。 *)
Definition sym_sig (x : sig (fun n => n = 0)) : sig (fun n => 0 = n) :=
match x with
| exist n pf => exist _ n (sym_eq pf)
end.
Extraction sym_sig.
(*
(** <<
(** val sym_sig : nat -> nat **)
let sym_sig x = x
>>
Since extraction erases proofs, the second components of [sig] values are elided, making [sig] a simple identity type family. The [sym_sig] operation is thus an identity function. *)
*)
(** <<
(** val sym_sig : nat -> nat **)
let sym_sig x = x
>>
抽出は証明を消去するので、 [sig] の二番目の成分は省略され、 [sig] は単純な恒等的な型の族になります。このため [sym_sig] 操作は恒等関数です。 *)
Definition sym_ex (x : ex (fun n => n = 0)) : ex (fun n => 0 = n) :=
match x with
| ex_intro n pf => ex_intro _ n (sym_eq pf)
end.
Extraction sym_ex.
(*
(** <<
(** val sym_ex : __ **)
let sym_ex = __
>>
In this example, the [ex] type itself is in [Prop], so whole [ex] packages are erased. Coq extracts every proposition as the (Coq-specific) type <<__>>, whose single constructor is <<__>>. Not only are proofs replaced by [__], but proof arguments to functions are also removed completely, as we see here.
Extraction is very helpful as an optimization over programs that contain proofs. In languages like Haskell, advanced features make it possible to program with proofs, as a way of convincing the type checker to accept particular definitions. Unfortunately, when proofs are encoded as values in GADTs%~\cite{GADT}%, these proofs exist at runtime and consume resources. In contrast, with Coq, as long as all proofs are kept within [Prop], extraction is guaranteed to erase them.
Many fans of the %\index{Curry-Howard correspondence}%Curry-Howard correspondence support the idea of _extracting programs from proofs_. In reality, few users of Coq and related tools do any such thing. Instead, extraction is better thought of as an optimization that reduces the runtime costs of expressive typing.
%\medskip%
We have seen two of the differences between proofs and programs: proofs are subject to an elimination restriction and are elided by extraction. The remaining difference is that [Prop] is%\index{impredicativity}% _impredicative_, as this example shows. *)
*)
(** <<
(** val sym_ex : __ **)
let sym_ex = __
>>
この例では、[ex] 型は [Prop] にあるため、[ex] パッケージ全体が消去されます。Coq は全ての命題を (Coq特有の) 型 <<__>> として抽出します。その構築子は <<__>> です。証明が [__] に置き換えられるだけでなく、関数の証明引数も、ここで見たように、完全に削除されます。
抽出は証明を含むプログラムの最適化として非常に便利です。Haskell のような言語では、特殊な定義を型検査器に受理させる方法として、先進的な機能で証明付きのプログラムを書くことができます。残念ながら、証明が GADT%~\cite{GADT}% の値としてエンコードすると、これらの証明は実行時にも存在しリソースを消費します。対照的に、Coqを使えば、すべての証明が [Prop] に保持されている限り、抽出がそれらを消去することが保証されています。
%\index{カリー・ハワード同型対応}%カリー・ハワード同型対応の多くのファンは_証明からプログラムを抽出する_というアイデアを支持しています。現実には、ほとんどのCoqユーザーと関連ツールはそのようなことをしていません。そうではなく、抽出は表現力の高い型付けの実行時コストを削減する最適化のひとつ見なすほうが良いです。
%\medskip%
ここまで証明とプログラムの違いを二つ見てきました。つまり、証明は除去の制限が課されており、抽出によって省略されます。残りの違いは、[Prop] が%\index{非可述性}% _非可述的_であることで、この例が示しています。 *)
Check forall P Q : Prop, P \/ Q -> Q \/ P.
(*
(** %\vspace{-.15in}% [[
forall P Q : Prop, P \/ Q -> Q \/ P
: Prop
]]
We see that it is possible to define a [Prop] that quantifies over other [Prop]s. This is fortunate, as we start wanting that ability even for such basic purposes as stating propositional tautologies. In the next section of this chapter, we will see some reasons why unrestricted impredicativity is undesirable. The impredicativity of [Prop] interacts crucially with the elimination restriction to avoid those pitfalls.
Impredicativity also allows us to implement a version of our earlier [exp] type that does not suffer from the weakness that we found. *)
*)
(** %\vspace{-.15in}% [[
forall P Q : Prop, P \/ Q -> Q \/ P
: Prop
]]
他の [Prop] の上で量化された [Prop] を定義できることが分かります。これは有難いことです、なぜなら命題的トートロジーを述べるような基本的な用途でさえそのような能力が必要になってくるからです。この章の次の節で、無制限な非可述性が好ましくない理由を見ていくことになるでしょう。そのような落とし穴を避けるため、[Prop] の非可述性は除去の制限との間に重要な相互作用があります。
また非可述性により、以前の [exp] 型について、先に見た弱点の影響を受けない別バージョンを実装できます。 *)
Inductive expP : Type -> Prop :=
| ConstP : forall T, T -> expP T
| PairP : forall T1 T2, expP T1 -> expP T2 -> expP (T1 * T2)
| EqP : forall T, expP T -> expP T -> expP bool.
Check ConstP 0.
(** %\vspace{-.15in}% [[
ConstP 0
: expP nat
]]
*)
Check PairP (ConstP 0) (ConstP tt).
(** %\vspace{-.15in}% [[
PairP (ConstP 0) (ConstP tt)
: expP (nat * unit)
]]
*)
Check EqP (ConstP Set) (ConstP Type).
(** %\vspace{-.15in}% [[
EqP (ConstP Set) (ConstP Type)
: expP bool
]]
*)
Check ConstP (ConstP O).
(*
(** %\vspace{-.15in}% [[
ConstP (ConstP 0)
: expP (expP nat)
]]
In this case, our victory is really a shallow one. As we have marked [expP] as a family of proofs, we cannot deconstruct our expressions in the usual programmatic ways, which makes them almost useless for the usual purposes. Impredicative quantification is much more useful in defining inductive families that we really think of as judgments. For instance, this code defines a notion of equality that is strictly more permissive than the base equality [=]. *)
*)
(** %\vspace{-.15in}% [[
ConstP (ConstP 0)
: expP (expP nat)
]]
この場合、我々の勝利は非常に薄っぺらいものです。我々は [expP] を証明の一族であるとマークしたため、その式は普通のプログラミング的な方法ではdeconstructできず、通常の用途にはほとんど使い物にならないのです。非可述的な量化はまさしく判定(judgments)のような帰納的な命題の族を定義するときに非常に便利です。例えば、このコードは基本の等価性 [=] よりも真に許容的であるような等価性の概念を定義します。 *)
Inductive eqPlus : forall T, T -> T -> Prop :=
| Base : forall T (x : T), eqPlus x x
| Func : forall dom ran (f1 f2 : dom -> ran),
(forall x : dom, eqPlus (f1 x) (f2 x))
-> eqPlus f1 f2.
Check (Base 0).
(** %\vspace{-.15in}% [[
Base 0
: eqPlus 0 0
]]
*)
Check (Func (fun n => n) (fun n => 0 + n) (fun n => Base n)).
(** %\vspace{-.15in}% [[
Func (fun n : nat => n) (fun n : nat => 0 + n) (fun n : nat => Base n)
: eqPlus (fun n : nat => n) (fun n : nat => 0 + n)
]]
*)
Check (Base (Base 1)).
(** %\vspace{-.15in}% [[
Base (Base 1)
: eqPlus (Base 1) (Base 1)
]]
*)
(*
(** Stating equality facts about proofs may seem baroque, but we have already seen its utility in the chapter on reasoning about equality proofs. *)
*)
(** 証明に関する等価性の事実を述べるのは装飾的に見えるかもしれませんが、その利便性は既に等価性の証明に関する論証の章で見てきました。*)
(*
(** * Axioms *)
*)
(** * 公理 *)
(*
(** While the specific logic Gallina is hardcoded into Coq's implementation, it is possible to add certain logical rules in a controlled way. In other words, Coq may be used to reason about many different refinements of Gallina where strictly more theorems are provable. We achieve this by asserting%\index{axioms}% _axioms_ without proof.
We will motivate the idea by touring through some standard axioms, as enumerated in Coq's online FAQ. I will add additional commentary as appropriate. *)
*)
(** 特定の論理体系である Gallina が Coq の実装にハードコードされている一方で、制御された方法である種の論理規則を追加することも可能です。言い換えると、Coq は真により多くの定理を証明可能な、数多くの異なる Gallina の詳細化について論証するのに使えます。 これは証明を持たない %\index{公理}%_公理_ を用いて達成します。
Coq のオンライン FAQ に並べられている、いくつかの標準的な公理をひととおり見物してこのアイデアの動機付けをします。しかるべきところには追加の解説を加えておきます。 *)
(*
(** ** The Basics *)
*)
(** ** 基本 *)
(*
(** One simple example of a useful axiom is the %\index{law of the excluded middle}%law of the excluded middle. *)
*)
(** 有用な公理の単純な例の一つは%\index{排中律}%排中律です。 *)
Require Import Classical_Prop.
Print classic.
(*
(** %\vspace{-.15in}% [[
*** [ classic : forall P : Prop, P \/ ~ P ]
]]
In the implementation of module [Classical_Prop], this axiom was defined with the command%\index{Vernacular commands!Axiom}% *)
*)
(** %\vspace{-.15in}% [[
*** [ classic : forall P : Prop, P \/ ~ P ]
]]
[Classical_Prop] モジュールの実装において、この公理はコマンド%\index{Vernacular commands!Axiom}%で定義されています。*)
Axiom classic : forall P : Prop, P \/ ~ P.
(*
(** An [Axiom] may be declared with any type, in any of the universes. There is a synonym %\index{Vernacular commands!Parameter}%[Parameter] for [Axiom], and that synonym is often clearer for assertions not of type [Prop]. For instance, we can assert the existence of objects with certain properties. *)
*)
(** [Axiom] はどのような型でも、どのような宇宙にも宣言できます。[Axiom] と同義の %\index{Vernacular commands!Parameter}%[Parameter] があり、これを使えば型 [Prop] でない表明をする時にしばしばより明確にできます。例えば、ある性質を持つオブジェクトの存在を表明できます。*)
Parameter num : nat.
Axiom positive : num > 0.
Reset num.
(*
(** This kind of "axiomatic presentation" of a theory is very common outside of higher-order logic. However, in Coq, it is almost always preferable to stick to defining your objects, functions, and predicates via inductive definitions and functional programming.
In general, there is a significant burden associated with any use of axioms. It is easy to assert a set of axioms that together is%\index{inconsistent axioms}% _inconsistent_. That is, a set of axioms may imply [False], which allows any theorem to be proved, which defeats the purpose of a proof assistant. For example, we could assert the following axiom, which is consistent by itself but inconsistent when combined with [classic]. *)
*)
(** この種の「公理的な説明」は高階論理の世界の外では非常によくあることです。しかしながら、Coq では、ほとんど常にオブジェクト、関数、述語を帰納的定義や関数プログラミングで定義することに固執したほうが良いです。
一般に、公理はどのような使い方においても非常な苦痛を伴います。互いに%\index{矛盾する公理}% _矛盾する_公理の集合を表明するのは簡単です。つまり、公理の集合が [False] を含意し、どのような定理も証明でき、定理証明支援器の目的を否定してしまいます。例えば、それ自体では無矛盾ですが [classic] と組み合わせると矛盾する、次のような公理を表明できます。*)
Axiom not_classic : ~ forall P : Prop, P \/ ~ P.
Theorem uhoh : False.
generalize classic not_classic; tauto.
Qed.
Theorem uhoh_again : 1 + 1 = 3.
destruct uhoh.
Qed.
Reset not_classic.
(*
(** On the subject of the law of the excluded middle itself, this axiom is usually quite harmless, and many practical Coq developments assume it. It has been proved metatheoretically to be consistent with CIC. Here, "proved metatheoretically" means that someone proved on paper that excluded middle holds in a _model_ of CIC in set theory%~\cite{SetsInTypes}%. All of the other axioms that we will survey in this section hold in the same model, so they are all consistent together.
Recall that Coq implements%\index{constructive logic}% _constructive_ logic by default, where the law of the excluded middle is not provable. Proofs in constructive logic can be thought of as programs. A [forall] quantifier denotes a dependent function type, and a disjunction denotes a variant type. In such a setting, excluded middle could be interpreted as a decision procedure for arbitrary propositions, which computability theory tells us cannot exist. Thus, constructive logic with excluded middle can no longer be associated with our usual notion of programming.
Given all this, why is it all right to assert excluded middle as an axiom? The intuitive justification is that the elimination restriction for [Prop] prevents us from treating proofs as programs. An excluded middle axiom that quantified over [Set] instead of [Prop] _would_ be problematic. If a development used that axiom, we would not be able to extract the code to OCaml (soundly) without implementing a genuine universal decision procedure. In contrast, values whose types belong to [Prop] are always erased by extraction, so we sidestep the axiom's algorithmic consequences.
Because the proper use of axioms is so precarious, there are helpful commands for determining which axioms a theorem relies on.%\index{Vernacular commands!Print Assumptions}% *)
*)
(** 排中律それ自体については、大抵の場合はその公理に全く害はなく、Coq を用いた実践的な開発の多くはこれを仮定しています。これは CIC と矛盾しないことがメタ理論的に証明されています。ここで、「メタ理論的に証明された」とは、集合論%~\cite{SetsInTypes}%における CIC の_モデル_において排中律が成り立つことを誰かが紙の上で証明したことを意味します。この節で調べる他の全ての公理は同じモデルで成り立つため、すべては同時に無矛盾です。
Coq は、排中律が証明できない%\index{構成的論理}%_構成的論理_をデフォルトで実装していることを思い出してください。 構成的論理の証明はプログラムであると見なせます。[forall] 量化子は依存関数型を示し、選言はヴァリアント型を示します。そのような状況において、排中律は任意の命題のための決定手続きと解釈し得るのですが、計算可能性理論によればそのような手続きは存在しません。このため、構成的論理と排中律はいつものプログラミングの概念と関連付けることは出来なくなります。
それでは、なぜ排中律を公理として表明してよいのでしょうか？直観的な説明は、[Prop] の除去に関する制限のため、証明をプログラムとして扱えなくしていることです。[Prop] でなく [Set] の上で量化された排中律の公理は問題がある_でしょう_。ある開発においてその公理が用いられたら、真に普遍的な決定手続きを実装せずOCamlにコードを (健全に) 抽出することはできないかもしれません。対照的に、[Prop] に属する型の値は抽出により消去されるため、この公理のアルゴリズム論的な結論は回避されるのです。
公理の適切な使用はとても危ういため、ある定理がどの公理に依存しているか知るための有用なコマンドがあります。%\index{Vernacular commands!Print Assumptions}% *)
Theorem t1 : forall P : Prop, P -> ~ ~ P.
tauto.
Qed.
Print Assumptions t1.
(** <<
Closed under the global context
>>
*)
Theorem t2 : forall P : Prop, ~ ~ P -> P.
(** %\vspace{-.25in}%[[
tauto.
]]
<<
Error: tauto failed.
>>
*)
intro P; destruct (classic P); tauto.
Qed.
Print Assumptions t2.
(*
(** %\vspace{-.15in}% [[
Axioms:
classic : forall P : Prop, P \/ ~ P
]]
It is possible to avoid this dependence in some specific cases, where excluded middle _is_ provable, for decidable families of propositions. *)
*)
(** %\vspace{-.15in}% [[
Axioms:
classic : forall P : Prop, P \/ ~ P
]]
決定可能な種類の命題については、排中律_が_証明可能であり、そのようなケースにおいてはこの依存関係を避けることができます。 *)
Theorem nat_eq_dec : forall n m : nat, n = m \/ n <> m.
induction n; destruct m; intuition; generalize (IHn m); intuition.
Qed.
Theorem t2' : forall n m : nat, ~ ~ (n = m) -> n = m.
intros n m; destruct (nat_eq_dec n m); tauto.
Qed.
Print Assumptions t2'.
(*
(** <<
Closed under the global context
>>
%\bigskip%
Mainstream mathematical practice assumes excluded middle, so it can be useful to have it available in Coq developments, though it is also nice to know that a theorem is proved in a simpler formal system than classical logic. There is a similar story for%\index{proof irrelevance}% _proof irrelevance_, which simplifies proof issues that would not even arise in mainstream math. *)
*)
(** <<
Closed under the global context
>>
%\bigskip%
主流の数学的な実践では排中律を前提としているため、Coq における開発でそれを支えるようにしておくのは便利ですが、ある定理が古典論理よりも単純な形式システムで証明できると知っておくのも良いことです。同様の話は、主流の数学では関わってくることさえない証明上の問題を単純化します。 *)
Require Import ProofIrrelevance.
Print proof_irrelevance.
(*
(** %\vspace{-.15in}% [[
*** [ proof_irrelevance : forall (P : Prop) (p1 p2 : P), p1 = p2 ]
]]
This axiom asserts that any two proofs of the same proposition are equal. Recall this example function from Chapter 6. *)
*)
(** %\vspace{-.15in}% [[
*** [ proof_irrelevance : forall (P : Prop) (p1 p2 : P), p1 = p2 ]
]]
この公理は同じ命題に関するどんな2つの証明も等価であると表明します。6章で見た以下の例の関数を思い出して下さい。*)
(* begin hide *)
Lemma zgtz : 0 > 0 -> False.
crush.
Qed.
(* end hide *)
Definition pred_strong1 (n : nat) : n > 0 -> nat :=
match n with
| O => fun pf : 0 > 0 => match zgtz pf with end
| S n' => fun _ => n'
end.
(*
(** We might want to prove that different proofs of [n > 0] do not lead to different results from our richly typed predecessor function. *)
*)
(** [n > 0] の異なる証明が、このリッチに型付けされた前者関数において異なる結果にならないことを証明したいかもしれません。 *)
Theorem pred_strong1_irrel : forall n (pf1 pf2 : n > 0), pred_strong1 pf1 = pred_strong1 pf2.
destruct n; crush.
Qed.
(*
(** The proof script is simple, but it involved peeking into the definition of [pred_strong1]. For more complicated function definitions, it can be considerably more work to prove that they do not discriminate on details of proof arguments. This can seem like a shame, since the [Prop] elimination restriction makes it impossible to write any function that does otherwise. Unfortunately, this fact is only true metatheoretically, unless we assert an axiom like [proof_irrelevance]. With that axiom, we can prove our theorem without consulting the definition of [pred_strong1]. *)
*)
(** 証明スクリプトはシンプルですが、[pred_strong1] の定義を覗き込むことになります。より複雑な関数定義に対しては、証明引数の詳細について場合分けしないことを証明するのはかなりの大仕事になり得ます。これは残念なことです。なぜなら [Prop] 除去の制限により、そのようなことをする関数を書くことはもはや不可能になっているからです。残念ながら、[proof_irrelevance] のような公理を表明しないかぎり、この事実はメタ理論上でのみ真です。この公理により、[pred_strong1] の定義を参照することなく上の定理を証明できます。 *)
Theorem pred_strong1_irrel' : forall n (pf1 pf2 : n > 0), pred_strong1 pf1 = pred_strong1 pf2.
intros; f_equal; apply proof_irrelevance.
Qed.
(*
(** %\bigskip%
In the chapter on equality, we already discussed some axioms that are related to proof irrelevance. In particular, Coq's standard library includes this axiom: *)
*)
(** %\bigskip%
等価性の章で、既に proof irrelevance に関連するいくつかの公理について議論しました。特に、Coq の標準ライブラリはこの公理を含んでいます。 *)
Require Import Eqdep.
Import Eq_rect_eq.
Print eq_rect_eq.
(*
(** %\vspace{-.15in}% [[
*** [ eq_rect_eq :
forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = eq_rect p Q x p h ]
]]
This axiom says that it is permissible to simplify pattern matches over proofs of equalities like [e = e]. The axiom is logically equivalent to some simpler corollaries. In the theorem names, "UIP" stands for %\index{unicity of identity proofs}%"unicity of identity proofs", where "identity" is a synonym for "equality." *)
*)
(** %\vspace{-.15in}% [[
*** [ eq_rect_eq :
forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = eq_rect p Q x p h ]
]]
この公理は、[e = e] のような等価性の証明の上でのパターンマッチを単純化することは許容できると述べています。この公理はより単純な系と論理的に等価です。定理の名前において、「UIP」は%\index{恒等性の証明の単一性 (unicity of identity proofs)}%「恒等性の証明の単一性 (unicity of identity proofs)」を表しており、ここで「恒等性」は「等価性」と同義です。 *)
Corollary UIP_refl : forall A (x : A) (pf : x = x), pf = eq_refl x.
intros; replace pf with (eq_rect x (eq x) (eq_refl x) x pf); [
symmetry; apply eq_rect_eq
| exact (match pf as pf' return match pf' in _ = y return x = y with
| eq_refl => eq_refl x
end = pf' with
| eq_refl => eq_refl _
end) ].
Qed.
Corollary UIP : forall A (x y : A) (pf1 pf2 : x = y), pf1 = pf2.
intros; generalize pf1 pf2; subst; intros;
match goal with
| [ |- ?pf1 = ?pf2 ] => rewrite (UIP_refl pf1); rewrite (UIP_refl pf2); reflexivity
end.
Qed.
(* begin hide *)
(* begin thide *)
Require Eqdep_dec.
(* end thide *)
(* end hide *)
(*
(** These corollaries are special cases of proof irrelevance. In developments that only need proof irrelevance for equality, there is no need to assert full irrelevance.
Another facet of proof irrelevance is that, like excluded middle, it is often provable for specific propositions. For instance, [UIP] is provable whenever the type [A] has a decidable equality operation. The module [Eqdep_dec] of the standard library contains a proof. A similar phenomenon applies to other notable cases, including less-than proofs. Thus, it is often possible to use proof irrelevance without asserting axioms.
%\bigskip%
There are two more basic axioms that are often assumed, to avoid complications that do not arise in set theory. *)
*)
(** これらの系は proof irrelevance の特殊な場合です。等価性のためだけに proof irrelevance が必要な開発では、フルの irrelevance を表明する必要はないのです。
Proof irrelevance の別の側面は、排中律のように、特定の命題において証明可能であることです。例えば、[UIP] は型 [A] が決定可能な等価性演算を備えている場合にはいつでも証明可能です。似たような現象は他の、「〜以下」の証明などの重要な事例にも当てはまります。このため、proof irrelevance はしばしば公理を表明せずに証明できます。
%\bigskip%
集合論に無いような複雑さを避けるためによく仮定される基本的な公理が他に2つあります。 *)
Require Import FunctionalExtensionality.
Print functional_extensionality_dep.
(*
(** %\vspace{-.15in}% [[
*** [ functional_extensionality_dep :
forall (A : Type) (B : A -> Type) (f g : forall x : A, B x),
(forall x : A, f x = g x) -> f = g ]
]]
This axiom says that two functions are equal if they map equal inputs to equal outputs. Such facts are not provable in general in CIC, but it is consistent to assume that they are.
A simple corollary shows that the same property applies to predicates. *)
*)
(** %\vspace{-.15in}% [[
*** [ functional_extensionality_dep :
forall (A : Type) (B : A -> Type) (f g : forall x : A, B x),
(forall x : A, f x = g x) -> f = g ]
]]
この公理は、等価な入力を等価な出力に写像する2つの関数は等価であると述べています。そのような事実は一般に CIC では証明できませんが、それがあると仮定しても無矛盾です。
単純な系により、述語において同様の性質を適用できます。*)
Corollary predicate_extensionality : forall (A : Type) (B : A -> Prop) (f g : forall x : A, B x),
(forall x : A, f x = g x) -> f = g.
intros; apply functional_extensionality_dep; assumption.
Qed.
(*
(** In some cases, one might prefer to assert this corollary as the axiom, to restrict the consequences to proofs and not programs. *)
*)
(** いくつかの場合には、その結論を証明にのみ制限しプログラムには適用しないようにするため、この系を公理として表明したいこともあるでしょう。*)
(*
(** ** Axioms of Choice *)
*)
(** ** 選択公理 *)
(*
(** Some Coq axioms are also points of contention in mainstream math. The most prominent example is the %\index{axiom of choice}%axiom of choice. In fact, there are multiple versions that we might consider, and, considered in isolation, none of these versions means quite what it means in classical set theory.
First, it is possible to implement a choice operator _without_ axioms in some potentially surprising cases. *)
*)
(** いくつかの Coq の公理は主流の数学における論点でもあります。最も顕著な例は%\index{選択公理}%選択公理です。実際、考慮すべき複数のバージョンがあり、独立して考慮すべきであり、どのバージョンも古典的な集合論における意味と同じことを必ずしも意味しません。
まず、公理を_用いず_に選択演算子を実装できるいくつかの驚くべきかもしれないケースがあります。 *)
Require Import ConstructiveEpsilon.
Check constructive_definite_description.
(** %\vspace{-.15in}% [[
constructive_definite_description
: forall (A : Set) (f : A -> nat) (g : nat -> A),
(forall x : A, g (f x) = x) ->
forall P : A -> Prop,
(forall x : A, {P x} + { ~ P x}) ->
(exists! x : A, P x) -> {x : A | P x}
]]
*)
Print Assumptions constructive_definite_description.
(*
(** <<
Closed under the global context
>>
This function transforms a decidable predicate [P] into a function that produces an element satisfying [P] from a proof that such an element exists. The functions [f] and [g], in conjunction with an associated injectivity property, are used to express the idea that the set [A] is countable. Under these conditions, a simple brute force algorithm gets the job done: we just enumerate all elements of [A], stopping when we find one satisfying [P]. The existence proof, specified in terms of _unique_ existence [exists!], guarantees termination. The definition of this operator in Coq uses some interesting techniques, as seen in the implementation of the [ConstructiveEpsilon] module.
Countable choice is provable in set theory without appealing to the general axiom of choice. To support the more general principle in Coq, we must also add an axiom. Here is a functional version of the axiom of unique choice. *)
*)
(** <<
Closed under the global context
>>
この関数は決定可能な述語 [P] を、 [P] を満たす要素が存在するという証明から、その要素を出力する関数へと変換する関数です。関数 [f] と [g] は、それと結びついた単射性の性質と共に用いられ、集合 [A] が可算であるというアイデアを表現しています。このような条件下では、単純なブルートフォースのアルゴリズムが用を為します。つまり、全ての [A] の要素を列挙し、[P] を満たす要素が見つかったら止まればよいのです。_唯一_存在する [exists!] という方法で述べられた存在証明が、停止性を保証してくれます。[ConstructiveEpsilon] モジュールの実装に見られるように、Coq におけるこの演算子の定義はいくつかの興味深いテクニックを使っています。
集合論において、可算個の選択は一般の選択公理に訴えることなく証明可能です。Coq でより一般的な原理を裏付けるには、やはり公理を加えねばなりません。これが汎関数バージョンの、唯一性をもつ選択の公理 (axiom of unique choice) です。 *)
Require Import ClassicalUniqueChoice.
Check dependent_unique_choice.
(*
(** %\vspace{-.15in}% [[
dependent_unique_choice
: forall (A : Type) (B : A -> Type) (R : forall x : A, B x -> Prop),
(forall x : A, exists! y : B x, R x y) ->
exists f : forall x : A, B x,
forall x : A, R x (f x)
]]
This axiom lets us convert a relational specification [R] into a function implementing that specification. We need only prove that [R] is truly a function. An alternate, stronger formulation applies to cases where [R] maps each input to one or more outputs. We also simplify the statement of the theorem by considering only non-dependent function types. *)
*)
(** %\vspace{-.15in}% [[
dependent_unique_choice
: forall (A : Type) (B : A -> Type) (R : forall x : A, B x -> Prop),
(forall x : A, exists! y : B x, R x y) ->
exists f : forall x : A, B x,
forall x : A, R x (f x)
]]
この公理は関係による仕様 [R] を、その仕様を実装する関数に変換してくれます。我々は、[R] が真に関数であると証明すれば良いのです。別の、より強い定式化により、[R] がそれぞれの入力を一つ以上の出力に写像する場合に適用されます。非依存的な関数型(non-dependent function types)についてのみ考慮して、この定理をより単純化します。*)
(* begin hide *)
(* begin thide *)
Require RelationalChoice.
(* end thide *)
(* end hide *)
Require Import ClassicalChoice.
Check choice.
(*
(** %\vspace{-.15in}% [[
choice
: forall (A B : Type) (R : A -> B -> Prop),
(forall x : A, exists y : B, R x y) ->
exists f : A -> B, forall x : A, R x (f x)
]]
This principle is proved as a theorem, based on the unique choice axiom and an additional axiom of relational choice from the [RelationalChoice] module.
In set theory, the axiom of choice is a fundamental philosophical commitment one makes about the universe of sets. In Coq, the choice axioms say something weaker. For instance, consider the simple restatement of the [choice] axiom where we replace existential quantification by its Curry-Howard analogue, subset types. *)
*)
(** %\vspace{-.15in}% [[
choice
: forall (A B : Type) (R : A -> B -> Prop),
(forall x : A, exists y : B, R x y) ->
exists f : A -> B, forall x : A, R x (f x)
]]
この原理は、唯一性を持つ選択の公理と、 [RelationalChoice] モジュールの、関係についての選択に関する追加の公理に基づき、定理として証明されます。
集合論では、選択公理は基礎的かつ哲学的な、集合の宇宙に関する約束事です。Coq における選択公理は、何かしら弱いことを述べています。例えば、存在量化を部分集合型に関するカリー・ハワードのアナロジーで置き換えた、[choice] 公理の単純な言い換えについて考えてみましょう。 *)
Definition choice_Set (A B : Type) (R : A -> B -> Prop) (H : forall x : A, {y : B | R x y})
: {f : A -> B | forall x : A, R x (f x)} :=
exist (fun f => forall x : A, R x (f x))
(fun x => proj1_sig (H x)) (fun x => proj2_sig (H x)).
(*
(** %\smallskip{}%Via the Curry-Howard correspondence, this "axiom" can be taken to have the same meaning as the original. It is implemented trivially as a transformation not much deeper than uncurrying. Thus, we see that the utility of the axioms that we mentioned earlier comes in their usage to build programs from proofs. Normal set theory has no explicit proofs, so the meaning of the usual axiom of choice is subtly different. In Gallina, the axioms implement a controlled relaxation of the restrictions on information flow from proofs to programs.
However, when we combine an axiom of choice with the law of the excluded middle, the idea of "choice" becomes more interesting. Excluded middle gives us a highly non-computational way of constructing proofs, but it does not change the computational nature of programs. Thus, the axiom of choice is still giving us a way of translating between two different sorts of "programs," but the input programs (which are proofs) may be written in a rich language that goes beyond normal computability. This combination truly is more than repackaging a function with a different type.
%\bigskip%
The Coq tools support a command-line flag %\index{impredicative Set}%<<-impredicative-set>>, which modifies Gallina in a more fundamental way by making [Set] impredicative. A term like [forall T : Set, T] has type [Set], and inductive definitions in [Set] may have constructors that quantify over arguments of any types. To maintain consistency, an elimination restriction must be imposed, similarly to the restriction for [Prop]. The restriction only applies to large inductive types, where some constructor quantifies over a type of type [Type]. In such cases, a value in this inductive type may only be pattern-matched over to yield a result type whose type is [Set] or [Prop]. This rule contrasts with the rule for [Prop], where the restriction applies even to non-large inductive types, and where the result type may only have type [Prop].
In old versions of Coq, [Set] was impredicative by default. Later versions make [Set] predicative to avoid inconsistency with some classical axioms. In particular, one should watch out when using impredicative [Set] with axioms of choice. In combination with excluded middle or predicate extensionality, inconsistency can result. Impredicative [Set] can be useful for modeling inherently impredicative mathematical concepts, but almost all Coq developments get by fine without it. *)
*)
(** %\smallskip{}%カリー・ハワード同型対応を介して、この「公理」はオリジナルと同じ意味を持つと見なすことができます。これは、非カリー化よりもそれほど深くない変換によって、ごく簡単に実装できます。このため、以前に言及したこの公理の実用性は、証明からプログラムを構築するための使用法として現れることが分かります。普通の集合論は陽に証明を扱わないため、通常の選択公理とは微妙に意味が違います。Gallina では、この公理は、証明からプログラムへの情報流の制限について、管理されたやり方により緩和する方法を実装します。
しかしながら、選択公理と排中律を組み合わせると、「選択」のアイデアはより興味深いものとなります。排中律は非常に非計算論的な方法で証明を構築する方法を提供しますが、プログラムの計算論的な性質を変えることはありません。このため、選択公理は二種類の「プログラム」の間を変換する方法を依然として提供していますが、入力となるプログラム (証明) は通常の計算可能性を超えたリッチな言語で書かれているかもしれません。この組み合わせは関数を別の型で再パッケージ化する以上のものです。
%\bigskip%
Coq のツールはコマンドラインフラグ%\index{impredicative Set}%<<-impredicative-set>> をサポートしており、これは [Set] を非可述的にすることにより Gallina を根本的に変えてしまいます。[forall T : Set, T] のような項は型 [Set] を持ち、[Set] における帰納的定義は任意の型の上で量化した構築子を持つことができます。無矛盾性を保つため、[Prop] における制限と同様に、除去の制限が課されます。この制限は、型 [Type] をもつ型の上で量化するいくつかの構築子をもつ、大きな帰納型にのみ適用されます。そのような場合、この帰納型の値は [Set] か [Prop] の型を持つ結果の型を返すためにだけパターンマッチできます。この規則は、この制限が大きくない帰納型にも適用され、結果の型が型 [Prop] しか持てない [Prop] のそれとは対照的です。
Coq の古いバージョンでは、[Set] はデフォルトで非可述的でした。後のバージョンでは、古典論理の公理との矛盾を避けるため [Set] は可述的になっています。特に、非可述的な [Set] と選択公理を共に用いる時に注意が必要です。排中律や述語の外延性 (predicate extensionality) と組み合わせることで、矛盾が起こり得ます。非可述的な [Set] は本質的に非可述的な概念をモデル化するのに便利ですが、Coq における開発のほとんどはそれ無しでも大丈夫です。 *)
(*
(** ** Axioms and Computation *)
*)
(** ** 公理と計算 *)
(*
(** One additional axiom-related wrinkle arises from an aspect of Gallina that is very different from set theory: a notion of _computational equivalence_ is central to the definition of the formal system. Axioms tend not to play well with computation. Consider this example. We start by implementing a function that uses a type equality proof to perform a safe type-cast. *)
*)
(** Gallinaに由来し、集合論とは非常に異なる側面に由来した、公理に関するもう一つの引っかかり(winkle)があります。それは、_computational equivalence_ という、この形式体系の定義における中心的な概念です。公理は計算とあまりうまくやってくれない傾向があります。この例を考えてみてください。まず安全な型キャストを行うために型の等価性証明を使う関数を実装します。 *)
Definition cast (x y : Set) (pf : x = y) (v : x) : y :=
match pf with
| eq_refl => v
end.
(*
(** Computation over programs that use [cast] can proceed smoothly. *)
*)
(** [cast] を用いるプログラムの計算はスムースに進行できます。*)
Eval compute in (cast (eq_refl (nat -> nat)) (fun n => S n)) 12.
(** %\vspace{-.15in}%[[
= 13
: nat
]]
*)
(*
(** Things do not go as smoothly when we use [cast] with proofs that rely on axioms. *)
*)
(** [cast] を公理に依存する証明とともに用いたとき、スムースにはいかなくなります。 *)
Theorem t3 : (forall n : nat, fin (S n)) = (forall n : nat, fin (n + 1)).
change ((forall n : nat, (fun n => fin (S n)) n) = (forall n : nat, (fun n => fin (n + 1)) n));
rewrite (functional_extensionality (fun n => fin (n + 1)) (fun n => fin (S n))); crush.
Qed.
Eval compute in (cast t3 (fun _ => First)) 12.
(*
(** %\vspace{-.15in}%[[
= match t3 in (_ = P) return P with
| eq_refl => fun n : nat => First
end 12
: fin (12 + 1)
]]
Computation gets stuck in a pattern-match on the proof [t3]. The structure of [t3] is not known, so the match cannot proceed. It turns out a more basic problem leads to this particular situation. We ended the proof of [t3] with [Qed], so the definition of [t3] is not available to computation. That mistake is easily fixed. *)
*)
(** %\vspace{-.15in}%[[
= match t3 in (_ = P) return P with
| eq_refl => fun n : nat => First
end 12
: fin (12 + 1)
]]
証明 [t3] のパターンマッチで計算が詰まって (stuck) います。[t3] の構造が分かっておらず、照合が進められないのです。より基本的な問題から、この特別な状況に至っているのです。この [t3] の証明を [Qed] で終えたため、[t3] の証明は計算において利用できないのです。この失敗は簡潔に修正できます。*)
Reset t3.
Theorem t3 : (forall n : nat, fin (S n)) = (forall n : nat, fin (n + 1)).
change ((forall n : nat, (fun n => fin (S n)) n) = (forall n : nat, (fun n => fin (n + 1)) n));
rewrite (functional_extensionality (fun n => fin (n + 1)) (fun n => fin (S n))); crush.
Defined.
Eval compute in (cast t3 (fun _ => First)) 12.
(*
(** %\vspace{-.15in}%[[
= match
match
match
functional_extensionality
....
]]
We elide most of the details. A very unwieldy tree of nested matches on equality proofs appears. This time evaluation really _is_ stuck on a use of an axiom.
If we are careful in using tactics to prove an equality, we can still compute with casts over the proof. *)
*)
(** %\vspace{-.15in}%[[
= match
match
match
functional_extensionality
....
]]
殆どの詳細は省略します。等価性証明を照合するネストした手に負えない大きさの木が現れます。今度こそ、公理を用いることで評価が本当に_詰まった_のです。
もし我々が等価性を証明するために注意深くタクティクを使うならば、依然として証明の上でキャストを用いることができます。*)
Lemma plus1 : forall n, S n = n + 1.
induction n; simpl; intuition.
Defined.
Theorem t4 : forall n, fin (S n) = fin (n + 1).
intro; f_equal; apply plus1.
Defined.
Eval compute in cast (t4 13) First.
(*
(** %\vspace{-.15in}% [[
= First
: fin (13 + 1)
]]
This simple computational reduction hides the use of a recursive function to produce a suitable [eq_refl] proof term. The recursion originates in our use of [induction] in [t4]'s proof. *)
*)
(** %\vspace{-.15in}% [[
= First
: fin (13 + 1)
]]
この単純で計算的な簡約により、適切な [eq_refl] の証明項を生成する再帰関数の使用を隠しています。この再帰は [t4] の証明に対する我々の [induction] の使用に由来しています。 *)
(*
(** ** Methods for Avoiding Axioms *)
*)
(** ** 公理を避けるための手法 *)
(** The last section demonstrated one reason to avoid axioms: they interfere with computational behavior of terms. A further reason is to reduce the philosophical commitment of a theorem. The more axioms one assumes, the harder it becomes to convince oneself that the formal system corresponds appropriately to one's intuitions. A refinement of this last point, in applications like %\index{proof-carrying code}%proof-carrying code%~\cite{PCC}% in computer security, has to do with minimizing the size of a%\index{trusted code base}% _trusted code base_. To convince ourselves that a theorem is true, we must convince ourselves of the correctness of the program that checks the theorem. Axioms effectively become new source code for the checking program, increasing the effort required to perform a correctness audit.
An earlier section gave one example of avoiding an axiom. We proved that [pred_strong1] is agnostic to details of the proofs passed to it as arguments, by unfolding the definition of the function. A "simpler" proof keeps the function definition opaque and instead applies a proof irrelevance axiom. By accepting a more complex proof, we reduce our philosophical commitment and trusted base. (By the way, the less-than relation that the proofs in question here prove turns out to admit proof irrelevance as a theorem provable within normal Gallina!)
One dark secret of the [dep_destruct] tactic that we have used several times is reliance on an axiom. Consider this simple case analysis principle for [fin] values: *)
Theorem fin_cases : forall n (f : fin (S n)), f = First \/ exists f', f = Next f'.
intros; dep_destruct f; eauto.
Qed.
(* begin hide *)
Require Import JMeq.
(* begin thide *)
Definition jme := (JMeq, JMeq_eq).
(* end thide *)
(* end hide *)
Print Assumptions fin_cases.
(** %\vspace{-.15in}%[[
Axioms:
JMeq_eq : forall (A : Type) (x y : A), JMeq x y -> x = y
]]
The proof depends on the [JMeq_eq] axiom that we met in the chapter on equality proofs. However, a smarter tactic could have avoided an axiom dependence. Here is an alternate proof via a slightly strange looking lemma. *)
(* begin thide *)
Lemma fin_cases_again' : forall n (f : fin n),
match n return fin n -> Prop with
| O => fun _ => False
| S n' => fun f => f = First \/ exists f', f = Next f'
end f.
destruct f; eauto.
Qed.
(** We apply a variant of the %\index{convoy pattern}%convoy pattern, which we are used to seeing in function implementations. Here, the pattern helps us state a lemma in a form where the argument to [fin] is a variable. Recall that, thanks to basic typing rules for pattern-matching, [destruct] will only work effectively on types whose non-parameter arguments are variables. The %\index{tactics!exact}%[exact] tactic, which takes as argument a literal proof term, now gives us an easy way of proving the original theorem. *)
Theorem fin_cases_again : forall n (f : fin (S n)), f = First \/ exists f', f = Next f'.
intros; exact (fin_cases_again' f).
Qed.
(* end thide *)
Print Assumptions fin_cases_again.
(** %\vspace{-.15in}%
<<
Closed under the global context
>>
*)
(* begin thide *)
(** As the Curry-Howard correspondence might lead us to expect, the same pattern may be applied in programming as in proving. Axioms are relevant in programming, too, because, while Coq includes useful extensions like [Program] that make dependently typed programming more straightforward, in general these extensions generate code that relies on axioms about equality. We can use clever pattern matching to write our code axiom-free.
As an example, consider a [Set] version of [fin_cases]. We use [Set] types instead of [Prop] types, so that return values have computational content and may be used to guide the behavior of algorithms. Beside that, we are essentially writing the same "proof" in a more explicit way. *)
Definition finOut n (f : fin n) : match n return fin n -> Type with
| O => fun _ => Empty_set
| _ => fun f => {f' : _ | f = Next f'} + {f = First}
end f :=
match f with
| First _ => inright _ (eq_refl _)
| Next _ f' => inleft _ (exist _ f' (eq_refl _))
end.
(* end thide *)
(** As another example, consider the following type of formulas in first-order logic. The intent of the type definition will not be important in what follows, but we give a quick intuition for the curious reader. Our formulas may include [forall] quantification over arbitrary [Type]s, and we index formulas by environments telling which variables are in scope and what their types are; such an environment is a [list Type]. A constructor [Inject] lets us include any Coq [Prop] as a formula, and [VarEq] and [Lift] can be used for variable references, in what is essentially the de Bruijn index convention. (Again, the detail in this paragraph is not important to understand the discussion that follows!) *)
Inductive formula : list Type -> Type :=
| Inject : forall Ts, Prop -> formula Ts
| VarEq : forall T Ts, T -> formula (T :: Ts)
| Lift : forall T Ts, formula Ts -> formula (T :: Ts)
| Forall : forall T Ts, formula (T :: Ts) -> formula Ts
| And : forall Ts, formula Ts -> formula Ts -> formula Ts.
(** This example is based on my own experiences implementing variants of a program logic called XCAP%~\cite{XCAP}%, which also includes an inductive predicate for characterizing which formulas are provable. Here I include a pared-down version of such a predicate, with only two constructors, which is sufficient to illustrate certain tricky issues. *)
Inductive proof : formula nil -> Prop :=
| PInject : forall (P : Prop), P -> proof (Inject nil P)
| PAnd : forall p q, proof p -> proof q -> proof (And p q).
(** Let us prove a lemma showing that a "[P /\ Q -> P]" rule is derivable within the rules of [proof]. *)
Theorem proj1 : forall p q, proof (And p q) -> proof p.
destruct 1.
(** %\vspace{-.15in}%[[
p : formula nil
q : formula nil
P : Prop
H : P
============================
proof p
]]
*)
(** We are reminded that [induction] and [destruct] do not work effectively on types with non-variable arguments. The first subgoal, shown above, is clearly unprovable. (Consider the case where [p = Inject nil False].)
An application of the %\index{tactics!dependent destruction}%[dependent destruction] tactic (the basis for [dep_destruct]) solves the problem handily. We use a shorthand with the %\index{tactics!intros}%[intros] tactic that lets us use question marks for variable names that do not matter. *)
Restart.
Require Import Program.
intros ? ? H; dependent destruction H; auto.
Qed.
Print Assumptions proj1.
(** %\vspace{-.15in}%[[
Axioms:
eq_rect_eq : forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = eq_rect p Q x p h
]]
Unfortunately, that built-in tactic appeals to an axiom. It is still possible to avoid axioms by giving the proof via another odd-looking lemma. Here is a first attempt that fails at remaining axiom-free, using a common equality-based trick for supporting induction on non-variable arguments to type families. The trick works fine without axioms for datatypes more traditional than [formula], but we run into trouble with our current type. *)
Lemma proj1_again' : forall r, proof r
-> forall p q, r = And p q -> proof p.
destruct 1; crush.
(** %\vspace{-.15in}%[[
H0 : Inject [] P = And p q
============================
proof p
]]
The first goal looks reasonable. Hypothesis [H0] is clearly contradictory, as [discriminate] can show. *)
try discriminate. (* Note: Coq 8.6 is now solving this subgoal automatically!
* This line left here to keep everything working in
* 8.4, 8.5, and 8.6. *)
(** %\vspace{-.15in}%[[
H : proof p
H1 : And p q = And p0 q0
============================
proof p0
]]
It looks like we are almost done. Hypothesis [H1] gives [p = p0] by injectivity of constructors, and then [H] finishes the case. *)
injection H1; intros.
(* begin hide *)
(* begin thide *)
Definition existT' := existT.
(* end thide *)
(* end hide *)
(** Unfortunately, the "equality" that we expected between [p] and [p0] comes in a strange form:
[[
H3 : existT (fun Ts : list Type => formula Ts) []%list p =
existT (fun Ts : list Type => formula Ts) []%list p0
============================
proof p0
]]
It may take a bit of tinkering, but, reviewing Chapter 3's discussion of writing injection principles manually, it makes sense that an [existT] type is the most direct way to express the output of [injection] on a dependently typed constructor. The constructor [And] is dependently typed, since it takes a parameter [Ts] upon which the types of [p] and [q] depend. Let us not dwell further here on why this goal appears; the reader may like to attempt the (impossible) exercise of building a better injection lemma for [And], without using axioms.
How exactly does an axiom come into the picture here? Let us ask [crush] to finish the proof. *)
crush.
Qed.
Print Assumptions proj1_again'.
(** %\vspace{-.15in}%[[
Axioms:
eq_rect_eq : forall (U : Type) (p : U) (Q : U -> Type) (x : Q p) (h : p = p),
x = eq_rect p Q x p h
]]
It turns out that this familiar axiom about equality (or some other axiom) is required to deduce [p = p0] from the hypothesis [H3] above. The soundness of that proof step is neither provable nor disprovable in Gallina.
Hope is not lost, however. We can produce an even stranger looking lemma, which gives us the theorem without axioms. As always when we want to do case analysis on a term with a tricky dependent type, the key is to refactor the theorem statement so that every term we [match] on has _variables_ as its type indices; so instead of talking about proofs of [And p q], we talk about proofs of an arbitrary [r], but we only conclude anything interesting when [r] is an [And]. *)
Lemma proj1_again'' : forall r, proof r
-> match r with
| And Ps p _ => match Ps return formula Ps -> Prop with
| nil => fun p => proof p
| _ => fun _ => True
end p
| _ => True
end.
destruct 1; auto.
Qed.
Theorem proj1_again : forall p q, proof (And p q) -> proof p.
intros ? ? H; exact (proj1_again'' H).
Qed.
Print Assumptions proj1_again.
(** <<
Closed under the global context
>>
This example illustrates again how some of the same design patterns we learned for dependently typed programming can be used fruitfully in theorem statements.
%\medskip%
To close the chapter, we consider one final way to avoid dependence on axioms. Often this task is equivalent to writing definitions such that they _compute_. That is, we want Coq's normal reduction to be able to run certain programs to completion. Here is a simple example where such computation can get stuck. In proving properties of such functions, we would need to apply axioms like %\index{axiom K}%K manually to make progress.
Imagine we are working with %\index{deep embedding}%deeply embedded syntax of some programming language, where each term is considered to be in the scope of a number of free variables that hold normal Coq values. To enforce proper typing, we will need to model a Coq typing environment somehow. One natural choice is as a list of types, where variable number [i] will be treated as a reference to the [i]th element of the list. *)
Section withTypes.
Variable types : list Set.
(** To give the semantics of terms, we will need to represent value environments, which assign each variable a term of the proper type. *)
Variable values : hlist (fun x : Set => x) types.
(** Now imagine that we are writing some procedure that operates on a distinguished variable of type [nat]. A hypothesis formalizes this assumption, using the standard library function [nth_error] for looking up list elements by position. *)
Variable natIndex : nat.
Variable natIndex_ok : nth_error types natIndex = Some nat.
(** It is not hard to use this hypothesis to write a function for extracting the [nat] value in position [natIndex] of [values], starting with two helpful lemmas, each of which we finish with [Defined] to mark the lemma as transparent, so that its definition may be expanded during evaluation. *)
Lemma nth_error_nil : forall A n x,
nth_error (@nil A) n = Some x
-> False.
destruct n; simpl; unfold error; congruence.
Defined.
Arguments nth_error_nil [A n x] _.
Lemma Some_inj : forall A (x y : A),
Some x = Some y
-> x = y.
congruence.
Defined.
Fixpoint getNat (types' : list Set) (values' : hlist (fun x : Set => x) types')
(natIndex : nat) : (nth_error types' natIndex = Some nat) -> nat :=
match values' with
| HNil => fun pf => match nth_error_nil pf with end
| HCons t ts x values'' =>
match natIndex return nth_error (t :: ts) natIndex = Some nat -> nat with
| O => fun pf =>
match Some_inj pf in _ = T return T with
| eq_refl => x
end
| S natIndex' => getNat values'' natIndex'
end
end.
End withTypes.
(** The problem becomes apparent when we experiment with running [getNat] on a concrete [types] list. *)
Definition myTypes := unit :: nat :: bool :: nil.
Definition myValues : hlist (fun x : Set => x) myTypes :=
tt ::: 3 ::: false ::: HNil.
Definition myNatIndex := 1.
Theorem myNatIndex_ok : nth_error myTypes myNatIndex = Some nat.
reflexivity.
Defined.
Eval compute in getNat myValues myNatIndex myNatIndex_ok.
(** %\vspace{-.15in}%[[
= 3
]]
We have not hit the problem yet, since we proceeded with a concrete equality proof for [myNatIndex_ok]. However, consider a case where we want to reason about the behavior of [getNat] _independently_ of a specific proof. *)
Theorem getNat_is_reasonable : forall pf, getNat myValues myNatIndex pf = 3.
intro; compute.
(**
<<
1 subgoal
>>
%\vspace{-.3in}%[[
pf : nth_error myTypes myNatIndex = Some nat
============================
match
match
pf in (_ = y)
return (nat = match y with
| Some H => H
| None => nat
end)
with
| eq_refl => eq_refl
end in (_ = T) return T
with
| eq_refl => 3
end = 3
]]
Since the details of the equality proof [pf] are not known, computation can proceed no further. A rewrite with axiom K would allow us to make progress, but we can rethink the definitions a bit to avoid depending on axioms. *)
Abort.
(** Here is a definition of a function that turns out to be useful, though no doubt its purpose will be mysterious for now. A call [update ls n x] overwrites the [n]th position of the list [ls] with the value [x], padding the end of the list with extra [x] values as needed to ensure sufficient length. *)
Fixpoint copies A (x : A) (n : nat) : list A :=
match n with
| O => nil
| S n' => x :: copies x n'
end.
Fixpoint update A (ls : list A) (n : nat) (x : A) : list A :=
match ls with
| nil => copies x n ++ x :: nil
| y :: ls' => match n with
| O => x :: ls'
| S n' => y :: update ls' n' x
end
end.
(** Now let us revisit the definition of [getNat]. *)
Section withTypes'.
Variable types : list Set.
Variable natIndex : nat.
(** Here is the trick: instead of asserting properties about the list [types], we build a "new" list that is _guaranteed by construction_ to have those properties. *)
Definition types' := update types natIndex nat.
Variable values : hlist (fun x : Set => x) types'.
(** Now a bit of dependent pattern matching helps us rewrite [getNat] in a way that avoids any use of equality proofs. *)
Fixpoint skipCopies (n : nat)
: hlist (fun x : Set => x) (copies nat n ++ nat :: nil) -> nat :=
match n with
| O => fun vs => hhd vs
| S n' => fun vs => skipCopies n' (htl vs)
end.
Fixpoint getNat' (types'' : list Set) (natIndex : nat)
: hlist (fun x : Set => x) (update types'' natIndex nat) -> nat :=
match types'' with
| nil => skipCopies natIndex
| t :: types0 =>
match natIndex return hlist (fun x : Set => x)
(update (t :: types0) natIndex nat) -> nat with
| O => fun vs => hhd vs
| S natIndex' => fun vs => getNat' types0 natIndex' (htl vs)
end
end.
End withTypes'.
(** Now the surprise comes in how easy it is to _use_ [getNat']. While typing works by modification of a types list, we can choose parameters so that the modification has no effect. *)
Theorem getNat_is_reasonable : getNat' myTypes myNatIndex myValues = 3.
reflexivity.
Qed.
(** The same parameters as before work without alteration, and we avoid use of axioms. *)
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 19 17:53:12 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.v
// Design : fifo_generator_rx_inst
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty);
(* x_interface_info = "xilinx.com:signal:clock:1.0 core_clk CLK" *) input clk;
input srst;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire srst;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [11:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [11:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [11:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "12" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FULL_FLAGS_RST_VAL = "0" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "0" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "1" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "4kx9" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "4094" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "4093" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "12" *)
(* C_RD_DEPTH = "4096" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "12" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "12" *)
(* C_WR_DEPTH = "4096" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "12" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(clk),
.data_count(NLW_U0_data_count_UNCONNECTED[11:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[11:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(srst),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[11:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.Q(Q),
.clk(clk),
.din(din[3:0]),
.dout(dout[3:0]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.Q(Q),
.clk(clk),
.din(din[12:4]),
.dout(dout[12:4]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.Q(Q),
.clk(clk),
.din(din[21:13]),
.dout(dout[21:13]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.Q(Q),
.clk(clk),
.din(din[30:22]),
.dout(dout[30:22]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.Q(Q),
.clk(clk),
.din(din[39:31]),
.dout(dout[39:31]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.Q(Q),
.clk(clk),
.din(din[48:40]),
.dout(dout[48:40]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.Q(Q),
.clk(clk),
.din(din[57:49]),
.dout(dout[57:49]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.Q(Q),
.clk(clk),
.din(din[63:58]),
.dout(dout[63:58]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [3:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [3:0]din;
wire [11:0]Q;
wire clk;
wire [3:0]din;
wire [3:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [5:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [5:0]din;
wire [11:0]Q;
wire clk;
wire [5:0]din;
wire [5:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [3:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [3:0]din;
wire [11:0]Q;
wire clk;
wire [3:0]din;
wire [3:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({Q,1'b0,1'b0}),
.ADDRBWRADDR({\gc0.count_d1_reg[11] ,1'b0,1'b0}),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:4],dout}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(srst),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(srst),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(srst),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(srst),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(srst),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(srst),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(srst),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [5:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [5:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [11:0]Q;
wire clk;
wire [5:0]din;
wire [5:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,dout}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(srst),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
(ram_full_fb_i_reg,
v1_reg,
wr_en,
comp1,
out,
rd_en,
ram_empty_fb_i_reg);
output ram_full_fb_i_reg;
input [5:0]v1_reg;
input wr_en;
input comp1;
input out;
input rd_en;
input ram_empty_fb_i_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp0;
wire comp1;
wire out;
wire ram_empty_fb_i_reg;
wire ram_full_fb_i_reg;
wire rd_en;
wire [5:0]v1_reg;
wire wr_en;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT6 #(
.INIT(64'hFFC0FFC05500FFC0))
ram_full_fb_i_i_1
(.I0(comp0),
.I1(wr_en),
.I2(comp1),
.I3(out),
.I4(rd_en),
.I5(ram_empty_fb_i_reg),
.O(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0
(comp1,
v1_reg_0);
output comp1;
input [5:0]v1_reg_0;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp1;
wire [5:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg_0[5:4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1
(ram_empty_i_reg,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[10] ,
rd_en,
out,
comp1,
wr_en,
ram_full_fb_i_reg);
output ram_empty_i_reg;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gcc0.gc0.count_d1_reg[10] ;
input rd_en;
input out;
input comp1;
input wr_en;
input ram_full_fb_i_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp0;
wire comp1;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire rd_en;
wire wr_en;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S({\gcc0.gc0.count_d1_reg[6] ,\gcc0.gc0.count_d1_reg[4] ,\gcc0.gc0.count_d1_reg[2] ,\gcc0.gc0.count_d1_reg[0] }));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gcc0.gc0.count_d1_reg[10] ,\gcc0.gc0.count_d1_reg[8] }));
LUT6 #(
.INIT(64'hFCF0FCF05050FCF0))
ram_empty_fb_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(out),
.I3(comp1),
.I4(wr_en),
.I5(ram_full_fb_i_reg),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2
(comp1,
v1_reg);
output comp1;
input [5:0]v1_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp1;
wire [5:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
(dout,
empty,
full,
wr_en,
rd_en,
clk,
srst,
din);
output [63:0]dout;
output empty;
output full;
input wr_en;
input rd_en;
input clk;
input srst;
input [63:0]din;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.wr_n_0 ;
wire \gntv_or_sync_fifo.gl0.wr_n_2 ;
wire \gntv_or_sync_fifo.gl0.wr_n_21 ;
wire \gntv_or_sync_fifo.gl0.wr_n_22 ;
wire \gntv_or_sync_fifo.gl0.wr_n_23 ;
wire \gntv_or_sync_fifo.gl0.wr_n_24 ;
wire \gntv_or_sync_fifo.gl0.wr_n_25 ;
wire \gntv_or_sync_fifo.gl0.wr_n_26 ;
wire [5:0]\grss.rsts/c2/v1_reg ;
wire [11:0]p_0_out;
wire [11:0]p_11_out;
wire p_2_out;
wire rd_en;
wire [11:0]rd_pntr_plus1;
wire srst;
wire tmp_ram_rd_en;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic \gntv_or_sync_fifo.gl0.rd
(.D(rd_pntr_plus1),
.Q(p_0_out),
.clk(clk),
.empty(empty),
.\gcc0.gc0.count_d1_reg[0] (\gntv_or_sync_fifo.gl0.wr_n_21 ),
.\gcc0.gc0.count_d1_reg[10] (\gntv_or_sync_fifo.gl0.wr_n_26 ),
.\gcc0.gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.wr_n_22 ),
.\gcc0.gc0.count_d1_reg[4] (\gntv_or_sync_fifo.gl0.wr_n_23 ),
.\gcc0.gc0.count_d1_reg[6] (\gntv_or_sync_fifo.gl0.wr_n_24 ),
.\gcc0.gc0.count_d1_reg[8] (\gntv_or_sync_fifo.gl0.wr_n_25 ),
.out(p_2_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.rd_en(rd_en),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic \gntv_or_sync_fifo.gl0.wr
(.D(rd_pntr_plus1),
.Q(p_11_out),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[11] (p_0_out),
.\gcc0.gc0.count_d1_reg[11] (\gntv_or_sync_fifo.gl0.wr_n_2 ),
.out(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gl0.wr_n_21 ),
.ram_empty_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_22 ),
.ram_empty_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_23 ),
.ram_empty_i_reg_2(\gntv_or_sync_fifo.gl0.wr_n_24 ),
.ram_empty_i_reg_3(\gntv_or_sync_fifo.gl0.wr_n_25 ),
.ram_empty_i_reg_4(\gntv_or_sync_fifo.gl0.wr_n_26 ),
.rd_en(rd_en),
.srst(srst),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory \gntv_or_sync_fifo.mem
(.Q(p_11_out),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (p_0_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
(dout,
empty,
full,
wr_en,
rd_en,
clk,
srst,
din);
output [63:0]dout;
output empty;
output full;
input wr_en;
input rd_en;
input clk;
input srst;
input [63:0]din;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire srst;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo \grf.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.srst(srst),
.wr_en(wr_en));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "12" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "64" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "0" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "0" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "1" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "4kx9" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "4094" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "4093" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "12" *)
(* C_RD_DEPTH = "4096" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "12" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "12" *)
(* C_WR_DEPTH = "4096" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "12" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [11:0]prog_empty_thresh;
input [11:0]prog_empty_thresh_assert;
input [11:0]prog_empty_thresh_negate;
input [11:0]prog_full_thresh;
input [11:0]prog_full_thresh_assert;
input [11:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [11:0]data_count;
output [11:0]rd_data_count;
output [11:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire srst;
wire wr_en;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[11] = \<const0> ;
assign data_count[10] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[11] = \<const0> ;
assign rd_data_count[10] = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[11] = \<const0> ;
assign wr_data_count[10] = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth inst_fifo_gen
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.srst(srst),
.wr_en(wr_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
(dout,
empty,
full,
wr_en,
rd_en,
clk,
srst,
din);
output [63:0]dout;
output empty;
output full;
input wr_en;
input rd_en;
input clk;
input srst;
input [63:0]din;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire srst;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top \gconvfifo.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.srst(srst),
.wr_en(wr_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
srst,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input srst;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire ram_full_fb_i_reg;
wire srst;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
(D,
Q,
srst,
E,
clk);
output [11:0]D;
output [11:0]Q;
input srst;
input [0:0]E;
input clk;
wire [11:0]D;
wire [0:0]E;
wire [11:0]Q;
wire clk;
wire \gc0.count[0]_i_2_n_0 ;
wire \gc0.count[0]_i_3_n_0 ;
wire \gc0.count[0]_i_4_n_0 ;
wire \gc0.count[0]_i_5_n_0 ;
wire \gc0.count[4]_i_2_n_0 ;
wire \gc0.count[4]_i_3_n_0 ;
wire \gc0.count[4]_i_4_n_0 ;
wire \gc0.count[4]_i_5_n_0 ;
wire \gc0.count[8]_i_2_n_0 ;
wire \gc0.count[8]_i_3_n_0 ;
wire \gc0.count[8]_i_4_n_0 ;
wire \gc0.count[8]_i_5_n_0 ;
wire \gc0.count_reg[0]_i_1_n_0 ;
wire \gc0.count_reg[0]_i_1_n_1 ;
wire \gc0.count_reg[0]_i_1_n_2 ;
wire \gc0.count_reg[0]_i_1_n_3 ;
wire \gc0.count_reg[0]_i_1_n_4 ;
wire \gc0.count_reg[0]_i_1_n_5 ;
wire \gc0.count_reg[0]_i_1_n_6 ;
wire \gc0.count_reg[0]_i_1_n_7 ;
wire \gc0.count_reg[4]_i_1_n_0 ;
wire \gc0.count_reg[4]_i_1_n_1 ;
wire \gc0.count_reg[4]_i_1_n_2 ;
wire \gc0.count_reg[4]_i_1_n_3 ;
wire \gc0.count_reg[4]_i_1_n_4 ;
wire \gc0.count_reg[4]_i_1_n_5 ;
wire \gc0.count_reg[4]_i_1_n_6 ;
wire \gc0.count_reg[4]_i_1_n_7 ;
wire \gc0.count_reg[8]_i_1_n_1 ;
wire \gc0.count_reg[8]_i_1_n_2 ;
wire \gc0.count_reg[8]_i_1_n_3 ;
wire \gc0.count_reg[8]_i_1_n_4 ;
wire \gc0.count_reg[8]_i_1_n_5 ;
wire \gc0.count_reg[8]_i_1_n_6 ;
wire \gc0.count_reg[8]_i_1_n_7 ;
wire srst;
wire [3:3]\NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h2))
\gc0.count[0]_i_2
(.I0(D[3]),
.O(\gc0.count[0]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[0]_i_3
(.I0(D[2]),
.O(\gc0.count[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[0]_i_4
(.I0(D[1]),
.O(\gc0.count[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_5
(.I0(D[0]),
.O(\gc0.count[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[4]_i_2
(.I0(D[7]),
.O(\gc0.count[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[4]_i_3
(.I0(D[6]),
.O(\gc0.count[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[4]_i_4
(.I0(D[5]),
.O(\gc0.count[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[4]_i_5
(.I0(D[4]),
.O(\gc0.count[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[8]_i_2
(.I0(D[11]),
.O(\gc0.count[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[8]_i_3
(.I0(D[10]),
.O(\gc0.count[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[8]_i_4
(.I0(D[9]),
.O(\gc0.count[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[8]_i_5
(.I0(D[8]),
.O(\gc0.count[8]_i_5_n_0 ));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.D(D[0]),
.Q(Q[0]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[10]
(.C(clk),
.CE(E),
.D(D[10]),
.Q(Q[10]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[11]
(.C(clk),
.CE(E),
.D(D[11]),
.Q(Q[11]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.D(D[1]),
.Q(Q[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.D(D[2]),
.Q(Q[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.D(D[3]),
.Q(Q[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(clk),
.CE(E),
.D(D[4]),
.Q(Q[4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(clk),
.CE(E),
.D(D[5]),
.Q(Q[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(clk),
.CE(E),
.D(D[6]),
.Q(Q[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(clk),
.CE(E),
.D(D[7]),
.Q(Q[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(clk),
.CE(E),
.D(D[8]),
.Q(Q[8]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(clk),
.CE(E),
.D(D[9]),
.Q(Q[9]),
.R(srst));
FDSE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(\gc0.count_reg[0]_i_1_n_7 ),
.Q(D[0]),
.S(srst));
CARRY4 \gc0.count_reg[0]_i_1
(.CI(1'b0),
.CO({\gc0.count_reg[0]_i_1_n_0 ,\gc0.count_reg[0]_i_1_n_1 ,\gc0.count_reg[0]_i_1_n_2 ,\gc0.count_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\gc0.count_reg[0]_i_1_n_4 ,\gc0.count_reg[0]_i_1_n_5 ,\gc0.count_reg[0]_i_1_n_6 ,\gc0.count_reg[0]_i_1_n_7 }),
.S({\gc0.count[0]_i_2_n_0 ,\gc0.count[0]_i_3_n_0 ,\gc0.count[0]_i_4_n_0 ,\gc0.count[0]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[10]
(.C(clk),
.CE(E),
.D(\gc0.count_reg[8]_i_1_n_5 ),
.Q(D[10]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[11]
(.C(clk),
.CE(E),
.D(\gc0.count_reg[8]_i_1_n_4 ),
.Q(D[11]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(clk),
.CE(E),
.D(\gc0.count_reg[0]_i_1_n_6 ),
.Q(D[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(clk),
.CE(E),
.D(\gc0.count_reg[0]_i_1_n_5 ),
.Q(D[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(clk),
.CE(E),
.D(\gc0.count_reg[0]_i_1_n_4 ),
.Q(D[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(clk),
.CE(E),
.D(\gc0.count_reg[4]_i_1_n_7 ),
.Q(D[4]),
.R(srst));
CARRY4 \gc0.count_reg[4]_i_1
(.CI(\gc0.count_reg[0]_i_1_n_0 ),
.CO({\gc0.count_reg[4]_i_1_n_0 ,\gc0.count_reg[4]_i_1_n_1 ,\gc0.count_reg[4]_i_1_n_2 ,\gc0.count_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\gc0.count_reg[4]_i_1_n_4 ,\gc0.count_reg[4]_i_1_n_5 ,\gc0.count_reg[4]_i_1_n_6 ,\gc0.count_reg[4]_i_1_n_7 }),
.S({\gc0.count[4]_i_2_n_0 ,\gc0.count[4]_i_3_n_0 ,\gc0.count[4]_i_4_n_0 ,\gc0.count[4]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(clk),
.CE(E),
.D(\gc0.count_reg[4]_i_1_n_6 ),
.Q(D[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(clk),
.CE(E),
.D(\gc0.count_reg[4]_i_1_n_5 ),
.Q(D[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(clk),
.CE(E),
.D(\gc0.count_reg[4]_i_1_n_4 ),
.Q(D[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(clk),
.CE(E),
.D(\gc0.count_reg[8]_i_1_n_7 ),
.Q(D[8]),
.R(srst));
CARRY4 \gc0.count_reg[8]_i_1
(.CI(\gc0.count_reg[4]_i_1_n_0 ),
.CO({\NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED [3],\gc0.count_reg[8]_i_1_n_1 ,\gc0.count_reg[8]_i_1_n_2 ,\gc0.count_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\gc0.count_reg[8]_i_1_n_4 ,\gc0.count_reg[8]_i_1_n_5 ,\gc0.count_reg[8]_i_1_n_6 ,\gc0.count_reg[8]_i_1_n_7 }),
.S({\gc0.count[8]_i_2_n_0 ,\gc0.count[8]_i_3_n_0 ,\gc0.count[8]_i_4_n_0 ,\gc0.count[8]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(clk),
.CE(E),
.D(\gc0.count_reg[8]_i_1_n_6 ),
.Q(D[9]),
.R(srst));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
(out,
empty,
D,
tmp_ram_rd_en,
Q,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[10] ,
v1_reg,
srst,
clk,
rd_en,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output [11:0]D;
output tmp_ram_rd_en;
output [11:0]Q;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gcc0.gc0.count_d1_reg[10] ;
input [5:0]v1_reg;
input srst;
input clk;
input rd_en;
input wr_en;
input ram_full_fb_i_reg;
wire [11:0]D;
wire [11:0]Q;
wire clk;
wire empty;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire \grss.rsts_n_2 ;
wire out;
wire ram_full_fb_i_reg;
wire rd_en;
wire srst;
wire tmp_ram_rd_en;
wire [5:0]v1_reg;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss \grss.rsts
(.E(\grss.rsts_n_2 ),
.clk(clk),
.empty(empty),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.srst(srst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.v1_reg(v1_reg),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr rpntr
(.D(D),
.E(\grss.rsts_n_2 ),
.Q(Q),
.clk(clk),
.srst(srst));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
(out,
empty,
E,
tmp_ram_rd_en,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[10] ,
v1_reg,
srst,
clk,
rd_en,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output [0:0]E;
output tmp_ram_rd_en;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gcc0.gc0.count_d1_reg[10] ;
input [5:0]v1_reg;
input srst;
input clk;
input rd_en;
input wr_en;
input ram_full_fb_i_reg;
wire [0:0]E;
wire c1_n_0;
wire clk;
wire comp1;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire ram_full_fb_i_reg;
wire rd_en;
wire srst;
wire tmp_ram_rd_en;
wire [5:0]v1_reg;
wire wr_en;
assign empty = ram_empty_i;
assign out = ram_empty_fb_i;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(srst),
.I1(ram_empty_fb_i),
.I2(rd_en),
.O(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_1 c1
(.comp1(comp1),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.out(ram_empty_fb_i),
.ram_empty_i_reg(c1_n_0),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_2 c2
(.comp1(comp1),
.v1_reg(v1_reg));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[11]_i_1
(.I0(rd_en),
.I1(ram_empty_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDSE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.Q(ram_empty_fb_i),
.S(srst));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDSE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.Q(ram_empty_i),
.S(srst));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
(v1_reg_0,
Q,
v1_reg,
v1_reg_1,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
ram_empty_i_reg_4,
srst,
ram_full_fb_i_reg,
clk,
\gc0.count_d1_reg[11] ,
D);
output [5:0]v1_reg_0;
output [11:0]Q;
output [5:0]v1_reg;
output [5:0]v1_reg_1;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
output ram_empty_i_reg_4;
input srst;
input ram_full_fb_i_reg;
input clk;
input [11:0]\gc0.count_d1_reg[11] ;
input [11:0]D;
wire [11:0]D;
wire [11:0]Q;
wire clk;
wire [11:0]\gc0.count_d1_reg[11] ;
wire \gcc0.gc0.count[0]_i_2_n_0 ;
wire \gcc0.gc0.count[0]_i_3_n_0 ;
wire \gcc0.gc0.count[0]_i_4_n_0 ;
wire \gcc0.gc0.count[0]_i_5_n_0 ;
wire \gcc0.gc0.count[4]_i_2_n_0 ;
wire \gcc0.gc0.count[4]_i_3_n_0 ;
wire \gcc0.gc0.count[4]_i_4_n_0 ;
wire \gcc0.gc0.count[4]_i_5_n_0 ;
wire \gcc0.gc0.count[8]_i_2_n_0 ;
wire \gcc0.gc0.count[8]_i_3_n_0 ;
wire \gcc0.gc0.count[8]_i_4_n_0 ;
wire \gcc0.gc0.count[8]_i_5_n_0 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_0 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_1 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_2 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_3 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_4 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_5 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_6 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_7 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_0 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_1 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_2 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_3 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_4 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_5 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_6 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_7 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_1 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_2 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_3 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_4 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_5 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_6 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_7 ;
wire [11:0]p_12_out;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire ram_empty_i_reg_4;
wire ram_full_fb_i_reg;
wire srst;
wire [5:0]v1_reg;
wire [5:0]v1_reg_0;
wire [5:0]v1_reg_1;
wire [3:3]\NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[0]_i_2
(.I0(p_12_out[3]),
.O(\gcc0.gc0.count[0]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[0]_i_3
(.I0(p_12_out[2]),
.O(\gcc0.gc0.count[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[0]_i_4
(.I0(p_12_out[1]),
.O(\gcc0.gc0.count[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\gcc0.gc0.count[0]_i_5
(.I0(p_12_out[0]),
.O(\gcc0.gc0.count[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[4]_i_2
(.I0(p_12_out[7]),
.O(\gcc0.gc0.count[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[4]_i_3
(.I0(p_12_out[6]),
.O(\gcc0.gc0.count[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[4]_i_4
(.I0(p_12_out[5]),
.O(\gcc0.gc0.count[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[4]_i_5
(.I0(p_12_out[4]),
.O(\gcc0.gc0.count[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[8]_i_2
(.I0(p_12_out[11]),
.O(\gcc0.gc0.count[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[8]_i_3
(.I0(p_12_out[10]),
.O(\gcc0.gc0.count[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[8]_i_4
(.I0(p_12_out[9]),
.O(\gcc0.gc0.count[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[8]_i_5
(.I0(p_12_out[8]),
.O(\gcc0.gc0.count[8]_i_5_n_0 ));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[0]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(p_12_out[0]),
.Q(Q[0]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[10]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(p_12_out[10]),
.Q(Q[10]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[11]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(p_12_out[11]),
.Q(Q[11]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[1]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(p_12_out[1]),
.Q(Q[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[2]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(p_12_out[2]),
.Q(Q[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[3]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(p_12_out[3]),
.Q(Q[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[4]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(p_12_out[4]),
.Q(Q[4]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[5]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(p_12_out[5]),
.Q(Q[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[6]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(p_12_out[6]),
.Q(Q[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[7]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(p_12_out[7]),
.Q(Q[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[8]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(p_12_out[8]),
.Q(Q[8]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[9]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(p_12_out[9]),
.Q(Q[9]),
.R(srst));
FDSE #(
.INIT(1'b1))
\gcc0.gc0.count_reg[0]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[0]_i_1_n_7 ),
.Q(p_12_out[0]),
.S(srst));
CARRY4 \gcc0.gc0.count_reg[0]_i_1
(.CI(1'b0),
.CO({\gcc0.gc0.count_reg[0]_i_1_n_0 ,\gcc0.gc0.count_reg[0]_i_1_n_1 ,\gcc0.gc0.count_reg[0]_i_1_n_2 ,\gcc0.gc0.count_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\gcc0.gc0.count_reg[0]_i_1_n_4 ,\gcc0.gc0.count_reg[0]_i_1_n_5 ,\gcc0.gc0.count_reg[0]_i_1_n_6 ,\gcc0.gc0.count_reg[0]_i_1_n_7 }),
.S({\gcc0.gc0.count[0]_i_2_n_0 ,\gcc0.gc0.count[0]_i_3_n_0 ,\gcc0.gc0.count[0]_i_4_n_0 ,\gcc0.gc0.count[0]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[10]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[8]_i_1_n_5 ),
.Q(p_12_out[10]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[11]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[8]_i_1_n_4 ),
.Q(p_12_out[11]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[1]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[0]_i_1_n_6 ),
.Q(p_12_out[1]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[2]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[0]_i_1_n_5 ),
.Q(p_12_out[2]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[3]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[0]_i_1_n_4 ),
.Q(p_12_out[3]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[4]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[4]_i_1_n_7 ),
.Q(p_12_out[4]),
.R(srst));
CARRY4 \gcc0.gc0.count_reg[4]_i_1
(.CI(\gcc0.gc0.count_reg[0]_i_1_n_0 ),
.CO({\gcc0.gc0.count_reg[4]_i_1_n_0 ,\gcc0.gc0.count_reg[4]_i_1_n_1 ,\gcc0.gc0.count_reg[4]_i_1_n_2 ,\gcc0.gc0.count_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\gcc0.gc0.count_reg[4]_i_1_n_4 ,\gcc0.gc0.count_reg[4]_i_1_n_5 ,\gcc0.gc0.count_reg[4]_i_1_n_6 ,\gcc0.gc0.count_reg[4]_i_1_n_7 }),
.S({\gcc0.gc0.count[4]_i_2_n_0 ,\gcc0.gc0.count[4]_i_3_n_0 ,\gcc0.gc0.count[4]_i_4_n_0 ,\gcc0.gc0.count[4]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[5]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[4]_i_1_n_6 ),
.Q(p_12_out[5]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[6]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[4]_i_1_n_5 ),
.Q(p_12_out[6]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[7]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[4]_i_1_n_4 ),
.Q(p_12_out[7]),
.R(srst));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[8]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[8]_i_1_n_7 ),
.Q(p_12_out[8]),
.R(srst));
CARRY4 \gcc0.gc0.count_reg[8]_i_1
(.CI(\gcc0.gc0.count_reg[4]_i_1_n_0 ),
.CO({\NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED [3],\gcc0.gc0.count_reg[8]_i_1_n_1 ,\gcc0.gc0.count_reg[8]_i_1_n_2 ,\gcc0.gc0.count_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\gcc0.gc0.count_reg[8]_i_1_n_4 ,\gcc0.gc0.count_reg[8]_i_1_n_5 ,\gcc0.gc0.count_reg[8]_i_1_n_6 ,\gcc0.gc0.count_reg[8]_i_1_n_7 }),
.S({\gcc0.gc0.count[8]_i_2_n_0 ,\gcc0.gc0.count[8]_i_3_n_0 ,\gcc0.gc0.count[8]_i_4_n_0 ,\gcc0.gc0.count[8]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[9]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[8]_i_1_n_6 ),
.Q(p_12_out[9]),
.R(srst));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(Q[0]),
.I1(\gc0.count_d1_reg[11] [0]),
.I2(Q[1]),
.I3(\gc0.count_d1_reg[11] [1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(Q[0]),
.I1(D[0]),
.I2(Q[1]),
.I3(D[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(p_12_out[0]),
.I1(\gc0.count_d1_reg[11] [0]),
.I2(p_12_out[1]),
.I3(\gc0.count_d1_reg[11] [1]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(Q[0]),
.I1(\gc0.count_d1_reg[11] [0]),
.I2(Q[1]),
.I3(\gc0.count_d1_reg[11] [1]),
.O(ram_empty_i_reg));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(Q[2]),
.I1(\gc0.count_d1_reg[11] [2]),
.I2(Q[3]),
.I3(\gc0.count_d1_reg[11] [3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(Q[2]),
.I1(D[2]),
.I2(Q[3]),
.I3(D[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(p_12_out[2]),
.I1(\gc0.count_d1_reg[11] [2]),
.I2(p_12_out[3]),
.I3(\gc0.count_d1_reg[11] [3]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(Q[2]),
.I1(\gc0.count_d1_reg[11] [2]),
.I2(Q[3]),
.I3(\gc0.count_d1_reg[11] [3]),
.O(ram_empty_i_reg_0));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(Q[4]),
.I1(\gc0.count_d1_reg[11] [4]),
.I2(Q[5]),
.I3(\gc0.count_d1_reg[11] [5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(Q[4]),
.I1(D[4]),
.I2(Q[5]),
.I3(D[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(p_12_out[4]),
.I1(\gc0.count_d1_reg[11] [4]),
.I2(p_12_out[5]),
.I3(\gc0.count_d1_reg[11] [5]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(Q[4]),
.I1(\gc0.count_d1_reg[11] [4]),
.I2(Q[5]),
.I3(\gc0.count_d1_reg[11] [5]),
.O(ram_empty_i_reg_1));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(Q[6]),
.I1(\gc0.count_d1_reg[11] [6]),
.I2(Q[7]),
.I3(\gc0.count_d1_reg[11] [7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(Q[6]),
.I1(D[6]),
.I2(Q[7]),
.I3(D[7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(p_12_out[6]),
.I1(\gc0.count_d1_reg[11] [6]),
.I2(p_12_out[7]),
.I3(\gc0.count_d1_reg[11] [7]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(Q[6]),
.I1(\gc0.count_d1_reg[11] [6]),
.I2(Q[7]),
.I3(\gc0.count_d1_reg[11] [7]),
.O(ram_empty_i_reg_2));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(Q[8]),
.I1(\gc0.count_d1_reg[11] [8]),
.I2(Q[9]),
.I3(\gc0.count_d1_reg[11] [9]),
.O(v1_reg_0[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(Q[8]),
.I1(D[8]),
.I2(Q[9]),
.I3(D[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_12_out[8]),
.I1(\gc0.count_d1_reg[11] [8]),
.I2(p_12_out[9]),
.I3(\gc0.count_d1_reg[11] [9]),
.O(v1_reg_1[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(Q[8]),
.I1(\gc0.count_d1_reg[11] [8]),
.I2(Q[9]),
.I3(\gc0.count_d1_reg[11] [9]),
.O(ram_empty_i_reg_3));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(Q[10]),
.I1(\gc0.count_d1_reg[11] [10]),
.I2(Q[11]),
.I3(\gc0.count_d1_reg[11] [11]),
.O(v1_reg_0[5]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1__0
(.I0(Q[10]),
.I1(D[10]),
.I2(Q[11]),
.I3(D[11]),
.O(v1_reg[5]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1__1
(.I0(p_12_out[10]),
.I1(\gc0.count_d1_reg[11] [10]),
.I2(p_12_out[11]),
.I3(\gc0.count_d1_reg[11] [11]),
.O(v1_reg_1[5]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1__2
(.I0(Q[10]),
.I1(\gc0.count_d1_reg[11] [10]),
.I2(Q[11]),
.I3(\gc0.count_d1_reg[11] [11]),
.O(ram_empty_i_reg_4));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
(out,
full,
\gcc0.gc0.count_d1_reg[11] ,
Q,
v1_reg,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
ram_empty_i_reg_4,
srst,
clk,
wr_en,
rd_en,
ram_empty_fb_i_reg,
\gc0.count_d1_reg[11] ,
D);
output out;
output full;
output \gcc0.gc0.count_d1_reg[11] ;
output [11:0]Q;
output [5:0]v1_reg;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
output ram_empty_i_reg_4;
input srst;
input clk;
input wr_en;
input rd_en;
input ram_empty_fb_i_reg;
input [11:0]\gc0.count_d1_reg[11] ;
input [11:0]D;
wire [11:0]D;
wire [11:0]Q;
wire [5:0]\c0/v1_reg ;
wire [5:0]\c1/v1_reg ;
wire clk;
wire full;
wire [11:0]\gc0.count_d1_reg[11] ;
wire \gcc0.gc0.count_d1_reg[11] ;
wire out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire ram_empty_i_reg_4;
wire rd_en;
wire srst;
wire [5:0]v1_reg;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss \gwss.wsts
(.clk(clk),
.full(full),
.\gcc0.gc0.count_d1_reg[11] (\gcc0.gc0.count_d1_reg[11] ),
.out(out),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg),
.rd_en(rd_en),
.srst(srst),
.v1_reg(\c0/v1_reg ),
.v1_reg_0(\c1/v1_reg ),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr wpntr
(.D(D),
.Q(Q),
.clk(clk),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.ram_empty_i_reg(ram_empty_i_reg),
.ram_empty_i_reg_0(ram_empty_i_reg_0),
.ram_empty_i_reg_1(ram_empty_i_reg_1),
.ram_empty_i_reg_2(ram_empty_i_reg_2),
.ram_empty_i_reg_3(ram_empty_i_reg_3),
.ram_empty_i_reg_4(ram_empty_i_reg_4),
.ram_full_fb_i_reg(\gcc0.gc0.count_d1_reg[11] ),
.srst(srst),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ),
.v1_reg_1(\c1/v1_reg ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
(out,
full,
\gcc0.gc0.count_d1_reg[11] ,
v1_reg,
v1_reg_0,
srst,
clk,
wr_en,
rd_en,
ram_empty_fb_i_reg);
output out;
output full;
output \gcc0.gc0.count_d1_reg[11] ;
input [5:0]v1_reg;
input [5:0]v1_reg_0;
input srst;
input clk;
input wr_en;
input rd_en;
input ram_empty_fb_i_reg;
wire c0_n_0;
wire clk;
wire comp1;
wire \gcc0.gc0.count_d1_reg[11] ;
(* DONT_TOUCH *) wire ram_afull_fb;
(* DONT_TOUCH *) wire ram_afull_i;
wire ram_empty_fb_i_reg;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire rd_en;
wire srst;
wire [5:0]v1_reg;
wire [5:0]v1_reg_0;
wire wr_en;
assign full = ram_full_i;
assign out = ram_full_fb_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(\gcc0.gc0.count_d1_reg[11] ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare c0
(.comp1(comp1),
.out(ram_full_fb_i),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg),
.ram_full_fb_i_reg(c0_n_0),
.rd_en(rd_en),
.v1_reg(v1_reg),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_0 c1
(.comp1(comp1),
.v1_reg_0(v1_reg_0));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(ram_afull_i));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(ram_afull_fb));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
ram_full_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(c0_n_0),
.Q(ram_full_fb_i),
.R(srst));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
ram_full_i_reg
(.C(clk),
.CE(1'b1),
.D(c0_n_0),
.Q(ram_full_i),
.R(srst));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : db_sao_cal_offset.v
// Author : Chewein
// Created : 2015-03-19
// Description : calculation the offset dependent on the band
// number and state
//-------------------------------------------------------------------
module db_sao_cal_offset(
b_state_i ,
b_num_i ,
data_valid_i ,
b_offset_o ,
b_distortion_o
);
//---------------------------------------------------------------------------
//
// INPUT/OUTPUT DECLARATION
//
//----------------------------------------------------------------------------
parameter DATA_WIDTH = 128 ;
parameter PIXEL_WIDTH = 8 ;
parameter DIFF_WIDTH = 20 ;
parameter DIS_WIDTH = 25 ;
input signed [DIFF_WIDTH-1:0] b_state_i ;
input [ 12 :0] b_num_i ;
input data_valid_i ;
output signed [ 2 :0] b_offset_o ;
output signed [ DIS_WIDTH-1:0] b_distortion_o ;
reg signed [DIFF_WIDTH-1:0] b_state_r ;
reg [ 12 :0] b_num_r ;
reg [DIFF_WIDTH-1:0] b_state_unsigned_r ;
wire [ 14 :0] b_num_m2_w ;
wire [ 14 :0] b_num_m3_w ;
reg [ 1 :0] b_offset_unsigned_r;
reg signed [ 2 :0] b_offset_r ;
always @* begin
case(data_valid_i)
1'b0 :begin b_state_r = 'd0 ; b_num_r = 13'd0 ;end
1'b1 :begin b_state_r = b_state_i; b_num_r = b_num_i;end
endcase
end
always @* begin
case(b_state_r[DIFF_WIDTH-1])
1'b0 : b_state_unsigned_r = {1'b0,b_state_r} ;
1'b1 : b_state_unsigned_r = (~b_state_r)+1'b1 ;
endcase
end
assign b_num_m2_w = {b_num_r,1'b0} ;
assign b_num_m3_w = {b_num_r,1'b0} + b_num_r ;
always @* begin
if(!b_num_r)
b_offset_unsigned_r = 2'd0 ;
else if(b_state_unsigned_r<b_num_r)
b_offset_unsigned_r = 2'd0 ;
else if(b_state_unsigned_r<b_num_m2_w)
b_offset_unsigned_r = 2'd1 ;
else if(b_state_unsigned_r<b_num_m3_w)
b_offset_unsigned_r = 2'd2 ;
else
b_offset_unsigned_r = 2'd3 ;
end
always @* begin
case(b_state_r[DIFF_WIDTH-1])
1'b0 : b_offset_r = {1'b0,b_offset_unsigned_r} ;
1'b1 : b_offset_r = ~(b_offset_unsigned_r)+1'b1 ;
endcase
end
wire signed [ 5:0] temp1= b_offset_r * b_offset_r;
wire signed [18:0] temp2= b_num_r * temp1 ;
wire signed [DIS_WIDTH-1:0] temp3= b_state_r*b_offset_r ;
assign b_offset_o = b_offset_r ;
assign b_distortion_o = temp2 - {temp3,1'b0} ;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:10:16 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_selector_A, FSM_selector_C, exp_oper_result_8_,
Exp_module_Overflow_flag_A, Sgf_operation_EVEN1_left_N9,
Sgf_operation_EVEN1_left_N8, Sgf_operation_EVEN1_left_N7,
Sgf_operation_EVEN1_left_N6, Sgf_operation_EVEN1_left_N5,
Sgf_operation_EVEN1_left_N4, Sgf_operation_EVEN1_left_N3,
Sgf_operation_EVEN1_left_N2, Sgf_operation_EVEN1_left_N1,
Sgf_operation_EVEN1_left_N0, Sgf_operation_EVEN1_middle_N9,
Sgf_operation_EVEN1_middle_N8, Sgf_operation_EVEN1_middle_N7,
Sgf_operation_EVEN1_middle_N6, Sgf_operation_EVEN1_middle_N5,
Sgf_operation_EVEN1_middle_N4, Sgf_operation_EVEN1_middle_N3,
Sgf_operation_EVEN1_middle_N2, Sgf_operation_EVEN1_middle_N1,
Sgf_operation_EVEN1_middle_N0, Sgf_operation_EVEN1_right_N10,
Sgf_operation_EVEN1_right_N9, Sgf_operation_EVEN1_right_N8,
Sgf_operation_EVEN1_right_N7, Sgf_operation_EVEN1_right_N6,
Sgf_operation_EVEN1_right_N5, Sgf_operation_EVEN1_right_N4,
Sgf_operation_EVEN1_right_N3, Sgf_operation_EVEN1_right_N2,
Sgf_operation_EVEN1_right_N1, Sgf_operation_EVEN1_right_N0, n167,
n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179,
n180, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190,
n191, n192, n193, n194, n195, n196, n197, n198, n199, n200, n201,
n202, n203, n204, n205, n206, n207, n208, n209, n210, n211, n212,
n213, n214, n215, n216, n217, n218, n219, n220, n221, n222, n223,
n224, n225, n226, n227, n228, n229, n230, n231, n232, n233, n234,
n235, n236, n237, n238, n239, n240, n241, n242, n243, n244, n245,
n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256,
n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267,
n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278,
n279, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290,
n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301,
n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312,
n313, n314, n315, n316, n319, n320, n321, n322, n323, n324, n326,
n327, n328, n331, n333, n335, n336, n337, n338, n339, n340, n341,
n342, n343, n346, n348, n350, n354, n356, n358, n366, n367, n368,
n369, n370, n371, n372, n373, n374, n375, n376, n377, n378, n379,
n380, DP_OP_111J16_123_4462_n891, DP_OP_111J16_123_4462_n880,
DP_OP_111J16_123_4462_n831, DP_OP_111J16_123_4462_n827,
DP_OP_111J16_123_4462_n821, DP_OP_111J16_123_4462_n820,
DP_OP_111J16_123_4462_n792, DP_OP_111J16_123_4462_n785,
DP_OP_111J16_123_4462_n783, DP_OP_111J16_123_4462_n774,
DP_OP_111J16_123_4462_n773, DP_OP_111J16_123_4462_n767,
DP_OP_111J16_123_4462_n766, DP_OP_111J16_123_4462_n758,
DP_OP_111J16_123_4462_n757, DP_OP_111J16_123_4462_n754,
DP_OP_111J16_123_4462_n753, DP_OP_111J16_123_4462_n752,
DP_OP_111J16_123_4462_n751, DP_OP_111J16_123_4462_n749,
DP_OP_111J16_123_4462_n744, DP_OP_111J16_123_4462_n728,
DP_OP_111J16_123_4462_n720, DP_OP_111J16_123_4462_n713,
DP_OP_111J16_123_4462_n707, DP_OP_111J16_123_4462_n699,
DP_OP_111J16_123_4462_n698, DP_OP_111J16_123_4462_n697,
DP_OP_111J16_123_4462_n695, DP_OP_111J16_123_4462_n694,
DP_OP_111J16_123_4462_n685, DP_OP_111J16_123_4462_n684,
DP_OP_111J16_123_4462_n683, DP_OP_111J16_123_4462_n682,
DP_OP_111J16_123_4462_n680, DP_OP_111J16_123_4462_n625,
DP_OP_111J16_123_4462_n620, DP_OP_111J16_123_4462_n619,
DP_OP_111J16_123_4462_n617, DP_OP_111J16_123_4462_n616,
DP_OP_111J16_123_4462_n607, DP_OP_111J16_123_4462_n606,
DP_OP_111J16_123_4462_n605, DP_OP_111J16_123_4462_n224,
DP_OP_111J16_123_4462_n220, DP_OP_111J16_123_4462_n219,
DP_OP_111J16_123_4462_n168, DP_OP_111J16_123_4462_n161,
DP_OP_111J16_123_4462_n160, DP_OP_111J16_123_4462_n159,
DP_OP_111J16_123_4462_n158, DP_OP_111J16_123_4462_n150,
DP_OP_111J16_123_4462_n149, DP_OP_111J16_123_4462_n140,
DP_OP_111J16_123_4462_n130, DP_OP_111J16_123_4462_n128,
DP_OP_111J16_123_4462_n123, DP_OP_111J16_123_4462_n117,
DP_OP_111J16_123_4462_n116, DP_OP_111J16_123_4462_n106,
DP_OP_111J16_123_4462_n103, DP_OP_111J16_123_4462_n97,
DP_OP_111J16_123_4462_n96, DP_OP_111J16_123_4462_n94,
DP_OP_111J16_123_4462_n89, DP_OP_111J16_123_4462_n83,
DP_OP_111J16_123_4462_n82, DP_OP_111J16_123_4462_n72,
DP_OP_111J16_123_4462_n71, DP_OP_111J16_123_4462_n59,
DP_OP_111J16_123_4462_n58, DP_OP_111J16_123_4462_n48,
DP_OP_111J16_123_4462_n46, DP_OP_111J16_123_4462_n45,
DP_OP_111J16_123_4462_n39, DP_OP_111J16_123_4462_n36,
DP_OP_111J16_123_4462_n21, DP_OP_111J16_123_4462_n20,
DP_OP_111J16_123_4462_n19, DP_OP_111J16_123_4462_n18,
DP_OP_111J16_123_4462_n17, DP_OP_111J16_123_4462_n16,
DP_OP_111J16_123_4462_n15, DP_OP_111J16_123_4462_n14,
DP_OP_111J16_123_4462_n12, DP_OP_111J16_123_4462_n11,
DP_OP_111J16_123_4462_n10, DP_OP_111J16_123_4462_n9,
DP_OP_111J16_123_4462_n8, DP_OP_111J16_123_4462_n7,
DP_OP_111J16_123_4462_n6, add_x_19_n308, add_x_19_n272, add_x_19_n271,
add_x_19_n243, add_x_19_n232, add_x_19_n221, add_x_19_n216,
add_x_19_n215, add_x_19_n213, add_x_19_n205, add_x_19_n204,
add_x_19_n202, add_x_19_n201, add_x_19_n197, add_x_19_n194,
add_x_19_n186, add_x_19_n185, add_x_19_n179, add_x_19_n178,
add_x_19_n176, add_x_19_n168, add_x_19_n161, add_x_19_n160,
add_x_19_n152, add_x_19_n142, add_x_19_n141, add_x_19_n132,
add_x_19_n130, add_x_19_n125, add_x_19_n124, add_x_19_n122,
add_x_19_n104, add_x_19_n94, add_x_19_n85, add_x_19_n67, add_x_19_n57,
add_x_19_n51, add_x_19_n47, add_x_19_n39, add_x_19_n24, add_x_19_n19,
add_x_19_n18, add_x_19_n17, add_x_19_n16, add_x_19_n15, add_x_19_n14,
add_x_19_n13, add_x_19_n12, add_x_19_n11, add_x_19_n10, add_x_19_n9,
add_x_19_n8, add_x_19_n7, mult_x_23_a_0_, mult_x_23_n554,
mult_x_23_n553, mult_x_23_n552, mult_x_23_n551, mult_x_23_n550,
mult_x_23_n549, mult_x_23_n546, mult_x_23_n545, mult_x_23_n541,
mult_x_23_n540, mult_x_23_n533, mult_x_23_n530, mult_x_23_n525,
mult_x_23_n524, mult_x_23_n523, mult_x_23_n521, mult_x_23_n520,
mult_x_23_n518, mult_x_23_n517, mult_x_23_n516, mult_x_23_n492,
mult_x_23_n480, mult_x_23_n472, mult_x_23_n470, mult_x_23_n461,
mult_x_23_n459, mult_x_23_n194, mult_x_23_n190, mult_x_23_n141,
mult_x_23_n140, mult_x_23_n127, mult_x_23_n121, mult_x_23_n120,
mult_x_23_n114, mult_x_23_n113, mult_x_23_n109, mult_x_23_n101,
mult_x_23_n100, mult_x_23_n99, mult_x_23_n97, mult_x_23_n94,
mult_x_23_n88, mult_x_23_n87, mult_x_23_n81, mult_x_23_n78,
mult_x_23_n71, mult_x_23_n65, mult_x_23_n50, mult_x_23_n49,
mult_x_23_n47, mult_x_23_n39, mult_x_23_n38, mult_x_23_n36,
mult_x_23_n21, mult_x_23_n20, mult_x_23_n19, mult_x_23_n18,
mult_x_23_n17, mult_x_23_n16, mult_x_23_n15, mult_x_23_n14,
mult_x_23_n13, mult_x_23_n12, mult_x_23_n11, mult_x_23_n10,
mult_x_23_n9, mult_x_23_n8, mult_x_23_n7, mult_x_23_n6,
mult_x_55_a_8_, mult_x_55_a_0_, mult_x_55_n583, mult_x_55_n570,
mult_x_55_n569, mult_x_55_n568, mult_x_55_n567, mult_x_55_n566,
mult_x_55_n565, mult_x_55_n562, mult_x_55_n559, mult_x_55_n557,
mult_x_55_n556, mult_x_55_n555, mult_x_55_n554, mult_x_55_n544,
mult_x_55_n543, mult_x_55_n538, mult_x_55_n537, mult_x_55_n536,
mult_x_55_n535, mult_x_55_n533, mult_x_55_n532, mult_x_55_n531,
mult_x_55_n530, mult_x_55_n529, mult_x_55_n506, mult_x_55_n505,
mult_x_55_n504, mult_x_55_n494, mult_x_55_n490, mult_x_55_n480,
mult_x_55_n479, mult_x_55_n449, mult_x_55_n448, mult_x_55_n446,
mult_x_55_n445, mult_x_55_n444, mult_x_55_n270, mult_x_55_n188,
mult_x_55_n130, mult_x_55_n121, mult_x_55_n116, mult_x_55_n115,
mult_x_55_n95, mult_x_55_n94, mult_x_55_n88, mult_x_55_n87,
mult_x_55_n78, mult_x_55_n72, mult_x_55_n71, mult_x_55_n69,
mult_x_55_n59, mult_x_55_n58, mult_x_55_n56, mult_x_55_n48,
mult_x_55_n47, mult_x_55_n45, mult_x_55_n32, mult_x_55_n18,
mult_x_55_n17, mult_x_55_n16, mult_x_55_n15, mult_x_55_n14,
mult_x_55_n13, mult_x_55_n12, mult_x_55_n11, mult_x_55_n10,
mult_x_55_n9, mult_x_55_n8, mult_x_55_n7, mult_x_55_n6, mult_x_55_n4,
mult_x_55_n3, DP_OP_111J16_123_4462_n778, add_x_19_n310, n390, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n419, n420, n421, n424, n425, n426, n427, n428, n429, n430, n431,
n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442,
n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453,
n454, n455, n456, n457, n458, n459, n460, n461, n462, n463, n464,
n465, n466, n467, n468, n469, n470, n471, n472, n473, n474, n475,
n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, n486,
n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, n497,
n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508,
n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542,
n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553,
n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564,
n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n576,
n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587,
n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598,
n599, n600, n601, n602, n603, n604, n605, n606, n607, n608, n609,
n610, n611, n612, n613, n614, n615, n616, n617, n618, n619, n620,
n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631,
n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642,
n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653,
n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664,
n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675,
n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686,
n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697,
n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708,
n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, n719,
n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730,
n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741,
n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752,
n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763,
n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774,
n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, n785,
n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796,
n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807,
n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818,
n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829,
n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840,
n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851,
n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862,
n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873,
n874, n875, n876, n877, n878, n879, n880, n881, n882, n883, n884,
n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895,
n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, n906,
n907, n908, n909, n910, n911, n912, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025,
n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035,
n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045,
n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055,
n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298,
n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308,
n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318,
n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328,
n1329, n1330, n1331, n1332, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480,
n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701,
n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711,
n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721,
n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761,
n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771,
n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781,
n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791,
n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801,
n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811,
n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821,
n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831,
n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841,
n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851,
n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861,
n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871,
n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881,
n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891,
n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901,
n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911,
n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921,
n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931,
n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941,
n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951,
n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961,
n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971,
n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981,
n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991,
n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001,
n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011,
n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021,
n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031,
n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041,
n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051,
n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061,
n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071,
n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081,
n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091,
n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101,
n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111,
n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121,
n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131,
n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141,
n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151,
n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161,
n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171,
n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181,
n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191,
n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201,
n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211,
n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221,
n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231,
n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241,
n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251,
n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261,
n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271,
n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281,
n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331,
n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341,
n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351,
n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361,
n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371,
n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381,
n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391,
n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401,
n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411,
n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421,
n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511,
n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521,
n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531,
n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541,
n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551,
n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561,
n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571,
n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581,
n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591,
n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601,
n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611,
n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621,
n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631,
n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641,
n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651,
n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661,
n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671,
n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681,
n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691,
n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701,
n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711,
n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721,
n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731,
n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741,
n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751,
n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761,
n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771,
n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781,
n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791,
n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801,
n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811,
n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821,
n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831,
n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841,
n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851,
n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861,
n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871,
n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881,
n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921,
n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931,
n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941,
n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951,
n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961,
n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971,
n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981,
n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991,
n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001,
n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011,
n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021,
n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031,
n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041,
n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051,
n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061,
n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071,
n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081,
n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091,
n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101,
n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111,
n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121,
n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131,
n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141,
n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151,
n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161,
n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171,
n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181,
n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191,
n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201,
n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211,
n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221,
n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231,
n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241,
n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251,
n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261,
n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271,
n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281,
n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291,
n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301,
n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311,
n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321,
n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331,
n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341,
n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351,
n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361,
n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371,
n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381,
n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391,
n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401,
n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411,
n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421,
n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431,
n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441,
n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451,
n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461,
n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471,
n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481,
n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491,
n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501,
n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511,
n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521,
n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531,
n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541,
n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551,
n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561,
n3562, n3563, n3565, n3566, n3567, n3568, n3569, n3570, n3572, n3573,
n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583,
n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593,
n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603,
n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613,
n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623,
n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633,
n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643,
n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653,
n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663,
n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673,
n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683,
n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693,
n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703,
n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713,
n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723,
n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733,
n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743,
n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753,
n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763,
n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773,
n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783,
n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793,
n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803,
n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813,
n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823,
n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833,
n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843,
n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853,
n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863,
n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873,
n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883,
n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893,
n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903,
n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913,
n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923,
n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933,
n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943,
n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953,
n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963,
n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973,
n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983,
n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993,
n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003,
n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013,
n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023,
n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033,
n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043,
n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053,
n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063,
n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4072, n4073;
wire [19:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [23:1] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [24:0] Sgf_operation_Result;
wire [9:0] Sgf_operation_EVEN1_Q_middle;
wire [9:0] Sgf_operation_EVEN1_Q_left;
DFFHQX8TS Sgf_operation_EVEN1_left_DatO_reg_1_ ( .D(
Sgf_operation_EVEN1_left_N1), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[1]) );
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_4_ ( .D(
Sgf_operation_EVEN1_right_N4), .CK(clk), .Q(Sgf_operation_Result[4])
);
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_5_ ( .D(
Sgf_operation_EVEN1_right_N5), .CK(clk), .Q(Sgf_operation_Result[5])
);
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_7_ ( .D(
Sgf_operation_EVEN1_right_N7), .CK(clk), .Q(Sgf_operation_Result[7])
);
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_8_ ( .D(
Sgf_operation_EVEN1_right_N8), .CK(clk), .Q(Sgf_operation_Result[8])
);
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_9_ ( .D(
Sgf_operation_EVEN1_right_N9), .CK(clk), .Q(Sgf_operation_Result[9])
);
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_10_ ( .D(
Sgf_operation_EVEN1_right_N10), .CK(clk), .Q(Sgf_operation_Result[10])
);
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n310), .CK(clk), .RN(
n4060), .Q(Op_MY[31]) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n377), .CK(clk), .RN(n3973), .Q(
FS_Module_state_reg[1]), .QN(n3930) );
DFFRX4TS FS_Module_state_reg_reg_2_ ( .D(n376), .CK(clk), .RN(n3973), .Q(
FS_Module_state_reg[2]), .QN(n3906) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(n379), .CK(clk), .RN(n3973), .Q(
FS_Module_state_reg[3]), .QN(n3928) );
DFFRX4TS FS_Module_state_reg_reg_0_ ( .D(n378), .CK(clk), .RN(n3973), .Q(
FS_Module_state_reg[0]) );
DFFRX4TS Sel_A_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n4063), .Q(FSM_selector_A),
.QN(n3900) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n3648), .Q(Op_MX[26]), .QN(n3905) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n3972), .Q(Op_MX[25]), .QN(n3908) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n873), .Q(Op_MX[24]), .QN(n3981) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n299), .CK(clk), .RN(n4060),
.Q(Add_result[7]), .QN(n3955) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n300), .CK(clk), .RN(n4060),
.Q(Add_result[6]), .QN(n3956) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n301), .CK(clk), .RN(n4060),
.Q(Add_result[5]), .QN(n3954) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n303), .CK(clk), .RN(n4060),
.Q(Add_result[3]), .QN(n3957) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n304), .CK(clk), .RN(n4060),
.Q(Add_result[2]), .QN(n3958) );
DFFRX4TS R_31 ( .D(n324), .CK(clk), .RN(n412), .Q(Op_MY[12]), .QN(n867) );
DFFRX4TS R_1194 ( .D(n323), .CK(clk), .RN(n414), .Q(Op_MY[11]), .QN(n1451)
);
DFFRX2TS R_1075 ( .D(n319), .CK(clk), .RN(n413), .Q(Op_MY[7]) );
DFFRX4TS R_32 ( .D(n312), .CK(clk), .RN(n4062), .Q(Op_MY[0]), .QN(n1461) );
DFFRX4TS Sel_B_Q_reg_0_ ( .D(n309), .CK(clk), .RN(n4062), .Q(
FSM_selector_B[0]), .QN(n3909) );
DFFRX4TS Sel_B_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n4062), .Q(
FSM_selector_B[1]), .QN(n707) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n279), .CK(clk), .RN(n4062),
.QN(n3896) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n274), .CK(clk), .RN(n873),
.QN(n3903) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n234), .CK(clk), .RN(
n3973), .Q(P_Sgf[19]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n233), .CK(clk), .RN(
n3977), .Q(P_Sgf[18]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n232), .CK(clk), .RN(
n4057), .Q(P_Sgf[17]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n231), .CK(clk), .RN(
n4057), .Q(P_Sgf[16]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n230), .CK(clk), .RN(
n3974), .Q(P_Sgf[15]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n229), .CK(clk), .RN(
n3976), .Q(P_Sgf[14]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n227), .CK(clk), .RN(
n3976), .Q(P_Sgf[12]), .QN(n1448) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n226), .CK(clk), .RN(
n3976), .Q(P_Sgf[11]), .QN(n1449) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n215), .CK(clk), .RN(
n4056), .Q(P_Sgf[0]), .QN(n3940) );
DFFRX2TS R_772 ( .D(n2865), .CK(clk), .RN(n872), .Q(n4049) );
DFFRX2TS R_1064 ( .D(n4039), .CK(clk), .RN(n4067), .Q(n4040) );
DFFRX4TS R_151 ( .D(n326), .CK(clk), .RN(n411), .Q(mult_x_23_n524), .QN(
n4029) );
DFFRXLTS R_1137 ( .D(n358), .CK(clk), .RN(n409), .Q(n4046) );
DFFRX4TS R_120 ( .D(n315), .CK(clk), .RN(n411), .Q(mult_x_55_n536), .QN(
n4026) );
DFFRXLTS R_1038 ( .D(n314), .CK(clk), .RN(n414), .Q(n4035) );
DFFRXLTS R_243 ( .D(n380), .CK(clk), .RN(n3973), .Q(n4022) );
DFFRXLTS R_249 ( .D(n257), .CK(clk), .RN(n3975), .Q(n4020) );
DFFRXLTS R_252 ( .D(n258), .CK(clk), .RN(n3975), .Q(n4019) );
DFFRXLTS R_255 ( .D(n259), .CK(clk), .RN(n876), .Q(n4018) );
DFFRXLTS R_258 ( .D(n261), .CK(clk), .RN(n4072), .Q(n4017) );
DFFRXLTS R_261 ( .D(n252), .CK(clk), .RN(n876), .Q(n4016) );
DFFRXLTS R_264 ( .D(n253), .CK(clk), .RN(n876), .Q(n4015) );
DFFRXLTS R_267 ( .D(n254), .CK(clk), .RN(n3975), .Q(n4014) );
DFFRXLTS R_270 ( .D(n255), .CK(clk), .RN(n3975), .Q(n4013) );
DFFRXLTS R_273 ( .D(n256), .CK(clk), .RN(n3975), .Q(n4012) );
DFFRXLTS R_335 ( .D(n251), .CK(clk), .RN(n3975), .Q(n4011) );
DFFRX4TS R_89 ( .D(n356), .CK(clk), .RN(n908), .Q(mult_x_23_a_0_), .QN(n4008) );
DFFRXLTS R_364 ( .D(n249), .CK(clk), .RN(n4056), .Q(n4007) );
DFFRXLTS R_370 ( .D(n250), .CK(clk), .RN(n3975), .Q(n4005) );
DFFRXLTS R_665 ( .D(mult_x_55_n567), .CK(clk), .RN(n3649), .Q(n4047) );
DFFRXLTS R_858 ( .D(n333), .CK(clk), .RN(n4061), .Q(n4045) );
DFFRXLTS R_1156 ( .D(DP_OP_111J16_123_4462_n891), .CK(clk), .RN(n3979), .Q(
n4024) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n296), .CK(clk), .RN(n4059),
.Q(Add_result[10]), .QN(n3923) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n294), .CK(clk), .RN(n4059),
.Q(Add_result[12]), .QN(n3921) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n262),
.CK(clk), .RN(n4065), .Q(final_result_ieee[31]), .QN(n3971) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n189),
.CK(clk), .RN(n4058), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n188),
.CK(clk), .RN(n4073), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n187),
.CK(clk), .RN(n3734), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n186),
.CK(clk), .RN(n3878), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n185),
.CK(clk), .RN(n874), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n184),
.CK(clk), .RN(n3647), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n183),
.CK(clk), .RN(n873), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n182),
.CK(clk), .RN(n4073), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n181),
.CK(clk), .RN(n4073), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n180),
.CK(clk), .RN(n4073), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n179),
.CK(clk), .RN(n409), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n178),
.CK(clk), .RN(n908), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n177),
.CK(clk), .RN(n4066), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n176),
.CK(clk), .RN(n409), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n175),
.CK(clk), .RN(n908), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n174),
.CK(clk), .RN(n4066), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n173),
.CK(clk), .RN(n4066), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n172),
.CK(clk), .RN(n408), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n171),
.CK(clk), .RN(n908), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n170),
.CK(clk), .RN(n4066), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n167),
.CK(clk), .RN(n4067), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n270),
.CK(clk), .RN(n4065), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n269),
.CK(clk), .RN(n4065), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n268),
.CK(clk), .RN(n4065), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n267),
.CK(clk), .RN(n4065), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n266),
.CK(clk), .RN(n4065), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n265),
.CK(clk), .RN(n4065), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n264),
.CK(clk), .RN(n4065), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n263),
.CK(clk), .RN(n4065), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n190),
.CK(clk), .RN(n4065), .Q(final_result_ieee[0]) );
DFFRX1TS R_668 ( .D(mult_x_55_n565), .CK(clk), .RN(n878), .Q(Op_MX[11]),
.QN(n3960) );
DFFRX1TS R_121 ( .D(mult_x_55_n533), .CK(clk), .RN(n4062), .QN(n4038) );
DFFRX1TS R_145 ( .D(n314), .CK(clk), .RN(n3880), .QN(n4033) );
DFFRX1TS R_139 ( .D(DP_OP_111J16_123_4462_n891), .CK(clk), .RN(n3877), .QN(
n4037) );
DFFRX1TS R_750 ( .D(mult_x_23_n552), .CK(clk), .RN(n4062), .Q(Op_MX[17]),
.QN(n3993) );
DFFRX1TS R_65 ( .D(mult_x_55_n567), .CK(clk), .RN(n4073), .QN(n4031) );
DFFRXLTS R_1110 ( .D(mult_x_55_a_0_), .CK(clk), .RN(n908), .Q(Op_MX[0]),
.QN(n3951) );
DFFRXLTS R_149 ( .D(DP_OP_111J16_123_4462_n880), .CK(clk), .RN(n3979), .QN(
n4027) );
DFFRX1TS R_675 ( .D(n354), .CK(clk), .RN(n871), .Q(n4051), .QN(n4010) );
DFFRXLTS R_999 ( .D(mult_x_23_n518), .CK(clk), .RN(n412), .Q(Op_MY[20]),
.QN(n4028) );
DFFRX1TS R_682 ( .D(mult_x_23_n554), .CK(clk), .RN(n4073), .Q(Op_MX[13]),
.QN(n4043) );
DFFRX1TS R_671 ( .D(mult_x_55_n566), .CK(clk), .RN(n878), .Q(Op_MX[9]), .QN(
n4032) );
DFFRXLTS R_337 ( .D(mult_x_55_n570), .CK(clk), .RN(n4058), .Q(Op_MX[1]),
.QN(n3959) );
DFFRXLTS R_874 ( .D(n327), .CK(clk), .RN(n414), .Q(n4054), .QN(n4023) );
DFFRX1TS R_279 ( .D(mult_x_55_n568), .CK(clk), .RN(n4073), .QN(n3997) );
DFFRX1TS R_663 ( .D(mult_x_23_n550), .CK(clk), .RN(n4073), .Q(n4052), .QN(
n3996) );
DFFRX2TS R_752 ( .D(mult_x_23_n553), .CK(clk), .RN(n871), .QN(n733) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n220), .CK(clk), .RN(
n4056), .Q(P_Sgf[5]), .QN(n3967) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n216), .CK(clk), .RN(
n4056), .Q(P_Sgf[1]), .QN(n3963) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n221), .CK(clk), .RN(
n4056), .Q(P_Sgf[6]), .QN(n3968) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n217), .CK(clk), .RN(
n906), .Q(P_Sgf[2]), .QN(n3964) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n224), .CK(clk), .RN(
n3974), .Q(P_Sgf[9]), .QN(n3961) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n222), .CK(clk), .RN(
n906), .Q(P_Sgf[7]), .QN(n3969) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n218), .CK(clk), .RN(
n906), .Q(P_Sgf[3]), .QN(n3965) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n223), .CK(clk), .RN(
n4056), .Q(P_Sgf[8]), .QN(n3970) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n219), .CK(clk), .RN(
n4056), .Q(P_Sgf[4]), .QN(n3966) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n271), .CK(clk), .RN(n872), .Q(
Exp_module_Overflow_flag_A), .QN(n3962) );
DFFRX2TS R_870 ( .D(mult_x_55_a_8_), .CK(clk), .RN(n874), .Q(Op_MX[8]) );
DFFRX2TS R_679 ( .D(n348), .CK(clk), .RN(n4061), .Q(Op_MX[4]), .QN(n737) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n272), .CK(clk), .RN(n4066),
.Q(underflow_flag), .QN(n3935) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n194), .CK(clk),
.RN(n874), .Q(Sgf_normalized_result[3]), .QN(n3929) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n204), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[13]), .QN(n3944) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n198), .CK(clk),
.RN(n4067), .Q(Sgf_normalized_result[7]), .QN(n3939) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n203), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[12]), .QN(n3932) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n205), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[14]), .QN(n3941) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n207), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[16]), .QN(n3938) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n193), .CK(clk),
.RN(n4063), .Q(Sgf_normalized_result[2]), .QN(n437) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n197), .CK(clk),
.RN(n874), .Q(Sgf_normalized_result[6]), .QN(n3936) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n191), .CK(clk),
.RN(n3876), .Q(Sgf_normalized_result[0]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_4_ ( .D(
Sgf_operation_EVEN1_middle_N4), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[4]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_6_ ( .D(
Sgf_operation_EVEN1_middle_N6), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[6]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_7_ ( .D(
Sgf_operation_EVEN1_middle_N7), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[7]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_8_ ( .D(
Sgf_operation_EVEN1_middle_N8), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[8]) );
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_1_ ( .D(
Sgf_operation_EVEN1_right_N1), .CK(clk), .Q(Sgf_operation_Result[1])
);
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_0_ ( .D(
Sgf_operation_EVEN1_middle_N0), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[0]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_2_ ( .D(
Sgf_operation_EVEN1_middle_N2), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[2]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_3_ ( .D(
Sgf_operation_EVEN1_middle_N3), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[3]) );
DFFHQX4TS Sgf_operation_EVEN1_left_DatO_reg_6_ ( .D(
Sgf_operation_EVEN1_left_N6), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[6]) );
DFFRX1TS R_841 ( .D(n236), .CK(clk), .RN(n447), .Q(n3989) );
DFFRX1TS R_844 ( .D(n237), .CK(clk), .RN(n447), .Q(n3987) );
DFFRX1TS R_850 ( .D(n239), .CK(clk), .RN(n4056), .Q(n3983) );
DFFHQX4TS Sgf_operation_EVEN1_left_DatO_reg_0_ ( .D(
Sgf_operation_EVEN1_left_N0), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[0]) );
DFFHQX4TS DP_OP_111J16_123_4462_R_1081 ( .D(DP_OP_111J16_123_4462_n150),
.CK(clk), .Q(n3871) );
DFFHQX4TS DP_OP_111J16_123_4462_R_987 ( .D(n833), .CK(clk), .Q(n3856) );
DFFHQX4TS DP_OP_111J16_123_4462_R_947 ( .D(DP_OP_111J16_123_4462_n83), .CK(
clk), .Q(n3854) );
DFFHQX4TS DP_OP_111J16_123_4462_R_224 ( .D(DP_OP_111J16_123_4462_n9), .CK(
clk), .Q(n3811) );
DFFHQX2TS DP_OP_111J16_123_4462_R_218 ( .D(DP_OP_111J16_123_4462_n10), .CK(
clk), .Q(n3808) );
DFFHQX4TS DP_OP_111J16_123_4462_R_436 ( .D(DP_OP_111J16_123_4462_n140), .CK(
clk), .Q(n3822) );
DFFHQX4TS DP_OP_111J16_123_4462_R_352 ( .D(DP_OP_111J16_123_4462_n106), .CK(
clk), .Q(n3820) );
DFFHQX2TS DP_OP_111J16_123_4462_R_238 ( .D(DP_OP_111J16_123_4462_n17), .CK(
clk), .Q(n3815) );
DFFQX1TS DP_OP_111J16_123_4462_R_1061 ( .D(DP_OP_111J16_123_4462_n158), .CK(
clk), .Q(n3868) );
DFFQX1TS DP_OP_111J16_123_4462_R_1062 ( .D(DP_OP_111J16_123_4462_n159), .CK(
clk), .Q(n3869) );
DFFHQX2TS DP_OP_111J16_123_4462_R_456 ( .D(DP_OP_111J16_123_4462_n59), .CK(
clk), .Q(n3824) );
DFFQX1TS DP_OP_111J16_123_4462_R_450 ( .D(DP_OP_111J16_123_4462_n72), .CK(
clk), .Q(n3823) );
DFFQX1TS DP_OP_111J16_123_4462_R_926 ( .D(DP_OP_111J16_123_4462_n94), .CK(
clk), .Q(n3853) );
DFFHQX4TS DP_OP_111J16_123_4462_R_1164 ( .D(DP_OP_111J16_123_4462_n219),
.CK(clk), .Q(n3875) );
DFFQX1TS DP_OP_111J16_123_4462_R_658 ( .D(n3883), .CK(clk), .Q(n3834) );
DFFRX4TS DP_OP_111J16_123_4462_R_1103 ( .D(n3838), .CK(clk), .RN(n3876), .Q(
DP_OP_111J16_123_4462_n751) );
DFFSX4TS DP_OP_111J16_123_4462_R_1104 ( .D(n3874), .CK(clk), .SN(n3877), .Q(
DP_OP_111J16_123_4462_n753) );
DFFRX4TS DP_OP_111J16_123_4462_R_1085 ( .D(n3873), .CK(clk), .RN(n3878), .Q(
DP_OP_111J16_123_4462_n606), .QN(n3894) );
DFFSX2TS DP_OP_111J16_123_4462_R_1084 ( .D(n3872), .CK(clk), .SN(n3879), .Q(
DP_OP_111J16_123_4462_n616) );
DFFRX4TS DP_OP_111J16_123_4462_R_1071 ( .D(n3881), .CK(clk), .RN(n3877), .Q(
DP_OP_111J16_123_4462_n831) );
DFFSX4TS DP_OP_111J16_123_4462_R_1044 ( .D(n3852), .CK(clk), .SN(n871), .Q(
DP_OP_111J16_123_4462_n749) );
DFFRX4TS DP_OP_111J16_123_4462_R_1043 ( .D(n3863), .CK(clk), .RN(n3978), .Q(
DP_OP_111J16_123_4462_n821) );
DFFRX4TS DP_OP_111J16_123_4462_R_1025 ( .D(n3866), .CK(clk), .RN(n3880), .Q(
DP_OP_111J16_123_4462_n698), .QN(n3888) );
DFFRX4TS DP_OP_111J16_123_4462_R_1019 ( .D(n3865), .CK(clk), .RN(n3878), .Q(
DP_OP_111J16_123_4462_n607), .QN(n3887) );
DFFSX4TS DP_OP_111J16_123_4462_R_1015 ( .D(n3841), .CK(clk), .SN(n3978), .Q(
DP_OP_111J16_123_4462_n744) );
DFFRX4TS DP_OP_111J16_123_4462_R_1011 ( .D(n3861), .CK(clk), .RN(n3878), .Q(
DP_OP_111J16_123_4462_n605), .QN(n3889) );
DFFSX4TS DP_OP_111J16_123_4462_R_1010 ( .D(n3860), .CK(clk), .SN(n409), .Q(
DP_OP_111J16_123_4462_n680), .QN(n3893) );
DFFSX4TS DP_OP_111J16_123_4462_R_1009 ( .D(n730), .CK(clk), .SN(n409), .Q(
DP_OP_111J16_123_4462_n713), .QN(n740) );
DFFRX4TS DP_OP_111J16_123_4462_R_1007 ( .D(n3859), .CK(clk), .RN(n408), .Q(
DP_OP_111J16_123_4462_n699), .QN(n3886) );
DFFSX4TS DP_OP_111J16_123_4462_R_1003 ( .D(n3857), .CK(clk), .SN(n3735), .Q(
DP_OP_111J16_123_4462_n625) );
DFFSX4TS DP_OP_111J16_123_4462_R_993 ( .D(n649), .CK(clk), .SN(n3978), .Q(
DP_OP_111J16_123_4462_n754) );
DFFRX4TS DP_OP_111J16_123_4462_R_968 ( .D(n3855), .CK(clk), .RN(n3735), .Q(
DP_OP_111J16_123_4462_n697), .QN(n3890) );
DFFSX4TS DP_OP_111J16_123_4462_R_907 ( .D(n3849), .CK(clk), .SN(n3879), .Q(
DP_OP_111J16_123_4462_n684), .QN(n898) );
DFFSX4TS DP_OP_111J16_123_4462_R_905 ( .D(n3848), .CK(clk), .SN(n3879), .Q(
DP_OP_111J16_123_4462_n685), .QN(n896) );
DFFRX4TS DP_OP_111J16_123_4462_R_903 ( .D(n3847), .CK(clk), .RN(n3879), .Q(
DP_OP_111J16_123_4462_n695), .QN(n3892) );
DFFSX4TS DP_OP_111J16_123_4462_R_830 ( .D(n3800), .CK(clk), .SN(n3877), .Q(
n727) );
DFFSX4TS DP_OP_111J16_123_4462_R_831 ( .D(n3844), .CK(clk), .SN(n3876), .Q(
DP_OP_111J16_123_4462_n728) );
DFFRX4TS DP_OP_111J16_123_4462_R_822 ( .D(n3882), .CK(clk), .RN(n3879), .Q(
n3837), .QN(n1445) );
DFFSX4TS DP_OP_111J16_123_4462_R_819 ( .D(n3843), .CK(clk), .SN(n3879), .Q(
DP_OP_111J16_123_4462_n683), .QN(n734) );
DFFSX4TS DP_OP_111J16_123_4462_R_742 ( .D(n3799), .CK(clk), .SN(n872), .Q(
DP_OP_111J16_123_4462_n757) );
DFFSX4TS DP_OP_111J16_123_4462_R_744 ( .D(n3839), .CK(clk), .SN(n3876), .Q(
DP_OP_111J16_123_4462_n766) );
DFFRX4TS DP_OP_111J16_123_4462_R_820 ( .D(n3882), .CK(clk), .RN(n3879), .Q(
DP_OP_111J16_123_4462_n707), .QN(n880) );
DFFSX4TS DP_OP_111J16_123_4462_R_685 ( .D(n3836), .CK(clk), .SN(n3879), .Q(
DP_OP_111J16_123_4462_n694), .QN(n3891) );
DFFSX4TS DP_OP_111J16_123_4462_R_618 ( .D(n3801), .CK(clk), .SN(n3877), .Q(
DP_OP_111J16_123_4462_n767), .QN(n3885) );
DFFSX4TS DP_OP_111J16_123_4462_R_620 ( .D(n3831), .CK(clk), .SN(n872), .Q(
DP_OP_111J16_123_4462_n758) );
DFFSX4TS DP_OP_111J16_123_4462_R_427 ( .D(n3803), .CK(clk), .SN(n3876), .QN(
n1446) );
DFFSX4TS DP_OP_111J16_123_4462_R_289 ( .D(n3797), .CK(clk), .SN(n3877), .Q(
DP_OP_111J16_123_4462_n773) );
DFFSX4TS DP_OP_111J16_123_4462_R_278 ( .D(n3817), .CK(clk), .SN(n3876), .Q(
DP_OP_111J16_123_4462_n774) );
DFFSX4TS DP_OP_111J16_123_4462_R_277 ( .D(n3816), .CK(clk), .SN(n3876), .Q(
DP_OP_111J16_123_4462_n783) );
DFFSX4TS DP_OP_111J16_123_4462_R_1018 ( .D(n3796), .CK(clk), .SN(n3876), .Q(
DP_OP_111J16_123_4462_n820) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n200), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[9]), .QN(n3945) );
DFFSX1TS add_x_19_R_1142 ( .D(add_x_19_n216), .CK(clk), .SN(n875), .Q(n3784)
);
DFFSX1TS add_x_19_R_1125 ( .D(add_x_19_n232), .CK(clk), .SN(n875), .Q(n3776)
);
DFFSX2TS add_x_19_R_1078 ( .D(add_x_19_n160), .CK(clk), .SN(n876), .Q(n3773),
.QN(n1462) );
DFFSX2TS add_x_19_R_1133 ( .D(add_x_19_n124), .CK(clk), .SN(n3793), .Q(n3780) );
DFFSX2TS add_x_19_R_1035 ( .D(add_x_19_n178), .CK(clk), .SN(n3792), .Q(n3771) );
DFFSX2TS add_x_19_R_1130 ( .D(add_x_19_n272), .CK(clk), .SN(n3790), .Q(n3778) );
DFFSX2TS add_x_19_R_1134 ( .D(add_x_19_n132), .CK(clk), .SN(n3793), .Q(n3781) );
DFFSX2TS add_x_19_R_1082 ( .D(add_x_19_n310), .CK(clk), .SN(n3790), .QN(
n1447) );
DFFSX2TS add_x_19_R_1141 ( .D(add_x_19_n215), .CK(clk), .SN(n3976), .Q(n3783) );
DFFSX2TS add_x_19_R_1140 ( .D(add_x_19_n243), .CK(clk), .SN(n3976), .Q(n3782) );
DFFSX1TS add_x_19_R_1099 ( .D(add_x_19_n213), .CK(clk), .SN(n875), .Q(n3775)
);
DFFSX1TS add_x_19_R_1126 ( .D(add_x_19_n19), .CK(clk), .SN(n875), .Q(n3777)
);
DFFRXLTS add_x_19_R_1094 ( .D(add_x_19_n24), .CK(clk), .RN(n3793), .Q(n3774)
);
DFFSX1TS add_x_19_R_985 ( .D(add_x_19_n221), .CK(clk), .SN(n876), .Q(n3769)
);
DFFSX1TS add_x_19_R_1145 ( .D(n2984), .CK(clk), .SN(n3792), .Q(n3785) );
DFFRX2TS add_x_19_R_1147_RW_0 ( .D(add_x_19_n160), .CK(clk), .RN(n3792), .Q(
n3787) );
DFFRX2TS add_x_19_R_1146 ( .D(add_x_19_n185), .CK(clk), .RN(n447), .Q(n3786)
);
DFFRX4TS add_x_19_R_1131 ( .D(add_x_19_n204), .CK(clk), .RN(n3977), .Q(n3779) );
DFFSX4TS add_x_19_R_986 ( .D(add_x_19_n18), .CK(clk), .SN(n4057), .Q(n3770)
);
DFFSX1TS add_x_19_R_967 ( .D(add_x_19_n186), .CK(clk), .SN(n4057), .Q(n3768)
);
DFFSX1TS add_x_19_R_966 ( .D(add_x_19_n185), .CK(clk), .SN(n3976), .Q(n3767)
);
DFFSX2TS add_x_19_R_940 ( .D(add_x_19_n17), .CK(clk), .SN(n3977), .Q(n3766)
);
DFFSX1TS add_x_19_R_777 ( .D(add_x_19_n194), .CK(clk), .SN(n3792), .Q(n3765)
);
DFFRXLTS add_x_19_R_764 ( .D(add_x_19_n202), .CK(clk), .RN(n3977), .Q(n3764)
);
DFFSX1TS add_x_19_R_730 ( .D(add_x_19_n168), .CK(clk), .SN(n4057), .Q(n3763)
);
DFFSX1TS add_x_19_R_644 ( .D(add_x_19_n14), .CK(clk), .SN(n875), .Q(n3762)
);
DFFSX1TS add_x_19_R_642 ( .D(add_x_19_n12), .CK(clk), .SN(n3974), .Q(n3761)
);
DFFSX1TS add_x_19_R_637 ( .D(add_x_19_n13), .CK(clk), .SN(n3974), .Q(n3760)
);
DFFSX1TS add_x_19_R_635 ( .D(add_x_19_n15), .CK(clk), .SN(n3977), .Q(n3759)
);
DFFSX1TS add_x_19_R_631 ( .D(add_x_19_n11), .CK(clk), .SN(n3977), .Q(n3758)
);
DFFSX1TS add_x_19_R_629 ( .D(add_x_19_n10), .CK(clk), .SN(n3974), .Q(n3757)
);
DFFSX1TS add_x_19_R_608 ( .D(add_x_19_n9), .CK(clk), .SN(n420), .Q(n3756) );
DFFSX1TS add_x_19_R_576 ( .D(add_x_19_n130), .CK(clk), .SN(n3790), .Q(n3754)
);
DFFSX1TS add_x_19_R_458 ( .D(add_x_19_n8), .CK(clk), .SN(n421), .Q(n3753) );
DFFSX1TS add_x_19_R_421 ( .D(n1798), .CK(clk), .SN(n420), .Q(n3752) );
DFFSX1TS add_x_19_R_419 ( .D(n706), .CK(clk), .SN(n421), .Q(n3751) );
DFFSX1TS add_x_19_R_415 ( .D(n1859), .CK(clk), .SN(n3790), .Q(n3749) );
DFFSX1TS add_x_19_R_409 ( .D(n1875), .CK(clk), .SN(n3790), .Q(n3747) );
DFFSX1TS add_x_19_R_407 ( .D(n1878), .CK(clk), .SN(n3790), .Q(n3746) );
DFFSX1TS add_x_19_R_405 ( .D(n1467), .CK(clk), .SN(n421), .Q(n3745) );
DFFSX1TS add_x_19_R_403 ( .D(n1460), .CK(clk), .SN(n3793), .QN(n742) );
DFFHQX4TS mult_x_23_R_1128 ( .D(mult_x_23_n194), .CK(clk), .Q(n3727) );
DFFHQX4TS mult_x_23_R_1127 ( .D(mult_x_23_n140), .CK(clk), .Q(n3726) );
DFFHQX4TS mult_x_23_R_1129 ( .D(n1257), .CK(clk), .Q(n3728) );
DFFHQX4TS mult_x_23_R_490 ( .D(mult_x_23_n88), .CK(clk), .Q(n3689) );
DFFHQX4TS mult_x_23_R_970 ( .D(mult_x_23_n120), .CK(clk), .Q(n3707) );
DFFHQX4TS mult_x_23_R_972 ( .D(mult_x_23_n121), .CK(clk), .Q(n3709) );
DFFHQX4TS mult_x_23_R_971 ( .D(mult_x_23_n140), .CK(clk), .Q(n3708) );
DFFHQX4TS mult_x_23_R_1117 ( .D(mult_x_23_n140), .CK(clk), .Q(n3723) );
DFFHQX2TS mult_x_23_R_431 ( .D(mult_x_23_n19), .CK(clk), .Q(n3682) );
DFFHQX2TS mult_x_23_R_426 ( .D(mult_x_23_n18), .CK(clk), .Q(n3681) );
DFFHQX2TS mult_x_23_R_312 ( .D(mult_x_23_n16), .CK(clk), .Q(n3679) );
DFFHQX2TS mult_x_23_R_307 ( .D(mult_x_23_n15), .CK(clk), .Q(n3678) );
DFFHQX2TS mult_x_23_R_204 ( .D(mult_x_23_n14), .CK(clk), .Q(n3676) );
DFFHQX4TS mult_x_23_R_58 ( .D(mult_x_23_n12), .CK(clk), .Q(n3673) );
DFFHQX2TS mult_x_23_R_56 ( .D(mult_x_23_n11), .CK(clk), .Q(n3672) );
DFFHQX4TS mult_x_23_R_52 ( .D(mult_x_23_n9), .CK(clk), .Q(n3670) );
DFFHQX4TS mult_x_23_R_50 ( .D(mult_x_23_n8), .CK(clk), .Q(n3669) );
DFFHQX4TS mult_x_23_R_453 ( .D(mult_x_23_n109), .CK(clk), .Q(n3686) );
DFFHQX1TS mult_x_23_R_305 ( .D(mult_x_23_n81), .CK(clk), .Q(n3677) );
DFFHQX1TS mult_x_23_R_977 ( .D(mult_x_23_n7), .CK(clk), .Q(n3712) );
DFFHQX4TS mult_x_23_R_990 ( .D(mult_x_23_n140), .CK(clk), .Q(n3713) );
DFFHQX4TS mult_x_23_R_885 ( .D(mult_x_23_n50), .CK(clk), .Q(n3704) );
DFFHQX4TS mult_x_23_R_854 ( .D(mult_x_23_n39), .CK(clk), .Q(n3700) );
DFFHQX4TS mult_x_23_R_825 ( .D(mult_x_23_n65), .CK(clk), .Q(n3698) );
DFFHQX4TS mult_x_23_R_884 ( .D(mult_x_23_n49), .CK(clk), .Q(n3703) );
DFFHQX4TS mult_x_23_R_853 ( .D(mult_x_23_n38), .CK(clk), .Q(n3699) );
DFFRX4TS mult_x_23_R_1150 ( .D(mult_x_23_n520), .CK(clk), .RN(n3979), .Q(
n3666), .QN(n3739) );
DFFSX4TS mult_x_23_R_1144 ( .D(n3729), .CK(clk), .SN(n3880), .QN(n3738) );
DFFRX4TS mult_x_23_R_1138 ( .D(n3561), .CK(clk), .RN(n878), .Q(n3692), .QN(
n705) );
DFFSX4TS mult_x_23_R_1112 ( .D(n3694), .CK(clk), .SN(n3735), .Q(
mult_x_23_n546) );
DFFSX4TS mult_x_23_R_1114 ( .D(n2943), .CK(clk), .SN(n3734), .Q(n3675), .QN(
n840) );
DFFSX1TS mult_x_23_R_1113 ( .D(n3722), .CK(clk), .SN(n3880), .Q(
mult_x_23_n470) );
DFFRX4TS mult_x_23_R_1106 ( .D(n3721), .CK(clk), .RN(n3734), .Q(
mult_x_23_n533), .QN(n3737) );
DFFRX4TS mult_x_23_R_1097 ( .D(mult_x_23_n516), .CK(clk), .RN(n3978), .Q(
n3664), .QN(n3741) );
DFFSX1TS mult_x_23_R_1091 ( .D(n3720), .CK(clk), .SN(n3735), .Q(
mult_x_23_n461) );
DFFRX4TS mult_x_23_R_1092 ( .D(mult_x_23_n525), .CK(clk), .RN(n3979), .Q(
n3667), .QN(n3743) );
DFFSX1TS mult_x_23_R_1069 ( .D(n3719), .CK(clk), .SN(n3735), .Q(
mult_x_23_n459) );
DFFSX4TS mult_x_23_R_1065 ( .D(n3718), .CK(clk), .SN(n3734), .Q(
mult_x_23_n541), .QN(n888) );
DFFSX4TS mult_x_23_R_1105 ( .D(n3693), .CK(clk), .SN(n3734), .Q(n3668), .QN(
n3742) );
DFFSX4TS mult_x_23_R_1136 ( .D(n3716), .CK(clk), .SN(n869), .Q(
mult_x_23_n549) );
DFFSX1TS mult_x_23_R_1000 ( .D(n3715), .CK(clk), .SN(n3880), .Q(
mult_x_23_n480) );
DFFRX4TS mult_x_23_R_1001 ( .D(mult_x_23_n518), .CK(clk), .RN(n3972), .Q(
n3665), .QN(n3740) );
DFFRX4TS mult_x_23_R_976 ( .D(n3711), .CK(clk), .RN(n3735), .Q(n3696), .QN(
n729) );
DFFSX4TS mult_x_23_R_955 ( .D(n3716), .CK(clk), .SN(n870), .Q(n3691) );
DFFSX4TS mult_x_23_R_890 ( .D(n3705), .CK(clk), .SN(n3735), .Q(
mult_x_23_n540), .QN(n864) );
DFFSX1TS mult_x_23_R_875 ( .D(n3702), .CK(clk), .SN(n3734), .Q(
mult_x_23_n472) );
DFFSX1TS mult_x_23_R_859 ( .D(n3701), .CK(clk), .SN(n3734), .Q(
mult_x_23_n492) );
DFFRX2TS mult_x_23_R_975 ( .D(mult_x_23_n553), .CK(clk), .RN(n3972), .Q(
n3695) );
DFFRX4TS mult_x_23_R_861 ( .D(n333), .CK(clk), .RN(n3648), .Q(mult_x_23_n517), .QN(n3706) );
DFFRX4TS R_1206 ( .D(mult_x_23_n553), .CK(clk), .RN(n3649), .Q(n3663), .QN(
n1452) );
DFFRX4TS mult_x_23_R_1063 ( .D(mult_x_23_n552), .CK(clk), .RN(n3876), .Q(
n3662), .QN(n1450) );
DFFRX4TS mult_x_23_R_1143 ( .D(mult_x_23_n551), .CK(clk), .RN(n3972), .Q(
n3661) );
DFFHQX4TS mult_x_23_R_592 ( .D(mult_x_23_n100), .CK(clk), .Q(n3690) );
DFFHQX4TS mult_x_55_R_983 ( .D(mult_x_55_n115), .CK(clk), .Q(n3626) );
DFFHQX4TS mult_x_55_R_649 ( .D(mult_x_55_n87), .CK(clk), .Q(n3608) );
DFFHQX1TS mult_x_55_R_646 ( .D(mult_x_55_n188), .CK(clk), .Q(n3606) );
DFFHQX2TS mult_x_55_R_549 ( .D(mult_x_55_n16), .CK(clk), .Q(n3595) );
DFFHQX4TS mult_x_55_R_984 ( .D(mult_x_55_n116), .CK(clk), .Q(n3627) );
DFFHQX4TS mult_x_55_R_480 ( .D(mult_x_55_n69), .CK(clk), .Q(n3591) );
DFFHQX4TS mult_x_55_R_477 ( .D(mult_x_55_n56), .CK(clk), .Q(n3590) );
DFFHQX4TS mult_x_55_R_385 ( .D(mult_x_55_n11), .CK(clk), .Q(n3589) );
DFFHQX2TS mult_x_55_R_383 ( .D(mult_x_55_n13), .CK(clk), .Q(n3588) );
DFFHQX2TS mult_x_55_R_381 ( .D(mult_x_55_n12), .CK(clk), .Q(n3587) );
DFFHQX2TS mult_x_55_R_373 ( .D(mult_x_55_n10), .CK(clk), .Q(n3586) );
DFFHQX2TS mult_x_55_R_346 ( .D(mult_x_55_n9), .CK(clk), .Q(n3585) );
DFFHQX4TS mult_x_55_R_344 ( .D(mult_x_55_n7), .CK(clk), .Q(n3584) );
DFFHQX4TS mult_x_55_R_342 ( .D(mult_x_55_n6), .CK(clk), .Q(n3583) );
DFFHQX4TS mult_x_55_R_340 ( .D(mult_x_55_n8), .CK(clk), .Q(n3582) );
DFFHQX2TS mult_x_55_R_656 ( .D(mult_x_55_n14), .CK(clk), .Q(n3610) );
DFFHQX4TS mult_x_55_R_647 ( .D(n1011), .CK(clk), .Q(n3607) );
DFFQX1TS mult_x_55_R_748 ( .D(n3651), .CK(clk), .Q(n3619) );
DFFQX1TS mult_x_55_R_724 ( .D(mult_x_55_n47), .CK(clk), .Q(n3617) );
DFFHQX4TS mult_x_55_R_486 ( .D(mult_x_55_n32), .CK(clk), .Q(n3593) );
DFFHQX4TS mult_x_55_R_483 ( .D(mult_x_55_n45), .CK(clk), .Q(n3592) );
DFFHQX2TS mult_x_55_R_725 ( .D(mult_x_55_n48), .CK(clk), .Q(n3618) );
DFFQX1TS mult_x_55_R_616 ( .D(mult_x_55_n72), .CK(clk), .Q(n3603) );
DFFSX4TS mult_x_55_R_1167 ( .D(n3629), .CK(clk), .SN(n3978), .Q(
mult_x_55_n446) );
DFFSX1TS mult_x_55_R_298 ( .D(n3578), .CK(clk), .SN(n3880), .Q(
mult_x_55_n504), .QN(n3645) );
DFFSX1TS mult_x_55_R_1076 ( .D(n3634), .CK(clk), .SN(n3735), .Q(
mult_x_55_n506), .QN(n3643) );
DFFSX4TS mult_x_55_R_1163 ( .D(n3642), .CK(clk), .SN(n409), .Q(
mult_x_55_n557), .QN(n3658) );
DFFSX4TS mult_x_55_R_1160 ( .D(n3641), .CK(clk), .SN(n3647), .Q(
mult_x_55_n449) );
DFFRX1TS mult_x_55_R_1161 ( .D(n313), .CK(clk), .RN(n4063), .Q(
mult_x_55_n538) );
DFFSX4TS mult_x_55_R_1157 ( .D(n3639), .CK(clk), .SN(n3979), .Q(
mult_x_55_n445) );
DFFRX4TS mult_x_55_R_1121 ( .D(n320), .CK(clk), .RN(n3649), .Q(
mult_x_55_n531), .QN(n3655) );
DFFSX1TS mult_x_55_R_1122 ( .D(n3638), .CK(clk), .SN(n3648), .Q(
mult_x_55_n479) );
DFFSX4TS mult_x_55_R_1111 ( .D(n3637), .CK(clk), .SN(n908), .Q(
mult_x_55_n583), .QN(n3659) );
DFFRX4TS mult_x_55_R_1108 ( .D(n319), .CK(clk), .RN(n3649), .Q(
mult_x_55_n532), .QN(n3652) );
DFFSX1TS mult_x_55_R_1109 ( .D(n3636), .CK(clk), .SN(n3648), .Q(
mult_x_55_n480) );
DFFRX4TS mult_x_55_R_1073 ( .D(n3633), .CK(clk), .RN(n3647), .Q(n3613), .QN(
n700) );
DFFRX2TS mult_x_55_R_1041 ( .D(n314), .CK(clk), .RN(n4063), .Q(
mult_x_55_n537) );
DFFSX4TS mult_x_55_R_1040 ( .D(n3631), .CK(clk), .SN(n3647), .Q(
mult_x_55_n448), .QN(n3654) );
DFFSX4TS mult_x_55_R_1158 ( .D(n3630), .CK(clk), .SN(n3648), .Q(
mult_x_55_n559), .QN(n849) );
DFFRX4TS mult_x_55_R_1072 ( .D(mult_x_55_n566), .CK(clk), .RN(n4063), .Q(
n3612), .QN(n854) );
DFFSX4TS mult_x_55_R_882 ( .D(n3623), .CK(clk), .SN(n3648), .Q(
mult_x_55_n554), .QN(n715) );
DFFSX4TS mult_x_55_R_881 ( .D(n3622), .CK(clk), .SN(n3647), .Q(n3611) );
DFFSX1TS mult_x_55_R_815 ( .D(n3621), .CK(clk), .SN(n3647), .Q(
mult_x_55_n494) );
DFFSX4TS mult_x_55_R_1166 ( .D(n1174), .CK(clk), .SN(n3648), .Q(
mult_x_55_n562), .QN(n832) );
DFFSX4TS mult_x_55_R_814 ( .D(n3616), .CK(clk), .SN(n3979), .Q(
mult_x_55_n444) );
DFFSX4TS mult_x_55_R_680 ( .D(n3615), .CK(clk), .SN(n872), .Q(mult_x_55_n556), .QN(n862) );
DFFRX4TS R_1217 ( .D(mult_x_55_n567), .CK(clk), .RN(n408), .Q(n3573), .QN(
n3657) );
DFFRX4TS mult_x_55_R_284 ( .D(n322), .CK(clk), .RN(n3647), .Q(mult_x_55_n529), .QN(n3581) );
DFFRX4TS mult_x_55_R_299 ( .D(n321), .CK(clk), .RN(n3649), .Q(mult_x_55_n530), .QN(n3580) );
DFFSX4TS mult_x_55_R_318 ( .D(n3579), .CK(clk), .SN(n3648), .Q(
mult_x_55_n555), .QN(n892) );
DFFSX1TS mult_x_55_R_283 ( .D(n3576), .CK(clk), .SN(n3647), .Q(
mult_x_55_n490) );
DFFRX4TS mult_x_55_R_1101 ( .D(mult_x_55_n568), .CK(clk), .RN(n3648), .Q(
n3574) );
DFFRX4TS mult_x_55_R_1029 ( .D(mult_x_55_n565), .CK(clk), .RN(n3647), .Q(
n3572) );
DFFRX4TS DP_OP_111J16_123_4462_R_832 ( .D(n3845), .CK(clk), .RN(n3876), .Q(
DP_OP_111J16_123_4462_n827) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n4061), .Q(Op_MY[27]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n4061), .Q(Op_MY[25]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n208), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[17]), .QN(n3943) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n4061), .Q(Op_MY[28]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n871), .Q(Op_MY[29]) );
DFFRX4TS mult_x_55_R_1059 ( .D(n3632), .CK(clk), .RN(n3649), .Q(
mult_x_55_n544) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n202), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[11]), .QN(n3948) );
DFFSHQX4TS R_755_IP ( .D(n3629), .CK(clk), .SN(n878), .Q(n4036) );
DFFRHQX1TS R_40 ( .D(n313), .CK(clk), .RN(n869), .Q(n3570) );
DFFSHQX8TS R_809_IP ( .D(n3568), .CK(clk), .SN(n869), .Q(n3569) );
DFFSHQX8TS R_90_IP ( .D(n3567), .CK(clk), .SN(n870), .Q(n4034) );
DFFRHQX1TS R_701 ( .D(mult_x_23_n551), .CK(clk), .RN(n870), .Q(Op_MX[19]) );
DFFRX1TS R_847 ( .D(n238), .CK(clk), .RN(n3973), .Q(n3985) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n306), .CK(clk), .RN(n4060),
.QN(n4069) );
DFFRHQX2TS Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n228), .CK(clk), .RN(
n4072), .Q(P_Sgf[13]) );
DFFSHQX8TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n3565), .CK(clk), .SN(n869),
.Q(n3901) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n273), .CK(clk), .RN(n878),
.QN(n3902) );
DFFSRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n201), .CK(clk),
.SN(1'b1), .RN(n870), .Q(Sgf_normalized_result[10]) );
DFFSHQX8TS R_1090_IP ( .D(n3562), .CK(clk), .SN(n870), .Q(n3563) );
DFFRHQX2TS Sel_C_Q_reg_0_ ( .D(n214), .CK(clk), .RN(n869), .Q(FSM_selector_C) );
DFFSHQX4TS mult_x_55_R_1039_IP ( .D(n1442), .CK(clk), .SN(n878), .Q(n3660)
);
DFFRHQX8TS mult_x_55_R_756_IP ( .D(n425), .CK(clk), .RN(n870), .Q(n3644) );
DFFRHQX4TS DP_OP_111J16_123_4462_R_1045_IP ( .D(n738), .CK(clk), .RN(n870),
.Q(n3895) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n276), .CK(clk), .RN(n878),
.QN(n3897) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n225), .CK(clk), .RN(
n4057), .Q(P_Sgf[10]), .QN(n4068) );
DFFRX1TS R_317 ( .D(n350), .CK(clk), .RN(n4067), .Q(Op_MX[6]) );
DFFSX2TS DP_OP_111J16_123_4462_R_167 ( .D(n3804), .CK(clk), .SN(n3877), .Q(
DP_OP_111J16_123_4462_n792) );
DFFRXLTS R_498 ( .D(n245), .CK(clk), .RN(n3794), .Q(n4000) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n3978), .Q(Op_MY[30]), .QN(n3927) );
DFFHQX8TS Sgf_operation_EVEN1_left_DatO_reg_5_ ( .D(
Sgf_operation_EVEN1_left_N5), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[5]) );
DFFHQX8TS Sgf_operation_EVEN1_left_DatO_reg_2_ ( .D(
Sgf_operation_EVEN1_left_N2), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[2]) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n199), .CK(clk),
.RN(n4063), .Q(Sgf_normalized_result[8]), .QN(n3937) );
DFFRX2TS mult_x_55_R_1023 ( .D(n316), .CK(clk), .RN(n3649), .Q(
mult_x_55_n535) );
DFFSHQX8TS DP_OP_111J16_123_4462_R_770 ( .D(n3840), .CK(clk), .SN(n870), .Q(
DP_OP_111J16_123_4462_n682) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n4061), .Q(Op_MY[24]) );
DFFHQX4TS mult_x_23_R_1151 ( .D(mult_x_23_n113), .CK(clk), .Q(n3730) );
DFFHQX4TS DP_OP_111J16_123_4462_R_473 ( .D(DP_OP_111J16_123_4462_n46), .CK(
clk), .Q(n3825) );
DFFHQX4TS mult_x_55_R_550 ( .D(mult_x_55_n130), .CK(clk), .Q(n3596) );
DFFSX4TS mult_x_23_R_1067 ( .D(n3710), .CK(clk), .SN(n3880), .Q(
mult_x_23_n545) );
DFFHQX8TS mult_x_23_R_452 ( .D(mult_x_23_n190), .CK(clk), .Q(n3685) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n212), .CK(clk),
.RN(n871), .Q(Sgf_normalized_result[21]), .QN(n3942) );
DFFHQX4TS mult_x_23_R_1118 ( .D(mult_x_23_n127), .CK(clk), .Q(n3724) );
DFFHQX4TS mult_x_55_R_980 ( .D(mult_x_55_n18), .CK(clk), .Q(n3625) );
DFFRX2TS mult_x_55_R_1159 ( .D(n3640), .CK(clk), .RN(n871), .Q(
mult_x_55_n270), .QN(n3656) );
DFFHQX4TS Sgf_operation_EVEN1_left_DatO_reg_3_ ( .D(
Sgf_operation_EVEN1_left_N3), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[3]) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n277), .CK(clk), .RN(n4062),
.QN(n3899) );
DFFHQX4TS DP_OP_111J16_123_4462_R_234 ( .D(DP_OP_111J16_123_4462_n15), .CK(
clk), .Q(n3813) );
DFFSX2TS mult_x_55_R_996 ( .D(n3628), .CK(clk), .SN(n3734), .Q(
mult_x_55_n505) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n4061), .Q(Op_MY[23]) );
DFFHQX1TS mult_x_55_R_594 ( .D(mult_x_55_n58), .CK(clk), .Q(n3600) );
DFFHQX8TS Sgf_operation_EVEN1_left_DatO_reg_8_ ( .D(
Sgf_operation_EVEN1_left_N8), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[8]) );
DFFRX4TS DP_OP_111J16_123_4462_R_1012 ( .D(n3821), .CK(clk), .RN(n3878), .Q(
DP_OP_111J16_123_4462_n785) );
DFFHQX4TS DP_OP_111J16_123_4462_R_333 ( .D(DP_OP_111J16_123_4462_n16), .CK(
clk), .Q(n3818) );
DFFHQX8TS Sgf_operation_EVEN1_left_DatO_reg_9_ ( .D(
Sgf_operation_EVEN1_left_N9), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[9]) );
DFFHQX4TS DP_OP_111J16_123_4462_R_214 ( .D(DP_OP_111J16_123_4462_n12), .CK(
clk), .Q(n3807) );
DFFHQX4TS mult_x_23_R_1153 ( .D(mult_x_23_n114), .CK(clk), .Q(n3732) );
DFFQX4TS mult_x_55_R_595 ( .D(mult_x_55_n59), .CK(clk), .Q(n3601) );
DFFHQX8TS mult_x_55_R_749 ( .D(n3650), .CK(clk), .Q(n3620) );
DFFHQX8TS Sgf_operation_EVEN1_right_DatO_reg_0_ ( .D(
Sgf_operation_EVEN1_right_N0), .CK(clk), .Q(Sgf_operation_Result[0])
);
DFFRX4TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n278), .CK(clk), .RN(n4062),
.QN(n3898) );
DFFHQX4TS DP_OP_111J16_123_4462_R_633 ( .D(DP_OP_111J16_123_4462_n19), .CK(
clk), .Q(n3832) );
DFFHQX1TS mult_x_55_R_639 ( .D(mult_x_55_n94), .CK(clk), .Q(n3604) );
DFFQX4TS mult_x_55_R_615 ( .D(n1097), .CK(clk), .Q(n3602) );
DFFHQX8TS Sgf_operation_EVEN1_left_DatO_reg_7_ ( .D(
Sgf_operation_EVEN1_left_N7), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[7]) );
DFFRX2TS mult_x_55_R_1102 ( .D(n3635), .CK(clk), .RN(n3647), .Q(
mult_x_55_n543) );
DFFHQX8TS DP_OP_111J16_123_4462_R_236 ( .D(DP_OP_111J16_123_4462_n14), .CK(
clk), .Q(n3814) );
DFFRX4TS DP_OP_111J16_123_4462_R_1004 ( .D(n3858), .CK(clk), .RN(n3880), .Q(
DP_OP_111J16_123_4462_n617) );
DFFSX1TS R_849 ( .D(Sgf_operation_Result[24]), .CK(clk), .SN(n906), .Q(n3984) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n298), .CK(clk), .RN(n4059),
.Q(Add_result[8]), .QN(n3953) );
DFFSX1TS R_846 ( .D(Sgf_operation_Result[23]), .CK(clk), .SN(n447), .Q(n3986) );
DFFSX2TS R_843 ( .D(Sgf_operation_Result[22]), .CK(clk), .SN(n447), .Q(n3988) );
DFFSX2TS R_840 ( .D(Sgf_operation_Result[21]), .CK(clk), .SN(n447), .Q(n3990) );
DFFRX4TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n4062), .Q(zero_flag), .QN(n3952) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n408), .Q(Op_MX[31]) );
DFFRX4TS R_1149 ( .D(mult_x_23_n520), .CK(clk), .RN(n3979), .Q(Op_MY[18]) );
DFFRX4TS R_73 ( .D(n358), .CK(clk), .RN(n4067), .QN(n4042) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n284), .CK(clk), .RN(n4058),
.Q(Add_result[22]), .QN(n3911) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n288), .CK(clk), .RN(n4058),
.Q(Add_result[18]), .QN(n3915) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n169),
.CK(clk), .RN(n878), .Q(final_result_ieee[21]) );
DFFRHQX4TS mult_x_23_R_1068_IP ( .D(n327), .CK(clk), .RN(n869), .Q(n3717) );
DFFSX2TS add_x_19_R_1036 ( .D(add_x_19_n179), .CK(clk), .SN(n875), .Q(n3772)
);
DFFHQX8TS mult_x_55_R_897 ( .D(mult_x_55_n3), .CK(clk), .Q(n3624) );
DFFQX1TS DP_OP_111J16_123_4462_R_588 ( .D(DP_OP_111J16_123_4462_n128), .CK(
clk), .Q(n3826) );
DFFHQX4TS DP_OP_111J16_123_4462_R_599 ( .D(DP_OP_111J16_123_4462_n168), .CK(
clk), .Q(n3827) );
DFFHQX8TS Sgf_operation_EVEN1_middle_DatO_reg_1_ ( .D(
Sgf_operation_EVEN1_middle_N1), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[1]) );
DFFHQX4TS mult_x_55_R_553 ( .D(mult_x_55_n15), .CK(clk), .Q(n3598) );
DFFRHQX2TS mult_x_23_R_891 ( .D(n1475), .CK(clk), .RN(n3735), .Q(n817) );
DFFHQX8TS mult_x_23_R_991 ( .D(mult_x_23_n21), .CK(clk), .Q(n3714) );
DFFRHQX8TS mult_x_23_R_1089 ( .D(mult_x_23_n550), .CK(clk), .RN(n3877), .Q(
n811) );
DFFHQX8TS mult_x_55_R_581 ( .D(mult_x_55_n78), .CK(clk), .Q(n3599) );
DFFHQX8TS Sgf_operation_EVEN1_middle_DatO_reg_9_ ( .D(
Sgf_operation_EVEN1_middle_N9), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[9]) );
DFFHQX4TS Sgf_operation_EVEN1_left_DatO_reg_4_ ( .D(
Sgf_operation_EVEN1_left_N4), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[4]) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n293), .CK(clk), .RN(n4059),
.Q(Add_result[13]), .QN(n3920) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n292), .CK(clk), .RN(n4059),
.Q(Add_result[14]), .QN(n3919) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n295), .CK(clk), .RN(n4059),
.Q(Add_result[11]), .QN(n3922) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n297), .CK(clk), .RN(n4059),
.Q(Add_result[9]), .QN(n3924) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n213), .CK(clk),
.RN(n872), .Q(Sgf_normalized_result[22]), .QN(n3933) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n307), .CK(clk),
.RN(n873), .Q(Sgf_normalized_result[23]), .QN(n3949) );
DFFRX2TS R_1096 ( .D(mult_x_23_n516), .CK(clk), .RN(n4061), .Q(Op_MY[22]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n211), .CK(clk),
.RN(n874), .Q(Sgf_normalized_result[20]), .QN(n3931) );
DFFSHQX8TS DP_OP_111J16_123_4462_R_816 ( .D(n3842), .CK(clk), .SN(n908), .Q(
n695) );
DFFHQX4TS mult_x_55_R_551 ( .D(mult_x_55_n17), .CK(clk), .Q(n3597) );
DFFRHQX8TS DP_OP_111J16_123_4462_R_913 ( .D(n3851), .CK(clk), .RN(n3734),
.Q(n686) );
DFFRXLTS R_708 ( .D(n241), .CK(clk), .RN(n447), .Q(n3994) );
DFFRXLTS R_827 ( .D(n240), .CK(clk), .RN(n447), .Q(n3991) );
DFFRXLTS R_1116 ( .D(DP_OP_111J16_123_4462_n880), .CK(clk), .RN(n4063), .QN(
n3925) );
DFFRXLTS R_652 ( .D(n242), .CK(clk), .RN(n906), .Q(n3999) );
DFFRXLTS R_467 ( .D(n243), .CK(clk), .RN(n875), .Q(n4003) );
DFFRXLTS R_393 ( .D(n247), .CK(clk), .RN(n875), .Q(n4004) );
DFFRXLTS R_367 ( .D(n248), .CK(clk), .RN(n906), .Q(n4006) );
DFFRXLTS R_495 ( .D(n246), .CK(clk), .RN(n906), .Q(n4001) );
DFFRXLTS R_492 ( .D(n244), .CK(clk), .RN(n447), .Q(n4002) );
DFFRXLTS R_1162 ( .D(n313), .CK(clk), .RN(n4063), .Q(n4030) );
DFFRXLTS R_686 ( .D(mult_x_55_n533), .CK(clk), .RN(n413), .Q(n4025) );
DFFHQX4TS mult_x_23_R_1119 ( .D(n1258), .CK(clk), .Q(n3725) );
DFFHQX4TS DP_OP_111J16_123_4462_R_1080 ( .D(DP_OP_111J16_123_4462_n149),
.CK(clk), .Q(n3870) );
DFFHQX4TS mult_x_23_R_1152 ( .D(mult_x_23_n141), .CK(clk), .Q(n3731) );
DFFHQX8TS DP_OP_111J16_123_4462_R_600 ( .D(DP_OP_111J16_123_4462_n21), .CK(
clk), .Q(n3828) );
DFFRHQX2TS DP_OP_111J16_123_4462_R_1014 ( .D(n3862), .CK(clk), .RN(n3878),
.Q(n674) );
DFFHQX8TS Sgf_operation_EVEN1_middle_DatO_reg_5_ ( .D(
Sgf_operation_EVEN1_middle_N5), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[5]) );
DFFSX2TS R_1182 ( .D(add_x_19_n142), .CK(clk), .SN(n421), .Q(n663) );
DFFRX2TS R_1183 ( .D(n3003), .CK(clk), .RN(n420), .Q(n662) );
DFFSX2TS R_1184 ( .D(n1917), .CK(clk), .SN(n421), .Q(n661) );
DFFHQX8TS R_1186 ( .D(n660), .CK(clk), .Q(n1811) );
DFFHQX8TS R_1187 ( .D(n659), .CK(clk), .Q(n1805) );
DFFSX2TS R_1188 ( .D(n3440), .CK(clk), .SN(n415), .Q(n658) );
DFFSX2TS R_1190 ( .D(n843), .CK(clk), .SN(n415), .Q(n656) );
DFFQX1TS R_1193 ( .D(n463), .CK(clk), .Q(n654) );
DFFSX2TS R_1196 ( .D(n653), .CK(clk), .SN(n412), .Q(n1494) );
DFFRX4TS R_1195 ( .D(n3577), .CK(clk), .RN(n3649), .Q(n3575), .QN(n3653) );
DFFQX1TS R_1197 ( .D(n497), .CK(clk), .Q(n652) );
DFFQX1TS R_1198 ( .D(n3088), .CK(clk), .Q(n651) );
DFFRX4TS DP_OP_111J16_123_4462_R_856 ( .D(n3846), .CK(clk), .RN(n3878), .Q(
DP_OP_111J16_123_4462_n720), .QN(n823) );
DFFHQX4TS R_1204 ( .D(DP_OP_111J16_123_4462_n128), .CK(clk), .Q(n647) );
DFFHQX4TS R_1203 ( .D(n3083), .CK(clk), .Q(n648) );
DFFRX2TS R_1207 ( .D(n645), .CK(clk), .RN(n878), .Q(n961) );
DFFSX4TS DP_OP_111J16_123_4462_R_1013 ( .D(n3805), .CK(clk), .SN(n3877), .Q(
DP_OP_111J16_123_4462_n778), .QN(n3884) );
DFFHQX4TS DP_OP_111J16_123_4462_R_602 ( .D(DP_OP_111J16_123_4462_n20), .CK(
clk), .Q(n3829) );
DFFSX2TS R_1214 ( .D(n2233), .CK(clk), .SN(n3977), .Q(n641) );
DFFSX4TS R_1213 ( .D(n2234), .CK(clk), .SN(n3977), .Q(n642) );
DFFSX4TS R_1212 ( .D(n3008), .CK(clk), .SN(n3977), .Q(n643) );
DFFRX2TS R_1215 ( .D(n2987), .CK(clk), .RN(n3790), .Q(n640) );
DFFRX2TS R_1216 ( .D(add_x_19_n124), .CK(clk), .RN(n3790), .Q(n639) );
DFFRX2TS R_1218 ( .D(n638), .CK(clk), .RN(n408), .Q(n1478) );
DFFRX4TS add_x_19_R_1170 ( .D(add_x_19_n142), .CK(clk), .RN(n3792), .Q(n3789) );
DFFSX2TS R_1227 ( .D(n441), .CK(clk), .SN(n906), .Q(n633) );
DFFHQX4TS R_1229 ( .D(mult_x_23_n6), .CK(clk), .Q(n631) );
DFFHQX8TS R_1234 ( .D(DP_OP_111J16_123_4462_n130), .CK(clk), .Q(n626) );
DFFSX2TS R_1235 ( .D(add_x_19_n85), .CK(clk), .SN(n3793), .Q(n625) );
DFFRX2TS R_1236 ( .D(add_x_19_n94), .CK(clk), .RN(n3792), .Q(n624) );
DFFRX2TS R_1237 ( .D(add_x_19_n104), .CK(clk), .RN(n3792), .Q(n623) );
DFFRX2TS R_1238 ( .D(add_x_19_n57), .CK(clk), .RN(n3794), .Q(n622) );
DFFRX2TS R_1239 ( .D(add_x_19_n39), .CK(clk), .RN(n3794), .Q(n621) );
DFFRX2TS R_1240 ( .D(add_x_19_n67), .CK(clk), .RN(n3794), .Q(n620) );
DFFSX2TS R_1241 ( .D(n4055), .CK(clk), .SN(n447), .Q(n619), .QN(n618) );
DFFRX2TS R_1242 ( .D(add_x_19_n47), .CK(clk), .RN(n3794), .Q(n617) );
DFFSX2TS R_1243 ( .D(add_x_19_n161), .CK(clk), .SN(n421), .Q(n616), .QN(n615) );
DFFSX2TS R_1247 ( .D(n3004), .CK(clk), .SN(n876), .Q(n611) );
DFFHQX8TS R_1248 ( .D(DP_OP_111J16_123_4462_n224), .CK(clk), .Q(n610) );
DFFSX2TS R_1249 ( .D(add_x_19_n308), .CK(clk), .SN(n421), .Q(n609) );
DFFHQX4TS R_1250 ( .D(mult_x_23_n78), .CK(clk), .Q(n608) );
DFFSX2TS R_1251 ( .D(add_x_19_n271), .CK(clk), .SN(n3793), .Q(n607), .QN(
n606) );
DFFQX1TS R_1252 ( .D(DP_OP_111J16_123_4462_n36), .CK(clk), .Q(n605) );
DFFRX2TS R_1253 ( .D(add_x_19_n125), .CK(clk), .RN(n420), .Q(n604) );
DFFHQX4TS R_1259 ( .D(DP_OP_111J16_123_4462_n116), .CK(clk), .Q(n598) );
DFFQX4TS R_1256 ( .D(DP_OP_111J16_123_4462_n123), .CK(clk), .Q(n601) );
DFFHQX8TS R_1261 ( .D(DP_OP_111J16_123_4462_n82), .CK(clk), .Q(n596) );
DFFHQX8TS R_1264 ( .D(mult_x_23_n71), .CK(clk), .Q(n593) );
DFFHQX8TS R_1265 ( .D(mult_x_23_n36), .CK(clk), .Q(n592) );
DFFHQX8TS R_1266 ( .D(mult_x_23_n47), .CK(clk), .Q(n591) );
DFFRX2TS R_1267 ( .D(n1859), .CK(clk), .RN(n3792), .Q(n590) );
DFFSX2TS R_1268 ( .D(add_x_19_n152), .CK(clk), .SN(n421), .Q(n589) );
DFFRX2TS R_1269 ( .D(n1467), .CK(clk), .RN(n3794), .Q(n588) );
DFFQX1TS R_1270 ( .D(DP_OP_111J16_123_4462_n58), .CK(clk), .Q(n587) );
DFFQX1TS R_1271 ( .D(DP_OP_111J16_123_4462_n45), .CK(clk), .Q(n586) );
DFFSX2TS R_1273 ( .D(add_x_19_n176), .CK(clk), .SN(n876), .Q(n582), .QN(n581) );
DFFHQX8TS R_1274 ( .D(DP_OP_111J16_123_4462_n161), .CK(clk), .Q(n580) );
DFFRX2TS mult_x_23_R_773 ( .D(n3697), .CK(clk), .RN(n3972), .Q(
mult_x_23_n530) );
DFFHQX8TS mult_x_55_R_650 ( .D(mult_x_55_n88), .CK(clk), .Q(n3609) );
DFFHQX2TS mult_x_23_R_397 ( .D(mult_x_23_n97), .CK(clk), .Q(n3680) );
DFFHQX4TS R_1254 ( .D(n833), .CK(clk), .Q(n603) );
DFFHQX4TS mult_x_55_R_548 ( .D(mult_x_55_n121), .CK(clk), .Q(n3594) );
DFFRX4TS DP_OP_111J16_123_4462_R_911 ( .D(n3850), .CK(clk), .RN(n4058), .Q(
DP_OP_111J16_123_4462_n620) );
DFFRX2TS DP_OP_111J16_123_4462_R_1031 ( .D(n3867), .CK(clk), .RN(n3880), .Q(
DP_OP_111J16_123_4462_n619) );
DFFHQX8TS DP_OP_111J16_123_4462_R_351 ( .D(DP_OP_111J16_123_4462_n220), .CK(
clk), .Q(n3819) );
DFFHQX4TS DP_OP_111J16_123_4462_R_220 ( .D(DP_OP_111J16_123_4462_n11), .CK(
clk), .Q(n3809) );
DFFRXLTS R_806 ( .D(n235), .CK(clk), .RN(n3973), .Q(n3992) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n210), .CK(clk),
.RN(n871), .Q(Sgf_normalized_result[19]), .QN(n3946) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n206), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[15]), .QN(n3947) );
DFFSX4TS R_1225 ( .D(n441), .CK(clk), .SN(n3974), .Q(n636) );
DFFSX4TS R_1226 ( .D(n441), .CK(clk), .SN(n876), .Q(n635), .QN(n634) );
DFFRX4TS R_297 ( .D(n321), .CK(clk), .RN(n4058), .Q(Op_MY[9]) );
DFFRX4TS R_995 ( .D(n320), .CK(clk), .RN(n4058), .Q(Op_MY[8]) );
DFFRX1TS R_1189 ( .D(n287), .CK(clk), .RN(n4058), .Q(n657) );
DFFSHQX8TS DP_OP_111J16_123_4462_R_912 ( .D(n3798), .CK(clk), .SN(n3880),
.Q(n403) );
DFFHQX8TS R_1263 ( .D(n401), .CK(clk), .Q(n594) );
DFFHQX4TS R_1272 ( .D(mult_x_23_n87), .CK(clk), .Q(n585) );
DFFRHQX8TS R_45 ( .D(n331), .CK(clk), .RN(n413), .Q(n571) );
DFFSX4TS R_1231 ( .D(add_x_19_n197), .CK(clk), .SN(n876), .Q(n630), .QN(n629) );
DFFRX4TS add_x_19_R_1169 ( .D(n637), .CK(clk), .RN(n3792), .Q(n3788) );
DFFHQX4TS R_1228 ( .D(mult_x_55_n4), .CK(clk), .Q(n632) );
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_6_ ( .D(
Sgf_operation_EVEN1_right_N6), .CK(clk), .Q(Sgf_operation_Result[6])
);
DFFHQX4TS mult_x_23_R_1154 ( .D(mult_x_23_n101), .CK(clk), .Q(n3733) );
DFFHQX4TS R_1255 ( .D(mult_x_23_n99), .CK(clk), .Q(n602) );
DFFHQX4TS R_1246 ( .D(mult_x_23_n94), .CK(clk), .Q(n612) );
DFFHQX2TS mult_x_23_R_488 ( .D(mult_x_23_n100), .CK(clk), .Q(n3688) );
DFFHQX1TS mult_x_23_R_433 ( .D(mult_x_23_n20), .CK(clk), .Q(n3683) );
DFFHQX2TS R_1205 ( .D(n3082), .CK(clk), .Q(n646) );
DFFRHQX4TS mult_x_55_R_929 ( .D(mult_x_55_n570), .CK(clk), .RN(n908), .Q(
n671) );
DFFHQX1TS mult_x_23_R_470 ( .D(mult_x_23_n17), .CK(clk), .Q(n3687) );
DFFHQX2TS mult_x_23_R_441 ( .D(mult_x_23_n100), .CK(clk), .Q(n3684) );
DFFHQX1TS mult_x_55_R_640 ( .D(mult_x_55_n95), .CK(clk), .Q(n3605) );
DFFHQX2TS R_1262 ( .D(DP_OP_111J16_123_4462_n89), .CK(clk), .Q(n595) );
DFFHQX4TS R_1257 ( .D(DP_OP_111J16_123_4462_n97), .CK(clk), .Q(n600) );
DFFHQX1TS mult_x_23_R_114 ( .D(mult_x_23_n13), .CK(clk), .Q(n3674) );
DFFHQX4TS R_1232 ( .D(DP_OP_111J16_123_4462_n96), .CK(clk), .Q(n628) );
DFFRHQX2TS DP_OP_111J16_123_4462_R_712 ( .D(n3802), .CK(clk), .RN(n3877),
.Q(n816) );
DFFHQX4TS R_1245 ( .D(n3736), .CK(clk), .Q(n613) );
DFFQX2TS R_1258 ( .D(DP_OP_111J16_123_4462_n103), .CK(clk), .Q(n599) );
DFFRHQX4TS DP_OP_111J16_123_4462_R_1017 ( .D(n3864), .CK(clk), .RN(n3878),
.Q(n836) );
DFFRX4TS mult_x_55_R_676 ( .D(n3614), .CK(clk), .RN(n872), .QN(n390) );
DFFQX1TS mult_x_23_R_54 ( .D(mult_x_23_n10), .CK(clk), .Q(n3671) );
DFFHQX4TS R_1244 ( .D(DP_OP_111J16_123_4462_n71), .CK(clk), .Q(n614) );
DFFRX2TS DP_OP_111J16_123_4462_R_1042 ( .D(n3830), .CK(clk), .RN(n4061), .Q(
DP_OP_111J16_123_4462_n752) );
DFFRX2TS mult_x_23_R_1115 ( .D(DP_OP_111J16_123_4462_n880), .CK(clk), .RN(
n3972), .Q(mult_x_23_n521) );
DFFRHQX4TS R_100 ( .D(n328), .CK(clk), .RN(n869), .Q(Op_MY[16]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n4067), .Q(Op_MY[26]), .QN(n721) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n3878), .Q(Op_MX[27]), .QN(n3907) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n873), .Q(Op_MX[23]), .QN(n3982) );
DFFRX2TS DP_OP_111J16_123_4462_R_901 ( .D(n323), .CK(clk), .RN(n3878), .Q(
n430) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n3972), .Q(Op_MX[28]), .QN(n3904) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n3972), .Q(Op_MX[29]), .QN(n3995) );
DFFRX2TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n275), .CK(clk), .RN(n874),
.Q(n743), .QN(n4070) );
DFFRX1TS mult_x_55_R_1168 ( .D(n3646), .CK(clk), .RN(n3648), .QN(n697) );
DFFQX1TS DP_OP_111J16_123_4462_R_222 ( .D(DP_OP_111J16_123_4462_n8), .CK(clk), .Q(n3810) );
DFFQX1TS DP_OP_111J16_123_4462_R_210 ( .D(DP_OP_111J16_123_4462_n7), .CK(clk), .Q(n3806) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n195), .CK(clk),
.RN(n4067), .Q(Sgf_normalized_result[4]), .QN(n3950) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n3972), .Q(Op_MX[30]), .QN(n4044) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n196), .CK(clk),
.RN(n4066), .Q(Sgf_normalized_result[5]), .QN(n3926) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n192), .CK(clk),
.RN(n4073), .Q(Sgf_normalized_result[1]), .QN(n436) );
DFFRX2TS mult_x_23_R_877 ( .D(n327), .CK(clk), .RN(n3734), .Q(mult_x_23_n523) );
DFFHQX2TS DP_OP_111J16_123_4462_R_659 ( .D(DP_OP_111J16_123_4462_n39), .CK(
clk), .Q(n3835) );
DFFHQX1TS DP_OP_111J16_123_4462_R_657 ( .D(DP_OP_111J16_123_4462_n48), .CK(
clk), .Q(n3833) );
DFFRX2TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n282), .CK(clk), .RN(
n4060), .QN(n1443) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n209), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[18]), .QN(n3934) );
DFFRX1TS R_930 ( .D(n346), .CK(clk), .RN(n908), .Q(Op_MX[2]) );
DFFSX1TS add_x_19_R_417 ( .D(n1856), .CK(clk), .SN(n3790), .Q(n3750) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n281), .CK(clk), .RN(n4062),
.Q(exp_oper_result_8_), .QN(n3910) );
DFFRXLTS R_294 ( .D(mult_x_55_n569), .CK(clk), .RN(n3978), .Q(n4048), .QN(
n3998) );
DFFQX1TS DP_OP_111J16_123_4462_R_226 ( .D(DP_OP_111J16_123_4462_n6), .CK(clk), .Q(n3812) );
DFFSX1TS add_x_19_R_411 ( .D(n1900), .CK(clk), .SN(n4072), .Q(n3748) );
DFFSX1TS add_x_19_R_763 ( .D(add_x_19_n201), .CK(clk), .SN(n4057), .QN(n574)
);
DFFRX2TS R_246 ( .D(n260), .CK(clk), .RN(n4072), .Q(n4021) );
DFFSX1TS R_889_IP ( .D(n3566), .CK(clk), .SN(n869), .Q(n4041), .QN(n4050) );
DFFRXLTS add_x_19_R_604 ( .D(add_x_19_n16), .CK(clk), .RN(n4072), .Q(n3755)
);
DFFRXLTS R_689 ( .D(n366), .CK(clk), .RN(n3978), .Q(n4053), .QN(n4009) );
DFFSX1TS add_x_19_R_401 ( .D(add_x_19_n51), .CK(clk), .SN(n4072), .Q(n3744)
);
DFFRHQX2TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n302), .CK(clk), .RN(n870),
.Q(Add_result[4]) );
DFFSRHQX2TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n305), .CK(clk), .SN(1'b1),
.RN(n869), .Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n291), .CK(clk), .RN(n4059),
.Q(Add_result[15]), .QN(n3918) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n290), .CK(clk), .RN(n4059),
.Q(Add_result[16]), .QN(n3917) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n283), .CK(clk), .RN(n4060),
.Q(Add_result[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n289), .CK(clk), .RN(n4059),
.Q(Add_result[17]), .QN(n3916) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n286), .CK(clk), .RN(n415),
.Q(Add_result[20]), .QN(n3913) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n285), .CK(clk), .RN(n4058),
.Q(Add_result[21]), .QN(n3912) );
INVX2TS U405 ( .A(mult_x_23_n7), .Y(mult_x_23_n71) );
INVX2TS U406 ( .A(n419), .Y(n421) );
CLKINVX1TS U407 ( .A(n410), .Y(n414) );
CLKINVX1TS U408 ( .A(n410), .Y(n412) );
CLKINVX2TS U409 ( .A(n407), .Y(n408) );
CLKINVX2TS U410 ( .A(n407), .Y(n409) );
NAND2X1TS U411 ( .A(n2783), .B(mult_x_55_n72), .Y(mult_x_55_n10) );
BUFX3TS U412 ( .A(n3735), .Y(n4058) );
CLKINVX2TS U413 ( .A(n419), .Y(n420) );
NAND2X6TS U414 ( .A(add_x_19_n310), .B(add_x_19_n152), .Y(add_x_19_n10) );
CLKINVX1TS U415 ( .A(n410), .Y(n413) );
AOI2BB2X1TS U416 ( .B0(n3379), .B1(n243), .A0N(n900), .A1N(n3249), .Y(n3251)
);
INVX4TS U417 ( .A(n3005), .Y(n1393) );
INVX6TS U418 ( .A(n498), .Y(DP_OP_111J16_123_4462_n220) );
OR2X6TS U419 ( .A(mult_x_55_n58), .B(n2807), .Y(n3651) );
NOR2X4TS U420 ( .A(n2905), .B(n2904), .Y(mult_x_23_n99) );
INVX4TS U421 ( .A(mult_x_23_n94), .Y(n2442) );
INVX4TS U422 ( .A(n3012), .Y(n3004) );
NAND2X1TS U423 ( .A(n2847), .B(n2846), .Y(n2848) );
NAND2X6TS U424 ( .A(n1695), .B(n1694), .Y(n2895) );
INVX2TS U425 ( .A(n3525), .Y(n3526) );
INVX6TS U426 ( .A(add_x_19_n201), .Y(n1395) );
NAND2X1TS U427 ( .A(n2784), .B(n2821), .Y(n2785) );
NAND2X1TS U428 ( .A(n3028), .B(n3027), .Y(n3029) );
BUFX4TS U429 ( .A(n3525), .Y(n3523) );
NOR2X1TS U430 ( .A(n4067), .B(beg_FSM), .Y(n732) );
AOI2BB2X1TS U431 ( .B0(n3379), .B1(n239), .A0N(n900), .A1N(n4069), .Y(n3351)
);
NAND2X1TS U432 ( .A(n4055), .B(P_Sgf[19]), .Y(n554) );
NAND2XLTS U433 ( .A(n842), .B(Add_result[23]), .Y(n471) );
CLKINVX2TS U434 ( .A(n3071), .Y(n3081) );
INVX1TS U435 ( .A(n3049), .Y(n3014) );
BUFX3TS U436 ( .A(n3978), .Y(n3735) );
NAND2XLTS U437 ( .A(n3559), .B(n743), .Y(n1359) );
NAND2XLTS U438 ( .A(n842), .B(Add_result[6]), .Y(n1220) );
INVX1TS U439 ( .A(n2099), .Y(n3100) );
NAND2X2TS U440 ( .A(n2991), .B(n1101), .Y(n3006) );
NAND2XLTS U441 ( .A(n443), .B(Add_result[20]), .Y(n922) );
NAND2XLTS U442 ( .A(n443), .B(Add_result[21]), .Y(n1014) );
NAND2X1TS U443 ( .A(n3106), .B(n1457), .Y(n3107) );
NAND2X2TS U444 ( .A(n2936), .B(n919), .Y(n2937) );
NAND2X1TS U445 ( .A(n3852), .B(n1468), .Y(n1469) );
NAND2X2TS U446 ( .A(n2909), .B(n2908), .Y(n2910) );
NAND2X2TS U447 ( .A(n2998), .B(n512), .Y(n3009) );
NAND2X6TS U448 ( .A(n547), .B(n2819), .Y(n1380) );
CLKINVX2TS U449 ( .A(n1317), .Y(n2919) );
INVX2TS U450 ( .A(n3980), .Y(n410) );
CLKINVX1TS U451 ( .A(n2778), .Y(n2734) );
INVX2TS U452 ( .A(n907), .Y(n407) );
INVX2TS U453 ( .A(n3791), .Y(n419) );
NAND2X1TS U454 ( .A(n3052), .B(n3050), .Y(n3019) );
BUFX8TS U455 ( .A(n3086), .Y(n1073) );
NAND2X2TS U456 ( .A(n3335), .B(n254), .Y(n3237) );
INVX2TS U457 ( .A(n3262), .Y(n3384) );
NAND2X4TS U458 ( .A(n1755), .B(n1754), .Y(n2903) );
INVX4TS U459 ( .A(n964), .Y(n3094) );
CLKMX2X2TS U460 ( .A(n2582), .B(n3991), .S0(n633), .Y(n240) );
CLKINVX6TS U461 ( .A(n3257), .Y(n2588) );
NOR2X6TS U462 ( .A(n1625), .B(n1624), .Y(n2912) );
NAND2X6TS U463 ( .A(n2096), .B(n2095), .Y(n1110) );
NOR2X6TS U464 ( .A(n2370), .B(n2369), .Y(n498) );
NAND2X4TS U465 ( .A(n985), .B(n548), .Y(n547) );
INVX4TS U466 ( .A(n2907), .Y(n2909) );
CLKINVX6TS U467 ( .A(n3257), .Y(n3392) );
INVX2TS U468 ( .A(n950), .Y(n3098) );
NAND2X4TS U469 ( .A(n2229), .B(n515), .Y(n3044) );
NAND2X1TS U470 ( .A(n354), .B(n366), .Y(n3167) );
NAND2X1TS U471 ( .A(n3425), .B(n3448), .Y(n3426) );
OAI2BB1X2TS U472 ( .A0N(mult_x_55_n570), .A1N(n1203), .B0(n3123), .Y(n3157)
);
INVX4TS U473 ( .A(n841), .Y(n443) );
BUFX3TS U474 ( .A(n3353), .Y(n3361) );
CLKBUFX2TS U475 ( .A(n3975), .Y(n3791) );
CLKBUFX2TS U476 ( .A(n908), .Y(n907) );
CLKBUFX2TS U477 ( .A(n3649), .Y(n3980) );
INVX8TS U478 ( .A(n2825), .Y(n2835) );
MX2X4TS U479 ( .A(n3364), .B(n4011), .S0(n635), .Y(n251) );
XOR2X2TS U480 ( .A(n350), .B(n4039), .Y(n3183) );
OR2X1TS U481 ( .A(n3177), .B(n1071), .Y(n741) );
AOI22X2TS U482 ( .A0(n1350), .A1(Add_result[16]), .B0(n3388), .B1(
Sgf_normalized_result[15]), .Y(n1352) );
NAND2X2TS U483 ( .A(n2794), .B(n2793), .Y(n2802) );
AO21XLTS U484 ( .A0(n853), .A1(n2842), .B0(n850), .Y(n2843) );
INVX2TS U485 ( .A(n2781), .Y(n773) );
NOR2X1TS U486 ( .A(n850), .B(n1451), .Y(n2844) );
AND4X1TS U487 ( .A(n455), .B(n3538), .C(n4033), .D(n4034), .Y(n3543) );
INVX2TS U488 ( .A(n2138), .Y(n1030) );
INVX2TS U489 ( .A(n3403), .Y(n3483) );
BUFX4TS U490 ( .A(n3390), .Y(n902) );
AO21X1TS U491 ( .A0(n861), .A1(n895), .B0(n3891), .Y(n3176) );
OR2X4TS U492 ( .A(n2794), .B(n2793), .Y(n2804) );
INVX2TS U493 ( .A(n2136), .Y(n1301) );
NAND2X6TS U494 ( .A(n1007), .B(n1740), .Y(n2913) );
NAND2X1TS U495 ( .A(n346), .B(n358), .Y(n3123) );
NAND2X2TS U496 ( .A(n1768), .B(n1769), .Y(n2772) );
NAND2X4TS U497 ( .A(n2364), .B(n2365), .Y(n2776) );
BUFX3TS U498 ( .A(n3309), .Y(n3388) );
CLKINVX1TS U499 ( .A(n829), .Y(n1193) );
NOR2X1TS U500 ( .A(n977), .B(n2585), .Y(n976) );
NAND2X2TS U501 ( .A(n2227), .B(Sgf_operation_EVEN1_Q_left[0]), .Y(n3050) );
INVX2TS U502 ( .A(n2818), .Y(n548) );
CLKINVX2TS U503 ( .A(n2916), .Y(n1315) );
NAND2X2TS U504 ( .A(n328), .B(n316), .Y(n3800) );
CLKBUFX2TS U505 ( .A(Sgf_operation_EVEN1_Q_left[5]), .Y(n1101) );
INVX2TS U506 ( .A(n3073), .Y(n1151) );
NAND2X4TS U507 ( .A(n561), .B(n562), .Y(n3465) );
NAND2X2TS U508 ( .A(n4055), .B(n3557), .Y(n1473) );
CLKBUFX2TS U509 ( .A(Sgf_operation_EVEN1_Q_left[9]), .Y(n807) );
NOR2X2TS U510 ( .A(n3142), .B(n3125), .Y(n1338) );
NOR4X1TS U511 ( .A(Op_MX[8]), .B(Op_MX[2]), .C(Op_MX[6]), .D(Op_MX[4]), .Y(
n3545) );
INVX6TS U512 ( .A(n3389), .Y(n3261) );
BUFX4TS U513 ( .A(n1741), .Y(n1007) );
CLKINVX6TS U514 ( .A(mult_x_55_n71), .Y(n2783) );
NAND2X4TS U515 ( .A(n2526), .B(n2525), .Y(n2916) );
NAND2X1TS U516 ( .A(Sgf_normalized_result[20]), .B(Sgf_normalized_result[21]), .Y(n3475) );
NAND2X1TS U517 ( .A(n2325), .B(n2348), .Y(n2331) );
NAND2X6TS U518 ( .A(n2756), .B(n2755), .Y(DP_OP_111J16_123_4462_n72) );
INVX2TS U519 ( .A(n3569), .Y(n3539) );
NOR2X6TS U520 ( .A(n2758), .B(n2759), .Y(n2780) );
INVX6TS U521 ( .A(n1213), .Y(n950) );
NAND2BX1TS U522 ( .AN(n3516), .B(round_mode[1]), .Y(n1288) );
NAND2X2TS U523 ( .A(n2758), .B(n2759), .Y(n2781) );
CLKMX2X4TS U524 ( .A(Data_MY[19]), .B(n571), .S0(n3129), .Y(n331) );
NOR2X4TS U525 ( .A(n314), .B(n326), .Y(n3142) );
INVX2TS U526 ( .A(n1100), .Y(n3177) );
INVX4TS U527 ( .A(n2858), .Y(n4039) );
NOR2X4TS U528 ( .A(n2526), .B(n2525), .Y(n2915) );
CLKBUFX2TS U529 ( .A(Sgf_operation_EVEN1_Q_left[2]), .Y(n515) );
NAND2XLTS U530 ( .A(n661), .B(n604), .Y(add_x_19_n7) );
AO21X2TS U531 ( .A0(n576), .A1(n577), .B0(n578), .Y(n3253) );
NAND2X1TS U532 ( .A(n348), .B(n2865), .Y(n3150) );
NOR2X4TS U533 ( .A(n2098), .B(n3099), .Y(n1300) );
INVX1TS U534 ( .A(n3309), .Y(n972) );
NOR2X6TS U535 ( .A(n3031), .B(n3032), .Y(n3036) );
NOR2X6TS U536 ( .A(n3024), .B(n3026), .Y(n3007) );
CLKAND2X2TS U537 ( .A(n2996), .B(n2995), .Y(n664) );
NAND2X4TS U538 ( .A(n324), .B(n312), .Y(n3796) );
NOR2X4TS U539 ( .A(n701), .B(n1224), .Y(n1433) );
INVX2TS U540 ( .A(Data_MY[11]), .Y(n784) );
NOR2X4TS U541 ( .A(n2818), .B(n2811), .Y(n763) );
NOR2X6TS U542 ( .A(n2811), .B(n2819), .Y(n761) );
ADDFHX2TS U543 ( .A(n2433), .B(n2432), .CI(n2431), .CO(n2437), .S(n2709) );
NAND2X2TS U544 ( .A(n3512), .B(n2775), .Y(n3557) );
NAND2X2TS U545 ( .A(n3101), .B(n3102), .Y(n951) );
CLKBUFX2TS U546 ( .A(Sgf_operation_EVEN1_Q_left[3]), .Y(n1165) );
AND2X4TS U547 ( .A(n1918), .B(n701), .Y(n535) );
NAND2X4TS U548 ( .A(n981), .B(n3102), .Y(n948) );
INVX3TS U549 ( .A(n2812), .Y(n760) );
NOR3X1TS U550 ( .A(n236), .B(n237), .C(P_Sgf[0]), .Y(n3219) );
INVX3TS U551 ( .A(n3052), .Y(n3018) );
NAND2X4TS U552 ( .A(n1918), .B(n2366), .Y(n499) );
NAND2X1TS U553 ( .A(n2982), .B(n2981), .Y(n2983) );
NAND2X4TS U554 ( .A(n565), .B(n2163), .Y(n3027) );
NAND2X1TS U555 ( .A(n712), .B(n2977), .Y(n2978) );
BUFX2TS U556 ( .A(n2541), .Y(n838) );
AND2X6TS U557 ( .A(n1144), .B(n1885), .Y(n579) );
NAND2X4TS U558 ( .A(n2867), .B(n2866), .Y(n2868) );
AND2X6TS U559 ( .A(n1223), .B(n506), .Y(n428) );
NAND2X4TS U560 ( .A(n2701), .B(n2700), .Y(n2819) );
BUFX3TS U561 ( .A(n2549), .Y(n667) );
INVX2TS U562 ( .A(n2994), .Y(n2996) );
INVX2TS U563 ( .A(n2350), .Y(n2325) );
NAND2X6TS U564 ( .A(n2022), .B(n2021), .Y(n3102) );
NOR2X6TS U565 ( .A(n2022), .B(n2021), .Y(n3101) );
NAND2X6TS U566 ( .A(n1757), .B(n1756), .Y(mult_x_55_n72) );
INVX2TS U567 ( .A(Data_MX[5]), .Y(n1175) );
INVX12TS U568 ( .A(n2801), .Y(n1011) );
NOR2X4TS U569 ( .A(n3930), .B(n3193), .Y(n3512) );
BUFX3TS U570 ( .A(n2345), .Y(n1096) );
NOR2X6TS U571 ( .A(n565), .B(n2163), .Y(n3026) );
INVX6TS U572 ( .A(n1417), .Y(n503) );
CLKAND2X2TS U573 ( .A(n3314), .B(n882), .Y(n456) );
CLKINVX1TS U574 ( .A(n2225), .Y(n2971) );
AO21XLTS U575 ( .A0(n1601), .A1(n729), .B0(n459), .Y(n2374) );
NAND2X1TS U576 ( .A(n735), .B(n1063), .Y(n1062) );
NOR2X2TS U577 ( .A(n3900), .B(n3910), .Y(n3454) );
NAND2X2TS U578 ( .A(n2435), .B(n2436), .Y(n1249) );
INVX2TS U579 ( .A(round_mode[0]), .Y(n1287) );
ADDFHX2TS U580 ( .A(n2548), .B(n2547), .CI(n1463), .CO(n2597), .S(n2553) );
NAND2X4TS U581 ( .A(n1438), .B(n815), .Y(n1083) );
ADDFHX2TS U582 ( .A(n1592), .B(n1590), .CI(n1591), .CO(n1599), .S(n1639) );
ADDFHX2TS U583 ( .A(n1612), .B(n1611), .CI(n1610), .CO(n2439), .S(n2431) );
NAND2X1TS U584 ( .A(n1455), .B(n2225), .Y(n2226) );
NOR2X2TS U585 ( .A(n2318), .B(n2333), .Y(n2323) );
CLKINVX1TS U586 ( .A(n3340), .Y(n3299) );
NAND2X2TS U587 ( .A(n1311), .B(n1304), .Y(n1303) );
ADDFHX2TS U588 ( .A(n1617), .B(n1616), .CI(n1615), .CO(n2380), .S(n1623) );
NOR2X1TS U589 ( .A(n3340), .B(n588), .Y(n3313) );
NOR2X1TS U590 ( .A(n3340), .B(n622), .Y(n3319) );
NOR2X2TS U591 ( .A(n850), .B(n3580), .Y(n2791) );
INVX2TS U592 ( .A(n1308), .Y(n1304) );
NAND2X4TS U593 ( .A(n999), .B(n998), .Y(n1641) );
NAND2X2TS U594 ( .A(n2505), .B(n2504), .Y(n2922) );
INVX2TS U595 ( .A(n2353), .Y(n2327) );
OAI22X2TS U596 ( .A0(n853), .A1(n1773), .B0(n2842), .B1(n2789), .Y(n2790) );
OAI22X2TS U597 ( .A0(n1252), .A1(n1606), .B0(n865), .B1(n1603), .Y(n1612) );
AND2X6TS U598 ( .A(n2823), .B(n2821), .Y(n724) );
NAND2X4TS U599 ( .A(n2214), .B(n2213), .Y(n3448) );
INVX8TS U600 ( .A(n882), .Y(n444) );
INVX6TS U601 ( .A(n2368), .Y(n506) );
NOR2X2TS U602 ( .A(n1462), .B(n1447), .Y(n3278) );
OAI2BB1X2TS U603 ( .A0N(n736), .A1N(n1358), .B0(n3202), .Y(n3468) );
INVX8TS U604 ( .A(n1223), .Y(n2367) );
CLKINVX2TS U605 ( .A(n3456), .Y(n442) );
INVX2TS U606 ( .A(FSM_selector_C), .Y(n3226) );
INVX2TS U607 ( .A(Data_MY[0]), .Y(n758) );
NAND2X6TS U608 ( .A(n1137), .B(n2854), .Y(n1136) );
NAND2X2TS U609 ( .A(n986), .B(n2081), .Y(n923) );
NOR2BX1TS U610 ( .AN(Sgf_normalized_result[18]), .B(n3946), .Y(n1332) );
NOR2X4TS U611 ( .A(n1440), .B(n1843), .Y(n2223) );
NOR2X4TS U612 ( .A(n3339), .B(n620), .Y(n3322) );
NAND2X4TS U613 ( .A(n746), .B(n894), .Y(n757) );
CLKBUFX2TS U614 ( .A(n2955), .Y(n1074) );
XNOR2X1TS U615 ( .A(n2237), .B(n2254), .Y(n1472) );
NAND2X2TS U616 ( .A(n815), .B(n826), .Y(n1404) );
NAND2X2TS U617 ( .A(n2551), .B(n2550), .Y(n912) );
ADDFHX2TS U618 ( .A(n2430), .B(n2429), .CI(n2428), .CO(n2710), .S(n2434) );
OAI22X2TS U619 ( .A0(n1647), .A1(n858), .B0(n1633), .B1(n890), .Y(n1648) );
OAI21X2TS U620 ( .A0(n2350), .A1(n2349), .B0(n2348), .Y(n2351) );
NAND2X4TS U621 ( .A(n2678), .B(n2677), .Y(n2784) );
INVX6TS U622 ( .A(n2345), .Y(n2324) );
AND2X6TS U623 ( .A(n1428), .B(n2982), .Y(n717) );
OAI21X2TS U624 ( .A0(n943), .A1(n2389), .B0(n2388), .Y(n944) );
INVX4TS U625 ( .A(n1080), .Y(n2551) );
OAI2BB1X2TS U626 ( .A0N(n990), .A1N(n989), .B0(n2053), .Y(n988) );
CMPR32X2TS U627 ( .A(n2423), .B(n2422), .C(n2421), .CO(n2751), .S(n2417) );
OAI21X2TS U628 ( .A0(n2509), .A1(n2508), .B0(n1240), .Y(n1238) );
AO21X2TS U629 ( .A0(n2483), .A1(n2481), .B0(mult_x_23_n546), .Y(n2871) );
XNOR2X2TS U630 ( .A(n1570), .B(n686), .Y(n1579) );
OAI21X2TS U631 ( .A0(n2152), .A1(n2151), .B0(n692), .Y(n2157) );
OAI2BB1X2TS U632 ( .A0N(n1487), .A1N(n1023), .B0(n1021), .Y(n1760) );
INVX3TS U633 ( .A(n1414), .Y(n1412) );
XNOR2X2TS U634 ( .A(n1099), .B(n1077), .Y(n2122) );
XNOR2X2TS U635 ( .A(n2103), .B(n886), .Y(n2117) );
NAND2X4TS U636 ( .A(n1313), .B(n1312), .Y(n1311) );
NAND2X1TS U637 ( .A(n720), .B(n2158), .Y(n2159) );
NOR2X4TS U638 ( .A(n2211), .B(n2210), .Y(n3403) );
NAND2X4TS U639 ( .A(n1181), .B(n2859), .Y(n1182) );
INVX4TS U640 ( .A(n2939), .Y(n1137) );
INVX2TS U641 ( .A(n2012), .Y(n1173) );
NOR2X6TS U642 ( .A(n2212), .B(n1148), .Y(n3484) );
INVX2TS U643 ( .A(Data_MX[4]), .Y(n1177) );
OAI21X2TS U644 ( .A0(n2479), .A1(n1158), .B0(n960), .Y(n1675) );
NAND2XLTS U645 ( .A(n2146), .B(n2145), .Y(n2147) );
AOI21X2TS U646 ( .A0(n882), .A1(n2564), .B0(n2563), .Y(n979) );
NAND2X1TS U647 ( .A(n2336), .B(n2335), .Y(n2337) );
XNOR2X2TS U648 ( .A(n811), .B(Op_MY[16]), .Y(n1668) );
NOR2X6TS U649 ( .A(n567), .B(n2281), .Y(n2347) );
XNOR2X2TS U650 ( .A(n2409), .B(DP_OP_111J16_123_4462_n698), .Y(n1653) );
NAND2X2TS U651 ( .A(n2277), .B(n2349), .Y(n2282) );
NOR2X6TS U652 ( .A(n3339), .B(n588), .Y(n3314) );
CLKBUFX3TS U653 ( .A(n2071), .Y(n397) );
ADDFHX2TS U654 ( .A(n1985), .B(n1984), .CI(n1983), .CO(n2395), .S(n1989) );
OAI22X2TS U655 ( .A0(n2109), .A1(n856), .B0(n2110), .B1(n1302), .Y(n2120) );
NAND2BX2TS U656 ( .AN(n1368), .B(n2295), .Y(n2301) );
NAND2X2TS U657 ( .A(n2250), .B(n2280), .Y(n2266) );
BUFX3TS U658 ( .A(n2222), .Y(n815) );
NAND2X2TS U659 ( .A(n746), .B(n4049), .Y(n1178) );
NAND2X2TS U660 ( .A(n2336), .B(n2332), .Y(n2348) );
ADDFHX2TS U661 ( .A(n1767), .B(n1766), .CI(n1765), .CO(n1770), .S(n1758) );
NAND2XLTS U662 ( .A(n2142), .B(n2141), .Y(n2143) );
INVX6TS U663 ( .A(n2032), .Y(n2046) );
NAND2X1TS U664 ( .A(n2054), .B(n991), .Y(n987) );
NOR2X2TS U665 ( .A(n3214), .B(n3213), .Y(n3215) );
NAND2X1TS U666 ( .A(n1645), .B(n1002), .Y(n998) );
OAI22X2TS U667 ( .A0(n1581), .A1(n858), .B0(n1986), .B1(n890), .Y(n1990) );
NAND2X1TS U668 ( .A(n1158), .B(n3692), .Y(n960) );
BUFX6TS U669 ( .A(n1971), .Y(n402) );
CLKBUFX2TS U670 ( .A(n1056), .Y(n834) );
INVX2TS U671 ( .A(n1570), .Y(n2754) );
NAND2BX2TS U672 ( .AN(n2083), .B(n740), .Y(n1312) );
NOR2X4TS U673 ( .A(n2247), .B(n2263), .Y(n2270) );
CLKAND2X2TS U674 ( .A(mult_x_23_a_0_), .B(n2463), .Y(n1690) );
INVX2TS U675 ( .A(n828), .Y(n2145) );
INVX2TS U676 ( .A(n2332), .Y(n2335) );
AO21X1TS U677 ( .A0(n770), .A1(n893), .B0(n518), .Y(n1766) );
CLKINVX6TS U678 ( .A(n2317), .Y(n2320) );
NOR2X2TS U679 ( .A(n621), .B(n3340), .Y(n2563) );
NAND2XLTS U680 ( .A(n1452), .B(n3692), .Y(n1183) );
CLKINVX2TS U681 ( .A(n2422), .Y(n2415) );
OAI21X2TS U682 ( .A0(n1487), .A1(n1023), .B0(n1026), .Y(n1021) );
NOR2X6TS U683 ( .A(n2583), .B(n1089), .Y(n3394) );
CLKBUFX2TS U684 ( .A(n2140), .Y(n509) );
INVX4TS U685 ( .A(n2980), .Y(n2982) );
NAND2X2TS U686 ( .A(n2084), .B(n3893), .Y(n1313) );
ADDFHX2TS U687 ( .A(n1969), .B(n1968), .CI(n1967), .CO(n2724), .S(n2727) );
OAI22X2TS U688 ( .A0(n1986), .A1(n858), .B0(n2397), .B1(n890), .Y(n2404) );
OAI22X1TS U689 ( .A0(n1156), .A1(n1712), .B0(n1711), .B1(n835), .Y(n1716) );
NAND2X2TS U690 ( .A(n2285), .B(n2298), .Y(n2288) );
INVX1TS U691 ( .A(n1799), .Y(n1148) );
NOR2X6TS U692 ( .A(n2994), .B(n2992), .Y(n507) );
CLKXOR2X2TS U693 ( .A(n1565), .B(n1076), .Y(n1580) );
INVX4TS U694 ( .A(n2412), .Y(n2420) );
INVX2TS U695 ( .A(n2496), .Y(n1230) );
INVX2TS U696 ( .A(n1924), .Y(n837) );
NAND2X4TS U697 ( .A(n1887), .B(n1886), .Y(n2992) );
NOR2BX2TS U698 ( .AN(n848), .B(DP_OP_111J16_123_4462_n682), .Y(n2089) );
NAND2X4TS U699 ( .A(n3227), .B(n625), .Y(n3340) );
INVX4TS U700 ( .A(n993), .Y(n895) );
NOR2BX2TS U701 ( .AN(n1066), .B(n2110), .Y(n2029) );
INVX4TS U702 ( .A(n734), .Y(n890) );
BUFX3TS U703 ( .A(n1423), .Y(n1072) );
OAI2BB1X2TS U704 ( .A0N(DP_OP_111J16_123_4462_n680), .A1N(
DP_OP_111J16_123_4462_n713), .B0(DP_OP_111J16_123_4462_n699), .Y(n1644) );
NOR2X4TS U705 ( .A(n1887), .B(n1886), .Y(n2993) );
INVX4TS U706 ( .A(n2269), .Y(n2272) );
NAND2XLTS U707 ( .A(n831), .B(n2183), .Y(n2184) );
CLKINVX6TS U708 ( .A(n1596), .Y(n1645) );
OAI22X2TS U709 ( .A0(n2068), .A1(n2411), .B0(n857), .B1(n2085), .Y(n2088) );
NAND2X2TS U710 ( .A(n2007), .B(n2006), .Y(n3170) );
NAND2X4TS U711 ( .A(n1185), .B(n1184), .Y(n2054) );
NAND2X2TS U712 ( .A(n528), .B(n527), .Y(n2401) );
XOR2X2TS U713 ( .A(n1100), .B(n825), .Y(n1582) );
NAND2X1TS U714 ( .A(Sgf_normalized_result[10]), .B(Sgf_normalized_result[11]), .Y(n3397) );
NAND2XLTS U715 ( .A(n2173), .B(n800), .Y(n2174) );
XNOR2X2TS U716 ( .A(n3662), .B(n571), .Y(n1685) );
CLKINVX6TS U717 ( .A(n709), .Y(n858) );
CLKXOR2X2TS U718 ( .A(n1099), .B(n1076), .Y(n1988) );
XNOR2X2TS U719 ( .A(n4029), .B(mult_x_23_n545), .Y(n1708) );
CLKBUFX2TS U720 ( .A(n2408), .Y(n396) );
NAND2X6TS U721 ( .A(n2264), .B(n2263), .Y(n2313) );
NOR2X6TS U722 ( .A(n2317), .B(n2319), .Y(n2346) );
NOR2X2TS U723 ( .A(n850), .B(n468), .Y(n1762) );
NOR2X2TS U724 ( .A(n2292), .B(n2244), .Y(n2246) );
NAND2BX2TS U725 ( .AN(n932), .B(n813), .Y(n930) );
XNOR2X2TS U726 ( .A(n2103), .B(n1077), .Y(n2017) );
ADDFHX2TS U727 ( .A(n1530), .B(n1529), .CI(n1528), .CO(n1547), .S(n1531) );
ADDFHX2TS U728 ( .A(n2689), .B(n2690), .CI(n2688), .CO(n2695), .S(n2697) );
NAND2X2TS U729 ( .A(n2196), .B(n513), .Y(n2197) );
OAI22X2TS U730 ( .A0(n1517), .A1(n1020), .B0(n891), .B1(n1186), .Y(n1969) );
NAND2X4TS U731 ( .A(n1889), .B(n1888), .Y(n2995) );
OAI21X2TS U732 ( .A0(n1079), .A1(n2198), .B0(n513), .Y(n2203) );
XOR2X2TS U733 ( .A(n2412), .B(n1076), .Y(n2396) );
NOR2X2TS U734 ( .A(n1034), .B(n501), .Y(n1904) );
NAND2X4TS U735 ( .A(n2637), .B(n2636), .Y(n2836) );
AOI2BB1X2TS U736 ( .A0N(n1913), .A1N(n1891), .B0(n1890), .Y(n1892) );
XOR2X2TS U737 ( .A(n1565), .B(n1077), .Y(n426) );
AND2X6TS U738 ( .A(n2247), .B(n568), .Y(n567) );
XNOR2X2TS U739 ( .A(n1147), .B(n3664), .Y(n2387) );
INVX2TS U740 ( .A(n2186), .Y(n1347) );
BUFX3TS U741 ( .A(n1166), .Y(n1079) );
INVX2TS U742 ( .A(n570), .Y(n1938) );
INVX6TS U743 ( .A(n1085), .Y(n2181) );
OR2X1TS U744 ( .A(n1823), .B(n1824), .Y(n831) );
INVX2TS U745 ( .A(n1565), .Y(n2398) );
OR2X2TS U746 ( .A(n3887), .B(DP_OP_111J16_123_4462_n707), .Y(n1184) );
OR2X2TS U747 ( .A(n3889), .B(DP_OP_111J16_123_4462_n707), .Y(n1003) );
NOR2X1TS U748 ( .A(n2177), .B(n2178), .Y(n2180) );
INVX6TS U749 ( .A(n2977), .Y(n2964) );
NAND2X4TS U750 ( .A(n973), .B(n3787), .Y(n2562) );
INVX4TS U751 ( .A(Op_MY[16]), .Y(n1617) );
NOR2BX2TS U752 ( .AN(n848), .B(DP_OP_111J16_123_4462_n707), .Y(n2059) );
CLKINVX6TS U753 ( .A(n2247), .Y(n2264) );
XNOR2X2TS U754 ( .A(n1090), .B(n1077), .Y(n2030) );
NOR2BX1TS U755 ( .AN(n868), .B(n729), .Y(n2467) );
BUFX16TS U756 ( .A(mult_x_23_n533), .Y(n883) );
XNOR2X2TS U757 ( .A(n1168), .B(n894), .Y(n1928) );
INVX2TS U758 ( .A(n2198), .Y(n2196) );
NAND2X4TS U759 ( .A(n1454), .B(n1345), .Y(n2269) );
INVX2TS U760 ( .A(n2165), .Y(n2168) );
INVX2TS U761 ( .A(n3837), .Y(n1071) );
INVX12TS U762 ( .A(n2837), .Y(n541) );
NAND2X1TS U763 ( .A(n1035), .B(n3824), .Y(n1034) );
AND4X6TS U764 ( .A(n712), .B(n1191), .C(n1459), .D(n1428), .Y(n718) );
NOR2X2TS U765 ( .A(n850), .B(mult_x_55_n444), .Y(n1763) );
NOR2X6TS U766 ( .A(n2259), .B(n2258), .Y(n2299) );
BUFX6TS U767 ( .A(n1566), .Y(n859) );
OAI22X1TS U768 ( .A0(n1476), .A1(n3660), .B0(n863), .B1(n2651), .Y(n2668) );
OR2X4TS U769 ( .A(n2242), .B(n553), .Y(n1369) );
ADDFHX2TS U770 ( .A(n1521), .B(n1520), .CI(n1519), .CO(n1968), .S(n1921) );
OAI22X2TS U771 ( .A0(n847), .A1(n519), .B0(mult_x_55_n554), .B1(n1540), .Y(
n1550) );
NAND2X2TS U772 ( .A(n1295), .B(n1293), .Y(n1292) );
INVX8TS U773 ( .A(n400), .Y(n2014) );
CMPR22X2TS U774 ( .A(n2456), .B(n2455), .CO(n2457), .S(n2451) );
XNOR2X1TS U775 ( .A(n516), .B(n868), .Y(n2461) );
INVX6TS U776 ( .A(n851), .Y(n853) );
MX2X2TS U777 ( .A(n3907), .B(n3897), .S0(n569), .Y(n568) );
CLKINVX12TS U778 ( .A(n2408), .Y(n1076) );
INVX3TS U779 ( .A(n1948), .Y(n1195) );
INVX6TS U780 ( .A(n709), .Y(n857) );
INVX8TS U781 ( .A(n886), .Y(n470) );
INVX6TS U782 ( .A(n715), .Y(n891) );
NOR2BX2TS U783 ( .AN(n894), .B(n850), .Y(n1521) );
INVX2TS U784 ( .A(n1453), .Y(n1910) );
INVX6TS U785 ( .A(n864), .Y(n865) );
INVX2TS U786 ( .A(n1903), .Y(n1426) );
NOR2X2TS U787 ( .A(mult_x_55_n559), .B(mult_x_55_n446), .Y(n1482) );
INVX12TS U788 ( .A(n2753), .Y(n861) );
CLKINVX2TS U789 ( .A(n2636), .Y(n539) );
NAND2X4TS U790 ( .A(n1882), .B(n1883), .Y(n2965) );
BUFX16TS U791 ( .A(n1244), .Y(n1020) );
INVX2TS U792 ( .A(DP_OP_111J16_123_4462_n682), .Y(n993) );
NOR2BX2TS U793 ( .AN(n868), .B(mult_x_23_n540), .Y(n2512) );
INVX6TS U794 ( .A(n2259), .Y(n2241) );
NOR2BX2TS U795 ( .AN(n868), .B(n889), .Y(n2495) );
XOR2X2TS U796 ( .A(n2463), .B(n3706), .Y(n1712) );
OR3X1TS U797 ( .A(n1913), .B(n587), .C(n1908), .Y(n484) );
NAND2X4TS U798 ( .A(n1465), .B(n3076), .Y(n3188) );
NOR2X4TS U799 ( .A(n3788), .B(n3789), .Y(n973) );
NOR2X6TS U800 ( .A(n458), .B(n457), .Y(n1098) );
XNOR2X2TS U801 ( .A(n3573), .B(mult_x_55_n529), .Y(n1483) );
NAND2X6TS U802 ( .A(n1899), .B(n790), .Y(n792) );
CLKINVX6TS U803 ( .A(Op_MY[11]), .Y(n782) );
NOR2X2TS U804 ( .A(mult_x_55_n559), .B(mult_x_55_n448), .Y(n1507) );
INVX4TS U805 ( .A(n1413), .Y(n1864) );
XNOR2X2TS U806 ( .A(n3574), .B(mult_x_55_n530), .Y(n1496) );
OR2X4TS U807 ( .A(n1066), .B(n3890), .Y(n704) );
NAND2BX2TS U808 ( .AN(FSM_selector_B[1]), .B(Op_MY[28]), .Y(n1345) );
ADDHX2TS U809 ( .A(n2608), .B(n2607), .CO(n2675), .S(n2609) );
XNOR2X2TS U810 ( .A(n1450), .B(n2459), .Y(n2484) );
NOR2BX1TS U811 ( .AN(n868), .B(n705), .Y(n2446) );
NAND3X2TS U812 ( .A(n1033), .B(n2981), .C(n2980), .Y(n1191) );
XOR2X2TS U813 ( .A(n1901), .B(n2961), .Y(n479) );
XOR2X2TS U814 ( .A(n2474), .B(mult_x_23_n524), .Y(n2460) );
NAND2X2TS U815 ( .A(n1901), .B(n1900), .Y(n1086) );
AND2X6TS U816 ( .A(DP_OP_111J16_123_4462_n616), .B(
DP_OP_111J16_123_4462_n682), .Y(n2753) );
OR2X6TS U817 ( .A(n1867), .B(n1868), .Y(n1428) );
NAND2X4TS U818 ( .A(n1033), .B(n2981), .Y(n1192) );
CLKINVX6TS U819 ( .A(n686), .Y(n1093) );
NAND2X6TS U820 ( .A(n1454), .B(n2235), .Y(n2259) );
INVX2TS U821 ( .A(n3895), .Y(n1171) );
BUFX4TS U822 ( .A(n811), .Y(n1147) );
NOR2X6TS U823 ( .A(n1883), .B(n1882), .Y(n1396) );
INVX4TS U824 ( .A(n3613), .Y(n2842) );
INVX4TS U825 ( .A(n888), .Y(n889) );
INVX12TS U826 ( .A(n526), .Y(n2108) );
BUFX3TS U827 ( .A(n1995), .Y(n905) );
INVX4TS U828 ( .A(n851), .Y(n852) );
NOR2BX2TS U829 ( .AN(n894), .B(mult_x_55_n555), .Y(n2667) );
NAND2XLTS U830 ( .A(n1453), .B(n489), .Y(n488) );
BUFX3TS U831 ( .A(n3652), .Y(n468) );
INVX2TS U832 ( .A(n1294), .Y(n1293) );
INVX12TS U833 ( .A(DP_OP_111J16_123_4462_n695), .Y(n1006) );
XOR2X2TS U834 ( .A(n455), .B(n2463), .Y(n2450) );
NAND2BX2TS U835 ( .AN(Op_MY[12]), .B(n3695), .Y(n2448) );
XOR2X2TS U836 ( .A(n2474), .B(n3667), .Y(n2452) );
NAND2X4TS U837 ( .A(n3837), .B(DP_OP_111J16_123_4462_n607), .Y(n495) );
NOR2X2TS U838 ( .A(n893), .B(mult_x_55_n480), .Y(n457) );
INVX8TS U839 ( .A(n1495), .Y(n1511) );
NAND2BX2TS U840 ( .AN(n848), .B(DP_OP_111J16_123_4462_n699), .Y(n1994) );
NOR2X1TS U841 ( .A(n863), .B(n1461), .Y(n2633) );
INVX6TS U842 ( .A(n892), .Y(n893) );
NAND2X6TS U843 ( .A(n1865), .B(n1866), .Y(n2981) );
NOR2X1TS U844 ( .A(n1908), .B(n614), .Y(n491) );
INVX2TS U845 ( .A(n3717), .Y(n2459) );
NAND2X4TS U846 ( .A(n808), .B(n1863), .Y(n2972) );
NAND2X2TS U847 ( .A(n2445), .B(n867), .Y(n1140) );
CLKINVX1TS U848 ( .A(n614), .Y(n489) );
CLKINVX6TS U849 ( .A(n1900), .Y(n1088) );
BUFX12TS U850 ( .A(n1450), .Y(n459) );
CLKXOR2X4TS U851 ( .A(n817), .B(n811), .Y(n1253) );
CLKINVX3TS U852 ( .A(n1901), .Y(n1087) );
NAND2BX2TS U853 ( .AN(n2008), .B(n1309), .Y(n1296) );
CLKXOR2X2TS U854 ( .A(n1077), .B(n848), .Y(n1993) );
NAND2X2TS U855 ( .A(DP_OP_111J16_123_4462_n821), .B(
DP_OP_111J16_123_4462_n749), .Y(n1575) );
INVX6TS U856 ( .A(n679), .Y(n1875) );
CLKINVX6TS U857 ( .A(n1493), .Y(n2645) );
INVX4TS U858 ( .A(n2960), .Y(n1878) );
CLKINVX3TS U859 ( .A(n1156), .Y(n2445) );
INVX2TS U860 ( .A(n2215), .Y(n1879) );
INVX6TS U861 ( .A(n862), .Y(n863) );
INVX4TS U862 ( .A(n3885), .Y(n983) );
INVX6TS U863 ( .A(n1309), .Y(n866) );
OA22X2TS U864 ( .A0(n1161), .A1(n2627), .B0(n2628), .B1(n2659), .Y(n2629) );
BUFX8TS U865 ( .A(n3662), .Y(n516) );
NAND2X6TS U866 ( .A(n2761), .B(n2762), .Y(n1376) );
INVX12TS U867 ( .A(n1298), .Y(n884) );
NOR2BX2TS U868 ( .AN(n1896), .B(n1243), .Y(n1242) );
ADDFHX2TS U869 ( .A(n1799), .B(n1798), .CI(n1797), .CO(n806) );
OA21X1TS U870 ( .A0(n1913), .A1(n1219), .B0(n1218), .Y(n722) );
INVX8TS U871 ( .A(mult_x_23_n549), .Y(n2463) );
CLKINVX12TS U872 ( .A(n3696), .Y(n2485) );
NOR2X2TS U873 ( .A(n1160), .B(n592), .Y(n1243) );
CLKINVX2TS U874 ( .A(n1908), .Y(n1419) );
INVX2TS U875 ( .A(n695), .Y(n1309) );
NAND2X4TS U876 ( .A(n1038), .B(n1037), .Y(n1453) );
INVX12TS U877 ( .A(n918), .Y(n885) );
INVX3TS U878 ( .A(n2106), .Y(n1298) );
NOR2X2TS U879 ( .A(n691), .B(n675), .Y(n483) );
NAND2X4TS U880 ( .A(n1407), .B(n1109), .Y(n1107) );
AND2X6TS U881 ( .A(n485), .B(n1278), .Y(n486) );
INVX2TS U882 ( .A(n3854), .Y(n1037) );
INVX6TS U883 ( .A(n1291), .Y(n2106) );
NAND2X6TS U884 ( .A(n596), .B(n628), .Y(n1908) );
INVX2TS U885 ( .A(n816), .Y(n564) );
AND2X4TS U886 ( .A(n3712), .B(n613), .Y(n1109) );
INVX1TS U887 ( .A(n1850), .Y(n1114) );
INVX2TS U888 ( .A(n2206), .Y(n1857) );
CLKXOR2X4TS U889 ( .A(n1133), .B(n3588), .Y(n1852) );
XNOR2X2TS U890 ( .A(n1053), .B(n3598), .Y(n2204) );
XNOR2X2TS U891 ( .A(n672), .B(n894), .Y(n2619) );
NOR2X1TS U892 ( .A(n1895), .B(n591), .Y(n1784) );
NOR2X1TS U893 ( .A(n1895), .B(n608), .Y(n1871) );
INVX2TS U894 ( .A(n3587), .Y(n1043) );
AOI21X2TS U895 ( .A0(n1853), .A1(n626), .B0(n603), .Y(n1854) );
BUFX8TS U896 ( .A(mult_x_55_n583), .Y(n2659) );
NOR2BX2TS U897 ( .AN(n628), .B(n595), .Y(n1278) );
XOR2X2TS U898 ( .A(n2653), .B(mult_x_55_n537), .Y(n2627) );
BUFX8TS U899 ( .A(n2661), .Y(n462) );
OR2X6TS U900 ( .A(n1842), .B(n1841), .Y(n720) );
INVX6TS U901 ( .A(n671), .Y(n2653) );
INVX4TS U902 ( .A(n671), .Y(n672) );
AOI21X2TS U903 ( .A0(n631), .A1(n3703), .B0(n3704), .Y(n1783) );
CLKXOR2X2TS U904 ( .A(n1053), .B(n3598), .Y(n820) );
NAND2X6TS U905 ( .A(n754), .B(n537), .Y(n466) );
NOR2X4TS U906 ( .A(DP_OP_111J16_123_4462_n117), .B(n424), .Y(n492) );
INVX2TS U907 ( .A(n1919), .Y(n1841) );
NOR2X4TS U908 ( .A(n1059), .B(n2989), .Y(n1336) );
INVX12TS U909 ( .A(n1070), .Y(n1160) );
INVX6TS U910 ( .A(n1895), .Y(n1408) );
NAND2X2TS U911 ( .A(n1456), .B(n644), .Y(n1119) );
NOR2X6TS U912 ( .A(n677), .B(n1848), .Y(n777) );
INVX2TS U913 ( .A(n3689), .Y(n584) );
CLKINVX6TS U914 ( .A(n612), .Y(n453) );
INVX4TS U915 ( .A(n2194), .Y(n1848) );
NAND2X6TS U916 ( .A(n2989), .B(n1059), .Y(n1335) );
NOR2X6TS U917 ( .A(n1817), .B(n1818), .Y(n2165) );
NAND2X6TS U918 ( .A(n1822), .B(n1821), .Y(n800) );
INVX12TS U919 ( .A(n1846), .Y(n1059) );
NAND2X6TS U920 ( .A(n1806), .B(n1807), .Y(n747) );
INVX4TS U921 ( .A(n2141), .Y(n1836) );
NAND2X2TS U922 ( .A(n694), .B(n1402), .Y(n1122) );
CLKINVX6TS U923 ( .A(n1835), .Y(n749) );
NOR2X4TS U924 ( .A(n1832), .B(n1833), .Y(n2140) );
NAND2X6TS U925 ( .A(n1834), .B(n827), .Y(n2141) );
OR2X4TS U926 ( .A(n1803), .B(Sgf_operation_EVEN1_Q_middle[1]), .Y(n1806) );
INVX6TS U927 ( .A(Sgf_operation_EVEN1_Q_left[0]), .Y(n2192) );
INVX8TS U928 ( .A(Sgf_operation_EVEN1_Q_left[9]), .Y(n1828) );
INVX8TS U929 ( .A(Sgf_operation_Result[6]), .Y(n1816) );
INVX8TS U930 ( .A(Sgf_operation_EVEN1_Q_left[7]), .Y(n1826) );
NAND2X6TS U931 ( .A(n762), .B(n759), .Y(n1008) );
ADDFHX2TS U932 ( .A(n2666), .B(n2667), .CI(n2665), .CO(n2672), .S(n2674) );
INVX16TS U933 ( .A(n1067), .Y(n848) );
OAI21X4TS U934 ( .A0(n986), .A1(n2081), .B0(n2080), .Y(n924) );
OAI22X4TS U935 ( .A0(n744), .A1(n518), .B0(n893), .B1(n2657), .Y(n2664) );
INVX12TS U936 ( .A(n764), .Y(n770) );
OAI22X4TS U937 ( .A0(n853), .A1(n1541), .B0(n2842), .B1(n1477), .Y(n1485) );
ADDFHX4TS U938 ( .A(n1486), .B(n1485), .CI(n1484), .CO(n1562), .S(n1551) );
XOR2X4TS U939 ( .A(n2925), .B(n2924), .Y(Sgf_operation_EVEN1_left_N7) );
XOR2X4TS U940 ( .A(mult_x_23_n554), .B(n358), .Y(n3561) );
NAND2X4TS U941 ( .A(n1373), .B(n2903), .Y(mult_x_23_n121) );
INVX4TS U942 ( .A(n2615), .Y(n2631) );
AND2X8TS U943 ( .A(n2923), .B(n2936), .Y(n726) );
NAND3X4TS U944 ( .A(n1029), .B(n3078), .C(n1028), .Y(
DP_OP_111J16_123_4462_n161) );
XNOR2X4TS U945 ( .A(n3255), .B(n3762), .Y(n3256) );
OAI21X4TS U946 ( .A0(n3378), .A1(n3765), .B0(n629), .Y(n3255) );
NOR2X8TS U947 ( .A(n3499), .B(n1443), .Y(n2584) );
NOR2X4TS U948 ( .A(n1152), .B(n2906), .Y(mult_x_23_n120) );
XOR2X4TS U949 ( .A(n3151), .B(n1259), .Y(n3849) );
NAND2X2TS U950 ( .A(mult_x_23_n7), .B(mult_x_23_n49), .Y(mult_x_23_n47) );
NAND2X2TS U951 ( .A(mult_x_23_n7), .B(mult_x_23_n38), .Y(mult_x_23_n36) );
XNOR2X4TS U952 ( .A(n2937), .B(n1234), .Y(Sgf_operation_EVEN1_left_N6) );
NAND2X4TS U953 ( .A(n3006), .B(n1393), .Y(add_x_19_n15) );
OAI21X2TS U954 ( .A0(n3372), .A1(n3344), .B0(n3343), .Y(n3345) );
AOI21X4TS U955 ( .A0(n3376), .A1(n3342), .B0(n3341), .Y(n3343) );
XNOR2X2TS U956 ( .A(n3183), .B(n3149), .Y(n3151) );
OAI21X4TS U957 ( .A0(n3372), .A1(n3371), .B0(n3370), .Y(n3373) );
INVX6TS U958 ( .A(n3369), .Y(n3370) );
NOR2X4TS U959 ( .A(n3340), .B(n617), .Y(n3341) );
INVX4TS U960 ( .A(n3101), .Y(n3103) );
NOR2X6TS U961 ( .A(n2320), .B(n2319), .Y(n2333) );
NAND2X8TS U962 ( .A(n2894), .B(n2893), .Y(n2929) );
ADDFHX2TS U963 ( .A(n2376), .B(n2375), .CI(n2374), .CO(n2384), .S(n2373) );
AOI21X4TS U964 ( .A0(n3396), .A1(n3395), .B0(n732), .Y(n378) );
NAND3X2TS U965 ( .A(n3252), .B(n3251), .C(n3250), .Y(n195) );
NAND2X4TS U966 ( .A(n1073), .B(n3071), .Y(DP_OP_111J16_123_4462_n9) );
NAND2BX2TS U967 ( .AN(n2443), .B(mult_x_23_a_0_), .Y(n1141) );
NAND2X4TS U968 ( .A(n2241), .B(n2258), .Y(n2291) );
NOR2X2TS U969 ( .A(mult_x_23_n94), .B(n2912), .Y(mult_x_23_n87) );
NAND2X4TS U970 ( .A(n3015), .B(n2232), .Y(n3008) );
XNOR2X4TS U971 ( .A(n3294), .B(n3758), .Y(n3295) );
NAND2X4TS U972 ( .A(n2777), .B(n2776), .Y(mult_x_55_n12) );
INVX4TS U973 ( .A(n2030), .Y(n2031) );
OAI22X2TS U974 ( .A0(n2017), .A1(DP_OP_111J16_123_4462_n680), .B0(n2030),
.B1(n846), .Y(n1464) );
NOR2X8TS U975 ( .A(n2914), .B(n2934), .Y(mult_x_23_n38) );
NAND2X8TS U976 ( .A(n3736), .B(n2932), .Y(n2914) );
NAND2X6TS U977 ( .A(n1317), .B(n1233), .Y(n1157) );
XNOR2X4TS U978 ( .A(n3281), .B(n3756), .Y(n3282) );
CLKINVX3TS U979 ( .A(n3339), .Y(n3300) );
NOR2X8TS U980 ( .A(n3339), .B(n617), .Y(n3342) );
NAND2X8TS U981 ( .A(n1031), .B(n1030), .Y(n3079) );
AOI21X2TS U982 ( .A0(n882), .A1(n3233), .B0(n3232), .Y(n3234) );
INVX16TS U983 ( .A(n1206), .Y(n882) );
NOR2X4TS U984 ( .A(n2507), .B(n2915), .Y(n1316) );
MXI2X4TS U985 ( .A(n4044), .B(n3902), .S0(n569), .Y(n2336) );
MXI2X4TS U986 ( .A(n3995), .B(n3903), .S0(n569), .Y(n2319) );
NAND2X4TS U987 ( .A(n2900), .B(n2899), .Y(mult_x_23_n16) );
OAI22X1TS U988 ( .A0(mult_x_23_n533), .A1(n3665), .B0(n3668), .B1(
mult_x_23_n517), .Y(n2869) );
OAI21X4TS U989 ( .A0(n2327), .A1(n2346), .B0(n2349), .Y(n2328) );
XNOR2X4TS U990 ( .A(n2463), .B(mult_x_23_n521), .Y(n2489) );
INVX6TS U991 ( .A(n3021), .Y(n3045) );
NOR2X8TS U992 ( .A(n3022), .B(n3021), .Y(add_x_19_n215) );
BUFX8TS U993 ( .A(n3663), .Y(n1158) );
NAND2X4TS U994 ( .A(n2898), .B(n2897), .Y(mult_x_23_n18) );
ADDFHX4TS U995 ( .A(n2892), .B(n2891), .CI(n2890), .CO(n2876), .S(n2893) );
BUFX20TS U996 ( .A(FSM_selector_A), .Y(n569) );
OAI21X4TS U997 ( .A0(n3163), .A1(n3796), .B0(n3164), .Y(n3127) );
OR2X4TS U998 ( .A(n2706), .B(n2707), .Y(n689) );
NOR2X8TS U999 ( .A(n2991), .B(n1101), .Y(n3005) );
NOR2X4TS U1000 ( .A(n2346), .B(n2350), .Y(n2352) );
INVX12TS U1001 ( .A(n2468), .Y(n2854) );
NOR2X4TS U1002 ( .A(n1510), .B(n744), .Y(n458) );
INVX8TS U1003 ( .A(DP_OP_111J16_123_4462_n71), .Y(n3087) );
ADDFHX4TS U1004 ( .A(n2381), .B(n2380), .CI(n2379), .CO(n2382), .S(n2372) );
AOI21X4TS U1005 ( .A0(n882), .A1(n609), .B0(n3754), .Y(n3377) );
CLKINVX12TS U1006 ( .A(DP_OP_111J16_123_4462_n72), .Y(n439) );
AOI21X2TS U1007 ( .A0(n3016), .A1(n2232), .B0(n2231), .Y(n2233) );
INVX4TS U1008 ( .A(n3016), .Y(n3023) );
NOR2X8TS U1009 ( .A(n1979), .B(n404), .Y(mult_x_55_n115) );
XNOR2X4TS U1010 ( .A(n3307), .B(n3752), .Y(n3308) );
OAI21X4TS U1011 ( .A0(n3372), .A1(n3306), .B0(n3305), .Y(n3307) );
INVX4TS U1012 ( .A(mult_x_23_n99), .Y(mult_x_23_n101) );
NAND3X4TS U1013 ( .A(n983), .B(n431), .C(n522), .Y(n521) );
CLKINVX6TS U1014 ( .A(n983), .Y(n524) );
OAI22X2TS U1015 ( .A0(n1988), .A1(n860), .B0(n2396), .B1(n895), .Y(n2402) );
OAI22X2TS U1016 ( .A0(n1988), .A1(n895), .B0(n1580), .B1(n861), .Y(n1991) );
XOR2X4TS U1017 ( .A(n346), .B(n358), .Y(n3152) );
OAI22X2TS U1018 ( .A0(n1601), .A1(n1709), .B0(n729), .B1(n1685), .Y(n1714)
);
OAI22X2TS U1019 ( .A0(n1601), .A1(n516), .B0(n729), .B1(n459), .Y(n1615) );
NOR2X8TS U1020 ( .A(add_x_19_n201), .B(n3005), .Y(n2984) );
NAND2X6TS U1021 ( .A(n1162), .B(n1258), .Y(n1373) );
AOI2BB2X2TS U1022 ( .B0(n252), .B1(n3384), .A0N(n900), .A1N(n3920), .Y(n3386) );
NAND2X8TS U1023 ( .A(n2783), .B(n2773), .Y(mult_x_55_n58) );
NOR2X8TS U1024 ( .A(n3339), .B(n622), .Y(n3320) );
NAND2X4TS U1025 ( .A(mult_x_23_n190), .B(n2895), .Y(mult_x_23_n17) );
ADDFHX4TS U1026 ( .A(n1923), .B(n1922), .CI(n1921), .CO(n1973), .S(n1978) );
OAI22X4TS U1027 ( .A0(n2490), .A1(n1711), .B0(n835), .B1(n2453), .Y(n1715)
);
NAND2X4TS U1028 ( .A(DP_OP_111J16_123_4462_n220), .B(n497), .Y(
DP_OP_111J16_123_4462_n14) );
INVX12TS U1029 ( .A(n2815), .Y(n2817) );
XNOR2X4TS U1030 ( .A(n3345), .B(n3748), .Y(n3346) );
XOR2X4TS U1031 ( .A(n3488), .B(n3487), .Y(n3489) );
XOR2X4TS U1032 ( .A(n2835), .B(n2834), .Y(Sgf_operation_EVEN1_right_N5) );
BUFX20TS U1033 ( .A(n2483), .Y(n942) );
XNOR2X2TS U1034 ( .A(n3661), .B(Op_MY[12]), .Y(n2482) );
ADDFHX4TS U1035 ( .A(n1600), .B(n1599), .CI(n1598), .CO(n1981), .S(n1658) );
ADDFHX4TS U1036 ( .A(n1629), .B(n1628), .CI(n1627), .CO(n1598), .S(n1663) );
NOR2X2TS U1037 ( .A(n850), .B(mult_x_55_n445), .Y(n1481) );
OAI22X4TS U1038 ( .A0(n1701), .A1(n1252), .B0(n865), .B1(mult_x_23_n461),
.Y(n1721) );
XOR2X4TS U1039 ( .A(n3450), .B(n3426), .Y(n3427) );
OAI22X2TS U1040 ( .A0(n2483), .A1(n1702), .B0(n889), .B1(mult_x_23_n470),
.Y(n1698) );
ADDFHX4TS U1041 ( .A(n1609), .B(n1608), .CI(n1607), .CO(n1622), .S(n2432) );
XOR2X4TS U1042 ( .A(n1511), .B(mult_x_55_n270), .Y(n799) );
OAI21X2TS U1043 ( .A0(n3017), .A1(add_x_19_n271), .B0(n1403), .Y(
add_x_19_n221) );
OAI22X2TS U1044 ( .A0(n1577), .A1(n860), .B0(n1580), .B1(n895), .Y(n1589) );
ADDFHX4TS U1045 ( .A(n1690), .B(n1689), .CI(n1688), .CO(n1693), .S(n1748) );
OAI22X4TS U1046 ( .A0(n2483), .A1(mult_x_23_n470), .B0(n2481), .B1(n1666),
.Y(n1689) );
NOR2X8TS U1047 ( .A(n3339), .B(n621), .Y(n2564) );
NAND2X8TS U1048 ( .A(n1128), .B(n1126), .Y(n1125) );
INVX4TS U1049 ( .A(n2904), .Y(n2900) );
INVX4TS U1050 ( .A(n1585), .Y(n1591) );
ADDFHX2TS U1051 ( .A(n3666), .B(n571), .CI(n2869), .CO(n2892), .S(n2872) );
OAI22X2TS U1052 ( .A0(n883), .A1(n3666), .B0(n3668), .B1(n571), .Y(n2378) );
XNOR2X4TS U1053 ( .A(n2453), .B(n3666), .Y(n2488) );
ADDFHX4TS U1054 ( .A(n2889), .B(n2888), .CI(n2887), .CO(n2894), .S(n2391) );
ADDFHX4TS U1055 ( .A(n2872), .B(n2871), .CI(n2870), .CO(n2890), .S(n2888) );
NAND3X6TS U1056 ( .A(n3079), .B(n1027), .C(n3095), .Y(n1029) );
XNOR2X4TS U1057 ( .A(n571), .B(n1158), .Y(n1719) );
XNOR2X4TS U1058 ( .A(n2785), .B(n927), .Y(Sgf_operation_EVEN1_right_N7) );
OAI22X2TS U1059 ( .A0(n2479), .A1(n2476), .B0(n2477), .B1(n1723), .Y(n2510)
);
XNOR2X4TS U1060 ( .A(n2474), .B(n3675), .Y(n2476) );
XNOR2X4TS U1061 ( .A(n3286), .B(n3757), .Y(n3287) );
OAI21X2TS U1062 ( .A0(n3378), .A1(n3285), .B0(n3284), .Y(n3286) );
ADDFHX4TS U1063 ( .A(n1586), .B(n1584), .CI(n1585), .CO(n1983), .S(n1588) );
NAND2X2TS U1064 ( .A(n2779), .B(n2778), .Y(mult_x_55_n18) );
INVX4TS U1065 ( .A(n3046), .Y(n3048) );
INVX4TS U1066 ( .A(n3013), .Y(add_x_19_n186) );
OAI21X2TS U1067 ( .A0(n3010), .A1(n3013), .B0(n3009), .Y(add_x_19_n179) );
ADDFHX2TS U1068 ( .A(n1744), .B(n1743), .CI(n1742), .CO(n1691), .S(n2747) );
OAI22X4TS U1069 ( .A0(n1666), .A1(n2483), .B0(n889), .B1(n1019), .Y(n1673)
);
XNOR2X4TS U1070 ( .A(n3661), .B(n3665), .Y(n1605) );
INVX16TS U1071 ( .A(n392), .Y(n916) );
INVX3TS U1072 ( .A(n463), .Y(DP_OP_111J16_123_4462_n140) );
NAND2X8TS U1073 ( .A(n666), .B(n1103), .Y(DP_OP_111J16_123_4462_n48) );
NAND2X8TS U1074 ( .A(n439), .B(n665), .Y(n666) );
ADDFHX4TS U1075 ( .A(n1991), .B(n1990), .CI(n1989), .CO(n2393), .S(n1980) );
INVX8TS U1076 ( .A(n2757), .Y(n665) );
INVX4TS U1077 ( .A(add_x_19_n124), .Y(n1917) );
AOI21X2TS U1078 ( .A0(add_x_19_n243), .A1(n3052), .B0(n3051), .Y(n1040) );
AOI21X2TS U1079 ( .A0(n3015), .A1(add_x_19_n243), .B0(n3016), .Y(n1403) );
INVX4TS U1080 ( .A(n2227), .Y(n1042) );
INVX8TS U1081 ( .A(n771), .Y(n756) );
NAND2X4TS U1082 ( .A(n2833), .B(n2832), .Y(n2834) );
ADDFHX2TS U1083 ( .A(n2386), .B(n3739), .CI(n2385), .CO(n2889), .S(n2388) );
NAND2X6TS U1084 ( .A(n2424), .B(n2425), .Y(n3071) );
NAND2X4TS U1085 ( .A(n2149), .B(n2148), .Y(n3033) );
NOR2X8TS U1086 ( .A(n2148), .B(n2149), .Y(n3032) );
NAND2X4TS U1087 ( .A(n538), .B(n3003), .Y(add_x_19_n9) );
OAI22X2TS U1088 ( .A0(n1654), .A1(n859), .B0(n1636), .B1(n897), .Y(n2570) );
OAI22X2TS U1089 ( .A0(n2490), .A1(n1734), .B0(n1712), .B1(n835), .Y(n1720)
);
XNOR2X4TS U1090 ( .A(n2453), .B(n3665), .Y(n1734) );
BUFX20TS U1091 ( .A(n2409), .Y(n1100) );
NOR2X2TS U1092 ( .A(DP_OP_111J16_123_4462_n158), .B(n3097), .Y(
DP_OP_111J16_123_4462_n149) );
NAND2X2TS U1093 ( .A(n1067), .B(n887), .Y(n1068) );
OAI22X4TS U1094 ( .A0(n1708), .A1(n865), .B0(mult_x_23_n461), .B1(n1252),
.Y(n1718) );
XNOR2X4TS U1095 ( .A(n2856), .B(n2855), .Y(Sgf_operation_EVEN1_left_N5) );
NAND2X8TS U1096 ( .A(mult_x_23_n530), .B(n2485), .Y(n1601) );
INVX6TS U1097 ( .A(n1009), .Y(mult_x_55_n4) );
XNOR2X2TS U1098 ( .A(n3574), .B(Op_MY[0]), .Y(n2606) );
XOR2X4TS U1099 ( .A(n1195), .B(n782), .Y(n1194) );
OAI22X4TS U1100 ( .A0(n2108), .A1(n2026), .B0(n2043), .B1(n2110), .Y(n2041)
);
NAND2X4TS U1101 ( .A(n2099), .B(n950), .Y(n1105) );
NAND2X2TS U1102 ( .A(add_x_19_n132), .B(add_x_19_n308), .Y(add_x_19_n8) );
NAND2X6TS U1103 ( .A(n395), .B(n912), .Y(n2092) );
BUFX16TS U1104 ( .A(n1169), .Y(n392) );
BUFX6TS U1105 ( .A(DP_OP_111J16_123_4462_n607), .Y(n393) );
BUFX6TS U1106 ( .A(n3659), .Y(n394) );
XNOR2X4TS U1107 ( .A(n672), .B(n3580), .Y(n1943) );
OAI22X4TS U1108 ( .A0(n1161), .A1(n2654), .B0(n1943), .B1(n2659), .Y(n1960)
);
OAI2BB1X4TS U1109 ( .A0N(n1080), .A1N(n914), .B0(n2549), .Y(n395) );
INVX16TS U1110 ( .A(Sgf_operation_Result[0]), .Y(n1802) );
NAND2X8TS U1111 ( .A(n550), .B(n549), .Y(n985) );
NAND3X8TS U1112 ( .A(n398), .B(n1432), .C(n1431), .Y(n2990) );
NAND2X8TS U1113 ( .A(n536), .B(n535), .Y(n398) );
OA21X4TS U1114 ( .A0(n1151), .A1(n3071), .B0(n3072), .Y(n1103) );
NAND3X6TS U1115 ( .A(DP_OP_111J16_123_4462_n821), .B(
DP_OP_111J16_123_4462_n751), .C(DP_OP_111J16_123_4462_n720), .Y(n1172)
);
XOR2X4TS U1116 ( .A(mult_x_55_n445), .B(n2653), .Y(n2601) );
XOR2X4TS U1117 ( .A(n1380), .B(n405), .Y(Sgf_operation_EVEN1_right_N10) );
OAI22X4TS U1118 ( .A0(n1497), .A1(n2842), .B0(n853), .B1(n1513), .Y(n1515)
);
XOR2X4TS U1119 ( .A(n3573), .B(mult_x_55_n445), .Y(n1135) );
XOR2X4TS U1120 ( .A(n2053), .B(n785), .Y(n399) );
OA22X4TS U1121 ( .A0(n1566), .A1(n2009), .B0(n2015), .B1(
DP_OP_111J16_123_4462_n685), .Y(n400) );
NAND2X2TS U1122 ( .A(n2215), .B(n2216), .Y(n3452) );
NAND2X4TS U1123 ( .A(n1808), .B(n1809), .Y(n2200) );
NOR2X4TS U1124 ( .A(n1809), .B(n1808), .Y(n2199) );
NOR2X6TS U1125 ( .A(n1809), .B(n1808), .Y(n690) );
NAND2X8TS U1126 ( .A(n762), .B(n759), .Y(n401) );
OAI22X4TS U1127 ( .A0(n1483), .A1(n744), .B0(n893), .B1(n1479), .Y(n1480) );
CLKBUFX2TS U1128 ( .A(n690), .Y(n1150) );
BUFX3TS U1129 ( .A(n2164), .Y(n1085) );
NOR2X6TS U1130 ( .A(n2704), .B(n2705), .Y(n2733) );
NAND2X6TS U1131 ( .A(n2705), .B(n2704), .Y(n2778) );
XOR2X4TS U1132 ( .A(n2453), .B(n3741), .Y(n1711) );
AO21X1TS U1133 ( .A0(n857), .A1(n2411), .B0(n3892), .Y(n2423) );
OAI22X2TS U1134 ( .A0(n1068), .A1(n2411), .B0(n3892), .B1(n857), .Y(n2111)
);
OAI22X4TS U1135 ( .A0(n895), .A1(n1594), .B0(n1005), .B1(n860), .Y(n1630) );
XNOR2X1TS U1136 ( .A(n985), .B(n1248), .Y(Sgf_operation_EVEN1_right_N9) );
NAND2X6TS U1137 ( .A(n3037), .B(n3007), .Y(n1039) );
NAND2X2TS U1138 ( .A(n3037), .B(n3041), .Y(n1127) );
ADDFHX4TS U1139 ( .A(n1642), .B(n1641), .CI(n1640), .CO(n1637), .S(n2569) );
INVX4TS U1140 ( .A(n2817), .Y(n404) );
NAND2X6TS U1141 ( .A(n3884), .B(DP_OP_111J16_123_4462_n783), .Y(n1567) );
AND2X4TS U1142 ( .A(n2813), .B(n2812), .Y(n405) );
CLKBUFX3TS U1143 ( .A(n2172), .Y(n1102) );
OR2X6TS U1144 ( .A(n1420), .B(n1193), .Y(add_x_19_n152) );
CLKBUFX2TS U1145 ( .A(n810), .Y(n755) );
CLKBUFX3TS U1146 ( .A(n754), .Y(n681) );
INVX2TS U1147 ( .A(n410), .Y(n411) );
CLKINVX1TS U1148 ( .A(n877), .Y(n415) );
INVX16TS U1149 ( .A(n4073), .Y(n877) );
INVX2TS U1150 ( .A(Sgf_operation_EVEN1_right_N2), .Y(n659) );
NAND2BX1TS U1151 ( .AN(n477), .B(Sgf_normalized_result[16]), .Y(n478) );
NAND2X2TS U1152 ( .A(Sgf_normalized_result[17]), .B(
Sgf_normalized_result[16]), .Y(n3445) );
MX2X6TS U1153 ( .A(n3325), .B(n4018), .S0(n635), .Y(n259) );
MX2X6TS U1154 ( .A(n3231), .B(n4013), .S0(n635), .Y(n255) );
MX2X6TS U1155 ( .A(n3302), .B(n4020), .S0(n635), .Y(n257) );
MX2X6TS U1156 ( .A(n3374), .B(n4015), .S0(n635), .Y(n253) );
MX2X4TS U1157 ( .A(n3308), .B(n4012), .S0(n635), .Y(n256) );
MX2X6TS U1158 ( .A(n2581), .B(n3994), .S0(n636), .Y(n241) );
MX2X6TS U1159 ( .A(n3248), .B(n3999), .S0(n636), .Y(n242) );
CLKMX2X4TS U1160 ( .A(n3282), .B(n4005), .S0(n636), .Y(n250) );
MX2X6TS U1161 ( .A(n3254), .B(n4001), .S0(n636), .Y(n246) );
MX2X6TS U1162 ( .A(n3245), .B(n4003), .S0(n636), .Y(n243) );
MX2X6TS U1163 ( .A(n3268), .B(n4004), .S0(n636), .Y(n247) );
CLKINVX6TS U1164 ( .A(n3871), .Y(n1094) );
INVX2TS U1165 ( .A(n1847), .Y(n1048) );
INVX2TS U1166 ( .A(n484), .Y(n501) );
OR2X6TS U1167 ( .A(n804), .B(Sgf_operation_EVEN1_Q_left[1]), .Y(n2187) );
AND2X2TS U1168 ( .A(n2621), .B(n394), .Y(n803) );
OAI21X2TS U1169 ( .A0(n2339), .A1(n2338), .B0(n2337), .Y(n2340) );
NOR2BX2TS U1170 ( .AN(n894), .B(mult_x_55_n554), .Y(n2644) );
INVX2TS U1171 ( .A(n3933), .Y(n475) );
OAI22X2TS U1172 ( .A0(n698), .A1(mult_x_23_n545), .B0(n865), .B1(n1704), .Y(
n1731) );
AO21X2TS U1173 ( .A0(n1566), .A1(DP_OP_111J16_123_4462_n685), .B0(n3890),
.Y(n1586) );
NAND2BX2TS U1174 ( .AN(n1998), .B(n740), .Y(n1188) );
NAND2BX2TS U1175 ( .AN(n437), .B(Sgf_normalized_result[3]), .Y(n476) );
OAI22X2TS U1176 ( .A0(n2612), .A1(n2626), .B0(n2604), .B1(n844), .Y(n2611)
);
OAI21X2TS U1177 ( .A0(n2435), .A1(n2436), .B0(n2434), .Y(n1250) );
NOR2XLTS U1178 ( .A(n3407), .B(n3406), .Y(n3408) );
INVX2TS U1179 ( .A(n1763), .Y(n1487) );
NAND2X1TS U1180 ( .A(n2965), .B(n1459), .Y(n2966) );
INVX4TS U1181 ( .A(n2938), .Y(n440) );
CLKBUFX2TS U1182 ( .A(Sgf_operation_EVEN1_Q_left[7]), .Y(n512) );
OAI22X2TS U1183 ( .A0(n2420), .A1(n1071), .B0(n2754), .B1(n881), .Y(n1444)
);
INVX6TS U1184 ( .A(n3262), .Y(n3391) );
INVX4TS U1185 ( .A(n3093), .Y(n3091) );
AOI2BB2X2TS U1186 ( .B0(n3391), .B1(n261), .A0N(n901), .A1N(n3911), .Y(n3348) );
NAND2X1TS U1187 ( .A(n3041), .B(n3040), .Y(n3042) );
INVX4TS U1188 ( .A(Sgf_operation_Result[10]), .Y(n694) );
AND2X2TS U1189 ( .A(mult_x_55_a_0_), .B(n356), .Y(n3135) );
NAND2X4TS U1190 ( .A(n3090), .B(n3089), .Y(n3092) );
INVX2TS U1191 ( .A(Data_MY[17]), .Y(n2942) );
INVX4TS U1192 ( .A(n3525), .Y(n3527) );
NAND2X1TS U1193 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n3497) );
NOR2X2TS U1194 ( .A(n3088), .B(n498), .Y(DP_OP_111J16_123_4462_n96) );
AND2X8TS U1195 ( .A(n3856), .B(n598), .Y(n424) );
XOR2X1TS U1196 ( .A(n3577), .B(n316), .Y(n425) );
AND2X8TS U1197 ( .A(n1906), .B(n1907), .Y(n427) );
AND2X8TS U1198 ( .A(n2973), .B(n1455), .Y(n429) );
AND2X8TS U1199 ( .A(n1574), .B(DP_OP_111J16_123_4462_n758), .Y(n431) );
OR2X8TS U1200 ( .A(n1032), .B(n710), .Y(n432) );
AO21X4TS U1201 ( .A0(n786), .A1(n695), .B0(n3888), .Y(n433) );
CLKINVX12TS U1202 ( .A(Op_MY[0]), .Y(n2656) );
AND2X6TS U1203 ( .A(n2923), .B(n2921), .Y(n434) );
AND2X6TS U1204 ( .A(n941), .B(n1454), .Y(n2247) );
AO21X4TS U1205 ( .A0(n3468), .A1(n2209), .B0(n2208), .Y(n435) );
XOR2X4TS U1206 ( .A(n2975), .B(n2974), .Y(n438) );
NAND2X8TS U1207 ( .A(n1818), .B(n1817), .Y(n810) );
INVX2TS U1208 ( .A(n2957), .Y(n2959) );
MX2X2TS U1209 ( .A(n3427), .B(P_Sgf[18]), .S0(n441), .Y(n233) );
MX2X2TS U1210 ( .A(n3473), .B(P_Sgf[15]), .S0(n441), .Y(n230) );
INVX2TS U1211 ( .A(n3451), .Y(n557) );
INVX4TS U1212 ( .A(DP_OP_111J16_123_4462_n158), .Y(n2558) );
MX2X2TS U1213 ( .A(n3495), .B(P_Sgf[14]), .S0(n441), .Y(n229) );
NAND2X2TS U1214 ( .A(n3467), .B(n1473), .Y(n1360) );
MXI2X2TS U1215 ( .A(n3462), .B(n3897), .S0(n3559), .Y(n276) );
NAND3X2TS U1216 ( .A(n3328), .B(n3327), .C(n3326), .Y(n212) );
NAND2X2TS U1217 ( .A(n2801), .B(mult_x_55_n188), .Y(mult_x_55_n14) );
NAND3X2TS U1218 ( .A(n3239), .B(n3238), .C(n3237), .Y(n207) );
NAND3X4TS U1219 ( .A(n3461), .B(n1363), .C(n563), .Y(n560) );
MXI2X2TS U1220 ( .A(n3415), .B(n3898), .S0(n3559), .Y(n278) );
NAND2X2TS U1221 ( .A(n3531), .B(FSM_selector_B[0]), .Y(n975) );
INVX2TS U1222 ( .A(Sgf_operation_EVEN1_right_N3), .Y(n660) );
NAND2X2TS U1223 ( .A(n3798), .B(n3115), .Y(n3113) );
XNOR2X1TS U1224 ( .A(n3798), .B(n3115), .Y(n3851) );
AOI2BB2X2TS U1225 ( .B0(n3391), .B1(n244), .A0N(n902), .A1N(n3954), .Y(n3275) );
NAND2X2TS U1226 ( .A(n3144), .B(n3143), .Y(n3145) );
NAND2X4TS U1227 ( .A(n1355), .B(n1353), .Y(n254) );
NOR2X2TS U1228 ( .A(n3161), .B(n3160), .Y(n3162) );
NAND2X2TS U1229 ( .A(n440), .B(n2939), .Y(n2941) );
INVX2TS U1230 ( .A(n819), .Y(n3134) );
OAI21X1TS U1231 ( .A0(n1221), .A1(n842), .B0(n1220), .Y(n300) );
NAND2X2TS U1232 ( .A(n3845), .B(n3800), .Y(n3844) );
INVX4TS U1233 ( .A(n2637), .Y(n540) );
MX2X2TS U1234 ( .A(n3441), .B(Add_result[17]), .S0(n443), .Y(n289) );
NAND2X2TS U1235 ( .A(n3178), .B(n741), .Y(n3179) );
INVX8TS U1236 ( .A(n3261), .Y(n3383) );
BUFX6TS U1237 ( .A(n3390), .Y(n901) );
NOR2X4TS U1238 ( .A(n3839), .B(n3799), .Y(n3838) );
MX2X2TS U1239 ( .A(n3218), .B(Add_result[8]), .S0(n842), .Y(n298) );
NOR2X2TS U1240 ( .A(n3630), .B(n3641), .Y(n3640) );
INVX3TS U1241 ( .A(n2947), .Y(n1139) );
XOR2X1TS U1242 ( .A(n1914), .B(n3812), .Y(n1915) );
BUFX12TS U1243 ( .A(mult_x_55_n569), .Y(n3577) );
NAND2X2TS U1244 ( .A(n3500), .B(n1282), .Y(n1281) );
NOR2X4TS U1245 ( .A(DP_OP_111J16_123_4462_n891), .B(
DP_OP_111J16_123_4462_n880), .Y(n3803) );
MX2X2TS U1246 ( .A(n3212), .B(Add_result[7]), .S0(n842), .Y(n299) );
INVX8TS U1247 ( .A(mult_x_55_n568), .Y(n1174) );
OAI22X2TS U1248 ( .A0(n2410), .A1(n860), .B0(n2419), .B1(n895), .Y(n2418) );
NAND2X2TS U1249 ( .A(n1347), .B(n2187), .Y(n2189) );
BUFX6TS U1250 ( .A(n878), .Y(n4067) );
BUFX16TS U1251 ( .A(n3459), .Y(n4055) );
MX2X6TS U1252 ( .A(Data_MX[3]), .B(n4048), .S0(n745), .Y(mult_x_55_n569) );
NOR2X4TS U1253 ( .A(n2458), .B(n2457), .Y(n2938) );
INVX3TS U1254 ( .A(n2342), .Y(n2321) );
MX2X6TS U1255 ( .A(Data_MY[15]), .B(n4054), .S0(n746), .Y(n327) );
INVX6TS U1256 ( .A(n2161), .Y(n1901) );
NAND3X1TS U1257 ( .A(n3413), .B(n3557), .C(FSM_selector_B[1]), .Y(n3532) );
INVX16TS U1258 ( .A(n2850), .Y(n746) );
INVX8TS U1259 ( .A(n3412), .Y(n3433) );
INVX2TS U1260 ( .A(n2274), .Y(n2248) );
BUFX12TS U1261 ( .A(n3309), .Y(n3353) );
AND2X2TS U1262 ( .A(n3375), .B(n609), .Y(n696) );
BUFX8TS U1263 ( .A(n3062), .Y(n879) );
INVX2TS U1264 ( .A(n1852), .Y(n2210) );
INVX3TS U1265 ( .A(n3378), .Y(n576) );
INVX2TS U1266 ( .A(n2346), .Y(n2277) );
NAND2X1TS U1267 ( .A(n1159), .B(n3502), .Y(n1209) );
INVX2TS U1268 ( .A(n2583), .Y(n971) );
INVX4TS U1269 ( .A(n3437), .Y(n3477) );
NAND2X4TS U1270 ( .A(n1332), .B(n446), .Y(n3437) );
NAND2X8TS U1271 ( .A(n3502), .B(n3193), .Y(n2583) );
BUFX12TS U1272 ( .A(n3244), .Y(n3378) );
NAND2X6TS U1273 ( .A(n1377), .B(n1454), .Y(n2255) );
CLKINVX2TS U1274 ( .A(n3517), .Y(overflow_flag) );
NOR2X1TS U1275 ( .A(n3193), .B(FS_Module_state_reg[2]), .Y(n3194) );
AND2X2TS U1276 ( .A(n3220), .B(n3221), .Y(n1063) );
NAND2X4TS U1277 ( .A(n3935), .B(n3517), .Y(n3514) );
NAND2XLTS U1278 ( .A(n3516), .B(n3935), .Y(n3518) );
INVX4TS U1279 ( .A(n3733), .Y(n454) );
CLKMX2X2TS U1280 ( .A(n3988), .B(n3987), .S0(n633), .Y(n237) );
INVX2TS U1281 ( .A(n3563), .Y(n3533) );
INVX16TS U1282 ( .A(FS_Module_state_reg[0]), .Y(n3193) );
INVX12TS U1283 ( .A(n867), .Y(n868) );
NAND2X8TS U1284 ( .A(DP_OP_111J16_123_4462_n685), .B(
DP_OP_111J16_123_4462_n619), .Y(n1566) );
INVX8TS U1285 ( .A(n3692), .Y(n2477) );
INVX12TS U1286 ( .A(n880), .Y(n881) );
INVX2TS U1287 ( .A(n3627), .Y(n1054) );
CLKINVX1TS U1288 ( .A(n571), .Y(n572) );
NAND2X1TS U1289 ( .A(n1287), .B(n1285), .Y(n1284) );
INVX2TS U1290 ( .A(Data_MX[16]), .Y(n1180) );
INVX4TS U1291 ( .A(round_mode[1]), .Y(n1285) );
INVX4TS U1292 ( .A(n3000), .Y(n3002) );
NOR2X4TS U1293 ( .A(n3014), .B(n3008), .Y(add_x_19_n204) );
NAND2X2TS U1294 ( .A(n2959), .B(n2958), .Y(add_x_19_n19) );
NAND2X4TS U1295 ( .A(add_x_19_n272), .B(n1383), .Y(n1382) );
INVX4TS U1296 ( .A(mult_x_23_n140), .Y(mult_x_23_n141) );
NAND2X4TS U1297 ( .A(n723), .B(n435), .Y(n1130) );
NAND2X2TS U1298 ( .A(n1383), .B(n3030), .Y(add_x_19_n24) );
NAND2X2TS U1299 ( .A(n557), .B(n3452), .Y(n556) );
INVX4TS U1300 ( .A(n3024), .Y(n3041) );
NAND2X2TS U1301 ( .A(n1360), .B(n1359), .Y(n275) );
NAND2X2TS U1302 ( .A(n2969), .B(n2992), .Y(n2970) );
XOR2X1TS U1303 ( .A(n2941), .B(n2940), .Y(Sgf_operation_EVEN1_left_N4) );
NAND2X2TS U1304 ( .A(n975), .B(n974), .Y(n309) );
NAND2X2TS U1305 ( .A(n542), .B(n2836), .Y(n2838) );
NOR2X6TS U1306 ( .A(n3436), .B(n560), .Y(n559) );
NAND2X2TS U1307 ( .A(n3103), .B(n3102), .Y(n3104) );
NAND2X4TS U1308 ( .A(n1305), .B(n1303), .Y(n2593) );
INVX3TS U1309 ( .A(mult_x_55_n94), .Y(n2797) );
INVX4TS U1310 ( .A(n2995), .Y(n508) );
INVX2TS U1311 ( .A(n2780), .Y(n2782) );
NAND2X2TS U1312 ( .A(n2923), .B(n2922), .Y(n2924) );
NAND2X2TS U1313 ( .A(n3883), .B(n3080), .Y(DP_OP_111J16_123_4462_n7) );
NAND3X4TS U1314 ( .A(n1349), .B(n1351), .C(n1352), .Y(n1348) );
MXI2X2TS U1315 ( .A(n3436), .B(n3899), .S0(n3559), .Y(n277) );
XOR2X1TS U1316 ( .A(n1176), .B(n3155), .Y(n3867) );
NAND2X2TS U1317 ( .A(n3532), .B(n3531), .Y(n308) );
NAND2X4TS U1318 ( .A(n380), .B(n976), .Y(n3531) );
NOR2X4TS U1319 ( .A(n380), .B(n1209), .Y(n1208) );
MXI2X4TS U1320 ( .A(n2303), .B(n1362), .S0(n442), .Y(n3436) );
INVX6TS U1321 ( .A(n2905), .Y(mult_x_23_n190) );
XOR2X1TS U1322 ( .A(n3124), .B(n1202), .Y(n3848) );
OR2X4TS U1323 ( .A(n3075), .B(n3074), .Y(n3883) );
NOR2X2TS U1324 ( .A(n3156), .B(n3805), .Y(n3862) );
NAND2X4TS U1325 ( .A(n1088), .B(n1087), .Y(n790) );
INVX4TS U1326 ( .A(n2504), .Y(n1266) );
NAND2X2TS U1327 ( .A(n3112), .B(n3111), .Y(n3115) );
MXI2X2TS U1328 ( .A(n2312), .B(n3901), .S0(n3559), .Y(n1474) );
NOR2X2TS U1329 ( .A(n3184), .B(n3183), .Y(n3857) );
INVX4TS U1330 ( .A(n2774), .Y(n2805) );
MX2X2TS U1331 ( .A(n3447), .B(Add_result[18]), .S0(n843), .Y(n288) );
NAND2X2TS U1332 ( .A(n3180), .B(n3179), .Y(DP_OP_111J16_123_4462_n6) );
NAND2X2TS U1333 ( .A(n2886), .B(n2933), .Y(mult_x_23_n9) );
NAND2X2TS U1334 ( .A(n2765), .B(n2764), .Y(n2767) );
XNOR2X1TS U1335 ( .A(n323), .B(n3577), .Y(n653) );
NAND2X4TS U1336 ( .A(n2566), .B(n618), .Y(n1212) );
NAND2X4TS U1337 ( .A(n1625), .B(n1624), .Y(n2911) );
XOR2X1TS U1338 ( .A(n358), .B(mult_x_23_n553), .Y(n645) );
INVX2TS U1339 ( .A(n1915), .Y(n460) );
MX2X2TS U1340 ( .A(n3414), .B(Add_result[16]), .S0(n443), .Y(n290) );
MX2X2TS U1341 ( .A(n3435), .B(Add_result[15]), .S0(n443), .Y(n291) );
MX2X2TS U1342 ( .A(n3358), .B(Add_result[9]), .S0(n843), .Y(n297) );
MX2X2TS U1343 ( .A(n3410), .B(Add_result[11]), .S0(n443), .Y(n295) );
MX2X2TS U1344 ( .A(n3419), .B(Add_result[14]), .S0(n443), .Y(n292) );
MX2X2TS U1345 ( .A(n3422), .B(Add_result[13]), .S0(n843), .Y(n293) );
OR2X4TS U1346 ( .A(n477), .B(n3442), .Y(n3443) );
NAND2X2TS U1347 ( .A(n1281), .B(n3226), .Y(n214) );
NAND2X2TS U1348 ( .A(n2849), .B(n2848), .Y(mult_x_55_n6) );
NAND2X4TS U1349 ( .A(n1778), .B(n1777), .Y(n2774) );
NOR2X4TS U1350 ( .A(n3182), .B(n3803), .Y(n3821) );
MX2X2TS U1351 ( .A(n3402), .B(n903), .S0(n842), .Y(n296) );
MX2X2TS U1352 ( .A(n3399), .B(n904), .S0(n842), .Y(n294) );
INVX6TS U1353 ( .A(n2961), .Y(n1900) );
CLKMX2X3TS U1354 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n3511), .Y(n342) );
NOR2X4TS U1355 ( .A(n2885), .B(n2884), .Y(n2934) );
XOR2X4TS U1356 ( .A(n1782), .B(n3811), .Y(n1889) );
INVX2TS U1357 ( .A(n333), .Y(n3567) );
NAND2X2TS U1358 ( .A(n3693), .B(n2944), .Y(n3721) );
NAND2X2TS U1359 ( .A(n3479), .B(n3438), .Y(n3439) );
NAND2BX2TS U1360 ( .AN(mult_x_55_n570), .B(n3716), .Y(n819) );
NAND2X4TS U1361 ( .A(n333), .B(n321), .Y(n3831) );
INVX12TS U1362 ( .A(n2864), .Y(mult_x_23_n553) );
NAND2X2TS U1363 ( .A(n1205), .B(n1204), .Y(n1203) );
NOR2X4TS U1364 ( .A(n333), .B(n321), .Y(n3799) );
NAND2X2TS U1365 ( .A(n3479), .B(n475), .Y(n474) );
NOR2X4TS U1366 ( .A(mult_x_23_n520), .B(mult_x_55_n533), .Y(n3805) );
INVX8TS U1367 ( .A(n841), .Y(n843) );
INVX2TS U1368 ( .A(n348), .Y(n1262) );
INVX12TS U1369 ( .A(n841), .Y(n842) );
INVX6TS U1370 ( .A(n2497), .Y(n1232) );
INVX6TS U1371 ( .A(n2630), .Y(n546) );
INVX2TS U1372 ( .A(mult_x_23_n525), .Y(n3562) );
NAND3X6TS U1373 ( .A(n1398), .B(n1397), .C(n1790), .Y(n1069) );
INVX2TS U1374 ( .A(n350), .Y(n3110) );
NAND3X6TS U1375 ( .A(n972), .B(n3360), .C(n3226), .Y(n3257) );
INVX2TS U1376 ( .A(n2121), .Y(n2084) );
NOR2X4TS U1377 ( .A(n3353), .B(n3226), .Y(n2587) );
INVX12TS U1378 ( .A(n477), .Y(n3479) );
NAND2X2TS U1379 ( .A(n2954), .B(n2953), .Y(mult_x_23_n8) );
MX2X4TS U1380 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n746), .Y(n319) );
XOR2X1TS U1381 ( .A(mult_x_55_n567), .B(n350), .Y(n638) );
INVX2TS U1382 ( .A(n706), .Y(n3060) );
INVX12TS U1383 ( .A(n3413), .Y(n841) );
NAND2X4TS U1384 ( .A(n1141), .B(n1140), .Y(n2878) );
MX2X4TS U1385 ( .A(Data_MY[6]), .B(n4025), .S0(n2945), .Y(mult_x_55_n533) );
INVX8TS U1386 ( .A(n480), .Y(n940) );
CLKMX2X2TS U1387 ( .A(n3199), .B(Add_result[2]), .S0(n3413), .Y(n304) );
BUFX8TS U1388 ( .A(n3459), .Y(n441) );
INVX3TS U1389 ( .A(n1150), .Y(n2201) );
MX2X1TS U1390 ( .A(n3509), .B(Add_result[1]), .S0(n3413), .Y(n305) );
MX2X4TS U1391 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n2945), .Y(
mult_x_23_n520) );
AND2X2TS U1392 ( .A(n3477), .B(n3476), .Y(n3478) );
NOR2X8TS U1393 ( .A(n3529), .B(n3514), .Y(n3524) );
INVX8TS U1394 ( .A(n877), .Y(n878) );
MX2X6TS U1395 ( .A(Data_MX[11]), .B(Op_MX[11]), .S0(n3129), .Y(
mult_x_55_n565) );
NOR2BX2TS U1396 ( .AN(n1018), .B(n3437), .Y(n1017) );
INVX2TS U1397 ( .A(n2281), .Y(n2250) );
BUFX16TS U1398 ( .A(n3508), .Y(n2945) );
INVX4TS U1399 ( .A(n3217), .Y(n3210) );
NAND2BX1TS U1400 ( .AN(n3935), .B(n3557), .Y(n450) );
NAND2X8TS U1401 ( .A(n1159), .B(n3513), .Y(n3413) );
INVX6TS U1402 ( .A(n2304), .Y(n1385) );
BUFX3TS U1403 ( .A(n2390), .Y(n943) );
AND2X2TS U1404 ( .A(n3225), .B(n3930), .Y(n1282) );
INVX6TS U1405 ( .A(n2255), .Y(n2237) );
BUFX16TS U1406 ( .A(n3508), .Y(n3129) );
INVX8TS U1407 ( .A(n567), .Y(n2314) );
BUFX16TS U1408 ( .A(n2479), .Y(n445) );
NAND3X1TS U1409 ( .A(n1288), .B(n1286), .C(n1284), .Y(n1283) );
INVX3TS U1410 ( .A(n2628), .Y(n2614) );
OAI22X2TS U1411 ( .A0(n1156), .A1(n2450), .B0(n2454), .B1(n4008), .Y(n1143)
);
BUFX8TS U1412 ( .A(n3501), .Y(n1159) );
INVX1TS U1413 ( .A(n3499), .Y(n3225) );
INVX1TS U1414 ( .A(n3513), .Y(n3197) );
NOR2X1TS U1415 ( .A(n3475), .B(n3474), .Y(n3476) );
INVX2TS U1416 ( .A(n3213), .Y(n3207) );
INVX4TS U1417 ( .A(n2260), .Y(n553) );
INVX8TS U1418 ( .A(n2585), .Y(n3502) );
NAND2BX1TS U1419 ( .AN(n1287), .B(n3516), .Y(n1286) );
INVX8TS U1420 ( .A(n845), .Y(n846) );
NAND2X4TS U1421 ( .A(n1564), .B(DP_OP_111J16_123_4462_n774), .Y(n481) );
INVX4TS U1422 ( .A(n1291), .Y(n786) );
BUFX16TS U1423 ( .A(n2490), .Y(n1156) );
NOR2X4TS U1424 ( .A(n850), .B(n3655), .Y(n2792) );
INVX6TS U1425 ( .A(n2653), .Y(n2621) );
AND2X4TS U1426 ( .A(n3618), .B(n1325), .Y(n1324) );
INVX2TS U1427 ( .A(n287), .Y(n3914) );
NAND2X4TS U1428 ( .A(n454), .B(n453), .Y(n452) );
BUFX12TS U1429 ( .A(FS_Module_state_reg[1]), .Y(n1089) );
INVX2TS U1430 ( .A(n3644), .Y(n2603) );
INVX2TS U1431 ( .A(n4036), .Y(n1470) );
INVX8TS U1432 ( .A(DP_OP_111J16_123_4462_n698), .Y(n918) );
OAI21X2TS U1433 ( .A0(n643), .A1(n642), .B0(n641), .Y(add_x_19_n205) );
NAND2X4TS U1434 ( .A(n596), .B(n600), .Y(n1038) );
INVX2TS U1435 ( .A(n3582), .Y(n793) );
INVX2TS U1436 ( .A(n3584), .Y(n1322) );
INVX2TS U1437 ( .A(n3673), .Y(n1319) );
INVX2TS U1438 ( .A(n628), .Y(n487) );
INVX2TS U1439 ( .A(n674), .Y(n675) );
NOR2X4TS U1440 ( .A(exp_oper_result_8_), .B(Exp_module_Overflow_flag_A), .Y(
n3517) );
INVX2TS U1441 ( .A(Sgf_normalized_result[10]), .Y(n3406) );
INVX2TS U1442 ( .A(n3684), .Y(n627) );
INVX2TS U1443 ( .A(n3832), .Y(n1196) );
NAND2X4TS U1444 ( .A(n3724), .B(n3723), .Y(n1045) );
OR2X4TS U1445 ( .A(n3894), .B(n1445), .Y(n1004) );
INVX2TS U1446 ( .A(Add_result[4]), .Y(n3249) );
XOR2X1TS U1447 ( .A(n3774), .B(n606), .Y(n1280) );
NOR2BX1TS U1448 ( .AN(n4014), .B(n634), .Y(n1354) );
CLKAND2X2TS U1449 ( .A(n3785), .B(n3786), .Y(n577) );
NOR2X8TS U1450 ( .A(FS_Module_state_reg[2]), .B(n3928), .Y(n3513) );
CLKMX2X2TS U1451 ( .A(n3990), .B(n3989), .S0(n619), .Y(n236) );
NOR2BX2TS U1452 ( .AN(Op_MY[12]), .B(n3668), .Y(n1707) );
INVX8TS U1453 ( .A(mult_x_23_a_0_), .Y(n835) );
NAND2X2TS U1454 ( .A(n3002), .B(n3001), .Y(add_x_19_n11) );
INVX3TS U1455 ( .A(n2984), .Y(add_x_19_n194) );
NAND2X2TS U1456 ( .A(add_x_19_n215), .B(n3049), .Y(add_x_19_n213) );
NAND2X2TS U1457 ( .A(n3048), .B(n3047), .Y(add_x_19_n17) );
NAND2X6TS U1458 ( .A(n534), .B(n1429), .Y(n1431) );
NAND2X4TS U1459 ( .A(n1422), .B(n1421), .Y(n534) );
NAND2X4TS U1460 ( .A(n1382), .B(n3030), .Y(n1381) );
INVX2TS U1461 ( .A(add_x_19_n243), .Y(n2234) );
INVX8TS U1462 ( .A(add_x_19_n272), .Y(add_x_19_n271) );
INVX6TS U1463 ( .A(DP_OP_111J16_123_4462_n48), .Y(DP_OP_111J16_123_4462_n46)
);
MX2X2TS U1464 ( .A(n3489), .B(P_Sgf[17]), .S0(n4055), .Y(n232) );
MX2X2TS U1465 ( .A(n3405), .B(P_Sgf[16]), .S0(n441), .Y(n231) );
INVX4TS U1466 ( .A(n2546), .Y(DP_OP_111J16_123_4462_n224) );
NOR2X6TS U1467 ( .A(n1316), .B(n1315), .Y(n1314) );
INVX2TS U1468 ( .A(n3040), .Y(n3025) );
INVX2TS U1469 ( .A(n3032), .Y(n3034) );
INVX4TS U1470 ( .A(n3085), .Y(DP_OP_111J16_123_4462_n45) );
INVX8TS U1471 ( .A(n1149), .Y(n1440) );
INVX2TS U1472 ( .A(n3050), .Y(n3051) );
INVX3TS U1473 ( .A(n3484), .Y(n3486) );
NAND2X2TS U1474 ( .A(n3483), .B(n3481), .Y(n3404) );
NAND2X6TS U1475 ( .A(n1425), .B(n1424), .Y(n1906) );
NAND3X4TS U1476 ( .A(n939), .B(n3463), .C(n3464), .Y(n2359) );
NAND2X6TS U1477 ( .A(n2735), .B(n2798), .Y(mult_x_55_n47) );
NAND2X2TS U1478 ( .A(n2810), .B(n2809), .Y(mult_x_55_n15) );
NAND2X6TS U1479 ( .A(n3095), .B(n964), .Y(n963) );
NOR2X4TS U1480 ( .A(n2956), .B(n1074), .Y(n3031) );
NAND2X2TS U1481 ( .A(n3079), .B(n3078), .Y(DP_OP_111J16_123_4462_n21) );
NAND3X6TS U1482 ( .A(n559), .B(n3467), .C(n3465), .Y(n939) );
NAND2X2TS U1483 ( .A(n2782), .B(n2781), .Y(mult_x_55_n11) );
NAND2X4TS U1484 ( .A(n2442), .B(mult_x_23_n97), .Y(mult_x_23_n15) );
NAND2X2TS U1485 ( .A(mult_x_23_n194), .B(n2868), .Y(mult_x_23_n21) );
INVX2TS U1486 ( .A(n3461), .Y(n3462) );
INVX4TS U1487 ( .A(n2965), .Y(n1884) );
NAND2X4TS U1488 ( .A(n1367), .B(n3394), .Y(n561) );
INVX4TS U1489 ( .A(n2800), .Y(mult_x_55_n188) );
INVX8TS U1490 ( .A(n2868), .Y(n1257) );
INVX4TS U1491 ( .A(n1182), .Y(n2940) );
NAND2X1TS U1492 ( .A(n3055), .B(n2961), .Y(add_x_19_n39) );
MX2X2TS U1493 ( .A(n3362), .B(Sgf_normalized_result[23]), .S0(n3361), .Y(
n307) );
NAND2X1TS U1494 ( .A(n3056), .B(n679), .Y(add_x_19_n57) );
INVX6TS U1495 ( .A(n2137), .Y(n532) );
NAND2X4TS U1496 ( .A(n1366), .B(n3456), .Y(n562) );
NAND2X2TS U1497 ( .A(n2928), .B(n2927), .Y(mult_x_23_n12) );
INVX6TS U1498 ( .A(n2733), .Y(n2779) );
MX2X2TS U1499 ( .A(n3444), .B(Add_result[22]), .S0(n3413), .Y(n284) );
NAND2X6TS U1500 ( .A(n1267), .B(n1266), .Y(n2923) );
INVX4TS U1501 ( .A(n2914), .Y(mult_x_23_n49) );
NAND2X4TS U1502 ( .A(n1626), .B(n2911), .Y(mult_x_23_n14) );
NAND2X2TS U1503 ( .A(n1263), .B(n1262), .Y(n1261) );
NAND2X6TS U1504 ( .A(n2441), .B(n2440), .Y(mult_x_23_n97) );
NAND2X4TS U1505 ( .A(n254), .B(n3391), .Y(n1349) );
NAND2X2TS U1506 ( .A(n3075), .B(n3074), .Y(n3080) );
OAI21X2TS U1507 ( .A0(n472), .A1(n842), .B0(n471), .Y(n283) );
NAND2X4TS U1508 ( .A(n2861), .B(n2860), .Y(n1181) );
INVX6TS U1509 ( .A(n2929), .Y(mult_x_23_n65) );
AND2X4TS U1510 ( .A(n3181), .B(mult_x_55_n565), .Y(n3882) );
NAND2X2TS U1511 ( .A(n3157), .B(n3158), .Y(n1202) );
INVX6TS U1512 ( .A(n2912), .Y(n1626) );
XOR2X2TS U1513 ( .A(n921), .B(n3931), .Y(n920) );
ADDFHX2TS U1514 ( .A(n2752), .B(n1444), .CI(n2751), .CO(n3075), .S(n2426) );
NAND2X6TS U1515 ( .A(n1212), .B(n1210), .Y(n380) );
INVX2TS U1516 ( .A(n2045), .Y(n566) );
NAND2X6TS U1517 ( .A(n1179), .B(n1178), .Y(n2865) );
NAND2X2TS U1518 ( .A(n2930), .B(n2932), .Y(mult_x_23_n10) );
MXI2X4TS U1519 ( .A(n1328), .B(n1326), .S0(n634), .Y(n252) );
NAND2X2TS U1520 ( .A(n2195), .B(n2194), .Y(n3202) );
NAND2X6TS U1521 ( .A(n1250), .B(n1249), .Y(n2708) );
NAND2X2TS U1522 ( .A(n3168), .B(n3167), .Y(n3181) );
INVX3TS U1523 ( .A(n2082), .Y(n1310) );
AND2X2TS U1524 ( .A(n2947), .B(n2879), .Y(Sgf_operation_EVEN1_left_N1) );
INVX12TS U1525 ( .A(n1473), .Y(n3559) );
INVX2TS U1526 ( .A(n1467), .Y(n682) );
NOR2X4TS U1527 ( .A(n3442), .B(n474), .Y(n473) );
INVX2TS U1528 ( .A(n2123), .Y(n2132) );
XNOR2X2TS U1529 ( .A(n1016), .B(n3942), .Y(n1015) );
OAI21X1TS U1530 ( .A0(n3797), .A1(n3816), .B0(n3817), .Y(n3130) );
NAND2X2TS U1531 ( .A(n2804), .B(n2802), .Y(mult_x_55_n7) );
CLKMX2X3TS U1532 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n3511), .Y(n369) );
INVX3TS U1533 ( .A(n2284), .Y(n2293) );
CLKMX2X3TS U1534 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n3511), .Y(n368) );
XOR2X2TS U1535 ( .A(n3421), .B(n3944), .Y(n3422) );
XOR2X2TS U1536 ( .A(n3418), .B(n3941), .Y(n3419) );
CLKMX2X3TS U1537 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n3511), .Y(n339) );
CLKMX2X3TS U1538 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n3511), .Y(n370) );
XOR2X2TS U1539 ( .A(n3401), .B(n3406), .Y(n3402) );
CLKMX2X3TS U1540 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n3511), .Y(n367) );
XOR2X2TS U1541 ( .A(n3398), .B(n3932), .Y(n3399) );
AO22X2TS U1542 ( .A0(n3530), .A1(Sgf_normalized_result[21]), .B0(
final_result_ieee[21]), .B1(n3529), .Y(n169) );
AO22X2TS U1543 ( .A0(n3515), .A1(Sgf_normalized_result[18]), .B0(
final_result_ieee[18]), .B1(n3529), .Y(n172) );
NAND2X2TS U1544 ( .A(n3119), .B(n3118), .Y(n3147) );
AO22X2TS U1545 ( .A0(n3528), .A1(Sgf_normalized_result[1]), .B0(
final_result_ieee[1]), .B1(n3526), .Y(n189) );
INVX2TS U1546 ( .A(n3182), .Y(n3845) );
NAND2X2TS U1547 ( .A(n331), .B(n319), .Y(n3817) );
AO22X2TS U1548 ( .A0(n3528), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n3526), .Y(n188) );
CLKMX2X3TS U1549 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n3511), .Y(n338) );
NAND2X2TS U1550 ( .A(n3479), .B(n1017), .Y(n1016) );
AO22X2TS U1551 ( .A0(n3528), .A1(Sgf_normalized_result[3]), .B0(
final_result_ieee[3]), .B1(n3526), .Y(n187) );
AO22X2TS U1552 ( .A0(n3528), .A1(Sgf_normalized_result[5]), .B0(
final_result_ieee[5]), .B1(n3526), .Y(n185) );
AO22X2TS U1553 ( .A0(n3528), .A1(Sgf_normalized_result[10]), .B0(
final_result_ieee[10]), .B1(n3527), .Y(n180) );
XOR2X2TS U1554 ( .A(n478), .B(n3943), .Y(n3441) );
AO22X2TS U1555 ( .A0(n3528), .A1(Sgf_normalized_result[6]), .B0(
final_result_ieee[6]), .B1(n3527), .Y(n184) );
AO22X2TS U1556 ( .A0(n3528), .A1(Sgf_normalized_result[9]), .B0(
final_result_ieee[9]), .B1(n3527), .Y(n181) );
AO22X2TS U1557 ( .A0(n3528), .A1(Sgf_normalized_result[8]), .B0(
final_result_ieee[8]), .B1(n3527), .Y(n182) );
AO22X2TS U1558 ( .A0(n3528), .A1(Sgf_normalized_result[7]), .B0(
final_result_ieee[7]), .B1(n3527), .Y(n183) );
AO22X2TS U1559 ( .A0(n3515), .A1(n1018), .B0(final_result_ieee[20]), .B1(
n3529), .Y(n170) );
CLKMX2X4TS U1560 ( .A(n3273), .B(n4002), .S0(n636), .Y(n244) );
CLKMX2X3TS U1561 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n3511), .Y(n341) );
CLKMX2X3TS U1562 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n3511), .Y(n340) );
INVX3TS U1563 ( .A(n314), .Y(n3631) );
NAND2X2TS U1564 ( .A(n327), .B(n315), .Y(n1457) );
XNOR2X2TS U1565 ( .A(n3363), .B(n3753), .Y(n3364) );
XOR2X2TS U1566 ( .A(n3357), .B(n3945), .Y(n3358) );
CLKMX2X3TS U1567 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n3511), .Y(n337) );
XOR2X2TS U1568 ( .A(n3434), .B(n3947), .Y(n3435) );
XOR2X2TS U1569 ( .A(n3409), .B(n3948), .Y(n3410) );
AO22X2TS U1570 ( .A0(n3530), .A1(Sgf_normalized_result[22]), .B0(
final_result_ieee[22]), .B1(n3529), .Y(n167) );
INVX2TS U1571 ( .A(n3505), .Y(n1358) );
INVX6TS U1572 ( .A(n2505), .Y(n1267) );
INVX8TS U1573 ( .A(n2356), .Y(n2330) );
NAND2X4TS U1574 ( .A(n801), .B(n800), .Y(n2179) );
NAND2X6TS U1575 ( .A(n546), .B(n2629), .Y(n2765) );
INVX6TS U1576 ( .A(n1335), .Y(n778) );
INVX4TS U1577 ( .A(mult_x_23_n554), .Y(n3716) );
NAND2X6TS U1578 ( .A(n2877), .B(n2878), .Y(n2947) );
NOR2X4TS U1579 ( .A(n328), .B(n316), .Y(n3182) );
NAND2X2TS U1580 ( .A(mult_x_23_n520), .B(mult_x_55_n533), .Y(n3816) );
INVX3TS U1581 ( .A(mult_x_23_n550), .Y(n3710) );
MX2X4TS U1582 ( .A(n2863), .B(n733), .S0(n745), .Y(n2864) );
ADDFHX2TS U1583 ( .A(n2882), .B(n2881), .CI(n2880), .CO(n2885), .S(n2875) );
MX2X4TS U1584 ( .A(Data_MY[20]), .B(Op_MY[20]), .S0(n745), .Y(mult_x_23_n518) );
NAND2X2TS U1585 ( .A(mult_x_23_n525), .B(n313), .Y(n3164) );
INVX2TS U1586 ( .A(n2282), .Y(n2278) );
BUFX8TS U1587 ( .A(n3524), .Y(n3530) );
AO22X2TS U1588 ( .A0(n3524), .A1(Sgf_normalized_result[17]), .B0(
final_result_ieee[17]), .B1(n3527), .Y(n173) );
AO22X2TS U1589 ( .A0(n3524), .A1(Sgf_normalized_result[14]), .B0(
final_result_ieee[14]), .B1(n3527), .Y(n176) );
CLKMX2X4TS U1590 ( .A(n3256), .B(n4000), .S0(n636), .Y(n245) );
AO22X2TS U1591 ( .A0(n3524), .A1(Sgf_normalized_result[13]), .B0(
final_result_ieee[13]), .B1(n3527), .Y(n177) );
AO22X2TS U1592 ( .A0(n3524), .A1(Sgf_normalized_result[11]), .B0(
final_result_ieee[11]), .B1(n3527), .Y(n179) );
CLKMX2X3TS U1593 ( .A(Data_MY[31]), .B(Op_MY[31]), .S0(n879), .Y(n310) );
INVX3TS U1594 ( .A(n2287), .Y(n2300) );
NOR2X1TS U1595 ( .A(mult_x_23_n552), .B(mult_x_55_n568), .Y(n3149) );
BUFX8TS U1596 ( .A(n3524), .Y(n3528) );
MX2X4TS U1597 ( .A(Data_MY[5]), .B(n4024), .S0(n745), .Y(
DP_OP_111J16_123_4462_n891) );
INVX3TS U1598 ( .A(mult_x_55_n533), .Y(n3616) );
CLKMX2X3TS U1599 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n879), .Y(n374) );
XNOR2X1TS U1600 ( .A(n3205), .B(n3926), .Y(n3206) );
CLKMX2X3TS U1601 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n879), .Y(n373) );
OR2X4TS U1602 ( .A(n745), .B(n1180), .Y(n1179) );
CLKINVX3TS U1603 ( .A(n1295), .Y(n1290) );
CLKMX2X3TS U1604 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n879), .Y(n372) );
CLKMX2X3TS U1605 ( .A(Data_MX[31]), .B(Op_MX[31]), .S0(n879), .Y(n343) );
OAI2BB1X2TS U1606 ( .A0N(n1391), .A1N(n696), .B0(n3377), .Y(n1327) );
CLKMX2X3TS U1607 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n879), .Y(n371) );
NAND2X2TS U1608 ( .A(n745), .B(Op_MY[11]), .Y(n783) );
OAI21X2TS U1609 ( .A0(n2565), .A1(n3372), .B0(n979), .Y(n978) );
INVX3TS U1610 ( .A(n2309), .Y(n2307) );
AND3X4TS U1611 ( .A(n3823), .B(n490), .C(n488), .Y(n1782) );
BUFX20TS U1612 ( .A(n745), .Y(n3511) );
XNOR2X2TS U1613 ( .A(n1222), .B(n3936), .Y(n1221) );
OAI21X1TS U1614 ( .A0(n3210), .A1(n3209), .B0(n3208), .Y(n3211) );
NAND2X2TS U1615 ( .A(ready), .B(n3192), .Y(n3198) );
INVX2TS U1616 ( .A(n755), .Y(n2167) );
OR2X2TS U1617 ( .A(n3076), .B(n1465), .Y(n3077) );
MX2X4TS U1618 ( .A(Data_MX[12]), .B(mult_x_23_a_0_), .S0(n3129), .Y(n356) );
OR2X2TS U1619 ( .A(n2952), .B(n2951), .Y(n2954) );
MX2X4TS U1620 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n3062), .Y(n324) );
INVX2TS U1621 ( .A(n2989), .Y(n1430) );
INVX2TS U1622 ( .A(n2294), .Y(n2295) );
NOR2BX2TS U1623 ( .AN(n3219), .B(n1061), .Y(n1060) );
INVX2TS U1624 ( .A(n2313), .Y(n2265) );
INVX16TS U1625 ( .A(n2850), .Y(n745) );
NAND2X2TS U1626 ( .A(n3320), .B(n1329), .Y(n3321) );
MX2X4TS U1627 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n2945), .Y(
mult_x_23_n554) );
NAND2X6TS U1628 ( .A(n2305), .B(n1385), .Y(n2309) );
MX2X4TS U1629 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n2945), .Y(mult_x_55_n570)
);
ADDFHX2TS U1630 ( .A(n1732), .B(n1731), .CI(n1730), .CO(n1724), .S(n2509) );
NAND2X6TS U1631 ( .A(n1297), .B(n1296), .Y(n1295) );
MXI2X4TS U1632 ( .A(n1177), .B(n737), .S0(n3062), .Y(n348) );
MX2X4TS U1633 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n3129), .Y(n321) );
MX2X4TS U1634 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n3062), .Y(n320) );
ADDFHX2TS U1635 ( .A(n2687), .B(n2686), .CI(n2685), .CO(n1964), .S(n2696) );
NAND2X2TS U1636 ( .A(n3314), .B(n3375), .Y(n3315) );
INVX2TS U1637 ( .A(n1159), .Y(n977) );
INVX12TS U1638 ( .A(n1330), .Y(n3375) );
OR2X2TS U1639 ( .A(n1908), .B(n605), .Y(n1912) );
NOR2X1TS U1640 ( .A(n3520), .B(Sgf_normalized_result[2]), .Y(n3521) );
INVX4TS U1641 ( .A(n2148), .Y(n1787) );
NAND2X1TS U1642 ( .A(n683), .B(n2169), .Y(n2170) );
NAND2X6TS U1643 ( .A(n2586), .B(n1089), .Y(n3309) );
OR2X4TS U1644 ( .A(n2447), .B(n2446), .Y(n739) );
OR2X6TS U1645 ( .A(n2445), .B(n1142), .Y(n2877) );
OAI21X2TS U1646 ( .A0(n3378), .A1(n3280), .B0(n3279), .Y(n3281) );
AOI21X4TS U1647 ( .A0(n3217), .A1(n3216), .B0(n3215), .Y(n3412) );
INVX12TS U1648 ( .A(n1160), .Y(n1407) );
NAND2BX2TS U1649 ( .AN(n3411), .B(n1270), .Y(n1269) );
INVX12TS U1650 ( .A(n3525), .Y(n3529) );
NOR2X1TS U1651 ( .A(n3431), .B(n3932), .Y(n3420) );
NOR2X1TS U1652 ( .A(n3431), .B(n3428), .Y(n3417) );
NAND2X6TS U1653 ( .A(n2775), .B(n3190), .Y(n4073) );
INVX12TS U1654 ( .A(n2655), .Y(n2661) );
NOR2X1TS U1655 ( .A(FS_Module_state_reg[0]), .B(n731), .Y(n3496) );
OAI21X2TS U1656 ( .A0(mult_x_23_n523), .A1(n883), .B0(n1268), .Y(n1679) );
NAND2X6TS U1657 ( .A(n1118), .B(n1122), .Y(n1121) );
INVX8TS U1658 ( .A(n568), .Y(n2263) );
INVX2TS U1659 ( .A(n2845), .Y(n2841) );
NAND2X4TS U1660 ( .A(n3499), .B(n2585), .Y(n2586) );
INVX4TS U1661 ( .A(n677), .Y(n1916) );
INVX2TS U1662 ( .A(n2792), .Y(n1776) );
NAND2X2TS U1663 ( .A(n1453), .B(n1036), .Y(n1035) );
INVX4TS U1664 ( .A(n848), .Y(n655) );
NAND2X4TS U1665 ( .A(n3742), .B(n1617), .Y(n1268) );
INVX2TS U1666 ( .A(n1354), .Y(n1353) );
INVX4TS U1667 ( .A(add_x_19_n122), .Y(n3795) );
INVX2TS U1668 ( .A(n2463), .Y(n1671) );
NAND2X6TS U1669 ( .A(n1004), .B(n1003), .Y(n1002) );
INVX2TS U1670 ( .A(n1093), .Y(n527) );
OAI21X1TS U1671 ( .A0(n607), .A1(n3775), .B0(n3246), .Y(n3247) );
NAND2X6TS U1672 ( .A(n511), .B(n1094), .Y(n510) );
INVX6TS U1673 ( .A(n3503), .Y(n1846) );
NOR2X2TS U1674 ( .A(n1461), .B(n467), .Y(n2617) );
INVX4TS U1675 ( .A(n1093), .Y(n929) );
INVX2TS U1676 ( .A(n1211), .Y(n1210) );
CLKAND2X2TS U1677 ( .A(n3224), .B(n3223), .Y(n735) );
OAI21X2TS U1678 ( .A0(n1280), .A1(n633), .B0(n1279), .Y(n235) );
NOR2X1TS U1679 ( .A(n3445), .B(n3934), .Y(n3438) );
INVX2TS U1680 ( .A(n1482), .Y(n1536) );
INVX2TS U1681 ( .A(n3570), .Y(n3538) );
BUFX16TS U1682 ( .A(DP_OP_111J16_123_4462_n684), .Y(n2110) );
CLKINVX1TS U1683 ( .A(Op_MX[19]), .Y(n3548) );
OR2X8TS U1684 ( .A(n3906), .B(FS_Module_state_reg[3]), .Y(n2585) );
INVX8TS U1685 ( .A(n898), .Y(n899) );
INVX2TS U1686 ( .A(n3820), .Y(n1218) );
INVX4TS U1687 ( .A(DP_OP_111J16_123_4462_n713), .Y(n845) );
CLKMX2X4TS U1688 ( .A(n658), .B(n657), .S0(n656), .Y(n287) );
NAND2X2TS U1689 ( .A(n3875), .B(n599), .Y(n1796) );
BUFX12TS U1690 ( .A(n4029), .Y(n455) );
NAND2X2TS U1691 ( .A(n610), .B(n654), .Y(DP_OP_111J16_123_4462_n18) );
INVX2TS U1692 ( .A(n3607), .Y(n1134) );
INVX2TS U1693 ( .A(Add_result[1]), .Y(n3240) );
INVX12TS U1694 ( .A(Sgf_operation_Result[9]), .Y(n1829) );
INVX4TS U1695 ( .A(n3445), .Y(n446) );
INVX6TS U1696 ( .A(n3659), .Y(n552) );
BUFX16TS U1697 ( .A(mult_x_23_n541), .Y(n2481) );
CLKMX2X4TS U1698 ( .A(n3984), .B(n3983), .S0(n633), .Y(n239) );
INVX6TS U1699 ( .A(Sgf_operation_EVEN1_Q_middle[0]), .Y(n1081) );
INVX6TS U1700 ( .A(n3732), .Y(n1273) );
BUFX3TS U1701 ( .A(n4056), .Y(n447) );
CLKBUFX2TS U1702 ( .A(n2080), .Y(n448) );
INVX8TS U1703 ( .A(n1099), .Y(n1154) );
OAI22X4TS U1704 ( .A0(n1578), .A1(n890), .B0(n1593), .B1(n858), .Y(n1628) );
OAI21X4TS U1705 ( .A0(n1246), .A1(n2778), .B0(n2795), .Y(n1245) );
XOR2X4TS U1706 ( .A(n2053), .B(n785), .Y(n911) );
XOR2X4TS U1707 ( .A(n449), .B(n813), .Y(n1950) );
XOR2X4TS U1708 ( .A(n1929), .B(n933), .Y(n449) );
NOR2X8TS U1709 ( .A(n1012), .B(DP_OP_111J16_123_4462_n766), .Y(n688) );
OAI21X4TS U1710 ( .A0(n2359), .A1(n3557), .B0(n450), .Y(n272) );
NOR2X8TS U1711 ( .A(n2257), .B(n2256), .Y(n2304) );
NAND2X8TS U1712 ( .A(n2236), .B(n1454), .Y(n2257) );
AND2X4TS U1713 ( .A(n2224), .B(n1466), .Y(n719) );
XOR2X2TS U1714 ( .A(n2267), .B(n2266), .Y(n2268) );
BUFX8TS U1715 ( .A(n1110), .Y(n463) );
AND2X8TS U1716 ( .A(n1423), .B(n537), .Y(n673) );
NOR2X8TS U1717 ( .A(n1416), .B(n451), .Y(n1415) );
NOR2X4TS U1718 ( .A(n1276), .B(n452), .Y(n451) );
INVX6TS U1719 ( .A(n1065), .Y(n805) );
NOR2X8TS U1720 ( .A(n640), .B(n639), .Y(add_x_19_n122) );
AOI21X4TS U1721 ( .A0(n1190), .A1(n1455), .B0(n2971), .Y(n2975) );
NAND2X2TS U1722 ( .A(n2588), .B(n258), .Y(n3329) );
OR3X4TS U1723 ( .A(n3313), .B(n456), .C(n1390), .Y(n1389) );
INVX12TS U1724 ( .A(Sgf_operation_Result[4]), .Y(n1813) );
NAND3X8TS U1725 ( .A(n1190), .B(n429), .C(n717), .Y(n1410) );
NAND2BX4TS U1726 ( .AN(n1830), .B(n2985), .Y(n3011) );
OAI21X4TS U1727 ( .A0(n798), .A1(n1098), .B0(n797), .Y(n1498) );
NOR2X8TS U1728 ( .A(n434), .B(n2506), .Y(n2507) );
OAI22X2TS U1729 ( .A0(n1601), .A1(n2486), .B0(n729), .B1(n2484), .Y(n2513)
);
XOR2X4TS U1730 ( .A(n1451), .B(n2653), .Y(n1518) );
NOR2X8TS U1731 ( .A(n2749), .B(n2748), .Y(n2896) );
NAND2X8TS U1732 ( .A(n1217), .B(n1215), .Y(add_x_19_n185) );
AO21X4TS U1733 ( .A0(add_x_19_n272), .A1(n3049), .B0(add_x_19_n243), .Y(
n3020) );
XOR2X4TS U1734 ( .A(n2152), .B(n2147), .Y(n2956) );
NAND2X4TS U1735 ( .A(n3004), .B(n3011), .Y(add_x_19_n12) );
OAI21X4TS U1736 ( .A0(n3469), .A1(n3491), .B0(n3470), .Y(n2208) );
NAND2BX4TS U1737 ( .AN(DP_OP_111J16_123_4462_n123), .B(
DP_OP_111J16_123_4462_n128), .Y(DP_OP_111J16_123_4462_n16) );
AO22X2TS U1738 ( .A0(n3737), .A1(n3675), .B0(n3742), .B1(n3739), .Y(n1616)
);
OAI22X4TS U1739 ( .A0(n1005), .A1(DP_OP_111J16_123_4462_n682), .B0(n984),
.B1(n860), .Y(n1649) );
NAND2X2TS U1740 ( .A(n2876), .B(n2875), .Y(n2930) );
OAI22X4TS U1741 ( .A0(n942), .A1(n1602), .B0(n2481), .B1(n1614), .Y(n1620)
);
XOR2X4TS U1742 ( .A(n461), .B(n460), .Y(n533) );
NAND3X6TS U1743 ( .A(n504), .B(n502), .C(n505), .Y(n461) );
INVX8TS U1744 ( .A(n1027), .Y(n962) );
INVX6TS U1745 ( .A(n1838), .Y(n465) );
CLKINVX6TS U1746 ( .A(add_x_19_n308), .Y(n2987) );
NAND4X8TS U1747 ( .A(n1434), .B(n1431), .C(n1432), .D(n1430), .Y(
add_x_19_n308) );
INVX16TS U1748 ( .A(n940), .Y(n2090) );
AO22X4TS U1749 ( .A0(n426), .A1(n845), .B0(n3893), .B1(n2045), .Y(n2124) );
INVX12TS U1750 ( .A(n469), .Y(n1570) );
XNOR2X4TS U1751 ( .A(n448), .B(n464), .Y(n2594) );
XNOR2X4TS U1752 ( .A(n986), .B(n2081), .Y(n464) );
NAND2X8TS U1753 ( .A(n466), .B(n465), .Y(n1056) );
NAND2X6TS U1754 ( .A(n2172), .B(n1825), .Y(n1132) );
NAND2X8TS U1755 ( .A(n768), .B(n1008), .Y(n767) );
NAND3X6TS U1756 ( .A(n953), .B(n1414), .C(n1864), .Y(n1164) );
NAND2X8TS U1757 ( .A(n1411), .B(n1410), .Y(n2979) );
AOI21X4TS U1758 ( .A0(n1898), .A1(n3685), .B0(n3686), .Y(n1384) );
OAI21X4TS U1759 ( .A0(n2298), .A1(n2294), .B0(n1369), .Y(n2261) );
BUFX6TS U1760 ( .A(mult_x_55_n557), .Y(n467) );
ADDFHX4TS U1761 ( .A(n1857), .B(n1856), .CI(n1855), .CO(n808), .S(n676) );
OAI22X4TS U1762 ( .A0(n2626), .A1(n1494), .B0(n2647), .B1(n3653), .Y(n1506)
);
NAND2BX4TS U1763 ( .AN(n3083), .B(n3082), .Y(DP_OP_111J16_123_4462_n15) );
NAND2X4TS U1764 ( .A(n2580), .B(n2579), .Y(n3082) );
NOR2X8TS U1765 ( .A(n2580), .B(n2579), .Y(n3083) );
XOR2X4TS U1766 ( .A(n1570), .B(n470), .Y(n1636) );
XNOR2X4TS U1767 ( .A(n1569), .B(n430), .Y(n469) );
XOR2X4TS U1768 ( .A(n473), .B(n3949), .Y(n472) );
NOR2X8TS U1769 ( .A(n2800), .B(n771), .Y(mult_x_55_n94) );
NOR2X8TS U1770 ( .A(n2362), .B(n2363), .Y(n771) );
NOR2X8TS U1771 ( .A(n2360), .B(n2361), .Y(n2800) );
OAI21X4TS U1772 ( .A0(n2225), .A1(n1409), .B0(n2972), .Y(n1413) );
NOR2X8TS U1773 ( .A(n1863), .B(n1862), .Y(n1409) );
NAND2X8TS U1774 ( .A(n676), .B(n1860), .Y(n2225) );
OAI21X4TS U1775 ( .A0(n3929), .A1(n3200), .B0(n476), .Y(n3217) );
NOR2BX4TS U1776 ( .AN(n436), .B(Sgf_normalized_result[0]), .Y(n3200) );
OR2X8TS U1777 ( .A(n1269), .B(n3412), .Y(n477) );
XNOR2X4TS U1778 ( .A(n1899), .B(n479), .Y(n1888) );
NAND2X8TS U1779 ( .A(n2369), .B(n2370), .Y(n497) );
NOR2X4TS U1780 ( .A(n1563), .B(n483), .Y(n482) );
XOR2X4TS U1781 ( .A(n940), .B(n887), .Y(n1633) );
XOR2X4TS U1782 ( .A(n482), .B(n481), .Y(n480) );
NOR2X6TS U1783 ( .A(n2994), .B(n2993), .Y(n1418) );
NOR2X8TS U1784 ( .A(n1888), .B(n1889), .Y(n2994) );
AOI2BB1X4TS U1785 ( .A0N(n1913), .A1N(n487), .B0(n839), .Y(n1872) );
INVX12TS U1786 ( .A(n485), .Y(n1913) );
NAND2X8TS U1787 ( .A(n493), .B(n492), .Y(n485) );
NAND2XLTS U1788 ( .A(n485), .B(n491), .Y(n490) );
AOI21X4TS U1789 ( .A0(n485), .A1(n1419), .B0(n1453), .Y(n1785) );
NOR2X4TS U1790 ( .A(n1277), .B(n486), .Y(n1792) );
XOR2X4TS U1791 ( .A(n1913), .B(n3814), .Y(n1797) );
NAND2BX4TS U1792 ( .AN(n1781), .B(n510), .Y(n493) );
OAI21X4TS U1793 ( .A0(n1065), .A1(n1110), .B0(n3084), .Y(n833) );
NAND2X8TS U1794 ( .A(n494), .B(n1417), .Y(n500) );
NOR2X8TS U1795 ( .A(n508), .B(n507), .Y(n1417) );
NAND2X8TS U1796 ( .A(n2968), .B(n1418), .Y(n494) );
INVX12TS U1797 ( .A(n500), .Y(n678) );
NAND2X8TS U1798 ( .A(n678), .B(n1433), .Y(n1432) );
NAND2X8TS U1799 ( .A(n496), .B(n495), .Y(n1596) );
OR2X8TS U1800 ( .A(n3894), .B(DP_OP_111J16_123_4462_n707), .Y(n496) );
NOR2X8TS U1801 ( .A(n1920), .B(n1919), .Y(add_x_19_n142) );
XNOR2X4TS U1802 ( .A(n500), .B(n499), .Y(n1920) );
INVX12TS U1803 ( .A(n2367), .Y(n1918) );
NAND4X4TS U1804 ( .A(n2968), .B(n1418), .C(n1223), .D(n506), .Y(n504) );
NAND2X8TS U1805 ( .A(n503), .B(n428), .Y(n502) );
INVX12TS U1806 ( .A(n1224), .Y(n2366) );
AOI21X4TS U1807 ( .A0(n1224), .A1(n506), .B0(n427), .Y(n505) );
AND2X8TS U1808 ( .A(n2218), .B(n3424), .Y(n723) );
NAND2X8TS U1809 ( .A(n1121), .B(n1120), .Y(n779) );
OAI21X4TS U1810 ( .A0(n3011), .A1(n3000), .B0(n3001), .Y(add_x_19_n161) );
XOR2X2TS U1811 ( .A(n1792), .B(n3809), .Y(n1874) );
NAND2X8TS U1812 ( .A(n580), .B(n3870), .Y(n511) );
XNOR2X4TS U1813 ( .A(n1121), .B(n1117), .Y(n1842) );
INVX8TS U1814 ( .A(n580), .Y(DP_OP_111J16_123_4462_n160) );
XNOR2X4TS U1815 ( .A(n580), .B(n3829), .Y(n644) );
NOR2X8TS U1816 ( .A(n1437), .B(n1435), .Y(n1801) );
NAND2X6TS U1817 ( .A(n3870), .B(n580), .Y(n1095) );
NOR2X8TS U1818 ( .A(n1807), .B(n1806), .Y(n2198) );
BUFX3TS U1819 ( .A(n747), .Y(n513) );
NOR2X8TS U1820 ( .A(n1113), .B(n514), .Y(n2164) );
NOR3X8TS U1821 ( .A(n1166), .B(n690), .C(n2198), .Y(n514) );
NAND2X8TS U1822 ( .A(n724), .B(n1091), .Y(n550) );
NAND2X8TS U1823 ( .A(n1371), .B(n1370), .Y(n1091) );
NAND2X8TS U1824 ( .A(n1405), .B(n429), .Y(n953) );
OAI22X4TS U1825 ( .A0(n1601), .A1(n1685), .B0(n2485), .B1(mult_x_23_n480),
.Y(n1669) );
NAND2X4TS U1826 ( .A(mult_x_23_n127), .B(n2902), .Y(mult_x_23_n113) );
XOR2X4TS U1827 ( .A(n517), .B(n829), .Y(n1052) );
XOR2X4TS U1828 ( .A(n1839), .B(Sgf_operation_Result[10]), .Y(n517) );
BUFX6TS U1829 ( .A(n2658), .Y(n518) );
AND2X8TS U1830 ( .A(n1010), .B(n2814), .Y(n812) );
OAI22X4TS U1831 ( .A0(n1156), .A1(n2488), .B0(n1736), .B1(n835), .Y(n2471)
);
OAI22X4TS U1832 ( .A0(n1020), .A1(n1505), .B0(n891), .B1(n519), .Y(n1530) );
XNOR2X4TS U1833 ( .A(n468), .B(n854), .Y(n519) );
XOR2X4TS U1834 ( .A(n1099), .B(n825), .Y(n1635) );
NAND3X8TS U1835 ( .A(n523), .B(n521), .C(n520), .Y(n1099) );
OR2X8TS U1836 ( .A(n522), .B(n431), .Y(n520) );
NAND2X8TS U1837 ( .A(n1573), .B(DP_OP_111J16_123_4462_n720), .Y(n522) );
NAND2BX4TS U1838 ( .AN(n431), .B(n524), .Y(n523) );
NOR2X8TS U1839 ( .A(n390), .B(n3613), .Y(n851) );
NAND2X6TS U1840 ( .A(n767), .B(n765), .Y(mult_x_55_n3) );
OAI22X4TS U1841 ( .A0(n2626), .A1(n2604), .B0(n2647), .B1(n2603), .Y(n2665)
);
OAI22X2TS U1842 ( .A0(n1476), .A1(n697), .B0(n863), .B1(n1959), .Y(n2693) );
NAND2X4TS U1843 ( .A(n2736), .B(n2737), .Y(n3084) );
NAND2BX4TS U1844 ( .AN(n3097), .B(n3096), .Y(DP_OP_111J16_123_4462_n19) );
NAND2X4TS U1845 ( .A(n2598), .B(n2599), .Y(n3096) );
NOR2X8TS U1846 ( .A(n2599), .B(n2598), .Y(n3097) );
NAND2X2TS U1847 ( .A(n2108), .B(n2110), .Y(n528) );
AND2X8TS U1848 ( .A(n1571), .B(n2110), .Y(n526) );
OAI2BB1X4TS U1849 ( .A0N(n2063), .A1N(n2062), .B0(n529), .Y(n2541) );
OAI21X4TS U1850 ( .A0(n2062), .A1(n2063), .B0(n531), .Y(n529) );
XOR2X4TS U1851 ( .A(n530), .B(n2062), .Y(n2093) );
XOR2X4TS U1852 ( .A(n2063), .B(n531), .Y(n530) );
OAI22X4TS U1853 ( .A0(n2064), .A1(n859), .B0(n2061), .B1(n897), .Y(n531) );
XOR2X4TS U1854 ( .A(n940), .B(n886), .Y(n2064) );
NAND2X4TS U1855 ( .A(n2137), .B(n2136), .Y(n964) );
NAND2X8TS U1856 ( .A(n532), .B(n1301), .Y(n3095) );
NAND2X4TS U1857 ( .A(n1919), .B(n1920), .Y(n3003) );
NAND2X2TS U1858 ( .A(n533), .B(n1916), .Y(add_x_19_n125) );
NOR2X8TS U1859 ( .A(n533), .B(n1916), .Y(add_x_19_n124) );
NAND2X8TS U1860 ( .A(n536), .B(n535), .Y(n1434) );
INVX8TS U1861 ( .A(n678), .Y(n536) );
NOR2X8TS U1862 ( .A(n2151), .B(n2153), .Y(n537) );
INVX12TS U1863 ( .A(add_x_19_n142), .Y(n538) );
XNOR2X4TS U1864 ( .A(n4026), .B(n3653), .Y(n2604) );
NAND2X8TS U1865 ( .A(n540), .B(n539), .Y(n542) );
NOR2X8TS U1866 ( .A(n2641), .B(n2640), .Y(n2826) );
NAND2X8TS U1867 ( .A(n2825), .B(n543), .Y(n1371) );
NOR2X6TS U1868 ( .A(n2826), .B(n2831), .Y(n543) );
NOR2X4TS U1869 ( .A(n2639), .B(n2638), .Y(n2831) );
NAND2X8TS U1870 ( .A(n544), .B(n2836), .Y(n2825) );
NAND2X8TS U1871 ( .A(n542), .B(n541), .Y(n544) );
AND2X8TS U1872 ( .A(n545), .B(n2764), .Y(n2837) );
NAND2X4TS U1873 ( .A(n2766), .B(n2765), .Y(n545) );
OAI21X4TS U1874 ( .A0(n2768), .A1(n1376), .B0(n2769), .Y(n2766) );
NOR2X8TS U1875 ( .A(n2701), .B(n2700), .Y(n2818) );
AOI21X4TS U1876 ( .A0(n2823), .A1(n2820), .B0(n2681), .Y(n549) );
NAND2X8TS U1877 ( .A(n552), .B(n551), .Y(n2655) );
XNOR2X4TS U1878 ( .A(mult_x_55_n583), .B(n671), .Y(n551) );
NAND2X6TS U1879 ( .A(n2639), .B(n2638), .Y(n2832) );
AND2X8TS U1880 ( .A(n2242), .B(n553), .Y(n2294) );
OR2X8TS U1881 ( .A(n728), .B(FSM_selector_B[1]), .Y(n2242) );
OAI21X4TS U1882 ( .A0(n555), .A1(n4055), .B0(n554), .Y(n234) );
XOR2X4TS U1883 ( .A(n558), .B(n556), .Y(n555) );
OAI21X4TS U1884 ( .A0(n3450), .A1(n3449), .B0(n3448), .Y(n558) );
AOI21X4TS U1885 ( .A0(n435), .A1(n3424), .B0(n3423), .Y(n3450) );
NAND2X4TS U1886 ( .A(n2706), .B(n2707), .Y(n2795) );
NOR2X8TS U1887 ( .A(n2707), .B(n2706), .Y(n1246) );
INVX2TS U1888 ( .A(n563), .Y(n3415) );
MX2X6TS U1889 ( .A(n2289), .B(n2290), .S0(n442), .Y(n563) );
OAI21X4TS U1890 ( .A0(DP_OP_111J16_123_4462_n778), .A1(n564), .B0(
DP_OP_111J16_123_4462_n783), .Y(n1563) );
XOR2X4TS U1891 ( .A(n2160), .B(n2159), .Y(n565) );
AOI2BB2X4TS U1892 ( .B0(n2031), .B1(n3893), .A0N(n846), .A1N(n566), .Y(n2032) );
XOR2X4TS U1893 ( .A(n2090), .B(n1077), .Y(n2045) );
AOI21X4TS U1894 ( .A0(n1027), .A1(n3095), .B0(n3094), .Y(
DP_OP_111J16_123_4462_n168) );
NAND2X8TS U1895 ( .A(n966), .B(n965), .Y(n1027) );
OA22X4TS U1896 ( .A0(n2652), .A1(n1931), .B0(n2650), .B1(n1512), .Y(n570) );
XOR2X4TS U1897 ( .A(n573), .B(n1567), .Y(n1064) );
AO21X4TS U1898 ( .A0(n836), .A1(DP_OP_111J16_123_4462_n785), .B0(n816), .Y(
n573) );
OAI2BB1X4TS U1899 ( .A0N(n576), .A1N(n574), .B0(n3764), .Y(n3272) );
NOR2X8TS U1900 ( .A(n3731), .B(n3730), .Y(n1274) );
XNOR2X4TS U1901 ( .A(n3324), .B(n3747), .Y(n3325) );
OAI22X4TS U1902 ( .A0(n984), .A1(DP_OP_111J16_123_4462_n682), .B0(n861),
.B1(n1651), .Y(n1643) );
ADDHX4TS U1903 ( .A(n2066), .B(n2067), .CO(n2063), .S(n2077) );
ADDFHX4TS U1904 ( .A(n2415), .B(n2414), .CI(n2413), .CO(n2416), .S(n2406) );
ADDFHX4TS U1905 ( .A(n2401), .B(n2400), .CI(n2399), .CO(n2413), .S(n2403) );
NOR2X8TS U1906 ( .A(n3012), .B(n3000), .Y(add_x_19_n160) );
NAND2X8TS U1907 ( .A(n1868), .B(n1867), .Y(n1033) );
XNOR2X4TS U1908 ( .A(n1570), .B(n887), .Y(n1986) );
NOR2X2TS U1909 ( .A(n2546), .B(n1065), .Y(DP_OP_111J16_123_4462_n130) );
AO21X1TS U1910 ( .A0(n630), .A1(n3767), .B0(n3768), .Y(n578) );
INVX8TS U1911 ( .A(n1408), .Y(n583) );
NAND2X4TS U1912 ( .A(n602), .B(n585), .Y(n1895) );
OAI2BB1X4TS U1913 ( .A0N(n3688), .A1N(n585), .B0(n584), .Y(n1070) );
OR2X2TS U1914 ( .A(n1908), .B(n586), .Y(n1891) );
OAI21X1TS U1915 ( .A0(n1910), .A1(n586), .B0(n3825), .Y(n1890) );
OAI21X1TS U1916 ( .A0(n615), .A1(n1447), .B0(n589), .Y(n3277) );
NOR2X1TS U1917 ( .A(n3368), .B(n590), .Y(n3232) );
OR2X4TS U1918 ( .A(n1160), .B(n593), .Y(n1397) );
OAI21X2TS U1919 ( .A0(n595), .A1(n1791), .B0(n3853), .Y(n1277) );
OAI21X4TS U1920 ( .A0(n601), .A1(n597), .B0(n3826), .Y(n1437) );
INVX2TS U1921 ( .A(n603), .Y(n597) );
INVX2TS U1922 ( .A(n601), .Y(n1163) );
NAND2X2TS U1923 ( .A(n626), .B(n598), .Y(n1781) );
OA21X4TS U1924 ( .A0(n608), .A1(n1160), .B0(n3677), .Y(n1321) );
AOI21X1TS U1925 ( .A0(n1853), .A1(n610), .B0(n3822), .Y(n1849) );
NAND2X1TS U1926 ( .A(n581), .B(n611), .Y(n3293) );
AOI21X4TS U1927 ( .A0(n973), .A1(n616), .B0(add_x_19_n141), .Y(n2561) );
AOI2BB1X2TS U1928 ( .A0N(n3283), .A1N(n1462), .B0(n616), .Y(n3284) );
NOR2X1TS U1929 ( .A(n3368), .B(n623), .Y(n3228) );
NOR2X4TS U1930 ( .A(n3795), .B(n623), .Y(n3229) );
NOR2X1TS U1931 ( .A(n3368), .B(n624), .Y(n3303) );
CLKINVX1TS U1932 ( .A(n626), .Y(n1800) );
OAI21X4TS U1933 ( .A0(n1275), .A1(n1276), .B0(n627), .Y(n1272) );
XNOR2X4TS U1934 ( .A(n3713), .B(n3714), .Y(n829) );
XOR2X4TS U1935 ( .A(n3713), .B(n3714), .Y(n1402) );
XOR2X4TS U1936 ( .A(n3713), .B(n3714), .Y(n693) );
AOI21X4TS U1937 ( .A0(n3726), .A1(n3727), .B0(n3728), .Y(n1840) );
AOI21X2TS U1938 ( .A0(n631), .A1(n613), .B0(n3698), .Y(n1106) );
NAND2X1TS U1939 ( .A(n633), .B(n3992), .Y(n1279) );
CLKMX2X2TS U1940 ( .A(n3986), .B(n3985), .S0(n633), .Y(n238) );
CLKMX2X3TS U1941 ( .A(n3287), .B(n4007), .S0(n636), .Y(n249) );
CLKMX2X2TS U1942 ( .A(n3295), .B(n4006), .S0(n636), .Y(n248) );
INVX8TS U1943 ( .A(n637), .Y(add_x_19_n310) );
AND2X8TS U1944 ( .A(n1420), .B(n1193), .Y(n637) );
NAND2X4TS U1945 ( .A(n432), .B(n1458), .Y(n2221) );
OAI21X2TS U1946 ( .A0(n3868), .A1(DP_OP_111J16_123_4462_n160), .B0(n3869),
.Y(n1197) );
XOR2X4TS U1947 ( .A(n1452), .B(n3665), .Y(n1703) );
OAI21X4TS U1948 ( .A0(n648), .A1(n647), .B0(n646), .Y(
DP_OP_111J16_123_4462_n117) );
INVX2TS U1949 ( .A(n3830), .Y(n649) );
OAI21X2TS U1950 ( .A0(DP_OP_111J16_123_4462_n754), .A1(
DP_OP_111J16_123_4462_n744), .B0(DP_OP_111J16_123_4462_n749), .Y(n1568) );
INVX2TS U1951 ( .A(n3841), .Y(n3863) );
NOR2X2TS U1952 ( .A(mult_x_23_n516), .B(n322), .Y(n3841) );
NOR2X2TS U1953 ( .A(DP_OP_111J16_123_4462_n753), .B(
DP_OP_111J16_123_4462_n744), .Y(n650) );
AOI21X4TS U1954 ( .A0(n650), .A1(DP_OP_111J16_123_4462_n720), .B0(n1568),
.Y(n1569) );
OAI21X2TS U1955 ( .A0(n652), .A1(n651), .B0(n599), .Y(n839) );
AO21X1TS U1956 ( .A0(n2626), .A1(n2647), .B0(n3653), .Y(n1537) );
OAI22X2TS U1957 ( .A0(n2626), .A1(n3653), .B0(n844), .B1(n2623), .Y(n2635)
);
XNOR2X1TS U1958 ( .A(n3575), .B(n894), .Y(n2625) );
NAND2X1TS U1959 ( .A(n2656), .B(n3575), .Y(n2623) );
INVX8TS U1960 ( .A(n1067), .Y(n1066) );
NAND2X8TS U1961 ( .A(DP_OP_111J16_123_4462_n820), .B(
DP_OP_111J16_123_4462_n831), .Y(n1067) );
MXI2X1TS U1962 ( .A(n1805), .B(n3964), .S0(n4055), .Y(n217) );
MXI2X1TS U1963 ( .A(n1811), .B(n3965), .S0(n3510), .Y(n218) );
XNOR2X4TS U1964 ( .A(n2997), .B(n664), .Y(n1420) );
INVX12TS U1965 ( .A(n764), .Y(n744) );
NAND2X2TS U1966 ( .A(n2817), .B(n2816), .Y(mult_x_55_n16) );
OAI2BB1X4TS U1967 ( .A0N(n2817), .A1N(n1245), .B0(n2816), .Y(mult_x_55_n116)
);
ADDFHX4TS U1968 ( .A(n2135), .B(n2134), .CI(n2133), .S(n668) );
ADDFHX2TS U1969 ( .A(n2135), .B(n2134), .CI(n2133), .CO(n2136), .S(n2050) );
OAI22X4TS U1970 ( .A0(n2037), .A1(n884), .B0(n2107), .B1(n866), .Y(n2135) );
INVX4TS U1971 ( .A(n2662), .Y(n2663) );
NOR2X8TS U1972 ( .A(n2214), .B(n2213), .Y(n3449) );
INVX4TS U1973 ( .A(n2799), .Y(mult_x_55_n78) );
OAI22X2TS U1974 ( .A0(n2626), .A1(n2646), .B0(n2647), .B1(n1963), .Y(n2642)
);
XNOR2X4TS U1975 ( .A(n916), .B(n918), .Y(n2023) );
NAND2BX2TS U1976 ( .AN(n2098), .B(n2097), .Y(n2051) );
OAI2BB2X4TS U1977 ( .B0(n861), .B1(n3891), .A0N(n993), .A1N(n669), .Y(n2067)
);
NOR2X4TS U1978 ( .A(n1066), .B(n3891), .Y(n669) );
NAND2X8TS U1979 ( .A(n756), .B(n1011), .Y(n670) );
NAND2X4TS U1980 ( .A(n756), .B(n1011), .Y(n1010) );
OAI21X4TS U1981 ( .A0(n2816), .A1(n2808), .B0(n2809), .Y(n766) );
NOR2X8TS U1982 ( .A(n809), .B(n1047), .Y(n1046) );
ADDFHX4TS U1983 ( .A(n2643), .B(n2644), .CI(n2642), .CO(n2691), .S(n2699) );
NAND2X6TS U1984 ( .A(n2036), .B(n2035), .Y(n3099) );
XNOR2X2TS U1985 ( .A(DP_OP_111J16_123_4462_n605), .B(
DP_OP_111J16_123_4462_n697), .Y(n2044) );
CLKINVX12TS U1986 ( .A(DP_OP_111J16_123_4462_n697), .Y(n917) );
XNOR2X4TS U1987 ( .A(n2766), .B(n2767), .Y(Sgf_operation_EVEN1_right_N3) );
NAND2BX1TS U1988 ( .AN(n3657), .B(n2656), .Y(n2657) );
NOR2X6TS U1989 ( .A(Sgf_operation_EVEN1_Q_left[8]), .B(n2985), .Y(n3012) );
OR2X2TS U1990 ( .A(n1820), .B(n1819), .Y(n683) );
ADDFHX4TS U1991 ( .A(n2129), .B(n2128), .CI(n2127), .CO(n2554), .S(n2130) );
ADDFHX4TS U1992 ( .A(n2102), .B(n2101), .CI(n2100), .CO(n2552), .S(n2555) );
OAI22X2TS U1993 ( .A0(n2105), .A1(n884), .B0(n2091), .B1(n866), .Y(n2100) );
OAI22X4TS U1994 ( .A0(n2107), .A1(n884), .B0(n2105), .B1(n866), .Y(n2128) );
NOR2X8TS U1995 ( .A(n3018), .B(n2957), .Y(n3015) );
NOR2X8TS U1996 ( .A(n2228), .B(Sgf_operation_EVEN1_Q_left[1]), .Y(n2957) );
INVX8TS U1997 ( .A(n954), .Y(n1166) );
XNOR2X4TS U1998 ( .A(n1844), .B(n3681), .Y(n677) );
ADDFHX4TS U1999 ( .A(n2089), .B(n2087), .CI(n2088), .CO(n2076), .S(n2101) );
NAND2X4TS U2000 ( .A(n924), .B(n923), .Y(n2532) );
XNOR2X2TS U2001 ( .A(n2220), .B(n2221), .Y(n2227) );
CLKBUFX2TS U2002 ( .A(n673), .Y(n818) );
NOR2X8TS U2003 ( .A(n2164), .B(n1112), .Y(n1423) );
NAND2X4TS U2004 ( .A(add_x_19_n202), .B(n1395), .Y(add_x_19_n16) );
NAND2X4TS U2005 ( .A(n438), .B(n802), .Y(add_x_19_n202) );
NOR2X8TS U2006 ( .A(n438), .B(n802), .Y(add_x_19_n201) );
XOR2X2TS U2007 ( .A(n2188), .B(n2189), .Y(n2195) );
NAND2X2TS U2008 ( .A(n1460), .B(n1903), .Y(n1424) );
NAND2X6TS U2009 ( .A(n1902), .B(n791), .Y(n1425) );
NAND2X4TS U2010 ( .A(n1427), .B(n1426), .Y(n791) );
INVX4TS U2011 ( .A(DP_OP_111J16_123_4462_n767), .Y(n1012) );
OAI22X2TS U2012 ( .A0(n4008), .A1(n2489), .B0(n2464), .B1(n1156), .Y(n2491)
);
OAI22X2TS U2013 ( .A0(n2044), .A1(n897), .B0(n2024), .B1(n1566), .Y(n2040)
);
INVX4TS U2014 ( .A(n2097), .Y(n1299) );
NAND2BX1TS U2015 ( .AN(n1062), .B(n3222), .Y(n1061) );
NAND2X6TS U2016 ( .A(n1428), .B(n1192), .Y(n1414) );
NAND2X4TS U2017 ( .A(n2176), .B(n1825), .Y(n1112) );
ADDFHX2TS U2018 ( .A(n2115), .B(n2114), .CI(n2113), .CO(n2118), .S(n2125) );
INVX8TS U2019 ( .A(n1396), .Y(n1459) );
OAI22X2TS U2020 ( .A0(n445), .A1(n2449), .B0(n705), .B1(n2452), .Y(n2455) );
MXI2X4TS U2021 ( .A(n3982), .B(n3901), .S0(n569), .Y(n2254) );
INVX2TS U2022 ( .A(n631), .Y(n1790) );
INVX4TS U2023 ( .A(n701), .Y(n1422) );
OAI22X2TS U2024 ( .A0(n2487), .A1(n2461), .B0(n729), .B1(n2473), .Y(n2500)
);
INVX2TS U2025 ( .A(n947), .Y(n946) );
INVX2TS U2026 ( .A(n1318), .Y(n830) );
INVX12TS U2027 ( .A(Sgf_operation_EVEN1_Q_left[6]), .Y(n1215) );
INVX2TS U2028 ( .A(n1996), .Y(n1187) );
NAND2X6TS U2029 ( .A(n3513), .B(n3193), .Y(n3499) );
NOR2X4TS U2030 ( .A(n1283), .B(n1060), .Y(n3500) );
CLKINVX6TS U2031 ( .A(DP_OP_111J16_123_4462_n766), .Y(n1573) );
INVX2TS U2032 ( .A(n3819), .Y(n1219) );
INVX2TS U2033 ( .A(n2550), .Y(n914) );
INVX6TS U2034 ( .A(Sgf_operation_EVEN1_Q_left[3]), .Y(n1810) );
NAND2X1TS U2035 ( .A(n707), .B(Op_MY[27]), .Y(n941) );
NAND2X2TS U2036 ( .A(n1461), .B(n3572), .Y(n1926) );
NOR2X2TS U2037 ( .A(n700), .B(n1461), .Y(n1946) );
NAND2X2TS U2038 ( .A(n707), .B(Op_MY[25]), .Y(n2235) );
AOI2BB2X2TS U2039 ( .B0(n3742), .B1(n2459), .A0N(n883), .A1N(mult_x_23_n524),
.Y(n1665) );
OAI22X2TS U2040 ( .A0(n2487), .A1(n1677), .B0(n2485), .B1(n516), .Y(n1608)
);
INVX2TS U2041 ( .A(n1311), .Y(n1306) );
INVX2TS U2042 ( .A(n2347), .Y(n2326) );
NAND2X2TS U2043 ( .A(n707), .B(Op_MY[29]), .Y(n2276) );
NAND2X4TS U2044 ( .A(n2257), .B(n2256), .Y(n2305) );
NAND2X4TS U2045 ( .A(n3601), .B(n795), .Y(n794) );
NAND2X6TS U2046 ( .A(n774), .B(n772), .Y(n1024) );
INVX2TS U2047 ( .A(n1479), .Y(n774) );
INVX2TS U2048 ( .A(n1739), .Y(n1075) );
INVX2TS U2049 ( .A(n346), .Y(n1204) );
INVX4TS U2050 ( .A(n2013), .Y(n952) );
NAND3X6TS U2051 ( .A(n1092), .B(n1109), .C(n1408), .Y(n1108) );
NAND4X6TS U2052 ( .A(n950), .B(n949), .C(n951), .D(n948), .Y(n965) );
INVX6TS U2053 ( .A(n2139), .Y(n1031) );
INVX2TS U2054 ( .A(n3674), .Y(n687) );
INVX2TS U2055 ( .A(n3672), .Y(n680) );
NAND2X4TS U2056 ( .A(n2162), .B(n2161), .Y(n3040) );
NAND2X4TS U2057 ( .A(n701), .B(n2366), .Y(n1429) );
NAND2X4TS U2058 ( .A(n2367), .B(n2366), .Y(n1421) );
INVX2TS U2059 ( .A(n3175), .Y(n2752) );
INVX2TS U2060 ( .A(n2502), .Y(n1264) );
INVX4TS U2061 ( .A(n2503), .Y(n1265) );
NAND3X6TS U2062 ( .A(n440), .B(n1182), .C(n2854), .Y(n1138) );
INVX2TS U2063 ( .A(n3067), .Y(n2001) );
NOR2X4TS U2064 ( .A(n2007), .B(n2006), .Y(n3169) );
INVX12TS U2065 ( .A(Sgf_operation_Result[5]), .Y(n1815) );
INVX2TS U2066 ( .A(n3931), .Y(n1018) );
NOR2X4TS U2067 ( .A(FS_Module_state_reg[0]), .B(n1089), .Y(n3190) );
NAND2X4TS U2068 ( .A(n2253), .B(n3394), .Y(n1361) );
INVX2TS U2069 ( .A(n2444), .Y(n1142) );
INVX2TS U2070 ( .A(n602), .Y(n1275) );
NAND2X4TS U2071 ( .A(n2984), .B(add_x_19_n178), .Y(add_x_19_n176) );
INVX2TS U2072 ( .A(n3154), .Y(n1260) );
XOR2X1TS U2073 ( .A(n3153), .B(n3158), .Y(n3850) );
NOR2X2TS U2074 ( .A(n3711), .B(n3128), .Y(n1176) );
AOI2BB2X2TS U2075 ( .B0(n3391), .B1(n245), .A0N(n901), .A1N(n3956), .Y(n3355) );
NAND3X2TS U2076 ( .A(n2591), .B(n2590), .C(n2589), .Y(n193) );
NOR2BX1TS U2077 ( .AN(n4022), .B(n618), .Y(n1211) );
INVX2TS U2078 ( .A(n1460), .Y(n1427) );
INVX2TS U2079 ( .A(n836), .Y(n691) );
NAND2X6TS U2080 ( .A(n775), .B(n1124), .Y(n1858) );
INVX2TS U2081 ( .A(n587), .Y(n1036) );
INVX2TS U2082 ( .A(n600), .Y(n1791) );
INVX2TS U2083 ( .A(n1002), .Y(n1000) );
AND2X6TS U2084 ( .A(DP_OP_111J16_123_4462_n620), .B(n695), .Y(n1291) );
NAND2X2TS U2085 ( .A(n1461), .B(n1195), .Y(n1947) );
INVX6TS U2086 ( .A(n2190), .Y(n956) );
NAND2X2TS U2087 ( .A(n1511), .B(n3656), .Y(n797) );
OAI22X2TS U2088 ( .A0(n698), .A1(n1603), .B0(n865), .B1(n1613), .Y(n1619) );
INVX6TS U2089 ( .A(n2140), .Y(n2146) );
INVX6TS U2090 ( .A(n1834), .Y(n748) );
INVX2TS U2091 ( .A(n1078), .Y(n2155) );
OAI22X2TS U2092 ( .A0(n995), .A1(n881), .B0(n916), .B1(n1445), .Y(n1592) );
INVX2TS U2093 ( .A(n2054), .Y(n989) );
INVX2TS U2094 ( .A(n991), .Y(n990) );
INVX6TS U2095 ( .A(n2257), .Y(n2238) );
INVX2TS U2096 ( .A(n2176), .Y(n2177) );
NAND2X2TS U2097 ( .A(n2656), .B(n3574), .Y(n2600) );
INVX4TS U2098 ( .A(n933), .Y(n932) );
INVX2TS U2099 ( .A(n1369), .Y(n1368) );
INVX2TS U2100 ( .A(n2301), .Y(n2296) );
OAI22X2TS U2101 ( .A0(n1601), .A1(n1678), .B0(n2485), .B1(n1677), .Y(n2430)
);
INVX6TS U2102 ( .A(n1409), .Y(n2973) );
INVX8TS U2103 ( .A(Sgf_operation_EVEN1_Q_left[4]), .Y(n1812) );
NOR2X4TS U2104 ( .A(n1160), .B(n591), .Y(n1228) );
INVX2TS U2105 ( .A(n2993), .Y(n2969) );
NOR2X2TS U2106 ( .A(n2326), .B(n2346), .Y(n2329) );
INVX2TS U2107 ( .A(n632), .Y(n1869) );
NAND2X4TS U2108 ( .A(add_x_19_n272), .B(n1129), .Y(n1128) );
INVX2TS U2109 ( .A(n3428), .Y(n3429) );
NAND2X4TS U2110 ( .A(n2458), .B(n2457), .Y(n2939) );
NAND2X6TS U2111 ( .A(n2361), .B(n2360), .Y(n2801) );
INVX4TS U2112 ( .A(n1768), .Y(n1200) );
INVX4TS U2113 ( .A(n1769), .Y(n1199) );
INVX3TS U2114 ( .A(n327), .Y(n2857) );
NOR2X6TS U2115 ( .A(n1695), .B(n1694), .Y(n2905) );
NOR2X6TS U2116 ( .A(n2392), .B(n2391), .Y(n2926) );
CLKINVX6TS U2117 ( .A(n2908), .Y(n1236) );
OAI21X2TS U2118 ( .A0(n1738), .A1(n1739), .B0(n1737), .Y(n1254) );
INVX2TS U2119 ( .A(n3690), .Y(n1795) );
NAND2X1TS U2120 ( .A(n2973), .B(n2972), .Y(n2974) );
INVX4TS U2121 ( .A(n1812), .Y(n802) );
INVX2TS U2122 ( .A(add_x_19_n51), .Y(n1780) );
NOR2X6TS U2123 ( .A(n2216), .B(n2215), .Y(n3451) );
INVX2TS U2124 ( .A(n358), .Y(n1205) );
OAI22X2TS U2125 ( .A0(n2754), .A1(n1071), .B0(n3177), .B1(n881), .Y(n3174)
);
INVX4TS U2126 ( .A(n3468), .Y(n3494) );
NOR2X1TS U2127 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .Y(
n1207) );
INVX4TS U2128 ( .A(n2822), .Y(n2681) );
BUFX8TS U2129 ( .A(n1091), .Y(n927) );
INVX2TS U2130 ( .A(n3190), .Y(n3191) );
NAND2X1TS U2131 ( .A(n952), .B(n1173), .Y(n3064) );
INVX2TS U2132 ( .A(n3133), .Y(n3864) );
INVX2TS U2133 ( .A(n1340), .Y(n1339) );
NOR2BX1TS U2134 ( .AN(n4021), .B(n634), .Y(n1340) );
OAI21X2TS U2135 ( .A0(n920), .A1(n843), .B0(n922), .Y(n286) );
NOR2X2TS U2136 ( .A(n477), .B(n3437), .Y(n921) );
OAI21X2TS U2137 ( .A0(n1015), .A1(n443), .B0(n1014), .Y(n285) );
MXI2X2TS U2138 ( .A(n3463), .B(n3910), .S0(n3559), .Y(n281) );
INVX2TS U2139 ( .A(n2852), .Y(Sgf_operation_EVEN1_right_N0) );
INVX6TS U2140 ( .A(n1779), .Y(mult_x_55_n59) );
CLKMX2X2TS U2141 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n879), .Y(n335) );
XOR2X1TS U2142 ( .A(mult_x_55_n565), .B(n354), .Y(n3614) );
XOR2X1TS U2143 ( .A(n1174), .B(n3629), .Y(n3646) );
CLKMX2X2TS U2144 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n879), .Y(n336) );
XOR2X1TS U2145 ( .A(n3121), .B(n3120), .Y(n3840) );
NAND2X1TS U2146 ( .A(n3148), .B(n3147), .Y(n3120) );
AOI2BB2X2TS U2147 ( .B0(n3391), .B1(n247), .A0N(n901), .A1N(n3953), .Y(n3270) );
XOR2X1TS U2148 ( .A(n2948), .B(n2947), .Y(Sgf_operation_EVEN1_left_N2) );
MXI2X2TS U2149 ( .A(n3464), .B(n3902), .S0(n3559), .Y(n273) );
NAND2X4TS U2150 ( .A(n3094), .B(n3079), .Y(n1028) );
INVX3TS U2151 ( .A(mult_x_55_a_8_), .Y(n3622) );
XOR2X1TS U2152 ( .A(mult_x_55_n567), .B(n3622), .Y(n3623) );
INVX3TS U2153 ( .A(mult_x_55_n565), .Y(n3630) );
XOR2X1TS U2154 ( .A(n354), .B(mult_x_55_n566), .Y(n3633) );
INVX3TS U2155 ( .A(n313), .Y(n3641) );
INVX4TS U2156 ( .A(n316), .Y(n3629) );
INVX4TS U2157 ( .A(n2728), .Y(n1979) );
INVX3TS U2158 ( .A(n877), .Y(n870) );
INVX3TS U2159 ( .A(n877), .Y(n869) );
NAND2X2TS U2160 ( .A(n2920), .B(mult_x_23_n81), .Y(mult_x_23_n13) );
NAND2X2TS U2161 ( .A(n3013), .B(add_x_19_n185), .Y(add_x_19_n14) );
INVX2TS U2162 ( .A(n3011), .Y(add_x_19_n168) );
CLKBUFX3TS U2163 ( .A(n3975), .Y(n3790) );
INVX8TS U2164 ( .A(add_x_19_n185), .Y(n2988) );
CLKBUFX2TS U2165 ( .A(n3973), .Y(n3793) );
OAI21X2TS U2166 ( .A0(add_x_19_n271), .A1(n1041), .B0(n1040), .Y(
add_x_19_n232) );
NAND2X2TS U2167 ( .A(n3049), .B(n3052), .Y(n1041) );
OAI2BB1X2TS U2168 ( .A0N(n3131), .A1N(n1337), .B0(n3132), .Y(n3846) );
NOR2X2TS U2169 ( .A(n3133), .B(n3156), .Y(n1337) );
BUFX3TS U2170 ( .A(n874), .Y(n3978) );
XOR2X1TS U2171 ( .A(n3146), .B(n3145), .Y(n3873) );
INVX2TS U2172 ( .A(n3142), .Y(n3144) );
INVX2TS U2173 ( .A(n3838), .Y(n3874) );
INVX2TS U2174 ( .A(n3080), .Y(DP_OP_111J16_123_4462_n39) );
INVX2TS U2175 ( .A(n3088), .Y(DP_OP_111J16_123_4462_n219) );
NAND2X4TS U2176 ( .A(n3087), .B(n1073), .Y(DP_OP_111J16_123_4462_n58) );
INVX6TS U2177 ( .A(n497), .Y(DP_OP_111J16_123_4462_n106) );
NAND2X2TS U2178 ( .A(n3087), .B(DP_OP_111J16_123_4462_n72), .Y(
DP_OP_111J16_123_4462_n10) );
XOR2X1TS U2179 ( .A(n3189), .B(n3188), .Y(Sgf_operation_EVEN1_middle_N2) );
AND2X4TS U2180 ( .A(n2763), .B(n1376), .Y(Sgf_operation_EVEN1_right_N1) );
XOR2X1TS U2181 ( .A(n3173), .B(n3172), .Y(Sgf_operation_EVEN1_middle_N4) );
BUFX3TS U2182 ( .A(n873), .Y(n4064) );
INVX2TS U2183 ( .A(Data_MX[15]), .Y(n2863) );
INVX2TS U2184 ( .A(n877), .Y(n871) );
BUFX3TS U2185 ( .A(n4061), .Y(n4065) );
BUFX3TS U2186 ( .A(n3972), .Y(n4059) );
BUFX3TS U2187 ( .A(n4060), .Y(n4061) );
BUFX3TS U2188 ( .A(n3978), .Y(n3649) );
INVX2TS U2189 ( .A(rst), .Y(n875) );
NOR2X4TS U2190 ( .A(n970), .B(n969), .Y(n968) );
NAND2X2TS U2191 ( .A(n3342), .B(n3375), .Y(n3344) );
INVX2TS U2192 ( .A(rst), .Y(n4072) );
INVX2TS U2193 ( .A(n1387), .Y(n1386) );
NOR2BX1TS U2194 ( .AN(n4019), .B(n634), .Y(n1387) );
INVX2TS U2195 ( .A(rst), .Y(n876) );
MX2X4TS U2196 ( .A(Data_MY[3]), .B(mult_x_55_n536), .S0(n746), .Y(n315) );
INVX2TS U2197 ( .A(n877), .Y(n872) );
CLKBUFX3TS U2198 ( .A(n4072), .Y(n4056) );
INVX2TS U2199 ( .A(n3449), .Y(n3425) );
AND2X2TS U2200 ( .A(n3413), .B(n3557), .Y(n974) );
AOI21X2TS U2201 ( .A0(n3217), .A1(Sgf_normalized_result[5]), .B0(n3207), .Y(
n1222) );
BUFX3TS U2202 ( .A(n3979), .Y(n3878) );
CLKBUFX3TS U2203 ( .A(n3879), .Y(n4063) );
OR2X2TS U2204 ( .A(n3930), .B(FS_Module_state_reg[2]), .Y(n731) );
XOR2X2TS U2205 ( .A(n2838), .B(n2837), .Y(Sgf_operation_EVEN1_right_N4) );
NAND2X2TS U2206 ( .A(n689), .B(n2795), .Y(mult_x_55_n17) );
XOR2X2TS U2207 ( .A(n1066), .B(n1093), .Y(n2026) );
AO22X4TS U2208 ( .A0(n2103), .A1(n3837), .B0(n1090), .B1(n880), .Y(n1584) );
XOR2X4TS U2209 ( .A(n1069), .B(n680), .Y(n679) );
INVX6TS U2210 ( .A(n3053), .Y(n1467) );
NOR2X8TS U2211 ( .A(n2205), .B(n2204), .Y(n3490) );
NAND2X4TS U2212 ( .A(n2205), .B(n2204), .Y(n3491) );
XOR2X4TS U2213 ( .A(n1873), .B(n684), .Y(n1867) );
XNOR2X4TS U2214 ( .A(n3053), .B(n925), .Y(n684) );
ADDFHX4TS U2215 ( .A(n2404), .B(n2403), .CI(n2402), .CO(n2405), .S(n2394) );
NAND2X4TS U2216 ( .A(n2049), .B(n2050), .Y(n2097) );
INVX6TS U2217 ( .A(n2098), .Y(n949) );
NOR2X4TS U2218 ( .A(n2336), .B(n2335), .Y(n2339) );
ADDHX4TS U2219 ( .A(n2005), .B(n2004), .CO(n2006), .S(n2000) );
OAI22X4TS U2220 ( .A0(n2106), .A1(n3888), .B0(n695), .B1(n1372), .Y(n2005)
);
ADDFHX4TS U2221 ( .A(n2120), .B(n2119), .CI(n2118), .CO(n2547), .S(n2127) );
OAI21X2TS U2222 ( .A0(n1750), .A1(n1749), .B0(n1748), .Y(n1378) );
INVX8TS U2223 ( .A(n2906), .Y(n1162) );
NOR2X6TS U2224 ( .A(n2906), .B(n2896), .Y(n2902) );
ADDFHX4TS U2225 ( .A(n1700), .B(n1699), .CI(n1698), .CO(n1749), .S(n1753) );
INVX6TS U2226 ( .A(n1215), .Y(n685) );
NAND2X4TS U2227 ( .A(n2363), .B(n2362), .Y(n2814) );
XOR2X4TS U2228 ( .A(n1272), .B(n3678), .Y(n706) );
CLKINVX1TS U2229 ( .A(n809), .Y(n1466) );
INVX8TS U2230 ( .A(n3057), .Y(n1859) );
INVX12TS U2231 ( .A(n2963), .Y(n1798) );
XNOR2X2TS U2232 ( .A(n2621), .B(mult_x_55_n531), .Y(n2654) );
XNOR2X4TS U2233 ( .A(n1793), .B(n687), .Y(n3053) );
CMPR22X2TS U2234 ( .A(n1935), .B(n1934), .CO(n1922), .S(n1939) );
OAI21X2TS U2235 ( .A0(n2355), .A1(n2356), .B0(n2354), .Y(n3455) );
NAND2X6TS U2236 ( .A(n2730), .B(n2729), .Y(n2816) );
XOR2X4TS U2237 ( .A(n688), .B(n823), .Y(n822) );
INVX6TS U2238 ( .A(n2955), .Y(n1876) );
AOI21X4TS U2239 ( .A0(n3624), .A1(n3591), .B0(n1788), .Y(n1789) );
AOI21X1TS U2240 ( .A0(n2142), .A1(n828), .B0(n1836), .Y(n692) );
AND2X6TS U2241 ( .A(n1833), .B(n1832), .Y(n828) );
OAI22X2TS U2242 ( .A0(n942), .A1(n1605), .B0(n2481), .B1(n1602), .Y(n1609)
);
INVX8TS U2243 ( .A(n929), .Y(n825) );
NAND2X2TS U2244 ( .A(n677), .B(n1848), .Y(n1124) );
ADDFHX2TS U2245 ( .A(n1620), .B(n1619), .CI(n1618), .CO(n2379), .S(n1621) );
XNOR2X4TS U2246 ( .A(n3661), .B(n3666), .Y(n1666) );
ADDFHX4TS U2247 ( .A(n1501), .B(n1503), .CI(n1502), .CO(n1533), .S(n1523) );
ADDFHX4TS U2248 ( .A(n1707), .B(n1706), .CI(n1705), .CO(n1747), .S(n1725) );
OAI22X4TS U2249 ( .A0(n942), .A1(mult_x_23_n472), .B0(n2481), .B1(n1702),
.Y(n1706) );
OAI2BB2X2TS U2250 ( .B0(n1161), .B1(n1943), .A0N(n837), .A1N(n2851), .Y(
n1956) );
XNOR2X4TS U2251 ( .A(n2463), .B(n3717), .Y(n2454) );
AO21X2TS U2252 ( .A0(n2659), .A1(n2655), .B0(n672), .Y(n1516) );
CLKXOR2X2TS U2253 ( .A(n672), .B(mult_x_55_n449), .Y(n2618) );
NAND2X6TS U2254 ( .A(n1697), .B(n1696), .Y(DP_OP_111J16_123_4462_n94) );
OAI22X4TS U2255 ( .A0(n2652), .A1(n1959), .B0(n863), .B1(mult_x_55_n494),
.Y(n1958) );
ADDFHX4TS U2256 ( .A(n1958), .B(n1957), .CI(n1956), .CO(n1951), .S(n2684) );
ADDFHX4TS U2257 ( .A(n1632), .B(n1631), .CI(n1630), .CO(n1638), .S(n1657) );
INVX2TS U2258 ( .A(n3893), .Y(n967) );
NAND2X8TS U2259 ( .A(n1253), .B(mult_x_23_n540), .Y(n698) );
XNOR2X4TS U2260 ( .A(n1948), .B(n3580), .Y(n699) );
OR2X8TS U2261 ( .A(n2368), .B(n427), .Y(n701) );
XNOR2X2TS U2262 ( .A(n1948), .B(mult_x_55_n449), .Y(n702) );
OR2X8TS U2263 ( .A(n1741), .B(n1740), .Y(n703) );
NOR2X4TS U2264 ( .A(n2035), .B(n2036), .Y(n1213) );
BUFX12TS U2265 ( .A(n3244), .Y(n3372) );
INVX4TS U2266 ( .A(n3372), .Y(n1391) );
CLKINVX6TS U2267 ( .A(n1330), .Y(n1329) );
OAI22X4TS U2268 ( .A0(n2490), .A1(n2489), .B0(n2488), .B1(n835), .Y(n2498)
);
XNOR2X2TS U2269 ( .A(n2453), .B(Op_MY[16]), .Y(n2464) );
NOR2X1TS U2270 ( .A(mult_x_55_n566), .B(mult_x_23_n550), .Y(n708) );
AND2X8TS U2271 ( .A(DP_OP_111J16_123_4462_n617), .B(
DP_OP_111J16_123_4462_n683), .Y(n709) );
XNOR2X4TS U2272 ( .A(n1197), .B(n1196), .Y(n710) );
OA21X4TS U2273 ( .A0(n3026), .A1(n3040), .B0(n3027), .Y(n711) );
OR2X8TS U2274 ( .A(n1881), .B(n1880), .Y(n712) );
XNOR2X4TS U2275 ( .A(n2653), .B(n3652), .Y(n713) );
OA22X4TS U2276 ( .A0(n444), .A1(n3339), .B0(n3372), .B1(n1331), .Y(n714) );
INVX8TS U2277 ( .A(n3508), .Y(n2850) );
OA21X4TS U2278 ( .A0(n2182), .A1(n800), .B0(n2183), .Y(n716) );
INVX2TS U2279 ( .A(n925), .Y(n2213) );
INVX4TS U2280 ( .A(n1152), .Y(mult_x_23_n127) );
NAND2X4TS U2281 ( .A(mult_x_23_n194), .B(n703), .Y(n1152) );
XNOR2X2TS U2282 ( .A(DP_OP_111J16_123_4462_n605), .B(
DP_OP_111J16_123_4462_n699), .Y(n2003) );
NAND2X4TS U2283 ( .A(n1841), .B(n1842), .Y(n2158) );
INVX2TS U2284 ( .A(n2178), .Y(n2173) );
AND2X8TS U2285 ( .A(mult_x_23_n65), .B(n2932), .Y(n725) );
NOR2X4TS U2286 ( .A(n2867), .B(n2866), .Y(n2901) );
INVX6TS U2287 ( .A(n2901), .Y(mult_x_23_n194) );
AND2X8TS U2288 ( .A(n1146), .B(n721), .Y(n728) );
NAND2X2TS U2289 ( .A(n2470), .B(n2469), .Y(n2853) );
XNOR2X1TS U2290 ( .A(mult_x_55_a_0_), .B(n356), .Y(n730) );
OR2X4TS U2291 ( .A(n2195), .B(n2194), .Y(n736) );
AO21X2TS U2292 ( .A0(n3830), .A1(n3863), .B0(n1469), .Y(n738) );
INVX4TS U2293 ( .A(n2865), .Y(n1263) );
INVX2TS U2294 ( .A(n3031), .Y(n1383) );
INVX2TS U2295 ( .A(n3821), .Y(n3156) );
INVX2TS U2296 ( .A(n1472), .Y(n2312) );
XNOR2X2TS U2297 ( .A(n1853), .B(DP_OP_111J16_123_4462_n18), .Y(n1847) );
INVX2TS U2298 ( .A(n877), .Y(n874) );
INVX2TS U2299 ( .A(n877), .Y(n873) );
BUFX3TS U2300 ( .A(n4067), .Y(n4060) );
BUFX3TS U2301 ( .A(n4067), .Y(n4062) );
BUFX3TS U2302 ( .A(n3979), .Y(n3877) );
BUFX3TS U2303 ( .A(n3979), .Y(n3876) );
BUFX3TS U2304 ( .A(n4064), .Y(n908) );
CLKBUFX2TS U2305 ( .A(n3973), .Y(n3794) );
CLKBUFX3TS U2306 ( .A(n3975), .Y(n3792) );
CLKINVX12TS U2307 ( .A(Sgf_operation_EVEN1_Q_left[2]), .Y(n1804) );
OAI21X4TS U2308 ( .A0(n2199), .A1(n747), .B0(n2200), .Y(n1113) );
NAND2X8TS U2309 ( .A(n749), .B(n748), .Y(n2142) );
OAI22X4TS U2310 ( .A0(n1542), .A1(n700), .B0(n853), .B1(n750), .Y(n1538) );
OAI22X4TS U2311 ( .A0(n1497), .A1(n853), .B0(n700), .B1(n750), .Y(n1501) );
XNOR2X4TS U2312 ( .A(n1168), .B(mult_x_55_n535), .Y(n750) );
INVX8TS U2313 ( .A(Sgf_operation_Result[8]), .Y(n1831) );
INVX6TS U2314 ( .A(n3065), .Y(n751) );
NAND2X8TS U2315 ( .A(n753), .B(n752), .Y(n981) );
NAND2X8TS U2316 ( .A(n751), .B(n3063), .Y(n752) );
OAI21X4TS U2317 ( .A0(n3172), .A1(n3169), .B0(n3170), .Y(n3065) );
NAND3X6TS U2318 ( .A(n952), .B(n1173), .C(n3063), .Y(n753) );
NAND2X6TS U2319 ( .A(n2013), .B(n2012), .Y(n3063) );
XNOR2X4TS U2320 ( .A(n886), .B(n1066), .Y(n2009) );
NOR2X8TS U2321 ( .A(n1072), .B(n681), .Y(n2152) );
NAND2X8TS U2322 ( .A(n1132), .B(n716), .Y(n754) );
OAI21X4TS U2323 ( .A0(n796), .A1(n810), .B0(n2169), .Y(n2172) );
NAND2XLTS U2324 ( .A(n756), .B(n2814), .Y(mult_x_55_n13) );
NOR2X1TS U2325 ( .A(n672), .B(n894), .Y(n2620) );
OAI21X4TS U2326 ( .A0(n745), .A1(n758), .B0(n757), .Y(n312) );
NOR2X8TS U2327 ( .A(n761), .B(n760), .Y(n759) );
NAND2X8TS U2328 ( .A(n985), .B(n763), .Y(n762) );
AND2X8TS U2329 ( .A(n1478), .B(mult_x_55_n555), .Y(n764) );
AOI21X4TS U2330 ( .A0(n1245), .A1(n769), .B0(n766), .Y(n765) );
AND2X8TS U2331 ( .A(n2728), .B(n769), .Y(n768) );
NOR2X6TS U2332 ( .A(n2733), .B(n1246), .Y(n2728) );
NOR2X6TS U2333 ( .A(n2815), .B(n2808), .Y(n769) );
NOR2X8TS U2334 ( .A(n2730), .B(n2729), .Y(n2815) );
NOR2X8TS U2335 ( .A(n2732), .B(n2731), .Y(n2808) );
NOR2X8TS U2336 ( .A(n2703), .B(n2702), .Y(n2811) );
INVX4TS U2337 ( .A(n744), .Y(n772) );
AOI2BB1X4TS U2338 ( .A0N(n2780), .A1N(n2776), .B0(n773), .Y(n780) );
XNOR2X4TS U2339 ( .A(n3573), .B(Op_MY[11]), .Y(n1479) );
OAI21X4TS U2340 ( .A0(n1845), .A1(n1336), .B0(n776), .Y(n775) );
NOR2X6TS U2341 ( .A(n778), .B(n777), .Y(n776) );
NAND2X8TS U2342 ( .A(n779), .B(n1119), .Y(n1845) );
NAND2X8TS U2343 ( .A(n781), .B(n780), .Y(n1009) );
NAND2X8TS U2344 ( .A(mult_x_55_n95), .B(n2760), .Y(n781) );
NOR2X8TS U2345 ( .A(n2796), .B(n2780), .Y(n2760) );
NOR2X8TS U2346 ( .A(n2364), .B(n2365), .Y(n2796) );
NAND2X8TS U2347 ( .A(n670), .B(n2814), .Y(mult_x_55_n95) );
XNOR2X4TS U2348 ( .A(Op_MY[11]), .B(n3574), .Y(n1504) );
NOR3X1TS U2349 ( .A(Op_MY[23]), .B(Op_MY[24]), .C(Op_MY[11]), .Y(n3534) );
XOR2X4TS U2350 ( .A(n1168), .B(n782), .Y(n2789) );
OAI21X4TS U2351 ( .A0(n746), .A1(n784), .B0(n783), .Y(n323) );
OAI21X4TS U2352 ( .A0(n2542), .A1(n399), .B0(n2541), .Y(n909) );
XOR2X4TS U2353 ( .A(n991), .B(n2054), .Y(n785) );
OAI2BB1X4TS U2354 ( .A0N(n433), .A1N(n1596), .B0(n787), .Y(n1585) );
OAI21X4TS U2355 ( .A0(n433), .A1(n1596), .B0(n788), .Y(n787) );
XOR2X4TS U2356 ( .A(n788), .B(n789), .Y(n1632) );
OAI22X4TS U2357 ( .A0(n916), .A1(n881), .B0(n3889), .B1(n1445), .Y(n788) );
XOR2X4TS U2358 ( .A(n433), .B(n1596), .Y(n789) );
NAND2X8TS U2359 ( .A(n792), .B(n1086), .Y(n1902) );
NAND2BX4TS U2360 ( .AN(DP_OP_111J16_123_4462_n89), .B(
DP_OP_111J16_123_4462_n94), .Y(DP_OP_111J16_123_4462_n12) );
NOR2X8TS U2361 ( .A(n1697), .B(n1696), .Y(DP_OP_111J16_123_4462_n89) );
INVX3TS U2362 ( .A(add_x_19_n132), .Y(add_x_19_n130) );
NAND2X8TS U2363 ( .A(n2990), .B(n2989), .Y(add_x_19_n132) );
XOR2X4TS U2364 ( .A(n794), .B(n793), .Y(n2148) );
AOI2BB2X4TS U2365 ( .B0(n3590), .B1(n3624), .A0N(n3600), .A1N(n632), .Y(n795) );
NOR2X8TS U2366 ( .A(n2165), .B(n796), .Y(n2176) );
NOR2X8TS U2367 ( .A(n1820), .B(n1819), .Y(n796) );
NOR2X4TS U2368 ( .A(n1511), .B(n3656), .Y(n798) );
XOR2X4TS U2369 ( .A(n1098), .B(n799), .Y(n1967) );
NAND2X4TS U2370 ( .A(n1102), .B(n2173), .Y(n801) );
AO21X4TS U2371 ( .A0(n2661), .A1(n1518), .B0(n803), .Y(n1936) );
XOR2X4TS U2372 ( .A(n1803), .B(Sgf_operation_EVEN1_Q_middle[1]), .Y(n804) );
MXI2X4TS U2373 ( .A(n3981), .B(n3896), .S0(FSM_selector_A), .Y(n2256) );
BUFX12TS U2374 ( .A(mult_x_55_n557), .Y(n2647) );
NAND2XLTS U2375 ( .A(n2191), .B(n2190), .Y(n2193) );
NAND2X4TS U2376 ( .A(n1105), .B(n3099), .Y(n2052) );
INVX12TS U2377 ( .A(n1276), .Y(n1898) );
ADDFHX4TS U2378 ( .A(n1676), .B(n1675), .CI(n1674), .CO(n2433), .S(n2435) );
OAI22X2TS U2379 ( .A0(n1597), .A1(n856), .B0(n1579), .B1(n899), .Y(n1627) );
XOR2X4TS U2380 ( .A(n2412), .B(n825), .Y(n1597) );
NOR2X2TS U2381 ( .A(n3140), .B(n3139), .Y(n3141) );
XOR2X2TS U2382 ( .A(mult_x_55_a_8_), .B(n1475), .Y(n3139) );
BUFX12TS U2383 ( .A(n3661), .Y(n1153) );
INVX8TS U2384 ( .A(n1116), .Y(n1456) );
XNOR2X4TS U2385 ( .A(n1948), .B(mult_x_55_n444), .Y(n1505) );
BUFX20TS U2386 ( .A(n1898), .Y(n1092) );
OAI21X4TS U2387 ( .A0(n2244), .A1(n2291), .B0(n2243), .Y(n2245) );
NOR2X4TS U2388 ( .A(n2242), .B(n2260), .Y(n2244) );
XOR2X2TS U2389 ( .A(n1872), .B(n3807), .Y(n1877) );
XOR2X4TS U2390 ( .A(n1854), .B(n3818), .Y(n1855) );
INVX8TS U2391 ( .A(n2962), .Y(n1856) );
OAI22X4TS U2392 ( .A0(n698), .A1(n1708), .B0(mult_x_23_n540), .B1(
mult_x_23_n459), .Y(n1699) );
AND2X8TS U2393 ( .A(n1123), .B(n1114), .Y(n809) );
OAI22X4TS U2394 ( .A0(n1636), .A1(n859), .B0(n1595), .B1(n897), .Y(n1642) );
OAI22X2TS U2395 ( .A0(n2626), .A1(n1963), .B0(n2647), .B1(mult_x_55_n506),
.Y(n2687) );
MXI2X4TS U2396 ( .A(n3460), .B(n3962), .S0(n3510), .Y(n271) );
ADDHX4TS U2397 ( .A(n2635), .B(n2634), .CO(n2636), .S(n2630) );
AOI21X2TS U2398 ( .A0(n435), .A1(n3483), .B0(n3482), .Y(n3488) );
ADDFHX2TS U2399 ( .A(n2512), .B(n2511), .CI(n2510), .CO(n1737), .S(n2521) );
BUFX20TS U2400 ( .A(DP_OP_111J16_123_4462_n699), .Y(n1077) );
NOR2X6TS U2401 ( .A(n3360), .B(n3226), .Y(n3389) );
OR2X6TS U2402 ( .A(n3360), .B(FSM_selector_C), .Y(n3262) );
BUFX12TS U2403 ( .A(n3389), .Y(n1350) );
ADDFHX2TS U2404 ( .A(n1776), .B(n1775), .CI(n1774), .CO(n2786), .S(n1771) );
CLKINVX12TS U2405 ( .A(n3612), .Y(n1948) );
BUFX12TS U2406 ( .A(n1930), .Y(n813) );
NAND2X2TS U2407 ( .A(n1859), .B(n820), .Y(n1400) );
OAI22X4TS U2408 ( .A0(n852), .A1(n1927), .B0(n700), .B1(n1513), .Y(n1937) );
OAI22X4TS U2409 ( .A0(n2069), .A1(n884), .B0(n1653), .B1(n866), .Y(n2530) );
ADDFHX2TS U2410 ( .A(Sgf_operation_EVEN1_Q_middle[5]), .B(n1814), .CI(n1815),
.S(n814) );
OAI21X4TS U2411 ( .A0(n812), .A1(n2796), .B0(n2776), .Y(mult_x_55_n88) );
NAND2X4TS U2412 ( .A(n1051), .B(n1847), .Y(n2222) );
ADDFHX2TS U2413 ( .A(n3743), .B(n1681), .CI(n1680), .CO(n2428), .S(n1682) );
ADDFHX2TS U2414 ( .A(mult_x_23_n524), .B(n3743), .CI(n1679), .CO(n1610), .S(
n2429) );
NAND2X4TS U2415 ( .A(n1823), .B(n1824), .Y(n2183) );
AOI21X2TS U2416 ( .A0(n1779), .A1(n2798), .B0(n2805), .Y(mult_x_55_n48) );
ADDHX4TS U2417 ( .A(n2111), .B(n2112), .CO(n2102), .S(n2119) );
OAI22X4TS U2418 ( .A0(n2086), .A1(n857), .B0(n2085), .B1(n2411), .Y(n2112)
);
XNOR2X2TS U2419 ( .A(n887), .B(n1066), .Y(n2086) );
NAND2X4TS U2420 ( .A(n2731), .B(n2732), .Y(n2809) );
NOR2X4TS U2421 ( .A(n3093), .B(DP_OP_111J16_123_4462_n89), .Y(
DP_OP_111J16_123_4462_n82) );
INVX4TS U2422 ( .A(n2826), .Y(n2828) );
AO22X2TS U2423 ( .A0(n462), .A1(n2601), .B0(n2660), .B1(n394), .Y(n2676) );
NAND2X4TS U2424 ( .A(n814), .B(n1819), .Y(n2169) );
XOR2X4TS U2425 ( .A(n962), .B(n963), .Y(Sgf_operation_EVEN1_middle_N9) );
AND2X4TS U2426 ( .A(n1864), .B(n953), .Y(n821) );
INVX12TS U2427 ( .A(n822), .Y(n1565) );
XOR2X2TS U2428 ( .A(n3828), .B(n3827), .Y(n824) );
ADDFHX4TS U2429 ( .A(n2536), .B(n2537), .CI(n2535), .CO(n2575), .S(n2533) );
OAI22X2TS U2430 ( .A0(n2079), .A1(DP_OP_111J16_123_4462_n680), .B0(n3886),
.B1(DP_OP_111J16_123_4462_n713), .Y(n2537) );
CLKINVX6TS U2431 ( .A(n1047), .Y(n826) );
ADDFHX4TS U2432 ( .A(Sgf_operation_EVEN1_Q_middle[9]), .B(n1829), .CI(n1828),
.S(n827) );
OAI22X2TS U2433 ( .A0(n1578), .A1(n858), .B0(n1581), .B1(n890), .Y(n1600) );
OAI21X2TS U2434 ( .A0(n2293), .A1(n2292), .B0(n2291), .Y(n2297) );
OAI22X2TS U2435 ( .A0(n2484), .A1(n2487), .B0(n2485), .B1(n1733), .Y(n2518)
);
OAI2BB1X4TS U2436 ( .A0N(n2917), .A1N(n830), .B0(n1314), .Y(n1170) );
OAI22X4TS U2437 ( .A0(DP_OP_111J16_123_4462_n680), .A1(n3886), .B0(n1994),
.B1(DP_OP_111J16_123_4462_n713), .Y(n1465) );
BUFX4TS U2438 ( .A(n1392), .Y(n1149) );
ADDFHX4TS U2439 ( .A(mult_x_55_n270), .B(n1544), .CI(n1543), .CO(n1548), .S(
n1528) );
XNOR2X4TS U2440 ( .A(mult_x_55_n531), .B(n832), .Y(n1512) );
CLKBUFX2TS U2441 ( .A(n2153), .Y(n1078) );
NAND2X8TS U2442 ( .A(n1082), .B(n1081), .Y(n2191) );
ADDFHX4TS U2443 ( .A(n1713), .B(n1715), .CI(n1714), .CO(n1750), .S(n1745) );
NAND2X2TS U2444 ( .A(n2168), .B(n755), .Y(n2166) );
ADDFHX4TS U2445 ( .A(n1944), .B(n1946), .CI(n1945), .CO(n1952), .S(n1965) );
ADDFHX2TS U2446 ( .A(n2515), .B(n2514), .CI(n2513), .CO(n2520), .S(n2522) );
BUFX8TS U2447 ( .A(n2655), .Y(n1161) );
ADDFHX2TS U2448 ( .A(n1536), .B(n1535), .CI(n1534), .CO(n1552), .S(n1556) );
CMPR22X2TS U2449 ( .A(n1961), .B(n1960), .CO(n1966), .S(n2692) );
OAI2BB1X1TS U2450 ( .A0N(n1092), .A1N(n1897), .B0(n1242), .Y(n1241) );
NOR2X4TS U2451 ( .A(n583), .B(n592), .Y(n1897) );
OAI22X4TS U2452 ( .A0(n1594), .A1(n861), .B0(n1577), .B1(n895), .Y(n1629) );
INVX6TS U2453 ( .A(n1217), .Y(n1216) );
OAI22X4TS U2454 ( .A0(n445), .A1(n2478), .B0(n2477), .B1(n2476), .Y(n2515)
);
XOR2X2TS U2455 ( .A(n2474), .B(Op_MY[16]), .Y(n2478) );
ADDHX4TS U2456 ( .A(n2042), .B(n2041), .CO(n2126), .S(n2039) );
XNOR2X4TS U2457 ( .A(n686), .B(DP_OP_111J16_123_4462_n607), .Y(n2043) );
NAND2X4TS U2458 ( .A(n2702), .B(n2703), .Y(n2812) );
INVX8TS U2459 ( .A(n2659), .Y(n2851) );
NAND2X6TS U2460 ( .A(n2739), .B(n2738), .Y(DP_OP_111J16_123_4462_n128) );
OAI22X2TS U2461 ( .A0(n2072), .A1(n858), .B0(n1647), .B1(n2411), .Y(n2538)
);
ADDFHX4TS U2462 ( .A(n1936), .B(n1937), .CI(n1938), .CO(n1975), .S(n1970) );
NAND2X8TS U2463 ( .A(n3086), .B(n3073), .Y(n2757) );
ADDFHX4TS U2464 ( .A(n2669), .B(n2670), .CI(n2668), .CO(n2698), .S(n2671) );
OR2X8TS U2465 ( .A(mult_x_23_a_0_), .B(mult_x_23_n549), .Y(n2490) );
NOR2X6TS U2466 ( .A(n2237), .B(n2254), .Y(n2306) );
NAND2X4TS U2467 ( .A(n1032), .B(n710), .Y(n1458) );
OAI22X2TS U2468 ( .A0(n445), .A1(mult_x_23_n492), .B0(n2477), .B1(n1667),
.Y(n1744) );
ADDFHX2TS U2469 ( .A(n1673), .B(n1672), .CI(n1671), .CO(n2436), .S(n1692) );
ADDFHX4TS U2470 ( .A(n2029), .B(n2028), .CI(n2027), .CO(n2038), .S(n2033) );
OAI22X4TS U2471 ( .A0(n2023), .A1(n866), .B0(n2016), .B1(n884), .Y(n2027) );
OAI22X2TS U2472 ( .A0(n2037), .A1(n866), .B0(n2023), .B1(n884), .Y(n2048) );
XOR2X4TS U2473 ( .A(n1169), .B(n3892), .Y(n2071) );
BUFX20TS U2474 ( .A(n1493), .Y(n2626) );
ADDFHX2TS U2475 ( .A(n1507), .B(n3656), .CI(n1506), .CO(n1529), .S(n1499) );
ADDFHX4TS U2476 ( .A(n2020), .B(n2019), .CI(n2018), .CO(n2021), .S(n2013) );
OAI22X4TS U2477 ( .A0(n2483), .A1(n2480), .B0(n2481), .B1(n1722), .Y(n2511)
);
OAI22X4TS U2478 ( .A0(n942), .A1(mult_x_23_n546), .B0(n2481), .B1(n1735),
.Y(n2472) );
INVX8TS U2479 ( .A(n1439), .Y(n1047) );
CLKINVX12TS U2480 ( .A(Sgf_operation_EVEN1_Q_left[8]), .Y(n1830) );
NAND2X4TS U2481 ( .A(n2527), .B(n2528), .Y(n2908) );
INVX8TS U2482 ( .A(n1394), .Y(n2989) );
XNOR2X4TS U2483 ( .A(n393), .B(n887), .Y(n2085) );
XNOR2X4TS U2484 ( .A(DP_OP_111J16_123_4462_n606), .B(n887), .Y(n2068) );
ADDFHX4TS U2485 ( .A(n1649), .B(n1650), .CI(n1648), .CO(n1656), .S(n2577) );
INVX12TS U2486 ( .A(n995), .Y(n2103) );
ADDFHX4TS U2487 ( .A(n1940), .B(n1941), .CI(n1939), .CO(n1971), .S(n1955) );
XOR2X4TS U2488 ( .A(n1801), .B(n3813), .Y(n1851) );
XNOR2X4TS U2489 ( .A(n3574), .B(mult_x_55_n532), .Y(n1931) );
ADDFHX4TS U2490 ( .A(n1747), .B(n1745), .CI(n1746), .CO(n2746), .S(n1751) );
NAND2X4TS U2491 ( .A(n3592), .B(n3624), .Y(n1325) );
ADDFHX4TS U2492 ( .A(n2540), .B(n2539), .CI(n2538), .CO(n2578), .S(n2574) );
NOR2X4TS U2493 ( .A(DP_OP_111J16_123_4462_n123), .B(n3083), .Y(
DP_OP_111J16_123_4462_n116) );
OAI22X4TS U2494 ( .A0(n2652), .A1(n1504), .B0(n2650), .B1(mult_x_55_n562),
.Y(n1535) );
AO22X4TS U2495 ( .A0(n462), .A1(n2621), .B0(n2620), .B1(n2851), .Y(n2761) );
AO22X4TS U2496 ( .A0(n462), .A1(n2619), .B0(n2618), .B1(n2851), .Y(n2762) );
INVX12TS U2497 ( .A(n1090), .Y(n1583) );
MXI2X4TS U2498 ( .A(n261), .B(Add_result[23]), .S0(FSM_selector_C), .Y(n3359) );
NAND2X2TS U2499 ( .A(n3360), .B(n3359), .Y(n3362) );
MX2X6TS U2500 ( .A(n3346), .B(n4017), .S0(n633), .Y(n261) );
NAND2X4TS U2501 ( .A(n988), .B(n987), .Y(n2531) );
ADDFHX2TS U2502 ( .A(n3667), .B(mult_x_23_n523), .CI(n1604), .CO(n1618), .S(
n1611) );
OAI2BB2X2TS U2503 ( .B0(n3668), .B1(n840), .A0N(n3737), .A1N(n1617), .Y(
n1604) );
ADDFHX2TS U2504 ( .A(n2530), .B(n2529), .CI(n2531), .CO(n2576), .S(n2721) );
INVX12TS U2505 ( .A(n1013), .Y(n2412) );
BUFX20TS U2506 ( .A(n2647), .Y(n844) );
OAI2BB2X2TS U2507 ( .B0(n2647), .B1(mult_x_55_n505), .A0N(n2645), .A1N(n3643), .Y(n1944) );
BUFX20TS U2508 ( .A(n1244), .Y(n847) );
OAI22X4TS U2509 ( .A0(n1020), .A1(n854), .B0(mult_x_55_n554), .B1(n1947),
.Y(n2686) );
OAI22X2TS U2510 ( .A0(n854), .A1(n891), .B0(n1194), .B1(n1020), .Y(n1775) );
INVX12TS U2511 ( .A(n849), .Y(n850) );
NOR2X2TS U2512 ( .A(mult_x_55_n559), .B(n4026), .Y(n1544) );
OAI22X4TS U2513 ( .A0(n2487), .A1(n2473), .B0(n729), .B1(n2486), .Y(n2494)
);
OAI22X2TS U2514 ( .A0(n445), .A1(n2474), .B0(n705), .B1(n2448), .Y(n2456) );
OAI22X2TS U2515 ( .A0(n445), .A1(n2460), .B0(n705), .B1(n2475), .Y(n2501) );
XOR2X4TS U2516 ( .A(n854), .B(mult_x_55_n535), .Y(n1517) );
XNOR2X4TS U2517 ( .A(n1948), .B(n3581), .Y(n1492) );
INVX16TS U2518 ( .A(n2108), .Y(n855) );
INVX16TS U2519 ( .A(n855), .Y(n856) );
OAI22X2TS U2520 ( .A0(n1582), .A1(n2108), .B0(n2110), .B1(n1093), .Y(n1985)
);
OAI22X2TS U2521 ( .A0(n2117), .A1(n859), .B0(n2116), .B1(n897), .Y(n2548) );
OAI22X4TS U2522 ( .A0(n2055), .A1(n897), .B0(n2061), .B1(n859), .Y(n2542) );
OAI22X4TS U2523 ( .A0(n1595), .A1(n1566), .B0(DP_OP_111J16_123_4462_n685),
.B1(n3890), .Y(n1590) );
INVX4TS U2524 ( .A(n2753), .Y(n860) );
NAND2X8TS U2525 ( .A(mult_x_55_n543), .B(n2650), .Y(n1476) );
OAI22X2TS U2526 ( .A0(n2652), .A1(mult_x_55_n562), .B0(n863), .B1(n2600),
.Y(n2608) );
OAI22X4TS U2527 ( .A0(n2652), .A1(mult_x_55_n494), .B0(n2650), .B1(n1931),
.Y(n1941) );
OAI22X2TS U2528 ( .A0(n2652), .A1(n2651), .B0(n863), .B1(n697), .Y(n2690) );
OAI22X2TS U2529 ( .A0(n2070), .A1(n884), .B0(n2069), .B1(n866), .Y(n2534) );
OAI22X2TS U2530 ( .A0(n1653), .A1(n2106), .B0(n695), .B1(n3888), .Y(n1650)
);
BUFX3TS U2531 ( .A(n870), .Y(n3879) );
NOR2X4TS U2532 ( .A(n3214), .B(n3926), .Y(n3216) );
NAND2X6TS U2533 ( .A(n2000), .B(n1999), .Y(n3067) );
OAI22X2TS U2534 ( .A0(n2003), .A1(n846), .B0(n1998), .B1(
DP_OP_111J16_123_4462_n680), .Y(n1999) );
XNOR2X4TS U2535 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n3516) );
BUFX3TS U2536 ( .A(n872), .Y(n3734) );
BUFX3TS U2537 ( .A(n871), .Y(n3880) );
BUFX3TS U2538 ( .A(n873), .Y(n3647) );
BUFX3TS U2539 ( .A(n3879), .Y(n3648) );
NAND2X4TS U2540 ( .A(n3322), .B(n1329), .Y(n3323) );
AOI21X2TS U2541 ( .A0(n3320), .A1(n882), .B0(n1344), .Y(n1343) );
AOI2BB2X4TS U2542 ( .B0(n3376), .B1(n3322), .A0N(n620), .A1N(n3340), .Y(
n1346) );
INVX4TS U2543 ( .A(n1206), .Y(n3376) );
NOR2X2TS U2544 ( .A(n883), .B(n3664), .Y(n2883) );
OAI22X2TS U2545 ( .A0(n883), .A1(n868), .B0(n3668), .B1(n3667), .Y(n1686) );
OAI2BB2X2TS U2546 ( .B0(n883), .B1(n3667), .A0N(n3742), .A1N(n455), .Y(n1670) );
XNOR2X4TS U2547 ( .A(DP_OP_111J16_123_4462_n605), .B(
DP_OP_111J16_123_4462_n698), .Y(n2016) );
XNOR2X4TS U2548 ( .A(n885), .B(n1066), .Y(n1997) );
NAND2X2TS U2549 ( .A(n655), .B(n885), .Y(n1372) );
INVX16TS U2550 ( .A(n917), .Y(n886) );
INVX16TS U2551 ( .A(n1006), .Y(n887) );
OAI22X2TS U2552 ( .A0(n2483), .A1(n2482), .B0(n889), .B1(n2480), .Y(n2514)
);
OAI22X2TS U2553 ( .A0(n2483), .A1(n1722), .B0(n2481), .B1(mult_x_23_n472),
.Y(n1732) );
OAI22X2TS U2554 ( .A0(n852), .A1(n1542), .B0(n700), .B1(n1541), .Y(n1549) );
OAI22X4TS U2555 ( .A0(n853), .A1(n1928), .B0(n2842), .B1(n1927), .Y(n1929)
);
OAI22X4TS U2556 ( .A0(n2065), .A1(n2411), .B0(n2068), .B1(n858), .Y(n2078)
);
NOR2BX4TS U2557 ( .AN(n1066), .B(n2411), .Y(n2115) );
BUFX8TS U2558 ( .A(DP_OP_111J16_123_4462_n683), .Y(n2411) );
OAI22X2TS U2559 ( .A0(n2487), .A1(mult_x_23_n480), .B0(n2485), .B1(n1678),
.Y(n1680) );
OAI22X2TS U2560 ( .A0(n2487), .A1(n459), .B0(n729), .B1(n2462), .Y(n2492) );
OAI22X4TS U2561 ( .A0(n847), .A1(n1540), .B0(n891), .B1(n699), .Y(n1486) );
OAI22X2TS U2562 ( .A0(n744), .A1(mult_x_55_n480), .B0(n893), .B1(
mult_x_55_n479), .Y(n1502) );
INVX16TS U2563 ( .A(n2656), .Y(n894) );
OAI22X4TS U2564 ( .A0(n861), .A1(n2057), .B0(n2056), .B1(
DP_OP_111J16_123_4462_n682), .Y(n2066) );
INVX12TS U2565 ( .A(n896), .Y(n897) );
OAI22X4TS U2566 ( .A0(n2024), .A1(n897), .B0(n1566), .B1(n2015), .Y(n2028)
);
OAI22X4TS U2567 ( .A0(n856), .A1(n825), .B0(n2110), .B1(n2025), .Y(n2042) );
BUFX6TS U2568 ( .A(n3390), .Y(n900) );
AOI2BB2X2TS U2569 ( .B0(n3379), .B1(n248), .A0N(n901), .A1N(n3924), .Y(n3337) );
AOI2BB2X2TS U2570 ( .B0(n3379), .B1(n251), .A0N(n901), .A1N(n3921), .Y(n3366) );
AOI2BB2X2TS U2571 ( .B0(n3379), .B1(n255), .A0N(n902), .A1N(n3917), .Y(n3238) );
AOI2BB2X2TS U2572 ( .B0(n3379), .B1(n253), .A0N(n901), .A1N(n3919), .Y(n3381) );
AOI2BB2X2TS U2573 ( .B0(n3384), .B1(n256), .A0N(n902), .A1N(n3916), .Y(n3333) );
AOI2BB2X2TS U2574 ( .B0(n3379), .B1(n250), .A0N(n902), .A1N(n3922), .Y(n3289) );
OR2X4TS U2575 ( .A(n902), .B(n3918), .Y(n1351) );
AOI2BB2X2TS U2576 ( .B0(n3391), .B1(n258), .A0N(n902), .A1N(n3914), .Y(n3317) );
AOI2BB2X2TS U2577 ( .B0(n3379), .B1(n246), .A0N(n902), .A1N(n3955), .Y(n3259) );
AOI2BB2X2TS U2578 ( .B0(n3391), .B1(n260), .A0N(n900), .A1N(n3912), .Y(n3327) );
AOI2BB2X2TS U2579 ( .B0(n3384), .B1(n240), .A0N(n901), .A1N(n3240), .Y(n3242) );
NAND2X4TS U2580 ( .A(n3360), .B(n2587), .Y(n3390) );
AOI21X1TS U2581 ( .A0(n3802), .A1(n3131), .B0(n3130), .Y(n3132) );
CLKBUFX2TS U2582 ( .A(Add_result[10]), .Y(n903) );
CLKBUFX2TS U2583 ( .A(Add_result[12]), .Y(n904) );
OAI22X2TS U2584 ( .A0(n698), .A1(n2377), .B0(n865), .B1(n2387), .Y(n2390) );
CLKXOR2X2TS U2585 ( .A(n1904), .B(n3810), .Y(n1905) );
XOR2X4TS U2586 ( .A(n2453), .B(n3743), .Y(n2443) );
INVX2TS U2587 ( .A(n4016), .Y(n1328) );
NAND2X4TS U2588 ( .A(n3504), .B(n3503), .Y(n3505) );
XNOR2X2TS U2589 ( .A(n2193), .B(n2192), .Y(n3504) );
NAND2X2TS U2590 ( .A(Sgf_normalized_result[4]), .B(Sgf_normalized_result[5]),
.Y(n3213) );
AO22X2TS U2591 ( .A0(n3528), .A1(Sgf_normalized_result[4]), .B0(
final_result_ieee[4]), .B1(n3526), .Y(n186) );
XNOR2X4TS U2592 ( .A(mult_x_55_n570), .B(mult_x_23_n554), .Y(n3136) );
OAI21X4TS U2593 ( .A0(n3799), .A1(n3801), .B0(n3831), .Y(n3830) );
XNOR2X2TS U2594 ( .A(mult_x_55_n566), .B(mult_x_23_n550), .Y(n3148) );
NAND3X2TS U2595 ( .A(n3331), .B(n3330), .C(n3329), .Y(n211) );
INVX2TS U2596 ( .A(rst), .Y(n906) );
OAI2BB1X4TS U2597 ( .A0N(n2542), .A1N(n399), .B0(n909), .Y(n2573) );
XOR2X4TS U2598 ( .A(n838), .B(n910), .Y(n2545) );
XOR2X4TS U2599 ( .A(n911), .B(n2542), .Y(n910) );
XOR2X4TS U2600 ( .A(n667), .B(n915), .Y(n2596) );
XOR2X4TS U2601 ( .A(n2551), .B(n2550), .Y(n915) );
XOR2X4TS U2602 ( .A(n1169), .B(n470), .Y(n2104) );
XOR2X4TS U2603 ( .A(n392), .B(n3886), .Y(n2011) );
INVX2TS U2604 ( .A(n2921), .Y(n919) );
AND2X8TS U2605 ( .A(n2503), .B(n2502), .Y(n2921) );
NAND2X4TS U2606 ( .A(n2559), .B(n2560), .Y(DP_OP_111J16_123_4462_n103) );
XNOR2X4TS U2607 ( .A(n926), .B(n3589), .Y(n925) );
AOI21X4TS U2608 ( .A0(n3624), .A1(n3608), .B0(n3609), .Y(n926) );
NOR2X8TS U2609 ( .A(n1865), .B(n1866), .Y(n2980) );
XOR2X4TS U2610 ( .A(n2824), .B(n928), .Y(Sgf_operation_EVEN1_right_N8) );
AOI21X4TS U2611 ( .A0(n927), .A1(n2821), .B0(n2820), .Y(n928) );
INVX12TS U2612 ( .A(n1064), .Y(n1090) );
OAI22X4TS U2613 ( .A0(n2075), .A1(n856), .B0(n899), .B1(n2074), .Y(n2081) );
XOR2X4TS U2614 ( .A(n1583), .B(n929), .Y(n2074) );
OAI2BB1X4TS U2615 ( .A0N(n931), .A1N(n1929), .B0(n930), .Y(n1972) );
NAND2BX4TS U2616 ( .AN(n813), .B(n932), .Y(n931) );
OAI22X4TS U2617 ( .A0(n1926), .A1(n2842), .B0(n852), .B1(n850), .Y(n933) );
NOR2X8TS U2618 ( .A(n668), .B(n2049), .Y(n2098) );
MXI2X8TS U2619 ( .A(n936), .B(n934), .S0(n3456), .Y(n3464) );
XNOR2X4TS U2620 ( .A(n935), .B(n2331), .Y(n934) );
AO21X4TS U2621 ( .A0(n2330), .A1(n2329), .B0(n2328), .Y(n935) );
XOR2X4TS U2622 ( .A(n937), .B(n2331), .Y(n936) );
AO21X4TS U2623 ( .A0(n2324), .A1(n2323), .B0(n2322), .Y(n937) );
MXI2X8TS U2624 ( .A(n938), .B(n2358), .S0(n3456), .Y(n3463) );
XNOR2X4TS U2625 ( .A(n3453), .B(n3454), .Y(n938) );
OAI2BB1X4TS U2626 ( .A0N(n3456), .A1N(n2268), .B0(n1361), .Y(n3467) );
OAI22X4TS U2627 ( .A0(n2074), .A1(n2108), .B0(n899), .B1(n2073), .Y(n2535)
);
XNOR2X4TS U2628 ( .A(n2090), .B(n686), .Y(n2073) );
NAND2X4TS U2629 ( .A(n2247), .B(n2263), .Y(n2274) );
OR2X8TS U2630 ( .A(n3909), .B(FSM_selector_B[1]), .Y(n1454) );
OAI21X4TS U2631 ( .A0(n497), .A1(n3088), .B0(DP_OP_111J16_123_4462_n103),
.Y(DP_OP_111J16_123_4462_n97) );
NAND2X8TS U2632 ( .A(n3738), .B(mult_x_23_n541), .Y(n2483) );
OAI2BB1X4TS U2633 ( .A0N(n943), .A1N(n2389), .B0(n944), .Y(n2887) );
XOR2X4TS U2634 ( .A(n945), .B(n2388), .Y(n2383) );
XOR2X4TS U2635 ( .A(n2390), .B(n2389), .Y(n945) );
NOR2BX4TS U2636 ( .AN(n2014), .B(n946), .Y(n2034) );
XOR2X4TS U2637 ( .A(n2014), .B(n947), .Y(n2019) );
OAI22X4TS U2638 ( .A0(n704), .A1(DP_OP_111J16_123_4462_n685), .B0(n1566),
.B1(n3890), .Y(n947) );
OAI21X4TS U2639 ( .A0(n981), .A1(n3101), .B0(n3102), .Y(n2099) );
OAI21X4TS U2640 ( .A0(n2186), .A1(n2188), .B0(n2187), .Y(n954) );
AND2X8TS U2641 ( .A(n955), .B(Sgf_operation_EVEN1_Q_left[1]), .Y(n2186) );
XOR2X4TS U2642 ( .A(n1803), .B(Sgf_operation_EVEN1_Q_middle[1]), .Y(n955) );
AOI21X4TS U2643 ( .A0(n2191), .A1(n2192), .B0(n956), .Y(n2188) );
NAND3X8TS U2644 ( .A(n958), .B(n957), .C(n2158), .Y(n2220) );
NAND2X8TS U2645 ( .A(n673), .B(n720), .Y(n957) );
NAND2X8TS U2646 ( .A(n1056), .B(n720), .Y(n958) );
XNOR2X4TS U2647 ( .A(n1902), .B(n959), .Y(n1225) );
XNOR2X4TS U2648 ( .A(n1460), .B(n1903), .Y(n959) );
XOR2X4TS U2649 ( .A(n1241), .B(n3669), .Y(n1460) );
NAND2X8TS U2650 ( .A(n961), .B(n2477), .Y(n2479) );
XOR2X4TS U2651 ( .A(DP_OP_111J16_123_4462_n606), .B(n1093), .Y(n2109) );
XNOR2X4TS U2652 ( .A(n3889), .B(n1093), .Y(n1302) );
NAND2X2TS U2653 ( .A(n655), .B(n686), .Y(n2025) );
XOR2X2TS U2654 ( .A(n1565), .B(n825), .Y(n1646) );
XNOR2X4TS U2655 ( .A(n459), .B(n3675), .Y(n1710) );
NOR2X8TS U2656 ( .A(n1300), .B(n1299), .Y(n966) );
XNOR2X4TS U2657 ( .A(mult_x_23_n545), .B(n3675), .Y(n1664) );
OAI21X4TS U2658 ( .A0(n1992), .A1(n967), .B0(n1188), .Y(n1996) );
XOR2X4TS U2659 ( .A(n968), .B(n3751), .Y(n3231) );
NOR2BX4TS U2660 ( .AN(n1391), .B(n3230), .Y(n969) );
AO21X4TS U2661 ( .A0(n3229), .A1(n882), .B0(n3228), .Y(n970) );
OAI21X4TS U2662 ( .A0(n2584), .A1(n971), .B0(n1089), .Y(n3360) );
XOR2X4TS U2663 ( .A(n1100), .B(n1076), .Y(n2419) );
XOR2X4TS U2664 ( .A(n1090), .B(n1076), .Y(n1594) );
XNOR2X4TS U2665 ( .A(n2090), .B(n396), .Y(n1577) );
XNOR2X4TS U2666 ( .A(n1570), .B(n396), .Y(n2410) );
XOR2X4TS U2667 ( .A(n978), .B(n742), .Y(n2566) );
INVX12TS U2668 ( .A(n980), .Y(n1169) );
XOR2X4TS U2669 ( .A(DP_OP_111J16_123_4462_n728), .B(n836), .Y(n980) );
XOR2X4TS U2670 ( .A(n1970), .B(n1971), .Y(n1375) );
XOR2X1TS U2671 ( .A(n3104), .B(n981), .Y(Sgf_operation_EVEN1_middle_N6) );
XOR2X4TS U2672 ( .A(n982), .B(n2010), .Y(n2007) );
OAI22X4TS U2673 ( .A0(n2011), .A1(n846), .B0(n967), .B1(n2003), .Y(n2010) );
XOR2X4TS U2674 ( .A(n1295), .B(n1293), .Y(n982) );
XOR2X4TS U2675 ( .A(n1169), .B(n1076), .Y(n984) );
OAI22X4TS U2676 ( .A0(n2083), .A1(DP_OP_111J16_123_4462_n680), .B0(n2079),
.B1(n846), .Y(n986) );
XNOR2X4TS U2677 ( .A(n1570), .B(n1077), .Y(n2083) );
NAND2X8TS U2678 ( .A(n994), .B(n992), .Y(n991) );
NAND2BX4TS U2679 ( .AN(n1651), .B(n993), .Y(n992) );
NAND2BX4TS U2680 ( .AN(n1652), .B(n2753), .Y(n994) );
NAND2X4TS U2681 ( .A(DP_OP_111J16_123_4462_n792), .B(n1446), .Y(n996) );
XOR2X4TS U2682 ( .A(n996), .B(n997), .Y(n995) );
OAI2BB1X4TS U2683 ( .A0N(DP_OP_111J16_123_4462_n827), .A1N(n836), .B0(n727),
.Y(n997) );
OAI2BB1X4TS U2684 ( .A0N(n1000), .A1N(n1596), .B0(n1634), .Y(n999) );
XOR2X4TS U2685 ( .A(n1634), .B(n1001), .Y(n2572) );
XOR2X4TS U2686 ( .A(n1645), .B(n1002), .Y(n1001) );
XOR2X4TS U2687 ( .A(n2103), .B(n1076), .Y(n1005) );
OAI22X4TS U2688 ( .A0(n2072), .A1(n890), .B0(n858), .B1(n397), .Y(n2536) );
XOR2X4TS U2689 ( .A(n2103), .B(n1006), .Y(n2072) );
NAND2X8TS U2690 ( .A(n703), .B(n1257), .Y(n1256) );
OAI22X2TS U2691 ( .A0(n1601), .A1(n1710), .B0(n729), .B1(n1709), .Y(n1717)
);
OAI22X2TS U2692 ( .A0(n2487), .A1(n1733), .B0(n729), .B1(n1710), .Y(n1730)
);
NAND2X8TS U2693 ( .A(mult_x_55_n94), .B(n2760), .Y(n2799) );
NAND3X2TS U2694 ( .A(n3312), .B(n3311), .C(n3310), .Y(n209) );
XNOR2X4TS U2695 ( .A(n3043), .B(n3042), .Y(Sgf_operation_Result[22]) );
AOI21X4TS U2696 ( .A0(n3423), .A1(n2218), .B0(n2217), .Y(n2219) );
AOI21X2TS U2697 ( .A0(n882), .A1(n3304), .B0(n3303), .Y(n3305) );
AOI21X4TS U2698 ( .A0(n401), .A1(n2728), .B0(n1245), .Y(mult_x_55_n121) );
AOI21X4TS U2699 ( .A0(n401), .A1(n2779), .B0(n2734), .Y(mult_x_55_n130) );
NAND2X8TS U2700 ( .A(mult_x_55_n557), .B(mult_x_55_n544), .Y(n1493) );
NOR2X8TS U2701 ( .A(n2739), .B(n2738), .Y(DP_OP_111J16_123_4462_n123) );
XNOR2X4TS U2702 ( .A(n1576), .B(n1575), .Y(n1013) );
OAI22X4TS U2703 ( .A0(n1605), .A1(n2481), .B0(n942), .B1(n1019), .Y(n1676)
);
XNOR2X4TS U2704 ( .A(n3661), .B(n571), .Y(n1019) );
NOR2X8TS U2705 ( .A(n2715), .B(n2714), .Y(n2904) );
XOR2X4TS U2706 ( .A(n1022), .B(n1487), .Y(n1488) );
XOR2X4TS U2707 ( .A(n1026), .B(n1023), .Y(n1022) );
NAND2X8TS U2708 ( .A(n1025), .B(n1024), .Y(n1023) );
OR2X4TS U2709 ( .A(n518), .B(n893), .Y(n1025) );
OAI22X4TS U2710 ( .A0(n1492), .A1(n891), .B0(n699), .B1(n847), .Y(n1026) );
NAND2X8TS U2711 ( .A(n1214), .B(mult_x_55_n554), .Y(n1244) );
NOR2X8TS U2712 ( .A(n2560), .B(n2559), .Y(n3088) );
XOR2X4TS U2713 ( .A(n1845), .B(n1441), .Y(n1032) );
NAND2X1TS U2714 ( .A(n1033), .B(n1428), .Y(n2976) );
NAND2X8TS U2715 ( .A(n1039), .B(n711), .Y(add_x_19_n243) );
NAND2X8TS U2716 ( .A(n1042), .B(n2192), .Y(n3052) );
AND2X8TS U2717 ( .A(n3036), .B(n3007), .Y(n3049) );
XOR2X4TS U2718 ( .A(n1794), .B(n1043), .Y(n1799) );
XOR2X4TS U2719 ( .A(n1044), .B(n3682), .Y(n1394) );
NAND2BX4TS U2720 ( .AN(n3725), .B(n1045), .Y(n1044) );
OAI21X4TS U2721 ( .A0(n589), .A1(n663), .B0(n662), .Y(add_x_19_n141) );
NAND2BX4TS U2722 ( .AN(n1051), .B(n1048), .Y(n1439) );
XNOR2X4TS U2723 ( .A(n1058), .B(n1057), .Y(n1051) );
NAND2X8TS U2724 ( .A(n1049), .B(n1046), .Y(n1055) );
NAND2X8TS U2725 ( .A(n1392), .B(n1050), .Y(n1049) );
AND2X8TS U2726 ( .A(n2222), .B(n432), .Y(n1050) );
INVX12TS U2727 ( .A(n432), .Y(n1843) );
NAND2X8TS U2728 ( .A(n2220), .B(n1458), .Y(n1392) );
NAND2X4TS U2729 ( .A(n1837), .B(n1052), .Y(n2154) );
NOR2X8TS U2730 ( .A(n1052), .B(n1837), .Y(n2153) );
OAI2BB1X4TS U2731 ( .A0N(n3626), .A1N(n594), .B0(n1054), .Y(n1053) );
NAND2X8TS U2732 ( .A(n1055), .B(n2224), .Y(n1405) );
NAND2BX4TS U2733 ( .AN(n1123), .B(n1850), .Y(n2224) );
NOR2X4TS U2734 ( .A(n818), .B(n834), .Y(n2160) );
XOR2X4TS U2735 ( .A(n677), .B(n1848), .Y(n1057) );
AOI21X4TS U2736 ( .A0(n1845), .A1(n1335), .B0(n1336), .Y(n1058) );
OAI21X4TS U2737 ( .A0(n693), .A1(n694), .B0(n824), .Y(n1118) );
XOR2X4TS U2738 ( .A(n3827), .B(n3828), .Y(n1839) );
NOR2X8TS U2739 ( .A(n2178), .B(n2182), .Y(n1825) );
NOR2X8TS U2740 ( .A(n1824), .B(n1823), .Y(n2182) );
NOR2X8TS U2741 ( .A(n1822), .B(n1821), .Y(n2178) );
OAI21X4TS U2742 ( .A0(n3500), .A1(n3499), .B0(n3498), .Y(n377) );
NAND2X4TS U2743 ( .A(n2139), .B(n2138), .Y(n3078) );
NOR2X8TS U2744 ( .A(n2737), .B(n2736), .Y(n1065) );
OAI22X4TS U2745 ( .A0(n2056), .A1(n861), .B0(n1652), .B1(
DP_OP_111J16_123_4462_n682), .Y(n2060) );
OR2X8TS U2746 ( .A(n1999), .B(n2000), .Y(n3068) );
OAI22X2TS U2747 ( .A0(n884), .A1(n1997), .B0(n2002), .B1(n866), .Y(n2004) );
XNOR2X4TS U2748 ( .A(n1100), .B(n886), .Y(n1595) );
ADDFHX2TS U2749 ( .A(n868), .B(n1669), .CI(n1670), .CO(n1683), .S(n1742) );
NAND2X2TS U2750 ( .A(n2427), .B(n2426), .Y(n3072) );
XNOR2X2TS U2751 ( .A(n2453), .B(n571), .Y(n1736) );
OAI22X2TS U2752 ( .A0(n2490), .A1(n1736), .B0(n1734), .B1(n835), .Y(n2517)
);
XOR2X4TS U2753 ( .A(n1737), .B(n1075), .Y(n1255) );
XNOR2X4TS U2754 ( .A(n1858), .B(n1401), .Y(n1123) );
NAND2X2TS U2755 ( .A(n2917), .B(n2916), .Y(n2918) );
OAI22X4TS U2756 ( .A0(n1020), .A1(n1186), .B0(mult_x_55_n554), .B1(n1505),
.Y(n1503) );
OAI22X2TS U2757 ( .A0(n2117), .A1(n897), .B0(n2104), .B1(n859), .Y(n2129) );
XNOR2X2TS U2758 ( .A(n2474), .B(n2459), .Y(n2475) );
OAI22X2TS U2759 ( .A0(n2082), .A1(n884), .B0(n2070), .B1(n866), .Y(n2094) );
OAI22X2TS U2760 ( .A0(n1483), .A1(n893), .B0(n744), .B1(n1508), .Y(n1534) );
ADDFHX4TS U2761 ( .A(n2059), .B(n2060), .CI(n2058), .CO(n2053), .S(n2062) );
BUFX20TS U2762 ( .A(mult_x_55_n556), .Y(n2650) );
OAI22X4TS U2763 ( .A0(n2109), .A1(n2110), .B0(n2108), .B1(n2043), .Y(n2114)
);
OA22X2TS U2764 ( .A0(n2075), .A1(n2110), .B0(n1111), .B1(n2108), .Y(n1080)
);
NAND2X2TS U2765 ( .A(n2622), .B(n2617), .Y(n2769) );
AOI2BB2X4TS U2766 ( .B0(n462), .B1(n2618), .A0N(n2627), .A1N(n2659), .Y(
n2616) );
AO22X2TS U2767 ( .A0(n2661), .A1(n2602), .B0(n2601), .B1(n2851), .Y(n2607)
);
OAI22X4TS U2768 ( .A0(n2073), .A1(n856), .B0(n1646), .B1(n899), .Y(n2539) );
OAI22X4TS U2769 ( .A0(n847), .A1(n1932), .B0(n891), .B1(n1517), .Y(n1923) );
INVX12TS U2770 ( .A(n1802), .Y(n1082) );
ADDFHX4TS U2771 ( .A(n2693), .B(n2692), .CI(n2691), .CO(n2683), .S(n2694) );
XOR2X4TS U2772 ( .A(n1083), .B(n719), .Y(n2229) );
OAI21X4TS U2773 ( .A0(n3046), .A1(n3044), .B0(n3047), .Y(n2231) );
XOR2X4TS U2774 ( .A(n1084), .B(n2976), .Y(n1217) );
OAI21X4TS U2775 ( .A0(n821), .A1(n2980), .B0(n2981), .Y(n1084) );
CLKINVX12TS U2776 ( .A(mult_x_55_n72), .Y(n1201) );
NOR2X4TS U2777 ( .A(n3490), .B(n3469), .Y(n2209) );
XOR2X2TS U2778 ( .A(n2658), .B(n894), .Y(n2649) );
OAI22X2TS U2779 ( .A0(n1161), .A1(n713), .B0(n2654), .B1(n2659), .Y(n2689)
);
ADDFHX4TS U2780 ( .A(n2126), .B(n2124), .CI(n2125), .CO(n2131), .S(n2133) );
OAI2BB2X4TS U2781 ( .B0(n1924), .B1(n2655), .A0N(n1518), .A1N(n2851), .Y(
n1934) );
OAI22X2TS U2782 ( .A0(n2652), .A1(mult_x_55_n490), .B0(n2650), .B1(n1504),
.Y(n1539) );
OAI22X4TS U2783 ( .A0(n770), .A1(n2648), .B0(n1962), .B1(mult_x_55_n555),
.Y(n2643) );
XOR2X4TS U2784 ( .A(n2658), .B(mult_x_55_n538), .Y(n2648) );
OAI22X4TS U2785 ( .A0(n770), .A1(n1962), .B0(n1942), .B1(n893), .Y(n1961) );
ADDFHX4TS U2786 ( .A(n2495), .B(n2494), .CI(n2493), .CO(n2523), .S(n2496) );
ADDFHX4TS U2787 ( .A(n1857), .B(n1856), .CI(n1855), .CO(n1862), .S(n1861) );
XOR2X4TS U2788 ( .A(n2103), .B(n825), .Y(n2075) );
NAND2X8TS U2789 ( .A(n1095), .B(n1094), .Y(n1853) );
XOR2X4TS U2790 ( .A(n1849), .B(n3815), .Y(n1850) );
NOR2X4TS U2791 ( .A(n2470), .B(n2469), .Y(n2468) );
XNOR2X4TS U2792 ( .A(n2658), .B(mult_x_55_n446), .Y(n1925) );
BUFX6TS U2793 ( .A(mult_x_55_n71), .Y(n1097) );
XOR2X4TS U2794 ( .A(n2324), .B(n2315), .Y(n1365) );
NOR2X6TS U2795 ( .A(n2241), .B(n2258), .Y(n2292) );
CLKXOR2X2TS U2796 ( .A(n1892), .B(n3806), .Y(n1907) );
BUFX20TS U2797 ( .A(n1476), .Y(n2652) );
XNOR2X2TS U2798 ( .A(n848), .B(n2408), .Y(n2057) );
AO22X4TS U2799 ( .A0(n2645), .A1(n3645), .B0(n3658), .B1(n1509), .Y(n1520)
);
NAND2X4TS U2800 ( .A(n2558), .B(DP_OP_111J16_123_4462_n159), .Y(
DP_OP_111J16_123_4462_n20) );
OAI22X2TS U2801 ( .A0(n1493), .A1(mult_x_55_n505), .B0(n467), .B1(
mult_x_55_n504), .Y(n1935) );
OAI22X4TS U2802 ( .A0(n1633), .A1(n858), .B0(n1593), .B1(n890), .Y(n1631) );
AOI2BB2X2TS U2803 ( .B0(n3391), .B1(n257), .A0N(n902), .A1N(n3915), .Y(n3311) );
XNOR2X2TS U2804 ( .A(n2412), .B(n885), .Y(n2070) );
XNOR2X4TS U2805 ( .A(n3301), .B(n3745), .Y(n3302) );
XNOR2X2TS U2806 ( .A(n2103), .B(n885), .Y(n2037) );
NAND2X4TS U2807 ( .A(Sgf_normalized_result[12]), .B(
Sgf_normalized_result[13]), .Y(n3428) );
NOR2X1TS U2808 ( .A(n3431), .B(n3430), .Y(n3432) );
OAI22X4TS U2809 ( .A0(n2071), .A1(n2411), .B0(n2065), .B1(n857), .Y(n2058)
);
NAND2X4TS U2810 ( .A(n3085), .B(n3883), .Y(DP_OP_111J16_123_4462_n36) );
BUFX20TS U2811 ( .A(n3572), .Y(n1168) );
NAND3X8TS U2812 ( .A(n1108), .B(n1107), .C(n1106), .Y(n1406) );
OAI22X4TS U2813 ( .A0(n1111), .A1(n2110), .B0(n2108), .B1(n1302), .Y(n2087)
);
XOR2X4TS U2814 ( .A(n1169), .B(n1093), .Y(n1111) );
XNOR2X4TS U2815 ( .A(n644), .B(n1456), .Y(n1117) );
XNOR2X4TS U2816 ( .A(n594), .B(n3625), .Y(n1116) );
XNOR2X4TS U2817 ( .A(n3829), .B(DP_OP_111J16_123_4462_n160), .Y(n1115) );
NAND2BX4TS U2818 ( .AN(n1456), .B(n1115), .Y(n1120) );
CLKINVX12TS U2819 ( .A(Sgf_operation_EVEN1_Q_left[5]), .Y(n1814) );
AOI21X4TS U2820 ( .A0(n2181), .A1(n2176), .B0(n1102), .Y(n2175) );
NOR2X8TS U2821 ( .A(n3484), .B(n3403), .Y(n3424) );
XOR2X4TS U2822 ( .A(n2171), .B(n2170), .Y(n2212) );
NOR2X8TS U2823 ( .A(n3451), .B(n3449), .Y(n2218) );
XOR2X4TS U2824 ( .A(n2185), .B(n2184), .Y(n2216) );
XNOR2X4TS U2825 ( .A(n1125), .B(n3029), .Y(Sgf_operation_Result[23]) );
NOR2BX4TS U2826 ( .AN(n1127), .B(n3025), .Y(n1126) );
OAI21X4TS U2827 ( .A0(n3032), .A1(n3030), .B0(n3033), .Y(n3037) );
NOR2BX4TS U2828 ( .AN(n3036), .B(n3024), .Y(n1129) );
NAND2X8TS U2829 ( .A(n2219), .B(n1130), .Y(add_x_19_n272) );
NAND2X8TS U2830 ( .A(n1131), .B(n1400), .Y(n1860) );
OAI2BB1X4TS U2831 ( .A0N(n3057), .A1N(n2204), .B0(n1858), .Y(n1131) );
OAI2BB1X4TS U2832 ( .A0N(n3624), .A1N(n3606), .B0(n1134), .Y(n1133) );
NOR2X8TS U2833 ( .A(n2162), .B(n2161), .Y(n3024) );
OAI22X4TS U2834 ( .A0(n893), .A1(n1135), .B0(n744), .B1(n1925), .Y(n1930) );
OAI22X4TS U2835 ( .A0(n1510), .A1(n893), .B0(n744), .B1(n1135), .Y(n1519) );
XOR2X4TS U2836 ( .A(mult_x_55_n536), .B(mult_x_55_n562), .Y(n2651) );
NAND3X8TS U2837 ( .A(n1138), .B(n2853), .C(n1136), .Y(n1234) );
OAI2BB1X4TS U2838 ( .A0N(n1139), .A1N(n739), .B0(n2946), .Y(n2861) );
OAI22X4TS U2839 ( .A0(n1156), .A1(n2443), .B0(n4008), .B1(n2450), .Y(n2447)
);
OAI22X2TS U2840 ( .A0(n2017), .A1(n846), .B0(n2011), .B1(
DP_OP_111J16_123_4462_n680), .Y(n2012) );
OAI22X2TS U2841 ( .A0(n1020), .A1(n1949), .B0(n891), .B1(n702), .Y(n2685) );
ADDFHX4TS U2842 ( .A(n1516), .B(n1515), .CI(n1514), .CO(n1524), .S(n1974) );
INVX12TS U2843 ( .A(n3691), .Y(n2453) );
NAND2X8TS U2844 ( .A(n1144), .B(n1885), .Y(n2968) );
NAND2X8TS U2845 ( .A(n1164), .B(n718), .Y(n1144) );
OAI22X2TS U2846 ( .A0(n2479), .A1(n1703), .B0(n705), .B1(mult_x_23_n492),
.Y(n1700) );
NAND2X4TS U2847 ( .A(n2451), .B(n1143), .Y(n2859) );
OAI22X2TS U2848 ( .A0(n445), .A1(n1719), .B0(n705), .B1(n1703), .Y(n1705) );
OAI22X2TS U2849 ( .A0(n2055), .A1(n1566), .B0(n1654), .B1(n897), .Y(n2529)
);
ADDFHX4TS U2850 ( .A(n1645), .B(n1644), .CI(n1643), .CO(n1634), .S(n2540) );
BUFX6TS U2851 ( .A(n3909), .Y(n1146) );
OAI22X4TS U2852 ( .A0(n770), .A1(mult_x_55_n479), .B0(mult_x_55_n555), .B1(
n1508), .Y(n1543) );
OR2X6TS U2853 ( .A(n2427), .B(n2426), .Y(n3073) );
OAI21X4TS U2854 ( .A0(DP_OP_111J16_123_4462_n159), .A1(n3097), .B0(n3096),
.Y(DP_OP_111J16_123_4462_n150) );
OAI22X2TS U2855 ( .A0(n1154), .A1(n881), .B0(n2398), .B1(n1071), .Y(n2414)
);
XNOR2X2TS U2856 ( .A(n1565), .B(n885), .Y(n2091) );
NOR2X8TS U2857 ( .A(n2757), .B(DP_OP_111J16_123_4462_n71), .Y(n3085) );
OAI22X4TS U2858 ( .A0(n1583), .A1(n1071), .B0(n1987), .B1(n881), .Y(n2399)
);
XNOR2X2TS U2859 ( .A(mult_x_23_n553), .B(mult_x_55_n569), .Y(n3158) );
ADDFHX2TS U2860 ( .A(n2611), .B(n2610), .CI(n2609), .CO(n2640), .S(n2639) );
INVX2TS U2861 ( .A(n3037), .Y(n3038) );
OAI21X4TS U2862 ( .A0(add_x_19_n271), .A1(n3039), .B0(n3038), .Y(n3043) );
OAI22X2TS U2863 ( .A0(n1154), .A1(n1445), .B0(n2420), .B1(n881), .Y(n2421)
);
NAND2X2TS U2864 ( .A(n2798), .B(n2804), .Y(n2807) );
XNOR2X2TS U2865 ( .A(n2090), .B(n885), .Y(n2105) );
XNOR2X4TS U2866 ( .A(n1170), .B(n2910), .Y(Sgf_operation_EVEN1_left_N9) );
ADDFHX4TS U2867 ( .A(n1622), .B(n1623), .CI(n1621), .CO(n2371), .S(n2438) );
ADDFHX2TS U2868 ( .A(n3740), .B(n2874), .CI(n2873), .CO(n2880), .S(n2891) );
OAI21X4TS U2869 ( .A0(n2935), .A1(n2934), .B0(n2933), .Y(mult_x_23_n39) );
NOR2X8TS U2870 ( .A(n2931), .B(n725), .Y(n2935) );
ADDFHX2TS U2871 ( .A(n2517), .B(n2518), .CI(n2516), .CO(n2508), .S(n2519) );
AO22X2TS U2872 ( .A0(n3515), .A1(Sgf_normalized_result[12]), .B0(
final_result_ieee[12]), .B1(n3527), .Y(n178) );
INVX2TS U2873 ( .A(n2613), .Y(n2602) );
NAND2X2TS U2874 ( .A(n2392), .B(n2391), .Y(n2927) );
NAND2X8TS U2875 ( .A(n1157), .B(n1235), .Y(mult_x_23_n140) );
OAI21X4TS U2876 ( .A0(n3023), .A1(n3021), .B0(n3044), .Y(add_x_19_n216) );
NAND2X2TS U2877 ( .A(n3479), .B(n3478), .Y(n3480) );
OAI22X2TS U2878 ( .A0(n1635), .A1(n899), .B0(n1646), .B1(n2108), .Y(n2571)
);
ADDFHX4TS U2879 ( .A(n2571), .B(n2572), .CI(n2570), .CO(n1655), .S(n2718) );
OAI22X2TS U2880 ( .A0(n445), .A1(n2452), .B0(n705), .B1(n2460), .Y(n2466) );
MX2X6TS U2881 ( .A(Data_MX[14]), .B(n4046), .S0(n2945), .Y(n358) );
NOR2X1TS U2882 ( .A(n3561), .B(n3152), .Y(n3153) );
OAI22X2TS U2883 ( .A0(n2104), .A1(DP_OP_111J16_123_4462_n685), .B0(n2044),
.B1(n1566), .Y(n2113) );
MX2X6TS U2884 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n3062), .Y(n350) );
AOI21X4TS U2885 ( .A0(n1408), .A1(n1898), .B0(n1407), .Y(n1793) );
OAI21X2TS U2886 ( .A0(n3372), .A1(n3235), .B0(n3234), .Y(n3236) );
XNOR2X4TS U2887 ( .A(n3455), .B(n2357), .Y(n2358) );
OAI21X2TS U2888 ( .A0(n3378), .A1(n3293), .B0(n3292), .Y(n3294) );
OAI21X2TS U2889 ( .A0(n632), .A1(n3619), .B0(n3620), .Y(n1893) );
NAND2X4TS U2890 ( .A(n2913), .B(n703), .Y(mult_x_23_n20) );
OAI22X4TS U2891 ( .A0(n445), .A1(n1723), .B0(n705), .B1(n1719), .Y(n1739) );
OAI21X4TS U2892 ( .A0(mult_x_23_n81), .A1(n2926), .B0(n2927), .Y(
mult_x_23_n6) );
AOI21X4TS U2893 ( .A0(n439), .A1(n1073), .B0(n3081), .Y(
DP_OP_111J16_123_4462_n59) );
INVX2TS U2894 ( .A(n2399), .Y(n1984) );
AOI21X4TS U2895 ( .A0(n2324), .A1(n2334), .B0(n2342), .Y(n2279) );
NAND2X2TS U2896 ( .A(n2238), .B(n2256), .Y(n2239) );
INVX4TS U2897 ( .A(n2922), .Y(n2506) );
NOR2X8TS U2898 ( .A(n1756), .B(n1757), .Y(mult_x_55_n71) );
INVX6TS U2899 ( .A(mult_x_55_n58), .Y(n2735) );
AND2X8TS U2900 ( .A(n1436), .B(n1163), .Y(n1435) );
XNOR2X2TS U2901 ( .A(n1090), .B(n885), .Y(n2107) );
OAI22X2TS U2902 ( .A0(n698), .A1(n1664), .B0(mult_x_23_n540), .B1(n1606),
.Y(n1674) );
NAND2X4TS U2903 ( .A(n3091), .B(n3092), .Y(DP_OP_111J16_123_4462_n11) );
XNOR2X2TS U2904 ( .A(n2412), .B(n887), .Y(n1581) );
AOI21X2TS U2905 ( .A0(n2342), .A1(n2341), .B0(n2340), .Y(n2343) );
NAND2X4TS U2906 ( .A(n2207), .B(n2206), .Y(n3470) );
XOR2X4TS U2907 ( .A(n1167), .B(n2496), .Y(n2503) );
XNOR2X4TS U2908 ( .A(n1232), .B(n2498), .Y(n1167) );
OAI22X2TS U2909 ( .A0(n2475), .A1(n445), .B0(n2478), .B1(n705), .Y(n2493) );
OAI21X2TS U2910 ( .A0(mult_x_55_a_8_), .A1(n1475), .B0(mult_x_55_n567), .Y(
n3119) );
INVX2TS U2911 ( .A(n2288), .Y(n2286) );
INVX2TS U2912 ( .A(n2299), .Y(n2285) );
NAND2X4TS U2913 ( .A(n1162), .B(n2903), .Y(mult_x_23_n19) );
CMPR22X2TS U2914 ( .A(n1721), .B(n1720), .CO(n1726), .S(n1738) );
XNOR2X4TS U2915 ( .A(n3373), .B(n3749), .Y(n3374) );
OAI2BB1X4TS U2916 ( .A0N(n882), .A1N(add_x_19_n122), .B0(n3368), .Y(n3369)
);
AO21X2TS U2917 ( .A0(n445), .A1(n705), .B0(n1452), .Y(n1607) );
NAND3X2TS U2918 ( .A(n3338), .B(n3337), .C(n3336), .Y(n200) );
INVX4TS U2919 ( .A(n3257), .Y(n3335) );
OAI21X4TS U2920 ( .A0(n3146), .A1(n3142), .B0(n3143), .Y(n3108) );
ADDFHX4TS U2921 ( .A(n2040), .B(n2039), .CI(n2038), .CO(n2134), .S(n2047) );
NAND2X8TS U2922 ( .A(n1172), .B(n1171), .Y(n2409) );
XNOR2X4TS U2923 ( .A(n3612), .B(n3611), .Y(n1214) );
NAND2X2TS U2924 ( .A(n2347), .B(n2352), .Y(n2355) );
XOR2X4TS U2925 ( .A(mult_x_23_n552), .B(n1174), .Y(n3155) );
MXI2X8TS U2926 ( .A(n1175), .B(n3997), .S0(n3062), .Y(mult_x_55_n568) );
XOR2X4TS U2927 ( .A(n348), .B(n2865), .Y(n3128) );
XNOR2X4TS U2928 ( .A(mult_x_23_n553), .B(n1263), .Y(n3711) );
OR2X4TS U2929 ( .A(n2451), .B(n1143), .Y(n2860) );
XOR2X4TS U2930 ( .A(n2474), .B(n3666), .Y(n1723) );
CLKINVX12TS U2931 ( .A(n3663), .Y(n2474) );
AOI2BB2X4TS U2932 ( .B0(n2661), .B1(n2660), .A0N(n713), .A1N(n2659), .Y(
n2662) );
XNOR2X4TS U2933 ( .A(n2621), .B(mult_x_55_n444), .Y(n2660) );
XNOR2X4TS U2934 ( .A(n2436), .B(n2435), .Y(n1251) );
OAI21X2TS U2935 ( .A0(n2479), .A1(n1667), .B0(n1183), .Y(n1672) );
NAND2BX4TS U2936 ( .AN(n1445), .B(n848), .Y(n1185) );
XNOR2X4TS U2937 ( .A(n854), .B(mult_x_55_n445), .Y(n1186) );
OAI21X4TS U2938 ( .A0(n3185), .A1(n3188), .B0(n3186), .Y(n3069) );
NAND2BX4TS U2939 ( .AN(n1187), .B(n905), .Y(n3186) );
OAI2BB1X4TS U2940 ( .A0N(n3893), .A1N(n1993), .B0(n1189), .Y(n3076) );
NAND2BX4TS U2941 ( .AN(n1992), .B(n740), .Y(n1189) );
BUFX6TS U2942 ( .A(n1405), .Y(n1190) );
OAI22X2TS U2943 ( .A0(n1492), .A1(n847), .B0(mult_x_55_n554), .B1(n1194),
.Y(n1761) );
NAND2X8TS U2944 ( .A(n1198), .B(n2772), .Y(n1779) );
NAND2X8TS U2945 ( .A(n1201), .B(n2773), .Y(n1198) );
NAND2X8TS U2946 ( .A(n1200), .B(n1199), .Y(n2773) );
OA21X4TS U2947 ( .A0(n2562), .A1(n3266), .B0(n2561), .Y(n1206) );
NOR2X4TS U2948 ( .A(n1208), .B(n1207), .Y(n3395) );
NAND2X8TS U2949 ( .A(n1216), .B(n685), .Y(n3013) );
XOR2X4TS U2950 ( .A(n722), .B(n1796), .Y(n1868) );
AND2X8TS U2951 ( .A(n1225), .B(n1905), .Y(n1224) );
OR2X8TS U2952 ( .A(n1225), .B(n1905), .Y(n1223) );
XNOR2X4TS U2953 ( .A(n1226), .B(n3670), .Y(n2961) );
OAI2BB1X4TS U2954 ( .A0N(n1898), .A1N(n1784), .B0(n1227), .Y(n1226) );
NOR2BX4TS U2955 ( .AN(n1783), .B(n1228), .Y(n1227) );
OAI21X4TS U2956 ( .A0(n1231), .A1(n1230), .B0(n1229), .Y(n2504) );
NAND2BX4TS U2957 ( .AN(n1232), .B(n2498), .Y(n1229) );
NOR2BX4TS U2958 ( .AN(n1232), .B(n2498), .Y(n1231) );
NOR2X8TS U2959 ( .A(n2907), .B(n2915), .Y(n1233) );
NAND2X8TS U2960 ( .A(n1318), .B(n2507), .Y(n1317) );
NAND2X8TS U2961 ( .A(n1234), .B(n726), .Y(n1318) );
NOR2X8TS U2962 ( .A(n1237), .B(n1236), .Y(n1235) );
NOR2X8TS U2963 ( .A(n2916), .B(n2907), .Y(n1237) );
NOR2X8TS U2964 ( .A(n2528), .B(n2527), .Y(n2907) );
OAI2BB1X4TS U2965 ( .A0N(n2509), .A1N(n2508), .B0(n1238), .Y(n2866) );
XOR2X4TS U2966 ( .A(n1239), .B(n1240), .Y(n2528) );
XOR2X4TS U2967 ( .A(n2509), .B(n2508), .Y(n1239) );
XNOR2X4TS U2968 ( .A(n1255), .B(n1738), .Y(n1240) );
OAI22X4TS U2969 ( .A0(n1932), .A1(n891), .B0(n1933), .B1(n1244), .Y(n1940)
);
XOR2X4TS U2970 ( .A(n3100), .B(n1247), .Y(Sgf_operation_EVEN1_middle_N7) );
NAND2BX4TS U2971 ( .AN(n3098), .B(n3099), .Y(n1247) );
XOR2X4TS U2972 ( .A(mult_x_55_n444), .B(n3575), .Y(n1963) );
NAND2BX4TS U2973 ( .AN(n2818), .B(n2819), .Y(n1248) );
OAI21X4TS U2974 ( .A0(n2895), .A1(n2904), .B0(n2899), .Y(mult_x_23_n100) );
XNOR2X4TS U2975 ( .A(n1251), .B(n2434), .Y(n2711) );
BUFX16TS U2976 ( .A(n698), .Y(n1252) );
OAI2BB1X4TS U2977 ( .A0N(n1739), .A1N(n1738), .B0(n1254), .Y(n1728) );
AOI21X4TS U2978 ( .A0(n2902), .A1(n1258), .B0(n2750), .Y(mult_x_23_n114) );
NAND2X8TS U2979 ( .A(n1256), .B(n2913), .Y(n1258) );
NOR2X8TS U2980 ( .A(mult_x_23_n78), .B(n2926), .Y(mult_x_23_n7) );
NOR2X8TS U2981 ( .A(n2741), .B(n2740), .Y(mult_x_23_n78) );
NAND2BX4TS U2982 ( .AN(n1260), .B(n3155), .Y(n1259) );
OAI2BB1X4TS U2983 ( .A0N(mult_x_55_n569), .A1N(n1261), .B0(n3150), .Y(n3154)
);
OAI21X1TS U2984 ( .A0(n2940), .A1(n2938), .B0(n2939), .Y(n2856) );
NAND2X8TS U2985 ( .A(n1265), .B(n1264), .Y(n2936) );
NAND2BX4TS U2986 ( .AN(n3475), .B(n3477), .Y(n3442) );
NOR2BX4TS U2987 ( .AN(n3416), .B(n3428), .Y(n1270) );
OAI2BB1X4TS U2988 ( .A0N(n925), .A1N(n1467), .B0(n1271), .Y(n1880) );
OAI21X4TS U2989 ( .A0(n925), .A1(n1467), .B0(n806), .Y(n1271) );
NOR2X8TS U2990 ( .A(n1274), .B(n1273), .Y(n1276) );
NAND2X4TS U2991 ( .A(n1289), .B(n1292), .Y(n2018) );
OAI2BB1X4TS U2992 ( .A0N(n1294), .A1N(n1290), .B0(n2010), .Y(n1289) );
NAND2X2TS U2993 ( .A(n896), .B(n848), .Y(n1294) );
NAND2BX4TS U2994 ( .AN(n2002), .B(n1298), .Y(n1297) );
OAI2BB1X4TS U2995 ( .A0N(n1306), .A1N(n1308), .B0(n2552), .Y(n1305) );
XNOR2X4TS U2996 ( .A(n1307), .B(n2552), .Y(n2595) );
XOR2X4TS U2997 ( .A(n1311), .B(n1308), .Y(n1307) );
AOI2BB2X4TS U2998 ( .B0(n1310), .B1(n1309), .A0N(n2091), .A1N(n884), .Y(
n1308) );
XOR2X4TS U2999 ( .A(n1154), .B(n885), .Y(n2082) );
XNOR2X4TS U3000 ( .A(n1168), .B(mult_x_55_n532), .Y(n1477) );
XOR2X4TS U3001 ( .A(n3572), .B(mult_x_55_n444), .Y(n1541) );
XOR2X4TS U3002 ( .A(n1320), .B(n1319), .Y(n2960) );
OAI2BB1X4TS U3003 ( .A0N(n1092), .A1N(n1871), .B0(n1321), .Y(n1320) );
XOR2X4TS U3004 ( .A(n1323), .B(n1322), .Y(n2161) );
OAI21X4TS U3005 ( .A0(n3617), .A1(n632), .B0(n1324), .Y(n1323) );
XOR2X4TS U3006 ( .A(n1327), .B(add_x_19_n7), .Y(n1326) );
NAND2BX4TS U3007 ( .AN(n3299), .B(n714), .Y(n3301) );
NAND2X4TS U3008 ( .A(n3300), .B(n1329), .Y(n1331) );
OR2X8TS U3009 ( .A(n2562), .B(n582), .Y(n1330) );
ADDFHX4TS U3010 ( .A(n1726), .B(n1725), .CI(n1724), .CO(n1752), .S(n1727) );
INVX2TS U3011 ( .A(n3416), .Y(n3431) );
INVX2TS U3012 ( .A(n2930), .Y(n2931) );
INVX2TS U3013 ( .A(n2935), .Y(mult_x_23_n50) );
OAI21X2TS U3014 ( .A0(n3378), .A1(n1330), .B0(n444), .Y(n3363) );
AOI21X4TS U3015 ( .A0(n3707), .A1(n3708), .B0(n3709), .Y(n1844) );
NAND2X4TS U3016 ( .A(n805), .B(n3084), .Y(DP_OP_111J16_123_4462_n17) );
XOR2X4TS U3017 ( .A(n2919), .B(n2918), .Y(Sgf_operation_EVEN1_left_N8) );
MXI2X4TS U3018 ( .A(Data_MX[18]), .B(n4040), .S0(n745), .Y(n2858) );
OAI21X2TS U3019 ( .A0(n632), .A1(n3602), .B0(n3603), .Y(n1788) );
ADDFX2TS U3020 ( .A(n2841), .B(n2840), .CI(n2839), .CO(n2847), .S(n2793) );
INVX2TS U3021 ( .A(n2802), .Y(n2803) );
INVX2TS U3022 ( .A(n1665), .Y(n1681) );
OA21X4TS U3023 ( .A0(mult_x_55_n59), .A1(n2807), .B0(n2806), .Y(n3650) );
OAI22X4TS U3024 ( .A0(n1987), .A1(n1445), .B0(n2398), .B1(n881), .Y(n2400)
);
NAND2X4TS U3025 ( .A(n2314), .B(n2313), .Y(n2316) );
OAI22X4TS U3026 ( .A0(n2397), .A1(n857), .B0(n2411), .B1(n3892), .Y(n2422)
);
XNOR2X4TS U3027 ( .A(n1565), .B(n886), .Y(n2061) );
ADDFHX4TS U3028 ( .A(n1952), .B(n1951), .CI(n1950), .CO(n1977), .S(n1953) );
XNOR2X4TS U3029 ( .A(mult_x_55_n562), .B(mult_x_55_n445), .Y(n1959) );
NAND3X2TS U3030 ( .A(n3318), .B(n3317), .C(n3316), .Y(n210) );
BUFX20TS U3031 ( .A(n1601), .Y(n2487) );
OAI21X4TS U3032 ( .A0(n2344), .A1(n1096), .B0(n2343), .Y(n3453) );
NOR2X4TS U3033 ( .A(n2333), .B(n2339), .Y(n2341) );
NAND2X8TS U3034 ( .A(n2775), .B(n3501), .Y(n3508) );
NOR2X8TS U3035 ( .A(n3193), .B(FS_Module_state_reg[1]), .Y(n3501) );
AOI21X4TS U3036 ( .A0(n3127), .A1(n1338), .B0(n3126), .Y(n3133) );
OAI21X4TS U3037 ( .A0(n1341), .A1(n635), .B0(n1339), .Y(n260) );
XOR2X4TS U3038 ( .A(n1342), .B(n3744), .Y(n1341) );
NAND2BX4TS U3039 ( .AN(n3319), .B(n1343), .Y(n1342) );
NOR2BX4TS U3040 ( .AN(n1391), .B(n3321), .Y(n1344) );
OAI21X4TS U3041 ( .A0(n3323), .A1(n3372), .B0(n1346), .Y(n3324) );
NAND2BX2TS U3042 ( .AN(n1348), .B(n3393), .Y(n206) );
NAND2BX4TS U3043 ( .AN(n635), .B(n1356), .Y(n1355) );
XNOR2X4TS U3044 ( .A(n3236), .B(n3750), .Y(n1356) );
XOR2X4TS U3045 ( .A(n3472), .B(n1357), .Y(n3473) );
OA21X4TS U3046 ( .A0(n3490), .A1(n3494), .B0(n3491), .Y(n1357) );
AOI2BB2X4TS U3047 ( .B0(n2614), .B1(n462), .A0N(n2613), .A1N(n2659), .Y(
n2615) );
XNOR2X4TS U3048 ( .A(n2296), .B(n2297), .Y(n1362) );
NOR2BX4TS U3049 ( .AN(n1472), .B(n3560), .Y(n1363) );
OAI22X4TS U3050 ( .A0(n1365), .A1(n3456), .B0(n1364), .B1(n442), .Y(n3461)
);
XOR2X4TS U3051 ( .A(n2330), .B(n2316), .Y(n1364) );
XOR2X4TS U3052 ( .A(n2283), .B(n2282), .Y(n1366) );
XOR2X4TS U3053 ( .A(n2279), .B(n2278), .Y(n1367) );
OA21X4TS U3054 ( .A0(n2826), .A1(n2832), .B0(n2827), .Y(n1370) );
OAI21X4TS U3055 ( .A0(n2304), .A1(n2308), .B0(n2305), .Y(n2287) );
NAND2BX4TS U3056 ( .AN(n2629), .B(n2630), .Y(n2764) );
OAI2BB1X4TS U3057 ( .A0N(n1972), .A1N(n402), .B0(n1374), .Y(n2726) );
OAI21X4TS U3058 ( .A0(n1972), .A1(n402), .B0(n1970), .Y(n1374) );
XOR2X4TS U3059 ( .A(n1375), .B(n1972), .Y(n1976) );
XNOR2X4TS U3060 ( .A(n4029), .B(mult_x_23_n546), .Y(n1722) );
XOR2X1TS U3061 ( .A(n2771), .B(n1376), .Y(Sgf_operation_EVEN1_right_N2) );
OAI21X4TS U3062 ( .A0(Op_MY[23]), .A1(FSM_selector_B[1]), .B0(n1146), .Y(
n1377) );
OAI2BB1X4TS U3063 ( .A0N(n1749), .A1N(n1750), .B0(n1378), .Y(n2743) );
XOR2X4TS U3064 ( .A(n1379), .B(n1750), .Y(n2745) );
XOR2X4TS U3065 ( .A(n1749), .B(n1748), .Y(n1379) );
NOR2X8TS U3066 ( .A(n1755), .B(n1754), .Y(n2906) );
XNOR2X4TS U3067 ( .A(n3035), .B(n1381), .Y(Sgf_operation_Result[21]) );
XOR2X4TS U3068 ( .A(n1384), .B(n3679), .Y(n2962) );
OAI21X4TS U3069 ( .A0(n1388), .A1(n635), .B0(n1386), .Y(n258) );
XOR2X4TS U3070 ( .A(n1389), .B(n3746), .Y(n1388) );
NOR2BX4TS U3071 ( .AN(n1391), .B(n3315), .Y(n1390) );
XOR2X4TS U3072 ( .A(n821), .B(n2983), .Y(n2991) );
XOR2X4TS U3073 ( .A(n2989), .B(n1846), .Y(n1441) );
NAND2X8TS U3074 ( .A(n1092), .B(n1399), .Y(n1398) );
NOR2X8TS U3075 ( .A(n583), .B(n593), .Y(n1399) );
XOR2X4TS U3076 ( .A(n1859), .B(n820), .Y(n1401) );
XOR2X4TS U3077 ( .A(n2223), .B(n1404), .Y(n2228) );
XOR2X4TS U3078 ( .A(n1406), .B(n3671), .Y(add_x_19_n51) );
AOI21X4TS U3079 ( .A0(n717), .A1(n1413), .B0(n1412), .Y(n1411) );
XOR2X4TS U3080 ( .A(n1415), .B(n3676), .Y(n2963) );
OAI21X4TS U3081 ( .A0(n612), .A1(n1795), .B0(n3680), .Y(n1416) );
NOR2BX4TS U3082 ( .AN(n1853), .B(n1800), .Y(n1436) );
OAI21X4TS U3083 ( .A0(n1440), .A1(n1843), .B0(n826), .Y(n1438) );
OAI21X4TS U3084 ( .A0(n2957), .A1(n3050), .B0(n2958), .Y(n3016) );
NAND2X4TS U3085 ( .A(n2228), .B(Sgf_operation_EVEN1_Q_left[1]), .Y(n2958) );
XNOR2X4TS U3086 ( .A(n3020), .B(n3019), .Y(Sgf_operation_Result[24]) );
INVX8TS U3087 ( .A(n3015), .Y(n3022) );
OAI22X4TS U3088 ( .A0(n2116), .A1(n859), .B0(n2064), .B1(n897), .Y(n2550) );
XNOR2X4TS U3089 ( .A(n1090), .B(n886), .Y(n2116) );
OAI21X4TS U3090 ( .A0(n3005), .A1(add_x_19_n202), .B0(n3006), .Y(
add_x_19_n197) );
NAND2X2TS U3091 ( .A(n2447), .B(n2446), .Y(n2946) );
NOR2X4TS U3092 ( .A(n2799), .B(n1097), .Y(mult_x_55_n69) );
NOR2X4TS U3093 ( .A(n2799), .B(mult_x_55_n58), .Y(mult_x_55_n56) );
NOR2X8TS U3094 ( .A(n2988), .B(n3010), .Y(add_x_19_n178) );
ADDFHX2TS U3095 ( .A(n1589), .B(n1588), .CI(n1587), .CO(n1982), .S(n1660) );
AOI21X2TS U3096 ( .A0(n2353), .A1(n2352), .B0(n2351), .Y(n2354) );
XNOR2X4TS U3097 ( .A(DP_OP_111J16_123_4462_n606), .B(
DP_OP_111J16_123_4462_n699), .Y(n1998) );
MX2X6TS U3098 ( .A(Data_MX[20]), .B(n4050), .S0(n2945), .Y(n1475) );
AOI2BB2X2TS U3099 ( .B0(n426), .B1(n3893), .A0N(n2122), .A1N(n846), .Y(n2123) );
NAND2X4TS U3100 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n3214) );
OAI22X4TS U3101 ( .A0(n2419), .A1(n860), .B0(n895), .B1(n3891), .Y(n3175) );
OAI21X4TS U3102 ( .A0(n2321), .A1(n2333), .B0(n2338), .Y(n2322) );
MXI2X2TS U3103 ( .A(n3480), .B(n1443), .S0(n443), .Y(n282) );
XNOR2X4TS U3104 ( .A(n2412), .B(n886), .Y(n1654) );
XNOR2X4TS U3105 ( .A(n2412), .B(n1077), .Y(n2121) );
INVX2TS U3106 ( .A(n3036), .Y(n3039) );
NAND2X2TS U3107 ( .A(n2320), .B(n2319), .Y(n2338) );
XOR2X2TS U3108 ( .A(n2293), .B(n2286), .Y(n2290) );
OAI21X2TS U3109 ( .A0(n3143), .A1(n3125), .B0(n1457), .Y(n3126) );
NAND2X4TS U3110 ( .A(n326), .B(n314), .Y(n3143) );
XNOR2X4TS U3111 ( .A(n1099), .B(n886), .Y(n2055) );
XNOR2X4TS U3112 ( .A(n2409), .B(DP_OP_111J16_123_4462_n699), .Y(n2079) );
AOI2BB2X4TS U3113 ( .B0(n2645), .B1(n1509), .A0N(n2647), .A1N(n1494), .Y(
n1495) );
OAI21X4TS U3114 ( .A0(n2896), .A1(n2903), .B0(n2897), .Y(n2750) );
NOR2X4TS U3115 ( .A(n327), .B(n315), .Y(n3125) );
OR2X8TS U3116 ( .A(n2680), .B(n2679), .Y(n2823) );
ADDFHX4TS U3117 ( .A(n1556), .B(n1555), .CI(n1554), .CO(n1557), .S(n1545) );
XNOR2X4TS U3118 ( .A(n393), .B(n1077), .Y(n1992) );
ADDFHX4TS U3119 ( .A(n1490), .B(n1489), .CI(n1488), .CO(n1759), .S(n1561) );
NAND2X6TS U3120 ( .A(n2741), .B(n2740), .Y(mult_x_23_n81) );
OAI22X4TS U3121 ( .A0(n2626), .A1(n2624), .B0(n844), .B1(n2612), .Y(n2632)
);
XNOR2X4TS U3122 ( .A(n3653), .B(mult_x_55_n448), .Y(n2612) );
XNOR2X4TS U3123 ( .A(n3653), .B(mult_x_55_n449), .Y(n2624) );
XNOR2X2TS U3124 ( .A(n2302), .B(n2301), .Y(n2303) );
OAI21X2TS U3125 ( .A0(n2300), .A1(n2299), .B0(n2298), .Y(n2302) );
XNOR2X4TS U3126 ( .A(DP_OP_111J16_123_4462_n605), .B(n2408), .Y(n1651) );
NAND2X4TS U3127 ( .A(n2212), .B(n1148), .Y(n3485) );
NAND2X4TS U3128 ( .A(n2715), .B(n2714), .Y(n2899) );
NOR2X4TS U3129 ( .A(n2336), .B(n2332), .Y(n2350) );
INVX6TS U3130 ( .A(n3266), .Y(n3291) );
AOI21X4TS U3131 ( .A0(n630), .A1(n3771), .B0(n3772), .Y(n3266) );
NAND2X4TS U3132 ( .A(n2211), .B(n2210), .Y(n3481) );
NOR2X6TS U3133 ( .A(n2095), .B(n2096), .Y(n2546) );
OAI22X2TS U3134 ( .A0(n2652), .A1(n2605), .B0(n2650), .B1(n3660), .Y(n2666)
);
XNOR2X4TS U3135 ( .A(mult_x_55_n562), .B(mult_x_55_n449), .Y(n2605) );
OR2X2TS U3136 ( .A(n2878), .B(n2877), .Y(n2879) );
MXI2X2TS U3137 ( .A(n3466), .B(n3903), .S0(n3559), .Y(n274) );
INVX4TS U3138 ( .A(n3465), .Y(n3466) );
XNOR2X4TS U3139 ( .A(n1948), .B(n3655), .Y(n1540) );
ADDFHX4TS U3140 ( .A(n1533), .B(n1532), .CI(n1531), .CO(n1546), .S(n1525) );
NAND2X4TS U3141 ( .A(n2748), .B(n2749), .Y(n2897) );
XNOR2X2TS U3142 ( .A(n1147), .B(n868), .Y(n1701) );
NAND2BX2TS U3143 ( .AN(Op_MY[12]), .B(n811), .Y(n1704) );
XNOR2X4TS U3144 ( .A(n1147), .B(mult_x_23_n517), .Y(n2377) );
XNOR2X4TS U3145 ( .A(n811), .B(n3666), .Y(n1606) );
XNOR2X4TS U3146 ( .A(n1147), .B(n571), .Y(n1603) );
XNOR2X4TS U3147 ( .A(n1147), .B(n3665), .Y(n1613) );
NAND2BX2TS U3148 ( .AN(Op_MY[12]), .B(n516), .Y(n2462) );
XNOR2X4TS U3149 ( .A(n516), .B(Op_MY[16]), .Y(n1733) );
XNOR2X4TS U3150 ( .A(n516), .B(n3666), .Y(n1709) );
XNOR2X4TS U3151 ( .A(n516), .B(n3667), .Y(n2473) );
XNOR2X4TS U3152 ( .A(n516), .B(mult_x_23_n517), .Y(n1678) );
XNOR2X4TS U3153 ( .A(n516), .B(n3664), .Y(n1677) );
NOR2X6TS U3154 ( .A(n2998), .B(n512), .Y(n3010) );
NAND2X4TS U3155 ( .A(n2999), .B(n3009), .Y(add_x_19_n13) );
INVX4TS U3156 ( .A(n3010), .Y(n2999) );
XNOR2X4TS U3157 ( .A(n3573), .B(mult_x_55_n530), .Y(n1508) );
ADDFHX2TS U3158 ( .A(n1718), .B(n1717), .CI(n1716), .CO(n1746), .S(n1729) );
MXI2X4TS U3159 ( .A(n2311), .B(n2310), .S0(n3456), .Y(n3560) );
ADDFHX4TS U3160 ( .A(n1524), .B(n1523), .CI(n1522), .CO(n1526), .S(n2722) );
ADDFHX2TS U3161 ( .A(n1500), .B(n1499), .CI(n1498), .CO(n1527), .S(n1522) );
XOR2X4TS U3162 ( .A(n1870), .B(n3586), .Y(n2215) );
AOI21X4TS U3163 ( .A0(n3624), .A1(n3599), .B0(n1869), .Y(n1870) );
NOR2X8TS U3164 ( .A(n3021), .B(n3046), .Y(n2232) );
NOR2X8TS U3165 ( .A(n2229), .B(n515), .Y(n3021) );
ADDFHX4TS U3166 ( .A(n2078), .B(n2077), .CI(n2076), .CO(n2080), .S(n2549) );
ADDFHX4TS U3167 ( .A(n1657), .B(n1656), .CI(n1655), .CO(n1662), .S(n2567) );
ADDFHX2TS U3168 ( .A(n1539), .B(n1538), .CI(n1537), .CO(n1555), .S(n1532) );
ADDFHX4TS U3169 ( .A(n2524), .B(n2523), .CI(n2522), .CO(n2525), .S(n2505) );
OR2X8TS U3170 ( .A(n2876), .B(n2875), .Y(n2932) );
NAND2BX2TS U3171 ( .AN(Op_MY[12]), .B(n1153), .Y(n1735) );
XNOR2X4TS U3172 ( .A(n3661), .B(n3664), .Y(n1614) );
XNOR2X4TS U3173 ( .A(n3661), .B(mult_x_23_n517), .Y(n1602) );
XNOR2X4TS U3174 ( .A(n3661), .B(n3667), .Y(n2480) );
XNOR2X4TS U3175 ( .A(n1153), .B(Op_MY[16]), .Y(n1702) );
INVX4TS U3176 ( .A(n2796), .Y(n2777) );
NOR2X4TS U3177 ( .A(n2797), .B(n2796), .Y(mult_x_55_n87) );
OAI21X2TS U3178 ( .A0(n3800), .A1(n3803), .B0(n3804), .Y(n3802) );
ADDFHX4TS U3179 ( .A(n1639), .B(n1638), .CI(n1637), .CO(n1659), .S(n1661) );
ADDFHX4TS U3180 ( .A(n1553), .B(n1552), .CI(n1551), .CO(n1560), .S(n1558) );
XNOR2X4TS U3181 ( .A(n2658), .B(mult_x_55_n444), .Y(n1510) );
AOI21X4TS U3182 ( .A0(DP_OP_111J16_123_4462_n720), .A1(
DP_OP_111J16_123_4462_n751), .B0(DP_OP_111J16_123_4462_n752), .Y(n1576) );
XNOR2X4TS U3183 ( .A(n1090), .B(n887), .Y(n1647) );
NAND2X2TS U3184 ( .A(n707), .B(Op_MY[24]), .Y(n2236) );
XOR2X4TS U3185 ( .A(n3575), .B(mult_x_55_n529), .Y(n1509) );
NOR2X4TS U3186 ( .A(mult_x_23_n525), .B(n313), .Y(n3163) );
MX2X6TS U3187 ( .A(Data_MY[1]), .B(n4030), .S0(n2945), .Y(n313) );
NAND2X4TS U3188 ( .A(n2230), .B(n1165), .Y(n3047) );
XNOR2X4TS U3189 ( .A(DP_OP_111J16_123_4462_n606), .B(
DP_OP_111J16_123_4462_n698), .Y(n2008) );
ADDFHX4TS U3190 ( .A(n2788), .B(n2787), .CI(n2786), .CO(n2794), .S(n1777) );
NOR2X2TS U3191 ( .A(n3805), .B(n3797), .Y(n3131) );
NOR2X4TS U3192 ( .A(n331), .B(n319), .Y(n3797) );
AOI21X4TS U3193 ( .A0(n3778), .A1(n3779), .B0(add_x_19_n205), .Y(n3244) );
NOR2X4TS U3194 ( .A(n624), .B(n3795), .Y(n3304) );
NOR2X4TS U3195 ( .A(n3795), .B(n590), .Y(n3233) );
INVX6TS U3196 ( .A(n2616), .Y(n2622) );
XOR2X4TS U3197 ( .A(n2175), .B(n2174), .Y(n2214) );
XNOR2X4TS U3198 ( .A(DP_OP_111J16_123_4462_n605), .B(
DP_OP_111J16_123_4462_n695), .Y(n2065) );
XNOR2X4TS U3199 ( .A(n393), .B(DP_OP_111J16_123_4462_n698), .Y(n2002) );
ADDFHX4TS U3200 ( .A(n2744), .B(n2743), .CI(n2742), .CO(n1694), .S(n2749) );
XNOR2X4TS U3201 ( .A(n2653), .B(n4026), .Y(n2628) );
ADDFHX2TS U3202 ( .A(n1549), .B(n1548), .CI(n1550), .CO(n1559), .S(n1554) );
OAI21X4TS U3203 ( .A0(n3484), .A1(n3481), .B0(n3485), .Y(n3423) );
XNOR2X4TS U3204 ( .A(n2409), .B(DP_OP_111J16_123_4462_n695), .Y(n2397) );
ADDFHX2TS U3205 ( .A(n1482), .B(n1481), .CI(n1480), .CO(n1489), .S(n1553) );
NOR2X4TS U3206 ( .A(n2799), .B(mult_x_55_n47), .Y(mult_x_55_n45) );
ADDFHX4TS U3207 ( .A(n1978), .B(n1977), .CI(n1976), .CO(n2729), .S(n2707) );
NAND2X4TS U3208 ( .A(n2640), .B(n2641), .Y(n2827) );
XNOR2X4TS U3209 ( .A(n1570), .B(n885), .Y(n2069) );
XOR2X4TS U3210 ( .A(n2252), .B(n2251), .Y(n2253) );
INVX2TS U3211 ( .A(n2266), .Y(n2251) );
NAND2X4TS U3212 ( .A(n2679), .B(n2680), .Y(n2822) );
NAND2X4TS U3213 ( .A(n2259), .B(n2258), .Y(n2298) );
NAND2X2TS U3214 ( .A(n3045), .B(n3044), .Y(add_x_19_n18) );
NOR2X4TS U3215 ( .A(n1996), .B(n905), .Y(n3185) );
XNOR2X4TS U3216 ( .A(DP_OP_111J16_123_4462_n606), .B(n2408), .Y(n1652) );
NOR2X8TS U3217 ( .A(n2557), .B(n2556), .Y(DP_OP_111J16_123_4462_n158) );
INVX6TS U3218 ( .A(n3227), .Y(n3368) );
XNOR2X4TS U3219 ( .A(DP_OP_111J16_123_4462_n606), .B(n886), .Y(n2024) );
XNOR2X4TS U3220 ( .A(n1168), .B(mult_x_55_n531), .Y(n1491) );
XNOR2X4TS U3221 ( .A(n1168), .B(mult_x_55_n530), .Y(n1764) );
XOR2X4TS U3222 ( .A(n1168), .B(mult_x_55_n449), .Y(n1927) );
XOR2X4TS U3223 ( .A(n1168), .B(n4026), .Y(n1497) );
XOR2X4TS U3224 ( .A(n1168), .B(mult_x_55_n448), .Y(n1513) );
XNOR2X4TS U3225 ( .A(n1168), .B(mult_x_55_n529), .Y(n1773) );
XOR2X4TS U3226 ( .A(n3572), .B(mult_x_55_n445), .Y(n1542) );
ADDFHX2TS U3227 ( .A(n2633), .B(n2632), .CI(n2631), .CO(n2638), .S(n2637) );
OAI21X4TS U3228 ( .A0(n2912), .A1(mult_x_23_n97), .B0(n2911), .Y(
mult_x_23_n88) );
OAI22X2TS U3229 ( .A0(n770), .A1(n1942), .B0(n1925), .B1(mult_x_55_n555),
.Y(n1945) );
XOR2X4TS U3230 ( .A(n2658), .B(mult_x_55_n536), .Y(n1942) );
XOR2X4TS U3231 ( .A(n2967), .B(n2966), .Y(n2985) );
ADDFHX4TS U3232 ( .A(n2384), .B(n2382), .CI(n2383), .CO(n2392), .S(n2740) );
NOR2X4TS U3233 ( .A(n850), .B(n3581), .Y(n2845) );
NOR2X4TS U3234 ( .A(n3407), .B(n3397), .Y(n3416) );
NAND2X2TS U3235 ( .A(Sgf_normalized_result[8]), .B(Sgf_normalized_result[9]),
.Y(n3407) );
NAND2X4TS U3236 ( .A(n2317), .B(n2319), .Y(n2349) );
NAND2X4TS U3237 ( .A(n2986), .B(n807), .Y(n3001) );
XOR2X4TS U3238 ( .A(n579), .B(n2970), .Y(n2986) );
NAND2X4TS U3239 ( .A(n2255), .B(n2254), .Y(n2308) );
OR2X8TS U3240 ( .A(n2678), .B(n2677), .Y(n2821) );
ADDFHX4TS U3241 ( .A(n2673), .B(n2672), .CI(n2671), .CO(n2679), .S(n2678) );
XNOR2X4TS U3242 ( .A(n393), .B(DP_OP_111J16_123_4462_n697), .Y(n2015) );
NOR2X8TS U3243 ( .A(n2207), .B(n2206), .Y(n3469) );
OAI21X4TS U3244 ( .A0(n2240), .A1(n2306), .B0(n2239), .Y(n2284) );
XOR2X4TS U3245 ( .A(n1948), .B(n3654), .Y(n1933) );
AND2X8TS U3246 ( .A(n3513), .B(n3512), .Y(n3525) );
MXI2X4TS U3247 ( .A(n3105), .B(n455), .S0(n3129), .Y(n326) );
MXI2X4TS U3248 ( .A(n3458), .B(n3457), .S0(n3456), .Y(n3460) );
NOR2X2TS U3249 ( .A(n3453), .B(n3454), .Y(n3458) );
ADDFHX4TS U3250 ( .A(n2675), .B(n2676), .CI(n2674), .CO(n2677), .S(n2641) );
ADDFHX4TS U3251 ( .A(n2699), .B(n2698), .CI(n2697), .CO(n2700), .S(n2680) );
ADDFHX4TS U3252 ( .A(n2713), .B(n2712), .CI(n2711), .CO(n2714), .S(n1695) );
ADDFHX4TS U3253 ( .A(n2034), .B(n2033), .CI(n1464), .CO(n2035), .S(n2022) );
ADDFHX4TS U3254 ( .A(n1753), .B(n1752), .CI(n1751), .CO(n1754), .S(n1741) );
NOR2X4TS U3255 ( .A(n2622), .B(n2617), .Y(n2768) );
CMPR22X2TS U3256 ( .A(n2492), .B(n2491), .CO(n2497), .S(n2499) );
OAI22X2TS U3257 ( .A0(n2649), .A1(n744), .B0(n2648), .B1(mult_x_55_n555),
.Y(n2669) );
ADDFHX4TS U3258 ( .A(n1982), .B(n1981), .CI(n1980), .CO(n3090), .S(n1697) );
ADDFHX2TS U3259 ( .A(n1763), .B(n1762), .CI(n1761), .CO(n1772), .S(n1765) );
INVX8TS U3260 ( .A(n2090), .Y(n1987) );
XOR2X4TS U3261 ( .A(n3695), .B(n3741), .Y(n1667) );
XOR2X4TS U3262 ( .A(DP_OP_111J16_123_4462_n625), .B(n403), .Y(n1571) );
INVX12TS U3263 ( .A(n3394), .Y(n3456) );
XNOR2X4TS U3264 ( .A(n1565), .B(n887), .Y(n1593) );
XOR2X4TS U3265 ( .A(n1450), .B(mult_x_23_n524), .Y(n2486) );
NOR2X4TS U3266 ( .A(n2238), .B(n2256), .Y(n2240) );
CMPR22X2TS U3267 ( .A(n2472), .B(n2471), .CO(n2516), .S(n2524) );
NAND2X4TS U3268 ( .A(n2956), .B(n1074), .Y(n3030) );
NOR2X4TS U3269 ( .A(n2799), .B(n3651), .Y(mult_x_55_n32) );
XOR2X4TS U3270 ( .A(n1894), .B(n3583), .Y(n2163) );
AOI21X2TS U3271 ( .A0(n3624), .A1(n3593), .B0(n1893), .Y(n1894) );
OAI21X4TS U3272 ( .A0(n3451), .A1(n3448), .B0(n3452), .Y(n2217) );
NOR2X8TS U3273 ( .A(n2441), .B(n2440), .Y(mult_x_23_n94) );
ADDFHX4TS U3274 ( .A(n2439), .B(n2437), .CI(n2438), .CO(n1625), .S(n2440) );
INVX6TS U3275 ( .A(n2784), .Y(n2820) );
XOR2X4TS U3276 ( .A(n3594), .B(n3595), .Y(n2194) );
XOR2X4TS U3277 ( .A(n2658), .B(mult_x_55_n537), .Y(n1962) );
OR2X8TS U3278 ( .A(n2894), .B(n2893), .Y(n3736) );
NOR2X8TS U3279 ( .A(n2230), .B(n1165), .Y(n3046) );
NAND2X2TS U3280 ( .A(n3049), .B(n3015), .Y(n3017) );
ADDFHX4TS U3281 ( .A(n2724), .B(n2723), .CI(n2722), .CO(n2360), .S(n2732) );
ADDFHX4TS U3282 ( .A(n2132), .B(n2131), .CI(n2130), .CO(n2138), .S(n2137) );
ADDFHX4TS U3283 ( .A(n2373), .B(n2372), .CI(n2371), .CO(n2741), .S(n1624) );
ADDFHX4TS U3284 ( .A(n2710), .B(n2708), .CI(n2709), .CO(n2441), .S(n2715) );
ADDFHX4TS U3285 ( .A(n2597), .B(n2596), .CI(n2595), .CO(n2598), .S(n2557) );
NOR2X8TS U3286 ( .A(n2755), .B(n2756), .Y(DP_OP_111J16_123_4462_n71) );
ADDFHX4TS U3287 ( .A(n1760), .B(n1759), .CI(n1758), .CO(n1769), .S(n1757) );
NAND2X4TS U3288 ( .A(n2557), .B(n2556), .Y(DP_OP_111J16_123_4462_n159) );
MXI2X4TS U3289 ( .A(n3904), .B(n4070), .S0(n569), .Y(n2271) );
OAI2BB2X2TS U3290 ( .B0(n2647), .B1(n2646), .A0N(n2645), .A1N(n3644), .Y(
n2670) );
XOR2X4TS U3291 ( .A(n3575), .B(mult_x_55_n445), .Y(n2646) );
CMPR22X2TS U3292 ( .A(n1687), .B(n1686), .CO(n1688), .S(n1713) );
OAI21X2TS U3293 ( .A0(n3668), .A1(Op_MY[12]), .B0(n883), .Y(n1687) );
ADDFHX4TS U3294 ( .A(n2521), .B(n2520), .CI(n2519), .CO(n2527), .S(n2526) );
XNOR2X4TS U3295 ( .A(n3624), .B(n3610), .Y(n2206) );
ADDFHX4TS U3296 ( .A(n2555), .B(n2554), .CI(n2553), .CO(n2556), .S(n2139) );
XOR2X4TS U3297 ( .A(n1948), .B(mult_x_55_n536), .Y(n1932) );
ADDFHX2TS U3298 ( .A(n2501), .B(n2500), .CI(n2499), .CO(n2502), .S(n2470) );
XNOR2X4TS U3299 ( .A(DP_OP_111J16_123_4462_n607), .B(n2408), .Y(n2056) );
BUFX20TS U3300 ( .A(DP_OP_111J16_123_4462_n694), .Y(n2408) );
NOR3X4TS U3301 ( .A(n3927), .B(FSM_selector_B[1]), .C(FSM_selector_B[0]),
.Y(n2332) );
ADDFHX4TS U3302 ( .A(n2418), .B(n2416), .CI(n2417), .CO(n2427), .S(n2424) );
ADDFHX4TS U3303 ( .A(n2718), .B(n2717), .CI(n2716), .CO(n2579), .S(n2739) );
ADDFHX2TS U3304 ( .A(n2467), .B(n2466), .CI(n2465), .CO(n2469), .S(n2458) );
CMPR22X2TS U3305 ( .A(n2663), .B(n2664), .CO(n2688), .S(n2673) );
AOI21X4TS U3306 ( .A0(n3069), .A1(n3068), .B0(n2001), .Y(n3172) );
OAI21X4TS U3307 ( .A0(n3780), .A1(n3781), .B0(n604), .Y(n3227) );
ADDFHX4TS U3308 ( .A(n1660), .B(n1659), .CI(n1658), .CO(n1696), .S(n2560) );
ADDFHX4TS U3309 ( .A(n1562), .B(n1560), .CI(n1561), .CO(n1756), .S(n2758) );
AOI21X4TS U3310 ( .A0(n2246), .A1(n2284), .B0(n2245), .Y(n2345) );
NAND2X4TS U3311 ( .A(n1454), .B(n2276), .Y(n2317) );
ADDFHX4TS U3312 ( .A(n2594), .B(n2593), .CI(n2592), .CO(n2095), .S(n2599) );
NAND2X8TS U3313 ( .A(n625), .B(add_x_19_n122), .Y(n3339) );
OR2X8TS U3314 ( .A(n1778), .B(n1777), .Y(n2798) );
ADDFHX4TS U3315 ( .A(n1772), .B(n1771), .CI(n1770), .CO(n1778), .S(n1768) );
BUFX20TS U3316 ( .A(n3657), .Y(n2658) );
ADDFHX4TS U3317 ( .A(n1955), .B(n1954), .CI(n1953), .CO(n2706), .S(n2705) );
OR2X8TS U3318 ( .A(n2425), .B(n2424), .Y(n3086) );
ADDFHX4TS U3319 ( .A(n2048), .B(n2046), .CI(n2047), .CO(n2049), .S(n2036) );
ADDFHX4TS U3320 ( .A(n1527), .B(n1526), .CI(n1525), .CO(n2363), .S(n2361) );
ADDFHX4TS U3321 ( .A(n2395), .B(n2394), .CI(n2393), .CO(n2756), .S(n3089) );
ADDFHX4TS U3322 ( .A(n2747), .B(n2746), .CI(n2745), .CO(n2748), .S(n1755) );
ADDFHX4TS U3323 ( .A(n2696), .B(n2695), .CI(n2694), .CO(n2702), .S(n2701) );
ADDFHX4TS U3324 ( .A(n2683), .B(n2684), .CI(n2682), .CO(n2704), .S(n2703) );
AOI21X4TS U3325 ( .A0(n2262), .A1(n2287), .B0(n2261), .Y(n2356) );
NOR2X4TS U3326 ( .A(n2272), .B(n2271), .Y(n2275) );
NAND2X2TS U3327 ( .A(n2269), .B(n2271), .Y(n2280) );
NOR2X4TS U3328 ( .A(n2269), .B(n2271), .Y(n2281) );
OAI21X4TS U3329 ( .A0(DP_OP_111J16_123_4462_n94), .A1(n3093), .B0(n3092),
.Y(DP_OP_111J16_123_4462_n83) );
NOR2X8TS U3330 ( .A(n3090), .B(n3089), .Y(n3093) );
ADDFHX4TS U3331 ( .A(n2569), .B(n2568), .CI(n2567), .CO(n2369), .S(n2580) );
NOR2X8TS U3332 ( .A(n2986), .B(n807), .Y(n3000) );
MXI2X4TS U3333 ( .A(n3908), .B(n3898), .S0(FSM_selector_A), .Y(n2258) );
AOI21X4TS U3334 ( .A0(n3624), .A1(n3604), .B0(n3605), .Y(n1794) );
ADDFHX4TS U3335 ( .A(n1663), .B(n1662), .CI(n1661), .CO(n2559), .S(n2370) );
XOR2X4TS U3336 ( .A(n3596), .B(n3597), .Y(n3503) );
OAI22X2TS U3337 ( .A0(n2625), .A1(n2626), .B0(n844), .B1(n2624), .Y(n2634)
);
MXI2X4TS U3338 ( .A(n3905), .B(n3899), .S0(FSM_selector_A), .Y(n2260) );
ADDFHX4TS U3339 ( .A(n1729), .B(n1728), .CI(n1727), .CO(n1740), .S(n2867) );
ADDFHX4TS U3340 ( .A(n1559), .B(n1558), .CI(n1557), .CO(n2759), .S(n2364) );
ADDFHX4TS U3341 ( .A(n1547), .B(n1546), .CI(n1545), .CO(n2365), .S(n2362) );
XOR2X4TS U3342 ( .A(n1789), .B(n3585), .Y(n2955) );
XNOR2X1TS U3343 ( .A(n1174), .B(n3631), .Y(n1442) );
INVX2TS U3344 ( .A(DP_OP_111J16_123_4462_n880), .Y(n2943) );
OR2X8TS U3345 ( .A(n1861), .B(n1860), .Y(n1455) );
OAI22X1TS U3346 ( .A0(n2122), .A1(DP_OP_111J16_123_4462_n680), .B0(n2121),
.B1(n846), .Y(n1463) );
CLKBUFX3TS U3347 ( .A(n4057), .Y(n3977) );
BUFX3TS U3348 ( .A(n3649), .Y(n3979) );
INVX2TS U3349 ( .A(n2316), .Y(n2315) );
INVX2TS U3350 ( .A(n2334), .Y(n2318) );
NAND2X2TS U3351 ( .A(n2200), .B(n2201), .Y(n2202) );
NAND2X1TS U3352 ( .A(n2154), .B(n2155), .Y(n2156) );
INVX2TS U3353 ( .A(n3291), .Y(n3283) );
INVX8TS U3354 ( .A(n3262), .Y(n3379) );
INVX2TS U3355 ( .A(n2811), .Y(n2813) );
INVX2TS U3356 ( .A(n2831), .Y(n2833) );
INVX2TS U3357 ( .A(n2808), .Y(n2810) );
INVX2TS U3358 ( .A(mult_x_23_n78), .Y(n2920) );
OAI21X2TS U3359 ( .A0(n2835), .A1(n2831), .B0(n2832), .Y(n2830) );
INVX2TS U3360 ( .A(DP_OP_111J16_123_4462_n891), .Y(n3639) );
INVX2TS U3361 ( .A(n3055), .Y(add_x_19_n47) );
XOR2X1TS U3362 ( .A(n3114), .B(n3113), .Y(n3843) );
XOR2X1TS U3363 ( .A(n3162), .B(mult_x_55_n565), .Y(n3872) );
NOR2X8TS U3364 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n2775) );
MX2X6TS U3365 ( .A(Data_MY[21]), .B(n4045), .S0(n879), .Y(n333) );
BUFX20TS U3366 ( .A(n3508), .Y(n3062) );
NAND2X2TS U3367 ( .A(mult_x_23_n518), .B(n320), .Y(n3801) );
MX2X4TS U3368 ( .A(Data_MY[22]), .B(Op_MY[22]), .S0(n879), .Y(mult_x_23_n516) );
MX2X4TS U3369 ( .A(Data_MY[10]), .B(n3539), .S0(n746), .Y(n322) );
NAND2X2TS U3370 ( .A(mult_x_23_n516), .B(n322), .Y(n3852) );
INVX2TS U3371 ( .A(n323), .Y(n1468) );
MX2X6TS U3372 ( .A(Data_MY[4]), .B(n1470), .S0(n3129), .Y(n316) );
MX2X6TS U3373 ( .A(Data_MY[2]), .B(n4035), .S0(n745), .Y(n314) );
MX2X6TS U3374 ( .A(Data_MY[13]), .B(n3533), .S0(n2945), .Y(mult_x_23_n525)
);
NAND2X4TS U3376 ( .A(n2584), .B(n1089), .Y(n1471) );
AND2X8TS U3377 ( .A(n1471), .B(n2583), .Y(n3459) );
INVX2TS U3378 ( .A(n1474), .Y(n3565) );
INVX2TS U3379 ( .A(n1475), .Y(n3566) );
INVX2TS U3380 ( .A(n322), .Y(n3568) );
AO21X1TS U3382 ( .A0(n1476), .A1(n863), .B0(mult_x_55_n562), .Y(n1484) );
OAI22X1TS U3383 ( .A0(n852), .A1(n1477), .B0(n2842), .B1(n1491), .Y(n1490)
);
OAI22X1TS U3384 ( .A0(n852), .A1(n1491), .B0(n700), .B1(n1764), .Y(n1767) );
OAI22X1TS U3385 ( .A0(n2652), .A1(n1496), .B0(n863), .B1(mult_x_55_n490),
.Y(n1500) );
OAI22X1TS U3386 ( .A0(n1476), .A1(n1512), .B0(n863), .B1(n1496), .Y(n1514)
);
XNOR2X4TS U3387 ( .A(n672), .B(n3581), .Y(n1924) );
CLKINVX6TS U3388 ( .A(DP_OP_111J16_123_4462_n773), .Y(n1564) );
OAI22X1TS U3389 ( .A0(n1579), .A1(n856), .B0(n1582), .B1(n899), .Y(n1587) );
CLKINVX6TS U3390 ( .A(DP_OP_111J16_123_4462_n757), .Y(n1574) );
XNOR2X4TS U3391 ( .A(n1099), .B(n887), .Y(n1578) );
OAI22X1TS U3392 ( .A0(n1635), .A1(n856), .B0(n1597), .B1(n899), .Y(n1640) );
OAI22X1TS U3393 ( .A0(n698), .A1(n1613), .B0(n865), .B1(n2377), .Y(n2376) );
OAI22X1TS U3394 ( .A0(n2483), .A1(n1614), .B0(n889), .B1(n1153), .Y(n2375)
);
OAI22X1TS U3395 ( .A0(n698), .A1(n1668), .B0(n865), .B1(n1664), .Y(n1684) );
OAI22X1TS U3396 ( .A0(n698), .A1(mult_x_23_n459), .B0(mult_x_23_n540), .B1(
n1668), .Y(n1743) );
CMPR32X2TS U3397 ( .A(n1683), .B(n1684), .C(n1682), .CO(n2713), .S(n2744) );
ADDFHX4TS U3398 ( .A(n1693), .B(n1692), .CI(n1691), .CO(n2712), .S(n2742) );
OAI22X1TS U3399 ( .A0(n852), .A1(n1764), .B0(n2842), .B1(n1773), .Y(n1774)
);
AO21X1TS U3400 ( .A0(n1020), .A1(n891), .B0(n854), .Y(n2788) );
XOR2X1TS U3401 ( .A(n1785), .B(n3808), .Y(n1786) );
ADDFHX4TS U3402 ( .A(n1787), .B(add_x_19_n51), .CI(n1786), .CO(n1899), .S(
n1887) );
ADDFHX4TS U3403 ( .A(n1799), .B(n1798), .CI(n1797), .CO(n1873), .S(n1866) );
INVX12TS U3404 ( .A(Sgf_operation_Result[1]), .Y(n1803) );
NAND2X8TS U3405 ( .A(n1802), .B(Sgf_operation_EVEN1_Q_middle[0]), .Y(n2190)
);
ADDFHX4TS U3406 ( .A(Sgf_operation_EVEN1_Q_middle[2]), .B(n1805), .CI(n1804),
.CO(n1808), .S(n1807) );
ADDFHX4TS U3407 ( .A(Sgf_operation_EVEN1_Q_middle[3]), .B(n1811), .CI(n1810),
.CO(n1817), .S(n1809) );
ADDFHX4TS U3408 ( .A(Sgf_operation_EVEN1_Q_middle[4]), .B(n1813), .CI(n1812),
.CO(n1819), .S(n1818) );
ADDFHX4TS U3409 ( .A(Sgf_operation_EVEN1_Q_middle[5]), .B(n1815), .CI(n1814),
.CO(n1821), .S(n1820) );
INVX12TS U3410 ( .A(Sgf_operation_Result[7]), .Y(n1827) );
ADDFHX4TS U3411 ( .A(Sgf_operation_EVEN1_Q_middle[6]), .B(n1816), .CI(n1215),
.CO(n1823), .S(n1822) );
ADDFHX4TS U3412 ( .A(Sgf_operation_EVEN1_Q_middle[7]), .B(n1827), .CI(n1826),
.CO(n1832), .S(n1824) );
ADDFHX4TS U3413 ( .A(Sgf_operation_EVEN1_Q_middle[9]), .B(n1829), .CI(n1828),
.CO(n1837), .S(n1835) );
ADDFHX4TS U3414 ( .A(Sgf_operation_EVEN1_Q_middle[8]), .B(n1831), .CI(n1830),
.CO(n1834), .S(n1833) );
NAND2X8TS U3415 ( .A(n2146), .B(n2142), .Y(n2151) );
AOI21X4TS U3416 ( .A0(n2142), .A1(n828), .B0(n1836), .Y(n2150) );
OAI21X4TS U3417 ( .A0(n2153), .A1(n2150), .B0(n2154), .Y(n1838) );
CLKXOR2X4TS U3418 ( .A(n1840), .B(n3683), .Y(n1919) );
XNOR2X4TS U3419 ( .A(n1898), .B(n3687), .Y(n3057) );
ADDFHX4TS U3420 ( .A(n1852), .B(n706), .CI(n1851), .CO(n1865), .S(n1863) );
ADDFHX4TS U3421 ( .A(n1876), .B(n1875), .CI(n1874), .CO(n1886), .S(n1883) );
ADDFHX4TS U3422 ( .A(n1879), .B(n1878), .CI(n1877), .CO(n1882), .S(n1881) );
NAND2X8TS U3423 ( .A(n1880), .B(n1881), .Y(n2977) );
AOI21X4TS U3424 ( .A0(n1459), .A1(n2964), .B0(n1884), .Y(n1885) );
INVX12TS U3425 ( .A(n2163), .Y(n1903) );
AOI21X1TS U3426 ( .A0(n631), .A1(n3699), .B0(n3700), .Y(n1896) );
NOR2X8TS U3427 ( .A(n1907), .B(n1906), .Y(n2368) );
AOI21X1TS U3428 ( .A0(n3833), .A1(n3834), .B0(n3835), .Y(n1909) );
OAI21X1TS U3429 ( .A0(n1910), .A1(n605), .B0(n1909), .Y(n1911) );
AOI2BB1X1TS U3430 ( .A0N(n1913), .A1N(n1912), .B0(n1911), .Y(n1914) );
OAI22X4TS U3431 ( .A0(n847), .A1(n702), .B0(n891), .B1(n1933), .Y(n1957) );
XOR2X1TS U3432 ( .A(n1948), .B(n894), .Y(n1949) );
ADDFHX4TS U3433 ( .A(n1966), .B(n1965), .CI(n1964), .CO(n1954), .S(n2682) );
ADDFHX4TS U3434 ( .A(n1975), .B(n1974), .CI(n1973), .CO(n2723), .S(n2725) );
NOR2BX1TS U3435 ( .AN(n848), .B(n695), .Y(n1995) );
OAI22X1TS U3436 ( .A0(n2016), .A1(n695), .B0(n2008), .B1(n2106), .Y(n2020)
);
XNOR2X4TS U3437 ( .A(n2052), .B(n2051), .Y(Sgf_operation_EVEN1_middle_N8) );
ADDFHX4TS U3438 ( .A(n2094), .B(n2093), .CI(n2092), .CO(n2544), .S(n2592) );
OAI21X4TS U3439 ( .A0(n2152), .A1(n509), .B0(n2145), .Y(n2144) );
XNOR2X4TS U3440 ( .A(n2144), .B(n2143), .Y(n2149) );
XNOR2X4TS U3441 ( .A(n2157), .B(n2156), .Y(n2162) );
XNOR2X4TS U3442 ( .A(n2181), .B(n2166), .Y(n2211) );
AOI21X4TS U3443 ( .A0(n2181), .A1(n2168), .B0(n2167), .Y(n2171) );
AOI21X4TS U3444 ( .A0(n2181), .A1(n2180), .B0(n2179), .Y(n2185) );
CLKXOR2X4TS U3445 ( .A(n2197), .B(n1079), .Y(n2205) );
XNOR2X4TS U3446 ( .A(n2203), .B(n2202), .Y(n2207) );
XNOR2X4TS U3447 ( .A(n1190), .B(n2226), .Y(n2230) );
NAND2X1TS U3448 ( .A(n2242), .B(n2260), .Y(n2243) );
INVX2TS U3449 ( .A(n2270), .Y(n2249) );
AOI21X4TS U3450 ( .A0(n2324), .A1(n2249), .B0(n2248), .Y(n2252) );
NOR2X2TS U3451 ( .A(n2299), .B(n2294), .Y(n2262) );
AOI21X4TS U3452 ( .A0(n2330), .A1(n2314), .B0(n2265), .Y(n2267) );
NOR2X8TS U3453 ( .A(n2270), .B(n2275), .Y(n2334) );
NAND2X1TS U3454 ( .A(n2272), .B(n2271), .Y(n2273) );
OAI21X4TS U3455 ( .A0(n2275), .A1(n2274), .B0(n2273), .Y(n2342) );
OAI21X4TS U3456 ( .A0(n2281), .A1(n2313), .B0(n2280), .Y(n2353) );
AOI21X2TS U3457 ( .A0(n2330), .A1(n2347), .B0(n2353), .Y(n2283) );
XOR2X1TS U3458 ( .A(n2300), .B(n2288), .Y(n2289) );
XOR2X1TS U3459 ( .A(n2307), .B(n2306), .Y(n2311) );
XOR2X1TS U3460 ( .A(n2309), .B(n2308), .Y(n2310) );
NAND2X1TS U3461 ( .A(n2334), .B(n2341), .Y(n2344) );
INVX2TS U3462 ( .A(n3454), .Y(n2357) );
CMPR32X2TS U3463 ( .A(Op_MY[16]), .B(mult_x_23_n521), .C(n2378), .CO(n2389),
.S(n2381) );
OAI22X1TS U3464 ( .A0(n883), .A1(n571), .B0(n3668), .B1(n3665), .Y(n2386) );
OAI22X1TS U3465 ( .A0(n2483), .A1(n1153), .B0(n2481), .B1(mult_x_23_n546),
.Y(n2385) );
OAI22X1TS U3466 ( .A0(n698), .A1(n2387), .B0(n865), .B1(n1147), .Y(n2870) );
OAI22X1TS U3467 ( .A0(n2396), .A1(n861), .B0(n2410), .B1(n895), .Y(n2407) );
ADDFHX4TS U3468 ( .A(n2407), .B(n2406), .CI(n2405), .CO(n2425), .S(n2755) );
NAND2BX1TS U3469 ( .AN(n868), .B(n2463), .Y(n2444) );
XNOR2X1TS U3470 ( .A(n3695), .B(Op_MY[12]), .Y(n2449) );
OAI22X1TS U3471 ( .A0(n1156), .A1(n2454), .B0(n2464), .B1(n835), .Y(n2465)
);
ADDFHX4TS U3472 ( .A(n2534), .B(n2533), .CI(n2532), .CO(n2720), .S(n2543) );
ADDFHX4TS U3473 ( .A(n2545), .B(n2544), .CI(n2543), .CO(n2736), .S(n2096) );
NAND2X1TS U3474 ( .A(n2564), .B(n1329), .Y(n2565) );
ADDFHX4TS U3475 ( .A(n2575), .B(n2574), .CI(n2573), .CO(n2717), .S(n2719) );
ADDFHX4TS U3476 ( .A(n2578), .B(n2577), .CI(n2576), .CO(n2568), .S(n2716) );
XNOR2X1TS U3477 ( .A(n3769), .B(n3770), .Y(n2581) );
XNOR2X1TS U3478 ( .A(n3776), .B(n3777), .Y(n2582) );
AOI22X1TS U3479 ( .A0(n1350), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n3353), .Y(n2591) );
AOI2BB2X1TS U3480 ( .B0(n3379), .B1(n241), .A0N(n900), .A1N(n3958), .Y(n2590) );
NAND2X1TS U3481 ( .A(n3335), .B(n240), .Y(n2589) );
XNOR2X4TS U3482 ( .A(n2653), .B(mult_x_55_n446), .Y(n2613) );
OAI22X1TS U3483 ( .A0(n2652), .A1(n2606), .B0(n2605), .B1(n2650), .Y(n2610)
);
ADDFHX4TS U3484 ( .A(n2721), .B(n2720), .CI(n2719), .CO(n2738), .S(n2737) );
ADDFHX4TS U3485 ( .A(n2727), .B(n2726), .CI(n2725), .CO(n2731), .S(n2730) );
MX2X6TS U3486 ( .A(Data_MX[2]), .B(Op_MX[2]), .S0(n3129), .Y(n346) );
XOR2X1TS U3487 ( .A(n3577), .B(n346), .Y(n3632) );
XNOR2X1TS U3488 ( .A(mult_x_55_n570), .B(n346), .Y(n3642) );
OR2X2TS U3489 ( .A(n2762), .B(n2761), .Y(n2763) );
XOR2X1TS U3490 ( .A(mult_x_55_n568), .B(n348), .Y(n3635) );
MX2X6TS U3491 ( .A(Data_MX[7]), .B(n4047), .S0(n3129), .Y(mult_x_55_n567) );
XNOR2X1TS U3492 ( .A(mult_x_55_n567), .B(n319), .Y(n3636) );
XNOR2X1TS U3493 ( .A(mult_x_55_n567), .B(n320), .Y(n3638) );
INVX2TS U3494 ( .A(n2768), .Y(n2770) );
NAND2X1TS U3495 ( .A(n2770), .B(n2769), .Y(n2771) );
NAND2X2TS U3496 ( .A(n2773), .B(n2772), .Y(mult_x_55_n9) );
NAND2X2TS U3497 ( .A(n2798), .B(n2774), .Y(mult_x_55_n8) );
OAI22X1TS U3498 ( .A0(n852), .A1(n2789), .B0(n700), .B1(mult_x_55_n559), .Y(
n2840) );
CMPR32X2TS U3499 ( .A(n2792), .B(n2791), .C(n2790), .CO(n2839), .S(n2787) );
MX2X4TS U3500 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n3062), .Y(mult_x_55_a_0_)
);
INVX2TS U3501 ( .A(mult_x_55_a_0_), .Y(n3637) );
AOI21X1TS U3502 ( .A0(n2805), .A1(n2804), .B0(n2803), .Y(n2806) );
NAND2X1TS U3503 ( .A(n2823), .B(n2822), .Y(n2824) );
NAND2X1TS U3504 ( .A(n2828), .B(n2827), .Y(n2829) );
XNOR2X1TS U3505 ( .A(n2830), .B(n2829), .Y(Sgf_operation_EVEN1_right_N6) );
XOR3X2TS U3506 ( .A(n2845), .B(n2844), .C(n2843), .Y(n2846) );
OR2X2TS U3507 ( .A(n2847), .B(n2846), .Y(n2849) );
MX2X6TS U3508 ( .A(Data_MX[10]), .B(n4051), .S0(n746), .Y(n354) );
XNOR2X1TS U3509 ( .A(n1174), .B(n3616), .Y(n3621) );
XNOR2X1TS U3510 ( .A(mult_x_55_n568), .B(n350), .Y(n3579) );
MX2X4TS U3511 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n2945), .Y(mult_x_55_a_8_)
);
XNOR2X1TS U3512 ( .A(mult_x_55_n568), .B(n322), .Y(n3576) );
MX2X4TS U3513 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(n3129), .Y(mult_x_55_n566)
);
XNOR2X1TS U3514 ( .A(n3577), .B(n320), .Y(n3628) );
XNOR2X1TS U3515 ( .A(n3577), .B(n348), .Y(n3615) );
XNOR2X1TS U3516 ( .A(n3577), .B(n319), .Y(n3634) );
XNOR2X1TS U3517 ( .A(n3577), .B(n321), .Y(n3578) );
NAND2BX1TS U3518 ( .AN(n1461), .B(n2851), .Y(n2852) );
NAND2X1TS U3519 ( .A(n2854), .B(n2853), .Y(n2855) );
MX2X6TS U3520 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n2945), .Y(
mult_x_23_n551) );
INVX4TS U3521 ( .A(mult_x_23_n551), .Y(n3694) );
XNOR2X1TS U3522 ( .A(n3694), .B(n2857), .Y(n3702) );
MX2X6TS U3523 ( .A(Data_MX[21]), .B(n4052), .S0(n3062), .Y(mult_x_23_n550)
);
XNOR2X1TS U3524 ( .A(n3710), .B(n2857), .Y(n3719) );
XNOR2X1TS U3525 ( .A(mult_x_23_n550), .B(mult_x_23_n525), .Y(n3720) );
XNOR2X1TS U3526 ( .A(mult_x_23_n551), .B(n4039), .Y(n3729) );
NAND2X1TS U3527 ( .A(n2860), .B(n2859), .Y(n2862) );
XNOR2X1TS U3528 ( .A(n2862), .B(n2861), .Y(Sgf_operation_EVEN1_left_N3) );
XNOR2X1TS U3529 ( .A(mult_x_23_n553), .B(n333), .Y(n3701) );
NOR2BX1TS U3530 ( .AN(n868), .B(n835), .Y(Sgf_operation_EVEN1_left_N0) );
OAI22X1TS U3531 ( .A0(n883), .A1(mult_x_23_n517), .B0(n3668), .B1(n3664),
.Y(n2874) );
OAI22X1TS U3532 ( .A0(n1252), .A1(n1147), .B0(mult_x_23_n540), .B1(
mult_x_23_n545), .Y(n2873) );
AO21X1TS U3533 ( .A0(n1252), .A1(n865), .B0(mult_x_23_n545), .Y(n2882) );
MX2X6TS U3534 ( .A(Data_MX[22]), .B(n4053), .S0(n3129), .Y(n366) );
CMPR32X2TS U3535 ( .A(n3665), .B(mult_x_23_n517), .C(n2883), .CO(n2949), .S(
n2881) );
INVX2TS U3536 ( .A(n2934), .Y(n2886) );
NAND2X2TS U3537 ( .A(n2885), .B(n2884), .Y(n2933) );
NAND2X1TS U3538 ( .A(n3736), .B(n2929), .Y(mult_x_23_n11) );
CLKINVX1TS U3539 ( .A(n2895), .Y(mult_x_23_n109) );
INVX4TS U3540 ( .A(n2896), .Y(n2898) );
INVX4TS U3541 ( .A(n2915), .Y(n2917) );
AOI21X4TS U3542 ( .A0(n1234), .A1(n2936), .B0(n2921), .Y(n2925) );
INVX2TS U3543 ( .A(n2926), .Y(n2928) );
MXI2X4TS U3544 ( .A(n2942), .B(n3925), .S0(n746), .Y(
DP_OP_111J16_123_4462_n880) );
XNOR2X1TS U3545 ( .A(n3694), .B(n2943), .Y(n3722) );
XNOR2X2TS U3546 ( .A(mult_x_23_n550), .B(n366), .Y(n3693) );
INVX2TS U3547 ( .A(n366), .Y(n2944) );
MX2X6TS U3548 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n3062), .Y(
mult_x_23_n552) );
XOR2X1TS U3549 ( .A(mult_x_23_n552), .B(n2865), .Y(n3697) );
XNOR2X1TS U3550 ( .A(mult_x_23_n551), .B(n1475), .Y(n3705) );
XNOR2X1TS U3551 ( .A(mult_x_23_n552), .B(n4039), .Y(n3718) );
XNOR2X1TS U3552 ( .A(mult_x_23_n552), .B(mult_x_23_n518), .Y(n3715) );
NAND2X1TS U3553 ( .A(n739), .B(n2946), .Y(n2948) );
CMPR32X2TS U3554 ( .A(n3741), .B(n3742), .C(n2949), .CO(n2952), .S(n2884) );
AND2X2TS U3555 ( .A(n883), .B(n3668), .Y(n2950) );
XNOR2X1TS U3556 ( .A(n2950), .B(n3664), .Y(n2951) );
NAND2X1TS U3557 ( .A(n2952), .B(n2951), .Y(n2953) );
CLKBUFX3TS U3558 ( .A(n875), .Y(n4057) );
BUFX3TS U3559 ( .A(n4057), .Y(n3975) );
AOI21X4TS U3560 ( .A0(n2979), .A1(n712), .B0(n2964), .Y(n2967) );
XNOR2X4TS U3561 ( .A(n2979), .B(n2978), .Y(n2998) );
OAI21X4TS U3562 ( .A0(n579), .A1(n2993), .B0(n2992), .Y(n2997) );
INVX2TS U3563 ( .A(n3026), .Y(n3028) );
NAND2X1TS U3564 ( .A(n3034), .B(n3033), .Y(n3035) );
NAND2X2TS U3565 ( .A(n682), .B(n2960), .Y(add_x_19_n67) );
NAND2X1TS U3566 ( .A(n679), .B(n1780), .Y(n3054) );
NOR2X2TS U3567 ( .A(add_x_19_n67), .B(n3054), .Y(n3055) );
INVX2TS U3568 ( .A(add_x_19_n67), .Y(n3056) );
NAND2X2TS U3569 ( .A(n2962), .B(n3057), .Y(add_x_19_n104) );
INVX2TS U3570 ( .A(add_x_19_n104), .Y(n3058) );
NAND2X1TS U3571 ( .A(n3058), .B(n3060), .Y(add_x_19_n94) );
INVX2TS U3572 ( .A(n1798), .Y(n3059) );
NAND2X1TS U3573 ( .A(n3060), .B(n3059), .Y(n3061) );
NOR2X1TS U3574 ( .A(add_x_19_n104), .B(n3061), .Y(add_x_19_n85) );
BUFX3TS U3575 ( .A(n4072), .Y(n3973) );
XNOR2X1TS U3576 ( .A(n3136), .B(n3135), .Y(n3859) );
NOR2BX1TS U3577 ( .AN(n848), .B(n846), .Y(Sgf_operation_EVEN1_middle_N0) );
NAND2X1TS U3578 ( .A(n3064), .B(n3063), .Y(n3066) );
XNOR2X1TS U3579 ( .A(n3066), .B(n3065), .Y(Sgf_operation_EVEN1_middle_N5) );
NAND2X2TS U3580 ( .A(n3068), .B(n3067), .Y(n3070) );
XNOR2X1TS U3581 ( .A(n3070), .B(n3069), .Y(Sgf_operation_EVEN1_middle_N3) );
NAND2X1TS U3582 ( .A(n3073), .B(n3072), .Y(DP_OP_111J16_123_4462_n8) );
AND2X2TS U3583 ( .A(n3077), .B(n3188), .Y(Sgf_operation_EVEN1_middle_N1) );
INVX2TS U3584 ( .A(Data_MY[14]), .Y(n3105) );
INVX2TS U3585 ( .A(n3127), .Y(n3146) );
INVX2TS U3586 ( .A(n3125), .Y(n3106) );
XNOR2X1TS U3587 ( .A(n3108), .B(n3107), .Y(n3861) );
XNOR2X4TS U3588 ( .A(mult_x_23_n551), .B(mult_x_55_n567), .Y(n3798) );
NOR2X1TS U3589 ( .A(mult_x_23_n551), .B(mult_x_55_n567), .Y(n3109) );
XNOR2X1TS U3590 ( .A(n3139), .B(n3109), .Y(n3114) );
NAND2X1TS U3591 ( .A(n350), .B(n4039), .Y(n3112) );
OAI2BB1X1TS U3592 ( .A0N(n3110), .A1N(n2858), .B0(mult_x_55_n568), .Y(n3111)
);
INVX2TS U3593 ( .A(n356), .Y(n3116) );
XOR2X1TS U3594 ( .A(n3116), .B(n3136), .Y(n3117) );
NAND2X1TS U3595 ( .A(n3117), .B(n730), .Y(n3860) );
XOR2X2TS U3596 ( .A(n354), .B(n366), .Y(n3160) );
XNOR2X1TS U3597 ( .A(n3160), .B(n708), .Y(n3121) );
NAND2X1TS U3598 ( .A(mult_x_55_a_8_), .B(n1475), .Y(n3118) );
NOR2X1TS U3599 ( .A(mult_x_23_n553), .B(mult_x_55_n569), .Y(n3122) );
XNOR2X1TS U3600 ( .A(n3128), .B(n3122), .Y(n3124) );
MX2X4TS U3601 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n3062), .Y(n328) );
NAND2X2TS U3602 ( .A(DP_OP_111J16_123_4462_n880), .B(
DP_OP_111J16_123_4462_n891), .Y(n3804) );
XNOR2X1TS U3603 ( .A(n3152), .B(n3134), .Y(n3138) );
NAND2X1TS U3604 ( .A(n3136), .B(n3135), .Y(n3137) );
XOR2X1TS U3605 ( .A(n3138), .B(n3137), .Y(n3842) );
XOR2X1TS U3606 ( .A(mult_x_23_n551), .B(n1475), .Y(n3140) );
XOR2X1TS U3607 ( .A(n3141), .B(n3148), .Y(n3858) );
XNOR2X1TS U3608 ( .A(n3148), .B(n3147), .Y(n3847) );
XNOR2X1TS U3609 ( .A(n3155), .B(n3154), .Y(n3855) );
XNOR2X1TS U3610 ( .A(n3158), .B(n3157), .Y(n3866) );
INVX2TS U3611 ( .A(n354), .Y(n3159) );
XNOR2X1TS U3612 ( .A(mult_x_23_n550), .B(n3159), .Y(n3161) );
INVX2TS U3613 ( .A(n3163), .Y(n3165) );
NAND2X1TS U3614 ( .A(n3165), .B(n3164), .Y(n3166) );
XOR2X1TS U3615 ( .A(n3166), .B(n3796), .Y(n3865) );
OAI21X1TS U3616 ( .A0(n354), .A1(n366), .B0(mult_x_55_n566), .Y(n3168) );
INVX2TS U3617 ( .A(n3169), .Y(n3171) );
NAND2X1TS U3618 ( .A(n3171), .B(n3170), .Y(n3173) );
CMPR32X2TS U3619 ( .A(n3176), .B(n3175), .C(n3174), .CO(n3178), .S(n3074) );
OR2X2TS U3620 ( .A(n3178), .B(n741), .Y(n3180) );
XNOR2X1TS U3621 ( .A(n3181), .B(mult_x_55_n565), .Y(n3836) );
NOR2X2TS U3622 ( .A(mult_x_23_n518), .B(n320), .Y(n3839) );
XOR2X1TS U3623 ( .A(mult_x_23_n552), .B(n4039), .Y(n3184) );
OR2X2TS U3624 ( .A(n324), .B(n312), .Y(n3881) );
INVX2TS U3625 ( .A(n3185), .Y(n3187) );
NAND2X1TS U3626 ( .A(n3187), .B(n3186), .Y(n3189) );
CLKBUFX2TS U3627 ( .A(n4057), .Y(n3976) );
CLKBUFX2TS U3628 ( .A(n4063), .Y(n4066) );
BUFX3TS U3629 ( .A(n869), .Y(n3972) );
NOR2X2TS U3630 ( .A(n3191), .B(n3497), .Y(ready) );
INVX2TS U3631 ( .A(ack_FSM), .Y(n3192) );
MXI2X1TS U3632 ( .A(n3502), .B(n3194), .S0(n1089), .Y(n3195) );
NAND2X1TS U3633 ( .A(n3198), .B(n3195), .Y(n376) );
NAND2X1TS U3634 ( .A(n3394), .B(zero_flag), .Y(n3196) );
NAND4X1TS U3635 ( .A(n3198), .B(n3197), .C(n3353), .D(n3196), .Y(n379) );
INVX2TS U3636 ( .A(n3200), .Y(n3520) );
XNOR2X1TS U3637 ( .A(n3520), .B(Sgf_normalized_result[2]), .Y(n3199) );
XOR2X1TS U3638 ( .A(n3210), .B(Sgf_normalized_result[4]), .Y(n3201) );
CLKMX2X2TS U3639 ( .A(n3201), .B(Add_result[4]), .S0(n843), .Y(n302) );
NAND2X1TS U3640 ( .A(n736), .B(n3202), .Y(n3203) );
XOR2X1TS U3641 ( .A(n3203), .B(n3505), .Y(n3204) );
CLKMX2X2TS U3642 ( .A(n3204), .B(P_Sgf[13]), .S0(n4055), .Y(n228) );
NAND2X1TS U3643 ( .A(n3210), .B(n3950), .Y(n3205) );
CLKMX2X2TS U3644 ( .A(n3206), .B(Add_result[5]), .S0(n3413), .Y(n301) );
NAND2X1TS U3645 ( .A(Sgf_normalized_result[5]), .B(Sgf_normalized_result[6]),
.Y(n3209) );
NAND2X1TS U3646 ( .A(n3207), .B(Sgf_normalized_result[6]), .Y(n3208) );
XNOR2X1TS U3647 ( .A(n3211), .B(n3939), .Y(n3212) );
XNOR2X1TS U3648 ( .A(n3433), .B(n3937), .Y(n3218) );
NOR4X1TS U3649 ( .A(n235), .B(P_Sgf[18]), .C(P_Sgf[19]), .D(P_Sgf[17]), .Y(
n3222) );
NOR4X1TS U3650 ( .A(P_Sgf[16]), .B(P_Sgf[14]), .C(P_Sgf[15]), .D(P_Sgf[13]),
.Y(n3221) );
NOR4X1TS U3651 ( .A(P_Sgf[12]), .B(P_Sgf[9]), .C(P_Sgf[10]), .D(P_Sgf[11]),
.Y(n3220) );
NOR4X1TS U3652 ( .A(P_Sgf[5]), .B(P_Sgf[6]), .C(P_Sgf[7]), .D(P_Sgf[8]), .Y(
n3224) );
NOR4X1TS U3653 ( .A(P_Sgf[1]), .B(P_Sgf[2]), .C(P_Sgf[3]), .D(P_Sgf[4]), .Y(
n3223) );
NAND2X1TS U3654 ( .A(n3375), .B(n3229), .Y(n3230) );
NAND2X1TS U3655 ( .A(n3375), .B(n3233), .Y(n3235) );
AOI22X1TS U3656 ( .A0(n3383), .A1(Add_result[17]), .B0(
Sgf_normalized_result[16]), .B1(n3388), .Y(n3239) );
AOI22X1TS U3657 ( .A0(n3383), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n3353), .Y(n3243) );
NAND2X1TS U3658 ( .A(n3392), .B(n239), .Y(n3241) );
NAND3X1TS U3659 ( .A(n3243), .B(n3242), .C(n3241), .Y(n192) );
XOR2X1TS U3660 ( .A(n3378), .B(n3755), .Y(n3245) );
AOI21X1TS U3661 ( .A0(n3782), .A1(n3783), .B0(n3784), .Y(n3246) );
XNOR2X1TS U3662 ( .A(n3247), .B(n3766), .Y(n3248) );
AOI22X1TS U3663 ( .A0(n3383), .A1(Add_result[5]), .B0(
Sgf_normalized_result[4]), .B1(n3353), .Y(n3252) );
NAND2X1TS U3664 ( .A(n3392), .B(n242), .Y(n3250) );
XNOR2X1TS U3665 ( .A(n3253), .B(n3760), .Y(n3254) );
AOI22X1TS U3666 ( .A0(n3383), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n3353), .Y(n3260) );
NAND2X1TS U3667 ( .A(n2588), .B(n245), .Y(n3258) );
NAND3X1TS U3668 ( .A(n3260), .B(n3259), .C(n3258), .Y(n198) );
AOI22X1TS U3669 ( .A0(n1350), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n3353), .Y(n3265) );
AOI2BB2X1TS U3670 ( .B0(n3391), .B1(n242), .A0N(n900), .A1N(n3957), .Y(n3264) );
NAND2X1TS U3671 ( .A(n2588), .B(n241), .Y(n3263) );
NAND3X1TS U3672 ( .A(n3265), .B(n3264), .C(n3263), .Y(n194) );
OAI21X1TS U3673 ( .A0(n3378), .A1(n582), .B0(n3283), .Y(n3267) );
XNOR2X1TS U3674 ( .A(n3267), .B(n3761), .Y(n3268) );
AOI22X1TS U3675 ( .A0(n3383), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n3388), .Y(n3271) );
NAND2X1TS U3676 ( .A(n2588), .B(n246), .Y(n3269) );
NAND3X1TS U3677 ( .A(n3271), .B(n3270), .C(n3269), .Y(n199) );
XNOR2X1TS U3678 ( .A(n3272), .B(n3759), .Y(n3273) );
AOI22X1TS U3679 ( .A0(n1350), .A1(Add_result[6]), .B0(
Sgf_normalized_result[5]), .B1(n3353), .Y(n3276) );
NAND2X1TS U3680 ( .A(n3335), .B(n243), .Y(n3274) );
NAND3X1TS U3681 ( .A(n3276), .B(n3275), .C(n3274), .Y(n196) );
NAND2X1TS U3682 ( .A(n3278), .B(n581), .Y(n3280) );
AOI21X1TS U3683 ( .A0(n3291), .A1(n3278), .B0(n3277), .Y(n3279) );
NAND2X1TS U3684 ( .A(n581), .B(n3773), .Y(n3285) );
AOI22X1TS U3685 ( .A0(n1350), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n3388), .Y(n3290) );
NAND2X1TS U3686 ( .A(n3392), .B(n249), .Y(n3288) );
NAND3X1TS U3687 ( .A(n3290), .B(n3289), .C(n3288), .Y(n202) );
AOI21X1TS U3688 ( .A0(n3291), .A1(n611), .B0(n3763), .Y(n3292) );
AOI22X1TS U3689 ( .A0(n3389), .A1(Add_result[11]), .B0(
Sgf_normalized_result[10]), .B1(n3388), .Y(n3298) );
AOI2BB2X1TS U3690 ( .B0(n3384), .B1(n249), .A0N(n900), .A1N(n3923), .Y(n3297) );
NAND2X1TS U3691 ( .A(n3392), .B(n248), .Y(n3296) );
NAND3X1TS U3692 ( .A(n3298), .B(n3297), .C(n3296), .Y(n201) );
NAND2X1TS U3693 ( .A(n1329), .B(n3304), .Y(n3306) );
AOI22X1TS U3694 ( .A0(n1350), .A1(n287), .B0(Sgf_normalized_result[18]),
.B1(n3361), .Y(n3312) );
NAND2X1TS U3695 ( .A(n2588), .B(n256), .Y(n3310) );
AOI22X1TS U3696 ( .A0(n3383), .A1(Add_result[20]), .B0(
Sgf_normalized_result[19]), .B1(n3361), .Y(n3318) );
NAND2X1TS U3697 ( .A(n3392), .B(n257), .Y(n3316) );
AOI22X1TS U3698 ( .A0(n1350), .A1(Add_result[22]), .B0(
Sgf_normalized_result[21]), .B1(n3361), .Y(n3328) );
NAND2X1TS U3699 ( .A(n2588), .B(n259), .Y(n3326) );
AOI22X1TS U3700 ( .A0(n3389), .A1(Add_result[21]), .B0(n1018), .B1(n3361),
.Y(n3331) );
AOI2BB2X1TS U3701 ( .B0(n3379), .B1(n259), .A0N(n901), .A1N(n3913), .Y(n3330) );
AOI22X1TS U3702 ( .A0(n3389), .A1(Add_result[18]), .B0(
Sgf_normalized_result[17]), .B1(n3361), .Y(n3334) );
NAND2X1TS U3703 ( .A(n3392), .B(n255), .Y(n3332) );
NAND3X1TS U3704 ( .A(n3334), .B(n3333), .C(n3332), .Y(n208) );
AOI22X1TS U3705 ( .A0(n1350), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n3388), .Y(n3338) );
NAND2X1TS U3706 ( .A(n3335), .B(n247), .Y(n3336) );
AOI22X1TS U3707 ( .A0(n3383), .A1(Add_result[23]), .B0(
Sgf_normalized_result[22]), .B1(n3361), .Y(n3349) );
NAND2X1TS U3708 ( .A(n3392), .B(n260), .Y(n3347) );
NAND3X1TS U3709 ( .A(n3349), .B(n3348), .C(n3347), .Y(n213) );
AOI22X1TS U3710 ( .A0(n1350), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n3388), .Y(n3352) );
NAND2X1TS U3711 ( .A(n3392), .B(n238), .Y(n3350) );
NAND3X1TS U3712 ( .A(n3352), .B(n3351), .C(n3350), .Y(n191) );
AOI22X1TS U3713 ( .A0(n3389), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n3353), .Y(n3356) );
NAND2X1TS U3714 ( .A(n3392), .B(n244), .Y(n3354) );
NAND3X1TS U3715 ( .A(n3356), .B(n3355), .C(n3354), .Y(n197) );
NAND2X1TS U3716 ( .A(n3433), .B(Sgf_normalized_result[8]), .Y(n3357) );
AOI22X1TS U3717 ( .A0(n1350), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n3388), .Y(n3367) );
NAND2X1TS U3718 ( .A(n2588), .B(n250), .Y(n3365) );
NAND3X1TS U3719 ( .A(n3367), .B(n3366), .C(n3365), .Y(n203) );
NAND2X1TS U3720 ( .A(n3375), .B(add_x_19_n122), .Y(n3371) );
AOI22X1TS U3721 ( .A0(n3389), .A1(Add_result[15]), .B0(
Sgf_normalized_result[14]), .B1(n3388), .Y(n3382) );
NAND2X1TS U3722 ( .A(n3335), .B(n252), .Y(n3380) );
NAND3X1TS U3723 ( .A(n3382), .B(n3381), .C(n3380), .Y(n205) );
AOI22X1TS U3724 ( .A0(n3383), .A1(Add_result[14]), .B0(
Sgf_normalized_result[13]), .B1(n3388), .Y(n3387) );
NAND2X1TS U3725 ( .A(n2588), .B(n251), .Y(n3385) );
NAND3X1TS U3726 ( .A(n3387), .B(n3386), .C(n3385), .Y(n204) );
NAND2X1TS U3727 ( .A(n3392), .B(n253), .Y(n3393) );
NAND2X1TS U3728 ( .A(n3394), .B(n3952), .Y(n3396) );
NAND2X1TS U3729 ( .A(n3433), .B(n3416), .Y(n3398) );
INVX2TS U3730 ( .A(n3407), .Y(n3400) );
NAND2X1TS U3731 ( .A(n3433), .B(n3400), .Y(n3401) );
XNOR2X1TS U3732 ( .A(n435), .B(n3404), .Y(n3405) );
NAND2X1TS U3733 ( .A(n3433), .B(n3408), .Y(n3409) );
NAND2X1TS U3734 ( .A(Sgf_normalized_result[14]), .B(
Sgf_normalized_result[15]), .Y(n3411) );
XNOR2X1TS U3735 ( .A(n3479), .B(n3938), .Y(n3414) );
NAND2X1TS U3736 ( .A(n3433), .B(n3417), .Y(n3418) );
NAND2X1TS U3737 ( .A(n3433), .B(n3420), .Y(n3421) );
NAND2X1TS U3738 ( .A(n3429), .B(Sgf_normalized_result[14]), .Y(n3430) );
NAND2X1TS U3739 ( .A(n3433), .B(n3432), .Y(n3434) );
XOR2X1TS U3740 ( .A(n3439), .B(n3946), .Y(n3440) );
XOR2X1TS U3741 ( .A(n3443), .B(n3933), .Y(n3444) );
NAND2X1TS U3742 ( .A(n3479), .B(n446), .Y(n3446) );
XOR2X1TS U3743 ( .A(n3446), .B(n3934), .Y(n3447) );
AND2X2TS U3744 ( .A(n3455), .B(n3454), .Y(n3457) );
BUFX16TS U3745 ( .A(n3459), .Y(n3510) );
INVX2TS U3746 ( .A(n3469), .Y(n3471) );
NAND2X1TS U3747 ( .A(n3471), .B(n3470), .Y(n3472) );
NAND2X1TS U3748 ( .A(Sgf_normalized_result[22]), .B(
Sgf_normalized_result[23]), .Y(n3474) );
INVX2TS U3749 ( .A(n3481), .Y(n3482) );
NAND2X1TS U3750 ( .A(n3486), .B(n3485), .Y(n3487) );
INVX2TS U3751 ( .A(n3490), .Y(n3492) );
NAND2X1TS U3752 ( .A(n3492), .B(n3491), .Y(n3493) );
XOR2X1TS U3753 ( .A(n3494), .B(n3493), .Y(n3495) );
AOI21X1TS U3754 ( .A0(n1159), .A1(n3497), .B0(n3496), .Y(n3498) );
MXI2X1TS U3755 ( .A(n1456), .B(n1449), .S0(n3510), .Y(n226) );
OR2X2TS U3756 ( .A(n3504), .B(n3503), .Y(n3506) );
NAND2X1TS U3757 ( .A(n3506), .B(n3505), .Y(n3507) );
MXI2X1TS U3758 ( .A(n3507), .B(n1448), .S0(n3510), .Y(n227) );
CLKBUFX2TS U3759 ( .A(n3977), .Y(n3974) );
NAND2X1TS U3760 ( .A(n3557), .B(n3900), .Y(n375) );
MXI2X1TS U3761 ( .A(n1802), .B(n3940), .S0(n4055), .Y(n215) );
MXI2X1TS U3762 ( .A(n694), .B(n4068), .S0(n3510), .Y(n225) );
MXI2X1TS U3763 ( .A(Sgf_normalized_result[0]), .B(n4069), .S0(n3413), .Y(
n306) );
XNOR2X1TS U3764 ( .A(Sgf_normalized_result[1]), .B(Sgf_normalized_result[0]),
.Y(n3509) );
MXI2X1TS U3765 ( .A(n1827), .B(n3969), .S0(n4055), .Y(n222) );
MXI2X1TS U3766 ( .A(n1829), .B(n3961), .S0(n4055), .Y(n224) );
MXI2X1TS U3767 ( .A(n1816), .B(n3968), .S0(n3510), .Y(n221) );
MXI2X1TS U3768 ( .A(n1813), .B(n3966), .S0(n3510), .Y(n219) );
MXI2X1TS U3769 ( .A(n1803), .B(n3963), .S0(n3510), .Y(n216) );
MXI2X1TS U3770 ( .A(n1815), .B(n3967), .S0(n3510), .Y(n220) );
MXI2X1TS U3771 ( .A(n1831), .B(n3970), .S0(n3510), .Y(n223) );
BUFX8TS U3772 ( .A(n3524), .Y(n3515) );
AO22X2TS U3773 ( .A0(n3515), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n3529), .Y(n190) );
NAND2X1TS U3774 ( .A(n3518), .B(n3517), .Y(n3519) );
MXI2X1TS U3775 ( .A(n3519), .B(n3971), .S0(n3529), .Y(n262) );
XOR2X1TS U3776 ( .A(n3521), .B(n3929), .Y(n3522) );
CLKMX2X2TS U3777 ( .A(n3522), .B(Add_result[3]), .S0(n3413), .Y(n303) );
AOI2BB2X1TS U3778 ( .B0(n3530), .B1(n3898), .A0N(n3523), .A1N(
final_result_ieee[25]), .Y(n268) );
AOI2BB2X1TS U3779 ( .B0(n3530), .B1(n3897), .A0N(n3523), .A1N(
final_result_ieee[27]), .Y(n266) );
AOI2BB2X1TS U3780 ( .B0(n4070), .B1(n3530), .A0N(n3523), .A1N(
final_result_ieee[28]), .Y(n265) );
AOI2BB2X1TS U3781 ( .B0(n3530), .B1(n3896), .A0N(n3523), .A1N(
final_result_ieee[24]), .Y(n269) );
AOI2BB2X1TS U3782 ( .B0(n3530), .B1(n3899), .A0N(n3523), .A1N(
final_result_ieee[26]), .Y(n267) );
AOI2BB2X1TS U3783 ( .B0(n3530), .B1(n3901), .A0N(n3523), .A1N(
final_result_ieee[23]), .Y(n270) );
AOI2BB2X1TS U3784 ( .B0(n3530), .B1(n3903), .A0N(n3523), .A1N(
final_result_ieee[29]), .Y(n264) );
AOI2BB2X1TS U3785 ( .B0(n3530), .B1(n3902), .A0N(n3523), .A1N(
final_result_ieee[30]), .Y(n263) );
AO22X1TS U3786 ( .A0(n3515), .A1(Sgf_normalized_result[16]), .B0(
final_result_ieee[16]), .B1(n3529), .Y(n174) );
AO22X2TS U3787 ( .A0(n3515), .A1(Sgf_normalized_result[15]), .B0(
final_result_ieee[15]), .B1(n3529), .Y(n175) );
AO22X2TS U3788 ( .A0(n3515), .A1(Sgf_normalized_result[19]), .B0(
final_result_ieee[19]), .B1(n3529), .Y(n171) );
NOR4X1TS U3789 ( .A(Op_MY[26]), .B(Op_MY[25]), .C(Op_MY[28]), .D(Op_MY[27]),
.Y(n3537) );
NOR4X1TS U3790 ( .A(n3533), .B(Op_MY[22]), .C(Op_MY[16]), .D(Op_MY[18]), .Y(
n3536) );
NOR4X1TS U3791 ( .A(Op_MY[29]), .B(Op_MY[12]), .C(Op_MY[0]), .D(Op_MY[30]),
.Y(n3535) );
NAND4X1TS U3792 ( .A(n3537), .B(n3536), .C(n3535), .D(n3534), .Y(n3556) );
AND4X2TS U3793 ( .A(n4026), .B(n4036), .C(n4037), .D(n4038), .Y(n3542) );
NOR4X1TS U3794 ( .A(Op_MY[7]), .B(Op_MY[8]), .C(Op_MY[9]), .D(n3539), .Y(
n3541) );
AND4X2TS U3795 ( .A(n4023), .B(n4027), .C(n572), .D(n4028), .Y(n3540) );
NAND4X1TS U3796 ( .A(n3543), .B(n3542), .C(n3541), .D(n3540), .Y(n3555) );
AND4X2TS U3797 ( .A(n4031), .B(n3997), .C(n4032), .D(n3998), .Y(n3547) );
NOR4BBX1TS U3798 ( .AN(n4041), .BN(n4042), .C(n4040), .D(n4049), .Y(n3546)
);
AND4X1TS U3799 ( .A(n835), .B(n4009), .C(n4010), .D(n3959), .Y(n3544) );
NAND4X1TS U3800 ( .A(n3547), .B(n3546), .C(n3545), .D(n3544), .Y(n3554) );
NOR4X1TS U3801 ( .A(Op_MX[26]), .B(Op_MX[25]), .C(Op_MX[28]), .D(Op_MX[27]),
.Y(n3552) );
AND4X2TS U3802 ( .A(n3548), .B(n3993), .C(n733), .D(n3960), .Y(n3551) );
AND4X2TS U3803 ( .A(n3995), .B(n3996), .C(n4043), .D(n4044), .Y(n3550) );
AND3X2TS U3804 ( .A(n3951), .B(n3981), .C(n3982), .Y(n3549) );
NAND4X1TS U3805 ( .A(n3552), .B(n3551), .C(n3550), .D(n3549), .Y(n3553) );
OAI22X1TS U3806 ( .A0(n3556), .A1(n3555), .B0(n3554), .B1(n3553), .Y(n3558)
);
CLKMX2X2TS U3807 ( .A(n3558), .B(zero_flag), .S0(n3557), .Y(n311) );
MXI2X1TS U3808 ( .A(n3560), .B(n3896), .S0(n3559), .Y(n279) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk1.tcl_KOA_2STAGE_syn.sdf");
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp_array02.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp_array02(/*AUTOARG*/
// Outputs
pcx_scache2_data_px_l, pcx_scache0_data_px_l, scan_out,
// Inputs
spc7_pcx_data_pa, spc6_pcx_data_pa, spc5_pcx_data_pa,
spc4_pcx_data_pa, spc3_pcx_data_pa, spc2_pcx_data_pa,
spc1_pcx_data_pa, spc0_pcx_data_pa, shiftenable, rclk,
arbpc2_pcxdp_shift_px, arbpc2_pcxdp_qsel1_pa,
arbpc2_pcxdp_qsel0_pa, arbpc2_pcxdp_q0_hold_pa,
arbpc2_pcxdp_grant_pa, arbpc0_pcxdp_shift_px,
arbpc0_pcxdp_qsel1_pa, arbpc0_pcxdp_qsel0_pa,
arbpc0_pcxdp_q0_hold_pa, arbpc0_pcxdp_grant_pa, scan_in
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [`PCX_WIDTH-1:0]pcx_scache0_data_px_l;// From pcx_dp0 of pcx_dp0.v
output [`PCX_WIDTH-1:0]pcx_scache2_data_px_l;// From pcx_dp2 of pcx_dp2.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0] arbpc0_pcxdp_grant_pa; // To pcx_dp0 of pcx_dp0.v
input [7:0] arbpc0_pcxdp_q0_hold_pa;// To pcx_dp0 of pcx_dp0.v
input [7:0] arbpc0_pcxdp_qsel0_pa; // To pcx_dp0 of pcx_dp0.v
input [7:0] arbpc0_pcxdp_qsel1_pa; // To pcx_dp0 of pcx_dp0.v
input [7:0] arbpc0_pcxdp_shift_px; // To pcx_dp0 of pcx_dp0.v
input [7:0] arbpc2_pcxdp_grant_pa; // To pcx_dp2 of pcx_dp2.v
input [7:0] arbpc2_pcxdp_q0_hold_pa;// To pcx_dp2 of pcx_dp2.v
input [7:0] arbpc2_pcxdp_qsel0_pa; // To pcx_dp2 of pcx_dp2.v
input [7:0] arbpc2_pcxdp_qsel1_pa; // To pcx_dp2 of pcx_dp2.v
input [7:0] arbpc2_pcxdp_shift_px; // To pcx_dp2 of pcx_dp2.v
input rclk; // To pcx_dp0 of pcx_dp0.v, ...
input shiftenable; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc0_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc1_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc2_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc3_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc4_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc5_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc6_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
input [`PCX_WIDTH-1:0]spc7_pcx_data_pa; // To pcx_dp0 of pcx_dp0.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
input scan_in;
output scan_out;
/*
pcx_dp0 AUTO_TEMPLATE(
.scan_out (),
.scan_in ());
*/
pcx_dp0 pcx_dp0(/*AUTOINST*/
// Outputs
.scan_out (), // Templated
.pcx_scache0_data_px_l(pcx_scache0_data_px_l[`PCX_WIDTH-1:0]),
// Inputs
.arbpc0_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[7:0]),
.arbpc0_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa[7:0]),
.arbpc0_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[7:0]),
.arbpc0_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa[7:0]),
.arbpc0_pcxdp_shift_px(arbpc0_pcxdp_shift_px[7:0]),
.rclk (rclk),
.scan_in (), // Templated
.shiftenable (shiftenable),
.spc0_pcx_data_pa (spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc1_pcx_data_pa (spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc2_pcx_data_pa (spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc3_pcx_data_pa (spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc4_pcx_data_pa (spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc5_pcx_data_pa (spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc6_pcx_data_pa (spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc7_pcx_data_pa (spc7_pcx_data_pa[`PCX_WIDTH-1:0]));
/*
pcx_dp2 AUTO_TEMPLATE(
.scan_out (),
.scan_in ());
*/
pcx_dp2 pcx_dp2(/*AUTOINST*/
// Outputs
.scan_out (), // Templated
.pcx_scache2_data_px_l(pcx_scache2_data_px_l[`PCX_WIDTH-1:0]),
// Inputs
.arbpc2_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[7:0]),
.arbpc2_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa[7:0]),
.arbpc2_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[7:0]),
.arbpc2_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa[7:0]),
.arbpc2_pcxdp_shift_px(arbpc2_pcxdp_shift_px[7:0]),
.rclk (rclk),
.scan_in (), // Templated
.shiftenable (shiftenable),
.spc0_pcx_data_pa (spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc1_pcx_data_pa (spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc2_pcx_data_pa (spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc3_pcx_data_pa (spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc4_pcx_data_pa (spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc5_pcx_data_pa (spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc6_pcx_data_pa (spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc7_pcx_data_pa (spc7_pcx_data_pa[`PCX_WIDTH-1:0]));
endmodule // pcx_dp_array02
|
// input 50mhz, output ~60hz
module clk60hz(
input wire clk,
output wire outclk
);
reg [19:0] cnt = 0;
assign outclk = cnt == 833333;
always @(posedge clk)
if(outclk)
cnt <= 0;
else
cnt <= cnt + 20'b1;
endmodule
// input 50mhz, output 63.3hz
module clk63_3hz(
input wire clk,
output wire outclk
);
reg [19:0] cnt = 0;
assign outclk = cnt == 789900;
always @(posedge clk)
if(outclk)
cnt <= 0;
else
cnt <= cnt + 20'b1;
endmodule
// input 50mhz, output 25khz
module clk25khz(
input wire clk,
input wire en,
output wire outclk
);
reg [10:0] cnt = 0;
assign outclk = en & (cnt == 2000);
always @(posedge clk)
if(outclk)
cnt <= 0;
else
cnt <= cnt + 11'b1;
endmodule
// input 50mhz, output 50khz
module clk50khz(
input wire clk,
output wire outclk
);
reg [9:0] cnt = 0;
assign outclk = cnt == 1000;
always @(posedge clk)
if(outclk)
cnt <= 0;
else
cnt <= cnt + 10'b1;
endmodule
module pg(
input clk,
input reset,
input in,
output p
);
reg [1:0] x;
always @(posedge clk or posedge reset)
if(reset)
x <= 0;
else
x <= { x[0], in };
assign p = x[0] & !x[1];
endmodule
/*
// This breaks things because it doesn't detect power on
module pg(input wire clk, input wire reset, input wire in, output wire p);
reg [1:0] x;
reg [1:0] init = 0;
always @(posedge clk or posedge reset)
if(reset)
init <= 0;
else begin
x <= { x[0], in };
init <= { init[0], 1'b1 };
end
assign p = (&init) & x[0] & !x[1];
endmodule
*/
module pa(input wire clk, input wire reset, input wire in, output wire p);
reg [1:0] x;
reg [1:0] init = 0;
always @(posedge clk or posedge reset)
if(reset)
init <= 0;
else begin
x <= { x[0], in };
init <= { init[0], 1'b1 };
end
assign p = (&init) & x[0] & !x[1];
endmodule
// TODO: check the purpose of these
/* "bus driver", 40ns delayed pulse */
module bd(input clk, input reset, input in, output p);
reg [2:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 3'b1;
if(in)
r <= 1;
end
end
assign p = r == 2;
endmodule
/* Same as above but with longer pulse. Used to pulse mb
* because one more clock cycle is needed to get the data
* after the pulse has been synchronized. */
// TODO? get rid of this and just latch
module bd2(input clk, input reset, input in, output p);
reg [2:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 3'b1;
if(in)
r <= 1;
end
end
assign p = r == 2 || r == 3 || r == 4 || r == 5;
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module MARIO_ROM (
clka,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [15 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("MARIO_ROM.mif"),
.C_INIT_FILE("MARIO_ROM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(65536),
.C_READ_DEPTH_A(65536),
.C_ADDRA_WIDTH(16),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(65536),
.C_READ_DEPTH_B(65536),
.C_ADDRB_WIDTH(16),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("16"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 17.198 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(8'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(16'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:51:57 11/06/2011
// Design Name: Kestrel-2 rev 1A
// Module Name: M_kestrel2
// Project Name: Kestrel-2
// Target Devices: NEXYS2
// Tool versions:
// Description:
// The Kestrel 2 computer, top-level integration module.
//
// Dependencies:
// M_uxa, M_mem, M_j1a
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module M_kestrel2(
output N2_CA_O,
output N2_CB_O,
output N2_CC_O,
output N2_CD_O,
output N2_CE_O,
output N2_CF_O,
output N2_CG_O,
output N2_DP_O,
output N2_A0_O,
output N2_A1_O,
output N2_A2_O,
output N2_A3_O,
output N2_HSYNC_O,
output N2_VSYNC_O,
output [2:0] N2_RED_O,
output [2:0] N2_GRN_O,
output [2:1] N2_BLU_O,
input N2_PS2D_I,
input N2_PS2C_I,
input N2_50MHZ_I,
input N2_RST_I
);
// Permanently hold the LED outputs in an inactive state,
// to prevent unnecessary current draw on the part of the
// FPGA.
reg a_, b_, c_, d_, e_, f_, g_, dp_, a0_, a1_, a2_, a3_;
assign N2_CA_O = a_;
assign N2_CB_O = b_;
assign N2_CC_O = c_;
assign N2_CD_O = d_;
assign N2_CE_O = e_;
assign N2_CF_O = f_;
assign N2_CG_O = g_;
assign N2_DP_O = dp_;
assign N2_A0_O = a0_;
assign N2_A1_O = a1_;
assign N2_A2_O = a2_;
assign N2_A3_O = a3_;
initial begin
a_ <= 1; e_ <= 1;
b_ <= 1; f_ <= 1;
c_ <= 1; g_ <= 1;
d_ <= 1; dp_ <= 1;
a0_ <= 1; a1_ <= 1;
a2_ <= 1; a3_ <= 1;
end
// Each major module has its own set of inputs and
// outputs. We declare them here so that the synthesizer
// has complete knowledge of what to expect before we start
// routing signals around.
wire [13:1] j1a_ins_adr_o;
wire [15:0] j1a_ins_dat_i;
wire j1a_ins_cyc_o;
wire [15:1] j1a_dat_adr_o;
reg [15:0] j1a_dat_dat_i;
wire [15:0] j1a_dat_dat_o;
wire j1a_dat_cyc_o;
wire j1a_dat_we_o;
wire j1a_stb_o;
reg j1a_ack_i;
wire pm_dat_ack_o;
wire pm_ins_ack_o;
wire [15:0] pm_dat_o;
reg pm_dat_stb;
wire [15:0] vm_dat_o;
reg vm_dat_stb;
wire vm_dat_ack_o;
wire [13:1] mgia_adr_o;
wire [15:0] mgia_dat_i;
wire mgia_cyc_o;
wire mgia_stb_o;
wire mgia_ack_i;
wire sys_clk;
wire kbd_ack_o;
reg kbd_stb_i;
wire kbd_we_i;
wire [15:0] kbd_dat_o;
// Instantiate the J1A microprocessor.
M_j1a j1a(
.sys_res_i(N2_RST_I),
.sys_clk_i(sys_clk),
.ins_adr_o(j1a_ins_adr_o),
.ins_dat_i(j1a_ins_dat_i),
.dat_adr_o(j1a_dat_adr_o),
.dat_dat_o(j1a_dat_dat_o),
.dat_dat_i(j1a_dat_dat_i),
.dat_we_o(j1a_dat_we_o),
.dat_cyc_o(j1a_dat_cyc_o),
.ins_cyc_o(j1a_ins_cyc_o),
.shr_stb_o(j1a_stb_o),
.shr_ack_i(j1a_ack_i)
);
wire data_access = ~N2_RST_I & j1a_stb_o & j1a_dat_cyc_o;
wire addressing_prg_mem = j1a_dat_adr_o[15:14] == 2'b00;
wire addressing_vid_mem = j1a_dat_adr_o[15:14] == 2'b10;
wire addressing_ps2 = j1a_dat_adr_o[15:2] == 14'h3FFF;
// wire addressing_mou_ps2 = addressing_ps2 & ~j1a_dat_adr_o[0];
wire addressing_kbd_ps2 = addressing_ps2 & j1a_dat_adr_o[1];
assign kbd_we_i = j1a_dat_we_o;
always @* begin
// When fetching data from various resources, the CPU will
// need to select which output data bus to read from.
if (addressing_prg_mem)
j1a_dat_dat_i <= pm_dat_o;
else if (addressing_vid_mem)
j1a_dat_dat_i <= vm_dat_o;
else if (addressing_kbd_ps2)
j1a_dat_dat_i <= kbd_dat_o;
else
j1a_dat_dat_i <= 16'hxxxx;
// Peripherals won't know to drive their buses, however,
// unless told to do so by asserting the appropriate
// data strobes.
pm_dat_stb <= data_access & addressing_prg_mem;
vm_dat_stb <= data_access & addressing_vid_mem;
kbd_stb_i <= data_access & addressing_kbd_ps2;
// Since the Kestrel-2 lacks multi-master support,
// we can get by with simply ORing all the acknowledgements
// together.
j1a_ack_i <= pm_ins_ack_o | pm_dat_ack_o | vm_dat_ack_o | kbd_ack_o;
end
// Program Memory ($0000-$3FFF)
M_mem pm(
.ins_adr_i(j1a_ins_adr_o),
.ins_dat_o(j1a_ins_dat_i),
.ins_cyc_i(j1a_ins_cyc_o),
.ins_stb_i(j1a_stb_o),
.ins_ack_o(pm_ins_ack_o),
.dat_adr_i(j1a_dat_adr_o[13:1]),
.dat_dat_o(pm_dat_o),
.dat_dat_i(j1a_dat_dat_o),
.dat_we_i(j1a_dat_we_o),
.dat_cyc_i(j1a_dat_cyc_o),
.dat_stb_i(pm_dat_stb),
.dat_ack_o(pm_dat_ack_o),
.sys_clk_i(sys_clk),
.sys_rst_i(N2_RST_I)
);
// Video Memory ($8000-$BFFF)
M_mem vm(
.ins_adr_i(mgia_adr_o),
.ins_dat_o(mgia_dat_i),
.ins_cyc_i(mgia_cyc_o),
.ins_stb_i(mgia_stb_o),
.ins_ack_o(mgia_ack_i),
.dat_adr_i(j1a_dat_adr_o[13:1]),
.dat_dat_o(vm_dat_o),
.dat_dat_i(j1a_dat_dat_o),
.dat_we_i(j1a_dat_we_o),
.dat_cyc_i(j1a_dat_cyc_o),
.dat_stb_i(vm_dat_stb),
.dat_ack_o(vm_dat_ack_o),
.sys_clk_i(sys_clk),
.sys_rst_i(N2_RST_I)
);
// Monochrome Graphics Interface Adapter
M_uxa_mgia mgia(
.CLK_I_50MHZ(N2_50MHZ_I),
.RST_I(N2_RST_I),
.CLK_O_25MHZ(sys_clk),
.HSYNC_O(N2_HSYNC_O),
.VSYNC_O(N2_VSYNC_O),
.RED_O(N2_RED_O),
.GRN_O(N2_GRN_O),
.BLU_O(N2_BLU_O),
.MGIA_ADR_O(mgia_adr_o),
.MGIA_DAT_I(mgia_dat_i),
.MGIA_CYC_O(mgia_cyc_o),
.MGIA_STB_O(mgia_stb_o),
.MGIA_ACK_I(mgia_ack_i)
);
// Keyboard PS2IO ($FFFE)
M_uxa_ps2 ps2kbd(
// .ps2_c_oe_o(DELIBERATELY UNUSED),
// .ps2_d_oe_o(DELIBERATELY UNUSED),
.ps2_d_i(N2_PS2D_I),
.ps2_c_i(N2_PS2C_I),
.sys_clk_i(sys_clk),
.sys_reset_i(N2_RST_I),
.io_ack_o(kbd_ack_o),
.io_stb_i(kbd_stb_i),
.io_we_i(kbd_we_i),
.io_dat_i(j1a_dat_dat_o[9:8]),
.io_dat_o(kbd_dat_o)
);
// Video RAM static image (at boot-time)
defparam
vm.ram00_07.WRITE_MODE_A = "READ_FIRST",
vm.ram08_0F.WRITE_MODE_A = "READ_FIRST",
vm.ram10_17.WRITE_MODE_A = "READ_FIRST",
vm.ram18_1F.WRITE_MODE_A = "READ_FIRST",
vm.ram20_27.WRITE_MODE_A = "READ_FIRST",
vm.ram28_2F.WRITE_MODE_A = "READ_FIRST",
vm.ram30_37.WRITE_MODE_A = "READ_FIRST",
vm.ram38_3F.WRITE_MODE_A = "READ_FIRST",
vm.ram00_07.WRITE_MODE_B = "READ_FIRST",
vm.ram08_0F.WRITE_MODE_B = "READ_FIRST",
vm.ram10_17.WRITE_MODE_B = "READ_FIRST",
vm.ram18_1F.WRITE_MODE_B = "READ_FIRST",
vm.ram20_27.WRITE_MODE_B = "READ_FIRST",
vm.ram28_2F.WRITE_MODE_B = "READ_FIRST",
vm.ram30_37.WRITE_MODE_B = "READ_FIRST",
vm.ram38_3F.WRITE_MODE_B = "READ_FIRST",
vm.ram00_07.INIT_3F = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_3E = 256'h55555555555555555555555555555555AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_3D = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_3C = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_3B = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_3A = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_39 = 256'h55555555555555555555000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_38 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_37 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA000C228AF1C2,
vm.ram00_07.INIT_36 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_35 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_34 = 256'h55555555555555555555010C228A8882AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_33 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_32 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA019822FA8882,
vm.ram00_07.INIT_31 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_30 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_2F = 256'h55555555555555555555C1D82A53F082AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_2E = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_2D = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA21F02A528882,
vm.ram00_07.INIT_2C = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_2B = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_2A = 256'h5555555555555555555521FC36228882AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_29 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_28 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAC1F8A223F1CF,
vm.ram00_07.INIT_27 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_26 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_25 = 256'h5555555555555555555501F000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_24 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_23 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAE1E0A0FB7228,
vm.ram00_07.INIT_22 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_21 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_20 = 256'h5555555555555555555501C0A0828A28AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_1F = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_1E = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA0180A0820A28,
vm.ram00_07.INIT_1D = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_1C = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_1B = 256'h555555555555555555558100BC8373EAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_1A = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_19 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA0000A282822A,
vm.ram00_07.INIT_18 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_17 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_16 = 256'h555555555555555555550000A282894DAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_15 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_14 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAE000BC837088,
vm.ram00_07.INIT_13 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_12 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_11 = 256'h55555555555555555555000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_10 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_0F = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAEF88088B8BE7,
vm.ram00_07.INIT_0E = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_0D = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_0C = 256'h55555555555555555555080088929208AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_0B = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_0A = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA080888A2A200,
vm.ram00_07.INIT_09 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_08 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_07 = 256'h55555555555555555555880808F3C387AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_06 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_05 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA081C088AA208,
vm.ram00_07.INIT_04 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_03 = 256'h5555555555555555555555555555555555555555555555555555555555555555,
vm.ram00_07.INIT_02 = 256'h55555555555555555555081C888A9208AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_01 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
vm.ram00_07.INIT_00 = 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAE8083EF38BE7;
// System Firmware
defparam
pm.ram00_07.INIT_00 = 256'h6181710F710F6180200E4001620380016203660061816181730F6600FFFF125C,
pm.ram00_07.INIT_01 = 256'h401A20226303800160817C0C710F6180710F2018400162038001620366006181,
pm.ram00_07.INIT_02 = 256'h61806403630380FF401A61816D0380086180730F80FF69038008401A730F80FF,
pm.ram00_07.INIT_03 = 256'h80016081710F6123618064036303660080FF401A6181630380FF6180710F6123,
pm.ram00_07.INIT_04 = 256'h7D0F80047D0F8003710F6103612361806203401A618161810027003220436303,
pm.ram00_07.INIT_05 = 256'h0000700C80BE0000700C80B8004C40507D0F8008720F6D03800260816D038004,
pm.ram00_07.INIT_06 = 256'h00000000000000000000000F0F0000F0700C80D00000700C80CA0000700C80C4,
pm.ram00_07.INIT_07 = 256'h0000000000000C3038181870666C001800000000000000000000000000000000,
pm.ram00_07.INIT_08 = 256'h663C60420666663C7E3C787E7C1E3C10203C040000003C3C1C7E0C7E3C3C1808,
pm.ram00_07.INIT_09 = 256'h00001800006060001C000600600030001800003C7E3C6666C6667E667C3C7C3C,
pm.ram00_07.INIT_0A = 256'h000000000000FF00020108042010804036AA1830000C00000000080000000000,
pm.ram00_07.INIT_0B = 256'h387C000038002838103800441018001000200004FFFF80018001E0F0FFC0FFFF,
pm.ram00_07.INIT_0C = 256'h10282008102820082E38281010342008C0103030380000107C00080038381010,
pm.ram00_07.INIT_0D = 256'h102820081028200800002810103410082030280808103C202800103420087034,
pm.ram00_07.INIT_0E = 256'h00000000000000000000000F0F0000F040282808081002202800103420084834,
pm.ram00_07.INIT_0F = 256'h00060000241818186C183E54666C001800000000000000000000000000000000,
pm.ram00_07.INIT_10 = 256'h76666066066C661860606C606630663830660C001818666630061C4066662418,
pm.ram00_07.INIT_11 = 256'h000018001860601830000600600018001800600C06306666C666186666666666,
pm.ram00_07.INIT_12 = 256'h00000000000000FF02010804201080406C551818001800000000180000000000,
pm.ram00_07.INIT_13 = 256'h740000001C1400541040444438200000002000047FFEC0034002E0F0FFC0FFFF,
pm.ram00_07.INIT_14 = 256'h280010102800101058440028285810102000101044500030F400100004042810,
pm.ram00_07.INIT_15 = 256'h280010102800101000000028285808102048001010284C100044285810104858,
pm.ram00_07.INIT_16 = 256'h00000000000000000000000F0F0000F04000001010283C100010285810103058,
pm.ram00_07.INIT_17 = 256'h000C00001818300C6818586824FE001800000000000000000000000000000000,
pm.ram00_07.INIT_18 = 256'h7666607E067866186060666066606E381806187E18186666600C3C7C06066638,
pm.ram00_07.INIT_19 = 256'h5C3C18FC00667C00303E3E3C7C3E0C3C3C00300C0C303C3C6C66186666606666,
pm.ram00_07.INIT_1A = 256'h00000000FF000000020108042010804000AA18187E18666666C63C665E3E7C3E,
pm.ram00_07.INIT_1B = 256'h6C007C006428006C10383828542000100720E0043FFCE0072004E0F0FFC000FF,
pm.ram00_07.INIT_1C = 256'h383838387C7C7C7C5840001000000000C410101044280010F4000044181C107C,
pm.ram00_07.INIT_1D = 256'h00000000383838386C3838103838383838500044000054003828383838384444,
pm.ram00_07.INIT_1E = 256'h00000000000000000000000F0F0000F05844444444004C443800383838380858,
pm.ram00_07.INIT_1F = 256'h0018007E7E7E300C32003C10006C001800000000000000000000000000000000,
pm.ram00_07.INIT_20 = 256'h7E66607E06707E18786E66787C606A6C0C0C300000003C3E7C0C6C060C1C6618,
pm.ram00_07.INIT_21 = 256'h666618D6186C66387C666666666000063C00180C1830183C6C7E18667C3C7C66,
pm.ram00_07.INIT_22 = 256'h0000000000FF00000201080420108040005518060C603C6666C6186660606666,
pm.ram00_07.INIT_23 = 256'h740004383C5000640044287C50700010181018081FF8F00F1008E0F0FFC00000,
pm.ram00_07.INIT_24 = 256'h10101010404040408C4010101010101028207C7C381400107410004420040010,
pm.ram00_07.INIT_25 = 256'h303030304444444412440438040404042478442844445444441044444444E464,
pm.ram00_07.INIT_26 = 256'h000000000000000000000FF000F000006444444444445444447C444444443864,
pm.ram00_07.INIT_27 = 256'h003010001818300C6C001A2C00FE001800000000000000000000000000000000,
pm.ram00_07.INIT_28 = 256'h6E66606666786618606666606660667C1818187E0018660666187E0630066618,
pm.ram00_07.INIT_29 = 256'h666618D6187866183066667E6660003E66000C0C30303C18387E186678066066,
pm.ram00_07.INIT_2A = 256'h0000FF0000000000020108042010804000AA1818181818663CD61866603C6666,
pm.ram00_07.INIT_2B = 256'h6C0000007C28006C1038381054200010101808180FF0F81F0810E0F000C00000,
pm.ram00_07.INIT_2C = 256'h1010101060707070F840282828282828D440083000280010140000443C380010,
pm.ram00_07.INIT_2D = 256'h101010107C7C7C7C7E403C1C3C3C3C3C38444410444454444428444444444454,
pm.ram00_07.INIT_2E = 256'h000000000000000000000FF000F0000064444444444464444400444444444444,
pm.ram00_07.INIT_2F = 256'h18601800241818186C007C54006C000000000000000000000000000000000000,
pm.ram00_07.INIT_30 = 256'h6E666066666C661860666C60663060C630000C001818660C66180C6660662418,
pm.ram00_07.INIT_31 = 256'h666618C6186C6618303E6660666000660000060C60306618386618666C66606E,
pm.ram00_07.INIT_32 = 256'h000000FF0000000002010804201080400055181830183C3E3CD6186660067C3E,
pm.ram00_07.INIT_33 = 256'h6C000000001400541004447C38200010200704E007E0FC3F0420E0F000C00000,
pm.ram00_07.INIT_34 = 256'h101010104040404088444444444444442C4428087C5000001400006400000000,
pm.ram00_07.INIT_35 = 256'h101010104040404090444464444444442064441044446444444444444444484C,
pm.ram00_07.INIT_36 = 256'h000000000000000000000FF000F00000583C443C444478444410444444444444,
pm.ram00_07.INIT_37 = 256'h1800100000000C303A00181C006C001800000000000000000000000000000000,
pm.ram00_07.INIT_38 = 256'h663C7E663C66663C603C787E7C1E3CC62018040018103C383C180C3C7E3C183C,
pm.ram00_07.INIT_39 = 256'h663C0CC61866663C30063E3C7C3E003A007E003C7E3C66181042183C663C603C,
pm.ram00_07.INIT_3A = 256'hFF00000000000000020108042010804000AA18307E0C6606187C0C3A607C6006,
pm.ram00_07.INIT_3B = 256'h380000000000003810380010105C00102000040003C0FE7F0240E0F000C00000,
pm.ram00_07.INIT_3C = 256'h383838387C7C7C7C8E387C7C7C7C7C7C5C383810000008001400005C0000007C,
pm.ram00_07.INIT_3D = 256'h38383838383838386E383C3C3C3C3C3C20583810383878383800383838387044,
pm.ram00_07.INIT_3E = 256'h000000000000000000000FF000F0000040043804383880383800383838383844,
pm.ram00_07.INIT_3F = 256'h0000200000000000000000000000000000000000000000000000000000000000;
defparam
pm.ram08_0F.INIT_00 = 256'h0000000000000000000000000000000000000000002000000000000000000000,
pm.ram08_0F.INIT_01 = 256'h0000000070000000003C00000000000000000000000000000000000000000006,
pm.ram08_0F.INIT_02 = 256'h00FF0000000000000201080420108040005500000000003C0000000000006006,
pm.ram08_0F.INIT_03 = 256'h00000000000000000000000000000000200004000180FFFF0180E0F000C00000,
pm.ram08_0F.INIT_04 = 256'h0000000000000000006044444444444404000838000010000000004000000000,
pm.ram08_0F.INIT_05 = 256'h0000000000000000006000000000000000800000000000000000000000000000,
pm.ram08_0F.INIT_06 = 256'h401A40606203401A405A4050401A405D40380038000000000000000000000000,
pm.ram08_0F.INIT_07 = 256'h401A405A62034050401A40634058401A405D720F4056401A406362034066720F,
pm.ram08_0F.INIT_08 = 256'h612340636203401A40638001403E4477401B4471401B4468720F6600FFFF6203,
pm.ram08_0F.INIT_09 = 256'h401A405A8001448444844484448444844484448444846103612340638000710F,
pm.ram08_0F.INIT_0A = 256'h44A444A40491449144914491449144914491449144914491710F6123405A6203,
pm.ram08_0F.INIT_0B = 256'h405D6203401A405D800161036123405A800044AE04A444A444A444A444A444A4,
pm.ram08_0F.INIT_0C = 256'h405A800004B644C244C244C204B644B644B644B644B644B644B644B6710F6123,
pm.ram08_0F.INIT_0D = 256'h89C20000700C89BC720F804044D7700CBF0004CA61036123405D800061036123,
pm.ram08_0F.INIT_0E = 256'h801840048000401A44DF6103612344DC400F804F40048000401A44DC0000700C,
pm.ram08_0F.INIT_0F = 256'h04E2404444DF6600800004E26103612344DC6103612344DF710F612344DF400F,
pm.ram08_0F.INIT_10 = 256'h4058401A44DF04E2404444DC800104E2404444DC6600800004E2404444DF8001,
pm.ram08_0F.INIT_11 = 256'h8050403E61806600401B608160810000700C8A30720F6600FFFF6203401A44DC,
pm.ram08_0F.INIT_12 = 256'h650366008000401A4516610345194519451945194519451945194519450D720F,
pm.ram08_0F.INIT_13 = 256'h60816203401A453880010000700C8A74700C45212537401A4516710F61234516,
pm.ram08_0F.INIT_14 = 256'h0000700C8A9E710F61234538800045216103710F61234538254765036600BFFF,
pm.ram08_0F.INIT_15 = 256'h002300210032001C0046003E003D0036002E00250026001E00160045700C8AA4,
pm.ram08_0F.INIT_16 = 256'h004200410039003800370036003500340033003200310030700C8AC8002B0024,
pm.ram08_0F.INIT_17 = 256'h000B006A0C0000BF000B006A130000CF000B006A700C8AEC0046004500440043,
pm.ram08_0F.INIT_18 = 256'h000B0070140000EF000B00701200000F000B006D0C0000BF000B006D060000BF,
pm.ram08_0F.INIT_19 = 256'h000B0071060000BF000B00711200000F000B00704400008F000B0070110000EF,
pm.ram08_0F.INIT_1A = 256'h000B0071060000DF000B0071180000EF000B0071190000CF000B00710D00005F,
pm.ram08_0F.INIT_1B = 256'h000B00730D00005F000B0073060000FF000B00710D00005F000B0071130000CF,
pm.ram08_0F.INIT_1C = 256'h000B0077110000CF000B00771300000F000B00740C0000BF000B0074060000FF,
pm.ram08_0F.INIT_1D = 256'h000B007A1200004F000B007A440000AF000B00794500003F000B00771700002F,
pm.ram08_0F.INIT_1E = 256'h000B007B440000AF000B007A4500003F000B007A1700000F000B007A1200002F,
pm.ram08_0F.INIT_1F = 256'h000B007C460000FF000B007B4500003F000B007B1700002F000B007B110000CF,
pm.ram08_0F.INIT_20 = 256'h000B007D4600004F000B007D4500003F000B007D1200004F000B007D440000AF,
pm.ram08_0F.INIT_21 = 256'h000B007E4600004F000B007E450000FF000B007E1200004F000B007E440000AF,
pm.ram08_0F.INIT_22 = 256'h000B0080450000FF000B00804500003F000B00801200000F000B0080430000FF,
pm.ram08_0F.INIT_23 = 256'h000B008B0F00009F000B008A0F00007F000B008A440000AF000B008A0F00009F,
pm.ram08_0F.INIT_24 = 256'h000B008C1200002F000B008C1700002F000B008C1300000F000B008C1200002F,
pm.ram08_0F.INIT_25 = 256'h000B008D110000EF000B008D140000EF000B008D1B0000FF000B008D120000AF,
pm.ram08_0F.INIT_26 = 256'h000B008E1700000F000B008E0F00009F000B008E1200002F000B008E0F00007F,
pm.ram08_0F.INIT_27 = 256'h000B00911200000F000B00910F00007F000B0090110000EF000B008E0F00009F,
pm.ram08_0F.INIT_28 = 256'h000B0093120000CF000B00930F00007F000B00921700002F000B00921300000F,
pm.ram08_0F.INIT_29 = 256'h000B00970F00009F000B0097470000DF000B00971200000F000B00944500003F,
pm.ram08_0F.INIT_2A = 256'h000B00971700000F000B00971200002F000B00970F00007F000B0097440000AF,
pm.ram08_0F.INIT_2B = 256'h000B009A0F00007F000B009A440000AF000B009A0F00009F000B00974500003F,
pm.ram08_0F.INIT_2C = 256'h000B009B120000EF000B009B120000AF000B009B120000AF000B009A120000AF,
pm.ram08_0F.INIT_2D = 256'h000B009C110000CF000B009B1300006F000B009B120000AF000B009B140000EF,
pm.ram08_0F.INIT_2E = 256'h000E002D5000001F000E002D120000CF000C00534A00001F000C00530E00005F,
pm.ram08_0F.INIT_2F = 256'h000E0032370000CF000E00324400005F000E002E5000004F000E002E120000CF,
pm.ram08_0F.INIT_30 = 256'h000E00341200000F000E00331300000F000E00333500009F000E0032180000AF,
pm.ram08_0F.INIT_31 = 256'h000E00351200002F000E00343A0000EF000E00341200000F000E00343900001F,
pm.ram08_0F.INIT_32 = 256'h000E00350D00005F000E00351200002F000E00354A0000EF000E00351700000F,
pm.ram08_0F.INIT_33 = 256'h000E003B1200000F000E003A1300000F000E003A3500009F000E00394A00005F,
pm.ram08_0F.INIT_34 = 256'h000E003C3A0000EF000E003C1200000F000E003B3500009F000E003B180000AF,
pm.ram08_0F.INIT_35 = 256'h000E003D3500009F000E003D180000AF000E003D180000AF000E003D1200000F,
pm.ram08_0F.INIT_36 = 256'h000E003E4B00000F000E003E1700000F000E003E120000AF000E003D0C0000BF,
pm.ram08_0F.INIT_37 = 256'h000E004351000075000E00435100000A000E003F0D00005F000E003F1200002F,
pm.ram08_0F.INIT_38 = 256'h000F000D1300004F000F000D1600008F000F000D1200000F000F000D4D0000AF,
pm.ram08_0F.INIT_39 = 256'h000F00101300004F000F00101600008F000F00101200000F000F00104D0000DF,
pm.ram08_0F.INIT_3A = 256'h001000371200000F001000251300006F000F0012110000EF000F00124C0000CF,
pm.ram08_0F.INIT_3B = 256'h001000371800002F001000371200002F001000371300006F001000371300004F,
pm.ram08_0F.INIT_3C = 256'h001000380F0000BF001000381100007F001000381C00001F001000371300006F,
pm.ram08_0F.INIT_3D = 256'h001000394E00009F00100039120000CF001000390F00007F001000382C0000BF,
pm.ram08_0F.INIT_3E = 256'h0010003C1300004F001000391300004F00100039160000CF001000391200000F,
pm.ram08_0F.INIT_3F = 256'h0010003C2C0000BF0010003C0F0000BF0010003C1100007F0010003C1C00001F;
defparam
pm.ram10_17.INIT_00 = 256'h0010003D1200000F0010003D4E00009F0010003D120000CF0010003D0F00007F,
pm.ram10_17.INIT_01 = 256'h0010003F1600006F0010003F4E0000CF0010003D1300004F0010003D160000CF,
pm.ram10_17.INIT_02 = 256'h001000422C0000BF001000420F0000BF001000421100007F0010003F1300004F,
pm.ram10_17.INIT_03 = 256'h001000421300004F001000421600006F001000424C00007F001000420F00007F,
pm.ram10_17.INIT_04 = 256'h001000450F00007F001000452C0000BF001000450F0000BF001000451100007F,
pm.ram10_17.INIT_05 = 256'h001000452C0000BF001000450F0000BF001000451100007F00100045120000CF,
pm.ram10_17.INIT_06 = 256'h001000451600006F001000454C0000EF001000451200002F001000450F00007F,
pm.ram10_17.INIT_07 = 256'h001000531200000F001000534F00002F00100053120000CF001000451300004F,
pm.ram10_17.INIT_08 = 256'h001000531300004F00100053160000CF001000531200002F00100053150000AF,
pm.ram10_17.INIT_09 = 256'h001000561300004F00100056160000CF001000564E0000FF00100056120000CF,
pm.ram10_17.INIT_0A = 256'h0010006D1100007F001000591300004F00100059160000CF001000594D00001F,
pm.ram10_17.INIT_0B = 256'h0010006D5700004F0010006D0F00007F0010006D500000BF0010006D0F0000BF,
pm.ram10_17.INIT_0C = 256'h0010006D1600006F0010006D120000AF0010006D0C0000BF0010006D130000CF,
pm.ram10_17.INIT_0D = 256'h00100074160000CF001000741200004F001000744F0000EF0010006D1300004F,
pm.ram10_17.INIT_0E = 256'h00100077020000CF001000771B0000DF001000771200002F001000741300004F,
pm.ram10_17.INIT_0F = 256'h001000781300004F00100078160000CF001000784F0000EF001000781200002F,
pm.ram10_17.INIT_10 = 256'h0010007C1200002F0010007B020000CF0010007B1B0000DF0010007B1200002F,
pm.ram10_17.INIT_11 = 256'h0010007F1100007F0010007C1300004F0010007C1600006F0010007C4D00004F,
pm.ram10_17.INIT_12 = 256'h0010007F1200000F0010007F0F0000BF0010007F2C0000BF0010007F0F0000BF,
pm.ram10_17.INIT_13 = 256'h0010007F1200002F0010007F0D00001F0010007F0F00007F0010007F5000007F,
pm.ram10_17.INIT_14 = 256'h001000A05700006F001000A01200000F0010007F1300004F0010007F160000CF,
pm.ram10_17.INIT_15 = 256'h001000A01B0000DF001000A0110000EF001000A00F00009F001000A01300000F,
pm.ram10_17.INIT_16 = 256'h001000A11200002F001000A0110000EF001000A0020000CF001000A00F00007F,
pm.ram10_17.INIT_17 = 256'h93020000700C92FC0000700C92F60000700C92F01200004F001000A10F00009F,
pm.ram10_17.INIT_18 = 256'h66008000618062038001403E618180206180299260810000700C93080000700C,
pm.ram10_17.INIT_19 = 256'h710F612344DF80006103612344DC8000498587D0401A4060710F610309856203,
pm.ram10_17.INIT_1A = 256'h450949A4003E62036203401A44DC4050401A44DF401A4060710F612340604574,
pm.ram10_17.INIT_1B = 256'h62038001618062036600800049AE401B618129C26081710F6123497666008000,
pm.ram10_17.INIT_1C = 256'h09D86303800F09AE802B09AE802005006103612344DC8000710F610309B56180,
pm.ram10_17.INIT_1D = 256'h8004608109AE401B62036103801093A045464344414238393637343532333031,
pm.ram10_17.INIT_1E = 256'h49E949E9720F800249E3401A608109C949DE49DE69038008608109CD49CD6903,
pm.ram10_17.INIT_1F = 256'h49F649F649F649F649F6720F800149AE401B608109E949E949E949E949E949E9,
pm.ram10_17.INIT_20 = 256'h941A20202D2D0A0F49EE09F649F649F649F649F649F649F649F649F649F649F6,
pm.ram10_17.INIT_21 = 256'h6E20656550726C20726573744B650A21710F49C449FB62036600800F49B58003,
pm.ram10_17.INIT_22 = 256'h0A0BBF0049B58007944E202430202030442B0A2B09C449C449B5801094323141,
pm.ram10_17.INIT_23 = 256'h9476202730202032442B0A3F0A0BBF1049B580079462208F30202031442B0A35,
pm.ram10_17.INIT_24 = 256'h4A304A260A0BBF3049B58007948A206F30202033442B0A490A0BBF2049B58007,
pm.ram10_17.INIT_25 = 256'h2031522B0A620A0BBF4049B5800794A8201230202030522B0A5809C44A444A3A,
pm.ram10_17.INIT_26 = 256'hBF6049B5800794D0201230202032522B0A6C0A0BBF5049B5800794BC20003020,
pm.ram10_17.INIT_27 = 256'h09C44A714A674A5D4A530A0BBF7049B5800794E4200030202033522B0A760A0B,
pm.ram10_17.INIT_28 = 256'h401A4A80608149C949C949DE608149B58003950820004D2B0A860000700C9504,
pm.ram10_17.INIT_29 = 256'h4A83800049C449E3401A4A8049B58003952A204E4D3D0A97720F80104A0B6203,
pm.ram10_17.INIT_2A = 256'h474F0AB04A944A7B4A4E4A18499409C461034A834A834A834A834A834A834A83,
pm.ram10_17.INIT_2B = 256'h6103610349AE4AB4001A620345626203800162036600455009C449B58002955E,
pm.ram10_17.INIT_2C = 256'h4AC1710F6B8D6B8D610361036B8D6B8D4ABC700C2AC76503401A61816181710F,
pm.ram10_17.INIT_2D = 256'h4ACF4ACF4ACF4ACF4ACF4ACF4ACF4ACF4ACF4ACF4ACF4ACF4ACF4ACF720F8002,
pm.ram10_17.INIT_2E = 256'h710F61036B8D44FB700C2AEC650381756081710F61034AD2455060810ACF4ACF,
pm.ram10_17.INIT_2F = 256'h6B8D4504700C2AFE6503816B6081710F61036B8D4500700C2AF5650381726081,
pm.ram10_17.INIT_30 = 256'h720F401A497C401A4982710F61036B8D4509700C2B07650381746081710F6103,
pm.ram10_17.INIT_31 = 256'h710F6B8D700C2B1E63036600FFFF62038001620366008050401A4982001B4B0B,
pm.ram10_17.INIT_32 = 256'h0B294044498280012B304B204B12730F6600FFFF620380016203660080214B10,
pm.ram10_17.INIT_33 = 256'h6203660061814B0B4B314B0B4B290B31404449828001700C2B354B204B12700C,
pm.ram10_17.INIT_34 = 256'h2B5163036600FFFF620366008009608162036600802F0000700C9688720F8001,
pm.ram10_17.INIT_35 = 256'h6081710F61234B4264036D038004401A4B424B45401B6181720F66008006700C,
pm.ram10_17.INIT_36 = 256'h610361234B428000710F61030B5F61806203800161806203660080004B542B6A,
pm.ram10_17.INIT_37 = 256'h4B744B744B744B744B744B74720F80026103612361814B6C001A4B424B5F4B39,
pm.ram10_17.INIT_38 = 256'h610361234A804B6C0B7A620344D94B6C0B7A620344D74B6C0AA961034B744B74,
pm.ram10_17.INIT_39 = 256'hBF786147401ABF7A6147401ABF7C6147401ABF7E0B7A6203401A4A804B6C0AA9,
pm.ram10_17.INIT_3A = 256'h401ABF6E6147401ABF706147401ABF726147401ABF746147401ABF766147401A,
pm.ram10_17.INIT_3B = 256'h6147401ABF646147401ABF666147401ABF686147401ABF6A6147401ABF6C6147,
pm.ram10_17.INIT_3C = 256'hBF586147401ABF5A6147401ABF5C6147401ABF5E6147401ABF606147401ABF62,
pm.ram10_17.INIT_3D = 256'h401ABF4E6147401ABF506147401ABF526147401ABF546147401ABF566147401A,
pm.ram10_17.INIT_3E = 256'h6147401ABF446147401ABF466147401ABF486147401ABF4A6147401ABF4C6147,
pm.ram10_17.INIT_3F = 256'h401ABF36401ABF38401ABF3A401ABF3C401ABF3E6147401ABF406147401ABF42;
defparam
pm.ram18_1F.INIT_00 = 256'h401ABF26401ABF28401ABF2A401ABF2C401ABF2E401ABF30401ABF32401ABF34,
pm.ram18_1F.INIT_01 = 256'h401ABF16401ABF18401ABF1A401ABF1C401ABF1E401ABF20401ABF22401ABF24,
pm.ram18_1F.INIT_02 = 256'h401ABF06401ABF08401ABF0A401ABF0C401ABF0E401ABF10401ABF12401ABF14,
pm.ram18_1F.INIT_03 = 256'h442B700C987E0B960B910B8C0B880B84700C9870001ABF00401ABF02401ABF04,
pm.ram18_1F.INIT_04 = 256'h6181001A62034C3662038001620366004C3D0AA9700C988C474F4D2B4D3D522B,
pm.ram18_1F.INIT_05 = 256'h4C4F4C4F4C3D710F61036B8D6B8D4C4761036180720F80022C566503401A6181,
pm.ram18_1F.INIT_06 = 256'h4B39710F6B8D700C2C6D6081001A4C4461034C5D401A6103700C4C4F4C4F4C4F,
pm.ram18_1F.INIT_07 = 256'h6123497F805061036123497C6203401A40604050401A44DF700C61474C644C6A,
pm.ram18_1F.INIT_08 = 256'h4AE7710F61036B8D4C74700C2C8B6503805A60810C6F61036123498280006103,
pm.ram18_1F.INIT_09 = 256'h454D8100700C2C9E650380E0608105214C8F4533710F4AE24C864B024AF94AF0,
pm.ram18_1F.INIT_0A = 256'h454D6600FFFF700C2CAD650380F06081710F61036B8D61036123454D6403401A,
pm.ram18_1F.INIT_0B = 256'h454D80004C966403401A454D4CA84C99710F61036B8D61036123454D6403401A,
pm.ram18_1F.INIT_0C = 256'h660080018300730F80FF401A66008001730F6600FFFF401A66008001710F6123,
pm.ram18_1F.INIT_0D = 256'h49768000452144CE45332CE2401A4976700C4CCD4CB84CC82CD74CC2710F6123,
pm.ram18_1F.INIT_0E = 256'h800061036123454D8000700C0CE32CEA401A49794CD2453B4CD8700C61036123,
pm.ram18_1F.INIT_0F = 256'hBF0661036123BF0461036123BF0261036123BF0005334CE36103612349796600,
pm.ram18_1F.INIT_10 = 256'h6123BF1061036123BF0E61036123BF0C61036123BF0A61036123BF0861036123,
pm.ram18_1F.INIT_11 = 256'h61036123BF1A61036123BF1861036123BF1661036123BF1461036123BF126103,
pm.ram18_1F.INIT_12 = 256'hBF2661036123BF2461036123BF2261036123BF2061036123BF1E61036123BF1C,
pm.ram18_1F.INIT_13 = 256'h6123BF3061036123BF2E61036123BF2C61036123BF2A61036123BF2861036123,
pm.ram18_1F.INIT_14 = 256'h61036123BF3A61036123BF3861036123BF3661036123BF3461036123BF326103,
pm.ram18_1F.INIT_15 = 256'hBF446B8D61036123BF426B8D61036123BF406B8D61036123BF3E61036123BF3C,
pm.ram18_1F.INIT_16 = 256'hBF4C6B8D61036123BF4A6B8D61036123BF486B8D61036123BF466B8D61036123,
pm.ram18_1F.INIT_17 = 256'hBF546B8D61036123BF526B8D61036123BF506B8D61036123BF4E6B8D61036123,
pm.ram18_1F.INIT_18 = 256'hBF5C6B8D61036123BF5A6B8D61036123BF586B8D61036123BF566B8D61036123,
pm.ram18_1F.INIT_19 = 256'hBF646B8D61036123BF626B8D61036123BF606B8D61036123BF5E6B8D61036123,
pm.ram18_1F.INIT_1A = 256'hBF6C6B8D61036123BF6A6B8D61036123BF686B8D61036123BF666B8D61036123,
pm.ram18_1F.INIT_1B = 256'hBF746B8D61036123BF726B8D61036123BF706B8D61036123BF6E6B8D61036123,
pm.ram18_1F.INIT_1C = 256'hBF7C6B8D61036123BF7A6B8D61036123BF786B8D61036123BF766B8D61036123,
pm.ram18_1F.INIT_1D = 256'h0014002E1200000F0014700C9BB60CEB4AA949A061036123BF7E6B8D61036123,
pm.ram18_1F.INIT_1E = 256'h0014002F1200000F0014002E020000CF0014002E6A0000310014002E140000EF,
pm.ram18_1F.INIT_1F = 256'h001400301200000F0014002F020000CF0014002F6A0000AB0014002F140000EF,
pm.ram18_1F.INIT_20 = 256'h001400316A0000D000140030020000CF001400306A00007900140030140000EF,
pm.ram18_1F.INIT_21 = 256'h00140035160000AF00140035160000CF001400351200000F001400341200002F,
pm.ram18_1F.INIT_22 = 256'h001400396B0000E9001400371B0000DF001400366B000038001400362500002F,
pm.ram18_1F.INIT_23 = 256'h0014004E0C0000BF0014004E070000EF0014003B0C0000BF0014003B0600007F,
pm.ram18_1F.INIT_24 = 256'h001400510800002F001400511500008F001400511700000F001400516C00008F,
pm.ram18_1F.INIT_25 = 256'h001400530600005F001400511300004F001400511600008F001400510C0000BF,
pm.ram18_1F.INIT_26 = 256'h001400580800004F001400586D00001F001400556C0000EF001400530E00005F,
pm.ram18_1F.INIT_27 = 256'h001400730E0000DF001400730800004F001400582A00007F001400580C0000BF,
pm.ram18_1F.INIT_28 = 256'h001400732600006F00140073090000AF001400730C0000BF001400730600007F,
pm.ram18_1F.INIT_29 = 256'h001400760800004F001400736100002F001400730D00005F001400730600005F,
pm.ram18_1F.INIT_2A = 256'h001400766D00009F001400760C0000BF001400760800002F001400760E0000DF,
pm.ram18_1F.INIT_2B = 256'h001400796E00002F001400791700000F001400796C00008F001400766D00006F,
pm.ram18_1F.INIT_2C = 256'h0014007C6C00008F0014007B0E0000DF0014007B080000AF0014007B300000EF,
pm.ram18_1F.INIT_2D = 256'h0015002470000038001500246F00005F0014007C6D0000CF0014007C6E00007F,
pm.ram18_1F.INIT_2E = 256'h001500250D00005F0015002570000038001500256F00007F001500240D00005F,
pm.ram18_1F.INIT_2F = 256'h0015002A0D00003F0015002A130000CF0015002A6F0000AA0015002A0D00003F,
pm.ram18_1F.INIT_30 = 256'h001500531600008F001500534E00006F001500536F0000AA001500536F00003F,
pm.ram18_1F.INIT_31 = 256'h001500546F0000F1001500546F0000AA001500530D00005F001500536F00009F,
pm.ram18_1F.INIT_32 = 256'h001500550E00005F001500551200000F00150055720000A7001500542900002F,
pm.ram18_1F.INIT_33 = 256'h001500550C0000BF00150055130000CF00150055190000CF001500556F0000F1,
pm.ram18_1F.INIT_34 = 256'h00150056190000CF001500566F0000F1001500551300006F001500551300004F,
pm.ram18_1F.INIT_35 = 256'h00150056110000EF00150056130000CF001500560D00005F00150056130000CF,
pm.ram18_1F.INIT_36 = 256'h00150059110000EF001500594E00006F001500596F0000AA001500596F00003F,
pm.ram18_1F.INIT_37 = 256'h0015005E110000EF0015005E4E00006F0015005E6F0000F10015005E6F00003F,
pm.ram18_1F.INIT_38 = 256'h0015006C730000C90015006C0C0000BF0015006C6F00009F0015006C2300005F,
pm.ram18_1F.INIT_39 = 256'h0015006D4C00002F0015006D0C0000BF0015006D7400003F0015006C260000AF,
pm.ram18_1F.INIT_3A = 256'h00150070110000EF001500704E0000FF00150070120000CF001500706F00007F,
pm.ram18_1F.INIT_3B = 256'h001500864F00005F0015008675000005001500727400005F001500707400005F,
pm.ram18_1F.INIT_3C = 256'h001500894F00002F00150089740000FA001500896F00003F001500861400002F,
pm.ram18_1F.INIT_3D = 256'h0015008C70000038001500890D00003F00150089740000FA00150089110000EF,
pm.ram18_1F.INIT_3E = 256'h0015008C110000EF0015008C4E0000FF0015008C120000CF0015008C0C0000BF,
pm.ram18_1F.INIT_3F = 256'h0015008F0C0000BF0015008F700000380015008F0D00009F0015008F740000FA;
defparam
pm.ram20_27.INIT_00 = 256'h001500911100007F0015008F110000EF0015008F4E0000FF0015008F740000FA,
pm.ram20_27.INIT_01 = 256'h00150092110000EF001500924E00006F001500920F0000BF001500926F00003F,
pm.ram20_27.INIT_02 = 256'h001500A47500008A001500931A00009F001500930C0000BF001500930F00007F,
pm.ram20_27.INIT_03 = 256'h001500A80F00009F001500A80C0000BF001500A80600009F001500A62200009F,
pm.ram20_27.INIT_04 = 256'h001500A96700006F001500A91700000F001500A87600000C001500A8610000FF,
pm.ram20_27.INIT_05 = 256'h001500A90600009F001500A90F00007F001500A96700006F001500A91700000F,
pm.ram20_27.INIT_06 = 256'h001500AC1600002F001500AC1200000F001500AC2400002F001500A90D00005F,
pm.ram20_27.INIT_07 = 256'h001500AC130000CF001500AC3C00004F001500AC1200002F001500AC1400000F,
pm.ram20_27.INIT_08 = 256'h001500B07600000C001500AD1700002F001500AD1300000F001500AD110000EF,
pm.ram20_27.INIT_09 = 256'h001500B1140000EF001500B12400002F001500B0140000EF001500B02400002F,
pm.ram20_27.INIT_0A = 256'h001500B11200002F001500B17600009A001500B17600009A001500B11B0000DF,
pm.ram20_27.INIT_0B = 256'h001500B4110000CF001500B4750000BF001500B4110000CF001500B477000036,
pm.ram20_27.INIT_0C = 256'h001500B5750000F9001500B51700000F001500B4250000AF001500B41700002F,
pm.ram20_27.INIT_0D = 256'h001500BF0F00009F001500BF0C0000BF001500BF0600009F001500B5250000AF,
pm.ram20_27.INIT_0E = 256'h001500BF78000021001500BF150000CF001500BF150000AF001500BF610000FF,
pm.ram20_27.INIT_0F = 256'h001500C01300000F001500BF7600000C001500BF0D00003F001500BF130000CF,
pm.ram20_27.INIT_10 = 256'h001500C0140000CF001500C0220000DF001500C06500008F001500C01200000F,
pm.ram20_27.INIT_11 = 256'h001500CA1200004F001500C10D00005F001500C10600009F001500C10F00007F,
pm.ram20_27.INIT_12 = 256'h001500CA4F00002F001500CA1200004F001500CA6F00003F001500CA1200002F,
pm.ram20_27.INIT_13 = 256'h001500CB1700000F001500CB140000EF001500CB0D00003F001500CB1200000F,
pm.ram20_27.INIT_14 = 256'h001500CD1200002F001500CC740000EF001500CC1600008F001500CC190000CF,
pm.ram20_27.INIT_15 = 256'h001500D04F00002F001500D0740000FA001500D06F00003F001500CD1400000F,
pm.ram20_27.INIT_16 = 256'h001500D00D00003F001500D0740000FA001500D0740000EF001500D01600008F,
pm.ram20_27.INIT_17 = 256'h001500E47500008A001500E31300002F001500E21300002F001500E11300002F,
pm.ram20_27.INIT_18 = 256'h001500E8770000C0001500E7750000F9001500E675000067001500E575000067,
pm.ram20_27.INIT_19 = 256'h001500EC75000039001500EB75000014001500EA75000039001500E97800002D,
pm.ram20_27.INIT_1A = 256'h001500F07600002C001500EF1B0000DF001500EE75000039001500ED75000014,
pm.ram20_27.INIT_1B = 256'h001500FA1300002F001500F36C00004F001500F2750000BF001500F177000036,
pm.ram20_27.INIT_1C = 256'h001500FE75000067001500FD7500008A001500FC1300002F001500FB1300002F,
pm.ram20_27.INIT_1D = 256'h62038001403E6181618100011300002F01150000750000F9001500FF75000067,
pm.ram20_27.INIT_1E = 256'h51DB51DB51DB51DB51DB51DB51DB51DB51DB51DB51DB51DB718C620380016180,
pm.ram20_27.INIT_1F = 256'h51F451F451F451F451F451F451F4720F8001403E6181802011DB51DB51DB51DB,
pm.ram20_27.INIT_20 = 256'h520D120951E411F951F951F951F911F451F451F451F451F451F451F451F451F4,
pm.ram20_27.INIT_21 = 256'h802E120D520D520D520D520D520D520D520D520D520D520D520D520D520D520D,
pm.ram20_27.INIT_22 = 256'h52245224121F521F521F521F521F521F521F521F521F521F720F8001403E6181,
pm.ram20_27.INIT_23 = 256'h8000122E522E522E522E522E522E522E522E522E122452245224522452245224,
pm.ram20_27.INIT_24 = 256'h4DD9523F1245610361236600FEFF6600401A6600FEFF710F61035236520F4DD9,
pm.ram20_27.INIT_25 = 256'h0016001F12554CF61255610361236600F77766008000124544CE610361234060,
pm.ram20_27.INIT_26 = 256'h001600226D00003F0016001F0E00007F0016001F0800004F0016001F130000CF,
pm.ram20_27.INIT_27 = 256'h001600222A0000EF001600221B00002F001600220F00009F001600221200004F,
pm.ram20_27.INIT_28 = 256'h001600220800004F001600221400000F001600220F00007F00160022110000EF,
pm.ram20_27.INIT_29 = 256'h001600230600007F00160023110000EF001600236D00003F001600220E00007F,
pm.ram20_27.INIT_2A = 256'h001600230D00005F00160023080000CF001600231400000F001600230C0000BF,
pm.ram20_27.INIT_2B = 256'h00160023180000AF00160023080000CF001600231200000F001600237B0000AF,
pm.ram20_27.INIT_2C = 256'h001600245D00006F001600240D00009F001600245D00006F001600230D00005F,
pm.ram20_27.INIT_2D = 256'h001600276D00003F001600245D00006F001600242900002F001600242900000F,
pm.ram20_27.INIT_2E = 256'h001600272A0000EF001600270900000F001600270F00009F001600271200004F,
pm.ram20_27.INIT_2F = 256'h001600270800004F001600271400000F001600270F00007F00160027110000EF,
pm.ram20_27.INIT_30 = 256'h0017007F0000003F001600277B0000AF001600270900000F001600270E00007F,
pm.ram20_27.INIT_31 = 256'h0017007F7E00004F0017007F0F00009F0017007F1200002F0017007F0F00001F,
pm.ram20_27.INIT_32 = 256'h0017008B0C0000BF0017008B0A0000DF0017007F130000CF0017007F0F00007F,
pm.ram20_27.INIT_33 = 256'h0017008B1300006F0017008B1800004F0017008B0C0000BF0017008B0A0000FF,
pm.ram20_27.INIT_34 = 256'h0017008B0E00002F0017008B0C0000BF0017008B7E0000EF0017008B1200002F,
pm.ram20_27.INIT_35 = 256'h0017008E1200000F0017008E130000CF0017008B0E00007F0017008B7E0000EF,
pm.ram20_27.INIT_36 = 256'h0017008F3500009F0017008F7E0000FE0017008E0E00002F0017008E7E0000EF,
pm.ram20_27.INIT_37 = 256'h0017008F0F00009F0017008F0F00001F0017008F1200000F0017008F1300000F,
pm.ram20_27.INIT_38 = 256'h001700902900002F001700900F0000BF001700900C0000BF001700907E0000EF,
pm.ram20_27.INIT_39 = 256'h001700912A00001F00170091180000AF001700910C0000BF001700911200000F,
pm.ram20_27.INIT_3A = 256'h001700927E0000FE001700920E00007F001700927E0000EF001700920F00007F,
pm.ram20_27.INIT_3B = 256'h001700AD1200006F001700AC1200004F001700947F000009001700920D00005F,
pm.ram20_27.INIT_3C = 256'h001700AD7D0000DF001700AD7E00009F001700AD120000AF001700AD1200006F,
pm.ram20_27.INIT_3D = 256'h001700AE020000CF001700AD8000004F001700AD1200004F001700AD1200000F,
pm.ram20_27.INIT_3E = 256'h001700B20C0000BF001700B2060000BF001700B2060000DF001700AF4100007F,
pm.ram20_27.INIT_3F = 256'h001700B21200002F001700B2130000CF001700B21200004F001700B2180000EF;
defparam
pm.ram28_2F.INIT_00 = 256'h001700B38000007F001700B30C0000BF001700B3190000CF001700B31B0000FF,
pm.ram28_2F.INIT_01 = 256'h001700B3020000CF001700B3190000AF001700B31C00007F001700B31300000F,
pm.ram28_2F.INIT_02 = 256'h001700B72900000F001700B71200000F001700B41B0000DF001700B41800006F,
pm.ram28_2F.INIT_03 = 256'h001700B8120000AF001700B81200000F001700B88100000F001700B71200000F,
pm.ram28_2F.INIT_04 = 256'h001700BC0900000F001700B91B0000DF001700B8020000CF001700B8110000EF,
pm.ram28_2F.INIT_05 = 256'h001700BE110000CF001700BE8200003F001700BC810000BF001700BC7C00005F,
pm.ram28_2F.INIT_06 = 256'h001800270C0000BF001800270A00006F001700BF160000AF001700BF8200006F,
pm.ram28_2F.INIT_07 = 256'h00180027110000EF00180027020000CF001800271700002F001800271200000F,
pm.ram28_2F.INIT_08 = 256'h0018002A1300004F0018002A0D00003F0018002A820000CB001800275D00006F,
pm.ram28_2F.INIT_09 = 256'h0018002C820000F60018002A0D00009F0018002A820000CB0018002A1300006F,
pm.ram28_2F.INIT_0A = 256'h00180030390000DF001800302300005F0018002E820000F60018002D820000F6,
pm.ram28_2F.INIT_0B = 256'h001800330C00006F00180033830000BD00180030220000DF001800302900000F,
pm.ram28_2F.INIT_0C = 256'h0018003A4100009F001800393100001F00180036830000BD001800330E0000FF,
pm.ram28_2F.INIT_0D = 256'h0018003C0C00007A0018003B3100001F0018003A830000DC0018003A8000007F,
pm.ram28_2F.INIT_0E = 256'h0018003D0E0000BF0018003D0C00007A0018003C1600008F0018003C0C0000BF,
pm.ram28_2F.INIT_0F = 256'h0018003F0C00007A0018003E8400000D0018003E8000007F0018003E4100009F,
pm.ram28_2F.INIT_10 = 256'h0018004D0A0000DF0018004D6C0000AF00180043300000EF0018003F0E0000DF,
pm.ram28_2F.INIT_11 = 256'h0018004D0C0000BF0018004D0A0000FF0018004D150000CF0018004D0C0000BF,
pm.ram28_2F.INIT_12 = 256'h001800511200000F001800517E00009F0018004D1300006F0018004D1800004F,
pm.ram28_2F.INIT_13 = 256'h001800510D00005F00180051130000CF00180051180000EF001800510A00006F,
pm.ram28_2F.INIT_14 = 256'h001800525D00006F001800523600001F001800523500009F001800521200000F,
pm.ram28_2F.INIT_15 = 256'h001800555D00006F00180052350000BF001800521200002F001800521400000F,
pm.ram28_2F.INIT_16 = 256'h001800551200004F001800555D00006F001800550D00005F001800550A00006F,
pm.ram28_2F.INIT_17 = 256'h0018006F1200004F001800552B0000EF001800555D00008F001800551700000F,
pm.ram28_2F.INIT_18 = 256'h00180070120000CF0018006F840000350018006F3100005F0018006F1600008F,
pm.ram28_2F.INIT_19 = 256'h001800702B0000EF001800700F0000BF001800701100007F00180070150000CF,
pm.ram28_2F.INIT_1A = 256'h001800710D00003F001800710F0000BF00180071130000CF001800715D00006F,
pm.ram28_2F.INIT_1B = 256'h001800711400000F001800711200002F001800711300004F00180071130000CF,
pm.ram28_2F.INIT_1C = 256'h001800720F0000BF001800725E00001F001800728500002F001800715D00008F,
pm.ram28_2F.INIT_1D = 256'h001800735E00008F001800728500009F00180072120000AF001800722900000F,
pm.ram28_2F.INIT_1E = 256'h001800748600002F001800742900000F001800740F00007F001800735E00008F,
pm.ram28_2F.INIT_1F = 256'h001800750A00006F001800755D00006F001800751700000F001800755D00006F,
pm.ram28_2F.INIT_20 = 256'h001800780900000F001800755E00008F001800750E00002F00180075180000AF,
pm.ram28_2F.INIT_21 = 256'h001800788600007F001800784600002F001800782900000F001800787C00005F,
pm.ram28_2F.INIT_22 = 256'h0018007E2300001F0018007E2900000F0018007E1300000F0018007B8600007F,
pm.ram28_2F.INIT_23 = 256'h001800860E0000DF001800860C00007A001800808800005F0018007E6100002F,
pm.ram28_2F.INIT_24 = 256'h001900140C0000BF001900148900007F001800870E0000BF001800870C00007A,
pm.ram28_2F.INIT_25 = 256'h001900150100004F001900140E00002F001900148900007F001900141200004F,
pm.ram28_2F.INIT_26 = 256'h001900181200002F001900155E00001F001900155D00008F001900156000007F,
pm.ram28_2F.INIT_27 = 256'h001900341200004F001900340E00007F00190034050000BF001900341200000F,
pm.ram28_2F.INIT_28 = 256'h001900351200000F001900351400000F001900342F00006F001900340D00003F,
pm.ram28_2F.INIT_29 = 256'h00190036140000CF001900351200000F001900351300006F001900351600002F,
pm.ram28_2F.INIT_2A = 256'h001900360600009F001900361200000F001900361400000F001900361300004F,
pm.ram28_2F.INIT_2B = 256'h001900370F00009F001900371200002F001900361600002F001900360C0000BF,
pm.ram28_2F.INIT_2C = 256'h001900373C00004F001900370C0000BF001900370600009F001900371C00001F,
pm.ram28_2F.INIT_2D = 256'h001900373C00000F001900370C0000BF001900370600009F001900371200002F,
pm.ram28_2F.INIT_2E = 256'h001900380F00007F001900371700000F00190037120000AF001900371D00002F,
pm.ram28_2F.INIT_2F = 256'h00190038020000CF001900381600008F001900381200000F001900381700002F,
pm.ram28_2F.INIT_30 = 256'h0019003B110000EF0019003B8A00006F0019003B1700000F00190038110000EF,
pm.ram28_2F.INIT_31 = 256'h0019003E0D00003F0019003E1200004F0019003E0D00005F0019003E050000BF,
pm.ram28_2F.INIT_32 = 256'h0019003E0D00005F0019003E8A00004F0019003E1200000F0019003E140000EF,
pm.ram28_2F.INIT_33 = 256'h0019003F1B0000DF0019003F140000AF0019003F1200000F0019003E2A00007F,
pm.ram28_2F.INIT_34 = 256'h001900401200000F001900408A00006F0019003F1C00001F0019003F020000CF,
pm.ram28_2F.INIT_35 = 256'h001900411600002F001900411200000F001900410D00003F001900411200004F,
pm.ram28_2F.INIT_36 = 256'h001900422A00007F001900421300006F00190042140000EF001900421200002F,
pm.ram28_2F.INIT_37 = 256'h001900431B0000DF001900431B0000DF001900420D00005F00190042050000BF,
pm.ram28_2F.INIT_38 = 256'h001900440C0000BF001900448A00004F001900441B0000DF00190043020000CF,
pm.ram28_2F.INIT_39 = 256'h00190045160000CF001900450C0000BF00190045050000BF001900441D00005F,
pm.ram28_2F.INIT_3A = 256'h001900451700002F001900450D00005F001900458A00004F001900451200002F,
pm.ram28_2F.INIT_3B = 256'h00190048110000EF00190048140000EF001900481200000F001900471200002F,
pm.ram28_2F.INIT_3C = 256'h00190049140000EF001900491200000F00190048020000CF00190048610000CF,
pm.ram28_2F.INIT_3D = 256'h0019004A1200000F00190049020000CF00190049610000FF00190049110000EF,
pm.ram28_2F.INIT_3E = 256'h0019004A020000CF0019004A6200002F0019004A110000EF0019004A140000EF,
pm.ram28_2F.INIT_3F = 256'h0019004B6200005F0019004B110000EF0019004B140000EF0019004B1200000F;
defparam
pm.ram30_37.INIT_00 = 256'h0019004F0600009F0019004C1700002F0019004C110000EF0019004B020000CF,
pm.ram30_37.INIT_01 = 256'h0019004F0D00003F0019004F1200004F0019004F0F00009F0019004F0C0000BF,
pm.ram30_37.INIT_02 = 256'h0019004F0F00007F0019004F8C00002F0019004F2A00007F0019004F8E00002E,
pm.ram30_37.INIT_03 = 256'h001A001E0900000F001A001B1600008F0019004F0D00005F0019004F0600009F,
pm.ram30_37.INIT_04 = 256'h001A001E8F0000BF001A001E0D00003F001A001E1200000F001A001E7C00005F,
pm.ram30_37.INIT_05 = 256'h001A00240900000F001A00218F0000EF001A001E8F0000BF001A001E810000BF,
pm.ram30_37.INIT_06 = 256'h001A00248F0000BF001A00240D00003F001A00241200000F001A00247C00005F,
pm.ram30_37.INIT_07 = 256'h001A0024160000CF001A00248F0000BF001A00241200000F001A0024810000BF,
pm.ram30_37.INIT_08 = 256'h001A002E1A0000FF001A00286000007F001A00288F0000EF001A00266000007F,
pm.ram30_37.INIT_09 = 256'h001A00351B0000DF001A0030900000EF001A002E3100005F001A002E160000CF,
pm.ram30_37.INIT_0A = 256'h001A003A1200000F001A003A9100005F001A003A1B0000FF001A00379100002A,
pm.ram30_37.INIT_0B = 256'h001A003B1B0000FF001A003A110000EF001A003A020000CF001A003A1C00007F,
pm.ram30_37.INIT_0C = 256'h001A003E1200000F001A003B1C00007F001A003B1200000F001A003B8100000F,
pm.ram30_37.INIT_0D = 256'h001A003F8F00002F001A003F1B0000FF001A003E110000EF001A003E020000EF,
pm.ram30_37.INIT_0E = 256'h001A0040110000CF001A0040140000EF001A003F0300002F001A003F1200000F,
pm.ram30_37.INIT_0F = 256'h001A00408A00001F001A00401C00007F001A0040890000AF001A0040110000CF,
pm.ram30_37.INIT_10 = 256'h001A0052200000EF001A00522B0000EF001A0052920000BF001A0043910000FF,
pm.ram30_37.INIT_11 = 256'h001A00560300004F001A00566000007F001A0056160000CF001A0053930000DF,
pm.ram30_37.INIT_12 = 256'h001A0059020000CF001A00599400002A001A00591200000F001A00599100007F,
pm.ram30_37.INIT_13 = 256'h001A005A020000CF001A005A0300004F001A005A1200000F001A005A9200009F,
pm.ram30_37.INIT_14 = 256'h001A005E0300004F001A005E9100007F001A005B9400001F001A005A110000EF,
pm.ram30_37.INIT_15 = 256'h001A00609400001F001A005F020000EF001A005F9200009F001A005E020000CF,
pm.ram30_37.INIT_16 = 256'h001A00710900000F001A00701600008F001A00700C0000BF001A00700800008F,
pm.ram30_37.INIT_17 = 256'h001A00722900000F001A00710D00003F001A00711200000F001A00717C00005F,
pm.ram30_37.INIT_18 = 256'h001A00770800008F001A00731600006F001A00729100001F001A0072940000DF,
pm.ram30_37.INIT_19 = 256'h001A00781200000F001A00787C00005F001A00780900000F001A00770C0000BF,
pm.ram30_37.INIT_1A = 256'h001A00799100001F001A00799400006F001A00792900000F001A00780D00003F,
pm.ram30_37.INIT_1B = 256'h001A00810800008F001A007D9500003F001A007C950000CF001A007A1600006F,
pm.ram30_37.INIT_1C = 256'h001A00880800008F001A00819600007F001A00819600004F001A00810C0000BF,
pm.ram30_37.INIT_1D = 256'h001A00981200000F001A00890E0000BF001A00890800008F001A00880E0000DF,
pm.ram30_37.INIT_1E = 256'h001A00981200000F001A00981700004F001A00981200000F001A00981700000F,
pm.ram30_37.INIT_1F = 256'h001A0099110000EF001A0099220000DF001A0099320000EF001A00986700009F,
pm.ram30_37.INIT_20 = 256'h001A009F0C0000BF001A009F0800008F001A009F970000BF001A009B97000023,
pm.ram30_37.INIT_21 = 256'h001A00B3970000BF001A00A1970000CA001A009F2300005F001A009F1600008F,
pm.ram30_37.INIT_22 = 256'h001A00B49800001F001A00B49600009F001A00B4110000EF001A00B46E0000BF,
pm.ram30_37.INIT_23 = 256'h001A00B70600007F001A00B70C0000BF001A00B7180000AF001A00B70600007F,
pm.ram30_37.INIT_24 = 256'h001A00B70800002F001A00B70E0000DF001A00B7070000EF001A00B70D00005F,
pm.ram30_37.INIT_25 = 256'h001A00BB0400004F001A00BB0C0000BF001A00BB0500003F001A00B70E0000DF,
pm.ram30_37.INIT_26 = 256'h001A00BD9700009F001A00BD2000008F001A00BD9800005F001A00BC9800009F,
pm.ram30_37.INIT_27 = 256'h001A00BE0400006F001A00BE0C0000BF001A00BE0500001F001A00BD2300005F,
pm.ram30_37.INIT_28 = 256'h001A00CB0E00002F001A00CB0800000F001A00CA1500004F001A00BE9800003F,
pm.ram30_37.INIT_29 = 256'h001A00CB0D00005F001A00CB0800002F001A00CB0D00005F001A00CB0A0000DF,
pm.ram30_37.INIT_2A = 256'h001A00CB0D00005F001A00CB0800004F001A00CB0D00005F001A00CB070000EF,
pm.ram30_37.INIT_2B = 256'h001A00CE0E00005F001A00CE0600005F001A00CB0E00002F001A00CB0600005F,
pm.ram30_37.INIT_2C = 256'h001A00CE0C0000BF001A00CE070000EF001A00CE0C0000BF001A00CE0800004F,
pm.ram30_37.INIT_2D = 256'h001A00CE0C0000BF001A00CE0A0000DF001A00CE0C0000BF001A00CE0800002F,
pm.ram30_37.INIT_2E = 256'h001A00D70C0000BF001A00D70600007F001A00CE0E00005F001A00CE0800000F,
pm.ram30_37.INIT_2F = 256'h001A00D72700000F001A00D71B0000FF001A00D70C0000BF001A00D70800004F,
pm.ram30_37.INIT_30 = 256'h001A00D80C0000BF001A00D80600005F001A00D7260000AF001A00D7220000DF,
pm.ram30_37.INIT_31 = 256'h001A00D86100002F001A00D8220000DF001A00D82A00007F001A00D81200002F,
pm.ram30_37.INIT_32 = 256'h001A00DC0E00002F001A00DC0600005F001A00DB100000CF001A00DB9A00003F,
pm.ram30_37.INIT_33 = 256'h001A00DC0E0000DF001A00DC0A0000DF001A00DC0E0000DF001A00DC0800004F,
pm.ram30_37.INIT_34 = 256'h001A00DC0D00005F001A00DC070000EF001A00DC0E0000DF001A00DC0800002F,
pm.ram30_37.INIT_35 = 256'h001A00DE2300005F001A00DE1200000F001A00DD2000008F001A00DD9600009F,
pm.ram30_37.INIT_36 = 256'h001A00DF110000EF001A00DF9900006F001A00DF100000FF001A00DE9A00009F,
pm.ram30_37.INIT_37 = 256'h001A00F31600008F001A00F36E0000BF001A00F36C00008F001A00DF200000EF,
pm.ram30_37.INIT_38 = 256'h001A00F60C0000BF001A00F60800004F001A00F60C0000BF001A00F60800002F,
pm.ram30_37.INIT_39 = 256'h001A00F70C0000BF001A00F70600005F001A00F61300004F001A00F6130000CF,
pm.ram30_37.INIT_3A = 256'h001A00FB1200006F001A00FB6D00003F001A00F70D00005F001A00F70800004F,
pm.ram30_37.INIT_3B = 256'h001A00FC1B0000DF001A00FC7B0000AF001A00FB110000CF001A00FB2B00001F,
pm.ram30_37.INIT_3C = 256'h001A00FF110000EF001A00FE1600008F001A00FE6E0000BF001A00FC020000CF,
pm.ram30_37.INIT_3D = 256'h011A00061200006F011A00066D00003F011A00029C00009F011A00019C00009F,
pm.ram30_37.INIT_3E = 256'h011A0007220000DF011A00077B0000AF011A0006110000CF011A00062B00001F,
pm.ram30_37.INIT_3F = 256'h011A00092300005F011A0009220000DF011A00096D00003F011A0007020000CF;
defparam
pm.ram38_3F.INIT_00 = 256'h011A000D9D00004F011A000B110000EF011A000A1600008F011A000A6E0000BF,
pm.ram38_3F.INIT_01 = 256'h011A002C0A00006F011A002B0F00007F011A000E9D0000BF011A000E2300005F,
pm.ram38_3F.INIT_02 = 256'h011A002C1400000F011A002C3700004F011A002C390000FF011A002C0C0000BF,
pm.ram38_3F.INIT_03 = 256'h011A002D3700008F011A002D390000FF011A002D0C0000BF011A002D0A00006F,
pm.ram38_3F.INIT_04 = 256'h011A002D0D00005F011A002D1700000F011A002D0D00009F011A002D1200004F,
pm.ram38_3F.INIT_05 = 256'h011A00340C0000BF011A0034180000AF011A0034180000AF011A00340A00006F,
pm.ram38_3F.INIT_06 = 256'h011A0037370000AF011A00370F00007F011A00346000007F011A0034370000AF,
pm.ram38_3F.INIT_07 = 256'h001B002E0C0000BF001B002E9F00002E011A00370D00005F011A00371200002F,
pm.ram38_3F.INIT_08 = 256'h001B00301500006F001B00309F00004F001B00301200000F001B002E0C0000BF,
pm.ram38_3F.INIT_09 = 256'h001B00310C0000BF001B00319F00002E001B0031180000EF001B00311700000F,
pm.ram38_3F.INIT_0A = 256'h001B00379F0000B8001B00312C00002F001B00310C0000BF001B0031130000CF,
pm.ram38_3F.INIT_0B = 256'h001B0037140000CF001B00371200000F001B00379F00004F001B00370D00009F,
pm.ram38_3F.INIT_0C = 256'h001B00389F0000B8001B00389F00006F001B0038190000CF001B00381200000F,
pm.ram38_3F.INIT_0D = 256'h001B003A110000EF001B00392B00008F001B00399F0000B8001B00382B00008F,
pm.ram38_3F.INIT_0E = 256'h001B004D1100007F001B003A2B00005F001B003A2900000F001B003A9F0000B8,
pm.ram38_3F.INIT_0F = 256'h001B004D0F0000BF001B004D2B0000EF001B004D0F0000BF001B004D1B0000FF,
pm.ram38_3F.INIT_10 = 256'h001B004E0F00001F001B004E0C0000BF001B004E9F00002E001B004D2B00008F,
pm.ram38_3F.INIT_11 = 256'h001B004E1200000F001B004E180000AF001B004E130000CF001B004E180000EF,
pm.ram38_3F.INIT_12 = 256'h001B004F2900000F001B004F0F0000BF001B004E1300000F001B004E0C0000BF,
pm.ram38_3F.INIT_13 = 256'h001B004F1600008F001B004F2E00003F001B004F1200004F001B004F120000AF,
pm.ram38_3F.INIT_14 = 256'h001B00500D00003F001B00500F00007F001B00502C00002F001B00500C0000BF,
pm.ram38_3F.INIT_15 = 256'h001B0051020000CF001B00501B0000DF001B00501C00001F001B00502A00007F,
pm.ram38_3F.INIT_16 = 256'h001B00540C0000BF001B00549F00002E001B00511B0000DF001B00510F00007F,
pm.ram38_3F.INIT_17 = 256'h001B0054130000CF001B0054180000EF001B00541700000F001B00540F00001F,
pm.ram38_3F.INIT_18 = 256'h001B0056180000EF001B00560F00001F001B00560C0000BF001B00569F00002E,
pm.ram38_3F.INIT_19 = 256'h001B00570C0000BF001B00571200000F001B0057180000AF001B0056130000CF,
pm.ram38_3F.INIT_1A = 256'h001B0057220000DF001B00572C00002F001B00572300005F001B00571300000F,
pm.ram38_3F.INIT_1B = 256'h001B00670C0000BF001B00670600009F001B0059A300000F001B0057110000EF,
pm.ram38_3F.INIT_1C = 256'h001B0068140000EF001B00680D00003F001B00681200004F001B00670F00009F,
pm.ram38_3F.INIT_1D = 256'h001B00691200004F001B00682A00007F001B00680F00009F001B00681200000F,
pm.ram38_3F.INIT_1E = 256'h001B0069610000CF001B0069140000EF001B00691300006F001B00690C0000FF,
pm.ram38_3F.INIT_1F = 256'h001B006A1B0000DF001B006A8A00006F001B006A1C00001F001B00692A00007F,
pm.ram38_3F.INIT_20 = 256'h001B006B0F00007F001B006A1400002F001B006A0F00007F001B006A110000EF,
pm.ram38_3F.INIT_21 = 256'h001B006E1200000F001B006E1200000F001B006B0D00005F001B006B0600009F,
pm.ram38_3F.INIT_22 = 256'h001B006E0F00009F001B006E0D00003F001B006E1200004F001B006E110000EF,
pm.ram38_3F.INIT_23 = 256'h001C00161B0000FF001C00160F00009F001B006E0F00007F001B006E2A00007F,
pm.ram38_3F.INIT_24 = 256'h001C00171C00001F001C00171300000F001C00162B00001F001C00160F0000BF,
pm.ram38_3F.INIT_25 = 256'h001C00181B0000DF001C00180F00007F001C00172A00007F001C00171B0000DF,
pm.ram38_3F.INIT_26 = 256'h001C001B1400000F001C001B110000CF001C001BA5000059001C001B1B0000FF,
pm.ram38_3F.INIT_27 = 256'h001C001E2C00002F001C001E1200000F001C001B150000AF001C001B1700002F,
pm.ram38_3F.INIT_28 = 256'h001C001E1500004F001C001E1B0000FF001C001E1700002F001C001E130000CF,
pm.ram38_3F.INIT_29 = 256'h001C001F140000EF001C001F0D00003F001C001F1700002F001C001F1200000F,
pm.ram38_3F.INIT_2A = 256'h001C0023A5000059001C00201B0000DF001C001F0D00009F001C001F1200004F,
pm.ram38_3F.INIT_2B = 256'h001C00392900000F001C0039A60000FF001C0039110000EF001C0023150000AF,
pm.ram38_3F.INIT_2C = 256'h001C00391600008F001C00392E00003F001C00391200004F001C00391200002F,
pm.ram38_3F.INIT_2D = 256'h001C003D1200000F001C003CA800001F001C003C2C00002F001C003C1200000F,
pm.ram38_3F.INIT_2E = 256'h001C003D2A00007F001C003D0D00003F001C003DA60000FF001C003D2C00002F,
pm.ram38_3F.INIT_2F = 256'h001C003E2D00001F001C003E2C0000BF001C003E1200006F001C003E1200006F,
pm.ram38_3F.INIT_30 = 256'h001C0042140000EF001C00420D00003F001C00421200004F001C003F2C00002F,
pm.ram38_3F.INIT_31 = 256'h001C00432B0000EF001C00430B00002F001C00432900000F001C0043A60000FF,
pm.ram38_3F.INIT_32 = 256'h001C00450B00002F001C00442B00008F001C00440B00002F001C00442A00007F,
pm.ram38_3F.INIT_33 = 256'h001C0051130000CF001C00511B0000FF001C00500F00009F001C00452900000F,
pm.ram38_3F.INIT_34 = 256'h001C00511B0000DF001C0051140000EF001C00510D00003F001C00511700002F,
pm.ram38_3F.INIT_35 = 256'h001C00521200004F001C0051020000CF001C00510D00009F001C00510F00007F,
pm.ram38_3F.INIT_36 = 256'h001C00522C0000BF001C00520F00007F001C0052140000EF001C00520D00003F,
pm.ram38_3F.INIT_37 = 256'h001C0053110000EF001C00534D00007F001C00530F0000BF001C0052020000CF,
pm.ram38_3F.INIT_38 = 256'h001C00541200004F001C00541B0000FF001C00532D00001F001C00530F0000BF,
pm.ram38_3F.INIT_39 = 256'h001C00552E00003F001C00551200004F001C00550F0000BF001C00540F00009F,
pm.ram38_3F.INIT_3A = 256'h001C00561200004F001C00560F00007F001C00552A00007F001C00551600008F,
pm.ram38_3F.INIT_3B = 256'h001C0056A600002A001C00560F0000BF001C00561600008F001C00562E00003F,
pm.ram38_3F.INIT_3C = 256'h001C00571E00008F001C00571C00004F001C00571C00001F001C00562A00007F,
pm.ram38_3F.INIT_3D = 256'h001C005CA60000BF001C005C1B0000FF001C00572D00001F001C00570F00007F,
pm.ram38_3F.INIT_3E = 256'h001C005D0B00002F001C005C020000EF001C005C110000CF001C005C2B00001F,
pm.ram38_3F.INIT_3F = 256'h001C005D0B00002F001C005D2900000F001C005DAB00007F001C005D2B0000EF;
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
//
// Signal Descriptions
// ===================
//
// clk_i Processor clock.
// reset_i 1 to reset the circuit in the next cycle.
// 0 for normal operation.
//
// Inputs from the instruction fetch stage:
//
// inst_i Instruction. If none, use NOP (ADDI X0, X0, 0).
// inst_en_i 1 if a new instruction is to be registered.
// 0 to retain the previously registered instruction.
// (Put another way, inst_i is valid if 1.)
//
// I/Os to/from the register writeback stage:
//
// rs1val_i Source register value 1.
// rs2val_i Source register value 2.
//
// rs1_o Source register address. Data must appear on
// rs1val_i before next cycle.
// rs2_o As with rs1_o.
//
// Inputs from Execute Stage (Register Bypass Feedback):
// ex_rd_i The destination register to receive the execute-stage results.
// ex_q_i The value intended to be written to the above register.
//
// Inputs from Memory Stage (Register Bypass Feedback):
// mem_rd_i As above.
// mem_q_i
//
// Outputs to the decode stage:
//
// inpa_o ALU input value A. Corresponds to RS1.
// inpb_o ALU input value B. Corresponds to RS2 or immediate.
// invB_o 1 to invert the B input.
// cflag_o ALU carry input. Used with invB_o to effect subtractions.
// lsh_en_o Arithmetic/logic operations.
// rsh_en_o
// ltu_en_o
// lts_en_o
// sum_en_o
// and_en_o
// xor_en_o
// rd_o The destination register to write to (0 if none).
// we_o 1 if memory store operation; 0 otherwise.
// nomem_o 1 if ALU-to-register write.
// mem_o 1 if memory load or store operation; 0 otherwise.
// dat_o Value to store in memory writes. Corresponds to RS2.
// xrs_rwe_o The size of the value to write.
//
// illegal_o 1 if the last instruction received is illegal.
// 0 if it's a valid instruction.
//
// ADDI X0, X0, 0
`define INST_NOP (32'b000000000000_00000_000_00000_0010011)
module decode(
input clk_i,
input reset_i,
input [31:0] inst_i,
input inst_en_i,
input [63:0] rs1val_i,
input [63:0] rs2val_i,
input [4:0] ex_rd_i,
input [4:0] mem_rd_i,
input [63:0] ex_q_i,
input [63:0] mem_q_i,
output [63:0] inpa_o,
output [63:0] inpb_o,
output invB_o,
output cflag_o,
output lsh_en_o,
output rsh_en_o,
output ltu_en_o,
output lts_en_o,
output sum_en_o,
output and_en_o,
output xor_en_o,
output [4:0] rd_o,
output [4:0] rs1_o,
output [4:0] rs2_o,
output we_o,
output nomem_o,
output mem_o,
output [63:0] dat_o,
output [2:0] xrs_rwe_o,
output illegal_o
);
reg [31:0] inst_r;
reg illegal_o;
reg [63:0] inpa_o;
reg [63:0] inpb_o;
reg [63:0] dat_o;
reg invB_o;
reg cflag_o;
reg lsh_en_o;
reg rsh_en_o;
reg ltu_en_o;
reg lts_en_o;
reg sum_en_o;
reg and_en_o;
reg xor_en_o;
reg we_o;
reg nomem_o;
reg mem_o;
reg [2:0] xrs_rwe_o;
wire [4:0] rs1_r = inst_r[19:15];
wire [4:0] rs2_r = inst_r[24:20];
// We make rs{1,2}_o depend on the instruction _inputs_
// (instead of the registered instruction) because it saves
// us a pipeline stage on iCE40-class FPGAs. For FPGAs with
// asynchronously read block RAMs, you can switch these to
// forward inst_r bits instead without loss of functionality.
assign rs2_o = inst_i[24:20];
assign rs1_o = inst_i[19:15];
assign rd_o = inst_r[11:7];
// We use ex_rd_i as-is, unregistered, because these signals
// will already be registered in subsequent pipeline stages.
wire hit1_ex = (ex_rd_i === rs1_r) && |rs1_r;
wire hit1_mem = (mem_rd_i === rs1_r) && |rs1_r;
wire hit2_ex = (ex_rd_i === rs2_r) && |rs2_r;
wire hit2_mem = (mem_rd_i === rs2_r) && |rs2_r;
wire [63:0] rs1val =
(hit1_ex ? ex_q_i
: (hit1_mem ? mem_q_i
: rs1val_i));
wire [63:0] rs2val =
(hit2_ex ? ex_q_i
: (hit2_mem ? mem_q_i
: rs2val_i));
wire [63:0] imm12 = {{52{inst_r[31]}}, inst_r[31:20]};
wire [63:0] imm12s = {{52{inst_r[31]}}, inst_r[31:25], inst_r[11:7]};
always @(*) begin
illegal_o <= 1;
inpa_o <= 0;
inpb_o <= 0;
dat_o <= 0;
invB_o <= 0;
cflag_o <= 0;
{lsh_en_o,
rsh_en_o,
ltu_en_o,
lts_en_o,
sum_en_o,
and_en_o,
xor_en_o
} <= 0;
we_o <= 0;
nomem_o <= 1;
mem_o <= 0;
xrs_rwe_o <= `XRS_RWE_S64;
if (inst_r[1:0] == 2'b11) begin
// STORE
if((inst_r[6:5] == 2'b01) &&
(inst_r[4:2] == 3'b000) &&
(inst_r[14] == 0)) begin
illegal_o <= 0;
inpa_o <= rs1val;
inpb_o <= imm12s;
sum_en_o <= 1;
nomem_o <= 0;
mem_o <= 1;
we_o <= 1;
dat_o <= rs2val;
case (inst_r[13:12])
2'b00: xrs_rwe_o <= `XRS_RWE_S8;
2'b01: xrs_rwe_o <= `XRS_RWE_S16;
2'b10: xrs_rwe_o <= `XRS_RWE_S32;
2'b11: xrs_rwe_o <= `XRS_RWE_S64;
endcase
end
// OP-IMM
if((inst_r[6:5] == 2'b00) &&
(inst_r[4:2] == 3'b100)) begin
illegal_o <= 0;
inpa_o <= rs1val;
inpb_o <= imm12;
case (inst_r[14:12])
3'b000: sum_en_o <= 1;
3'b001: lsh_en_o <= 1;
3'b010: lts_en_o <= 1;
3'b011: ltu_en_o <= 1;
3'b100: xor_en_o <= 1;
3'b101: {cflag_o, rsh_en_o} <= {inst_r[30], 1'b1};
3'b110: {and_en_o, xor_en_o} <= 2'b11;
3'b111: and_en_o <= 1;
endcase
end
end
end
always @(posedge clk_i) begin
inst_r <= inst_r;
if (reset_i) begin
inst_r <= `INST_NOP;
end
else begin
if(inst_en_i) begin
inst_r <= inst_i;
end
end
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 11
(* X_CORE_INFO = "axi_register_slice_v2_1_11_axi_register_slice,Vivado 2016.4" *)
(* CHECK_LICENSE_TYPE = "mig_wrap_s00_regslice_0,axi_register_slice_v2_1_11_axi_register_slice,{}" *)
(* CORE_GENERATION_INFO = "mig_wrap_s00_regslice_0,axi_register_slice_v2_1_11_axi_register_slice,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=virtex7,C_AXI_PROTOCOL=0,C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONFIG_W=1,C_RE\
G_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module mig_wrap_s00_regslice_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [3 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [3 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [3 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [3 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [3 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [3 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [3 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [3 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_11_axi_register_slice #(
.C_FAMILY("virtex7"),
.C_AXI_PROTOCOL(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(1),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(4'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVPWRVGND_PP_SYMBOL_V
`define SKY130_FD_SC_HS__TAPVPWRVGND_PP_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapvpwrvgnd (
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVPWRVGND_PP_SYMBOL_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file controller_command_fifo.v when simulating
// the core, controller_command_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module controller_command_fifo(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
data_count
);
input clk;
input rst;
input [127 : 0] din;
input wr_en;
input rd_en;
output [127 : 0] dout;
output full;
output empty;
output [4 : 0] data_count;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(128),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(128),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(1),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(14),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.DATA_COUNT(data_count),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
(** * Logic: Logic in Coq *)
Require Export MoreCoq.
(** Coq's built-in logic is very small: the only primitives are
[Inductive] definitions, universal quantification ([forall]), and
implication ([->]), while all the other familiar logical
connectives -- conjunction, disjunction, negation, existential
quantification, even equality -- can be encoded using just these.
This chapter explains the encodings and shows how the tactics
we've seen can be used to carry out standard forms of logical
reasoning involving these connectives.
*)
(* ########################################################### *)
(** * Propositions *)
(** In previous chapters, we have seen many examples of factual
claims (_propositions_) and ways of presenting evidence of their
truth (_proofs_). In particular, we have worked extensively with
_equality propositions_ of the form [e1 = e2], with
implications ([P -> Q]), and with quantified propositions
([forall x, P]).
*)
(** In Coq, the type of things that can (potentially)
be proven is [Prop]. *)
(** Here is an example of a provable proposition: *)
Check (3 = 3).
(* ===> Prop *)
(** Here is an example of an unprovable proposition: *)
Check (forall (n:nat), n = 2).
(* ===> Prop *)
(** Recall that [Check] asks Coq to tell us the type of the indicated
expression. *)
(* ########################################################### *)
(** * Proofs and Evidence *)
(** In Coq, propositions have the same status as other types, such as
[nat]. Just as the natural numbers [0], [1], [2], etc. inhabit
the type [nat], a Coq proposition [P] is inhabited by its
_proofs_. We will refer to such inhabitants as _proof term_ or
_proof object_ or _evidence_ for the truth of [P].
In Coq, when we state and then prove a lemma such as:
Lemma silly : 0 * 3 = 0.
Proof. reflexivity. Qed.
the tactics we use within the [Proof]...[Qed] keywords tell Coq
how to construct a proof term that inhabits the proposition. In
this case, the proposition [0 * 3 = 0] is justified by a
combination of the _definition_ of [mult], which says that [0 * 3]
_simplifies_ to just [0], and the _reflexive_ principle of
equality, which says that [0 = 0].
*)
(** *** *)
Lemma silly : 0 * 3 = 0.
Proof. reflexivity. Qed.
(** We can see which proof term Coq constructs for a given Lemma by
using the [Print] directive: *)
Print silly.
(* ===> silly = eq_refl : 0 * 3 = 0 *)
(** Here, the [eq_refl] proof term witnesses the equality. (More on
equality later!)*)
(** ** Implications _are_ functions *)
(** Just as we can implement natural number multiplication as a
function:
[
mult : nat -> nat -> nat
]
The _proof term_ for an implication [P -> Q] is a _function_ that
takes evidence for [P] as input and produces evidence for [Q] as its
output.
*)
Lemma silly_implication : (1 + 1) = 2 -> 0 * 3 = 0.
Proof.
intros H.
reflexivity.
Qed.
(** We can see that the proof term for the above lemma is indeed a
function: *)
Print silly_implication.
(* ===> silly_implication = fun _ : 1 + 1 = 2 => eq_refl
: 1 + 1 = 2 -> 0 * 3 = 0 *)
(** ** Defining propositions *)
(** Just as we can create user-defined inductive types (like the
lists, binary representations of natural numbers, etc., that we
seen before), we can also create _user-defined_ propositions.
Question: How do you define the meaning of a proposition?
*)
(** *** *)
(** The meaning of a proposition is given by _rules_ and _definitions_
that say how to construct _evidence_ for the truth of the
proposition from other evidence.
- Typically, rules are defined _inductively_, just like any other
datatype.
- Sometimes a proposition is declared to be true without
substantiating evidence. Such propositions are called _axioms_.
In this, and subsequence chapters, we'll see more about how these
proof terms work in more detail.
*)
(* ########################################################### *)
(** * Conjunction (Logical "and") *)
(** The logical conjunction of propositions [P] and [Q] can be
represented using an [Inductive] definition with one
constructor. *)
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
(** The intuition behind this definition is simple: to
construct evidence for [and P Q], we must provide evidence
for [P] and evidence for [Q]. More precisely:
- [conj p q] can be taken as evidence for [and P Q] if [p]
is evidence for [P] and [q] is evidence for [Q]; and
- this is the _only_ way to give evidence for [and P Q] --
that is, if someone gives us evidence for [and P Q], we
know it must have the form [conj p q], where [p] is
evidence for [P] and [q] is evidence for [Q].
Since we'll be using conjunction a lot, let's introduce a more
familiar-looking infix notation for it. *)
Notation "P /\ Q" := (and P Q) : type_scope.
(** (The [type_scope] annotation tells Coq that this notation
will be appearing in propositions, not values.) *)
(** Consider the "type" of the constructor [conj]: *)
Check conj.
(* ===> forall P Q : Prop, P -> Q -> P /\ Q *)
(** Notice that it takes 4 inputs -- namely the propositions [P]
and [Q] and evidence for [P] and [Q] -- and returns as output the
evidence of [P /\ Q]. *)
(** ** "Introducing" conjunctions *)
(** Besides the elegance of building everything up from a tiny
foundation, what's nice about defining conjunction this way is
that we can prove statements involving conjunction using the
tactics that we already know. For example, if the goal statement
is a conjuction, we can prove it by applying the single
constructor [conj], which (as can be seen from the type of [conj])
solves the current goal and leaves the two parts of the
conjunction as subgoals to be proved separately. *)
Theorem and_example :
(0 = 0) /\ (4 = mult 2 2).
Proof.
apply conj.
reflexivity.
reflexivity.
Qed.
(** Just for convenience, we can use the tactic [split] as a shorthand for
[apply conj]. *)
Theorem and_example' :
(0 = 0) /\ (4 = mult 2 2).
Proof.
split.
reflexivity.
reflexivity.
Qed.
(** ** "Eliminating" conjunctions *)
(** Conversely, the [destruct] tactic can be used to take a
conjunction hypothesis in the context, calculate what evidence
must have been used to build it, and add variables representing
this evidence to the proof context. *)
Theorem proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros.
destruct H as [HP HQ].
apply HP.
Qed.
(** **** Exercise: 1 star, optional (proj2) *)
Theorem proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
intros.
destruct H as [HP HQ].
apply HQ.
Qed.
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
intros.
destruct H as [HP HQ].
split.
apply HQ. apply HP.
Qed.
(** **** Exercise: 2 stars (and_assoc) *)
(** In the following proof, notice how the _nested pattern_ in the
[destruct] breaks the hypothesis [H : P /\ (Q /\ R)] down into
[HP: P], [HQ : Q], and [HR : R]. Finish the proof from there: *)
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R H.
destruct H as [HP [HQ HR]].
split.
split.
apply HP.
apply HQ.
apply HR.
Qed.
(* ###################################################### *)
(** * Iff *)
(** The handy "if and only if" connective is just the conjunction of
two implications. *)
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity)
: type_scope.
Theorem iff_implies : forall P Q : Prop,
(P <-> Q) -> P -> Q.
Proof.
intros.
destruct H as [HA HB].
apply HA.
apply H0.
Qed.
Theorem iff_sym : forall P Q : Prop,
(P <-> Q) -> (Q <-> P).
Proof.
intros.
destruct H as [HA HB].
split. apply HB. apply HA.
Qed.
(** **** Exercise: 1 star, optional (iff_properties) *)
(** Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof.
intros.
split.
intros. apply H.
intros. apply H.
Qed.
Theorem iff_trans : forall P Q R : Prop,
(P <-> Q) -> (Q <-> R) -> (P <-> R).
Proof.
intros.
inversion H. inversion H0.
split.
intros. apply H3. apply H1. apply H5.
intros. apply H2. apply H4. apply H5.
Qed.
(** Hint: If you have an iff hypothesis in the context, you can use
[inversion] to break it into two separate implications. (Think
about why this works.) *)
(** [] *)
(** Some of Coq's tactics treat [iff] statements specially, thus
avoiding the need for some low-level manipulation when reasoning
with them. In particular, [rewrite] can be used with [iff]
statements, not just equalities. *)
(* ############################################################ *)
(** * Disjunction (Logical "or") *)
(** ** Implementing disjunction *)
(** Disjunction ("logical or") can also be defined as an
inductive proposition. *)
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
Notation "P \/ Q" := (or P Q) : type_scope.
(** Consider the "type" of the constructor [or_introl]: *)
Check or_introl.
(* ===> forall P Q : Prop, P -> P \/ Q *)
(** It takes 3 inputs, namely the propositions [P], [Q] and
evidence of [P], and returns, as output, the evidence of [P \/ Q].
Next, look at the type of [or_intror]: *)
Check or_intror.
(* ===> forall P Q : Prop, Q -> P \/ Q *)
(** It is like [or_introl] but it requires evidence of [Q]
instead of evidence of [P]. *)
(** Intuitively, there are two ways of giving evidence for [P \/ Q]:
- give evidence for [P] (and say that it is [P] you are giving
evidence for -- this is the function of the [or_introl]
constructor), or
- give evidence for [Q], tagged with the [or_intror]
constructor. *)
(** *** *)
(** Since [P \/ Q] has two constructors, doing [destruct] on a
hypothesis of type [P \/ Q] yields two subgoals. *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros.
destruct H as [HP | HQ].
apply or_intror. apply HP.
apply or_introl. apply HQ.
Qed.
(** From here on, we'll use the shorthand tactics [left] and [right]
in place of [apply or_introl] and [apply or_intror]. *)
Theorem or_commut' : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
destruct H as [HP | HQ].
Case "left". right. apply HP.
Case "right". left. apply HQ.
Qed.
Theorem or_distributes_over_and_1 : forall P Q R : Prop,
P \/ (Q /\ R) -> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R.
intros H.
destruct H as [HP | [HQ HR]].
Case "left". split.
SCase "left". left. apply HP.
SCase "right". left. apply HP.
Case "right". split.
SCase "left". right. apply HQ.
SCase "right". right. apply HR.
Qed.
(** **** Exercise: 2 stars (or_distributes_over_and_2) *)
Theorem or_distributes_over_and_2 : forall P Q R : Prop,
(P \/ Q) /\ (P \/ R) -> P \/ (Q /\ R).
Proof.
intros.
destruct H as [HL HR]. destruct HL as [HP|HQ]. destruct HR as [HP'|HR].
left. apply HP.
left. apply HP.
destruct HR as [HP|HR']. left. apply HP. right. apply conj. apply HQ. apply HR'.
Qed.
(** **** Exercise: 1 star, optional (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R.
split.
intros H1.
apply conj.
destruct H1 as [H1L | H1R].
left.
apply H1L.
destruct H1R as [A B].
right.
apply A.
destruct H1 as [A | [B C]].
left.
apply A.
right.
apply C.
intros H2.
destruct H2 as [[LP | LQ] [RP | RQ]].
left.
apply LP.
left.
apply LP.
left.
apply RP.
right.
apply conj.
apply LQ.
apply RQ.
Qed.
(* ################################################### *)
(** ** Relating [/\] and [\/] with [andb] and [orb] *)
(** We've already seen several places where analogous structures
can be found in Coq's computational ([Type]) and logical ([Prop])
worlds. Here is one more: the boolean operators [andb] and [orb]
are clearly analogs of the logical connectives [/\] and [\/].
This analogy can be made more precise by the following theorems,
which show how to translate knowledge about [andb] and [orb]'s
behaviors on certain inputs into propositional facts about those
inputs. *)
Theorem andb_prop : forall b c,
andb b c = true -> b = true /\ c = true.
Proof.
intros.
destruct b.
Case "b=true". destruct c. apply conj. reflexivity. reflexivity. inversion H.
Case "b=false". destruct c. inversion H. inversion H.
Qed.
Theorem andb_true_intro : forall b c,
b = true /\ c = true -> andb b c = true.
Proof.
intros.
destruct b.
inversion H. rewrite -> H1. simpl. reflexivity.
inversion H. inversion H0.
Qed.
(** **** Exercise: 2 stars, optional (andb_false) *)
Theorem andb_false : forall b c,
andb b c = false -> b = false \/ c = false.
Proof.
intros b c H.
destruct b.
Case "b = true".
destruct c.
inversion H.
right.
reflexivity.
Case "b = false".
destruct c.
left.
reflexivity.
left.
reflexivity.
Qed.
(** **** Exercise: 2 stars, optional (orb_false) *)
Theorem orb_prop : forall b c,
orb b c = true -> b = true \/ c = true.
Proof.
intros b c H.
destruct b.
Case "b = true".
left.
reflexivity.
Case "b = false".
destruct c.
right.
reflexivity.
inversion H.
Qed.
(** **** Exercise: 2 stars, optional (orb_false_elim) *)
Theorem orb_false_elim : forall b c,
orb b c = false -> b = false /\ c = false.
Proof.
intros b c H.
destruct b.
Case "b = true".
destruct c.
apply conj.
inversion H.
inversion H.
inversion H.
Case "b = false".
destruct c.
apply conj.
reflexivity.
inversion H.
apply conj.
reflexivity.
reflexivity.
Qed.
(* ################################################### *)
(** * Falsehood *)
(** Logical falsehood can be represented in Coq as an inductively
defined proposition with no constructors. *)
Inductive False : Prop := .
(** Intuition: [False] is a proposition for which there is no way
to give evidence. *)
(** Since [False] has no constructors, inverting an assumption
of type [False] always yields zero subgoals, allowing us to
immediately prove any goal. *)
Theorem False_implies_nonsense :
False -> 2 + 2 = 5.
Proof.
intros contra.
inversion contra.
Qed.
(** How does this work? The [inversion] tactic breaks [contra] into
each of its possible cases, and yields a subgoal for each case.
As [contra] is evidence for [False], it has _no_ possible cases,
hence, there are no possible subgoals and the proof is done. *)
(** *** *)
(** Conversely, the only way to prove [False] is if there is already
something nonsensical or contradictory in the context: *)
Theorem nonsense_implies_False :
2 + 2 = 5 -> False.
Proof.
intros contra.
inversion contra.
Qed.
(** Actually, since the proof of [False_implies_nonsense]
doesn't actually have anything to do with the specific nonsensical
thing being proved; it can easily be generalized to work for an
arbitrary [P]: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
intros P contra.
inversion contra.
Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from
falsehood follows whatever you please." This theorem is also
known as the _principle of explosion_. *)
(* #################################################### *)
(** ** Truth *)
(** Since we have defined falsehood in Coq, one might wonder whether
it is possible to define truth in the same way. We can. *)
(** **** Exercise: 2 stars, advanced (True) *)
(** Define [True] as another inductively defined proposition. (The
intution is that [True] should be a proposition for which it is
trivial to give evidence.) *)
(* FILL IN HERE *)
(** [] *)
(** However, unlike [False], which we'll use extensively, [True] is
used fairly rarely. By itself, it is trivial (and therefore
uninteresting) to prove as a goal, and it carries no useful
information as a hypothesis. But it can be useful when defining
complex [Prop]s using conditionals, or as a parameter to
higher-order [Prop]s. *)
(* #################################################### *)
(** * Negation *)
(** The logical complement of a proposition [P] is written [not
P] or, for shorthand, [~P]: *)
Definition not (P:Prop) := P -> False.
(** The intuition is that, if [P] is not true, then anything at
all (even [False]) follows from assuming [P]. *)
Notation "~ x" := (not x) : type_scope.
Check not.
(* ===> Prop -> Prop *)
(** It takes a little practice to get used to working with
negation in Coq. Even though you can see perfectly well why
something is true, it can be a little hard at first to get things
into the right configuration so that Coq can see it! Here are
proofs of a few familiar facts about negation to get you warmed
up. *)
Theorem not_False :
~ False.
Proof.
unfold not.
intros H.
inversion H.
Qed.
Theorem not_False':
~ False.
Proof.
unfold not.
intros.
inversion H.
Qed.
(** *** *)
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
intros.
destruct H as [HP NHP].
unfold not in NHP.
apply NHP in HP.
inversion HP.
Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
intros.
unfold not.
intros.
apply H0 in H.
apply H.
Qed.
(** **** Exercise: 2 stars, advanced (double_neg_inf) *)
(** Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (contrapositive) *)
Theorem contrapositive : forall P Q : Prop,
(P -> Q) -> (~Q -> ~P).
Proof.
intros.
unfold not in H0.
unfold not.
intros.
apply H in H1.
apply H0 in H1.
apply H1.
Qed.
(** **** Exercise: 1 star (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
intros.
unfold not.
intros.
destruct H as [HP NHP].
apply NHP in HP.
apply HP.
Qed.
(** **** Exercise: 1 star, advanced (informal_not_PNP) *)
(** Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)]. *)
(* FILL IN HERE *)
(** [] *)
(** *** Constructive logic *)
(** Note that some theorems that are true in classical logic are _not_
provable in Coq's (constructive) logic. E.g., let's look at how
this proof gets stuck... *)
Theorem classic_double_neg : forall P : Prop,
~~P -> P.
Proof.
intros P H.
unfold not in H.
(* But now what? There is no way to "invent" evidence for [~P]
from evidence for [P]. *)
Abort.
(** **** Exercise: 5 stars, advanced, optional (classical_axioms) *)
(** For those who like a challenge, here is an exercise
taken from the Coq'Art book (p. 123). The following five
statements are often considered as characterizations of
classical logic (as opposed to constructive logic, which is
what is "built in" to Coq). We can't prove them in Coq, but
we can consistently add any one of them as an unproven axiom
if we wish to work in classical logic. Prove that these five
propositions are equivalent. *)
Definition peirce := forall P Q: Prop,
((P->Q)->P)->P.
Definition classic := forall P:Prop,
~~P -> P.
Definition excluded_middle := forall P:Prop,
P \/ ~P.
Definition de_morgan_not_and_not := forall P Q:Prop,
~(~P /\ ~Q) -> P\/Q.
Definition implies_to_or := forall P Q:Prop,
(P->Q) -> (~P\/Q).
Theorem equiv1: forall (P:Prop),
(~~P -> P) <-> (P \/ ~P).
Proof.
intros P.
unfold not.
split.
Case "one side".
intros H1.
left. apply H1. intros. apply H. apply H1. intros. admit.
Case "other side".
intros H2.
intros H3.
destruct H2 as [H4 | H5].
apply H4.
apply H3 in H5.
inversion H5.
Qed.
(** **** Exercise: 3 stars (excluded_middle_irrefutable) *)
(** This theorem implies that it is always safe to add a decidability
axiom (i.e. an instance of excluded middle) for any _particular_ Prop [P].
Why? Because we cannot prove the negation of such an axiom; if we could,
we would have both [~ (P \/ ~P)] and [~ ~ (P \/ ~P)], a contradiction. *)
Theorem excluded_middle_irrefutable: forall (P:Prop),
~ ~ (P \/ ~ P).
Proof.
intros.
unfold not.
intros.
apply H.
right. intros. apply H. left. apply H0.
Qed.
(* ########################################################## *)
(** ** Inequality *)
(** Saying [x <> y] is just the same as saying [~(x = y)]. *)
Notation "x <> y" := (~ (x = y)) : type_scope.
(** Since inequality involves a negation, it again requires
a little practice to be able to work with it fluently. Here
is one very useful trick. If you are trying to prove a goal
that is nonsensical (e.g., the goal state is [false = true]),
apply the lemma [ex_falso_quodlibet] to change the goal to
[False]. This makes it easier to use assumptions of the form
[~P] that are available in the context -- in particular,
assumptions of the form [x<>y]. *)
Theorem not_false_then_true : forall b : bool,
b <> false -> b = true.
Proof.
intros.
unfold not in H.
destruct b.
Case "b=true". reflexivity.
Case "b=false". apply ex_falso_quodlibet. apply H. reflexivity.
Qed.
(** *** *)
(** **** Exercise: 2 stars (false_beq_nat) *)
Theorem false_beq_nat : forall n m : nat,
n <> m ->
beq_nat n m = false.
Proof.
intros n.
induction n as [| n'].
Case "n=0".
intros m H.
destruct m.
unfold not in H.
simpl.
apply ex_falso_quodlibet.
apply H.
reflexivity.
unfold not in H.
simpl.
reflexivity.
Case "n= Sn'".
intros m H.
destruct m.
simpl.
reflexivity.
unfold not in H.
apply IHn'.
unfold not.
intros Y.
apply H.
rewrite Y.
reflexivity.
Qed.
(** **** Exercise: 2 stars, optional (beq_nat_false) *)
Theorem beq_nat_false : forall n m,
beq_nat n m = false -> n <> m.
Proof.
intros n.
induction n as [| n'].
Case "n=0".
intros m H.
unfold not.
intros F.
destruct m.
inversion H.
inversion F.
Case "n = S n'".
intros.
unfold not.
intros.
destruct m.
inversion H0.
unfold not in IHn'. inversion H.
apply IHn' in H2. apply H2.
inversion H0. reflexivity.
Qed.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module ac97_dma(
input sys_rst,
input sys_clk,
output reg [31:0] wbm_adr_o,
output [2:0] wbm_cti_o,
output reg wbm_we_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i,
input [31:0] wbm_dat_i,
output [31:0] wbm_dat_o,
output reg down_en,
input down_next_frame,
output reg down_pcmleft_valid,
output reg [19:0] down_pcmleft,
output reg down_pcmright_valid,
output reg [19:0] down_pcmright,
output reg up_en,
input up_next_frame,
input up_frame_valid,
input up_pcmleft_valid,
input [19:0] up_pcmleft,
input up_pcmright_valid,
input [19:0] up_pcmright,
/* in 32-bit words */
input dmar_en,
input [29:0] dmar_addr,
input [15:0] dmar_remaining,
output reg dmar_next,
input dmaw_en,
input [29:0] dmaw_addr,
input [15:0] dmaw_remaining,
output reg dmaw_next
);
assign wbm_cti_o = 3'd0;
reg wbm_strobe;
assign wbm_cyc_o = wbm_strobe;
assign wbm_stb_o = wbm_strobe;
reg load_read_addr;
reg load_write_addr;
always @(posedge sys_clk) begin
if(load_read_addr)
wbm_adr_o <= {dmar_addr, 2'b00};
else if(load_write_addr)
wbm_adr_o <= {dmaw_addr, 2'b00};
end
reg load_downpcm;
always @(posedge sys_clk) begin
if(load_downpcm) begin
down_pcmleft_valid <= dmar_en;
down_pcmright_valid <= dmar_en;
down_pcmleft <= {wbm_dat_i[31:16], wbm_dat_i[30:27]};
down_pcmright <= {wbm_dat_i[15:0], wbm_dat_i[14:11]};
end
end
assign wbm_dat_o = {up_pcmleft[19:4], up_pcmright[19:4]};
reg [2:0] state;
reg [2:0] next_state;
parameter IDLE = 3'd0;
parameter DMAR = 3'd1;
parameter DMAW = 3'd2;
parameter NEXTDFRAME = 3'd3;
parameter NEXTUFRAME = 3'd4;
wire dmar_finished = dmar_remaining == 16'd0;
wire dmaw_finished = dmaw_remaining == 16'd0;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
//$display("state:%d->%d %b %b %b", state, next_state, down_next_frame, dmar_en, ~dmar_finished);
end
always @(*) begin
next_state = state;
wbm_strobe = 1'b0;
load_read_addr = 1'b0;
load_write_addr = 1'b0;
wbm_we_o = 1'b0;
down_en = 1'b0;
up_en = 1'b0;
dmar_next = 1'b0;
dmaw_next = 1'b0;
load_downpcm = 1'b0;
case(state)
IDLE: begin
down_en = 1'b1;
up_en = 1'b1;
if(down_next_frame) begin
if(dmar_en)
down_en = 1'b0;
else
load_downpcm = 1'b1;
end
if(up_next_frame) begin
if(dmaw_en)
up_en = 1'b0;
else
load_downpcm = 1'b1;
end
if(down_next_frame & dmar_en & ~dmar_finished) begin
load_read_addr = 1'b1;
next_state = DMAR;
end else if(up_next_frame & dmaw_en & ~dmaw_finished) begin
load_write_addr = 1'b1;
next_state = DMAW;
end
end
DMAR: begin
wbm_strobe = 1'b1;
load_downpcm = 1'b1;
if(wbm_ack_i) begin
dmar_next = 1'b1;
next_state = NEXTDFRAME;
end
end
DMAW: begin
wbm_strobe = 1'b1;
wbm_we_o = 1'b1;
if(wbm_ack_i) begin
dmaw_next = 1'b1;
next_state = NEXTUFRAME;
end
end
NEXTDFRAME: begin
down_en = 1'b1;
next_state = IDLE;
end
NEXTUFRAME: begin
up_en = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
|
//======================================================================
//
// blake2_G.v
// -----------
// Verilog 2001 implementation of the G function in the
// blake2 hash function core. This is pure combinational logic in a
// separade module to allow us to build versions with 1, 2, 4
// and even 8 parallel compression functions.
//
//
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blake2_G(
input wire [63 : 0] a,
input wire [63 : 0] b,
input wire [63 : 0] c,
input wire [63 : 0] d,
input wire [63 : 0] m0,
input wire [63 : 0] m1,
output wire [63 : 0] a_prim,
output wire [63 : 0] b_prim,
output wire [63 : 0] c_prim,
output wire [63 : 0] d_prim
);
//----------------------------------------------------------------
// The actual G function.
//----------------------------------------------------------------
wire [63 : 0] a0 = a + b + m0;
wire [63 : 0] d0 = d ^ a0;
wire [63 : 0] d1 = {d0[31 : 0], d0[63 : 32]};
wire [63 : 0] c0 = c + d1;
wire [63 : 0] b0 = b ^ c0;
wire [63 : 0] b1 = {b0[23 : 0], b0[63 : 24]};
wire [63 : 0] a1 = a0 + b1 + m1;
wire [63 : 0] d2 = d1 ^ a1;
wire [63 : 0] d3 = {d2[15 : 0], d2[63 : 16]};
wire [63 : 0] c1 = c0 + d3;
wire [63 : 0] b2 = b1 ^ c1;
wire [63 : 0] b3 = {b2[62 : 0], b2[63]};
//----------------------------------------------------------------
// Concurrent connectivity for ports.
//----------------------------------------------------------------
assign a_prim = a1;
assign b_prim = b3;
assign c_prim = c1;
assign d_prim = d3;
endmodule // blake2_G
//======================================================================
// EOF blake2_G.v
//======================================================================
|
module mac_loopback(
input wire reset,
input wire tx_clock,
input wire rx_clock,
input wire carrier_sense,
input wire collision,
output wire tx_enable,
output wire [7:0] tx_data,
input wire rx_data_valid,
input wire [7:0] rx_data,
input wire rx_error
);
wire [7:0] data_out;
wire data_out_start;
wire data_out_end;
reg data_out_clock;
wire data_out_enable;
wire data_available;
tx_sm U_tx_sm(
.reset(reset),
.clock(tx_clock),
.fifo_data(data_out),
.fifo_data_read(data_out_enable),
.fifo_data_start(data_out_start),
.fifo_data_end(data_out_end),
.fifo_data_available(data_available),
.mode(1'b1),
.carrier_sense(carrier_sense),
.collision(collision),
.tx_enable(tx_enable),
.tx_data(tx_data)
);
rx_sm #(.FIFO_DEPTH(10)) U_rx_sm(
.reset(reset),
.clock(rx_clock),
.data_out(data_out),
.data_out_clock(tx_clock),
.data_out_enable(data_out_enable),
.data_out_start(data_out_start),
.data_out_end(data_out_end),
.data_available(data_available),
.rx_data_valid(rx_data_valid),
.rx_data(rx_data),
.rx_error(rx_error)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:12:45 05/24/2016
// Design Name:
// Module Name: PICOBLAZE
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PICOBLAZE(
input interrupt,
input sleep,
input clk,
input [7:0]in_port,
input rst,
output write_strobe,
output k_write_strobe,
output read_strobe,
output [7:0]out_port,
output [7:0]port_id,
output interrupt_ack
);
wire bram_enable;
wire [7:0] Dir,Dato;
wire [11:0] address;
wire rdl;
wire [17:0] instruction;
wire reset;
assign reset= rdl || rst;
kcpsm6 kcpsm6 (
.address(address),
.instruction(instruction),
.bram_enable(bram_enable),
.in_port(in_port),
.out_port(out_port),
.port_id(port_id),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe),
.read_strobe(read_strobe),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.sleep(sleep),
.reset(reset),
.clk(clk)
);
hhh pBlaze (
.address(address),
.instruction(instruction),
.enable(bram_enable),
.rdl(rdl),
.clk(clk)
);
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Last modified date: 04/08 '13
* Last modified by: Ye-sheng Kuo <[email protected]>
* Last modified content: add external interrupt
* --------------------------------------------------------------------------
* IMPORTANT:
* --------------------------------------------------------------------------
* */
`timescale 1ns/1ps
`include "include/mbus_def.v"
module mbus_master_wire_ctrl(
input RESETn,
input DOUT_FROM_BUS,
input CLKOUT_FROM_BUS,
input RELEASE_ISO_FROM_SLEEP_CTRL,
output reg DOUT,
output reg CLKOUT,
input EXTERNAL_INT
);
always @ *
begin
if( !RESETn )
CLKOUT <= #1 1'b1;
else if (RELEASE_ISO_FROM_SLEEP_CTRL==`IO_HOLD)
CLKOUT <= #1 1'b1;
else
CLKOUT <= #1 CLKOUT_FROM_BUS;
if ( !RESETn )
DOUT <= #1 1'b1;
else if (EXTERNAL_INT)
begin
DOUT <= #1 0;
end
else
begin
if (RELEASE_ISO_FROM_SLEEP_CTRL==`IO_HOLD)
begin
DOUT <= #1 1'b1;
end
else
begin
DOUT <= #1 DOUT_FROM_BUS;
end
end
end
endmodule // mbus_wire_ctrl_wresetn
|
`ifndef _cdb
`define _cdb
`include "arbiter.v"
module cdb (
input clk,
input rst,
input cdb_req0,
input cdb_req1,
input [31:0] cdb_data0,
input [3:0] cdb_tag0,
input [31:0] cdb_data1,
input [3:0] cdb_tag1,
output cdb_grant0,
output cdb_grant1,
output reg [31:0] cdb_data,
output reg [3:0] cdb_tag,
output reg cdb_valid
);
wire [1:0] cdb_grant;
arbiter #(.WIDTH(2)) u_arbiter_cdb (
.req ({cdb_req0, cdb_req1}),
.clk (clk),
.rst (rst),
.enable (1'b1), // fixme: connect to function unit avail
.grant ({cdb_grant0, cdb_grant1}),
.anyreq()
);
always @(*) begin
case ({cdb_grant0,cdb_grant1})
2'b01: begin
cdb_data <= cdb_data1;
cdb_tag <= cdb_tag1;
cdb_valid <= 1'b1;
end
2'b10: begin
cdb_data <= cdb_data0;
cdb_tag <= cdb_tag0;
cdb_valid <= 1'b1;
end
default: begin
cdb_data <= 0;
cdb_tag <= 0;
cdb_valid <= 1'b0;
end
endcase // case rs_grant
end
endmodule // cdb
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111AI_TB_V
`define SKY130_FD_SC_HS__O2111AI_TB_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o2111ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 C1 = 1'b1;
#240 D1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 C1 = 1'b0;
#380 D1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 D1 = 1'b1;
#500 C1 = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 D1 = 1'bx;
#640 C1 = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__o2111ai dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111AI_TB_V
|
// Copyright (c) 2013 Andrew Downing
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
`timescale 1ns / 1ps
module CpuHardcodedTb();
// constants
localparam INSTRUC_SIZE = 32, ARG_SIZE = 8, DATA_SIZE = 8;
// inputs
reg clk, reset, start, ack;
reg [3:0] btn;
reg [7:0] sw;
// outputs
wire done;
wire [7:0] ld;
wire [3:0] ssd0;
wire [3:0] ssd1;
wire [3:0] ssd2;
wire [3:0] ssd3;
CpuHardcoded uut(.clk(clk), .reset(reset), .start(start), .ack(ack), .btn(btn), .sw(sw),
.done(done), .ld(ld), .ssd0(ssd0), .ssd1(ssd1), .ssd2(ssd2), .ssd3(ssd3));
initial begin : CLOCK_GEN
clk = 1;
forever begin
#5;
clk = ~clk;
end
end
initial begin
// do reset
reset = 1;
btn = 4'b0;
sw = 8'b0;
#15;
// start program
reset = 0;
start = 1;
ack = 0;
#10;
// let program run
start = 0;
wait (done);
#5;
// ack
ack = 1;
wait (!done);
#5;
ack = 0;
end
endmodule
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* LFSR CRC generator
*/
module lfsr_crc #
(
// width of LFSR
parameter LFSR_WIDTH = 32,
// LFSR polynomial
parameter LFSR_POLY = 32'h04c11db7,
// Initial state
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}},
// LFSR configuration: "GALOIS", "FIBONACCI"
parameter LFSR_CONFIG = "GALOIS",
// bit-reverse input and output
parameter REVERSE = 1,
// invert output
parameter INVERT = 1,
// width of data input and output
parameter DATA_WIDTH = 8,
// implementation style: "AUTO", "LOOP", "REDUCTION"
parameter STYLE = "AUTO"
)
(
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] data_in,
input wire data_in_valid,
output wire [LFSR_WIDTH-1:0] crc_out
);
/*
Fully parametrizable combinatorial parallel LFSR CRC module. Implements an unrolled LFSR
next state computation.
Ports:
clk
Clock input
rst
Reset module, set state to LFSR_INIT
data_in
CRC data input
data_in_valid
Shift input data through CRC when asserted
data_out
LFSR output (OUTPUT_WIDTH bits)
Parameters:
LFSR_WIDTH
Specify width of LFSR/CRC register
LFSR_POLY
Specify the LFSR/CRC polynomial in hex format. For example, the polynomial
x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
would be represented as
32'h04c11db7
Note that the largest term (x^32) is suppressed. This term is generated automatically based
on LFSR_WIDTH.
LFSR_INIT
Initial state of LFSR. Defaults to all 1s.
LFSR_CONFIG
Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used
for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators,
scramblers, and descrambers, while Galois is generally used for cyclic redundancy check
generators and checkers.
Fibonacci style (example for 64b66b scrambler, 0x8000000001)
DIN (LSB first)
|
V
(+)<---------------------------(+)<-----------------------------.
| ^ |
| .----. .----. .----. | .----. .----. .----. |
+->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--'
| '----' '----' '----' '----' '----' '----'
V
DOUT
Galois style (example for CRC16, 0x8005)
,-------------------+-------------------------+----------(+)<-- DIN (MSB first)
| | | ^
| .----. .----. V .----. .----. V .----. |
`->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT
'----' '----' '----' '----' '----'
REVERSE
Bit-reverse LFSR input and output. Shifts MSB first by default, set REVERSE for LSB first.
INVERT
Bitwise invert CRC output.
DATA_WIDTH
Specify width of input data bus. The module will perform one shift per input data bit,
so if the input data bus is not required tie data_in to zero and set DATA_WIDTH to the
required number of shifts per clock cycle.
STYLE
Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO"
is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate
directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate
and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog
reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction
operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in
Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing
problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO"
will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey
synthesis translate directives.
Settings for common LFSR/CRC implementations:
Name Configuration Length Polynomial Initial value Notes
CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
PRBS6 Fibonacci 6 6'h21 any
PRBS7 Fibonacci 7 7'h41 any
PRBS9 Fibonacci 9 9'h021 any ITU V.52
PRBS10 Fibonacci 10 10'h081 any ITU
PRBS11 Fibonacci 11 11'h201 any ITU O.152
PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152
PRBS17 Fibonacci 17 17'h04001 any
PRBS20 Fibonacci 20 20'h00009 any ITU V.57
PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151
PRBS29 Fibonacci, inverted 29 29'h08000001 any
PRBS31 Fibonacci, inverted 31 31'h10000001 any
64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet
128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3
*/
reg [LFSR_WIDTH-1:0] state_reg = LFSR_INIT;
reg [LFSR_WIDTH-1:0] output_reg = 0;
wire [LFSR_WIDTH-1:0] lfsr_state;
assign crc_out = output_reg;
lfsr #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_CONFIG(LFSR_CONFIG),
.LFSR_FEED_FORWARD(0),
.REVERSE(REVERSE),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
lfsr_inst (
.data_in(data_in),
.state_in(state_reg),
.data_out(),
.state_out(lfsr_state)
);
always @(posedge clk) begin
if (rst) begin
state_reg <= LFSR_INIT;
output_reg <= 0;
end else begin
if (data_in_valid) begin
state_reg <= lfsr_state;
if (INVERT) begin
output_reg <= ~lfsr_state;
end else begin
output_reg <= lfsr_state;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_4_V
`define SKY130_FD_SC_LP__SDFXTP_4_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxtp_4 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_4_V
`define SKY130_FD_SC_LS__DECAPHE_4_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Verilog wrapper for decaphe with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decaphe.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphe_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__decaphe base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__decaphe_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__decaphe base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_4_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
function int f_no_no ();
int st = 2; st++; return st;
endfunction
function int f_no_st ();
static int st = 2; st++; return st;
endfunction
function int f_no_au ();
automatic int st = 2; st++; return st;
endfunction
function static int f_st_no ();
int st = 2; st++; return st;
endfunction
function static int f_st_st ();
static int st = 2; st++; return st;
endfunction
function static int f_st_au ();
automatic int st = 2; st++; return st;
endfunction
function automatic int f_au_no ();
int st = 2; st++; return st;
endfunction
function automatic int f_au_st ();
static int st = 2; st++; return st;
endfunction
function automatic int f_au_au ();
automatic int st = 2; st++; return st;
endfunction
initial begin
if (f_no_no() != 3) $stop;
if (f_no_no() != 4) $stop;
if (f_no_st() != 3) $stop;
if (f_no_st() != 4) $stop;
if (f_no_au() != 3) $stop;
if (f_no_au() != 3) $stop;
//
if (f_st_no() != 3) $stop;
if (f_st_no() != 4) $stop;
if (f_st_st() != 3) $stop;
if (f_st_st() != 4) $stop;
if (f_st_au() != 3) $stop;
if (f_st_au() != 3) $stop;
//
if (f_au_no() != 3) $stop;
if (f_au_no() != 3) $stop;
if (f_au_st() != 3) $stop;
if (f_au_st() != 4) $stop;
if (f_au_au() != 3) $stop;
if (f_au_au() != 3) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// hub_mem
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module hub_mem
(
input clk_cog,
input ena_bus,
input w,
input [3:0] wb,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// 8192 x 32 ram with byte-write enables ($0000..$7FFF)
reg [7:0] ram3 [8191:0];
reg [7:0] ram2 [8191:0];
reg [7:0] ram1 [8191:0];
reg [7:0] ram0 [8191:0];
reg [7:0] ram_q3;
reg [7:0] ram_q2;
reg [7:0] ram_q1;
reg [7:0] ram_q0;
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[3])
ram3[a[12:0]] <= d[31:24];
if (ena_bus && !a[13])
ram_q3 <= ram3[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[2])
ram2[a[12:0]] <= d[23:16];
if (ena_bus && !a[13])
ram_q2 <= ram2[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[1])
ram1[a[12:0]] <= d[15:8];
if (ena_bus && !a[13])
ram_q1 <= ram1[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[0])
ram0[a[12:0]] <= d[7:0];
if (ena_bus && !a[13])
ram_q0 <= ram0[a[12:0]];
end
// 4096 x 32 rom containing character definitions ($8000..$BFFF)
(* ram_init_file = "hub_rom_low.hex" *) reg [31:0] rom_low [4095:0];
reg [31:0] rom_low_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b10)
rom_low_q <= rom_low[a[11:0]];
// 4096 x 32 rom containing sin table, log table, booter, and interpreter ($C000..$FFFF)
(* ram_init_file = "hub_rom_high.hex" *) reg [31:0] rom_high [4095:0];
reg [31:0] rom_high_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b11)
rom_high_q <= rom_high[a[11:0]];
// memory output mux
reg [1:0] mem;
always @(posedge clk_cog)
if (ena_bus)
mem <= a[13:12];
assign q = !mem[1] ? {ram_q3, ram_q2, ram_q1, ram_q0}
// : !mem[0] ? rom_low_q // comment out this line for DE0-Nano (sacrifices character rom to fit device)
: rom_high_q;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 15
(* X_CORE_INFO = "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "DemoInterconnect_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "DemoInterconnect_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_NUM_SLAVE_SLOTS=3,C_NUM_MASTER_SLOTS=7,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000000300000000000000020000000000000001000000000000000030000000000000002000000000000000100000000000000000\
000,C_M_AXI_ADDR_WIDTH=0x0000001000000010000000100000000c0000000c0000000c0000000c,C_S_AXI_BASE_ID=0x000000020000000100000000,C_S_AXI_THREAD_ID_WIDTH=0x000000000000000000000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000007000000070000000700000007000000070000000700000007,C_M_AXI_READ_CONNECTIVITY=0x00000007000000070000000700000007000000070000000700000007,C_R_REGISTER=1,C_S_AX\
I_SINGLE_THREAD=0x000000010000000100000001,C_S_AXI_WRITE_ACCEPTANCE=0x000000010000000100000001,C_S_AXI_READ_ACCEPTANCE=0x000000010000000100000001,C_M_AXI_WRITE_ISSUING=0x00000001000000010000000100000001000000010000000100000001,C_M_AXI_READ_ISSUING=0x00000001000000010000000100000001000000010000000100000001,C_S_AXI_ARB_PRIORITY=0x000000000000000000000000,C_M_AXI_SECURE=0x00000000000000000000000000000000000000000000000000000000,C_CONNECTIVITY_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module DemoInterconnect_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI AWADDR [31:0] [95:64]" *)
input wire [95 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI AWPROT [2:0] [8:6]" *)
input wire [8 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI AWREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI WDATA [31:0] [95:64]" *)
input wire [95 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 S02_AXI WSTRB [3:0] [11:8]" *)
input wire [11 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI WREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI BRESP [1:0] [5:4]" *)
output wire [5 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI BVALID [0:0] [2:2]" *)
output wire [2 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI BREADY [0:0] [2:2]" *)
input wire [2 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI ARADDR [31:0] [95:64]" *)
input wire [95 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 S02_AXI ARPROT [2:0] [8:6]" *)
input wire [8 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARVALID [0:0] [2:2]" *)
input wire [2 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI ARREADY [0:0] [2:2]" *)
output wire [2 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 S02_AXI RDATA [31:0] [95:64]" *)
output wire [95 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 S02_AXI RRESP [1:0] [5:4]" *)
output wire [5 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RVALID [0:0] [2:2]" *)
output wire [2 : 0] s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME S01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME S02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 S02_AXI RREADY [0:0] [2:2]" *)
input wire [2 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI AWADDR [31:0] [223:192]" *)
output wire [223 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI AWPROT [2:0] [20:18]" *)
output wire [20 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI WDATA [31:0] [223:192]" *)
output wire [223 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20], xilinx.com:interface:aximm:1.0 M06_AXI WSTRB [3:0] [27:24]" *)
output wire [27 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI BRESP [1:0] [13:12]" *)
input wire [13 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BVALID [0:0] [6:6]" *)
input wire [6 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BREADY [0:0] [6:6]" *)
output wire [6 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI ARADDR [31:0] [223:192]" *)
output wire [223 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI ARPROT [2:0] [20:18]" *)
output wire [20 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI RDATA [31:0] [223:192]" *)
input wire [223 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI RRESP [1:0] [13:12]" *)
input wire [13 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RVALID [0:0] [6:6]" *)
input wire [6 : 0] m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M05_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M06_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RREADY [0:0] [6:6]" *)
output wire [6 : 0] m_axi_rready;
axi_crossbar_v2_1_15_axi_crossbar #(
.C_FAMILY("artix7"),
.C_NUM_SLAVE_SLOTS(3),
.C_NUM_MASTER_SLOTS(7),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(448'H0000000000300000000000000020000000000000001000000000000000030000000000000002000000000000000100000000000000000000),
.C_M_AXI_ADDR_WIDTH(224'H0000001000000010000000100000000c0000000c0000000c0000000c),
.C_S_AXI_BASE_ID(96'H000000020000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(96'H000000000000000000000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(224'H00000007000000070000000700000007000000070000000700000007),
.C_M_AXI_READ_CONNECTIVITY(224'H00000007000000070000000700000007000000070000000700000007),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(96'H000000010000000100000001),
.C_S_AXI_WRITE_ACCEPTANCE(96'H000000010000000100000001),
.C_S_AXI_READ_ACCEPTANCE(96'H000000010000000100000001),
.C_M_AXI_WRITE_ISSUING(224'H00000001000000010000000100000001000000010000000100000001),
.C_M_AXI_READ_ISSUING(224'H00000001000000010000000100000001000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(96'H000000000000000000000000),
.C_M_AXI_SECURE(224'H00000000000000000000000000000000000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(3'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(24'H000000),
.s_axi_awsize(9'H000),
.s_axi_awburst(6'H00),
.s_axi_awlock(3'H0),
.s_axi_awcache(12'H000),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(12'H000),
.s_axi_awuser(3'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(3'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(3'H7),
.s_axi_wuser(3'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(3'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(24'H000000),
.s_axi_arsize(9'H000),
.s_axi_arburst(6'H00),
.s_axi_arlock(3'H0),
.s_axi_arcache(12'H000),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(12'H000),
.s_axi_aruser(3'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(7'H00),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(7'H00),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(7'H00),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(7'H7F),
.m_axi_ruser(7'H00),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_TB_V
`define SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_TB_V
/**
* udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND
* power pins and notifier pin.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 SET = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 NOTIFIER = 1'b1;
#180 RESET = 1'b1;
#200 SET = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 NOTIFIER = 1'b0;
#300 RESET = 1'b0;
#320 SET = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SET = 1'b1;
#440 RESET = 1'b1;
#460 NOTIFIER = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SET = 1'bx;
#560 RESET = 1'bx;
#580 NOTIFIER = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dut (.SET(SET), .RESET(RESET), .D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2_BLACKBOX_V
`define SKY130_FD_SC_LS__MUX2_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2_BLACKBOX_V
|
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(** %\chapter{Some Quick Examples}% *)
(** I will start off by jumping right in to a fully worked set of examples, building certified compilers from increasingly complicated source languages to stack machines. We will meet a few useful tactics and see how they can be used in manual proofs, and we will also see how easily these proofs can be automated instead. This chapter is not meant to give full explanations of the features that are employed. Rather, it is meant more as an advertisement of what is possible. Later chapters will introduce all of the concepts in bottom-up fashion. In other words, it is expected that most readers will not understand what exactly is going on here, but I hope this demo will whet your appetite for the remaining chapters!
As always, you can step through the source file <<StackMachine.v>> for this chapter interactively in Proof General. Alternatively, to get a feel for the whole lifecycle of creating a Coq development, you can enter the pieces of source code in this chapter in a new <<.v>> file in an Emacs buffer. If you do the latter, include these two lines at the start of the file. *)
Require Import Bool Arith List CpdtTactics.
Set Implicit Arguments.
(** In general, similar commands will be hidden in the book rendering of each chapter's source code, so you will need to insert them in from-scratch replayings of the code that is presented. To be more specific, every chapter begins with the above two lines, with the import list tweaked as appropriate, considering which definitions the chapter uses. The second command above affects the default behavior of definitions regarding type inference. *)
(** * Arithmetic Expressions Over Natural Numbers *)
(** We will begin with that staple of compiler textbooks, arithmetic expressions over a single type of numbers. *)
(** ** Source Language *)
(** We begin with the syntax of the source language.%\index{Vernacular commands!Inductive}% *)
Inductive binop : Set := Plus | Times.
(** Our first line of Coq code should be unsurprising to ML and Haskell programmers. We define an %\index{algebraic datatypes}%algebraic datatype [binop] to stand for the binary operators of our source language. There are just two wrinkles compared to ML and Haskell. First, we use the keyword [Inductive], in place of <<data>>, <<datatype>>, or <<type>>. This is not just a trivial surface syntax difference; inductive types in Coq are much more expressive than garden variety algebraic datatypes, essentially enabling us to encode all of mathematics, though we begin humbly in this chapter. Second, there is the %\index{Gallina terms!Set}%[: Set] fragment, which declares that we are defining a datatype that should be thought of as a constituent of programs. Later, we will see other options for defining datatypes in the universe of proofs or in an infinite hierarchy of universes, encompassing both programs and proofs, that is useful in higher-order constructions. *)
Inductive exp : Set :=
| Const : nat -> exp
| Binop : binop -> exp -> exp -> exp.
(** Now we define the type of arithmetic expressions. We write that a constant may be built from one argument, a natural number; and a binary operation may be built from a choice of operator and two operand expressions.
A note for readers following along in the PDF version: %\index{coqdoc}%coqdoc supports pretty-printing of tokens in %\LaTeX{}%#LaTeX# or HTML. Where you see a right arrow character, the source contains the ASCII text <<->>>. Other examples of this substitution appearing in this chapter are a double right arrow for <<=>>>, the inverted %`%#'#A' symbol for <<forall>>, and the Cartesian product %`%#'#X' for <<*>>. When in doubt about the ASCII version of a symbol, you can consult the chapter source code.
%\medskip%
Now we are ready to say what programs in our expression language mean. We will do this by writing an %\index{interpreters}%interpreter that can be thought of as a trivial operational or denotational semantics. (If you are not familiar with these semantic techniques, no need to worry: we will stick to "common sense" constructions.)%\index{Vernacular commands!Definition}% *)
Definition binopDenote (b : binop) : nat -> nat -> nat :=
match b with
| Plus => plus
| Times => mult
end.
(** The meaning of a binary operator is a binary function over naturals, defined with pattern-matching notation analogous to the <<case>> and <<match>> of ML and Haskell, and referring to the functions [plus] and [mult] from the Coq standard library. The keyword [Definition] is Coq's all-purpose notation for binding a term of the programming language to a name, with some associated syntactic sugar, like the notation we see here for defining a function. That sugar could be expanded to yield this definition:
[[
Definition binopDenote : binop -> nat -> nat -> nat := fun (b : binop) =>
match b with
| Plus => plus
| Times => mult
end.
]]
In this example, we could also omit all of the type annotations, arriving at:
[[
Definition binopDenote := fun b =>
match b with
| Plus => plus
| Times => mult
end.
]]
Languages like Haskell and ML have a convenient%\index{principal types}\index{type inference}% _principal types_ property, which gives us strong guarantees about how effective type inference will be. Unfortunately, Coq's type system is so expressive that any kind of "complete" type inference is impossible, and the task even seems to be hard in practice. Nonetheless, Coq includes some very helpful heuristics, many of them copying the workings of Haskell and ML type-checkers for programs that fall in simple fragments of Coq's language.
This is as good a time as any to mention the profusion of different languages associated with Coq. The theoretical foundation of Coq is a formal system called the%\index{Calculus of Inductive Constructions}\index{CIC|see{Calculus of Inductive Constructions}}% _Calculus of Inductive Constructions_ (CIC)%~\cite{CIC}%, which is an extension of the older%\index{Calculus of Constructions}\index{CoC|see{Calculus of Constructions}}% _Calculus of Constructions_ (CoC)%~\cite{CoC}%. CIC is quite a spartan foundation, which is helpful for proving metatheory but not so helpful for real development. Still, it is nice to know that it has been proved that CIC enjoys properties like%\index{strong normalization}% _strong normalization_ %\cite{CIC}%, meaning that every program (and, more importantly, every proof term) terminates; and%\index{relative consistency}% _relative consistency_ %\cite{SetsInTypes}% with systems like versions of %\index{Zermelo-Fraenkel set theory}%Zermelo-Fraenkel set theory, which roughly means that you can believe that Coq proofs mean that the corresponding propositions are "really true," if you believe in set theory.
Coq is actually based on an extension of CIC called %\index{Gallina}%Gallina. The text after the [:=] and before the period in the last code example is a term of Gallina. Gallina includes several useful features that must be considered as extensions to CIC. The important metatheorems about CIC have not been extended to the full breadth of the features that go beyond the formalized language, but most Coq users do not seem to lose much sleep over this omission.
Next, there is %\index{Ltac}%Ltac, Coq's domain-specific language for writing proofs and decision procedures. We will see some basic examples of Ltac later in this chapter, and much of this book is devoted to more involved Ltac examples.
Finally, commands like [Inductive] and [Definition] are part of %\index{Vernacular commands}%the Vernacular, which includes all sorts of useful queries and requests to the Coq system. Every Coq source file is a series of vernacular commands, where many command forms take arguments that are Gallina or Ltac programs. (Actually, Coq source files are more like _trees_ of vernacular commands, thanks to various nested scoping constructs.)
%\medskip%
We can give a simple definition of the meaning of an expression:%\index{Vernacular commands!Fixpoint}% *)
Fixpoint expDenote (e : exp) : nat :=
match e with
| Const n => n
| Binop b e1 e2 => (binopDenote b) (expDenote e1) (expDenote e2)
end.
(** We declare explicitly that this is a recursive definition, using the keyword [Fixpoint]. The rest should be old hat for functional programmers. *)
(** It is convenient to be able to test definitions before starting to prove things about them. We can verify that our semantics is sensible by evaluating some sample uses, using the command %\index{Vernacular commands!Eval}%[Eval]. This command takes an argument expressing a%\index{reduction strategy}% _reduction strategy_, or an "order of evaluation." Unlike with ML, which hardcodes an _eager_ reduction strategy, or Haskell, which hardcodes a _lazy_ strategy, in Coq we are free to choose between these and many other orders of evaluation, because all Coq programs terminate. In fact, Coq silently checked %\index{termination checking}%termination of our [Fixpoint] definition above, using a simple heuristic based on monotonically decreasing size of arguments across recursive calls. Specifically, recursive calls must be made on arguments that were pulled out of the original recursive argument with [match] expressions. (In Chapter 7, we will see some ways of getting around this restriction, though simply removing the restriction would leave Coq useless as a theorem proving tool, for reasons we will start to learn about in the next chapter.)
To return to our test evaluations, we run the [Eval] command using the [simpl] evaluation strategy, whose definition is best postponed until we have learned more about Coq's foundations, but which usually gets the job done. *)
Eval simpl in expDenote (Const 42).
(** [= 42 : nat] *)
Eval simpl in expDenote (Binop Plus (Const 2) (Const 2)).
(** [= 4 : nat] *)
Eval simpl in expDenote (Binop Times (Binop Plus (Const 2) (Const 2)) (Const 7)).
(** [= 28 : nat] *)
(** %\smallskip{}%Nothing too surprising goes on here, so we are ready to move on to the target language of our compiler. *)
(** ** Target Language *)
(** We will compile our source programs onto a simple stack machine, whose syntax is: *)
Inductive instr : Set :=
| iConst : nat -> instr
| iBinop : binop -> instr.
Definition prog := list instr.
Definition stack := list nat.
(** An instruction either pushes a constant onto the stack or pops two arguments, applies a binary operator to them, and pushes the result onto the stack. A program is a list of instructions, and a stack is a list of natural numbers.
We can give instructions meanings as functions from stacks to optional stacks, where running an instruction results in [None] in case of a stack underflow and results in [Some s'] when the result of execution is the new stack [s']. %\index{Gallina operators!::}%The infix operator [::] is "list cons" from the Coq standard library.%\index{Gallina terms!option}% *)
Definition instrDenote (i : instr) (s : stack) : option stack :=
match i with
| iConst n => Some (n :: s)
| iBinop b =>
match s with
| arg1 :: arg2 :: s' => Some ((binopDenote b) arg1 arg2 :: s')
| _ => None
end
end.
(** With [instrDenote] defined, it is easy to define a function [progDenote], which iterates application of [instrDenote] through a whole program. *)
Fixpoint progDenote (p : prog) (s : stack) : option stack :=
match p with
| nil => Some s
| i :: p' =>
match instrDenote i s with
| None => None
| Some s' => progDenote p' s'
end
end.
(** With the two programming languages defined, we can turn to the compiler definition. *)
(** ** Translation *)
(** Our compiler itself is now unsurprising. The list concatenation operator %\index{Gallina operators!++}\coqdocnotation{%#<tt>#++#</tt>#%}% comes from the Coq standard library. *)
Fixpoint compile (e : exp) : prog :=
match e with
| Const n => iConst n :: nil
| Binop b e1 e2 => compile e2 ++ compile e1 ++ iBinop b :: nil
end.
(** Before we set about proving that this compiler is correct, we can try a few test runs, using our sample programs from earlier. *)
Eval simpl in compile (Const 42).
(** [= iConst 42 :: nil : prog] *)
Eval simpl in compile (Binop Plus (Const 2) (Const 2)).
(** [= iConst 2 :: iConst 2 :: iBinop Plus :: nil : prog] *)
Eval simpl in compile (Binop Times (Binop Plus (Const 2) (Const 2)) (Const 7)).
(** [= iConst 7 :: iConst 2 :: iConst 2 :: iBinop Plus :: iBinop Times :: nil : prog] *)
(** %\smallskip{}%We can also run our compiled programs and check that they give the right results. *)
Eval simpl in progDenote (compile (Const 42)) nil.
(** [= Some (42 :: nil) : option stack] *)
Eval simpl in progDenote (compile (Binop Plus (Const 2) (Const 2))) nil.
(** [= Some (4 :: nil) : option stack] *)
Eval simpl in progDenote (compile (Binop Times (Binop Plus (Const 2) (Const 2))
(Const 7))) nil.
(** [= Some (28 :: nil) : option stack] *)
(** %\smallskip{}%So far so good, but how can we be sure the compiler operates correctly for _all_ input programs? *)
(** ** Translation Correctness *)
(** We are ready to prove that our compiler is implemented correctly. We can use a new vernacular command [Theorem] to start a correctness proof, in terms of the semantics we defined earlier:%\index{Vernacular commands!Theorem}% *)
Theorem compile_correct : forall e, progDenote (compile e) nil = Some (expDenote e :: nil).
(* begin thide *)
(** Though a pencil-and-paper proof might clock out at this point, writing "by a routine induction on [e]," it turns out not to make sense to attack this proof directly. We need to use the standard trick of%\index{strengthening the induction hypothesis}% _strengthening the induction hypothesis_. We do that by proving an auxiliary lemma, using the command [Lemma] that is a synonym for [Theorem], conventionally used for less important theorems that appear in the proofs of primary theorems.%\index{Vernacular commands!Lemma}% *)
Abort.
Lemma compile_correct' : forall e p s,
progDenote (compile e ++ p) s = progDenote p (expDenote e :: s).
(** After the period in the [Lemma] command, we are in%\index{interactive proof-editing mode}% _the interactive proof-editing mode_. We find ourselves staring at this ominous screen of text:
[[
1 subgoal
============================
forall (e : exp) (p : list instr) (s : stack),
progDenote (compile e ++ p) s = progDenote p (expDenote e :: s)
]]
Coq seems to be restating the lemma for us. What we are seeing is a limited case of a more general protocol for describing where we are in a proof. We are told that we have a single subgoal. In general, during a proof, we can have many pending %\index{subgoals}%subgoals, each of which is a logical proposition to prove. Subgoals can be proved in any order, but it usually works best to prove them in the order that Coq chooses.
Next in the output, we see our single subgoal described in full detail. There is a double-dashed line, above which would be our free variables and %\index{hypotheses}%hypotheses, if we had any. Below the line is the %\index{conclusion}%conclusion, which, in general, is to be proved from the hypotheses.
We manipulate the proof state by running commands called%\index{tactics}% _tactics_. Let us start out by running one of the most important tactics:%\index{tactics!induction}%
*)
induction e.
(** We declare that this proof will proceed by induction on the structure of the expression [e]. This swaps out our initial subgoal for two new subgoals, one for each case of the inductive proof:
[[
2 subgoals
n : nat
============================
forall (s : stack) (p : list instr),
progDenote (compile (Const n) ++ p) s =
progDenote p (expDenote (Const n) :: s)
subgoal 2 is
forall (s : stack) (p : list instr),
progDenote (compile (Binop b e1 e2) ++ p) s =
progDenote p (expDenote (Binop b e1 e2) :: s)
]]
The first and current subgoal is displayed with the double-dashed line below free variables and hypotheses, while later subgoals are only summarized with their conclusions. We see an example of a %\index{free variable}%free variable in the first subgoal; [n] is a free variable of type [nat]. The conclusion is the original theorem statement where [e] has been replaced by [Const n]. In a similar manner, the second case has [e] replaced by a generalized invocation of the [Binop] expression constructor. We can see that proving both cases corresponds to a standard proof by %\index{structural induction}%structural induction.
We begin the first case with another very common tactic.%\index{tactics!intros}%
*)
intros.
(** The current subgoal changes to:
[[
n : nat
s : stack
p : list instr
============================
progDenote (compile (Const n) ++ p) s =
progDenote p (expDenote (Const n) :: s)
]]
We see that [intros] changes [forall]-bound variables at the beginning of a goal into free variables.
To progress further, we need to use the definitions of some of the functions appearing in the goal. The [unfold] tactic replaces an identifier with its definition.%\index{tactics!unfold}%
*)
unfold compile.
(** [[
n : nat
s : stack
p : list instr
============================
progDenote ((iConst n :: nil) ++ p) s =
progDenote p (expDenote (Const n) :: s)
]]
*)
unfold expDenote.
(** [[
n : nat
s : stack
p : list instr
============================
progDenote ((iConst n :: nil) ++ p) s = progDenote p (n :: s)
]]
We only need to unfold the first occurrence of [progDenote] to prove the goal. An [at] clause used with [unfold] specifies a particular occurrence of an identifier to unfold, where we count occurrences from left to right.%\index{tactics!unfold}% *)
unfold progDenote at 1.
(** [[
n : nat
s : stack
p : list instr
============================
(fix progDenote (p0 : prog) (s0 : stack) {struct p0} :
option stack :=
match p0 with
| nil => Some s0
| i :: p' =>
match instrDenote i s0 with
| Some s' => progDenote p' s'
| None => None (A:=stack)
end
end) ((iConst n :: nil) ++ p) s =
progDenote p (n :: s)
]]
This last [unfold] has left us with an anonymous recursive definition of [progDenote] (similarly to how [fun] or "lambda" constructs in general allow anonymous non-recursive functions), which will generally happen when unfolding recursive definitions. Note that Coq has automatically renamed the [fix] arguments [p] and [s] to [p0] and [s0], to avoid clashes with our local free variables. There is also a subterm [None (A:=stack)], which has an annotation specifying that the type of the term ought to be [option stack]. This is phrased as an explicit instantiation of a named type parameter [A] from the definition of [option].
Fortunately, in this case, we can eliminate the complications of anonymous recursion right away, since the structure of the argument ([iConst n :: nil) ++ p] is known, allowing us to simplify the internal pattern match with the [simpl] tactic, which applies the same reduction strategy that we used earlier with [Eval] (and whose details we still postpone).%\index{tactics!simpl}%
*)
simpl.
(** [[
n : nat
s : stack
p : list instr
============================
(fix progDenote (p0 : prog) (s0 : stack) {struct p0} :
option stack :=
match p0 with
| nil => Some s0
| i :: p' =>
match instrDenote i s0 with
| Some s' => progDenote p' s'
| None => None (A:=stack)
end
end) p (n :: s) = progDenote p (n :: s)
]]
Now we can unexpand the definition of [progDenote]:%\index{tactics!fold}%
*)
fold progDenote.
(** [[
n : nat
s : stack
p : list instr
============================
progDenote p (n :: s) = progDenote p (n :: s)
]]
It looks like we are at the end of this case, since we have a trivial equality. Indeed, a single tactic finishes us off:%\index{tactics!reflexivity}%
*)
reflexivity.
(** On to the second inductive case:
[[
b : binop
e1 : exp
IHe1 : forall (s : stack) (p : list instr),
progDenote (compile e1 ++ p) s = progDenote p (expDenote e1 :: s)
e2 : exp
IHe2 : forall (s : stack) (p : list instr),
progDenote (compile e2 ++ p) s = progDenote p (expDenote e2 :: s)
============================
forall (s : stack) (p : list instr),
progDenote (compile (Binop b e1 e2) ++ p) s =
progDenote p (expDenote (Binop b e1 e2) :: s)
]]
We see our first example of %\index{hypotheses}%hypotheses above the double-dashed line. They are the inductive hypotheses [IHe1] and [IHe2] corresponding to the subterms [e1] and [e2], respectively.
We start out the same way as before, introducing new free variables and unfolding and folding the appropriate definitions. The seemingly frivolous [unfold]/[fold] pairs are actually accomplishing useful work, because [unfold] will sometimes perform easy simplifications. %\index{tactics!intros}\index{tactics!unfold}\index{tactics!fold}% *)
intros.
unfold compile.
fold compile.
unfold expDenote.
fold expDenote.
(** Now we arrive at a point where the tactics we have seen so far are insufficient. No further definition unfoldings get us anywhere, so we will need to try something different.
[[
b : binop
e1 : exp
IHe1 : forall (s : stack) (p : list instr),
progDenote (compile e1 ++ p) s = progDenote p (expDenote e1 :: s)
e2 : exp
IHe2 : forall (s : stack) (p : list instr),
progDenote (compile e2 ++ p) s = progDenote p (expDenote e2 :: s)
s : stack
p : list instr
============================
progDenote ((compile e2 ++ compile e1 ++ iBinop b :: nil) ++ p) s =
progDenote p (binopDenote b (expDenote e1) (expDenote e2) :: s)
]]
What we need is the associative law of list concatenation, which is available as a theorem [app_assoc_reverse] in the standard library.%\index{Vernacular commands!Check}% (Here and elsewhere, it is possible to tell the difference between inputs and outputs to Coq by periods at the ends of the inputs.) *)
Check app_assoc_reverse.
(** %\vspace{-.15in}%[[
app_assoc_reverse
: forall (A : Type) (l m n : list A), (l ++ m) ++ n = l ++ m ++ n
]]
If we did not already know the name of the theorem, we could use the %\index{Vernacular commands!SearchRewrite}%[SearchRewrite] command to find it, based on a pattern that we would like to rewrite: *)
(* begin hide *)
(* begin thide *)
Definition bleh := app_assoc.
(* end thide *)
(* end hide *)
SearchRewrite ((_ ++ _) ++ _).
(** %\vspace{-.15in}%[[
app_assoc_reverse:
forall (A : Type) (l m n : list A), (l ++ m) ++ n = l ++ m ++ n
]]
%\vspace{-.25in}%
[[
app_assoc: forall (A : Type) (l m n : list A), l ++ m ++ n = (l ++ m) ++ n
]]
We use [app_assoc_reverse] to perform a rewrite: %\index{tactics!rewrite}% *)
rewrite app_assoc_reverse.
(** %\noindent{}%changing the conclusion to:
[[
progDenote (compile e2 ++ (compile e1 ++ iBinop b :: nil) ++ p) s =
progDenote p (binopDenote b (expDenote e1) (expDenote e2) :: s)
]]
Now we can notice that the lefthand side of the equality matches the lefthand side of the second inductive hypothesis, so we can rewrite with that hypothesis, too.%\index{tactics!rewrite}% *)
rewrite IHe2.
(** [[
progDenote ((compile e1 ++ iBinop b :: nil) ++ p) (expDenote e2 :: s) =
progDenote p (binopDenote b (expDenote e1) (expDenote e2) :: s)
]]
The same process lets us apply the remaining hypothesis.%\index{tactics!rewrite}% *)
rewrite app_assoc_reverse.
rewrite IHe1.
(** [[
progDenote ((iBinop b :: nil) ++ p) (expDenote e1 :: expDenote e2 :: s) =
progDenote p (binopDenote b (expDenote e1) (expDenote e2) :: s)
]]
Now we can apply a similar sequence of tactics to the one that ended the proof of the first case.%\index{tactics!unfold}\index{tactics!simpl}\index{tactics!fold}\index{tactics!reflexivity}%
*)
unfold progDenote at 1.
simpl.
fold progDenote.
reflexivity.
(** And the proof is completed, as indicated by the message: *)
(**
<<
Proof completed.
>>
*)
(** And there lies our first proof. Already, even for simple theorems like this, the final proof script is unstructured and not very enlightening to readers. If we extend this approach to more serious theorems, we arrive at the unreadable proof scripts that are the favorite complaints of opponents of tactic-based proving. Fortunately, Coq has rich support for scripted automation, and we can take advantage of such a scripted tactic (defined elsewhere) to make short work of this lemma. We abort the old proof attempt and start again.%\index{Vernacular commands!Abort}%
*)
Abort.
(** %\index{tactics!induction}\index{tactics!crush}% *)
Lemma compile_correct' : forall e s p, progDenote (compile e ++ p) s =
progDenote p (expDenote e :: s).
induction e; crush.
Qed.
(** We need only to state the basic inductive proof scheme and call a tactic that automates the tedious reasoning in between. In contrast to the period tactic terminator from our last proof, the %\index{tactics!semicolon}%semicolon tactic separator supports structured, compositional proofs. The tactic [t1; t2] has the effect of running [t1] and then running [t2] on each remaining subgoal. The semicolon is one of the most fundamental building blocks of effective proof automation. The period terminator is very useful for exploratory proving, where you need to see intermediate proof states, but final proofs of any serious complexity should have just one period, terminating a single compound tactic that probably uses semicolons.
The [crush] tactic comes from the library associated with this book and is not part of the Coq standard library. The book's library contains a number of other tactics that are especially helpful in highly automated proofs.
The %\index{Vernacular commands!Qed}%[Qed] command checks that the proof is finished and, if so, saves it. The tactic commands we have written above are an example of a _proof script_, or a series of Ltac programs; while [Qed] uses the result of the script to generate a _proof term_, a well-typed term of Gallina. To believe that a theorem is true, we only need to trust that the (relatively simple) checker for proof terms is correct; the use of proof scripts is immaterial. Part I of this book will introduce the principles behind encoding all proofs as terms of Gallina.
The proof of our main theorem is now easy. We prove it with four period-terminated tactics, though separating them with semicolons would work as well; the version here is easier to step through.%\index{tactics!intros}% *)
Theorem compile_correct : forall e, progDenote (compile e) nil = Some (expDenote e :: nil).
intros.
(** [[
e : exp
============================
progDenote (compile e) nil = Some (expDenote e :: nil)
]]
At this point, we want to massage the lefthand side to match the statement of [compile_correct']. A theorem from the standard library is useful: *)
Check app_nil_end.
(** [[
app_nil_end
: forall (A : Type) (l : list A), l = l ++ nil
]]
%\index{tactics!rewrite}% *)
rewrite (app_nil_end (compile e)).
(** This time, we explicitly specify the value of the variable [l] from the theorem statement, since multiple expressions of list type appear in the conclusion. The [rewrite] tactic might choose the wrong place to rewrite if we did not specify which we want.
[[
e : exp
============================
progDenote (compile e ++ nil) nil = Some (expDenote e :: nil)
]]
Now we can apply the lemma.%\index{tactics!rewrite}% *)
rewrite compile_correct'.
(** [[
e : exp
============================
progDenote nil (expDenote e :: nil) = Some (expDenote e :: nil)
]]
We are almost done. The lefthand and righthand sides can be seen to match by simple symbolic evaluation. That means we are in luck, because Coq identifies any pair of terms as equal whenever they normalize to the same result by symbolic evaluation. By the definition of [progDenote], that is the case here, but we do not need to worry about such details. A simple invocation of %\index{tactics!reflexivity}%[reflexivity] does the normalization and checks that the two results are syntactically equal.%\index{tactics!reflexivity}% *)
reflexivity.
Qed.
(* end thide *)
(** This proof can be shortened and automated, but we leave that task as an exercise for the reader. *)
(** * Typed Expressions *)
(** In this section, we will build on the initial example by adding additional expression forms that depend on static typing of terms for safety. *)
(** ** Source Language *)
(** We define a trivial language of types to classify our expressions: *)
Inductive type : Set := Nat | Bool.
(** Like most programming languages, Coq uses case-sensitive variable names, so that our user-defined type [type] is distinct from the [Type] keyword that we have already seen appear in the statement of a polymorphic theorem (and that we will meet in more detail later), and our constructor names [Nat] and [Bool] are distinct from the types [nat] and [bool] in the standard library.
Now we define an expanded set of binary operators. *)
Inductive tbinop : type -> type -> type -> Set :=
| TPlus : tbinop Nat Nat Nat
| TTimes : tbinop Nat Nat Nat
| TEq : forall t, tbinop t t Bool
| TLt : tbinop Nat Nat Bool.
(** The definition of [tbinop] is different from [binop] in an important way. Where we declared that [binop] has type [Set], here we declare that [tbinop] has type [type -> type -> type -> Set]. We define [tbinop] as an _indexed type family_. Indexed inductive types are at the heart of Coq's expressive power; almost everything else of interest is defined in terms of them.
The intuitive explanation of [tbinop] is that a [tbinop t1 t2 t] is a binary operator whose operands should have types [t1] and [t2], and whose result has type [t]. For instance, constructor [TLt] (for less-than comparison of numbers) is assigned type [tbinop Nat Nat Bool], meaning the operator's arguments are naturals and its result is Boolean. The type of [TEq] introduces a small bit of additional complication via polymorphism: we want to allow equality comparison of any two values of any type, as long as they have the _same_ type.
ML and Haskell have indexed algebraic datatypes. For instance, their list types are indexed by the type of data that the list carries. However, compared to Coq, ML and Haskell 98 place two important restrictions on datatype definitions.
First, the indices of the range of each data constructor must be type variables bound at the top level of the datatype definition. There is no way to do what we did here, where we, for instance, say that [TPlus] is a constructor building a [tbinop] whose indices are all fixed at [Nat]. %\index{generalized algebraic datatypes}\index{GADTs|see{generalized algebraic datatypes}}% _Generalized algebraic datatypes_ (GADTs)%~\cite{GADT}% are a popular feature in %\index{GHC Haskell}%GHC Haskell, OCaml 4, and other languages that removes this first restriction.
The second restriction is not lifted by GADTs. In ML and Haskell, indices of types must be types and may not be _expressions_. In Coq, types may be indexed by arbitrary Gallina terms. Type indices can live in the same universe as programs, and we can compute with them just like regular programs. Haskell supports a hobbled form of computation in type indices based on %\index{Haskell}%multi-parameter type classes, and recent extensions like type functions bring Haskell programming even closer to "real" functional programming with types, but, without dependent typing, there must always be a gap between how one programs with types and how one programs normally.
*)
(** We can define a similar type family for typed expressions, where a term of type [texp t] can be assigned object language type [t]. (It is conventional in the world of interactive theorem proving to call the language of the proof assistant the%\index{meta language}% _meta language_ and a language being formalized the%\index{object language}% _object language_.) *)
Inductive texp : type -> Set :=
| TNConst : nat -> texp Nat
| TBConst : bool -> texp Bool
| TBinop : forall t1 t2 t, tbinop t1 t2 t -> texp t1 -> texp t2 -> texp t.
(** Thanks to our use of dependent types, every well-typed [texp] represents a well-typed source expression, by construction. This turns out to be very convenient for many things we might want to do with expressions. For instance, it is easy to adapt our interpreter approach to defining semantics. We start by defining a function mapping the types of our object language into Coq types: *)
Definition typeDenote (t : type) : Set :=
match t with
| Nat => nat
| Bool => bool
end.
(** It can take a few moments to come to terms with the fact that [Set], the type of types of programs, is itself a first-class type, and that we can write functions that return [Set]s. Past that wrinkle, the definition of [typeDenote] is trivial, relying on the [nat] and [bool] types from the Coq standard library. We can interpret binary operators by relying on standard-library equality test functions [eqb] and [beq_nat] for Booleans and naturals, respectively, along with a less-than test [leb]: *)
Definition tbinopDenote arg1 arg2 res (b : tbinop arg1 arg2 res)
: typeDenote arg1 -> typeDenote arg2 -> typeDenote res :=
match b with
| TPlus => plus
| TTimes => mult
| TEq Nat => beq_nat
| TEq Bool => eqb
| TLt => leb
end.
(** This function has just a few differences from the denotation functions we saw earlier. First, [tbinop] is an indexed type, so its indices become additional arguments to [tbinopDenote]. Second, we need to perform a genuine%\index{dependent pattern matching}% _dependent pattern match_, where the necessary _type_ of each case body depends on the _value_ that has been matched. At this early stage, we will not go into detail on the many subtle aspects of Gallina that support dependent pattern-matching, but the subject is central to Part II of the book.
The same tricks suffice to define an expression denotation function in an unsurprising way. Note that the [type] arguments to the [TBinop] constructor must be included explicitly in pattern-matching, but here we write underscores because we do not need to refer to those arguments directly. *)
Fixpoint texpDenote t (e : texp t) : typeDenote t :=
match e with
| TNConst n => n
| TBConst b => b
| TBinop _ _ _ b e1 e2 => (tbinopDenote b) (texpDenote e1) (texpDenote e2)
end.
(** We can evaluate a few example programs to convince ourselves that this semantics is correct. *)
Eval simpl in texpDenote (TNConst 42).
(** [= 42 : typeDenote Nat] *)
(* begin hide *)
Eval simpl in texpDenote (TBConst false).
(* end hide *)
Eval simpl in texpDenote (TBConst true).
(** [= true : typeDenote Bool] *)
Eval simpl in texpDenote (TBinop TTimes (TBinop TPlus (TNConst 2) (TNConst 2))
(TNConst 7)).
(** [= 28 : typeDenote Nat] *)
Eval simpl in texpDenote (TBinop (TEq Nat) (TBinop TPlus (TNConst 2) (TNConst 2))
(TNConst 7)).
(** [= false : typeDenote Bool] *)
Eval simpl in texpDenote (TBinop TLt (TBinop TPlus (TNConst 2) (TNConst 2))
(TNConst 7)).
(** [= true : typeDenote Bool] *)
(** %\smallskip{}%Now we are ready to define a suitable stack machine target for compilation. *)
(** ** Target Language *)
(** In the example of the untyped language, stack machine programs could encounter stack underflows and "get stuck." This was unfortunate, since we had to deal with this complication even though we proved that our compiler never produced underflowing programs. We could have used dependent types to force all stack machine programs to be underflow-free.
For our new languages, besides underflow, we also have the problem of stack slots with naturals instead of bools or vice versa. This time, we will use indexed typed families to avoid the need to reason about potential failures.
We start by defining stack types, which classify sets of possible stacks. *)
Definition tstack := list type.
(** Any stack classified by a [tstack] must have exactly as many elements, and each stack element must have the type found in the same position of the stack type.
We can define instructions in terms of stack types, where every instruction's type tells us what initial stack type it expects and what final stack type it will produce. *)
Inductive tinstr : tstack -> tstack -> Set :=
| TiNConst : forall s, nat -> tinstr s (Nat :: s)
| TiBConst : forall s, bool -> tinstr s (Bool :: s)
| TiBinop : forall arg1 arg2 res s,
tbinop arg1 arg2 res
-> tinstr (arg1 :: arg2 :: s) (res :: s).
(** Stack machine programs must be a similar inductive family, since, if we again used the [list] type family, we would not be able to guarantee that intermediate stack types match within a program. *)
Inductive tprog : tstack -> tstack -> Set :=
| TNil : forall s, tprog s s
| TCons : forall s1 s2 s3,
tinstr s1 s2
-> tprog s2 s3
-> tprog s1 s3.
(** Now, to define the semantics of our new target language, we need a representation for stacks at runtime. We will again take advantage of type information to define types of value stacks that, by construction, contain the right number and types of elements. *)
Fixpoint vstack (ts : tstack) : Set :=
match ts with
| nil => unit
| t :: ts' => typeDenote t * vstack ts'
end%type.
(** This is another [Set]-valued function. This time it is recursive, which is perfectly valid, since [Set] is not treated specially in determining which functions may be written. We say that the value stack of an empty stack type is any value of type [unit], which has just a single value, [tt]. A nonempty stack type leads to a value stack that is a pair, whose first element has the proper type and whose second element follows the representation for the remainder of the stack type. We write [%]%\index{notation scopes}\coqdocvar{%#<tt>#type#</tt>#%}% as an instruction to Coq's extensible parser. In particular, this directive applies to the whole [match] expression, which we ask to be parsed as though it were a type, so that the operator [*] is interpreted as Cartesian product instead of, say, multiplication. (Note that this use of %\coqdocvar{%#<tt>#type#</tt>#%}% has no connection to the inductive type [type] that we have defined.)
This idea of programming with types can take a while to internalize, but it enables a very simple definition of instruction denotation. Our definition is like what you might expect from a Lisp-like version of ML that ignored type information. Nonetheless, the fact that [tinstrDenote] passes the type-checker guarantees that our stack machine programs can never go wrong. We use a special form of [let] to destructure a multi-level tuple. *)
Definition tinstrDenote ts ts' (i : tinstr ts ts') : vstack ts -> vstack ts' :=
match i with
| TiNConst _ n => fun s => (n, s)
| TiBConst _ b => fun s => (b, s)
| TiBinop _ _ _ _ b => fun s =>
let '(arg1, (arg2, s')) := s in
((tbinopDenote b) arg1 arg2, s')
end.
(** Why do we choose to use an anonymous function to bind the initial stack in every case of the [match]? Consider this well-intentioned but invalid alternative version:
[[
Definition tinstrDenote ts ts' (i : tinstr ts ts') (s : vstack ts) : vstack ts' :=
match i with
| TiNConst _ n => (n, s)
| TiBConst _ b => (b, s)
| TiBinop _ _ _ _ b =>
let '(arg1, (arg2, s')) := s in
((tbinopDenote b) arg1 arg2, s')
end.
]]
The Coq type checker complains that:
<<
The term "(n, s)" has type "(nat * vstack ts)%type"
while it is expected to have type "vstack ?119".
>>
This and other mysteries of Coq dependent typing we postpone until Part II of the book. The upshot of our later discussion is that it is often useful to push inside of [match] branches those function parameters whose types depend on the type of the value being matched. Our later, more complete treatment of Gallina's typing rules will explain why this helps.
*)
(** We finish the semantics with a straightforward definition of program denotation. *)
Fixpoint tprogDenote ts ts' (p : tprog ts ts') : vstack ts -> vstack ts' :=
match p with
| TNil _ => fun s => s
| TCons _ _ _ i p' => fun s => tprogDenote p' (tinstrDenote i s)
end.
(** The same argument-postponing trick is crucial for this definition. *)
(** ** Translation *)
(** To define our compilation, it is useful to have an auxiliary function for concatenating two stack machine programs. *)
Fixpoint tconcat ts ts' ts'' (p : tprog ts ts') : tprog ts' ts'' -> tprog ts ts'' :=
match p with
| TNil _ => fun p' => p'
| TCons _ _ _ i p1 => fun p' => TCons i (tconcat p1 p')
end.
(** With that function in place, the compilation is defined very similarly to how it was before, modulo the use of dependent typing. *)
Fixpoint tcompile t (e : texp t) (ts : tstack) : tprog ts (t :: ts) :=
match e with
| TNConst n => TCons (TiNConst _ n) (TNil _)
| TBConst b => TCons (TiBConst _ b) (TNil _)
| TBinop _ _ _ b e1 e2 => tconcat (tcompile e2 _)
(tconcat (tcompile e1 _) (TCons (TiBinop _ b) (TNil _)))
end.
(** One interesting feature of the definition is the underscores appearing to the right of [=>] arrows. Haskell and ML programmers are quite familiar with compilers that infer type parameters to polymorphic values. In Coq, it is possible to go even further and ask the system to infer arbitrary terms, by writing underscores in place of specific values. You may have noticed that we have been calling functions without specifying all of their arguments. For instance, the recursive calls here to [tcompile] omit the [t] argument. Coq's _implicit argument_ mechanism automatically inserts underscores for arguments that it will probably be able to infer. Inference of such values is far from complete, though; generally, it only works in cases similar to those encountered with polymorphic type instantiation in Haskell and ML.
The underscores here are being filled in with stack types. That is, the Coq type inferencer is, in a sense, inferring something about the flow of control in the translated programs. We can take a look at exactly which values are filled in: *)
Print tcompile.
(** %\vspace{-.15in}%[[
tcompile =
fix tcompile (t : type) (e : texp t) (ts : tstack) {struct e} :
tprog ts (t :: ts) :=
match e in (texp t0) return (tprog ts (t0 :: ts)) with
| TNConst n => TCons (TiNConst ts n) (TNil (Nat :: ts))
| TBConst b => TCons (TiBConst ts b) (TNil (Bool :: ts))
| TBinop arg1 arg2 res b e1 e2 =>
tconcat (tcompile arg2 e2 ts)
(tconcat (tcompile arg1 e1 (arg2 :: ts))
(TCons (TiBinop ts b) (TNil (res :: ts))))
end
: forall t : type, texp t -> forall ts : tstack, tprog ts (t :: ts)
]]
*)
(** We can check that the compiler generates programs that behave appropriately on our sample programs from above: *)
Eval simpl in tprogDenote (tcompile (TNConst 42) nil) tt.
(** [= (42, tt) : vstack (Nat :: nil)] *)
Eval simpl in tprogDenote (tcompile (TBConst true) nil) tt.
(** [= (true, tt) : vstack (Bool :: nil)] *)
Eval simpl in tprogDenote (tcompile (TBinop TTimes (TBinop TPlus (TNConst 2)
(TNConst 2)) (TNConst 7)) nil) tt.
(** [= (28, tt) : vstack (Nat :: nil)] *)
Eval simpl in tprogDenote (tcompile (TBinop (TEq Nat) (TBinop TPlus (TNConst 2)
(TNConst 2)) (TNConst 7)) nil) tt.
(** [= (false, tt) : vstack (Bool :: nil)] *)
Eval simpl in tprogDenote (tcompile (TBinop TLt (TBinop TPlus (TNConst 2) (TNConst 2))
(TNConst 7)) nil) tt.
(** [= (true, tt) : vstack (Bool :: nil)] *)
(** %\smallskip{}%The compiler seems to be working, so let us turn to proving that it _always_ works. *)
(** ** Translation Correctness *)
(** We can state a correctness theorem similar to the last one. *)
Theorem tcompile_correct : forall t (e : texp t),
tprogDenote (tcompile e nil) tt = (texpDenote e, tt).
(* begin hide *)
Abort.
(* end hide *)
(* begin thide *)
(** Again, we need to strengthen the theorem statement so that the induction will go through. This time, to provide an excuse to demonstrate different tactics, I will develop an alternative approach to this kind of proof, stating the key lemma as: *)
Lemma tcompile_correct' : forall t (e : texp t) ts (s : vstack ts),
tprogDenote (tcompile e ts) s = (texpDenote e, s).
(** While lemma [compile_correct'] quantified over a program that is the "continuation"%~\cite{continuations}% for the expression we are considering, here we avoid drawing in any extra syntactic elements. In addition to the source expression and its type, we also quantify over an initial stack type and a stack compatible with it. Running the compilation of the program starting from that stack, we should arrive at a stack that differs only in having the program's denotation pushed onto it.
Let us try to prove this theorem in the same way that we settled on in the last section. *)
induction e; crush.
(** We are left with this unproved conclusion:
[[
tprogDenote
(tconcat (tcompile e2 ts)
(tconcat (tcompile e1 (arg2 :: ts))
(TCons (TiBinop ts t) (TNil (res :: ts))))) s =
(tbinopDenote t (texpDenote e1) (texpDenote e2), s)
]]
We need an analogue to the [app_assoc_reverse] theorem that we used to rewrite the goal in the last section. We can abort this proof and prove such a lemma about [tconcat].
*)
Abort.
Lemma tconcat_correct : forall ts ts' ts'' (p : tprog ts ts') (p' : tprog ts' ts'')
(s : vstack ts),
tprogDenote (tconcat p p') s
= tprogDenote p' (tprogDenote p s).
induction p; crush.
Qed.
(** This one goes through completely automatically.
Some code behind the scenes registers [app_assoc_reverse] for use by [crush]. We must register [tconcat_correct] similarly to get the same effect:%\index{Vernacular commands!Hint Rewrite}% *)
Hint Rewrite tconcat_correct.
(** Here we meet the pervasive concept of a _hint_. Many proofs can be found through exhaustive enumerations of combinations of possible proof steps; hints provide the set of steps to consider. The tactic [crush] is applying such brute force search for us silently, and it will consider more possibilities as we add more hints. This particular hint asks that the lemma be used for left-to-right rewriting.
Now we are ready to return to [tcompile_correct'], proving it automatically this time. *)
Lemma tcompile_correct' : forall t (e : texp t) ts (s : vstack ts),
tprogDenote (tcompile e ts) s = (texpDenote e, s).
induction e; crush.
Qed.
(** We can register this main lemma as another hint, allowing us to prove the final theorem trivially. *)
Hint Rewrite tcompile_correct'.
Theorem tcompile_correct : forall t (e : texp t),
tprogDenote (tcompile e nil) tt = (texpDenote e, tt).
crush.
Qed.
(* end thide *)
(** It is probably worth emphasizing that we are doing more than building mathematical models. Our compilers are functional programs that can be executed efficiently. One strategy for doing so is based on%\index{program extraction}% _program extraction_, which generates OCaml code from Coq developments. For instance, we run a command to output the OCaml version of [tcompile]:%\index{Vernacular commands!Extraction}% *)
Extraction tcompile.
(** <<
let rec tcompile t e ts =
match e with
| TNConst n ->
TCons (ts, (Cons (Nat, ts)), (Cons (Nat, ts)), (TiNConst (ts, n)), (TNil
(Cons (Nat, ts))))
| TBConst b ->
TCons (ts, (Cons (Bool, ts)), (Cons (Bool, ts)), (TiBConst (ts, b)),
(TNil (Cons (Bool, ts))))
| TBinop (t1, t2, t0, b, e1, e2) ->
tconcat ts (Cons (t2, ts)) (Cons (t0, ts)) (tcompile t2 e2 ts)
(tconcat (Cons (t2, ts)) (Cons (t1, (Cons (t2, ts)))) (Cons (t0, ts))
(tcompile t1 e1 (Cons (t2, ts))) (TCons ((Cons (t1, (Cons (t2,
ts)))), (Cons (t0, ts)), (Cons (t0, ts)), (TiBinop (t1, t2, t0, ts,
b)), (TNil (Cons (t0, ts))))))
>>
We can compile this code with the usual OCaml compiler and obtain an executable program with halfway decent performance.
This chapter has been a whirlwind tour through two examples of the style of Coq development that I advocate. Parts II and III of the book focus on the key elements of that style, namely dependent types and scripted proof automation, respectively. Before we get there, we will spend some time in Part I on more standard foundational material. Part I may still be of interest to seasoned Coq hackers, since I follow the highly automated proof style even at that early stage. *)
|
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rom (addr_rd, addr_rw, clock, data, wren, q, q_rw);
input clock;
input [13:0] addr_rw;
input [7:0] data;
input wren;
input [13:0] addr_rd;
output [7:0] q;
output [7:0] q_rw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q = sub_wire0[7:0];
wire [7:0] q_rw = sub_wire1[7:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (1'b0),
.wren_b (wren),
.address_a (addr_rd),
.address_b (addr_rw),
.data_a (16'h0),
.data_b (data),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "rom.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.numwords_b = 16384,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.widthad_a = 14,
altsyncram_component.widthad_b = 14,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLYGATE4SD3_PP_BLACKBOX_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2B_1_V
`define SKY130_FD_SC_MS__AND2B_1_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2b_1 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2b_1 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2B_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUF_BEHAVIORAL_V
`define SKY130_FD_SC_HS__BUF_BEHAVIORAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__buf (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUF_BEHAVIORAL_V |
///2016/8/6
///ShaoMin Zhai
///module function: used to debug core
`include "define.v"
module top_level(
clk,
rst
);
input clk;
input rst;
wire [31:0] pc;
wire [31:0] mem_data;
wire [31:0] mem_addr;
wire [3:0] mem_head;
wire v_mem;
wire v_pc;
wire [31:0] data;
wire v_data;
wire [31:0] inst;
wire v_inst;
core core_du(//input
.clk(clk),
.rst(rst),
.v_inst(v_inst),
.inst(inst),
.v_data(v_data),
.data(data),
//output
.pc(pc),
.v_pc(v_pc),
.v_mem(v_mem),
.mem_head(mem_head),
.mem_addr(mem_addr),
.mem_data(mem_data)
);
instmem instmem_du(
.clk(clk),
.rst(rst),
.pc(pc),
.read(v_pc),
.inst(inst),
.v_inst(v_inst)
);
datamem datamem_du(
.clk(clk),
.rst(rst),
.addr(mem_addr),
.data_in(mem_data),
.r_w(mem_head[3]),
.v_cmd(v_mem),
.data_out(data),
.v_data_out(v_data)
);
endmodule |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module pio_sw (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 17: 0] in_port;
input reset_n;
wire clk_en;
wire [ 17: 0] data_in;
wire [ 17: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {18 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 18}{1'b0}},read_mux_out};
end
assign data_in = in_port;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_write_datapath(
pll_afi_clk,
reset_n,
force_oct_off,
phy_ddio_oct_ena,
afi_dqs_en,
afi_wdata,
afi_wdata_valid,
afi_dm,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter NUM_WRITE_PATH_FLOP_STAGES = "";
input pll_afi_clk;
input reset_n;
input [AFI_DQS_WIDTH-1:0] force_oct_off;
output [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
input [AFI_DQS_WIDTH-1:0] afi_dqs_en;
input [AFI_DATA_WIDTH-1:0] afi_wdata;
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm;
output [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
output [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
output [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
output [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_pre_shift;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq_pre_shift;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_pre_shift;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_pre_shift;
generate
genvar stage;
if (NUM_WRITE_PATH_FLOP_STAGES == 0)
begin
assign phy_ddio_dq_pre_shift = afi_wdata;
assign phy_ddio_dqs_en_pre_shift = afi_dqs_en;
assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid;
assign phy_ddio_wrdata_mask_pre_shift = afi_dm;
end
else
begin
reg [AFI_DATA_WIDTH-1:0] afi_wdata_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
reg [AFI_DQS_WIDTH-1:0] afi_wdata_valid_r [NUM_WRITE_PATH_FLOP_STAGES-1:0] /* synthesis dont_merge */;
reg [AFI_DQS_WIDTH-1:0] afi_dqs_en_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
// phy_ddio_wrdata_mask is tied low during calibration
// the purpose of the assignment is to avoid Quartus from connecting the signal to the sclr pin of the flop
// sclr pin is very slow and causes timing failures
(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [AFI_DATA_MASK_WIDTH-1:0] afi_dm_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
always @(posedge pll_afi_clk)
begin
afi_wdata_r[0] <= afi_wdata;
afi_dqs_en_r[0] <= afi_dqs_en;
afi_wdata_valid_r[0] <= afi_wdata_valid;
afi_dm_r[0] <= afi_dm;
end
for (stage = 1; stage < NUM_WRITE_PATH_FLOP_STAGES; stage = stage + 1)
begin : stage_gen
always @(posedge pll_afi_clk)
begin
afi_wdata_r[stage] <= afi_wdata_r[stage-1];
afi_dqs_en_r[stage] <= afi_dqs_en_r[stage-1];
afi_wdata_valid_r[stage] <= afi_wdata_valid_r[stage-1];
afi_dm_r[stage] <= afi_dm_r[stage-1];
end
end
assign phy_ddio_dq_pre_shift = afi_wdata_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_dqs_en_pre_shift = afi_dqs_en_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_mask_pre_shift = afi_dm_r[NUM_WRITE_PATH_FLOP_STAGES-1];
end
endgenerate
wire [AFI_DQS_WIDTH-1:0] oct_ena;
reg [MEM_WRITE_DQS_WIDTH-1:0] dqs_en_reg;
always @(posedge pll_afi_clk)
dqs_en_reg <= phy_ddio_dqs_en[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH];
assign oct_ena[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH] = ~phy_ddio_dqs_en[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH];
assign oct_ena[MEM_WRITE_DQS_WIDTH-1:0] = ~(phy_ddio_dqs_en[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH] | dqs_en_reg);
assign phy_ddio_oct_ena_pre_shift = oct_ena & ~force_oct_off;
assign phy_ddio_dq = phy_ddio_dq_pre_shift;
assign phy_ddio_wrdata_mask = phy_ddio_wrdata_mask_pre_shift;
assign phy_ddio_wrdata_en = phy_ddio_wrdata_en_pre_shift;
assign phy_ddio_dqs_en = phy_ddio_dqs_en_pre_shift;
assign phy_ddio_oct_ena = phy_ddio_oct_ena_pre_shift;
endmodule
|
module RotaryLed(clock0,clock180,reset,rotary,leds,vga_hsync,vga_vsync,vga_r,vga_g,vga_b);
input wire clock0;
input wire clock180;
input wire reset;
input wire [1:0] rotary;
output wire [7:0] leds;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
wire [7:0] seq_next;
wire [11:0] seq_oreg;
wire [7:0] seq_oreg_wen;
wire [19:0] coderom_data_o;
wire [4095:0] coderomtext_data_o;
wire [7:0] alu_result;
wire mrotary_rotary_left_status;
wire mrotary_rotary_right_status;
wire [7:0] ledbank_leds;
assign leds = ledbank_leds;
Seq
seq (.clock(clock0),
.reset(reset),
.inst(coderom_data_o),
.inst_text(coderomtext_data_o),
.inst_en(1),
.ireg_0(alu_result),
.ireg_1({7'h0,mrotary_rotary_left_status}),
.ireg_2({7'h0,mrotary_rotary_right_status}),
.ireg_3({8'h00}),
.next(seq_next),
.oreg(seq_oreg),
.oreg_wen(seq_oreg_wen));
RotaryLedRom
coderom (.addr(seq_next),
.data_o(coderom_data_o));
`ifdef SIM
RotaryLedRomText
coderomtext (.addr(seq_next),
.data_o(coderomtext_data_o));
`endif
Alu
alu (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[0]),
.result(alu_result));
Rotary
mrotary (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[1]),
.rotary(rotary),
.rotary_left_status(mrotary_rotary_left_status),
.rotary_right_status(mrotary_rotary_right_status));
LedBank
ledbank (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[2]),
.leds(ledbank_leds));
VGA1
vga (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[3]),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b));
endmodule // RotaryLed
|
/* This module implements the VGA controller. It assumes a 25MHz clock is supplied as input.
*
* General approach:
* Go through each line of the screen and read the colour each pixel on that line should have from
* the Video memory. To do that for each (x,y) pixel on the screen convert (x,y) coordinate to
* a memory_address at which the pixel colour is stored in Video memory. Once the pixel colour is
* read from video memory its brightness is first increased before it is forwarded to the VGA DAC.
*/
module vga_controller( vga_clock, resetn, pixel_colour, memory_address,
VGA_R, VGA_G, VGA_B,
VGA_HS, VGA_VS, VGA_BLANK,
VGA_SYNC, VGA_CLK);
/* Screen resolution and colour depth parameters. */
parameter BITS_PER_COLOUR_CHANNEL = 1;
/* The number of bits per colour channel used to represent the colour of each pixel. A value
* of 1 means that Red, Green and Blue colour channels will use 1 bit each to represent the intensity
* of the respective colour channel. For BITS_PER_COLOUR_CHANNEL=1, the adapter can display 8 colours.
* In general, the adapter is able to use 2^(3*BITS_PER_COLOUR_CHANNEL) colours. The number of colours is
* limited by the screen resolution and the amount of on-chip memory available on the target device.
*/
parameter MONOCHROME = "FALSE";
/* Set this parameter to "TRUE" if you only wish to use black and white colours. Doing so will reduce
* the amount of memory you will use by a factor of 3. */
parameter RESOLUTION = "320x240";
/* Set this parameter to "160x120" or "320x240". It will cause the VGA adapter to draw each dot on
* the screen by using a block of 4x4 pixels ("160x120" resolution) or 2x2 pixels ("320x240" resolution).
* It effectively reduces the screen resolution to an integer fraction of 640x480. It was necessary
* to reduce the resolution for the Video Memory to fit within the on-chip memory limits.
*/
//--- Timing parameters.
/* Recall that the VGA specification requires a few more rows and columns are drawn
* when refreshing the screen than are actually present on the screen. This is necessary to
* generate the vertical and the horizontal syncronization signals. If you wish to use a
* display mode other than 640x480 you will need to modify the parameters below as well
* as change the frequency of the clock driving the monitor (VGA_CLK).
*/
parameter C_VERT_NUM_PIXELS = 10'd480;
parameter C_VERT_SYNC_START = 10'd493;
parameter C_VERT_SYNC_END = 10'd494; //(C_VERT_SYNC_START + 2 - 1);
parameter C_VERT_TOTAL_COUNT = 10'd525;
parameter C_HORZ_NUM_PIXELS = 10'd640;
parameter C_HORZ_SYNC_START = 10'd659;
parameter C_HORZ_SYNC_END = 10'd754; //(C_HORZ_SYNC_START + 96 - 1);
parameter C_HORZ_TOTAL_COUNT = 10'd800;
/*****************************************************************************/
/* Declare inputs and outputs. */
/*****************************************************************************/
input vga_clock, resetn;
input [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] pixel_colour;
output [((RESOLUTION == "320x240") ? (16) : (14)):0] memory_address;
output reg [9:0] VGA_R;
output reg [9:0] VGA_G;
output reg [9:0] VGA_B;
output reg VGA_HS;
output reg VGA_VS;
output reg VGA_BLANK;
output VGA_SYNC, VGA_CLK;
/*****************************************************************************/
/* Local Signals. */
/*****************************************************************************/
reg VGA_HS1;
reg VGA_VS1;
reg VGA_BLANK1;
reg [9:0] xCounter, yCounter;
wire xCounter_clear;
wire yCounter_clear;
wire vcc;
reg [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
reg [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
/* Inputs to the converter. */
/*****************************************************************************/
/* Controller implementation. */
/*****************************************************************************/
assign vcc =1'b1;
/* A counter to scan through a horizontal line. */
always @(posedge vga_clock or negedge resetn)
begin
if (!resetn)
xCounter <= 10'd0;
else if (xCounter_clear)
xCounter <= 10'd0;
else
begin
xCounter <= xCounter + 1'b1;
end
end
assign xCounter_clear = (xCounter == (C_HORZ_TOTAL_COUNT-1));
/* A counter to scan vertically, indicating the row currently being drawn. */
always @(posedge vga_clock or negedge resetn)
begin
if (!resetn)
yCounter <= 10'd0;
else if (xCounter_clear && yCounter_clear)
yCounter <= 10'd0;
else if (xCounter_clear) //Increment when x counter resets
yCounter <= yCounter + 1'b1;
end
assign yCounter_clear = (yCounter == (C_VERT_TOTAL_COUNT-1));
/* Convert the xCounter/yCounter location from screen pixels (640x480) to our
* local dots (320x240 or 160x120). Here we effectively divide x/y coordinate by 2 or 4,
* depending on the resolution. */
always @(*)
begin
if (RESOLUTION == "320x240")
begin
x = xCounter[9:1];
y = yCounter[8:1];
end
else
begin
x = xCounter[9:2];
y = yCounter[8:2];
end
end
/* Change the (x,y) coordinate into a memory address. */
vga_address_translator controller_translator(
.x(x), .y(y), .mem_address(memory_address) );
defparam controller_translator.RESOLUTION = RESOLUTION;
/* Generate the vertical and horizontal synchronization pulses. */
always @(posedge vga_clock)
begin
//- Sync Generator (ACTIVE LOW)
VGA_HS1 <= ~((xCounter >= C_HORZ_SYNC_START) && (xCounter <= C_HORZ_SYNC_END));
VGA_VS1 <= ~((yCounter >= C_VERT_SYNC_START) && (yCounter <= C_VERT_SYNC_END));
//- Current X and Y is valid pixel range
VGA_BLANK1 <= ((xCounter < C_HORZ_NUM_PIXELS) && (yCounter < C_VERT_NUM_PIXELS));
//- Add 1 cycle delay
VGA_HS <= VGA_HS1;
VGA_VS <= VGA_VS1;
VGA_BLANK <= VGA_BLANK1;
end
/* VGA sync should be 1 at all times. */
assign VGA_SYNC = vcc;
/* Generate the VGA clock signal. */
assign VGA_CLK = vga_clock;
/* Brighten the colour output. */
// The colour input is first processed to brighten the image a little. Setting the top
// bits to correspond to the R,G,B colour makes the image a bit dull. To brighten the image,
// each bit of the colour is replicated through the 10 DAC colour input bits. For example,
// when BITS_PER_COLOUR_CHANNEL is 2 and the red component is set to 2'b10, then the
// VGA_R input to the DAC will be set to 10'b1010101010.
integer index;
integer sub_index;
always @(pixel_colour)
begin
VGA_R <= 'b0;
VGA_G <= 'b0;
VGA_B <= 'b0;
if (MONOCHROME == "FALSE")
begin
for (index = 10-BITS_PER_COLOUR_CHANNEL; index >= 0; index = index - BITS_PER_COLOUR_CHANNEL)
begin
for (sub_index = BITS_PER_COLOUR_CHANNEL - 1; sub_index >= 0; sub_index = sub_index - 1)
begin
VGA_R[sub_index+index] <= pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL*2];
VGA_G[sub_index+index] <= pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL];
VGA_B[sub_index+index] <= pixel_colour[sub_index];
end
end
end
else
begin
for (index = 0; index < 10; index = index + 1)
begin
VGA_R[index] <= pixel_colour[0:0];
VGA_G[index] <= pixel_colour[0:0];
VGA_B[index] <= pixel_colour[0:0];
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_1_V
`define SKY130_FD_SC_LP__DLXTN_1_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtn_1 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtn_1 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_1_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:54:12 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_rst_ps7_0_100M_0_sim_netlist.v
// Design : ip_design_rst_ps7_0_100M_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(lpf_asr_reg,
scndry_out,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
aux_reset_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input aux_reset_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
(lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0]p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule
(* CHECK_LICENSE_TYPE = "ip_design_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "zynq" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFEF))
lpf_int0
(.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Bsr_out;
wire MB_out;
wire Pr_out;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\BSR_OUT_DFF[0].FDRE_BSR
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Bsr_out),
.Q(bus_struct_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
FDRE_inst
(.C(slowest_sync_clk),
.CE(1'b1),
.D(MB_out),
.Q(mb_reset),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\PR_OUT_DFF[0].FDRE_PER
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Pr_out),
.Q(peripheral_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (SEQ_n_4),
.Bsr_out(Bsr_out),
.MB_out(MB_out),
.Pr_out(Pr_out),
.lpf_int(lpf_int),
.slowest_sync_clk(slowest_sync_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
(MB_out,
Bsr_out,
Pr_out,
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ,
lpf_int,
slowest_sync_clk);
output MB_out;
output Bsr_out;
output Pr_out;
output \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ;
output \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ;
wire Bsr_out;
wire Core_i_1_n_0;
wire MB_out;
wire Pr_out;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
(.I0(Bsr_out),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
(.I0(Pr_out),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(MB_out),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b1))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(MB_out),
.S(lpf_int));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(Bsr_out),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b1))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(Bsr_out),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(MB_out),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(Pr_out),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b1))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(Pr_out),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAH_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__FAH_FUNCTIONAL_PP_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAH_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A32OI_FUNCTIONAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_FUNCTIONAL_PP_V |
module Alu(input[31:0] op1,
input[31:0] op2,
input[3:0] f,
output reg[31:0] result,
output zero);
always @(op1, op2, f)
case (f)
0: result = op1 + op2;
1: result = op1 - op2;
2: result = op1 & op2;
3: result = op1 | op2;
4: result = op1 ~| op2;
5: result = op1 ^ op2;
6: result = op1 << op2;
7: result = op1 >> op2;
8: result = op1 >>> op2;
9: result = ($signed(op1) < $signed(op2)) ? 1 : 0; //SLT
10: result = (op1 < op2) ? 1 : 0; //SLTU
/* 11:
12:
13:
14:
15:*/
endcase
assign zero = result == 0;
endmodule
module Mult_Div_Alu(input[31:0] op1,
input[31:0] op2,
input[3:0] f,
input en,
output reg[31:0] result_hi,
output reg[31:0] result_lo);
always @(op1, op2, f)
if(en) begin
case (f)
0: begin
result_lo = $signed(op1) / $signed(op2);
result_hi = $signed(op1) % $signed(op2);
end
1: begin
result_lo = op1 / op2;
result_hi = op1 % op2;
end
2: begin
{result_hi, result_lo} = $signed(op1) * $signed(op2);
end
3: begin
{result_hi, result_lo} = op1 * op2;
end
/* 4:
5:
6:
7:
8:
9:
10:
11:
12:
13:
14:
15: */
endcase
$display("\tR[lo] = %x (hex)", result_lo);
$display("\tR[hi] = %x (hex)", result_hi);
end
endmodule
|
`timescale 1ns / 1ps
/* Do NOT allow undeclared nets */
`default_nettype none
/*
Example for June 2014 - Programmable Logic In Practice.
Copyright Colin O'Flynn 2014. All Rights Reserved.
*/
module lx9_reconfig_top(
//Inputs
input wire USER_RESET,
input wire USER_CLOCK,
//PMod Connection: J5, Pin 1
output wire PMOD1_P1,
//Serial Connection (if used)
input wire USB_RS232_RXD,
output wire USB_RS232_TXD,
//LEDs
output wire GPIO_LED1,
output wire GPIO_LED2
);
wire reset;
wire inpclk;
wire oupclk;
assign reset = USER_RESET;
BUFG bufg_inst (
.O(inpclk), // 1-bit output: Clock buffer output
.I(USER_CLOCK) // 1-bit input: Clock buffer input
);
reg [24:0] counterinp;
reg [24:0] counteroup;
assign GPIO_LED1 = counterinp[24];
assign GPIO_LED2 = counteroup[24];
always @(posedge inpclk) begin
counterinp <= counterinp + 25'd1;
end
always @(posedge oupclk) begin
counteroup <= counteroup + 25'd1;
end
//DCM Block we will be reconfiguring with partial reconfiguration
generate_clock gclock_i
(
.CLK_IN1(inpclk),
.CLK_OUT1(oupclk),
.RESET(reset)
);
//Outputing clock on S6 device only requires this
ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR2_inst (
.Q (PMOD1_P1), // 1-bit DDR output data
.C0 (oupclk), // 1-bit clock input
.C1 (~oupclk), // 1-bit clock input
.CE (1'b1), // 1-bit clock enable input
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0), // 1-bit reset input
.S (1'b0));
wire sysclk;
assign sysclk = inpclk;
/***** Serial Interface *****/
wire cmdfifo_rxf;
wire cmdfifo_txe;
wire cmdfifo_rd;
wire cmdfifo_wr;
wire cmdfifo_isout;
wire [7:0] cmdfifo_din;
wire [7:0] cmdfifo_dout;
serial_reg_iface cmdfifo_serial(.reset_i(reset),
.clk_i(sysclk),
.rx_i(USB_RS232_RXD),
.tx_o(USB_RS232_TXD),
.cmdfifo_rxf(cmdfifo_rxf),
.cmdfifo_txe(cmdfifo_txe),
.cmdfifo_rd(cmdfifo_rd),
.cmdfifo_wr(cmdfifo_wr),
.cmdfifo_din(cmdfifo_din),
.cmdfifo_dout(cmdfifo_dout));
/***** Register Interface *****/
wire reg_clk;
wire [5:0] reg_address;
wire [15:0] reg_bytecnt;
wire [7:0] reg_datao;
wire [15:0] reg_size;
wire reg_read;
wire reg_write;
wire reg_addrvalid;
wire [5:0] reg_hypaddress;
wire reg_stream;
wire [15:0] reg_hyplen;
wire [7:0] reg_datai_reconfig;
reg_main registers_mainctl (
.reset_i(reset),
.clk(sysclk),
.cmdfifo_rxf(cmdfifo_rxf),
.cmdfifo_txe(cmdfifo_txe),
.cmdfifo_rd(cmdfifo_rd),
.cmdfifo_wr(cmdfifo_wr),
.cmdfifo_din(cmdfifo_din),
.cmdfifo_dout(cmdfifo_dout),
.cmdfifo_isout(cmdfifo_isout),
.reg_clk(reg_clk),
.reg_address(reg_address),
.reg_bytecnt(reg_bytecnt),
.reg_datao(reg_datao),
.reg_datai(reg_datai_reconfig),
.reg_size(reg_size),
.reg_read(reg_read),
.reg_write(reg_write),
.reg_addrvalid(reg_addrvalid),
.reg_stream(reg_stream),
.reg_hypaddress(reg_hypaddress),
.reg_hyplen(reg_hyplen)
);
/***** Reconfiguration Registers *****/
reg_reconfig reconfiguration(
.reset_i(reset),
.clk(reg_clk),
.reg_address(reg_address),
.reg_bytecnt(reg_bytecnt),
.reg_datao(reg_datai_reconfig),
.reg_datai(reg_datao),
.reg_size(reg_size),
.reg_read(reg_read),
.reg_write(reg_write),
.reg_addrvalid(reg_addrvalid),
.reg_stream(reg_stream),
.reg_hypaddress(reg_hypaddress),
.reg_hyplen(reg_hyplen)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_MUX_4TO2_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_MUX_4TO2_BLACKBOX_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_mux_4to2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_MUX_4TO2_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A21O_PP_BLACKBOX_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_4_V
`define SKY130_FD_SC_LP__MUX2I_4_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_4 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_4 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/12/2015 12:55:13 PM
// Design Name:
// Module Name: SerialHandler_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SerialServo_tb;
parameter CHANNEL_WIDTH = 5;
parameter POSITION_WIDTH = 11;
reg clk;
reg rst;
reg ext_clk;
reg ext_flush;
reg serial;
wire [1:0] pwm;
reg [7:0] data_in [3:0];
SerialServo U0 (
.clk100MHz(clk),
.clk1MHz(clk),
.rst(rst),
.ext_clk(ext_clk),
.ext_flush(ext_flush),
.serial(serial),
.channel(5'h02),
.pwm(pwm[0])
);
SerialServo U1 (
.clk100MHz(clk),
.clk1MHz(clk),
.rst(rst),
.ext_clk(ext_clk),
.ext_flush(ext_flush),
.serial(serial),
.channel(5'h04),
.pwm(pwm[1])
);
integer i = 0;
integer state = 0;
initial
begin
ext_clk = 0;
rst = 1;
ext_flush = 0;
serial = 0;
data_in[0] = 8'b00010_111;
data_in[1] = 8'b1111_1111;
data_in[2] = 8'b00100_100;
data_in[3] = 8'b0000_0000;
#5
ext_flush = 1;
rst = 0;
#5
ext_flush = 0;
state = 1;
for(i = 0; i < 8; i=i+1) begin
#1
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[2][7-i];
#5
ext_clk = 1;
#1
clk = 1;
end
state = 2;
for(i = 0; i < 8; i=i+1) begin
#1
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[3][7-i];
#5
ext_clk = 1;
#1
clk = 1;
end
state = 3;
for(i = 0; i < 8; i=i+1) begin
#1
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[0][7-i];
#5
ext_clk = 1;
#1
clk = 1;
end
state = 4;
for(i = 0; i < 8; i=i+1) begin
#1
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[1][7-i];
#5
ext_clk = 1;
#1
clk = 1;
end
state = 5;
for(i = 0; i < 8; i=i+1) begin
#1
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = 1;
#5
ext_clk = 1;
#1
clk = 1;
end
#5
ext_flush = 1;
#5
ext_flush = 0;
#50
#10 $stop;
#5 $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BLACKBOX_V
/**
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer, vpb/vnb
* taps, double-row-height cell.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
X,
A
);
output X;
input A;
// Voltage supply signals
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "sys.h"
module dram (/*AUTOARG*/
// Outputs
dram_io_addr0, dram_io_addr1, dram_io_bank0, dram_io_bank1,
dram_io_cas0_l, dram_io_cas1_l, dram_io_channel_disabled0,
dram_io_channel_disabled1, dram_io_cke0, dram_io_cke1,
dram_io_clk_enable0, dram_io_clk_enable1, dram_io_cs0_l,
dram_io_cs1_l, dram_io_data0_out, dram_io_data1_out,
dram_io_drive_data0, dram_io_drive_data1, dram_io_drive_enable0,
dram_io_drive_enable1, dram_io_pad_clk_inv0, dram_io_pad_clk_inv1,
dram_io_pad_enable0, dram_io_pad_enable1, dram_io_ptr_clk_inv0,
dram_io_ptr_clk_inv1, dram_io_ras0_l, dram_io_ras1_l,
dram_io_write_en0_l, dram_io_write_en1_l, dram_sctag0_data_vld_r0,
dram_sctag0_rd_ack, dram_sctag0_scb_mecc_err,
dram_sctag0_scb_secc_err, dram_sctag0_wr_ack,
dram_sctag1_data_vld_r0, dram_sctag1_rd_ack,
dram_sctag1_scb_mecc_err, dram_sctag1_scb_secc_err,
dram_sctag1_wr_ack, ucb_iob_data, ucb_iob_stall, ucb_iob_vld,
dram_sctag0_chunk_id_r0, dram_sctag0_mecc_err_r2,
dram_sctag0_rd_req_id_r0, dram_sctag0_secc_err_r2,
dram_sctag1_chunk_id_r0, dram_sctag1_mecc_err_r2,
dram_sctag1_rd_req_id_r0, dram_sctag1_secc_err_r2,
dram_scbuf0_data_r2, dram_scbuf0_ecc_r2, dram_scbuf1_data_r2,
dram_scbuf1_ecc_r2, dram_local_pt0_opened_bank,
dram_local_pt1_opened_bank, dram_pt_max_banks_open_valid,
dram_pt_max_time_valid, dram_pt_ucb_data, dram_clk_tr, dram_so,
// Inputs
dram_other_pt_max_banks_open_valid, dram_other_pt_max_time_valid,
dram_other_pt_ucb_data, dram_other_pt0_opened_bank,
dram_other_pt1_opened_bank, io_dram0_data_in, io_dram0_data_valid,
io_dram0_ecc_in, io_dram1_data_in, io_dram1_data_valid,
io_dram1_ecc_in, iob_ucb_data, iob_ucb_stall, iob_ucb_vld,
scbuf0_dram_data_mecc_r5, scbuf0_dram_data_vld_r5,
scbuf0_dram_wr_data_r5, scbuf1_dram_data_mecc_r5,
scbuf1_dram_data_vld_r5, scbuf1_dram_wr_data_r5, sctag0_dram_addr,
sctag0_dram_rd_dummy_req, sctag0_dram_rd_req,
sctag0_dram_rd_req_id, sctag0_dram_wr_req, sctag1_dram_addr,
sctag1_dram_rd_dummy_req, sctag1_dram_rd_req,
sctag1_dram_rd_req_id, sctag1_dram_wr_req, clspine_dram_rx_sync,
clspine_dram_tx_sync, clspine_jbus_rx_sync, clspine_jbus_tx_sync,
dram_gdbginit_l, clk_dram_jbus_cken, clk_dram_dram_cken,
clk_dram_cmp_cken, clspine_dram_selfrsh, global_shift_enable,
dram_si, jbus_gclk, dram_gclk, cmp_gclk, dram_adbginit_l,
dram_arst_l, jbus_grst_l, dram_grst_l, cmp_grst_l,
ctu_tst_scanmode, ctu_tst_pre_grst_l, ctu_tst_scan_disable,
ctu_tst_macrotest, ctu_tst_short_chain
);
//////////////////////////////
// OUTPUTS
//////////////////////////////
/*UTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [14:0] dram_io_addr0; // From dramctl0 of dramctl.v
output [14:0] dram_io_addr1; // From dramctl1 of dramctl.v
output [2:0] dram_io_bank0; // From dramctl0 of dramctl.v
output [2:0] dram_io_bank1; // From dramctl1 of dramctl.v
output dram_io_cas0_l; // From dramctl0 of dramctl.v
output dram_io_cas1_l; // From dramctl1 of dramctl.v
output dram_io_channel_disabled0;// From dramctl0 of dramctl.v
output dram_io_channel_disabled1;// From dramctl1 of dramctl.v
output dram_io_cke0; // From dramctl0 of dramctl.v
output dram_io_cke1; // From dramctl1 of dramctl.v
output dram_io_clk_enable0; // From dramctl0 of dramctl.v
output dram_io_clk_enable1; // From dramctl1 of dramctl.v
output [3:0] dram_io_cs0_l; // From dramctl0 of dramctl.v
output [3:0] dram_io_cs1_l; // From dramctl1 of dramctl.v
output [287:0] dram_io_data0_out; // From dramctl0 of dramctl.v
output [287:0] dram_io_data1_out; // From dramctl1 of dramctl.v
output dram_io_drive_data0; // From dramctl0 of dramctl.v
output dram_io_drive_data1; // From dramctl1 of dramctl.v
output dram_io_drive_enable0; // From dramctl0 of dramctl.v
output dram_io_drive_enable1; // From dramctl1 of dramctl.v
output dram_io_pad_clk_inv0; // From dramctl0 of dramctl.v
output dram_io_pad_clk_inv1; // From dramctl1 of dramctl.v
output dram_io_pad_enable0; // From dramctl0 of dramctl.v
output dram_io_pad_enable1; // From dramctl1 of dramctl.v
output [4:0] dram_io_ptr_clk_inv0; // From dramctl0 of dramctl.v
output [4:0] dram_io_ptr_clk_inv1; // From dramctl1 of dramctl.v
output dram_io_ras0_l; // From dramctl0 of dramctl.v
output dram_io_ras1_l; // From dramctl1 of dramctl.v
output dram_io_write_en0_l; // From dramctl0 of dramctl.v
output dram_io_write_en1_l; // From dramctl1 of dramctl.v
output dram_sctag0_data_vld_r0;// From dramctl0 of dramctl.v
output dram_sctag0_rd_ack; // From dramctl0 of dramctl.v
output dram_sctag0_scb_mecc_err;// From dramctl0 of dramctl.v
output dram_sctag0_scb_secc_err;// From dramctl0 of dramctl.v
output dram_sctag0_wr_ack; // From dramctl0 of dramctl.v
output dram_sctag1_data_vld_r0;// From dramctl1 of dramctl.v
output dram_sctag1_rd_ack; // From dramctl1 of dramctl.v
output dram_sctag1_scb_mecc_err;// From dramctl1 of dramctl.v
output dram_sctag1_scb_secc_err;// From dramctl1 of dramctl.v
output dram_sctag1_wr_ack; // From dramctl1 of dramctl.v
output [3:0] ucb_iob_data; // From dram_ucb of dram_ucb.v
output ucb_iob_stall; // From dram_ucb of dram_ucb.v
output ucb_iob_vld; // From dram_ucb of dram_ucb.v
output [1:0] dram_sctag0_chunk_id_r0;// From dramctl0 of dramctl.v
output dram_sctag0_mecc_err_r2;// From dramctl0 of dramctl.v
output [2:0] dram_sctag0_rd_req_id_r0;// From dramctl0 of dramctl.v
output dram_sctag0_secc_err_r2;// From dramctl0 of dramctl.v
output [1:0] dram_sctag1_chunk_id_r0;// From dramctl1 of dramctl.v
output dram_sctag1_mecc_err_r2;// From dramctl1 of dramctl.v
output [2:0] dram_sctag1_rd_req_id_r0;// From dramctl1 of dramctl.v
output dram_sctag1_secc_err_r2;// From dramctl1 of dramctl.v
output [127:0] dram_scbuf0_data_r2; // From dramctl0 of dramctl.v
output [27:0] dram_scbuf0_ecc_r2; // From dramctl0 of dramctl.v
output [127:0] dram_scbuf1_data_r2; // From dramctl1 of dramctl.v
output [27:0] dram_scbuf1_ecc_r2; // From dramctl1 of dramctl.v
output dram_local_pt0_opened_bank;// From dramctl0 of dramctl.v
output dram_local_pt1_opened_bank;// From dramctl1 of dramctl.v
output dram_pt_max_banks_open_valid;
output dram_pt_max_time_valid;
output [16:0] dram_pt_ucb_data;
// End of automatics
//////////////////////////////
// INPUTS
//////////////////////////////
/*UTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input dram_other_pt_max_banks_open_valid;
input dram_other_pt_max_time_valid;
input [16:0] dram_other_pt_ucb_data;
input dram_other_pt0_opened_bank;// To dram_common_ctl of dram_common_ctl.v
input dram_other_pt1_opened_bank;// To dram_common_ctl of dram_common_ctl.v
input [255:0] io_dram0_data_in; // To dramctl0 of dramctl.v
input io_dram0_data_valid; // To dramctl0 of dramctl.v
input [31:0] io_dram0_ecc_in; // To dramctl0 of dramctl.v
input [255:0] io_dram1_data_in; // To dramctl1 of dramctl.v
input io_dram1_data_valid; // To dramctl1 of dramctl.v
input [31:0] io_dram1_ecc_in; // To dramctl1 of dramctl.v
input [3:0] iob_ucb_data; // To dram_ucb of dram_ucb.v
input iob_ucb_stall; // To dram_ucb of dram_ucb.v
input iob_ucb_vld; // To dram_ucb of dram_ucb.v
input scbuf0_dram_data_mecc_r5;// To dramctl0 of dramctl.v
input scbuf0_dram_data_vld_r5;// To dramctl0 of dramctl.v
input [63:0] scbuf0_dram_wr_data_r5; // To dramctl0 of dramctl.v
input scbuf1_dram_data_mecc_r5;// To dramctl1 of dramctl.v
input scbuf1_dram_data_vld_r5;// To dramctl1 of dramctl.v
input [63:0] scbuf1_dram_wr_data_r5; // To dramctl1 of dramctl.v
input [39:5] sctag0_dram_addr; // To dramctl0 of dramctl.v
input sctag0_dram_rd_dummy_req;// To dramctl0 of dramctl.v
input sctag0_dram_rd_req; // To dramctl0 of dramctl.v
input [2:0] sctag0_dram_rd_req_id; // To dramctl0 of dramctl.v
input sctag0_dram_wr_req; // To dramctl0 of dramctl.v
input [39:5] sctag1_dram_addr; // To dramctl1 of dramctl.v
input sctag1_dram_rd_dummy_req;// To dramctl1 of dramctl.v
input sctag1_dram_rd_req; // To dramctl1 of dramctl.v
input [2:0] sctag1_dram_rd_req_id; // To dramctl1 of dramctl.v
input sctag1_dram_wr_req; // To dramctl1 of dramctl.v
// End of automatics
//////////////////////////////
//ddr test/clk signals
//////////////////////////////
input clspine_dram_rx_sync; // To dramctl0 of dramctl.v, ...
input clspine_dram_tx_sync; // To dramctl0 of dramctl.v, ...
input clspine_jbus_rx_sync; // To dramctl0 of dramctl.v, ...
input clspine_jbus_tx_sync; // To dramctl0 of dramctl.v, ...
input dram_gdbginit_l; // Debug init for repeatability @jubs freq
input clk_dram_jbus_cken; // jbus clock enable
input clk_dram_dram_cken; // ddr clock enable
input clk_dram_cmp_cken; // cmp clock enable
input clspine_dram_selfrsh; // signal from clk to put in self refresh @jbus freq
input global_shift_enable; // scan shift enable signal
output dram_clk_tr; // debug trigger @ jbus freq
input dram_si;
output dram_so;
input jbus_gclk; // jbus clock
input dram_gclk; // ddr clock
input cmp_gclk; // cmp clock
input dram_adbginit_l; // active low async reset of dbginit_l
input dram_arst_l; // active low async reset of rst_l
input jbus_grst_l; // active low reset signal
input dram_grst_l; // active low reset signal
input cmp_grst_l; // active low reset signal
input ctu_tst_scanmode;
input ctu_tst_pre_grst_l;
input ctu_tst_scan_disable;
input ctu_tst_macrotest;
input ctu_tst_short_chain;
//////////////////////////////////////////////////////////////////
// Wires
//////////////////////////////////////////////////////////////////
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ch0_dp_data_mecc0; // From dramctl0 of dramctl.v
wire [3:0] ch0_dp_data_mecc1; // From dramctl0 of dramctl.v
wire [3:0] ch0_dp_data_mecc2; // From dramctl0 of dramctl.v
wire [3:0] ch0_dp_data_mecc3; // From dramctl0 of dramctl.v
wire [3:0] ch0_dp_data_mecc4; // From dramctl0 of dramctl.v
wire [3:0] ch0_dp_data_mecc5; // From dramctl0 of dramctl.v
wire [3:0] ch0_dp_data_mecc6; // From dramctl0 of dramctl.v
wire [3:0] ch0_dp_data_mecc7; // From dramctl0 of dramctl.v
wire ch0_dp_data_valid_d1; // From dramctl0 of dramctl.v
wire ch0_dram_data_val_other_ch;// From dramctl0 of dramctl.v
wire [35:0] ch0_err_loc; // From dramctl0 of dramctl.v
wire [15:0] ch0_err_syn; // From dramctl0 of dramctl.v
wire [35:0] ch0_que_b0_addr_picked; // From dramctl0 of dramctl.v
wire ch0_que_b0_cmd_picked; // From dramctl0 of dramctl.v
wire [5:0] ch0_que_b0_data_addr; // From dramctl0 of dramctl.v
wire [2:0] ch0_que_b0_id_picked; // From dramctl0 of dramctl.v
wire [2:0] ch0_que_b0_index_picked;// From dramctl0 of dramctl.v
wire [7:0] ch0_que_cas_int_picked; // From dramctl0 of dramctl.v
wire ch0_que_channel_picked; // From dramctl0 of dramctl.v
wire [6:0] ch0_que_int_wr_que_inv_info;// From dramctl0 of dramctl.v
wire [7:0] ch0_que_l2req_valids; // From dramctl0 of dramctl.v
wire [255:0] ch0_que_mem_data; // From dramctl0 of dramctl.v
wire ch0_que_mux_write_en; // From dramctl0 of dramctl.v
wire [4:0] ch0_que_pos; // From dramctl0 of dramctl.v
wire [7:0] ch0_que_ras_int_picked; // From dramctl0 of dramctl.v
wire ch0_que_wr_cas_ch01_picked;// From dramctl0 of dramctl.v
wire [3:0] ch1_dp_data_mecc0; // From dramctl1 of dramctl.v
wire [3:0] ch1_dp_data_mecc1; // From dramctl1 of dramctl.v
wire [3:0] ch1_dp_data_mecc2; // From dramctl1 of dramctl.v
wire [3:0] ch1_dp_data_mecc3; // From dramctl1 of dramctl.v
wire [3:0] ch1_dp_data_mecc4; // From dramctl1 of dramctl.v
wire [3:0] ch1_dp_data_mecc5; // From dramctl1 of dramctl.v
wire [3:0] ch1_dp_data_mecc6; // From dramctl1 of dramctl.v
wire [3:0] ch1_dp_data_mecc7; // From dramctl1 of dramctl.v
wire ch1_dp_data_valid_d1; // From dramctl1 of dramctl.v
wire ch1_dram_data_val_other_ch;// From dramctl1 of dramctl.v
wire [35:0] ch1_err_loc; // From dramctl1 of dramctl.v
wire [15:0] ch1_err_syn; // From dramctl1 of dramctl.v
wire [35:0] ch1_que_b0_addr_picked; // From dramctl1 of dramctl.v
wire ch1_que_b0_cmd_picked; // From dramctl1 of dramctl.v
wire [5:0] ch1_que_b0_data_addr; // From dramctl1 of dramctl.v
wire [2:0] ch1_que_b0_id_picked; // From dramctl1 of dramctl.v
wire [2:0] ch1_que_b0_index_picked;// From dramctl1 of dramctl.v
wire [7:0] ch1_que_cas_int_picked; // From dramctl1 of dramctl.v
wire ch1_que_channel_picked; // From dramctl1 of dramctl.v
wire [6:0] ch1_que_int_wr_que_inv_info;// From dramctl1 of dramctl.v
wire [7:0] ch1_que_l2req_valids; // From dramctl1 of dramctl.v
wire [255:0] ch1_que_mem_data; // From dramctl1 of dramctl.v
wire ch1_que_mux_write_en; // From dramctl1 of dramctl.v
wire [4:0] ch1_que_pos; // From dramctl1 of dramctl.v
wire [7:0] ch1_que_ras_int_picked; // From dramctl1 of dramctl.v
wire ch1_que_wr_cas_ch01_picked;// From dramctl1 of dramctl.v
wire cmp_after_clk_rst_l; // From cpu_cluster_header of bw_clk_cl_dram_cmp.v
wire cmp_rclk; // From cpu_cluster_header of bw_clk_cl_dram_cmp.v
wire cpu_cluster_so; // From cpu_cluster_header of bw_clk_cl_dram_cmp.v
wire dbginit_l; // From dram_cluster_header of bw_clk_cl_dram_ddr.v
wire dram_cluster_so; // From dram_cluster_header of bw_clk_cl_dram_ddr.v
wire dram_dram_rx_sync; // From jbus_cluster_header_sync of cluster_header_sync.v
wire dram_dram_tx_sync; // From jbus_cluster_header_sync of cluster_header_sync.v
wire dram_jbus_rx_sync; // From jbus_cluster_header_sync of cluster_header_sync.v
wire dram_jbus_tx_sync; // From jbus_cluster_header_sync of cluster_header_sync.v
wire dram_rclk; // From dram_cluster_header of bw_clk_cl_dram_ddr.v
wire dram_rst_l; // From dram_cluster_header of bw_clk_cl_dram_ddr.v
wire dram_sctag0_pa_err_r2; // From dramctl0 of dramctl.v
wire dram_sctag1_pa_err_r2; // From dramctl1 of dramctl.v
wire dram_ucb_ack_vld0; // From dramctl0 of dramctl.v
wire dram_ucb_ack_vld1; // From dramctl1 of dramctl.v
wire [63:0] dram_ucb_data0; // From dramctl0 of dramctl.v
wire [63:0] dram_ucb_data1; // From dramctl1 of dramctl.v
wire dram_ucb_nack_vld0; // From dramctl0 of dramctl.v
wire dram_ucb_nack_vld1; // From dramctl1 of dramctl.v
wire jbus_cluster_so; // From jbus_cluster_header of bw_clk_cl_dram_jbus.v
wire jbus_rclk; // From jbus_cluster_header of bw_clk_cl_dram_jbus.v
wire jbus_rst_l; // From jbus_cluster_header of bw_clk_cl_dram_jbus.v
wire l2if0_channel_disabled; // From dramctl0 of dramctl.v
wire l2if1_channel_disabled; // From dramctl1 of dramctl.v
wire l2if_err_intr0; // From dramctl0 of dramctl.v
wire l2if_err_intr1; // From dramctl1 of dramctl.v
wire l2if_ucb_trig0; // From dramctl0 of dramctl.v
wire l2if_ucb_trig1; // From dramctl1 of dramctl.v
wire [64:0] listen_out0; // From dramctl0 of dramctl.v
wire [64:0] listen_out1; // From dramctl1 of dramctl.v
wire mem_bypass; // From test_stub_scan of test_stub_scan.v
wire pt_ch0_blk_new_openbank;// From dram_pt of dram_pt.v
wire pt_ch1_blk_new_openbank;// From dram_pt of dram_pt.v
wire [16:0] pt_max_banks_open; // From dram_pt of dram_pt.v
wire [15:0] pt_max_time; // From dram_pt of dram_pt.v
wire que0_channel_disabled; // From dramctl0 of dramctl.v
wire que1_channel_disabled; // From dramctl1 of dramctl.v
wire [16:0] que_max_banks_open0; // From dramctl0 of dramctl.v
wire [16:0] que_max_banks_open1; // From dramctl1 of dramctl.v
wire que_max_banks_open_valid0;// From dramctl0 of dramctl.v
wire que_max_banks_open_valid1;// From dramctl1 of dramctl.v
wire que_max_time_valid0; // From dramctl0 of dramctl.v
wire que_max_time_valid1; // From dramctl1 of dramctl.v
wire se; // From test_stub_scan of test_stub_scan.v
wire sehold; // From test_stub_scan of test_stub_scan.v
wire so_0; // From test_stub_scan of test_stub_scan.v
wire testmode_l; // From test_stub_scan of test_stub_scan.v
wire [31:0] ucb_dram_addr; // From dram_ucb of dram_ucb.v
wire [63:0] ucb_dram_data; // From dram_ucb of dram_ucb.v
wire ucb_dram_rd_req_vld0; // From dram_ucb of dram_ucb.v
wire ucb_dram_rd_req_vld1; // From dram_ucb of dram_ucb.v
wire ucb_dram_wr_req_vld0; // From dram_ucb of dram_ucb.v
wire ucb_dram_wr_req_vld1; // From dram_ucb of dram_ucb.v
wire ucb_l2if_selfrsh; // From dram_ucb of dram_ucb.v
// End of automatics
wire cpu_cluster_si;
wire dram_cluster_si;
wire jbus_cluster_si;
wire long_chain_so_0;
wire short_chain_so_0;
/*****************************************************************
* Cluster Header
****************************************************************/
/*bw_clk_cl_dram_ddr AUTO_TEMPLATE(.rclk(dram_rclk),
.cluster_grst_l(dram_rst_l),
.gclk(dram_gclk),
.grst_l(dram_grst_l),
.so(dram_cluster_so),
.si(dram_cluster_si),
.se(se),
.arst_l(dram_arst_l),
.gdbginit_l(dram_gdbginit_l),
.adbginit_l(dram_adbginit_l),
.cluster_cken(clk_dram_dram_cken));
*/
bw_clk_cl_dram_ddr dram_cluster_header(/*AUTOINST*/
// Outputs
.cluster_grst_l(dram_rst_l), // Templated
.dbginit_l(dbginit_l),
.rclk(dram_rclk), // Templated
.so(dram_cluster_so), // Templated
// Inputs
.adbginit_l(dram_adbginit_l), // Templated
.arst_l(dram_arst_l), // Templated
.cluster_cken(clk_dram_dram_cken), // Templated
.gclk(dram_gclk), // Templated
.gdbginit_l(dram_gdbginit_l), // Templated
.grst_l(dram_grst_l), // Templated
.se(se), // Templated
.si(dram_cluster_si)); // Templated
/*bw_clk_cl_dram_cmp AUTO_TEMPLATE(.rclk(cmp_rclk),
.dbginit_l(),
.cluster_grst_l(cmp_after_clk_rst_l),
.gclk(cmp_gclk),
.grst_l(cmp_grst_l),
.so(cpu_cluster_so),
.si(cpu_cluster_si),
.se(se),
.arst_l(dram_arst_l),
.adbginit_l(1'b1),
.gdbginit_l(1'b1),
.cluster_cken(clk_dram_cmp_cken));
*/
bw_clk_cl_dram_cmp cpu_cluster_header(/*AUTOINST*/
// Outputs
.cluster_grst_l(cmp_after_clk_rst_l), // Templated
.dbginit_l(), // Templated
.rclk(cmp_rclk), // Templated
.so(cpu_cluster_so), // Templated
// Inputs
.adbginit_l(1'b1), // Templated
.arst_l(dram_arst_l), // Templated
.cluster_cken(clk_dram_cmp_cken), // Templated
.gclk(cmp_gclk), // Templated
.gdbginit_l(1'b1), // Templated
.grst_l(cmp_grst_l), // Templated
.se(se), // Templated
.si(cpu_cluster_si)); // Templated
dffrl_async_ns #(1) async_rst_flop(
.din(cmp_after_clk_rst_l),
.q(cmp_rst_l),
.rst_l(dram_arst_l),
.clk(cmp_rclk));
/*bw_clk_cl_dram_jbus AUTO_TEMPLATE(.rclk(jbus_rclk),
.dbginit_l(),
.cluster_grst_l(jbus_rst_l),
.gclk(jbus_gclk),
.grst_l(jbus_grst_l),
.so(jbus_cluster_so),
.si(jbus_cluster_si),
.se(se),
.arst_l(dram_arst_l),
.adbginit_l(1'b1),
.gdbginit_l(1'b1),
.cluster_cken(clk_dram_jbus_cken));
*/
bw_clk_cl_dram_jbus jbus_cluster_header(/*AUTOINST*/
// Outputs
.cluster_grst_l(jbus_rst_l), // Templated
.dbginit_l(), // Templated
.rclk(jbus_rclk), // Templated
.so(jbus_cluster_so), // Templated
// Inputs
.adbginit_l(1'b1), // Templated
.arst_l(dram_arst_l), // Templated
.cluster_cken(clk_dram_jbus_cken), // Templated
.gclk(jbus_gclk), // Templated
.gdbginit_l(1'b1), // Templated
.grst_l(jbus_grst_l), // Templated
.se(se), // Templated
.si(jbus_cluster_si)); // Templated
/*****************************************************************
* Test Stub
****************************************************************/
/*test_stub_scan AUTO_TEMPLATE(.rclk(dram_rclk),
.arst_l(dram_arst_l),
.mux_drive_disable(),
.mem_write_disable(),
.long_chain_so_1(),
.long_chain_so_2(),
.short_chain_so_1(),
.short_chain_so_2(),
.so_1(),
.so_2());
*/
test_stub_scan test_stub_scan(/*AUTOINST*/
// Outputs
.mux_drive_disable(), // Templated
.mem_write_disable(), // Templated
.sehold(sehold),
.se (se),
.testmode_l(testmode_l),
.mem_bypass(mem_bypass),
.so_0(so_0),
.so_1(), // Templated
.so_2(), // Templated
// Inputs
.ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
.arst_l(dram_arst_l), // Templated
.global_shift_enable(global_shift_enable),
.ctu_tst_scan_disable(ctu_tst_scan_disable),
.ctu_tst_scanmode(ctu_tst_scanmode),
.ctu_tst_macrotest(ctu_tst_macrotest),
.ctu_tst_short_chain(ctu_tst_short_chain),
.long_chain_so_0(long_chain_so_0),
.short_chain_so_0(short_chain_so_0),
.long_chain_so_1(), // Templated
.short_chain_so_1(), // Templated
.long_chain_so_2(), // Templated
.short_chain_so_2()); // Templated
/*****************************************************************
* cluster header synchronizers
****************************************************************/
/* cluster_header_sync AUTO_TEMPLATE(
.dram_rx_sync_local(dram_dram_rx_sync),
.dram_tx_sync_local(dram_dram_tx_sync),
.jbus_rx_sync_local(dram_jbus_rx_sync),
.jbus_tx_sync_local(dram_jbus_tx_sync),
.so(),
.dram_rx_sync_global(clspine_dram_rx_sync),
.dram_tx_sync_global(clspine_dram_tx_sync),
.jbus_rx_sync_global(clspine_jbus_rx_sync),
.jbus_tx_sync_global(clspine_jbus_tx_sync),
.cmp_rclk(cmp_rclk),
.si());
*/
cluster_header_sync jbus_cluster_header_sync(/*AUTOINST*/
// Outputs
.dram_rx_sync_local(dram_dram_rx_sync), // Templated
.dram_tx_sync_local(dram_dram_tx_sync), // Templated
.jbus_rx_sync_local(dram_jbus_rx_sync), // Templated
.jbus_tx_sync_local(dram_jbus_tx_sync), // Templated
.so(), // Templated
// Inputs
.dram_rx_sync_global(clspine_dram_rx_sync), // Templated
.dram_tx_sync_global(clspine_dram_tx_sync), // Templated
.jbus_rx_sync_global(clspine_jbus_rx_sync), // Templated
.jbus_tx_sync_global(clspine_jbus_tx_sync), // Templated
.cmp_gclk(cmp_gclk),
.cmp_rclk(cmp_rclk), // Templated
.si(), // Templated
.se(se));
/*****************************************************************
* DRAM controller design
****************************************************************/
/* dramctl AUTO_TEMPLATE(
// Outputs
.que_cas_int_picked (ch@_que_cas_int_picked[7:0]),
.que_wr_cas_ch01_picked (ch@_que_wr_cas_ch01_picked),
.que_mux_write_en (ch@_que_mux_write_en),
.err_loc (ch@_err_loc[35:0]),
.err_syn (ch@_err_syn[15:0]),
.listen_out (listen_out@[64:0]),
.que_channel_disabled (que@_channel_disabled),
.dram_io_channel_disabled(dram_io_channel_disabled@),
.l2if_channel_disabled (l2if@_channel_disabled),
.que_int_pos (ch@_que_pos[4:0]),
.que_mem_data (ch@_que_mem_data[255:0]),
.dp_data_mecc0 (ch@_dp_data_mecc0[3:0]),
.dp_data_mecc1 (ch@_dp_data_mecc1[3:0]),
.dp_data_mecc2 (ch@_dp_data_mecc2[3:0]),
.dp_data_mecc3 (ch@_dp_data_mecc3[3:0]),
.dp_data_mecc4 (ch@_dp_data_mecc4[3:0]),
.dp_data_mecc5 (ch@_dp_data_mecc5[3:0]),
.dp_data_mecc6 (ch@_dp_data_mecc6[3:0]),
.dp_data_mecc7 (ch@_dp_data_mecc7[3:0]),
.que_int_wr_que_inv_info(ch@_que_int_wr_que_inv_info[6:0]),
.dp_data_valid_d1 (ch@_dp_data_valid_d1),
.que_ras_int_picked (ch@_que_ras_int_picked[7:0]),
.que_b0_data_addr (ch@_que_b0_data_addr[5:0]),
.que_l2req_valids (ch@_que_l2req_valids[7:0]),
.que_b0_addr_picked (ch@_que_b0_addr_picked[35:0]),
.que_b0_id_picked (ch@_que_b0_id_picked[2:0]),
.que_b0_index_picked (ch@_que_b0_index_picked[2:0]),
.que_b0_cmd_picked (ch@_que_b0_cmd_picked),
.que_channel_picked (ch@_que_channel_picked),
.dram_data_val_other_ch (ch@_dram_data_val_other_ch),
.dram_sctag_scb_mecc_err(dram_sctag@_scb_mecc_err),
.dram_sctag_scb_secc_err(dram_sctag@_scb_secc_err),
.dram_io_clk_enable (dram_io_clk_enable@),
.dram_io_pad_clk_inv (dram_io_pad_clk_inv@),
.dram_io_ptr_clk_inv (dram_io_ptr_clk_inv@),
.dram_io_pad_enable (dram_io_pad_enable@),
.dram_local_pt_opened_bank(dram_local_pt@_opened_bank),
.que_max_banks_open_valid(que_max_banks_open_valid@),
.que_max_banks_open (que_max_banks_open@[16:0]),
.que_max_time_valid (que_max_time_valid@),
.dram_sctag_chunk_id (dram_sctag@_chunk_id_r0[1:0]),
.dram_sctag_data_vld (dram_sctag@_data_vld_r0),
.dram_sctag_rd_req_id (dram_sctag@_rd_req_id_r0[2:0]),
.dram_sctag_data (dram_scbuf@_data_r2[127:0]),
.dram_sctag_mecc_err (dram_sctag@_mecc_err_r2),
.dram_sctag_pa_err (dram_sctag@_pa_err_r2),
.dram_sctag_secc_err (dram_sctag@_secc_err_r2),
.dram_sctag_ecc (dram_scbuf@_ecc_r2[27:0]),
.dram_sctag_rd_ack (dram_sctag@_rd_ack),
.dram_sctag_wr_ack (dram_sctag@_wr_ack),
.dram_io_data_out (dram_io_data@_out[287:0]),
.dram_io_addr (dram_io_addr@[14:0]),
.dram_io_bank (dram_io_bank@[2:0]),
.dram_io_cas_l (dram_io_cas@_l),
.dram_io_cke (dram_io_cke@),
.dram_io_cs_l (dram_io_cs@_l[3:0]),
.dram_io_drive_data (dram_io_drive_data@),
.dram_io_drive_enable (dram_io_drive_enable@),
.dram_io_ras_l (dram_io_ras@_l),
.dram_io_write_en_l (dram_io_write_en@_l),
.l2if_err_intr (l2if_err_intr@),
.dram_ucb_ack_vld (dram_ucb_ack_vld@),
.dram_ucb_nack_vld (dram_ucb_nack_vld@),
.dram_ucb_data (dram_ucb_data@[63:0]),
.l2if_ucb_trig (l2if_ucb_trig@),
// Inputs
.other_que_pos (ch@"(% (+ @ 1) 2)"_que_pos[4:0]),
.dram_dbginit_l (dbginit_l),
.margin (8'h55),
.mem_bypass (mem_bypass),
.sehold (sehold),
.ch0_que_cas_int_picked (ch@"(% (+ @ 1) 2)"_que_cas_int_picked[7:0]),
.ch0_que_wr_cas_ch01_picked(ch@"(% (+ @ 1) 2)"_que_wr_cas_ch01_picked),
.ch0_que_mux_write_en (ch@"(% (+ @ 1) 2)"_que_mux_write_en),
.other_que_channel_disabled(que@"(% (+ @ 1) 2)"_channel_disabled),
.other_channel_disabled (l2if@"(% (+ @ 1) 2)"_channel_disabled),
.ch1_que_mem_data (ch@"(% (+ @ 1) 2)"_que_mem_data[255:0]),
.ch1_dp_data_mecc0 (ch@"(% (+ @ 1) 2)"_dp_data_mecc0[3:0]),
.ch1_dp_data_mecc1 (ch@"(% (+ @ 1) 2)"_dp_data_mecc1[3:0]),
.ch1_dp_data_mecc2 (ch@"(% (+ @ 1) 2)"_dp_data_mecc2[3:0]),
.ch1_dp_data_mecc3 (ch@"(% (+ @ 1) 2)"_dp_data_mecc3[3:0]),
.ch1_dp_data_mecc4 (ch@"(% (+ @ 1) 2)"_dp_data_mecc4[3:0]),
.ch1_dp_data_mecc5 (ch@"(% (+ @ 1) 2)"_dp_data_mecc5[3:0]),
.ch1_dp_data_mecc6 (ch@"(% (+ @ 1) 2)"_dp_data_mecc6[3:0]),
.ch1_dp_data_mecc7 (ch@"(% (+ @ 1) 2)"_dp_data_mecc7[3:0]),
.ch1_que_int_wr_que_inv_info (ch@"(% (+ @ 1) 2)"_que_int_wr_que_inv_info[6:0]),
.ch1_que_l2req_valids (ch@"(% (+ @ 1) 2)"_que_l2req_valids[7:0]),
.ch1_que_b0_addr_picked (ch@"(% (+ @ 1) 2)"_que_b0_addr_picked[35:0]),
.ch1_que_b0_id_picked (ch@"(% (+ @ 1) 2)"_que_b0_id_picked[2:0]),
.ch1_que_b0_index_picked(ch@"(% (+ @ 1) 2)"_que_b0_index_picked[2:0]),
.ch1_que_b0_cmd_picked (ch@"(% (+ @ 1) 2)"_que_b0_cmd_picked),
.ch0_que_ras_int_picked (ch@"(% (+ @ 1) 2)"_que_ras_int_picked[7:0]),
.ch0_que_b0_data_addr (ch@"(% (+ @ 1) 2)"_que_b0_data_addr[5:0]),
.ch0_que_channel_picked (ch@"(% (+ @ 1) 2)"_que_channel_picked),
.ch0_dram_data_val_other_ch(ch@"(% (+ @ 1) 2)"_dram_data_val_other_ch),
.ch0_dram_sctag_chunk_id(dram_sctag@"(% (+ @ 1) 2)"_chunk_id_r0[1:0]),
.ch0_dram_sctag_rd_req_id (dram_sctag@"(% (+ @ 1) 2)"_rd_req_id_r0[2:0]),
.ch0_dram_sctag_data (dram_scbuf@"(% (+ @ 1) 2)"_data_r2[127:0]),
.ch0_dram_sctag_ecc (dram_scbuf@"(% (+ @ 1) 2)"_ecc_r2[27:0]),
.ch0_dram_sctag_mecc_err(dram_sctag@"(% (+ @ 1) 2)"_mecc_err_r2),
.ch0_dram_sctag_pa_err(dram_sctag@"(% (+ @ 1) 2)"_pa_err_r2),
.ch0_dram_sctag_secc_err(dram_sctag@"(% (+ @ 1) 2)"_secc_err_r2),
.ch0_dp_data_valid_d1 (ch@"(% (+ @ 1) 2)"_dp_data_valid_d1),
.ch0_err_loc (ch@"(% (+ @ 1) 2)"_err_loc[35:0]),
.ch0_err_syn (ch@"(% (+ @ 1) 2)"_err_syn[15:0]),
.dram_dram_rx_sync (dram_dram_rx_sync),
.dram_dram_tx_sync (dram_dram_tx_sync),
.dram_jbus_rx_sync (dram_jbus_rx_sync),
.dram_jbus_tx_sync (dram_jbus_tx_sync),
.ucb_l2if_slfrsh (ucb_l2if_selfrsh),
.pt_ch_blk_new_openbank (pt_ch@_blk_new_openbank),
.pt_max_banks_open (pt_max_banks_open[16:0]),
.pt_max_time (pt_max_time[15:0]),
.ucb_dram_rd_req_vld (ucb_dram_rd_req_vld@),
.ucb_dram_wr_req_vld (ucb_dram_wr_req_vld@),
.ucb_dram_addr (ucb_dram_addr[31:0]),
.ucb_dram_data (ucb_dram_data[63:0]),
.sctag_dram_rd_req (sctag@_dram_rd_req),
.sctag_dram_rd_dummy_req(sctag@_dram_rd_dummy_req),
.sctag_dram_data_vld (scbuf@_dram_data_vld_r5),
.sctag_dram_rd_req_id (sctag@_dram_rd_req_id[2:0]),
.sctag_dram_addr (sctag@_dram_addr[39:5]),
.sctag_dram_wr_req (sctag@_dram_wr_req),
.sctag_dram_wr_data (scbuf@_dram_wr_data_r5[63:0]),
.sctag_dram_data_mecc (scbuf@_dram_data_mecc_r5),
.cmp_clk (cmp_rclk),
.cmp_rst_l (cmp_rst_l),
.dram_clk (dram_rclk),
.dram_rst_l (dram_rst_l),
.dram_arst_l (dram_arst_l),
.io_dram_data_valid (io_dram@_data_valid),
.io_dram_data_in (io_dram@_data_in[255:0]),
.io_dram_ecc_in (io_dram@_ecc_in[31:0]));
*/
/*****************************************************************
* Channel 0 or 1 in four Channel mode
****************************************************************/
dramctl dramctl0(/*AUTOINST*/
// Outputs
.l2if_ucb_trig (l2if_ucb_trig0), // Templated
.dram_sctag_chunk_id (dram_sctag0_chunk_id_r0[1:0]), // Templated
.dram_sctag_data_vld (dram_sctag0_data_vld_r0), // Templated
.dram_sctag_rd_req_id (dram_sctag0_rd_req_id_r0[2:0]), // Templated
.dram_sctag_data (dram_scbuf0_data_r2[127:0]), // Templated
.dram_sctag_mecc_err (dram_sctag0_mecc_err_r2), // Templated
.dram_sctag_pa_err (dram_sctag0_pa_err_r2), // Templated
.dram_sctag_secc_err (dram_sctag0_secc_err_r2), // Templated
.dram_sctag_ecc (dram_scbuf0_ecc_r2[27:0]), // Templated
.dram_sctag_rd_ack (dram_sctag0_rd_ack), // Templated
.dram_sctag_wr_ack (dram_sctag0_wr_ack), // Templated
.dram_io_data_out (dram_io_data0_out[287:0]), // Templated
.dram_io_addr (dram_io_addr0[14:0]), // Templated
.dram_io_bank (dram_io_bank0[2:0]), // Templated
.dram_io_cas_l (dram_io_cas0_l), // Templated
.dram_io_cke (dram_io_cke0), // Templated
.dram_io_cs_l (dram_io_cs0_l[3:0]), // Templated
.dram_io_drive_data (dram_io_drive_data0), // Templated
.dram_io_drive_enable (dram_io_drive_enable0), // Templated
.dram_io_ras_l (dram_io_ras0_l), // Templated
.dram_io_write_en_l (dram_io_write_en0_l), // Templated
.dram_io_pad_enable (dram_io_pad_enable0), // Templated
.dram_io_clk_enable (dram_io_clk_enable0), // Templated
.dram_io_ptr_clk_inv (dram_io_ptr_clk_inv0), // Templated
.dram_io_pad_clk_inv (dram_io_pad_clk_inv0), // Templated
.dram_io_channel_disabled(dram_io_channel_disabled0), // Templated
.dram_ucb_ack_vld (dram_ucb_ack_vld0), // Templated
.dram_ucb_nack_vld (dram_ucb_nack_vld0), // Templated
.dram_ucb_data (dram_ucb_data0[63:0]), // Templated
.l2if_err_intr (l2if_err_intr0), // Templated
.dram_local_pt_opened_bank(dram_local_pt0_opened_bank), // Templated
.que_max_banks_open_valid(que_max_banks_open_valid0), // Templated
.que_max_banks_open (que_max_banks_open0[16:0]), // Templated
.que_max_time_valid (que_max_time_valid0), // Templated
.dram_sctag_scb_mecc_err(dram_sctag0_scb_mecc_err), // Templated
.dram_sctag_scb_secc_err(dram_sctag0_scb_secc_err), // Templated
.que_int_pos (ch0_que_pos[4:0]), // Templated
.que_int_wr_que_inv_info(ch0_que_int_wr_que_inv_info[6:0]), // Templated
.que_ras_int_picked (ch0_que_ras_int_picked[7:0]), // Templated
.que_b0_data_addr (ch0_que_b0_data_addr[5:0]), // Templated
.que_l2req_valids (ch0_que_l2req_valids[7:0]), // Templated
.que_b0_addr_picked (ch0_que_b0_addr_picked[35:0]), // Templated
.que_b0_id_picked (ch0_que_b0_id_picked[2:0]), // Templated
.que_b0_index_picked (ch0_que_b0_index_picked[2:0]), // Templated
.que_b0_cmd_picked (ch0_que_b0_cmd_picked), // Templated
.que_channel_picked (ch0_que_channel_picked), // Templated
.dp_data_valid_d1 (ch0_dp_data_valid_d1), // Templated
.dram_data_val_other_ch(ch0_dram_data_val_other_ch), // Templated
.que_mem_data (ch0_que_mem_data[255:0]), // Templated
.dp_data_mecc0 (ch0_dp_data_mecc0[3:0]), // Templated
.dp_data_mecc1 (ch0_dp_data_mecc1[3:0]), // Templated
.dp_data_mecc2 (ch0_dp_data_mecc2[3:0]), // Templated
.dp_data_mecc3 (ch0_dp_data_mecc3[3:0]), // Templated
.dp_data_mecc4 (ch0_dp_data_mecc4[3:0]), // Templated
.dp_data_mecc5 (ch0_dp_data_mecc5[3:0]), // Templated
.dp_data_mecc6 (ch0_dp_data_mecc6[3:0]), // Templated
.dp_data_mecc7 (ch0_dp_data_mecc7[3:0]), // Templated
.err_syn (ch0_err_syn[15:0]), // Templated
.err_loc (ch0_err_loc[35:0]), // Templated
.que_channel_disabled (que0_channel_disabled), // Templated
.l2if_channel_disabled (l2if0_channel_disabled), // Templated
.listen_out (listen_out0[64:0]), // Templated
.que_cas_int_picked (ch0_que_cas_int_picked[7:0]), // Templated
.que_wr_cas_ch01_picked(ch0_que_wr_cas_ch01_picked), // Templated
.que_mux_write_en (ch0_que_mux_write_en), // Templated
// Inputs
.ucb_l2if_selfrsh (ucb_l2if_selfrsh),
.dram_dbginit_l (dbginit_l), // Templated
.sctag_dram_rd_req (sctag0_dram_rd_req), // Templated
.sctag_dram_rd_dummy_req(sctag0_dram_rd_dummy_req), // Templated
.sctag_dram_data_vld (scbuf0_dram_data_vld_r5), // Templated
.sctag_dram_rd_req_id (sctag0_dram_rd_req_id[2:0]), // Templated
.sctag_dram_addr (sctag0_dram_addr[39:5]), // Templated
.sctag_dram_wr_req (sctag0_dram_wr_req), // Templated
.sctag_dram_wr_data (scbuf0_dram_wr_data_r5[63:0]), // Templated
.sctag_dram_data_mecc (scbuf0_dram_data_mecc_r5), // Templated
.cmp_clk (cmp_rclk), // Templated
.dram_clk (dram_rclk), // Templated
.cmp_rst_l (cmp_rst_l), // Templated
.dram_rst_l (dram_rst_l), // Templated
.dram_arst_l (dram_arst_l), // Templated
.io_dram_data_valid (io_dram0_data_valid), // Templated
.io_dram_data_in (io_dram0_data_in[255:0]), // Templated
.io_dram_ecc_in (io_dram0_ecc_in[31:0]), // Templated
.ucb_dram_rd_req_vld (ucb_dram_rd_req_vld0), // Templated
.ucb_dram_wr_req_vld (ucb_dram_wr_req_vld0), // Templated
.ucb_dram_addr (ucb_dram_addr[31:0]), // Templated
.ucb_dram_data (ucb_dram_data[63:0]), // Templated
.pt_ch_blk_new_openbank(pt_ch0_blk_new_openbank), // Templated
.pt_max_banks_open (pt_max_banks_open[16:0]), // Templated
.pt_max_time (pt_max_time[15:0]), // Templated
.dram_dram_rx_sync (dram_dram_rx_sync), // Templated
.dram_dram_tx_sync (dram_dram_tx_sync), // Templated
.dram_jbus_rx_sync (dram_jbus_rx_sync), // Templated
.dram_jbus_tx_sync (dram_jbus_tx_sync), // Templated
.ch0_que_ras_int_picked(ch1_que_ras_int_picked[7:0]), // Templated
.ch0_que_b0_data_addr (ch1_que_b0_data_addr[5:0]), // Templated
.ch0_que_channel_picked(ch1_que_channel_picked), // Templated
.ch1_que_l2req_valids (ch1_que_l2req_valids[7:0]), // Templated
.ch1_que_b0_addr_picked(ch1_que_b0_addr_picked[35:0]), // Templated
.ch1_que_b0_id_picked (ch1_que_b0_id_picked[2:0]), // Templated
.ch1_que_b0_index_picked(ch1_que_b0_index_picked[2:0]), // Templated
.ch1_que_b0_cmd_picked (ch1_que_b0_cmd_picked), // Templated
.ch1_que_int_wr_que_inv_info(ch1_que_int_wr_que_inv_info[6:0]), // Templated
.other_que_pos (ch1_que_pos[4:0]), // Templated
.ch0_dram_data_val_other_ch(ch1_dram_data_val_other_ch), // Templated
.ch0_dram_sctag_chunk_id(dram_sctag1_chunk_id_r0[1:0]), // Templated
.ch0_dram_sctag_rd_req_id(dram_sctag1_rd_req_id_r0[2:0]), // Templated
.ch0_dram_sctag_data (dram_scbuf1_data_r2[127:0]), // Templated
.ch0_dram_sctag_ecc (dram_scbuf1_ecc_r2[27:0]), // Templated
.ch0_dram_sctag_mecc_err(dram_sctag1_mecc_err_r2), // Templated
.ch0_dram_sctag_pa_err (dram_sctag1_pa_err_r2), // Templated
.ch0_dram_sctag_secc_err(dram_sctag1_secc_err_r2), // Templated
.ch0_dp_data_valid_d1 (ch1_dp_data_valid_d1), // Templated
.ch0_err_syn (ch1_err_syn[15:0]), // Templated
.ch0_err_loc (ch1_err_loc[35:0]), // Templated
.ch1_que_mem_data (ch1_que_mem_data[255:0]), // Templated
.ch1_dp_data_mecc0 (ch1_dp_data_mecc0[3:0]), // Templated
.ch1_dp_data_mecc1 (ch1_dp_data_mecc1[3:0]), // Templated
.ch1_dp_data_mecc2 (ch1_dp_data_mecc2[3:0]), // Templated
.ch1_dp_data_mecc3 (ch1_dp_data_mecc3[3:0]), // Templated
.ch1_dp_data_mecc4 (ch1_dp_data_mecc4[3:0]), // Templated
.ch1_dp_data_mecc5 (ch1_dp_data_mecc5[3:0]), // Templated
.ch1_dp_data_mecc6 (ch1_dp_data_mecc6[3:0]), // Templated
.ch1_dp_data_mecc7 (ch1_dp_data_mecc7[3:0]), // Templated
.other_channel_disabled(l2if1_channel_disabled), // Templated
.other_que_channel_disabled(que1_channel_disabled), // Templated
.sehold (sehold), // Templated
.mem_bypass (mem_bypass), // Templated
.ch0_que_cas_int_picked(ch1_que_cas_int_picked[7:0]), // Templated
.ch0_que_wr_cas_ch01_picked(ch1_que_wr_cas_ch01_picked), // Templated
.ch0_que_mux_write_en (ch1_que_mux_write_en)); // Templated
/*****************************************************************
* Channel 2 or 3 in four Channel mode
****************************************************************/
dramctl dramctl1(/*AUTOINST*/
// Outputs
.l2if_ucb_trig (l2if_ucb_trig1), // Templated
.dram_sctag_chunk_id (dram_sctag1_chunk_id_r0[1:0]), // Templated
.dram_sctag_data_vld (dram_sctag1_data_vld_r0), // Templated
.dram_sctag_rd_req_id (dram_sctag1_rd_req_id_r0[2:0]), // Templated
.dram_sctag_data (dram_scbuf1_data_r2[127:0]), // Templated
.dram_sctag_mecc_err (dram_sctag1_mecc_err_r2), // Templated
.dram_sctag_pa_err (dram_sctag1_pa_err_r2), // Templated
.dram_sctag_secc_err (dram_sctag1_secc_err_r2), // Templated
.dram_sctag_ecc (dram_scbuf1_ecc_r2[27:0]), // Templated
.dram_sctag_rd_ack (dram_sctag1_rd_ack), // Templated
.dram_sctag_wr_ack (dram_sctag1_wr_ack), // Templated
.dram_io_data_out (dram_io_data1_out[287:0]), // Templated
.dram_io_addr (dram_io_addr1[14:0]), // Templated
.dram_io_bank (dram_io_bank1[2:0]), // Templated
.dram_io_cas_l (dram_io_cas1_l), // Templated
.dram_io_cke (dram_io_cke1), // Templated
.dram_io_cs_l (dram_io_cs1_l[3:0]), // Templated
.dram_io_drive_data (dram_io_drive_data1), // Templated
.dram_io_drive_enable (dram_io_drive_enable1), // Templated
.dram_io_ras_l (dram_io_ras1_l), // Templated
.dram_io_write_en_l (dram_io_write_en1_l), // Templated
.dram_io_pad_enable (dram_io_pad_enable1), // Templated
.dram_io_clk_enable (dram_io_clk_enable1), // Templated
.dram_io_ptr_clk_inv (dram_io_ptr_clk_inv1), // Templated
.dram_io_pad_clk_inv (dram_io_pad_clk_inv1), // Templated
.dram_io_channel_disabled(dram_io_channel_disabled1), // Templated
.dram_ucb_ack_vld (dram_ucb_ack_vld1), // Templated
.dram_ucb_nack_vld (dram_ucb_nack_vld1), // Templated
.dram_ucb_data (dram_ucb_data1[63:0]), // Templated
.l2if_err_intr (l2if_err_intr1), // Templated
.dram_local_pt_opened_bank(dram_local_pt1_opened_bank), // Templated
.que_max_banks_open_valid(que_max_banks_open_valid1), // Templated
.que_max_banks_open (que_max_banks_open1[16:0]), // Templated
.que_max_time_valid (que_max_time_valid1), // Templated
.dram_sctag_scb_mecc_err(dram_sctag1_scb_mecc_err), // Templated
.dram_sctag_scb_secc_err(dram_sctag1_scb_secc_err), // Templated
.que_int_pos (ch1_que_pos[4:0]), // Templated
.que_int_wr_que_inv_info(ch1_que_int_wr_que_inv_info[6:0]), // Templated
.que_ras_int_picked (ch1_que_ras_int_picked[7:0]), // Templated
.que_b0_data_addr (ch1_que_b0_data_addr[5:0]), // Templated
.que_l2req_valids (ch1_que_l2req_valids[7:0]), // Templated
.que_b0_addr_picked (ch1_que_b0_addr_picked[35:0]), // Templated
.que_b0_id_picked (ch1_que_b0_id_picked[2:0]), // Templated
.que_b0_index_picked (ch1_que_b0_index_picked[2:0]), // Templated
.que_b0_cmd_picked (ch1_que_b0_cmd_picked), // Templated
.que_channel_picked (ch1_que_channel_picked), // Templated
.dp_data_valid_d1 (ch1_dp_data_valid_d1), // Templated
.dram_data_val_other_ch(ch1_dram_data_val_other_ch), // Templated
.que_mem_data (ch1_que_mem_data[255:0]), // Templated
.dp_data_mecc0 (ch1_dp_data_mecc0[3:0]), // Templated
.dp_data_mecc1 (ch1_dp_data_mecc1[3:0]), // Templated
.dp_data_mecc2 (ch1_dp_data_mecc2[3:0]), // Templated
.dp_data_mecc3 (ch1_dp_data_mecc3[3:0]), // Templated
.dp_data_mecc4 (ch1_dp_data_mecc4[3:0]), // Templated
.dp_data_mecc5 (ch1_dp_data_mecc5[3:0]), // Templated
.dp_data_mecc6 (ch1_dp_data_mecc6[3:0]), // Templated
.dp_data_mecc7 (ch1_dp_data_mecc7[3:0]), // Templated
.err_syn (ch1_err_syn[15:0]), // Templated
.err_loc (ch1_err_loc[35:0]), // Templated
.que_channel_disabled (que1_channel_disabled), // Templated
.l2if_channel_disabled (l2if1_channel_disabled), // Templated
.listen_out (listen_out1[64:0]), // Templated
.que_cas_int_picked (ch1_que_cas_int_picked[7:0]), // Templated
.que_wr_cas_ch01_picked(ch1_que_wr_cas_ch01_picked), // Templated
.que_mux_write_en (ch1_que_mux_write_en), // Templated
// Inputs
.ucb_l2if_selfrsh (ucb_l2if_selfrsh),
.dram_dbginit_l (dbginit_l), // Templated
.sctag_dram_rd_req (sctag1_dram_rd_req), // Templated
.sctag_dram_rd_dummy_req(sctag1_dram_rd_dummy_req), // Templated
.sctag_dram_data_vld (scbuf1_dram_data_vld_r5), // Templated
.sctag_dram_rd_req_id (sctag1_dram_rd_req_id[2:0]), // Templated
.sctag_dram_addr (sctag1_dram_addr[39:5]), // Templated
.sctag_dram_wr_req (sctag1_dram_wr_req), // Templated
.sctag_dram_wr_data (scbuf1_dram_wr_data_r5[63:0]), // Templated
.sctag_dram_data_mecc (scbuf1_dram_data_mecc_r5), // Templated
.cmp_clk (cmp_rclk), // Templated
.dram_clk (dram_rclk), // Templated
.cmp_rst_l (cmp_rst_l), // Templated
.dram_rst_l (dram_rst_l), // Templated
.dram_arst_l (dram_arst_l), // Templated
.io_dram_data_valid (io_dram1_data_valid), // Templated
.io_dram_data_in (io_dram1_data_in[255:0]), // Templated
.io_dram_ecc_in (io_dram1_ecc_in[31:0]), // Templated
.ucb_dram_rd_req_vld (ucb_dram_rd_req_vld1), // Templated
.ucb_dram_wr_req_vld (ucb_dram_wr_req_vld1), // Templated
.ucb_dram_addr (ucb_dram_addr[31:0]), // Templated
.ucb_dram_data (ucb_dram_data[63:0]), // Templated
.pt_ch_blk_new_openbank(pt_ch1_blk_new_openbank), // Templated
.pt_max_banks_open (pt_max_banks_open[16:0]), // Templated
.pt_max_time (pt_max_time[15:0]), // Templated
.dram_dram_rx_sync (dram_dram_rx_sync), // Templated
.dram_dram_tx_sync (dram_dram_tx_sync), // Templated
.dram_jbus_rx_sync (dram_jbus_rx_sync), // Templated
.dram_jbus_tx_sync (dram_jbus_tx_sync), // Templated
.ch0_que_ras_int_picked(ch0_que_ras_int_picked[7:0]), // Templated
.ch0_que_b0_data_addr (ch0_que_b0_data_addr[5:0]), // Templated
.ch0_que_channel_picked(ch0_que_channel_picked), // Templated
.ch1_que_l2req_valids (ch0_que_l2req_valids[7:0]), // Templated
.ch1_que_b0_addr_picked(ch0_que_b0_addr_picked[35:0]), // Templated
.ch1_que_b0_id_picked (ch0_que_b0_id_picked[2:0]), // Templated
.ch1_que_b0_index_picked(ch0_que_b0_index_picked[2:0]), // Templated
.ch1_que_b0_cmd_picked (ch0_que_b0_cmd_picked), // Templated
.ch1_que_int_wr_que_inv_info(ch0_que_int_wr_que_inv_info[6:0]), // Templated
.other_que_pos (ch0_que_pos[4:0]), // Templated
.ch0_dram_data_val_other_ch(ch0_dram_data_val_other_ch), // Templated
.ch0_dram_sctag_chunk_id(dram_sctag0_chunk_id_r0[1:0]), // Templated
.ch0_dram_sctag_rd_req_id(dram_sctag0_rd_req_id_r0[2:0]), // Templated
.ch0_dram_sctag_data (dram_scbuf0_data_r2[127:0]), // Templated
.ch0_dram_sctag_ecc (dram_scbuf0_ecc_r2[27:0]), // Templated
.ch0_dram_sctag_mecc_err(dram_sctag0_mecc_err_r2), // Templated
.ch0_dram_sctag_pa_err (dram_sctag0_pa_err_r2), // Templated
.ch0_dram_sctag_secc_err(dram_sctag0_secc_err_r2), // Templated
.ch0_dp_data_valid_d1 (ch0_dp_data_valid_d1), // Templated
.ch0_err_syn (ch0_err_syn[15:0]), // Templated
.ch0_err_loc (ch0_err_loc[35:0]), // Templated
.ch1_que_mem_data (ch0_que_mem_data[255:0]), // Templated
.ch1_dp_data_mecc0 (ch0_dp_data_mecc0[3:0]), // Templated
.ch1_dp_data_mecc1 (ch0_dp_data_mecc1[3:0]), // Templated
.ch1_dp_data_mecc2 (ch0_dp_data_mecc2[3:0]), // Templated
.ch1_dp_data_mecc3 (ch0_dp_data_mecc3[3:0]), // Templated
.ch1_dp_data_mecc4 (ch0_dp_data_mecc4[3:0]), // Templated
.ch1_dp_data_mecc5 (ch0_dp_data_mecc5[3:0]), // Templated
.ch1_dp_data_mecc6 (ch0_dp_data_mecc6[3:0]), // Templated
.ch1_dp_data_mecc7 (ch0_dp_data_mecc7[3:0]), // Templated
.other_channel_disabled(l2if0_channel_disabled), // Templated
.other_que_channel_disabled(que0_channel_disabled), // Templated
.sehold (sehold), // Templated
.mem_bypass (mem_bypass), // Templated
.ch0_que_cas_int_picked(ch0_que_cas_int_picked[7:0]), // Templated
.ch0_que_wr_cas_ch01_picked(ch0_que_wr_cas_ch01_picked), // Templated
.ch0_que_mux_write_en (ch0_que_mux_write_en)); // Templated
/*****************************************************************
* Power throttle logic block
****************************************************************/
/*dram_pt AUTO_TEMPLATE( .clk(dram_rclk),
.rst_l(dram_rst_l)); */
dram_pt dram_pt(/*AUTOINST*/
// Outputs
.pt_ch0_blk_new_openbank(pt_ch0_blk_new_openbank),
.pt_ch1_blk_new_openbank(pt_ch1_blk_new_openbank),
.pt_max_banks_open (pt_max_banks_open[16:0]),
.pt_max_time (pt_max_time[15:0]),
.dram_pt_max_banks_open_valid(dram_pt_max_banks_open_valid),
.dram_pt_max_time_valid (dram_pt_max_time_valid),
.dram_pt_ucb_data (dram_pt_ucb_data[16:0]),
// Inputs
.clk (dram_rclk), // Templated
.rst_l (dram_rst_l), // Templated
.arst_l (dram_arst_l), // Templated
.dram_local_pt0_opened_bank(dram_local_pt0_opened_bank),
.dram_local_pt1_opened_bank(dram_local_pt1_opened_bank),
.dram_other_pt0_opened_bank(dram_other_pt0_opened_bank),
.dram_other_pt1_opened_bank(dram_other_pt1_opened_bank),
.que_max_banks_open_valid0(que_max_banks_open_valid0),
.que_max_banks_open_valid1(que_max_banks_open_valid1),
.que_max_banks_open0 (que_max_banks_open0[16:0]),
.que_max_banks_open1 (que_max_banks_open1[16:0]),
.que_max_time_valid0 (que_max_time_valid0),
.que_max_time_valid1 (que_max_time_valid1),
.dram_other_pt_max_banks_open_valid(dram_other_pt_max_banks_open_valid),
.dram_other_pt_max_time_valid(dram_other_pt_max_time_valid),
.dram_other_pt_ucb_data (dram_other_pt_ucb_data[16:0]));
/*****************************************************************
* UCB logic block for I/O Reads and Writes
****************************************************************/
/*dram_ucb AUTO_TEMPLATE( .clk(jbus_rclk),
.ddr_clk_tr(dram_clk_tr),
.rst_l(jbus_rst_l)); */
dram_ucb dram_ucb(/*AUTOINST*/
// Outputs
.ucb_dram_rd_req_vld0 (ucb_dram_rd_req_vld0),
.ucb_dram_rd_req_vld1 (ucb_dram_rd_req_vld1),
.ucb_dram_wr_req_vld0 (ucb_dram_wr_req_vld0),
.ucb_dram_wr_req_vld1 (ucb_dram_wr_req_vld1),
.ucb_dram_addr (ucb_dram_addr[31:0]),
.ucb_dram_data (ucb_dram_data[63:0]),
.ucb_iob_data (ucb_iob_data[3:0]),
.ucb_iob_stall (ucb_iob_stall),
.ucb_iob_vld (ucb_iob_vld),
.ddr_clk_tr (dram_clk_tr), // Templated
.ucb_l2if_selfrsh (ucb_l2if_selfrsh),
// Inputs
.clk (jbus_rclk), // Templated
.rst_l (jbus_rst_l), // Templated
.clspine_dram_selfrsh (clspine_dram_selfrsh),
.iob_ucb_data (iob_ucb_data[3:0]),
.iob_ucb_stall (iob_ucb_stall),
.iob_ucb_vld (iob_ucb_vld),
.dram_ucb_ack_vld0 (dram_ucb_ack_vld0),
.dram_ucb_ack_vld1 (dram_ucb_ack_vld1),
.dram_ucb_nack_vld0 (dram_ucb_nack_vld0),
.dram_ucb_nack_vld1 (dram_ucb_nack_vld1),
.dram_ucb_data0 (dram_ucb_data0[63:0]),
.dram_ucb_data1 (dram_ucb_data1[63:0]),
.l2if_err_intr0 (l2if_err_intr0),
.l2if_err_intr1 (l2if_err_intr1),
.l2if_ucb_trig0 (l2if_ucb_trig0),
.l2if_ucb_trig1 (l2if_ucb_trig1));
endmodule // dram
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// End:
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_arbdecdp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// change ( 6/12/2003 ).
// Input arbdp_word_addr_c7 has changed to arbdp_byte_addr_c6
// sctag_scbuf_ctag_c7 logic has moved to C6. The new
// output is called arbdec_ctag_c6;
// Comments
// Change 4/10/2003: Added one pin arbdp_rdma_inst_c1 to the left.
//
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "iop.h"
`include "sctag.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local define
////////////////////////////////////////////////////////////////////////
module sctag_arbdecdp( /*AUTOARG*/
// Outputs
so, arbdp_inst_c8, arbdp_inst_way_c1, arbdp_tecc_c1,
arbdp_poison_c1, arbdp_inst_mb_entry_c1, arbdp_inst_fb_c1,
arbdp_inst_mb_c1, arbdp_evict_c1, arbdp_inst_rqtyp_c1,
arbdp_inst_rsvd_c1, arbdp_inst_nc_c1, arbdp_inst_size_c1,
arbdp_inst_bufidhi_c1, arbdp_inst_bufid1_c1, arbdp_inst_ctrue_c1,
arbdp_inst_fb_c2, arbdp_inst_mb_c2, arbdp_rdma_entry_c3,
arbdp_rdma_inst_c1, arbdp_rdma_inst_c2, arbdp_inst_dep_c2,
arbdp_inst_way_c2, arbdp_inst_rqtyp_c2, arbdp_inst_bufidlo_c2,
arbdp_inst_rqtyp_c6, arbdp_inst_way_c3, arbdp_inst_fb_c3,
arbdp_inst_mb_c3, arbdp_inst_tecc_c3, arbdp_inst_nc_c3,
arbdp_l1way_c3, arbdec_dbgdp_inst_c3, arbdp_cpuid_c3,
arbdp_cpuid_c4, arbdp_cpuid_c5, arbdp_cpuid_c6,
arbdp_int_bcast_c5, arbdp_inst_l1way_c7, arbdp_inst_size_c7,
arbdp_inst_tid_c7, arbdp_inst_cpuid_c7, arbdp_inst_nc_c7,
arbdec_ctag_c6, arbdp_async_bit_c8, size_field_c8,
// Inputs
snpq_arbdp_inst_px2, iq_arbdp_inst_px2, mb_data_read_data,
mbctl_arbdp_ctrue_px2, mbctl_arb_l2rd_en, fbctl_arbdp_entry_px2,
fbctl_arbdp_tecc_px2, l2_steering_tid, fbctl_arbdp_way_px2,
mux1_mbsel_px2, mux2_snpsel_px2, mux3_bufsel_px2, mux4_c1sel_px2,
prim_req_c3, write_req_c3, atomic_req_c3, si, se, rclk,
arbdp_byte_addr_c6
);
// snp IQ instruction fields
input [`JBI_HDR_SZ-1:0] snpq_arbdp_inst_px2; // grown by 1 bit since 2.0
// IQ instruction fields
input [18:0] iq_arbdp_inst_px2 ; // from iq ( no valid bit required )
// Miss buffer instruction fields
input [`MBD_EVICT:`MBD_SZ_LO] mb_data_read_data ; // grown by 1 bit since 2.0
input mbctl_arbdp_ctrue_px2;
input mbctl_arb_l2rd_en ; // from mbctl
// Fill buffer instruction fields
input [2:0] fbctl_arbdp_entry_px2;
input fbctl_arbdp_tecc_px2;
input [4:0] l2_steering_tid;
input [3:0] fbctl_arbdp_way_px2;
input mux1_mbsel_px2; // arbctl
input mux2_snpsel_px2; // arbctl
input mux3_bufsel_px2; // arbctl
input mux4_c1sel_px2; // arbctl
input prim_req_c3, write_req_c3, atomic_req_c3 ; // NEW_PIN
input si, se;
input rclk;
input [1:0] arbdp_byte_addr_c6; // from arbaddr
output so;
output [`L2_POISON:`L2_SZ_LO] arbdp_inst_c8; // to mbdata.
output [3:0] arbdp_inst_way_c1;
output arbdp_tecc_c1 ; // used in arbctl for waysel gate
output arbdp_poison_c1; // NEW_PIN to arbdata
output [3:0] arbdp_inst_mb_entry_c1; // Miss Buffer entry to mbctl
output arbdp_inst_fb_c1 ; // used by arbctl to turn off fb hits.
output arbdp_inst_mb_c1 ; // used by arbctl to turn off fb hits.
output arbdp_evict_c1; // unqualled evict to arbctl
output [`L2_RQTYP_HI:`L2_RQTYP_LO] arbdp_inst_rqtyp_c1 ; // NEW_PIN decode
output arbdp_inst_rsvd_c1; // NEW_PIN decode
output arbdp_inst_nc_c1 ; // NEW_PIN decode
output [`L2_SZ_HI:`L2_SZ_LO] arbdp_inst_size_c1; // NEW_PIN decode
output arbdp_inst_bufidhi_c1;
output arbdp_inst_bufid1_c1; // buf_id hi-1
output arbdp_inst_ctrue_c1;
output arbdp_inst_fb_c2; // output to arbctl for
// generation of scdata wrdata mux sel.
output arbdp_inst_mb_c2;
output [1:0] arbdp_rdma_entry_c3;
output arbdp_rdma_inst_c1; // used in mbctl,fbctl,tagctl.
output arbdp_rdma_inst_c2; // used in arbctl.
output arbdp_inst_dep_c2; // to arbctl for dir cam logic
output [3:0] arbdp_inst_way_c2; // used in vuad dp.v
output [`L2_RQTYP_HI:`L2_RQTYP_LO] arbdp_inst_rqtyp_c2 ; // NEW_PIN decode
output arbdp_inst_bufidlo_c2 ; // NEW_PIN decode
output [`L2_RQTYP_HI:`L2_RQTYP_LO] arbdp_inst_rqtyp_c6 ;
output [3:0] arbdp_inst_way_c3; // used in tagctl.v
output arbdp_inst_fb_c3;
output arbdp_inst_mb_c3;
output arbdp_inst_tecc_c3;
output arbdp_inst_nc_c3; // L1 non allocating instruction
output [1:0] arbdp_l1way_c3; // l1 replacement way.
output [8:0] arbdec_dbgdp_inst_c3; // ro dbgdp
output [2:0] arbdp_cpuid_c3;
output [2:0] arbdp_cpuid_c4;
output [2:0] arbdp_cpuid_c5, arbdp_cpuid_c6;
output arbdp_int_bcast_c5; // to oqctl.
output [1:0] arbdp_inst_l1way_c7; // to oqdp
output [2:0] arbdp_inst_size_c7; // to oqdp
output [1:0] arbdp_inst_tid_c7; // to oqdp
output [2:0] arbdp_inst_cpuid_c7; // to oqdp
output arbdp_inst_nc_c7; // to oqdp
output [14:0] arbdec_ctag_c6; // to SCBUF
output arbdp_async_bit_c8; // To CSR NEW_PIN
output [1:0] size_field_c8; // used for CAS instructions compare qualification
wire [`L2_FBF:`L2_SZ_LO] snpq_inst_px2;
wire [`L2_FBF:`L2_SZ_LO] iq_inst_px2;
wire [`L2_FBF:`L2_SZ_LO] fbf_inst_px2;
wire [`L2_FBF:`L2_SZ_LO] mbf_inst_px2;
wire [`L2_FBF:`L2_SZ_LO] mux1_inst_px2;
wire [`L2_FBF:`L2_SZ_LO] mux2_inst_px2;
wire [`L2_FBF:`L2_SZ_LO] mux3_inst_px2;
wire [`L2_FBF:`L2_SZ_LO] mux4_inst_px2;
wire [`L2_FBF:`L2_SZ_LO] arbdp_inst_c1;
wire [`L2_FBF:`L2_SZ_LO] arbdp_inst_c2;
wire [`L2_FBF:`L2_SZ_LO] arbdp_inst_c3;
wire [`L2_POISON:`L2_SZ_LO] arbdp_inst_c4;
wire [`L2_POISON:`L2_SZ_LO] arbdp_inst_c5;
wire [`L2_POISON:`L2_SZ_LO] arbdp_inst_c6;
wire [`L2_POISON:`L2_SZ_LO] arbdp_inst_c7;
wire clk_0;
//////////////////////////////////////////////////////////////////////////////////////
// INSTRUCTION FIELDS MBF FBF SNP IQ/PCX
//////////////////////////////////////////////////////////////////////////////////////
// L2_FBF 0 1 0 0
// L2_MBF 1 0 0 0
// L2_SNP 0 0 1 0
// L2_CTRUE V 0 0 0
// L2_EVICT V 0 0 0
// L2_DEP V 0 0 0
// L2_TECC V V 0 0
// L2_ENTRY<3:0> mbid fbid
// L2_POISON 0 0 V 0
// L2_RDMA<1:0> V 0 V 0
// L2_RQTYP<4:0> V** 1F ctag<11:10>.V<2:0> V
// L2_NC V 0 0 V
// L2_RSVD 0 0 1 0
// L2_CPUID<2:0> V** 0*** ctag<9:7> V
// L2_TID<1:0> V 0*** ctag<6:5> V
// L2_BUFID<2:0> rsvd X ctag<4:2> rsvd
// L2_L1WY<1:0> V X ctag<1:0> V
// L2_SZ_HI<2:0> V X V V
//////////////////////////////////////////////////////////////////////////////////////
// snoop instuction.
assign snpq_inst_px2[`L2_FBF] = 1'b0 ;
assign snpq_inst_px2[`L2_MBF] = 1'b0 ;
assign snpq_inst_px2[`L2_SNP] = 1'b1 ; // currently this bit is RSVD
assign snpq_inst_px2[`L2_CTRUE] = 1'b0 ;
assign snpq_inst_px2[`L2_EVICT] = 1'b0;
assign snpq_inst_px2[`L2_DEP] = 1'b0 ;
assign snpq_inst_px2[`L2_TECC] = 1'b0 ;
assign snpq_inst_px2[`L2_POISON] = snpq_arbdp_inst_px2[`JBINST_POISON];
assign snpq_inst_px2[`L2_ENTRY_HI:`L2_ENTRY_LO] = 4'b0 ;
assign snpq_inst_px2[`L2_RDMA_HI:`L2_RDMA_LO] = {
snpq_arbdp_inst_px2[`JBINST_ENTRY_HI:`JBINST_ENTRY_LO] } ;
assign snpq_inst_px2[`L2_RQTYP_HI:`L2_RQTYP_LO] =
{
snpq_arbdp_inst_px2[`JBINST_CTAG_HI:`JBINST_CTAG_HI-1],
snpq_arbdp_inst_px2[`JBINST_RQ_WR64:`JBINST_RQ_RD]
} ;
assign snpq_inst_px2[`L2_NC] = 1'b0 ;
assign snpq_inst_px2[`L2_RSVD] = snpq_arbdp_inst_px2[`JBINST_RSVD]; // Changed POST_4.0
assign snpq_inst_px2[`L2_CPUID_HI:`L2_CPUID_LO] =
{ snpq_arbdp_inst_px2[`JBINST_CTAG_HI-2:`JBINST_CTAG_HI-4]};
assign snpq_inst_px2[`L2_TID_HI:`L2_TID_LO] =
{ snpq_arbdp_inst_px2[`JBINST_CTAG_HI-5:`JBINST_CTAG_HI-6]};
assign snpq_inst_px2[`L2_BUFID_HI:`L2_BUFID_LO] =
{ snpq_arbdp_inst_px2[`JBINST_CTAG_HI-7:`JBINST_CTAG_HI-9]};
assign snpq_inst_px2[`L2_L1WY_HI:`L2_L1WY_LO] =
{ snpq_arbdp_inst_px2[`JBINST_CTAG_HI-10:`JBINST_CTAG_HI-11]};
assign snpq_inst_px2[`L2_SZ_HI:`L2_SZ_LO] =
snpq_arbdp_inst_px2[`JBINST_SZ_HI:`JBINST_SZ_LO];
//**********************
// iq instuction.
//**********************
// inst bits 30:20
assign iq_inst_px2[`L2_FBF:`L2_ENTRY_LO] = 11'b0 ;
assign iq_inst_px2[`L2_POISON] = 1'b0 ;
assign iq_inst_px2[`L2_RDMA_HI:`L2_RDMA_LO] = 2'b0;
// inst bits 19:0
assign iq_inst_px2[`L2_RQTYP_HI:`L2_SZ_LO] =
{iq_arbdp_inst_px2[18:13],
1'b0, // RSVD bit
iq_arbdp_inst_px2[`L2_CPUID_HI:`L2_SZ_LO]} ;
//**********************
// fill buffer instuction.
//**********************
// inst bits 30:20
assign fbf_inst_px2[`L2_FBF] = 1'b1 ;
assign fbf_inst_px2[`L2_MBF] = 1'b0 ;
assign fbf_inst_px2[`L2_SNP] = 1'b0 ;
assign fbf_inst_px2[`L2_RSVD] = 1'b0 ;
assign fbf_inst_px2[`L2_CTRUE] = 1'b0 ;
assign fbf_inst_px2[`L2_EVICT] = 1'b0;
assign fbf_inst_px2[`L2_DEP] = 1'b0 ;
assign fbf_inst_px2[`L2_TECC] = fbctl_arbdp_tecc_px2 ;
assign fbf_inst_px2[`L2_ENTRY_HI:`L2_ENTRY_LO] = { 1'b0 , fbctl_arbdp_entry_px2[2:0] } ;
// inst bits 19:0
assign fbf_inst_px2[`L2_POISON] = 1'b0;
assign fbf_inst_px2[`L2_RDMA_HI:`L2_RDMA_LO] = 2'b0;
assign fbf_inst_px2[`L2_RQTYP_HI:`L2_RQTYP_LO] = 5'b11111;
assign fbf_inst_px2[`L2_NC] = 1'b0 ;
assign fbf_inst_px2[`L2_RSVD] = 1'b0 ;
assign fbf_inst_px2[`L2_CPUID_HI:`L2_CPUID_LO] = l2_steering_tid[4:2];
assign fbf_inst_px2[`L2_TID_HI:`L2_TID_LO] = l2_steering_tid[1:0];
assign fbf_inst_px2[`L2_BUFID_HI:`L2_BUFID_HI-3] = fbctl_arbdp_way_px2[3:0] ;
assign fbf_inst_px2[`L2_BUFID_HI-4:`L2_SZ_LO] = 4'b0 ;
//**********************
// miss buffer instuction.
//**********************
assign mbf_inst_px2[`L2_FBF] = 1'b0 ;
assign mbf_inst_px2[`L2_MBF] = 1'b1 ;
assign mbf_inst_px2[`L2_SNP] = 1'b0 ;
assign mbf_inst_px2[`L2_CTRUE] = mbctl_arbdp_ctrue_px2;
// dffe #(7) ff_read_mbdata_reg_inst1
// (.din(mb_data_read_data[`MBD_EVICT:`MBD_ENTRY_LO]),
// .clk(rclk), .en(mbctl_arb_l2rd_en),
// .q(mbf_inst_px2[`L2_EVICT:`L2_ENTRY_LO]), .se(se), .si(), .so());
//
// dffe #(23) ff_read_mbdata_reg_inst2
// (.din(mb_data_read_data[`MBD_POISON:`MBD_SZ_LO]),
// .clk(rclk), .en(mbctl_arb_l2rd_en),
// .q(mbf_inst_px2[`L2_POISON:`L2_SZ_LO]), .se(se), .si(), .so());
clken_buf ckbuf_0 (.clk(clk_0), .rclk(rclk), .enb_l(~mbctl_arb_l2rd_en), .tmb_l(~se));
dff_s #(7) ff_read_mbdata_reg_inst1
(.din(mb_data_read_data[`MBD_EVICT:`MBD_ENTRY_LO]),
.clk(clk_0),
.q(mbf_inst_px2[`L2_EVICT:`L2_ENTRY_LO]), .se(se), .si(), .so());
dff_s #(23) ff_read_mbdata_reg_inst2
(.din(mb_data_read_data[`MBD_POISON:`MBD_SZ_LO]),
.clk(clk_0),
.q(mbf_inst_px2[`L2_POISON:`L2_SZ_LO]), .se(se), .si(), .so());
//************************
// arbiter muxes
// arbiter is split into two rows
// The first row contains 11 bits. The second row contains 20 bits.
//************************
mux2ds #(11) mux_mux1_inst1_px2 (.dout (mux1_inst_px2[`L2_FBF:`L2_ENTRY_LO]) ,
.in0(mbf_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // mbf inst 30:20
.in1(fbf_inst_px2[`L2_FBF:`L2_ENTRY_LO] ), // fbf inst 30:20
.sel0(mux1_mbsel_px2), .sel1(~mux1_mbsel_px2)) ;
mux2ds #(23) mux_mux1_inst2_px2 (.dout (mux1_inst_px2[`L2_POISON:`L2_SZ_LO]) ,
.in0(mbf_inst_px2[`L2_POISON:`L2_SZ_LO]), // mbf inst 19:0
.in1(fbf_inst_px2[`L2_POISON:`L2_SZ_LO] ), // fbf inst 19:0
.sel0(mux1_mbsel_px2), .sel1(~mux1_mbsel_px2)) ;
mux2ds #(11) mux_mux2_inst1_px2(.dout (mux2_inst_px2[`L2_FBF:`L2_ENTRY_LO]) ,
.in0(snpq_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // snoop
.in1(mux1_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // fbf/mbf instuction 30:20
.sel0(mux2_snpsel_px2), .sel1(~mux2_snpsel_px2));
mux2ds #(23) mux_mux2_inst2_px2 (.dout (mux2_inst_px2[`L2_POISON:`L2_SZ_LO]) ,
.in0(snpq_inst_px2[`L2_POISON:`L2_SZ_LO]), // snoop inst 19:0
.in1(mux1_inst_px2[`L2_POISON:`L2_SZ_LO] ), // fbf/mbf inst 19:0
.sel0(mux2_snpsel_px2), .sel1(~mux2_snpsel_px2)) ;
mux2ds #(11) mux_mux3_inst1_px2(.dout (mux3_inst_px2[`L2_FBF:`L2_ENTRY_LO]) ,
.in0(mux2_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // snoop and mbf and fbf
.in1(iq_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // iq instuction 30:20
.sel0(mux3_bufsel_px2), .sel1(~mux3_bufsel_px2));
mux2ds #(23) mux_mux3_inst2_px2 (.dout (mux3_inst_px2[`L2_POISON:`L2_SZ_LO]) ,
.in0(mux2_inst_px2[`L2_POISON:`L2_SZ_LO]), // snoop and mbf and fbf
.in1(iq_inst_px2[`L2_POISON:`L2_SZ_LO] ), // iq inst 19:0
.sel0(mux3_bufsel_px2), .sel1(~mux3_bufsel_px2)) ;
// a mux flop cannot be used here.
mux2ds #(11) mux_mux4_inst1_px2(.dout (mux4_inst_px2[`L2_FBF:`L2_ENTRY_LO]) ,
.in0(mux3_inst_px2[`L2_FBF:`L2_ENTRY_LO]), // snoop and mbf and fbf and iq
.in1(arbdp_inst_c1[`L2_FBF:`L2_ENTRY_LO]), // c1 instuction 30:20
.sel0(~mux4_c1sel_px2), .sel1(mux4_c1sel_px2));
mux2ds #(23) mux_mux4_inst2_px2 (.dout (mux4_inst_px2[`L2_POISON:`L2_SZ_LO]) ,
.in0(mux3_inst_px2[`L2_POISON:`L2_SZ_LO]), // snoop and mbf and fbf and iq
.in1(arbdp_inst_c1[`L2_POISON:`L2_SZ_LO] ), // c1 inst 19:0
.sel0(~mux4_c1sel_px2), .sel1(mux4_c1sel_px2)) ;
dff_s #(11) ff_inst1_c1 (.din(mux4_inst_px2[`L2_FBF:`L2_ENTRY_LO]),
.clk(rclk),
.q(arbdp_inst_c1[`L2_FBF:`L2_ENTRY_LO]),
.se(se), .si(), .so());
dff_s #(11) ff_inst1_c2 (.din(arbdp_inst_c1[`L2_FBF:`L2_ENTRY_LO]),
.clk(rclk),
.q(arbdp_inst_c2[`L2_FBF:`L2_ENTRY_LO]),
.se(se), .si(), .so());
dff_s #(11) ff_inst1_c3 (.din(arbdp_inst_c2[`L2_FBF:`L2_ENTRY_LO]),
.clk(rclk),
.q(arbdp_inst_c3[`L2_FBF:`L2_ENTRY_LO]),
.se(se), .si(), .so());
dff_s #(23) ff_inst2_c1 (.din(mux4_inst_px2[`L2_POISON:`L2_SZ_LO]),
.clk(rclk),
.q(arbdp_inst_c1[`L2_POISON:`L2_SZ_LO]),
.se(se), .si(), .so());
dff_s #(23) ff_inst2_c2 (.din(arbdp_inst_c1[`L2_POISON:`L2_SZ_LO]),
.clk(rclk),
.q(arbdp_inst_c2[`L2_POISON:`L2_SZ_LO]),
.se(se), .si(), .so());
dff_s #(23) ff_inst2_c3 (.din(arbdp_inst_c2[`L2_POISON:`L2_SZ_LO]),
.clk(rclk),
.q(arbdp_inst_c3[`L2_POISON:`L2_SZ_LO]),
.se(se), .si(), .so());
dff_s #(23) ff_inst2_c4 (.din(arbdp_inst_c3[`L2_POISON:`L2_SZ_LO]),
.clk(rclk),
.q(arbdp_inst_c4[`L2_POISON:`L2_SZ_LO]),
.se(se), .si(), .so());
dff_s #(23) ff_inst2_c5 (.din(arbdp_inst_c4[`L2_POISON:`L2_SZ_LO]),
.clk(rclk),
.q(arbdp_inst_c5[`L2_POISON:`L2_SZ_LO]),
.se(se), .si(), .so());
dff_s #(23) ff_inst2_c6 (.din(arbdp_inst_c5[`L2_POISON:`L2_SZ_LO]),
.clk(rclk),
.q(arbdp_inst_c6[`L2_POISON:`L2_SZ_LO]),
.se(se), .si(), .so());
dff_s #(23) ff_inst2_c7 (.din(arbdp_inst_c6[`L2_POISON:`L2_SZ_LO]),
.clk(rclk),
.q(arbdp_inst_c7[`L2_POISON:`L2_SZ_LO]),
.se(se), .si(), .so());
dff_s #(23) ff_inst2_c8 (.din(arbdp_inst_c7[`L2_POISON:`L2_SZ_LO]),
.clk(rclk),
.q(arbdp_inst_c8[`L2_POISON:`L2_SZ_LO]),
.se(se), .si(), .so());
//////////////////////////////////////////////////////
// C1 Bits used in decode
//////////////////////////////////////////////////////
assign arbdp_poison_c1 = arbdp_inst_c1[`L2_POISON];
assign arbdp_inst_way_c1 = arbdp_inst_c1[`L2_BUFID_HI:`L2_BUFID_HI-3] ;
assign arbdp_inst_fb_c1 = arbdp_inst_c1[`L2_FBF] ; // used by
// arbctl to turn off fb hits.
assign arbdp_evict_c1 = arbdp_inst_c1[`L2_EVICT] ;
assign arbdp_tecc_c1 = arbdp_inst_c1[`L2_TECC] ;
assign arbdp_inst_mb_c1 = arbdp_inst_c1[`L2_MBF] ;
assign arbdp_inst_rsvd_c1 = arbdp_inst_c1[`L2_RSVD] ;
assign arbdp_inst_nc_c1 = arbdp_inst_c1[`L2_NC] ;
assign arbdp_inst_ctrue_c1 = arbdp_inst_c1[`L2_CTRUE] ;
assign arbdp_inst_size_c1[`L2_SZ_HI:`L2_SZ_LO] =
arbdp_inst_c1[`L2_SZ_HI:`L2_SZ_LO];
assign arbdp_inst_bufidhi_c1 = arbdp_inst_c1[`L2_BUFID_HI] ;
assign arbdp_inst_bufid1_c1 = arbdp_inst_c1[`L2_BUFID_HI-1];
assign arbdp_inst_rqtyp_c1 = arbdp_inst_c1[`L2_RQTYP_HI:`L2_RQTYP_LO] ;
assign arbdp_inst_mb_entry_c1 = arbdp_inst_c1[`L2_ENTRY_HI:`L2_ENTRY_LO] ;
assign arbdp_rdma_inst_c1 = arbdp_inst_c1[`L2_RSVD] ;
//////////////////////////////////////////////////////
// C2 Bits used in decode
//////////////////////////////////////////////////////
assign arbdp_inst_bufidlo_c2 = arbdp_inst_c2[`L2_BUFID_LO] ;
assign arbdp_inst_mb_c2 = arbdp_inst_c2[`L2_MBF] ; // used in vuad dp, arbctl
assign arbdp_inst_fb_c2 = arbdp_inst_c2[`L2_FBF] ; // fill instruction in C2.
// output to arbctl and vuad dp.
assign arbdp_inst_dep_c2 = arbdp_inst_c2[`L2_DEP];
assign arbdp_rdma_inst_c2 = arbdp_inst_c2[`L2_RSVD] ;
assign arbdp_inst_rqtyp_c2 = arbdp_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] ;
assign arbdp_inst_way_c2 = arbdp_inst_c2[`L2_BUFID_HI:`L2_BUFID_HI-3] ;
//////////////////////////////////////////////////////
// C3 Bits used in decode
//////////////////////////////////////////////////////
assign arbdp_inst_mb_c3 = arbdp_inst_c3[`L2_MBF] ;
assign arbdp_inst_fb_c3 = arbdp_inst_c3[`L2_FBF] ;
assign arbdp_inst_tecc_c3 = arbdp_inst_c3[`L2_TECC];
assign arbdp_inst_way_c3 = arbdp_inst_c3[`L2_BUFID_HI:`L2_BUFID_HI-3] ;
assign arbdp_rdma_entry_c3 = arbdp_inst_c3[`L2_RDMA_HI:`L2_RDMA_LO] ;
assign arbdp_inst_nc_c3 = arbdp_inst_c3[`L2_NC] ;
assign arbdp_l1way_c3 = arbdp_inst_c3[`L2_L1WY_HI:`L2_L1WY_LO] ;
//////////////////////////////////////////////////////
// C5+ Bits used in decode
//////////////////////////////////////////////////////
assign arbdp_int_bcast_c5 = arbdp_inst_c5[`L2_NC] ;
assign arbdp_inst_rqtyp_c6 = arbdp_inst_c6[`L2_RQTYP_HI:`L2_RQTYP_LO] ;
//////////////////////////////////////////////////////
// CTAG sent to scbuf
// Ctag<14:0> = { addr_c7<1:0>, r/wbar, ctag<11:0> }
//////////////////////////////////////////////////////
assign arbdec_ctag_c6[14:0] = { arbdp_byte_addr_c6[1:0],
arbdp_inst_c6[`L2_RQTYP_LO], // rd
arbdp_inst_c6[`L2_RQTYP_HI:`L2_RQTYP_HI-1], // ctag 11:10
arbdp_inst_c6[`L2_CPUID_HI:`L2_L1WY_LO] } ;
// Fields that go to oqdp for return to the
// sparcs
assign arbdp_inst_l1way_c7 = arbdp_inst_c7[`L2_L1WY_HI:`L2_L1WY_LO] ;
assign arbdp_inst_size_c7 = arbdp_inst_c7[`L2_SZ_HI:`L2_SZ_LO] ;
assign arbdp_inst_tid_c7 = arbdp_inst_c7[`L2_TID_HI:`L2_TID_LO] ;
assign arbdp_inst_cpuid_c7 = arbdp_inst_c7[`L2_CPUID_HI:`L2_CPUID_LO] ;
assign arbdp_inst_nc_c7 = arbdp_inst_c7[`L2_NC] ;
// to arbctl for determining if an instruction
// is a CAS or CASX.
assign size_field_c8[1:0]= arbdp_inst_c8[`L2_SZ_HI-1:`L2_SZ_LO] ;
assign arbdp_async_bit_c8 = arbdp_inst_c8[`L2_SZ_HI] ;
// cpu id in C3,C4,C5,C6 to arbctl for
// directory invalidation mask calculation.
// C6 and C7 cpuid are used in direvec_ctl for
// dirvec_dp mux selects
assign arbdp_cpuid_c3 = arbdp_inst_c3[`L2_CPUID_HI:`L2_CPUID_LO] ;
assign arbdp_cpuid_c4 = arbdp_inst_c4[`L2_CPUID_HI:`L2_CPUID_LO] ;
assign arbdp_cpuid_c5 = arbdp_inst_c5[`L2_CPUID_HI:`L2_CPUID_LO] ;
assign arbdp_cpuid_c6 = arbdp_inst_c6[`L2_CPUID_HI:`L2_CPUID_LO] ;
// dbg information sent to dbgdp
// { JBI instruction
// Primary request
// Write ( store, strmstore, wr64, wr8 )
// Atomic ( cas or swap )
// cpuid<2:0>,
// tid }
assign arbdec_dbgdp_inst_c3 = { arbdp_inst_c3[`L2_RSVD], // JBI instruction bit
prim_req_c3, // PRIM req from JBI/PCX interface
write_req_c3, // Any write
atomic_req_c3, // SWAP/CAS
arbdp_inst_c3[`L2_CPUID_HI:`L2_CPUID_LO], // CPUID
arbdp_inst_c3[`L2_TID_HI:`L2_TID_LO] // TID
} ;
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND2_BLACKBOX_V
`define SKY130_FD_SC_HS__TAPVGND2_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND2_BLACKBOX_V
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////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// pipeline_registers.v
// Created: 4.4.2012
// Modified: 4.4.2012
//
// Implements a series of pipeline registers specified by the input
// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the
// size of the signal passed through each of the pipeline
// registers. NUMBER_OF_STAGES is the number of pipeline registers
// generated. This accepts values of 0 (yes, it just passes data from
// input to output...) up to however many stages specified.
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule
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