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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_PP_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
hdmi_rx_clk,
hdmi_rx_data,
hdmi_rx_int,
hdmi_tx_clk,
hdmi_tx_data,
hdmi_tx_spdif,
hdmi_iic_scl,
hdmi_iic_sda,
hdmi_iic_rstn);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input hdmi_rx_clk;
input [15:0] hdmi_rx_data;
inout hdmi_rx_int;
output hdmi_tx_clk;
output [15:0] hdmi_tx_data;
output hdmi_tx_spdif;
inout hdmi_iic_rstn;
inout hdmi_iic_scl;
inout hdmi_iic_sda;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// base hdmi
assign hdmi_out_clk = 1'd0;
assign hdmi_vsync = 1'd0;
assign hdmi_hsync = 1'd0;
assign hdmi_data_e = 1'd0;
assign hdmi_data = 24'd0;
assign spdif = 1'd0;
// instantiations
ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi_iic_rstn (
.dio_t (gpio_t[33]),
.dio_i (gpio_o[33]),
.dio_o (gpio_i[33]),
.dio_p (hdmi_iic_rstn));
ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi (
.dio_t (gpio_t[32]),
.dio_i (gpio_o[32]),
.dio_o (gpio_i[32]),
.dio_p (hdmi_rx_int));
ad_iobuf #(.DATA_WIDTH(15)) i_gpio_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (),
.hdmi_data_e (),
.hdmi_es_data (hdmi_tx_data),
.hdmi_hsync (),
.hdmi_out_clk (hdmi_tx_clk),
.hdmi_rx_clk (hdmi_rx_clk),
.hdmi_rx_data (hdmi_rx_data),
.hdmi_vsync (),
.iic_imageon_scl_io (hdmi_iic_scl),
.iic_imageon_sda_io (hdmi_iic_sda),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_13 (1'b0),
.spdif (hdmi_tx_spdif),
.spi0_clk_i (1'b0),
.spi0_clk_o (),
.spi0_csn_0_o (),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b0),
.spi0_sdi_i (1'b0),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b0),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o ());
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSTP_1_V
`define SKY130_FD_SC_HD__DFSTP_1_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfstp_1 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfstp_1 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSTP_1_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 7
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_7_top,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_auto_us_df_0,axi_dwidth_converter_v2_1_7_top,{}" *)
(* CORE_GENERATION_INFO = "zc702_auto_us_df_0,axi_dwidth_converter_v2_1_7_top,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=1,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_auto_us_df_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_7_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(1),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBN_1_V
`define SKY130_FD_SC_HS__SDFBBN_1_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfbbn_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfbbn_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBN_1_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_if0_p0_read_valid_selector(
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2**MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency_shifter;
input [MAX_LATENCY_COUNT_WIDTH-1:0] latency_counter;
output read_enable;
output read_valid;
wire [LATENCY_NUM-1:0] selector;
reg [LATENCY_NUM-1:0] selector_reg;
reg read_enable;
reg reading_data;
reg read_valid;
wire [LATENCY_NUM-1:0] valid_select;
lpm_decode uvalid_select(
.data (latency_counter),
.eq (selector)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.enable ()
// synopsys translate_on
);
defparam uvalid_select.lpm_decodes = LATENCY_NUM;
defparam uvalid_select.lpm_type = "LPM_DECODE";
defparam uvalid_select.lpm_width = MAX_LATENCY_COUNT_WIDTH;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
selector_reg <= {LATENCY_NUM{1'b0}};
else
selector_reg <= selector;
end
assign valid_select = selector_reg & latency_shifter;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
begin
read_enable <= 1'b0;
read_valid <= 1'b0;
end
else
begin
read_enable <= |valid_select;
read_valid <= |valid_select;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_1_V
`define SKY130_FD_SC_HS__A211O_1_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a211o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a211o_1 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_SN_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_SN_BLACKBOX_V
/**
* udp_isolatch_pp$PKG$sN: Power isolating latch. Includes VPWR,
* KAPWR, and VGND power pins with notifier
* and active low sleep pin (SLEEP_B).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_isolatch_pp$PKG$sN (
Q ,
D ,
SLEEP_B ,
NOTIFIER,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input SLEEP_B ;
input NOTIFIER;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_SN_BLACKBOX_V
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module aestest (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
ap_ce,
inptext_V_read,
key_V_read,
ap_return
);
parameter ap_ST_fsm_pp0_stage0 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input ap_ce;
input [127:0] inptext_V_read;
input [127:0] key_V_read;
output [127:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_pp0_stage0;
wire ap_enable_reg_pp0_iter0;
wire ap_block_pp0_stage0_flag00000000;
reg ap_enable_reg_pp0_iter1;
reg ap_enable_reg_pp0_iter2;
reg ap_enable_reg_pp0_iter3;
reg ap_enable_reg_pp0_iter4;
reg ap_enable_reg_pp0_iter5;
reg ap_enable_reg_pp0_iter6;
reg ap_enable_reg_pp0_iter7;
reg ap_enable_reg_pp0_iter8;
reg ap_enable_reg_pp0_iter9;
reg ap_enable_reg_pp0_iter10;
reg ap_idle_pp0;
reg ap_block_state1_pp0_stage0_iter0;
wire ap_block_state2_pp0_stage0_iter1;
wire ap_block_state3_pp0_stage0_iter2;
wire ap_block_state4_pp0_stage0_iter3;
wire ap_block_state5_pp0_stage0_iter4;
wire ap_block_state6_pp0_stage0_iter5;
wire ap_block_state7_pp0_stage0_iter6;
wire ap_block_state8_pp0_stage0_iter7;
wire ap_block_state9_pp0_stage0_iter8;
wire ap_block_state10_pp0_stage0_iter9;
wire ap_block_state11_pp0_stage0_iter10;
reg ap_block_pp0_stage0_flag00011001;
wire [7:0] sboxes_address0;
reg sboxes_ce0;
wire [7:0] sboxes_q0;
wire [7:0] sboxes_address1;
reg sboxes_ce1;
wire [7:0] sboxes_q1;
wire [7:0] sboxes_address2;
reg sboxes_ce2;
wire [7:0] sboxes_q2;
wire [7:0] sboxes_address3;
reg sboxes_ce3;
wire [7:0] sboxes_q3;
wire [7:0] sboxes_address4;
reg sboxes_ce4;
wire [7:0] sboxes_q4;
wire [7:0] sboxes_address5;
reg sboxes_ce5;
wire [7:0] sboxes_q5;
wire [7:0] sboxes_address6;
reg sboxes_ce6;
wire [7:0] sboxes_q6;
wire [7:0] sboxes_address7;
reg sboxes_ce7;
wire [7:0] sboxes_q7;
wire [7:0] sboxes_address8;
reg sboxes_ce8;
wire [7:0] sboxes_q8;
wire [7:0] sboxes_address9;
reg sboxes_ce9;
wire [7:0] sboxes_q9;
wire [7:0] sboxes_address10;
reg sboxes_ce10;
wire [7:0] sboxes_q10;
wire [7:0] sboxes_address11;
reg sboxes_ce11;
wire [7:0] sboxes_q11;
wire [7:0] sboxes_address12;
reg sboxes_ce12;
wire [7:0] sboxes_q12;
wire [7:0] sboxes_address13;
reg sboxes_ce13;
wire [7:0] sboxes_q13;
wire [7:0] sboxes_address14;
reg sboxes_ce14;
wire [7:0] sboxes_q14;
wire [7:0] sboxes_address15;
reg sboxes_ce15;
wire [7:0] sboxes_q15;
wire [7:0] sboxes_address16;
reg sboxes_ce16;
wire [7:0] sboxes_q16;
wire [7:0] sboxes_address17;
reg sboxes_ce17;
wire [7:0] sboxes_q17;
wire [7:0] sboxes_address18;
reg sboxes_ce18;
wire [7:0] sboxes_q18;
wire [7:0] sboxes_address19;
reg sboxes_ce19;
wire [7:0] sboxes_q19;
wire [7:0] sboxes_address20;
reg sboxes_ce20;
wire [7:0] sboxes_q20;
wire [7:0] sboxes_address21;
reg sboxes_ce21;
wire [7:0] sboxes_q21;
wire [7:0] sboxes_address22;
reg sboxes_ce22;
wire [7:0] sboxes_q22;
wire [7:0] sboxes_address23;
reg sboxes_ce23;
wire [7:0] sboxes_q23;
wire [7:0] sboxes_address24;
reg sboxes_ce24;
wire [7:0] sboxes_q24;
wire [7:0] sboxes_address25;
reg sboxes_ce25;
wire [7:0] sboxes_q25;
wire [7:0] sboxes_address26;
reg sboxes_ce26;
wire [7:0] sboxes_q26;
wire [7:0] sboxes_address27;
reg sboxes_ce27;
wire [7:0] sboxes_q27;
wire [7:0] sboxes_address28;
reg sboxes_ce28;
wire [7:0] sboxes_q28;
wire [7:0] sboxes_address29;
reg sboxes_ce29;
wire [7:0] sboxes_q29;
wire [7:0] sboxes_address30;
reg sboxes_ce30;
wire [7:0] sboxes_q30;
wire [7:0] sboxes_address31;
reg sboxes_ce31;
wire [7:0] sboxes_q31;
wire [7:0] sboxes_address32;
reg sboxes_ce32;
wire [7:0] sboxes_q32;
wire [7:0] sboxes_address33;
reg sboxes_ce33;
wire [7:0] sboxes_q33;
wire [7:0] sboxes_address34;
reg sboxes_ce34;
wire [7:0] sboxes_q34;
wire [7:0] sboxes_address35;
reg sboxes_ce35;
wire [7:0] sboxes_q35;
wire [7:0] sboxes_address36;
reg sboxes_ce36;
wire [7:0] sboxes_q36;
wire [7:0] sboxes_address37;
reg sboxes_ce37;
wire [7:0] sboxes_q37;
wire [7:0] sboxes_address38;
reg sboxes_ce38;
wire [7:0] sboxes_q38;
wire [7:0] sboxes_address39;
reg sboxes_ce39;
wire [7:0] sboxes_q39;
wire [7:0] sboxes_address40;
reg sboxes_ce40;
wire [7:0] sboxes_q40;
wire [7:0] sboxes_address41;
reg sboxes_ce41;
wire [7:0] sboxes_q41;
wire [7:0] sboxes_address42;
reg sboxes_ce42;
wire [7:0] sboxes_q42;
wire [7:0] sboxes_address43;
reg sboxes_ce43;
wire [7:0] sboxes_q43;
wire [7:0] sboxes_address44;
reg sboxes_ce44;
wire [7:0] sboxes_q44;
wire [7:0] sboxes_address45;
reg sboxes_ce45;
wire [7:0] sboxes_q45;
wire [7:0] sboxes_address46;
reg sboxes_ce46;
wire [7:0] sboxes_q46;
wire [7:0] sboxes_address47;
reg sboxes_ce47;
wire [7:0] sboxes_q47;
wire [7:0] sboxes_address48;
reg sboxes_ce48;
wire [7:0] sboxes_q48;
wire [7:0] sboxes_address49;
reg sboxes_ce49;
wire [7:0] sboxes_q49;
wire [7:0] sboxes_address50;
reg sboxes_ce50;
wire [7:0] sboxes_q50;
wire [7:0] sboxes_address51;
reg sboxes_ce51;
wire [7:0] sboxes_q51;
wire [7:0] sboxes_address52;
reg sboxes_ce52;
wire [7:0] sboxes_q52;
wire [7:0] sboxes_address53;
reg sboxes_ce53;
wire [7:0] sboxes_q53;
wire [7:0] sboxes_address54;
reg sboxes_ce54;
wire [7:0] sboxes_q54;
wire [7:0] sboxes_address55;
reg sboxes_ce55;
wire [7:0] sboxes_q55;
wire [7:0] sboxes_address56;
reg sboxes_ce56;
wire [7:0] sboxes_q56;
wire [7:0] sboxes_address57;
reg sboxes_ce57;
wire [7:0] sboxes_q57;
wire [7:0] sboxes_address58;
reg sboxes_ce58;
wire [7:0] sboxes_q58;
wire [7:0] sboxes_address59;
reg sboxes_ce59;
wire [7:0] sboxes_q59;
wire [7:0] sboxes_address60;
reg sboxes_ce60;
wire [7:0] sboxes_q60;
wire [7:0] sboxes_address61;
reg sboxes_ce61;
wire [7:0] sboxes_q61;
wire [7:0] sboxes_address62;
reg sboxes_ce62;
wire [7:0] sboxes_q62;
wire [7:0] sboxes_address63;
reg sboxes_ce63;
wire [7:0] sboxes_q63;
wire [7:0] sboxes_address64;
reg sboxes_ce64;
wire [7:0] sboxes_q64;
wire [7:0] sboxes_address65;
reg sboxes_ce65;
wire [7:0] sboxes_q65;
wire [7:0] sboxes_address66;
reg sboxes_ce66;
wire [7:0] sboxes_q66;
wire [7:0] sboxes_address67;
reg sboxes_ce67;
wire [7:0] sboxes_q67;
wire [7:0] sboxes_address68;
reg sboxes_ce68;
wire [7:0] sboxes_q68;
wire [7:0] sboxes_address69;
reg sboxes_ce69;
wire [7:0] sboxes_q69;
wire [7:0] sboxes_address70;
reg sboxes_ce70;
wire [7:0] sboxes_q70;
wire [7:0] sboxes_address71;
reg sboxes_ce71;
wire [7:0] sboxes_q71;
wire [7:0] sboxes_address72;
reg sboxes_ce72;
wire [7:0] sboxes_q72;
wire [7:0] sboxes_address73;
reg sboxes_ce73;
wire [7:0] sboxes_q73;
wire [7:0] sboxes_address74;
reg sboxes_ce74;
wire [7:0] sboxes_q74;
wire [7:0] sboxes_address75;
reg sboxes_ce75;
wire [7:0] sboxes_q75;
wire [7:0] sboxes_address76;
reg sboxes_ce76;
wire [7:0] sboxes_q76;
wire [7:0] sboxes_address77;
reg sboxes_ce77;
wire [7:0] sboxes_q77;
wire [7:0] sboxes_address78;
reg sboxes_ce78;
wire [7:0] sboxes_q78;
wire [7:0] sboxes_address79;
reg sboxes_ce79;
wire [7:0] sboxes_q79;
wire [7:0] sboxes_address80;
reg sboxes_ce80;
wire [7:0] sboxes_q80;
wire [7:0] sboxes_address81;
reg sboxes_ce81;
wire [7:0] sboxes_q81;
wire [7:0] sboxes_address82;
reg sboxes_ce82;
wire [7:0] sboxes_q82;
wire [7:0] sboxes_address83;
reg sboxes_ce83;
wire [7:0] sboxes_q83;
wire [7:0] sboxes_address84;
reg sboxes_ce84;
wire [7:0] sboxes_q84;
wire [7:0] sboxes_address85;
reg sboxes_ce85;
wire [7:0] sboxes_q85;
wire [7:0] sboxes_address86;
reg sboxes_ce86;
wire [7:0] sboxes_q86;
wire [7:0] sboxes_address87;
reg sboxes_ce87;
wire [7:0] sboxes_q87;
wire [7:0] sboxes_address88;
reg sboxes_ce88;
wire [7:0] sboxes_q88;
wire [7:0] sboxes_address89;
reg sboxes_ce89;
wire [7:0] sboxes_q89;
wire [7:0] sboxes_address90;
reg sboxes_ce90;
wire [7:0] sboxes_q90;
wire [7:0] sboxes_address91;
reg sboxes_ce91;
wire [7:0] sboxes_q91;
wire [7:0] sboxes_address92;
reg sboxes_ce92;
wire [7:0] sboxes_q92;
wire [7:0] sboxes_address93;
reg sboxes_ce93;
wire [7:0] sboxes_q93;
wire [7:0] sboxes_address94;
reg sboxes_ce94;
wire [7:0] sboxes_q94;
wire [7:0] sboxes_address95;
reg sboxes_ce95;
wire [7:0] sboxes_q95;
wire [7:0] sboxes_address96;
reg sboxes_ce96;
wire [7:0] sboxes_q96;
wire [7:0] sboxes_address97;
reg sboxes_ce97;
wire [7:0] sboxes_q97;
wire [7:0] sboxes_address98;
reg sboxes_ce98;
wire [7:0] sboxes_q98;
wire [7:0] sboxes_address99;
reg sboxes_ce99;
wire [7:0] sboxes_q99;
wire [7:0] sboxes_address100;
reg sboxes_ce100;
wire [7:0] sboxes_q100;
wire [7:0] sboxes_address101;
reg sboxes_ce101;
wire [7:0] sboxes_q101;
wire [7:0] sboxes_address102;
reg sboxes_ce102;
wire [7:0] sboxes_q102;
wire [7:0] sboxes_address103;
reg sboxes_ce103;
wire [7:0] sboxes_q103;
wire [7:0] sboxes_address104;
reg sboxes_ce104;
wire [7:0] sboxes_q104;
wire [7:0] sboxes_address105;
reg sboxes_ce105;
wire [7:0] sboxes_q105;
wire [7:0] sboxes_address106;
reg sboxes_ce106;
wire [7:0] sboxes_q106;
wire [7:0] sboxes_address107;
reg sboxes_ce107;
wire [7:0] sboxes_q107;
wire [7:0] sboxes_address108;
reg sboxes_ce108;
wire [7:0] sboxes_q108;
wire [7:0] sboxes_address109;
reg sboxes_ce109;
wire [7:0] sboxes_q109;
wire [7:0] sboxes_address110;
reg sboxes_ce110;
wire [7:0] sboxes_q110;
wire [7:0] sboxes_address111;
reg sboxes_ce111;
wire [7:0] sboxes_q111;
wire [7:0] sboxes_address112;
reg sboxes_ce112;
wire [7:0] sboxes_q112;
wire [7:0] sboxes_address113;
reg sboxes_ce113;
wire [7:0] sboxes_q113;
wire [7:0] sboxes_address114;
reg sboxes_ce114;
wire [7:0] sboxes_q114;
wire [7:0] sboxes_address115;
reg sboxes_ce115;
wire [7:0] sboxes_q115;
wire [7:0] sboxes_address116;
reg sboxes_ce116;
wire [7:0] sboxes_q116;
wire [7:0] sboxes_address117;
reg sboxes_ce117;
wire [7:0] sboxes_q117;
wire [7:0] sboxes_address118;
reg sboxes_ce118;
wire [7:0] sboxes_q118;
wire [7:0] sboxes_address119;
reg sboxes_ce119;
wire [7:0] sboxes_q119;
wire [7:0] sboxes_address120;
reg sboxes_ce120;
wire [7:0] sboxes_q120;
wire [7:0] sboxes_address121;
reg sboxes_ce121;
wire [7:0] sboxes_q121;
wire [7:0] sboxes_address122;
reg sboxes_ce122;
wire [7:0] sboxes_q122;
wire [7:0] sboxes_address123;
reg sboxes_ce123;
wire [7:0] sboxes_q123;
wire [7:0] sboxes_address124;
reg sboxes_ce124;
wire [7:0] sboxes_q124;
wire [7:0] sboxes_address125;
reg sboxes_ce125;
wire [7:0] sboxes_q125;
wire [7:0] sboxes_address126;
reg sboxes_ce126;
wire [7:0] sboxes_q126;
wire [7:0] sboxes_address127;
reg sboxes_ce127;
wire [7:0] sboxes_q127;
wire [7:0] sboxes_address128;
reg sboxes_ce128;
wire [7:0] sboxes_q128;
wire [7:0] sboxes_address129;
reg sboxes_ce129;
wire [7:0] sboxes_q129;
wire [7:0] sboxes_address130;
reg sboxes_ce130;
wire [7:0] sboxes_q130;
wire [7:0] sboxes_address131;
reg sboxes_ce131;
wire [7:0] sboxes_q131;
wire [7:0] sboxes_address132;
reg sboxes_ce132;
wire [7:0] sboxes_q132;
wire [7:0] sboxes_address133;
reg sboxes_ce133;
wire [7:0] sboxes_q133;
wire [7:0] sboxes_address134;
reg sboxes_ce134;
wire [7:0] sboxes_q134;
wire [7:0] sboxes_address135;
reg sboxes_ce135;
wire [7:0] sboxes_q135;
wire [7:0] sboxes_address136;
reg sboxes_ce136;
wire [7:0] sboxes_q136;
wire [7:0] sboxes_address137;
reg sboxes_ce137;
wire [7:0] sboxes_q137;
wire [7:0] sboxes_address138;
reg sboxes_ce138;
wire [7:0] sboxes_q138;
wire [7:0] sboxes_address139;
reg sboxes_ce139;
wire [7:0] sboxes_q139;
wire [7:0] sboxes_address140;
reg sboxes_ce140;
wire [7:0] sboxes_q140;
wire [7:0] sboxes_address141;
reg sboxes_ce141;
wire [7:0] sboxes_q141;
wire [7:0] sboxes_address142;
reg sboxes_ce142;
wire [7:0] sboxes_q142;
wire [7:0] sboxes_address143;
reg sboxes_ce143;
wire [7:0] sboxes_q143;
wire [7:0] sboxes_address144;
reg sboxes_ce144;
wire [7:0] sboxes_q144;
wire [7:0] sboxes_address145;
reg sboxes_ce145;
wire [7:0] sboxes_q145;
wire [7:0] sboxes_address146;
reg sboxes_ce146;
wire [7:0] sboxes_q146;
wire [7:0] sboxes_address147;
reg sboxes_ce147;
wire [7:0] sboxes_q147;
wire [7:0] sboxes_address148;
reg sboxes_ce148;
wire [7:0] sboxes_q148;
wire [7:0] sboxes_address149;
reg sboxes_ce149;
wire [7:0] sboxes_q149;
wire [7:0] sboxes_address150;
reg sboxes_ce150;
wire [7:0] sboxes_q150;
wire [7:0] sboxes_address151;
reg sboxes_ce151;
wire [7:0] sboxes_q151;
wire [7:0] sboxes_address152;
reg sboxes_ce152;
wire [7:0] sboxes_q152;
wire [7:0] sboxes_address153;
reg sboxes_ce153;
wire [7:0] sboxes_q153;
wire [7:0] sboxes_address154;
reg sboxes_ce154;
wire [7:0] sboxes_q154;
wire [7:0] sboxes_address155;
reg sboxes_ce155;
wire [7:0] sboxes_q155;
wire [7:0] sboxes_address156;
reg sboxes_ce156;
wire [7:0] sboxes_q156;
wire [7:0] sboxes_address157;
reg sboxes_ce157;
wire [7:0] sboxes_q157;
wire [7:0] sboxes_address158;
reg sboxes_ce158;
wire [7:0] sboxes_q158;
wire [7:0] sboxes_address159;
reg sboxes_ce159;
wire [7:0] sboxes_q159;
wire [7:0] sboxes_address160;
reg sboxes_ce160;
wire [7:0] sboxes_q160;
wire [7:0] sboxes_address161;
reg sboxes_ce161;
wire [7:0] sboxes_q161;
wire [7:0] sboxes_address162;
reg sboxes_ce162;
wire [7:0] sboxes_q162;
wire [7:0] sboxes_address163;
reg sboxes_ce163;
wire [7:0] sboxes_q163;
wire [7:0] sboxes_address164;
reg sboxes_ce164;
wire [7:0] sboxes_q164;
wire [7:0] sboxes_address165;
reg sboxes_ce165;
wire [7:0] sboxes_q165;
wire [7:0] sboxes_address166;
reg sboxes_ce166;
wire [7:0] sboxes_q166;
wire [7:0] sboxes_address167;
reg sboxes_ce167;
wire [7:0] sboxes_q167;
wire [7:0] sboxes_address168;
reg sboxes_ce168;
wire [7:0] sboxes_q168;
wire [7:0] sboxes_address169;
reg sboxes_ce169;
wire [7:0] sboxes_q169;
wire [7:0] sboxes_address170;
reg sboxes_ce170;
wire [7:0] sboxes_q170;
wire [7:0] sboxes_address171;
reg sboxes_ce171;
wire [7:0] sboxes_q171;
wire [7:0] sboxes_address172;
reg sboxes_ce172;
wire [7:0] sboxes_q172;
wire [7:0] sboxes_address173;
reg sboxes_ce173;
wire [7:0] sboxes_q173;
wire [7:0] sboxes_address174;
reg sboxes_ce174;
wire [7:0] sboxes_q174;
wire [7:0] sboxes_address175;
reg sboxes_ce175;
wire [7:0] sboxes_q175;
wire [7:0] sboxes_address176;
reg sboxes_ce176;
wire [7:0] sboxes_q176;
wire [7:0] sboxes_address177;
reg sboxes_ce177;
wire [7:0] sboxes_q177;
wire [7:0] sboxes_address178;
reg sboxes_ce178;
wire [7:0] sboxes_q178;
wire [7:0] sboxes_address179;
reg sboxes_ce179;
wire [7:0] sboxes_q179;
wire [7:0] sboxes_address180;
reg sboxes_ce180;
wire [7:0] sboxes_q180;
wire [7:0] sboxes_address181;
reg sboxes_ce181;
wire [7:0] sboxes_q181;
wire [7:0] sboxes_address182;
reg sboxes_ce182;
wire [7:0] sboxes_q182;
wire [7:0] sboxes_address183;
reg sboxes_ce183;
wire [7:0] sboxes_q183;
wire [7:0] sboxes_address184;
reg sboxes_ce184;
wire [7:0] sboxes_q184;
wire [7:0] sboxes_address185;
reg sboxes_ce185;
wire [7:0] sboxes_q185;
wire [7:0] sboxes_address186;
reg sboxes_ce186;
wire [7:0] sboxes_q186;
wire [7:0] sboxes_address187;
reg sboxes_ce187;
wire [7:0] sboxes_q187;
wire [7:0] sboxes_address188;
reg sboxes_ce188;
wire [7:0] sboxes_q188;
wire [7:0] sboxes_address189;
reg sboxes_ce189;
wire [7:0] sboxes_q189;
wire [7:0] sboxes_address190;
reg sboxes_ce190;
wire [7:0] sboxes_q190;
wire [7:0] sboxes_address191;
reg sboxes_ce191;
wire [7:0] sboxes_q191;
wire [7:0] sboxes_address192;
reg sboxes_ce192;
wire [7:0] sboxes_q192;
wire [7:0] sboxes_address193;
reg sboxes_ce193;
wire [7:0] sboxes_q193;
wire [7:0] sboxes_address194;
reg sboxes_ce194;
wire [7:0] sboxes_q194;
wire [7:0] sboxes_address195;
reg sboxes_ce195;
wire [7:0] sboxes_q195;
wire [7:0] sboxes_address196;
reg sboxes_ce196;
wire [7:0] sboxes_q196;
wire [7:0] sboxes_address197;
reg sboxes_ce197;
wire [7:0] sboxes_q197;
wire [7:0] sboxes_address198;
reg sboxes_ce198;
wire [7:0] sboxes_q198;
wire [7:0] sboxes_address199;
reg sboxes_ce199;
wire [7:0] sboxes_q199;
wire [7:0] p_Result_1_fu_2331_p4;
reg [7:0] p_Result_1_reg_12421;
wire [7:0] p_Result_1_1_fu_2351_p4;
reg [7:0] p_Result_1_1_reg_12426;
wire [7:0] p_Result_1_2_fu_2371_p4;
reg [7:0] p_Result_1_2_reg_12431;
wire [7:0] p_Result_1_3_fu_2391_p4;
reg [7:0] p_Result_1_3_reg_12436;
wire [7:0] p_Result_1_4_fu_2411_p4;
reg [7:0] p_Result_1_4_reg_12441;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_4_reg_12441;
wire [7:0] p_Result_1_5_fu_2431_p4;
reg [7:0] p_Result_1_5_reg_12447;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_5_reg_12447;
wire [7:0] p_Result_1_6_fu_2451_p4;
reg [7:0] p_Result_1_6_reg_12453;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_6_reg_12453;
wire [7:0] p_Result_1_7_fu_2471_p4;
reg [7:0] p_Result_1_7_reg_12459;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_7_reg_12459;
wire [7:0] p_Result_1_8_fu_2491_p4;
reg [7:0] p_Result_1_8_reg_12465;
wire [7:0] p_Result_1_9_fu_2511_p4;
reg [7:0] p_Result_1_9_reg_12470;
wire [7:0] p_Result_1_s_fu_2531_p4;
reg [7:0] p_Result_1_s_reg_12475;
wire [7:0] p_Result_1_10_fu_2551_p4;
reg [7:0] p_Result_1_10_reg_12480;
wire [7:0] p_Result_1_11_fu_2571_p4;
reg [7:0] p_Result_1_11_reg_12485;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_11_reg_12485;
reg [7:0] ap_reg_pp0_iter2_p_Result_1_11_reg_12485;
reg [7:0] ap_reg_pp0_iter3_p_Result_1_11_reg_12485;
wire [7:0] p_Result_1_12_fu_2591_p4;
reg [7:0] p_Result_1_12_reg_12492;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_12_reg_12492;
reg [7:0] ap_reg_pp0_iter2_p_Result_1_12_reg_12492;
reg [7:0] ap_reg_pp0_iter3_p_Result_1_12_reg_12492;
wire [7:0] p_Result_1_13_fu_2611_p4;
reg [7:0] p_Result_1_13_reg_12499;
reg [7:0] ap_reg_pp0_iter1_p_Result_1_13_reg_12499;
reg [7:0] ap_reg_pp0_iter2_p_Result_1_13_reg_12499;
reg [7:0] ap_reg_pp0_iter3_p_Result_1_13_reg_12499;
wire [7:0] tmp_100_fu_2625_p1;
reg [7:0] tmp_100_reg_12506;
reg [7:0] ap_reg_pp0_iter1_tmp_100_reg_12506;
reg [7:0] ap_reg_pp0_iter2_tmp_100_reg_12506;
reg [7:0] ap_reg_pp0_iter3_tmp_100_reg_12506;
wire [7:0] tmp_65_fu_3422_p2;
reg [7:0] tmp_65_reg_12613;
wire [7:0] tmp_66_fu_3428_p2;
reg [7:0] tmp_66_reg_12618;
wire [7:0] tmp_67_fu_3433_p2;
reg [7:0] tmp_67_reg_12623;
wire [7:0] tmp_68_fu_3438_p2;
reg [7:0] tmp_68_reg_12628;
wire [7:0] tmp_73_fu_3463_p2;
reg [7:0] tmp_73_reg_12633;
reg [7:0] ap_reg_pp0_iter2_tmp_73_reg_12633;
wire [7:0] tmp_74_fu_3468_p2;
reg [7:0] tmp_74_reg_12639;
reg [7:0] ap_reg_pp0_iter2_tmp_74_reg_12639;
wire [7:0] tmp_75_fu_3473_p2;
reg [7:0] tmp_75_reg_12645;
reg [7:0] ap_reg_pp0_iter2_tmp_75_reg_12645;
wire [7:0] tmp_76_fu_3478_p2;
reg [7:0] tmp_76_reg_12651;
reg [7:0] ap_reg_pp0_iter2_tmp_76_reg_12651;
wire [7:0] tmp_65_1_fu_4465_p2;
reg [7:0] tmp_65_1_reg_12757;
wire [7:0] tmp_66_1_fu_4470_p2;
reg [7:0] tmp_66_1_reg_12762;
wire [7:0] tmp_67_1_fu_4475_p2;
reg [7:0] tmp_67_1_reg_12767;
wire [7:0] tmp_68_1_fu_4480_p2;
reg [7:0] tmp_68_1_reg_12772;
wire [7:0] tmp_69_1_fu_4485_p2;
reg [7:0] tmp_69_1_reg_12777;
reg [7:0] ap_reg_pp0_iter3_tmp_69_1_reg_12777;
wire [7:0] tmp_70_1_fu_4490_p2;
reg [7:0] tmp_70_1_reg_12783;
reg [7:0] ap_reg_pp0_iter3_tmp_70_1_reg_12783;
wire [7:0] tmp_71_1_fu_4495_p2;
reg [7:0] tmp_71_1_reg_12789;
reg [7:0] ap_reg_pp0_iter3_tmp_71_1_reg_12789;
wire [7:0] tmp_72_1_fu_4500_p2;
reg [7:0] tmp_72_1_reg_12795;
reg [7:0] ap_reg_pp0_iter3_tmp_72_1_reg_12795;
wire [7:0] tmp_77_1_fu_4505_p2;
reg [7:0] tmp_77_1_reg_12801;
wire [7:0] tmp_78_1_fu_4510_p2;
reg [7:0] tmp_78_1_reg_12806;
wire [7:0] tmp_79_1_fu_4515_p2;
reg [7:0] tmp_79_1_reg_12811;
wire [7:0] tmp_80_1_fu_4520_p2;
reg [7:0] tmp_80_1_reg_12816;
wire [7:0] tmp_65_2_fu_5506_p2;
reg [7:0] tmp_65_2_reg_12921;
wire [7:0] tmp_66_2_fu_5512_p2;
reg [7:0] tmp_66_2_reg_12926;
wire [7:0] tmp_67_2_fu_5517_p2;
reg [7:0] tmp_67_2_reg_12931;
wire [7:0] tmp_68_2_fu_5522_p2;
reg [7:0] tmp_68_2_reg_12936;
wire [7:0] tmp_73_2_fu_5527_p2;
reg [7:0] tmp_73_2_reg_12941;
reg [7:0] ap_reg_pp0_iter4_tmp_73_2_reg_12941;
wire [7:0] tmp_74_2_fu_5532_p2;
reg [7:0] tmp_74_2_reg_12947;
reg [7:0] ap_reg_pp0_iter4_tmp_74_2_reg_12947;
wire [7:0] tmp_75_2_fu_5537_p2;
reg [7:0] tmp_75_2_reg_12953;
reg [7:0] ap_reg_pp0_iter4_tmp_75_2_reg_12953;
wire [7:0] tmp_76_2_fu_5542_p2;
reg [7:0] tmp_76_2_reg_12959;
reg [7:0] ap_reg_pp0_iter4_tmp_76_2_reg_12959;
wire [7:0] tmp_65_3_fu_6549_p2;
reg [7:0] tmp_65_3_reg_13065;
wire [7:0] tmp_66_3_fu_6554_p2;
reg [7:0] tmp_66_3_reg_13070;
wire [7:0] tmp_67_3_fu_6559_p2;
reg [7:0] tmp_67_3_reg_13075;
wire [7:0] tmp_68_3_fu_6564_p2;
reg [7:0] tmp_68_3_reg_13080;
wire [7:0] tmp_69_3_fu_6569_p2;
reg [7:0] tmp_69_3_reg_13085;
reg [7:0] ap_reg_pp0_iter5_tmp_69_3_reg_13085;
wire [7:0] tmp_70_3_fu_6574_p2;
reg [7:0] tmp_70_3_reg_13091;
reg [7:0] ap_reg_pp0_iter5_tmp_70_3_reg_13091;
wire [7:0] tmp_71_3_fu_6579_p2;
reg [7:0] tmp_71_3_reg_13097;
reg [7:0] ap_reg_pp0_iter5_tmp_71_3_reg_13097;
wire [7:0] tmp_72_3_fu_6584_p2;
reg [7:0] tmp_72_3_reg_13103;
reg [7:0] ap_reg_pp0_iter5_tmp_72_3_reg_13103;
wire [7:0] tmp_77_3_fu_6589_p2;
reg [7:0] tmp_77_3_reg_13109;
reg [7:0] ap_reg_pp0_iter5_tmp_77_3_reg_13109;
reg [7:0] ap_reg_pp0_iter6_tmp_77_3_reg_13109;
reg [7:0] ap_reg_pp0_iter7_tmp_77_3_reg_13109;
wire [7:0] tmp_78_3_fu_6594_p2;
reg [7:0] tmp_78_3_reg_13116;
reg [7:0] ap_reg_pp0_iter5_tmp_78_3_reg_13116;
reg [7:0] ap_reg_pp0_iter6_tmp_78_3_reg_13116;
reg [7:0] ap_reg_pp0_iter7_tmp_78_3_reg_13116;
wire [7:0] tmp_79_3_fu_6599_p2;
reg [7:0] tmp_79_3_reg_13123;
reg [7:0] ap_reg_pp0_iter5_tmp_79_3_reg_13123;
reg [7:0] ap_reg_pp0_iter6_tmp_79_3_reg_13123;
reg [7:0] ap_reg_pp0_iter7_tmp_79_3_reg_13123;
wire [7:0] tmp_80_3_fu_6604_p2;
reg [7:0] tmp_80_3_reg_13130;
reg [7:0] ap_reg_pp0_iter5_tmp_80_3_reg_13130;
reg [7:0] ap_reg_pp0_iter6_tmp_80_3_reg_13130;
reg [7:0] ap_reg_pp0_iter7_tmp_80_3_reg_13130;
wire [7:0] tmp_65_4_fu_7590_p2;
reg [7:0] tmp_65_4_reg_13237;
wire [7:0] tmp_66_4_fu_7596_p2;
reg [7:0] tmp_66_4_reg_13242;
wire [7:0] tmp_67_4_fu_7601_p2;
reg [7:0] tmp_67_4_reg_13247;
wire [7:0] tmp_68_4_fu_7606_p2;
reg [7:0] tmp_68_4_reg_13252;
wire [7:0] tmp_73_4_fu_7611_p2;
reg [7:0] tmp_73_4_reg_13257;
reg [7:0] ap_reg_pp0_iter6_tmp_73_4_reg_13257;
wire [7:0] tmp_74_4_fu_7616_p2;
reg [7:0] tmp_74_4_reg_13263;
reg [7:0] ap_reg_pp0_iter6_tmp_74_4_reg_13263;
wire [7:0] tmp_75_4_fu_7621_p2;
reg [7:0] tmp_75_4_reg_13269;
reg [7:0] ap_reg_pp0_iter6_tmp_75_4_reg_13269;
wire [7:0] tmp_76_4_fu_7626_p2;
reg [7:0] tmp_76_4_reg_13275;
reg [7:0] ap_reg_pp0_iter6_tmp_76_4_reg_13275;
wire [7:0] tmp_65_5_fu_8633_p2;
reg [7:0] tmp_65_5_reg_13381;
wire [7:0] tmp_66_5_fu_8638_p2;
reg [7:0] tmp_66_5_reg_13386;
wire [7:0] tmp_67_5_fu_8643_p2;
reg [7:0] tmp_67_5_reg_13391;
wire [7:0] tmp_68_5_fu_8648_p2;
reg [7:0] tmp_68_5_reg_13396;
wire [7:0] tmp_69_5_fu_8653_p2;
reg [7:0] tmp_69_5_reg_13401;
reg [7:0] ap_reg_pp0_iter7_tmp_69_5_reg_13401;
wire [7:0] tmp_70_5_fu_8658_p2;
reg [7:0] tmp_70_5_reg_13407;
reg [7:0] ap_reg_pp0_iter7_tmp_70_5_reg_13407;
wire [7:0] tmp_71_5_fu_8663_p2;
reg [7:0] tmp_71_5_reg_13413;
reg [7:0] ap_reg_pp0_iter7_tmp_71_5_reg_13413;
wire [7:0] tmp_72_5_fu_8668_p2;
reg [7:0] tmp_72_5_reg_13419;
reg [7:0] ap_reg_pp0_iter7_tmp_72_5_reg_13419;
wire [7:0] tmp_77_5_fu_8673_p2;
reg [7:0] tmp_77_5_reg_13425;
wire [7:0] tmp_78_5_fu_8678_p2;
reg [7:0] tmp_78_5_reg_13430;
wire [7:0] tmp_79_5_fu_8683_p2;
reg [7:0] tmp_79_5_reg_13435;
wire [7:0] tmp_80_5_fu_8688_p2;
reg [7:0] tmp_80_5_reg_13440;
wire [7:0] tmp_65_6_fu_9674_p2;
reg [7:0] tmp_65_6_reg_13545;
wire [7:0] tmp_66_6_fu_9680_p2;
reg [7:0] tmp_66_6_reg_13550;
wire [7:0] tmp_67_6_fu_9685_p2;
reg [7:0] tmp_67_6_reg_13555;
wire [7:0] tmp_68_6_fu_9690_p2;
reg [7:0] tmp_68_6_reg_13560;
wire [7:0] tmp_73_6_fu_9695_p2;
reg [7:0] tmp_73_6_reg_13565;
reg [7:0] ap_reg_pp0_iter8_tmp_73_6_reg_13565;
wire [7:0] tmp_74_6_fu_9700_p2;
reg [7:0] tmp_74_6_reg_13571;
reg [7:0] ap_reg_pp0_iter8_tmp_74_6_reg_13571;
wire [7:0] tmp_75_6_fu_9705_p2;
reg [7:0] tmp_75_6_reg_13577;
reg [7:0] ap_reg_pp0_iter8_tmp_75_6_reg_13577;
wire [7:0] tmp_76_6_fu_9710_p2;
reg [7:0] tmp_76_6_reg_13583;
reg [7:0] ap_reg_pp0_iter8_tmp_76_6_reg_13583;
wire [7:0] tmp_65_7_fu_10717_p2;
reg [7:0] tmp_65_7_reg_13689;
wire [7:0] tmp_66_7_fu_10722_p2;
reg [7:0] tmp_66_7_reg_13694;
wire [7:0] tmp_67_7_fu_10727_p2;
reg [7:0] tmp_67_7_reg_13699;
wire [7:0] tmp_68_7_fu_10732_p2;
reg [7:0] tmp_68_7_reg_13704;
wire [7:0] tmp_69_7_fu_10737_p2;
reg [7:0] tmp_69_7_reg_13709;
reg [7:0] ap_reg_pp0_iter9_tmp_69_7_reg_13709;
wire [7:0] tmp_70_7_fu_10742_p2;
reg [7:0] tmp_70_7_reg_13715;
reg [7:0] ap_reg_pp0_iter9_tmp_70_7_reg_13715;
wire [7:0] tmp_71_7_fu_10747_p2;
reg [7:0] tmp_71_7_reg_13721;
reg [7:0] ap_reg_pp0_iter9_tmp_71_7_reg_13721;
wire [7:0] tmp_72_7_fu_10752_p2;
reg [7:0] tmp_72_7_reg_13727;
reg [7:0] ap_reg_pp0_iter9_tmp_72_7_reg_13727;
wire [7:0] tmp_77_7_fu_10757_p2;
reg [7:0] tmp_77_7_reg_13733;
reg [7:0] ap_reg_pp0_iter9_tmp_77_7_reg_13733;
wire [7:0] tmp_78_7_fu_10762_p2;
reg [7:0] tmp_78_7_reg_13739;
reg [7:0] ap_reg_pp0_iter9_tmp_78_7_reg_13739;
wire [7:0] tmp_79_7_fu_10767_p2;
reg [7:0] tmp_79_7_reg_13745;
reg [7:0] ap_reg_pp0_iter9_tmp_79_7_reg_13745;
wire [7:0] tmp_80_7_fu_10772_p2;
reg [7:0] tmp_80_7_reg_13751;
reg [7:0] ap_reg_pp0_iter9_tmp_80_7_reg_13751;
wire [7:0] tmp_65_8_fu_11758_p2;
reg [7:0] tmp_65_8_reg_13857;
wire [7:0] tmp_66_8_fu_11764_p2;
reg [7:0] tmp_66_8_reg_13862;
wire [7:0] tmp_67_8_fu_11769_p2;
reg [7:0] tmp_67_8_reg_13867;
wire [7:0] tmp_68_8_fu_11774_p2;
reg [7:0] tmp_68_8_reg_13872;
wire [7:0] tmp_73_8_fu_11779_p2;
reg [7:0] tmp_73_8_reg_13877;
wire [7:0] tmp_74_8_fu_11784_p2;
reg [7:0] tmp_74_8_reg_13882;
wire [7:0] tmp_75_8_fu_11789_p2;
reg [7:0] tmp_75_8_reg_13887;
wire [7:0] tmp_76_8_fu_11794_p2;
reg [7:0] tmp_76_8_reg_13892;
reg ap_block_pp0_stage0_flag00011011;
wire [63:0] tmp_35_fu_2725_p1;
wire [63:0] tmp_35_0_1_fu_2730_p1;
wire [63:0] tmp_35_0_2_fu_2735_p1;
wire [63:0] tmp_35_0_3_fu_2740_p1;
wire [63:0] tmp_35_0_4_fu_2745_p1;
wire [63:0] tmp_35_0_5_fu_2750_p1;
wire [63:0] tmp_35_0_6_fu_2755_p1;
wire [63:0] tmp_35_0_7_fu_2760_p1;
wire [63:0] tmp_35_0_8_fu_2765_p1;
wire [63:0] tmp_35_0_9_fu_2770_p1;
wire [63:0] tmp_35_0_s_fu_2775_p1;
wire [63:0] tmp_35_0_10_fu_2780_p1;
wire [63:0] tmp_35_0_11_fu_2785_p1;
wire [63:0] tmp_35_0_12_fu_2790_p1;
wire [63:0] tmp_35_0_13_fu_2795_p1;
wire [63:0] tmp_35_0_14_fu_2800_p1;
wire [63:0] tmp_60_fu_2805_p1;
wire [63:0] tmp_61_fu_2810_p1;
wire [63:0] tmp_62_fu_2815_p1;
wire [63:0] tmp_63_fu_2820_p1;
wire [63:0] tmp_35_1_fu_3767_p1;
wire [63:0] tmp_35_1_1_fu_3772_p1;
wire [63:0] tmp_35_1_2_fu_3777_p1;
wire [63:0] tmp_35_1_3_fu_3782_p1;
wire [63:0] tmp_35_1_4_fu_3787_p1;
wire [63:0] tmp_35_1_5_fu_3792_p1;
wire [63:0] tmp_35_1_6_fu_3797_p1;
wire [63:0] tmp_35_1_7_fu_3802_p1;
wire [63:0] tmp_35_1_8_fu_3807_p1;
wire [63:0] tmp_35_1_9_fu_3812_p1;
wire [63:0] tmp_35_1_s_fu_3817_p1;
wire [63:0] tmp_35_1_10_fu_3822_p1;
wire [63:0] tmp_35_1_11_fu_3827_p1;
wire [63:0] tmp_35_1_12_fu_3832_p1;
wire [63:0] tmp_35_1_13_fu_3837_p1;
wire [63:0] tmp_35_1_14_fu_3842_p1;
wire [63:0] tmp_60_1_fu_3847_p1;
wire [63:0] tmp_61_1_fu_3852_p1;
wire [63:0] tmp_62_1_fu_3857_p1;
wire [63:0] tmp_63_1_fu_3862_p1;
wire [63:0] tmp_35_2_fu_4809_p1;
wire [63:0] tmp_35_2_1_fu_4814_p1;
wire [63:0] tmp_35_2_2_fu_4819_p1;
wire [63:0] tmp_35_2_3_fu_4824_p1;
wire [63:0] tmp_35_2_4_fu_4829_p1;
wire [63:0] tmp_35_2_5_fu_4834_p1;
wire [63:0] tmp_35_2_6_fu_4839_p1;
wire [63:0] tmp_35_2_7_fu_4844_p1;
wire [63:0] tmp_35_2_8_fu_4849_p1;
wire [63:0] tmp_35_2_9_fu_4854_p1;
wire [63:0] tmp_35_2_s_fu_4859_p1;
wire [63:0] tmp_35_2_10_fu_4864_p1;
wire [63:0] tmp_35_2_11_fu_4869_p1;
wire [63:0] tmp_35_2_12_fu_4874_p1;
wire [63:0] tmp_35_2_13_fu_4879_p1;
wire [63:0] tmp_35_2_14_fu_4884_p1;
wire [63:0] tmp_60_2_fu_4889_p1;
wire [63:0] tmp_61_2_fu_4894_p1;
wire [63:0] tmp_62_2_fu_4899_p1;
wire [63:0] tmp_63_2_fu_4904_p1;
wire [63:0] tmp_35_3_fu_5851_p1;
wire [63:0] tmp_35_3_1_fu_5856_p1;
wire [63:0] tmp_35_3_2_fu_5861_p1;
wire [63:0] tmp_35_3_3_fu_5866_p1;
wire [63:0] tmp_35_3_4_fu_5871_p1;
wire [63:0] tmp_35_3_5_fu_5876_p1;
wire [63:0] tmp_35_3_6_fu_5881_p1;
wire [63:0] tmp_35_3_7_fu_5886_p1;
wire [63:0] tmp_35_3_8_fu_5891_p1;
wire [63:0] tmp_35_3_9_fu_5896_p1;
wire [63:0] tmp_35_3_s_fu_5901_p1;
wire [63:0] tmp_35_3_10_fu_5906_p1;
wire [63:0] tmp_35_3_11_fu_5911_p1;
wire [63:0] tmp_35_3_12_fu_5916_p1;
wire [63:0] tmp_35_3_13_fu_5921_p1;
wire [63:0] tmp_35_3_14_fu_5926_p1;
wire [63:0] tmp_60_3_fu_5931_p1;
wire [63:0] tmp_61_3_fu_5936_p1;
wire [63:0] tmp_62_3_fu_5941_p1;
wire [63:0] tmp_63_3_fu_5946_p1;
wire [63:0] tmp_35_4_fu_6893_p1;
wire [63:0] tmp_35_4_1_fu_6898_p1;
wire [63:0] tmp_35_4_2_fu_6903_p1;
wire [63:0] tmp_35_4_3_fu_6908_p1;
wire [63:0] tmp_35_4_4_fu_6913_p1;
wire [63:0] tmp_35_4_5_fu_6918_p1;
wire [63:0] tmp_35_4_6_fu_6923_p1;
wire [63:0] tmp_35_4_7_fu_6928_p1;
wire [63:0] tmp_35_4_8_fu_6933_p1;
wire [63:0] tmp_35_4_9_fu_6938_p1;
wire [63:0] tmp_35_4_s_fu_6943_p1;
wire [63:0] tmp_35_4_10_fu_6948_p1;
wire [63:0] tmp_35_4_11_fu_6953_p1;
wire [63:0] tmp_35_4_12_fu_6958_p1;
wire [63:0] tmp_35_4_13_fu_6963_p1;
wire [63:0] tmp_35_4_14_fu_6968_p1;
wire [63:0] tmp_60_4_fu_6973_p1;
wire [63:0] tmp_61_4_fu_6978_p1;
wire [63:0] tmp_62_4_fu_6983_p1;
wire [63:0] tmp_63_4_fu_6988_p1;
wire [63:0] tmp_35_5_fu_7935_p1;
wire [63:0] tmp_35_5_1_fu_7940_p1;
wire [63:0] tmp_35_5_2_fu_7945_p1;
wire [63:0] tmp_35_5_3_fu_7950_p1;
wire [63:0] tmp_35_5_4_fu_7955_p1;
wire [63:0] tmp_35_5_5_fu_7960_p1;
wire [63:0] tmp_35_5_6_fu_7965_p1;
wire [63:0] tmp_35_5_7_fu_7970_p1;
wire [63:0] tmp_35_5_8_fu_7975_p1;
wire [63:0] tmp_35_5_9_fu_7980_p1;
wire [63:0] tmp_35_5_s_fu_7985_p1;
wire [63:0] tmp_35_5_10_fu_7990_p1;
wire [63:0] tmp_35_5_11_fu_7995_p1;
wire [63:0] tmp_35_5_12_fu_8000_p1;
wire [63:0] tmp_35_5_13_fu_8005_p1;
wire [63:0] tmp_35_5_14_fu_8010_p1;
wire [63:0] tmp_60_5_fu_8015_p1;
wire [63:0] tmp_61_5_fu_8020_p1;
wire [63:0] tmp_62_5_fu_8025_p1;
wire [63:0] tmp_63_5_fu_8030_p1;
wire [63:0] tmp_35_6_fu_8977_p1;
wire [63:0] tmp_35_6_1_fu_8982_p1;
wire [63:0] tmp_35_6_2_fu_8987_p1;
wire [63:0] tmp_35_6_3_fu_8992_p1;
wire [63:0] tmp_35_6_4_fu_8997_p1;
wire [63:0] tmp_35_6_5_fu_9002_p1;
wire [63:0] tmp_35_6_6_fu_9007_p1;
wire [63:0] tmp_35_6_7_fu_9012_p1;
wire [63:0] tmp_35_6_8_fu_9017_p1;
wire [63:0] tmp_35_6_9_fu_9022_p1;
wire [63:0] tmp_35_6_s_fu_9027_p1;
wire [63:0] tmp_35_6_10_fu_9032_p1;
wire [63:0] tmp_35_6_11_fu_9037_p1;
wire [63:0] tmp_35_6_12_fu_9042_p1;
wire [63:0] tmp_35_6_13_fu_9047_p1;
wire [63:0] tmp_35_6_14_fu_9052_p1;
wire [63:0] tmp_60_6_fu_9057_p1;
wire [63:0] tmp_61_6_fu_9062_p1;
wire [63:0] tmp_62_6_fu_9067_p1;
wire [63:0] tmp_63_6_fu_9072_p1;
wire [63:0] tmp_35_7_fu_10019_p1;
wire [63:0] tmp_35_7_1_fu_10024_p1;
wire [63:0] tmp_35_7_2_fu_10029_p1;
wire [63:0] tmp_35_7_3_fu_10034_p1;
wire [63:0] tmp_35_7_4_fu_10039_p1;
wire [63:0] tmp_35_7_5_fu_10044_p1;
wire [63:0] tmp_35_7_6_fu_10049_p1;
wire [63:0] tmp_35_7_7_fu_10054_p1;
wire [63:0] tmp_35_7_8_fu_10059_p1;
wire [63:0] tmp_35_7_9_fu_10064_p1;
wire [63:0] tmp_35_7_s_fu_10069_p1;
wire [63:0] tmp_35_7_10_fu_10074_p1;
wire [63:0] tmp_35_7_11_fu_10079_p1;
wire [63:0] tmp_35_7_12_fu_10084_p1;
wire [63:0] tmp_35_7_13_fu_10089_p1;
wire [63:0] tmp_35_7_14_fu_10094_p1;
wire [63:0] tmp_60_7_fu_10099_p1;
wire [63:0] tmp_61_7_fu_10104_p1;
wire [63:0] tmp_62_7_fu_10109_p1;
wire [63:0] tmp_63_7_fu_10114_p1;
wire [63:0] tmp_35_8_fu_11061_p1;
wire [63:0] tmp_35_8_1_fu_11066_p1;
wire [63:0] tmp_35_8_2_fu_11071_p1;
wire [63:0] tmp_35_8_3_fu_11076_p1;
wire [63:0] tmp_35_8_4_fu_11081_p1;
wire [63:0] tmp_35_8_5_fu_11086_p1;
wire [63:0] tmp_35_8_6_fu_11091_p1;
wire [63:0] tmp_35_8_7_fu_11096_p1;
wire [63:0] tmp_35_8_8_fu_11101_p1;
wire [63:0] tmp_35_8_9_fu_11106_p1;
wire [63:0] tmp_35_8_s_fu_11111_p1;
wire [63:0] tmp_35_8_10_fu_11116_p1;
wire [63:0] tmp_35_8_11_fu_11121_p1;
wire [63:0] tmp_35_8_12_fu_11126_p1;
wire [63:0] tmp_35_8_13_fu_11131_p1;
wire [63:0] tmp_35_8_14_fu_11136_p1;
wire [63:0] tmp_60_8_fu_11141_p1;
wire [63:0] tmp_61_8_fu_11146_p1;
wire [63:0] tmp_62_8_fu_11151_p1;
wire [63:0] tmp_63_8_fu_11156_p1;
wire [63:0] tmp_33_fu_12103_p1;
wire [63:0] tmp_33_1_fu_12108_p1;
wire [63:0] tmp_33_2_fu_12113_p1;
wire [63:0] tmp_33_3_fu_12118_p1;
wire [63:0] tmp_33_4_fu_12123_p1;
wire [63:0] tmp_33_5_fu_12128_p1;
wire [63:0] tmp_33_6_fu_12133_p1;
wire [63:0] tmp_33_7_fu_12138_p1;
wire [63:0] tmp_33_8_fu_12143_p1;
wire [63:0] tmp_33_9_fu_12148_p1;
wire [63:0] tmp_33_s_fu_12153_p1;
wire [63:0] tmp_33_10_fu_12158_p1;
wire [63:0] tmp_33_11_fu_12163_p1;
wire [63:0] tmp_33_12_fu_12168_p1;
wire [63:0] tmp_33_13_fu_12173_p1;
wire [63:0] tmp_33_14_fu_12178_p1;
wire [63:0] tmp_s_fu_12183_p1;
wire [63:0] tmp_1_fu_12188_p1;
wire [63:0] tmp_2_fu_12193_p1;
wire [63:0] tmp_3_fu_12198_p1;
wire [7:0] p_Result_s_fu_2321_p4;
wire [7:0] p_Result_s_39_fu_2341_p4;
wire [7:0] p_Result_2_fu_2361_p4;
wire [7:0] p_Result_3_fu_2381_p4;
wire [7:0] p_Result_4_fu_2401_p4;
wire [7:0] p_Result_5_fu_2421_p4;
wire [7:0] p_Result_6_fu_2441_p4;
wire [7:0] p_Result_7_fu_2461_p4;
wire [7:0] p_Result_8_fu_2481_p4;
wire [7:0] p_Result_9_fu_2501_p4;
wire [7:0] p_Result_10_fu_2521_p4;
wire [7:0] p_Result_11_fu_2541_p4;
wire [7:0] p_Result_12_fu_2561_p4;
wire [7:0] p_Result_13_fu_2581_p4;
wire [7:0] p_Result_14_fu_2601_p4;
wire [7:0] tmp_99_fu_2621_p1;
wire [7:0] tmp_10_fu_2629_p2;
wire [7:0] tmp_10_1_fu_2635_p2;
wire [7:0] tmp_10_2_fu_2641_p2;
wire [7:0] tmp_10_3_fu_2647_p2;
wire [7:0] tmp_10_4_fu_2653_p2;
wire [7:0] tmp_10_5_fu_2659_p2;
wire [7:0] tmp_10_6_fu_2665_p2;
wire [7:0] tmp_10_7_fu_2671_p2;
wire [7:0] tmp_10_8_fu_2677_p2;
wire [7:0] tmp_10_9_fu_2683_p2;
wire [7:0] tmp_10_s_fu_2689_p2;
wire [7:0] tmp_10_10_fu_2695_p2;
wire [7:0] tmp_10_11_fu_2701_p2;
wire [7:0] tmp_10_12_fu_2707_p2;
wire [7:0] tmp_10_13_fu_2713_p2;
wire [7:0] tmp_10_14_fu_2719_p2;
wire [7:0] x_assign_fu_2825_p2;
wire [7:0] tmp_47_fu_2831_p2;
wire [7:0] tmp_101_fu_2843_p2;
wire [0:0] tmp_102_fu_2849_p3;
wire [7:0] rv_1_fu_2857_p2;
wire [7:0] x_assign_1_fu_2871_p2;
wire [7:0] tmp_103_fu_2877_p2;
wire [0:0] tmp_104_fu_2883_p3;
wire [7:0] rv_4_fu_2891_p2;
wire [7:0] x_assign_2_fu_2905_p2;
wire [7:0] tmp_105_fu_2911_p2;
wire [0:0] tmp_106_fu_2917_p3;
wire [7:0] rv_7_fu_2925_p2;
wire [7:0] x_assign_3_fu_2939_p2;
wire [7:0] tmp_107_fu_2945_p2;
wire [0:0] tmp_108_fu_2951_p3;
wire [7:0] rv_s_fu_2959_p2;
wire [7:0] x_assign_0_1_fu_2973_p2;
wire [7:0] tmp_47_0_1_fu_2979_p2;
wire [7:0] tmp_109_fu_2991_p2;
wire [0:0] tmp_110_fu_2997_p3;
wire [7:0] rv_1_0_1_fu_3005_p2;
wire [7:0] x_assign_1_0_1_fu_3019_p2;
wire [7:0] tmp_111_fu_3025_p2;
wire [0:0] tmp_112_fu_3031_p3;
wire [7:0] rv_4_0_1_fu_3039_p2;
wire [7:0] x_assign_2_0_1_fu_3053_p2;
wire [7:0] tmp_113_fu_3059_p2;
wire [0:0] tmp_114_fu_3065_p3;
wire [7:0] rv_7_0_1_fu_3073_p2;
wire [7:0] x_assign_3_0_1_fu_3087_p2;
wire [7:0] tmp_115_fu_3093_p2;
wire [0:0] tmp_116_fu_3099_p3;
wire [7:0] rv_10_0_1_fu_3107_p2;
wire [7:0] x_assign_0_2_fu_3121_p2;
wire [7:0] tmp_47_0_2_fu_3127_p2;
wire [7:0] tmp_117_fu_3139_p2;
wire [0:0] tmp_118_fu_3145_p3;
wire [7:0] rv_1_0_2_fu_3153_p2;
wire [7:0] x_assign_1_0_2_fu_3167_p2;
wire [7:0] tmp_119_fu_3173_p2;
wire [0:0] tmp_120_fu_3179_p3;
wire [7:0] rv_4_0_2_fu_3187_p2;
wire [7:0] x_assign_2_0_2_fu_3201_p2;
wire [7:0] tmp_121_fu_3207_p2;
wire [0:0] tmp_122_fu_3213_p3;
wire [7:0] rv_7_0_2_fu_3221_p2;
wire [7:0] x_assign_3_0_2_fu_3235_p2;
wire [7:0] tmp_123_fu_3241_p2;
wire [0:0] tmp_124_fu_3247_p3;
wire [7:0] rv_10_0_2_fu_3255_p2;
wire [7:0] x_assign_0_3_fu_3269_p2;
wire [7:0] tmp_47_0_3_fu_3275_p2;
wire [7:0] tmp_125_fu_3287_p2;
wire [0:0] tmp_126_fu_3293_p3;
wire [7:0] rv_1_0_3_fu_3301_p2;
wire [7:0] x_assign_1_0_3_fu_3315_p2;
wire [7:0] tmp_127_fu_3321_p2;
wire [0:0] tmp_128_fu_3327_p3;
wire [7:0] rv_4_0_3_fu_3335_p2;
wire [7:0] x_assign_2_0_3_fu_3349_p2;
wire [7:0] tmp_129_fu_3355_p2;
wire [0:0] tmp_130_fu_3361_p3;
wire [7:0] rv_7_0_3_fu_3369_p2;
wire [7:0] x_assign_3_0_3_fu_3383_p2;
wire [7:0] tmp_131_fu_3389_p2;
wire [0:0] tmp_132_fu_3395_p3;
wire [7:0] rv_10_0_3_fu_3403_p2;
wire [7:0] tmp_fu_3417_p2;
wire [7:0] tmp_69_fu_3443_p2;
wire [7:0] tmp_70_fu_3448_p2;
wire [7:0] tmp_71_fu_3453_p2;
wire [7:0] tmp_72_fu_3458_p2;
wire [7:0] rv_2_fu_2863_p3;
wire [7:0] e_fu_2837_p2;
wire [7:0] tmp2_fu_3509_p2;
wire [7:0] tmp1_fu_3503_p2;
wire [7:0] rv_5_fu_2897_p3;
wire [7:0] tmp4_fu_3527_p2;
wire [7:0] tmp3_fu_3521_p2;
wire [7:0] rv_8_fu_2931_p3;
wire [7:0] tmp6_fu_3545_p2;
wire [7:0] tmp5_fu_3539_p2;
wire [7:0] tmp7_fu_3557_p2;
wire [7:0] rv_3_fu_2965_p3;
wire [7:0] rv_2_0_1_fu_3011_p3;
wire [7:0] e_0_1_fu_2985_p2;
wire [7:0] tmp9_fu_3575_p2;
wire [7:0] tmp8_fu_3569_p2;
wire [7:0] rv_5_0_1_fu_3045_p3;
wire [7:0] tmp11_fu_3593_p2;
wire [7:0] tmp10_fu_3587_p2;
wire [7:0] rv_8_0_1_fu_3079_p3;
wire [7:0] tmp13_fu_3611_p2;
wire [7:0] tmp12_fu_3605_p2;
wire [7:0] tmp14_fu_3623_p2;
wire [7:0] rv_11_0_1_fu_3113_p3;
wire [7:0] rv_2_0_2_fu_3159_p3;
wire [7:0] e_0_2_fu_3133_p2;
wire [7:0] tmp16_fu_3641_p2;
wire [7:0] tmp15_fu_3635_p2;
wire [7:0] rv_5_0_2_fu_3193_p3;
wire [7:0] tmp18_fu_3659_p2;
wire [7:0] tmp17_fu_3653_p2;
wire [7:0] rv_8_0_2_fu_3227_p3;
wire [7:0] tmp20_fu_3677_p2;
wire [7:0] tmp19_fu_3671_p2;
wire [7:0] tmp21_fu_3689_p2;
wire [7:0] rv_11_0_2_fu_3261_p3;
wire [7:0] rv_2_0_3_fu_3307_p3;
wire [7:0] e_0_3_fu_3281_p2;
wire [7:0] tmp_77_fu_3483_p2;
wire [7:0] tmp23_fu_3707_p2;
wire [7:0] tmp22_fu_3701_p2;
wire [7:0] rv_5_0_3_fu_3341_p3;
wire [7:0] tmp_78_fu_3488_p2;
wire [7:0] tmp25_fu_3725_p2;
wire [7:0] tmp24_fu_3719_p2;
wire [7:0] rv_8_0_3_fu_3375_p3;
wire [7:0] tmp_79_fu_3493_p2;
wire [7:0] tmp27_fu_3743_p2;
wire [7:0] tmp26_fu_3737_p2;
wire [7:0] tmp_80_fu_3498_p2;
wire [7:0] tmp28_fu_3755_p2;
wire [7:0] rv_11_0_3_fu_3409_p3;
wire [7:0] tmp_85_fu_3515_p2;
wire [7:0] tmp_85_0_1_fu_3533_p2;
wire [7:0] tmp_85_0_2_fu_3551_p2;
wire [7:0] tmp_85_0_3_fu_3563_p2;
wire [7:0] tmp_85_0_4_fu_3581_p2;
wire [7:0] tmp_85_0_5_fu_3599_p2;
wire [7:0] tmp_85_0_6_fu_3617_p2;
wire [7:0] tmp_85_0_7_fu_3629_p2;
wire [7:0] tmp_85_0_8_fu_3647_p2;
wire [7:0] tmp_85_0_9_fu_3665_p2;
wire [7:0] tmp_85_0_s_fu_3683_p2;
wire [7:0] tmp_85_0_10_fu_3695_p2;
wire [7:0] tmp_85_0_11_fu_3713_p2;
wire [7:0] tmp_85_0_12_fu_3731_p2;
wire [7:0] tmp_85_0_13_fu_3749_p2;
wire [7:0] tmp_85_0_14_fu_3761_p2;
wire [7:0] x_assign_s_fu_3867_p2;
wire [7:0] tmp_47_1_fu_3873_p2;
wire [7:0] tmp_133_fu_3885_p2;
wire [0:0] tmp_134_fu_3891_p3;
wire [7:0] rv_1_1_fu_3899_p2;
wire [7:0] x_assign_1_1_fu_3913_p2;
wire [7:0] tmp_135_fu_3919_p2;
wire [0:0] tmp_136_fu_3925_p3;
wire [7:0] rv_4_1_fu_3933_p2;
wire [7:0] x_assign_2_1_fu_3947_p2;
wire [7:0] tmp_137_fu_3953_p2;
wire [0:0] tmp_138_fu_3959_p3;
wire [7:0] rv_7_1_fu_3967_p2;
wire [7:0] x_assign_3_1_fu_3981_p2;
wire [7:0] tmp_139_fu_3987_p2;
wire [0:0] tmp_140_fu_3993_p3;
wire [7:0] rv_10_1_fu_4001_p2;
wire [7:0] x_assign_171_1_fu_4015_p2;
wire [7:0] tmp_47_1_1_fu_4021_p2;
wire [7:0] tmp_141_fu_4033_p2;
wire [0:0] tmp_142_fu_4039_p3;
wire [7:0] rv_1_1_1_fu_4047_p2;
wire [7:0] x_assign_1_1_1_fu_4061_p2;
wire [7:0] tmp_143_fu_4067_p2;
wire [0:0] tmp_144_fu_4073_p3;
wire [7:0] rv_4_1_1_fu_4081_p2;
wire [7:0] x_assign_2_1_1_fu_4095_p2;
wire [7:0] tmp_145_fu_4101_p2;
wire [0:0] tmp_146_fu_4107_p3;
wire [7:0] rv_7_1_1_fu_4115_p2;
wire [7:0] x_assign_3_1_1_fu_4129_p2;
wire [7:0] tmp_147_fu_4135_p2;
wire [0:0] tmp_148_fu_4141_p3;
wire [7:0] rv_10_1_1_fu_4149_p2;
wire [7:0] x_assign_171_2_fu_4163_p2;
wire [7:0] tmp_47_1_2_fu_4169_p2;
wire [7:0] tmp_149_fu_4181_p2;
wire [0:0] tmp_150_fu_4187_p3;
wire [7:0] rv_1_1_2_fu_4195_p2;
wire [7:0] x_assign_1_1_2_fu_4209_p2;
wire [7:0] tmp_151_fu_4215_p2;
wire [0:0] tmp_152_fu_4221_p3;
wire [7:0] rv_4_1_2_fu_4229_p2;
wire [7:0] x_assign_2_1_2_fu_4243_p2;
wire [7:0] tmp_153_fu_4249_p2;
wire [0:0] tmp_154_fu_4255_p3;
wire [7:0] rv_7_1_2_fu_4263_p2;
wire [7:0] x_assign_3_1_2_fu_4277_p2;
wire [7:0] tmp_155_fu_4283_p2;
wire [0:0] tmp_156_fu_4289_p3;
wire [7:0] rv_10_1_2_fu_4297_p2;
wire [7:0] x_assign_171_3_fu_4311_p2;
wire [7:0] tmp_47_1_3_fu_4317_p2;
wire [7:0] tmp_157_fu_4329_p2;
wire [0:0] tmp_158_fu_4335_p3;
wire [7:0] rv_1_1_3_fu_4343_p2;
wire [7:0] x_assign_1_1_3_fu_4357_p2;
wire [7:0] tmp_159_fu_4363_p2;
wire [0:0] tmp_160_fu_4369_p3;
wire [7:0] rv_4_1_3_fu_4377_p2;
wire [7:0] x_assign_2_1_3_fu_4391_p2;
wire [7:0] tmp_161_fu_4397_p2;
wire [0:0] tmp_162_fu_4403_p3;
wire [7:0] rv_7_1_3_fu_4411_p2;
wire [7:0] x_assign_3_1_3_fu_4425_p2;
wire [7:0] tmp_163_fu_4431_p2;
wire [0:0] tmp_164_fu_4437_p3;
wire [7:0] rv_10_1_3_fu_4445_p2;
wire [7:0] tmp_64_1_fu_4459_p2;
wire [7:0] rv_2_1_fu_3905_p3;
wire [7:0] e_1_fu_3879_p2;
wire [7:0] tmp30_fu_4531_p2;
wire [7:0] tmp29_fu_4525_p2;
wire [7:0] rv_5_1_fu_3939_p3;
wire [7:0] tmp32_fu_4549_p2;
wire [7:0] tmp31_fu_4543_p2;
wire [7:0] rv_8_1_fu_3973_p3;
wire [7:0] tmp34_fu_4567_p2;
wire [7:0] tmp33_fu_4561_p2;
wire [7:0] tmp35_fu_4579_p2;
wire [7:0] rv_11_1_fu_4007_p3;
wire [7:0] rv_2_1_1_fu_4053_p3;
wire [7:0] e_1_1_fu_4027_p2;
wire [7:0] tmp37_fu_4597_p2;
wire [7:0] tmp36_fu_4591_p2;
wire [7:0] rv_5_1_1_fu_4087_p3;
wire [7:0] tmp39_fu_4615_p2;
wire [7:0] tmp38_fu_4609_p2;
wire [7:0] rv_8_1_1_fu_4121_p3;
wire [7:0] tmp41_fu_4633_p2;
wire [7:0] tmp40_fu_4627_p2;
wire [7:0] tmp42_fu_4645_p2;
wire [7:0] rv_11_1_1_fu_4155_p3;
wire [7:0] rv_2_1_2_fu_4201_p3;
wire [7:0] tmp45_fu_4663_p2;
wire [7:0] e_1_2_fu_4175_p2;
wire [7:0] tmp44_fu_4668_p2;
wire [7:0] tmp43_fu_4657_p2;
wire [7:0] tmp48_fu_4686_p2;
wire [7:0] rv_5_1_2_fu_4235_p3;
wire [7:0] tmp47_fu_4691_p2;
wire [7:0] tmp46_fu_4680_p2;
wire [7:0] tmp51_fu_4709_p2;
wire [7:0] rv_8_1_2_fu_4269_p3;
wire [7:0] tmp50_fu_4714_p2;
wire [7:0] tmp49_fu_4703_p2;
wire [7:0] rv_11_1_2_fu_4303_p3;
wire [7:0] tmp53_fu_4732_p2;
wire [7:0] tmp52_fu_4726_p2;
wire [7:0] rv_2_1_3_fu_4349_p3;
wire [7:0] e_1_3_fu_4323_p2;
wire [7:0] tmp55_fu_4749_p2;
wire [7:0] tmp54_fu_4743_p2;
wire [7:0] rv_5_1_3_fu_4383_p3;
wire [7:0] tmp57_fu_4767_p2;
wire [7:0] tmp56_fu_4761_p2;
wire [7:0] rv_8_1_3_fu_4417_p3;
wire [7:0] tmp59_fu_4785_p2;
wire [7:0] tmp58_fu_4779_p2;
wire [7:0] tmp60_fu_4797_p2;
wire [7:0] rv_11_1_3_fu_4451_p3;
wire [7:0] tmp_85_1_fu_4537_p2;
wire [7:0] tmp_85_1_1_fu_4555_p2;
wire [7:0] tmp_85_1_2_fu_4573_p2;
wire [7:0] tmp_85_1_3_fu_4585_p2;
wire [7:0] tmp_85_1_4_fu_4603_p2;
wire [7:0] tmp_85_1_5_fu_4621_p2;
wire [7:0] tmp_85_1_6_fu_4639_p2;
wire [7:0] tmp_85_1_7_fu_4651_p2;
wire [7:0] tmp_85_1_8_fu_4674_p2;
wire [7:0] tmp_85_1_9_fu_4697_p2;
wire [7:0] tmp_85_1_s_fu_4720_p2;
wire [7:0] tmp_85_1_10_fu_4737_p2;
wire [7:0] tmp_85_1_11_fu_4755_p2;
wire [7:0] tmp_85_1_12_fu_4773_p2;
wire [7:0] tmp_85_1_13_fu_4791_p2;
wire [7:0] tmp_85_1_14_fu_4803_p2;
wire [7:0] x_assign_9_fu_4909_p2;
wire [7:0] tmp_47_2_fu_4915_p2;
wire [7:0] tmp_165_fu_4927_p2;
wire [0:0] tmp_166_fu_4933_p3;
wire [7:0] rv_1_2_fu_4941_p2;
wire [7:0] x_assign_1_2_fu_4955_p2;
wire [7:0] tmp_167_fu_4961_p2;
wire [0:0] tmp_168_fu_4967_p3;
wire [7:0] rv_4_2_fu_4975_p2;
wire [7:0] x_assign_2_2_fu_4989_p2;
wire [7:0] tmp_169_fu_4995_p2;
wire [0:0] tmp_170_fu_5001_p3;
wire [7:0] rv_7_2_fu_5009_p2;
wire [7:0] x_assign_3_2_fu_5023_p2;
wire [7:0] tmp_171_fu_5029_p2;
wire [0:0] tmp_172_fu_5035_p3;
wire [7:0] rv_10_2_fu_5043_p2;
wire [7:0] x_assign_273_1_fu_5057_p2;
wire [7:0] tmp_47_2_1_fu_5063_p2;
wire [7:0] tmp_173_fu_5075_p2;
wire [0:0] tmp_174_fu_5081_p3;
wire [7:0] rv_1_2_1_fu_5089_p2;
wire [7:0] x_assign_1_2_1_fu_5103_p2;
wire [7:0] tmp_175_fu_5109_p2;
wire [0:0] tmp_176_fu_5115_p3;
wire [7:0] rv_4_2_1_fu_5123_p2;
wire [7:0] x_assign_2_2_1_fu_5137_p2;
wire [7:0] tmp_177_fu_5143_p2;
wire [0:0] tmp_178_fu_5149_p3;
wire [7:0] rv_7_2_1_fu_5157_p2;
wire [7:0] x_assign_3_2_1_fu_5171_p2;
wire [7:0] tmp_179_fu_5177_p2;
wire [0:0] tmp_180_fu_5183_p3;
wire [7:0] rv_10_2_1_fu_5191_p2;
wire [7:0] x_assign_273_2_fu_5205_p2;
wire [7:0] tmp_47_2_2_fu_5211_p2;
wire [7:0] tmp_181_fu_5223_p2;
wire [0:0] tmp_182_fu_5229_p3;
wire [7:0] rv_1_2_2_fu_5237_p2;
wire [7:0] x_assign_1_2_2_fu_5251_p2;
wire [7:0] tmp_183_fu_5257_p2;
wire [0:0] tmp_184_fu_5263_p3;
wire [7:0] rv_4_2_2_fu_5271_p2;
wire [7:0] x_assign_2_2_2_fu_5285_p2;
wire [7:0] tmp_185_fu_5291_p2;
wire [0:0] tmp_186_fu_5297_p3;
wire [7:0] rv_7_2_2_fu_5305_p2;
wire [7:0] x_assign_3_2_2_fu_5319_p2;
wire [7:0] tmp_187_fu_5325_p2;
wire [0:0] tmp_188_fu_5331_p3;
wire [7:0] rv_10_2_2_fu_5339_p2;
wire [7:0] x_assign_273_3_fu_5353_p2;
wire [7:0] tmp_47_2_3_fu_5359_p2;
wire [7:0] tmp_189_fu_5371_p2;
wire [0:0] tmp_190_fu_5377_p3;
wire [7:0] rv_1_2_3_fu_5385_p2;
wire [7:0] x_assign_1_2_3_fu_5399_p2;
wire [7:0] tmp_191_fu_5405_p2;
wire [0:0] tmp_192_fu_5411_p3;
wire [7:0] rv_4_2_3_fu_5419_p2;
wire [7:0] x_assign_2_2_3_fu_5433_p2;
wire [7:0] tmp_193_fu_5439_p2;
wire [0:0] tmp_194_fu_5445_p3;
wire [7:0] rv_7_2_3_fu_5453_p2;
wire [7:0] x_assign_3_2_3_fu_5467_p2;
wire [7:0] tmp_195_fu_5473_p2;
wire [0:0] tmp_196_fu_5479_p3;
wire [7:0] rv_10_2_3_fu_5487_p2;
wire [7:0] tmp61_fu_5501_p2;
wire [7:0] rv_2_2_fu_4947_p3;
wire [7:0] e_2_fu_4921_p2;
wire [7:0] tmp63_fu_5573_p2;
wire [7:0] tmp62_fu_5567_p2;
wire [7:0] rv_5_2_fu_4981_p3;
wire [7:0] tmp65_fu_5591_p2;
wire [7:0] tmp64_fu_5585_p2;
wire [7:0] rv_8_2_fu_5015_p3;
wire [7:0] tmp67_fu_5609_p2;
wire [7:0] tmp66_fu_5603_p2;
wire [7:0] tmp68_fu_5621_p2;
wire [7:0] rv_11_2_fu_5049_p3;
wire [7:0] rv_2_2_1_fu_5095_p3;
wire [7:0] tmp71_fu_5639_p2;
wire [7:0] e_2_1_fu_5069_p2;
wire [7:0] tmp70_fu_5644_p2;
wire [7:0] tmp69_fu_5633_p2;
wire [7:0] tmp74_fu_5662_p2;
wire [7:0] rv_5_2_1_fu_5129_p3;
wire [7:0] tmp73_fu_5667_p2;
wire [7:0] tmp72_fu_5656_p2;
wire [7:0] tmp77_fu_5685_p2;
wire [7:0] rv_8_2_1_fu_5163_p3;
wire [7:0] tmp76_fu_5690_p2;
wire [7:0] tmp75_fu_5679_p2;
wire [7:0] rv_11_2_1_fu_5197_p3;
wire [7:0] tmp79_fu_5708_p2;
wire [7:0] tmp78_fu_5702_p2;
wire [7:0] rv_2_2_2_fu_5243_p3;
wire [7:0] e_2_2_fu_5217_p2;
wire [7:0] tmp81_fu_5725_p2;
wire [7:0] tmp80_fu_5719_p2;
wire [7:0] rv_5_2_2_fu_5277_p3;
wire [7:0] tmp83_fu_5743_p2;
wire [7:0] tmp82_fu_5737_p2;
wire [7:0] rv_8_2_2_fu_5311_p3;
wire [7:0] tmp85_fu_5761_p2;
wire [7:0] tmp84_fu_5755_p2;
wire [7:0] tmp86_fu_5773_p2;
wire [7:0] rv_11_2_2_fu_5345_p3;
wire [7:0] rv_2_2_3_fu_5391_p3;
wire [7:0] e_2_3_fu_5365_p2;
wire [7:0] tmp_77_2_fu_5547_p2;
wire [7:0] tmp88_fu_5791_p2;
wire [7:0] tmp87_fu_5785_p2;
wire [7:0] rv_5_2_3_fu_5425_p3;
wire [7:0] tmp_78_2_fu_5552_p2;
wire [7:0] tmp90_fu_5809_p2;
wire [7:0] tmp89_fu_5803_p2;
wire [7:0] rv_8_2_3_fu_5459_p3;
wire [7:0] tmp_79_2_fu_5557_p2;
wire [7:0] tmp92_fu_5827_p2;
wire [7:0] tmp91_fu_5821_p2;
wire [7:0] tmp_80_2_fu_5562_p2;
wire [7:0] tmp93_fu_5839_p2;
wire [7:0] rv_11_2_3_fu_5493_p3;
wire [7:0] tmp_85_2_fu_5579_p2;
wire [7:0] tmp_85_2_1_fu_5597_p2;
wire [7:0] tmp_85_2_2_fu_5615_p2;
wire [7:0] tmp_85_2_3_fu_5627_p2;
wire [7:0] tmp_85_2_4_fu_5650_p2;
wire [7:0] tmp_85_2_5_fu_5673_p2;
wire [7:0] tmp_85_2_6_fu_5696_p2;
wire [7:0] tmp_85_2_7_fu_5713_p2;
wire [7:0] tmp_85_2_8_fu_5731_p2;
wire [7:0] tmp_85_2_9_fu_5749_p2;
wire [7:0] tmp_85_2_s_fu_5767_p2;
wire [7:0] tmp_85_2_10_fu_5779_p2;
wire [7:0] tmp_85_2_11_fu_5797_p2;
wire [7:0] tmp_85_2_12_fu_5815_p2;
wire [7:0] tmp_85_2_13_fu_5833_p2;
wire [7:0] tmp_85_2_14_fu_5845_p2;
wire [7:0] x_assign_10_fu_5951_p2;
wire [7:0] tmp_47_3_fu_5957_p2;
wire [7:0] tmp_197_fu_5969_p2;
wire [0:0] tmp_198_fu_5975_p3;
wire [7:0] rv_1_3_fu_5983_p2;
wire [7:0] x_assign_1_3_fu_5997_p2;
wire [7:0] tmp_199_fu_6003_p2;
wire [0:0] tmp_200_fu_6009_p3;
wire [7:0] rv_4_3_fu_6017_p2;
wire [7:0] x_assign_2_3_fu_6031_p2;
wire [7:0] tmp_201_fu_6037_p2;
wire [0:0] tmp_202_fu_6043_p3;
wire [7:0] rv_7_3_fu_6051_p2;
wire [7:0] x_assign_3_3_fu_6065_p2;
wire [7:0] tmp_203_fu_6071_p2;
wire [0:0] tmp_204_fu_6077_p3;
wire [7:0] rv_10_3_fu_6085_p2;
wire [7:0] x_assign_375_1_fu_6099_p2;
wire [7:0] tmp_47_3_1_fu_6105_p2;
wire [7:0] tmp_205_fu_6117_p2;
wire [0:0] tmp_206_fu_6123_p3;
wire [7:0] rv_1_3_1_fu_6131_p2;
wire [7:0] x_assign_1_3_1_fu_6145_p2;
wire [7:0] tmp_207_fu_6151_p2;
wire [0:0] tmp_208_fu_6157_p3;
wire [7:0] rv_4_3_1_fu_6165_p2;
wire [7:0] x_assign_2_3_1_fu_6179_p2;
wire [7:0] tmp_209_fu_6185_p2;
wire [0:0] tmp_210_fu_6191_p3;
wire [7:0] rv_7_3_1_fu_6199_p2;
wire [7:0] x_assign_3_3_1_fu_6213_p2;
wire [7:0] tmp_211_fu_6219_p2;
wire [0:0] tmp_212_fu_6225_p3;
wire [7:0] rv_10_3_1_fu_6233_p2;
wire [7:0] x_assign_375_2_fu_6247_p2;
wire [7:0] tmp_47_3_2_fu_6253_p2;
wire [7:0] tmp_213_fu_6265_p2;
wire [0:0] tmp_214_fu_6271_p3;
wire [7:0] rv_1_3_2_fu_6279_p2;
wire [7:0] x_assign_1_3_2_fu_6293_p2;
wire [7:0] tmp_215_fu_6299_p2;
wire [0:0] tmp_216_fu_6305_p3;
wire [7:0] rv_4_3_2_fu_6313_p2;
wire [7:0] x_assign_2_3_2_fu_6327_p2;
wire [7:0] tmp_217_fu_6333_p2;
wire [0:0] tmp_218_fu_6339_p3;
wire [7:0] rv_7_3_2_fu_6347_p2;
wire [7:0] x_assign_3_3_2_fu_6361_p2;
wire [7:0] tmp_219_fu_6367_p2;
wire [0:0] tmp_220_fu_6373_p3;
wire [7:0] rv_10_3_2_fu_6381_p2;
wire [7:0] x_assign_375_3_fu_6395_p2;
wire [7:0] tmp_47_3_3_fu_6401_p2;
wire [7:0] tmp_221_fu_6413_p2;
wire [0:0] tmp_222_fu_6419_p3;
wire [7:0] rv_1_3_3_fu_6427_p2;
wire [7:0] x_assign_1_3_3_fu_6441_p2;
wire [7:0] tmp_223_fu_6447_p2;
wire [0:0] tmp_224_fu_6453_p3;
wire [7:0] rv_4_3_3_fu_6461_p2;
wire [7:0] x_assign_2_3_3_fu_6475_p2;
wire [7:0] tmp_225_fu_6481_p2;
wire [0:0] tmp_226_fu_6487_p3;
wire [7:0] rv_7_3_3_fu_6495_p2;
wire [7:0] x_assign_3_3_3_fu_6509_p2;
wire [7:0] tmp_227_fu_6515_p2;
wire [0:0] tmp_228_fu_6521_p3;
wire [7:0] rv_10_3_3_fu_6529_p2;
wire [7:0] tmp_64_3_fu_6543_p2;
wire [7:0] rv_2_3_fu_5989_p3;
wire [7:0] e_3_fu_5963_p2;
wire [7:0] tmp95_fu_6615_p2;
wire [7:0] tmp94_fu_6609_p2;
wire [7:0] rv_5_3_fu_6023_p3;
wire [7:0] tmp97_fu_6633_p2;
wire [7:0] tmp96_fu_6627_p2;
wire [7:0] rv_8_3_fu_6057_p3;
wire [7:0] tmp99_fu_6651_p2;
wire [7:0] tmp98_fu_6645_p2;
wire [7:0] tmp100_fu_6663_p2;
wire [7:0] rv_11_3_fu_6091_p3;
wire [7:0] rv_2_3_1_fu_6137_p3;
wire [7:0] e_3_1_fu_6111_p2;
wire [7:0] tmp102_fu_6681_p2;
wire [7:0] tmp101_fu_6675_p2;
wire [7:0] rv_5_3_1_fu_6171_p3;
wire [7:0] tmp104_fu_6699_p2;
wire [7:0] tmp103_fu_6693_p2;
wire [7:0] rv_8_3_1_fu_6205_p3;
wire [7:0] tmp106_fu_6717_p2;
wire [7:0] tmp105_fu_6711_p2;
wire [7:0] tmp107_fu_6729_p2;
wire [7:0] rv_11_3_1_fu_6239_p3;
wire [7:0] rv_2_3_2_fu_6285_p3;
wire [7:0] tmp110_fu_6747_p2;
wire [7:0] e_3_2_fu_6259_p2;
wire [7:0] tmp109_fu_6752_p2;
wire [7:0] tmp108_fu_6741_p2;
wire [7:0] tmp113_fu_6770_p2;
wire [7:0] rv_5_3_2_fu_6319_p3;
wire [7:0] tmp112_fu_6775_p2;
wire [7:0] tmp111_fu_6764_p2;
wire [7:0] tmp116_fu_6793_p2;
wire [7:0] rv_8_3_2_fu_6353_p3;
wire [7:0] tmp115_fu_6798_p2;
wire [7:0] tmp114_fu_6787_p2;
wire [7:0] rv_11_3_2_fu_6387_p3;
wire [7:0] tmp118_fu_6816_p2;
wire [7:0] tmp117_fu_6810_p2;
wire [7:0] rv_2_3_3_fu_6433_p3;
wire [7:0] e_3_3_fu_6407_p2;
wire [7:0] tmp120_fu_6833_p2;
wire [7:0] tmp119_fu_6827_p2;
wire [7:0] rv_5_3_3_fu_6467_p3;
wire [7:0] tmp122_fu_6851_p2;
wire [7:0] tmp121_fu_6845_p2;
wire [7:0] rv_8_3_3_fu_6501_p3;
wire [7:0] tmp124_fu_6869_p2;
wire [7:0] tmp123_fu_6863_p2;
wire [7:0] tmp125_fu_6881_p2;
wire [7:0] rv_11_3_3_fu_6535_p3;
wire [7:0] tmp_85_3_fu_6621_p2;
wire [7:0] tmp_85_3_1_fu_6639_p2;
wire [7:0] tmp_85_3_2_fu_6657_p2;
wire [7:0] tmp_85_3_3_fu_6669_p2;
wire [7:0] tmp_85_3_4_fu_6687_p2;
wire [7:0] tmp_85_3_5_fu_6705_p2;
wire [7:0] tmp_85_3_6_fu_6723_p2;
wire [7:0] tmp_85_3_7_fu_6735_p2;
wire [7:0] tmp_85_3_8_fu_6758_p2;
wire [7:0] tmp_85_3_9_fu_6781_p2;
wire [7:0] tmp_85_3_s_fu_6804_p2;
wire [7:0] tmp_85_3_10_fu_6821_p2;
wire [7:0] tmp_85_3_11_fu_6839_p2;
wire [7:0] tmp_85_3_12_fu_6857_p2;
wire [7:0] tmp_85_3_13_fu_6875_p2;
wire [7:0] tmp_85_3_14_fu_6887_p2;
wire [7:0] x_assign_4_fu_6993_p2;
wire [7:0] tmp_47_4_fu_6999_p2;
wire [7:0] tmp_229_fu_7011_p2;
wire [0:0] tmp_230_fu_7017_p3;
wire [7:0] rv_1_4_fu_7025_p2;
wire [7:0] x_assign_1_4_fu_7039_p2;
wire [7:0] tmp_231_fu_7045_p2;
wire [0:0] tmp_232_fu_7051_p3;
wire [7:0] rv_4_4_fu_7059_p2;
wire [7:0] x_assign_2_4_fu_7073_p2;
wire [7:0] tmp_233_fu_7079_p2;
wire [0:0] tmp_234_fu_7085_p3;
wire [7:0] rv_7_4_fu_7093_p2;
wire [7:0] x_assign_3_4_fu_7107_p2;
wire [7:0] tmp_235_fu_7113_p2;
wire [0:0] tmp_236_fu_7119_p3;
wire [7:0] rv_10_4_fu_7127_p2;
wire [7:0] x_assign_4_1_fu_7141_p2;
wire [7:0] tmp_47_4_1_fu_7147_p2;
wire [7:0] tmp_237_fu_7159_p2;
wire [0:0] tmp_238_fu_7165_p3;
wire [7:0] rv_1_4_1_fu_7173_p2;
wire [7:0] x_assign_1_4_1_fu_7187_p2;
wire [7:0] tmp_239_fu_7193_p2;
wire [0:0] tmp_240_fu_7199_p3;
wire [7:0] rv_4_4_1_fu_7207_p2;
wire [7:0] x_assign_2_4_1_fu_7221_p2;
wire [7:0] tmp_241_fu_7227_p2;
wire [0:0] tmp_242_fu_7233_p3;
wire [7:0] rv_7_4_1_fu_7241_p2;
wire [7:0] x_assign_3_4_1_fu_7255_p2;
wire [7:0] tmp_243_fu_7261_p2;
wire [0:0] tmp_244_fu_7267_p3;
wire [7:0] rv_10_4_1_fu_7275_p2;
wire [7:0] x_assign_4_2_fu_7289_p2;
wire [7:0] tmp_47_4_2_fu_7295_p2;
wire [7:0] tmp_245_fu_7307_p2;
wire [0:0] tmp_246_fu_7313_p3;
wire [7:0] rv_1_4_2_fu_7321_p2;
wire [7:0] x_assign_1_4_2_fu_7335_p2;
wire [7:0] tmp_247_fu_7341_p2;
wire [0:0] tmp_248_fu_7347_p3;
wire [7:0] rv_4_4_2_fu_7355_p2;
wire [7:0] x_assign_2_4_2_fu_7369_p2;
wire [7:0] tmp_249_fu_7375_p2;
wire [0:0] tmp_250_fu_7381_p3;
wire [7:0] rv_7_4_2_fu_7389_p2;
wire [7:0] x_assign_3_4_2_fu_7403_p2;
wire [7:0] tmp_251_fu_7409_p2;
wire [0:0] tmp_252_fu_7415_p3;
wire [7:0] rv_10_4_2_fu_7423_p2;
wire [7:0] x_assign_4_3_fu_7437_p2;
wire [7:0] tmp_47_4_3_fu_7443_p2;
wire [7:0] tmp_253_fu_7455_p2;
wire [0:0] tmp_254_fu_7461_p3;
wire [7:0] rv_1_4_3_fu_7469_p2;
wire [7:0] x_assign_1_4_3_fu_7483_p2;
wire [7:0] tmp_255_fu_7489_p2;
wire [0:0] tmp_256_fu_7495_p3;
wire [7:0] rv_4_4_3_fu_7503_p2;
wire [7:0] x_assign_2_4_3_fu_7517_p2;
wire [7:0] tmp_257_fu_7523_p2;
wire [0:0] tmp_258_fu_7529_p3;
wire [7:0] rv_7_4_3_fu_7537_p2;
wire [7:0] x_assign_3_4_3_fu_7551_p2;
wire [7:0] tmp_259_fu_7557_p2;
wire [0:0] tmp_260_fu_7563_p3;
wire [7:0] rv_10_4_3_fu_7571_p2;
wire [7:0] tmp126_fu_7585_p2;
wire [7:0] rv_2_4_fu_7031_p3;
wire [7:0] e_4_fu_7005_p2;
wire [7:0] tmp128_fu_7657_p2;
wire [7:0] tmp127_fu_7651_p2;
wire [7:0] rv_5_4_fu_7065_p3;
wire [7:0] tmp130_fu_7675_p2;
wire [7:0] tmp129_fu_7669_p2;
wire [7:0] rv_8_4_fu_7099_p3;
wire [7:0] tmp132_fu_7693_p2;
wire [7:0] tmp131_fu_7687_p2;
wire [7:0] tmp133_fu_7705_p2;
wire [7:0] rv_11_4_fu_7133_p3;
wire [7:0] rv_2_4_1_fu_7179_p3;
wire [7:0] tmp136_fu_7723_p2;
wire [7:0] e_4_1_fu_7153_p2;
wire [7:0] tmp135_fu_7728_p2;
wire [7:0] tmp134_fu_7717_p2;
wire [7:0] tmp139_fu_7746_p2;
wire [7:0] rv_5_4_1_fu_7213_p3;
wire [7:0] tmp138_fu_7751_p2;
wire [7:0] tmp137_fu_7740_p2;
wire [7:0] tmp142_fu_7769_p2;
wire [7:0] rv_8_4_1_fu_7247_p3;
wire [7:0] tmp141_fu_7774_p2;
wire [7:0] tmp140_fu_7763_p2;
wire [7:0] rv_11_4_1_fu_7281_p3;
wire [7:0] tmp144_fu_7792_p2;
wire [7:0] tmp143_fu_7786_p2;
wire [7:0] rv_2_4_2_fu_7327_p3;
wire [7:0] e_4_2_fu_7301_p2;
wire [7:0] tmp146_fu_7809_p2;
wire [7:0] tmp145_fu_7803_p2;
wire [7:0] rv_5_4_2_fu_7361_p3;
wire [7:0] tmp148_fu_7827_p2;
wire [7:0] tmp147_fu_7821_p2;
wire [7:0] rv_8_4_2_fu_7395_p3;
wire [7:0] tmp150_fu_7845_p2;
wire [7:0] tmp149_fu_7839_p2;
wire [7:0] tmp151_fu_7857_p2;
wire [7:0] rv_11_4_2_fu_7429_p3;
wire [7:0] rv_2_4_3_fu_7475_p3;
wire [7:0] e_4_3_fu_7449_p2;
wire [7:0] tmp_77_4_fu_7631_p2;
wire [7:0] tmp153_fu_7875_p2;
wire [7:0] tmp152_fu_7869_p2;
wire [7:0] rv_5_4_3_fu_7509_p3;
wire [7:0] tmp_78_4_fu_7636_p2;
wire [7:0] tmp155_fu_7893_p2;
wire [7:0] tmp154_fu_7887_p2;
wire [7:0] rv_8_4_3_fu_7543_p3;
wire [7:0] tmp_79_4_fu_7641_p2;
wire [7:0] tmp157_fu_7911_p2;
wire [7:0] tmp156_fu_7905_p2;
wire [7:0] tmp_80_4_fu_7646_p2;
wire [7:0] tmp158_fu_7923_p2;
wire [7:0] rv_11_4_3_fu_7577_p3;
wire [7:0] tmp_85_4_fu_7663_p2;
wire [7:0] tmp_85_4_1_fu_7681_p2;
wire [7:0] tmp_85_4_2_fu_7699_p2;
wire [7:0] tmp_85_4_3_fu_7711_p2;
wire [7:0] tmp_85_4_4_fu_7734_p2;
wire [7:0] tmp_85_4_5_fu_7757_p2;
wire [7:0] tmp_85_4_6_fu_7780_p2;
wire [7:0] tmp_85_4_7_fu_7797_p2;
wire [7:0] tmp_85_4_8_fu_7815_p2;
wire [7:0] tmp_85_4_9_fu_7833_p2;
wire [7:0] tmp_85_4_s_fu_7851_p2;
wire [7:0] tmp_85_4_10_fu_7863_p2;
wire [7:0] tmp_85_4_11_fu_7881_p2;
wire [7:0] tmp_85_4_12_fu_7899_p2;
wire [7:0] tmp_85_4_13_fu_7917_p2;
wire [7:0] tmp_85_4_14_fu_7929_p2;
wire [7:0] x_assign_5_fu_8035_p2;
wire [7:0] tmp_47_5_fu_8041_p2;
wire [7:0] tmp_261_fu_8053_p2;
wire [0:0] tmp_262_fu_8059_p3;
wire [7:0] rv_1_5_fu_8067_p2;
wire [7:0] x_assign_1_5_fu_8081_p2;
wire [7:0] tmp_263_fu_8087_p2;
wire [0:0] tmp_264_fu_8093_p3;
wire [7:0] rv_4_5_fu_8101_p2;
wire [7:0] x_assign_2_5_fu_8115_p2;
wire [7:0] tmp_265_fu_8121_p2;
wire [0:0] tmp_266_fu_8127_p3;
wire [7:0] rv_7_5_fu_8135_p2;
wire [7:0] x_assign_3_5_fu_8149_p2;
wire [7:0] tmp_267_fu_8155_p2;
wire [0:0] tmp_268_fu_8161_p3;
wire [7:0] rv_10_5_fu_8169_p2;
wire [7:0] x_assign_5_1_fu_8183_p2;
wire [7:0] tmp_47_5_1_fu_8189_p2;
wire [7:0] tmp_269_fu_8201_p2;
wire [0:0] tmp_270_fu_8207_p3;
wire [7:0] rv_1_5_1_fu_8215_p2;
wire [7:0] x_assign_1_5_1_fu_8229_p2;
wire [7:0] tmp_271_fu_8235_p2;
wire [0:0] tmp_272_fu_8241_p3;
wire [7:0] rv_4_5_1_fu_8249_p2;
wire [7:0] x_assign_2_5_1_fu_8263_p2;
wire [7:0] tmp_273_fu_8269_p2;
wire [0:0] tmp_274_fu_8275_p3;
wire [7:0] rv_7_5_1_fu_8283_p2;
wire [7:0] x_assign_3_5_1_fu_8297_p2;
wire [7:0] tmp_275_fu_8303_p2;
wire [0:0] tmp_276_fu_8309_p3;
wire [7:0] rv_10_5_1_fu_8317_p2;
wire [7:0] x_assign_5_2_fu_8331_p2;
wire [7:0] tmp_47_5_2_fu_8337_p2;
wire [7:0] tmp_277_fu_8349_p2;
wire [0:0] tmp_278_fu_8355_p3;
wire [7:0] rv_1_5_2_fu_8363_p2;
wire [7:0] x_assign_1_5_2_fu_8377_p2;
wire [7:0] tmp_279_fu_8383_p2;
wire [0:0] tmp_280_fu_8389_p3;
wire [7:0] rv_4_5_2_fu_8397_p2;
wire [7:0] x_assign_2_5_2_fu_8411_p2;
wire [7:0] tmp_281_fu_8417_p2;
wire [0:0] tmp_282_fu_8423_p3;
wire [7:0] rv_7_5_2_fu_8431_p2;
wire [7:0] x_assign_3_5_2_fu_8445_p2;
wire [7:0] tmp_283_fu_8451_p2;
wire [0:0] tmp_284_fu_8457_p3;
wire [7:0] rv_10_5_2_fu_8465_p2;
wire [7:0] x_assign_5_3_fu_8479_p2;
wire [7:0] tmp_47_5_3_fu_8485_p2;
wire [7:0] tmp_285_fu_8497_p2;
wire [0:0] tmp_286_fu_8503_p3;
wire [7:0] rv_1_5_3_fu_8511_p2;
wire [7:0] x_assign_1_5_3_fu_8525_p2;
wire [7:0] tmp_287_fu_8531_p2;
wire [0:0] tmp_288_fu_8537_p3;
wire [7:0] rv_4_5_3_fu_8545_p2;
wire [7:0] x_assign_2_5_3_fu_8559_p2;
wire [7:0] tmp_289_fu_8565_p2;
wire [0:0] tmp_290_fu_8571_p3;
wire [7:0] rv_7_5_3_fu_8579_p2;
wire [7:0] x_assign_3_5_3_fu_8593_p2;
wire [7:0] tmp_291_fu_8599_p2;
wire [0:0] tmp_292_fu_8605_p3;
wire [7:0] rv_10_5_3_fu_8613_p2;
wire [7:0] tmp_64_5_fu_8627_p2;
wire [7:0] rv_2_5_fu_8073_p3;
wire [7:0] e_5_fu_8047_p2;
wire [7:0] tmp160_fu_8699_p2;
wire [7:0] tmp159_fu_8693_p2;
wire [7:0] rv_5_5_fu_8107_p3;
wire [7:0] tmp162_fu_8717_p2;
wire [7:0] tmp161_fu_8711_p2;
wire [7:0] rv_8_5_fu_8141_p3;
wire [7:0] tmp164_fu_8735_p2;
wire [7:0] tmp163_fu_8729_p2;
wire [7:0] tmp165_fu_8747_p2;
wire [7:0] rv_11_5_fu_8175_p3;
wire [7:0] rv_2_5_1_fu_8221_p3;
wire [7:0] e_5_1_fu_8195_p2;
wire [7:0] tmp167_fu_8765_p2;
wire [7:0] tmp166_fu_8759_p2;
wire [7:0] rv_5_5_1_fu_8255_p3;
wire [7:0] tmp169_fu_8783_p2;
wire [7:0] tmp168_fu_8777_p2;
wire [7:0] rv_8_5_1_fu_8289_p3;
wire [7:0] tmp171_fu_8801_p2;
wire [7:0] tmp170_fu_8795_p2;
wire [7:0] tmp172_fu_8813_p2;
wire [7:0] rv_11_5_1_fu_8323_p3;
wire [7:0] rv_2_5_2_fu_8369_p3;
wire [7:0] tmp175_fu_8831_p2;
wire [7:0] e_5_2_fu_8343_p2;
wire [7:0] tmp174_fu_8836_p2;
wire [7:0] tmp173_fu_8825_p2;
wire [7:0] tmp178_fu_8854_p2;
wire [7:0] rv_5_5_2_fu_8403_p3;
wire [7:0] tmp177_fu_8859_p2;
wire [7:0] tmp176_fu_8848_p2;
wire [7:0] tmp181_fu_8877_p2;
wire [7:0] rv_8_5_2_fu_8437_p3;
wire [7:0] tmp180_fu_8882_p2;
wire [7:0] tmp179_fu_8871_p2;
wire [7:0] rv_11_5_2_fu_8471_p3;
wire [7:0] tmp183_fu_8900_p2;
wire [7:0] tmp182_fu_8894_p2;
wire [7:0] rv_2_5_3_fu_8517_p3;
wire [7:0] e_5_3_fu_8491_p2;
wire [7:0] tmp185_fu_8917_p2;
wire [7:0] tmp184_fu_8911_p2;
wire [7:0] rv_5_5_3_fu_8551_p3;
wire [7:0] tmp187_fu_8935_p2;
wire [7:0] tmp186_fu_8929_p2;
wire [7:0] rv_8_5_3_fu_8585_p3;
wire [7:0] tmp189_fu_8953_p2;
wire [7:0] tmp188_fu_8947_p2;
wire [7:0] tmp190_fu_8965_p2;
wire [7:0] rv_11_5_3_fu_8619_p3;
wire [7:0] tmp_85_5_fu_8705_p2;
wire [7:0] tmp_85_5_1_fu_8723_p2;
wire [7:0] tmp_85_5_2_fu_8741_p2;
wire [7:0] tmp_85_5_3_fu_8753_p2;
wire [7:0] tmp_85_5_4_fu_8771_p2;
wire [7:0] tmp_85_5_5_fu_8789_p2;
wire [7:0] tmp_85_5_6_fu_8807_p2;
wire [7:0] tmp_85_5_7_fu_8819_p2;
wire [7:0] tmp_85_5_8_fu_8842_p2;
wire [7:0] tmp_85_5_9_fu_8865_p2;
wire [7:0] tmp_85_5_s_fu_8888_p2;
wire [7:0] tmp_85_5_10_fu_8905_p2;
wire [7:0] tmp_85_5_11_fu_8923_p2;
wire [7:0] tmp_85_5_12_fu_8941_p2;
wire [7:0] tmp_85_5_13_fu_8959_p2;
wire [7:0] tmp_85_5_14_fu_8971_p2;
wire [7:0] x_assign_6_fu_9077_p2;
wire [7:0] tmp_47_6_fu_9083_p2;
wire [7:0] tmp_293_fu_9095_p2;
wire [0:0] tmp_294_fu_9101_p3;
wire [7:0] rv_1_6_fu_9109_p2;
wire [7:0] x_assign_1_6_fu_9123_p2;
wire [7:0] tmp_295_fu_9129_p2;
wire [0:0] tmp_296_fu_9135_p3;
wire [7:0] rv_4_6_fu_9143_p2;
wire [7:0] x_assign_2_6_fu_9157_p2;
wire [7:0] tmp_297_fu_9163_p2;
wire [0:0] tmp_298_fu_9169_p3;
wire [7:0] rv_7_6_fu_9177_p2;
wire [7:0] x_assign_3_6_fu_9191_p2;
wire [7:0] tmp_299_fu_9197_p2;
wire [0:0] tmp_300_fu_9203_p3;
wire [7:0] rv_10_6_fu_9211_p2;
wire [7:0] x_assign_6_1_fu_9225_p2;
wire [7:0] tmp_47_6_1_fu_9231_p2;
wire [7:0] tmp_301_fu_9243_p2;
wire [0:0] tmp_302_fu_9249_p3;
wire [7:0] rv_1_6_1_fu_9257_p2;
wire [7:0] x_assign_1_6_1_fu_9271_p2;
wire [7:0] tmp_303_fu_9277_p2;
wire [0:0] tmp_304_fu_9283_p3;
wire [7:0] rv_4_6_1_fu_9291_p2;
wire [7:0] x_assign_2_6_1_fu_9305_p2;
wire [7:0] tmp_305_fu_9311_p2;
wire [0:0] tmp_306_fu_9317_p3;
wire [7:0] rv_7_6_1_fu_9325_p2;
wire [7:0] x_assign_3_6_1_fu_9339_p2;
wire [7:0] tmp_307_fu_9345_p2;
wire [0:0] tmp_308_fu_9351_p3;
wire [7:0] rv_10_6_1_fu_9359_p2;
wire [7:0] x_assign_6_2_fu_9373_p2;
wire [7:0] tmp_47_6_2_fu_9379_p2;
wire [7:0] tmp_309_fu_9391_p2;
wire [0:0] tmp_310_fu_9397_p3;
wire [7:0] rv_1_6_2_fu_9405_p2;
wire [7:0] x_assign_1_6_2_fu_9419_p2;
wire [7:0] tmp_311_fu_9425_p2;
wire [0:0] tmp_312_fu_9431_p3;
wire [7:0] rv_4_6_2_fu_9439_p2;
wire [7:0] x_assign_2_6_2_fu_9453_p2;
wire [7:0] tmp_313_fu_9459_p2;
wire [0:0] tmp_314_fu_9465_p3;
wire [7:0] rv_7_6_2_fu_9473_p2;
wire [7:0] x_assign_3_6_2_fu_9487_p2;
wire [7:0] tmp_315_fu_9493_p2;
wire [0:0] tmp_316_fu_9499_p3;
wire [7:0] rv_10_6_2_fu_9507_p2;
wire [7:0] x_assign_6_3_fu_9521_p2;
wire [7:0] tmp_47_6_3_fu_9527_p2;
wire [7:0] tmp_317_fu_9539_p2;
wire [0:0] tmp_318_fu_9545_p3;
wire [7:0] rv_1_6_3_fu_9553_p2;
wire [7:0] x_assign_1_6_3_fu_9567_p2;
wire [7:0] tmp_319_fu_9573_p2;
wire [0:0] tmp_320_fu_9579_p3;
wire [7:0] rv_4_6_3_fu_9587_p2;
wire [7:0] x_assign_2_6_3_fu_9601_p2;
wire [7:0] tmp_321_fu_9607_p2;
wire [0:0] tmp_322_fu_9613_p3;
wire [7:0] rv_7_6_3_fu_9621_p2;
wire [7:0] x_assign_3_6_3_fu_9635_p2;
wire [7:0] tmp_323_fu_9641_p2;
wire [0:0] tmp_324_fu_9647_p3;
wire [7:0] rv_10_6_3_fu_9655_p2;
wire [7:0] tmp191_fu_9669_p2;
wire [7:0] rv_2_6_fu_9115_p3;
wire [7:0] e_6_fu_9089_p2;
wire [7:0] tmp193_fu_9741_p2;
wire [7:0] tmp192_fu_9735_p2;
wire [7:0] rv_5_6_fu_9149_p3;
wire [7:0] tmp195_fu_9759_p2;
wire [7:0] tmp194_fu_9753_p2;
wire [7:0] rv_8_6_fu_9183_p3;
wire [7:0] tmp197_fu_9777_p2;
wire [7:0] tmp196_fu_9771_p2;
wire [7:0] tmp198_fu_9789_p2;
wire [7:0] rv_11_6_fu_9217_p3;
wire [7:0] rv_2_6_1_fu_9263_p3;
wire [7:0] tmp201_fu_9807_p2;
wire [7:0] e_6_1_fu_9237_p2;
wire [7:0] tmp200_fu_9812_p2;
wire [7:0] tmp199_fu_9801_p2;
wire [7:0] tmp204_fu_9830_p2;
wire [7:0] rv_5_6_1_fu_9297_p3;
wire [7:0] tmp203_fu_9835_p2;
wire [7:0] tmp202_fu_9824_p2;
wire [7:0] tmp207_fu_9853_p2;
wire [7:0] rv_8_6_1_fu_9331_p3;
wire [7:0] tmp206_fu_9858_p2;
wire [7:0] tmp205_fu_9847_p2;
wire [7:0] rv_11_6_1_fu_9365_p3;
wire [7:0] tmp209_fu_9876_p2;
wire [7:0] tmp208_fu_9870_p2;
wire [7:0] rv_2_6_2_fu_9411_p3;
wire [7:0] e_6_2_fu_9385_p2;
wire [7:0] tmp211_fu_9893_p2;
wire [7:0] tmp210_fu_9887_p2;
wire [7:0] rv_5_6_2_fu_9445_p3;
wire [7:0] tmp213_fu_9911_p2;
wire [7:0] tmp212_fu_9905_p2;
wire [7:0] rv_8_6_2_fu_9479_p3;
wire [7:0] tmp215_fu_9929_p2;
wire [7:0] tmp214_fu_9923_p2;
wire [7:0] tmp216_fu_9941_p2;
wire [7:0] rv_11_6_2_fu_9513_p3;
wire [7:0] rv_2_6_3_fu_9559_p3;
wire [7:0] e_6_3_fu_9533_p2;
wire [7:0] tmp_77_6_fu_9715_p2;
wire [7:0] tmp218_fu_9959_p2;
wire [7:0] tmp217_fu_9953_p2;
wire [7:0] rv_5_6_3_fu_9593_p3;
wire [7:0] tmp_78_6_fu_9720_p2;
wire [7:0] tmp220_fu_9977_p2;
wire [7:0] tmp219_fu_9971_p2;
wire [7:0] rv_8_6_3_fu_9627_p3;
wire [7:0] tmp_79_6_fu_9725_p2;
wire [7:0] tmp222_fu_9995_p2;
wire [7:0] tmp221_fu_9989_p2;
wire [7:0] tmp_80_6_fu_9730_p2;
wire [7:0] tmp223_fu_10007_p2;
wire [7:0] rv_11_6_3_fu_9661_p3;
wire [7:0] tmp_85_6_fu_9747_p2;
wire [7:0] tmp_85_6_1_fu_9765_p2;
wire [7:0] tmp_85_6_2_fu_9783_p2;
wire [7:0] tmp_85_6_3_fu_9795_p2;
wire [7:0] tmp_85_6_4_fu_9818_p2;
wire [7:0] tmp_85_6_5_fu_9841_p2;
wire [7:0] tmp_85_6_6_fu_9864_p2;
wire [7:0] tmp_85_6_7_fu_9881_p2;
wire [7:0] tmp_85_6_8_fu_9899_p2;
wire [7:0] tmp_85_6_9_fu_9917_p2;
wire [7:0] tmp_85_6_s_fu_9935_p2;
wire [7:0] tmp_85_6_10_fu_9947_p2;
wire [7:0] tmp_85_6_11_fu_9965_p2;
wire [7:0] tmp_85_6_12_fu_9983_p2;
wire [7:0] tmp_85_6_13_fu_10001_p2;
wire [7:0] tmp_85_6_14_fu_10013_p2;
wire [7:0] x_assign_7_fu_10119_p2;
wire [7:0] tmp_47_7_fu_10125_p2;
wire [7:0] tmp_325_fu_10137_p2;
wire [0:0] tmp_326_fu_10143_p3;
wire [7:0] rv_1_7_fu_10151_p2;
wire [7:0] x_assign_1_7_fu_10165_p2;
wire [7:0] tmp_327_fu_10171_p2;
wire [0:0] tmp_328_fu_10177_p3;
wire [7:0] rv_4_7_fu_10185_p2;
wire [7:0] x_assign_2_7_fu_10199_p2;
wire [7:0] tmp_329_fu_10205_p2;
wire [0:0] tmp_330_fu_10211_p3;
wire [7:0] rv_7_7_fu_10219_p2;
wire [7:0] x_assign_3_7_fu_10233_p2;
wire [7:0] tmp_331_fu_10239_p2;
wire [0:0] tmp_332_fu_10245_p3;
wire [7:0] rv_10_7_fu_10253_p2;
wire [7:0] x_assign_7_1_fu_10267_p2;
wire [7:0] tmp_47_7_1_fu_10273_p2;
wire [7:0] tmp_333_fu_10285_p2;
wire [0:0] tmp_334_fu_10291_p3;
wire [7:0] rv_1_7_1_fu_10299_p2;
wire [7:0] x_assign_1_7_1_fu_10313_p2;
wire [7:0] tmp_335_fu_10319_p2;
wire [0:0] tmp_336_fu_10325_p3;
wire [7:0] rv_4_7_1_fu_10333_p2;
wire [7:0] x_assign_2_7_1_fu_10347_p2;
wire [7:0] tmp_337_fu_10353_p2;
wire [0:0] tmp_338_fu_10359_p3;
wire [7:0] rv_7_7_1_fu_10367_p2;
wire [7:0] x_assign_3_7_1_fu_10381_p2;
wire [7:0] tmp_339_fu_10387_p2;
wire [0:0] tmp_340_fu_10393_p3;
wire [7:0] rv_10_7_1_fu_10401_p2;
wire [7:0] x_assign_7_2_fu_10415_p2;
wire [7:0] tmp_47_7_2_fu_10421_p2;
wire [7:0] tmp_341_fu_10433_p2;
wire [0:0] tmp_342_fu_10439_p3;
wire [7:0] rv_1_7_2_fu_10447_p2;
wire [7:0] x_assign_1_7_2_fu_10461_p2;
wire [7:0] tmp_343_fu_10467_p2;
wire [0:0] tmp_344_fu_10473_p3;
wire [7:0] rv_4_7_2_fu_10481_p2;
wire [7:0] x_assign_2_7_2_fu_10495_p2;
wire [7:0] tmp_345_fu_10501_p2;
wire [0:0] tmp_346_fu_10507_p3;
wire [7:0] rv_7_7_2_fu_10515_p2;
wire [7:0] x_assign_3_7_2_fu_10529_p2;
wire [7:0] tmp_347_fu_10535_p2;
wire [0:0] tmp_348_fu_10541_p3;
wire [7:0] rv_10_7_2_fu_10549_p2;
wire [7:0] x_assign_7_3_fu_10563_p2;
wire [7:0] tmp_47_7_3_fu_10569_p2;
wire [7:0] tmp_349_fu_10581_p2;
wire [0:0] tmp_350_fu_10587_p3;
wire [7:0] rv_1_7_3_fu_10595_p2;
wire [7:0] x_assign_1_7_3_fu_10609_p2;
wire [7:0] tmp_351_fu_10615_p2;
wire [0:0] tmp_352_fu_10621_p3;
wire [7:0] rv_4_7_3_fu_10629_p2;
wire [7:0] x_assign_2_7_3_fu_10643_p2;
wire [7:0] tmp_353_fu_10649_p2;
wire [0:0] tmp_354_fu_10655_p3;
wire [7:0] rv_7_7_3_fu_10663_p2;
wire [7:0] x_assign_3_7_3_fu_10677_p2;
wire [7:0] tmp_355_fu_10683_p2;
wire [0:0] tmp_356_fu_10689_p3;
wire [7:0] rv_10_7_3_fu_10697_p2;
wire [7:0] tmp_64_7_fu_10711_p2;
wire [7:0] rv_2_7_fu_10157_p3;
wire [7:0] e_7_fu_10131_p2;
wire [7:0] tmp225_fu_10783_p2;
wire [7:0] tmp224_fu_10777_p2;
wire [7:0] rv_5_7_fu_10191_p3;
wire [7:0] tmp227_fu_10801_p2;
wire [7:0] tmp226_fu_10795_p2;
wire [7:0] rv_8_7_fu_10225_p3;
wire [7:0] tmp229_fu_10819_p2;
wire [7:0] tmp228_fu_10813_p2;
wire [7:0] tmp230_fu_10831_p2;
wire [7:0] rv_11_7_fu_10259_p3;
wire [7:0] rv_2_7_1_fu_10305_p3;
wire [7:0] e_7_1_fu_10279_p2;
wire [7:0] tmp232_fu_10849_p2;
wire [7:0] tmp231_fu_10843_p2;
wire [7:0] rv_5_7_1_fu_10339_p3;
wire [7:0] tmp234_fu_10867_p2;
wire [7:0] tmp233_fu_10861_p2;
wire [7:0] rv_8_7_1_fu_10373_p3;
wire [7:0] tmp236_fu_10885_p2;
wire [7:0] tmp235_fu_10879_p2;
wire [7:0] tmp237_fu_10897_p2;
wire [7:0] rv_11_7_1_fu_10407_p3;
wire [7:0] rv_2_7_2_fu_10453_p3;
wire [7:0] tmp240_fu_10915_p2;
wire [7:0] e_7_2_fu_10427_p2;
wire [7:0] tmp239_fu_10920_p2;
wire [7:0] tmp238_fu_10909_p2;
wire [7:0] tmp243_fu_10938_p2;
wire [7:0] rv_5_7_2_fu_10487_p3;
wire [7:0] tmp242_fu_10943_p2;
wire [7:0] tmp241_fu_10932_p2;
wire [7:0] tmp246_fu_10961_p2;
wire [7:0] rv_8_7_2_fu_10521_p3;
wire [7:0] tmp245_fu_10966_p2;
wire [7:0] tmp244_fu_10955_p2;
wire [7:0] rv_11_7_2_fu_10555_p3;
wire [7:0] tmp248_fu_10984_p2;
wire [7:0] tmp247_fu_10978_p2;
wire [7:0] rv_2_7_3_fu_10601_p3;
wire [7:0] e_7_3_fu_10575_p2;
wire [7:0] tmp250_fu_11001_p2;
wire [7:0] tmp249_fu_10995_p2;
wire [7:0] rv_5_7_3_fu_10635_p3;
wire [7:0] tmp252_fu_11019_p2;
wire [7:0] tmp251_fu_11013_p2;
wire [7:0] rv_8_7_3_fu_10669_p3;
wire [7:0] tmp254_fu_11037_p2;
wire [7:0] tmp253_fu_11031_p2;
wire [7:0] tmp255_fu_11049_p2;
wire [7:0] rv_11_7_3_fu_10703_p3;
wire [7:0] tmp_85_7_fu_10789_p2;
wire [7:0] tmp_85_7_1_fu_10807_p2;
wire [7:0] tmp_85_7_2_fu_10825_p2;
wire [7:0] tmp_85_7_3_fu_10837_p2;
wire [7:0] tmp_85_7_4_fu_10855_p2;
wire [7:0] tmp_85_7_5_fu_10873_p2;
wire [7:0] tmp_85_7_6_fu_10891_p2;
wire [7:0] tmp_85_7_7_fu_10903_p2;
wire [7:0] tmp_85_7_8_fu_10926_p2;
wire [7:0] tmp_85_7_9_fu_10949_p2;
wire [7:0] tmp_85_7_s_fu_10972_p2;
wire [7:0] tmp_85_7_10_fu_10989_p2;
wire [7:0] tmp_85_7_11_fu_11007_p2;
wire [7:0] tmp_85_7_12_fu_11025_p2;
wire [7:0] tmp_85_7_13_fu_11043_p2;
wire [7:0] tmp_85_7_14_fu_11055_p2;
wire [7:0] x_assign_8_fu_11161_p2;
wire [7:0] tmp_47_8_fu_11167_p2;
wire [7:0] tmp_357_fu_11179_p2;
wire [0:0] tmp_358_fu_11185_p3;
wire [7:0] rv_1_8_fu_11193_p2;
wire [7:0] x_assign_1_8_fu_11207_p2;
wire [7:0] tmp_359_fu_11213_p2;
wire [0:0] tmp_360_fu_11219_p3;
wire [7:0] rv_4_8_fu_11227_p2;
wire [7:0] x_assign_2_8_fu_11241_p2;
wire [7:0] tmp_361_fu_11247_p2;
wire [0:0] tmp_362_fu_11253_p3;
wire [7:0] rv_7_8_fu_11261_p2;
wire [7:0] x_assign_3_8_fu_11275_p2;
wire [7:0] tmp_363_fu_11281_p2;
wire [0:0] tmp_364_fu_11287_p3;
wire [7:0] rv_10_8_fu_11295_p2;
wire [7:0] x_assign_8_1_fu_11309_p2;
wire [7:0] tmp_47_8_1_fu_11315_p2;
wire [7:0] tmp_365_fu_11327_p2;
wire [0:0] tmp_366_fu_11333_p3;
wire [7:0] rv_1_8_1_fu_11341_p2;
wire [7:0] x_assign_1_8_1_fu_11355_p2;
wire [7:0] tmp_367_fu_11361_p2;
wire [0:0] tmp_368_fu_11367_p3;
wire [7:0] rv_4_8_1_fu_11375_p2;
wire [7:0] x_assign_2_8_1_fu_11389_p2;
wire [7:0] tmp_369_fu_11395_p2;
wire [0:0] tmp_370_fu_11401_p3;
wire [7:0] rv_7_8_1_fu_11409_p2;
wire [7:0] x_assign_3_8_1_fu_11423_p2;
wire [7:0] tmp_371_fu_11429_p2;
wire [0:0] tmp_372_fu_11435_p3;
wire [7:0] rv_10_8_1_fu_11443_p2;
wire [7:0] x_assign_8_2_fu_11457_p2;
wire [7:0] tmp_47_8_2_fu_11463_p2;
wire [7:0] tmp_373_fu_11475_p2;
wire [0:0] tmp_374_fu_11481_p3;
wire [7:0] rv_1_8_2_fu_11489_p2;
wire [7:0] x_assign_1_8_2_fu_11503_p2;
wire [7:0] tmp_375_fu_11509_p2;
wire [0:0] tmp_376_fu_11515_p3;
wire [7:0] rv_4_8_2_fu_11523_p2;
wire [7:0] x_assign_2_8_2_fu_11537_p2;
wire [7:0] tmp_377_fu_11543_p2;
wire [0:0] tmp_378_fu_11549_p3;
wire [7:0] rv_7_8_2_fu_11557_p2;
wire [7:0] x_assign_3_8_2_fu_11571_p2;
wire [7:0] tmp_379_fu_11577_p2;
wire [0:0] tmp_380_fu_11583_p3;
wire [7:0] rv_10_8_2_fu_11591_p2;
wire [7:0] x_assign_8_3_fu_11605_p2;
wire [7:0] tmp_47_8_3_fu_11611_p2;
wire [7:0] tmp_381_fu_11623_p2;
wire [0:0] tmp_382_fu_11629_p3;
wire [7:0] rv_1_8_3_fu_11637_p2;
wire [7:0] x_assign_1_8_3_fu_11651_p2;
wire [7:0] tmp_383_fu_11657_p2;
wire [0:0] tmp_384_fu_11663_p3;
wire [7:0] rv_4_8_3_fu_11671_p2;
wire [7:0] x_assign_2_8_3_fu_11685_p2;
wire [7:0] tmp_385_fu_11691_p2;
wire [0:0] tmp_386_fu_11697_p3;
wire [7:0] rv_7_8_3_fu_11705_p2;
wire [7:0] x_assign_3_8_3_fu_11719_p2;
wire [7:0] tmp_387_fu_11725_p2;
wire [0:0] tmp_388_fu_11731_p3;
wire [7:0] rv_10_8_3_fu_11739_p2;
wire [7:0] tmp256_fu_11753_p2;
wire [7:0] rv_2_8_fu_11199_p3;
wire [7:0] e_8_fu_11173_p2;
wire [7:0] tmp258_fu_11825_p2;
wire [7:0] tmp257_fu_11819_p2;
wire [7:0] rv_5_8_fu_11233_p3;
wire [7:0] tmp260_fu_11843_p2;
wire [7:0] tmp259_fu_11837_p2;
wire [7:0] rv_8_8_fu_11267_p3;
wire [7:0] tmp262_fu_11861_p2;
wire [7:0] tmp261_fu_11855_p2;
wire [7:0] tmp263_fu_11873_p2;
wire [7:0] rv_11_8_fu_11301_p3;
wire [7:0] rv_2_8_1_fu_11347_p3;
wire [7:0] tmp266_fu_11891_p2;
wire [7:0] e_8_1_fu_11321_p2;
wire [7:0] tmp265_fu_11896_p2;
wire [7:0] tmp264_fu_11885_p2;
wire [7:0] tmp269_fu_11914_p2;
wire [7:0] rv_5_8_1_fu_11381_p3;
wire [7:0] tmp268_fu_11919_p2;
wire [7:0] tmp267_fu_11908_p2;
wire [7:0] tmp272_fu_11937_p2;
wire [7:0] rv_8_8_1_fu_11415_p3;
wire [7:0] tmp271_fu_11942_p2;
wire [7:0] tmp270_fu_11931_p2;
wire [7:0] rv_11_8_1_fu_11449_p3;
wire [7:0] tmp274_fu_11960_p2;
wire [7:0] tmp273_fu_11954_p2;
wire [7:0] rv_2_8_2_fu_11495_p3;
wire [7:0] e_8_2_fu_11469_p2;
wire [7:0] tmp276_fu_11977_p2;
wire [7:0] tmp275_fu_11971_p2;
wire [7:0] rv_5_8_2_fu_11529_p3;
wire [7:0] tmp278_fu_11995_p2;
wire [7:0] tmp277_fu_11989_p2;
wire [7:0] rv_8_8_2_fu_11563_p3;
wire [7:0] tmp280_fu_12013_p2;
wire [7:0] tmp279_fu_12007_p2;
wire [7:0] tmp281_fu_12025_p2;
wire [7:0] rv_11_8_2_fu_11597_p3;
wire [7:0] rv_2_8_3_fu_11643_p3;
wire [7:0] e_8_3_fu_11617_p2;
wire [7:0] tmp_77_8_fu_11799_p2;
wire [7:0] tmp283_fu_12043_p2;
wire [7:0] tmp282_fu_12037_p2;
wire [7:0] rv_5_8_3_fu_11677_p3;
wire [7:0] tmp_78_8_fu_11804_p2;
wire [7:0] tmp285_fu_12061_p2;
wire [7:0] tmp284_fu_12055_p2;
wire [7:0] rv_8_8_3_fu_11711_p3;
wire [7:0] tmp_79_8_fu_11809_p2;
wire [7:0] tmp287_fu_12079_p2;
wire [7:0] tmp286_fu_12073_p2;
wire [7:0] tmp_80_8_fu_11814_p2;
wire [7:0] tmp288_fu_12091_p2;
wire [7:0] rv_11_8_3_fu_11745_p3;
wire [7:0] tmp_85_8_fu_11831_p2;
wire [7:0] tmp_85_8_1_fu_11849_p2;
wire [7:0] tmp_85_8_2_fu_11867_p2;
wire [7:0] tmp_85_8_3_fu_11879_p2;
wire [7:0] tmp_85_8_4_fu_11902_p2;
wire [7:0] tmp_85_8_5_fu_11925_p2;
wire [7:0] tmp_85_8_6_fu_11948_p2;
wire [7:0] tmp_85_8_7_fu_11965_p2;
wire [7:0] tmp_85_8_8_fu_11983_p2;
wire [7:0] tmp_85_8_9_fu_12001_p2;
wire [7:0] tmp_85_8_s_fu_12019_p2;
wire [7:0] tmp_85_8_10_fu_12031_p2;
wire [7:0] tmp_85_8_11_fu_12049_p2;
wire [7:0] tmp_85_8_12_fu_12067_p2;
wire [7:0] tmp_85_8_13_fu_12085_p2;
wire [7:0] tmp_85_8_14_fu_12097_p2;
wire [7:0] tmp_4_fu_12203_p2;
wire [7:0] tmp289_fu_12229_p2;
wire [7:0] tmp290_fu_12240_p2;
wire [7:0] tmp291_fu_12251_p2;
wire [7:0] tmp292_fu_12262_p2;
wire [7:0] tmp_9_fu_12209_p2;
wire [7:0] tmp_11_fu_12214_p2;
wire [7:0] tmp_12_fu_12219_p2;
wire [7:0] tmp_13_fu_12224_p2;
wire [7:0] tmp293_fu_12297_p2;
wire [7:0] tmp294_fu_12308_p2;
wire [7:0] tmp295_fu_12319_p2;
wire [7:0] tmp296_fu_12330_p2;
wire [7:0] tmp297_fu_12341_p2;
wire [7:0] tmp298_fu_12352_p2;
wire [7:0] tmp299_fu_12363_p2;
wire [7:0] tmp300_fu_12374_p2;
wire [7:0] tmp_38_fu_12234_p2;
wire [7:0] tmp_38_1_fu_12245_p2;
wire [7:0] tmp_38_2_fu_12256_p2;
wire [7:0] tmp_38_3_fu_12267_p2;
wire [7:0] tmp_38_4_fu_12273_p2;
wire [7:0] tmp_38_5_fu_12279_p2;
wire [7:0] tmp_38_6_fu_12285_p2;
wire [7:0] tmp_38_7_fu_12291_p2;
wire [7:0] tmp_38_8_fu_12302_p2;
wire [7:0] tmp_38_9_fu_12313_p2;
wire [7:0] tmp_38_s_fu_12324_p2;
wire [7:0] tmp_38_10_fu_12335_p2;
wire [7:0] tmp_38_11_fu_12346_p2;
wire [7:0] tmp_38_12_fu_12357_p2;
wire [7:0] tmp_38_13_fu_12368_p2;
wire [7:0] tmp_38_14_fu_12379_p2;
reg [0:0] ap_NS_fsm;
reg ap_idle_pp0_0to9;
reg ap_reset_idle_pp0;
reg ap_reset_start_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 ap_CS_fsm = 1'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
#0 ap_enable_reg_pp0_iter5 = 1'b0;
#0 ap_enable_reg_pp0_iter6 = 1'b0;
#0 ap_enable_reg_pp0_iter7 = 1'b0;
#0 ap_enable_reg_pp0_iter8 = 1'b0;
#0 ap_enable_reg_pp0_iter9 = 1'b0;
#0 ap_enable_reg_pp0_iter10 = 1'b0;
end
aestest_sboxes #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
sboxes_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(sboxes_address0),
.ce0(sboxes_ce0),
.q0(sboxes_q0),
.address1(sboxes_address1),
.ce1(sboxes_ce1),
.q1(sboxes_q1),
.address2(sboxes_address2),
.ce2(sboxes_ce2),
.q2(sboxes_q2),
.address3(sboxes_address3),
.ce3(sboxes_ce3),
.q3(sboxes_q3),
.address4(sboxes_address4),
.ce4(sboxes_ce4),
.q4(sboxes_q4),
.address5(sboxes_address5),
.ce5(sboxes_ce5),
.q5(sboxes_q5),
.address6(sboxes_address6),
.ce6(sboxes_ce6),
.q6(sboxes_q6),
.address7(sboxes_address7),
.ce7(sboxes_ce7),
.q7(sboxes_q7),
.address8(sboxes_address8),
.ce8(sboxes_ce8),
.q8(sboxes_q8),
.address9(sboxes_address9),
.ce9(sboxes_ce9),
.q9(sboxes_q9),
.address10(sboxes_address10),
.ce10(sboxes_ce10),
.q10(sboxes_q10),
.address11(sboxes_address11),
.ce11(sboxes_ce11),
.q11(sboxes_q11),
.address12(sboxes_address12),
.ce12(sboxes_ce12),
.q12(sboxes_q12),
.address13(sboxes_address13),
.ce13(sboxes_ce13),
.q13(sboxes_q13),
.address14(sboxes_address14),
.ce14(sboxes_ce14),
.q14(sboxes_q14),
.address15(sboxes_address15),
.ce15(sboxes_ce15),
.q15(sboxes_q15),
.address16(sboxes_address16),
.ce16(sboxes_ce16),
.q16(sboxes_q16),
.address17(sboxes_address17),
.ce17(sboxes_ce17),
.q17(sboxes_q17),
.address18(sboxes_address18),
.ce18(sboxes_ce18),
.q18(sboxes_q18),
.address19(sboxes_address19),
.ce19(sboxes_ce19),
.q19(sboxes_q19),
.address20(sboxes_address20),
.ce20(sboxes_ce20),
.q20(sboxes_q20),
.address21(sboxes_address21),
.ce21(sboxes_ce21),
.q21(sboxes_q21),
.address22(sboxes_address22),
.ce22(sboxes_ce22),
.q22(sboxes_q22),
.address23(sboxes_address23),
.ce23(sboxes_ce23),
.q23(sboxes_q23),
.address24(sboxes_address24),
.ce24(sboxes_ce24),
.q24(sboxes_q24),
.address25(sboxes_address25),
.ce25(sboxes_ce25),
.q25(sboxes_q25),
.address26(sboxes_address26),
.ce26(sboxes_ce26),
.q26(sboxes_q26),
.address27(sboxes_address27),
.ce27(sboxes_ce27),
.q27(sboxes_q27),
.address28(sboxes_address28),
.ce28(sboxes_ce28),
.q28(sboxes_q28),
.address29(sboxes_address29),
.ce29(sboxes_ce29),
.q29(sboxes_q29),
.address30(sboxes_address30),
.ce30(sboxes_ce30),
.q30(sboxes_q30),
.address31(sboxes_address31),
.ce31(sboxes_ce31),
.q31(sboxes_q31),
.address32(sboxes_address32),
.ce32(sboxes_ce32),
.q32(sboxes_q32),
.address33(sboxes_address33),
.ce33(sboxes_ce33),
.q33(sboxes_q33),
.address34(sboxes_address34),
.ce34(sboxes_ce34),
.q34(sboxes_q34),
.address35(sboxes_address35),
.ce35(sboxes_ce35),
.q35(sboxes_q35),
.address36(sboxes_address36),
.ce36(sboxes_ce36),
.q36(sboxes_q36),
.address37(sboxes_address37),
.ce37(sboxes_ce37),
.q37(sboxes_q37),
.address38(sboxes_address38),
.ce38(sboxes_ce38),
.q38(sboxes_q38),
.address39(sboxes_address39),
.ce39(sboxes_ce39),
.q39(sboxes_q39),
.address40(sboxes_address40),
.ce40(sboxes_ce40),
.q40(sboxes_q40),
.address41(sboxes_address41),
.ce41(sboxes_ce41),
.q41(sboxes_q41),
.address42(sboxes_address42),
.ce42(sboxes_ce42),
.q42(sboxes_q42),
.address43(sboxes_address43),
.ce43(sboxes_ce43),
.q43(sboxes_q43),
.address44(sboxes_address44),
.ce44(sboxes_ce44),
.q44(sboxes_q44),
.address45(sboxes_address45),
.ce45(sboxes_ce45),
.q45(sboxes_q45),
.address46(sboxes_address46),
.ce46(sboxes_ce46),
.q46(sboxes_q46),
.address47(sboxes_address47),
.ce47(sboxes_ce47),
.q47(sboxes_q47),
.address48(sboxes_address48),
.ce48(sboxes_ce48),
.q48(sboxes_q48),
.address49(sboxes_address49),
.ce49(sboxes_ce49),
.q49(sboxes_q49),
.address50(sboxes_address50),
.ce50(sboxes_ce50),
.q50(sboxes_q50),
.address51(sboxes_address51),
.ce51(sboxes_ce51),
.q51(sboxes_q51),
.address52(sboxes_address52),
.ce52(sboxes_ce52),
.q52(sboxes_q52),
.address53(sboxes_address53),
.ce53(sboxes_ce53),
.q53(sboxes_q53),
.address54(sboxes_address54),
.ce54(sboxes_ce54),
.q54(sboxes_q54),
.address55(sboxes_address55),
.ce55(sboxes_ce55),
.q55(sboxes_q55),
.address56(sboxes_address56),
.ce56(sboxes_ce56),
.q56(sboxes_q56),
.address57(sboxes_address57),
.ce57(sboxes_ce57),
.q57(sboxes_q57),
.address58(sboxes_address58),
.ce58(sboxes_ce58),
.q58(sboxes_q58),
.address59(sboxes_address59),
.ce59(sboxes_ce59),
.q59(sboxes_q59),
.address60(sboxes_address60),
.ce60(sboxes_ce60),
.q60(sboxes_q60),
.address61(sboxes_address61),
.ce61(sboxes_ce61),
.q61(sboxes_q61),
.address62(sboxes_address62),
.ce62(sboxes_ce62),
.q62(sboxes_q62),
.address63(sboxes_address63),
.ce63(sboxes_ce63),
.q63(sboxes_q63),
.address64(sboxes_address64),
.ce64(sboxes_ce64),
.q64(sboxes_q64),
.address65(sboxes_address65),
.ce65(sboxes_ce65),
.q65(sboxes_q65),
.address66(sboxes_address66),
.ce66(sboxes_ce66),
.q66(sboxes_q66),
.address67(sboxes_address67),
.ce67(sboxes_ce67),
.q67(sboxes_q67),
.address68(sboxes_address68),
.ce68(sboxes_ce68),
.q68(sboxes_q68),
.address69(sboxes_address69),
.ce69(sboxes_ce69),
.q69(sboxes_q69),
.address70(sboxes_address70),
.ce70(sboxes_ce70),
.q70(sboxes_q70),
.address71(sboxes_address71),
.ce71(sboxes_ce71),
.q71(sboxes_q71),
.address72(sboxes_address72),
.ce72(sboxes_ce72),
.q72(sboxes_q72),
.address73(sboxes_address73),
.ce73(sboxes_ce73),
.q73(sboxes_q73),
.address74(sboxes_address74),
.ce74(sboxes_ce74),
.q74(sboxes_q74),
.address75(sboxes_address75),
.ce75(sboxes_ce75),
.q75(sboxes_q75),
.address76(sboxes_address76),
.ce76(sboxes_ce76),
.q76(sboxes_q76),
.address77(sboxes_address77),
.ce77(sboxes_ce77),
.q77(sboxes_q77),
.address78(sboxes_address78),
.ce78(sboxes_ce78),
.q78(sboxes_q78),
.address79(sboxes_address79),
.ce79(sboxes_ce79),
.q79(sboxes_q79),
.address80(sboxes_address80),
.ce80(sboxes_ce80),
.q80(sboxes_q80),
.address81(sboxes_address81),
.ce81(sboxes_ce81),
.q81(sboxes_q81),
.address82(sboxes_address82),
.ce82(sboxes_ce82),
.q82(sboxes_q82),
.address83(sboxes_address83),
.ce83(sboxes_ce83),
.q83(sboxes_q83),
.address84(sboxes_address84),
.ce84(sboxes_ce84),
.q84(sboxes_q84),
.address85(sboxes_address85),
.ce85(sboxes_ce85),
.q85(sboxes_q85),
.address86(sboxes_address86),
.ce86(sboxes_ce86),
.q86(sboxes_q86),
.address87(sboxes_address87),
.ce87(sboxes_ce87),
.q87(sboxes_q87),
.address88(sboxes_address88),
.ce88(sboxes_ce88),
.q88(sboxes_q88),
.address89(sboxes_address89),
.ce89(sboxes_ce89),
.q89(sboxes_q89),
.address90(sboxes_address90),
.ce90(sboxes_ce90),
.q90(sboxes_q90),
.address91(sboxes_address91),
.ce91(sboxes_ce91),
.q91(sboxes_q91),
.address92(sboxes_address92),
.ce92(sboxes_ce92),
.q92(sboxes_q92),
.address93(sboxes_address93),
.ce93(sboxes_ce93),
.q93(sboxes_q93),
.address94(sboxes_address94),
.ce94(sboxes_ce94),
.q94(sboxes_q94),
.address95(sboxes_address95),
.ce95(sboxes_ce95),
.q95(sboxes_q95),
.address96(sboxes_address96),
.ce96(sboxes_ce96),
.q96(sboxes_q96),
.address97(sboxes_address97),
.ce97(sboxes_ce97),
.q97(sboxes_q97),
.address98(sboxes_address98),
.ce98(sboxes_ce98),
.q98(sboxes_q98),
.address99(sboxes_address99),
.ce99(sboxes_ce99),
.q99(sboxes_q99),
.address100(sboxes_address100),
.ce100(sboxes_ce100),
.q100(sboxes_q100),
.address101(sboxes_address101),
.ce101(sboxes_ce101),
.q101(sboxes_q101),
.address102(sboxes_address102),
.ce102(sboxes_ce102),
.q102(sboxes_q102),
.address103(sboxes_address103),
.ce103(sboxes_ce103),
.q103(sboxes_q103),
.address104(sboxes_address104),
.ce104(sboxes_ce104),
.q104(sboxes_q104),
.address105(sboxes_address105),
.ce105(sboxes_ce105),
.q105(sboxes_q105),
.address106(sboxes_address106),
.ce106(sboxes_ce106),
.q106(sboxes_q106),
.address107(sboxes_address107),
.ce107(sboxes_ce107),
.q107(sboxes_q107),
.address108(sboxes_address108),
.ce108(sboxes_ce108),
.q108(sboxes_q108),
.address109(sboxes_address109),
.ce109(sboxes_ce109),
.q109(sboxes_q109),
.address110(sboxes_address110),
.ce110(sboxes_ce110),
.q110(sboxes_q110),
.address111(sboxes_address111),
.ce111(sboxes_ce111),
.q111(sboxes_q111),
.address112(sboxes_address112),
.ce112(sboxes_ce112),
.q112(sboxes_q112),
.address113(sboxes_address113),
.ce113(sboxes_ce113),
.q113(sboxes_q113),
.address114(sboxes_address114),
.ce114(sboxes_ce114),
.q114(sboxes_q114),
.address115(sboxes_address115),
.ce115(sboxes_ce115),
.q115(sboxes_q115),
.address116(sboxes_address116),
.ce116(sboxes_ce116),
.q116(sboxes_q116),
.address117(sboxes_address117),
.ce117(sboxes_ce117),
.q117(sboxes_q117),
.address118(sboxes_address118),
.ce118(sboxes_ce118),
.q118(sboxes_q118),
.address119(sboxes_address119),
.ce119(sboxes_ce119),
.q119(sboxes_q119),
.address120(sboxes_address120),
.ce120(sboxes_ce120),
.q120(sboxes_q120),
.address121(sboxes_address121),
.ce121(sboxes_ce121),
.q121(sboxes_q121),
.address122(sboxes_address122),
.ce122(sboxes_ce122),
.q122(sboxes_q122),
.address123(sboxes_address123),
.ce123(sboxes_ce123),
.q123(sboxes_q123),
.address124(sboxes_address124),
.ce124(sboxes_ce124),
.q124(sboxes_q124),
.address125(sboxes_address125),
.ce125(sboxes_ce125),
.q125(sboxes_q125),
.address126(sboxes_address126),
.ce126(sboxes_ce126),
.q126(sboxes_q126),
.address127(sboxes_address127),
.ce127(sboxes_ce127),
.q127(sboxes_q127),
.address128(sboxes_address128),
.ce128(sboxes_ce128),
.q128(sboxes_q128),
.address129(sboxes_address129),
.ce129(sboxes_ce129),
.q129(sboxes_q129),
.address130(sboxes_address130),
.ce130(sboxes_ce130),
.q130(sboxes_q130),
.address131(sboxes_address131),
.ce131(sboxes_ce131),
.q131(sboxes_q131),
.address132(sboxes_address132),
.ce132(sboxes_ce132),
.q132(sboxes_q132),
.address133(sboxes_address133),
.ce133(sboxes_ce133),
.q133(sboxes_q133),
.address134(sboxes_address134),
.ce134(sboxes_ce134),
.q134(sboxes_q134),
.address135(sboxes_address135),
.ce135(sboxes_ce135),
.q135(sboxes_q135),
.address136(sboxes_address136),
.ce136(sboxes_ce136),
.q136(sboxes_q136),
.address137(sboxes_address137),
.ce137(sboxes_ce137),
.q137(sboxes_q137),
.address138(sboxes_address138),
.ce138(sboxes_ce138),
.q138(sboxes_q138),
.address139(sboxes_address139),
.ce139(sboxes_ce139),
.q139(sboxes_q139),
.address140(sboxes_address140),
.ce140(sboxes_ce140),
.q140(sboxes_q140),
.address141(sboxes_address141),
.ce141(sboxes_ce141),
.q141(sboxes_q141),
.address142(sboxes_address142),
.ce142(sboxes_ce142),
.q142(sboxes_q142),
.address143(sboxes_address143),
.ce143(sboxes_ce143),
.q143(sboxes_q143),
.address144(sboxes_address144),
.ce144(sboxes_ce144),
.q144(sboxes_q144),
.address145(sboxes_address145),
.ce145(sboxes_ce145),
.q145(sboxes_q145),
.address146(sboxes_address146),
.ce146(sboxes_ce146),
.q146(sboxes_q146),
.address147(sboxes_address147),
.ce147(sboxes_ce147),
.q147(sboxes_q147),
.address148(sboxes_address148),
.ce148(sboxes_ce148),
.q148(sboxes_q148),
.address149(sboxes_address149),
.ce149(sboxes_ce149),
.q149(sboxes_q149),
.address150(sboxes_address150),
.ce150(sboxes_ce150),
.q150(sboxes_q150),
.address151(sboxes_address151),
.ce151(sboxes_ce151),
.q151(sboxes_q151),
.address152(sboxes_address152),
.ce152(sboxes_ce152),
.q152(sboxes_q152),
.address153(sboxes_address153),
.ce153(sboxes_ce153),
.q153(sboxes_q153),
.address154(sboxes_address154),
.ce154(sboxes_ce154),
.q154(sboxes_q154),
.address155(sboxes_address155),
.ce155(sboxes_ce155),
.q155(sboxes_q155),
.address156(sboxes_address156),
.ce156(sboxes_ce156),
.q156(sboxes_q156),
.address157(sboxes_address157),
.ce157(sboxes_ce157),
.q157(sboxes_q157),
.address158(sboxes_address158),
.ce158(sboxes_ce158),
.q158(sboxes_q158),
.address159(sboxes_address159),
.ce159(sboxes_ce159),
.q159(sboxes_q159),
.address160(sboxes_address160),
.ce160(sboxes_ce160),
.q160(sboxes_q160),
.address161(sboxes_address161),
.ce161(sboxes_ce161),
.q161(sboxes_q161),
.address162(sboxes_address162),
.ce162(sboxes_ce162),
.q162(sboxes_q162),
.address163(sboxes_address163),
.ce163(sboxes_ce163),
.q163(sboxes_q163),
.address164(sboxes_address164),
.ce164(sboxes_ce164),
.q164(sboxes_q164),
.address165(sboxes_address165),
.ce165(sboxes_ce165),
.q165(sboxes_q165),
.address166(sboxes_address166),
.ce166(sboxes_ce166),
.q166(sboxes_q166),
.address167(sboxes_address167),
.ce167(sboxes_ce167),
.q167(sboxes_q167),
.address168(sboxes_address168),
.ce168(sboxes_ce168),
.q168(sboxes_q168),
.address169(sboxes_address169),
.ce169(sboxes_ce169),
.q169(sboxes_q169),
.address170(sboxes_address170),
.ce170(sboxes_ce170),
.q170(sboxes_q170),
.address171(sboxes_address171),
.ce171(sboxes_ce171),
.q171(sboxes_q171),
.address172(sboxes_address172),
.ce172(sboxes_ce172),
.q172(sboxes_q172),
.address173(sboxes_address173),
.ce173(sboxes_ce173),
.q173(sboxes_q173),
.address174(sboxes_address174),
.ce174(sboxes_ce174),
.q174(sboxes_q174),
.address175(sboxes_address175),
.ce175(sboxes_ce175),
.q175(sboxes_q175),
.address176(sboxes_address176),
.ce176(sboxes_ce176),
.q176(sboxes_q176),
.address177(sboxes_address177),
.ce177(sboxes_ce177),
.q177(sboxes_q177),
.address178(sboxes_address178),
.ce178(sboxes_ce178),
.q178(sboxes_q178),
.address179(sboxes_address179),
.ce179(sboxes_ce179),
.q179(sboxes_q179),
.address180(sboxes_address180),
.ce180(sboxes_ce180),
.q180(sboxes_q180),
.address181(sboxes_address181),
.ce181(sboxes_ce181),
.q181(sboxes_q181),
.address182(sboxes_address182),
.ce182(sboxes_ce182),
.q182(sboxes_q182),
.address183(sboxes_address183),
.ce183(sboxes_ce183),
.q183(sboxes_q183),
.address184(sboxes_address184),
.ce184(sboxes_ce184),
.q184(sboxes_q184),
.address185(sboxes_address185),
.ce185(sboxes_ce185),
.q185(sboxes_q185),
.address186(sboxes_address186),
.ce186(sboxes_ce186),
.q186(sboxes_q186),
.address187(sboxes_address187),
.ce187(sboxes_ce187),
.q187(sboxes_q187),
.address188(sboxes_address188),
.ce188(sboxes_ce188),
.q188(sboxes_q188),
.address189(sboxes_address189),
.ce189(sboxes_ce189),
.q189(sboxes_q189),
.address190(sboxes_address190),
.ce190(sboxes_ce190),
.q190(sboxes_q190),
.address191(sboxes_address191),
.ce191(sboxes_ce191),
.q191(sboxes_q191),
.address192(sboxes_address192),
.ce192(sboxes_ce192),
.q192(sboxes_q192),
.address193(sboxes_address193),
.ce193(sboxes_ce193),
.q193(sboxes_q193),
.address194(sboxes_address194),
.ce194(sboxes_ce194),
.q194(sboxes_q194),
.address195(sboxes_address195),
.ce195(sboxes_ce195),
.q195(sboxes_q195),
.address196(sboxes_address196),
.ce196(sboxes_ce196),
.q196(sboxes_q196),
.address197(sboxes_address197),
.ce197(sboxes_ce197),
.q197(sboxes_q197),
.address198(sboxes_address198),
.ce198(sboxes_ce198),
.q198(sboxes_q198),
.address199(sboxes_address199),
.ce199(sboxes_ce199),
.q199(sboxes_q199)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter1 <= ap_start;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter10 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter5 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter6 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter7 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter8 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter9 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
ap_reg_pp0_iter1_p_Result_1_11_reg_12485 <= p_Result_1_11_reg_12485;
ap_reg_pp0_iter1_p_Result_1_12_reg_12492 <= p_Result_1_12_reg_12492;
ap_reg_pp0_iter1_p_Result_1_13_reg_12499 <= p_Result_1_13_reg_12499;
ap_reg_pp0_iter1_p_Result_1_4_reg_12441 <= p_Result_1_4_reg_12441;
ap_reg_pp0_iter1_p_Result_1_5_reg_12447 <= p_Result_1_5_reg_12447;
ap_reg_pp0_iter1_p_Result_1_6_reg_12453 <= p_Result_1_6_reg_12453;
ap_reg_pp0_iter1_p_Result_1_7_reg_12459 <= p_Result_1_7_reg_12459;
ap_reg_pp0_iter1_tmp_100_reg_12506 <= tmp_100_reg_12506;
p_Result_1_10_reg_12480 <= {{key_V_read[39:32]}};
p_Result_1_11_reg_12485 <= {{key_V_read[31:24]}};
p_Result_1_12_reg_12492 <= {{key_V_read[23:16]}};
p_Result_1_13_reg_12499 <= {{key_V_read[15:8]}};
p_Result_1_1_reg_12426 <= {{key_V_read[119:112]}};
p_Result_1_2_reg_12431 <= {{key_V_read[111:104]}};
p_Result_1_3_reg_12436 <= {{key_V_read[103:96]}};
p_Result_1_4_reg_12441 <= {{key_V_read[95:88]}};
p_Result_1_5_reg_12447 <= {{key_V_read[87:80]}};
p_Result_1_6_reg_12453 <= {{key_V_read[79:72]}};
p_Result_1_7_reg_12459 <= {{key_V_read[71:64]}};
p_Result_1_8_reg_12465 <= {{key_V_read[63:56]}};
p_Result_1_9_reg_12470 <= {{key_V_read[55:48]}};
p_Result_1_reg_12421 <= {{key_V_read[127:120]}};
p_Result_1_s_reg_12475 <= {{key_V_read[47:40]}};
tmp_100_reg_12506 <= tmp_100_fu_2625_p1;
tmp_65_reg_12613 <= tmp_65_fu_3422_p2;
tmp_66_reg_12618 <= tmp_66_fu_3428_p2;
tmp_67_reg_12623 <= tmp_67_fu_3433_p2;
tmp_68_reg_12628 <= tmp_68_fu_3438_p2;
tmp_73_reg_12633 <= tmp_73_fu_3463_p2;
tmp_74_reg_12639 <= tmp_74_fu_3468_p2;
tmp_75_reg_12645 <= tmp_75_fu_3473_p2;
tmp_76_reg_12651 <= tmp_76_fu_3478_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
ap_reg_pp0_iter2_p_Result_1_11_reg_12485 <= ap_reg_pp0_iter1_p_Result_1_11_reg_12485;
ap_reg_pp0_iter2_p_Result_1_12_reg_12492 <= ap_reg_pp0_iter1_p_Result_1_12_reg_12492;
ap_reg_pp0_iter2_p_Result_1_13_reg_12499 <= ap_reg_pp0_iter1_p_Result_1_13_reg_12499;
ap_reg_pp0_iter2_tmp_100_reg_12506 <= ap_reg_pp0_iter1_tmp_100_reg_12506;
ap_reg_pp0_iter2_tmp_73_reg_12633 <= tmp_73_reg_12633;
ap_reg_pp0_iter2_tmp_74_reg_12639 <= tmp_74_reg_12639;
ap_reg_pp0_iter2_tmp_75_reg_12645 <= tmp_75_reg_12645;
ap_reg_pp0_iter2_tmp_76_reg_12651 <= tmp_76_reg_12651;
ap_reg_pp0_iter3_p_Result_1_11_reg_12485 <= ap_reg_pp0_iter2_p_Result_1_11_reg_12485;
ap_reg_pp0_iter3_p_Result_1_12_reg_12492 <= ap_reg_pp0_iter2_p_Result_1_12_reg_12492;
ap_reg_pp0_iter3_p_Result_1_13_reg_12499 <= ap_reg_pp0_iter2_p_Result_1_13_reg_12499;
ap_reg_pp0_iter3_tmp_100_reg_12506 <= ap_reg_pp0_iter2_tmp_100_reg_12506;
ap_reg_pp0_iter3_tmp_69_1_reg_12777 <= tmp_69_1_reg_12777;
ap_reg_pp0_iter3_tmp_70_1_reg_12783 <= tmp_70_1_reg_12783;
ap_reg_pp0_iter3_tmp_71_1_reg_12789 <= tmp_71_1_reg_12789;
ap_reg_pp0_iter3_tmp_72_1_reg_12795 <= tmp_72_1_reg_12795;
ap_reg_pp0_iter4_tmp_73_2_reg_12941 <= tmp_73_2_reg_12941;
ap_reg_pp0_iter4_tmp_74_2_reg_12947 <= tmp_74_2_reg_12947;
ap_reg_pp0_iter4_tmp_75_2_reg_12953 <= tmp_75_2_reg_12953;
ap_reg_pp0_iter4_tmp_76_2_reg_12959 <= tmp_76_2_reg_12959;
ap_reg_pp0_iter5_tmp_69_3_reg_13085 <= tmp_69_3_reg_13085;
ap_reg_pp0_iter5_tmp_70_3_reg_13091 <= tmp_70_3_reg_13091;
ap_reg_pp0_iter5_tmp_71_3_reg_13097 <= tmp_71_3_reg_13097;
ap_reg_pp0_iter5_tmp_72_3_reg_13103 <= tmp_72_3_reg_13103;
ap_reg_pp0_iter5_tmp_77_3_reg_13109 <= tmp_77_3_reg_13109;
ap_reg_pp0_iter5_tmp_78_3_reg_13116 <= tmp_78_3_reg_13116;
ap_reg_pp0_iter5_tmp_79_3_reg_13123 <= tmp_79_3_reg_13123;
ap_reg_pp0_iter5_tmp_80_3_reg_13130 <= tmp_80_3_reg_13130;
ap_reg_pp0_iter6_tmp_73_4_reg_13257 <= tmp_73_4_reg_13257;
ap_reg_pp0_iter6_tmp_74_4_reg_13263 <= tmp_74_4_reg_13263;
ap_reg_pp0_iter6_tmp_75_4_reg_13269 <= tmp_75_4_reg_13269;
ap_reg_pp0_iter6_tmp_76_4_reg_13275 <= tmp_76_4_reg_13275;
ap_reg_pp0_iter6_tmp_77_3_reg_13109 <= ap_reg_pp0_iter5_tmp_77_3_reg_13109;
ap_reg_pp0_iter6_tmp_78_3_reg_13116 <= ap_reg_pp0_iter5_tmp_78_3_reg_13116;
ap_reg_pp0_iter6_tmp_79_3_reg_13123 <= ap_reg_pp0_iter5_tmp_79_3_reg_13123;
ap_reg_pp0_iter6_tmp_80_3_reg_13130 <= ap_reg_pp0_iter5_tmp_80_3_reg_13130;
ap_reg_pp0_iter7_tmp_69_5_reg_13401 <= tmp_69_5_reg_13401;
ap_reg_pp0_iter7_tmp_70_5_reg_13407 <= tmp_70_5_reg_13407;
ap_reg_pp0_iter7_tmp_71_5_reg_13413 <= tmp_71_5_reg_13413;
ap_reg_pp0_iter7_tmp_72_5_reg_13419 <= tmp_72_5_reg_13419;
ap_reg_pp0_iter7_tmp_77_3_reg_13109 <= ap_reg_pp0_iter6_tmp_77_3_reg_13109;
ap_reg_pp0_iter7_tmp_78_3_reg_13116 <= ap_reg_pp0_iter6_tmp_78_3_reg_13116;
ap_reg_pp0_iter7_tmp_79_3_reg_13123 <= ap_reg_pp0_iter6_tmp_79_3_reg_13123;
ap_reg_pp0_iter7_tmp_80_3_reg_13130 <= ap_reg_pp0_iter6_tmp_80_3_reg_13130;
ap_reg_pp0_iter8_tmp_73_6_reg_13565 <= tmp_73_6_reg_13565;
ap_reg_pp0_iter8_tmp_74_6_reg_13571 <= tmp_74_6_reg_13571;
ap_reg_pp0_iter8_tmp_75_6_reg_13577 <= tmp_75_6_reg_13577;
ap_reg_pp0_iter8_tmp_76_6_reg_13583 <= tmp_76_6_reg_13583;
ap_reg_pp0_iter9_tmp_69_7_reg_13709 <= tmp_69_7_reg_13709;
ap_reg_pp0_iter9_tmp_70_7_reg_13715 <= tmp_70_7_reg_13715;
ap_reg_pp0_iter9_tmp_71_7_reg_13721 <= tmp_71_7_reg_13721;
ap_reg_pp0_iter9_tmp_72_7_reg_13727 <= tmp_72_7_reg_13727;
ap_reg_pp0_iter9_tmp_77_7_reg_13733 <= tmp_77_7_reg_13733;
ap_reg_pp0_iter9_tmp_78_7_reg_13739 <= tmp_78_7_reg_13739;
ap_reg_pp0_iter9_tmp_79_7_reg_13745 <= tmp_79_7_reg_13745;
ap_reg_pp0_iter9_tmp_80_7_reg_13751 <= tmp_80_7_reg_13751;
tmp_65_1_reg_12757 <= tmp_65_1_fu_4465_p2;
tmp_65_2_reg_12921 <= tmp_65_2_fu_5506_p2;
tmp_65_3_reg_13065 <= tmp_65_3_fu_6549_p2;
tmp_65_4_reg_13237 <= tmp_65_4_fu_7590_p2;
tmp_65_5_reg_13381 <= tmp_65_5_fu_8633_p2;
tmp_65_6_reg_13545 <= tmp_65_6_fu_9674_p2;
tmp_65_7_reg_13689 <= tmp_65_7_fu_10717_p2;
tmp_65_8_reg_13857 <= tmp_65_8_fu_11758_p2;
tmp_66_1_reg_12762 <= tmp_66_1_fu_4470_p2;
tmp_66_2_reg_12926 <= tmp_66_2_fu_5512_p2;
tmp_66_3_reg_13070 <= tmp_66_3_fu_6554_p2;
tmp_66_4_reg_13242 <= tmp_66_4_fu_7596_p2;
tmp_66_5_reg_13386 <= tmp_66_5_fu_8638_p2;
tmp_66_6_reg_13550 <= tmp_66_6_fu_9680_p2;
tmp_66_7_reg_13694 <= tmp_66_7_fu_10722_p2;
tmp_66_8_reg_13862 <= tmp_66_8_fu_11764_p2;
tmp_67_1_reg_12767 <= tmp_67_1_fu_4475_p2;
tmp_67_2_reg_12931 <= tmp_67_2_fu_5517_p2;
tmp_67_3_reg_13075 <= tmp_67_3_fu_6559_p2;
tmp_67_4_reg_13247 <= tmp_67_4_fu_7601_p2;
tmp_67_5_reg_13391 <= tmp_67_5_fu_8643_p2;
tmp_67_6_reg_13555 <= tmp_67_6_fu_9685_p2;
tmp_67_7_reg_13699 <= tmp_67_7_fu_10727_p2;
tmp_67_8_reg_13867 <= tmp_67_8_fu_11769_p2;
tmp_68_1_reg_12772 <= tmp_68_1_fu_4480_p2;
tmp_68_2_reg_12936 <= tmp_68_2_fu_5522_p2;
tmp_68_3_reg_13080 <= tmp_68_3_fu_6564_p2;
tmp_68_4_reg_13252 <= tmp_68_4_fu_7606_p2;
tmp_68_5_reg_13396 <= tmp_68_5_fu_8648_p2;
tmp_68_6_reg_13560 <= tmp_68_6_fu_9690_p2;
tmp_68_7_reg_13704 <= tmp_68_7_fu_10732_p2;
tmp_68_8_reg_13872 <= tmp_68_8_fu_11774_p2;
tmp_69_1_reg_12777 <= tmp_69_1_fu_4485_p2;
tmp_69_3_reg_13085 <= tmp_69_3_fu_6569_p2;
tmp_69_5_reg_13401 <= tmp_69_5_fu_8653_p2;
tmp_69_7_reg_13709 <= tmp_69_7_fu_10737_p2;
tmp_70_1_reg_12783 <= tmp_70_1_fu_4490_p2;
tmp_70_3_reg_13091 <= tmp_70_3_fu_6574_p2;
tmp_70_5_reg_13407 <= tmp_70_5_fu_8658_p2;
tmp_70_7_reg_13715 <= tmp_70_7_fu_10742_p2;
tmp_71_1_reg_12789 <= tmp_71_1_fu_4495_p2;
tmp_71_3_reg_13097 <= tmp_71_3_fu_6579_p2;
tmp_71_5_reg_13413 <= tmp_71_5_fu_8663_p2;
tmp_71_7_reg_13721 <= tmp_71_7_fu_10747_p2;
tmp_72_1_reg_12795 <= tmp_72_1_fu_4500_p2;
tmp_72_3_reg_13103 <= tmp_72_3_fu_6584_p2;
tmp_72_5_reg_13419 <= tmp_72_5_fu_8668_p2;
tmp_72_7_reg_13727 <= tmp_72_7_fu_10752_p2;
tmp_73_2_reg_12941 <= tmp_73_2_fu_5527_p2;
tmp_73_4_reg_13257 <= tmp_73_4_fu_7611_p2;
tmp_73_6_reg_13565 <= tmp_73_6_fu_9695_p2;
tmp_73_8_reg_13877 <= tmp_73_8_fu_11779_p2;
tmp_74_2_reg_12947 <= tmp_74_2_fu_5532_p2;
tmp_74_4_reg_13263 <= tmp_74_4_fu_7616_p2;
tmp_74_6_reg_13571 <= tmp_74_6_fu_9700_p2;
tmp_74_8_reg_13882 <= tmp_74_8_fu_11784_p2;
tmp_75_2_reg_12953 <= tmp_75_2_fu_5537_p2;
tmp_75_4_reg_13269 <= tmp_75_4_fu_7621_p2;
tmp_75_6_reg_13577 <= tmp_75_6_fu_9705_p2;
tmp_75_8_reg_13887 <= tmp_75_8_fu_11789_p2;
tmp_76_2_reg_12959 <= tmp_76_2_fu_5542_p2;
tmp_76_4_reg_13275 <= tmp_76_4_fu_7626_p2;
tmp_76_6_reg_13583 <= tmp_76_6_fu_9710_p2;
tmp_76_8_reg_13892 <= tmp_76_8_fu_11794_p2;
tmp_77_1_reg_12801 <= tmp_77_1_fu_4505_p2;
tmp_77_3_reg_13109 <= tmp_77_3_fu_6589_p2;
tmp_77_5_reg_13425 <= tmp_77_5_fu_8673_p2;
tmp_77_7_reg_13733 <= tmp_77_7_fu_10757_p2;
tmp_78_1_reg_12806 <= tmp_78_1_fu_4510_p2;
tmp_78_3_reg_13116 <= tmp_78_3_fu_6594_p2;
tmp_78_5_reg_13430 <= tmp_78_5_fu_8678_p2;
tmp_78_7_reg_13739 <= tmp_78_7_fu_10762_p2;
tmp_79_1_reg_12811 <= tmp_79_1_fu_4515_p2;
tmp_79_3_reg_13123 <= tmp_79_3_fu_6599_p2;
tmp_79_5_reg_13435 <= tmp_79_5_fu_8683_p2;
tmp_79_7_reg_13745 <= tmp_79_7_fu_10767_p2;
tmp_80_1_reg_12816 <= tmp_80_1_fu_4520_p2;
tmp_80_3_reg_13130 <= tmp_80_3_fu_6604_p2;
tmp_80_5_reg_13440 <= tmp_80_5_fu_8688_p2;
tmp_80_7_reg_13751 <= tmp_80_7_fu_10772_p2;
end
end
always @ (*) begin
if ((((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter10)))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_idle_pp0))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter4) & (1'b0 == ap_enable_reg_pp0_iter5) & (1'b0 == ap_enable_reg_pp0_iter6) & (1'b0 == ap_enable_reg_pp0_iter7) & (1'b0 == ap_enable_reg_pp0_iter8) & (1'b0 == ap_enable_reg_pp0_iter9) & (1'b0 == ap_enable_reg_pp0_iter10))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter4) & (1'b0 == ap_enable_reg_pp0_iter5) & (1'b0 == ap_enable_reg_pp0_iter6) & (1'b0 == ap_enable_reg_pp0_iter7) & (1'b0 == ap_enable_reg_pp0_iter8) & (1'b0 == ap_enable_reg_pp0_iter9))) begin
ap_idle_pp0_0to9 = 1'b1;
end else begin
ap_idle_pp0_0to9 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_idle_pp0_0to9))) begin
ap_reset_idle_pp0 = 1'b1;
end else begin
ap_reset_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_idle_pp0_0to9) & (1'b1 == ap_start))) begin
ap_reset_start_pp0 = 1'b1;
end else begin
ap_reset_start_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce0 = 1'b1;
end else begin
sboxes_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce1 = 1'b1;
end else begin
sboxes_ce1 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce10 = 1'b1;
end else begin
sboxes_ce10 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce100 = 1'b1;
end else begin
sboxes_ce100 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce101 = 1'b1;
end else begin
sboxes_ce101 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce102 = 1'b1;
end else begin
sboxes_ce102 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce103 = 1'b1;
end else begin
sboxes_ce103 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce104 = 1'b1;
end else begin
sboxes_ce104 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce105 = 1'b1;
end else begin
sboxes_ce105 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce106 = 1'b1;
end else begin
sboxes_ce106 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce107 = 1'b1;
end else begin
sboxes_ce107 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce108 = 1'b1;
end else begin
sboxes_ce108 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce109 = 1'b1;
end else begin
sboxes_ce109 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce11 = 1'b1;
end else begin
sboxes_ce11 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce110 = 1'b1;
end else begin
sboxes_ce110 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce111 = 1'b1;
end else begin
sboxes_ce111 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce112 = 1'b1;
end else begin
sboxes_ce112 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce113 = 1'b1;
end else begin
sboxes_ce113 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce114 = 1'b1;
end else begin
sboxes_ce114 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce115 = 1'b1;
end else begin
sboxes_ce115 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce116 = 1'b1;
end else begin
sboxes_ce116 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce117 = 1'b1;
end else begin
sboxes_ce117 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce118 = 1'b1;
end else begin
sboxes_ce118 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter5))) begin
sboxes_ce119 = 1'b1;
end else begin
sboxes_ce119 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce12 = 1'b1;
end else begin
sboxes_ce12 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce120 = 1'b1;
end else begin
sboxes_ce120 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce121 = 1'b1;
end else begin
sboxes_ce121 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce122 = 1'b1;
end else begin
sboxes_ce122 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce123 = 1'b1;
end else begin
sboxes_ce123 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce124 = 1'b1;
end else begin
sboxes_ce124 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce125 = 1'b1;
end else begin
sboxes_ce125 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce126 = 1'b1;
end else begin
sboxes_ce126 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce127 = 1'b1;
end else begin
sboxes_ce127 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce128 = 1'b1;
end else begin
sboxes_ce128 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce129 = 1'b1;
end else begin
sboxes_ce129 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce13 = 1'b1;
end else begin
sboxes_ce13 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce130 = 1'b1;
end else begin
sboxes_ce130 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce131 = 1'b1;
end else begin
sboxes_ce131 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce132 = 1'b1;
end else begin
sboxes_ce132 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce133 = 1'b1;
end else begin
sboxes_ce133 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce134 = 1'b1;
end else begin
sboxes_ce134 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce135 = 1'b1;
end else begin
sboxes_ce135 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce136 = 1'b1;
end else begin
sboxes_ce136 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce137 = 1'b1;
end else begin
sboxes_ce137 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce138 = 1'b1;
end else begin
sboxes_ce138 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter6))) begin
sboxes_ce139 = 1'b1;
end else begin
sboxes_ce139 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce14 = 1'b1;
end else begin
sboxes_ce14 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce140 = 1'b1;
end else begin
sboxes_ce140 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce141 = 1'b1;
end else begin
sboxes_ce141 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce142 = 1'b1;
end else begin
sboxes_ce142 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce143 = 1'b1;
end else begin
sboxes_ce143 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce144 = 1'b1;
end else begin
sboxes_ce144 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce145 = 1'b1;
end else begin
sboxes_ce145 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce146 = 1'b1;
end else begin
sboxes_ce146 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce147 = 1'b1;
end else begin
sboxes_ce147 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce148 = 1'b1;
end else begin
sboxes_ce148 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce149 = 1'b1;
end else begin
sboxes_ce149 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce15 = 1'b1;
end else begin
sboxes_ce15 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce150 = 1'b1;
end else begin
sboxes_ce150 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce151 = 1'b1;
end else begin
sboxes_ce151 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce152 = 1'b1;
end else begin
sboxes_ce152 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce153 = 1'b1;
end else begin
sboxes_ce153 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce154 = 1'b1;
end else begin
sboxes_ce154 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce155 = 1'b1;
end else begin
sboxes_ce155 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce156 = 1'b1;
end else begin
sboxes_ce156 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce157 = 1'b1;
end else begin
sboxes_ce157 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce158 = 1'b1;
end else begin
sboxes_ce158 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter7))) begin
sboxes_ce159 = 1'b1;
end else begin
sboxes_ce159 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce16 = 1'b1;
end else begin
sboxes_ce16 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce160 = 1'b1;
end else begin
sboxes_ce160 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce161 = 1'b1;
end else begin
sboxes_ce161 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce162 = 1'b1;
end else begin
sboxes_ce162 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce163 = 1'b1;
end else begin
sboxes_ce163 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce164 = 1'b1;
end else begin
sboxes_ce164 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce165 = 1'b1;
end else begin
sboxes_ce165 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce166 = 1'b1;
end else begin
sboxes_ce166 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce167 = 1'b1;
end else begin
sboxes_ce167 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce168 = 1'b1;
end else begin
sboxes_ce168 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce169 = 1'b1;
end else begin
sboxes_ce169 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce17 = 1'b1;
end else begin
sboxes_ce17 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce170 = 1'b1;
end else begin
sboxes_ce170 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce171 = 1'b1;
end else begin
sboxes_ce171 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce172 = 1'b1;
end else begin
sboxes_ce172 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce173 = 1'b1;
end else begin
sboxes_ce173 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce174 = 1'b1;
end else begin
sboxes_ce174 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce175 = 1'b1;
end else begin
sboxes_ce175 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce176 = 1'b1;
end else begin
sboxes_ce176 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce177 = 1'b1;
end else begin
sboxes_ce177 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce178 = 1'b1;
end else begin
sboxes_ce178 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter8))) begin
sboxes_ce179 = 1'b1;
end else begin
sboxes_ce179 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce18 = 1'b1;
end else begin
sboxes_ce18 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce180 = 1'b1;
end else begin
sboxes_ce180 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce181 = 1'b1;
end else begin
sboxes_ce181 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce182 = 1'b1;
end else begin
sboxes_ce182 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce183 = 1'b1;
end else begin
sboxes_ce183 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce184 = 1'b1;
end else begin
sboxes_ce184 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce185 = 1'b1;
end else begin
sboxes_ce185 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce186 = 1'b1;
end else begin
sboxes_ce186 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce187 = 1'b1;
end else begin
sboxes_ce187 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce188 = 1'b1;
end else begin
sboxes_ce188 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce189 = 1'b1;
end else begin
sboxes_ce189 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce19 = 1'b1;
end else begin
sboxes_ce19 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce190 = 1'b1;
end else begin
sboxes_ce190 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce191 = 1'b1;
end else begin
sboxes_ce191 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce192 = 1'b1;
end else begin
sboxes_ce192 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce193 = 1'b1;
end else begin
sboxes_ce193 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce194 = 1'b1;
end else begin
sboxes_ce194 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce195 = 1'b1;
end else begin
sboxes_ce195 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce196 = 1'b1;
end else begin
sboxes_ce196 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce197 = 1'b1;
end else begin
sboxes_ce197 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce198 = 1'b1;
end else begin
sboxes_ce198 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter9))) begin
sboxes_ce199 = 1'b1;
end else begin
sboxes_ce199 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce2 = 1'b1;
end else begin
sboxes_ce2 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce20 = 1'b1;
end else begin
sboxes_ce20 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce21 = 1'b1;
end else begin
sboxes_ce21 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce22 = 1'b1;
end else begin
sboxes_ce22 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce23 = 1'b1;
end else begin
sboxes_ce23 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce24 = 1'b1;
end else begin
sboxes_ce24 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce25 = 1'b1;
end else begin
sboxes_ce25 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce26 = 1'b1;
end else begin
sboxes_ce26 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce27 = 1'b1;
end else begin
sboxes_ce27 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce28 = 1'b1;
end else begin
sboxes_ce28 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce29 = 1'b1;
end else begin
sboxes_ce29 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce3 = 1'b1;
end else begin
sboxes_ce3 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce30 = 1'b1;
end else begin
sboxes_ce30 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce31 = 1'b1;
end else begin
sboxes_ce31 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce32 = 1'b1;
end else begin
sboxes_ce32 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce33 = 1'b1;
end else begin
sboxes_ce33 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce34 = 1'b1;
end else begin
sboxes_ce34 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce35 = 1'b1;
end else begin
sboxes_ce35 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce36 = 1'b1;
end else begin
sboxes_ce36 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce37 = 1'b1;
end else begin
sboxes_ce37 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce38 = 1'b1;
end else begin
sboxes_ce38 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
sboxes_ce39 = 1'b1;
end else begin
sboxes_ce39 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce4 = 1'b1;
end else begin
sboxes_ce4 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce40 = 1'b1;
end else begin
sboxes_ce40 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce41 = 1'b1;
end else begin
sboxes_ce41 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce42 = 1'b1;
end else begin
sboxes_ce42 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce43 = 1'b1;
end else begin
sboxes_ce43 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce44 = 1'b1;
end else begin
sboxes_ce44 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce45 = 1'b1;
end else begin
sboxes_ce45 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce46 = 1'b1;
end else begin
sboxes_ce46 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce47 = 1'b1;
end else begin
sboxes_ce47 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce48 = 1'b1;
end else begin
sboxes_ce48 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce49 = 1'b1;
end else begin
sboxes_ce49 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce5 = 1'b1;
end else begin
sboxes_ce5 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce50 = 1'b1;
end else begin
sboxes_ce50 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce51 = 1'b1;
end else begin
sboxes_ce51 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce52 = 1'b1;
end else begin
sboxes_ce52 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce53 = 1'b1;
end else begin
sboxes_ce53 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce54 = 1'b1;
end else begin
sboxes_ce54 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce55 = 1'b1;
end else begin
sboxes_ce55 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce56 = 1'b1;
end else begin
sboxes_ce56 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce57 = 1'b1;
end else begin
sboxes_ce57 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce58 = 1'b1;
end else begin
sboxes_ce58 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
sboxes_ce59 = 1'b1;
end else begin
sboxes_ce59 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce6 = 1'b1;
end else begin
sboxes_ce6 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce60 = 1'b1;
end else begin
sboxes_ce60 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce61 = 1'b1;
end else begin
sboxes_ce61 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce62 = 1'b1;
end else begin
sboxes_ce62 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce63 = 1'b1;
end else begin
sboxes_ce63 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce64 = 1'b1;
end else begin
sboxes_ce64 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce65 = 1'b1;
end else begin
sboxes_ce65 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce66 = 1'b1;
end else begin
sboxes_ce66 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce67 = 1'b1;
end else begin
sboxes_ce67 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce68 = 1'b1;
end else begin
sboxes_ce68 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce69 = 1'b1;
end else begin
sboxes_ce69 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce7 = 1'b1;
end else begin
sboxes_ce7 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce70 = 1'b1;
end else begin
sboxes_ce70 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce71 = 1'b1;
end else begin
sboxes_ce71 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce72 = 1'b1;
end else begin
sboxes_ce72 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce73 = 1'b1;
end else begin
sboxes_ce73 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce74 = 1'b1;
end else begin
sboxes_ce74 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce75 = 1'b1;
end else begin
sboxes_ce75 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce76 = 1'b1;
end else begin
sboxes_ce76 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce77 = 1'b1;
end else begin
sboxes_ce77 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce78 = 1'b1;
end else begin
sboxes_ce78 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter3))) begin
sboxes_ce79 = 1'b1;
end else begin
sboxes_ce79 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce8 = 1'b1;
end else begin
sboxes_ce8 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce80 = 1'b1;
end else begin
sboxes_ce80 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce81 = 1'b1;
end else begin
sboxes_ce81 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce82 = 1'b1;
end else begin
sboxes_ce82 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce83 = 1'b1;
end else begin
sboxes_ce83 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce84 = 1'b1;
end else begin
sboxes_ce84 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce85 = 1'b1;
end else begin
sboxes_ce85 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce86 = 1'b1;
end else begin
sboxes_ce86 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce87 = 1'b1;
end else begin
sboxes_ce87 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce88 = 1'b1;
end else begin
sboxes_ce88 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce89 = 1'b1;
end else begin
sboxes_ce89 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1))) begin
sboxes_ce9 = 1'b1;
end else begin
sboxes_ce9 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce90 = 1'b1;
end else begin
sboxes_ce90 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce91 = 1'b1;
end else begin
sboxes_ce91 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce92 = 1'b1;
end else begin
sboxes_ce92 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce93 = 1'b1;
end else begin
sboxes_ce93 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce94 = 1'b1;
end else begin
sboxes_ce94 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce95 = 1'b1;
end else begin
sboxes_ce95 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce96 = 1'b1;
end else begin
sboxes_ce96 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce97 = 1'b1;
end else begin
sboxes_ce97 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce98 = 1'b1;
end else begin
sboxes_ce98 = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (ap_ce == 1'b1) & (1'b1 == ap_enable_reg_pp0_iter4))) begin
sboxes_ce99 = 1'b1;
end else begin
sboxes_ce99 = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_pp0_stage0 : begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0];
assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_flag00011001 = ((1'b0 == ap_start) & (1'b1 == ap_start));
end
always @ (*) begin
ap_block_pp0_stage0_flag00011011 = (((1'b0 == ap_start) & (1'b1 == ap_start)) | (ap_ce == 1'b0));
end
assign ap_block_state10_pp0_stage0_iter9 = ~(1'b1 == 1'b1);
assign ap_block_state11_pp0_stage0_iter10 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state1_pp0_stage0_iter0 = (1'b0 == ap_start);
end
assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
assign ap_block_state6_pp0_stage0_iter5 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage0_iter6 = ~(1'b1 == 1'b1);
assign ap_block_state8_pp0_stage0_iter7 = ~(1'b1 == 1'b1);
assign ap_block_state9_pp0_stage0_iter8 = ~(1'b1 == 1'b1);
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign ap_enable_reg_pp0_iter0 = ap_start;
assign ap_return = {{{{{{{{{{{{{{{{tmp_38_fu_12234_p2}, {tmp_38_1_fu_12245_p2}}, {tmp_38_2_fu_12256_p2}}, {tmp_38_3_fu_12267_p2}}, {tmp_38_4_fu_12273_p2}}, {tmp_38_5_fu_12279_p2}}, {tmp_38_6_fu_12285_p2}}, {tmp_38_7_fu_12291_p2}}, {tmp_38_8_fu_12302_p2}}, {tmp_38_9_fu_12313_p2}}, {tmp_38_s_fu_12324_p2}}, {tmp_38_10_fu_12335_p2}}, {tmp_38_11_fu_12346_p2}}, {tmp_38_12_fu_12357_p2}}, {tmp_38_13_fu_12368_p2}}, {tmp_38_14_fu_12379_p2}};
assign e_0_1_fu_2985_p2 = (sboxes_q3 ^ tmp_47_0_1_fu_2979_p2);
assign e_0_2_fu_3133_p2 = (sboxes_q7 ^ tmp_47_0_2_fu_3127_p2);
assign e_0_3_fu_3281_p2 = (sboxes_q11 ^ tmp_47_0_3_fu_3275_p2);
assign e_1_1_fu_4027_p2 = (sboxes_q23 ^ tmp_47_1_1_fu_4021_p2);
assign e_1_2_fu_4175_p2 = (sboxes_q27 ^ tmp_47_1_2_fu_4169_p2);
assign e_1_3_fu_4323_p2 = (sboxes_q31 ^ tmp_47_1_3_fu_4317_p2);
assign e_1_fu_3879_p2 = (sboxes_q35 ^ tmp_47_1_fu_3873_p2);
assign e_2_1_fu_5069_p2 = (sboxes_q43 ^ tmp_47_2_1_fu_5063_p2);
assign e_2_2_fu_5217_p2 = (sboxes_q47 ^ tmp_47_2_2_fu_5211_p2);
assign e_2_3_fu_5365_p2 = (sboxes_q51 ^ tmp_47_2_3_fu_5359_p2);
assign e_2_fu_4921_p2 = (sboxes_q55 ^ tmp_47_2_fu_4915_p2);
assign e_3_1_fu_6111_p2 = (sboxes_q63 ^ tmp_47_3_1_fu_6105_p2);
assign e_3_2_fu_6259_p2 = (sboxes_q67 ^ tmp_47_3_2_fu_6253_p2);
assign e_3_3_fu_6407_p2 = (sboxes_q71 ^ tmp_47_3_3_fu_6401_p2);
assign e_3_fu_5963_p2 = (sboxes_q75 ^ tmp_47_3_fu_5957_p2);
assign e_4_1_fu_7153_p2 = (sboxes_q83 ^ tmp_47_4_1_fu_7147_p2);
assign e_4_2_fu_7301_p2 = (sboxes_q87 ^ tmp_47_4_2_fu_7295_p2);
assign e_4_3_fu_7449_p2 = (sboxes_q91 ^ tmp_47_4_3_fu_7443_p2);
assign e_4_fu_7005_p2 = (sboxes_q95 ^ tmp_47_4_fu_6999_p2);
assign e_5_1_fu_8195_p2 = (sboxes_q103 ^ tmp_47_5_1_fu_8189_p2);
assign e_5_2_fu_8343_p2 = (sboxes_q107 ^ tmp_47_5_2_fu_8337_p2);
assign e_5_3_fu_8491_p2 = (sboxes_q111 ^ tmp_47_5_3_fu_8485_p2);
assign e_5_fu_8047_p2 = (sboxes_q115 ^ tmp_47_5_fu_8041_p2);
assign e_6_1_fu_9237_p2 = (sboxes_q123 ^ tmp_47_6_1_fu_9231_p2);
assign e_6_2_fu_9385_p2 = (sboxes_q127 ^ tmp_47_6_2_fu_9379_p2);
assign e_6_3_fu_9533_p2 = (sboxes_q131 ^ tmp_47_6_3_fu_9527_p2);
assign e_6_fu_9089_p2 = (sboxes_q135 ^ tmp_47_6_fu_9083_p2);
assign e_7_1_fu_10279_p2 = (sboxes_q143 ^ tmp_47_7_1_fu_10273_p2);
assign e_7_2_fu_10427_p2 = (sboxes_q147 ^ tmp_47_7_2_fu_10421_p2);
assign e_7_3_fu_10575_p2 = (sboxes_q151 ^ tmp_47_7_3_fu_10569_p2);
assign e_7_fu_10131_p2 = (sboxes_q155 ^ tmp_47_7_fu_10125_p2);
assign e_8_1_fu_11321_p2 = (sboxes_q163 ^ tmp_47_8_1_fu_11315_p2);
assign e_8_2_fu_11469_p2 = (sboxes_q167 ^ tmp_47_8_2_fu_11463_p2);
assign e_8_3_fu_11617_p2 = (sboxes_q171 ^ tmp_47_8_3_fu_11611_p2);
assign e_8_fu_11173_p2 = (sboxes_q175 ^ tmp_47_8_fu_11167_p2);
assign e_fu_2837_p2 = (sboxes_q15 ^ tmp_47_fu_2831_p2);
assign p_Result_10_fu_2521_p4 = {{inptext_V_read[47:40]}};
assign p_Result_11_fu_2541_p4 = {{inptext_V_read[39:32]}};
assign p_Result_12_fu_2561_p4 = {{inptext_V_read[31:24]}};
assign p_Result_13_fu_2581_p4 = {{inptext_V_read[23:16]}};
assign p_Result_14_fu_2601_p4 = {{inptext_V_read[15:8]}};
assign p_Result_1_10_fu_2551_p4 = {{key_V_read[39:32]}};
assign p_Result_1_11_fu_2571_p4 = {{key_V_read[31:24]}};
assign p_Result_1_12_fu_2591_p4 = {{key_V_read[23:16]}};
assign p_Result_1_13_fu_2611_p4 = {{key_V_read[15:8]}};
assign p_Result_1_1_fu_2351_p4 = {{key_V_read[119:112]}};
assign p_Result_1_2_fu_2371_p4 = {{key_V_read[111:104]}};
assign p_Result_1_3_fu_2391_p4 = {{key_V_read[103:96]}};
assign p_Result_1_4_fu_2411_p4 = {{key_V_read[95:88]}};
assign p_Result_1_5_fu_2431_p4 = {{key_V_read[87:80]}};
assign p_Result_1_6_fu_2451_p4 = {{key_V_read[79:72]}};
assign p_Result_1_7_fu_2471_p4 = {{key_V_read[71:64]}};
assign p_Result_1_8_fu_2491_p4 = {{key_V_read[63:56]}};
assign p_Result_1_9_fu_2511_p4 = {{key_V_read[55:48]}};
assign p_Result_1_fu_2331_p4 = {{key_V_read[127:120]}};
assign p_Result_1_s_fu_2531_p4 = {{key_V_read[47:40]}};
assign p_Result_2_fu_2361_p4 = {{inptext_V_read[111:104]}};
assign p_Result_3_fu_2381_p4 = {{inptext_V_read[103:96]}};
assign p_Result_4_fu_2401_p4 = {{inptext_V_read[95:88]}};
assign p_Result_5_fu_2421_p4 = {{inptext_V_read[87:80]}};
assign p_Result_6_fu_2441_p4 = {{inptext_V_read[79:72]}};
assign p_Result_7_fu_2461_p4 = {{inptext_V_read[71:64]}};
assign p_Result_8_fu_2481_p4 = {{inptext_V_read[63:56]}};
assign p_Result_9_fu_2501_p4 = {{inptext_V_read[55:48]}};
assign p_Result_s_39_fu_2341_p4 = {{inptext_V_read[119:112]}};
assign p_Result_s_fu_2321_p4 = {{inptext_V_read[127:120]}};
assign rv_10_0_1_fu_3107_p2 = (tmp_115_fu_3093_p2 ^ 8'd27);
assign rv_10_0_2_fu_3255_p2 = (tmp_123_fu_3241_p2 ^ 8'd27);
assign rv_10_0_3_fu_3403_p2 = (tmp_131_fu_3389_p2 ^ 8'd27);
assign rv_10_1_1_fu_4149_p2 = (tmp_147_fu_4135_p2 ^ 8'd27);
assign rv_10_1_2_fu_4297_p2 = (tmp_155_fu_4283_p2 ^ 8'd27);
assign rv_10_1_3_fu_4445_p2 = (tmp_163_fu_4431_p2 ^ 8'd27);
assign rv_10_1_fu_4001_p2 = (tmp_139_fu_3987_p2 ^ 8'd27);
assign rv_10_2_1_fu_5191_p2 = (tmp_179_fu_5177_p2 ^ 8'd27);
assign rv_10_2_2_fu_5339_p2 = (tmp_187_fu_5325_p2 ^ 8'd27);
assign rv_10_2_3_fu_5487_p2 = (tmp_195_fu_5473_p2 ^ 8'd27);
assign rv_10_2_fu_5043_p2 = (tmp_171_fu_5029_p2 ^ 8'd27);
assign rv_10_3_1_fu_6233_p2 = (tmp_211_fu_6219_p2 ^ 8'd27);
assign rv_10_3_2_fu_6381_p2 = (tmp_219_fu_6367_p2 ^ 8'd27);
assign rv_10_3_3_fu_6529_p2 = (tmp_227_fu_6515_p2 ^ 8'd27);
assign rv_10_3_fu_6085_p2 = (tmp_203_fu_6071_p2 ^ 8'd27);
assign rv_10_4_1_fu_7275_p2 = (tmp_243_fu_7261_p2 ^ 8'd27);
assign rv_10_4_2_fu_7423_p2 = (tmp_251_fu_7409_p2 ^ 8'd27);
assign rv_10_4_3_fu_7571_p2 = (tmp_259_fu_7557_p2 ^ 8'd27);
assign rv_10_4_fu_7127_p2 = (tmp_235_fu_7113_p2 ^ 8'd27);
assign rv_10_5_1_fu_8317_p2 = (tmp_275_fu_8303_p2 ^ 8'd27);
assign rv_10_5_2_fu_8465_p2 = (tmp_283_fu_8451_p2 ^ 8'd27);
assign rv_10_5_3_fu_8613_p2 = (tmp_291_fu_8599_p2 ^ 8'd27);
assign rv_10_5_fu_8169_p2 = (tmp_267_fu_8155_p2 ^ 8'd27);
assign rv_10_6_1_fu_9359_p2 = (tmp_307_fu_9345_p2 ^ 8'd27);
assign rv_10_6_2_fu_9507_p2 = (tmp_315_fu_9493_p2 ^ 8'd27);
assign rv_10_6_3_fu_9655_p2 = (tmp_323_fu_9641_p2 ^ 8'd27);
assign rv_10_6_fu_9211_p2 = (tmp_299_fu_9197_p2 ^ 8'd27);
assign rv_10_7_1_fu_10401_p2 = (tmp_339_fu_10387_p2 ^ 8'd27);
assign rv_10_7_2_fu_10549_p2 = (tmp_347_fu_10535_p2 ^ 8'd27);
assign rv_10_7_3_fu_10697_p2 = (tmp_355_fu_10683_p2 ^ 8'd27);
assign rv_10_7_fu_10253_p2 = (tmp_331_fu_10239_p2 ^ 8'd27);
assign rv_10_8_1_fu_11443_p2 = (tmp_371_fu_11429_p2 ^ 8'd27);
assign rv_10_8_2_fu_11591_p2 = (tmp_379_fu_11577_p2 ^ 8'd27);
assign rv_10_8_3_fu_11739_p2 = (tmp_387_fu_11725_p2 ^ 8'd27);
assign rv_10_8_fu_11295_p2 = (tmp_363_fu_11281_p2 ^ 8'd27);
assign rv_11_0_1_fu_3113_p3 = ((tmp_116_fu_3099_p3[0:0] === 1'b1) ? rv_10_0_1_fu_3107_p2 : tmp_115_fu_3093_p2);
assign rv_11_0_2_fu_3261_p3 = ((tmp_124_fu_3247_p3[0:0] === 1'b1) ? rv_10_0_2_fu_3255_p2 : tmp_123_fu_3241_p2);
assign rv_11_0_3_fu_3409_p3 = ((tmp_132_fu_3395_p3[0:0] === 1'b1) ? rv_10_0_3_fu_3403_p2 : tmp_131_fu_3389_p2);
assign rv_11_1_1_fu_4155_p3 = ((tmp_148_fu_4141_p3[0:0] === 1'b1) ? rv_10_1_1_fu_4149_p2 : tmp_147_fu_4135_p2);
assign rv_11_1_2_fu_4303_p3 = ((tmp_156_fu_4289_p3[0:0] === 1'b1) ? rv_10_1_2_fu_4297_p2 : tmp_155_fu_4283_p2);
assign rv_11_1_3_fu_4451_p3 = ((tmp_164_fu_4437_p3[0:0] === 1'b1) ? rv_10_1_3_fu_4445_p2 : tmp_163_fu_4431_p2);
assign rv_11_1_fu_4007_p3 = ((tmp_140_fu_3993_p3[0:0] === 1'b1) ? rv_10_1_fu_4001_p2 : tmp_139_fu_3987_p2);
assign rv_11_2_1_fu_5197_p3 = ((tmp_180_fu_5183_p3[0:0] === 1'b1) ? rv_10_2_1_fu_5191_p2 : tmp_179_fu_5177_p2);
assign rv_11_2_2_fu_5345_p3 = ((tmp_188_fu_5331_p3[0:0] === 1'b1) ? rv_10_2_2_fu_5339_p2 : tmp_187_fu_5325_p2);
assign rv_11_2_3_fu_5493_p3 = ((tmp_196_fu_5479_p3[0:0] === 1'b1) ? rv_10_2_3_fu_5487_p2 : tmp_195_fu_5473_p2);
assign rv_11_2_fu_5049_p3 = ((tmp_172_fu_5035_p3[0:0] === 1'b1) ? rv_10_2_fu_5043_p2 : tmp_171_fu_5029_p2);
assign rv_11_3_1_fu_6239_p3 = ((tmp_212_fu_6225_p3[0:0] === 1'b1) ? rv_10_3_1_fu_6233_p2 : tmp_211_fu_6219_p2);
assign rv_11_3_2_fu_6387_p3 = ((tmp_220_fu_6373_p3[0:0] === 1'b1) ? rv_10_3_2_fu_6381_p2 : tmp_219_fu_6367_p2);
assign rv_11_3_3_fu_6535_p3 = ((tmp_228_fu_6521_p3[0:0] === 1'b1) ? rv_10_3_3_fu_6529_p2 : tmp_227_fu_6515_p2);
assign rv_11_3_fu_6091_p3 = ((tmp_204_fu_6077_p3[0:0] === 1'b1) ? rv_10_3_fu_6085_p2 : tmp_203_fu_6071_p2);
assign rv_11_4_1_fu_7281_p3 = ((tmp_244_fu_7267_p3[0:0] === 1'b1) ? rv_10_4_1_fu_7275_p2 : tmp_243_fu_7261_p2);
assign rv_11_4_2_fu_7429_p3 = ((tmp_252_fu_7415_p3[0:0] === 1'b1) ? rv_10_4_2_fu_7423_p2 : tmp_251_fu_7409_p2);
assign rv_11_4_3_fu_7577_p3 = ((tmp_260_fu_7563_p3[0:0] === 1'b1) ? rv_10_4_3_fu_7571_p2 : tmp_259_fu_7557_p2);
assign rv_11_4_fu_7133_p3 = ((tmp_236_fu_7119_p3[0:0] === 1'b1) ? rv_10_4_fu_7127_p2 : tmp_235_fu_7113_p2);
assign rv_11_5_1_fu_8323_p3 = ((tmp_276_fu_8309_p3[0:0] === 1'b1) ? rv_10_5_1_fu_8317_p2 : tmp_275_fu_8303_p2);
assign rv_11_5_2_fu_8471_p3 = ((tmp_284_fu_8457_p3[0:0] === 1'b1) ? rv_10_5_2_fu_8465_p2 : tmp_283_fu_8451_p2);
assign rv_11_5_3_fu_8619_p3 = ((tmp_292_fu_8605_p3[0:0] === 1'b1) ? rv_10_5_3_fu_8613_p2 : tmp_291_fu_8599_p2);
assign rv_11_5_fu_8175_p3 = ((tmp_268_fu_8161_p3[0:0] === 1'b1) ? rv_10_5_fu_8169_p2 : tmp_267_fu_8155_p2);
assign rv_11_6_1_fu_9365_p3 = ((tmp_308_fu_9351_p3[0:0] === 1'b1) ? rv_10_6_1_fu_9359_p2 : tmp_307_fu_9345_p2);
assign rv_11_6_2_fu_9513_p3 = ((tmp_316_fu_9499_p3[0:0] === 1'b1) ? rv_10_6_2_fu_9507_p2 : tmp_315_fu_9493_p2);
assign rv_11_6_3_fu_9661_p3 = ((tmp_324_fu_9647_p3[0:0] === 1'b1) ? rv_10_6_3_fu_9655_p2 : tmp_323_fu_9641_p2);
assign rv_11_6_fu_9217_p3 = ((tmp_300_fu_9203_p3[0:0] === 1'b1) ? rv_10_6_fu_9211_p2 : tmp_299_fu_9197_p2);
assign rv_11_7_1_fu_10407_p3 = ((tmp_340_fu_10393_p3[0:0] === 1'b1) ? rv_10_7_1_fu_10401_p2 : tmp_339_fu_10387_p2);
assign rv_11_7_2_fu_10555_p3 = ((tmp_348_fu_10541_p3[0:0] === 1'b1) ? rv_10_7_2_fu_10549_p2 : tmp_347_fu_10535_p2);
assign rv_11_7_3_fu_10703_p3 = ((tmp_356_fu_10689_p3[0:0] === 1'b1) ? rv_10_7_3_fu_10697_p2 : tmp_355_fu_10683_p2);
assign rv_11_7_fu_10259_p3 = ((tmp_332_fu_10245_p3[0:0] === 1'b1) ? rv_10_7_fu_10253_p2 : tmp_331_fu_10239_p2);
assign rv_11_8_1_fu_11449_p3 = ((tmp_372_fu_11435_p3[0:0] === 1'b1) ? rv_10_8_1_fu_11443_p2 : tmp_371_fu_11429_p2);
assign rv_11_8_2_fu_11597_p3 = ((tmp_380_fu_11583_p3[0:0] === 1'b1) ? rv_10_8_2_fu_11591_p2 : tmp_379_fu_11577_p2);
assign rv_11_8_3_fu_11745_p3 = ((tmp_388_fu_11731_p3[0:0] === 1'b1) ? rv_10_8_3_fu_11739_p2 : tmp_387_fu_11725_p2);
assign rv_11_8_fu_11301_p3 = ((tmp_364_fu_11287_p3[0:0] === 1'b1) ? rv_10_8_fu_11295_p2 : tmp_363_fu_11281_p2);
assign rv_1_0_1_fu_3005_p2 = (tmp_109_fu_2991_p2 ^ 8'd27);
assign rv_1_0_2_fu_3153_p2 = (tmp_117_fu_3139_p2 ^ 8'd27);
assign rv_1_0_3_fu_3301_p2 = (tmp_125_fu_3287_p2 ^ 8'd27);
assign rv_1_1_1_fu_4047_p2 = (tmp_141_fu_4033_p2 ^ 8'd27);
assign rv_1_1_2_fu_4195_p2 = (tmp_149_fu_4181_p2 ^ 8'd27);
assign rv_1_1_3_fu_4343_p2 = (tmp_157_fu_4329_p2 ^ 8'd27);
assign rv_1_1_fu_3899_p2 = (tmp_133_fu_3885_p2 ^ 8'd27);
assign rv_1_2_1_fu_5089_p2 = (tmp_173_fu_5075_p2 ^ 8'd27);
assign rv_1_2_2_fu_5237_p2 = (tmp_181_fu_5223_p2 ^ 8'd27);
assign rv_1_2_3_fu_5385_p2 = (tmp_189_fu_5371_p2 ^ 8'd27);
assign rv_1_2_fu_4941_p2 = (tmp_165_fu_4927_p2 ^ 8'd27);
assign rv_1_3_1_fu_6131_p2 = (tmp_205_fu_6117_p2 ^ 8'd27);
assign rv_1_3_2_fu_6279_p2 = (tmp_213_fu_6265_p2 ^ 8'd27);
assign rv_1_3_3_fu_6427_p2 = (tmp_221_fu_6413_p2 ^ 8'd27);
assign rv_1_3_fu_5983_p2 = (tmp_197_fu_5969_p2 ^ 8'd27);
assign rv_1_4_1_fu_7173_p2 = (tmp_237_fu_7159_p2 ^ 8'd27);
assign rv_1_4_2_fu_7321_p2 = (tmp_245_fu_7307_p2 ^ 8'd27);
assign rv_1_4_3_fu_7469_p2 = (tmp_253_fu_7455_p2 ^ 8'd27);
assign rv_1_4_fu_7025_p2 = (tmp_229_fu_7011_p2 ^ 8'd27);
assign rv_1_5_1_fu_8215_p2 = (tmp_269_fu_8201_p2 ^ 8'd27);
assign rv_1_5_2_fu_8363_p2 = (tmp_277_fu_8349_p2 ^ 8'd27);
assign rv_1_5_3_fu_8511_p2 = (tmp_285_fu_8497_p2 ^ 8'd27);
assign rv_1_5_fu_8067_p2 = (tmp_261_fu_8053_p2 ^ 8'd27);
assign rv_1_6_1_fu_9257_p2 = (tmp_301_fu_9243_p2 ^ 8'd27);
assign rv_1_6_2_fu_9405_p2 = (tmp_309_fu_9391_p2 ^ 8'd27);
assign rv_1_6_3_fu_9553_p2 = (tmp_317_fu_9539_p2 ^ 8'd27);
assign rv_1_6_fu_9109_p2 = (tmp_293_fu_9095_p2 ^ 8'd27);
assign rv_1_7_1_fu_10299_p2 = (tmp_333_fu_10285_p2 ^ 8'd27);
assign rv_1_7_2_fu_10447_p2 = (tmp_341_fu_10433_p2 ^ 8'd27);
assign rv_1_7_3_fu_10595_p2 = (tmp_349_fu_10581_p2 ^ 8'd27);
assign rv_1_7_fu_10151_p2 = (tmp_325_fu_10137_p2 ^ 8'd27);
assign rv_1_8_1_fu_11341_p2 = (tmp_365_fu_11327_p2 ^ 8'd27);
assign rv_1_8_2_fu_11489_p2 = (tmp_373_fu_11475_p2 ^ 8'd27);
assign rv_1_8_3_fu_11637_p2 = (tmp_381_fu_11623_p2 ^ 8'd27);
assign rv_1_8_fu_11193_p2 = (tmp_357_fu_11179_p2 ^ 8'd27);
assign rv_1_fu_2857_p2 = (tmp_101_fu_2843_p2 ^ 8'd27);
assign rv_2_0_1_fu_3011_p3 = ((tmp_110_fu_2997_p3[0:0] === 1'b1) ? rv_1_0_1_fu_3005_p2 : tmp_109_fu_2991_p2);
assign rv_2_0_2_fu_3159_p3 = ((tmp_118_fu_3145_p3[0:0] === 1'b1) ? rv_1_0_2_fu_3153_p2 : tmp_117_fu_3139_p2);
assign rv_2_0_3_fu_3307_p3 = ((tmp_126_fu_3293_p3[0:0] === 1'b1) ? rv_1_0_3_fu_3301_p2 : tmp_125_fu_3287_p2);
assign rv_2_1_1_fu_4053_p3 = ((tmp_142_fu_4039_p3[0:0] === 1'b1) ? rv_1_1_1_fu_4047_p2 : tmp_141_fu_4033_p2);
assign rv_2_1_2_fu_4201_p3 = ((tmp_150_fu_4187_p3[0:0] === 1'b1) ? rv_1_1_2_fu_4195_p2 : tmp_149_fu_4181_p2);
assign rv_2_1_3_fu_4349_p3 = ((tmp_158_fu_4335_p3[0:0] === 1'b1) ? rv_1_1_3_fu_4343_p2 : tmp_157_fu_4329_p2);
assign rv_2_1_fu_3905_p3 = ((tmp_134_fu_3891_p3[0:0] === 1'b1) ? rv_1_1_fu_3899_p2 : tmp_133_fu_3885_p2);
assign rv_2_2_1_fu_5095_p3 = ((tmp_174_fu_5081_p3[0:0] === 1'b1) ? rv_1_2_1_fu_5089_p2 : tmp_173_fu_5075_p2);
assign rv_2_2_2_fu_5243_p3 = ((tmp_182_fu_5229_p3[0:0] === 1'b1) ? rv_1_2_2_fu_5237_p2 : tmp_181_fu_5223_p2);
assign rv_2_2_3_fu_5391_p3 = ((tmp_190_fu_5377_p3[0:0] === 1'b1) ? rv_1_2_3_fu_5385_p2 : tmp_189_fu_5371_p2);
assign rv_2_2_fu_4947_p3 = ((tmp_166_fu_4933_p3[0:0] === 1'b1) ? rv_1_2_fu_4941_p2 : tmp_165_fu_4927_p2);
assign rv_2_3_1_fu_6137_p3 = ((tmp_206_fu_6123_p3[0:0] === 1'b1) ? rv_1_3_1_fu_6131_p2 : tmp_205_fu_6117_p2);
assign rv_2_3_2_fu_6285_p3 = ((tmp_214_fu_6271_p3[0:0] === 1'b1) ? rv_1_3_2_fu_6279_p2 : tmp_213_fu_6265_p2);
assign rv_2_3_3_fu_6433_p3 = ((tmp_222_fu_6419_p3[0:0] === 1'b1) ? rv_1_3_3_fu_6427_p2 : tmp_221_fu_6413_p2);
assign rv_2_3_fu_5989_p3 = ((tmp_198_fu_5975_p3[0:0] === 1'b1) ? rv_1_3_fu_5983_p2 : tmp_197_fu_5969_p2);
assign rv_2_4_1_fu_7179_p3 = ((tmp_238_fu_7165_p3[0:0] === 1'b1) ? rv_1_4_1_fu_7173_p2 : tmp_237_fu_7159_p2);
assign rv_2_4_2_fu_7327_p3 = ((tmp_246_fu_7313_p3[0:0] === 1'b1) ? rv_1_4_2_fu_7321_p2 : tmp_245_fu_7307_p2);
assign rv_2_4_3_fu_7475_p3 = ((tmp_254_fu_7461_p3[0:0] === 1'b1) ? rv_1_4_3_fu_7469_p2 : tmp_253_fu_7455_p2);
assign rv_2_4_fu_7031_p3 = ((tmp_230_fu_7017_p3[0:0] === 1'b1) ? rv_1_4_fu_7025_p2 : tmp_229_fu_7011_p2);
assign rv_2_5_1_fu_8221_p3 = ((tmp_270_fu_8207_p3[0:0] === 1'b1) ? rv_1_5_1_fu_8215_p2 : tmp_269_fu_8201_p2);
assign rv_2_5_2_fu_8369_p3 = ((tmp_278_fu_8355_p3[0:0] === 1'b1) ? rv_1_5_2_fu_8363_p2 : tmp_277_fu_8349_p2);
assign rv_2_5_3_fu_8517_p3 = ((tmp_286_fu_8503_p3[0:0] === 1'b1) ? rv_1_5_3_fu_8511_p2 : tmp_285_fu_8497_p2);
assign rv_2_5_fu_8073_p3 = ((tmp_262_fu_8059_p3[0:0] === 1'b1) ? rv_1_5_fu_8067_p2 : tmp_261_fu_8053_p2);
assign rv_2_6_1_fu_9263_p3 = ((tmp_302_fu_9249_p3[0:0] === 1'b1) ? rv_1_6_1_fu_9257_p2 : tmp_301_fu_9243_p2);
assign rv_2_6_2_fu_9411_p3 = ((tmp_310_fu_9397_p3[0:0] === 1'b1) ? rv_1_6_2_fu_9405_p2 : tmp_309_fu_9391_p2);
assign rv_2_6_3_fu_9559_p3 = ((tmp_318_fu_9545_p3[0:0] === 1'b1) ? rv_1_6_3_fu_9553_p2 : tmp_317_fu_9539_p2);
assign rv_2_6_fu_9115_p3 = ((tmp_294_fu_9101_p3[0:0] === 1'b1) ? rv_1_6_fu_9109_p2 : tmp_293_fu_9095_p2);
assign rv_2_7_1_fu_10305_p3 = ((tmp_334_fu_10291_p3[0:0] === 1'b1) ? rv_1_7_1_fu_10299_p2 : tmp_333_fu_10285_p2);
assign rv_2_7_2_fu_10453_p3 = ((tmp_342_fu_10439_p3[0:0] === 1'b1) ? rv_1_7_2_fu_10447_p2 : tmp_341_fu_10433_p2);
assign rv_2_7_3_fu_10601_p3 = ((tmp_350_fu_10587_p3[0:0] === 1'b1) ? rv_1_7_3_fu_10595_p2 : tmp_349_fu_10581_p2);
assign rv_2_7_fu_10157_p3 = ((tmp_326_fu_10143_p3[0:0] === 1'b1) ? rv_1_7_fu_10151_p2 : tmp_325_fu_10137_p2);
assign rv_2_8_1_fu_11347_p3 = ((tmp_366_fu_11333_p3[0:0] === 1'b1) ? rv_1_8_1_fu_11341_p2 : tmp_365_fu_11327_p2);
assign rv_2_8_2_fu_11495_p3 = ((tmp_374_fu_11481_p3[0:0] === 1'b1) ? rv_1_8_2_fu_11489_p2 : tmp_373_fu_11475_p2);
assign rv_2_8_3_fu_11643_p3 = ((tmp_382_fu_11629_p3[0:0] === 1'b1) ? rv_1_8_3_fu_11637_p2 : tmp_381_fu_11623_p2);
assign rv_2_8_fu_11199_p3 = ((tmp_358_fu_11185_p3[0:0] === 1'b1) ? rv_1_8_fu_11193_p2 : tmp_357_fu_11179_p2);
assign rv_2_fu_2863_p3 = ((tmp_102_fu_2849_p3[0:0] === 1'b1) ? rv_1_fu_2857_p2 : tmp_101_fu_2843_p2);
assign rv_3_fu_2965_p3 = ((tmp_108_fu_2951_p3[0:0] === 1'b1) ? rv_s_fu_2959_p2 : tmp_107_fu_2945_p2);
assign rv_4_0_1_fu_3039_p2 = (tmp_111_fu_3025_p2 ^ 8'd27);
assign rv_4_0_2_fu_3187_p2 = (tmp_119_fu_3173_p2 ^ 8'd27);
assign rv_4_0_3_fu_3335_p2 = (tmp_127_fu_3321_p2 ^ 8'd27);
assign rv_4_1_1_fu_4081_p2 = (tmp_143_fu_4067_p2 ^ 8'd27);
assign rv_4_1_2_fu_4229_p2 = (tmp_151_fu_4215_p2 ^ 8'd27);
assign rv_4_1_3_fu_4377_p2 = (tmp_159_fu_4363_p2 ^ 8'd27);
assign rv_4_1_fu_3933_p2 = (tmp_135_fu_3919_p2 ^ 8'd27);
assign rv_4_2_1_fu_5123_p2 = (tmp_175_fu_5109_p2 ^ 8'd27);
assign rv_4_2_2_fu_5271_p2 = (tmp_183_fu_5257_p2 ^ 8'd27);
assign rv_4_2_3_fu_5419_p2 = (tmp_191_fu_5405_p2 ^ 8'd27);
assign rv_4_2_fu_4975_p2 = (tmp_167_fu_4961_p2 ^ 8'd27);
assign rv_4_3_1_fu_6165_p2 = (tmp_207_fu_6151_p2 ^ 8'd27);
assign rv_4_3_2_fu_6313_p2 = (tmp_215_fu_6299_p2 ^ 8'd27);
assign rv_4_3_3_fu_6461_p2 = (tmp_223_fu_6447_p2 ^ 8'd27);
assign rv_4_3_fu_6017_p2 = (tmp_199_fu_6003_p2 ^ 8'd27);
assign rv_4_4_1_fu_7207_p2 = (tmp_239_fu_7193_p2 ^ 8'd27);
assign rv_4_4_2_fu_7355_p2 = (tmp_247_fu_7341_p2 ^ 8'd27);
assign rv_4_4_3_fu_7503_p2 = (tmp_255_fu_7489_p2 ^ 8'd27);
assign rv_4_4_fu_7059_p2 = (tmp_231_fu_7045_p2 ^ 8'd27);
assign rv_4_5_1_fu_8249_p2 = (tmp_271_fu_8235_p2 ^ 8'd27);
assign rv_4_5_2_fu_8397_p2 = (tmp_279_fu_8383_p2 ^ 8'd27);
assign rv_4_5_3_fu_8545_p2 = (tmp_287_fu_8531_p2 ^ 8'd27);
assign rv_4_5_fu_8101_p2 = (tmp_263_fu_8087_p2 ^ 8'd27);
assign rv_4_6_1_fu_9291_p2 = (tmp_303_fu_9277_p2 ^ 8'd27);
assign rv_4_6_2_fu_9439_p2 = (tmp_311_fu_9425_p2 ^ 8'd27);
assign rv_4_6_3_fu_9587_p2 = (tmp_319_fu_9573_p2 ^ 8'd27);
assign rv_4_6_fu_9143_p2 = (tmp_295_fu_9129_p2 ^ 8'd27);
assign rv_4_7_1_fu_10333_p2 = (tmp_335_fu_10319_p2 ^ 8'd27);
assign rv_4_7_2_fu_10481_p2 = (tmp_343_fu_10467_p2 ^ 8'd27);
assign rv_4_7_3_fu_10629_p2 = (tmp_351_fu_10615_p2 ^ 8'd27);
assign rv_4_7_fu_10185_p2 = (tmp_327_fu_10171_p2 ^ 8'd27);
assign rv_4_8_1_fu_11375_p2 = (tmp_367_fu_11361_p2 ^ 8'd27);
assign rv_4_8_2_fu_11523_p2 = (tmp_375_fu_11509_p2 ^ 8'd27);
assign rv_4_8_3_fu_11671_p2 = (tmp_383_fu_11657_p2 ^ 8'd27);
assign rv_4_8_fu_11227_p2 = (tmp_359_fu_11213_p2 ^ 8'd27);
assign rv_4_fu_2891_p2 = (tmp_103_fu_2877_p2 ^ 8'd27);
assign rv_5_0_1_fu_3045_p3 = ((tmp_112_fu_3031_p3[0:0] === 1'b1) ? rv_4_0_1_fu_3039_p2 : tmp_111_fu_3025_p2);
assign rv_5_0_2_fu_3193_p3 = ((tmp_120_fu_3179_p3[0:0] === 1'b1) ? rv_4_0_2_fu_3187_p2 : tmp_119_fu_3173_p2);
assign rv_5_0_3_fu_3341_p3 = ((tmp_128_fu_3327_p3[0:0] === 1'b1) ? rv_4_0_3_fu_3335_p2 : tmp_127_fu_3321_p2);
assign rv_5_1_1_fu_4087_p3 = ((tmp_144_fu_4073_p3[0:0] === 1'b1) ? rv_4_1_1_fu_4081_p2 : tmp_143_fu_4067_p2);
assign rv_5_1_2_fu_4235_p3 = ((tmp_152_fu_4221_p3[0:0] === 1'b1) ? rv_4_1_2_fu_4229_p2 : tmp_151_fu_4215_p2);
assign rv_5_1_3_fu_4383_p3 = ((tmp_160_fu_4369_p3[0:0] === 1'b1) ? rv_4_1_3_fu_4377_p2 : tmp_159_fu_4363_p2);
assign rv_5_1_fu_3939_p3 = ((tmp_136_fu_3925_p3[0:0] === 1'b1) ? rv_4_1_fu_3933_p2 : tmp_135_fu_3919_p2);
assign rv_5_2_1_fu_5129_p3 = ((tmp_176_fu_5115_p3[0:0] === 1'b1) ? rv_4_2_1_fu_5123_p2 : tmp_175_fu_5109_p2);
assign rv_5_2_2_fu_5277_p3 = ((tmp_184_fu_5263_p3[0:0] === 1'b1) ? rv_4_2_2_fu_5271_p2 : tmp_183_fu_5257_p2);
assign rv_5_2_3_fu_5425_p3 = ((tmp_192_fu_5411_p3[0:0] === 1'b1) ? rv_4_2_3_fu_5419_p2 : tmp_191_fu_5405_p2);
assign rv_5_2_fu_4981_p3 = ((tmp_168_fu_4967_p3[0:0] === 1'b1) ? rv_4_2_fu_4975_p2 : tmp_167_fu_4961_p2);
assign rv_5_3_1_fu_6171_p3 = ((tmp_208_fu_6157_p3[0:0] === 1'b1) ? rv_4_3_1_fu_6165_p2 : tmp_207_fu_6151_p2);
assign rv_5_3_2_fu_6319_p3 = ((tmp_216_fu_6305_p3[0:0] === 1'b1) ? rv_4_3_2_fu_6313_p2 : tmp_215_fu_6299_p2);
assign rv_5_3_3_fu_6467_p3 = ((tmp_224_fu_6453_p3[0:0] === 1'b1) ? rv_4_3_3_fu_6461_p2 : tmp_223_fu_6447_p2);
assign rv_5_3_fu_6023_p3 = ((tmp_200_fu_6009_p3[0:0] === 1'b1) ? rv_4_3_fu_6017_p2 : tmp_199_fu_6003_p2);
assign rv_5_4_1_fu_7213_p3 = ((tmp_240_fu_7199_p3[0:0] === 1'b1) ? rv_4_4_1_fu_7207_p2 : tmp_239_fu_7193_p2);
assign rv_5_4_2_fu_7361_p3 = ((tmp_248_fu_7347_p3[0:0] === 1'b1) ? rv_4_4_2_fu_7355_p2 : tmp_247_fu_7341_p2);
assign rv_5_4_3_fu_7509_p3 = ((tmp_256_fu_7495_p3[0:0] === 1'b1) ? rv_4_4_3_fu_7503_p2 : tmp_255_fu_7489_p2);
assign rv_5_4_fu_7065_p3 = ((tmp_232_fu_7051_p3[0:0] === 1'b1) ? rv_4_4_fu_7059_p2 : tmp_231_fu_7045_p2);
assign rv_5_5_1_fu_8255_p3 = ((tmp_272_fu_8241_p3[0:0] === 1'b1) ? rv_4_5_1_fu_8249_p2 : tmp_271_fu_8235_p2);
assign rv_5_5_2_fu_8403_p3 = ((tmp_280_fu_8389_p3[0:0] === 1'b1) ? rv_4_5_2_fu_8397_p2 : tmp_279_fu_8383_p2);
assign rv_5_5_3_fu_8551_p3 = ((tmp_288_fu_8537_p3[0:0] === 1'b1) ? rv_4_5_3_fu_8545_p2 : tmp_287_fu_8531_p2);
assign rv_5_5_fu_8107_p3 = ((tmp_264_fu_8093_p3[0:0] === 1'b1) ? rv_4_5_fu_8101_p2 : tmp_263_fu_8087_p2);
assign rv_5_6_1_fu_9297_p3 = ((tmp_304_fu_9283_p3[0:0] === 1'b1) ? rv_4_6_1_fu_9291_p2 : tmp_303_fu_9277_p2);
assign rv_5_6_2_fu_9445_p3 = ((tmp_312_fu_9431_p3[0:0] === 1'b1) ? rv_4_6_2_fu_9439_p2 : tmp_311_fu_9425_p2);
assign rv_5_6_3_fu_9593_p3 = ((tmp_320_fu_9579_p3[0:0] === 1'b1) ? rv_4_6_3_fu_9587_p2 : tmp_319_fu_9573_p2);
assign rv_5_6_fu_9149_p3 = ((tmp_296_fu_9135_p3[0:0] === 1'b1) ? rv_4_6_fu_9143_p2 : tmp_295_fu_9129_p2);
assign rv_5_7_1_fu_10339_p3 = ((tmp_336_fu_10325_p3[0:0] === 1'b1) ? rv_4_7_1_fu_10333_p2 : tmp_335_fu_10319_p2);
assign rv_5_7_2_fu_10487_p3 = ((tmp_344_fu_10473_p3[0:0] === 1'b1) ? rv_4_7_2_fu_10481_p2 : tmp_343_fu_10467_p2);
assign rv_5_7_3_fu_10635_p3 = ((tmp_352_fu_10621_p3[0:0] === 1'b1) ? rv_4_7_3_fu_10629_p2 : tmp_351_fu_10615_p2);
assign rv_5_7_fu_10191_p3 = ((tmp_328_fu_10177_p3[0:0] === 1'b1) ? rv_4_7_fu_10185_p2 : tmp_327_fu_10171_p2);
assign rv_5_8_1_fu_11381_p3 = ((tmp_368_fu_11367_p3[0:0] === 1'b1) ? rv_4_8_1_fu_11375_p2 : tmp_367_fu_11361_p2);
assign rv_5_8_2_fu_11529_p3 = ((tmp_376_fu_11515_p3[0:0] === 1'b1) ? rv_4_8_2_fu_11523_p2 : tmp_375_fu_11509_p2);
assign rv_5_8_3_fu_11677_p3 = ((tmp_384_fu_11663_p3[0:0] === 1'b1) ? rv_4_8_3_fu_11671_p2 : tmp_383_fu_11657_p2);
assign rv_5_8_fu_11233_p3 = ((tmp_360_fu_11219_p3[0:0] === 1'b1) ? rv_4_8_fu_11227_p2 : tmp_359_fu_11213_p2);
assign rv_5_fu_2897_p3 = ((tmp_104_fu_2883_p3[0:0] === 1'b1) ? rv_4_fu_2891_p2 : tmp_103_fu_2877_p2);
assign rv_7_0_1_fu_3073_p2 = (tmp_113_fu_3059_p2 ^ 8'd27);
assign rv_7_0_2_fu_3221_p2 = (tmp_121_fu_3207_p2 ^ 8'd27);
assign rv_7_0_3_fu_3369_p2 = (tmp_129_fu_3355_p2 ^ 8'd27);
assign rv_7_1_1_fu_4115_p2 = (tmp_145_fu_4101_p2 ^ 8'd27);
assign rv_7_1_2_fu_4263_p2 = (tmp_153_fu_4249_p2 ^ 8'd27);
assign rv_7_1_3_fu_4411_p2 = (tmp_161_fu_4397_p2 ^ 8'd27);
assign rv_7_1_fu_3967_p2 = (tmp_137_fu_3953_p2 ^ 8'd27);
assign rv_7_2_1_fu_5157_p2 = (tmp_177_fu_5143_p2 ^ 8'd27);
assign rv_7_2_2_fu_5305_p2 = (tmp_185_fu_5291_p2 ^ 8'd27);
assign rv_7_2_3_fu_5453_p2 = (tmp_193_fu_5439_p2 ^ 8'd27);
assign rv_7_2_fu_5009_p2 = (tmp_169_fu_4995_p2 ^ 8'd27);
assign rv_7_3_1_fu_6199_p2 = (tmp_209_fu_6185_p2 ^ 8'd27);
assign rv_7_3_2_fu_6347_p2 = (tmp_217_fu_6333_p2 ^ 8'd27);
assign rv_7_3_3_fu_6495_p2 = (tmp_225_fu_6481_p2 ^ 8'd27);
assign rv_7_3_fu_6051_p2 = (tmp_201_fu_6037_p2 ^ 8'd27);
assign rv_7_4_1_fu_7241_p2 = (tmp_241_fu_7227_p2 ^ 8'd27);
assign rv_7_4_2_fu_7389_p2 = (tmp_249_fu_7375_p2 ^ 8'd27);
assign rv_7_4_3_fu_7537_p2 = (tmp_257_fu_7523_p2 ^ 8'd27);
assign rv_7_4_fu_7093_p2 = (tmp_233_fu_7079_p2 ^ 8'd27);
assign rv_7_5_1_fu_8283_p2 = (tmp_273_fu_8269_p2 ^ 8'd27);
assign rv_7_5_2_fu_8431_p2 = (tmp_281_fu_8417_p2 ^ 8'd27);
assign rv_7_5_3_fu_8579_p2 = (tmp_289_fu_8565_p2 ^ 8'd27);
assign rv_7_5_fu_8135_p2 = (tmp_265_fu_8121_p2 ^ 8'd27);
assign rv_7_6_1_fu_9325_p2 = (tmp_305_fu_9311_p2 ^ 8'd27);
assign rv_7_6_2_fu_9473_p2 = (tmp_313_fu_9459_p2 ^ 8'd27);
assign rv_7_6_3_fu_9621_p2 = (tmp_321_fu_9607_p2 ^ 8'd27);
assign rv_7_6_fu_9177_p2 = (tmp_297_fu_9163_p2 ^ 8'd27);
assign rv_7_7_1_fu_10367_p2 = (tmp_337_fu_10353_p2 ^ 8'd27);
assign rv_7_7_2_fu_10515_p2 = (tmp_345_fu_10501_p2 ^ 8'd27);
assign rv_7_7_3_fu_10663_p2 = (tmp_353_fu_10649_p2 ^ 8'd27);
assign rv_7_7_fu_10219_p2 = (tmp_329_fu_10205_p2 ^ 8'd27);
assign rv_7_8_1_fu_11409_p2 = (tmp_369_fu_11395_p2 ^ 8'd27);
assign rv_7_8_2_fu_11557_p2 = (tmp_377_fu_11543_p2 ^ 8'd27);
assign rv_7_8_3_fu_11705_p2 = (tmp_385_fu_11691_p2 ^ 8'd27);
assign rv_7_8_fu_11261_p2 = (tmp_361_fu_11247_p2 ^ 8'd27);
assign rv_7_fu_2925_p2 = (tmp_105_fu_2911_p2 ^ 8'd27);
assign rv_8_0_1_fu_3079_p3 = ((tmp_114_fu_3065_p3[0:0] === 1'b1) ? rv_7_0_1_fu_3073_p2 : tmp_113_fu_3059_p2);
assign rv_8_0_2_fu_3227_p3 = ((tmp_122_fu_3213_p3[0:0] === 1'b1) ? rv_7_0_2_fu_3221_p2 : tmp_121_fu_3207_p2);
assign rv_8_0_3_fu_3375_p3 = ((tmp_130_fu_3361_p3[0:0] === 1'b1) ? rv_7_0_3_fu_3369_p2 : tmp_129_fu_3355_p2);
assign rv_8_1_1_fu_4121_p3 = ((tmp_146_fu_4107_p3[0:0] === 1'b1) ? rv_7_1_1_fu_4115_p2 : tmp_145_fu_4101_p2);
assign rv_8_1_2_fu_4269_p3 = ((tmp_154_fu_4255_p3[0:0] === 1'b1) ? rv_7_1_2_fu_4263_p2 : tmp_153_fu_4249_p2);
assign rv_8_1_3_fu_4417_p3 = ((tmp_162_fu_4403_p3[0:0] === 1'b1) ? rv_7_1_3_fu_4411_p2 : tmp_161_fu_4397_p2);
assign rv_8_1_fu_3973_p3 = ((tmp_138_fu_3959_p3[0:0] === 1'b1) ? rv_7_1_fu_3967_p2 : tmp_137_fu_3953_p2);
assign rv_8_2_1_fu_5163_p3 = ((tmp_178_fu_5149_p3[0:0] === 1'b1) ? rv_7_2_1_fu_5157_p2 : tmp_177_fu_5143_p2);
assign rv_8_2_2_fu_5311_p3 = ((tmp_186_fu_5297_p3[0:0] === 1'b1) ? rv_7_2_2_fu_5305_p2 : tmp_185_fu_5291_p2);
assign rv_8_2_3_fu_5459_p3 = ((tmp_194_fu_5445_p3[0:0] === 1'b1) ? rv_7_2_3_fu_5453_p2 : tmp_193_fu_5439_p2);
assign rv_8_2_fu_5015_p3 = ((tmp_170_fu_5001_p3[0:0] === 1'b1) ? rv_7_2_fu_5009_p2 : tmp_169_fu_4995_p2);
assign rv_8_3_1_fu_6205_p3 = ((tmp_210_fu_6191_p3[0:0] === 1'b1) ? rv_7_3_1_fu_6199_p2 : tmp_209_fu_6185_p2);
assign rv_8_3_2_fu_6353_p3 = ((tmp_218_fu_6339_p3[0:0] === 1'b1) ? rv_7_3_2_fu_6347_p2 : tmp_217_fu_6333_p2);
assign rv_8_3_3_fu_6501_p3 = ((tmp_226_fu_6487_p3[0:0] === 1'b1) ? rv_7_3_3_fu_6495_p2 : tmp_225_fu_6481_p2);
assign rv_8_3_fu_6057_p3 = ((tmp_202_fu_6043_p3[0:0] === 1'b1) ? rv_7_3_fu_6051_p2 : tmp_201_fu_6037_p2);
assign rv_8_4_1_fu_7247_p3 = ((tmp_242_fu_7233_p3[0:0] === 1'b1) ? rv_7_4_1_fu_7241_p2 : tmp_241_fu_7227_p2);
assign rv_8_4_2_fu_7395_p3 = ((tmp_250_fu_7381_p3[0:0] === 1'b1) ? rv_7_4_2_fu_7389_p2 : tmp_249_fu_7375_p2);
assign rv_8_4_3_fu_7543_p3 = ((tmp_258_fu_7529_p3[0:0] === 1'b1) ? rv_7_4_3_fu_7537_p2 : tmp_257_fu_7523_p2);
assign rv_8_4_fu_7099_p3 = ((tmp_234_fu_7085_p3[0:0] === 1'b1) ? rv_7_4_fu_7093_p2 : tmp_233_fu_7079_p2);
assign rv_8_5_1_fu_8289_p3 = ((tmp_274_fu_8275_p3[0:0] === 1'b1) ? rv_7_5_1_fu_8283_p2 : tmp_273_fu_8269_p2);
assign rv_8_5_2_fu_8437_p3 = ((tmp_282_fu_8423_p3[0:0] === 1'b1) ? rv_7_5_2_fu_8431_p2 : tmp_281_fu_8417_p2);
assign rv_8_5_3_fu_8585_p3 = ((tmp_290_fu_8571_p3[0:0] === 1'b1) ? rv_7_5_3_fu_8579_p2 : tmp_289_fu_8565_p2);
assign rv_8_5_fu_8141_p3 = ((tmp_266_fu_8127_p3[0:0] === 1'b1) ? rv_7_5_fu_8135_p2 : tmp_265_fu_8121_p2);
assign rv_8_6_1_fu_9331_p3 = ((tmp_306_fu_9317_p3[0:0] === 1'b1) ? rv_7_6_1_fu_9325_p2 : tmp_305_fu_9311_p2);
assign rv_8_6_2_fu_9479_p3 = ((tmp_314_fu_9465_p3[0:0] === 1'b1) ? rv_7_6_2_fu_9473_p2 : tmp_313_fu_9459_p2);
assign rv_8_6_3_fu_9627_p3 = ((tmp_322_fu_9613_p3[0:0] === 1'b1) ? rv_7_6_3_fu_9621_p2 : tmp_321_fu_9607_p2);
assign rv_8_6_fu_9183_p3 = ((tmp_298_fu_9169_p3[0:0] === 1'b1) ? rv_7_6_fu_9177_p2 : tmp_297_fu_9163_p2);
assign rv_8_7_1_fu_10373_p3 = ((tmp_338_fu_10359_p3[0:0] === 1'b1) ? rv_7_7_1_fu_10367_p2 : tmp_337_fu_10353_p2);
assign rv_8_7_2_fu_10521_p3 = ((tmp_346_fu_10507_p3[0:0] === 1'b1) ? rv_7_7_2_fu_10515_p2 : tmp_345_fu_10501_p2);
assign rv_8_7_3_fu_10669_p3 = ((tmp_354_fu_10655_p3[0:0] === 1'b1) ? rv_7_7_3_fu_10663_p2 : tmp_353_fu_10649_p2);
assign rv_8_7_fu_10225_p3 = ((tmp_330_fu_10211_p3[0:0] === 1'b1) ? rv_7_7_fu_10219_p2 : tmp_329_fu_10205_p2);
assign rv_8_8_1_fu_11415_p3 = ((tmp_370_fu_11401_p3[0:0] === 1'b1) ? rv_7_8_1_fu_11409_p2 : tmp_369_fu_11395_p2);
assign rv_8_8_2_fu_11563_p3 = ((tmp_378_fu_11549_p3[0:0] === 1'b1) ? rv_7_8_2_fu_11557_p2 : tmp_377_fu_11543_p2);
assign rv_8_8_3_fu_11711_p3 = ((tmp_386_fu_11697_p3[0:0] === 1'b1) ? rv_7_8_3_fu_11705_p2 : tmp_385_fu_11691_p2);
assign rv_8_8_fu_11267_p3 = ((tmp_362_fu_11253_p3[0:0] === 1'b1) ? rv_7_8_fu_11261_p2 : tmp_361_fu_11247_p2);
assign rv_8_fu_2931_p3 = ((tmp_106_fu_2917_p3[0:0] === 1'b1) ? rv_7_fu_2925_p2 : tmp_105_fu_2911_p2);
assign rv_s_fu_2959_p2 = (tmp_107_fu_2945_p2 ^ 8'd27);
assign sboxes_address0 = tmp_35_fu_2725_p1;
assign sboxes_address1 = tmp_35_0_1_fu_2730_p1;
assign sboxes_address10 = tmp_35_0_s_fu_2775_p1;
assign sboxes_address100 = tmp_35_5_fu_7935_p1;
assign sboxes_address101 = tmp_35_5_1_fu_7940_p1;
assign sboxes_address102 = tmp_35_5_2_fu_7945_p1;
assign sboxes_address103 = tmp_35_5_3_fu_7950_p1;
assign sboxes_address104 = tmp_35_5_4_fu_7955_p1;
assign sboxes_address105 = tmp_35_5_5_fu_7960_p1;
assign sboxes_address106 = tmp_35_5_6_fu_7965_p1;
assign sboxes_address107 = tmp_35_5_7_fu_7970_p1;
assign sboxes_address108 = tmp_35_5_8_fu_7975_p1;
assign sboxes_address109 = tmp_35_5_9_fu_7980_p1;
assign sboxes_address11 = tmp_35_0_10_fu_2780_p1;
assign sboxes_address110 = tmp_35_5_s_fu_7985_p1;
assign sboxes_address111 = tmp_35_5_10_fu_7990_p1;
assign sboxes_address112 = tmp_35_5_11_fu_7995_p1;
assign sboxes_address113 = tmp_35_5_12_fu_8000_p1;
assign sboxes_address114 = tmp_35_5_13_fu_8005_p1;
assign sboxes_address115 = tmp_35_5_14_fu_8010_p1;
assign sboxes_address116 = tmp_60_5_fu_8015_p1;
assign sboxes_address117 = tmp_61_5_fu_8020_p1;
assign sboxes_address118 = tmp_62_5_fu_8025_p1;
assign sboxes_address119 = tmp_63_5_fu_8030_p1;
assign sboxes_address12 = tmp_35_0_11_fu_2785_p1;
assign sboxes_address120 = tmp_35_6_fu_8977_p1;
assign sboxes_address121 = tmp_35_6_1_fu_8982_p1;
assign sboxes_address122 = tmp_35_6_2_fu_8987_p1;
assign sboxes_address123 = tmp_35_6_3_fu_8992_p1;
assign sboxes_address124 = tmp_35_6_4_fu_8997_p1;
assign sboxes_address125 = tmp_35_6_5_fu_9002_p1;
assign sboxes_address126 = tmp_35_6_6_fu_9007_p1;
assign sboxes_address127 = tmp_35_6_7_fu_9012_p1;
assign sboxes_address128 = tmp_35_6_8_fu_9017_p1;
assign sboxes_address129 = tmp_35_6_9_fu_9022_p1;
assign sboxes_address13 = tmp_35_0_12_fu_2790_p1;
assign sboxes_address130 = tmp_35_6_s_fu_9027_p1;
assign sboxes_address131 = tmp_35_6_10_fu_9032_p1;
assign sboxes_address132 = tmp_35_6_11_fu_9037_p1;
assign sboxes_address133 = tmp_35_6_12_fu_9042_p1;
assign sboxes_address134 = tmp_35_6_13_fu_9047_p1;
assign sboxes_address135 = tmp_35_6_14_fu_9052_p1;
assign sboxes_address136 = tmp_60_6_fu_9057_p1;
assign sboxes_address137 = tmp_61_6_fu_9062_p1;
assign sboxes_address138 = tmp_62_6_fu_9067_p1;
assign sboxes_address139 = tmp_63_6_fu_9072_p1;
assign sboxes_address14 = tmp_35_0_13_fu_2795_p1;
assign sboxes_address140 = tmp_35_7_fu_10019_p1;
assign sboxes_address141 = tmp_35_7_1_fu_10024_p1;
assign sboxes_address142 = tmp_35_7_2_fu_10029_p1;
assign sboxes_address143 = tmp_35_7_3_fu_10034_p1;
assign sboxes_address144 = tmp_35_7_4_fu_10039_p1;
assign sboxes_address145 = tmp_35_7_5_fu_10044_p1;
assign sboxes_address146 = tmp_35_7_6_fu_10049_p1;
assign sboxes_address147 = tmp_35_7_7_fu_10054_p1;
assign sboxes_address148 = tmp_35_7_8_fu_10059_p1;
assign sboxes_address149 = tmp_35_7_9_fu_10064_p1;
assign sboxes_address15 = tmp_35_0_14_fu_2800_p1;
assign sboxes_address150 = tmp_35_7_s_fu_10069_p1;
assign sboxes_address151 = tmp_35_7_10_fu_10074_p1;
assign sboxes_address152 = tmp_35_7_11_fu_10079_p1;
assign sboxes_address153 = tmp_35_7_12_fu_10084_p1;
assign sboxes_address154 = tmp_35_7_13_fu_10089_p1;
assign sboxes_address155 = tmp_35_7_14_fu_10094_p1;
assign sboxes_address156 = tmp_60_7_fu_10099_p1;
assign sboxes_address157 = tmp_61_7_fu_10104_p1;
assign sboxes_address158 = tmp_62_7_fu_10109_p1;
assign sboxes_address159 = tmp_63_7_fu_10114_p1;
assign sboxes_address16 = tmp_60_fu_2805_p1;
assign sboxes_address160 = tmp_35_8_fu_11061_p1;
assign sboxes_address161 = tmp_35_8_1_fu_11066_p1;
assign sboxes_address162 = tmp_35_8_2_fu_11071_p1;
assign sboxes_address163 = tmp_35_8_3_fu_11076_p1;
assign sboxes_address164 = tmp_35_8_4_fu_11081_p1;
assign sboxes_address165 = tmp_35_8_5_fu_11086_p1;
assign sboxes_address166 = tmp_35_8_6_fu_11091_p1;
assign sboxes_address167 = tmp_35_8_7_fu_11096_p1;
assign sboxes_address168 = tmp_35_8_8_fu_11101_p1;
assign sboxes_address169 = tmp_35_8_9_fu_11106_p1;
assign sboxes_address17 = tmp_61_fu_2810_p1;
assign sboxes_address170 = tmp_35_8_s_fu_11111_p1;
assign sboxes_address171 = tmp_35_8_10_fu_11116_p1;
assign sboxes_address172 = tmp_35_8_11_fu_11121_p1;
assign sboxes_address173 = tmp_35_8_12_fu_11126_p1;
assign sboxes_address174 = tmp_35_8_13_fu_11131_p1;
assign sboxes_address175 = tmp_35_8_14_fu_11136_p1;
assign sboxes_address176 = tmp_60_8_fu_11141_p1;
assign sboxes_address177 = tmp_61_8_fu_11146_p1;
assign sboxes_address178 = tmp_62_8_fu_11151_p1;
assign sboxes_address179 = tmp_63_8_fu_11156_p1;
assign sboxes_address18 = tmp_62_fu_2815_p1;
assign sboxes_address180 = tmp_33_fu_12103_p1;
assign sboxes_address181 = tmp_33_1_fu_12108_p1;
assign sboxes_address182 = tmp_33_2_fu_12113_p1;
assign sboxes_address183 = tmp_33_3_fu_12118_p1;
assign sboxes_address184 = tmp_33_4_fu_12123_p1;
assign sboxes_address185 = tmp_33_5_fu_12128_p1;
assign sboxes_address186 = tmp_33_6_fu_12133_p1;
assign sboxes_address187 = tmp_33_7_fu_12138_p1;
assign sboxes_address188 = tmp_33_8_fu_12143_p1;
assign sboxes_address189 = tmp_33_9_fu_12148_p1;
assign sboxes_address19 = tmp_63_fu_2820_p1;
assign sboxes_address190 = tmp_33_s_fu_12153_p1;
assign sboxes_address191 = tmp_33_10_fu_12158_p1;
assign sboxes_address192 = tmp_33_11_fu_12163_p1;
assign sboxes_address193 = tmp_33_12_fu_12168_p1;
assign sboxes_address194 = tmp_33_13_fu_12173_p1;
assign sboxes_address195 = tmp_33_14_fu_12178_p1;
assign sboxes_address196 = tmp_s_fu_12183_p1;
assign sboxes_address197 = tmp_1_fu_12188_p1;
assign sboxes_address198 = tmp_2_fu_12193_p1;
assign sboxes_address199 = tmp_3_fu_12198_p1;
assign sboxes_address2 = tmp_35_0_2_fu_2735_p1;
assign sboxes_address20 = tmp_35_1_fu_3767_p1;
assign sboxes_address21 = tmp_35_1_1_fu_3772_p1;
assign sboxes_address22 = tmp_35_1_2_fu_3777_p1;
assign sboxes_address23 = tmp_35_1_3_fu_3782_p1;
assign sboxes_address24 = tmp_35_1_4_fu_3787_p1;
assign sboxes_address25 = tmp_35_1_5_fu_3792_p1;
assign sboxes_address26 = tmp_35_1_6_fu_3797_p1;
assign sboxes_address27 = tmp_35_1_7_fu_3802_p1;
assign sboxes_address28 = tmp_35_1_8_fu_3807_p1;
assign sboxes_address29 = tmp_35_1_9_fu_3812_p1;
assign sboxes_address3 = tmp_35_0_3_fu_2740_p1;
assign sboxes_address30 = tmp_35_1_s_fu_3817_p1;
assign sboxes_address31 = tmp_35_1_10_fu_3822_p1;
assign sboxes_address32 = tmp_35_1_11_fu_3827_p1;
assign sboxes_address33 = tmp_35_1_12_fu_3832_p1;
assign sboxes_address34 = tmp_35_1_13_fu_3837_p1;
assign sboxes_address35 = tmp_35_1_14_fu_3842_p1;
assign sboxes_address36 = tmp_60_1_fu_3847_p1;
assign sboxes_address37 = tmp_61_1_fu_3852_p1;
assign sboxes_address38 = tmp_62_1_fu_3857_p1;
assign sboxes_address39 = tmp_63_1_fu_3862_p1;
assign sboxes_address4 = tmp_35_0_4_fu_2745_p1;
assign sboxes_address40 = tmp_35_2_fu_4809_p1;
assign sboxes_address41 = tmp_35_2_1_fu_4814_p1;
assign sboxes_address42 = tmp_35_2_2_fu_4819_p1;
assign sboxes_address43 = tmp_35_2_3_fu_4824_p1;
assign sboxes_address44 = tmp_35_2_4_fu_4829_p1;
assign sboxes_address45 = tmp_35_2_5_fu_4834_p1;
assign sboxes_address46 = tmp_35_2_6_fu_4839_p1;
assign sboxes_address47 = tmp_35_2_7_fu_4844_p1;
assign sboxes_address48 = tmp_35_2_8_fu_4849_p1;
assign sboxes_address49 = tmp_35_2_9_fu_4854_p1;
assign sboxes_address5 = tmp_35_0_5_fu_2750_p1;
assign sboxes_address50 = tmp_35_2_s_fu_4859_p1;
assign sboxes_address51 = tmp_35_2_10_fu_4864_p1;
assign sboxes_address52 = tmp_35_2_11_fu_4869_p1;
assign sboxes_address53 = tmp_35_2_12_fu_4874_p1;
assign sboxes_address54 = tmp_35_2_13_fu_4879_p1;
assign sboxes_address55 = tmp_35_2_14_fu_4884_p1;
assign sboxes_address56 = tmp_60_2_fu_4889_p1;
assign sboxes_address57 = tmp_61_2_fu_4894_p1;
assign sboxes_address58 = tmp_62_2_fu_4899_p1;
assign sboxes_address59 = tmp_63_2_fu_4904_p1;
assign sboxes_address6 = tmp_35_0_6_fu_2755_p1;
assign sboxes_address60 = tmp_35_3_fu_5851_p1;
assign sboxes_address61 = tmp_35_3_1_fu_5856_p1;
assign sboxes_address62 = tmp_35_3_2_fu_5861_p1;
assign sboxes_address63 = tmp_35_3_3_fu_5866_p1;
assign sboxes_address64 = tmp_35_3_4_fu_5871_p1;
assign sboxes_address65 = tmp_35_3_5_fu_5876_p1;
assign sboxes_address66 = tmp_35_3_6_fu_5881_p1;
assign sboxes_address67 = tmp_35_3_7_fu_5886_p1;
assign sboxes_address68 = tmp_35_3_8_fu_5891_p1;
assign sboxes_address69 = tmp_35_3_9_fu_5896_p1;
assign sboxes_address7 = tmp_35_0_7_fu_2760_p1;
assign sboxes_address70 = tmp_35_3_s_fu_5901_p1;
assign sboxes_address71 = tmp_35_3_10_fu_5906_p1;
assign sboxes_address72 = tmp_35_3_11_fu_5911_p1;
assign sboxes_address73 = tmp_35_3_12_fu_5916_p1;
assign sboxes_address74 = tmp_35_3_13_fu_5921_p1;
assign sboxes_address75 = tmp_35_3_14_fu_5926_p1;
assign sboxes_address76 = tmp_60_3_fu_5931_p1;
assign sboxes_address77 = tmp_61_3_fu_5936_p1;
assign sboxes_address78 = tmp_62_3_fu_5941_p1;
assign sboxes_address79 = tmp_63_3_fu_5946_p1;
assign sboxes_address8 = tmp_35_0_8_fu_2765_p1;
assign sboxes_address80 = tmp_35_4_fu_6893_p1;
assign sboxes_address81 = tmp_35_4_1_fu_6898_p1;
assign sboxes_address82 = tmp_35_4_2_fu_6903_p1;
assign sboxes_address83 = tmp_35_4_3_fu_6908_p1;
assign sboxes_address84 = tmp_35_4_4_fu_6913_p1;
assign sboxes_address85 = tmp_35_4_5_fu_6918_p1;
assign sboxes_address86 = tmp_35_4_6_fu_6923_p1;
assign sboxes_address87 = tmp_35_4_7_fu_6928_p1;
assign sboxes_address88 = tmp_35_4_8_fu_6933_p1;
assign sboxes_address89 = tmp_35_4_9_fu_6938_p1;
assign sboxes_address9 = tmp_35_0_9_fu_2770_p1;
assign sboxes_address90 = tmp_35_4_s_fu_6943_p1;
assign sboxes_address91 = tmp_35_4_10_fu_6948_p1;
assign sboxes_address92 = tmp_35_4_11_fu_6953_p1;
assign sboxes_address93 = tmp_35_4_12_fu_6958_p1;
assign sboxes_address94 = tmp_35_4_13_fu_6963_p1;
assign sboxes_address95 = tmp_35_4_14_fu_6968_p1;
assign sboxes_address96 = tmp_60_4_fu_6973_p1;
assign sboxes_address97 = tmp_61_4_fu_6978_p1;
assign sboxes_address98 = tmp_62_4_fu_6983_p1;
assign sboxes_address99 = tmp_63_4_fu_6988_p1;
assign tmp100_fu_6663_p2 = (tmp_47_3_fu_5957_p2 ^ tmp_68_3_fu_6564_p2);
assign tmp101_fu_6675_p2 = (sboxes_q64 ^ rv_2_3_1_fu_6137_p3);
assign tmp102_fu_6681_p2 = (e_3_1_fu_6111_p2 ^ tmp_69_3_fu_6569_p2);
assign tmp103_fu_6693_p2 = (sboxes_q69 ^ e_3_1_fu_6111_p2);
assign tmp104_fu_6699_p2 = (rv_5_3_1_fu_6171_p3 ^ tmp_70_3_fu_6574_p2);
assign tmp105_fu_6711_p2 = (sboxes_q63 ^ x_assign_375_1_fu_6099_p2);
assign tmp106_fu_6717_p2 = (rv_8_3_1_fu_6205_p3 ^ tmp_71_3_fu_6579_p2);
assign tmp107_fu_6729_p2 = (tmp_47_3_1_fu_6105_p2 ^ tmp_72_3_fu_6584_p2);
assign tmp108_fu_6741_p2 = (sboxes_q68 ^ rv_2_3_2_fu_6285_p3);
assign tmp109_fu_6752_p2 = (tmp110_fu_6747_p2 ^ e_3_2_fu_6259_p2);
assign tmp10_fu_3587_p2 = (sboxes_q9 ^ e_0_1_fu_2985_p2);
assign tmp110_fu_6747_p2 = (tmp_69_3_fu_6569_p2 ^ tmp_73_2_reg_12941);
assign tmp111_fu_6764_p2 = (sboxes_q73 ^ e_3_2_fu_6259_p2);
assign tmp112_fu_6775_p2 = (tmp113_fu_6770_p2 ^ rv_5_3_2_fu_6319_p3);
assign tmp113_fu_6770_p2 = (tmp_70_3_fu_6574_p2 ^ tmp_74_2_reg_12947);
assign tmp114_fu_6787_p2 = (sboxes_q67 ^ x_assign_375_2_fu_6247_p2);
assign tmp115_fu_6798_p2 = (tmp116_fu_6793_p2 ^ rv_8_3_2_fu_6353_p3);
assign tmp116_fu_6793_p2 = (tmp_71_3_fu_6579_p2 ^ tmp_75_2_reg_12953);
assign tmp117_fu_6810_p2 = (rv_11_3_2_fu_6387_p3 ^ tmp_47_3_2_fu_6253_p2);
assign tmp118_fu_6816_p2 = (tmp_72_3_fu_6584_p2 ^ tmp_76_2_reg_12959);
assign tmp119_fu_6827_p2 = (sboxes_q72 ^ rv_2_3_3_fu_6433_p3);
assign tmp11_fu_3593_p2 = (rv_5_0_1_fu_3045_p3 ^ tmp_70_fu_3448_p2);
assign tmp120_fu_6833_p2 = (e_3_3_fu_6407_p2 ^ tmp_77_3_fu_6589_p2);
assign tmp121_fu_6845_p2 = (sboxes_q61 ^ e_3_3_fu_6407_p2);
assign tmp122_fu_6851_p2 = (rv_5_3_3_fu_6467_p3 ^ tmp_78_3_fu_6594_p2);
assign tmp123_fu_6863_p2 = (sboxes_q71 ^ x_assign_375_3_fu_6395_p2);
assign tmp124_fu_6869_p2 = (rv_8_3_3_fu_6501_p3 ^ tmp_79_3_fu_6599_p2);
assign tmp125_fu_6881_p2 = (tmp_47_3_3_fu_6401_p2 ^ tmp_80_3_fu_6604_p2);
assign tmp126_fu_7585_p2 = (tmp_65_3_reg_13065 ^ 8'd16);
assign tmp127_fu_7651_p2 = (sboxes_q80 ^ rv_2_4_fu_7031_p3);
assign tmp128_fu_7657_p2 = (e_4_fu_7005_p2 ^ tmp_65_4_fu_7590_p2);
assign tmp129_fu_7669_p2 = (sboxes_q85 ^ e_4_fu_7005_p2);
assign tmp12_fu_3605_p2 = (sboxes_q3 ^ x_assign_0_1_fu_2973_p2);
assign tmp130_fu_7675_p2 = (rv_5_4_fu_7065_p3 ^ tmp_66_4_fu_7596_p2);
assign tmp131_fu_7687_p2 = (sboxes_q95 ^ x_assign_4_fu_6993_p2);
assign tmp132_fu_7693_p2 = (rv_8_4_fu_7099_p3 ^ tmp_67_4_fu_7601_p2);
assign tmp133_fu_7705_p2 = (tmp_47_4_fu_6999_p2 ^ tmp_68_4_fu_7606_p2);
assign tmp134_fu_7717_p2 = (sboxes_q84 ^ rv_2_4_1_fu_7179_p3);
assign tmp135_fu_7728_p2 = (tmp136_fu_7723_p2 ^ e_4_1_fu_7153_p2);
assign tmp136_fu_7723_p2 = (tmp_65_4_fu_7590_p2 ^ tmp_69_3_reg_13085);
assign tmp137_fu_7740_p2 = (sboxes_q89 ^ e_4_1_fu_7153_p2);
assign tmp138_fu_7751_p2 = (tmp139_fu_7746_p2 ^ rv_5_4_1_fu_7213_p3);
assign tmp139_fu_7746_p2 = (tmp_66_4_fu_7596_p2 ^ tmp_70_3_reg_13091);
assign tmp13_fu_3611_p2 = (rv_8_0_1_fu_3079_p3 ^ tmp_71_fu_3453_p2);
assign tmp140_fu_7763_p2 = (sboxes_q83 ^ x_assign_4_1_fu_7141_p2);
assign tmp141_fu_7774_p2 = (tmp142_fu_7769_p2 ^ rv_8_4_1_fu_7247_p3);
assign tmp142_fu_7769_p2 = (tmp_67_4_fu_7601_p2 ^ tmp_71_3_reg_13097);
assign tmp143_fu_7786_p2 = (rv_11_4_1_fu_7281_p3 ^ tmp_47_4_1_fu_7147_p2);
assign tmp144_fu_7792_p2 = (tmp_68_4_fu_7606_p2 ^ tmp_72_3_reg_13103);
assign tmp145_fu_7803_p2 = (sboxes_q88 ^ rv_2_4_2_fu_7327_p3);
assign tmp146_fu_7809_p2 = (e_4_2_fu_7301_p2 ^ tmp_73_4_fu_7611_p2);
assign tmp147_fu_7821_p2 = (sboxes_q93 ^ e_4_2_fu_7301_p2);
assign tmp148_fu_7827_p2 = (rv_5_4_2_fu_7361_p3 ^ tmp_74_4_fu_7616_p2);
assign tmp149_fu_7839_p2 = (sboxes_q87 ^ x_assign_4_2_fu_7289_p2);
assign tmp14_fu_3623_p2 = (tmp_47_0_1_fu_2979_p2 ^ tmp_72_fu_3458_p2);
assign tmp150_fu_7845_p2 = (rv_8_4_2_fu_7395_p3 ^ tmp_75_4_fu_7621_p2);
assign tmp151_fu_7857_p2 = (tmp_47_4_2_fu_7295_p2 ^ tmp_76_4_fu_7626_p2);
assign tmp152_fu_7869_p2 = (sboxes_q92 ^ rv_2_4_3_fu_7475_p3);
assign tmp153_fu_7875_p2 = (e_4_3_fu_7449_p2 ^ tmp_77_4_fu_7631_p2);
assign tmp154_fu_7887_p2 = (sboxes_q81 ^ e_4_3_fu_7449_p2);
assign tmp155_fu_7893_p2 = (rv_5_4_3_fu_7509_p3 ^ tmp_78_4_fu_7636_p2);
assign tmp156_fu_7905_p2 = (sboxes_q91 ^ x_assign_4_3_fu_7437_p2);
assign tmp157_fu_7911_p2 = (rv_8_4_3_fu_7543_p3 ^ tmp_79_4_fu_7641_p2);
assign tmp158_fu_7923_p2 = (tmp_47_4_3_fu_7443_p2 ^ tmp_80_4_fu_7646_p2);
assign tmp159_fu_8693_p2 = (sboxes_q100 ^ rv_2_5_fu_8073_p3);
assign tmp15_fu_3635_p2 = (sboxes_q8 ^ rv_2_0_2_fu_3159_p3);
assign tmp160_fu_8699_p2 = (e_5_fu_8047_p2 ^ tmp_65_5_fu_8633_p2);
assign tmp161_fu_8711_p2 = (sboxes_q105 ^ e_5_fu_8047_p2);
assign tmp162_fu_8717_p2 = (rv_5_5_fu_8107_p3 ^ tmp_66_5_fu_8638_p2);
assign tmp163_fu_8729_p2 = (sboxes_q115 ^ x_assign_5_fu_8035_p2);
assign tmp164_fu_8735_p2 = (rv_8_5_fu_8141_p3 ^ tmp_67_5_fu_8643_p2);
assign tmp165_fu_8747_p2 = (tmp_47_5_fu_8041_p2 ^ tmp_68_5_fu_8648_p2);
assign tmp166_fu_8759_p2 = (sboxes_q104 ^ rv_2_5_1_fu_8221_p3);
assign tmp167_fu_8765_p2 = (e_5_1_fu_8195_p2 ^ tmp_69_5_fu_8653_p2);
assign tmp168_fu_8777_p2 = (sboxes_q109 ^ e_5_1_fu_8195_p2);
assign tmp169_fu_8783_p2 = (rv_5_5_1_fu_8255_p3 ^ tmp_70_5_fu_8658_p2);
assign tmp16_fu_3641_p2 = (e_0_2_fu_3133_p2 ^ tmp_73_fu_3463_p2);
assign tmp170_fu_8795_p2 = (sboxes_q103 ^ x_assign_5_1_fu_8183_p2);
assign tmp171_fu_8801_p2 = (rv_8_5_1_fu_8289_p3 ^ tmp_71_5_fu_8663_p2);
assign tmp172_fu_8813_p2 = (tmp_47_5_1_fu_8189_p2 ^ tmp_72_5_fu_8668_p2);
assign tmp173_fu_8825_p2 = (sboxes_q108 ^ rv_2_5_2_fu_8369_p3);
assign tmp174_fu_8836_p2 = (tmp175_fu_8831_p2 ^ e_5_2_fu_8343_p2);
assign tmp175_fu_8831_p2 = (tmp_69_5_fu_8653_p2 ^ tmp_73_4_reg_13257);
assign tmp176_fu_8848_p2 = (sboxes_q113 ^ e_5_2_fu_8343_p2);
assign tmp177_fu_8859_p2 = (tmp178_fu_8854_p2 ^ rv_5_5_2_fu_8403_p3);
assign tmp178_fu_8854_p2 = (tmp_70_5_fu_8658_p2 ^ tmp_74_4_reg_13263);
assign tmp179_fu_8871_p2 = (sboxes_q107 ^ x_assign_5_2_fu_8331_p2);
assign tmp17_fu_3653_p2 = (sboxes_q13 ^ e_0_2_fu_3133_p2);
assign tmp180_fu_8882_p2 = (tmp181_fu_8877_p2 ^ rv_8_5_2_fu_8437_p3);
assign tmp181_fu_8877_p2 = (tmp_71_5_fu_8663_p2 ^ tmp_75_4_reg_13269);
assign tmp182_fu_8894_p2 = (rv_11_5_2_fu_8471_p3 ^ tmp_47_5_2_fu_8337_p2);
assign tmp183_fu_8900_p2 = (tmp_72_5_fu_8668_p2 ^ tmp_76_4_reg_13275);
assign tmp184_fu_8911_p2 = (sboxes_q112 ^ rv_2_5_3_fu_8517_p3);
assign tmp185_fu_8917_p2 = (e_5_3_fu_8491_p2 ^ tmp_77_5_fu_8673_p2);
assign tmp186_fu_8929_p2 = (sboxes_q101 ^ e_5_3_fu_8491_p2);
assign tmp187_fu_8935_p2 = (rv_5_5_3_fu_8551_p3 ^ tmp_78_5_fu_8678_p2);
assign tmp188_fu_8947_p2 = (sboxes_q111 ^ x_assign_5_3_fu_8479_p2);
assign tmp189_fu_8953_p2 = (rv_8_5_3_fu_8585_p3 ^ tmp_79_5_fu_8683_p2);
assign tmp18_fu_3659_p2 = (rv_5_0_2_fu_3193_p3 ^ tmp_74_fu_3468_p2);
assign tmp190_fu_8965_p2 = (tmp_47_5_3_fu_8485_p2 ^ tmp_80_5_fu_8688_p2);
assign tmp191_fu_9669_p2 = (tmp_65_5_reg_13381 ^ 8'd64);
assign tmp192_fu_9735_p2 = (sboxes_q120 ^ rv_2_6_fu_9115_p3);
assign tmp193_fu_9741_p2 = (e_6_fu_9089_p2 ^ tmp_65_6_fu_9674_p2);
assign tmp194_fu_9753_p2 = (sboxes_q125 ^ e_6_fu_9089_p2);
assign tmp195_fu_9759_p2 = (rv_5_6_fu_9149_p3 ^ tmp_66_6_fu_9680_p2);
assign tmp196_fu_9771_p2 = (sboxes_q135 ^ x_assign_6_fu_9077_p2);
assign tmp197_fu_9777_p2 = (rv_8_6_fu_9183_p3 ^ tmp_67_6_fu_9685_p2);
assign tmp198_fu_9789_p2 = (tmp_47_6_fu_9083_p2 ^ tmp_68_6_fu_9690_p2);
assign tmp199_fu_9801_p2 = (sboxes_q124 ^ rv_2_6_1_fu_9263_p3);
assign tmp19_fu_3671_p2 = (sboxes_q7 ^ x_assign_0_2_fu_3121_p2);
assign tmp1_fu_3503_p2 = (sboxes_q0 ^ rv_2_fu_2863_p3);
assign tmp200_fu_9812_p2 = (tmp201_fu_9807_p2 ^ e_6_1_fu_9237_p2);
assign tmp201_fu_9807_p2 = (tmp_65_6_fu_9674_p2 ^ tmp_69_5_reg_13401);
assign tmp202_fu_9824_p2 = (sboxes_q129 ^ e_6_1_fu_9237_p2);
assign tmp203_fu_9835_p2 = (tmp204_fu_9830_p2 ^ rv_5_6_1_fu_9297_p3);
assign tmp204_fu_9830_p2 = (tmp_66_6_fu_9680_p2 ^ tmp_70_5_reg_13407);
assign tmp205_fu_9847_p2 = (sboxes_q123 ^ x_assign_6_1_fu_9225_p2);
assign tmp206_fu_9858_p2 = (tmp207_fu_9853_p2 ^ rv_8_6_1_fu_9331_p3);
assign tmp207_fu_9853_p2 = (tmp_67_6_fu_9685_p2 ^ tmp_71_5_reg_13413);
assign tmp208_fu_9870_p2 = (rv_11_6_1_fu_9365_p3 ^ tmp_47_6_1_fu_9231_p2);
assign tmp209_fu_9876_p2 = (tmp_68_6_fu_9690_p2 ^ tmp_72_5_reg_13419);
assign tmp20_fu_3677_p2 = (rv_8_0_2_fu_3227_p3 ^ tmp_75_fu_3473_p2);
assign tmp210_fu_9887_p2 = (sboxes_q128 ^ rv_2_6_2_fu_9411_p3);
assign tmp211_fu_9893_p2 = (e_6_2_fu_9385_p2 ^ tmp_73_6_fu_9695_p2);
assign tmp212_fu_9905_p2 = (sboxes_q133 ^ e_6_2_fu_9385_p2);
assign tmp213_fu_9911_p2 = (rv_5_6_2_fu_9445_p3 ^ tmp_74_6_fu_9700_p2);
assign tmp214_fu_9923_p2 = (sboxes_q127 ^ x_assign_6_2_fu_9373_p2);
assign tmp215_fu_9929_p2 = (rv_8_6_2_fu_9479_p3 ^ tmp_75_6_fu_9705_p2);
assign tmp216_fu_9941_p2 = (tmp_47_6_2_fu_9379_p2 ^ tmp_76_6_fu_9710_p2);
assign tmp217_fu_9953_p2 = (sboxes_q132 ^ rv_2_6_3_fu_9559_p3);
assign tmp218_fu_9959_p2 = (e_6_3_fu_9533_p2 ^ tmp_77_6_fu_9715_p2);
assign tmp219_fu_9971_p2 = (sboxes_q121 ^ e_6_3_fu_9533_p2);
assign tmp21_fu_3689_p2 = (tmp_47_0_2_fu_3127_p2 ^ tmp_76_fu_3478_p2);
assign tmp220_fu_9977_p2 = (rv_5_6_3_fu_9593_p3 ^ tmp_78_6_fu_9720_p2);
assign tmp221_fu_9989_p2 = (sboxes_q131 ^ x_assign_6_3_fu_9521_p2);
assign tmp222_fu_9995_p2 = (rv_8_6_3_fu_9627_p3 ^ tmp_79_6_fu_9725_p2);
assign tmp223_fu_10007_p2 = (tmp_47_6_3_fu_9527_p2 ^ tmp_80_6_fu_9730_p2);
assign tmp224_fu_10777_p2 = (sboxes_q140 ^ rv_2_7_fu_10157_p3);
assign tmp225_fu_10783_p2 = (e_7_fu_10131_p2 ^ tmp_65_7_fu_10717_p2);
assign tmp226_fu_10795_p2 = (sboxes_q145 ^ e_7_fu_10131_p2);
assign tmp227_fu_10801_p2 = (rv_5_7_fu_10191_p3 ^ tmp_66_7_fu_10722_p2);
assign tmp228_fu_10813_p2 = (sboxes_q155 ^ x_assign_7_fu_10119_p2);
assign tmp229_fu_10819_p2 = (rv_8_7_fu_10225_p3 ^ tmp_67_7_fu_10727_p2);
assign tmp22_fu_3701_p2 = (sboxes_q12 ^ rv_2_0_3_fu_3307_p3);
assign tmp230_fu_10831_p2 = (tmp_47_7_fu_10125_p2 ^ tmp_68_7_fu_10732_p2);
assign tmp231_fu_10843_p2 = (sboxes_q144 ^ rv_2_7_1_fu_10305_p3);
assign tmp232_fu_10849_p2 = (e_7_1_fu_10279_p2 ^ tmp_69_7_fu_10737_p2);
assign tmp233_fu_10861_p2 = (sboxes_q149 ^ e_7_1_fu_10279_p2);
assign tmp234_fu_10867_p2 = (rv_5_7_1_fu_10339_p3 ^ tmp_70_7_fu_10742_p2);
assign tmp235_fu_10879_p2 = (sboxes_q143 ^ x_assign_7_1_fu_10267_p2);
assign tmp236_fu_10885_p2 = (rv_8_7_1_fu_10373_p3 ^ tmp_71_7_fu_10747_p2);
assign tmp237_fu_10897_p2 = (tmp_47_7_1_fu_10273_p2 ^ tmp_72_7_fu_10752_p2);
assign tmp238_fu_10909_p2 = (sboxes_q148 ^ rv_2_7_2_fu_10453_p3);
assign tmp239_fu_10920_p2 = (tmp240_fu_10915_p2 ^ e_7_2_fu_10427_p2);
assign tmp23_fu_3707_p2 = (e_0_3_fu_3281_p2 ^ tmp_77_fu_3483_p2);
assign tmp240_fu_10915_p2 = (tmp_69_7_fu_10737_p2 ^ tmp_73_6_reg_13565);
assign tmp241_fu_10932_p2 = (sboxes_q153 ^ e_7_2_fu_10427_p2);
assign tmp242_fu_10943_p2 = (tmp243_fu_10938_p2 ^ rv_5_7_2_fu_10487_p3);
assign tmp243_fu_10938_p2 = (tmp_70_7_fu_10742_p2 ^ tmp_74_6_reg_13571);
assign tmp244_fu_10955_p2 = (sboxes_q147 ^ x_assign_7_2_fu_10415_p2);
assign tmp245_fu_10966_p2 = (tmp246_fu_10961_p2 ^ rv_8_7_2_fu_10521_p3);
assign tmp246_fu_10961_p2 = (tmp_71_7_fu_10747_p2 ^ tmp_75_6_reg_13577);
assign tmp247_fu_10978_p2 = (rv_11_7_2_fu_10555_p3 ^ tmp_47_7_2_fu_10421_p2);
assign tmp248_fu_10984_p2 = (tmp_72_7_fu_10752_p2 ^ tmp_76_6_reg_13583);
assign tmp249_fu_10995_p2 = (sboxes_q152 ^ rv_2_7_3_fu_10601_p3);
assign tmp24_fu_3719_p2 = (sboxes_q1 ^ e_0_3_fu_3281_p2);
assign tmp250_fu_11001_p2 = (e_7_3_fu_10575_p2 ^ tmp_77_7_fu_10757_p2);
assign tmp251_fu_11013_p2 = (sboxes_q141 ^ e_7_3_fu_10575_p2);
assign tmp252_fu_11019_p2 = (rv_5_7_3_fu_10635_p3 ^ tmp_78_7_fu_10762_p2);
assign tmp253_fu_11031_p2 = (sboxes_q151 ^ x_assign_7_3_fu_10563_p2);
assign tmp254_fu_11037_p2 = (rv_8_7_3_fu_10669_p3 ^ tmp_79_7_fu_10767_p2);
assign tmp255_fu_11049_p2 = (tmp_47_7_3_fu_10569_p2 ^ tmp_80_7_fu_10772_p2);
assign tmp256_fu_11753_p2 = (tmp_65_7_reg_13689 ^ 8'd27);
assign tmp257_fu_11819_p2 = (sboxes_q160 ^ rv_2_8_fu_11199_p3);
assign tmp258_fu_11825_p2 = (e_8_fu_11173_p2 ^ tmp_65_8_fu_11758_p2);
assign tmp259_fu_11837_p2 = (sboxes_q165 ^ e_8_fu_11173_p2);
assign tmp25_fu_3725_p2 = (rv_5_0_3_fu_3341_p3 ^ tmp_78_fu_3488_p2);
assign tmp260_fu_11843_p2 = (rv_5_8_fu_11233_p3 ^ tmp_66_8_fu_11764_p2);
assign tmp261_fu_11855_p2 = (sboxes_q175 ^ x_assign_8_fu_11161_p2);
assign tmp262_fu_11861_p2 = (rv_8_8_fu_11267_p3 ^ tmp_67_8_fu_11769_p2);
assign tmp263_fu_11873_p2 = (tmp_47_8_fu_11167_p2 ^ tmp_68_8_fu_11774_p2);
assign tmp264_fu_11885_p2 = (sboxes_q164 ^ rv_2_8_1_fu_11347_p3);
assign tmp265_fu_11896_p2 = (tmp266_fu_11891_p2 ^ e_8_1_fu_11321_p2);
assign tmp266_fu_11891_p2 = (tmp_65_8_fu_11758_p2 ^ tmp_69_7_reg_13709);
assign tmp267_fu_11908_p2 = (sboxes_q169 ^ e_8_1_fu_11321_p2);
assign tmp268_fu_11919_p2 = (tmp269_fu_11914_p2 ^ rv_5_8_1_fu_11381_p3);
assign tmp269_fu_11914_p2 = (tmp_66_8_fu_11764_p2 ^ tmp_70_7_reg_13715);
assign tmp26_fu_3737_p2 = (sboxes_q11 ^ x_assign_0_3_fu_3269_p2);
assign tmp270_fu_11931_p2 = (sboxes_q163 ^ x_assign_8_1_fu_11309_p2);
assign tmp271_fu_11942_p2 = (tmp272_fu_11937_p2 ^ rv_8_8_1_fu_11415_p3);
assign tmp272_fu_11937_p2 = (tmp_67_8_fu_11769_p2 ^ tmp_71_7_reg_13721);
assign tmp273_fu_11954_p2 = (rv_11_8_1_fu_11449_p3 ^ tmp_47_8_1_fu_11315_p2);
assign tmp274_fu_11960_p2 = (tmp_68_8_fu_11774_p2 ^ tmp_72_7_reg_13727);
assign tmp275_fu_11971_p2 = (sboxes_q168 ^ rv_2_8_2_fu_11495_p3);
assign tmp276_fu_11977_p2 = (e_8_2_fu_11469_p2 ^ tmp_73_8_fu_11779_p2);
assign tmp277_fu_11989_p2 = (sboxes_q173 ^ e_8_2_fu_11469_p2);
assign tmp278_fu_11995_p2 = (rv_5_8_2_fu_11529_p3 ^ tmp_74_8_fu_11784_p2);
assign tmp279_fu_12007_p2 = (sboxes_q167 ^ x_assign_8_2_fu_11457_p2);
assign tmp27_fu_3743_p2 = (rv_8_0_3_fu_3375_p3 ^ tmp_79_fu_3493_p2);
assign tmp280_fu_12013_p2 = (rv_8_8_2_fu_11563_p3 ^ tmp_75_8_fu_11789_p2);
assign tmp281_fu_12025_p2 = (tmp_47_8_2_fu_11463_p2 ^ tmp_76_8_fu_11794_p2);
assign tmp282_fu_12037_p2 = (sboxes_q172 ^ rv_2_8_3_fu_11643_p3);
assign tmp283_fu_12043_p2 = (e_8_3_fu_11617_p2 ^ tmp_77_8_fu_11799_p2);
assign tmp284_fu_12055_p2 = (sboxes_q161 ^ e_8_3_fu_11617_p2);
assign tmp285_fu_12061_p2 = (rv_5_8_3_fu_11677_p3 ^ tmp_78_8_fu_11804_p2);
assign tmp286_fu_12073_p2 = (sboxes_q171 ^ x_assign_8_3_fu_11605_p2);
assign tmp287_fu_12079_p2 = (rv_8_8_3_fu_11711_p3 ^ tmp_79_8_fu_11809_p2);
assign tmp288_fu_12091_p2 = (tmp_47_8_3_fu_11611_p2 ^ tmp_80_8_fu_11814_p2);
assign tmp289_fu_12229_p2 = (tmp_4_fu_12203_p2 ^ tmp_65_8_reg_13857);
assign tmp28_fu_3755_p2 = (tmp_47_0_3_fu_3275_p2 ^ tmp_80_fu_3498_p2);
assign tmp290_fu_12240_p2 = (sboxes_q185 ^ tmp_66_8_reg_13862);
assign tmp291_fu_12251_p2 = (sboxes_q190 ^ tmp_67_8_reg_13867);
assign tmp292_fu_12262_p2 = (sboxes_q195 ^ tmp_68_8_reg_13872);
assign tmp293_fu_12297_p2 = (tmp_73_8_reg_13877 ^ tmp_9_fu_12209_p2);
assign tmp294_fu_12308_p2 = (tmp_74_8_reg_13882 ^ tmp_11_fu_12214_p2);
assign tmp295_fu_12319_p2 = (tmp_75_8_reg_13887 ^ tmp_12_fu_12219_p2);
assign tmp296_fu_12330_p2 = (tmp_76_8_reg_13892 ^ tmp_13_fu_12224_p2);
assign tmp297_fu_12341_p2 = (tmp_9_fu_12209_p2 ^ ap_reg_pp0_iter9_tmp_77_7_reg_13733);
assign tmp298_fu_12352_p2 = (tmp_11_fu_12214_p2 ^ ap_reg_pp0_iter9_tmp_78_7_reg_13739);
assign tmp299_fu_12363_p2 = (tmp_12_fu_12219_p2 ^ ap_reg_pp0_iter9_tmp_79_7_reg_13745);
assign tmp29_fu_4525_p2 = (sboxes_q20 ^ rv_2_1_fu_3905_p3);
assign tmp2_fu_3509_p2 = (e_fu_2837_p2 ^ tmp_65_fu_3422_p2);
assign tmp300_fu_12374_p2 = (tmp_13_fu_12224_p2 ^ ap_reg_pp0_iter9_tmp_80_7_reg_13751);
assign tmp30_fu_4531_p2 = (e_1_fu_3879_p2 ^ tmp_65_1_fu_4465_p2);
assign tmp31_fu_4543_p2 = (sboxes_q25 ^ e_1_fu_3879_p2);
assign tmp32_fu_4549_p2 = (rv_5_1_fu_3939_p3 ^ tmp_66_1_fu_4470_p2);
assign tmp33_fu_4561_p2 = (sboxes_q35 ^ x_assign_s_fu_3867_p2);
assign tmp34_fu_4567_p2 = (rv_8_1_fu_3973_p3 ^ tmp_67_1_fu_4475_p2);
assign tmp35_fu_4579_p2 = (tmp_47_1_fu_3873_p2 ^ tmp_68_1_fu_4480_p2);
assign tmp36_fu_4591_p2 = (sboxes_q24 ^ rv_2_1_1_fu_4053_p3);
assign tmp37_fu_4597_p2 = (e_1_1_fu_4027_p2 ^ tmp_69_1_fu_4485_p2);
assign tmp38_fu_4609_p2 = (sboxes_q29 ^ e_1_1_fu_4027_p2);
assign tmp39_fu_4615_p2 = (rv_5_1_1_fu_4087_p3 ^ tmp_70_1_fu_4490_p2);
assign tmp3_fu_3521_p2 = (sboxes_q5 ^ e_fu_2837_p2);
assign tmp40_fu_4627_p2 = (sboxes_q23 ^ x_assign_171_1_fu_4015_p2);
assign tmp41_fu_4633_p2 = (rv_8_1_1_fu_4121_p3 ^ tmp_71_1_fu_4495_p2);
assign tmp42_fu_4645_p2 = (tmp_47_1_1_fu_4021_p2 ^ tmp_72_1_fu_4500_p2);
assign tmp43_fu_4657_p2 = (sboxes_q28 ^ rv_2_1_2_fu_4201_p3);
assign tmp44_fu_4668_p2 = (tmp45_fu_4663_p2 ^ e_1_2_fu_4175_p2);
assign tmp45_fu_4663_p2 = (tmp_69_1_fu_4485_p2 ^ tmp_73_reg_12633);
assign tmp46_fu_4680_p2 = (sboxes_q33 ^ e_1_2_fu_4175_p2);
assign tmp47_fu_4691_p2 = (tmp48_fu_4686_p2 ^ rv_5_1_2_fu_4235_p3);
assign tmp48_fu_4686_p2 = (tmp_70_1_fu_4490_p2 ^ tmp_74_reg_12639);
assign tmp49_fu_4703_p2 = (sboxes_q27 ^ x_assign_171_2_fu_4163_p2);
assign tmp4_fu_3527_p2 = (rv_5_fu_2897_p3 ^ tmp_66_fu_3428_p2);
assign tmp50_fu_4714_p2 = (tmp51_fu_4709_p2 ^ rv_8_1_2_fu_4269_p3);
assign tmp51_fu_4709_p2 = (tmp_71_1_fu_4495_p2 ^ tmp_75_reg_12645);
assign tmp52_fu_4726_p2 = (rv_11_1_2_fu_4303_p3 ^ tmp_47_1_2_fu_4169_p2);
assign tmp53_fu_4732_p2 = (tmp_72_1_fu_4500_p2 ^ tmp_76_reg_12651);
assign tmp54_fu_4743_p2 = (sboxes_q32 ^ rv_2_1_3_fu_4349_p3);
assign tmp55_fu_4749_p2 = (e_1_3_fu_4323_p2 ^ tmp_77_1_fu_4505_p2);
assign tmp56_fu_4761_p2 = (sboxes_q21 ^ e_1_3_fu_4323_p2);
assign tmp57_fu_4767_p2 = (rv_5_1_3_fu_4383_p3 ^ tmp_78_1_fu_4510_p2);
assign tmp58_fu_4779_p2 = (sboxes_q31 ^ x_assign_171_3_fu_4311_p2);
assign tmp59_fu_4785_p2 = (rv_8_1_3_fu_4417_p3 ^ tmp_79_1_fu_4515_p2);
assign tmp5_fu_3539_p2 = (sboxes_q15 ^ x_assign_fu_2825_p2);
assign tmp60_fu_4797_p2 = (tmp_47_1_3_fu_4317_p2 ^ tmp_80_1_fu_4520_p2);
assign tmp61_fu_5501_p2 = (tmp_65_1_reg_12757 ^ 8'd4);
assign tmp62_fu_5567_p2 = (sboxes_q40 ^ rv_2_2_fu_4947_p3);
assign tmp63_fu_5573_p2 = (e_2_fu_4921_p2 ^ tmp_65_2_fu_5506_p2);
assign tmp64_fu_5585_p2 = (sboxes_q45 ^ e_2_fu_4921_p2);
assign tmp65_fu_5591_p2 = (rv_5_2_fu_4981_p3 ^ tmp_66_2_fu_5512_p2);
assign tmp66_fu_5603_p2 = (sboxes_q55 ^ x_assign_9_fu_4909_p2);
assign tmp67_fu_5609_p2 = (rv_8_2_fu_5015_p3 ^ tmp_67_2_fu_5517_p2);
assign tmp68_fu_5621_p2 = (tmp_47_2_fu_4915_p2 ^ tmp_68_2_fu_5522_p2);
assign tmp69_fu_5633_p2 = (sboxes_q44 ^ rv_2_2_1_fu_5095_p3);
assign tmp6_fu_3545_p2 = (rv_8_fu_2931_p3 ^ tmp_67_fu_3433_p2);
assign tmp70_fu_5644_p2 = (tmp71_fu_5639_p2 ^ e_2_1_fu_5069_p2);
assign tmp71_fu_5639_p2 = (tmp_65_2_fu_5506_p2 ^ tmp_69_1_reg_12777);
assign tmp72_fu_5656_p2 = (sboxes_q49 ^ e_2_1_fu_5069_p2);
assign tmp73_fu_5667_p2 = (tmp74_fu_5662_p2 ^ rv_5_2_1_fu_5129_p3);
assign tmp74_fu_5662_p2 = (tmp_66_2_fu_5512_p2 ^ tmp_70_1_reg_12783);
assign tmp75_fu_5679_p2 = (sboxes_q43 ^ x_assign_273_1_fu_5057_p2);
assign tmp76_fu_5690_p2 = (tmp77_fu_5685_p2 ^ rv_8_2_1_fu_5163_p3);
assign tmp77_fu_5685_p2 = (tmp_67_2_fu_5517_p2 ^ tmp_71_1_reg_12789);
assign tmp78_fu_5702_p2 = (rv_11_2_1_fu_5197_p3 ^ tmp_47_2_1_fu_5063_p2);
assign tmp79_fu_5708_p2 = (tmp_68_2_fu_5522_p2 ^ tmp_72_1_reg_12795);
assign tmp7_fu_3557_p2 = (tmp_47_fu_2831_p2 ^ tmp_68_fu_3438_p2);
assign tmp80_fu_5719_p2 = (sboxes_q48 ^ rv_2_2_2_fu_5243_p3);
assign tmp81_fu_5725_p2 = (e_2_2_fu_5217_p2 ^ tmp_73_2_fu_5527_p2);
assign tmp82_fu_5737_p2 = (sboxes_q53 ^ e_2_2_fu_5217_p2);
assign tmp83_fu_5743_p2 = (rv_5_2_2_fu_5277_p3 ^ tmp_74_2_fu_5532_p2);
assign tmp84_fu_5755_p2 = (sboxes_q47 ^ x_assign_273_2_fu_5205_p2);
assign tmp85_fu_5761_p2 = (rv_8_2_2_fu_5311_p3 ^ tmp_75_2_fu_5537_p2);
assign tmp86_fu_5773_p2 = (tmp_47_2_2_fu_5211_p2 ^ tmp_76_2_fu_5542_p2);
assign tmp87_fu_5785_p2 = (sboxes_q52 ^ rv_2_2_3_fu_5391_p3);
assign tmp88_fu_5791_p2 = (e_2_3_fu_5365_p2 ^ tmp_77_2_fu_5547_p2);
assign tmp89_fu_5803_p2 = (sboxes_q41 ^ e_2_3_fu_5365_p2);
assign tmp8_fu_3569_p2 = (sboxes_q4 ^ rv_2_0_1_fu_3011_p3);
assign tmp90_fu_5809_p2 = (rv_5_2_3_fu_5425_p3 ^ tmp_78_2_fu_5552_p2);
assign tmp91_fu_5821_p2 = (sboxes_q51 ^ x_assign_273_3_fu_5353_p2);
assign tmp92_fu_5827_p2 = (rv_8_2_3_fu_5459_p3 ^ tmp_79_2_fu_5557_p2);
assign tmp93_fu_5839_p2 = (tmp_47_2_3_fu_5359_p2 ^ tmp_80_2_fu_5562_p2);
assign tmp94_fu_6609_p2 = (sboxes_q60 ^ rv_2_3_fu_5989_p3);
assign tmp95_fu_6615_p2 = (e_3_fu_5963_p2 ^ tmp_65_3_fu_6549_p2);
assign tmp96_fu_6627_p2 = (sboxes_q65 ^ e_3_fu_5963_p2);
assign tmp97_fu_6633_p2 = (rv_5_3_fu_6023_p3 ^ tmp_66_3_fu_6554_p2);
assign tmp98_fu_6645_p2 = (sboxes_q75 ^ x_assign_10_fu_5951_p2);
assign tmp99_fu_6651_p2 = (rv_8_3_fu_6057_p3 ^ tmp_67_3_fu_6559_p2);
assign tmp9_fu_3575_p2 = (e_0_1_fu_2985_p2 ^ tmp_69_fu_3443_p2);
assign tmp_100_fu_2625_p1 = key_V_read[7:0];
assign tmp_101_fu_2843_p2 = x_assign_fu_2825_p2 << 8'd1;
assign tmp_102_fu_2849_p3 = x_assign_fu_2825_p2[32'd7];
assign tmp_103_fu_2877_p2 = x_assign_1_fu_2871_p2 << 8'd1;
assign tmp_104_fu_2883_p3 = x_assign_1_fu_2871_p2[32'd7];
assign tmp_105_fu_2911_p2 = x_assign_2_fu_2905_p2 << 8'd1;
assign tmp_106_fu_2917_p3 = x_assign_2_fu_2905_p2[32'd7];
assign tmp_107_fu_2945_p2 = x_assign_3_fu_2939_p2 << 8'd1;
assign tmp_108_fu_2951_p3 = x_assign_3_fu_2939_p2[32'd7];
assign tmp_109_fu_2991_p2 = x_assign_0_1_fu_2973_p2 << 8'd1;
assign tmp_10_10_fu_2695_p2 = (p_Result_11_fu_2541_p4 ^ p_Result_1_10_fu_2551_p4);
assign tmp_10_11_fu_2701_p2 = (p_Result_12_fu_2561_p4 ^ p_Result_1_11_fu_2571_p4);
assign tmp_10_12_fu_2707_p2 = (p_Result_13_fu_2581_p4 ^ p_Result_1_12_fu_2591_p4);
assign tmp_10_13_fu_2713_p2 = (p_Result_14_fu_2601_p4 ^ p_Result_1_13_fu_2611_p4);
assign tmp_10_14_fu_2719_p2 = (tmp_99_fu_2621_p1 ^ tmp_100_fu_2625_p1);
assign tmp_10_1_fu_2635_p2 = (p_Result_s_39_fu_2341_p4 ^ p_Result_1_1_fu_2351_p4);
assign tmp_10_2_fu_2641_p2 = (p_Result_2_fu_2361_p4 ^ p_Result_1_2_fu_2371_p4);
assign tmp_10_3_fu_2647_p2 = (p_Result_3_fu_2381_p4 ^ p_Result_1_3_fu_2391_p4);
assign tmp_10_4_fu_2653_p2 = (p_Result_4_fu_2401_p4 ^ p_Result_1_4_fu_2411_p4);
assign tmp_10_5_fu_2659_p2 = (p_Result_5_fu_2421_p4 ^ p_Result_1_5_fu_2431_p4);
assign tmp_10_6_fu_2665_p2 = (p_Result_6_fu_2441_p4 ^ p_Result_1_6_fu_2451_p4);
assign tmp_10_7_fu_2671_p2 = (p_Result_7_fu_2461_p4 ^ p_Result_1_7_fu_2471_p4);
assign tmp_10_8_fu_2677_p2 = (p_Result_8_fu_2481_p4 ^ p_Result_1_8_fu_2491_p4);
assign tmp_10_9_fu_2683_p2 = (p_Result_9_fu_2501_p4 ^ p_Result_1_9_fu_2511_p4);
assign tmp_10_fu_2629_p2 = (p_Result_s_fu_2321_p4 ^ p_Result_1_fu_2331_p4);
assign tmp_10_s_fu_2689_p2 = (p_Result_10_fu_2521_p4 ^ p_Result_1_s_fu_2531_p4);
assign tmp_110_fu_2997_p3 = x_assign_0_1_fu_2973_p2[32'd7];
assign tmp_111_fu_3025_p2 = x_assign_1_0_1_fu_3019_p2 << 8'd1;
assign tmp_112_fu_3031_p3 = x_assign_1_0_1_fu_3019_p2[32'd7];
assign tmp_113_fu_3059_p2 = x_assign_2_0_1_fu_3053_p2 << 8'd1;
assign tmp_114_fu_3065_p3 = x_assign_2_0_1_fu_3053_p2[32'd7];
assign tmp_115_fu_3093_p2 = x_assign_3_0_1_fu_3087_p2 << 8'd1;
assign tmp_116_fu_3099_p3 = x_assign_3_0_1_fu_3087_p2[32'd7];
assign tmp_117_fu_3139_p2 = x_assign_0_2_fu_3121_p2 << 8'd1;
assign tmp_118_fu_3145_p3 = x_assign_0_2_fu_3121_p2[32'd7];
assign tmp_119_fu_3173_p2 = x_assign_1_0_2_fu_3167_p2 << 8'd1;
assign tmp_11_fu_12214_p2 = (sboxes_q197 ^ ap_reg_pp0_iter9_tmp_70_7_reg_13715);
assign tmp_120_fu_3179_p3 = x_assign_1_0_2_fu_3167_p2[32'd7];
assign tmp_121_fu_3207_p2 = x_assign_2_0_2_fu_3201_p2 << 8'd1;
assign tmp_122_fu_3213_p3 = x_assign_2_0_2_fu_3201_p2[32'd7];
assign tmp_123_fu_3241_p2 = x_assign_3_0_2_fu_3235_p2 << 8'd1;
assign tmp_124_fu_3247_p3 = x_assign_3_0_2_fu_3235_p2[32'd7];
assign tmp_125_fu_3287_p2 = x_assign_0_3_fu_3269_p2 << 8'd1;
assign tmp_126_fu_3293_p3 = x_assign_0_3_fu_3269_p2[32'd7];
assign tmp_127_fu_3321_p2 = x_assign_1_0_3_fu_3315_p2 << 8'd1;
assign tmp_128_fu_3327_p3 = x_assign_1_0_3_fu_3315_p2[32'd7];
assign tmp_129_fu_3355_p2 = x_assign_2_0_3_fu_3349_p2 << 8'd1;
assign tmp_12_fu_12219_p2 = (sboxes_q198 ^ ap_reg_pp0_iter9_tmp_71_7_reg_13721);
assign tmp_130_fu_3361_p3 = x_assign_2_0_3_fu_3349_p2[32'd7];
assign tmp_131_fu_3389_p2 = x_assign_3_0_3_fu_3383_p2 << 8'd1;
assign tmp_132_fu_3395_p3 = x_assign_3_0_3_fu_3383_p2[32'd7];
assign tmp_133_fu_3885_p2 = x_assign_s_fu_3867_p2 << 8'd1;
assign tmp_134_fu_3891_p3 = x_assign_s_fu_3867_p2[32'd7];
assign tmp_135_fu_3919_p2 = x_assign_1_1_fu_3913_p2 << 8'd1;
assign tmp_136_fu_3925_p3 = x_assign_1_1_fu_3913_p2[32'd7];
assign tmp_137_fu_3953_p2 = x_assign_2_1_fu_3947_p2 << 8'd1;
assign tmp_138_fu_3959_p3 = x_assign_2_1_fu_3947_p2[32'd7];
assign tmp_139_fu_3987_p2 = x_assign_3_1_fu_3981_p2 << 8'd1;
assign tmp_13_fu_12224_p2 = (sboxes_q199 ^ ap_reg_pp0_iter9_tmp_72_7_reg_13727);
assign tmp_140_fu_3993_p3 = x_assign_3_1_fu_3981_p2[32'd7];
assign tmp_141_fu_4033_p2 = x_assign_171_1_fu_4015_p2 << 8'd1;
assign tmp_142_fu_4039_p3 = x_assign_171_1_fu_4015_p2[32'd7];
assign tmp_143_fu_4067_p2 = x_assign_1_1_1_fu_4061_p2 << 8'd1;
assign tmp_144_fu_4073_p3 = x_assign_1_1_1_fu_4061_p2[32'd7];
assign tmp_145_fu_4101_p2 = x_assign_2_1_1_fu_4095_p2 << 8'd1;
assign tmp_146_fu_4107_p3 = x_assign_2_1_1_fu_4095_p2[32'd7];
assign tmp_147_fu_4135_p2 = x_assign_3_1_1_fu_4129_p2 << 8'd1;
assign tmp_148_fu_4141_p3 = x_assign_3_1_1_fu_4129_p2[32'd7];
assign tmp_149_fu_4181_p2 = x_assign_171_2_fu_4163_p2 << 8'd1;
assign tmp_150_fu_4187_p3 = x_assign_171_2_fu_4163_p2[32'd7];
assign tmp_151_fu_4215_p2 = x_assign_1_1_2_fu_4209_p2 << 8'd1;
assign tmp_152_fu_4221_p3 = x_assign_1_1_2_fu_4209_p2[32'd7];
assign tmp_153_fu_4249_p2 = x_assign_2_1_2_fu_4243_p2 << 8'd1;
assign tmp_154_fu_4255_p3 = x_assign_2_1_2_fu_4243_p2[32'd7];
assign tmp_155_fu_4283_p2 = x_assign_3_1_2_fu_4277_p2 << 8'd1;
assign tmp_156_fu_4289_p3 = x_assign_3_1_2_fu_4277_p2[32'd7];
assign tmp_157_fu_4329_p2 = x_assign_171_3_fu_4311_p2 << 8'd1;
assign tmp_158_fu_4335_p3 = x_assign_171_3_fu_4311_p2[32'd7];
assign tmp_159_fu_4363_p2 = x_assign_1_1_3_fu_4357_p2 << 8'd1;
assign tmp_160_fu_4369_p3 = x_assign_1_1_3_fu_4357_p2[32'd7];
assign tmp_161_fu_4397_p2 = x_assign_2_1_3_fu_4391_p2 << 8'd1;
assign tmp_162_fu_4403_p3 = x_assign_2_1_3_fu_4391_p2[32'd7];
assign tmp_163_fu_4431_p2 = x_assign_3_1_3_fu_4425_p2 << 8'd1;
assign tmp_164_fu_4437_p3 = x_assign_3_1_3_fu_4425_p2[32'd7];
assign tmp_165_fu_4927_p2 = x_assign_9_fu_4909_p2 << 8'd1;
assign tmp_166_fu_4933_p3 = x_assign_9_fu_4909_p2[32'd7];
assign tmp_167_fu_4961_p2 = x_assign_1_2_fu_4955_p2 << 8'd1;
assign tmp_168_fu_4967_p3 = x_assign_1_2_fu_4955_p2[32'd7];
assign tmp_169_fu_4995_p2 = x_assign_2_2_fu_4989_p2 << 8'd1;
assign tmp_170_fu_5001_p3 = x_assign_2_2_fu_4989_p2[32'd7];
assign tmp_171_fu_5029_p2 = x_assign_3_2_fu_5023_p2 << 8'd1;
assign tmp_172_fu_5035_p3 = x_assign_3_2_fu_5023_p2[32'd7];
assign tmp_173_fu_5075_p2 = x_assign_273_1_fu_5057_p2 << 8'd1;
assign tmp_174_fu_5081_p3 = x_assign_273_1_fu_5057_p2[32'd7];
assign tmp_175_fu_5109_p2 = x_assign_1_2_1_fu_5103_p2 << 8'd1;
assign tmp_176_fu_5115_p3 = x_assign_1_2_1_fu_5103_p2[32'd7];
assign tmp_177_fu_5143_p2 = x_assign_2_2_1_fu_5137_p2 << 8'd1;
assign tmp_178_fu_5149_p3 = x_assign_2_2_1_fu_5137_p2[32'd7];
assign tmp_179_fu_5177_p2 = x_assign_3_2_1_fu_5171_p2 << 8'd1;
assign tmp_180_fu_5183_p3 = x_assign_3_2_1_fu_5171_p2[32'd7];
assign tmp_181_fu_5223_p2 = x_assign_273_2_fu_5205_p2 << 8'd1;
assign tmp_182_fu_5229_p3 = x_assign_273_2_fu_5205_p2[32'd7];
assign tmp_183_fu_5257_p2 = x_assign_1_2_2_fu_5251_p2 << 8'd1;
assign tmp_184_fu_5263_p3 = x_assign_1_2_2_fu_5251_p2[32'd7];
assign tmp_185_fu_5291_p2 = x_assign_2_2_2_fu_5285_p2 << 8'd1;
assign tmp_186_fu_5297_p3 = x_assign_2_2_2_fu_5285_p2[32'd7];
assign tmp_187_fu_5325_p2 = x_assign_3_2_2_fu_5319_p2 << 8'd1;
assign tmp_188_fu_5331_p3 = x_assign_3_2_2_fu_5319_p2[32'd7];
assign tmp_189_fu_5371_p2 = x_assign_273_3_fu_5353_p2 << 8'd1;
assign tmp_190_fu_5377_p3 = x_assign_273_3_fu_5353_p2[32'd7];
assign tmp_191_fu_5405_p2 = x_assign_1_2_3_fu_5399_p2 << 8'd1;
assign tmp_192_fu_5411_p3 = x_assign_1_2_3_fu_5399_p2[32'd7];
assign tmp_193_fu_5439_p2 = x_assign_2_2_3_fu_5433_p2 << 8'd1;
assign tmp_194_fu_5445_p3 = x_assign_2_2_3_fu_5433_p2[32'd7];
assign tmp_195_fu_5473_p2 = x_assign_3_2_3_fu_5467_p2 << 8'd1;
assign tmp_196_fu_5479_p3 = x_assign_3_2_3_fu_5467_p2[32'd7];
assign tmp_197_fu_5969_p2 = x_assign_10_fu_5951_p2 << 8'd1;
assign tmp_198_fu_5975_p3 = x_assign_10_fu_5951_p2[32'd7];
assign tmp_199_fu_6003_p2 = x_assign_1_3_fu_5997_p2 << 8'd1;
assign tmp_1_fu_12188_p1 = tmp_79_8_fu_11809_p2;
assign tmp_200_fu_6009_p3 = x_assign_1_3_fu_5997_p2[32'd7];
assign tmp_201_fu_6037_p2 = x_assign_2_3_fu_6031_p2 << 8'd1;
assign tmp_202_fu_6043_p3 = x_assign_2_3_fu_6031_p2[32'd7];
assign tmp_203_fu_6071_p2 = x_assign_3_3_fu_6065_p2 << 8'd1;
assign tmp_204_fu_6077_p3 = x_assign_3_3_fu_6065_p2[32'd7];
assign tmp_205_fu_6117_p2 = x_assign_375_1_fu_6099_p2 << 8'd1;
assign tmp_206_fu_6123_p3 = x_assign_375_1_fu_6099_p2[32'd7];
assign tmp_207_fu_6151_p2 = x_assign_1_3_1_fu_6145_p2 << 8'd1;
assign tmp_208_fu_6157_p3 = x_assign_1_3_1_fu_6145_p2[32'd7];
assign tmp_209_fu_6185_p2 = x_assign_2_3_1_fu_6179_p2 << 8'd1;
assign tmp_210_fu_6191_p3 = x_assign_2_3_1_fu_6179_p2[32'd7];
assign tmp_211_fu_6219_p2 = x_assign_3_3_1_fu_6213_p2 << 8'd1;
assign tmp_212_fu_6225_p3 = x_assign_3_3_1_fu_6213_p2[32'd7];
assign tmp_213_fu_6265_p2 = x_assign_375_2_fu_6247_p2 << 8'd1;
assign tmp_214_fu_6271_p3 = x_assign_375_2_fu_6247_p2[32'd7];
assign tmp_215_fu_6299_p2 = x_assign_1_3_2_fu_6293_p2 << 8'd1;
assign tmp_216_fu_6305_p3 = x_assign_1_3_2_fu_6293_p2[32'd7];
assign tmp_217_fu_6333_p2 = x_assign_2_3_2_fu_6327_p2 << 8'd1;
assign tmp_218_fu_6339_p3 = x_assign_2_3_2_fu_6327_p2[32'd7];
assign tmp_219_fu_6367_p2 = x_assign_3_3_2_fu_6361_p2 << 8'd1;
assign tmp_220_fu_6373_p3 = x_assign_3_3_2_fu_6361_p2[32'd7];
assign tmp_221_fu_6413_p2 = x_assign_375_3_fu_6395_p2 << 8'd1;
assign tmp_222_fu_6419_p3 = x_assign_375_3_fu_6395_p2[32'd7];
assign tmp_223_fu_6447_p2 = x_assign_1_3_3_fu_6441_p2 << 8'd1;
assign tmp_224_fu_6453_p3 = x_assign_1_3_3_fu_6441_p2[32'd7];
assign tmp_225_fu_6481_p2 = x_assign_2_3_3_fu_6475_p2 << 8'd1;
assign tmp_226_fu_6487_p3 = x_assign_2_3_3_fu_6475_p2[32'd7];
assign tmp_227_fu_6515_p2 = x_assign_3_3_3_fu_6509_p2 << 8'd1;
assign tmp_228_fu_6521_p3 = x_assign_3_3_3_fu_6509_p2[32'd7];
assign tmp_229_fu_7011_p2 = x_assign_4_fu_6993_p2 << 8'd1;
assign tmp_230_fu_7017_p3 = x_assign_4_fu_6993_p2[32'd7];
assign tmp_231_fu_7045_p2 = x_assign_1_4_fu_7039_p2 << 8'd1;
assign tmp_232_fu_7051_p3 = x_assign_1_4_fu_7039_p2[32'd7];
assign tmp_233_fu_7079_p2 = x_assign_2_4_fu_7073_p2 << 8'd1;
assign tmp_234_fu_7085_p3 = x_assign_2_4_fu_7073_p2[32'd7];
assign tmp_235_fu_7113_p2 = x_assign_3_4_fu_7107_p2 << 8'd1;
assign tmp_236_fu_7119_p3 = x_assign_3_4_fu_7107_p2[32'd7];
assign tmp_237_fu_7159_p2 = x_assign_4_1_fu_7141_p2 << 8'd1;
assign tmp_238_fu_7165_p3 = x_assign_4_1_fu_7141_p2[32'd7];
assign tmp_239_fu_7193_p2 = x_assign_1_4_1_fu_7187_p2 << 8'd1;
assign tmp_240_fu_7199_p3 = x_assign_1_4_1_fu_7187_p2[32'd7];
assign tmp_241_fu_7227_p2 = x_assign_2_4_1_fu_7221_p2 << 8'd1;
assign tmp_242_fu_7233_p3 = x_assign_2_4_1_fu_7221_p2[32'd7];
assign tmp_243_fu_7261_p2 = x_assign_3_4_1_fu_7255_p2 << 8'd1;
assign tmp_244_fu_7267_p3 = x_assign_3_4_1_fu_7255_p2[32'd7];
assign tmp_245_fu_7307_p2 = x_assign_4_2_fu_7289_p2 << 8'd1;
assign tmp_246_fu_7313_p3 = x_assign_4_2_fu_7289_p2[32'd7];
assign tmp_247_fu_7341_p2 = x_assign_1_4_2_fu_7335_p2 << 8'd1;
assign tmp_248_fu_7347_p3 = x_assign_1_4_2_fu_7335_p2[32'd7];
assign tmp_249_fu_7375_p2 = x_assign_2_4_2_fu_7369_p2 << 8'd1;
assign tmp_250_fu_7381_p3 = x_assign_2_4_2_fu_7369_p2[32'd7];
assign tmp_251_fu_7409_p2 = x_assign_3_4_2_fu_7403_p2 << 8'd1;
assign tmp_252_fu_7415_p3 = x_assign_3_4_2_fu_7403_p2[32'd7];
assign tmp_253_fu_7455_p2 = x_assign_4_3_fu_7437_p2 << 8'd1;
assign tmp_254_fu_7461_p3 = x_assign_4_3_fu_7437_p2[32'd7];
assign tmp_255_fu_7489_p2 = x_assign_1_4_3_fu_7483_p2 << 8'd1;
assign tmp_256_fu_7495_p3 = x_assign_1_4_3_fu_7483_p2[32'd7];
assign tmp_257_fu_7523_p2 = x_assign_2_4_3_fu_7517_p2 << 8'd1;
assign tmp_258_fu_7529_p3 = x_assign_2_4_3_fu_7517_p2[32'd7];
assign tmp_259_fu_7557_p2 = x_assign_3_4_3_fu_7551_p2 << 8'd1;
assign tmp_260_fu_7563_p3 = x_assign_3_4_3_fu_7551_p2[32'd7];
assign tmp_261_fu_8053_p2 = x_assign_5_fu_8035_p2 << 8'd1;
assign tmp_262_fu_8059_p3 = x_assign_5_fu_8035_p2[32'd7];
assign tmp_263_fu_8087_p2 = x_assign_1_5_fu_8081_p2 << 8'd1;
assign tmp_264_fu_8093_p3 = x_assign_1_5_fu_8081_p2[32'd7];
assign tmp_265_fu_8121_p2 = x_assign_2_5_fu_8115_p2 << 8'd1;
assign tmp_266_fu_8127_p3 = x_assign_2_5_fu_8115_p2[32'd7];
assign tmp_267_fu_8155_p2 = x_assign_3_5_fu_8149_p2 << 8'd1;
assign tmp_268_fu_8161_p3 = x_assign_3_5_fu_8149_p2[32'd7];
assign tmp_269_fu_8201_p2 = x_assign_5_1_fu_8183_p2 << 8'd1;
assign tmp_270_fu_8207_p3 = x_assign_5_1_fu_8183_p2[32'd7];
assign tmp_271_fu_8235_p2 = x_assign_1_5_1_fu_8229_p2 << 8'd1;
assign tmp_272_fu_8241_p3 = x_assign_1_5_1_fu_8229_p2[32'd7];
assign tmp_273_fu_8269_p2 = x_assign_2_5_1_fu_8263_p2 << 8'd1;
assign tmp_274_fu_8275_p3 = x_assign_2_5_1_fu_8263_p2[32'd7];
assign tmp_275_fu_8303_p2 = x_assign_3_5_1_fu_8297_p2 << 8'd1;
assign tmp_276_fu_8309_p3 = x_assign_3_5_1_fu_8297_p2[32'd7];
assign tmp_277_fu_8349_p2 = x_assign_5_2_fu_8331_p2 << 8'd1;
assign tmp_278_fu_8355_p3 = x_assign_5_2_fu_8331_p2[32'd7];
assign tmp_279_fu_8383_p2 = x_assign_1_5_2_fu_8377_p2 << 8'd1;
assign tmp_280_fu_8389_p3 = x_assign_1_5_2_fu_8377_p2[32'd7];
assign tmp_281_fu_8417_p2 = x_assign_2_5_2_fu_8411_p2 << 8'd1;
assign tmp_282_fu_8423_p3 = x_assign_2_5_2_fu_8411_p2[32'd7];
assign tmp_283_fu_8451_p2 = x_assign_3_5_2_fu_8445_p2 << 8'd1;
assign tmp_284_fu_8457_p3 = x_assign_3_5_2_fu_8445_p2[32'd7];
assign tmp_285_fu_8497_p2 = x_assign_5_3_fu_8479_p2 << 8'd1;
assign tmp_286_fu_8503_p3 = x_assign_5_3_fu_8479_p2[32'd7];
assign tmp_287_fu_8531_p2 = x_assign_1_5_3_fu_8525_p2 << 8'd1;
assign tmp_288_fu_8537_p3 = x_assign_1_5_3_fu_8525_p2[32'd7];
assign tmp_289_fu_8565_p2 = x_assign_2_5_3_fu_8559_p2 << 8'd1;
assign tmp_290_fu_8571_p3 = x_assign_2_5_3_fu_8559_p2[32'd7];
assign tmp_291_fu_8599_p2 = x_assign_3_5_3_fu_8593_p2 << 8'd1;
assign tmp_292_fu_8605_p3 = x_assign_3_5_3_fu_8593_p2[32'd7];
assign tmp_293_fu_9095_p2 = x_assign_6_fu_9077_p2 << 8'd1;
assign tmp_294_fu_9101_p3 = x_assign_6_fu_9077_p2[32'd7];
assign tmp_295_fu_9129_p2 = x_assign_1_6_fu_9123_p2 << 8'd1;
assign tmp_296_fu_9135_p3 = x_assign_1_6_fu_9123_p2[32'd7];
assign tmp_297_fu_9163_p2 = x_assign_2_6_fu_9157_p2 << 8'd1;
assign tmp_298_fu_9169_p3 = x_assign_2_6_fu_9157_p2[32'd7];
assign tmp_299_fu_9197_p2 = x_assign_3_6_fu_9191_p2 << 8'd1;
assign tmp_2_fu_12193_p1 = tmp_80_8_fu_11814_p2;
assign tmp_300_fu_9203_p3 = x_assign_3_6_fu_9191_p2[32'd7];
assign tmp_301_fu_9243_p2 = x_assign_6_1_fu_9225_p2 << 8'd1;
assign tmp_302_fu_9249_p3 = x_assign_6_1_fu_9225_p2[32'd7];
assign tmp_303_fu_9277_p2 = x_assign_1_6_1_fu_9271_p2 << 8'd1;
assign tmp_304_fu_9283_p3 = x_assign_1_6_1_fu_9271_p2[32'd7];
assign tmp_305_fu_9311_p2 = x_assign_2_6_1_fu_9305_p2 << 8'd1;
assign tmp_306_fu_9317_p3 = x_assign_2_6_1_fu_9305_p2[32'd7];
assign tmp_307_fu_9345_p2 = x_assign_3_6_1_fu_9339_p2 << 8'd1;
assign tmp_308_fu_9351_p3 = x_assign_3_6_1_fu_9339_p2[32'd7];
assign tmp_309_fu_9391_p2 = x_assign_6_2_fu_9373_p2 << 8'd1;
assign tmp_310_fu_9397_p3 = x_assign_6_2_fu_9373_p2[32'd7];
assign tmp_311_fu_9425_p2 = x_assign_1_6_2_fu_9419_p2 << 8'd1;
assign tmp_312_fu_9431_p3 = x_assign_1_6_2_fu_9419_p2[32'd7];
assign tmp_313_fu_9459_p2 = x_assign_2_6_2_fu_9453_p2 << 8'd1;
assign tmp_314_fu_9465_p3 = x_assign_2_6_2_fu_9453_p2[32'd7];
assign tmp_315_fu_9493_p2 = x_assign_3_6_2_fu_9487_p2 << 8'd1;
assign tmp_316_fu_9499_p3 = x_assign_3_6_2_fu_9487_p2[32'd7];
assign tmp_317_fu_9539_p2 = x_assign_6_3_fu_9521_p2 << 8'd1;
assign tmp_318_fu_9545_p3 = x_assign_6_3_fu_9521_p2[32'd7];
assign tmp_319_fu_9573_p2 = x_assign_1_6_3_fu_9567_p2 << 8'd1;
assign tmp_320_fu_9579_p3 = x_assign_1_6_3_fu_9567_p2[32'd7];
assign tmp_321_fu_9607_p2 = x_assign_2_6_3_fu_9601_p2 << 8'd1;
assign tmp_322_fu_9613_p3 = x_assign_2_6_3_fu_9601_p2[32'd7];
assign tmp_323_fu_9641_p2 = x_assign_3_6_3_fu_9635_p2 << 8'd1;
assign tmp_324_fu_9647_p3 = x_assign_3_6_3_fu_9635_p2[32'd7];
assign tmp_325_fu_10137_p2 = x_assign_7_fu_10119_p2 << 8'd1;
assign tmp_326_fu_10143_p3 = x_assign_7_fu_10119_p2[32'd7];
assign tmp_327_fu_10171_p2 = x_assign_1_7_fu_10165_p2 << 8'd1;
assign tmp_328_fu_10177_p3 = x_assign_1_7_fu_10165_p2[32'd7];
assign tmp_329_fu_10205_p2 = x_assign_2_7_fu_10199_p2 << 8'd1;
assign tmp_330_fu_10211_p3 = x_assign_2_7_fu_10199_p2[32'd7];
assign tmp_331_fu_10239_p2 = x_assign_3_7_fu_10233_p2 << 8'd1;
assign tmp_332_fu_10245_p3 = x_assign_3_7_fu_10233_p2[32'd7];
assign tmp_333_fu_10285_p2 = x_assign_7_1_fu_10267_p2 << 8'd1;
assign tmp_334_fu_10291_p3 = x_assign_7_1_fu_10267_p2[32'd7];
assign tmp_335_fu_10319_p2 = x_assign_1_7_1_fu_10313_p2 << 8'd1;
assign tmp_336_fu_10325_p3 = x_assign_1_7_1_fu_10313_p2[32'd7];
assign tmp_337_fu_10353_p2 = x_assign_2_7_1_fu_10347_p2 << 8'd1;
assign tmp_338_fu_10359_p3 = x_assign_2_7_1_fu_10347_p2[32'd7];
assign tmp_339_fu_10387_p2 = x_assign_3_7_1_fu_10381_p2 << 8'd1;
assign tmp_33_10_fu_12158_p1 = tmp_85_8_10_fu_12031_p2;
assign tmp_33_11_fu_12163_p1 = tmp_85_8_11_fu_12049_p2;
assign tmp_33_12_fu_12168_p1 = tmp_85_8_12_fu_12067_p2;
assign tmp_33_13_fu_12173_p1 = tmp_85_8_13_fu_12085_p2;
assign tmp_33_14_fu_12178_p1 = tmp_85_8_14_fu_12097_p2;
assign tmp_33_1_fu_12108_p1 = tmp_85_8_1_fu_11849_p2;
assign tmp_33_2_fu_12113_p1 = tmp_85_8_2_fu_11867_p2;
assign tmp_33_3_fu_12118_p1 = tmp_85_8_3_fu_11879_p2;
assign tmp_33_4_fu_12123_p1 = tmp_85_8_4_fu_11902_p2;
assign tmp_33_5_fu_12128_p1 = tmp_85_8_5_fu_11925_p2;
assign tmp_33_6_fu_12133_p1 = tmp_85_8_6_fu_11948_p2;
assign tmp_33_7_fu_12138_p1 = tmp_85_8_7_fu_11965_p2;
assign tmp_33_8_fu_12143_p1 = tmp_85_8_8_fu_11983_p2;
assign tmp_33_9_fu_12148_p1 = tmp_85_8_9_fu_12001_p2;
assign tmp_33_fu_12103_p1 = tmp_85_8_fu_11831_p2;
assign tmp_33_s_fu_12153_p1 = tmp_85_8_s_fu_12019_p2;
assign tmp_340_fu_10393_p3 = x_assign_3_7_1_fu_10381_p2[32'd7];
assign tmp_341_fu_10433_p2 = x_assign_7_2_fu_10415_p2 << 8'd1;
assign tmp_342_fu_10439_p3 = x_assign_7_2_fu_10415_p2[32'd7];
assign tmp_343_fu_10467_p2 = x_assign_1_7_2_fu_10461_p2 << 8'd1;
assign tmp_344_fu_10473_p3 = x_assign_1_7_2_fu_10461_p2[32'd7];
assign tmp_345_fu_10501_p2 = x_assign_2_7_2_fu_10495_p2 << 8'd1;
assign tmp_346_fu_10507_p3 = x_assign_2_7_2_fu_10495_p2[32'd7];
assign tmp_347_fu_10535_p2 = x_assign_3_7_2_fu_10529_p2 << 8'd1;
assign tmp_348_fu_10541_p3 = x_assign_3_7_2_fu_10529_p2[32'd7];
assign tmp_349_fu_10581_p2 = x_assign_7_3_fu_10563_p2 << 8'd1;
assign tmp_350_fu_10587_p3 = x_assign_7_3_fu_10563_p2[32'd7];
assign tmp_351_fu_10615_p2 = x_assign_1_7_3_fu_10609_p2 << 8'd1;
assign tmp_352_fu_10621_p3 = x_assign_1_7_3_fu_10609_p2[32'd7];
assign tmp_353_fu_10649_p2 = x_assign_2_7_3_fu_10643_p2 << 8'd1;
assign tmp_354_fu_10655_p3 = x_assign_2_7_3_fu_10643_p2[32'd7];
assign tmp_355_fu_10683_p2 = x_assign_3_7_3_fu_10677_p2 << 8'd1;
assign tmp_356_fu_10689_p3 = x_assign_3_7_3_fu_10677_p2[32'd7];
assign tmp_357_fu_11179_p2 = x_assign_8_fu_11161_p2 << 8'd1;
assign tmp_358_fu_11185_p3 = x_assign_8_fu_11161_p2[32'd7];
assign tmp_359_fu_11213_p2 = x_assign_1_8_fu_11207_p2 << 8'd1;
assign tmp_35_0_10_fu_2780_p1 = tmp_10_10_fu_2695_p2;
assign tmp_35_0_11_fu_2785_p1 = tmp_10_11_fu_2701_p2;
assign tmp_35_0_12_fu_2790_p1 = tmp_10_12_fu_2707_p2;
assign tmp_35_0_13_fu_2795_p1 = tmp_10_13_fu_2713_p2;
assign tmp_35_0_14_fu_2800_p1 = tmp_10_14_fu_2719_p2;
assign tmp_35_0_1_fu_2730_p1 = tmp_10_1_fu_2635_p2;
assign tmp_35_0_2_fu_2735_p1 = tmp_10_2_fu_2641_p2;
assign tmp_35_0_3_fu_2740_p1 = tmp_10_3_fu_2647_p2;
assign tmp_35_0_4_fu_2745_p1 = tmp_10_4_fu_2653_p2;
assign tmp_35_0_5_fu_2750_p1 = tmp_10_5_fu_2659_p2;
assign tmp_35_0_6_fu_2755_p1 = tmp_10_6_fu_2665_p2;
assign tmp_35_0_7_fu_2760_p1 = tmp_10_7_fu_2671_p2;
assign tmp_35_0_8_fu_2765_p1 = tmp_10_8_fu_2677_p2;
assign tmp_35_0_9_fu_2770_p1 = tmp_10_9_fu_2683_p2;
assign tmp_35_0_s_fu_2775_p1 = tmp_10_s_fu_2689_p2;
assign tmp_35_1_10_fu_3822_p1 = tmp_85_0_10_fu_3695_p2;
assign tmp_35_1_11_fu_3827_p1 = tmp_85_0_11_fu_3713_p2;
assign tmp_35_1_12_fu_3832_p1 = tmp_85_0_12_fu_3731_p2;
assign tmp_35_1_13_fu_3837_p1 = tmp_85_0_13_fu_3749_p2;
assign tmp_35_1_14_fu_3842_p1 = tmp_85_0_14_fu_3761_p2;
assign tmp_35_1_1_fu_3772_p1 = tmp_85_0_1_fu_3533_p2;
assign tmp_35_1_2_fu_3777_p1 = tmp_85_0_2_fu_3551_p2;
assign tmp_35_1_3_fu_3782_p1 = tmp_85_0_3_fu_3563_p2;
assign tmp_35_1_4_fu_3787_p1 = tmp_85_0_4_fu_3581_p2;
assign tmp_35_1_5_fu_3792_p1 = tmp_85_0_5_fu_3599_p2;
assign tmp_35_1_6_fu_3797_p1 = tmp_85_0_6_fu_3617_p2;
assign tmp_35_1_7_fu_3802_p1 = tmp_85_0_7_fu_3629_p2;
assign tmp_35_1_8_fu_3807_p1 = tmp_85_0_8_fu_3647_p2;
assign tmp_35_1_9_fu_3812_p1 = tmp_85_0_9_fu_3665_p2;
assign tmp_35_1_fu_3767_p1 = tmp_85_fu_3515_p2;
assign tmp_35_1_s_fu_3817_p1 = tmp_85_0_s_fu_3683_p2;
assign tmp_35_2_10_fu_4864_p1 = tmp_85_1_10_fu_4737_p2;
assign tmp_35_2_11_fu_4869_p1 = tmp_85_1_11_fu_4755_p2;
assign tmp_35_2_12_fu_4874_p1 = tmp_85_1_12_fu_4773_p2;
assign tmp_35_2_13_fu_4879_p1 = tmp_85_1_13_fu_4791_p2;
assign tmp_35_2_14_fu_4884_p1 = tmp_85_1_14_fu_4803_p2;
assign tmp_35_2_1_fu_4814_p1 = tmp_85_1_1_fu_4555_p2;
assign tmp_35_2_2_fu_4819_p1 = tmp_85_1_2_fu_4573_p2;
assign tmp_35_2_3_fu_4824_p1 = tmp_85_1_3_fu_4585_p2;
assign tmp_35_2_4_fu_4829_p1 = tmp_85_1_4_fu_4603_p2;
assign tmp_35_2_5_fu_4834_p1 = tmp_85_1_5_fu_4621_p2;
assign tmp_35_2_6_fu_4839_p1 = tmp_85_1_6_fu_4639_p2;
assign tmp_35_2_7_fu_4844_p1 = tmp_85_1_7_fu_4651_p2;
assign tmp_35_2_8_fu_4849_p1 = tmp_85_1_8_fu_4674_p2;
assign tmp_35_2_9_fu_4854_p1 = tmp_85_1_9_fu_4697_p2;
assign tmp_35_2_fu_4809_p1 = tmp_85_1_fu_4537_p2;
assign tmp_35_2_s_fu_4859_p1 = tmp_85_1_s_fu_4720_p2;
assign tmp_35_3_10_fu_5906_p1 = tmp_85_2_10_fu_5779_p2;
assign tmp_35_3_11_fu_5911_p1 = tmp_85_2_11_fu_5797_p2;
assign tmp_35_3_12_fu_5916_p1 = tmp_85_2_12_fu_5815_p2;
assign tmp_35_3_13_fu_5921_p1 = tmp_85_2_13_fu_5833_p2;
assign tmp_35_3_14_fu_5926_p1 = tmp_85_2_14_fu_5845_p2;
assign tmp_35_3_1_fu_5856_p1 = tmp_85_2_1_fu_5597_p2;
assign tmp_35_3_2_fu_5861_p1 = tmp_85_2_2_fu_5615_p2;
assign tmp_35_3_3_fu_5866_p1 = tmp_85_2_3_fu_5627_p2;
assign tmp_35_3_4_fu_5871_p1 = tmp_85_2_4_fu_5650_p2;
assign tmp_35_3_5_fu_5876_p1 = tmp_85_2_5_fu_5673_p2;
assign tmp_35_3_6_fu_5881_p1 = tmp_85_2_6_fu_5696_p2;
assign tmp_35_3_7_fu_5886_p1 = tmp_85_2_7_fu_5713_p2;
assign tmp_35_3_8_fu_5891_p1 = tmp_85_2_8_fu_5731_p2;
assign tmp_35_3_9_fu_5896_p1 = tmp_85_2_9_fu_5749_p2;
assign tmp_35_3_fu_5851_p1 = tmp_85_2_fu_5579_p2;
assign tmp_35_3_s_fu_5901_p1 = tmp_85_2_s_fu_5767_p2;
assign tmp_35_4_10_fu_6948_p1 = tmp_85_3_10_fu_6821_p2;
assign tmp_35_4_11_fu_6953_p1 = tmp_85_3_11_fu_6839_p2;
assign tmp_35_4_12_fu_6958_p1 = tmp_85_3_12_fu_6857_p2;
assign tmp_35_4_13_fu_6963_p1 = tmp_85_3_13_fu_6875_p2;
assign tmp_35_4_14_fu_6968_p1 = tmp_85_3_14_fu_6887_p2;
assign tmp_35_4_1_fu_6898_p1 = tmp_85_3_1_fu_6639_p2;
assign tmp_35_4_2_fu_6903_p1 = tmp_85_3_2_fu_6657_p2;
assign tmp_35_4_3_fu_6908_p1 = tmp_85_3_3_fu_6669_p2;
assign tmp_35_4_4_fu_6913_p1 = tmp_85_3_4_fu_6687_p2;
assign tmp_35_4_5_fu_6918_p1 = tmp_85_3_5_fu_6705_p2;
assign tmp_35_4_6_fu_6923_p1 = tmp_85_3_6_fu_6723_p2;
assign tmp_35_4_7_fu_6928_p1 = tmp_85_3_7_fu_6735_p2;
assign tmp_35_4_8_fu_6933_p1 = tmp_85_3_8_fu_6758_p2;
assign tmp_35_4_9_fu_6938_p1 = tmp_85_3_9_fu_6781_p2;
assign tmp_35_4_fu_6893_p1 = tmp_85_3_fu_6621_p2;
assign tmp_35_4_s_fu_6943_p1 = tmp_85_3_s_fu_6804_p2;
assign tmp_35_5_10_fu_7990_p1 = tmp_85_4_10_fu_7863_p2;
assign tmp_35_5_11_fu_7995_p1 = tmp_85_4_11_fu_7881_p2;
assign tmp_35_5_12_fu_8000_p1 = tmp_85_4_12_fu_7899_p2;
assign tmp_35_5_13_fu_8005_p1 = tmp_85_4_13_fu_7917_p2;
assign tmp_35_5_14_fu_8010_p1 = tmp_85_4_14_fu_7929_p2;
assign tmp_35_5_1_fu_7940_p1 = tmp_85_4_1_fu_7681_p2;
assign tmp_35_5_2_fu_7945_p1 = tmp_85_4_2_fu_7699_p2;
assign tmp_35_5_3_fu_7950_p1 = tmp_85_4_3_fu_7711_p2;
assign tmp_35_5_4_fu_7955_p1 = tmp_85_4_4_fu_7734_p2;
assign tmp_35_5_5_fu_7960_p1 = tmp_85_4_5_fu_7757_p2;
assign tmp_35_5_6_fu_7965_p1 = tmp_85_4_6_fu_7780_p2;
assign tmp_35_5_7_fu_7970_p1 = tmp_85_4_7_fu_7797_p2;
assign tmp_35_5_8_fu_7975_p1 = tmp_85_4_8_fu_7815_p2;
assign tmp_35_5_9_fu_7980_p1 = tmp_85_4_9_fu_7833_p2;
assign tmp_35_5_fu_7935_p1 = tmp_85_4_fu_7663_p2;
assign tmp_35_5_s_fu_7985_p1 = tmp_85_4_s_fu_7851_p2;
assign tmp_35_6_10_fu_9032_p1 = tmp_85_5_10_fu_8905_p2;
assign tmp_35_6_11_fu_9037_p1 = tmp_85_5_11_fu_8923_p2;
assign tmp_35_6_12_fu_9042_p1 = tmp_85_5_12_fu_8941_p2;
assign tmp_35_6_13_fu_9047_p1 = tmp_85_5_13_fu_8959_p2;
assign tmp_35_6_14_fu_9052_p1 = tmp_85_5_14_fu_8971_p2;
assign tmp_35_6_1_fu_8982_p1 = tmp_85_5_1_fu_8723_p2;
assign tmp_35_6_2_fu_8987_p1 = tmp_85_5_2_fu_8741_p2;
assign tmp_35_6_3_fu_8992_p1 = tmp_85_5_3_fu_8753_p2;
assign tmp_35_6_4_fu_8997_p1 = tmp_85_5_4_fu_8771_p2;
assign tmp_35_6_5_fu_9002_p1 = tmp_85_5_5_fu_8789_p2;
assign tmp_35_6_6_fu_9007_p1 = tmp_85_5_6_fu_8807_p2;
assign tmp_35_6_7_fu_9012_p1 = tmp_85_5_7_fu_8819_p2;
assign tmp_35_6_8_fu_9017_p1 = tmp_85_5_8_fu_8842_p2;
assign tmp_35_6_9_fu_9022_p1 = tmp_85_5_9_fu_8865_p2;
assign tmp_35_6_fu_8977_p1 = tmp_85_5_fu_8705_p2;
assign tmp_35_6_s_fu_9027_p1 = tmp_85_5_s_fu_8888_p2;
assign tmp_35_7_10_fu_10074_p1 = tmp_85_6_10_fu_9947_p2;
assign tmp_35_7_11_fu_10079_p1 = tmp_85_6_11_fu_9965_p2;
assign tmp_35_7_12_fu_10084_p1 = tmp_85_6_12_fu_9983_p2;
assign tmp_35_7_13_fu_10089_p1 = tmp_85_6_13_fu_10001_p2;
assign tmp_35_7_14_fu_10094_p1 = tmp_85_6_14_fu_10013_p2;
assign tmp_35_7_1_fu_10024_p1 = tmp_85_6_1_fu_9765_p2;
assign tmp_35_7_2_fu_10029_p1 = tmp_85_6_2_fu_9783_p2;
assign tmp_35_7_3_fu_10034_p1 = tmp_85_6_3_fu_9795_p2;
assign tmp_35_7_4_fu_10039_p1 = tmp_85_6_4_fu_9818_p2;
assign tmp_35_7_5_fu_10044_p1 = tmp_85_6_5_fu_9841_p2;
assign tmp_35_7_6_fu_10049_p1 = tmp_85_6_6_fu_9864_p2;
assign tmp_35_7_7_fu_10054_p1 = tmp_85_6_7_fu_9881_p2;
assign tmp_35_7_8_fu_10059_p1 = tmp_85_6_8_fu_9899_p2;
assign tmp_35_7_9_fu_10064_p1 = tmp_85_6_9_fu_9917_p2;
assign tmp_35_7_fu_10019_p1 = tmp_85_6_fu_9747_p2;
assign tmp_35_7_s_fu_10069_p1 = tmp_85_6_s_fu_9935_p2;
assign tmp_35_8_10_fu_11116_p1 = tmp_85_7_10_fu_10989_p2;
assign tmp_35_8_11_fu_11121_p1 = tmp_85_7_11_fu_11007_p2;
assign tmp_35_8_12_fu_11126_p1 = tmp_85_7_12_fu_11025_p2;
assign tmp_35_8_13_fu_11131_p1 = tmp_85_7_13_fu_11043_p2;
assign tmp_35_8_14_fu_11136_p1 = tmp_85_7_14_fu_11055_p2;
assign tmp_35_8_1_fu_11066_p1 = tmp_85_7_1_fu_10807_p2;
assign tmp_35_8_2_fu_11071_p1 = tmp_85_7_2_fu_10825_p2;
assign tmp_35_8_3_fu_11076_p1 = tmp_85_7_3_fu_10837_p2;
assign tmp_35_8_4_fu_11081_p1 = tmp_85_7_4_fu_10855_p2;
assign tmp_35_8_5_fu_11086_p1 = tmp_85_7_5_fu_10873_p2;
assign tmp_35_8_6_fu_11091_p1 = tmp_85_7_6_fu_10891_p2;
assign tmp_35_8_7_fu_11096_p1 = tmp_85_7_7_fu_10903_p2;
assign tmp_35_8_8_fu_11101_p1 = tmp_85_7_8_fu_10926_p2;
assign tmp_35_8_9_fu_11106_p1 = tmp_85_7_9_fu_10949_p2;
assign tmp_35_8_fu_11061_p1 = tmp_85_7_fu_10789_p2;
assign tmp_35_8_s_fu_11111_p1 = tmp_85_7_s_fu_10972_p2;
assign tmp_35_fu_2725_p1 = tmp_10_fu_2629_p2;
assign tmp_360_fu_11219_p3 = x_assign_1_8_fu_11207_p2[32'd7];
assign tmp_361_fu_11247_p2 = x_assign_2_8_fu_11241_p2 << 8'd1;
assign tmp_362_fu_11253_p3 = x_assign_2_8_fu_11241_p2[32'd7];
assign tmp_363_fu_11281_p2 = x_assign_3_8_fu_11275_p2 << 8'd1;
assign tmp_364_fu_11287_p3 = x_assign_3_8_fu_11275_p2[32'd7];
assign tmp_365_fu_11327_p2 = x_assign_8_1_fu_11309_p2 << 8'd1;
assign tmp_366_fu_11333_p3 = x_assign_8_1_fu_11309_p2[32'd7];
assign tmp_367_fu_11361_p2 = x_assign_1_8_1_fu_11355_p2 << 8'd1;
assign tmp_368_fu_11367_p3 = x_assign_1_8_1_fu_11355_p2[32'd7];
assign tmp_369_fu_11395_p2 = x_assign_2_8_1_fu_11389_p2 << 8'd1;
assign tmp_370_fu_11401_p3 = x_assign_2_8_1_fu_11389_p2[32'd7];
assign tmp_371_fu_11429_p2 = x_assign_3_8_1_fu_11423_p2 << 8'd1;
assign tmp_372_fu_11435_p3 = x_assign_3_8_1_fu_11423_p2[32'd7];
assign tmp_373_fu_11475_p2 = x_assign_8_2_fu_11457_p2 << 8'd1;
assign tmp_374_fu_11481_p3 = x_assign_8_2_fu_11457_p2[32'd7];
assign tmp_375_fu_11509_p2 = x_assign_1_8_2_fu_11503_p2 << 8'd1;
assign tmp_376_fu_11515_p3 = x_assign_1_8_2_fu_11503_p2[32'd7];
assign tmp_377_fu_11543_p2 = x_assign_2_8_2_fu_11537_p2 << 8'd1;
assign tmp_378_fu_11549_p3 = x_assign_2_8_2_fu_11537_p2[32'd7];
assign tmp_379_fu_11577_p2 = x_assign_3_8_2_fu_11571_p2 << 8'd1;
assign tmp_380_fu_11583_p3 = x_assign_3_8_2_fu_11571_p2[32'd7];
assign tmp_381_fu_11623_p2 = x_assign_8_3_fu_11605_p2 << 8'd1;
assign tmp_382_fu_11629_p3 = x_assign_8_3_fu_11605_p2[32'd7];
assign tmp_383_fu_11657_p2 = x_assign_1_8_3_fu_11651_p2 << 8'd1;
assign tmp_384_fu_11663_p3 = x_assign_1_8_3_fu_11651_p2[32'd7];
assign tmp_385_fu_11691_p2 = x_assign_2_8_3_fu_11685_p2 << 8'd1;
assign tmp_386_fu_11697_p3 = x_assign_2_8_3_fu_11685_p2[32'd7];
assign tmp_387_fu_11725_p2 = x_assign_3_8_3_fu_11719_p2 << 8'd1;
assign tmp_388_fu_11731_p3 = x_assign_3_8_3_fu_11719_p2[32'd7];
assign tmp_38_10_fu_12335_p2 = (tmp296_fu_12330_p2 ^ sboxes_q187);
assign tmp_38_11_fu_12346_p2 = (tmp297_fu_12341_p2 ^ sboxes_q192);
assign tmp_38_12_fu_12357_p2 = (tmp298_fu_12352_p2 ^ sboxes_q181);
assign tmp_38_13_fu_12368_p2 = (tmp299_fu_12363_p2 ^ sboxes_q186);
assign tmp_38_14_fu_12379_p2 = (tmp300_fu_12374_p2 ^ sboxes_q191);
assign tmp_38_1_fu_12245_p2 = (tmp290_fu_12240_p2 ^ sboxes_q197);
assign tmp_38_2_fu_12256_p2 = (tmp291_fu_12251_p2 ^ sboxes_q198);
assign tmp_38_3_fu_12267_p2 = (tmp292_fu_12262_p2 ^ sboxes_q199);
assign tmp_38_4_fu_12273_p2 = (sboxes_q184 ^ tmp_9_fu_12209_p2);
assign tmp_38_5_fu_12279_p2 = (sboxes_q189 ^ tmp_11_fu_12214_p2);
assign tmp_38_6_fu_12285_p2 = (sboxes_q194 ^ tmp_12_fu_12219_p2);
assign tmp_38_7_fu_12291_p2 = (sboxes_q183 ^ tmp_13_fu_12224_p2);
assign tmp_38_8_fu_12302_p2 = (tmp293_fu_12297_p2 ^ sboxes_q188);
assign tmp_38_9_fu_12313_p2 = (tmp294_fu_12308_p2 ^ sboxes_q193);
assign tmp_38_fu_12234_p2 = (tmp289_fu_12229_p2 ^ sboxes_q180);
assign tmp_38_s_fu_12324_p2 = (tmp295_fu_12319_p2 ^ sboxes_q182);
assign tmp_3_fu_12198_p1 = tmp_77_8_fu_11799_p2;
assign tmp_47_0_1_fu_2979_p2 = (sboxes_q14 ^ x_assign_0_1_fu_2973_p2);
assign tmp_47_0_2_fu_3127_p2 = (sboxes_q2 ^ x_assign_0_2_fu_3121_p2);
assign tmp_47_0_3_fu_3275_p2 = (sboxes_q6 ^ x_assign_0_3_fu_3269_p2);
assign tmp_47_1_1_fu_4021_p2 = (sboxes_q34 ^ x_assign_171_1_fu_4015_p2);
assign tmp_47_1_2_fu_4169_p2 = (sboxes_q22 ^ x_assign_171_2_fu_4163_p2);
assign tmp_47_1_3_fu_4317_p2 = (sboxes_q26 ^ x_assign_171_3_fu_4311_p2);
assign tmp_47_1_fu_3873_p2 = (sboxes_q30 ^ x_assign_s_fu_3867_p2);
assign tmp_47_2_1_fu_5063_p2 = (sboxes_q54 ^ x_assign_273_1_fu_5057_p2);
assign tmp_47_2_2_fu_5211_p2 = (sboxes_q42 ^ x_assign_273_2_fu_5205_p2);
assign tmp_47_2_3_fu_5359_p2 = (sboxes_q46 ^ x_assign_273_3_fu_5353_p2);
assign tmp_47_2_fu_4915_p2 = (sboxes_q50 ^ x_assign_9_fu_4909_p2);
assign tmp_47_3_1_fu_6105_p2 = (sboxes_q74 ^ x_assign_375_1_fu_6099_p2);
assign tmp_47_3_2_fu_6253_p2 = (sboxes_q62 ^ x_assign_375_2_fu_6247_p2);
assign tmp_47_3_3_fu_6401_p2 = (sboxes_q66 ^ x_assign_375_3_fu_6395_p2);
assign tmp_47_3_fu_5957_p2 = (sboxes_q70 ^ x_assign_10_fu_5951_p2);
assign tmp_47_4_1_fu_7147_p2 = (sboxes_q94 ^ x_assign_4_1_fu_7141_p2);
assign tmp_47_4_2_fu_7295_p2 = (sboxes_q82 ^ x_assign_4_2_fu_7289_p2);
assign tmp_47_4_3_fu_7443_p2 = (sboxes_q86 ^ x_assign_4_3_fu_7437_p2);
assign tmp_47_4_fu_6999_p2 = (sboxes_q90 ^ x_assign_4_fu_6993_p2);
assign tmp_47_5_1_fu_8189_p2 = (sboxes_q114 ^ x_assign_5_1_fu_8183_p2);
assign tmp_47_5_2_fu_8337_p2 = (sboxes_q102 ^ x_assign_5_2_fu_8331_p2);
assign tmp_47_5_3_fu_8485_p2 = (sboxes_q106 ^ x_assign_5_3_fu_8479_p2);
assign tmp_47_5_fu_8041_p2 = (sboxes_q110 ^ x_assign_5_fu_8035_p2);
assign tmp_47_6_1_fu_9231_p2 = (sboxes_q134 ^ x_assign_6_1_fu_9225_p2);
assign tmp_47_6_2_fu_9379_p2 = (sboxes_q122 ^ x_assign_6_2_fu_9373_p2);
assign tmp_47_6_3_fu_9527_p2 = (sboxes_q126 ^ x_assign_6_3_fu_9521_p2);
assign tmp_47_6_fu_9083_p2 = (sboxes_q130 ^ x_assign_6_fu_9077_p2);
assign tmp_47_7_1_fu_10273_p2 = (sboxes_q154 ^ x_assign_7_1_fu_10267_p2);
assign tmp_47_7_2_fu_10421_p2 = (sboxes_q142 ^ x_assign_7_2_fu_10415_p2);
assign tmp_47_7_3_fu_10569_p2 = (sboxes_q146 ^ x_assign_7_3_fu_10563_p2);
assign tmp_47_7_fu_10125_p2 = (sboxes_q150 ^ x_assign_7_fu_10119_p2);
assign tmp_47_8_1_fu_11315_p2 = (sboxes_q174 ^ x_assign_8_1_fu_11309_p2);
assign tmp_47_8_2_fu_11463_p2 = (sboxes_q162 ^ x_assign_8_2_fu_11457_p2);
assign tmp_47_8_3_fu_11611_p2 = (sboxes_q166 ^ x_assign_8_3_fu_11605_p2);
assign tmp_47_8_fu_11167_p2 = (sboxes_q170 ^ x_assign_8_fu_11161_p2);
assign tmp_47_fu_2831_p2 = (sboxes_q10 ^ x_assign_fu_2825_p2);
assign tmp_4_fu_12203_p2 = (sboxes_q196 ^ 8'd54);
assign tmp_60_1_fu_3847_p1 = tmp_78_fu_3488_p2;
assign tmp_60_2_fu_4889_p1 = tmp_78_1_fu_4510_p2;
assign tmp_60_3_fu_5931_p1 = tmp_78_2_fu_5552_p2;
assign tmp_60_4_fu_6973_p1 = tmp_78_3_fu_6594_p2;
assign tmp_60_5_fu_8015_p1 = tmp_78_4_fu_7636_p2;
assign tmp_60_6_fu_9057_p1 = tmp_78_5_fu_8678_p2;
assign tmp_60_7_fu_10099_p1 = tmp_78_6_fu_9720_p2;
assign tmp_60_8_fu_11141_p1 = tmp_78_7_fu_10762_p2;
assign tmp_60_fu_2805_p1 = p_Result_1_12_fu_2591_p4;
assign tmp_61_1_fu_3852_p1 = tmp_79_fu_3493_p2;
assign tmp_61_2_fu_4894_p1 = tmp_79_1_fu_4515_p2;
assign tmp_61_3_fu_5936_p1 = tmp_79_2_fu_5557_p2;
assign tmp_61_4_fu_6978_p1 = tmp_79_3_fu_6599_p2;
assign tmp_61_5_fu_8020_p1 = tmp_79_4_fu_7641_p2;
assign tmp_61_6_fu_9062_p1 = tmp_79_5_fu_8683_p2;
assign tmp_61_7_fu_10104_p1 = tmp_79_6_fu_9725_p2;
assign tmp_61_8_fu_11146_p1 = tmp_79_7_fu_10767_p2;
assign tmp_61_fu_2810_p1 = p_Result_1_13_fu_2611_p4;
assign tmp_62_1_fu_3857_p1 = tmp_80_fu_3498_p2;
assign tmp_62_2_fu_4899_p1 = tmp_80_1_fu_4520_p2;
assign tmp_62_3_fu_5941_p1 = tmp_80_2_fu_5562_p2;
assign tmp_62_4_fu_6983_p1 = tmp_80_3_fu_6604_p2;
assign tmp_62_5_fu_8025_p1 = tmp_80_4_fu_7646_p2;
assign tmp_62_6_fu_9067_p1 = tmp_80_5_fu_8688_p2;
assign tmp_62_7_fu_10109_p1 = tmp_80_6_fu_9730_p2;
assign tmp_62_8_fu_11151_p1 = tmp_80_7_fu_10772_p2;
assign tmp_62_fu_2815_p1 = tmp_100_fu_2625_p1;
assign tmp_63_1_fu_3862_p1 = tmp_77_fu_3483_p2;
assign tmp_63_2_fu_4904_p1 = tmp_77_1_fu_4505_p2;
assign tmp_63_3_fu_5946_p1 = tmp_77_2_fu_5547_p2;
assign tmp_63_4_fu_6988_p1 = tmp_77_3_fu_6589_p2;
assign tmp_63_5_fu_8030_p1 = tmp_77_4_fu_7631_p2;
assign tmp_63_6_fu_9072_p1 = tmp_77_5_fu_8673_p2;
assign tmp_63_7_fu_10114_p1 = tmp_77_6_fu_9715_p2;
assign tmp_63_8_fu_11156_p1 = tmp_77_7_fu_10757_p2;
assign tmp_63_fu_2820_p1 = p_Result_1_11_fu_2571_p4;
assign tmp_64_1_fu_4459_p2 = (sboxes_q36 ^ 8'd2);
assign tmp_64_3_fu_6543_p2 = (sboxes_q76 ^ 8'd8);
assign tmp_64_5_fu_8627_p2 = (sboxes_q116 ^ 8'd32);
assign tmp_64_7_fu_10711_p2 = (sboxes_q156 ^ 8'd128);
assign tmp_65_1_fu_4465_p2 = (tmp_64_1_fu_4459_p2 ^ tmp_65_reg_12613);
assign tmp_65_2_fu_5506_p2 = (tmp61_fu_5501_p2 ^ sboxes_q56);
assign tmp_65_3_fu_6549_p2 = (tmp_64_3_fu_6543_p2 ^ tmp_65_2_reg_12921);
assign tmp_65_4_fu_7590_p2 = (tmp126_fu_7585_p2 ^ sboxes_q96);
assign tmp_65_5_fu_8633_p2 = (tmp_64_5_fu_8627_p2 ^ tmp_65_4_reg_13237);
assign tmp_65_6_fu_9674_p2 = (tmp191_fu_9669_p2 ^ sboxes_q136);
assign tmp_65_7_fu_10717_p2 = (tmp_64_7_fu_10711_p2 ^ tmp_65_6_reg_13545);
assign tmp_65_8_fu_11758_p2 = (tmp256_fu_11753_p2 ^ sboxes_q176);
assign tmp_65_fu_3422_p2 = (tmp_fu_3417_p2 ^ sboxes_q16);
assign tmp_66_1_fu_4470_p2 = (sboxes_q37 ^ tmp_66_reg_12618);
assign tmp_66_2_fu_5512_p2 = (sboxes_q57 ^ tmp_66_1_reg_12762);
assign tmp_66_3_fu_6554_p2 = (sboxes_q77 ^ tmp_66_2_reg_12926);
assign tmp_66_4_fu_7596_p2 = (sboxes_q97 ^ tmp_66_3_reg_13070);
assign tmp_66_5_fu_8638_p2 = (sboxes_q117 ^ tmp_66_4_reg_13242);
assign tmp_66_6_fu_9680_p2 = (sboxes_q137 ^ tmp_66_5_reg_13386);
assign tmp_66_7_fu_10722_p2 = (sboxes_q157 ^ tmp_66_6_reg_13550);
assign tmp_66_8_fu_11764_p2 = (sboxes_q177 ^ tmp_66_7_reg_13694);
assign tmp_66_fu_3428_p2 = (sboxes_q17 ^ p_Result_1_1_reg_12426);
assign tmp_67_1_fu_4475_p2 = (sboxes_q38 ^ tmp_67_reg_12623);
assign tmp_67_2_fu_5517_p2 = (sboxes_q58 ^ tmp_67_1_reg_12767);
assign tmp_67_3_fu_6559_p2 = (sboxes_q78 ^ tmp_67_2_reg_12931);
assign tmp_67_4_fu_7601_p2 = (sboxes_q98 ^ tmp_67_3_reg_13075);
assign tmp_67_5_fu_8643_p2 = (sboxes_q118 ^ tmp_67_4_reg_13247);
assign tmp_67_6_fu_9685_p2 = (sboxes_q138 ^ tmp_67_5_reg_13391);
assign tmp_67_7_fu_10727_p2 = (sboxes_q158 ^ tmp_67_6_reg_13555);
assign tmp_67_8_fu_11769_p2 = (sboxes_q178 ^ tmp_67_7_reg_13699);
assign tmp_67_fu_3433_p2 = (sboxes_q18 ^ p_Result_1_2_reg_12431);
assign tmp_68_1_fu_4480_p2 = (sboxes_q39 ^ tmp_68_reg_12628);
assign tmp_68_2_fu_5522_p2 = (sboxes_q59 ^ tmp_68_1_reg_12772);
assign tmp_68_3_fu_6564_p2 = (sboxes_q79 ^ tmp_68_2_reg_12936);
assign tmp_68_4_fu_7606_p2 = (sboxes_q99 ^ tmp_68_3_reg_13080);
assign tmp_68_5_fu_8648_p2 = (sboxes_q119 ^ tmp_68_4_reg_13252);
assign tmp_68_6_fu_9690_p2 = (sboxes_q139 ^ tmp_68_5_reg_13396);
assign tmp_68_7_fu_10732_p2 = (sboxes_q159 ^ tmp_68_6_reg_13560);
assign tmp_68_8_fu_11774_p2 = (sboxes_q179 ^ tmp_68_7_reg_13704);
assign tmp_68_fu_3438_p2 = (sboxes_q19 ^ p_Result_1_3_reg_12436);
assign tmp_69_1_fu_4485_p2 = (ap_reg_pp0_iter1_p_Result_1_4_reg_12441 ^ tmp_64_1_fu_4459_p2);
assign tmp_69_3_fu_6569_p2 = (ap_reg_pp0_iter3_tmp_69_1_reg_12777 ^ tmp_64_3_fu_6543_p2);
assign tmp_69_5_fu_8653_p2 = (ap_reg_pp0_iter5_tmp_69_3_reg_13085 ^ tmp_64_5_fu_8627_p2);
assign tmp_69_7_fu_10737_p2 = (ap_reg_pp0_iter7_tmp_69_5_reg_13401 ^ tmp_64_7_fu_10711_p2);
assign tmp_69_fu_3443_p2 = (p_Result_1_4_reg_12441 ^ tmp_65_fu_3422_p2);
assign tmp_70_1_fu_4490_p2 = (sboxes_q37 ^ ap_reg_pp0_iter1_p_Result_1_5_reg_12447);
assign tmp_70_3_fu_6574_p2 = (sboxes_q77 ^ ap_reg_pp0_iter3_tmp_70_1_reg_12783);
assign tmp_70_5_fu_8658_p2 = (sboxes_q117 ^ ap_reg_pp0_iter5_tmp_70_3_reg_13091);
assign tmp_70_7_fu_10742_p2 = (sboxes_q157 ^ ap_reg_pp0_iter7_tmp_70_5_reg_13407);
assign tmp_70_fu_3448_p2 = (p_Result_1_5_reg_12447 ^ tmp_66_fu_3428_p2);
assign tmp_71_1_fu_4495_p2 = (sboxes_q38 ^ ap_reg_pp0_iter1_p_Result_1_6_reg_12453);
assign tmp_71_3_fu_6579_p2 = (sboxes_q78 ^ ap_reg_pp0_iter3_tmp_71_1_reg_12789);
assign tmp_71_5_fu_8663_p2 = (sboxes_q118 ^ ap_reg_pp0_iter5_tmp_71_3_reg_13097);
assign tmp_71_7_fu_10747_p2 = (sboxes_q158 ^ ap_reg_pp0_iter7_tmp_71_5_reg_13413);
assign tmp_71_fu_3453_p2 = (p_Result_1_6_reg_12453 ^ tmp_67_fu_3433_p2);
assign tmp_72_1_fu_4500_p2 = (sboxes_q39 ^ ap_reg_pp0_iter1_p_Result_1_7_reg_12459);
assign tmp_72_3_fu_6584_p2 = (sboxes_q79 ^ ap_reg_pp0_iter3_tmp_72_1_reg_12795);
assign tmp_72_5_fu_8668_p2 = (sboxes_q119 ^ ap_reg_pp0_iter5_tmp_72_3_reg_13103);
assign tmp_72_7_fu_10752_p2 = (sboxes_q159 ^ ap_reg_pp0_iter7_tmp_72_5_reg_13419);
assign tmp_72_fu_3458_p2 = (p_Result_1_7_reg_12459 ^ tmp_68_fu_3438_p2);
assign tmp_73_2_fu_5527_p2 = (ap_reg_pp0_iter2_tmp_73_reg_12633 ^ tmp_65_2_fu_5506_p2);
assign tmp_73_4_fu_7611_p2 = (ap_reg_pp0_iter4_tmp_73_2_reg_12941 ^ tmp_65_4_fu_7590_p2);
assign tmp_73_6_fu_9695_p2 = (ap_reg_pp0_iter6_tmp_73_4_reg_13257 ^ tmp_65_6_fu_9674_p2);
assign tmp_73_8_fu_11779_p2 = (ap_reg_pp0_iter8_tmp_73_6_reg_13565 ^ tmp_65_8_fu_11758_p2);
assign tmp_73_fu_3463_p2 = (p_Result_1_8_reg_12465 ^ tmp_69_fu_3443_p2);
assign tmp_74_2_fu_5532_p2 = (ap_reg_pp0_iter2_tmp_74_reg_12639 ^ tmp_66_2_fu_5512_p2);
assign tmp_74_4_fu_7616_p2 = (ap_reg_pp0_iter4_tmp_74_2_reg_12947 ^ tmp_66_4_fu_7596_p2);
assign tmp_74_6_fu_9700_p2 = (ap_reg_pp0_iter6_tmp_74_4_reg_13263 ^ tmp_66_6_fu_9680_p2);
assign tmp_74_8_fu_11784_p2 = (ap_reg_pp0_iter8_tmp_74_6_reg_13571 ^ tmp_66_8_fu_11764_p2);
assign tmp_74_fu_3468_p2 = (p_Result_1_9_reg_12470 ^ tmp_70_fu_3448_p2);
assign tmp_75_2_fu_5537_p2 = (ap_reg_pp0_iter2_tmp_75_reg_12645 ^ tmp_67_2_fu_5517_p2);
assign tmp_75_4_fu_7621_p2 = (ap_reg_pp0_iter4_tmp_75_2_reg_12953 ^ tmp_67_4_fu_7601_p2);
assign tmp_75_6_fu_9705_p2 = (ap_reg_pp0_iter6_tmp_75_4_reg_13269 ^ tmp_67_6_fu_9685_p2);
assign tmp_75_8_fu_11789_p2 = (ap_reg_pp0_iter8_tmp_75_6_reg_13577 ^ tmp_67_8_fu_11769_p2);
assign tmp_75_fu_3473_p2 = (p_Result_1_s_reg_12475 ^ tmp_71_fu_3453_p2);
assign tmp_76_2_fu_5542_p2 = (ap_reg_pp0_iter2_tmp_76_reg_12651 ^ tmp_68_2_fu_5522_p2);
assign tmp_76_4_fu_7626_p2 = (ap_reg_pp0_iter4_tmp_76_2_reg_12959 ^ tmp_68_4_fu_7606_p2);
assign tmp_76_6_fu_9710_p2 = (ap_reg_pp0_iter6_tmp_76_4_reg_13275 ^ tmp_68_6_fu_9690_p2);
assign tmp_76_8_fu_11794_p2 = (ap_reg_pp0_iter8_tmp_76_6_reg_13583 ^ tmp_68_8_fu_11774_p2);
assign tmp_76_fu_3478_p2 = (p_Result_1_10_reg_12480 ^ tmp_72_fu_3458_p2);
assign tmp_77_1_fu_4505_p2 = (tmp_69_1_fu_4485_p2 ^ ap_reg_pp0_iter1_p_Result_1_11_reg_12485);
assign tmp_77_2_fu_5547_p2 = (tmp_73_2_fu_5527_p2 ^ tmp_77_1_reg_12801);
assign tmp_77_3_fu_6589_p2 = (tmp_64_3_fu_6543_p2 ^ ap_reg_pp0_iter3_p_Result_1_11_reg_12485);
assign tmp_77_4_fu_7631_p2 = (tmp_73_4_fu_7611_p2 ^ tmp_77_3_reg_13109);
assign tmp_77_5_fu_8673_p2 = (tmp_69_5_fu_8653_p2 ^ ap_reg_pp0_iter5_tmp_77_3_reg_13109);
assign tmp_77_6_fu_9715_p2 = (tmp_73_6_fu_9695_p2 ^ tmp_77_5_reg_13425);
assign tmp_77_7_fu_10757_p2 = (tmp_64_7_fu_10711_p2 ^ ap_reg_pp0_iter7_tmp_77_3_reg_13109);
assign tmp_77_8_fu_11799_p2 = (tmp_73_8_fu_11779_p2 ^ tmp_77_7_reg_13733);
assign tmp_77_fu_3483_p2 = (tmp_73_fu_3463_p2 ^ p_Result_1_11_reg_12485);
assign tmp_78_1_fu_4510_p2 = (tmp_70_1_fu_4490_p2 ^ ap_reg_pp0_iter1_p_Result_1_12_reg_12492);
assign tmp_78_2_fu_5552_p2 = (tmp_74_2_fu_5532_p2 ^ tmp_78_1_reg_12806);
assign tmp_78_3_fu_6594_p2 = (sboxes_q77 ^ ap_reg_pp0_iter3_p_Result_1_12_reg_12492);
assign tmp_78_4_fu_7636_p2 = (tmp_74_4_fu_7616_p2 ^ tmp_78_3_reg_13116);
assign tmp_78_5_fu_8678_p2 = (tmp_70_5_fu_8658_p2 ^ ap_reg_pp0_iter5_tmp_78_3_reg_13116);
assign tmp_78_6_fu_9720_p2 = (tmp_74_6_fu_9700_p2 ^ tmp_78_5_reg_13430);
assign tmp_78_7_fu_10762_p2 = (sboxes_q157 ^ ap_reg_pp0_iter7_tmp_78_3_reg_13116);
assign tmp_78_8_fu_11804_p2 = (tmp_74_8_fu_11784_p2 ^ tmp_78_7_reg_13739);
assign tmp_78_fu_3488_p2 = (tmp_74_fu_3468_p2 ^ p_Result_1_12_reg_12492);
assign tmp_79_1_fu_4515_p2 = (tmp_71_1_fu_4495_p2 ^ ap_reg_pp0_iter1_p_Result_1_13_reg_12499);
assign tmp_79_2_fu_5557_p2 = (tmp_75_2_fu_5537_p2 ^ tmp_79_1_reg_12811);
assign tmp_79_3_fu_6599_p2 = (sboxes_q78 ^ ap_reg_pp0_iter3_p_Result_1_13_reg_12499);
assign tmp_79_4_fu_7641_p2 = (tmp_75_4_fu_7621_p2 ^ tmp_79_3_reg_13123);
assign tmp_79_5_fu_8683_p2 = (tmp_71_5_fu_8663_p2 ^ ap_reg_pp0_iter5_tmp_79_3_reg_13123);
assign tmp_79_6_fu_9725_p2 = (tmp_75_6_fu_9705_p2 ^ tmp_79_5_reg_13435);
assign tmp_79_7_fu_10767_p2 = (sboxes_q158 ^ ap_reg_pp0_iter7_tmp_79_3_reg_13123);
assign tmp_79_8_fu_11809_p2 = (tmp_75_8_fu_11789_p2 ^ tmp_79_7_reg_13745);
assign tmp_79_fu_3493_p2 = (tmp_75_fu_3473_p2 ^ p_Result_1_13_reg_12499);
assign tmp_80_1_fu_4520_p2 = (tmp_72_1_fu_4500_p2 ^ ap_reg_pp0_iter1_tmp_100_reg_12506);
assign tmp_80_2_fu_5562_p2 = (tmp_76_2_fu_5542_p2 ^ tmp_80_1_reg_12816);
assign tmp_80_3_fu_6604_p2 = (sboxes_q79 ^ ap_reg_pp0_iter3_tmp_100_reg_12506);
assign tmp_80_4_fu_7646_p2 = (tmp_76_4_fu_7626_p2 ^ tmp_80_3_reg_13130);
assign tmp_80_5_fu_8688_p2 = (tmp_72_5_fu_8668_p2 ^ ap_reg_pp0_iter5_tmp_80_3_reg_13130);
assign tmp_80_6_fu_9730_p2 = (tmp_76_6_fu_9710_p2 ^ tmp_80_5_reg_13440);
assign tmp_80_7_fu_10772_p2 = (sboxes_q159 ^ ap_reg_pp0_iter7_tmp_80_3_reg_13130);
assign tmp_80_8_fu_11814_p2 = (tmp_76_8_fu_11794_p2 ^ tmp_80_7_reg_13751);
assign tmp_80_fu_3498_p2 = (tmp_76_fu_3478_p2 ^ tmp_100_reg_12506);
assign tmp_85_0_10_fu_3695_p2 = (tmp21_fu_3689_p2 ^ rv_11_0_2_fu_3261_p3);
assign tmp_85_0_11_fu_3713_p2 = (tmp23_fu_3707_p2 ^ tmp22_fu_3701_p2);
assign tmp_85_0_12_fu_3731_p2 = (tmp25_fu_3725_p2 ^ tmp24_fu_3719_p2);
assign tmp_85_0_13_fu_3749_p2 = (tmp27_fu_3743_p2 ^ tmp26_fu_3737_p2);
assign tmp_85_0_14_fu_3761_p2 = (tmp28_fu_3755_p2 ^ rv_11_0_3_fu_3409_p3);
assign tmp_85_0_1_fu_3533_p2 = (tmp4_fu_3527_p2 ^ tmp3_fu_3521_p2);
assign tmp_85_0_2_fu_3551_p2 = (tmp6_fu_3545_p2 ^ tmp5_fu_3539_p2);
assign tmp_85_0_3_fu_3563_p2 = (tmp7_fu_3557_p2 ^ rv_3_fu_2965_p3);
assign tmp_85_0_4_fu_3581_p2 = (tmp9_fu_3575_p2 ^ tmp8_fu_3569_p2);
assign tmp_85_0_5_fu_3599_p2 = (tmp11_fu_3593_p2 ^ tmp10_fu_3587_p2);
assign tmp_85_0_6_fu_3617_p2 = (tmp13_fu_3611_p2 ^ tmp12_fu_3605_p2);
assign tmp_85_0_7_fu_3629_p2 = (tmp14_fu_3623_p2 ^ rv_11_0_1_fu_3113_p3);
assign tmp_85_0_8_fu_3647_p2 = (tmp16_fu_3641_p2 ^ tmp15_fu_3635_p2);
assign tmp_85_0_9_fu_3665_p2 = (tmp18_fu_3659_p2 ^ tmp17_fu_3653_p2);
assign tmp_85_0_s_fu_3683_p2 = (tmp20_fu_3677_p2 ^ tmp19_fu_3671_p2);
assign tmp_85_1_10_fu_4737_p2 = (tmp53_fu_4732_p2 ^ tmp52_fu_4726_p2);
assign tmp_85_1_11_fu_4755_p2 = (tmp55_fu_4749_p2 ^ tmp54_fu_4743_p2);
assign tmp_85_1_12_fu_4773_p2 = (tmp57_fu_4767_p2 ^ tmp56_fu_4761_p2);
assign tmp_85_1_13_fu_4791_p2 = (tmp59_fu_4785_p2 ^ tmp58_fu_4779_p2);
assign tmp_85_1_14_fu_4803_p2 = (tmp60_fu_4797_p2 ^ rv_11_1_3_fu_4451_p3);
assign tmp_85_1_1_fu_4555_p2 = (tmp32_fu_4549_p2 ^ tmp31_fu_4543_p2);
assign tmp_85_1_2_fu_4573_p2 = (tmp34_fu_4567_p2 ^ tmp33_fu_4561_p2);
assign tmp_85_1_3_fu_4585_p2 = (tmp35_fu_4579_p2 ^ rv_11_1_fu_4007_p3);
assign tmp_85_1_4_fu_4603_p2 = (tmp37_fu_4597_p2 ^ tmp36_fu_4591_p2);
assign tmp_85_1_5_fu_4621_p2 = (tmp39_fu_4615_p2 ^ tmp38_fu_4609_p2);
assign tmp_85_1_6_fu_4639_p2 = (tmp41_fu_4633_p2 ^ tmp40_fu_4627_p2);
assign tmp_85_1_7_fu_4651_p2 = (tmp42_fu_4645_p2 ^ rv_11_1_1_fu_4155_p3);
assign tmp_85_1_8_fu_4674_p2 = (tmp44_fu_4668_p2 ^ tmp43_fu_4657_p2);
assign tmp_85_1_9_fu_4697_p2 = (tmp47_fu_4691_p2 ^ tmp46_fu_4680_p2);
assign tmp_85_1_fu_4537_p2 = (tmp30_fu_4531_p2 ^ tmp29_fu_4525_p2);
assign tmp_85_1_s_fu_4720_p2 = (tmp50_fu_4714_p2 ^ tmp49_fu_4703_p2);
assign tmp_85_2_10_fu_5779_p2 = (tmp86_fu_5773_p2 ^ rv_11_2_2_fu_5345_p3);
assign tmp_85_2_11_fu_5797_p2 = (tmp88_fu_5791_p2 ^ tmp87_fu_5785_p2);
assign tmp_85_2_12_fu_5815_p2 = (tmp90_fu_5809_p2 ^ tmp89_fu_5803_p2);
assign tmp_85_2_13_fu_5833_p2 = (tmp92_fu_5827_p2 ^ tmp91_fu_5821_p2);
assign tmp_85_2_14_fu_5845_p2 = (tmp93_fu_5839_p2 ^ rv_11_2_3_fu_5493_p3);
assign tmp_85_2_1_fu_5597_p2 = (tmp65_fu_5591_p2 ^ tmp64_fu_5585_p2);
assign tmp_85_2_2_fu_5615_p2 = (tmp67_fu_5609_p2 ^ tmp66_fu_5603_p2);
assign tmp_85_2_3_fu_5627_p2 = (tmp68_fu_5621_p2 ^ rv_11_2_fu_5049_p3);
assign tmp_85_2_4_fu_5650_p2 = (tmp70_fu_5644_p2 ^ tmp69_fu_5633_p2);
assign tmp_85_2_5_fu_5673_p2 = (tmp73_fu_5667_p2 ^ tmp72_fu_5656_p2);
assign tmp_85_2_6_fu_5696_p2 = (tmp76_fu_5690_p2 ^ tmp75_fu_5679_p2);
assign tmp_85_2_7_fu_5713_p2 = (tmp79_fu_5708_p2 ^ tmp78_fu_5702_p2);
assign tmp_85_2_8_fu_5731_p2 = (tmp81_fu_5725_p2 ^ tmp80_fu_5719_p2);
assign tmp_85_2_9_fu_5749_p2 = (tmp83_fu_5743_p2 ^ tmp82_fu_5737_p2);
assign tmp_85_2_fu_5579_p2 = (tmp63_fu_5573_p2 ^ tmp62_fu_5567_p2);
assign tmp_85_2_s_fu_5767_p2 = (tmp85_fu_5761_p2 ^ tmp84_fu_5755_p2);
assign tmp_85_3_10_fu_6821_p2 = (tmp118_fu_6816_p2 ^ tmp117_fu_6810_p2);
assign tmp_85_3_11_fu_6839_p2 = (tmp120_fu_6833_p2 ^ tmp119_fu_6827_p2);
assign tmp_85_3_12_fu_6857_p2 = (tmp122_fu_6851_p2 ^ tmp121_fu_6845_p2);
assign tmp_85_3_13_fu_6875_p2 = (tmp124_fu_6869_p2 ^ tmp123_fu_6863_p2);
assign tmp_85_3_14_fu_6887_p2 = (tmp125_fu_6881_p2 ^ rv_11_3_3_fu_6535_p3);
assign tmp_85_3_1_fu_6639_p2 = (tmp97_fu_6633_p2 ^ tmp96_fu_6627_p2);
assign tmp_85_3_2_fu_6657_p2 = (tmp99_fu_6651_p2 ^ tmp98_fu_6645_p2);
assign tmp_85_3_3_fu_6669_p2 = (tmp100_fu_6663_p2 ^ rv_11_3_fu_6091_p3);
assign tmp_85_3_4_fu_6687_p2 = (tmp102_fu_6681_p2 ^ tmp101_fu_6675_p2);
assign tmp_85_3_5_fu_6705_p2 = (tmp104_fu_6699_p2 ^ tmp103_fu_6693_p2);
assign tmp_85_3_6_fu_6723_p2 = (tmp106_fu_6717_p2 ^ tmp105_fu_6711_p2);
assign tmp_85_3_7_fu_6735_p2 = (tmp107_fu_6729_p2 ^ rv_11_3_1_fu_6239_p3);
assign tmp_85_3_8_fu_6758_p2 = (tmp109_fu_6752_p2 ^ tmp108_fu_6741_p2);
assign tmp_85_3_9_fu_6781_p2 = (tmp112_fu_6775_p2 ^ tmp111_fu_6764_p2);
assign tmp_85_3_fu_6621_p2 = (tmp95_fu_6615_p2 ^ tmp94_fu_6609_p2);
assign tmp_85_3_s_fu_6804_p2 = (tmp115_fu_6798_p2 ^ tmp114_fu_6787_p2);
assign tmp_85_4_10_fu_7863_p2 = (tmp151_fu_7857_p2 ^ rv_11_4_2_fu_7429_p3);
assign tmp_85_4_11_fu_7881_p2 = (tmp153_fu_7875_p2 ^ tmp152_fu_7869_p2);
assign tmp_85_4_12_fu_7899_p2 = (tmp155_fu_7893_p2 ^ tmp154_fu_7887_p2);
assign tmp_85_4_13_fu_7917_p2 = (tmp157_fu_7911_p2 ^ tmp156_fu_7905_p2);
assign tmp_85_4_14_fu_7929_p2 = (tmp158_fu_7923_p2 ^ rv_11_4_3_fu_7577_p3);
assign tmp_85_4_1_fu_7681_p2 = (tmp130_fu_7675_p2 ^ tmp129_fu_7669_p2);
assign tmp_85_4_2_fu_7699_p2 = (tmp132_fu_7693_p2 ^ tmp131_fu_7687_p2);
assign tmp_85_4_3_fu_7711_p2 = (tmp133_fu_7705_p2 ^ rv_11_4_fu_7133_p3);
assign tmp_85_4_4_fu_7734_p2 = (tmp135_fu_7728_p2 ^ tmp134_fu_7717_p2);
assign tmp_85_4_5_fu_7757_p2 = (tmp138_fu_7751_p2 ^ tmp137_fu_7740_p2);
assign tmp_85_4_6_fu_7780_p2 = (tmp141_fu_7774_p2 ^ tmp140_fu_7763_p2);
assign tmp_85_4_7_fu_7797_p2 = (tmp144_fu_7792_p2 ^ tmp143_fu_7786_p2);
assign tmp_85_4_8_fu_7815_p2 = (tmp146_fu_7809_p2 ^ tmp145_fu_7803_p2);
assign tmp_85_4_9_fu_7833_p2 = (tmp148_fu_7827_p2 ^ tmp147_fu_7821_p2);
assign tmp_85_4_fu_7663_p2 = (tmp128_fu_7657_p2 ^ tmp127_fu_7651_p2);
assign tmp_85_4_s_fu_7851_p2 = (tmp150_fu_7845_p2 ^ tmp149_fu_7839_p2);
assign tmp_85_5_10_fu_8905_p2 = (tmp183_fu_8900_p2 ^ tmp182_fu_8894_p2);
assign tmp_85_5_11_fu_8923_p2 = (tmp185_fu_8917_p2 ^ tmp184_fu_8911_p2);
assign tmp_85_5_12_fu_8941_p2 = (tmp187_fu_8935_p2 ^ tmp186_fu_8929_p2);
assign tmp_85_5_13_fu_8959_p2 = (tmp189_fu_8953_p2 ^ tmp188_fu_8947_p2);
assign tmp_85_5_14_fu_8971_p2 = (tmp190_fu_8965_p2 ^ rv_11_5_3_fu_8619_p3);
assign tmp_85_5_1_fu_8723_p2 = (tmp162_fu_8717_p2 ^ tmp161_fu_8711_p2);
assign tmp_85_5_2_fu_8741_p2 = (tmp164_fu_8735_p2 ^ tmp163_fu_8729_p2);
assign tmp_85_5_3_fu_8753_p2 = (tmp165_fu_8747_p2 ^ rv_11_5_fu_8175_p3);
assign tmp_85_5_4_fu_8771_p2 = (tmp167_fu_8765_p2 ^ tmp166_fu_8759_p2);
assign tmp_85_5_5_fu_8789_p2 = (tmp169_fu_8783_p2 ^ tmp168_fu_8777_p2);
assign tmp_85_5_6_fu_8807_p2 = (tmp171_fu_8801_p2 ^ tmp170_fu_8795_p2);
assign tmp_85_5_7_fu_8819_p2 = (tmp172_fu_8813_p2 ^ rv_11_5_1_fu_8323_p3);
assign tmp_85_5_8_fu_8842_p2 = (tmp174_fu_8836_p2 ^ tmp173_fu_8825_p2);
assign tmp_85_5_9_fu_8865_p2 = (tmp177_fu_8859_p2 ^ tmp176_fu_8848_p2);
assign tmp_85_5_fu_8705_p2 = (tmp160_fu_8699_p2 ^ tmp159_fu_8693_p2);
assign tmp_85_5_s_fu_8888_p2 = (tmp180_fu_8882_p2 ^ tmp179_fu_8871_p2);
assign tmp_85_6_10_fu_9947_p2 = (tmp216_fu_9941_p2 ^ rv_11_6_2_fu_9513_p3);
assign tmp_85_6_11_fu_9965_p2 = (tmp218_fu_9959_p2 ^ tmp217_fu_9953_p2);
assign tmp_85_6_12_fu_9983_p2 = (tmp220_fu_9977_p2 ^ tmp219_fu_9971_p2);
assign tmp_85_6_13_fu_10001_p2 = (tmp222_fu_9995_p2 ^ tmp221_fu_9989_p2);
assign tmp_85_6_14_fu_10013_p2 = (tmp223_fu_10007_p2 ^ rv_11_6_3_fu_9661_p3);
assign tmp_85_6_1_fu_9765_p2 = (tmp195_fu_9759_p2 ^ tmp194_fu_9753_p2);
assign tmp_85_6_2_fu_9783_p2 = (tmp197_fu_9777_p2 ^ tmp196_fu_9771_p2);
assign tmp_85_6_3_fu_9795_p2 = (tmp198_fu_9789_p2 ^ rv_11_6_fu_9217_p3);
assign tmp_85_6_4_fu_9818_p2 = (tmp200_fu_9812_p2 ^ tmp199_fu_9801_p2);
assign tmp_85_6_5_fu_9841_p2 = (tmp203_fu_9835_p2 ^ tmp202_fu_9824_p2);
assign tmp_85_6_6_fu_9864_p2 = (tmp206_fu_9858_p2 ^ tmp205_fu_9847_p2);
assign tmp_85_6_7_fu_9881_p2 = (tmp209_fu_9876_p2 ^ tmp208_fu_9870_p2);
assign tmp_85_6_8_fu_9899_p2 = (tmp211_fu_9893_p2 ^ tmp210_fu_9887_p2);
assign tmp_85_6_9_fu_9917_p2 = (tmp213_fu_9911_p2 ^ tmp212_fu_9905_p2);
assign tmp_85_6_fu_9747_p2 = (tmp193_fu_9741_p2 ^ tmp192_fu_9735_p2);
assign tmp_85_6_s_fu_9935_p2 = (tmp215_fu_9929_p2 ^ tmp214_fu_9923_p2);
assign tmp_85_7_10_fu_10989_p2 = (tmp248_fu_10984_p2 ^ tmp247_fu_10978_p2);
assign tmp_85_7_11_fu_11007_p2 = (tmp250_fu_11001_p2 ^ tmp249_fu_10995_p2);
assign tmp_85_7_12_fu_11025_p2 = (tmp252_fu_11019_p2 ^ tmp251_fu_11013_p2);
assign tmp_85_7_13_fu_11043_p2 = (tmp254_fu_11037_p2 ^ tmp253_fu_11031_p2);
assign tmp_85_7_14_fu_11055_p2 = (tmp255_fu_11049_p2 ^ rv_11_7_3_fu_10703_p3);
assign tmp_85_7_1_fu_10807_p2 = (tmp227_fu_10801_p2 ^ tmp226_fu_10795_p2);
assign tmp_85_7_2_fu_10825_p2 = (tmp229_fu_10819_p2 ^ tmp228_fu_10813_p2);
assign tmp_85_7_3_fu_10837_p2 = (tmp230_fu_10831_p2 ^ rv_11_7_fu_10259_p3);
assign tmp_85_7_4_fu_10855_p2 = (tmp232_fu_10849_p2 ^ tmp231_fu_10843_p2);
assign tmp_85_7_5_fu_10873_p2 = (tmp234_fu_10867_p2 ^ tmp233_fu_10861_p2);
assign tmp_85_7_6_fu_10891_p2 = (tmp236_fu_10885_p2 ^ tmp235_fu_10879_p2);
assign tmp_85_7_7_fu_10903_p2 = (tmp237_fu_10897_p2 ^ rv_11_7_1_fu_10407_p3);
assign tmp_85_7_8_fu_10926_p2 = (tmp239_fu_10920_p2 ^ tmp238_fu_10909_p2);
assign tmp_85_7_9_fu_10949_p2 = (tmp242_fu_10943_p2 ^ tmp241_fu_10932_p2);
assign tmp_85_7_fu_10789_p2 = (tmp225_fu_10783_p2 ^ tmp224_fu_10777_p2);
assign tmp_85_7_s_fu_10972_p2 = (tmp245_fu_10966_p2 ^ tmp244_fu_10955_p2);
assign tmp_85_8_10_fu_12031_p2 = (tmp281_fu_12025_p2 ^ rv_11_8_2_fu_11597_p3);
assign tmp_85_8_11_fu_12049_p2 = (tmp283_fu_12043_p2 ^ tmp282_fu_12037_p2);
assign tmp_85_8_12_fu_12067_p2 = (tmp285_fu_12061_p2 ^ tmp284_fu_12055_p2);
assign tmp_85_8_13_fu_12085_p2 = (tmp287_fu_12079_p2 ^ tmp286_fu_12073_p2);
assign tmp_85_8_14_fu_12097_p2 = (tmp288_fu_12091_p2 ^ rv_11_8_3_fu_11745_p3);
assign tmp_85_8_1_fu_11849_p2 = (tmp260_fu_11843_p2 ^ tmp259_fu_11837_p2);
assign tmp_85_8_2_fu_11867_p2 = (tmp262_fu_11861_p2 ^ tmp261_fu_11855_p2);
assign tmp_85_8_3_fu_11879_p2 = (tmp263_fu_11873_p2 ^ rv_11_8_fu_11301_p3);
assign tmp_85_8_4_fu_11902_p2 = (tmp265_fu_11896_p2 ^ tmp264_fu_11885_p2);
assign tmp_85_8_5_fu_11925_p2 = (tmp268_fu_11919_p2 ^ tmp267_fu_11908_p2);
assign tmp_85_8_6_fu_11948_p2 = (tmp271_fu_11942_p2 ^ tmp270_fu_11931_p2);
assign tmp_85_8_7_fu_11965_p2 = (tmp274_fu_11960_p2 ^ tmp273_fu_11954_p2);
assign tmp_85_8_8_fu_11983_p2 = (tmp276_fu_11977_p2 ^ tmp275_fu_11971_p2);
assign tmp_85_8_9_fu_12001_p2 = (tmp278_fu_11995_p2 ^ tmp277_fu_11989_p2);
assign tmp_85_8_fu_11831_p2 = (tmp258_fu_11825_p2 ^ tmp257_fu_11819_p2);
assign tmp_85_8_s_fu_12019_p2 = (tmp280_fu_12013_p2 ^ tmp279_fu_12007_p2);
assign tmp_85_fu_3515_p2 = (tmp2_fu_3509_p2 ^ tmp1_fu_3503_p2);
assign tmp_99_fu_2621_p1 = inptext_V_read[7:0];
assign tmp_9_fu_12209_p2 = (ap_reg_pp0_iter9_tmp_69_7_reg_13709 ^ tmp_4_fu_12203_p2);
assign tmp_fu_3417_p2 = (p_Result_1_reg_12421 ^ 8'd1);
assign tmp_s_fu_12183_p1 = tmp_78_8_fu_11804_p2;
assign x_assign_0_1_fu_2973_p2 = (sboxes_q9 ^ sboxes_q4);
assign x_assign_0_2_fu_3121_p2 = (sboxes_q13 ^ sboxes_q8);
assign x_assign_0_3_fu_3269_p2 = (sboxes_q1 ^ sboxes_q12);
assign x_assign_10_fu_5951_p2 = (sboxes_q65 ^ sboxes_q60);
assign x_assign_171_1_fu_4015_p2 = (sboxes_q29 ^ sboxes_q24);
assign x_assign_171_2_fu_4163_p2 = (sboxes_q33 ^ sboxes_q28);
assign x_assign_171_3_fu_4311_p2 = (sboxes_q21 ^ sboxes_q32);
assign x_assign_1_0_1_fu_3019_p2 = (sboxes_q14 ^ sboxes_q9);
assign x_assign_1_0_2_fu_3167_p2 = (sboxes_q2 ^ sboxes_q13);
assign x_assign_1_0_3_fu_3315_p2 = (sboxes_q6 ^ sboxes_q1);
assign x_assign_1_1_1_fu_4061_p2 = (sboxes_q34 ^ sboxes_q29);
assign x_assign_1_1_2_fu_4209_p2 = (sboxes_q22 ^ sboxes_q33);
assign x_assign_1_1_3_fu_4357_p2 = (sboxes_q26 ^ sboxes_q21);
assign x_assign_1_1_fu_3913_p2 = (sboxes_q30 ^ sboxes_q25);
assign x_assign_1_2_1_fu_5103_p2 = (sboxes_q54 ^ sboxes_q49);
assign x_assign_1_2_2_fu_5251_p2 = (sboxes_q42 ^ sboxes_q53);
assign x_assign_1_2_3_fu_5399_p2 = (sboxes_q46 ^ sboxes_q41);
assign x_assign_1_2_fu_4955_p2 = (sboxes_q50 ^ sboxes_q45);
assign x_assign_1_3_1_fu_6145_p2 = (sboxes_q74 ^ sboxes_q69);
assign x_assign_1_3_2_fu_6293_p2 = (sboxes_q62 ^ sboxes_q73);
assign x_assign_1_3_3_fu_6441_p2 = (sboxes_q66 ^ sboxes_q61);
assign x_assign_1_3_fu_5997_p2 = (sboxes_q70 ^ sboxes_q65);
assign x_assign_1_4_1_fu_7187_p2 = (sboxes_q94 ^ sboxes_q89);
assign x_assign_1_4_2_fu_7335_p2 = (sboxes_q82 ^ sboxes_q93);
assign x_assign_1_4_3_fu_7483_p2 = (sboxes_q86 ^ sboxes_q81);
assign x_assign_1_4_fu_7039_p2 = (sboxes_q90 ^ sboxes_q85);
assign x_assign_1_5_1_fu_8229_p2 = (sboxes_q114 ^ sboxes_q109);
assign x_assign_1_5_2_fu_8377_p2 = (sboxes_q102 ^ sboxes_q113);
assign x_assign_1_5_3_fu_8525_p2 = (sboxes_q106 ^ sboxes_q101);
assign x_assign_1_5_fu_8081_p2 = (sboxes_q110 ^ sboxes_q105);
assign x_assign_1_6_1_fu_9271_p2 = (sboxes_q134 ^ sboxes_q129);
assign x_assign_1_6_2_fu_9419_p2 = (sboxes_q122 ^ sboxes_q133);
assign x_assign_1_6_3_fu_9567_p2 = (sboxes_q126 ^ sboxes_q121);
assign x_assign_1_6_fu_9123_p2 = (sboxes_q130 ^ sboxes_q125);
assign x_assign_1_7_1_fu_10313_p2 = (sboxes_q154 ^ sboxes_q149);
assign x_assign_1_7_2_fu_10461_p2 = (sboxes_q142 ^ sboxes_q153);
assign x_assign_1_7_3_fu_10609_p2 = (sboxes_q146 ^ sboxes_q141);
assign x_assign_1_7_fu_10165_p2 = (sboxes_q150 ^ sboxes_q145);
assign x_assign_1_8_1_fu_11355_p2 = (sboxes_q174 ^ sboxes_q169);
assign x_assign_1_8_2_fu_11503_p2 = (sboxes_q162 ^ sboxes_q173);
assign x_assign_1_8_3_fu_11651_p2 = (sboxes_q166 ^ sboxes_q161);
assign x_assign_1_8_fu_11207_p2 = (sboxes_q170 ^ sboxes_q165);
assign x_assign_1_fu_2871_p2 = (sboxes_q10 ^ sboxes_q5);
assign x_assign_273_1_fu_5057_p2 = (sboxes_q49 ^ sboxes_q44);
assign x_assign_273_2_fu_5205_p2 = (sboxes_q53 ^ sboxes_q48);
assign x_assign_273_3_fu_5353_p2 = (sboxes_q41 ^ sboxes_q52);
assign x_assign_2_0_1_fu_3053_p2 = (sboxes_q3 ^ sboxes_q14);
assign x_assign_2_0_2_fu_3201_p2 = (sboxes_q7 ^ sboxes_q2);
assign x_assign_2_0_3_fu_3349_p2 = (sboxes_q11 ^ sboxes_q6);
assign x_assign_2_1_1_fu_4095_p2 = (sboxes_q23 ^ sboxes_q34);
assign x_assign_2_1_2_fu_4243_p2 = (sboxes_q27 ^ sboxes_q22);
assign x_assign_2_1_3_fu_4391_p2 = (sboxes_q31 ^ sboxes_q26);
assign x_assign_2_1_fu_3947_p2 = (sboxes_q35 ^ sboxes_q30);
assign x_assign_2_2_1_fu_5137_p2 = (sboxes_q43 ^ sboxes_q54);
assign x_assign_2_2_2_fu_5285_p2 = (sboxes_q47 ^ sboxes_q42);
assign x_assign_2_2_3_fu_5433_p2 = (sboxes_q51 ^ sboxes_q46);
assign x_assign_2_2_fu_4989_p2 = (sboxes_q55 ^ sboxes_q50);
assign x_assign_2_3_1_fu_6179_p2 = (sboxes_q63 ^ sboxes_q74);
assign x_assign_2_3_2_fu_6327_p2 = (sboxes_q67 ^ sboxes_q62);
assign x_assign_2_3_3_fu_6475_p2 = (sboxes_q71 ^ sboxes_q66);
assign x_assign_2_3_fu_6031_p2 = (sboxes_q75 ^ sboxes_q70);
assign x_assign_2_4_1_fu_7221_p2 = (sboxes_q83 ^ sboxes_q94);
assign x_assign_2_4_2_fu_7369_p2 = (sboxes_q87 ^ sboxes_q82);
assign x_assign_2_4_3_fu_7517_p2 = (sboxes_q91 ^ sboxes_q86);
assign x_assign_2_4_fu_7073_p2 = (sboxes_q95 ^ sboxes_q90);
assign x_assign_2_5_1_fu_8263_p2 = (sboxes_q103 ^ sboxes_q114);
assign x_assign_2_5_2_fu_8411_p2 = (sboxes_q107 ^ sboxes_q102);
assign x_assign_2_5_3_fu_8559_p2 = (sboxes_q111 ^ sboxes_q106);
assign x_assign_2_5_fu_8115_p2 = (sboxes_q115 ^ sboxes_q110);
assign x_assign_2_6_1_fu_9305_p2 = (sboxes_q123 ^ sboxes_q134);
assign x_assign_2_6_2_fu_9453_p2 = (sboxes_q127 ^ sboxes_q122);
assign x_assign_2_6_3_fu_9601_p2 = (sboxes_q131 ^ sboxes_q126);
assign x_assign_2_6_fu_9157_p2 = (sboxes_q135 ^ sboxes_q130);
assign x_assign_2_7_1_fu_10347_p2 = (sboxes_q143 ^ sboxes_q154);
assign x_assign_2_7_2_fu_10495_p2 = (sboxes_q147 ^ sboxes_q142);
assign x_assign_2_7_3_fu_10643_p2 = (sboxes_q151 ^ sboxes_q146);
assign x_assign_2_7_fu_10199_p2 = (sboxes_q155 ^ sboxes_q150);
assign x_assign_2_8_1_fu_11389_p2 = (sboxes_q163 ^ sboxes_q174);
assign x_assign_2_8_2_fu_11537_p2 = (sboxes_q167 ^ sboxes_q162);
assign x_assign_2_8_3_fu_11685_p2 = (sboxes_q171 ^ sboxes_q166);
assign x_assign_2_8_fu_11241_p2 = (sboxes_q175 ^ sboxes_q170);
assign x_assign_2_fu_2905_p2 = (sboxes_q15 ^ sboxes_q10);
assign x_assign_375_1_fu_6099_p2 = (sboxes_q69 ^ sboxes_q64);
assign x_assign_375_2_fu_6247_p2 = (sboxes_q73 ^ sboxes_q68);
assign x_assign_375_3_fu_6395_p2 = (sboxes_q61 ^ sboxes_q72);
assign x_assign_3_0_1_fu_3087_p2 = (sboxes_q3 ^ sboxes_q4);
assign x_assign_3_0_2_fu_3235_p2 = (sboxes_q7 ^ sboxes_q8);
assign x_assign_3_0_3_fu_3383_p2 = (sboxes_q11 ^ sboxes_q12);
assign x_assign_3_1_1_fu_4129_p2 = (sboxes_q23 ^ sboxes_q24);
assign x_assign_3_1_2_fu_4277_p2 = (sboxes_q27 ^ sboxes_q28);
assign x_assign_3_1_3_fu_4425_p2 = (sboxes_q31 ^ sboxes_q32);
assign x_assign_3_1_fu_3981_p2 = (sboxes_q35 ^ sboxes_q20);
assign x_assign_3_2_1_fu_5171_p2 = (sboxes_q43 ^ sboxes_q44);
assign x_assign_3_2_2_fu_5319_p2 = (sboxes_q47 ^ sboxes_q48);
assign x_assign_3_2_3_fu_5467_p2 = (sboxes_q51 ^ sboxes_q52);
assign x_assign_3_2_fu_5023_p2 = (sboxes_q55 ^ sboxes_q40);
assign x_assign_3_3_1_fu_6213_p2 = (sboxes_q63 ^ sboxes_q64);
assign x_assign_3_3_2_fu_6361_p2 = (sboxes_q67 ^ sboxes_q68);
assign x_assign_3_3_3_fu_6509_p2 = (sboxes_q71 ^ sboxes_q72);
assign x_assign_3_3_fu_6065_p2 = (sboxes_q75 ^ sboxes_q60);
assign x_assign_3_4_1_fu_7255_p2 = (sboxes_q83 ^ sboxes_q84);
assign x_assign_3_4_2_fu_7403_p2 = (sboxes_q87 ^ sboxes_q88);
assign x_assign_3_4_3_fu_7551_p2 = (sboxes_q91 ^ sboxes_q92);
assign x_assign_3_4_fu_7107_p2 = (sboxes_q95 ^ sboxes_q80);
assign x_assign_3_5_1_fu_8297_p2 = (sboxes_q103 ^ sboxes_q104);
assign x_assign_3_5_2_fu_8445_p2 = (sboxes_q107 ^ sboxes_q108);
assign x_assign_3_5_3_fu_8593_p2 = (sboxes_q111 ^ sboxes_q112);
assign x_assign_3_5_fu_8149_p2 = (sboxes_q115 ^ sboxes_q100);
assign x_assign_3_6_1_fu_9339_p2 = (sboxes_q123 ^ sboxes_q124);
assign x_assign_3_6_2_fu_9487_p2 = (sboxes_q127 ^ sboxes_q128);
assign x_assign_3_6_3_fu_9635_p2 = (sboxes_q131 ^ sboxes_q132);
assign x_assign_3_6_fu_9191_p2 = (sboxes_q135 ^ sboxes_q120);
assign x_assign_3_7_1_fu_10381_p2 = (sboxes_q143 ^ sboxes_q144);
assign x_assign_3_7_2_fu_10529_p2 = (sboxes_q147 ^ sboxes_q148);
assign x_assign_3_7_3_fu_10677_p2 = (sboxes_q151 ^ sboxes_q152);
assign x_assign_3_7_fu_10233_p2 = (sboxes_q155 ^ sboxes_q140);
assign x_assign_3_8_1_fu_11423_p2 = (sboxes_q163 ^ sboxes_q164);
assign x_assign_3_8_2_fu_11571_p2 = (sboxes_q167 ^ sboxes_q168);
assign x_assign_3_8_3_fu_11719_p2 = (sboxes_q171 ^ sboxes_q172);
assign x_assign_3_8_fu_11275_p2 = (sboxes_q175 ^ sboxes_q160);
assign x_assign_3_fu_2939_p2 = (sboxes_q15 ^ sboxes_q0);
assign x_assign_4_1_fu_7141_p2 = (sboxes_q89 ^ sboxes_q84);
assign x_assign_4_2_fu_7289_p2 = (sboxes_q93 ^ sboxes_q88);
assign x_assign_4_3_fu_7437_p2 = (sboxes_q81 ^ sboxes_q92);
assign x_assign_4_fu_6993_p2 = (sboxes_q85 ^ sboxes_q80);
assign x_assign_5_1_fu_8183_p2 = (sboxes_q109 ^ sboxes_q104);
assign x_assign_5_2_fu_8331_p2 = (sboxes_q113 ^ sboxes_q108);
assign x_assign_5_3_fu_8479_p2 = (sboxes_q101 ^ sboxes_q112);
assign x_assign_5_fu_8035_p2 = (sboxes_q105 ^ sboxes_q100);
assign x_assign_6_1_fu_9225_p2 = (sboxes_q129 ^ sboxes_q124);
assign x_assign_6_2_fu_9373_p2 = (sboxes_q133 ^ sboxes_q128);
assign x_assign_6_3_fu_9521_p2 = (sboxes_q121 ^ sboxes_q132);
assign x_assign_6_fu_9077_p2 = (sboxes_q125 ^ sboxes_q120);
assign x_assign_7_1_fu_10267_p2 = (sboxes_q149 ^ sboxes_q144);
assign x_assign_7_2_fu_10415_p2 = (sboxes_q153 ^ sboxes_q148);
assign x_assign_7_3_fu_10563_p2 = (sboxes_q141 ^ sboxes_q152);
assign x_assign_7_fu_10119_p2 = (sboxes_q145 ^ sboxes_q140);
assign x_assign_8_1_fu_11309_p2 = (sboxes_q169 ^ sboxes_q164);
assign x_assign_8_2_fu_11457_p2 = (sboxes_q173 ^ sboxes_q168);
assign x_assign_8_3_fu_11605_p2 = (sboxes_q161 ^ sboxes_q172);
assign x_assign_8_fu_11161_p2 = (sboxes_q165 ^ sboxes_q160);
assign x_assign_9_fu_4909_p2 = (sboxes_q45 ^ sboxes_q40);
assign x_assign_fu_2825_p2 = (sboxes_q5 ^ sboxes_q0);
assign x_assign_s_fu_3867_p2 = (sboxes_q25 ^ sboxes_q20);
endmodule //aestest
|
`timescale 1 ns / 1 ps
`include "AXIOutputRegisters_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module AXIOutputRegisters_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
task automatic COMPARE_LITE_DATA;
input expected;
input actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_CPU_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altmult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.intended_device_family = "CYCLONEIVGX",
the_altmult_add_part_1.lpm_type = "altmult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altmult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.intended_device_family = "CYCLONEIVGX",
the_altmult_add_part_2.lpm_type = "altmult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.92
// \ \ Application : MIG
// / / Filename : nkmd_ddr3 #.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:09 $
// \ \ / \ Date Created : Tue Feb 23 2010
// \___\/\___\
//
//Device : Spartan-6
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : This is a template file for the design top module. This module contains
// all the four memory controllers and the two infrastructures. However,
// only the enabled modules will be active and others inactive.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ns/1ps
(* X_CORE_INFO = "mig_v3_92_ddr3_ddr3_ddr3_ddr3_s6, Coregen 14.7" , CORE_GENERATION_INFO = "ddr3_ddr3_ddr3_ddr3_s6,mig_v3_92,{component_name=nkmd_ddr3, C1_MEM_INTERFACE_TYPE=DDR3_SDRAM, C1_CLK_PERIOD=3000, C1_MEMORY_PART=mt41j64m16xx-187e, C1_MEMORY_DEVICE_WIDTH=16, C1_OUTPUT_DRV=DIV6, C1_RTT_NOM=DIV4, C1_AUTO_SR=ENABLED, C1_HIGH_TEMP_SR=NORMAL, C1_PORT_CONFIG=Four 32-bit bi-directional ports, C1_MEM_ADDR_ORDER=ROW_BANK_COLUMN, C1_PORT_ENABLE=Port0_Port1_Port2_Port3, C1_INPUT_PIN_TERMINATION=CALIB_TERM, C1_DATA_TERMINATION=25 Ohms, C1_CLKFBOUT_MULT_F=2, C1_CLKOUT_DIVIDE=1, C1_DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended,C3_MEM_INTERFACE_TYPE=DDR3_SDRAM, C3_CLK_PERIOD=3000, C3_MEMORY_PART=mt41j64m16xx-187e, C3_MEMORY_DEVICE_WIDTH=16, C3_OUTPUT_DRV=DIV6, C3_RTT_NOM=DIV4, C3_AUTO_SR=ENABLED, C3_HIGH_TEMP_SR=NORMAL, C3_PORT_CONFIG=Four 32-bit bi-directional ports, C3_MEM_ADDR_ORDER=ROW_BANK_COLUMN, C3_PORT_ENABLE=Port0_Port1_Port2_Port3, C3_INPUT_PIN_TERMINATION=CALIB_TERM, C3_DATA_TERMINATION=25 Ohms, C3_CLKFBOUT_MULT_F=2, C3_CLKOUT_DIVIDE=1, C3_DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended, LANGUAGE=Verilog, SYNTHESIS_TOOL=Foundation_ISE, NO_OF_CONTROLLERS=2}" *)
module nkmd_ddr3 #
(
parameter C1_P0_MASK_SIZE = 4,
parameter C1_P0_DATA_PORT_SIZE = 32,
parameter C1_P1_MASK_SIZE = 4,
parameter C1_P1_DATA_PORT_SIZE = 32,
parameter DEBUG_EN = 0,
// # = 1, Enable debug signals/controls,
// = 0, Disable debug signals/controls.
parameter C1_MEMCLK_PERIOD = 3000,
// Memory data transfer clock period
parameter C1_CALIB_SOFT_IP = "TRUE",
// # = TRUE, Enables the soft calibration logic,
// # = FALSE, Disables the soft calibration logic.
parameter C1_SIMULATION = "FALSE",
// # = TRUE, Simulating the design. Useful to reduce the simulation time,
// # = FALSE, Implementing the design.
parameter C1_RST_ACT_LOW = 0,
// # = 1 for active low reset,
// # = 0 for active high reset.
parameter C1_INPUT_CLK_TYPE = "SINGLE_ENDED",
// input clock type DIFFERENTIAL or SINGLE_ENDED
parameter C1_MEM_ADDR_ORDER = "ROW_BANK_COLUMN",
// The order in which user address is provided to the memory controller,
// ROW_BANK_COLUMN or BANK_ROW_COLUMN
parameter C1_NUM_DQ_PINS = 16,
// External memory data width
parameter C1_MEM_ADDR_WIDTH = 13,
// External memory address width
parameter C1_MEM_BANKADDR_WIDTH = 3,
// External memory bank address width
parameter C3_P0_MASK_SIZE = 4,
parameter C3_P0_DATA_PORT_SIZE = 32,
parameter C3_P1_MASK_SIZE = 4,
parameter C3_P1_DATA_PORT_SIZE = 32,
parameter C3_MEMCLK_PERIOD = 3000,
// Memory data transfer clock period
parameter C3_CALIB_SOFT_IP = "TRUE",
// # = TRUE, Enables the soft calibration logic,
// # = FALSE, Disables the soft calibration logic.
parameter C3_SIMULATION = "FALSE",
// # = TRUE, Simulating the design. Useful to reduce the simulation time,
// # = FALSE, Implementing the design.
parameter C3_RST_ACT_LOW = 0,
// # = 1 for active low reset,
// # = 0 for active high reset.
parameter C3_INPUT_CLK_TYPE = "SINGLE_ENDED",
// input clock type DIFFERENTIAL or SINGLE_ENDED
parameter C3_MEM_ADDR_ORDER = "ROW_BANK_COLUMN",
// The order in which user address is provided to the memory controller,
// ROW_BANK_COLUMN or BANK_ROW_COLUMN
parameter C3_NUM_DQ_PINS = 16,
// External memory data width
parameter C3_MEM_ADDR_WIDTH = 13,
// External memory address width
parameter C3_MEM_BANKADDR_WIDTH = 3
// External memory bank address width
)
(
inout [C1_NUM_DQ_PINS-1:0] mcb1_dram_dq,
output [C1_MEM_ADDR_WIDTH-1:0] mcb1_dram_a,
output [C1_MEM_BANKADDR_WIDTH-1:0] mcb1_dram_ba,
output mcb1_dram_ras_n,
output mcb1_dram_cas_n,
output mcb1_dram_we_n,
output mcb1_dram_odt,
output mcb1_dram_reset_n,
output mcb1_dram_cke,
output mcb1_dram_dm,
inout mcb1_dram_udqs,
inout mcb1_dram_udqs_n,
inout mcb1_rzq,
inout mcb1_zio,
output mcb1_dram_udm,
input c1_sys_clk,
input c1_sys_rst_i,
output c1_calib_done,
output c1_clk0,
output c1_rst0,
inout mcb1_dram_dqs,
inout mcb1_dram_dqs_n,
output mcb1_dram_ck,
output mcb1_dram_ck_n,
inout [C3_NUM_DQ_PINS-1:0] mcb3_dram_dq,
output [C3_MEM_ADDR_WIDTH-1:0] mcb3_dram_a,
output [C3_MEM_BANKADDR_WIDTH-1:0] mcb3_dram_ba,
output mcb3_dram_ras_n,
output mcb3_dram_cas_n,
output mcb3_dram_we_n,
output mcb3_dram_odt,
output mcb3_dram_reset_n,
output mcb3_dram_cke,
output mcb3_dram_dm,
inout mcb3_dram_udqs,
inout mcb3_dram_udqs_n,
inout mcb3_rzq,
inout mcb3_zio,
output mcb3_dram_udm,
input c3_sys_clk,
input c3_sys_rst_i,
output c3_calib_done,
output c3_clk0,
output c3_rst0,
inout mcb3_dram_dqs,
inout mcb3_dram_dqs_n,
output mcb3_dram_ck,
output mcb3_dram_ck_n,
input c1_p0_cmd_clk,
input c1_p0_cmd_en,
input [2:0] c1_p0_cmd_instr,
input [5:0] c1_p0_cmd_bl,
input [29:0] c1_p0_cmd_byte_addr,
output c1_p0_cmd_empty,
output c1_p0_cmd_full,
input c1_p0_wr_clk,
input c1_p0_wr_en,
input [C1_P0_MASK_SIZE - 1:0] c1_p0_wr_mask,
input [C1_P0_DATA_PORT_SIZE - 1:0] c1_p0_wr_data,
output c1_p0_wr_full,
output c1_p0_wr_empty,
output [6:0] c1_p0_wr_count,
output c1_p0_wr_underrun,
output c1_p0_wr_error,
input c1_p0_rd_clk,
input c1_p0_rd_en,
output [C1_P0_DATA_PORT_SIZE - 1:0] c1_p0_rd_data,
output c1_p0_rd_full,
output c1_p0_rd_empty,
output [6:0] c1_p0_rd_count,
output c1_p0_rd_overflow,
output c1_p0_rd_error,
input c1_p1_cmd_clk,
input c1_p1_cmd_en,
input [2:0] c1_p1_cmd_instr,
input [5:0] c1_p1_cmd_bl,
input [29:0] c1_p1_cmd_byte_addr,
output c1_p1_cmd_empty,
output c1_p1_cmd_full,
input c1_p1_wr_clk,
input c1_p1_wr_en,
input [C1_P1_MASK_SIZE - 1:0] c1_p1_wr_mask,
input [C1_P1_DATA_PORT_SIZE - 1:0] c1_p1_wr_data,
output c1_p1_wr_full,
output c1_p1_wr_empty,
output [6:0] c1_p1_wr_count,
output c1_p1_wr_underrun,
output c1_p1_wr_error,
input c1_p1_rd_clk,
input c1_p1_rd_en,
output [C1_P1_DATA_PORT_SIZE - 1:0] c1_p1_rd_data,
output c1_p1_rd_full,
output c1_p1_rd_empty,
output [6:0] c1_p1_rd_count,
output c1_p1_rd_overflow,
output c1_p1_rd_error,
input c1_p2_cmd_clk,
input c1_p2_cmd_en,
input [2:0] c1_p2_cmd_instr,
input [5:0] c1_p2_cmd_bl,
input [29:0] c1_p2_cmd_byte_addr,
output c1_p2_cmd_empty,
output c1_p2_cmd_full,
input c1_p2_wr_clk,
input c1_p2_wr_en,
input [3:0] c1_p2_wr_mask,
input [31:0] c1_p2_wr_data,
output c1_p2_wr_full,
output c1_p2_wr_empty,
output [6:0] c1_p2_wr_count,
output c1_p2_wr_underrun,
output c1_p2_wr_error,
input c1_p2_rd_clk,
input c1_p2_rd_en,
output [31:0] c1_p2_rd_data,
output c1_p2_rd_full,
output c1_p2_rd_empty,
output [6:0] c1_p2_rd_count,
output c1_p2_rd_overflow,
output c1_p2_rd_error,
input c1_p3_cmd_clk,
input c1_p3_cmd_en,
input [2:0] c1_p3_cmd_instr,
input [5:0] c1_p3_cmd_bl,
input [29:0] c1_p3_cmd_byte_addr,
output c1_p3_cmd_empty,
output c1_p3_cmd_full,
input c1_p3_wr_clk,
input c1_p3_wr_en,
input [3:0] c1_p3_wr_mask,
input [31:0] c1_p3_wr_data,
output c1_p3_wr_full,
output c1_p3_wr_empty,
output [6:0] c1_p3_wr_count,
output c1_p3_wr_underrun,
output c1_p3_wr_error,
input c1_p3_rd_clk,
input c1_p3_rd_en,
output [31:0] c1_p3_rd_data,
output c1_p3_rd_full,
output c1_p3_rd_empty,
output [6:0] c1_p3_rd_count,
output c1_p3_rd_overflow,
output c1_p3_rd_error,
input c3_p0_cmd_clk,
input c3_p0_cmd_en,
input [2:0] c3_p0_cmd_instr,
input [5:0] c3_p0_cmd_bl,
input [29:0] c3_p0_cmd_byte_addr,
output c3_p0_cmd_empty,
output c3_p0_cmd_full,
input c3_p0_wr_clk,
input c3_p0_wr_en,
input [C3_P0_MASK_SIZE - 1:0] c3_p0_wr_mask,
input [C3_P0_DATA_PORT_SIZE - 1:0] c3_p0_wr_data,
output c3_p0_wr_full,
output c3_p0_wr_empty,
output [6:0] c3_p0_wr_count,
output c3_p0_wr_underrun,
output c3_p0_wr_error,
input c3_p0_rd_clk,
input c3_p0_rd_en,
output [C3_P0_DATA_PORT_SIZE - 1:0] c3_p0_rd_data,
output c3_p0_rd_full,
output c3_p0_rd_empty,
output [6:0] c3_p0_rd_count,
output c3_p0_rd_overflow,
output c3_p0_rd_error,
input c3_p1_cmd_clk,
input c3_p1_cmd_en,
input [2:0] c3_p1_cmd_instr,
input [5:0] c3_p1_cmd_bl,
input [29:0] c3_p1_cmd_byte_addr,
output c3_p1_cmd_empty,
output c3_p1_cmd_full,
input c3_p1_wr_clk,
input c3_p1_wr_en,
input [C3_P1_MASK_SIZE - 1:0] c3_p1_wr_mask,
input [C3_P1_DATA_PORT_SIZE - 1:0] c3_p1_wr_data,
output c3_p1_wr_full,
output c3_p1_wr_empty,
output [6:0] c3_p1_wr_count,
output c3_p1_wr_underrun,
output c3_p1_wr_error,
input c3_p1_rd_clk,
input c3_p1_rd_en,
output [C3_P1_DATA_PORT_SIZE - 1:0] c3_p1_rd_data,
output c3_p1_rd_full,
output c3_p1_rd_empty,
output [6:0] c3_p1_rd_count,
output c3_p1_rd_overflow,
output c3_p1_rd_error,
input c3_p2_cmd_clk,
input c3_p2_cmd_en,
input [2:0] c3_p2_cmd_instr,
input [5:0] c3_p2_cmd_bl,
input [29:0] c3_p2_cmd_byte_addr,
output c3_p2_cmd_empty,
output c3_p2_cmd_full,
input c3_p2_wr_clk,
input c3_p2_wr_en,
input [3:0] c3_p2_wr_mask,
input [31:0] c3_p2_wr_data,
output c3_p2_wr_full,
output c3_p2_wr_empty,
output [6:0] c3_p2_wr_count,
output c3_p2_wr_underrun,
output c3_p2_wr_error,
input c3_p2_rd_clk,
input c3_p2_rd_en,
output [31:0] c3_p2_rd_data,
output c3_p2_rd_full,
output c3_p2_rd_empty,
output [6:0] c3_p2_rd_count,
output c3_p2_rd_overflow,
output c3_p2_rd_error,
input c3_p3_cmd_clk,
input c3_p3_cmd_en,
input [2:0] c3_p3_cmd_instr,
input [5:0] c3_p3_cmd_bl,
input [29:0] c3_p3_cmd_byte_addr,
output c3_p3_cmd_empty,
output c3_p3_cmd_full,
input c3_p3_wr_clk,
input c3_p3_wr_en,
input [3:0] c3_p3_wr_mask,
input [31:0] c3_p3_wr_data,
output c3_p3_wr_full,
output c3_p3_wr_empty,
output [6:0] c3_p3_wr_count,
output c3_p3_wr_underrun,
output c3_p3_wr_error,
input c3_p3_rd_clk,
input c3_p3_rd_en,
output [31:0] c3_p3_rd_data,
output c3_p3_rd_full,
output c3_p3_rd_empty,
output [6:0] c3_p3_rd_count,
output c3_p3_rd_overflow,
output c3_p3_rd_error
);
// The parameter CX_PORT_ENABLE shows all the active user ports in the design.
// For example, the value 6'b111100 tells that only port-2, port-3, port-4
// and port-5 are enabled. The other two ports are inactive. An inactive port
// can be a disabled port or an invisible logical port. Few examples to the
// invisible logical port are port-4 and port-5 in the user port configuration,
// Config-2: Four 32-bit bi-directional ports and the ports port-2 through
// port-5 in Config-4: Two 64-bit bi-directional ports. Please look into the
// Chapter-2 of ug388.pdf in the /docs directory for further details.
localparam C1_PORT_ENABLE = 6'b001111;
localparam C1_PORT_CONFIG = "B32_B32_B32_B32";
localparam C1_CLKOUT0_DIVIDE = 1;
localparam C1_CLKOUT1_DIVIDE = 1;
localparam C1_CLKOUT2_DIVIDE = 16;
localparam C1_CLKOUT3_DIVIDE = 8;
localparam C1_CLKFBOUT_MULT = 2;
localparam C1_DIVCLK_DIVIDE = 1;
localparam C1_ARB_ALGORITHM = 0;
localparam C1_ARB_NUM_TIME_SLOTS = 12;
localparam C1_ARB_TIME_SLOT_0 = 12'o0123;
localparam C1_ARB_TIME_SLOT_1 = 12'o1230;
localparam C1_ARB_TIME_SLOT_2 = 12'o2301;
localparam C1_ARB_TIME_SLOT_3 = 12'o3012;
localparam C1_ARB_TIME_SLOT_4 = 12'o0123;
localparam C1_ARB_TIME_SLOT_5 = 12'o1230;
localparam C1_ARB_TIME_SLOT_6 = 12'o2301;
localparam C1_ARB_TIME_SLOT_7 = 12'o3012;
localparam C1_ARB_TIME_SLOT_8 = 12'o0123;
localparam C1_ARB_TIME_SLOT_9 = 12'o1230;
localparam C1_ARB_TIME_SLOT_10 = 12'o2301;
localparam C1_ARB_TIME_SLOT_11 = 12'o3012;
localparam C1_MEM_TRAS = 37500;
localparam C1_MEM_TRCD = 13130;
localparam C1_MEM_TREFI = 7800000;
localparam C1_MEM_TRFC = 110000;
localparam C1_MEM_TRP = 13130;
localparam C1_MEM_TWR = 15000;
localparam C1_MEM_TRTP = 7500;
localparam C1_MEM_TWTR = 7500;
localparam C1_MEM_TYPE = "DDR3";
localparam C1_MEM_DENSITY = "1Gb";
localparam C1_MEM_BURST_LEN = 8;
localparam C1_MEM_CAS_LATENCY = 6;
localparam C1_MEM_NUM_COL_BITS = 10;
localparam C1_MEM_DDR1_2_ODS = "FULL";
localparam C1_MEM_DDR2_RTT = "150OHMS";
localparam C1_MEM_DDR2_DIFF_DQS_EN = "YES";
localparam C1_MEM_DDR2_3_PA_SR = "FULL";
localparam C1_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL";
localparam C1_MEM_DDR3_CAS_LATENCY = 6;
localparam C1_MEM_DDR3_ODS = "DIV6";
localparam C1_MEM_DDR3_RTT = "DIV4";
localparam C1_MEM_DDR3_CAS_WR_LATENCY = 5;
localparam C1_MEM_DDR3_AUTO_SR = "ENABLED";
localparam C1_MEM_MOBILE_PA_SR = "FULL";
localparam C1_MEM_MDDR_ODS = "FULL";
localparam C1_MC_CALIB_BYPASS = "NO";
localparam C1_MC_CALIBRATION_MODE = "CALIBRATION";
localparam C1_MC_CALIBRATION_DELAY = "HALF";
localparam C1_SKIP_IN_TERM_CAL = 0;
localparam C1_SKIP_DYNAMIC_CAL = 0;
localparam C1_LDQSP_TAP_DELAY_VAL = 0;
localparam C1_LDQSN_TAP_DELAY_VAL = 0;
localparam C1_UDQSP_TAP_DELAY_VAL = 0;
localparam C1_UDQSN_TAP_DELAY_VAL = 0;
localparam C1_DQ0_TAP_DELAY_VAL = 0;
localparam C1_DQ1_TAP_DELAY_VAL = 0;
localparam C1_DQ2_TAP_DELAY_VAL = 0;
localparam C1_DQ3_TAP_DELAY_VAL = 0;
localparam C1_DQ4_TAP_DELAY_VAL = 0;
localparam C1_DQ5_TAP_DELAY_VAL = 0;
localparam C1_DQ6_TAP_DELAY_VAL = 0;
localparam C1_DQ7_TAP_DELAY_VAL = 0;
localparam C1_DQ8_TAP_DELAY_VAL = 0;
localparam C1_DQ9_TAP_DELAY_VAL = 0;
localparam C1_DQ10_TAP_DELAY_VAL = 0;
localparam C1_DQ11_TAP_DELAY_VAL = 0;
localparam C1_DQ12_TAP_DELAY_VAL = 0;
localparam C1_DQ13_TAP_DELAY_VAL = 0;
localparam C1_DQ14_TAP_DELAY_VAL = 0;
localparam C1_DQ15_TAP_DELAY_VAL = 0;
localparam C1_MCB_USE_EXTERNAL_BUFPLL = 1;
localparam C1_SMALL_DEVICE = "FALSE"; // The parameter is set to TRUE for all packages of xc6slx9 device
// as most of them cannot fit the complete example design when the
// Chip scope modules are enabled
localparam C1_INCLK_PERIOD = ((C1_MEMCLK_PERIOD * C1_CLKFBOUT_MULT) / (C1_DIVCLK_DIVIDE * C1_CLKOUT0_DIVIDE * 2));
localparam C3_PORT_ENABLE = 6'b001111;
localparam C3_PORT_CONFIG = "B32_B32_B32_B32";
localparam C3_CLKOUT0_DIVIDE = 1;
localparam C3_CLKOUT1_DIVIDE = 1;
localparam C3_CLKOUT2_DIVIDE = 16;
localparam C3_CLKOUT3_DIVIDE = 8;
localparam C3_CLKFBOUT_MULT = 2;
localparam C3_DIVCLK_DIVIDE = 1;
localparam C3_ARB_ALGORITHM = 0;
localparam C3_ARB_NUM_TIME_SLOTS = 12;
localparam C3_ARB_TIME_SLOT_0 = 12'o0123;
localparam C3_ARB_TIME_SLOT_1 = 12'o1230;
localparam C3_ARB_TIME_SLOT_2 = 12'o2301;
localparam C3_ARB_TIME_SLOT_3 = 12'o3012;
localparam C3_ARB_TIME_SLOT_4 = 12'o0123;
localparam C3_ARB_TIME_SLOT_5 = 12'o1230;
localparam C3_ARB_TIME_SLOT_6 = 12'o2301;
localparam C3_ARB_TIME_SLOT_7 = 12'o3012;
localparam C3_ARB_TIME_SLOT_8 = 12'o0123;
localparam C3_ARB_TIME_SLOT_9 = 12'o1230;
localparam C3_ARB_TIME_SLOT_10 = 12'o2301;
localparam C3_ARB_TIME_SLOT_11 = 12'o3012;
localparam C3_MEM_TRAS = 37500;
localparam C3_MEM_TRCD = 13130;
localparam C3_MEM_TREFI = 7800000;
localparam C3_MEM_TRFC = 110000;
localparam C3_MEM_TRP = 13130;
localparam C3_MEM_TWR = 15000;
localparam C3_MEM_TRTP = 7500;
localparam C3_MEM_TWTR = 7500;
localparam C3_MEM_TYPE = "DDR3";
localparam C3_MEM_DENSITY = "1Gb";
localparam C3_MEM_BURST_LEN = 8;
localparam C3_MEM_CAS_LATENCY = 6;
localparam C3_MEM_NUM_COL_BITS = 10;
localparam C3_MEM_DDR1_2_ODS = "FULL";
localparam C3_MEM_DDR2_RTT = "150OHMS";
localparam C3_MEM_DDR2_DIFF_DQS_EN = "YES";
localparam C3_MEM_DDR2_3_PA_SR = "FULL";
localparam C3_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL";
localparam C3_MEM_DDR3_CAS_LATENCY = 6;
localparam C3_MEM_DDR3_ODS = "DIV6";
localparam C3_MEM_DDR3_RTT = "DIV4";
localparam C3_MEM_DDR3_CAS_WR_LATENCY = 5;
localparam C3_MEM_DDR3_AUTO_SR = "ENABLED";
localparam C3_MEM_MOBILE_PA_SR = "FULL";
localparam C3_MEM_MDDR_ODS = "FULL";
localparam C3_MC_CALIB_BYPASS = "NO";
localparam C3_MC_CALIBRATION_MODE = "CALIBRATION";
localparam C3_MC_CALIBRATION_DELAY = "HALF";
localparam C3_SKIP_IN_TERM_CAL = 0;
localparam C3_SKIP_DYNAMIC_CAL = 0;
localparam C3_LDQSP_TAP_DELAY_VAL = 0;
localparam C3_LDQSN_TAP_DELAY_VAL = 0;
localparam C3_UDQSP_TAP_DELAY_VAL = 0;
localparam C3_UDQSN_TAP_DELAY_VAL = 0;
localparam C3_DQ0_TAP_DELAY_VAL = 0;
localparam C3_DQ1_TAP_DELAY_VAL = 0;
localparam C3_DQ2_TAP_DELAY_VAL = 0;
localparam C3_DQ3_TAP_DELAY_VAL = 0;
localparam C3_DQ4_TAP_DELAY_VAL = 0;
localparam C3_DQ5_TAP_DELAY_VAL = 0;
localparam C3_DQ6_TAP_DELAY_VAL = 0;
localparam C3_DQ7_TAP_DELAY_VAL = 0;
localparam C3_DQ8_TAP_DELAY_VAL = 0;
localparam C3_DQ9_TAP_DELAY_VAL = 0;
localparam C3_DQ10_TAP_DELAY_VAL = 0;
localparam C3_DQ11_TAP_DELAY_VAL = 0;
localparam C3_DQ12_TAP_DELAY_VAL = 0;
localparam C3_DQ13_TAP_DELAY_VAL = 0;
localparam C3_DQ14_TAP_DELAY_VAL = 0;
localparam C3_DQ15_TAP_DELAY_VAL = 0;
localparam C3_MCB_USE_EXTERNAL_BUFPLL = 1;
localparam C3_SMALL_DEVICE = "FALSE"; // The parameter is set to TRUE for all packages of xc6slx9 device
// as most of them cannot fit the complete example design when the
// Chip scope modules are enabled
localparam C3_INCLK_PERIOD = ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
localparam DBG_WR_STS_WIDTH = 32;
localparam DBG_RD_STS_WIDTH = 32;
localparam C1_ARB_TIME0_SLOT = {3'b000, 3'b000, C1_ARB_TIME_SLOT_0[11:9], C1_ARB_TIME_SLOT_0[8:6], C1_ARB_TIME_SLOT_0[5:3], C1_ARB_TIME_SLOT_0[2:0]};
localparam C1_ARB_TIME1_SLOT = {3'b000, 3'b000, C1_ARB_TIME_SLOT_1[11:9], C1_ARB_TIME_SLOT_1[8:6], C1_ARB_TIME_SLOT_1[5:3], C1_ARB_TIME_SLOT_1[2:0]};
localparam C1_ARB_TIME2_SLOT = {3'b000, 3'b000, C1_ARB_TIME_SLOT_2[11:9], C1_ARB_TIME_SLOT_2[8:6], C1_ARB_TIME_SLOT_2[5:3], C1_ARB_TIME_SLOT_2[2:0]};
localparam C1_ARB_TIME3_SLOT = {3'b000, 3'b000, C1_ARB_TIME_SLOT_3[11:9], C1_ARB_TIME_SLOT_3[8:6], C1_ARB_TIME_SLOT_3[5:3], C1_ARB_TIME_SLOT_3[2:0]};
localparam C1_ARB_TIME4_SLOT = {3'b000, 3'b000, C1_ARB_TIME_SLOT_4[11:9], C1_ARB_TIME_SLOT_4[8:6], C1_ARB_TIME_SLOT_4[5:3], C1_ARB_TIME_SLOT_4[2:0]};
localparam C1_ARB_TIME5_SLOT = {3'b000, 3'b000, C1_ARB_TIME_SLOT_5[11:9], C1_ARB_TIME_SLOT_5[8:6], C1_ARB_TIME_SLOT_5[5:3], C1_ARB_TIME_SLOT_5[2:0]};
localparam C1_ARB_TIME6_SLOT = {3'b000, 3'b000, C1_ARB_TIME_SLOT_6[11:9], C1_ARB_TIME_SLOT_6[8:6], C1_ARB_TIME_SLOT_6[5:3], C1_ARB_TIME_SLOT_6[2:0]};
localparam C1_ARB_TIME7_SLOT = {3'b000, 3'b000, C1_ARB_TIME_SLOT_7[11:9], C1_ARB_TIME_SLOT_7[8:6], C1_ARB_TIME_SLOT_7[5:3], C1_ARB_TIME_SLOT_7[2:0]};
localparam C1_ARB_TIME8_SLOT = {3'b000, 3'b000, C1_ARB_TIME_SLOT_8[11:9], C1_ARB_TIME_SLOT_8[8:6], C1_ARB_TIME_SLOT_8[5:3], C1_ARB_TIME_SLOT_8[2:0]};
localparam C1_ARB_TIME9_SLOT = {3'b000, 3'b000, C1_ARB_TIME_SLOT_9[11:9], C1_ARB_TIME_SLOT_9[8:6], C1_ARB_TIME_SLOT_9[5:3], C1_ARB_TIME_SLOT_9[2:0]};
localparam C1_ARB_TIME10_SLOT = {3'b000, 3'b000, C1_ARB_TIME_SLOT_10[11:9], C1_ARB_TIME_SLOT_10[8:6], C1_ARB_TIME_SLOT_10[5:3], C1_ARB_TIME_SLOT_10[2:0]};
localparam C1_ARB_TIME11_SLOT = {3'b000, 3'b000, C1_ARB_TIME_SLOT_11[11:9], C1_ARB_TIME_SLOT_11[8:6], C1_ARB_TIME_SLOT_11[5:3], C1_ARB_TIME_SLOT_11[2:0]};
localparam C3_ARB_TIME0_SLOT = {3'b000, 3'b000, C3_ARB_TIME_SLOT_0[11:9], C3_ARB_TIME_SLOT_0[8:6], C3_ARB_TIME_SLOT_0[5:3], C3_ARB_TIME_SLOT_0[2:0]};
localparam C3_ARB_TIME1_SLOT = {3'b000, 3'b000, C3_ARB_TIME_SLOT_1[11:9], C3_ARB_TIME_SLOT_1[8:6], C3_ARB_TIME_SLOT_1[5:3], C3_ARB_TIME_SLOT_1[2:0]};
localparam C3_ARB_TIME2_SLOT = {3'b000, 3'b000, C3_ARB_TIME_SLOT_2[11:9], C3_ARB_TIME_SLOT_2[8:6], C3_ARB_TIME_SLOT_2[5:3], C3_ARB_TIME_SLOT_2[2:0]};
localparam C3_ARB_TIME3_SLOT = {3'b000, 3'b000, C3_ARB_TIME_SLOT_3[11:9], C3_ARB_TIME_SLOT_3[8:6], C3_ARB_TIME_SLOT_3[5:3], C3_ARB_TIME_SLOT_3[2:0]};
localparam C3_ARB_TIME4_SLOT = {3'b000, 3'b000, C3_ARB_TIME_SLOT_4[11:9], C3_ARB_TIME_SLOT_4[8:6], C3_ARB_TIME_SLOT_4[5:3], C3_ARB_TIME_SLOT_4[2:0]};
localparam C3_ARB_TIME5_SLOT = {3'b000, 3'b000, C3_ARB_TIME_SLOT_5[11:9], C3_ARB_TIME_SLOT_5[8:6], C3_ARB_TIME_SLOT_5[5:3], C3_ARB_TIME_SLOT_5[2:0]};
localparam C3_ARB_TIME6_SLOT = {3'b000, 3'b000, C3_ARB_TIME_SLOT_6[11:9], C3_ARB_TIME_SLOT_6[8:6], C3_ARB_TIME_SLOT_6[5:3], C3_ARB_TIME_SLOT_6[2:0]};
localparam C3_ARB_TIME7_SLOT = {3'b000, 3'b000, C3_ARB_TIME_SLOT_7[11:9], C3_ARB_TIME_SLOT_7[8:6], C3_ARB_TIME_SLOT_7[5:3], C3_ARB_TIME_SLOT_7[2:0]};
localparam C3_ARB_TIME8_SLOT = {3'b000, 3'b000, C3_ARB_TIME_SLOT_8[11:9], C3_ARB_TIME_SLOT_8[8:6], C3_ARB_TIME_SLOT_8[5:3], C3_ARB_TIME_SLOT_8[2:0]};
localparam C3_ARB_TIME9_SLOT = {3'b000, 3'b000, C3_ARB_TIME_SLOT_9[11:9], C3_ARB_TIME_SLOT_9[8:6], C3_ARB_TIME_SLOT_9[5:3], C3_ARB_TIME_SLOT_9[2:0]};
localparam C3_ARB_TIME10_SLOT = {3'b000, 3'b000, C3_ARB_TIME_SLOT_10[11:9], C3_ARB_TIME_SLOT_10[8:6], C3_ARB_TIME_SLOT_10[5:3], C3_ARB_TIME_SLOT_10[2:0]};
localparam C3_ARB_TIME11_SLOT = {3'b000, 3'b000, C3_ARB_TIME_SLOT_11[11:9], C3_ARB_TIME_SLOT_11[8:6], C3_ARB_TIME_SLOT_11[5:3], C3_ARB_TIME_SLOT_11[2:0]};
wire c1_sys_clk_p;
wire c1_sys_clk_n;
wire c1_async_rst;
wire c1_sysclk_2x;
wire c1_sysclk_2x_180;
wire c1_pll_ce_0;
wire c1_pll_ce_90;
wire c1_pll_lock;
wire c1_mcb_drp_clk;
wire c1_cmp_error;
wire c1_cmp_data_valid;
wire c1_vio_modify_enable;
wire [2:0] c1_vio_data_mode_value;
wire [2:0] c1_vio_addr_mode_value;
wire [31:0] c1_cmp_data;
wire c3_sys_clk_p;
wire c3_sys_clk_n;
wire c3_async_rst;
wire c3_sysclk_2x;
wire c3_sysclk_2x_180;
wire c3_pll_ce_0;
wire c3_pll_ce_90;
wire c3_pll_lock;
wire c3_mcb_drp_clk;
wire c3_cmp_error;
wire c3_cmp_data_valid;
wire c3_vio_modify_enable;
wire [2:0] c3_vio_data_mode_value;
wire [2:0] c3_vio_addr_mode_value;
wire [31:0] c3_cmp_data;
wire c1_p4_cmd_clk;
wire c1_p4_cmd_en;
wire[2:0] c1_p4_cmd_instr;
wire[5:0] c1_p4_cmd_bl;
wire[29:0] c1_p4_cmd_byte_addr;
wire c1_p4_cmd_empty;
wire c1_p4_cmd_full;
wire c1_p4_wr_clk;
wire c1_p4_wr_en;
wire[3:0] c1_p4_wr_mask;
wire[31:0] c1_p4_wr_data;
wire c1_p4_wr_full;
wire c1_p4_wr_empty;
wire[6:0] c1_p4_wr_count;
wire c1_p4_wr_underrun;
wire c1_p4_wr_error;
wire c1_p4_rd_clk;
wire c1_p4_rd_en;
wire[31:0] c1_p4_rd_data;
wire c1_p4_rd_full;
wire c1_p4_rd_empty;
wire[6:0] c1_p4_rd_count;
wire c1_p4_rd_overflow;
wire c1_p4_rd_error;
wire c1_p5_cmd_clk;
wire c1_p5_cmd_en;
wire[2:0] c1_p5_cmd_instr;
wire[5:0] c1_p5_cmd_bl;
wire[29:0] c1_p5_cmd_byte_addr;
wire c1_p5_cmd_empty;
wire c1_p5_cmd_full;
wire c1_p5_wr_clk;
wire c1_p5_wr_en;
wire[3:0] c1_p5_wr_mask;
wire[31:0] c1_p5_wr_data;
wire c1_p5_wr_full;
wire c1_p5_wr_empty;
wire[6:0] c1_p5_wr_count;
wire c1_p5_wr_underrun;
wire c1_p5_wr_error;
wire c1_p5_rd_clk;
wire c1_p5_rd_en;
wire[31:0] c1_p5_rd_data;
wire c1_p5_rd_full;
wire c1_p5_rd_empty;
wire[6:0] c1_p5_rd_count;
wire c1_p5_rd_overflow;
wire c1_p5_rd_error;
wire c3_p4_cmd_clk;
wire c3_p4_cmd_en;
wire[2:0] c3_p4_cmd_instr;
wire[5:0] c3_p4_cmd_bl;
wire[29:0] c3_p4_cmd_byte_addr;
wire c3_p4_cmd_empty;
wire c3_p4_cmd_full;
wire c3_p4_wr_clk;
wire c3_p4_wr_en;
wire[3:0] c3_p4_wr_mask;
wire[31:0] c3_p4_wr_data;
wire c3_p4_wr_full;
wire c3_p4_wr_empty;
wire[6:0] c3_p4_wr_count;
wire c3_p4_wr_underrun;
wire c3_p4_wr_error;
wire c3_p4_rd_clk;
wire c3_p4_rd_en;
wire[31:0] c3_p4_rd_data;
wire c3_p4_rd_full;
wire c3_p4_rd_empty;
wire[6:0] c3_p4_rd_count;
wire c3_p4_rd_overflow;
wire c3_p4_rd_error;
wire c3_p5_cmd_clk;
wire c3_p5_cmd_en;
wire[2:0] c3_p5_cmd_instr;
wire[5:0] c3_p5_cmd_bl;
wire[29:0] c3_p5_cmd_byte_addr;
wire c3_p5_cmd_empty;
wire c3_p5_cmd_full;
wire c3_p5_wr_clk;
wire c3_p5_wr_en;
wire[3:0] c3_p5_wr_mask;
wire[31:0] c3_p5_wr_data;
wire c3_p5_wr_full;
wire c3_p5_wr_empty;
wire[6:0] c3_p5_wr_count;
wire c3_p5_wr_underrun;
wire c3_p5_wr_error;
wire c3_p5_rd_clk;
wire c3_p5_rd_en;
wire[31:0] c3_p5_rd_data;
wire c3_p5_rd_full;
wire c3_p5_rd_empty;
wire[6:0] c3_p5_rd_count;
wire c3_p5_rd_overflow;
wire c3_p5_rd_error;
reg c1_aresetn;
reg c3_aresetn;
reg c4_aresetn;
reg c5_aresetn;
assign c1_sys_clk_p = 1'b0;
assign c1_sys_clk_n = 1'b0;
assign c3_sys_clk_p = 1'b0;
assign c3_sys_clk_n = 1'b0;
// Infrastructure-1 instantiation
infrastructure #
(
.C_INCLK_PERIOD (C1_INCLK_PERIOD),
.C_RST_ACT_LOW (C1_RST_ACT_LOW),
.C_INPUT_CLK_TYPE (C1_INPUT_CLK_TYPE),
.C_CLKOUT0_DIVIDE (C1_CLKOUT0_DIVIDE),
.C_CLKOUT1_DIVIDE (C1_CLKOUT1_DIVIDE),
.C_CLKOUT2_DIVIDE (C1_CLKOUT2_DIVIDE),
.C_CLKOUT3_DIVIDE (C1_CLKOUT3_DIVIDE),
.C_CLKFBOUT_MULT (C1_CLKFBOUT_MULT),
.C_DIVCLK_DIVIDE (C1_DIVCLK_DIVIDE)
)
memc1_infrastructure_inst
(
.sys_clk_p (c1_sys_clk_p), // [input] differential p type clock from board
.sys_clk_n (c1_sys_clk_n), // [input] differential n type clock from board
.sys_clk (c1_sys_clk), // [input] single ended input clock from board
.sys_rst_i (c1_sys_rst_i),
.clk0 (c1_clk0), // [output] user clock which determines the operating frequency of user interface ports
.rst0 (c1_rst0),
.async_rst (c1_async_rst),
.sysclk_2x (c1_sysclk_2x),
.sysclk_2x_180 (c1_sysclk_2x_180),
.pll_ce_0 (c1_pll_ce_0),
.pll_ce_90 (c1_pll_ce_90),
.pll_lock (c1_pll_lock),
.mcb_drp_clk (c1_mcb_drp_clk)
);
// Infrastructure-3 instantiation
infrastructure #
(
.C_INCLK_PERIOD (C3_INCLK_PERIOD),
.C_RST_ACT_LOW (C3_RST_ACT_LOW),
.C_INPUT_CLK_TYPE (C3_INPUT_CLK_TYPE),
.C_CLKOUT0_DIVIDE (C3_CLKOUT0_DIVIDE),
.C_CLKOUT1_DIVIDE (C3_CLKOUT1_DIVIDE),
.C_CLKOUT2_DIVIDE (C3_CLKOUT2_DIVIDE),
.C_CLKOUT3_DIVIDE (C3_CLKOUT3_DIVIDE),
.C_CLKFBOUT_MULT (C3_CLKFBOUT_MULT),
.C_DIVCLK_DIVIDE (C3_DIVCLK_DIVIDE)
)
memc3_infrastructure_inst
(
.sys_clk_p (c3_sys_clk_p), // [input] differential p type clock from board
.sys_clk_n (c3_sys_clk_n), // [input] differential n type clock from board
.sys_clk (c3_sys_clk), // [input] single ended input clock from board
.sys_rst_i (c3_sys_rst_i),
.clk0 (c3_clk0), // [output] user clock which determines the operating frequency of user interface ports
.rst0 (c3_rst0),
.async_rst (c3_async_rst),
.sysclk_2x (c3_sysclk_2x),
.sysclk_2x_180 (c3_sysclk_2x_180),
.pll_ce_0 (c3_pll_ce_0),
.pll_ce_90 (c3_pll_ce_90),
.pll_lock (c3_pll_lock),
.mcb_drp_clk (c3_mcb_drp_clk)
);
// Controller-1 instantiation
memc_wrapper #
(
.C_MEMCLK_PERIOD (C1_MEMCLK_PERIOD),
.C_CALIB_SOFT_IP (C1_CALIB_SOFT_IP),
//synthesis translate_off
.C_SIMULATION (C1_SIMULATION),
//synthesis translate_on
.C_ARB_NUM_TIME_SLOTS (C1_ARB_NUM_TIME_SLOTS),
.C_ARB_TIME_SLOT_0 (C1_ARB_TIME0_SLOT),
.C_ARB_TIME_SLOT_1 (C1_ARB_TIME1_SLOT),
.C_ARB_TIME_SLOT_2 (C1_ARB_TIME2_SLOT),
.C_ARB_TIME_SLOT_3 (C1_ARB_TIME3_SLOT),
.C_ARB_TIME_SLOT_4 (C1_ARB_TIME4_SLOT),
.C_ARB_TIME_SLOT_5 (C1_ARB_TIME5_SLOT),
.C_ARB_TIME_SLOT_6 (C1_ARB_TIME6_SLOT),
.C_ARB_TIME_SLOT_7 (C1_ARB_TIME7_SLOT),
.C_ARB_TIME_SLOT_8 (C1_ARB_TIME8_SLOT),
.C_ARB_TIME_SLOT_9 (C1_ARB_TIME9_SLOT),
.C_ARB_TIME_SLOT_10 (C1_ARB_TIME10_SLOT),
.C_ARB_TIME_SLOT_11 (C1_ARB_TIME11_SLOT),
.C_ARB_ALGORITHM (C1_ARB_ALGORITHM),
.C_PORT_ENABLE (C1_PORT_ENABLE),
.C_PORT_CONFIG (C1_PORT_CONFIG),
.C_MEM_TRAS (C1_MEM_TRAS),
.C_MEM_TRCD (C1_MEM_TRCD),
.C_MEM_TREFI (C1_MEM_TREFI),
.C_MEM_TRFC (C1_MEM_TRFC),
.C_MEM_TRP (C1_MEM_TRP),
.C_MEM_TWR (C1_MEM_TWR),
.C_MEM_TRTP (C1_MEM_TRTP),
.C_MEM_TWTR (C1_MEM_TWTR),
.C_MEM_ADDR_ORDER (C1_MEM_ADDR_ORDER),
.C_NUM_DQ_PINS (C1_NUM_DQ_PINS),
.C_MEM_TYPE (C1_MEM_TYPE),
.C_MEM_DENSITY (C1_MEM_DENSITY),
.C_MEM_BURST_LEN (C1_MEM_BURST_LEN),
.C_MEM_CAS_LATENCY (C1_MEM_CAS_LATENCY),
.C_MEM_ADDR_WIDTH (C1_MEM_ADDR_WIDTH),
.C_MEM_BANKADDR_WIDTH (C1_MEM_BANKADDR_WIDTH),
.C_MEM_NUM_COL_BITS (C1_MEM_NUM_COL_BITS),
.C_MEM_DDR1_2_ODS (C1_MEM_DDR1_2_ODS),
.C_MEM_DDR2_RTT (C1_MEM_DDR2_RTT),
.C_MEM_DDR2_DIFF_DQS_EN (C1_MEM_DDR2_DIFF_DQS_EN),
.C_MEM_DDR2_3_PA_SR (C1_MEM_DDR2_3_PA_SR),
.C_MEM_DDR2_3_HIGH_TEMP_SR (C1_MEM_DDR2_3_HIGH_TEMP_SR),
.C_MEM_DDR3_CAS_LATENCY (C1_MEM_DDR3_CAS_LATENCY),
.C_MEM_DDR3_ODS (C1_MEM_DDR3_ODS),
.C_MEM_DDR3_RTT (C1_MEM_DDR3_RTT),
.C_MEM_DDR3_CAS_WR_LATENCY (C1_MEM_DDR3_CAS_WR_LATENCY),
.C_MEM_DDR3_AUTO_SR (C1_MEM_DDR3_AUTO_SR),
.C_MEM_MOBILE_PA_SR (C1_MEM_MOBILE_PA_SR),
.C_MEM_MDDR_ODS (C1_MEM_MDDR_ODS),
.C_MC_CALIB_BYPASS (C1_MC_CALIB_BYPASS),
.C_MC_CALIBRATION_MODE (C1_MC_CALIBRATION_MODE),
.C_MC_CALIBRATION_DELAY (C1_MC_CALIBRATION_DELAY),
.C_SKIP_IN_TERM_CAL (C1_SKIP_IN_TERM_CAL),
.C_SKIP_DYNAMIC_CAL (C1_SKIP_DYNAMIC_CAL),
.LDQSP_TAP_DELAY_VAL (C1_LDQSP_TAP_DELAY_VAL),
.UDQSP_TAP_DELAY_VAL (C1_UDQSP_TAP_DELAY_VAL),
.LDQSN_TAP_DELAY_VAL (C1_LDQSN_TAP_DELAY_VAL),
.UDQSN_TAP_DELAY_VAL (C1_UDQSN_TAP_DELAY_VAL),
.DQ0_TAP_DELAY_VAL (C1_DQ0_TAP_DELAY_VAL),
.DQ1_TAP_DELAY_VAL (C1_DQ1_TAP_DELAY_VAL),
.DQ2_TAP_DELAY_VAL (C1_DQ2_TAP_DELAY_VAL),
.DQ3_TAP_DELAY_VAL (C1_DQ3_TAP_DELAY_VAL),
.DQ4_TAP_DELAY_VAL (C1_DQ4_TAP_DELAY_VAL),
.DQ5_TAP_DELAY_VAL (C1_DQ5_TAP_DELAY_VAL),
.DQ6_TAP_DELAY_VAL (C1_DQ6_TAP_DELAY_VAL),
.DQ7_TAP_DELAY_VAL (C1_DQ7_TAP_DELAY_VAL),
.DQ8_TAP_DELAY_VAL (C1_DQ8_TAP_DELAY_VAL),
.DQ9_TAP_DELAY_VAL (C1_DQ9_TAP_DELAY_VAL),
.DQ10_TAP_DELAY_VAL (C1_DQ10_TAP_DELAY_VAL),
.DQ11_TAP_DELAY_VAL (C1_DQ11_TAP_DELAY_VAL),
.DQ12_TAP_DELAY_VAL (C1_DQ12_TAP_DELAY_VAL),
.DQ13_TAP_DELAY_VAL (C1_DQ13_TAP_DELAY_VAL),
.DQ14_TAP_DELAY_VAL (C1_DQ14_TAP_DELAY_VAL),
.DQ15_TAP_DELAY_VAL (C1_DQ15_TAP_DELAY_VAL),
.C_P0_MASK_SIZE (C1_P0_MASK_SIZE),
.C_P0_DATA_PORT_SIZE (C1_P0_DATA_PORT_SIZE),
.C_P1_MASK_SIZE (C1_P1_MASK_SIZE),
.C_P1_DATA_PORT_SIZE (C1_P1_DATA_PORT_SIZE)
)
memc1_wrapper_inst
(
.mcbx_dram_addr (mcb1_dram_a),
.mcbx_dram_ba (mcb1_dram_ba),
.mcbx_dram_ras_n (mcb1_dram_ras_n),
.mcbx_dram_cas_n (mcb1_dram_cas_n),
.mcbx_dram_we_n (mcb1_dram_we_n),
.mcbx_dram_cke (mcb1_dram_cke),
.mcbx_dram_clk (mcb1_dram_ck),
.mcbx_dram_clk_n (mcb1_dram_ck_n),
.mcbx_dram_dq (mcb1_dram_dq),
.mcbx_dram_dqs (mcb1_dram_dqs),
.mcbx_dram_dqs_n (mcb1_dram_dqs_n),
.mcbx_dram_udqs (mcb1_dram_udqs),
.mcbx_dram_udqs_n (mcb1_dram_udqs_n),
.mcbx_dram_udm (mcb1_dram_udm),
.mcbx_dram_ldm (mcb1_dram_dm),
.mcbx_dram_odt (mcb1_dram_odt),
.mcbx_dram_ddr3_rst (mcb1_dram_reset_n),
.mcbx_rzq (mcb1_rzq),
.mcbx_zio (mcb1_zio),
.calib_done (c1_calib_done),
.async_rst (c1_async_rst),
.sysclk_2x (c1_sysclk_2x),
.sysclk_2x_180 (c1_sysclk_2x_180),
.pll_ce_0 (c1_pll_ce_0),
.pll_ce_90 (c1_pll_ce_90),
.pll_lock (c1_pll_lock),
.mcb_drp_clk (c1_mcb_drp_clk),
// The following port map shows all the six logical user ports. However, all
// of them may not be active in this design. A port should be enabled to
// validate its port map. If it is not,the complete port is going to float
// by getting disconnected from the lower level MCB modules. The port enable
// information of a controller can be obtained from the corresponding local
// parameter CX_PORT_ENABLE. In such a case, we can simply ignore its port map.
// The following comments will explain when a port is going to be active.
// Config-1: Two 32-bit bi-directional and four 32-bit unidirectional ports
// Config-2: Four 32-bit bi-directional ports
// Config-3: One 64-bit bi-directional and two 32-bit bi-directional ports
// Config-4: Two 64-bit bi-directional ports
// Config-5: One 128-bit bi-directional port
// User Port-0 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_cmd_clk (c1_p0_cmd_clk),
.p0_cmd_en (c1_p0_cmd_en),
.p0_cmd_instr (c1_p0_cmd_instr),
.p0_cmd_bl (c1_p0_cmd_bl),
.p0_cmd_byte_addr (c1_p0_cmd_byte_addr),
.p0_cmd_full (c1_p0_cmd_full),
.p0_cmd_empty (c1_p0_cmd_empty),
// User Port-0 data write interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_wr_clk (c1_p0_wr_clk),
.p0_wr_en (c1_p0_wr_en),
.p0_wr_mask (c1_p0_wr_mask),
.p0_wr_data (c1_p0_wr_data),
.p0_wr_full (c1_p0_wr_full),
.p0_wr_count (c1_p0_wr_count),
.p0_wr_empty (c1_p0_wr_empty),
.p0_wr_underrun (c1_p0_wr_underrun),
.p0_wr_error (c1_p0_wr_error),
// User Port-0 data read interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_rd_clk (c1_p0_rd_clk),
.p0_rd_en (c1_p0_rd_en),
.p0_rd_data (c1_p0_rd_data),
.p0_rd_empty (c1_p0_rd_empty),
.p0_rd_count (c1_p0_rd_count),
.p0_rd_full (c1_p0_rd_full),
.p0_rd_overflow (c1_p0_rd_overflow),
.p0_rd_error (c1_p0_rd_error),
// User Port-1 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_cmd_clk (c1_p1_cmd_clk),
.p1_cmd_en (c1_p1_cmd_en),
.p1_cmd_instr (c1_p1_cmd_instr),
.p1_cmd_bl (c1_p1_cmd_bl),
.p1_cmd_byte_addr (c1_p1_cmd_byte_addr),
.p1_cmd_full (c1_p1_cmd_full),
.p1_cmd_empty (c1_p1_cmd_empty),
// User Port-1 data write interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_wr_clk (c1_p1_wr_clk),
.p1_wr_en (c1_p1_wr_en),
.p1_wr_mask (c1_p1_wr_mask),
.p1_wr_data (c1_p1_wr_data),
.p1_wr_full (c1_p1_wr_full),
.p1_wr_count (c1_p1_wr_count),
.p1_wr_empty (c1_p1_wr_empty),
.p1_wr_underrun (c1_p1_wr_underrun),
.p1_wr_error (c1_p1_wr_error),
// User Port-1 data read interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_rd_clk (c1_p1_rd_clk),
.p1_rd_en (c1_p1_rd_en),
.p1_rd_data (c1_p1_rd_data),
.p1_rd_empty (c1_p1_rd_empty),
.p1_rd_count (c1_p1_rd_count),
.p1_rd_full (c1_p1_rd_full),
.p1_rd_overflow (c1_p1_rd_overflow),
.p1_rd_error (c1_p1_rd_error),
// User Port-2 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2 and Config-3
.p2_cmd_clk (c1_p2_cmd_clk),
.p2_cmd_en (c1_p2_cmd_en),
.p2_cmd_instr (c1_p2_cmd_instr),
.p2_cmd_bl (c1_p2_cmd_bl),
.p2_cmd_byte_addr (c1_p2_cmd_byte_addr),
.p2_cmd_full (c1_p2_cmd_full),
.p2_cmd_empty (c1_p2_cmd_empty),
// User Port-2 data write interface will be active only when the port is enabled in
// the port configurations Config-1 write direction, Config-2 and Config-3
.p2_wr_clk (c1_p2_wr_clk),
.p2_wr_en (c1_p2_wr_en),
.p2_wr_mask (c1_p2_wr_mask),
.p2_wr_data (c1_p2_wr_data),
.p2_wr_full (c1_p2_wr_full),
.p2_wr_count (c1_p2_wr_count),
.p2_wr_empty (c1_p2_wr_empty),
.p2_wr_underrun (c1_p2_wr_underrun),
.p2_wr_error (c1_p2_wr_error),
// User Port-2 data read interface will be active only when the port is enabled in
// the port configurations Config-1 read direction, Config-2 and Config-3
.p2_rd_clk (c1_p2_rd_clk),
.p2_rd_en (c1_p2_rd_en),
.p2_rd_data (c1_p2_rd_data),
.p2_rd_empty (c1_p2_rd_empty),
.p2_rd_count (c1_p2_rd_count),
.p2_rd_full (c1_p2_rd_full),
.p2_rd_overflow (c1_p2_rd_overflow),
.p2_rd_error (c1_p2_rd_error),
// User Port-3 command interface will be active only when the port is enabled in
// the port configurations Config-1 and Config-2
.p3_cmd_clk (c1_p3_cmd_clk),
.p3_cmd_en (c1_p3_cmd_en),
.p3_cmd_instr (c1_p3_cmd_instr),
.p3_cmd_bl (c1_p3_cmd_bl),
.p3_cmd_byte_addr (c1_p3_cmd_byte_addr),
.p3_cmd_full (c1_p3_cmd_full),
.p3_cmd_empty (c1_p3_cmd_empty),
// User Port-3 data write interface will be active only when the port is enabled in
// the port configurations Config-1 write direction and Config-2
.p3_wr_clk (c1_p3_wr_clk),
.p3_wr_en (c1_p3_wr_en),
.p3_wr_mask (c1_p3_wr_mask),
.p3_wr_data (c1_p3_wr_data),
.p3_wr_full (c1_p3_wr_full),
.p3_wr_count (c1_p3_wr_count),
.p3_wr_empty (c1_p3_wr_empty),
.p3_wr_underrun (c1_p3_wr_underrun),
.p3_wr_error (c1_p3_wr_error),
// User Port-3 data read interface will be active only when the port is enabled in
// the port configurations Config-1 read direction and Config-2
.p3_rd_clk (c1_p3_rd_clk),
.p3_rd_en (c1_p3_rd_en),
.p3_rd_data (c1_p3_rd_data),
.p3_rd_empty (c1_p3_rd_empty),
.p3_rd_count (c1_p3_rd_count),
.p3_rd_full (c1_p3_rd_full),
.p3_rd_overflow (c1_p3_rd_overflow),
.p3_rd_error (c1_p3_rd_error),
// User Port-4 command interface will be active only when the port is enabled in
// the port configuration Config-1
.p4_cmd_clk (c1_p4_cmd_clk),
.p4_cmd_en (c1_p4_cmd_en),
.p4_cmd_instr (c1_p4_cmd_instr),
.p4_cmd_bl (c1_p4_cmd_bl),
.p4_cmd_byte_addr (c1_p4_cmd_byte_addr),
.p4_cmd_full (c1_p4_cmd_full),
.p4_cmd_empty (c1_p4_cmd_empty),
// User Port-4 data write interface will be active only when the port is enabled in
// the port configuration Config-1 write direction
.p4_wr_clk (c1_p4_wr_clk),
.p4_wr_en (c1_p4_wr_en),
.p4_wr_mask (c1_p4_wr_mask),
.p4_wr_data (c1_p4_wr_data),
.p4_wr_full (c1_p4_wr_full),
.p4_wr_count (c1_p4_wr_count),
.p4_wr_empty (c1_p4_wr_empty),
.p4_wr_underrun (c1_p4_wr_underrun),
.p4_wr_error (c1_p4_wr_error),
// User Port-4 data read interface will be active only when the port is enabled in
// the port configuration Config-1 read direction
.p4_rd_clk (c1_p4_rd_clk),
.p4_rd_en (c1_p4_rd_en),
.p4_rd_data (c1_p4_rd_data),
.p4_rd_empty (c1_p4_rd_empty),
.p4_rd_count (c1_p4_rd_count),
.p4_rd_full (c1_p4_rd_full),
.p4_rd_overflow (c1_p4_rd_overflow),
.p4_rd_error (c1_p4_rd_error),
// User Port-5 command interface will be active only when the port is enabled in
// the port configuration Config-1
.p5_cmd_clk (c1_p5_cmd_clk),
.p5_cmd_en (c1_p5_cmd_en),
.p5_cmd_instr (c1_p5_cmd_instr),
.p5_cmd_bl (c1_p5_cmd_bl),
.p5_cmd_byte_addr (c1_p5_cmd_byte_addr),
.p5_cmd_full (c1_p5_cmd_full),
.p5_cmd_empty (c1_p5_cmd_empty),
// User Port-5 data write interface will be active only when the port is enabled in
// the port configuration Config-1 write direction
.p5_wr_clk (c1_p5_wr_clk),
.p5_wr_en (c1_p5_wr_en),
.p5_wr_mask (c1_p5_wr_mask),
.p5_wr_data (c1_p5_wr_data),
.p5_wr_full (c1_p5_wr_full),
.p5_wr_count (c1_p5_wr_count),
.p5_wr_empty (c1_p5_wr_empty),
.p5_wr_underrun (c1_p5_wr_underrun),
.p5_wr_error (c1_p5_wr_error),
// User Port-5 data read interface will be active only when the port is enabled in
// the port configuration Config-1 read direction
.p5_rd_clk (c1_p5_rd_clk),
.p5_rd_en (c1_p5_rd_en),
.p5_rd_data (c1_p5_rd_data),
.p5_rd_empty (c1_p5_rd_empty),
.p5_rd_count (c1_p5_rd_count),
.p5_rd_full (c1_p5_rd_full),
.p5_rd_overflow (c1_p5_rd_overflow),
.p5_rd_error (c1_p5_rd_error),
.selfrefresh_enter (1'b0),
.selfrefresh_mode (c1_selfrefresh_mode)
);
// Controller-3 instantiation
memc_wrapper #
(
.C_MEMCLK_PERIOD (C3_MEMCLK_PERIOD),
.C_CALIB_SOFT_IP (C3_CALIB_SOFT_IP),
//synthesis translate_off
.C_SIMULATION (C3_SIMULATION),
//synthesis translate_on
.C_ARB_NUM_TIME_SLOTS (C3_ARB_NUM_TIME_SLOTS),
.C_ARB_TIME_SLOT_0 (C3_ARB_TIME0_SLOT),
.C_ARB_TIME_SLOT_1 (C3_ARB_TIME1_SLOT),
.C_ARB_TIME_SLOT_2 (C3_ARB_TIME2_SLOT),
.C_ARB_TIME_SLOT_3 (C3_ARB_TIME3_SLOT),
.C_ARB_TIME_SLOT_4 (C3_ARB_TIME4_SLOT),
.C_ARB_TIME_SLOT_5 (C3_ARB_TIME5_SLOT),
.C_ARB_TIME_SLOT_6 (C3_ARB_TIME6_SLOT),
.C_ARB_TIME_SLOT_7 (C3_ARB_TIME7_SLOT),
.C_ARB_TIME_SLOT_8 (C3_ARB_TIME8_SLOT),
.C_ARB_TIME_SLOT_9 (C3_ARB_TIME9_SLOT),
.C_ARB_TIME_SLOT_10 (C3_ARB_TIME10_SLOT),
.C_ARB_TIME_SLOT_11 (C3_ARB_TIME11_SLOT),
.C_ARB_ALGORITHM (C3_ARB_ALGORITHM),
.C_PORT_ENABLE (C3_PORT_ENABLE),
.C_PORT_CONFIG (C3_PORT_CONFIG),
.C_MEM_TRAS (C3_MEM_TRAS),
.C_MEM_TRCD (C3_MEM_TRCD),
.C_MEM_TREFI (C3_MEM_TREFI),
.C_MEM_TRFC (C3_MEM_TRFC),
.C_MEM_TRP (C3_MEM_TRP),
.C_MEM_TWR (C3_MEM_TWR),
.C_MEM_TRTP (C3_MEM_TRTP),
.C_MEM_TWTR (C3_MEM_TWTR),
.C_MEM_ADDR_ORDER (C3_MEM_ADDR_ORDER),
.C_NUM_DQ_PINS (C3_NUM_DQ_PINS),
.C_MEM_TYPE (C3_MEM_TYPE),
.C_MEM_DENSITY (C3_MEM_DENSITY),
.C_MEM_BURST_LEN (C3_MEM_BURST_LEN),
.C_MEM_CAS_LATENCY (C3_MEM_CAS_LATENCY),
.C_MEM_ADDR_WIDTH (C3_MEM_ADDR_WIDTH),
.C_MEM_BANKADDR_WIDTH (C3_MEM_BANKADDR_WIDTH),
.C_MEM_NUM_COL_BITS (C3_MEM_NUM_COL_BITS),
.C_MEM_DDR1_2_ODS (C3_MEM_DDR1_2_ODS),
.C_MEM_DDR2_RTT (C3_MEM_DDR2_RTT),
.C_MEM_DDR2_DIFF_DQS_EN (C3_MEM_DDR2_DIFF_DQS_EN),
.C_MEM_DDR2_3_PA_SR (C3_MEM_DDR2_3_PA_SR),
.C_MEM_DDR2_3_HIGH_TEMP_SR (C3_MEM_DDR2_3_HIGH_TEMP_SR),
.C_MEM_DDR3_CAS_LATENCY (C3_MEM_DDR3_CAS_LATENCY),
.C_MEM_DDR3_ODS (C3_MEM_DDR3_ODS),
.C_MEM_DDR3_RTT (C3_MEM_DDR3_RTT),
.C_MEM_DDR3_CAS_WR_LATENCY (C3_MEM_DDR3_CAS_WR_LATENCY),
.C_MEM_DDR3_AUTO_SR (C3_MEM_DDR3_AUTO_SR),
.C_MEM_MOBILE_PA_SR (C3_MEM_MOBILE_PA_SR),
.C_MEM_MDDR_ODS (C3_MEM_MDDR_ODS),
.C_MC_CALIB_BYPASS (C3_MC_CALIB_BYPASS),
.C_MC_CALIBRATION_MODE (C3_MC_CALIBRATION_MODE),
.C_MC_CALIBRATION_DELAY (C3_MC_CALIBRATION_DELAY),
.C_SKIP_IN_TERM_CAL (C3_SKIP_IN_TERM_CAL),
.C_SKIP_DYNAMIC_CAL (C3_SKIP_DYNAMIC_CAL),
.LDQSP_TAP_DELAY_VAL (C3_LDQSP_TAP_DELAY_VAL),
.UDQSP_TAP_DELAY_VAL (C3_UDQSP_TAP_DELAY_VAL),
.LDQSN_TAP_DELAY_VAL (C3_LDQSN_TAP_DELAY_VAL),
.UDQSN_TAP_DELAY_VAL (C3_UDQSN_TAP_DELAY_VAL),
.DQ0_TAP_DELAY_VAL (C3_DQ0_TAP_DELAY_VAL),
.DQ1_TAP_DELAY_VAL (C3_DQ1_TAP_DELAY_VAL),
.DQ2_TAP_DELAY_VAL (C3_DQ2_TAP_DELAY_VAL),
.DQ3_TAP_DELAY_VAL (C3_DQ3_TAP_DELAY_VAL),
.DQ4_TAP_DELAY_VAL (C3_DQ4_TAP_DELAY_VAL),
.DQ5_TAP_DELAY_VAL (C3_DQ5_TAP_DELAY_VAL),
.DQ6_TAP_DELAY_VAL (C3_DQ6_TAP_DELAY_VAL),
.DQ7_TAP_DELAY_VAL (C3_DQ7_TAP_DELAY_VAL),
.DQ8_TAP_DELAY_VAL (C3_DQ8_TAP_DELAY_VAL),
.DQ9_TAP_DELAY_VAL (C3_DQ9_TAP_DELAY_VAL),
.DQ10_TAP_DELAY_VAL (C3_DQ10_TAP_DELAY_VAL),
.DQ11_TAP_DELAY_VAL (C3_DQ11_TAP_DELAY_VAL),
.DQ12_TAP_DELAY_VAL (C3_DQ12_TAP_DELAY_VAL),
.DQ13_TAP_DELAY_VAL (C3_DQ13_TAP_DELAY_VAL),
.DQ14_TAP_DELAY_VAL (C3_DQ14_TAP_DELAY_VAL),
.DQ15_TAP_DELAY_VAL (C3_DQ15_TAP_DELAY_VAL),
.C_P0_MASK_SIZE (C3_P0_MASK_SIZE),
.C_P0_DATA_PORT_SIZE (C3_P0_DATA_PORT_SIZE),
.C_P1_MASK_SIZE (C3_P1_MASK_SIZE),
.C_P1_DATA_PORT_SIZE (C3_P1_DATA_PORT_SIZE)
)
memc3_wrapper_inst
(
.mcbx_dram_addr (mcb3_dram_a),
.mcbx_dram_ba (mcb3_dram_ba),
.mcbx_dram_ras_n (mcb3_dram_ras_n),
.mcbx_dram_cas_n (mcb3_dram_cas_n),
.mcbx_dram_we_n (mcb3_dram_we_n),
.mcbx_dram_cke (mcb3_dram_cke),
.mcbx_dram_clk (mcb3_dram_ck),
.mcbx_dram_clk_n (mcb3_dram_ck_n),
.mcbx_dram_dq (mcb3_dram_dq),
.mcbx_dram_dqs (mcb3_dram_dqs),
.mcbx_dram_dqs_n (mcb3_dram_dqs_n),
.mcbx_dram_udqs (mcb3_dram_udqs),
.mcbx_dram_udqs_n (mcb3_dram_udqs_n),
.mcbx_dram_udm (mcb3_dram_udm),
.mcbx_dram_ldm (mcb3_dram_dm),
.mcbx_dram_odt (mcb3_dram_odt),
.mcbx_dram_ddr3_rst (mcb3_dram_reset_n),
.mcbx_rzq (mcb3_rzq),
.mcbx_zio (mcb3_zio),
.calib_done (c3_calib_done),
.async_rst (c3_async_rst),
.sysclk_2x (c3_sysclk_2x),
.sysclk_2x_180 (c3_sysclk_2x_180),
.pll_ce_0 (c3_pll_ce_0),
.pll_ce_90 (c3_pll_ce_90),
.pll_lock (c3_pll_lock),
.mcb_drp_clk (c3_mcb_drp_clk),
// The following port map shows all the six logical user ports. However, all
// of them may not be active in this design. A port should be enabled to
// validate its port map. If it is not,the complete port is going to float
// by getting disconnected from the lower level MCB modules. The port enable
// information of a controller can be obtained from the corresponding local
// parameter CX_PORT_ENABLE. In such a case, we can simply ignore its port map.
// The following comments will explain when a port is going to be active.
// Config-1: Two 32-bit bi-directional and four 32-bit unidirectional ports
// Config-2: Four 32-bit bi-directional ports
// Config-3: One 64-bit bi-directional and two 32-bit bi-directional ports
// Config-4: Two 64-bit bi-directional ports
// Config-5: One 128-bit bi-directional port
// User Port-0 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_cmd_clk (c3_p0_cmd_clk),
.p0_cmd_en (c3_p0_cmd_en),
.p0_cmd_instr (c3_p0_cmd_instr),
.p0_cmd_bl (c3_p0_cmd_bl),
.p0_cmd_byte_addr (c3_p0_cmd_byte_addr),
.p0_cmd_full (c3_p0_cmd_full),
.p0_cmd_empty (c3_p0_cmd_empty),
// User Port-0 data write interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_wr_clk (c3_p0_wr_clk),
.p0_wr_en (c3_p0_wr_en),
.p0_wr_mask (c3_p0_wr_mask),
.p0_wr_data (c3_p0_wr_data),
.p0_wr_full (c3_p0_wr_full),
.p0_wr_count (c3_p0_wr_count),
.p0_wr_empty (c3_p0_wr_empty),
.p0_wr_underrun (c3_p0_wr_underrun),
.p0_wr_error (c3_p0_wr_error),
// User Port-0 data read interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
.p0_rd_clk (c3_p0_rd_clk),
.p0_rd_en (c3_p0_rd_en),
.p0_rd_data (c3_p0_rd_data),
.p0_rd_empty (c3_p0_rd_empty),
.p0_rd_count (c3_p0_rd_count),
.p0_rd_full (c3_p0_rd_full),
.p0_rd_overflow (c3_p0_rd_overflow),
.p0_rd_error (c3_p0_rd_error),
// User Port-1 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_cmd_clk (c3_p1_cmd_clk),
.p1_cmd_en (c3_p1_cmd_en),
.p1_cmd_instr (c3_p1_cmd_instr),
.p1_cmd_bl (c3_p1_cmd_bl),
.p1_cmd_byte_addr (c3_p1_cmd_byte_addr),
.p1_cmd_full (c3_p1_cmd_full),
.p1_cmd_empty (c3_p1_cmd_empty),
// User Port-1 data write interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_wr_clk (c3_p1_wr_clk),
.p1_wr_en (c3_p1_wr_en),
.p1_wr_mask (c3_p1_wr_mask),
.p1_wr_data (c3_p1_wr_data),
.p1_wr_full (c3_p1_wr_full),
.p1_wr_count (c3_p1_wr_count),
.p1_wr_empty (c3_p1_wr_empty),
.p1_wr_underrun (c3_p1_wr_underrun),
.p1_wr_error (c3_p1_wr_error),
// User Port-1 data read interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
.p1_rd_clk (c3_p1_rd_clk),
.p1_rd_en (c3_p1_rd_en),
.p1_rd_data (c3_p1_rd_data),
.p1_rd_empty (c3_p1_rd_empty),
.p1_rd_count (c3_p1_rd_count),
.p1_rd_full (c3_p1_rd_full),
.p1_rd_overflow (c3_p1_rd_overflow),
.p1_rd_error (c3_p1_rd_error),
// User Port-2 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2 and Config-3
.p2_cmd_clk (c3_p2_cmd_clk),
.p2_cmd_en (c3_p2_cmd_en),
.p2_cmd_instr (c3_p2_cmd_instr),
.p2_cmd_bl (c3_p2_cmd_bl),
.p2_cmd_byte_addr (c3_p2_cmd_byte_addr),
.p2_cmd_full (c3_p2_cmd_full),
.p2_cmd_empty (c3_p2_cmd_empty),
// User Port-2 data write interface will be active only when the port is enabled in
// the port configurations Config-1 write direction, Config-2 and Config-3
.p2_wr_clk (c3_p2_wr_clk),
.p2_wr_en (c3_p2_wr_en),
.p2_wr_mask (c3_p2_wr_mask),
.p2_wr_data (c3_p2_wr_data),
.p2_wr_full (c3_p2_wr_full),
.p2_wr_count (c3_p2_wr_count),
.p2_wr_empty (c3_p2_wr_empty),
.p2_wr_underrun (c3_p2_wr_underrun),
.p2_wr_error (c3_p2_wr_error),
// User Port-2 data read interface will be active only when the port is enabled in
// the port configurations Config-1 read direction, Config-2 and Config-3
.p2_rd_clk (c3_p2_rd_clk),
.p2_rd_en (c3_p2_rd_en),
.p2_rd_data (c3_p2_rd_data),
.p2_rd_empty (c3_p2_rd_empty),
.p2_rd_count (c3_p2_rd_count),
.p2_rd_full (c3_p2_rd_full),
.p2_rd_overflow (c3_p2_rd_overflow),
.p2_rd_error (c3_p2_rd_error),
// User Port-3 command interface will be active only when the port is enabled in
// the port configurations Config-1 and Config-2
.p3_cmd_clk (c3_p3_cmd_clk),
.p3_cmd_en (c3_p3_cmd_en),
.p3_cmd_instr (c3_p3_cmd_instr),
.p3_cmd_bl (c3_p3_cmd_bl),
.p3_cmd_byte_addr (c3_p3_cmd_byte_addr),
.p3_cmd_full (c3_p3_cmd_full),
.p3_cmd_empty (c3_p3_cmd_empty),
// User Port-3 data write interface will be active only when the port is enabled in
// the port configurations Config-1 write direction and Config-2
.p3_wr_clk (c3_p3_wr_clk),
.p3_wr_en (c3_p3_wr_en),
.p3_wr_mask (c3_p3_wr_mask),
.p3_wr_data (c3_p3_wr_data),
.p3_wr_full (c3_p3_wr_full),
.p3_wr_count (c3_p3_wr_count),
.p3_wr_empty (c3_p3_wr_empty),
.p3_wr_underrun (c3_p3_wr_underrun),
.p3_wr_error (c3_p3_wr_error),
// User Port-3 data read interface will be active only when the port is enabled in
// the port configurations Config-1 read direction and Config-2
.p3_rd_clk (c3_p3_rd_clk),
.p3_rd_en (c3_p3_rd_en),
.p3_rd_data (c3_p3_rd_data),
.p3_rd_empty (c3_p3_rd_empty),
.p3_rd_count (c3_p3_rd_count),
.p3_rd_full (c3_p3_rd_full),
.p3_rd_overflow (c3_p3_rd_overflow),
.p3_rd_error (c3_p3_rd_error),
// User Port-4 command interface will be active only when the port is enabled in
// the port configuration Config-1
.p4_cmd_clk (c3_p4_cmd_clk),
.p4_cmd_en (c3_p4_cmd_en),
.p4_cmd_instr (c3_p4_cmd_instr),
.p4_cmd_bl (c3_p4_cmd_bl),
.p4_cmd_byte_addr (c3_p4_cmd_byte_addr),
.p4_cmd_full (c3_p4_cmd_full),
.p4_cmd_empty (c3_p4_cmd_empty),
// User Port-4 data write interface will be active only when the port is enabled in
// the port configuration Config-1 write direction
.p4_wr_clk (c3_p4_wr_clk),
.p4_wr_en (c3_p4_wr_en),
.p4_wr_mask (c3_p4_wr_mask),
.p4_wr_data (c3_p4_wr_data),
.p4_wr_full (c3_p4_wr_full),
.p4_wr_count (c3_p4_wr_count),
.p4_wr_empty (c3_p4_wr_empty),
.p4_wr_underrun (c3_p4_wr_underrun),
.p4_wr_error (c3_p4_wr_error),
// User Port-4 data read interface will be active only when the port is enabled in
// the port configuration Config-1 read direction
.p4_rd_clk (c3_p4_rd_clk),
.p4_rd_en (c3_p4_rd_en),
.p4_rd_data (c3_p4_rd_data),
.p4_rd_empty (c3_p4_rd_empty),
.p4_rd_count (c3_p4_rd_count),
.p4_rd_full (c3_p4_rd_full),
.p4_rd_overflow (c3_p4_rd_overflow),
.p4_rd_error (c3_p4_rd_error),
// User Port-5 command interface will be active only when the port is enabled in
// the port configuration Config-1
.p5_cmd_clk (c3_p5_cmd_clk),
.p5_cmd_en (c3_p5_cmd_en),
.p5_cmd_instr (c3_p5_cmd_instr),
.p5_cmd_bl (c3_p5_cmd_bl),
.p5_cmd_byte_addr (c3_p5_cmd_byte_addr),
.p5_cmd_full (c3_p5_cmd_full),
.p5_cmd_empty (c3_p5_cmd_empty),
// User Port-5 data write interface will be active only when the port is enabled in
// the port configuration Config-1 write direction
.p5_wr_clk (c3_p5_wr_clk),
.p5_wr_en (c3_p5_wr_en),
.p5_wr_mask (c3_p5_wr_mask),
.p5_wr_data (c3_p5_wr_data),
.p5_wr_full (c3_p5_wr_full),
.p5_wr_count (c3_p5_wr_count),
.p5_wr_empty (c3_p5_wr_empty),
.p5_wr_underrun (c3_p5_wr_underrun),
.p5_wr_error (c3_p5_wr_error),
// User Port-5 data read interface will be active only when the port is enabled in
// the port configuration Config-1 read direction
.p5_rd_clk (c3_p5_rd_clk),
.p5_rd_en (c3_p5_rd_en),
.p5_rd_data (c3_p5_rd_data),
.p5_rd_empty (c3_p5_rd_empty),
.p5_rd_count (c3_p5_rd_count),
.p5_rd_full (c3_p5_rd_full),
.p5_rd_overflow (c3_p5_rd_overflow),
.p5_rd_error (c3_p5_rd_error),
.selfrefresh_enter (1'b0),
.selfrefresh_mode (c3_selfrefresh_mode)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_pipe_lane_v6.v
// Version : 2.3
//--
//-- Description: PIPE per lane module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_pipe_lane_v6 #
(
parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
parameter TCQ = 1 // clock to out delay model
)
(
output wire [ 1:0] pipe_rx_char_is_k_o ,
output wire [15:0] pipe_rx_data_o ,
output wire pipe_rx_valid_o ,
output wire pipe_rx_chanisaligned_o ,
output wire [ 2:0] pipe_rx_status_o ,
output wire pipe_rx_phy_status_o ,
output wire pipe_rx_elec_idle_o ,
input wire pipe_rx_polarity_i ,
input wire pipe_tx_compliance_i ,
input wire [ 1:0] pipe_tx_char_is_k_i ,
input wire [15:0] pipe_tx_data_i ,
input wire pipe_tx_elec_idle_i ,
input wire [ 1:0] pipe_tx_powerdown_i ,
input wire [ 1:0] pipe_rx_char_is_k_i ,
input wire [15:0] pipe_rx_data_i ,
input wire pipe_rx_valid_i ,
input wire pipe_rx_chanisaligned_i ,
input wire [ 2:0] pipe_rx_status_i ,
input wire pipe_rx_phy_status_i ,
input wire pipe_rx_elec_idle_i ,
output wire pipe_rx_polarity_o ,
output wire pipe_tx_compliance_o ,
output wire [ 1:0] pipe_tx_char_is_k_o ,
output wire [15:0] pipe_tx_data_o ,
output wire pipe_tx_elec_idle_o ,
output wire [ 1:0] pipe_tx_powerdown_o ,
input wire pipe_clk ,
input wire rst_n
);
//******************************************************************//
// Reality check. //
//******************************************************************//
reg [ 1:0] pipe_rx_char_is_k_q ;
reg [15:0] pipe_rx_data_q ;
reg pipe_rx_valid_q ;
reg pipe_rx_chanisaligned_q ;
reg [ 2:0] pipe_rx_status_q ;
reg pipe_rx_phy_status_q ;
reg pipe_rx_elec_idle_q ;
reg pipe_rx_polarity_q ;
reg pipe_tx_compliance_q ;
reg [ 1:0] pipe_tx_char_is_k_q ;
reg [15:0] pipe_tx_data_q ;
reg pipe_tx_elec_idle_q ;
reg [ 1:0] pipe_tx_powerdown_q ;
reg [ 1:0] pipe_rx_char_is_k_qq ;
reg [15:0] pipe_rx_data_qq ;
reg pipe_rx_valid_qq ;
reg pipe_rx_chanisaligned_qq;
reg [ 2:0] pipe_rx_status_qq ;
reg pipe_rx_phy_status_qq ;
reg pipe_rx_elec_idle_qq ;
reg pipe_rx_polarity_qq ;
reg pipe_tx_compliance_qq ;
reg [ 1:0] pipe_tx_char_is_k_qq ;
reg [15:0] pipe_tx_data_qq ;
reg pipe_tx_elec_idle_qq ;
reg [ 1:0] pipe_tx_powerdown_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i;
assign pipe_rx_data_o = pipe_rx_data_i;
assign pipe_rx_valid_o = pipe_rx_valid_i;
assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_i;
assign pipe_rx_status_o = pipe_rx_status_i;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_i;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i;
assign pipe_rx_polarity_o = pipe_rx_polarity_i;
assign pipe_tx_compliance_o = pipe_tx_compliance_i;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i;
assign pipe_tx_data_o = pipe_tx_data_i;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_i;
end else if (PIPE_PIPELINE_STAGES == 1) begin
always @(posedge pipe_clk) begin
if (rst_n) begin
pipe_rx_char_is_k_q <= #TCQ 0;
pipe_rx_data_q <= #TCQ 0;
pipe_rx_valid_q <= #TCQ 0;
pipe_rx_chanisaligned_q <= #TCQ 0;
pipe_rx_status_q <= #TCQ 0;
pipe_rx_phy_status_q <= #TCQ 0;
pipe_rx_elec_idle_q <= #TCQ 0;
pipe_rx_polarity_q <= #TCQ 0;
pipe_tx_compliance_q <= #TCQ 0;
pipe_tx_char_is_k_q <= #TCQ 0;
pipe_tx_data_q <= #TCQ 0;
pipe_tx_elec_idle_q <= #TCQ 1'b1;
pipe_tx_powerdown_q <= #TCQ 2'b10;
end else begin
pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i;
pipe_rx_data_q <= #TCQ pipe_rx_data_i;
pipe_rx_valid_q <= #TCQ pipe_rx_valid_i;
pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i;
pipe_rx_status_q <= #TCQ pipe_rx_status_i;
pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i;
pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i;
pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i;
pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i;
pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i;
pipe_tx_data_q <= #TCQ pipe_tx_data_i;
pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i;
pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i;
end
end
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_q;
assign pipe_rx_data_o = pipe_rx_data_q;
assign pipe_rx_valid_o = pipe_rx_valid_q;
assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_q;
assign pipe_rx_status_o = pipe_rx_status_q;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_q;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_q;
assign pipe_rx_polarity_o = pipe_rx_polarity_q;
assign pipe_tx_compliance_o = pipe_tx_compliance_q;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_q;
assign pipe_tx_data_o = pipe_tx_data_q;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_q;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_q;
end else if (PIPE_PIPELINE_STAGES == 2) begin
always @(posedge pipe_clk) begin
if (rst_n) begin
pipe_rx_char_is_k_q <= #TCQ 0;
pipe_rx_data_q <= #TCQ 0;
pipe_rx_valid_q <= #TCQ 0;
pipe_rx_chanisaligned_q <= #TCQ 0;
pipe_rx_status_q <= #TCQ 0;
pipe_rx_phy_status_q <= #TCQ 0;
pipe_rx_elec_idle_q <= #TCQ 0;
pipe_rx_polarity_q <= #TCQ 0;
pipe_tx_compliance_q <= #TCQ 0;
pipe_tx_char_is_k_q <= #TCQ 0;
pipe_tx_data_q <= #TCQ 0;
pipe_tx_elec_idle_q <= #TCQ 1'b1;
pipe_tx_powerdown_q <= #TCQ 2'b10;
pipe_rx_char_is_k_qq <= #TCQ 0;
pipe_rx_data_qq <= #TCQ 0;
pipe_rx_valid_qq <= #TCQ 0;
pipe_rx_chanisaligned_qq <= #TCQ 0;
pipe_rx_status_qq <= #TCQ 0;
pipe_rx_phy_status_qq <= #TCQ 0;
pipe_rx_elec_idle_qq <= #TCQ 0;
pipe_rx_polarity_qq <= #TCQ 0;
pipe_tx_compliance_qq <= #TCQ 0;
pipe_tx_char_is_k_qq <= #TCQ 0;
pipe_tx_data_qq <= #TCQ 0;
pipe_tx_elec_idle_qq <= #TCQ 1'b1;
pipe_tx_powerdown_qq <= #TCQ 2'b10;
end else begin
pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i;
pipe_rx_data_q <= #TCQ pipe_rx_data_i;
pipe_rx_valid_q <= #TCQ pipe_rx_valid_i;
pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i;
pipe_rx_status_q <= #TCQ pipe_rx_status_i;
pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i;
pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i;
pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i;
pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i;
pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i;
pipe_tx_data_q <= #TCQ pipe_tx_data_i;
pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i;
pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i;
pipe_rx_char_is_k_qq <= #TCQ pipe_rx_char_is_k_q;
pipe_rx_data_qq <= #TCQ pipe_rx_data_q;
pipe_rx_valid_qq <= #TCQ pipe_rx_valid_q;
pipe_rx_chanisaligned_qq <= #TCQ pipe_rx_chanisaligned_q;
pipe_rx_status_qq <= #TCQ pipe_rx_status_q;
pipe_rx_phy_status_qq <= #TCQ pipe_rx_phy_status_q;
pipe_rx_elec_idle_qq <= #TCQ pipe_rx_elec_idle_q;
pipe_rx_polarity_qq <= #TCQ pipe_rx_polarity_q;
pipe_tx_compliance_qq <= #TCQ pipe_tx_compliance_q;
pipe_tx_char_is_k_qq <= #TCQ pipe_tx_char_is_k_q;
pipe_tx_data_qq <= #TCQ pipe_tx_data_q;
pipe_tx_elec_idle_qq <= #TCQ pipe_tx_elec_idle_q;
pipe_tx_powerdown_qq <= #TCQ pipe_tx_powerdown_q;
end
end
assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_qq;
assign pipe_rx_data_o = pipe_rx_data_qq;
assign pipe_rx_valid_o = pipe_rx_valid_qq;
assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_qq;
assign pipe_rx_status_o = pipe_rx_status_qq;
assign pipe_rx_phy_status_o = pipe_rx_phy_status_qq;
assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_qq;
assign pipe_rx_polarity_o = pipe_rx_polarity_qq;
assign pipe_tx_compliance_o = pipe_tx_compliance_qq;
assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_qq;
assign pipe_tx_data_o = pipe_tx_data_qq;
assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_qq;
assign pipe_tx_powerdown_o = pipe_tx_powerdown_qq;
end
endgenerate
endmodule
|
module prometheus_fx3_partial(
input rst_n,
input clk_100,
input partial_mode_selected,
input i_gpif_in_ch0_rdy_d,
input i_gpif_out_ch0_rdy_d,
output o_gpif_we_n_partial_,
output o_gpif_pkt_end_n_partial_,
output [31:0] data_out_partial
);
reg [2:0]current_partial_state;
reg [2:0]next_partial_state;
//parameters for PARTIAL mode state machine
parameter [2:0] partial_idle = 3'd0;
parameter [2:0] partial_wait_flagb = 3'd1;
parameter [2:0] partial_write = 3'd2;
parameter [2:0] partial_write_wr_delay = 3'd3;
parameter [2:0] partial_wait = 3'd4;
reg [3:0] strob_cnt;
reg strob;
reg [3:0] short_pkt_cnt;
reg [31:0]data_gen_partial;
reg o_gpif_pkt_end_n_prtl_;
assign o_gpif_we_n_partial_ = ((current_partial_state == partial_write) && (i_gpif_out_ch0_rdy_d == 1'b1)) ? 1'b0 : 1'b1;
//counters for short pkt
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
short_pkt_cnt <= 4'd0;
end else if(current_partial_state == partial_idle)begin
short_pkt_cnt <= 4'd0;
end else if((current_partial_state == partial_write))begin
short_pkt_cnt <= short_pkt_cnt + 1'b1;
end
end
//counter to generate the strob for PARTIAL
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
strob_cnt <= 4'd0;
end else if(current_partial_state == partial_idle)begin
strob_cnt <= 4'd0;
end else if(current_partial_state == partial_wait)begin
strob_cnt <= strob_cnt + 1'b1;
end
end
//Strob logic
always@(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
strob <= 1'b0;
end else if((current_partial_state == partial_wait) && (strob_cnt == 4'b0111)) begin
strob <= !strob;
end
end
always@(*)begin
if((partial_mode_selected) & (strob == 1'b1) & (short_pkt_cnt == 4'b1111))begin
o_gpif_pkt_end_n_prtl_ = 1'b0;
end else begin
o_gpif_pkt_end_n_prtl_ = 1'b1;
end
end
assign o_gpif_pkt_end_n_partial_ = o_gpif_pkt_end_n_prtl_;
//PARTIAL mode state machine
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
current_partial_state <= partial_idle;
end else begin
current_partial_state <= next_partial_state;
end
end
//PARTIAL mode state machine combo
always @(*)begin
next_partial_state = current_partial_state;
case(current_partial_state)
partial_idle:begin
if((partial_mode_selected) & (i_gpif_in_ch0_rdy_d == 1'b1))begin
next_partial_state = partial_wait_flagb;
end else begin
next_partial_state = partial_idle;
end
end
partial_wait_flagb :begin
if (i_gpif_out_ch0_rdy_d == 1'b1)begin
next_partial_state = partial_write;
end else begin
next_partial_state = partial_wait_flagb;
end
end
partial_write:begin
if((i_gpif_out_ch0_rdy_d == 1'b0) | ((strob == 1'b1) & (short_pkt_cnt == 4'b1111)))begin
next_partial_state = partial_write_wr_delay;
end else begin
next_partial_state = partial_write;
end
end
partial_write_wr_delay:begin
next_partial_state = partial_wait;
end
partial_wait:begin
if(strob_cnt == 4'b0111)begin
next_partial_state = partial_idle;
end else begin
next_partial_state = partial_wait;
end
end
endcase
end
//data generator counter for Partial mode
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
data_gen_partial <= 32'd0;
end else if((o_gpif_we_n_partial_ == 1'b0) & (partial_mode_selected)) begin
data_gen_partial <= data_gen_partial + 1;
end else if (!partial_mode_selected) begin
data_gen_partial <= 32'd0;
end
end
assign data_out_partial = data_gen_partial;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_creg.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp_creg
//
//-----------------------------------------------------------------------------
`include "sys.h"
`include "ctu.h"
// Clock Unit Register Addresses (0x96_0000_00xx)
// 00 CLK_DIV
// 08 CLK_CTL
// 10 CLK_DBG_INT
// 18 CLK_DLL_CTRL
// 28 CLK_JSYNC
// 30 CLK_DSYNC
// 38 CLK_DLL_BYPASS
// 40 CLK_VERSION
module ctu_clsp_creg (/*AUTOARG*/
// Outputs
reg_cdiv_0, reg_ddiv_0, reg_jdiv_0, reg_cdiv_vec, reg_ddiv_vec,
reg_jdiv_vec, stretch_cnt_vec, clk_stretch_cnt_val_6,
clk_stretch_cnt_val_odd, reg_div_cmult, reg_div_dmult, reg_div_jmult,
dsync_reg_init, dsync_reg_period, dsync_reg_rx0, dsync_reg_rx1,
dsync_reg_rx2, dsync_reg_tx0, dsync_reg_tx1, dsync_reg_tx2,
jsync_reg_init, jsync_reg_period, jsync_reg_rx0, jsync_reg_rx1,
jsync_reg_rx2, jsync_reg_tx0, jsync_reg_tx1, jsync_reg_tx2,
ctu_spc_const_maskid, frq_chng_pending_jl, ctu_ddr0_dll_delayctr_jl,
ctu_ddr1_dll_delayctr_jl, ctu_ddr2_dll_delayctr_jl,
ctu_ddr3_dll_delayctr_jl, de_dbginit_jl, a_dbginit_jl,
clsp_ucb_rd_ack_vld, clsp_ucb_rd_nack_vld, clsp_ucb_thr_id_out,
clsp_ucb_buf_id_out, clsp_ucb_data_out, dbgtrig_dly_cnt_val,
jbus_grst_jl_l, jbus_dbginit_jl_l, clk_stretch_trig,
ctu_dll3_byp_val_jl, ctu_dll2_byp_val_jl, ctu_dll1_byp_val_jl,
ctu_dll0_byp_val_jl, ctu_dll3_byp_l_jl, ctu_dll2_byp_l_jl,
ctu_dll1_byp_l_jl, ctu_dll0_byp_l_jl, stop_id_vld_jl,
stop_id_decoded, update_clkctrl_reg_jl, clkctrl_data_in_reg,
rd_clkctrl_reg_jl,
// Inputs
se, mask_major_id, mask_minor_id, ddr0_ctu_dll_lock,
ddr1_ctu_dll_lock, ddr2_ctu_dll_lock, ddr3_ctu_dll_lock,
ddr0_ctu_dll_overflow, ddr1_ctu_dll_overflow, ddr2_ctu_dll_overflow,
ddr3_ctu_dll_overflow, jbus_clk, rst_l, io_pwron_rst_l, start_clk_jl,
start_clk_early_jl, a_grst_jl, io_clk_stretch, clsp_ctrl_rd_bus_cl,
shadreg_div_jmult, de_grst_jsync_edge, de_dbginit_jsync_edge,
ucb_clsp_rd_req_vld, ucb_clsp_wr_req_vld, ucb_clsp_addr_in,
ucb_clsp_data_in, ucb_clsp_thr_id_in, ucb_clsp_buf_id_in,
bypclksel, jbus_mult_rst_l, jtag_clsp_stop_id_vld,
jtag_clsp_stop_id, dll3_ctu_ctrl, dll2_ctu_ctrl, dll1_ctu_ctrl,
dll0_ctu_ctrl
);
parameter REG_WIDTH=64;
parameter DBG_CNT= 5'd31;
// to clkgn block
output reg_cdiv_0;
output reg_ddiv_0;
output reg_jdiv_0;
output [14:0] reg_cdiv_vec;
output [14:0] reg_ddiv_vec;
output [14:0] reg_jdiv_vec;
output [14:0] stretch_cnt_vec;
output clk_stretch_cnt_val_6;
output clk_stretch_cnt_val_odd;
output [13:0] reg_div_cmult; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [9:0] reg_div_dmult; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [9:0] reg_div_jmult; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [4:0] dsync_reg_init; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [4:0] dsync_reg_period; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [1:0] dsync_reg_rx0; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [1:0] dsync_reg_rx1; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [1:0] dsync_reg_rx2; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [4:0] dsync_reg_tx0; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [4:0] dsync_reg_tx1; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [4:0] dsync_reg_tx2; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [4:0] jsync_reg_init; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [4:0] jsync_reg_period; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [1:0] jsync_reg_rx0; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [1:0] jsync_reg_rx1; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [1:0] jsync_reg_rx2; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [4:0] jsync_reg_tx0; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [4:0] jsync_reg_tx1; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [4:0] jsync_reg_tx2; // To u_ctu_clsp_clkgn_shadreg of ctu_clsp_clkgn_shadreg.v
output [7:0] ctu_spc_const_maskid;
// to rstctrl
// output clk_dram_freq_200_sel;
output frq_chng_pending_jl;
// to ddr
output [2:0] ctu_ddr0_dll_delayctr_jl; // ddr0 deskew data
output [2:0] ctu_ddr1_dll_delayctr_jl; // ddr1 deskew data
output [2:0] ctu_ddr2_dll_delayctr_jl; // ddr2 deskew data
output [2:0] ctu_ddr3_dll_delayctr_jl; // ddr3 deskew data
output de_dbginit_jl;
output a_dbginit_jl;
input se;
input [3:0] mask_major_id;
input [3:0] mask_minor_id;
input ddr0_ctu_dll_lock; // ddr0 deskew lock
input ddr1_ctu_dll_lock; // ddr1 deskew lock
input ddr2_ctu_dll_lock; // ddr2 deskew lock
input ddr3_ctu_dll_lock; // ddr3 deskew lock
input ddr0_ctu_dll_overflow; // ddr0 deskew overflow
input ddr1_ctu_dll_overflow; // ddr0 deskew overflow
input ddr2_ctu_dll_overflow; // ddr0 deskew overflow
input ddr3_ctu_dll_overflow; // ddr0 deskew overflow
//output to ucb
output clsp_ucb_rd_ack_vld;
output clsp_ucb_rd_nack_vld;
output [`UCB_THR_HI-`UCB_THR_LO:0] clsp_ucb_thr_id_out;
output [`UCB_BUF_HI-`UCB_BUF_LO:0] clsp_ucb_buf_id_out;
output [REG_WIDTH-1:0] clsp_ucb_data_out;
output [4:0] dbgtrig_dly_cnt_val;
output jbus_grst_jl_l;
output jbus_dbginit_jl_l;
output clk_stretch_trig;
//global inputs
input jbus_clk;
input rst_l;
input io_pwron_rst_l;
input start_clk_jl;
input start_clk_early_jl;
input a_grst_jl;
input io_clk_stretch;
input [63:0] clsp_ctrl_rd_bus_cl;
// sync edge signals
input [9:0] shadreg_div_jmult;
input de_grst_jsync_edge;
input de_dbginit_jsync_edge;
//inputs from ucb
input ucb_clsp_rd_req_vld;
input ucb_clsp_wr_req_vld;
input [`UCB_ADDR_HI-`UCB_ADDR_LO:0] ucb_clsp_addr_in;
input [`UCB_DATA_HI-`UCB_DATA_LO:0] ucb_clsp_data_in;
input [`UCB_THR_HI-`UCB_THR_LO:0] ucb_clsp_thr_id_in;
input [`UCB_BUF_HI-`UCB_BUF_LO:0] ucb_clsp_buf_id_in;
// jtag stop id
input bypclksel;
input jbus_mult_rst_l;
input jtag_clsp_stop_id_vld;
input [5:0] jtag_clsp_stop_id;
input [4:0] dll3_ctu_ctrl;
input [4:0] dll2_ctu_ctrl;
input [4:0] dll1_ctu_ctrl;
input [4:0] dll0_ctu_ctrl;
output [4:0] ctu_dll3_byp_val_jl;
output [4:0] ctu_dll2_byp_val_jl;
output [4:0] ctu_dll1_byp_val_jl;
output [4:0] ctu_dll0_byp_val_jl;
output ctu_dll3_byp_l_jl;
output ctu_dll2_byp_l_jl;
output ctu_dll1_byp_l_jl;
output ctu_dll0_byp_l_jl;
output stop_id_vld_jl;
output [`CCTRLSM_MAX_ST-1:0] stop_id_decoded;
output update_clkctrl_reg_jl;
output [63:0] clkctrl_data_in_reg;
output rd_clkctrl_reg_jl;
wire mult_rst_l;
wire se_bar;
// Wires
wire ucb_clsp_rd_req_vld_reg;
wire ucb_clsp_wr_req_vld_reg;
wire [`UCB_THR_HI-`UCB_THR_LO:0] ucb_clsp_thr_id_in_reg;
wire [`UCB_BUF_HI-`UCB_BUF_LO:0] ucb_clsp_buf_id_in_reg;
wire [`UCB_ADDR_HI-`UCB_ADDR_LO:0] ucb_clsp_addr_in_reg;
wire [`UCB_DATA_HI-`UCB_DATA_LO:0] ucb_clsp_data_in_reg;
wire [`UCB_ADDR_HI-`UCB_ADDR_LO:0] ucb_clsp_addr_in_reg_nxt;
wire [`UCB_DATA_HI-`UCB_DATA_LO:0] ucb_clsp_data_in_reg_nxt;
wire [`UCB_DATA_HI-`UCB_DATA_LO:0] ucb_data_out_nxt;
// address decoding
wire clsp_div_sel;
wire clsp_ctrl_sel;
wire clsp_dbg_init_sel;
wire clsp_dll_ctrl_sel;
wire clsp_jsync_sel;
wire clsp_dsync_sel;
wire clsp_upper_addr_vld;
wire clsp_lower_addr_vld;
// ucbif signals
wire clsp_wr_req_nxt;
wire clsp_wr_req_vld;
wire clsp_wr_req_vld_d;
wire clsp_rd_req_vld_nxt;
wire clsp_rd_req_vld;
wire clsp_rd_req_vld_d;
wire clsp_rd_req_vld_1sht;
wire rd_nack_vld_nxt;
wire rd_nack_vld;
wire rd_nack_vld_d;
wire rd_nack_vld_1sht;
// clkdiv reg
wire [13:0] reg_div_cmult_nxt;
wire [13:0] reg_div_cmult;
wire [9:0] reg_div_dmult_nxt;
wire [9:0] reg_div_dmult;
wire [9:0] reg_div_jmult_nxt;
wire [9:0] reg_div_jmult;
wire frq_chng_pending_nxt;
//wire clk_dram_freq_200_sel_nxt;
//wire clk_dram_freq_200_sel;
wire [4:0] reg_jdiv_nxt;
wire [4:0] reg_ddiv_nxt;
wire [4:0] reg_cdiv_nxt;
wire [4:0] reg_jdiv;
wire [4:0] reg_ddiv;
wire [4:0] reg_cdiv;
wire frq_chng_pending_jl;
wire clsp_div_rd_vld;
wire [63:0] clsp_div_rd_bus;
// clkctrl reg
wire [63:0] clsp_ctrl_rd_bus;
// reg ddl_ctrl
wire [4:0] dbgtrig_dly_cnt_val_nxt;
wire [4:0] dbgtrig_dly_cnt_val;
wire clk_stretch_cnt_val_6_nxt;
wire [4:0] clk_stretch_cnt_val;
wire [4:0] clk_stretch_cnt_val_nxt;
wire [2:0] clsp_ddr3_dll_delayctr_jl;
wire [2:0] clsp_ddr3_dll_delay_nxt;
wire [2:0] clsp_ddr2_dll_delayctr_jl;
wire [2:0] clsp_ddr2_dll_delay_nxt;
wire [2:0] clsp_ddr1_dll_delayctr_jl;
wire [2:0] clsp_ddr1_dll_delay_nxt;
wire [2:0] clsp_ddr0_dll_delayctr_jl;
wire [2:0] clsp_ddr0_dll_delay_nxt;
wire ddr0_dll_lock_jl;
wire ddr1_dll_lock_jl;
wire ddr2_dll_lock_jl;
wire ddr3_dll_lock_jl;
wire ddr0_dll_overflow_jl;
wire ddr1_dll_overflow_jl;
wire ddr2_dll_overflow_jl;
wire ddr3_dll_overflow_jl;
wire ddr0_dll_lock_nxt;
wire ddr1_dll_lock_nxt;
wire ddr2_dll_lock_nxt;
wire ddr3_dll_lock_nxt;
wire ddr0_dll_overflow_nxt;
wire ddr1_dll_overflow_nxt;
wire ddr2_dll_overflow_nxt;
wire ddr3_dll_overflow_nxt;
wire ddr0_dll_lock;
wire ddr1_dll_lock;
wire ddr2_dll_lock;
wire ddr3_dll_lock;
wire ddr0_dll_overflow;
wire ddr1_dll_overflow;
wire ddr2_dll_overflow;
wire ddr3_dll_overflow;
wire clsp_dll_ctrl_rd_vld;
wire [63:0] clsp_dll_ctrl_rd_bus;
// reg jsync
wire [1:0] jsync_reg_rx2_nxt;
wire [1:0] jsync_reg_rx2;
wire [1:0] jsync_reg_rx1_nxt;
wire [1:0] jsync_reg_rx1;
wire [1:0] jsync_reg_rx0_nxt;
wire [1:0] jsync_reg_rx0;
wire [4:0] jsync_reg_tx2_nxt;
wire [4:0] jsync_reg_tx2;
wire [4:0] jsync_reg_tx1_nxt;
wire [4:0] jsync_reg_tx1;
wire [4:0] jsync_reg_tx0_nxt;
wire [4:0] jsync_reg_tx0;
wire [4:0] jsync_reg_period_nxt;
wire [4:0] jsync_reg_period;
wire [4:0] jsync_reg_init_nxt;
wire [4:0] jsync_reg_init;
wire clsp_jsync_rd_vld;
wire [63:0] clsp_jsync_rd_bus;
// reg dsync
wire [1:0] dsync_reg_rx2_nxt;
wire [1:0] dsync_reg_rx2;
wire [1:0] dsync_reg_rx1_nxt;
wire [1:0] dsync_reg_rx1;
wire [1:0] dsync_reg_rx0_nxt;
wire [1:0] dsync_reg_rx0;
wire [4:0] dsync_reg_tx2_nxt;
wire [4:0] dsync_reg_tx2;
wire [4:0] dsync_reg_tx1_nxt;
wire [4:0] dsync_reg_tx1;
wire [4:0] dsync_reg_tx0_nxt;
wire [4:0] dsync_reg_tx0;
wire [4:0] dsync_reg_period_nxt;
wire [4:0] dsync_reg_period;
wire [4:0] dsync_reg_init_nxt;
wire [4:0] dsync_reg_init;
wire clsp_dsync_rd_vld;
wire [63:0] clsp_dsync_rd_bus;
// read bus
wire [63:0] data_out;
wire [63:0] ucb_data_out;
wire ucb_rd_ack_vld;
// dbginit reg
wire dbginit_1sht;
wire [4:0] dbg_init_cnt_plus1;
wire [4:0] dbg_init_cnt_nxt;
wire [4:0] dbg_init_cnt;
wire dbg_init_cnt_dn;
wire de_dbginit_jl_nxt;
wire a_dbginit_jl_nxt;
wire jbus_grst_jl_l_nxt;
wire jbus_dbginit_jl_l_nxt;
wire a_dbginit_jl;
wire rd_clkctrl_reg_nxt;
wire rd_clkctrl_reg_jl;
wire update_clkctrl_reg_nxt;
wire update_clkctrl_reg_jl;
// sync edge count
wire [9:0] lcm_cnt_minus_1;
wire [9:0] lcm_cnt_nxt;
wire [9:0] lcm_cnt;
wire lcm_cnt_zero;
wire cnt_ld;
wire grst_en_window_nxt;
wire grst_en_window;
wire dbginit_en_window;
wire dbginit_en_window_nxt;
wire dbginit_rd_vld_window_nxt;
wire dbginit_rd_vld_window;
wire dbginit_rd_vld;
wire ucb_rd_ack_vld_nxt;
wire [`UCB_THR_HI-`UCB_THR_LO:0] ucb_clsp_thr_id_in_nxt;
wire [`UCB_BUF_HI-`UCB_BUF_LO:0] ucb_clsp_buf_id_in_nxt;
reg [14:0] cdiv_vec_nxt;
reg [14:0] jdiv_vec_nxt;
reg [14:0] ddiv_vec_nxt;
reg [14:0] stretch_cnt_vec_nxt;
// jtag stop id
wire [5:0] new_id_nxt;
wire [5:0] new_id;
reg [`CCTRLSM_MAX_ST-1:0] jtag_clsp_stop_id_decoded;
wire jtag_clsp_stop_id_vld_jl;
wire jtag_clsp_stop_id_vld_jl_dly_l;
wire jtag_clsp_stop_id_vld_1sht;
wire stop_id_vld_dly;
// dll bypass
wire clsp_dll_byp_sel;
wire ctu_dll3_byp_l_nxt;
wire ctu_dll3_byp_l_jl;
wire ctu_dll2_byp_l_nxt;
wire ctu_dll2_byp_l_jl;
wire ctu_dll1_byp_l_nxt;
wire ctu_dll1_byp_l_jl;
wire ctu_dll0_byp_l_nxt;
wire ctu_dll0_byp_l_jl;
wire [4:0] ctu_dll3_byp_val_nxt;
wire [4:0] ctu_dll2_byp_val_nxt;
wire [4:0] ctu_dll1_byp_val_nxt;
wire [4:0] ctu_dll0_byp_val_nxt;
wire clsp_dll_byp_rd_vld;
wire [63:0] clsp_dll_byp_rd_bus;
wire [4:0] dll3_ctu_ctrl_jl;
wire [4:0] dll2_ctu_ctrl_jl;
wire [4:0] dll1_ctu_ctrl_jl;
wire [4:0] dll0_ctu_ctrl_jl;
// version register
wire [15:0] manufacture_code;
wire [15:0] impl_code;
wire [7:0] mask_id;
wire [2:0] max_glb_reg;
wire [7:0] max_trap_level;
wire [4:0] max_cwp;
wire [63:0] clsp_version_rd_bus;
wire clsp_version_sel;
wire clsp_version_rd_vld;
wire bypclksel_sync;
wire [14:0] stretch_cnt_vec_pre;
//-----------------------------------------------------------------------
//
// Synchronizer
//
//-----------------------------------------------------------------------
// assuming all signals are level
ctu_synchronizer #(5) u_dll0_ctu_ctrl(
.presyncdata(dll0_ctu_ctrl),
.syncdata (dll0_ctu_ctrl_jl),
.clk(jbus_clk)
);
ctu_synchronizer #(5) u_dll1_ctu_ctrl(
.presyncdata(dll1_ctu_ctrl),
.syncdata (dll1_ctu_ctrl_jl),
.clk(jbus_clk)
);
ctu_synchronizer #(5) u_dll2_ctu_ctrl(
.presyncdata(dll2_ctu_ctrl),
.syncdata (dll2_ctu_ctrl_jl),
.clk(jbus_clk)
);
ctu_synchronizer #(5) u_dll3_ctu_ctrl(
.presyncdata(dll3_ctu_ctrl),
.syncdata (dll3_ctu_ctrl_jl),
.clk(jbus_clk)
);
ctu_synchronizer u_ddr0_ctu_dll_lock(
.presyncdata(ddr0_ctu_dll_lock),
.syncdata (ddr0_dll_lock_jl),
.clk(jbus_clk)
);
ctu_synchronizer u_ddr1_ctu_dll_lock(
.presyncdata(ddr1_ctu_dll_lock),
.syncdata (ddr1_dll_lock_jl),
.clk(jbus_clk)
);
ctu_synchronizer u_ddr2_ctu_dll_lock(
.presyncdata(ddr2_ctu_dll_lock),
.syncdata (ddr2_dll_lock_jl),
.clk(jbus_clk)
);
ctu_synchronizer u_ddr3_ctu_dll_lock(
.presyncdata(ddr3_ctu_dll_lock),
.syncdata (ddr3_dll_lock_jl),
.clk(jbus_clk)
);
ctu_synchronizer u_ddr0_ctu_dll_overflow(
.presyncdata(ddr0_ctu_dll_overflow),
.syncdata (ddr0_dll_overflow_jl),
.clk(jbus_clk)
);
ctu_synchronizer u_ddr1_ctu_dll_overflow(
.presyncdata(ddr1_ctu_dll_overflow),
.syncdata (ddr1_dll_overflow_jl),
.clk(jbus_clk)
);
ctu_synchronizer u_ddr2_ctu_dll_overflow(
.presyncdata(ddr2_ctu_dll_overflow),
.syncdata (ddr2_dll_overflow_jl),
.clk(jbus_clk)
);
ctu_synchronizer u_ddr3_ctu_dll_overflow(
.presyncdata(ddr3_ctu_dll_overflow),
.syncdata (ddr3_dll_overflow_jl),
.clk(jbus_clk)
);
// io_tck -> jbus_clk
ctu_synchronizer u_jtag_clsp_stop_id_vld(
.presyncdata(jtag_clsp_stop_id_vld),
.syncdata (jtag_clsp_stop_id_vld_jl),
.clk(jbus_clk)
);
ctu_synchronizer u_bypclksel(
.presyncdata( bypclksel),
.syncdata ( bypclksel_sync),
.clk(jbus_clk)
);
//---------------------------------------------------------------------------
//
// output assignments
//
//---------------------------------------------------------------------------
dffrl_async_ns u_clk_stretch_trig (.din(io_clk_stretch & start_clk_jl),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (clk_stretch_trig)
);
//---------------------------------------------------------------------------
//
// UCB interface logic
//
//---------------------------------------------------------------------------
assign clsp_ucb_rd_ack_vld = ucb_rd_ack_vld;
assign clsp_ucb_rd_nack_vld = rd_nack_vld_1sht;
assign clsp_ucb_data_out= ucb_data_out [63:0];
assign reg_cdiv_0 = reg_cdiv[0];
assign reg_jdiv_0 = reg_jdiv[0];
assign reg_ddiv_0 = reg_ddiv[0];
assign ctu_ddr0_dll_delayctr_jl = clsp_ddr0_dll_delayctr_jl;
assign ctu_ddr1_dll_delayctr_jl = clsp_ddr1_dll_delayctr_jl;
assign ctu_ddr2_dll_delayctr_jl = clsp_ddr2_dll_delayctr_jl;
assign ctu_ddr3_dll_delayctr_jl = clsp_ddr3_dll_delayctr_jl;
//---------------------------------------------------------------------------
//
// Address decoding:
//
//---------------------------------------------------------------------------
assign clsp_ucb_thr_id_out = ucb_clsp_thr_id_in_reg;
assign clsp_ucb_buf_id_out = ucb_clsp_buf_id_in_reg;
assign ucb_clsp_thr_id_in_nxt = ucb_clsp_rd_req_vld & rst_l ?
ucb_clsp_thr_id_in : ucb_clsp_thr_id_in_reg;
dffrl_async_ns #(`UCB_THR_HI-`UCB_THR_LO+1) u_ucb_clsp_thr_id_in(.din(ucb_clsp_thr_id_in_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ucb_clsp_thr_id_in_reg)
);
assign ucb_clsp_buf_id_in_nxt = ucb_clsp_rd_req_vld & rst_l ?
ucb_clsp_buf_id_in : ucb_clsp_buf_id_in_reg;
dffrl_async_ns #(`UCB_BUF_HI-`UCB_BUF_LO+1) u_ucb_clsp_buf_id_in_reg(.din(ucb_clsp_buf_id_in_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ucb_clsp_buf_id_in_reg)
);
dffrl_async_ns u_ucb_clsp_rd_req_vld_tmp (.din( ucb_clsp_rd_req_vld),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ucb_clsp_rd_req_vld_reg)
);
assign ucb_clsp_data_in_reg_nxt = (ucb_clsp_rd_req_vld | ucb_clsp_wr_req_vld) & rst_l ?
ucb_clsp_data_in : ucb_clsp_data_in_reg;
dffrl_async_ns #(`UCB_DATA_HI-`UCB_DATA_LO+1) u_ucb_clsp_data_in_tmp(.din( ucb_clsp_data_in_reg_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ucb_clsp_data_in_reg)
);
assign ucb_clsp_addr_in_reg_nxt = (ucb_clsp_rd_req_vld | ucb_clsp_wr_req_vld) & rst_l ?
ucb_clsp_addr_in : ucb_clsp_addr_in_reg;
dffrl_async_ns #(`UCB_ADDR_HI-`UCB_ADDR_LO+1) u_ucb_clsp_addr_in_tmp(.din( ucb_clsp_addr_in_reg_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ucb_clsp_addr_in_reg)
);
dffrl_async_ns u_ucb_clsp_wr_req_vld_reg (.din( ucb_clsp_wr_req_vld),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ucb_clsp_wr_req_vld_reg)
);
assign clsp_upper_addr_vld = ucb_clsp_addr_in_reg[`UCB_ADDR_HI-`UCB_ADDR_LO:`CLK_ADDR_HI+1] == `CLK_UPPER_ADDR;
assign clsp_div_sel = ucb_clsp_addr_in_reg[`CLK_ADDR_HI:0] == `CLK_DIV_ADDR;
assign clsp_ctrl_sel = ucb_clsp_addr_in_reg[`CLK_ADDR_HI:0] == `CLK_CTRL_ADDR;
assign clsp_dbg_init_sel = ucb_clsp_addr_in_reg[`CLK_ADDR_HI:0] == `CLK_DBG_INIT_ADDR;
assign clsp_dll_ctrl_sel = ucb_clsp_addr_in_reg[`CLK_ADDR_HI:0] == `CLK_DLL_CTRL_ADDR;
assign clsp_jsync_sel = ucb_clsp_addr_in_reg[`CLK_ADDR_HI:0] == `CLK_JSYNC_ADDR;
assign clsp_dsync_sel = ucb_clsp_addr_in_reg[`CLK_ADDR_HI:0] == `CLK_DSYNC_ADDR;
assign clsp_dll_byp_sel = ucb_clsp_addr_in_reg[`CLK_ADDR_HI:0] == `CLK_DLL_BYP_ADDR;
assign clsp_version_sel = ucb_clsp_addr_in_reg[`CLK_ADDR_HI:0] == `CLK_VERSION_ADDR;
assign clsp_lower_addr_vld = clsp_div_sel | clsp_ctrl_sel | clsp_dbg_init_sel | clsp_dll_byp_sel | clsp_version_sel |
clsp_dll_ctrl_sel | clsp_jsync_sel | clsp_dsync_sel ;
//---------------------------------------------------------------------------
//
// UCB IF signals
//
//---------------------------------------------------------------------------
assign clsp_wr_req_nxt = clsp_upper_addr_vld & ucb_clsp_wr_req_vld_reg ;
dffrl_async_ns u_clsp_wr_req_vld_ff (.din( clsp_wr_req_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (clsp_wr_req_vld)
);
dff_ns u_clsp_wr_req_vld_d (.din( clsp_wr_req_vld),
.clk(jbus_clk),
.q (clsp_wr_req_vld_d)
);
assign clsp_rd_req_vld_nxt = clsp_upper_addr_vld & ucb_clsp_rd_req_vld_reg;
dffrl_async_ns u_clsp_rd_req_vld_ff (.din( clsp_rd_req_vld_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (clsp_rd_req_vld)
);
dffrl_async_ns u_clsp_rd_req_vld_d_ff (.din( clsp_rd_req_vld),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (clsp_rd_req_vld_d)
);
assign clsp_rd_req_vld_1sht = clsp_rd_req_vld & ~clsp_rd_req_vld_d ;
//assign rd_nack_vld_nxt = clsp_upper_addr_vld & ~clsp_lower_addr_vld & ucb_clsp_rd_req_vld_reg & rst_l;
assign rd_nack_vld_nxt = ~(clsp_upper_addr_vld & clsp_lower_addr_vld) & ucb_clsp_rd_req_vld_reg & rst_l;
dffrl_async_ns u_clsp_rd_nack_vld_ff (.din( rd_nack_vld_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (rd_nack_vld)
);
dffrl_async_ns u_clsp_rd_nack_vld_d_ff (.din( rd_nack_vld),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (rd_nack_vld_d)
);
assign rd_nack_vld_1sht = rd_nack_vld & ~rd_nack_vld_d;
//---------------------------------------------------------------------------
//
// Register : Clock divide
//
//---------------------------------------------------------------------------
// MULT 41:28 (default 16)
// CHANGE 26 (default 0)
// DRAM200 25 (default 0 ; POR only)
// DDIV 24:19 (default 010000 ; POR only )
// JDIV 12:7 (default 010000 ; POR only)
// CDIV 5:0 (default 000100 ; POR only)
assign reg_div_dmult_nxt = clsp_div_sel & clsp_wr_req_vld_d & rst_l?
ucb_clsp_data_in_reg[61:52]
: reg_div_dmult;
assign reg_div_jmult_nxt = clsp_div_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[51:42]
: reg_div_jmult;
assign reg_div_cmult_nxt = clsp_div_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[41:28]
: reg_div_cmult;
assign reg_ddiv_nxt = clsp_div_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[20:16]
: reg_ddiv;
assign reg_jdiv_nxt = clsp_div_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[12:8]
: reg_jdiv;
assign reg_cdiv_nxt = clsp_div_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[4:0]
: reg_cdiv;
assign frq_chng_pending_nxt = ~rst_l ? 1'b0:
clsp_div_sel & clsp_wr_req_vld_d? ucb_clsp_data_in_reg[26]:
frq_chng_pending_jl;
dffrl_async_ns u_frq_chng_pending_jl_ff (.din(frq_chng_pending_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (frq_chng_pending_jl)
);
dffrl_async_ns #(2) u_reg_cdiv_4_3_ff (.din( reg_cdiv_nxt[4:3]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_cdiv[4:3])
);
dffsl_async_ns u_reg_cdiv_2_ff (.din( reg_cdiv_nxt[2]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_cdiv[2])
);
dffrl_async_ns #(2) u_reg_cdiv_1_0_ff (.din( reg_cdiv_nxt[1:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_cdiv[1:0])
);
// default to 0010_0000 (32)
dffrl_async_ns #(8) u_reg_div_cmult_13_6_ff (.din(reg_div_cmult_nxt[13:6]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_div_cmult[13:6])
);
dffsl_async_ns u_reg_div_cmult_5_ff (.din( reg_div_cmult_nxt[5]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_div_cmult[5])
);
dffrl_async_ns #(5) u_reg_div_cmult_4_0_ff (.din( reg_div_cmult_nxt[4:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_div_cmult[4:0])
);
// default to 0000_1000 (8)
dffrl_async_ns #(6) u_reg_div_dmult_9_4_ff (.din(reg_div_dmult_nxt[9:4]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_div_dmult[9:4])
);
dffsl_async_ns u_reg_div_dmult_3_ff (.din( reg_div_dmult_nxt[3]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_div_dmult[3])
);
dffrl_async_ns #(3) u_reg_div_dmult_2_0_ff (.din( reg_div_dmult_nxt[2:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_div_dmult[2:0])
);
// default to 0000_1000 (8)
dffrl_async_ns #(6) u_reg_div_jmult_9_4_ff (.din(reg_div_jmult_nxt[9:4]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_div_jmult[9:4])
);
dffsl_async_ns u_reg_div_jmult_3_ff (.din( reg_div_jmult_nxt[3]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_div_jmult[3])
);
dffrl_async_ns #(3) u_reg_div_jmult_2_0_ff (.din( reg_div_jmult_nxt[2:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_div_jmult[2:0])
);
// default to 010000
dffsl_async_ns u_reg_jdiv_4_ff (.din( reg_jdiv_nxt[4]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_jdiv[4])
);
dffrl_async_ns #(4) u_reg_jdiv_3_0_ff (.din( reg_jdiv_nxt[3:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_jdiv[3:0])
);
// default to 010000
dffsl_async_ns u_reg_ddiv_4_ff (.din( reg_ddiv_nxt[4]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_ddiv[4])
);
dffrl_async_ns #(4) u_reg_ddiv_3_0_ff (.din( reg_ddiv_nxt[3:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_ddiv[3:0])
);
assign clsp_div_rd_vld = clsp_rd_req_vld_1sht & clsp_div_sel;
assign clsp_div_rd_bus = { 2'b00,
reg_div_dmult[9:0],
reg_div_jmult[9:0],
reg_div_cmult[13:0],
1'b0,
frq_chng_pending_jl,
5'b00000,
reg_ddiv[4:0],
3'b000,
reg_jdiv[4:0],
3'b000,
reg_cdiv[4:0]} & { 64 {clsp_div_rd_vld}};
//---------------------------------------------------------------------------
//
// Register : Clock control
//
//---------------------------------------------------------------------------
// All registers all located on clkctrl block ; cmp_clk domain
assign update_clkctrl_reg_nxt = clsp_ctrl_sel & clsp_wr_req_vld_d & rst_l;
dffrl_async_ns u_update_clkctrl_reg(.din(update_clkctrl_reg_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (update_clkctrl_reg_jl)
);
dffe_ns #(64) u_rd_ucb_clsp_data_in_reg (.din(ucb_clsp_data_in_reg),
.clk(jbus_clk),
.en(update_clkctrl_reg_nxt),
.q (clkctrl_data_in_reg)
);
assign rd_clkctrl_reg_nxt = clsp_rd_req_vld_1sht & clsp_ctrl_sel & rst_l;
// Guarantee data is stable after 2 jbus_clk ; no need to get an ack
// clsp_ctrl_rd_bus_cl needs to hold for 2 cycles after rd_clkctrl_reg_jl is asserted
dffrl_async_ns u_rd_clkctrl_reg(.din(rd_clkctrl_reg_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (rd_clkctrl_reg_jl)
);
dffrl_async_ns u_rd_clkctrl_reg_dly (.din(rd_clkctrl_reg_jl),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (rd_clkctrl_reg_dly )
);
dffrl_async_ns u_clsp_ctrl_rd_vld (.din(rd_clkctrl_reg_dly),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (clsp_ctrl_rd_vld)
);
assign clsp_ctrl_rd_bus = clsp_ctrl_rd_bus_cl & {64 {clsp_ctrl_rd_vld}};
//---------------------------------------------------------------------------
//
// Register : dbg_init
//
//---------------------------------------------------------------------------
assign dbginit_1sht = clsp_rd_req_vld_1sht & clsp_dbg_init_sel;
//---------------------------------------------------------------------------
//
// dbginit assertion count
//
//---------------------------------------------------------------------------
// dbginit needs to be asserted more than 32 jbus cycles
assign dbg_init_cnt_plus1 = dbg_init_cnt + 5'b00001;
// We should not have another read (dbginit_1sht) while dbginit_l is asserted
// (rd_ack is not returned yet)
assign dbg_init_cnt_nxt = dbginit_1sht ? 5'b00000:
a_dbginit_jl & ~dbg_init_cnt_dn ? dbg_init_cnt_plus1:
dbg_init_cnt;
dffrl_async_ns #(5) u_dbg_init_cnt (.din( dbg_init_cnt_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (dbg_init_cnt)
);
assign dbg_init_cnt_dn = ( dbg_init_cnt == DBG_CNT);
//---------------------------------------------------------------------------
//
// dbginit assertion count
//
//---------------------------------------------------------------------------
// rd_ack should be returned only when dbginit_rd_vld_window is set to 1
// jbus_dbginit_jl_l is the actually dbginit signal (waited for coin_edge)
// rd_ack is returned after jbus_dbginit_jl_l is deasserted on coincidenet edge
// dbginit_rd_vld_window is 1 when a read to register
// dbginit_rd_vld_window is set to 0 when jbus_dbginit_jl_l is de-asserted and on coincident edge
// ECO 6534 TO_1_1
assign dbginit_rd_vld_window_nxt =
dbginit_1sht? 1'b1:
lcm_cnt_zero & de_dbginit_jl & jbus_dbginit_jl_l? 1'b0:
//lcm_cnt_zero & de_dbginit_jl & jbus_dbginit_jl_l? 1'b0:
//dbginit_1sht? 1'b1:
dbginit_rd_vld_window;
dffrl_async_ns u_dbginit_rd_vld_window(.din(dbginit_rd_vld_window_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q ( dbginit_rd_vld_window)
);
// rd ack returned to iob on coincident edge
assign dbginit_rd_vld = dbginit_rd_vld_window & lcm_cnt_zero & de_dbginit_jl & jbus_dbginit_jl_l ;
//---------------------------------------------------------------------------
//
// Generate ctrl signal to shadreg block
// All controls of assertion and de-assertion of dbginit signal are originated from cmp_clk domain
//
//---------------------------------------------------------------------------
assign de_dbginit_jl_nxt = dbginit_1sht? 1'b0: // read to register
dbg_init_cnt_dn ? 1'b1: // 32 jbus cycle done
de_dbginit_jl;
assign a_dbginit_jl_nxt = dbginit_1sht? 1'b1:
dbg_init_cnt_dn ? 1'b0:
a_dbginit_jl;
dffrl_async_ns u_de_dbginit_jl(.din(de_dbginit_jl_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (de_dbginit_jl)
);
dffrl_async_ns u_a_dbginit_jl(.din(a_dbginit_jl_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (a_dbginit_jl)
);
//---------------------------------------------------------------------------
//
// Register : clsp_dll_ctrl
//
//---------------------------------------------------------------------------
// TRIG_DELY 44:40
// STRETCH 38:32
// DDR3_DLL_OVF 19
// DDR3_DLL_LOCK 18
// DDR3_DLL_DELAY 17:15
// DDR2_DLL_OVF 14
// DDR2_DLL_LOCK 13
// DDR2_DLL_DELAY 12:10
// DDR1_DLL_OVF 9
// DDR1_DLL_LOCK 8
// DDR1_DLL_DELAY 7:5
// DDR0_DLL_OVF 4
// DDR0_DLL_LOCK 3
// DDR0_DLL_DELAY 2:0
assign dbgtrig_dly_cnt_val_nxt = clsp_dll_ctrl_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[44:40]
: dbgtrig_dly_cnt_val;
dffsl_async_ns #(5) u_dbgtrig_dly_cnt_val ( .din(dbgtrig_dly_cnt_val_nxt),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (dbgtrig_dly_cnt_val)
);
assign clk_stretch_cnt_val_6_nxt = clsp_dll_ctrl_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[38]
: clk_stretch_cnt_val_6;
dffrl_async_ns u_clk_stretch_cnt_val_6_ff ( .din(clk_stretch_cnt_val_6_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (clk_stretch_cnt_val_6)
);
assign clk_stretch_cnt_val_nxt = clsp_dll_ctrl_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[36:32]
: clk_stretch_cnt_val;
dffrl_async_ns #(3) u_clk_stretch_cnt_val_4_2_ff ( .din(clk_stretch_cnt_val_nxt[4:2]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (clk_stretch_cnt_val[4:2])
);
dffsl_async_ns #(1) u_clk_stretch_cnt_val_1_ff ( .din(clk_stretch_cnt_val_nxt[1]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (clk_stretch_cnt_val[1])
);
dffrl_async_ns #(1) u_clk_stretch_cnt_val_0_ff ( .din(clk_stretch_cnt_val_nxt[0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (clk_stretch_cnt_val[0])
);
assign clk_stretch_cnt_val_odd = clk_stretch_cnt_val[0];
assign clsp_ddr3_dll_delay_nxt = clsp_dll_ctrl_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[17:15]
: clsp_ddr3_dll_delayctr_jl;
dffrl_async_ns u_clsp_ddr3_dll_delay_2_ff ( .din(clsp_ddr3_dll_delay_nxt[2] ),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (clsp_ddr3_dll_delayctr_jl[2])
);
dffsl_async_ns #(2) u_clsp_ddr3_dll_delay_1_0_ff ( .din(clsp_ddr3_dll_delay_nxt[1:0] ),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ddr3_dll_delayctr_jl[1:0])
);
assign clsp_ddr2_dll_delay_nxt = clsp_dll_ctrl_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[12:10]
: clsp_ddr2_dll_delayctr_jl;
dffrl_async_ns u_clsp_ddr2_dll_delay_2_ff ( .din(clsp_ddr2_dll_delay_nxt[2] ),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (clsp_ddr2_dll_delayctr_jl[2])
);
dffsl_async_ns #(2) u_clsp_ddr2_dll_delay_1_0_ff ( .din(clsp_ddr2_dll_delay_nxt[1:0] ),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ddr2_dll_delayctr_jl[1:0])
);
assign clsp_ddr1_dll_delay_nxt = clsp_dll_ctrl_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[7:5]
: clsp_ddr1_dll_delayctr_jl;
dffrl_async_ns u_clsp_ddr1_dll_delay_2_ff ( .din(clsp_ddr1_dll_delay_nxt[2] ),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (clsp_ddr1_dll_delayctr_jl[2])
);
dffsl_async_ns #(2) u_clsp_ddr1_dll_delay_1_0_ff ( .din(clsp_ddr1_dll_delay_nxt[1:0] ),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ddr1_dll_delayctr_jl[1:0])
);
assign clsp_ddr0_dll_delay_nxt = clsp_dll_ctrl_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[2:0]
: clsp_ddr0_dll_delayctr_jl;
dffrl_async_ns u_clsp_ddr0_dll_delay_2_ff ( .din(clsp_ddr0_dll_delay_nxt[2] ),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (clsp_ddr0_dll_delayctr_jl[2])
);
dffsl_async_ns #(2) u_clsp_ddr0_dll_delay_1_0_ff ( .din(clsp_ddr0_dll_delay_nxt[1:0] ),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (clsp_ddr0_dll_delayctr_jl[1:0])
);
assign ddr3_dll_overflow_nxt = rst_l ? ddr3_dll_overflow_jl : ddr3_dll_overflow;
dffrl_async_ns u_clsp_ddr3_dll_overflow_jl ( .din(ddr3_dll_overflow_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ddr3_dll_overflow)
);
assign ddr2_dll_overflow_nxt = rst_l ? ddr2_dll_overflow_jl : ddr2_dll_overflow;
dffrl_async_ns u_clsp_ddr2_dll_overflow_jl ( .din(ddr2_dll_overflow_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ddr2_dll_overflow)
);
assign ddr1_dll_overflow_nxt = rst_l ? ddr1_dll_overflow_jl : ddr1_dll_overflow;
dffrl_async_ns u_clsp_ddr1_dll_overflow_jl ( .din(ddr1_dll_overflow_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ddr1_dll_overflow)
);
assign ddr0_dll_overflow_nxt = rst_l ? ddr0_dll_overflow_jl : ddr0_dll_overflow;
dffrl_async_ns u_clsp_ddr0_dll_overflow_jl ( .din(ddr0_dll_overflow_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ddr0_dll_overflow)
);
assign ddr3_dll_lock_nxt = rst_l ? ddr3_dll_lock_jl : ddr3_dll_lock;
dffrl_async_ns u_clsp_ddr3_dll_lock_jl ( .din(ddr3_dll_lock_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ddr3_dll_lock)
);
assign ddr2_dll_lock_nxt = rst_l ? ddr2_dll_lock_jl : ddr2_dll_lock;
dffrl_async_ns u_clsp_ddr2_dll_lock_jl ( .din(ddr2_dll_lock_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ddr2_dll_lock)
);
assign ddr1_dll_lock_nxt = rst_l ? ddr1_dll_lock_jl : ddr1_dll_lock;
dffrl_async_ns u_clsp_ddr1_dll_lock_jl ( .din(ddr1_dll_lock_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ddr1_dll_lock)
);
assign ddr0_dll_lock_nxt = rst_l ? ddr0_dll_lock_jl : ddr0_dll_lock;
dffrl_async_ns u_clsp_ddr0_dll_lock_jl ( .din(ddr0_dll_lock_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ddr0_dll_lock)
);
assign clsp_dll_ctrl_rd_vld = clsp_rd_req_vld_1sht & clsp_dll_ctrl_sel;
assign clsp_dll_ctrl_rd_bus = { 19'h00000,
dbgtrig_dly_cnt_val[4:0],
1'b0,
clk_stretch_cnt_val_6,
1'b0,
clk_stretch_cnt_val[4:0],
12'h000,
ddr3_dll_overflow,
ddr3_dll_lock,
ctu_ddr3_dll_delayctr_jl[2:0],
ddr2_dll_overflow,
ddr2_dll_lock,
ctu_ddr2_dll_delayctr_jl[2:0],
ddr1_dll_overflow,
ddr1_dll_lock,
ctu_ddr1_dll_delayctr_jl[2:0],
ddr0_dll_overflow,
ddr0_dll_lock,
ctu_ddr0_dll_delayctr_jl[2:0]} &
{ 64 {clsp_dll_ctrl_rd_vld }};
//---------------------------------------------------------------------------
//
// Register : sync pulse (jbus_clk)
//
//---------------------------------------------------------------------------
// default 13:2
// JSYNC_RCV2 39:38 (default 2)
// JSYNC_TRN2 36:32 (default 1)
// JSYNC_RCV1 28:24 (default 2)
// JSYNC_TRN1 23:22 (default 1)
// JSYNC_RCV0 20:16 (default 2)
// JSYNC_TRN0 15:13 (default 1)
// JSYNC_INIT 12:8 (default 3)
// JSYNC_PERIOD 4:0 (default 3)
assign jsync_reg_rx2_nxt = clsp_jsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[39:38]
: jsync_reg_rx2;
dffrl_async_ns u_jsync_reg_rx2_1_ff ( .din(jsync_reg_rx2_nxt[1]),
.clk(jbus_clk),
.rst_l(io_pwron_rst_l),
.q (jsync_reg_rx2[1])
);
dffsl_async_ns u_jsync_reg_rx2_0_ff ( .din(jsync_reg_rx2_nxt[0]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (jsync_reg_rx2[0])
);
assign jsync_reg_tx2_nxt = clsp_jsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[36:32]
: jsync_reg_tx2;
dffrl_async_ns #(5) u_jsync_reg_tx2_4_0_ff ( .din(jsync_reg_tx2_nxt[4:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (jsync_reg_tx2[4:0])
);
assign jsync_reg_rx1_nxt = clsp_jsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[31:30]
: jsync_reg_rx1;
dffrl_async_ns u_jsync_reg_rx1_1_ff ( .din(jsync_reg_rx1_nxt[1]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (jsync_reg_rx1[1])
);
dffsl_async_ns u_jsync_reg_rx1_0_ff ( .din(jsync_reg_rx1_nxt[0]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (jsync_reg_rx1[0])
);
assign jsync_reg_tx1_nxt = clsp_jsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[28:24]
: jsync_reg_tx1;
dffrl_async_ns #(5) u_jsync_reg_tx1_4_0_ff ( .din(jsync_reg_tx1_nxt[4:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (jsync_reg_tx1[4:0])
);
assign jsync_reg_rx0_nxt = clsp_jsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[23:22]
: jsync_reg_rx0;
dffrl_async_ns u_jsync_reg_rx0_1_ff ( .din(jsync_reg_rx0_nxt[1]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (jsync_reg_rx0[1])
);
dffsl_async_ns u_jsync_reg_rx0_0_ff ( .din(jsync_reg_rx0_nxt[0]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (jsync_reg_rx0[0])
);
assign jsync_reg_tx0_nxt = clsp_jsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[20:16]
: jsync_reg_tx0;
dffrl_async_ns #(5) u_jsync_reg_tx0_4_0_ff ( .din(jsync_reg_tx0_nxt[4:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (jsync_reg_tx0[4:0])
);
assign jsync_reg_init_nxt = clsp_jsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[12:8]
: jsync_reg_init;
dffrl_async_ns #(3) u_jsync_reg_4_3_init ( .din(jsync_reg_init_nxt[4:2]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (jsync_reg_init[4:2])
);
dffsl_async_ns u_jsync_reg_2_1_init ( .din(jsync_reg_init_nxt[1]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (jsync_reg_init[1])
);
dffrl_async_ns u_jsync_reg_0_init ( .din(jsync_reg_init_nxt[0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (jsync_reg_init[0])
);
// default to 3
assign jsync_reg_period_nxt = clsp_jsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[4:0]
: jsync_reg_period;
dffrl_async_ns #(3) u_jsync_reg_4_2_period ( .din(jsync_reg_period_nxt[4:2]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (jsync_reg_period[4:2])
);
dffsl_async_ns #(2) u_jsync_reg_1_0_period ( .din(jsync_reg_period_nxt[1:0]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (jsync_reg_period[1:0])
);
assign clsp_jsync_rd_vld = clsp_rd_req_vld_1sht & clsp_jsync_sel;
assign clsp_jsync_rd_bus= { 24'h000000,
jsync_reg_rx2[1:0],
1'b0,
jsync_reg_tx2[4:0],
jsync_reg_rx1[1:0],
1'b0,
jsync_reg_tx1[4:0],
jsync_reg_rx0[1:0],
1'b0,
jsync_reg_tx0[4:0],
3'b000,
jsync_reg_init[4:0],
3'b000,
jsync_reg_period[4:0]} & { 64 {clsp_jsync_rd_vld}};
//---------------------------------------------------------------------------
//
// Register : sync pulse (jbus_clk)
//
//---------------------------------------------------------------------------
// default 13:2
// DSYNC_RCV2 39:38 (default 1)
// DSYNC_TRN2 36:32 (default 4)
// DSYNC_RCV1 28:24 (default 10)
// DSYNC_TRN1 23:22 (default 2)
// DSYNC_RCV0 20:16 (default 4)
// DSYNC_TRN0 15:13 (default 1)
// DSYNC_INIT 12:8 (default 0)
// DSYNC_PERIOD 4:0 (default 12)
assign dsync_reg_rx2_nxt = clsp_dsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[39:38]
: dsync_reg_rx2;
dffrl_async_ns u_dsync_reg_rx2_1_ff ( .din(dsync_reg_rx2_nxt[1]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (dsync_reg_rx2[1])
);
dffsl_async_ns u_dsync_reg_rx2_0_ff ( .din(dsync_reg_rx2_nxt[0]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (dsync_reg_rx2[0])
);
assign dsync_reg_tx2_nxt = clsp_dsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[36:32]
: dsync_reg_tx2;
dffrl_async_ns #(5) u_dsync_reg_tx2_4_0_ff ( .din(dsync_reg_tx2_nxt[4:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (dsync_reg_tx2[4:0])
);
assign dsync_reg_rx1_nxt = clsp_dsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[31:30]
: dsync_reg_rx1;
dffrl_async_ns u_dsync_reg_rx1_1_ff ( .din(dsync_reg_rx1_nxt[1]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (dsync_reg_rx1[1])
);
dffsl_async_ns u_dsync_reg_rx1_0_ff ( .din(dsync_reg_rx1_nxt[0]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (dsync_reg_rx1[0])
);
assign dsync_reg_tx1_nxt = clsp_dsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[28:24]
: dsync_reg_tx1;
dffrl_async_ns #(5) u_dsync_reg_tx1_4_0_ff ( .din(dsync_reg_tx1_nxt[4:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (dsync_reg_tx1[4:0])
);
assign dsync_reg_rx0_nxt = clsp_dsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[23:22]
: dsync_reg_rx0;
dffrl_async_ns u_dsync_reg_rx0_1_ff ( .din(dsync_reg_rx0_nxt[1]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (dsync_reg_rx0[1])
);
dffsl_async_ns u_dsync_reg_rx0_0_ff ( .din(dsync_reg_rx0_nxt[0]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (dsync_reg_rx0[0])
);
assign dsync_reg_tx0_nxt = clsp_dsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[20:16]
: dsync_reg_tx0;
dffrl_async_ns #(5) u_dsync_reg_tx0_4_0_ff ( .din(dsync_reg_tx0_nxt[4:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (dsync_reg_tx0[4:0])
);
assign dsync_reg_init_nxt = clsp_dsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[12:8]
: dsync_reg_init;
dffrl_async_ns #(3) u_dsync_reg_4_2_init ( .din(dsync_reg_init_nxt[4:2]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (dsync_reg_init[4:2])
);
dffsl_async_ns u_dsync_reg_1_init ( .din(dsync_reg_init_nxt[1]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (dsync_reg_init[1])
);
dffrl_async_ns u_dsync_reg_0_init ( .din(dsync_reg_init_nxt[0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (dsync_reg_init[0])
);
assign dsync_reg_period_nxt = clsp_dsync_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[4:0]
: dsync_reg_period;
dffrl_async_ns #(3) u_dsync_reg_4_2_period ( .din(dsync_reg_period_nxt[4:2]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (dsync_reg_period[4:2])
);
dffsl_async_ns #(2) u_dsync_reg_1_0_period ( .din(dsync_reg_period_nxt[1:0]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (dsync_reg_period[1:0])
);
assign clsp_dsync_rd_vld = clsp_rd_req_vld_1sht & clsp_dsync_sel;
assign clsp_dsync_rd_bus= { 24'h000000,
dsync_reg_rx2[1:0],
1'b0,
dsync_reg_tx2[4:0],
dsync_reg_rx1[1:0],
1'b0,
dsync_reg_tx1[4:0],
dsync_reg_rx0[1:0],
1'b0,
dsync_reg_tx0[4:0],
3'b000,
dsync_reg_init[4:0],
3'b000,
dsync_reg_period[4:0]} & { 64 {clsp_dsync_rd_vld}};
//---------------------------------------------------------------------------
//
// Register : clsp_dll_byp
//
//---------------------------------------------------------------------------
// DLL3_BYP_L [61]
// DLL3_BYP_DATA [60:56]
// DLL3_CTRL [52:48]
// DLL2_BYP_L [45]
// DLL2_BYP_DATA [44:40]
// DLL2_CTRL [36:32]
// DLL1_BYP_L [29]
// DLL1_BYP_DATA [28:24]
// DLL1_CTRL [20:16]
// DLL0_BYP_L [13]
// DLL0_BYP_DATA [12:8]
// DLL0_CTRL [4:0]
assign ctu_dll3_byp_l_nxt = clsp_dll_byp_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[61]
: ctu_dll3_byp_l_jl;
dffsl_async_ns u_ctu_dll3_byp_l ( .din(ctu_dll3_byp_l_nxt),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (ctu_dll3_byp_l_jl)
);
assign ctu_dll2_byp_l_nxt = clsp_dll_byp_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[45]
: ctu_dll2_byp_l_jl;
dffsl_async_ns u_ctu_dll2_byp_l ( .din(ctu_dll2_byp_l_nxt),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (ctu_dll2_byp_l_jl)
);
assign ctu_dll1_byp_l_nxt = clsp_dll_byp_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[29]
: ctu_dll1_byp_l_jl;
dffsl_async_ns u_ctu_dll1_byp_l ( .din(ctu_dll1_byp_l_nxt),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (ctu_dll1_byp_l_jl)
);
assign ctu_dll0_byp_l_nxt = clsp_dll_byp_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[13]
: ctu_dll0_byp_l_jl;
dffsl_async_ns u_ctu_dll0_byp_l ( .din(ctu_dll0_byp_l_nxt),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (ctu_dll0_byp_l_jl)
);
assign ctu_dll3_byp_val_nxt = clsp_dll_byp_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[60:56]
: ctu_dll3_byp_val_jl;
dffrl_async_ns #(5) u_ctu_dll3_byp_val ( .din(ctu_dll3_byp_val_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ctu_dll3_byp_val_jl)
);
assign ctu_dll2_byp_val_nxt = clsp_dll_byp_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[44:40]
: ctu_dll2_byp_val_jl;
dffrl_async_ns #(5) u_ctu_dll2_byp_val ( .din(ctu_dll2_byp_val_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ctu_dll2_byp_val_jl)
);
assign ctu_dll1_byp_val_nxt = clsp_dll_byp_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[28:24]
: ctu_dll1_byp_val_jl;
dffrl_async_ns #(5) u_ctu_dll1_byp_val ( .din(ctu_dll1_byp_val_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ctu_dll1_byp_val_jl)
);
assign ctu_dll0_byp_val_nxt = clsp_dll_byp_sel & clsp_wr_req_vld_d & rst_l ? ucb_clsp_data_in_reg[12:8]
: ctu_dll0_byp_val_jl;
dffrl_async_ns #(5) u_ctu_dll0_byp_val ( .din(ctu_dll0_byp_val_nxt),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (ctu_dll0_byp_val_jl)
);
assign clsp_dll_byp_rd_vld = clsp_rd_req_vld_1sht & clsp_dll_byp_sel;
assign clsp_dll_byp_rd_bus = { 2'b00,
ctu_dll3_byp_l_jl,
ctu_dll3_byp_val_jl[4:0],
3'b000,
dll3_ctu_ctrl_jl[4:0],
2'b00,
ctu_dll2_byp_l_jl,
ctu_dll2_byp_val_jl[4:0],
3'b000,
dll2_ctu_ctrl_jl[4:0],
2'b00,
ctu_dll1_byp_l_jl,
ctu_dll1_byp_val_jl[4:0],
3'b000,
dll1_ctu_ctrl_jl[4:0],
2'b00,
ctu_dll0_byp_l_jl,
ctu_dll0_byp_val_jl[4:0],
3'b000,
dll0_ctu_ctrl_jl[4:0]
} &
{ 64 {clsp_dll_byp_rd_vld }};
//---------------------------------------------------------------------------
//
// Register : version
//
//---------------------------------------------------------------------------
// 63:48 Manufacture code
// 47:32 Implementation code
// 31:24 Mask code (major, minor)
// 18:16 Maximum index number global register set
// 15:8 Max trap level support
// 4:0 Max index number for use as a valid CWP value
assign manufacture_code = `CLK_MAN_ID;
assign impl_code = `CLK_IMPL_CODE;
assign mask_id = {mask_major_id[3:0],mask_minor_id[3:0]};
assign max_glb_reg = `CLK_MAX_GLB_REG;
assign max_trap_level = `CLK_MAX_TRAP_LEVEL;
assign max_cwp = `CLK_MAX_CWP;
assign clsp_version_rd_vld = clsp_rd_req_vld_1sht & clsp_version_sel;
assign clsp_version_rd_bus= { manufacture_code[15:0],
impl_code[15:0],
mask_id[7:0],
5'b00000,
max_glb_reg[2:0],
max_trap_level[7:0],
3'b000,
max_cwp[4:0]
} & {64 {clsp_version_rd_vld}};
assign ctu_spc_const_maskid = mask_id;
//---------------------------------------------------------------------------
//
// Read bus
//
//---------------------------------------------------------------------------
assign data_out = clsp_div_rd_bus |
clsp_ctrl_rd_bus |
clsp_jsync_rd_bus |
clsp_dll_ctrl_rd_bus |
clsp_dsync_rd_bus |
clsp_dll_byp_rd_bus |
clsp_version_rd_bus;
assign ucb_rd_ack_vld_nxt = (clsp_div_rd_vld | clsp_ctrl_rd_vld | clsp_dll_byp_rd_vld |
clsp_dll_ctrl_rd_vld | clsp_version_rd_vld |
clsp_jsync_rd_vld | clsp_dsync_rd_vld | dbginit_rd_vld) & rst_l ;
dffrl_async_ns u_ucb_rd_ack_vld (.din( ucb_rd_ack_vld_nxt),
.clk(jbus_clk),
.rst_l(io_pwron_rst_l),
.q (ucb_rd_ack_vld)
);
assign ucb_data_out_nxt = ucb_rd_ack_vld_nxt ? data_out[63:0]: ucb_data_out[63:0];
dffrl_async_ns #(64) u_ucb_data_out_ff (.din( ucb_data_out_nxt[63:0]),
.clk(jbus_clk),
.rst_l(io_pwron_rst_l),
.q (ucb_data_out[63:0])
);
//---------------------------------------------------------------------------
//
// Waveform Generation
//
//---------------------------------------------------------------------------
function [14:0] f_div_vect;
input [4:0] divisor;
begin
// 111 11
// 432 109 8765 4321 0
case (divisor) // 1175 4 3 1 0
5'b00010: f_div_vect = 15'b000_001_0010_0001_1;// 2
5'b00011: f_div_vect = 15'b100_001_1000_1000_0;// 3
5'b00100: f_div_vect = 15'b000_001_0100_0100_0;// 4
5'b00101: f_div_vect = 15'b100_001_1000_0010_0;// 5
5'b00110: f_div_vect = 15'b001_001_0100_0010_0;// 6
5'b00111: f_div_vect = 15'b100_001_1000_0001_0;// 7
5'b01000: f_div_vect = 15'b000_001_0100_0001_0;// 8
5'b01001: f_div_vect = 15'b100_001_0010_0001_0;// 9
5'b01010: f_div_vect = 15'b000_001_0010_0001_0;// 10
// align_edge generation changes here
5'b01011: f_div_vect = 15'b100_100_0001_0001_0;// 11
5'b01100: f_div_vect = 15'b000_100_0001_0001_0;// 12
5'b01101: f_div_vect = 15'b110_010_0001_0001_0;// 13
5'b01110: f_div_vect = 15'b010_010_0001_0001_0;// 14
5'b01111: f_div_vect = 15'b111_001_0001_0001_0;// 15
5'b10000: f_div_vect = 15'b011_001_0001_0001_0;// 16
5'b10001: f_div_vect = 15'b110_001_0001_0001_0;// 17
5'b10010: f_div_vect = 15'b010_001_0001_0001_0;// 18
5'b10011: f_div_vect = 15'b100_010_0001_0001_0;// 19
5'b10100: f_div_vect = 15'b000_010_0001_0001_0;// 20
5'b10101: f_div_vect = 15'b101_001_0001_0001_0;// 21
5'b10110: f_div_vect = 15'b001_001_0001_0001_0;// 22
5'b10111: f_div_vect = 15'b100_001_0001_0001_0;// 23
5'b11000: f_div_vect = 15'b000_001_0001_0001_0;// 24
// not done below here
// CoverMeter line_off
default: f_div_vect = 15'b000_001_0001_0001_0;// 4
// CoverMeter line_on
endcase
end
endfunction
/************************************************************
*Decoding clock divisor for cmp clk
************************************************************/
always @(/*AUTOSENSE*/reg_cdiv)
begin
cdiv_vec_nxt = f_div_vect(reg_cdiv);
end // always @ (reg_cdiv)
dffrl_async_ns #(5) u_cdiv_vec_14_10(.din( cdiv_vec_nxt[14:10]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_cdiv_vec[14:10])
);
dffsl_async_ns #(1) u_cdiv_vec_9 (.din( cdiv_vec_nxt[9]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_cdiv_vec[9])
);
dffrl_async_ns #(1) u_cdiv_vec_8 (.din( cdiv_vec_nxt[8]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_cdiv_vec[8])
);
dffsl_async_ns #(1) u_cdiv_vec_7 (.din( cdiv_vec_nxt[7]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_cdiv_vec[7])
);
dffrl_async_ns #(3) u_cdiv_vec_6_4(.din( cdiv_vec_nxt[6:4]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_cdiv_vec[6:4])
);
dffsl_async_ns #(1) u_cdiv_vec_3(.din( cdiv_vec_nxt[3]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_cdiv_vec[3])
);
dffrl_async_ns #(3) u_cdiv_vec_2_0(.din( cdiv_vec_nxt[2:0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_cdiv_vec[2:0])
);
/************************************************************
*Decoding clock divisor for jbus clk
************************************************************/
always @(/*AUTOSENSE*/reg_jdiv)
begin
jdiv_vec_nxt = f_div_vect(reg_jdiv);
end // always @ (reg_jdiv)
dffrl_async_ns #(1) u_jdiv_vec_14(.din( jdiv_vec_nxt[14]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_jdiv_vec[14])
);
dffsl_async_ns #(2) u_jdiv_vec_13_12 (.din( jdiv_vec_nxt[13:12]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_jdiv_vec[13:12])
);
dffrl_async_ns #(2) u_jdiv_vec_11_10(.din( jdiv_vec_nxt[11:10]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_jdiv_vec[11:10])
);
dffsl_async_ns #(1) u_jdiv_vec_9 (.din( jdiv_vec_nxt[9]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_jdiv_vec[9])
);
dffrl_async_ns #(3) u_jdiv_vec_8_6(.din( jdiv_vec_nxt[8:6]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_jdiv_vec[8:6])
);
dffsl_async_ns #(1) u_jdiv_vec_5(.din( jdiv_vec_nxt[5]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_jdiv_vec[5])
);
dffrl_async_ns #(3) u_jdiv_vec_4_2(.din( jdiv_vec_nxt[4:2]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_jdiv_vec[4:2])
);
dffsl_async_ns #(1) u_jdiv_vec_1(.din( jdiv_vec_nxt[1]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_jdiv_vec[1])
);
dffrl_async_ns #(1) u_jdiv_vec_0(.din( jdiv_vec_nxt[0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_jdiv_vec[0])
);
/************************************************************
*Decoding clock divisor for dram clk
************************************************************/
always @(/*AUTOSENSE*/reg_ddiv)
begin
ddiv_vec_nxt = f_div_vect(reg_ddiv);
end // always @ (reg_ddiv)
dffrl_async_ns #(1) u_ddiv_vec_14(.din( ddiv_vec_nxt[14]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_ddiv_vec[14])
);
dffsl_async_ns #(2) u_ddiv_vec_13_12 (.din( ddiv_vec_nxt[13:12]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_ddiv_vec[13:12])
);
dffrl_async_ns #(2) u_ddiv_vec_11_10(.din( ddiv_vec_nxt[11:10]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_ddiv_vec[11:10])
);
dffsl_async_ns #(1) u_ddiv_vec_9 (.din( ddiv_vec_nxt[9]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_ddiv_vec[9])
);
dffrl_async_ns #(3) u_ddiv_vec_8_6(.din( ddiv_vec_nxt[8:6]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_ddiv_vec[8:6])
);
dffsl_async_ns #(1) u_ddiv_vec_5(.din( ddiv_vec_nxt[5]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_ddiv_vec[5])
);
dffrl_async_ns #(3) u_ddiv_vec_4_2(.din( ddiv_vec_nxt[4:2]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_ddiv_vec[4:2])
);
dffsl_async_ns #(1) u_ddiv_vec_1(.din( ddiv_vec_nxt[1]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (reg_ddiv_vec[1])
);
dffrl_async_ns #(1) u_ddiv_vec_0(.din( ddiv_vec_nxt[0]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (reg_ddiv_vec[0])
);
/************************************************************
*Decoding cnt value for stretch_counter
************************************************************/
always @(/*AUTOSENSE*/clk_stretch_cnt_val)
begin
stretch_cnt_vec_nxt = f_div_vect(clk_stretch_cnt_val[4:0]);
end // always @ (reg_ddiv)
dffrl_async_ns #(5) u_stretch_cnt_vec_14_10(.din( stretch_cnt_vec_nxt[14:10]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (stretch_cnt_vec_pre[14:10])
);
dffsl_async_ns #(1) u_stretch_cnt_vec_9 (.din( stretch_cnt_vec_nxt[9]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (stretch_cnt_vec_pre[9])
);
dffrl_async_ns #(7) u_stretch_cnt_vec_8_2(.din( stretch_cnt_vec_nxt[8:2]),
.clk(jbus_clk),
.rst_l (io_pwron_rst_l),
.q (stretch_cnt_vec_pre[8:2])
);
dffsl_async_ns #(2) u_stretch_cnt_vec_1_0 (.din( stretch_cnt_vec_nxt[1:0]),
.clk(jbus_clk),
.set_l (io_pwron_rst_l),
.q (stretch_cnt_vec_pre[1:0])
);
//assign stretch_cnt_vec[14:0] = se? 15'b000_0000_0000_0000 : stretch_cnt_vec_pre[14:0];
assign se_bar = ~se;
assign stretch_cnt_vec[14:0] = {15 {se_bar}} & stretch_cnt_vec_pre[14:0];
//---------------------------------------------------------------------------
//
// Sync edge generator
//
//---------------------------------------------------------------------------
assign mult_rst_l = bypclksel_sync? jbus_mult_rst_l : start_clk_early_jl ;
//dffsl_async_ns u_cnt_ld(
dffsl_ns u_cnt_ld(
.din (1'b0),
.clk (jbus_clk),
.set_l (start_clk_early_jl),
//.set_l (mult_rst_l),
.q(cnt_ld));
assign lcm_cnt_minus_1 = lcm_cnt - 10'h001;
assign lcm_cnt_nxt = cnt_ld? shadreg_div_jmult[9:0]:
(|(lcm_cnt[9:1])) ? lcm_cnt_minus_1 :
shadreg_div_jmult[9:0];
//dffrl_async_ns #(10) u_lcm_ff (
dffrl_ns #(10) u_lcm_ff (
.din (lcm_cnt_nxt),
.clk (jbus_clk),
//.rst_l (start_clk_early_jl),
.rst_l (mult_rst_l),
.q(lcm_cnt));
assign lcm_cnt_zero = ~(|(lcm_cnt[9:1]));
/************************************************************
* Grst logic
************************************************************/
// -----------------------------------------
//
// grst_l signal only allow to de-assert when grst_en_window is 1
// jbus_grst_jl_l is set when the pipeline latency is reached and enable window is 1
// jbus_grst_jl_l is reset by a_grst_cl
//
// -----------------------------------------
assign grst_en_window_nxt = de_grst_jsync_edge & lcm_cnt_zero ? 1'b1:
lcm_cnt_zero & grst_en_window ? 1'b0:
grst_en_window;
dffrl_ns u_grst_en_window( .din (grst_en_window_nxt),
.clk (jbus_clk),
.rst_l (start_clk_jl),
.q(grst_en_window));
assign jbus_grst_jl_l_nxt = a_grst_jl ? 1'b0:
(lcm_cnt == `JBUS_GLOBAL_LATENCY) & grst_en_window ? 1'b1:
jbus_grst_jl_l;
dffrl_ns u_jbus_grst_jl_l(
.din (jbus_grst_jl_l_nxt),
.clk (jbus_clk),
.rst_l(start_clk_jl),
.q(jbus_grst_jl_l));
// ----------------------------------------------------------------------
//
// dbginit_l signal only allow to de-assert when dbginit_en_window is 1
// (i.e. when de_grst_cl | de_dbginit_cl is asserted)
// dbginit_l signal is reset by a_grst_cl | a_dbginit_cl signal
//
// ---------------------------------------------------------------------
assign dbginit_en_window_nxt = de_dbginit_jsync_edge & lcm_cnt_zero ? 1'b1:
lcm_cnt_zero & dbginit_en_window ? 1'b0:
dbginit_en_window;
dffrl_ns u_dbginit_en_window( .din (dbginit_en_window_nxt),
.clk (jbus_clk),
.rst_l (start_clk_jl),
.q(dbginit_en_window));
assign jbus_dbginit_jl_l_nxt =
(a_dbginit_jl | a_grst_jl)? 1'b0:
(lcm_cnt == `JBUS_GLOBAL_LATENCY) & dbginit_en_window? 1'b1:
jbus_dbginit_jl_l;
dffrl_ns u_jbus_dbginit_jl_l(
.din (jbus_dbginit_jl_l_nxt),
.clk (jbus_clk),
.rst_l(start_clk_jl),
.q(jbus_dbginit_jl_l));
//---------------------------------------------------------------------------
//
// Clock stop id from jtag
//
//---------------------------------------------------------------------------
// jtag_clsp_stop_id needs to be stable for 3 cycles
dffrl_async_ns u_jtag_clsp_stop_id_vld_dly(
.din (~jtag_clsp_stop_id_vld_jl),
.clk (jbus_clk),
.rst_l(io_pwron_rst_l),
.q (jtag_clsp_stop_id_vld_jl_dly_l)
);
assign jtag_clsp_stop_id_vld_1sht =
jtag_clsp_stop_id_vld_jl & jtag_clsp_stop_id_vld_jl_dly_l & start_clk_jl;
dffrl_async_ns u_stop_id_vld_dly(
.din (jtag_clsp_stop_id_vld_1sht),
.clk (jbus_clk),
.rst_l(io_pwron_rst_l),
.q (stop_id_vld_dly)
);
dffrl_async_ns u_stop_id_vld_jl(
.din (stop_id_vld_dly),
.clk (jbus_clk),
.rst_l(io_pwron_rst_l),
.q (stop_id_vld_jl)
);
assign new_id_nxt = jtag_clsp_stop_id_vld_1sht ? jtag_clsp_stop_id: new_id;
dffrl_async_ns #(6) u_jtag_clsp_stop_vld(
.din (new_id_nxt),
.clk (jbus_clk),
.rst_l(io_pwron_rst_l),
.q (new_id)
);
dffrl_async_ns #(`CCTRLSM_MAX_ST) u_stop_id_decoded(
.din (jtag_clsp_stop_id_decoded),
.clk (jbus_clk),
.rst_l(io_pwron_rst_l),
.q (stop_id_decoded)
);
always @(new_id)
case (new_id)
`CTU_SPARC0_ID: jtag_clsp_stop_id_decoded = `CTU_SPARC0_IDD;
`CTU_SPARC1_ID: jtag_clsp_stop_id_decoded = `CTU_SPARC1_IDD;
`CTU_SPARC2_ID: jtag_clsp_stop_id_decoded = `CTU_SPARC2_IDD;
`CTU_SPARC3_ID: jtag_clsp_stop_id_decoded = `CTU_SPARC3_IDD;
`CTU_SPARC4_ID: jtag_clsp_stop_id_decoded = `CTU_SPARC4_IDD;
`CTU_SPARC5_ID: jtag_clsp_stop_id_decoded = `CTU_SPARC5_IDD;
`CTU_SPARC6_ID: jtag_clsp_stop_id_decoded = `CTU_SPARC6_IDD;
`CTU_SPARC7_ID: jtag_clsp_stop_id_decoded = `CTU_SPARC7_IDD;
`CTU_SCDATA0_ID: jtag_clsp_stop_id_decoded = `CTU_SCDATA0_IDD;
`CTU_SCDATA1_ID: jtag_clsp_stop_id_decoded = `CTU_SCDATA1_IDD;
`CTU_SCDATA2_ID: jtag_clsp_stop_id_decoded = `CTU_SCDATA2_IDD;
`CTU_SCDATA3_ID: jtag_clsp_stop_id_decoded = `CTU_SCDATA3_IDD;
`CTU_SCTAG0_ID: jtag_clsp_stop_id_decoded = `CTU_SCTAG0_IDD;
`CTU_SCTAG1_ID: jtag_clsp_stop_id_decoded = `CTU_SCTAG1_IDD;
`CTU_SCTAG2_ID: jtag_clsp_stop_id_decoded = `CTU_SCTAG2_IDD;
`CTU_SCTAG3_ID: jtag_clsp_stop_id_decoded = `CTU_SCTAG3_IDD;
`CTU_DRAM02_ID: jtag_clsp_stop_id_decoded = `CTU_DRAM02_IDD;
`CTU_DRAM13_ID: jtag_clsp_stop_id_decoded = `CTU_DRAM13_IDD;
`CTU_CCX_ID: jtag_clsp_stop_id_decoded = `CTU_CCX_IDD;
`CTU_FPU_ID: jtag_clsp_stop_id_decoded = `CTU_FPU_IDD;
`CTU_DDR0_ID: jtag_clsp_stop_id_decoded = `CTU_DDR0_IDD;
`CTU_DDR1_ID: jtag_clsp_stop_id_decoded = `CTU_DDR1_IDD;
`CTU_DDR2_ID: jtag_clsp_stop_id_decoded = `CTU_DDR2_IDD;
`CTU_DDR3_ID: jtag_clsp_stop_id_decoded = `CTU_DDR3_IDD;
`CTU_JBI_ID: jtag_clsp_stop_id_decoded = `CTU_JBI_IDD;
`CTU_JBUSR_ID: jtag_clsp_stop_id_decoded = `CTU_JBUSR_IDD;
`CTU_JBUSL_ID: jtag_clsp_stop_id_decoded = `CTU_JBUSL_IDD;
`CTU_IOB_ID: jtag_clsp_stop_id_decoded = `CTU_IOB_IDD;
`CTU_EFC_ID: jtag_clsp_stop_id_decoded = `CTU_EFC_IDD;
`CTU_DBG_ID: jtag_clsp_stop_id_decoded = `CTU_DBG_IDD;
`CTU_MISC_ID: jtag_clsp_stop_id_decoded = `CTU_MISC_IDD;
// CoverMeter line_off
default : jtag_clsp_stop_id_decoded = 31'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
// CoverMeter line_on
endcase
//---------------------------------------------------------------------------
//
// Synchronization/Multicycle path checks
//
//---------------------------------------------------------------------------
// synopsys translate_off
reg [63:0] prev_clsp_ctrl_rd_bus_cl;
always @(clsp_ctrl_rd_bus_cl)
begin
prev_clsp_ctrl_rd_bus_cl <= clsp_ctrl_rd_bus_cl;
$display("CHECK TIME %d\n",$stime);
@(posedge `CTU_PATH.jbus_clk)
begin
$display("CHECK TIME2 %d\n",$stime);
if( (rst_l === 1'b1) &
(`CTU_PATH.testmode_l === 1'b1) & ( `CTU_PATH.pll_bypass === 1'b0) &
(prev_clsp_ctrl_rd_bus_cl !== 64'hx) &
(prev_clsp_ctrl_rd_bus_cl !== clsp_ctrl_rd_bus_cl)
)
`ifdef MODELSIM
$display ( "CTU_mpath_check_error", "clsp_ctrl_rd_bus_cl should hold for at least 2 jbus cycles ");
`else
$error ( "CTU_mpath_check_error", "clsp_ctrl_rd_bus_cl should hold for at least 2 jbus cycles ");
`endif
end
@(posedge `CTU_PATH.jbus_clk)
if( (rst_l === 1'b1) &
(`CTU_PATH.testmode_l === 1'b1) & ( `CTU_PATH.pll_bypass === 1'b0) &
(prev_clsp_ctrl_rd_bus_cl !== 64'hx) &
(prev_clsp_ctrl_rd_bus_cl !== clsp_ctrl_rd_bus_cl)
)
`ifdef MODELSIM
$display ( "CTU_mpath_check_error", "clsp_ctrl_rd_bus_cl should hold for at least 2 jbus cycles");
`else
$error ( "CTU_mpath_check_error", "clsp_ctrl_rd_bus_cl should hold for at least 2 jbus cycles");
`endif
end
//jtag_clsp_stop_id should hold for at least 3 clocks
reg [5:0] prev_jtag_clsp_stop_id;
always @(posedge jtag_clsp_stop_id_vld)
begin
prev_jtag_clsp_stop_id<= jtag_clsp_stop_id;
@(posedge `CTU_PATH.jbus_clk)
if( (start_clk_jl === 1'b1) &
(`CTU_PATH.testmode_l === 1'b1) & (`CTU_PATH.pll_bypass === 1'b0) &
(prev_jtag_clsp_stop_id !== jtag_clsp_stop_id)
)
`ifdef MODELSIM
$display ( "CTU_mpath_check_error", "jtag_clsp_stop_id should hold for at least 3 jbus cycles");
`else
$error ( "CTU_mpath_check_error", "jtag_clsp_stop_id should hold for at least 3 jbus cycles");
`endif
@(posedge `CTU_PATH.jbus_clk)
if( (start_clk_jl === 1'b1) &
(`CTU_PATH.testmode_l === 1'b1) & (`CTU_PATH.pll_bypass === 1'b0) &
(prev_jtag_clsp_stop_id !== jtag_clsp_stop_id)
)
`ifdef MODELSIM
$display ( "CTU_mpath_check_error", "jtag_clsp_stop_id should hold for at least 3 jbus cycles");
`else
$error ( "CTU_mpath_check_error", "jtag_clsp_stop_id should hold for at least 3 jbus cycles");
`endif
@(posedge `CTU_PATH.jbus_clk)
if( (start_clk_jl === 1'b1) &
(`CTU_PATH.testmode_l === 1'b1) & (`CTU_PATH.pll_bypass === 1'b0) &
(prev_jtag_clsp_stop_id !== jtag_clsp_stop_id)
)
`ifdef MODELSIM
$display ( "CTU_mpath_check_error", "jtag_clsp_stop_id should hold for at least 3 jbus cycles");
`else
$error ( "CTU_mpath_check_error", "jtag_clsp_stop_id should hold for at least 3 jbus cycles");
`endif
end
// synopsys translate_on
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// verilog-library-files: ("../../common/rtl/swrvr_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
`include "delay.v"
`include "arbiter.v"
module uartmm(input clk,
input rst,
input RX,
output TX,
output [31:0] data_b,
output reg strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
wire uart_RXD;
inpin _rcxd(.clk(clk), .pin(RX), .rd(uart_RXD));
reg qin_we, qin_re, qout_we, qout_re;
wire qout_oready, qin_oready;
wire [7:0] qin_idata;
reg [7:0] qout_idata;
wire [7:0] qin_wdata;
wire [7:0] qout_wdata;
wire uart_valid, uart_busy;
// Insert the byte incoming from mm port 65539 into the uart output queue, if
// queue is not full.
always @(posedge clk)
if (!rst) begin
qout_we <= 0;
qout_idata <= 0;
end else
if (qout_we) begin
qout_we <= 0;
end else if ((addr_b == 65539) & data_b_we &
!qin_full) begin
qout_idata <= data_b[7:0];
qout_we <= 1;
end
// If uart is ready to transmit and the output queue is not empty, send one byte
always @(posedge clk)
if (!rst) qout_re <= 0;
else if (qout_re) begin
qout_re <= 0;
end
else if (qout_oready & !uart_busy) begin
qout_re <= 1;
end
// If uart has a valid output, push it into the input queue
always @(posedge clk)
if (!rst) begin
qin_we <= 0;
end else if (qin_we) begin
qin_we <= 0;
end else if (uart_valid & !qin_full) begin
qin_we <= 1;
end
reg cmd;
wire addr_b_cmd =
(addr_b == 65539);
reg out_tmp;
assign data_b = cmd?{24'b0,qin_wdata}:{30'b0,out_tmp};
// Manage the output
always @(posedge clk)
if (!rst) begin
cmd <= 0;
qin_re <= 0;
out_tmp <= 0;
strobe_b <= 0;
end else begin
cmd <= addr_b_cmd;
if (qin_re) qin_re <= 0;
else if ((addr_b == 65539) & qin_oready) begin // UART DATA IN
qin_re <= 1;
strobe_b <= 1;
end else if (addr_b == 65537) begin // UART IN READY
out_tmp <= qin_oready;
strobe_b <= 1;
end else if (addr_b == 65538) begin // UART OUT READY
out_tmp <= !qout_full;
strobe_b <= 1;
end else strobe_b <= 0;
end
// Modules
delayqueue _qin (.clk(clk),
.rst(rst),
.we(qin_we),
.idata(qin_idata),
.re(qin_re),
.wdata(qin_wdata),
.oready(qin_oready),
.full(qin_full));
delayqueue _qout (.clk(clk),
.rst(rst),
.we(qout_we),
.idata(qout_idata),
.re(qout_re),
.wdata(qout_wdata),
.oready(qout_oready),
.full(qout_full));
buart _uart (
.clk(clk),
.resetq(rst),
.rx(uart_RXD),
.tx(TX),
.rd(qin_we),
.wr(qout_re),
.valid(uart_valid),
.busy(uart_busy),
.tx_data(qout_wdata),
.rx_data(qin_idata));
endmodule
module ledwriter (input clk,
input rst,
output reg [7:0] LED,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
always @(posedge clk)
if (~rst) begin
LED <= 0;
end else begin
if (addr_b == 65540)
LED <= data_b_in[7:0];
end
endmodule
// TODO:
// implement a 2-port RAM by using a double clock frequency + a single port
`define STR(a) `"a`"
`ifndef C2_RAM_DEPTH
`define C2_RAM_DEPTH 1024
`endif
module socram(input clk,
input rst,
output reg [31:0] data_a,
input [31:0] addr_a,
output reg [31:0] data_b,
output reg strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
parameter RAM_DEPTH = `C2_RAM_DEPTH;
parameter INIT_FILE = `STR(`INIT_FILE_PATH);
reg [31:0] mem [0:RAM_DEPTH-1];
initial begin
if (INIT_FILE != "")
$readmemh(INIT_FILE, mem);
end
always @(posedge clk)
begin
if (data_b_we & (addr_b[31:16] == 0)) begin
mem[addr_b] <= data_b_in;
end
data_a <= mem[addr_a];
data_b <= mem[addr_b];
strobe_b <= (addr_b[31:16] == 0);
end
endmodule // socram
module mul16x16 (input [15:0] a,
input [15:0] b,
output [31:0] o);
assign o = a * b;
endmodule // mul16x16
module hls_Mul(input clk,
input reset,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
wire [15:0] a = p0r[31:16];
wire [15:0] b = p0r[15:0];
wire [15:0] c = p1r[31:16];
wire [15:0] d = p1r[15:0];
wire [15:0] ad = a * d;
wire [15:0] bc = b * c;
wire [31:0] bd = b * d;
reg [15:0] adr;
reg [31:0] p0r;
reg [31:0] p1r;
reg [31:0] t1;
reg [31:0] t2;
assign out = t2;
always @(posedge clk)
begin
p0r <= p0; p1r <= p1;
t1 <= bd + {bc[15:0], 16'b0}; adr <= ad[15:0];
t2 <= t1 + {adr[15:0], 16'b0};
end
endmodule // hls_Mul
`include "../rtl/mul.v"
module hls_MulFSM(input clk,
input reset,
input req,
output ack,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
mul32x32_fsm S(.clk(clk),
.rst(reset),
.req(req),
.ack(ack),
.p0(p0),
.p1(p1),
.out(out));
endmodule // hls_MulFSM
`include "vgafifo.v"
`include "vga640x480ice.v"
`ifdef ENABLE_SOUND
`include "soundctl.v"
`endif
|
//
// Paul Gao 08/2019
//
//
`timescale 1ps/1ps
`include "bsg_noc_links.vh"
module bsg_fifo_1r1w_small_hardened_tester
#(
parameter width_p = 64
,parameter els_p = 16
,parameter channel_width_p = 8
)
();
`declare_bsg_ready_and_link_sif_s(width_p, bsg_ready_and_link_sif_s);
logic master_clk, master_reset;
logic client_clk, client_reset;
logic fifo_clk, fifo_reset;
logic master_en;
logic master_error;
logic [31:0] master_sent, master_received;
bsg_ready_and_link_sif_s master_node_link_li;
bsg_ready_and_link_sif_s master_node_link_lo;
bsg_ready_and_link_sif_s client_node_link_li;
bsg_ready_and_link_sif_s client_node_link_lo;
bsg_fifo_1r1w_small_hardened_test_node
#(.num_channels_p(width_p/channel_width_p)
,.channel_width_p(channel_width_p)
,.is_client_node_p(0)
) master_node
(.node_clk_i (master_clk)
,.node_reset_i(master_reset)
,.node_en_i (master_en)
,.error_o (master_error)
,.sent_o (master_sent)
,.received_o(master_received)
,.clk_i (fifo_clk)
,.reset_i (fifo_reset)
,.link_i(master_node_link_li)
,.link_o(master_node_link_lo)
);
bsg_fifo_1r1w_small
#(.width_p (width_p)
,.els_p (els_p)
,.harden_p(1)
) fifo_m2c
(.clk_i (fifo_clk)
,.reset_i(fifo_reset)
,.v_i (master_node_link_lo.v)
,.ready_o(master_node_link_li.ready_and_rev)
,.data_i (master_node_link_lo.data)
,.v_o (client_node_link_li.v)
,.data_o (client_node_link_li.data)
,.yumi_i (client_node_link_li.v & client_node_link_lo.ready_and_rev)
);
bsg_fifo_1r1w_small
#(.width_p (width_p)
,.els_p (els_p)
,.harden_p(1)
) fifo_c2m
(.clk_i (fifo_clk)
,.reset_i(fifo_reset)
,.v_i (client_node_link_lo.v)
,.ready_o(client_node_link_li.ready_and_rev)
,.data_i (client_node_link_lo.data)
,.v_o (master_node_link_li.v)
,.data_o (master_node_link_li.data)
,.yumi_i (master_node_link_li.v & master_node_link_lo.ready_and_rev)
);
bsg_fifo_1r1w_small_hardened_test_node
#(.num_channels_p(width_p/channel_width_p)
,.channel_width_p(channel_width_p)
,.is_client_node_p(1)
) client_node
(.node_clk_i (client_clk)
,.node_reset_i(client_reset)
,.node_en_i (1'b0)
,.error_o ()
,.sent_o ()
,.received_o()
,.clk_i (fifo_clk)
,.reset_i (fifo_reset)
,.link_i(client_node_link_li)
,.link_o(client_node_link_lo)
);
// Simulation of Clock
always #4 master_clk = ~master_clk;
always #4 fifo_clk = ~fifo_clk;
always #4 client_clk = ~client_clk;
initial
begin
$display("Start Simulation\n");
// Init
master_clk = 1;
fifo_clk = 1;
client_clk = 1;
master_reset = 1;
fifo_reset = 1;
client_reset = 1;
master_en = 0;
#500;
// fifo reset
@(posedge fifo_clk); #1;
fifo_reset = 0;
$display("fifo reset LOW");
#500;
// node reset
@(posedge master_clk); #1;
master_reset = 0;
@(posedge client_clk); #1;
client_reset = 0;
$display("node reset LOW");
#500;
$display("start running test");
// node enable
@(posedge master_clk); #1;
master_en = 1;
$display("node enable HIGH");
#50000;
// node disable
@(posedge master_clk); #1;
master_en = 0;
$display("node enable LOW");
#5000
assert(master_error == 0)
else
begin
$error("\nFAIL... Error in loopback node");
$finish;
end
assert(master_sent == master_received)
else
begin
$error("\nFAIL... Loopback node sent %d packets but received only %d\n", master_sent, master_received);
$finish;
end
$display("\nPASS!\n");
$display("Loopback node sent and received %d packets\n", master_sent);
$finish;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : BUFCE_LEAF.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/15/12 - Initial version.
// 02/04/14 - update specify block
// 10/22/14 - 808642 - Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFCE_LEAF #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFCE_LEAF";
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_SYNC = 0;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFCE_LEAF_dr.v"
`else
reg [40:1] CE_TYPE_REG = CE_TYPE;
reg [0:0] IS_CE_INVERTED_REG = IS_CE_INVERTED;
reg [0:0] IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
`ifdef XIL_XECLIB
wire CE_TYPE_BIN;
`else
reg CE_TYPE_BIN;
`endif
reg attr_test;
reg attr_err;
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
wire CE_in;
wire I_in;
`ifdef XIL_TIMING
wire CE_delay;
wire I_delay;
`endif
`ifdef XIL_TIMING
assign CE_in = (CE === 1'bz) || (CE_delay ^ IS_CE_INVERTED_REG); // rv 1
assign I_in = I_delay ^ IS_I_INVERTED_REG;
`else
assign CE_in = (CE === 1'bz) || (CE ^ IS_CE_INVERTED_REG); // rv 1
assign I_in = I ^ IS_I_INVERTED_REG;
`endif
`ifndef XIL_XECLIB
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
`else
always @ (trig_attr) begin
#1;
CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CE_TYPE_REG != "SYNC") &&
(CE_TYPE_REG != "ASYNC"))) begin
$display("Error: [Unisim %s-101] CE_TYPE attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
reg enable_clk = 1'b1;
always @(I_in or CE_in or glblGSR) begin
if (glblGSR)
enable_clk = 1'b1;
else if ((CE_TYPE_BIN == CE_TYPE_ASYNC) || ~I_in)
enable_clk = CE_in;
end
assign O = enable_clk & I_in;
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
wire i_en_n;
wire i_en_p;
assign i_en_n = IS_I_INVERTED_REG;
assign i_en_p = ~IS_I_INVERTED_REG;
`endif
`ifdef XIL_TIMING
specify
(CE => O) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay);
$width (negedge CE, 0:0:0, 0, notifier);
$width (posedge CE, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:31 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_processing_system7_0_0/zynq_design_1_processing_system7_0_0_stub.v
// Design : zynq_design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
module zynq_design_1_processing_system7_0_0(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0, FTMT_P2F_TRIGACK_0, FTMT_P2F_TRIG_0, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,FTMT_F2P_TRIG_0,FTMT_F2P_TRIGACK_0,FTMT_P2F_TRIGACK_0,FTMT_P2F_TRIG_0,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BOI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A21BOI_FUNCTIONAL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BOI_FUNCTIONAL_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_iddr32 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT_Q0 = 1'b0,
parameter INIT_Q1 = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [31:0] Q0,
output [31:0] Q1,
input C0,
input C1,
input CE,
input [31:0] D,
input R,
input S
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr0 (
.Q0(Q0[0]),
.Q1(Q1[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[0]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr1 (
.Q0(Q0[1]),
.Q1(Q1[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[1]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr2 (
.Q0(Q0[2]),
.Q1(Q1[2]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[2]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr3 (
.Q0(Q0[3]),
.Q1(Q1[3]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[3]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr4 (
.Q0(Q0[4]),
.Q1(Q1[4]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[4]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr5 (
.Q0(Q0[5]),
.Q1(Q1[5]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[5]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr6 (
.Q0(Q0[6]),
.Q1(Q1[6]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[6]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr7 (
.Q0(Q0[7]),
.Q1(Q1[7]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[7]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr8 (
.Q0(Q0[8]),
.Q1(Q1[8]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[8]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr9 (
.Q0(Q0[9]),
.Q1(Q1[9]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[9]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr10 (
.Q0(Q0[10]),
.Q1(Q1[10]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[10]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr11 (
.Q0(Q0[11]),
.Q1(Q1[11]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[11]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr12 (
.Q0(Q0[12]),
.Q1(Q1[12]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[12]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr13 (
.Q0(Q0[13]),
.Q1(Q1[13]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[13]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr14 (
.Q0(Q0[14]),
.Q1(Q1[14]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[14]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr15 (
.Q0(Q0[15]),
.Q1(Q1[15]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[15]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr16 (
.Q0(Q0[16]),
.Q1(Q1[16]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[16]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr17 (
.Q0(Q0[17]),
.Q1(Q1[17]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[17]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr18 (
.Q0(Q0[18]),
.Q1(Q1[18]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[18]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr19 (
.Q0(Q0[19]),
.Q1(Q1[19]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[19]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr20 (
.Q0(Q0[20]),
.Q1(Q1[20]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[20]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr21 (
.Q0(Q0[21]),
.Q1(Q1[21]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[21]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr22 (
.Q0(Q0[22]),
.Q1(Q1[22]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[22]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr23 (
.Q0(Q0[23]),
.Q1(Q1[23]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[23]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr24 (
.Q0(Q0[24]),
.Q1(Q1[24]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[24]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr25 (
.Q0(Q0[25]),
.Q1(Q1[25]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[25]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr26 (
.Q0(Q0[26]),
.Q1(Q1[26]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[26]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr27 (
.Q0(Q0[27]),
.Q1(Q1[27]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[27]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr28 (
.Q0(Q0[28]),
.Q1(Q1[28]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[28]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr29 (
.Q0(Q0[29]),
.Q1(Q1[29]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[29]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr30 (
.Q0(Q0[30]),
.Q1(Q1[30]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[30]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr31 (
.Q0(Q0[31]),
.Q1(Q1[31]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[31]),
.R(R),
.S(S)
);
endmodule
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data).
*)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** *** *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
(** *** *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: Coq already knows that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More precisely, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** *** *)
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
Module MumbleBaz.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 2 stars (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
(* FILL IN HERE *)
*)
(** [] *)
End MumbleBaz.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
(* ===> forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> forall X : Type, list X -> list X -> list X *)
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** In fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. The [Arguments] directive
specifies the name of the function or constructor, and then lists
its argument names, with curly braces around any arguments to be
treated as implicit.
*)
Arguments nil {X}.
Arguments cons {X} _ _. (* use underscore for argument position that has no name *)
Arguments length {X} l.
Arguments app {X} l1 l2.
Arguments rev {X} l.
Arguments snoc {X} l v.
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** *** *)
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length'']; indeed, it is invalid to provide
one.) We will use this style whenever possible, although we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. *)
(** *** *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, suppose we
write this: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** *** *)
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat {X : Type} (n : X) (count : nat) : list X :=
match count with
| 0 => []
| S c => n :: repeat n c
end.
Example test_repeat1:
repeat true 2 = cons true (cons true nil).
Proof. reflexivity. Qed.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
intros. simpl. reflexivity.
Qed.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
intros.
induction s.
Case "[]".
simpl. reflexivity.
Case "cons".
simpl. rewrite IHs. simpl. reflexivity.
Qed.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
intros. induction l.
Case "[]".
simpl. reflexivity.
Case "cons".
simpl. rewrite rev_snoc. rewrite IHl. reflexivity.
Qed.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
intros.
induction l1.
Case "[]".
simpl. reflexivity.
Case "cons".
simpl. rewrite IHl1. reflexivity.
Qed.
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** *** *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Eval compute in (combine [1;2] [false;false;true;true]).
print? []
*)
Check @combine.
Eval compute in (combine [1;2] [false;false;true;true]).
(** **** Exercise: 2 stars (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split
{X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
match l with
| [] => ([],[])
| (x,y)::t => match split t with
| (xs,ys) => (x::xs,y::ys)
end
end.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof.
reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** *** *)
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4;5;6;7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1];[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
match l with
| [] => None
| h::_ => Some h
end.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1;2] = Some 1.
reflexivity. Qed.
Example test_hd_opt2 : hd_opt [[1];[2]] = Some [1].
reflexivity. Qed.
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z := match p with (x,y) => f x y end.
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
intros. unfold prod_curry. unfold prod_uncurry. reflexivity.
Qed.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
intros. destruct p. simpl. unfold prod_curry. reflexivity.
Qed.
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
(** *** *)
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** *** *)
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
filter (fun n => andb (negb (ble_nat n 7)) (evenb n)) l.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
reflexivity. Qed.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
reflexivity. Qed.
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(filter test l, filter (fun x => negb (test x)) l).
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
reflexivity. Qed.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
reflexivity. Qed.
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** *** *)
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** ** Map for options *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_snoc: forall (X Y : Type) (f: X -> Y) (l: list X) (x: X),
map f (snoc l x) = snoc (map f l) (f x).
Proof.
intros.
induction l.
Case "[]". simpl. reflexivity.
Case "cons". simpl. rewrite <- IHl. reflexivity.
Qed.
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
intros.
induction l.
Case "[]". simpl. reflexivity.
Case "cons". simpl. rewrite <- IHl. rewrite map_snoc. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X) : (list Y) :=
match l with
| [] => []
| x::xs => f x ++ flat_map f xs
end.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
reflexivity. Qed.
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X) : option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** *** *)
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 : fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X := fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
(** *** *)
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** *** *)
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
intros. unfold override. simpl. unfold constfun. reflexivity.
Qed.
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the next chapter. For now, though, let's introduce just
one very useful tactic that will also help us with proving
properties of some of the other functions we have introduced in
this chapter. *)
(* ###################################################### *)
(* ###################################################### *)
(** * The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Abort.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
intros.
simpl. unfold override. rewrite H. rewrite H0. reflexivity.
Qed.
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
Proof. intros. induction l.
Case "[]". unfold fold_length. simpl. reflexivity.
Case "cons". simpl. rewrite <- IHl. unfold fold_length. simpl. reflexivity.
Qed.
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
fold (fun x l' => f x :: l') l [].
(** Write down a theorem [fold_map_correct] in Coq stating that
[fold_map] is correct, and prove it. *)
Theorem fold_map_correct : forall (X Y: Type) (f: X -> Y) (l: list X),
fold_map f l = map f l.
Proof. intros. induction l.
Case "[]". unfold fold_map. simpl. reflexivity.
Case "cons". simpl. rewrite <- IHl. unfold fold_map. simpl. reflexivity.
Qed.
(** **** Exercise: 2 stars, advanced (index_informal) *)
(** Recall the definition of the [index] function:
Fixpoint index {X : Type} (n : nat) (l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Write an informal proof of the following theorem:
forall X n l, length l = n -> @index X n l = None.
**)
(* FILL IN HERE *)
(*
Theorem length_index_none : forall X n l, length l = n -> @index X n l = None.
Proof. intros. induction l.
Case "[]". reflexivity.
Case "cons". simpl.
destruct n.
SCase "n=0". simpl. simpl in H. inversion H.
SCase "n>0". simpl. simpl in H. inversion H.
Theorem L:
here we prove that given a list of length list n, there is no value at index n in the list
(or that index n l returns None).
proof by induction on l.
base case, l = []
by the definition of index, index n [] returns None immediately.
induction step.
assume for any list l,
IH: length l = n -> index n l = None, we must prove that
index n (x::l) = None
by the definition of index n (x::l), we get
if beq_nat n 0 then Some x else index (pred n) l'
destruct n into 0 and S n'
Case 0: if beq_nat 0 0 then Some x else index (pred n) l'
STUCK....
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (church_numerals) *)
Module Church.
(** In this exercise, we will explore an alternative way of defining
natural numbers, using the so-called _Church numerals_, named
after mathematician Alonzo Church. We can represent a natural
number [n] as a function that takes a function [f] as a parameter
and returns [f] iterated [n] times. More formally, *)
Definition nat := forall X : Type, (X -> X) -> X -> X.
(** Let's see how to write some numbers with this notation. Any
function [f] iterated once shouldn't change. Thus, *)
Definition one : nat :=
fun (X : Type) (f : X -> X) (x : X) => f x.
(** [two] should apply [f] twice to its argument: *)
Definition two : nat :=
fun (X : Type) (f : X -> X) (x : X) => f (f x).
(** [zero] is somewhat trickier: how can we apply a function zero
times? The answer is simple: just leave the argument untouched. *)
Definition zero : nat :=
fun (X : Type) (f : X -> X) (x : X) => x.
(** More generally, a number [n] will be written as [fun X f x => f (f
... (f x) ...)], with [n] occurrences of [f]. Notice in particular
how the [doit3times] function we've defined previously is actually
just the representation of [3]. *)
Definition three : nat := @doit3times.
(** Complete the definitions of the following functions. Make sure
that the corresponding unit tests pass by proving them with
[reflexivity]. *)
(** Successor of a natural number *)
Definition succ (n : nat) : nat :=
fun (X: Type) (f: X -> X) (x: X) => n X f (f x).
Example succ_1 : succ zero = one.
Proof. reflexivity. Qed.
Example succ_2 : succ one = two.
Proof. reflexivity. Qed.
Example succ_3 : succ two = three.
Proof. reflexivity. Qed.
(** Addition of two natural numbers *)
Definition plus (n m : nat) : nat :=
fun (X: Type) (f: X -> X) (x: X) => m X f (n X f x).
Example plus_1 : plus zero one = one.
Proof. reflexivity. Qed.
Example plus_2 : plus two three = plus three two.
Proof. reflexivity. Qed.
Example plus_3 :
plus (plus two two) three = plus one (plus three three).
Proof. reflexivity. Qed.
(** Multiplication *)
Definition mult (n m : nat) : nat :=
fun (X: Type) (f: X -> X) (x: X) => m X (n X f) x.
Example mult_1 : mult one one = one.
Proof. reflexivity. Qed.
Example mult_2 : mult zero (plus three three) = zero.
Proof. reflexivity. Qed.
Example mult_3 : mult two three = plus three three.
Proof. reflexivity. Qed.
(** Exponentiation *)
(** Hint: Polymorphism plays a crucial role here. However, choosing
the right type to iterate over can be tricky. If you hit a
"Universe inconsistency" error, try iterating over a different
type: [nat] itself is usually problematic.
Definition nat := forall X : Type, (X -> X) -> X -> X.
*)
Definition exp (n m : nat) : nat :=
fun (X : Type) => m (X -> X) (n X).
Example exp_1 : exp two two = plus two two.
Proof. reflexivity. Qed.
Example exp_2 : exp three two = plus (mult two (mult two two)) one.
Proof. reflexivity. Qed.
Example exp_3 : exp three zero = one.
Proof. reflexivity. Qed.
End Church.
(** [] *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
// megafunction wizard: %LPM_DIVIDE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_DIVIDE
// ============================================================
// File Name: alt_div.v
// Megafunction Name(s):
// LPM_DIVIDE
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_div (
denom,
numer,
quotient,
remain);
input [31:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [31:0] remain;
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] quotient = sub_wire0[31:0];
wire [31:0] remain = sub_wire1[31:0];
lpm_divide LPM_DIVIDE_component (
.denom (denom),
.numer (numer),
.quotient (sub_wire0),
.remain (sub_wire1),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0));
defparam
LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 32,
LPM_DIVIDE_component.lpm_widthn = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
// Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]"
// Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]"
// Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]"
// Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]"
// Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0
// Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0
// Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0
// Retrieval info: CONNECT: remain 0 0 32 0 @remain 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_div.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_div.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_div.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_div.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_div_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_div_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
// Closed loop solution
module cdc_pulse_sync (
input wire clk_in,
input wire pulse_in,
input wire clk_out,
output wire pulse_out
);
wire aq_sync;
reg [1:0] in_pre_sync;
always @(posedge clk_in) begin
in_pre_sync[0] <= pulse_in;
in_pre_sync[1] <= in_pre_sync[0];
end
wire pulse_in_flag;
assign pulse_in_flag = !in_pre_sync[1] && in_pre_sync[0];
reg in_sync_pulse;
initial in_sync_pulse = 0; // works only in FPGA
always @(posedge clk_in) begin
if (aq_sync)
in_sync_pulse <= 0;
else if (pulse_in_flag)
in_sync_pulse <= 1;
end
(* ASYNC_REG = "TRUE" *) reg out_sync_ff_1;
(* ASYNC_REG = "TRUE" *) reg out_sync_ff_2;
reg out_sync_ff_3;
always @(posedge clk_out) begin
out_sync_ff_1 <= in_sync_pulse;
out_sync_ff_2 <= out_sync_ff_1;
out_sync_ff_3 <= out_sync_ff_2;
end
assign pulse_out = !out_sync_ff_3 && out_sync_ff_2;
(* ASYNC_REG = "TRUE" *) reg aq_sync_ff_1;
(* ASYNC_REG = "TRUE" *) reg aq_sync_ff_2;
always @(posedge clk_in) begin
aq_sync_ff_1 <= out_sync_ff_2;
aq_sync_ff_2 <= aq_sync_ff_1;
end
assign aq_sync = aq_sync_ff_2;
endmodule
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : bus_addr_dec.v
//Project Name : azpr_soc
//Description : the bus arbiter.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/bus_addr_dec.v
//License : CPL
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 01-07-2016 17:00(1th Fri,July,2016)
//First Author : lichangbeiju
//Modify Date : 02-09-2016 14:20(1th Sun,July,2016)
//Last Author : lichangbeiju
//Version Number : 002
//Last Commit : 03-09-2016 14:30(1th Sun,July,2016)
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.21 - lichangbeiju - Add io port.
//****************************************************************************************************
`include "../sys_include.h"
`include "bus.h"
module bus_addr_dec(
input wire [`WordAddrBus] s_addr ,//30 address
output reg s0_cs_n ,//01 slave 0 chip select rom
output reg s1_cs_n ,//01 slave 1 chip select spm
output reg s2_cs_n ,//01 slave 2 chip select timer
output reg s3_cs_n ,//01 slave 3 chip select uart
output reg s4_cs_n ,//01 slave 4 chip select gpio
output reg s5_cs_n ,//01 slave 5 chip select nc
output reg s6_cs_n ,//01 slave 6 chip select nc
output reg s7_cs_n //01 slave 7 chip select nc
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
// `define UDP
// `define CLK_TEST_EN
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
wire [02:00] s_index ;//the bus slave index
//************************************************************************************************
// 3.Main code
//************************************************************************************************
assign s_index = s_addr[`BusSlaveIndexLoc];
//------------------------------------------------------------------------------------------------
// 3.1 the master grant logic
//------------------------------------------------------------------------------------------------
always @(*) begin : BUS_SLAVE_INDEX
s0_cs_n = `DISABLE_N;
s1_cs_n = `DISABLE_N;
s2_cs_n = `DISABLE_N;
s3_cs_n = `DISABLE_N;
s4_cs_n = `DISABLE_N;
s5_cs_n = `DISABLE_N;
s6_cs_n = `DISABLE_N;
s7_cs_n = `DISABLE_N;
case(s_index)
`BUS_SLAVE_0 : begin
s0_cs_n = `ENABLE_N;
end
`BUS_SLAVE_1 : begin
s1_cs_n = `ENABLE_N;
end
`BUS_SLAVE_2 : begin
s2_cs_n = `ENABLE_N;
end
`BUS_SLAVE_3 : begin
s3_cs_n = `ENABLE_N;
end
`BUS_SLAVE_4 : begin
s4_cs_n = `ENABLE_N;
end
`BUS_SLAVE_5 : begin
s5_cs_n = `ENABLE_N;
end
`BUS_SLAVE_6 : begin
s6_cs_n = `ENABLE_N;
end
`BUS_SLAVE_7 : begin
s7_cs_n = `ENABLE_N;
end
endcase
end
//------------------------------------------------------------------------------------------------
// 3.2 the master owner control logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 4.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the clk generate module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
(** * Types: Type Systems *)
Require Export Smallstep.
Hint Constructors multi.
(** Our next major topic is _type systems_ -- static program
analyses that classify expressions according to the "shapes" of
their results. We'll begin with a typed version of a very simple
language with just booleans and numbers, to introduce the basic
ideas of types, typing rules, and the fundamental theorems about
type systems: _type preservation_ and _progress_. Then we'll move
on to the _simply typed lambda-calculus_, which lives at the core
of every modern functional programming language (including
Coq). *)
(* ###################################################################### *)
(** * Typed Arithmetic Expressions *)
(** To motivate the discussion of type systems, let's begin as
usual with an extremely simple toy language. We want it to have
the potential for programs "going wrong" because of runtime type
errors, so we need something a tiny bit more complex than the
language of constants and addition that we used in chapter
[Smallstep]: a single kind of data (just numbers) is too simple,
but just two kinds (numbers and booleans) already gives us enough
material to tell an interesting story.
The language definition is completely routine. The only thing to
notice is that we are _not_ using the [asnum]/[aslist] trick that
we used in chapter [HoareList] to make all the operations total by
forcibly coercing the arguments to [+] (for example) into numbers.
Instead, we simply let terms get stuck if they try to use an
operator with the wrong kind of operands: the [step] relation
doesn't relate them to anything. *)
(* ###################################################################### *)
(** ** Syntax *)
(** Informally:
t ::= true
| false
| if t then t else t
| 0
| succ t
| pred t
| iszero t
Formally:
*)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| tzero : tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tiszero : tm -> tm.
(** _Values_ are [true], [false], and numeric values... *)
Inductive bvalue : tm -> Prop :=
| bv_true : bvalue ttrue
| bv_false : bvalue tfalse.
Inductive nvalue : tm -> Prop :=
| nv_zero : nvalue tzero
| nv_succ : ∀ t, nvalue t -> nvalue (tsucc t).
Definition value (t:tm) := bvalue t \/ nvalue t.
Hint Constructors bvalue nvalue.
Hint Unfold value.
(* ###################################################################### *)
(** ** Operational Semantics *)
(** Informally: *)
(**
------------------------------ (ST_IfTrue)
if true then t1 else t2 ==> t1
------------------------------- (ST_IfFalse)
if false then t1 else t2 ==> t2
t1 ==> t1'
------------------------- (ST_If)
if t1 then t2 else t3 ==>
if t1' then t2 else t3
t1 ==> t1'
-------------------- (ST_Succ)
succ t1 ==> succ t1'
------------ (ST_PredZero)
pred 0 ==> 0
numeric value v1
--------------------- (ST_PredSucc)
pred (succ v1) ==> v1
t1 ==> t1'
-------------------- (ST_Pred)
pred t1 ==> pred t1'
----------------- (ST_IszeroZero)
iszero 0 ==> true
numeric value v1
-------------------------- (ST_IszeroSucc)
iszero (succ v1) ==> false
t1 ==> t1'
------------------------ (ST_Iszero)
iszero t1 ==> iszero t1'
*)
(** Formally: *)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : ∀ t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : ∀ t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : ∀ t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Succ : ∀ t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_PredZero :
(tpred tzero) ==> tzero
| ST_PredSucc : ∀ t1,
nvalue t1 ->
(tpred (tsucc t1)) ==> t1
| ST_Pred : ∀ t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_IszeroZero :
(tiszero tzero) ==> ttrue
| ST_IszeroSucc : ∀ t1,
nvalue t1 ->
(tiszero (tsucc t1)) ==> tfalse
| ST_Iszero : ∀ t1 t1',
t1 ==> t1' ->
(tiszero t1) ==> (tiszero t1')
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredZero"
| Case_aux c "ST_PredSucc" | Case_aux c "ST_Pred"
| Case_aux c "ST_IszeroZero" | Case_aux c "ST_IszeroSucc"
| Case_aux c "ST_Iszero" ].
Hint Constructors step.
(** Notice that the [step] relation doesn't care about whether
expressions make global sense -- it just checks that the operation
in the _next_ reduction step is being applied to the right kinds
of operands.
For example, the term [succ true] (i.e., [tsucc ttrue] in the
formal syntax) cannot take a step, but the almost as obviously
nonsensical term
succ (if true then true else true)
can take a step (once, before becoming stuck). *)
(* ###################################################################### *)
(** ** Normal Forms and Values *)
(** The first interesting thing about the [step] relation in this
language is that the strong progress theorem from the Smallstep
chapter fails! That is, there are terms that are normal
forms (they can't take a step) but not values (because we have not
included them in our definition of possible "results of
evaluation"). Such terms are _stuck_. *)
Notation step_normal_form := (normal_form step).
Definition stuck (t:tm) : Prop :=
step_normal_form t /\ ~ value t.
Hint Unfold stuck.
(** **** Exercise: 2 stars (some_term_is_stuck) *)
Example some_term_is_stuck : exists t, stuck t.
exists (tiszero ttrue); split; intro; solve by inversion 3.
Qed.
(** [] *)
(** However, although values and normal forms are not the same in this
language, the former set is included in the latter. This is
important because it shows we did not accidentally define things
so that some value could still take a step. *)
(** **** Exercise: 3 stars, advanced (value_is_nf) *)
(** Hint: You will reach a point in this proof where you need to
use an induction to reason about a term that is known to be a
numeric value. This induction can be performed either over the
term itself or over the evidence that it is a numeric value. The
proof goes through in either case, but you will find that one way
is quite a bit shorter than the other. For the sake of the
exercise, try to complete the proof both ways. *)
Lemma value_is_nf : ∀ t, value t -> step_normal_form t.
introv Hv Hnf; destruct Hnf; destruct Hv; intros;
repeat match goal with
| [ p : tsucc _ ==> _ |- _ ] => inverts p
| [ IH : forall x, ?t ==> x -> False, _ : ?t ==> _ |- _ ] =>
exfalso; eapply IH; eauto
| [ p1 : nvalue ?t, p2 : ?t ==> ?t' |- _ ] =>
generalize dependent t'; induction p1; intros; [solve by inversion | ]
| _ => solve by inversion 2
end.
Qed.
Hint Resolve value_is_nf.
(** [] *)
(** **** Exercise: 3 stars, optional (step_deterministic) *)
(** Using [value_is_nf], we can show that the [step] relation is
also deterministic... *)
Lemma nf_s : ∀ t, step_normal_form t -> step_normal_form (tsucc t).
unfold normal_form; destruct 2 as [k Hnfst]; inverts Hnfst; nexelim. Qed.
Hint Resolve nf_s.
Theorem step_deterministic : deterministic step.
introv Hy1 Hy2.
generalize dependent y2; induction Hy1; intros;
inverts Hy2; crush; try solve by inversion;
match goal with
| [ p1 : nvalue ?t, p2 : tsucc ?t ==> _ |- _ ]
=> exfalso; assert (step_normal_form (tsucc t)) by crush;
unfold normal_form in *; nexelim
| [ IH : forall t2, ?t ==> t2 -> ?t1 = t2, p : ?t ==> ?t2 |- _]
=> apply IH in p; crush
end.
Qed.
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(** The next critical observation about this language is that,
although there are stuck terms, they are all "nonsensical", mixing
booleans and numbers in a way that we don't even _want_ to have a
meaning. We can easily exclude such ill-typed terms by defining a
_typing relation_ that relates terms to the types (either numeric
or boolean) of their final results. *)
Inductive ty : Type :=
| TBool : ty
| TNat : ty.
(** In informal notation, the typing relation is often written
[|- t ∈ T], pronounced "[t] has type [T]." The [|-] symbol is
called a "turnstile". (Below, we're going to see richer typing
relations where an additional "context" argument is written to the
left of the turnstile. Here, the context is always empty.) *)
(**
---------------- (T_True)
|- true ∈ Bool
----------------- (T_False)
|- false ∈ Bool
|- t1 ∈ Bool |- t2 ∈ T |- t3 ∈ T
-------------------------------------------- (T_If)
|- if t1 then t2 else t3 ∈ T
------------ (T_Zero)
|- 0 ∈ Nat
|- t1 ∈ Nat
------------------ (T_Succ)
|- succ t1 ∈ Nat
|- t1 ∈ Nat
------------------ (T_Pred)
|- pred t1 ∈ Nat
|- t1 ∈ Nat
--------------------- (T_IsZero)
|- iszero t1 ∈ Bool
*)
Reserved Notation "'|-' t '∈' T" (at level 40).
Inductive has_type : tm -> ty -> Prop :=
| T_True :
|- ttrue ∈ TBool
| T_False :
|- tfalse ∈ TBool
| T_If : ∀ t1 t2 t3 T,
|- t1 ∈ TBool ->
|- t2 ∈ T ->
|- t3 ∈ T ->
|- tif t1 t2 t3 ∈ T
| T_Zero :
|- tzero ∈ TNat
| T_Succ : ∀ t1,
|- t1 ∈ TNat ->
|- tsucc t1 ∈ TNat
| T_Pred : ∀ t1,
|- t1 ∈ TNat ->
|- tpred t1 ∈ TNat
| T_Iszero : ∀ t1,
|- t1 ∈ TNat ->
|- tiszero t1 ∈ TBool
where "'|-' t '∈' T" := (has_type t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_True" | Case_aux c "T_False" | Case_aux c "T_If"
| Case_aux c "T_Zero" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Iszero" ].
Hint Constructors has_type.
(* ###################################################################### *)
(** *** Examples *)
(** It's important to realize that the typing relation is a
_conservative_ (or _static_) approximation: it does not calculate
the type of the normal form of a term. *)
Example has_type_1 :
|- tif tfalse tzero (tsucc tzero) ∈ TNat.
Proof. auto. Qed.
(** (Since we've included all the constructors of the typing relation
in the hint database, the [auto] tactic can actually find this
proof automatically.) *)
Example has_type_not :
~ (|- tif tfalse tzero ttrue ∈ TBool).
Proof. intro; solve by inversion 2. Qed.
(** **** Exercise: 1 star, optional (succ_hastype_nat__hastype_nat) *)
Example succ_hastype_nat__hastype_nat : ∀ t,
|- tsucc t ∈ TNat ->
|- t ∈ TNat.
Proof. inversion 1; crush. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Canonical forms *)
(** The following two lemmas capture the basic property that defines
the shape of well-typed values. They say that the definition of value
and the typing relation agree. *)
Lemma bool_canonical : ∀ t,
|- t ∈ TBool -> value t -> bvalue t.
Proof. repeat inversion 1; crush; solve by inversion. Qed.
Lemma nat_canonical : ∀ t,
|- t ∈ TNat -> value t -> nvalue t.
Proof. repeat inversion 1; crush; solve by inversion. Qed.
Hint Resolve bool_canonical nat_canonical.
(* ###################################################################### *)
(** ** Progress *)
(** The typing relation enjoys two critical properties. The first is
that well-typed normal forms are values (i.e., not stuck). *)
Theorem progress : ∀ t T,
|- t ∈ T ->
value t \/ exists t', t ==> t'.
(** **** Exercise: 3 stars (finish_progress) *)
(** Complete the formal proof of the [progress] property. (Make sure
you understand the informal proof fragment in the following
exercise before starting -- this will save you a lot of time.) *)
induction 1; destr_sums; destr_prods; eauto;
match goal with
| [ p : value ?t, _ : |- ?t ∈ TBool |- _ ] =>
apply bool_canonical in p; eauto
| [ p : value ?t, _ : |- ?t ∈ TNat |- _ ] =>
apply nat_canonical in p; eauto
end;
match goal with
| [ p : bvalue _ |- _ ] => inverts p
| [ p : nvalue _ |- _ ] => inverts p
end; right; eauto.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_progress_informal) *)
(** Complete the corresponding informal proof: *)
(** _Theorem_: If [|- t ∈ T], then either [t] is a value or else
[t ==> t'] for some [t']. *)
(** _Proof_: By induction on a derivation of [|- t ∈ T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 ∈ Bool], [|- t2 ∈ T] and [|- t3
∈ T]. By the IH, either [t1] is a value or else [t1] can step
to some [t1'].
- If [t1] is a value, then by the canonical forms lemmas
and the fact that [|- t1 ∈ Bool] we have that [t1]
is a [bvalue] -- i.e., it is either [true] or [false].
If [t1 = true], then [t] steps to [t2] by [ST_IfTrue],
while if [t1 = false], then [t] steps to [t3] by
[ST_IfFalse]. Either way, [t] can step, which is what
we wanted to show.
- If [t1] itself can take a step, then, by [ST_If], so can
[t].
(* Fill in here *)
[]
*)
(** This is more interesting than the strong progress theorem that we
saw in the Smallstep chapter, where _all_ normal forms were
values. Here, a term can be stuck, but only if it is ill
typed. *)
(** **** Exercise: 1 star (step_review) *)
(** Quick review. Answer _true_ or _false_. In this language...
- Every well-typed normal form is a value.
- true
- Every value is a normal form.
- false
- The single-step evaluation relation is
a partial function (i.e., it is deterministic).
- The single-step evaluation relation is a _total_ function.
*)
(** [] *)
(* ###################################################################### *)
(** ** Type Preservation *)
(** The second critical property of typing is that, when a well-typed
term takes a step, the result is also a well-typed term.
This theorem is often called the _subject reduction_ property,
because it tells us what happens when the "subject" of the typing
relation is reduced. This terminology comes from thinking of
typing statements as sentences, where the term is the subject and
the type is the predicate. *)
Theorem preservation : ∀ t t' T,
|- t ∈ T ->
t ==> t' ->
|- t' ∈ T.
(** **** Exercise: 2 stars (finish_preservation) *)
(** Complete the formal proof of the [preservation] property. (Again,
make sure you understand the informal proof fragment in the
following exercise first.) *)
Proof. introv Ht Hst;
generalize dependent t'; induction Ht; intros; inverts Hst;
match goal with
| [ p : |- tsucc _ ∈ TNat |- _ ] => inverts p
| _ => idtac
end; crush.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_preservation_informal) *)
(** Complete the following proof: *)
(** _Theorem_: If [|- t ∈ T] and [t ==> t'], then [|- t' ∈ T]. *)
(** _Proof_: By induction on a derivation of [|- t ∈ T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 ∈ Bool], [|- t2 ∈ T] and [|- t3
∈ T].
Inspecting the rules for the small-step reduction relation and
remembering that [t] has the form [if ...], we see that the
only ones that could have been used to prove [t ==> t'] are
[ST_IfTrue], [ST_IfFalse], or [ST_If].
- If the last rule was [ST_IfTrue], then [t' = t2]. But we
know that [|- t2 ∈ T], so we are done.
- If the last rule was [ST_IfFalse], then [t' = t3]. But we
know that [|- t3 ∈ T], so we are done.
- If the last rule was [ST_If], then [t' = if t1' then t2
else t3], where [t1 ==> t1']. We know [|- t1 ∈ Bool] so,
by the IH, [|- t1' ∈ Bool]. The [T_If] rule then gives us
[|- if t1' then t2 else t3 ∈ T], as required.
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars (preservation_alternate_proof) *)
(** Now prove the same property again by induction on the
_evaluation_ derivation instead of on the typing derivation.
Begin by carefully reading and thinking about the first few
lines of the above proof to make sure you understand what
each one is doing. The set-up for this proof is similar, but
not exactly the same. *)
Theorem nvalue_tnat : forall t, nvalue t -> |- t ∈ TNat.
induction 1; crush. Qed.
Hint Resolve nvalue_tnat.
Theorem preservation' : ∀ t t' T,
|- t ∈ T ->
t ==> t' ->
|- t' ∈ T.
introv Ht Hst; generalize dependent T; induction Hst; inversion 1; crush. Qed.
Hint Resolve preservation.
(** [] *)
(* ###################################################################### *)
(** ** Type Soundness *)
(** Putting progress and preservation together, we can see that a
well-typed term can _never_ reach a stuck state. *)
Definition multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Ltac prog :=
repeat match goal with
| [ p : |- ?t ∈ ?T |- _] =>
extend (progress t T p)
end.
Ltac preservation :=
repeat match goal with
| [ p1 : |- ?t1 ∈ ?T, p2 : ?t1 ==> ?t2 |- _ ] =>
extend (preservation t1 t2 T p1 p2)
end.
Corollary soundness : ∀ t t' T,
|- t ∈ T ->
t ==>* t' ->
~(stuck t').
unfold stuck; induction 2; intros; [prog | preservation]; crush. Qed.
(* ###################################################################### *)
(** * Aside: the [normalize] Tactic *)
(** When experimenting with definitions of programming languages in
Coq, we often want to see what a particular concrete term steps
to -- i.e., we want to find proofs for goals of the form [t ==>*
t'], where [t] is a completely concrete term and [t'] is unknown.
These proofs are simple but repetitive to do by hand. Consider for
example reducing an arithmetic expression using the small-step
relation [astep]. *)
Definition amultistep st := multi (astep st).
Notation " t '/' st '==>a*' t' " := (amultistep st t t')
(at level 40, st at level 39).
Example astep_example1 :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
apply multi_step with (APlus (ANum 3) (ANum 12)).
apply AS_Plus2.
apply av_num.
apply AS_Mult.
apply multi_step with (ANum 15).
apply AS_Plus.
apply multi_refl.
Qed.
(** We repeatedly apply [multi_step] until we get to a normal
form. The proofs that the intermediate steps are possible are
simple enough that [auto], with appropriate hints, can solve
them. *)
Hint Constructors astep aval.
Example astep_example1' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
eapply multi_step. auto. simpl.
eapply multi_step. auto. simpl.
apply multi_refl.
Qed.
(** The following custom [Tactic Notation] definition captures this
pattern. In addition, before each [multi_step] we print out the
current goal, so that the user can follow how the term is being
evaluated. *)
Tactic Notation "print_goal" := match goal with |- ?x => idtac x end.
Tactic Notation "normalize" :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; simpl)]);
apply multi_refl.
Example astep_example1'' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
normalize.
(* At this point in the proof script, the Coq response shows
a trace of how the expression evaluated.
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ANum 15)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) (ANum 15))
(multi (astep empty_state) (ANum 15) (ANum 15))
*)
Qed.
(** The [normalize] tactic also provides a simple way to calculate
what the normal form of a term is, by proving a goal with an
existential variable in it. *)
Example astep_example1''' : exists e',
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* e'.
Proof.
eapply ex_intro. normalize.
(* This time, the trace will be:
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ??)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) ??)
(multi (astep empty_state) (ANum 15) ??)
where ?? is the variable ``guessed'' by eapply.
*)
Qed.
(** **** Exercise: 1 star (normalize_ex) *)
Theorem normalize_ex : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof with normalize. eexists... Qed.
(** [] *)
(** **** Exercise: 1 star, optional (normalize_ex') *)
(** For comparison, prove it using [apply] instead of [eapply]. *)
Theorem normalize_ex' : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof with normalize. econstructor... Qed.
(** [] *)
(* ###################################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 2 stars (subject_expansion) *)
(** Having seen the subject reduction property, it is reasonable to
wonder whether the opposity property -- subject _expansion_ --
also holds. That is, is it always the case that, if [t ==> t']
and [|- t' ∈ T], then [|- t ∈ T]? If so, prove it. If
not, give a counter-example. (You do not need to prove your
counter-example in Coq, but feel free to do so if you like.)
tif ttrue ttrue tzero isn't well typed, but evaluates to a well typed expression
[]
*)
(** **** Exercise: 2 stars (variation1) *)
(** Suppose, that we add this new rule to the typing relation:
| T_SuccBool : ∀ t,
|- t ∈ TBool ->
|- tsucc t ∈ TBool
Which of the following properties remain true in the presence of
this rule? For each one, write either "remains true" or
else "becomes false." If a property becomes false, give a
counterexample.
- Determinism of [step]
- stays
- Progress
- nope
- Preservation
- stays
[]
*)
(** **** Exercise: 2 stars (variation2) *)
(** Suppose, instead, that we add this new rule to the [step] relation:
| ST_Funny1 : ∀ t2 t3,
(tif ttrue t2 t3) ==> t3
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
determinism
tif ttrue ttrue tfalse ==> ttrue /\ tif ttrue ttrue tfalse ==> tfalse
[]
*)
(** **** Exercise: 2 stars, optional (variation3) *)
(** Suppose instead that we add this rule:
| ST_Funny2 : ∀ t1 t2 t2' t3,
t2 ==> t2' ->
(tif t1 t2 t3) ==> (tif t1 t2' t3)
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation4) *)
(** Suppose instead that we add this rule:
| ST_Funny3 :
(tpred tfalse) ==> (tpred (tpred tfalse))
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation5) *)
(** Suppose instead that we add this rule:
| T_Funny4 :
|- tzero ∈ TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation6) *)
(** Suppose instead that we add this rule:
| T_Funny5 :
|- tpred tzero ∈ TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 3 stars, optional (more_variations) *)
(** Make up some exercises of your own along the same lines as
the ones above. Try to find ways of selectively breaking
properties -- i.e., ways of changing the definitions that
break just one of the properties and leave the others alone.
[]
*)
(** **** Exercise: 1 star (remove_predzero) *)
(** The evaluation rule [E_PredZero] is a bit counter-intuitive: we
might feel that it makes more sense for the predecessor of zero to
be undefined, rather than being defined to be zero. Can we
achieve this simply by removing the rule from the definition of
[step]? Would doing so create any problems elsewhere?
Nope, we also need to remove the T_Pred rule from has_type
Once we do that though all properties are preserved
[] *)
Module nopredzero.
Reserved Notation "t1 ==> t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : Π t1 t2, tif ttrue t1 t2 ==> t1
| ST_IfFalse : Π t1 t2, tif tfalse t1 t2 ==> t2
| ST_If : Π t1 t1' t2 t3, t1 ==> t1' -> tif t1 t2 t3 ==> tif t1' t2 t3
| ST_Succ : Π t1 t1', t1 ==> t1' -> tsucc t1 ==> tsucc t1'
| ST_PredSucc : Π t, nvalue t -> tpred (tsucc t) ==> t
| ST_Pred : Π t t', t ==> t' -> tpred t ==> tpred t'
| ST_IszeroZero : tiszero tzero ==> ttrue
| ST_IszeroSucc : Π t, nvalue t -> tiszero (tsucc t) ==> tfalse
| ST_Iszero : Π t t', t ==> t' -> tiszero t ==> tiszero t'
where "t1 ==> t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredSucc" | Case_aux c "ST_Pred"
| Case_aux c "ST_IszeroZero" | Case_aux c "ST_IszeroSucc"
| Case_aux c "ST_Iszero" ].
Hint Constructors step.
Reserved Notation "'|-' t '∈' T" (at level 40).
Inductive has_type : tm -> ty -> Prop :=
| T_True :
|- ttrue ∈ TBool
| T_False :
|- tfalse ∈ TBool
| T_If : ∀ t1 t2 t3 T,
|- t1 ∈ TBool ->
|- t2 ∈ T ->
|- t3 ∈ T ->
|- tif t1 t2 t3 ∈ T
| T_Zero :
|- tzero ∈ TNat
| T_Succ : ∀ t1,
|- t1 ∈ TNat ->
|- tsucc t1 ∈ TNat
| T_Iszero : ∀ t1,
|- t1 ∈ TNat ->
|- tiszero t1 ∈ TBool
where "'|-' t '∈' T" := (has_type t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_True" | Case_aux c "T_False" | Case_aux c "T_If"
| Case_aux c "T_Zero" | Case_aux c "T_Succ" | Case_aux c "T_Iszero" ].
Hint Constructors has_type.
Lemma nv_sp : forall t, nvalue t <-> nvalue (tsucc t).
split; inversion 1; crush. Qed.
Lemma bool_canonical : forall t, |- t ∈ TBool -> value t -> bvalue t.
repeat inversion 1; crush; solve by inversion. Qed.
Lemma nat_canonical : forall t, |- t ∈ TNat -> value t -> nvalue t.
repeat inversion 1; crush; solve by inversion. Qed.
Hint Resolve nv_sp nat_canonical bool_canonical.
Ltac bn_canonize :=
repeat match goal with
[ p1 : |- ?t ∈ ?T, p2 : value ?t |- _ ] =>
match T with
| TBool => extend (bool_canonical t p1 p2)
| TNat => extend (nat_canonical t p1 p2)
end
end.
Ltac destr_bvals :=
repeat match goal with
| [ p : bvalue _ |- _ ] => inverts p
end.
Lemma tif_ex : forall t1 t2 t3,
|- t1 ∈ TBool ->
(value t1 \/ exists t', t1 ==> t') ->
exists t', tif t1 t2 t3 ==> t'.
destruct 2.
- bn_canonize; destr_bvals; eauto.
- destr_prods; eauto.
Qed.
Hint Resolve tif_ex.
Theorem progress : Π t T,
|- t ∈ T →
value t \/ ∃ t', t ==> t'.
has_type_cases (induction 1) Case; eauto;
destr_sums; destr_prods; bn_canonize; eauto.
- Case "T_Iszero". right; inverts H1; eauto.
Qed.
Lemma nvalue_is_nf : forall t, nvalue t -> normal_form step t.
unfold normal_form; induction 1; destruct 1; try solve by inversion.
+ inverts H0; nexelim.
Qed.
Theorem value_is_nf : forall t, value t → normal_form step t.
destruct 1; [destr_bvals; intro; solve by inversion 2 | apply nvalue_is_nf; eauto].
Qed.
Theorem nf_is_value : forall t T, |- t ∈ T → normal_form step t → value t.
unfold normal_form; introv Ht; destruct (progress t T Ht); crush. Qed.
Hint Resolve value_is_nf nf_is_value.
Hint Immediate value_is_nf nf_is_value.
Theorem value_nf : forall t T, |- t ∈ T -> (value t <-> normal_form step t).
split; generalize dependent T; generalize dependent t; eauto. Qed.
Hint Rewrite value_nf.
Theorem tsucc_nf : forall t, nvalue t -> forall t', tsucc t ==> t' -> False.
induction 1; crush; try solve by inversion 2.
- match goal with [p : tsucc _ ==> _ |- _] => inverts p end; eauto.
Qed.
Hint Resolve tsucc_nf.
Theorem step_deterministic : Π t1 t2 t3,
t1 ==> t2 →
t1 ==> t3 →
t2 = t3.
introv Hst2 Hst3; generalize dependent t3; induction Hst2; intros;
inverts Hst3; eauto; try (exfalso; eauto; solve by inversion);
match goal with
| [ IH : forall t2, ?t ==> t2 -> ?t1 = t2,
p : ?t ==> ?t2 |- _ ] => apply IH in p; crush
| _ => idtac
end.
Qed.
End nopredzero.
(** **** Exercise: 4 stars, advanced (prog_pres_bigstep) *)
(** Suppose our evaluation relation is defined in the big-step style.
What are the appropriate analogs of the progress and preservation
properties?
(* FILL IN HERE *)
[]
*)
(* $Date: 2014-04-08 23:31:16 -0400 (Tue, 08 Apr 2014) $ *)
|
module uart_divider
#(parameter COUNT = 0, CLK2_MUL = 5)
(input sys_clk,
input reset,
output reg outclk,
output reg outclk2);
// COUNT values:
// 2.88MHz:
// Input @ 144MHz, COUNT = 25
// 576kHz:
// Input @ 144MHz, COUNT = 125
// 115.2kHz:
// Input @ 28.8MHz, COUNT = 125
// Input @ 144MHz, COUNT = 625
// 57.6kHz:
// Input @ 144MHz, COUNT = 1250
// TODO test:
// Input @ 28.8MHz, Output @ 57.6kHz, COUNT = 250
// Input @ 28.8MHz, Output @ 28.8kHz, COUNT = 500
// Input @ 144MHz, Output @ 115.2kHz, COUNT = 625
// TODO values:
// 1200, 2400, 4800, 9600, 19200, 28800, 38400, 57600, and 115200.
localparam BITS = $clog2(COUNT);
reg [(BITS-1):0] counter;
always @(posedge sys_clk or posedge reset)
begin
if(reset) begin
counter <= 'b0;
outclk <= 'b0;
end else begin
if(counter == (COUNT - 1)) begin
counter <= 'b0;
outclk <= ~outclk;
end else
counter <= counter + 1'b1;
end
end
// counter2 produces a clock that is a multiple of the uart clock.
// this clock is used to oversample the rx line
localparam COUNT2 = COUNT / CLK2_MUL;
localparam BITS2 = $clog2(COUNT2);
reg [(BITS2-1):0] counter2;
always @(posedge sys_clk or posedge reset)
begin
if(reset) begin
counter2 <= 'b0;
outclk2 <= 'b0;
end else begin
if(counter2 == (COUNT2 - 1)) begin
counter2 <= 'b0;
outclk2 <= ~outclk2;
end else
counter2 <= counter2 + 1'b1;
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_adl5904_rst (
input sys_cpu_clk,
input rf_peak_det_n,
output rf_peak_rst);
// internal registers
reg rf_peak_det_n_d = 'd0;
reg rf_peak_det_enb_d = 'd0;
reg rf_peak_rst_enb = 'd0;
reg rf_peak_rst_int = 'd0;
// internal signals
wire rf_peak_det_enb_s;
wire rf_peak_rst_1_s;
wire rf_peak_rst_0_s;
// adl5904 input protection
assign rf_peak_rst = rf_peak_rst_int;
assign rf_peak_det_enb_s = ~(rf_peak_det_n_d & rf_peak_det_n);
assign rf_peak_rst_1_s = ~rf_peak_det_enb_d & rf_peak_det_enb_s;
assign rf_peak_rst_0_s = rf_peak_det_enb_d & ~rf_peak_det_enb_s;
always @(posedge sys_cpu_clk) begin
rf_peak_det_n_d <= rf_peak_det_n;
rf_peak_det_enb_d <= rf_peak_det_enb_s;
if (rf_peak_rst_1_s == 1'b1) begin
rf_peak_rst_enb <= 1'b1;
end else if (rf_peak_rst_0_s == 1'b1) begin
rf_peak_rst_enb <= 1'b0;
end
rf_peak_rst_int = ~rf_peak_rst_int & rf_peak_rst_enb;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
`include "../include/tune.v"
module resetter(
clk,
rst_in_n,
rst_out_n );
parameter RST_CNT_SIZE = 4;
input clk;
input rst_in_n; // input of external asynchronous reset
output rst_out_n; // output of end-synchronized reset (beginning is asynchronous to clock)
reg rst_out_n;
reg [RST_CNT_SIZE:0] rst_cnt; // one bit more for counter stopping
reg rst1_n,rst2_n;
`ifdef SIMULATE
initial
begin
rst_cnt = 0;
rst1_n = 1'b0;
rst2_n = 1'b0;
rst_out_n = 1'b0;
end
`endif
always @(posedge clk, negedge rst_in_n)
if( !rst_in_n ) // external asynchronous reset
begin
rst_cnt <= 0;
rst1_n <= 1'b0;
rst2_n <= 1'b0;
rst_out_n <= 1'b0; // this zeroing also happens after FPGA configuration, so also power-up reset happens
end
else // clocking
begin
rst1_n <= 1'b1;
rst2_n <= rst1_n;
if( rst2_n && !rst_cnt[RST_CNT_SIZE] )
begin
rst_cnt <= rst_cnt + 1;
end
if( rst_cnt[RST_CNT_SIZE] )
begin
rst_out_n <= 1'b1;
end
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eca_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:27:22 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eca_e.v,v 1.1 2006/04/10 15:42:05 wig Exp $
// $Date: 2006/04/10 15:42:05 $
// $Log: inst_eca_e.v,v $
// Revision 1.1 2006/04/10 15:42:05 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_eca_e
//
// No user `defines in this module
module inst_eca_e
//
// Generated module inst_eca
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_eca_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: dma_engine_pci_xfer.v
// Project: CPCI (PCI Control FPGA)
// Description: PCI interface for DMA engine
//
// Note: read and write are from the perspective of the driver.
// Read means retrieve a packet from the CNET and place in memory.
// Write means send a packet from memory to CNET.
//
// Change history: 12/10/07 - Split from dma_engine
//
// Issues to address:
//
///////////////////////////////////////////////////////////////////////////////
module dma_engine_pci_xfer(
// PCI Signals
output [`PCI_DATA_WIDTH-1:0] dma_data, // Data being written to host
output [3:0] dma_cbe, // Command/Byte Enables for DMA data
output dma_vld, // There's currently data on the dma_data_bus
output dma_wrdn, // Transfer direction
// 1 - Write, 0 - read
output dma_request, // Request a new transaction
output dma_complete, // Finish current transaction
input dma_data_vld, // Indicates data should be captured
// from pci_data during a read or
// that a data transaction has
// occured during a write.
input dma_src_en, // The next piece of data should
// be provided on dma_data
input dma_lat_timeout, // Latency timer has expired
input dma_addr_st, // Core is in the address state
input dma_data_st, // Core is in the data state
input pci_retry, // Retry signal from CSRs
input pci_fatal, // Fatal error signal from CSRs
// CPCI register interface signals
input host_is_le, // The host is little endian
input [31:0] dma_time, // Number of clocks before a DMA transfer times out
output dma_timeout, // Indicates a timeout has occured
input [15:0] dma_retries, // Number of retries before a DMA transfer times out
output dma_retry_expire, // DMA retry counter has expired
// CNET DMA interface signals
input dma_wr_rdy, // There is space in the buffer
input dma_nearly_empty, // Three words or less left in the buffer
input dma_all_in_buf, // All data for the packet is in the buffer
// DMA engine signals
output done, // Transfer done?
output reg fatal,
output reg retry,
output abort_xfer, // Abort the transfer
output rd_undo, // Undo the current read
input start,
input ld_xfer_cnt,
input xfer_is_rd, // Transfer direction
output first_word_pci,// Transferring first word on PCI bus
output last_word_pci, // Transferring last word on PCI bus
input wr_fifo_empty, // Write fifo is empty
input dma_in_progress, // Is the engine idle
input enable_xfer_timer,
input reset_xfer_timer, // Reset the xfer counter
input [3:0] first_word_be,
input [3:0] last_word_be,
input [8:0] xfer_cnt_start, // Number of words to transfer
output reg [8:0] xfer_cnt, // Number of bytes left to transfer
// Note: xfer_cnt is how many have
// actually been transferred and
// acknowledged in the case of a 'read'.
input [`PCI_ADDR_WIDTH - 1 : 2] dma_addr, // Address pointer
input [`PCI_DATA_WIDTH - 1 : 0] rd_dout, // Output from FIFO
// Miscelaneous signals
input cnet_reprog, // Indicates that the CNET is
// currently being reprogrammed
input reset,
input clk
);
// ==================================================================
// Local
// ==================================================================
// Keep track of the data state
reg dma_data_d1;
wire dma_data_fell;
// Transaction termination variables
wire cnt3, cnt2, cnt1;
wire fin3, fin2, fin1;
wire assert_complete;
reg hold_complete;
wire full_buffer_abort;
// Command to send on CBE bus
wire [3:0] command;
wire [3:0] byte_enable;
// Byte-Enable for the first and last words
wire [3:0] first_word_be_swapped;
wire [3:0] last_word_be_swapped;
// Transfer timer
reg [31:0] xfer_timer;
// Retry counter
reg [15:0] retry_cnt;
// PCI transfer counter
//
// Note: xfer_cnt is how many have actually been transferred and
// acknowledged in the case of a 'read'.
// pci_cnt is how many have been transferred but not necessarily
// acknowledged.
reg [8:0] pci_cnt;
// ==================================================================
// Main DMA transfer state machine
// ==================================================================
reg [2:0] xfer_state;
`define DMA_Idle 3'h0
`define DMA_Req 3'h1
`define DMA_Write 3'h2
`define DMA_Read 3'h3
`define DMA_Dead 3'h4
`define DMA_Oops 3'h5
always @(posedge clk)
begin
// On either reset or the CNET being reprogrammed, go to the idle state
if (reset || cnet_reprog) begin
xfer_state <= `DMA_Idle;
end
else
case (xfer_state)
`DMA_Idle : begin
if (start)
xfer_state <= `DMA_Req;
end
`DMA_Req : begin
if (xfer_is_rd)
xfer_state <= `DMA_Write;
else
xfer_state <= `DMA_Read;
end
`DMA_Write : begin
if (dma_data_fell) begin
if (fatal)
xfer_state <= `DMA_Dead;
else
xfer_state <= `DMA_Oops;
end
end
`DMA_Read : begin
if (dma_data_fell) begin
if (fatal)
xfer_state <= `DMA_Dead;
else
xfer_state <= `DMA_Oops;
end
end
`DMA_Dead : begin
// Stay here until a reset is issued
end
`DMA_Oops : begin
xfer_state <= `DMA_Idle;
end
default : begin
xfer_state <= `DMA_Idle;
end
endcase
end
// ==================================================================
// Transfer timer
// ==================================================================
always @(posedge clk)
begin
if (reset)
xfer_timer <= - 'h1;
else if (reset_xfer_timer)
xfer_timer <= dma_time;
else if (enable_xfer_timer && xfer_timer != 'h0)
xfer_timer <= xfer_timer - 'h1;
end
assign dma_timeout = (xfer_timer == 'h0 && enable_xfer_timer);
// ==================================================================
// Retry counter
// ==================================================================
always @(posedge clk)
begin
if (reset)
retry_cnt <= - 'h1;
// Reset the counter when the control state machine is idle or
// there is a valid data cycle.
else if (!dma_in_progress || dma_data_vld)
retry_cnt <= dma_retries;
else if (retry && retry_cnt != 'h0)
retry_cnt <= retry_cnt - 'h1;
end
assign dma_retry_expire = dma_in_progress && retry_cnt == 'h0;
// ==================================================================
// PCI transfer counter
// ==================================================================
always @(posedge clk)
begin
if (reset || cnet_reprog)
pci_cnt <= 'h0;
else if (ld_xfer_cnt)
pci_cnt <= xfer_cnt_start;
else if (rd_undo)
pci_cnt <= xfer_cnt;
else if ((dma_data_vld && !xfer_is_rd) || (dma_src_en && xfer_is_rd))
pci_cnt <= pci_cnt - 'h1;
end
// Is this the first or last word being transfered?
assign first_word_pci = pci_cnt == xfer_cnt_start;
assign last_word_pci = pci_cnt == 'h1;
// ==================================================================
// Acknowledged transfer counter
// ==================================================================
always @(posedge clk)
begin
if (reset || cnet_reprog)
xfer_cnt <= 'h0;
else if (ld_xfer_cnt)
xfer_cnt <= xfer_cnt_start;
else if (dma_data_vld)
xfer_cnt <= xfer_cnt - 'h1;
end
assign done = xfer_cnt == 'h0;
// ==================================================================
// Transaction termination signals
// ==================================================================
assign cnt3 = xfer_cnt == 'h3 ||
(dma_nearly_empty && !dma_all_in_buf && xfer_is_rd);
assign cnt2 = xfer_cnt == 'h2;
assign cnt1 = xfer_cnt == 'h1;
assign fin3 = cnt3 & dma_data_vld;
assign fin2 = cnt2 & dma_data_d1;
assign fin1 = cnt1 & dma_request;
// Warning: Check if the dma_lat_timeout setting is correct here
assign assert_complete = fin1 | fin2 | fin3 | dma_lat_timeout;
assign dma_complete = assert_complete | hold_complete | full_buffer_abort;
// Note: The DMA_Read below is meaning reading from the host...
assign full_buffer_abort = !dma_wr_rdy && !xfer_is_rd && xfer_state == `DMA_Read;
always @(posedge clk)
begin
if (reset || ld_xfer_cnt)
hold_complete <= 1'b0;
else if (dma_data_fell)
hold_complete <= 1'b0;
else if (assert_complete)
hold_complete <= 1'b1;
end
// ==================================================================
// Miscelaneous signal generation
// ==================================================================
assign rd_undo = xfer_state == `DMA_Oops;
assign abort_xfer = dma_timeout || dma_retry_expire ||
(fatal && (xfer_state == `DMA_Write || xfer_state == `DMA_Read));
// Generate the dma_data_fell signal indicating when the core leaves the
// m_data state
always @(posedge clk)
begin
if (reset)
dma_data_d1 <= 1'b0;
else
dma_data_d1 <= dma_data_st;
end
assign dma_data_fell = !dma_data_st & dma_data_d1;
// Fatal and Retry signals
always @(posedge clk)
begin
if (reset) begin
fatal <= 1'b0;
retry <= 1'b0;
end
else if (dma_addr_st) begin
fatal <= 1'b0;
retry <= 1'b0;
end
else if (dma_data_st) begin
fatal <= pci_fatal;
retry <= pci_retry;
end
end
// Signals to PCI core
assign dma_request = xfer_state == `DMA_Req;
assign dma_vld = dma_addr_st | dma_src_en;
assign dma_data = dma_addr_st ? {dma_addr, 2'b00} : rd_dout;
assign command = {3'b011, xfer_is_rd};
assign first_word_be_swapped = host_is_le ? {
first_word_be[0], first_word_be[1],
first_word_be[2], first_word_be[3]} :
first_word_be;
assign last_word_be_swapped = host_is_le ? {
last_word_be[0], last_word_be[1],
last_word_be[2], last_word_be[3]} :
last_word_be;
assign byte_enable = /*xfer_is_rd ? 4'b0000 : */
(last_word_pci ? last_word_be_swapped : 4'b0000) |
(first_word_pci ? first_word_be_swapped : 4'b0000);
assign dma_cbe = dma_addr_st ? command : byte_enable;
assign dma_wrdn = xfer_is_rd;
endmodule // dma_engine_pci_xfer
|
`define WIDTH_P 4
`define OVERFLOW_P (2**(`WIDTH_P)-1)
`include "bsg_defines.v"
/**************************** TEST RATIONALE *******************************
1. STATE SPACE
This test module tests the outputs of DUT for a complete count-cycle i.e.,
from 0 to OVERFLOW_P and 0 (restarts after overflow). Since the number of
unique counts becomes very large as WIDTH_P increases ( 2**(WIDTH_P)
possible counts), the test input, OVERFLOW_P, is defined as a macro which can
be varied in the Makefile. If the OVERFLOW_P is more than 2**WIDTH_P the
simulation simply finishes doing nothing.
2. PARAMETERIZATION
Since the DUT implements an algorithm that simply increments or decrements
the count an arbitrary set of tests that include that include the edge cases
would do the job. So a minimum set of tests might be WIDTH_P=1,2,3,4,8 and
OVERFLOW_P=1,2,3,4,8. Time taken to complete a test grows exponentially with
WIDTH_P, simulation with large WIDTH_P value takes long to finish.
***************************************************************************/
module testbench
#(parameter width_p=`WIDTH_P,
parameter cycle_time_p=20,
parameter overflow_p=`OVERFLOW_P
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(1)
, .reset_cycles_hi_p(5)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display( "\n\n\n"
, "============================================================\n"
, "testing with ...\n"
, "WIDTH_P : %d\n", width_p
, "OVERFLOW_P: %d\n", overflow_p
);
assert(overflow_p < 2**width_p)
else
begin
$display("skipping the test due to incompatible parameters\n");
$display("=========================================================\n");
$finish;
end
end
logic [width_p-1:0] test_input, test_output, prev_count, count;
logic [`BSG_SAFE_CLOG2(overflow_p+1)-1:0] circular_ptr;
logic finish_r;
assign test_input = overflow_p;
bsg_circular_ptr #( .slots_p (overflow_p+1)
, .max_add_p (1)
, .ptr_width_lp()
) c_ptr
( .clk (clk)
, .reset_i(reset)
, .add_i (1'b1)
, .o (circular_ptr)
);
assign count = width_p ' (circular_ptr);
always_ff @(posedge clk)
begin
prev_count <= count;
//$display("count: %d, test_output: %d\n", count, test_output); ///////////////////////////
if(!reset)
assert (count == test_output)
else $error("error on count %x", count);
if(~(|count) & (prev_count == overflow_p))
finish_r <= 1;
if(finish_r)
begin
$display("==============================================================\n");
$finish;
end
end
bsg_counter_dynamic_limit #( .width_p(width_p)
) DUT
( .clk_i (clk)
, .reset_i (reset)
, .limit_i(test_input)
, .counter_o (test_output)
);
/*bsg_nonsynth_ascii_writer #( .width_p (width_p)
, .values_p (3)
, .filename_p ("output.log")
, .fopen_param_p("a+")
, .format_p ("%b")
) ascii_writer
( .clk (clk)
, .reset_i(reset)
, .valid_i(1'b1)
, .data_i ({test_output,
count,
test_input}
)
);*/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SDFRTN_BEHAVIORAL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_BEHAVIORAL_V
|
module ISpm(input clk,
input [11:0] io_core_r_addr,
input io_core_r_enable,
output[31:0] io_core_r_data_out,
input [11:0] io_core_rw_addr,
input io_core_rw_enable,
output[31:0] io_core_rw_data_out,
input io_core_rw_write,
input [31:0] io_core_rw_data_in,
input [11:0] io_bus_addr,
input io_bus_write,
input [31:0] io_bus_data_in,
output io_bus_ready
);
genvar i;
generate
for(i = 0; i < 8; i = i+1)
begin: BRAMS
reg [3:0] ispm [4095:0];
reg [3:0] r_data_out, rw_data_out;
always @(posedge clk) begin
if(io_core_r_enable) begin
r_data_out <= ispm[io_core_r_addr];
end
end
assign io_core_r_data_out[4*i+3:4*i] = r_data_out;
always @(posedge clk) begin
if(io_core_rw_enable) begin
if(io_core_rw_write) begin
ispm[io_core_rw_addr] <= io_core_rw_data_in[4*i+3:4*i];
end
rw_data_out <= ispm[io_core_rw_addr];
end
end
//assign io_core_rw_data_out[4*i+3:4*i] = rw_data_out;
end
endgenerate
//assign io_core_rw_data_out = 32'b0;
assign io_bus_ready = 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221A_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O221A_BLACKBOX_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221A_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_SYMBOL_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_SYMBOL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlygate4sd2 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__NOR2_FUNCTIONAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_FUNCTIONAL_PP_V
|
module adio_codec (
output oAUD_DATA,
output oAUD_LRCK,
output reg oAUD_BCK,
input key1_on,
input [1:0] iSrc_Select,
input iCLK_18_4,
input iRST_N,
input [15:0] sound1
);
parameter REF_CLK = 18432000; // 18.432 MHz
parameter SAMPLE_RATE = 48000; // 48 KHz
parameter DATA_WIDTH = 16; // 16 Bits
parameter CHANNEL_NUM = 2; // Dual Channel
parameter SIN_SAMPLE_DATA = 48;
//////////// Input Source Number //////////////
parameter SIN_SANPLE = 0;
//////////////////////////////////////////////////
// Internal Registers and Wires
reg [3:0] BCK_DIV;
reg [8:0] LRCK_1X_DIV;
reg [7:0] LRCK_2X_DIV;
reg [6:0] LRCK_4X_DIV;
reg [3:0] SEL_Cont;
//////// DATA Counter ////////
reg [5:0] SIN_Cont;
////////////////////////////////////
reg LRCK_1X;
reg LRCK_2X;
reg LRCK_4X;
//////////// AUD_BCK Generator //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
BCK_DIV <= 0;
oAUD_BCK <= 0;
end
else
begin
if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1 )
begin
BCK_DIV <= 0;
oAUD_BCK <= ~oAUD_BCK;
end
else
BCK_DIV <= BCK_DIV+1;
end
end
//////////////////////////////////////////////////
//////////// AUD_LRCK Generator //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
LRCK_1X_DIV <= 0;
LRCK_2X_DIV <= 0;
LRCK_4X_DIV <= 0;
LRCK_1X <= 0;
LRCK_2X <= 0;
LRCK_4X <= 0;
end
else
begin
// LRCK 1X
if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 )
begin
LRCK_1X_DIV <= 0;
LRCK_1X <= ~LRCK_1X;
end
else
LRCK_1X_DIV <= LRCK_1X_DIV+1;
// LRCK 2X
if(LRCK_2X_DIV >= REF_CLK/(SAMPLE_RATE*4)-1 )
begin
LRCK_2X_DIV <= 0;
LRCK_2X <= ~LRCK_2X;
end
else
LRCK_2X_DIV <= LRCK_2X_DIV+1;
// LRCK 4X
if(LRCK_4X_DIV >= REF_CLK/(SAMPLE_RATE*8)-1 )
begin
LRCK_4X_DIV <= 0;
LRCK_4X <= ~LRCK_4X;
end
else
LRCK_4X_DIV <= LRCK_4X_DIV+1;
end
end
assign oAUD_LRCK = LRCK_1X;
//////////////////////////////////////////////////
////////// Sin LUT ADDR Generator //////////////
always@(negedge LRCK_1X or negedge iRST_N)
begin
if(!iRST_N)
SIN_Cont <= 0;
else
begin
if(SIN_Cont < SIN_SAMPLE_DATA-1 )
SIN_Cont <= SIN_Cont+1;
else
SIN_Cont <= 0;
end
end
///////////////////Wave-Source generate////////////////
////////////Timbre selection & SoundOut///////////////
wire [15:0]music1_ramp;
wire [15:0]music1=music1_ramp;
wire [15:0]sound_o;
assign sound_o=music1;
always@(negedge oAUD_BCK or negedge iRST_N)begin
if(!iRST_N)
SEL_Cont <= 0;
else
SEL_Cont <= SEL_Cont+1;
end
assign oAUD_DATA = ((key1_on) && (iSrc_Select==SIN_SANPLE)) ? sound_o[~SEL_Cont] :0;
//////////Ramp address generater//////////////
reg [15:0]ramp1;
wire [15:0]ramp_max=60000;
//////CH1 Ramp//////
always@(negedge key1_on or negedge LRCK_1X)begin
if (!key1_on)
ramp1=0;
else if (ramp1>ramp_max) ramp1=0;
else ramp1=ramp1+sound1;
end
////////////Ramp address assign//////////////
wire [5:0] ramp1_ramp=ramp1[15:10];
////////String-wave Timbre///////
wave_gen_string r1(
.ramp(ramp1_ramp),
.music_o(music1_ramp)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_BLACKBOX_V
`define SKY130_FD_SC_LP__O211AI_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o211ai (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_2_V
`define SKY130_FD_SC_HS__DLRTP_2_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrtp_2 (
RESET_B,
D ,
GATE ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE ;
output Q ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlrtp base (
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrtp_2 (
RESET_B,
D ,
GATE ,
Q
);
input RESET_B;
input D ;
input GATE ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlrtp base (
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.Q(Q)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: MossbauerLab
// Engineer: EvilLord666 (Ushakov MV)
//
// Create Date: 01:41:52 01/09/2019
// Design Name:
// Module Name: messbauer_saw_tooth_generator
// Project Name: messbauer_test_environment
// Target Devices:
// Tool versions: ISE 14.7
// Description: ALINX AX309 Board Messbauer Generator
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`ifndef MAX_CHANNEL_NUMBER
`define MAX_CHANNEL_NUMBER 4096
`endif
module messbauer_saw_tooth_generator #
(
parameter GCLK_PERIOD = 20,
parameter DIRECT_SLOPE_DURATION = 512, // number of messbauer channels 4 code generation during direct motion
parameter CHANNEL_DURATION = (16 * (`MAX_CHANNEL_NUMBER / DIRECT_SLOPE_DURATION)) * 1000 / (2 * GCLK_PERIOD),
parameter REVERSE_SLOPE_DURATION = (15464000 / (2 * GCLK_PERIOD)) / CHANNEL_DURATION , // number of messbauer pseudo channels during reverse motion (channel does not actually generates) 15,464 ms
parameter DATA_WIDTH = 12
)
(
input wire clk,
input wire areset_n,
output reg [DATA_WIDTH-1:0] out_value
);
localparam RATIO_SLOPE_DURATOIN = DIRECT_SLOPE_DURATION / REVERSE_SLOPE_DURATION;
reg dir;
reg [15:0] counter;
always @ (posedge clk)
begin
if (!areset_n)
begin
out_value <= 0;
counter <=0;
dir <= 0;
end
else
begin
counter <= counter + 1;
if(dir == 0)
begin
if (counter == CHANNEL_DURATION)
begin
out_value <= out_value + 1;
counter <= 0;
end
if(out_value == DIRECT_SLOPE_DURATION)
dir <= 1;
end
else
begin
if (counter == CHANNEL_DURATION)
begin
out_value <= out_value > RATIO_SLOPE_DURATOIN ? out_value - RATIO_SLOPE_DURATOIN : 0;
counter <= 0;
end
if(out_value == 0)
dir <= 0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBP_TB_V
`define SKY130_FD_SC_LS__DFBBP_TB_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfbbp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 RESET_B = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 RESET_B = 1'b0;
#340 SET_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SET_B = 1'b1;
#540 RESET_B = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SET_B = 1'bx;
#680 RESET_B = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__dfbbp dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX4_BLACKBOX_V
`define SKY130_FD_SC_HD__MUX4_BLACKBOX_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX4_BLACKBOX_V
|
//-----------------------------------------------------------------
// RISC-V Core
// V1.0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014-2019, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
module riscv_csr
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SUPPORT_MULDIV = 1
,parameter SUPPORT_SUPER = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input intr_i
,input opcode_valid_i
,input [ 31:0] opcode_opcode_i
,input [ 31:0] opcode_pc_i
,input opcode_invalid_i
,input [ 4:0] opcode_rd_idx_i
,input [ 4:0] opcode_ra_idx_i
,input [ 4:0] opcode_rb_idx_i
,input [ 31:0] opcode_ra_operand_i
,input [ 31:0] opcode_rb_operand_i
,input csr_writeback_write_i
,input [ 11:0] csr_writeback_waddr_i
,input [ 31:0] csr_writeback_wdata_i
,input [ 5:0] csr_writeback_exception_i
,input [ 31:0] csr_writeback_exception_pc_i
,input [ 31:0] csr_writeback_exception_addr_i
,input [ 31:0] cpu_id_i
,input [ 31:0] reset_vector_i
,input interrupt_inhibit_i
// Outputs
,output [ 31:0] csr_result_e1_value_o
,output csr_result_e1_write_o
,output [ 31:0] csr_result_e1_wdata_o
,output [ 5:0] csr_result_e1_exception_o
,output branch_csr_request_o
,output [ 31:0] branch_csr_pc_o
,output [ 1:0] branch_csr_priv_o
,output take_interrupt_o
,output ifence_o
,output [ 1:0] mmu_priv_d_o
,output mmu_sum_o
,output mmu_mxr_o
,output mmu_flush_o
,output [ 31:0] mmu_satp_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire ecall_w = opcode_valid_i && ((opcode_opcode_i & `INST_ECALL_MASK) == `INST_ECALL);
wire ebreak_w = opcode_valid_i && ((opcode_opcode_i & `INST_EBREAK_MASK) == `INST_EBREAK);
wire eret_w = opcode_valid_i && ((opcode_opcode_i & `INST_ERET_MASK) == `INST_ERET);
wire [1:0] eret_priv_w = opcode_opcode_i[29:28];
wire csrrw_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRW_MASK) == `INST_CSRRW);
wire csrrs_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRS_MASK) == `INST_CSRRS);
wire csrrc_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRC_MASK) == `INST_CSRRC);
wire csrrwi_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRWI_MASK) == `INST_CSRRWI);
wire csrrsi_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRSI_MASK) == `INST_CSRRSI);
wire csrrci_w = opcode_valid_i && ((opcode_opcode_i & `INST_CSRRCI_MASK) == `INST_CSRRCI);
wire wfi_w = opcode_valid_i && ((opcode_opcode_i & `INST_WFI_MASK) == `INST_WFI);
wire fence_w = opcode_valid_i && ((opcode_opcode_i & `INST_FENCE_MASK) == `INST_FENCE);
wire sfence_w = opcode_valid_i && ((opcode_opcode_i & `INST_SFENCE_MASK) == `INST_SFENCE);
wire ifence_w = opcode_valid_i && ((opcode_opcode_i & `INST_IFENCE_MASK) == `INST_IFENCE);
//-----------------------------------------------------------------
// CSR handling
//-----------------------------------------------------------------
wire [1:0] current_priv_w;
reg [1:0] csr_priv_r;
reg csr_readonly_r;
reg csr_write_r;
reg set_r;
reg clr_r;
reg csr_fault_r;
reg [31:0] data_r;
always @ *
begin
set_r = csrrw_w | csrrs_w | csrrwi_w | csrrsi_w;
clr_r = csrrw_w | csrrc_w | csrrwi_w | csrrci_w;
csr_priv_r = opcode_opcode_i[29:28];
csr_readonly_r = (opcode_opcode_i[31:30] == 2'd3);
csr_write_r = (opcode_ra_idx_i != 5'b0) | csrrw_w | csrrwi_w;
data_r = (csrrwi_w |
csrrsi_w |
csrrci_w) ?
{27'b0, opcode_ra_idx_i} : opcode_ra_operand_i;
// Detect access fault on CSR access
csr_fault_r = SUPPORT_SUPER ? (opcode_valid_i && (set_r | clr_r) && ((csr_write_r && csr_readonly_r) || (current_priv_w < csr_priv_r))) : 1'b0;
end
wire satp_update_w = (opcode_valid_i && (set_r || clr_r) && csr_write_r && (opcode_opcode_i[31:20] == `CSR_SATP));
//-----------------------------------------------------------------
// CSR register file
//-----------------------------------------------------------------
wire timer_irq_w = 1'b0;
wire [31:0] misa_w = SUPPORT_MULDIV ? (`MISA_RV32 | `MISA_RVI | `MISA_RVM): (`MISA_RV32 | `MISA_RVI);
wire [31:0] csr_rdata_w;
wire csr_branch_w;
wire [31:0] csr_target_w;
wire [31:0] interrupt_w;
wire [31:0] status_reg_w;
wire [31:0] satp_reg_w;
riscv_csr_regfile
#( .SUPPORT_MTIMECMP(1)
,.SUPPORT_SUPER(SUPPORT_SUPER) )
u_csrfile
(
.clk_i(clk_i)
,.rst_i(rst_i)
,.ext_intr_i(intr_i)
,.timer_intr_i(timer_irq_w)
,.cpu_id_i(cpu_id_i)
,.misa_i(misa_w)
// Issue
,.csr_ren_i(opcode_valid_i)
,.csr_raddr_i(opcode_opcode_i[31:20])
,.csr_rdata_o(csr_rdata_w)
// Exception (WB)
,.exception_i(csr_writeback_exception_i)
,.exception_pc_i(csr_writeback_exception_pc_i)
,.exception_addr_i(csr_writeback_exception_addr_i)
// CSR register writes (WB)
,.csr_waddr_i(csr_writeback_write_i ? csr_writeback_waddr_i : 12'b0)
,.csr_wdata_i(csr_writeback_wdata_i)
// CSR branches
,.csr_branch_o(csr_branch_w)
,.csr_target_o(csr_target_w)
// Various CSR registers
,.priv_o(current_priv_w)
,.status_o(status_reg_w)
,.satp_o(satp_reg_w)
// Masked interrupt output
,.interrupt_o(interrupt_w)
);
//-----------------------------------------------------------------
// CSR Read Result (E1) / Early exceptions
//-----------------------------------------------------------------
reg rd_valid_e1_q;
reg [ 31:0] rd_result_e1_q;
reg [ 31:0] csr_wdata_e1_q;
reg [`EXCEPTION_W-1:0] exception_e1_q;
// Inappropriate xRET for the current exec priv level
wire eret_fault_w = eret_w && (current_priv_w < eret_priv_w);
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
rd_valid_e1_q <= 1'b0;
rd_result_e1_q <= 32'b0;
csr_wdata_e1_q <= 32'b0;
exception_e1_q <= `EXCEPTION_W'b0;
end
else if (opcode_valid_i)
begin
rd_valid_e1_q <= (set_r || clr_r) && ~csr_fault_r;
// Invalid instruction / CSR access fault?
// Record opcode for writing to csr_xtval later.
if (opcode_invalid_i || csr_fault_r || eret_fault_w)
rd_result_e1_q <= opcode_opcode_i;
else
rd_result_e1_q <= csr_rdata_w;
// E1 CSR exceptions
if ((opcode_opcode_i & `INST_ECALL_MASK) == `INST_ECALL)
exception_e1_q <= `EXCEPTION_ECALL + {4'b0, current_priv_w};
// xRET for priv level above this one - fault
else if (eret_fault_w)
exception_e1_q <= `EXCEPTION_ILLEGAL_INSTRUCTION;
else if ((opcode_opcode_i & `INST_ERET_MASK) == `INST_ERET)
exception_e1_q <= `EXCEPTION_ERET_U + {4'b0, eret_priv_w};
else if ((opcode_opcode_i & `INST_EBREAK_MASK) == `INST_EBREAK)
exception_e1_q <= `EXCEPTION_BREAKPOINT;
else if (opcode_invalid_i || csr_fault_r)
exception_e1_q <= `EXCEPTION_ILLEGAL_INSTRUCTION;
// Fence / MMU settings cause a pipeline flush
else if (satp_update_w || ifence_w || sfence_w)
exception_e1_q <= `EXCEPTION_FENCE;
else
exception_e1_q <= `EXCEPTION_W'b0;
// Value to be written to CSR registers
if (set_r && clr_r)
csr_wdata_e1_q <= data_r;
else if (set_r)
csr_wdata_e1_q <= csr_rdata_w | data_r;
else if (clr_r)
csr_wdata_e1_q <= csr_rdata_w & ~data_r;
end
else
begin
rd_valid_e1_q <= 1'b0;
rd_result_e1_q <= 32'b0;
csr_wdata_e1_q <= 32'b0;
exception_e1_q <= `EXCEPTION_W'b0;
end
assign csr_result_e1_value_o = rd_result_e1_q;
assign csr_result_e1_write_o = rd_valid_e1_q;
assign csr_result_e1_wdata_o = csr_wdata_e1_q;
assign csr_result_e1_exception_o = exception_e1_q;
//-----------------------------------------------------------------
// Interrupt launch enable
//-----------------------------------------------------------------
reg take_interrupt_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
take_interrupt_q <= 1'b0;
else
take_interrupt_q <= (|interrupt_w) & ~interrupt_inhibit_i;
assign take_interrupt_o = take_interrupt_q;
//-----------------------------------------------------------------
// TLB flush
//-----------------------------------------------------------------
reg tlb_flush_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
tlb_flush_q <= 1'b0;
else
tlb_flush_q <= satp_update_w || sfence_w;
//-----------------------------------------------------------------
// ifence
//-----------------------------------------------------------------
reg ifence_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
ifence_q <= 1'b0;
else
ifence_q <= ifence_w;
assign ifence_o = ifence_q;
//-----------------------------------------------------------------
// Execute - Branch operations
//-----------------------------------------------------------------
reg branch_q;
reg [31:0] branch_target_q;
reg reset_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
branch_target_q <= 32'b0;
branch_q <= 1'b0;
reset_q <= 1'b1;
end
else if (reset_q)
begin
branch_target_q <= reset_vector_i;
branch_q <= 1'b1;
reset_q <= 1'b0;
end
else
begin
branch_q <= csr_branch_w;
branch_target_q <= csr_target_w;
end
assign branch_csr_request_o = branch_q;
assign branch_csr_pc_o = branch_target_q;
assign branch_csr_priv_o = satp_reg_w[`SATP_MODE_R] ? current_priv_w : `PRIV_MACHINE;
//-----------------------------------------------------------------
// MMU
//-----------------------------------------------------------------
assign mmu_priv_d_o = status_reg_w[`SR_MPRV_R] ? status_reg_w[`SR_MPP_R] : current_priv_w;
assign mmu_satp_o = satp_reg_w;
assign mmu_flush_o = tlb_flush_q;
assign mmu_sum_o = status_reg_w[`SR_SUM_R];
assign mmu_mxr_o = status_reg_w[`SR_MXR_R];
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: tb_openMSP430_fpga.v
//
// *Module Description:
// openMSP430 FPGA testbench
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 111 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
//----------------------------------------------------------------------------
`include "timescale.v"
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module tb_openMSP430_fpga;
//
// Wire & Register definition
//------------------------------
// User Clocks
reg FPGA_CLK1_50;
reg FPGA_CLK2_50;
reg FPGA_CLK3_50;
// User Interface (FPGA)
reg [1:0] KEY;
reg [3:0] SW;
wire [7:0] LED;
// GPIO
wire [35:0] GPIO_0;
wire [35:0] GPIO_1;
// Arduino Digital Interface
wire [15:0] ARDUINO_IO;
wire ARDUINO_RESET_N;
// ADC
wire ADC_CONVST;
wire ADC_SCK;
wire ADC_SDI;
reg ADC_SDO;
// Core debug signals
wire [8*32-1:0] omsp_i_state;
wire [8*32-1:0] omsp_e_state;
wire [31:0] omsp_inst_cycle;
wire [8*32-1:0] omsp_inst_full;
wire [31:0] omsp_inst_number;
wire [15:0] omsp_inst_pc;
wire [8*32-1:0] omsp_inst_short;
// LT24 data bus
reg lt24_data_drive_en;
reg [15:0] lt24_data_reg;
wire [15:0] lt24_data = lt24_data_drive_en ? lt24_data_reg : 16'hzzzz;
// Testbench variables
integer i;
integer error;
reg stimulus_done;
//
// Include files
//------------------------------
// CPU & Memory registers
`include "registers_omsp.v"
// Verilog stimulus
`include "stimulus.v"
//
// Initialize Program Memory
//------------------------------
initial
begin
// Read memory file
#10 $readmemh("./pmem.mem", pmem);
end
//
// Generate Clock & Reset
//------------------------------
initial
begin
FPGA_CLK1_50 = 1'b0;
forever #10.0 FPGA_CLK1_50 <= ~FPGA_CLK1_50; // 50 MHz
end
initial
begin
FPGA_CLK2_50 = 1'b0;
forever #10.0 FPGA_CLK2_50 <= ~FPGA_CLK2_50; // 50 MHz
end
initial
begin
FPGA_CLK3_50 = 1'b0;
forever #10.0 FPGA_CLK3_50 <= ~FPGA_CLK3_50; // 50 MHz
end
initial
begin
KEY[0] = 1'b1;
#100 KEY[0] = 1'b0;
#600 KEY[0] = 1'b1;
end
//
// Global initialization
//------------------------------
initial
begin
error = 0; // Testbench
stimulus_done = 1;
KEY[1] = 1'b1; // Keys/Buttons
SW[0] = 1'b0; // Switches
SW[1] = 1'b0;
SW[2] = 1'b0;
SW[3] = 1'b0;
ADC_SDO = 1'b1; // ADC
lt24_data_drive_en = 1'b0; // LT24 Data bus
lt24_data_reg = 16'h0000;
end
//
// openMSP430 FPGA Instance
//----------------------------------
openMSP430_fpga dut (
// USER CLOCKS
.FPGA_CLK1_50 ( FPGA_CLK1_50 ),
.FPGA_CLK2_50 ( FPGA_CLK2_50 ),
.FPGA_CLK3_50 ( FPGA_CLK3_50 ),
// USER INTERFACE (FPGA)
.KEY ( KEY ),
.LED ( LED ),
.SW ( SW ),
// GPIO
.GPIO_0 ( GPIO_0 ),
.GPIO_1 ( GPIO_1 ),
// ARDUINO DIGITAL INTERFACE
.ARDUINO_IO ( ARDUINO_IO ),
.ARDUINO_RESET_N ( ARDUINO_RESET_N ),
// ADC
.ADC_CONVST ( ADC_CONVST ),
.ADC_SCK ( ADC_SCK ),
.ADC_SDI ( ADC_SDI ),
.ADC_SDO ( ADC_SDO )
);
// Pull-ups for the I2C debug interface
pullup dbg_scl_inst (ARDUINO_IO[15]);
pullup dbg_sda_inst (ARDUINO_IO[14]);
// Assign LT24 data bus
assign GPIO_0[8] = lt24_data[0] ;
assign GPIO_0[7] = lt24_data[1] ;
assign GPIO_0[6] = lt24_data[2] ;
assign GPIO_0[5] = lt24_data[3] ;
assign GPIO_0[13] = lt24_data[4] ;
assign GPIO_0[14] = lt24_data[5] ;
assign GPIO_0[15] = lt24_data[6] ;
assign GPIO_0[16] = lt24_data[7] ;
assign GPIO_0[17] = lt24_data[8] ;
assign GPIO_0[18] = lt24_data[9] ;
assign GPIO_0[19] = lt24_data[10];
assign GPIO_0[20] = lt24_data[11];
assign GPIO_0[21] = lt24_data[12];
assign GPIO_0[22] = lt24_data[13];
assign GPIO_0[23] = lt24_data[14];
assign GPIO_0[24] = lt24_data[15];
// Debug utility signals
//----------------------------------------
msp_debug msp_debug_omsp (
// OUTPUTs
.e_state (omsp_e_state), // Execution state
.i_state (omsp_i_state), // Instruction fetch state
.inst_cycle (omsp_inst_cycle), // Cycle number within current instruction
.inst_full (omsp_inst_full), // Currently executed instruction (full version)
.inst_number (omsp_inst_number), // Instruction number since last system reset
.inst_pc (omsp_inst_pc), // Instruction Program counter
.inst_short (omsp_inst_short) // Currently executed instruction (short version)
);
//
// Generate Waveform
//----------------------------------------
initial
begin
`ifdef VPD_FILE
$vcdplusfile("tb_openMSP430_fpga.vpd");
$vcdpluson();
`else
`ifdef TRN_FILE
$recordfile ("tb_openMSP430_fpga.trn");
$recordvars;
`else
$dumpfile("tb_openMSP430_fpga.vcd");
$dumpvars(0, tb_openMSP430_fpga);
`endif
`endif
end
//
// End of simulation
//----------------------------------------
initial // Timeout
begin
`ifdef NO_TIMEOUT
`else
`ifdef VERY_LONG_TIMEOUT
#500000000;
`else
`ifdef LONG_TIMEOUT
#5000000;
`else
#500000;
`endif
`endif
$display(" ===============================================");
$display("| SIMULATION FAILED |");
$display("| (simulation Timeout) |");
$display(" ===============================================");
$finish;
`endif
end
initial // Normal end of test
begin
@(omsp_inst_pc===16'hffff)
$display(" ===============================================");
if (error!=0)
begin
$display("| SIMULATION FAILED |");
$display("| (some verilog stimulus checks failed) |");
end
else if (~stimulus_done)
begin
$display("| SIMULATION FAILED |");
$display("| (the verilog stimulus didn't complete) |");
end
else
begin
$display("| SIMULATION PASSED |");
end
$display(" ===============================================");
$finish;
end
//
// Tasks Definition
//------------------------------
task tb_error;
input [65*8:0] error_string;
begin
$display("ERROR: %s %t", error_string, $time);
error = error+1;
end
endtask
endmodule
|
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Module: csrbrg.v
// Description: Configuration and Staus Register(CSR)Bus
// --------------------------------------------------------------------
// --------------------------------------------------------------------
module csrbrg(
input sys_clk,
input sys_rst,
input [ 3:1] wb_adr_i, // WB Slave
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
output reg [ 2:0] csr_a, // CSR Master
output reg csr_we,
output reg [15:0] csr_do,
input [15:0] csr_di
);
// Datapath: WB <- CSR
always @(posedge sys_clk) begin
wb_dat_o <= csr_di;
end
// Datapath: CSR -> WB
reg next_csr_we;
always @(posedge sys_clk) begin
csr_a <= wb_adr_i[3:1];
csr_we <= next_csr_we;
csr_do <= wb_dat_i;
end
// Controller
reg [1:0] state;
reg [1:0] next_state;
parameter IDLE = 2'd0;
parameter DELAYACK1 = 2'd1;
parameter DELAYACK2 = 2'd2;
parameter ACK = 2'd3;
always @(posedge sys_clk) begin
if(sys_rst) state <= IDLE;
else state <= next_state;
end
always @(*) begin
next_state = state;
wb_ack_o = 1'b0;
next_csr_we = 1'b0;
case(state)
IDLE: begin
if(wb_cyc_i & wb_stb_i) begin // We have a request
next_csr_we = wb_we_i;
if(wb_we_i) next_state = ACK;
else next_state = DELAYACK1;
end
end
DELAYACK1: next_state = DELAYACK2;
DELAYACK2: next_state = ACK;
ACK: begin
wb_ack_o = 1'b1;
next_state = IDLE;
end
endcase
end
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// This module to implement the AGU (address generation unit for load/store
// and AMO instructions), which is mostly share the datapath with ALU module
// to save gatecount to mininum
//
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_alu_lsuagu(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Issue Handshake Interface to AGU
//
input agu_i_valid, // Handshake valid
output agu_i_ready, // Handshake ready
input [`E203_XLEN-1:0] agu_i_rs1,
input [`E203_XLEN-1:0] agu_i_rs2,
input [`E203_XLEN-1:0] agu_i_imm,
input [`E203_DECINFO_AGU_WIDTH-1:0] agu_i_info,
input [`E203_ITAG_WIDTH-1:0] agu_i_itag,
output agu_i_longpipe,
input flush_req,
input flush_pulse,
output amo_wait,
input oitf_empty,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The AGU Write-Back/Commit Interface
output agu_o_valid, // Handshake valid
input agu_o_ready, // Handshake ready
output [`E203_XLEN-1:0] agu_o_wbck_wdat,
output agu_o_wbck_err,
// The Commit Interface for all ldst and amo instructions
output agu_o_cmt_misalgn, // The misalign exception generated
output agu_o_cmt_ld,
output agu_o_cmt_stamo,
output agu_o_cmt_buserr, // The bus-error exception generated
output [`E203_ADDR_SIZE-1:0] agu_o_cmt_badaddr,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to LSU-ctrl
// * Bus cmd channel
output agu_icb_cmd_valid, // Handshake valid
input agu_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr, // Bus transaction start addr
output agu_icb_cmd_read, // Read or write
output [`E203_XLEN-1:0] agu_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] agu_icb_cmd_wmask,
output agu_icb_cmd_back2agu,
output agu_icb_cmd_lock,
output agu_icb_cmd_excl,
output [1:0] agu_icb_cmd_size,
output [`E203_ITAG_WIDTH-1:0]agu_icb_cmd_itag,
output agu_icb_cmd_usign,
// * Bus RSP channel
input agu_icb_rsp_valid, // Response valid
output agu_icb_rsp_ready, // Response ready
input agu_icb_rsp_err , // Response error
input agu_icb_rsp_excl_ok,
// Note: the RSP rdata is inline with AXI definition
input [`E203_XLEN-1:0] agu_icb_rsp_rdata,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// To share the ALU datapath, generate interface to ALU
// for single-issue machine, seems the AGU must be shared with ALU, otherwise
// it wasted the area for no points
//
// The operands and info to ALU
output [`E203_XLEN-1:0] agu_req_alu_op1,
output [`E203_XLEN-1:0] agu_req_alu_op2,
output agu_req_alu_swap,
output agu_req_alu_add ,
output agu_req_alu_and ,
output agu_req_alu_or ,
output agu_req_alu_xor ,
output agu_req_alu_max ,
output agu_req_alu_min ,
output agu_req_alu_maxu,
output agu_req_alu_minu,
input [`E203_XLEN-1:0] agu_req_alu_res,
// The Shared-Buffer interface to ALU-Shared-Buffer
output agu_sbf_0_ena,
output [`E203_XLEN-1:0] agu_sbf_0_nxt,
input [`E203_XLEN-1:0] agu_sbf_0_r,
output agu_sbf_1_ena,
output [`E203_XLEN-1:0] agu_sbf_1_nxt,
input [`E203_XLEN-1:0] agu_sbf_1_r,
input clk,
input rst_n
);
//
// When there is a nonalu_flush which is going to flush the ALU, then we need to mask off it
wire icb_sta_is_idle;
wire flush_block = flush_req & icb_sta_is_idle;
wire agu_i_load = agu_i_info [`E203_DECINFO_AGU_LOAD ] & (~flush_block);
wire agu_i_store = agu_i_info [`E203_DECINFO_AGU_STORE ] & (~flush_block);
wire agu_i_amo = agu_i_info [`E203_DECINFO_AGU_AMO ] & (~flush_block);
wire [1:0] agu_i_size = agu_i_info [`E203_DECINFO_AGU_SIZE ];
wire agu_i_usign = agu_i_info [`E203_DECINFO_AGU_USIGN ];
wire agu_i_excl = agu_i_info [`E203_DECINFO_AGU_EXCL ];
wire agu_i_amoswap = agu_i_info [`E203_DECINFO_AGU_AMOSWAP];
wire agu_i_amoadd = agu_i_info [`E203_DECINFO_AGU_AMOADD ];
wire agu_i_amoand = agu_i_info [`E203_DECINFO_AGU_AMOAND ];
wire agu_i_amoor = agu_i_info [`E203_DECINFO_AGU_AMOOR ];
wire agu_i_amoxor = agu_i_info [`E203_DECINFO_AGU_AMOXOR ];
wire agu_i_amomax = agu_i_info [`E203_DECINFO_AGU_AMOMAX ];
wire agu_i_amomin = agu_i_info [`E203_DECINFO_AGU_AMOMIN ];
wire agu_i_amomaxu = agu_i_info [`E203_DECINFO_AGU_AMOMAXU];
wire agu_i_amominu = agu_i_info [`E203_DECINFO_AGU_AMOMINU];
wire agu_icb_cmd_hsked = agu_icb_cmd_valid & agu_icb_cmd_ready;
`ifdef E203_SUPPORT_AMO//{
wire agu_icb_rsp_hsked = agu_icb_rsp_valid & agu_icb_rsp_ready;
`endif//E203_SUPPORT_AMO}
// These strange ifdef/ifndef rather than the ifdef-else, because of
// our internal text processing scripts need this style
`ifndef E203_SUPPORT_AMO//{
`ifndef E203_SUPPORT_UNALGNLDST//{
wire agu_icb_rsp_hsked = 1'b0;
`endif//}
`endif//}
wire agu_i_size_b = (agu_i_size == 2'b00);
wire agu_i_size_hw = (agu_i_size == 2'b01);
wire agu_i_size_w = (agu_i_size == 2'b10);
wire agu_i_addr_unalgn =
(agu_i_size_hw & agu_icb_cmd_addr[0])
| (agu_i_size_w & (|agu_icb_cmd_addr[1:0]));
wire state_last_exit_ena;
`ifdef E203_SUPPORT_AMO//{
wire state_idle_exit_ena;
wire unalgn_flg_r;
// Set when the ICB state is starting and it is unalign
wire unalgn_flg_set = agu_i_addr_unalgn & state_idle_exit_ena;
// Clear when the ICB state is entering
wire unalgn_flg_clr = unalgn_flg_r & state_last_exit_ena;
wire unalgn_flg_ena = unalgn_flg_set | unalgn_flg_clr;
wire unalgn_flg_nxt = unalgn_flg_set | (~unalgn_flg_clr);
sirv_gnrl_dfflr #(1) unalgn_flg_dffl (unalgn_flg_ena, unalgn_flg_nxt, unalgn_flg_r, clk, rst_n);
`endif//E203_SUPPORT_AMO}
wire agu_addr_unalgn =
`ifndef E203_SUPPORT_UNALGNLDST//{
`ifdef E203_SUPPORT_AMO//{
icb_sta_is_idle ? agu_i_addr_unalgn : unalgn_flg_r;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
agu_i_addr_unalgn;
`endif//}
`endif//}
wire agu_i_unalgnld = (agu_addr_unalgn & agu_i_load)
;
wire agu_i_unalgnst = (agu_addr_unalgn & agu_i_store)
;
wire agu_i_unalgnldst = (agu_i_unalgnld | agu_i_unalgnst)
;
wire agu_i_algnld = (~agu_addr_unalgn) & agu_i_load
;
wire agu_i_algnst = (~agu_addr_unalgn) & agu_i_store
;
wire agu_i_algnldst = (agu_i_algnld | agu_i_algnst)
;
`ifdef E203_SUPPORT_AMO//{
wire agu_i_unalgnamo = (agu_addr_unalgn & agu_i_amo)
;
wire agu_i_algnamo = ((~agu_addr_unalgn) & agu_i_amo)
;
`endif//E203_SUPPORT_AMO}
wire agu_i_ofst0 = agu_i_amo | ((agu_i_load | agu_i_store) & agu_i_excl);
localparam ICB_STATE_WIDTH = 4;
wire icb_state_ena;
wire [ICB_STATE_WIDTH-1:0] icb_state_nxt;
wire [ICB_STATE_WIDTH-1:0] icb_state_r;
// State 0: The idle state, means there is no any oustanding ifetch request
localparam ICB_STATE_IDLE = 4'd0;
`ifdef E203_SUPPORT_AMO//{
// State : Issued first request and wait response
localparam ICB_STATE_1ST = 4'd1;
// State : Wait to issue second request
localparam ICB_STATE_WAIT2ND = 4'd2;
// State : Issued second request and wait response
localparam ICB_STATE_2ND = 4'd3;
// State : For AMO instructions, in this state, read-data was in leftover
// buffer for ALU calculation
localparam ICB_STATE_AMOALU = 4'd4;
// State : For AMO instructions, in this state, ALU have caculated the new
// result and put into leftover buffer again
localparam ICB_STATE_AMORDY = 4'd5;
// State : For AMO instructions, in this state, the response data have been returned
// and the write back result to commit/wback interface
localparam ICB_STATE_WBCK = 4'd6;
`endif//E203_SUPPORT_AMO}
`ifdef E203_SUPPORT_AMO//{
wire [ICB_STATE_WIDTH-1:0] state_idle_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_1st_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_wait2nd_nxt;
wire [ICB_STATE_WIDTH-1:0] state_2nd_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_amoalu_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_amordy_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_wbck_nxt ;
`endif//E203_SUPPORT_AMO}
`ifdef E203_SUPPORT_AMO//{
wire state_1st_exit_ena ;
wire state_wait2nd_exit_ena ;
wire state_2nd_exit_ena ;
wire state_amoalu_exit_ena ;
wire state_amordy_exit_ena ;
wire state_wbck_exit_ena ;
`endif//E203_SUPPORT_AMO}
// Define some common signals and reused later to save gatecounts
assign icb_sta_is_idle = (icb_state_r == ICB_STATE_IDLE );
`ifdef E203_SUPPORT_AMO//{
wire icb_sta_is_1st = (icb_state_r == ICB_STATE_1ST );
wire icb_sta_is_amoalu = (icb_state_r == ICB_STATE_AMOALU );
wire icb_sta_is_amordy = (icb_state_r == ICB_STATE_AMORDY );
wire icb_sta_is_wait2nd = (icb_state_r == ICB_STATE_WAIT2ND);
wire icb_sta_is_2nd = (icb_state_r == ICB_STATE_2ND );
wire icb_sta_is_wbck = (icb_state_r == ICB_STATE_WBCK );
`endif//E203_SUPPORT_AMO}
`ifdef E203_SUPPORT_AMO//{
// **** If the current state is idle,
// If a new load-store come and the ICB cmd channel is handshaked, next
// state is ICB_STATE_1ST
wire state_idle_to_exit = (( agu_i_algnamo
// Why do we add an oitf empty signal here? because
// it is better to start AMO state-machine when the
// long-pipes are completed, to avoid the long-pipes
// have error-return which need to flush the pipeline
// and which also need to wait the AMO state-machine
// to complete first, in corner cases it may end
// up with deadlock.
// Force to wait oitf empty before doing amo state-machine
// may hurt performance, but we dont care it. In e200 implementation
// the AMO was not target for performance.
& oitf_empty)
);
assign state_idle_exit_ena = icb_sta_is_idle & state_idle_to_exit
& agu_icb_cmd_hsked & (~flush_pulse);
assign state_idle_nxt = ICB_STATE_1ST;
// **** If the current state is 1st,
// If a response come, exit this state
assign state_1st_exit_ena = icb_sta_is_1st & (agu_icb_rsp_hsked | flush_pulse);
assign state_1st_nxt = flush_pulse ? ICB_STATE_IDLE :
(
// (agu_i_algnamo) ? // No need this condition, because it will be either
// amo or unalgn load-store in this state
ICB_STATE_AMOALU
);
// **** If the current state is AMOALU
// Since the ALU is must be holdoff now, it can always be
// served and then enter into next state
assign state_amoalu_exit_ena = icb_sta_is_amoalu & ( 1'b1 | flush_pulse);
assign state_amoalu_nxt = flush_pulse ? ICB_STATE_IDLE : ICB_STATE_AMORDY;
// **** If the current state is AMORDY
// It always enter into next state
assign state_amordy_exit_ena = icb_sta_is_amordy & ( 1'b1 | flush_pulse);
assign state_amordy_nxt = flush_pulse ? ICB_STATE_IDLE :
(
// AMO after caculated read-modify-result, need to issue 2nd uop as store
// back to memory, hence two ICB needed and we dont care the performance,
// so always let it jump to wait2nd state
ICB_STATE_WAIT2ND
);
// **** If the current state is wait-2nd,
assign state_wait2nd_exit_ena = icb_sta_is_wait2nd & (agu_icb_cmd_ready | flush_pulse);
// If the ICB CMD is ready, then next state is ICB_STATE_2ND
assign state_wait2nd_nxt = flush_pulse ? ICB_STATE_IDLE : ICB_STATE_2ND;
// **** If the current state is 2nd,
// If a response come, exit this state
assign state_2nd_exit_ena = icb_sta_is_2nd & (agu_icb_rsp_hsked | flush_pulse);
assign state_2nd_nxt = flush_pulse ? ICB_STATE_IDLE :
(
ICB_STATE_WBCK
);
// **** If the current state is wbck,
// If it can be write back, exit this state
assign state_wbck_exit_ena = icb_sta_is_wbck & (agu_o_ready | flush_pulse);
assign state_wbck_nxt = flush_pulse ? ICB_STATE_IDLE :
(
ICB_STATE_IDLE
);
`endif//E203_SUPPORT_AMO}
// The state will only toggle when each state is meeting the condition to exit:
assign icb_state_ena = 1'b0
`ifdef E203_SUPPORT_AMO//{
| state_idle_exit_ena | state_1st_exit_ena
| state_amoalu_exit_ena | state_amordy_exit_ena
| state_wait2nd_exit_ena | state_2nd_exit_ena
| state_wbck_exit_ena
`endif//E203_SUPPORT_AMO}
;
// The next-state is onehot mux to select different entries
assign icb_state_nxt =
({ICB_STATE_WIDTH{1'b0}})
`ifdef E203_SUPPORT_AMO//{
| ({ICB_STATE_WIDTH{state_idle_exit_ena }} & state_idle_nxt )
| ({ICB_STATE_WIDTH{state_1st_exit_ena }} & state_1st_nxt )
| ({ICB_STATE_WIDTH{state_amoalu_exit_ena }} & state_amoalu_nxt )
| ({ICB_STATE_WIDTH{state_amordy_exit_ena }} & state_amordy_nxt )
| ({ICB_STATE_WIDTH{state_wait2nd_exit_ena}} & state_wait2nd_nxt)
| ({ICB_STATE_WIDTH{state_2nd_exit_ena }} & state_2nd_nxt )
| ({ICB_STATE_WIDTH{state_wbck_exit_ena }} & state_wbck_nxt )
`endif//E203_SUPPORT_AMO}
;
sirv_gnrl_dfflr #(ICB_STATE_WIDTH) icb_state_dfflr (icb_state_ena, icb_state_nxt, icb_state_r, clk, rst_n);
`ifdef E203_SUPPORT_AMO//{
wire icb_sta_is_last = icb_sta_is_wbck;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
wire icb_sta_is_last = 1'b0;
`endif//}
`ifdef E203_SUPPORT_AMO//{
assign state_last_exit_ena = state_wbck_exit_ena;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
assign state_last_exit_ena = 1'b0;
`endif//}
`ifndef E203_SUPPORT_UNALGNLDST//{
`else//}{
`ifndef E203_SUPPORT_AMO
!!!! ERROR: This config is not supported, must be something wrong
`endif//}
`endif//
// Indicate there is no oustanding memory transactions
`ifdef E203_SUPPORT_AMO//{
// As long as the statemachine started, we must wait it to be empty
// We cannot really kill this instruction when IRQ comes, becuase
// the AMO uop alreay write data into the memory, and we must commit
// this instructions
assign amo_wait = ~icb_sta_is_idle;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
assign amo_wait = 1'b0;// If no AMO or UNaligned supported, then always 0
`endif//}
//
/////////////////////////////////////////////////////////////////////////////////
// Implement the leftover 0 buffer
wire leftover_ena;
wire [`E203_XLEN-1:0] leftover_nxt;
wire [`E203_XLEN-1:0] leftover_r;
wire leftover_err_nxt;
wire leftover_err_r;
wire [`E203_XLEN-1:0] leftover_1_r;
wire leftover_1_ena;
wire [`E203_XLEN-1:0] leftover_1_nxt;
//
`ifdef E203_SUPPORT_AMO//{
wire amo_1stuop = icb_sta_is_1st & agu_i_algnamo;
wire amo_2nduop = icb_sta_is_2nd & agu_i_algnamo;
`endif//E203_SUPPORT_AMO}
assign leftover_ena = agu_icb_rsp_hsked & (
1'b0
`ifdef E203_SUPPORT_AMO//{
| amo_1stuop
| amo_2nduop
`endif//E203_SUPPORT_AMO}
);
assign leftover_nxt =
{`E203_XLEN{1'b0}}
`ifdef E203_SUPPORT_AMO//{
| ({`E203_XLEN{amo_1stuop }} & agu_icb_rsp_rdata)// Load the data from bus
| ({`E203_XLEN{amo_2nduop }} & leftover_r)// Unchange the value of leftover_r
`endif//E203_SUPPORT_AMO}
;
assign leftover_err_nxt = 1'b0
`ifdef E203_SUPPORT_AMO//{
| ({{amo_1stuop }} & agu_icb_rsp_err)// 1st error from the bus
| ({{amo_2nduop }} & (agu_icb_rsp_err | leftover_err_r))// second error merged
`endif//E203_SUPPORT_AMO}
;
//
// The instantiation of leftover buffer is actually shared with the ALU SBF-0 Buffer
assign agu_sbf_0_ena = leftover_ena;
assign agu_sbf_0_nxt = leftover_nxt;
assign leftover_r = agu_sbf_0_r;
// The error bit is implemented here
sirv_gnrl_dfflr #(1) icb_leftover_err_dfflr (leftover_ena, leftover_err_nxt, leftover_err_r, clk, rst_n);
assign leftover_1_ena = 1'b0
`ifdef E203_SUPPORT_AMO//{
| icb_sta_is_amoalu
`endif//E203_SUPPORT_AMO}
;
assign leftover_1_nxt = agu_req_alu_res;
//
// The instantiation of last_icb_addr buffer is actually shared with the ALU SBF-1 Buffer
assign agu_sbf_1_ena = leftover_1_ena;
assign agu_sbf_1_nxt = leftover_1_nxt;
assign leftover_1_r = agu_sbf_1_r;
assign agu_req_alu_add = 1'b0
`ifdef E203_SUPPORT_AMO//{
| (icb_sta_is_amoalu & agu_i_amoadd)
// In order to let AMO 2nd uop have correct address
| (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck))
`endif//E203_SUPPORT_AMO}
// To cut down the timing loop from agu_i_valid // | (icb_sta_is_idle & agu_i_valid)
// we dont need this signal at all
| icb_sta_is_idle
;
assign agu_req_alu_op1 = icb_sta_is_idle ? agu_i_rs1
`ifdef E203_SUPPORT_AMO//{
: icb_sta_is_amoalu ? leftover_r
// In order to let AMO 2nd uop have correct address
: (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck)) ? agu_i_rs1
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_UNALGNLDST//{
: `E203_XLEN'd0
`endif//}
;
wire [`E203_XLEN-1:0] agu_addr_gen_op2 = agu_i_ofst0 ? `E203_XLEN'b0 : agu_i_imm;
assign agu_req_alu_op2 = icb_sta_is_idle ? agu_addr_gen_op2
`ifdef E203_SUPPORT_AMO//{
: icb_sta_is_amoalu ? agu_i_rs2
// In order to let AMO 2nd uop have correct address
: (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck)) ? agu_addr_gen_op2
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_UNALGNLDST//{
: `E203_XLEN'd0
`endif//}
;
`ifdef E203_SUPPORT_AMO//{
assign agu_req_alu_swap = (icb_sta_is_amoalu & agu_i_amoswap );
assign agu_req_alu_and = (icb_sta_is_amoalu & agu_i_amoand );
assign agu_req_alu_or = (icb_sta_is_amoalu & agu_i_amoor );
assign agu_req_alu_xor = (icb_sta_is_amoalu & agu_i_amoxor );
assign agu_req_alu_max = (icb_sta_is_amoalu & agu_i_amomax );
assign agu_req_alu_min = (icb_sta_is_amoalu & agu_i_amomin );
assign agu_req_alu_maxu = (icb_sta_is_amoalu & agu_i_amomaxu );
assign agu_req_alu_minu = (icb_sta_is_amoalu & agu_i_amominu );
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
assign agu_req_alu_swap = 1'b0;
assign agu_req_alu_and = 1'b0;
assign agu_req_alu_or = 1'b0;
assign agu_req_alu_xor = 1'b0;
assign agu_req_alu_max = 1'b0;
assign agu_req_alu_min = 1'b0;
assign agu_req_alu_maxu = 1'b0;
assign agu_req_alu_minu = 1'b0;
`endif//}
/////////////////////////////////////////////////////////////////////////////////
// Implement the AGU op handshake ready signal
//
// The AGU op handshakeke interface will be ready when
// * If it is unaligned instructions, then it will just
// directly pass out the write-back interface, hence it will only be
// ready when the write-back interface is ready
// * If it is not unaligned load/store instructions, then it will just
// directly pass out the instruction to LSU-ctrl interface, hence it need to check
// the AGU ICB interface is ready, but it also need to ask write-back interface
// for commit, so, also need to check if write-back interfac is ready
//
`ifndef E203_SUPPORT_UNALGNLDST//{
`else//}{
!!!! ERROR: This UNALIGNED load/store is not supported, must be something wrong
`endif//}
assign agu_i_ready =
( 1'b0
`ifdef E203_SUPPORT_AMO//{
| agu_i_algnamo
`endif//E203_SUPPORT_AMO}
) ? state_last_exit_ena :
(agu_icb_cmd_ready & agu_o_ready) ;
// The aligned load/store instruction will be dispatched to LSU as long pipeline
// instructions
assign agu_i_longpipe = agu_i_algnldst;
//
/////////////////////////////////////////////////////////////////////////////////
// Implement the Write-back interfaces (unaligned and AMO instructions)
// The AGU write-back will be valid when:
// * For the aligned load/store
// Directly passed to ICB interface, but also need to pass
// to write-back interface asking for commit
assign agu_o_valid =
`ifdef E203_SUPPORT_AMO//{
// For the unaligned load/store and aligned AMO, it will enter
// into the state machine and let the last state to send back
// to the commit stage
icb_sta_is_last
`endif//E203_SUPPORT_AMO}
// For the aligned load/store and unaligned AMO, it will be send
// to the commit stage right the same cycle of agu_i_valid
|(
agu_i_valid & ( agu_i_algnldst
`ifndef E203_SUPPORT_UNALGNLDST//{
// If not support the unaligned load/store by hardware, then
// the unaligned load/store will be treated as exception
// and it will also be send to the commit stage right the
// same cycle of agu_i_valid
| agu_i_unalgnldst
`endif//}
`ifdef E203_SUPPORT_AMO//{
| agu_i_unalgnamo
`endif//E203_SUPPORT_AMO}
)
//// // Since it is issuing to commit stage and
//// // LSU at same cycle, so we must qualify the icb_cmd_ready signal from LSU
//// // to make sure it is out to commit/LSU at same cycle
// To cut the critical timing path from longpipe signal
// we always assume the AGU will need icb_cmd_ready
& agu_icb_cmd_ready
);
assign agu_o_wbck_wdat = {`E203_XLEN{1'b0 }}
`ifdef E203_SUPPORT_AMO//{
| ({`E203_XLEN{agu_i_algnamo }} & leftover_r)
| ({`E203_XLEN{agu_i_unalgnamo}} & `E203_XLEN'b0)
`endif//E203_SUPPORT_AMO}
;
assign agu_o_cmt_buserr = (1'b0
`ifdef E203_SUPPORT_AMO//{
| (agu_i_algnamo & leftover_err_r)
| (agu_i_unalgnamo & 1'b0)
`endif//E203_SUPPORT_AMO}
)
;
assign agu_o_cmt_badaddr = agu_icb_cmd_addr;
assign agu_o_cmt_misalgn = (1'b0
`ifdef E203_SUPPORT_AMO//{
| agu_i_unalgnamo
`endif//E203_SUPPORT_AMO}
| (agu_i_unalgnldst) //& agu_i_excl) We dont support unaligned load/store regardless it is AMO or not
)
;
assign agu_o_cmt_ld = agu_i_load & (~agu_i_excl);
assign agu_o_cmt_stamo = agu_i_store | agu_i_amo | agu_i_excl;
// The exception or error result cannot write-back
assign agu_o_wbck_err = agu_o_cmt_buserr | agu_o_cmt_misalgn
;
assign agu_icb_rsp_ready = 1'b1;
assign agu_icb_cmd_valid =
((agu_i_algnldst & agu_i_valid)
// We must qualify the agu_o_ready signal from commit stage
// to make sure it is out to commit/LSU at same cycle
& (agu_o_ready)
)
`ifdef E203_SUPPORT_AMO//{
| (agu_i_algnamo & (
(icb_sta_is_idle & agu_i_valid
// We must qualify the agu_o_ready signal from commit stage
// to make sure it is out to commit/LSU at same cycle
& agu_o_ready)
| (icb_sta_is_wait2nd)))
| (agu_i_unalgnamo & 1'b0)
`endif//E203_SUPPORT_AMO}
;
assign agu_icb_cmd_addr = agu_req_alu_res[`E203_ADDR_SIZE-1:0];
assign agu_icb_cmd_read =
(agu_i_algnldst & agu_i_load)
`ifdef E203_SUPPORT_AMO//{
| (agu_i_algnamo & icb_sta_is_idle & 1'b1)
| (agu_i_algnamo & icb_sta_is_wait2nd & 1'b0)
`endif//E203_SUPPORT_AMO}
;
// The AGU ICB CMD Wdata sources:
// * For the aligned store instructions
// Directly passed to AGU ICB, wdata is op2 repetitive form,
// wmask is generated according to the LSB and size
wire [`E203_XLEN-1:0] algnst_wdata =
({`E203_XLEN{agu_i_size_b }} & {4{agu_i_rs2[ 7:0]}})
| ({`E203_XLEN{agu_i_size_hw}} & {2{agu_i_rs2[15:0]}})
| ({`E203_XLEN{agu_i_size_w }} & {1{agu_i_rs2[31:0]}});
wire [`E203_XLEN/8-1:0] algnst_wmask =
({`E203_XLEN/8{agu_i_size_b }} & (4'b0001 << agu_icb_cmd_addr[1:0]))
| ({`E203_XLEN/8{agu_i_size_hw}} & (4'b0011 << {agu_icb_cmd_addr[1],1'b0}))
| ({`E203_XLEN/8{agu_i_size_w }} & (4'b1111));
assign agu_icb_cmd_wdata =
`ifdef E203_SUPPORT_AMO//{
agu_i_amo ? leftover_1_r :
`endif//E203_SUPPORT_AMO}
algnst_wdata;
assign agu_icb_cmd_wmask =
`ifdef E203_SUPPORT_AMO//{
// If the 1st uop have bus-error, then not write the data for 2nd uop
agu_i_amo ? (leftover_err_r ? 4'h0 : 4'hF) :
`endif//E203_SUPPORT_AMO}
algnst_wmask;
assign agu_icb_cmd_back2agu = 1'b0
`ifdef E203_SUPPORT_AMO//{
| agu_i_algnamo
`endif//E203_SUPPORT_AMO}
;
//We dont support lock and exclusive in such 2 stage simple implementation
assign agu_icb_cmd_lock = 1'b0
`ifdef E203_SUPPORT_AMO//{
| (agu_i_algnamo & icb_sta_is_idle)
`endif//E203_SUPPORT_AMO}
;
assign agu_icb_cmd_excl = 1'b0
`ifdef E203_SUPPORT_AMO//{
| agu_i_excl
`endif//E203_SUPPORT_AMO}
;
assign agu_icb_cmd_itag = agu_i_itag;
assign agu_icb_cmd_usign = agu_i_usign;
assign agu_icb_cmd_size =
agu_i_size;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_axi_basic_tx_thrtl_ctl.v
// Version : 1.3
// //
// Description: //
// TX throttle controller. Anticipates back-pressure from PCIe block and //
// preemptively back-pressures user design (packet boundary throttling). //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// axi_basic_tx_thrtl_ctl //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_3_axi_basic_tx_thrtl_ctl #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter TCQ = 1 // Clock to Q time
) (
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
input [3:0] s_axis_tx_tuser, // TX user signals
input s_axis_tx_tlast, // TX data is last
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
// TRN TX
//-----------
input [5:0] trn_tbuf_av, // TX buffers available
input trn_tdst_rdy, // TX destination ready
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // TX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output reg cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output reg tready_thrtl, // TREADY to pipeline
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Thrtl user when TBUF hits this val
localparam TBUF_AV_MIN = (C_DATA_WIDTH == 128) ? 5 :
(C_DATA_WIDTH == 64) ? 1 : 0;
// Pause user when TBUF hits this val
localparam TBUF_AV_GAP = TBUF_AV_MIN + 1;
// GAP pause time - the latency from the time a packet is accepted on the TRN
// interface to the time trn_tbuf_av from the Block will decrement.
localparam TBUF_GAP_TIME = (C_DATA_WIDTH == 128) ? 4 : 1;
// Latency time from when tcfg_gnt is asserted to when PCIe block will throttle
localparam TCFG_LATENCY_TIME = 2'd2;
// Number of pipeline stages to delay trn_tcfg_gnt. For V6 128-bit only
localparam TCFG_GNT_PIPE_STAGES = 3;
// Throttle condition registers and constants
reg lnk_up_thrtl;
wire lnk_up_trig;
wire lnk_up_exit;
reg tbuf_av_min_thrtl;
wire tbuf_av_min_trig;
reg tbuf_av_gap_thrtl;
reg [2:0] tbuf_gap_cnt;
wire tbuf_av_gap_trig;
wire tbuf_av_gap_exit;
wire gap_trig_tlast;
wire gap_trig_decr;
reg [5:0] tbuf_av_d;
reg tcfg_req_thrtl;
reg [1:0] tcfg_req_cnt;
reg trn_tdst_rdy_d;
wire tcfg_req_trig;
wire tcfg_req_exit;
reg tcfg_gnt_log;
wire pre_throttle;
wire reg_throttle;
wire exit_crit;
reg reg_tcfg_gnt;
reg trn_tcfg_req_d;
reg tcfg_gnt_pending;
wire wire_to_turnoff;
reg reg_turnoff_ok;
reg tready_thrtl_mux;
localparam LINKSTATE_L0 = 3'b000;
localparam LINKSTATE_PPM_L1 = 3'b001;
localparam LINKSTATE_PPM_L1_TRANS = 3'b101;
localparam LINKSTATE_PPM_L23R_TRANS = 3'b110;
localparam PM_ENTER_L1 = 8'h20;
localparam POWERSTATE_D0 = 2'b00;
reg ppm_L1_thrtl;
wire ppm_L1_trig;
wire ppm_L1_exit;
reg [2:0] cfg_pcie_link_state_d;
reg trn_rdllp_src_rdy_d;
reg ppm_L23_thrtl;
wire ppm_L23_trig;
reg cfg_turnoff_ok_pending;
reg reg_tlast;
// Throttle control state machine states and registers
localparam IDLE = 0;
localparam THROTTLE = 1;
reg cur_state;
reg next_state;
reg reg_axi_in_pkt;
wire axi_in_pkt;
wire axi_pkt_ending;
wire axi_throttled;
wire axi_thrtl_ok;
wire tx_ecrc_pause;
//----------------------------------------------------------------------------//
// THROTTLE REASON: PCIe link is down //
// - When to throttle: trn_lnk_up deasserted //
// - When to stop: trn_tdst_rdy assesrted //
//----------------------------------------------------------------------------//
assign lnk_up_trig = !trn_lnk_up;
assign lnk_up_exit = trn_tdst_rdy;
always @(posedge user_clk) begin
if(user_rst) begin
lnk_up_thrtl <= #TCQ 1'b1;
end
else begin
if(lnk_up_trig) begin
lnk_up_thrtl <= #TCQ 1'b1;
end
else if(lnk_up_exit) begin
lnk_up_thrtl <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Transmit buffers depleted //
// - When to throttle: trn_tbuf_av falls to 0 //
// - When to stop: trn_tbuf_av rises above 0 again //
//----------------------------------------------------------------------------//
assign tbuf_av_min_trig = (trn_tbuf_av <= TBUF_AV_MIN);
always @(posedge user_clk) begin
if(user_rst) begin
tbuf_av_min_thrtl <= #TCQ 1'b0;
end
else begin
if(tbuf_av_min_trig) begin
tbuf_av_min_thrtl <= #TCQ 1'b1;
end
// The exit condition for tbuf_av_min_thrtl is !tbuf_av_min_trig
else begin
tbuf_av_min_thrtl <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Transmit buffers getting low //
// - When to throttle: trn_tbuf_av falls below "gap" threshold TBUF_AV_GAP //
// - When to stop: after TBUF_GAP_TIME cycles elapse //
// //
// If we're about to run out of transmit buffers, throttle the user for a //
// few clock cycles to give the PCIe block time to catch up. This is //
// needed to compensate for latency in decrementing trn_tbuf_av in the PCIe //
// Block transmit path. //
//----------------------------------------------------------------------------//
// Detect two different scenarios for buffers getting low:
// 1) If we see a TLAST. a new packet has been inserted into the buffer, and
// we need to pause and let that packet "soak in"
assign gap_trig_tlast = (trn_tbuf_av <= TBUF_AV_GAP) &&
s_axis_tx_tvalid && tready_thrtl && s_axis_tx_tlast;
// 2) Any time tbug_avail decrements to the TBUF_AV_GAP threshold, we need to
// pause and make sure no other packets are about to soak in and cause the
// buffer availability to drop further.
assign gap_trig_decr = (trn_tbuf_av == (TBUF_AV_GAP)) &&
(tbuf_av_d == (TBUF_AV_GAP+1));
assign gap_trig_tcfg = (tcfg_req_thrtl && tcfg_req_exit);
assign tbuf_av_gap_trig = gap_trig_tlast || gap_trig_decr || gap_trig_tcfg;
assign tbuf_av_gap_exit = (tbuf_gap_cnt == 0);
always @(posedge user_clk) begin
if(user_rst) begin
tbuf_av_gap_thrtl <= #TCQ 1'b0;
tbuf_gap_cnt <= #TCQ 3'h0;
tbuf_av_d <= #TCQ 6'h00;
end
else begin
if(tbuf_av_gap_trig) begin
tbuf_av_gap_thrtl <= #TCQ 1'b1;
end
else if(tbuf_av_gap_exit) begin
tbuf_av_gap_thrtl <= #TCQ 1'b0;
end
// tbuf gap counter:
// This logic controls the length of the throttle condition when tbufs are
// getting low.
if(tbuf_av_gap_thrtl && (cur_state == THROTTLE)) begin
if(tbuf_gap_cnt > 0) begin
tbuf_gap_cnt <= #TCQ tbuf_gap_cnt - 3'd1;
end
end
else begin
tbuf_gap_cnt <= #TCQ TBUF_GAP_TIME;
end
tbuf_av_d <= #TCQ trn_tbuf_av;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to send a CFG response //
// - When to throttle: trn_tcfg_req and user_tcfg_gnt asserted //
// - When to stop: after trn_tdst_rdy transitions to unasserted //
// //
// If the block needs to send a response to a CFG packet, this will cause //
// the subsequent deassertion of trn_tdst_rdy. When the user design permits, //
// grant permission to the block to service request and throttle the user. //
//----------------------------------------------------------------------------//
assign tcfg_req_trig = trn_tcfg_req && reg_tcfg_gnt;
assign tcfg_req_exit = (tcfg_req_cnt == 2'd0) && !trn_tdst_rdy_d &&
trn_tdst_rdy;
always @(posedge user_clk) begin
if(user_rst) begin
tcfg_req_thrtl <= #TCQ 1'b0;
trn_tcfg_req_d <= #TCQ 1'b0;
trn_tdst_rdy_d <= #TCQ 1'b1;
reg_tcfg_gnt <= #TCQ 1'b0;
tcfg_req_cnt <= #TCQ 2'd0;
tcfg_gnt_pending <= #TCQ 1'b0;
end
else begin
if(tcfg_req_trig) begin
tcfg_req_thrtl <= #TCQ 1'b1;
end
else if(tcfg_req_exit) begin
tcfg_req_thrtl <= #TCQ 1'b0;
end
// We need to wait the appropriate amount of time for the tcfg_gnt to
// "sink in" to the PCIe block. After that, we know that the PCIe block will
// not reassert trn_tdst_rdy until the CFG request has been serviced. If a
// new request is being service (tcfg_gnt_log == 1), then reset the timer.
if((trn_tcfg_req && !trn_tcfg_req_d) || tcfg_gnt_pending) begin
tcfg_req_cnt <= #TCQ TCFG_LATENCY_TIME;
end
else begin
if(tcfg_req_cnt > 0) begin
tcfg_req_cnt <= #TCQ tcfg_req_cnt - 2'd1;
end
end
// Make sure tcfg_gnt_log pulses once for one clock cycle for every
// cfg packet request.
if(trn_tcfg_req && !trn_tcfg_req_d) begin
tcfg_gnt_pending <= #TCQ 1'b1;
end
else if(tcfg_gnt_log) begin
tcfg_gnt_pending <= #TCQ 1'b0;
end
trn_tcfg_req_d <= #TCQ trn_tcfg_req;
trn_tdst_rdy_d <= #TCQ trn_tdst_rdy;
reg_tcfg_gnt <= #TCQ user_tcfg_gnt;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to transition to low power state PPM L1 //
// - When to throttle: appropriate low power state signal asserted //
// (architecture dependent) //
// - When to stop: cfg_pcie_link_state goes to proper value (C_ROOT_PORT //
// dependent) //
// //
// If the block needs to transition to PM state PPM L1, we need to finish //
// up what we're doing and throttle immediately. //
//----------------------------------------------------------------------------//
generate
// PPM L1 signals for 7 Series in RC mode
if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L1_thrtl_rp
assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
(cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
end
// PPM L1 signals for 7 Series in EP mode
else if((C_FAMILY == "X7") && (C_ROOT_PORT == "FALSE")) begin : x7_L1_thrtl_ep
assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
(cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
end
// PPM L1 signals for V6 in RC mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L1_thrtl_rp
assign ppm_L1_trig = (trn_rdllp_data[31:24] == PM_ENTER_L1) &&
trn_rdllp_src_rdy && !trn_rdllp_src_rdy_d;
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
end
// PPM L1 signals for V6 in EP mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "FALSE")) begin : v6_L1_thrtl_ep
assign ppm_L1_trig = (cfg_pmcsr_powerstate != POWERSTATE_D0);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
end
// PPM L1 detection not supported for S6
else begin : s6_L1_thrtl
assign ppm_L1_trig = 1'b0;
assign ppm_L1_exit = 1'b1;
end
endgenerate
always @(posedge user_clk) begin
if(user_rst) begin
ppm_L1_thrtl <= #TCQ 1'b0;
cfg_pcie_link_state_d <= #TCQ 3'b0;
trn_rdllp_src_rdy_d <= #TCQ 1'b0;
end
else begin
if(ppm_L1_trig) begin
ppm_L1_thrtl <= #TCQ 1'b1;
end
else if(ppm_L1_exit) begin
ppm_L1_thrtl <= #TCQ 1'b0;
end
cfg_pcie_link_state_d <= #TCQ cfg_pcie_link_state;
trn_rdllp_src_rdy_d <= #TCQ trn_rdllp_src_rdy;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to transition to low power state PPM L2/3 //
// - When to throttle: appropriate PM signal indicates a transition to //
// L2/3 is pending or in progress (family and role dependent) //
// - When to stop: never (the only path out of L2/3 is a full reset) //
// //
// If the block needs to transition to PM state PPM L2/3, we need to finish //
// up what we're doing and throttle when the user gives permission. //
//----------------------------------------------------------------------------//
generate
// PPM L2/3 signals for 7 Series in RC mode
if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L23_thrtl_rp
assign ppm_L23_trig = (cfg_pcie_link_state_d == LINKSTATE_PPM_L23R_TRANS);
assign wire_to_turnoff = 1'b0;
end
// PPM L2/3 signals for V6 in RC mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L23_thrtl_rp
assign ppm_L23_trig = cfg_pm_send_pme_to;
assign wire_to_turnoff = 1'b0;
end
// PPM L2/3 signals in EP mode
else begin : L23_thrtl_ep
assign ppm_L23_trig = wire_to_turnoff && reg_turnoff_ok;
// PPM L2/3 signals for 7 Series in EP mode
// For 7 Series, cfg_to_turnoff pulses once when a turnoff request is
// outstanding, so we need a "sticky" register that grabs the request.
if(C_FAMILY == "X7") begin : x7_L23_thrtl_ep
reg reg_to_turnoff;
always @(posedge user_clk) begin
if(user_rst) begin
reg_to_turnoff <= #TCQ 1'b0;
end
else begin
if(cfg_to_turnoff) begin
reg_to_turnoff <= #TCQ 1'b1;
end
end
end
assign wire_to_turnoff = reg_to_turnoff;
end
// PPM L2/3 signals for V6/S6 in EP mode
// In V6 and S6, the to_turnoff signal asserts and remains asserted until
// turnoff_ok is asserted, so a sticky reg is not necessary.
else begin : v6_s6_L23_thrtl_ep
assign wire_to_turnoff = cfg_to_turnoff;
end
always @(posedge user_clk) begin
if(user_rst) begin
reg_turnoff_ok <= #TCQ 1'b0;
end
else begin
reg_turnoff_ok <= #TCQ user_turnoff_ok;
end
end
end
endgenerate
always @(posedge user_clk) begin
if(user_rst) begin
ppm_L23_thrtl <= #TCQ 1'b0;
cfg_turnoff_ok_pending <= #TCQ 1'b0;
end
else begin
if(ppm_L23_trig) begin
ppm_L23_thrtl <= #TCQ 1'b1;
end
// Make sure cfg_turnoff_ok pulses once for one clock cycle for every
// turnoff request.
if(ppm_L23_trig && !ppm_L23_thrtl) begin
cfg_turnoff_ok_pending <= #TCQ 1'b1;
end
else if(cfg_turnoff_ok) begin
cfg_turnoff_ok_pending <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create axi_thrtl_ok. This signal determines if it's OK to throttle the //
// user design on the AXI interface. Since TREADY is registered, this signal //
// needs to assert on the cycle ~before~ we actually intend to throttle. //
// The only time it's OK to throttle when TVALID is asserted is on the first //
// beat of a new packet. Therefore, assert axi_thrtl_ok if one of the //
// is true: //
// 1) The user is not in a packet and is not starting one //
// 2) The user is just finishing a packet //
// 3) We're already throttled, so it's OK to continue throttling //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
reg_axi_in_pkt <= #TCQ 1'b0;
end
else begin
if(s_axis_tx_tvalid && s_axis_tx_tlast) begin
reg_axi_in_pkt <= #TCQ 1'b0;
end
else if(tready_thrtl && s_axis_tx_tvalid) begin
reg_axi_in_pkt <= #TCQ 1'b1;
end
end
end
assign axi_in_pkt = s_axis_tx_tvalid || reg_axi_in_pkt;
assign axi_pkt_ending = s_axis_tx_tvalid && s_axis_tx_tlast;
assign axi_throttled = !tready_thrtl;
assign axi_thrtl_ok = !axi_in_pkt || axi_pkt_ending || axi_throttled;
//----------------------------------------------------------------------------//
// Throttle CTL State Machine: //
// Throttle user design when a throttle trigger (or triggers) occur. //
// Keep user throttled until all exit criteria have been met. //
//----------------------------------------------------------------------------//
// Immediate throttle signal. Used to "pounce" on a throttle opportunity when
// we're seeking one
assign pre_throttle = tbuf_av_min_trig || tbuf_av_gap_trig || lnk_up_trig
|| tcfg_req_trig || ppm_L1_trig || ppm_L23_trig;
// Registered throttle signals. Used to control throttle state machine
assign reg_throttle = tbuf_av_min_thrtl || tbuf_av_gap_thrtl || lnk_up_thrtl
|| tcfg_req_thrtl || ppm_L1_thrtl || ppm_L23_thrtl;
assign exit_crit = !tbuf_av_min_thrtl && !tbuf_av_gap_thrtl && !lnk_up_thrtl
&& !tcfg_req_thrtl && !ppm_L1_thrtl && !ppm_L23_thrtl;
always @(*) begin
case(cur_state)
// IDLE: in this state we're waiting for a trigger event to occur. As
// soon as an event occurs and the user isn't transmitting a packet, we
// throttle the PCIe block and the user and next state is THROTTLE.
IDLE: begin
if(reg_throttle && axi_thrtl_ok) begin
// Throttle user
tready_thrtl_mux = 1'b0;
next_state = THROTTLE;
// Assert appropriate grant signal depending on the throttle type.
if(tcfg_req_thrtl) begin
tcfg_gnt_log = 1'b1; // For cfg request, grant the request
cfg_turnoff_ok = 1'b0; //
end
else if(ppm_L23_thrtl) begin
tcfg_gnt_log = 1'b0; //
cfg_turnoff_ok = 1'b1; // For PM request, permit transition
end
else begin
tcfg_gnt_log = 1'b0; // Otherwise do nothing
cfg_turnoff_ok = 1'b0; //
end
end
// If there's not throttle event, do nothing
else begin
// Throttle user as soon as possible
tready_thrtl_mux = !(axi_thrtl_ok && pre_throttle);
next_state = IDLE;
tcfg_gnt_log = 1'b0;
cfg_turnoff_ok = 1'b0;
end
end
// THROTTLE: in this state the user is throttle and we're waiting for
// exit criteria, which tells us that the throttle event is over. When
// the exit criteria is satisfied, de-throttle the user and next state
// is IDLE.
THROTTLE: begin
if(exit_crit) begin
// Dethrottle user
tready_thrtl_mux = !pre_throttle;
next_state = IDLE;
end
else begin
// Throttle user
tready_thrtl_mux = 1'b0;
next_state = THROTTLE;
end
// Assert appropriate grant signal depending on the throttle type.
if(tcfg_req_thrtl && tcfg_gnt_pending) begin
tcfg_gnt_log = 1'b1; // For cfg request, grant the request
cfg_turnoff_ok = 1'b0; //
end
else if(cfg_turnoff_ok_pending) begin
tcfg_gnt_log = 1'b0; //
cfg_turnoff_ok = 1'b1; // For PM request, permit transition
end
else begin
tcfg_gnt_log = 1'b0; // Otherwise do nothing
cfg_turnoff_ok = 1'b0; //
end
end
default: begin
tready_thrtl_mux = 1'b0;
next_state = IDLE;
tcfg_gnt_log = 1'b0;
cfg_turnoff_ok = 1'b0;
end
endcase
end
// Synchronous logic
always @(posedge user_clk) begin
if(user_rst) begin
// Throttle user by default until link comes up
cur_state <= #TCQ THROTTLE;
reg_tlast <= #TCQ 1'b0;
tready_thrtl <= #TCQ 1'b0;
end
else begin
cur_state <= #TCQ next_state;
tready_thrtl <= #TCQ tready_thrtl_mux && !tx_ecrc_pause;
reg_tlast <= #TCQ s_axis_tx_tlast;
end
end
// For X7, the PCIe block will generate the ECRC for a packet if trn_tecrc_gen
// is asserted at SOF. In this case, the Block needs an extra data beat to
// calculate the ECRC, but only if the following conditions are met:
// 1) there is no empty DWORDS at the end of the packet
// (i.e. packet length % C_DATA_WIDTH == 0)
//
// 2) There isn't a ECRC in the TLP already, as indicated by the TD bit in the
// TLP header
//
// If both conditions are met, the Block will stall the TRN interface for one
// data beat after EOF. We need to predict this stall and preemptively stall the
// User for one beat.
generate
if(C_FAMILY == "X7") begin : ecrc_pause_enabled
wire tx_ecrc_pkt;
reg reg_tx_ecrc_pkt;
wire [1:0] packet_fmt;
wire packet_td;
wire [2:0] header_len;
wire [9:0] payload_len;
wire [13:0] packet_len;
wire pause_needed;
// Grab necessary packet fields
assign packet_fmt = s_axis_tx_tdata[30:29];
assign packet_td = s_axis_tx_tdata[15];
// Calculate total packet length
assign header_len = packet_fmt[0] ? 3'd4 : 3'd3;
assign payload_len = packet_fmt[1] ? s_axis_tx_tdata[9:0] : 10'h0;
assign packet_len = {10'h000, header_len} + {4'h0, payload_len};
// Determine if packet a ECRC pause is needed
if(C_DATA_WIDTH == 128) begin : packet_len_check_128
assign pause_needed = (packet_len[1:0] == 2'b00) && !packet_td;
end
else begin : packet_len_check_64
assign pause_needed = (packet_len[0] == 1'b0) && !packet_td;
end
// Create flag to alert TX pipeline to insert a stall
assign tx_ecrc_pkt = s_axis_tx_tuser[0] && pause_needed &&
tready_thrtl && s_axis_tx_tvalid && !reg_axi_in_pkt;
always @(posedge user_clk) begin
if(user_rst) begin
reg_tx_ecrc_pkt <= #TCQ 1'b0;
end
else begin
if(tx_ecrc_pkt && !s_axis_tx_tlast) begin
reg_tx_ecrc_pkt <= #TCQ 1'b1;
end
else if(tready_thrtl && s_axis_tx_tvalid && s_axis_tx_tlast) begin
reg_tx_ecrc_pkt <= #TCQ 1'b0;
end
end
end
// Insert the stall now
assign tx_ecrc_pause = ((tx_ecrc_pkt || reg_tx_ecrc_pkt) &&
s_axis_tx_tlast && s_axis_tx_tvalid && tready_thrtl);
end
else begin : ecrc_pause_disabled
assign tx_ecrc_pause = 1'b0;
end
endgenerate
// Logic for 128-bit single cycle bug fix.
// This tcfg_gnt pipeline addresses an issue with 128-bit V6 designs where a
// single cycle packet transmitted simultaneously with an assertion of tcfg_gnt
// from AXI Basic causes the packet to be dropped. The packet drop occurs
// because the 128-bit shim doesn't know about the tcfg_req/gnt, and therefor
// isn't expecting trn_tdst_rdy to go low. Since the 128-bit shim does throttle
// prediction just as we do, it ignores the value of trn_tdst_rdy, and
// ultimately drops the packet when transmitting the packet to the block.
generate
if(C_DATA_WIDTH == 128 && C_FAMILY == "V6") begin : tcfg_gnt_pipeline
genvar stage;
reg tcfg_gnt_pipe [TCFG_GNT_PIPE_STAGES:0];
// Create a configurable depth FF delay pipeline
for(stage = 0; stage < TCFG_GNT_PIPE_STAGES; stage = stage + 1)
begin : tcfg_gnt_pipeline_stage
always @(posedge user_clk) begin
if(user_rst) begin
tcfg_gnt_pipe[stage] <= #TCQ 1'b0;
end
else begin
// For stage 0, insert the actual tcfg_gnt signal from logic
if(stage == 0) begin
tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_log;
end
// For stages 1+, chain together
else begin
tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_pipe[stage - 1];
end
end
end
// tcfg_gnt output to block assigned the last pipeline stage
assign trn_tcfg_gnt = tcfg_gnt_pipe[TCFG_GNT_PIPE_STAGES-1];
end
end
else begin : tcfg_gnt_no_pipeline
// For all other architectures, no pipeline delay needed for tcfg_gnt
assign trn_tcfg_gnt = tcfg_gnt_log;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Cal Poly Pomona
// Engineer: Byron Phung
//
// Create Date: 23:23:50 04/27/2016
// Design Name:
// Module Name: Search_8Comparators
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Search_8Comparators(
input clock,
input reset,
input [1023:0] data,
input [63:0] key,
output reg match
);
// Use the counter to determine which bits of data to use.
reg [7:0] counter;
// Track the data needed for each comparator.
reg [63:0] data1, data2, data3, data4, data5, data6, data7, data8;
// Track each match output for each comparator.
wire match1, match2, match3, match4, match5, match6, match7, match8;
Comparator c1
(
.data(data1),
.key(key),
.match(match1)
);
Comparator c2
(
.data(data2),
.key(key),
.match(match2)
);
Comparator c3
(
.data(data3),
.key(key),
.match(match3)
);
Comparator c4
(
.data(data4),
.key(key),
.match(match4)
);
Comparator c5
(
.data(data5),
.key(key),
.match(match5)
);
Comparator c6
(
.data(data6),
.key(key),
.match(match6)
);
Comparator c7
(
.data(data7),
.key(key),
.match(match7)
);
Comparator c8
(
.data(data8),
.key(key),
.match(match8)
);
// Sequential Logic
always @(posedge clock, posedge reset)
begin
// If reset, reset every variable to their defaults.
if (reset)
begin
counter <= 0;
match <= 0;
end
// Otherwise, calculate the desired values.
else
begin
// If the last count is reached, then reset the counter.
// Equation: last count = (data_size - comparator_size) / num_of_comparators
if (counter == 120)
counter <= 0;
// Otherwise, increment the counter.
else
counter <= counter + 1;
// If the comparators yield matches for any of the current searches,
// then set the overall match to 1.
if (match1 || match2 || match3 || match4)
match <= 1;
// Otherwise, set it to 0.
else
match <= 0;
end
end
always @*
begin
if (counter == 120)
begin
data1 = data[1023-4*counter-:64];
data2 = data[1023-4*counter-:64];
data3 = data[1023-4*counter-:64];
data4 = data[1023-4*counter-:64];
data5 = data[1023-4*counter-:64];
data6 = data[1023-4*counter-:64];
data7 = data[1023-4*counter-:64];
data8 = data[1023-4*counter-:64];
end
else
begin
data1 = data[1023-4*counter-:64];
data2 = data[1022-4*counter-:64];
data3 = data[1021-4*counter-:64];
data4 = data[1020-4*counter-:64];
data5 = data[1019-4*counter-:64];
data6 = data[1018-4*counter-:64];
data7 = data[1017-4*counter-:64];
data8 = data[1016-4*counter-:64];
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: ROM_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//////////////////////////////////////////////////////////////////////////////////
module ROM_test #(parameter W=32)(
input wire [9:0] address,
output reg [W-1:0] data
);
localparam ROM_FILE32 = "/home/carlos/Documents/0.0066777-0.58495_HEX.txt";
localparam ROM_FILE64= "C:/Users/XXXXX/Desktop/RTL/NORMALIZACION_V.txt";
//(* rom_style="{distributed | block}" *)
reg [W-1:0] rom_test [1023:0];
generate
if(W==32)
initial
begin
$readmemh( ROM_FILE32 , rom_test, 0, 1023);
end
else
initial
begin
$readmemh(ROM_FILE64, rom_test, 0, 1023);
end
endgenerate
always @*
begin
data = rom_test[address];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NAND3_FUNCTIONAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand3 (
VPWR,
VGND,
Y ,
A ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_TB_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD3_TB_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv3sd3.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__clkdlyinv3sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD3_TB_V
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module MC6502(
clk,
rst_x,
i_rdy,
i_irq_x,
i_nmi_x,
io_db,
o_clk1,
o_clk2,
o_sync,
o_rw,
o_ab);
input clk;
input rst_x;
input i_rdy;
input i_irq_x;
input i_nmi_x;
inout [ 7:0] io_db;
output o_clk1;
output o_clk2;
output o_sync;
output o_rw;
output [15:0] o_ab;
// InterruptLogic <=> MemoryController
wire [ 7:0] w_mc2il_data;
wire w_mc2il_brk;
wire [15:0] w_il2mc_addr;
wire w_il2mc_read;
wire w_il2mc_write;
wire [ 7:0] w_il2mc_data;
// InterruptLogic <=> RegisterFile
wire [ 7:0] w_rf2il_s;
wire [ 7:0] w_rf2il_psr;
wire [15:0] w_rf2il_pc;
wire w_il2rf_set_i;
wire w_il2rf_set_b;
wire [ 7:0] w_il2rf_data;
wire w_il2rf_set_pcl;
wire w_il2rf_set_pch;
wire w_il2rf_pushed;
// RegisterFile <=> MemoryController
wire [15:0] w_rf2mc_pc;
wire [ 7:0] w_rf2mc_a;
wire [ 7:0] w_rf2mc_x;
wire [ 7:0] w_rf2mc_y;
wire [ 7:0] w_rf2mc_s;
wire [ 7:0] w_rf2mc_psr;
wire w_mc2rf_fetched;
wire w_mc2rf_pushed;
wire w_mc2rf_pull;
wire [15:0] w_mc2rf_pc;
wire w_mc2rf_set_pc;
wire [ 7:0] w_mc2rf_psr;
wire w_mc2rf_set_psr;
// InstructionDecode <=> MemoryController
wire [ 7:0] w_mc2id_data;
wire w_mc2id_valid;
wire w_id2mc_fetch;
wire w_id2mc_sync;
wire w_id2mc_operand;
wire [ 2:0] w_id2mc_mode;
wire w_id2mc_modex;
wire [ 1:0] w_id2mc_reg;
wire w_id2mc_store;
wire w_id2mc_push;
wire w_id2mc_pop;
wire w_id2mc_p_reg;
wire w_id2mc_jump;
// InstructionDecode <=> ExecutionController
wire w_id2ec_reset_c;
wire w_id2ec_set_c;
wire w_id2ec_reset_i;
wire w_id2ec_set_i;
wire w_id2ec_reset_v;
wire w_id2ec_reset_d;
wire w_id2ec_set_d;
wire w_id2ec_load;
wire w_id2ec_ops;
wire w_id2ec_branch;
wire [ 4:0] w_id2ec_opcode;
wire [ 7:0] w_id2ec_data;
wire [ 1:0] w_id2ec_reg;
wire w_ec2id_done;
// ExecutionController <=> RegisterFile
wire [ 7:0] w_rf2ec_pcl;
wire [ 7:0] w_rf2ec_pch;
wire [ 7:0] w_rf2ec_a;
wire [ 7:0] w_rf2ec_x;
wire [ 7:0] w_rf2ec_y;
wire w_rf2ec_c;
wire w_rf2ec_d;
wire w_rf2ec_n;
wire w_rf2ec_v;
wire w_rf2ec_z;
wire w_ec2rf_c;
wire w_ec2rf_set_c;
wire w_ec2rf_i;
wire w_ec2rf_set_i;
wire w_ec2rf_v;
wire w_ec2rf_set_v;
wire w_ec2rf_d;
wire w_ec2rf_set_d;
wire w_ec2rf_n;
wire w_ec2rf_set_n;
wire w_ec2rf_z;
wire w_ec2rf_set_z;
wire [ 7:0] w_ec2rf_data;
wire w_ec2rf_set_a;
wire w_ec2rf_set_x;
wire w_ec2rf_set_y;
wire w_ec2rf_set_s;
wire w_ec2rf_set_pcl;
wire w_ec2rf_set_pch;
// ExecutionController <=> MemoryController
wire [ 7:0] w_ec2mc_data;
wire w_ec2mc_store;
// Global wires
wire [ 7:0] i_db;
wire [ 7:0] o_db;
assign o_clk1 = clk;
assign o_clk2 = !clk;
assign io_db = o_rw ? 8'hzz : o_db;
assign i_db = o_rw ? io_db : 8'hzz;
MC6502MemoryController mc(
.clk (clk ),
.rst_x (rst_x ),
.i_rdy (i_rdy ),
.i_db (i_db ),
.o_db (o_db ),
.o_ab (o_ab ),
.o_rw (o_rw ),
.o_sync (o_sync ),
.il2mc_addr (w_il2mc_addr ),
.il2mc_read (w_il2mc_read ),
.il2mc_write (w_il2mc_write ),
.il2mc_data (w_il2mc_data ),
.mc2il_data (w_mc2il_data ),
.mc2il_brk (w_mc2il_brk ),
.rf2mc_pc (w_rf2mc_pc ),
.rf2mc_a (w_rf2mc_a ),
.rf2mc_x (w_rf2mc_x ),
.rf2mc_y (w_rf2mc_y ),
.rf2mc_s (w_rf2mc_s ),
.rf2mc_psr (w_rf2mc_psr ),
.mc2rf_fetched(w_mc2rf_fetched),
.mc2rf_pushed (w_mc2rf_pushed ),
.mc2rf_pull (w_mc2rf_pull ),
.mc2rf_pc (w_mc2rf_pc ),
.mc2rf_set_pc (w_mc2rf_set_pc ),
.mc2rf_psr (w_mc2rf_psr ),
.mc2rf_set_psr(w_mc2rf_set_psr),
.id2mc_fetch (w_id2mc_fetch ),
.id2mc_sync (w_id2mc_sync ),
.id2mc_operand(w_id2mc_operand),
.id2mc_mode (w_id2mc_mode ),
.id2mc_modex (w_id2mc_modex ),
.id2mc_reg (w_id2mc_reg ),
.id2mc_store (w_id2mc_store ),
.id2mc_push (w_id2mc_push ),
.id2mc_pop (w_id2mc_pop ),
.id2mc_p_reg (w_id2mc_p_reg ),
.id2mc_jump (w_id2mc_jump ),
.mc2id_data (w_mc2id_data ),
.mc2id_valid (w_mc2id_valid ),
.ec2mc_data (w_ec2mc_data ),
.ec2mc_store (w_ec2mc_store ));
MC6502InterruptLogic il(
.clk (clk ),
.rst_x (rst_x ),
.i_irq_x (i_irq_x ),
.i_nmi_x (i_nmi_x ),
.mc2il_data (w_mc2il_data ),
.mc2il_brk (w_mc2il_brk ),
.il2mc_addr (w_il2mc_addr ),
.il2mc_read (w_il2mc_read ),
.il2mc_write (w_il2mc_write ),
.il2mc_data (w_il2mc_data ),
.rf2il_s (w_rf2il_s ),
.rf2il_psr (w_rf2il_psr ),
.rf2il_pc (w_rf2il_pc ),
.il2rf_set_i (w_il2rf_set_i ),
.il2rf_set_b (w_il2rf_set_b ),
.il2rf_data (w_il2rf_data ),
.il2rf_set_pcl(w_il2rf_set_pcl),
.il2rf_set_pch(w_il2rf_set_pch),
.il2rf_pushed (w_il2rf_pushed ));
MC6502RegisterFile rf(
.clk (clk ),
.rst_x (rst_x ),
.il2rf_set_i (w_il2rf_set_i ),
.il2rf_set_b (w_il2rf_set_b ),
.il2rf_data (w_il2rf_data ),
.il2rf_set_pcl(w_il2rf_set_pcl),
.il2rf_set_pch(w_il2rf_set_pch),
.il2rf_pushed (w_il2rf_pushed ),
.rf2il_s (w_rf2il_s ),
.rf2il_psr (w_rf2il_psr ),
.rf2il_pc (w_rf2il_pc ),
.mc2rf_fetched(w_mc2rf_fetched),
.mc2rf_pushed (w_mc2rf_pushed ),
.mc2rf_pull (w_mc2rf_pull ),
.mc2rf_pc (w_mc2rf_pc ),
.mc2rf_set_pc (w_mc2rf_set_pc ),
.mc2rf_psr (w_mc2rf_psr ),
.mc2rf_set_psr(w_mc2rf_set_psr),
.rf2mc_pc (w_rf2mc_pc ),
.rf2mc_a (w_rf2mc_a ),
.rf2mc_x (w_rf2mc_x ),
.rf2mc_y (w_rf2mc_y ),
.rf2mc_s (w_rf2mc_s ),
.rf2mc_psr (w_rf2mc_psr ),
.ec2rf_c (w_ec2rf_c ),
.ec2rf_set_c (w_ec2rf_set_c ),
.ec2rf_i (w_ec2rf_i ),
.ec2rf_set_i (w_ec2rf_set_i ),
.ec2rf_v (w_ec2rf_v ),
.ec2rf_set_v (w_ec2rf_set_v ),
.ec2rf_d (w_ec2rf_d ),
.ec2rf_set_d (w_ec2rf_set_d ),
.ec2rf_n (w_ec2rf_n ),
.ec2rf_set_n (w_ec2rf_set_n ),
.ec2rf_z (w_ec2rf_z ),
.ec2rf_set_z (w_ec2rf_set_z ),
.ec2rf_data (w_ec2rf_data ),
.ec2rf_set_a (w_ec2rf_set_a ),
.ec2rf_set_x (w_ec2rf_set_x ),
.ec2rf_set_y (w_ec2rf_set_y ),
.ec2rf_set_s (w_ec2rf_set_s ),
.ec2rf_set_pcl(w_ec2rf_set_pcl),
.ec2rf_set_pch(w_ec2rf_set_pch),
.rf2ec_pcl (w_rf2ec_pcl ),
.rf2ec_pch (w_rf2ec_pch ),
.rf2ec_a (w_rf2ec_a ),
.rf2ec_x (w_rf2ec_x ),
.rf2ec_y (w_rf2ec_y ),
.rf2ec_c (w_rf2ec_c ),
.rf2ec_d (w_rf2ec_d ),
.rf2ec_n (w_rf2ec_n ),
.rf2ec_v (w_rf2ec_v ),
.rf2ec_z (w_rf2ec_z ));
MC6502InstructionDecode id(
.clk (clk ),
.rst_x (rst_x ),
.mc2id_data (w_mc2id_data ),
.mc2id_valid (w_mc2id_valid ),
.id2mc_fetch (w_id2mc_fetch ),
.id2mc_sync (w_id2mc_sync ),
.id2mc_operand(w_id2mc_operand),
.id2mc_mode (w_id2mc_mode ),
.id2mc_modex (w_id2mc_modex ),
.id2mc_reg (w_id2mc_reg ),
.id2mc_store (w_id2mc_store ),
.id2mc_push (w_id2mc_push ),
.id2mc_pop (w_id2mc_pop ),
.id2mc_p_reg (w_id2mc_p_reg ),
.id2mc_jump (w_id2mc_jump ),
.id2ec_reset_c(w_id2ec_reset_c),
.id2ec_set_c (w_id2ec_set_c ),
.id2ec_reset_i(w_id2ec_reset_i),
.id2ec_set_i (w_id2ec_set_i ),
.id2ec_reset_v(w_id2ec_reset_v),
.id2ec_reset_d(w_id2ec_reset_d),
.id2ec_set_d (w_id2ec_set_d ),
.id2ec_load (w_id2ec_load ),
.id2ec_ops (w_id2ec_ops ),
.id2ec_branch (w_id2ec_branch ),
.id2ec_opcode (w_id2ec_opcode ),
.id2ec_data (w_id2ec_data ),
.id2ec_reg (w_id2ec_reg ),
.ec2id_done (w_ec2id_done ));
MC6502ExecutionController ec(
.clk (clk ),
.rst_x (rst_x ),
.id2ec_reset_c(w_id2ec_reset_c),
.id2ec_set_c (w_id2ec_set_c ),
.id2ec_reset_i(w_id2ec_reset_i),
.id2ec_set_i (w_id2ec_set_i ),
.id2ec_reset_v(w_id2ec_reset_v),
.id2ec_reset_d(w_id2ec_reset_d),
.id2ec_set_d (w_id2ec_set_d ),
.id2ec_load (w_id2ec_load ),
.id2ec_ops (w_id2ec_ops ),
.id2ec_branch (w_id2ec_branch ),
.id2ec_opcode (w_id2ec_opcode ),
.id2ec_data (w_id2ec_data ),
.id2ec_reg (w_id2ec_reg ),
.ec2id_done (w_ec2id_done ),
.rf2ec_pcl (w_rf2ec_pcl ),
.rf2ec_pch (w_rf2ec_pch ),
.rf2ec_a (w_rf2ec_a ),
.rf2ec_x (w_rf2ec_x ),
.rf2ec_y (w_rf2ec_y ),
.rf2ec_c (w_rf2ec_c ),
.rf2ec_d (w_rf2ec_d ),
.rf2ec_n (w_rf2ec_n ),
.rf2ec_v (w_rf2ec_v ),
.rf2ec_z (w_rf2ec_z ),
.ec2rf_c (w_ec2rf_c ),
.ec2rf_set_c (w_ec2rf_set_c ),
.ec2rf_i (w_ec2rf_i ),
.ec2rf_set_i (w_ec2rf_set_i ),
.ec2rf_v (w_ec2rf_v ),
.ec2rf_set_v (w_ec2rf_set_v ),
.ec2rf_d (w_ec2rf_d ),
.ec2rf_set_d (w_ec2rf_set_d ),
.ec2rf_n (w_ec2rf_n ),
.ec2rf_set_n (w_ec2rf_set_n ),
.ec2rf_z (w_ec2rf_z ),
.ec2rf_set_z (w_ec2rf_set_z ),
.ec2rf_data (w_ec2rf_data ),
.ec2rf_set_a (w_ec2rf_set_a ),
.ec2rf_set_x (w_ec2rf_set_x ),
.ec2rf_set_y (w_ec2rf_set_y ),
.ec2rf_set_s (w_ec2rf_set_s ),
.ec2rf_set_pcl(w_ec2rf_set_pcl),
.ec2rf_set_pch(w_ec2rf_set_pch),
.ec2mc_data (w_ec2mc_data ),
.ec2mc_store (w_ec2mc_store ));
endmodule // MC6502
|
// megafunction wizard: %ALTFP_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_mult
// ============================================================
// File Name: fp_mult_v1.v
// Megafunction Name(s):
// altfp_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_mult CBX_AUTO_BLACKBOX="ALL" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" PIPELINE=11 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=11 WIDTH_MAN=52 clock dataa datab result
//VERSION_BEGIN 8.1 cbx_alt_ded_mult_y 2008:05:19:10:01:35:SJ cbx_altbarrel_shift 2008:05:19:10:20:21:SJ cbx_altfp_mult 2008:05:19:10:46:44:SJ cbx_altmult_add 2008:09:05:12:07:25:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_lpm_mult 2008:08:08:14:38:02:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_padd 2008:07:31:17:08:03:SJ cbx_parallel_add 2008:05:19:10:26:21:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_add_sub 4 lpm_mult 1 reg 497
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_mult_v1_altfp_mult_ogj
(
clock,
dataa,
datab,
result) ;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
reg dataa_exp_all_one_ff_p1;
reg dataa_exp_not_zero_ff_p1;
reg dataa_man_not_zero_ff_p1;
reg dataa_man_not_zero_ff_p2;
reg datab_exp_all_one_ff_p1;
reg datab_exp_not_zero_ff_p1;
reg datab_man_not_zero_ff_p1;
reg datab_man_not_zero_ff_p2;
reg [12:0] delay_exp2_bias;
reg [12:0] delay_exp3_bias;
reg [12:0] delay_exp_bias;
reg delay_man_product_msb;
reg delay_man_product_msb2;
reg delay_man_product_msb_p0;
reg delay_man_product_msb_p1;
reg [52:0] delay_round;
reg [11:0] exp_add_p1;
reg [12:0] exp_adj_p1;
reg [12:0] exp_adj_p2;
reg [11:0] exp_bias_p1;
reg [11:0] exp_bias_p2;
reg [11:0] exp_bias_p3;
reg [10:0] exp_result_ff;
reg input_is_infinity_dffe_0;
reg input_is_infinity_dffe_1;
reg input_is_infinity_dffe_2;
reg input_is_infinity_dffe_3;
reg input_is_infinity_ff1;
reg input_is_infinity_ff2;
reg input_is_infinity_ff3;
reg input_is_infinity_ff4;
reg input_is_infinity_ff5;
reg input_is_nan_dffe_0;
reg input_is_nan_dffe_1;
reg input_is_nan_dffe_2;
reg input_is_nan_dffe_3;
reg input_is_nan_ff1;
reg input_is_nan_ff2;
reg input_is_nan_ff3;
reg input_is_nan_ff4;
reg input_is_nan_ff5;
reg input_not_zero_dffe_0;
reg input_not_zero_dffe_1;
reg input_not_zero_dffe_2;
reg input_not_zero_dffe_3;
reg input_not_zero_ff1;
reg input_not_zero_ff2;
reg input_not_zero_ff3;
reg input_not_zero_ff4;
reg input_not_zero_ff5;
reg lsb_dffe;
reg [51:0] man_result_ff;
reg man_round_carry;
reg man_round_carry_p0;
reg [52:0] man_round_p;
reg [52:0] man_round_p0;
reg [52:0] man_round_p1;
reg [53:0] man_round_p2;
reg round_dffe;
reg [0:0] sign_node_ff0;
reg [0:0] sign_node_ff1;
reg [0:0] sign_node_ff2;
reg [0:0] sign_node_ff3;
reg [0:0] sign_node_ff4;
reg [0:0] sign_node_ff5;
reg [0:0] sign_node_ff6;
reg [0:0] sign_node_ff7;
reg [0:0] sign_node_ff8;
reg [0:0] sign_node_ff9;
reg [0:0] sign_node_ff10;
reg sticky_dffe;
wire [11:0] wire_exp_add_adder_result;
wire [12:0] wire_exp_adj_adder_result;
wire [12:0] wire_exp_bias_subtr_result;
wire [53:0] wire_man_round_adder_result;
wire [105:0] wire_man_product2_mult_result;
wire aclr;
wire [12:0] bias;
wire clk_en;
wire [10:0] dataa_exp_all_one;
wire [10:0] dataa_exp_not_zero;
wire [51:0] dataa_man_not_zero;
wire [10:0] datab_exp_all_one;
wire [10:0] datab_exp_not_zero;
wire [51:0] datab_man_not_zero;
wire exp_is_inf;
wire exp_is_zero;
wire [12:0] expmod;
wire [10:0] inf_num;
wire lsb_bit;
wire [53:0] man_shift_full;
wire [10:0] result_exp_all_one;
wire [11:0] result_exp_not_zero;
wire round_bit;
wire round_carry;
wire [51:0] sticky_bit;
// synopsys translate_off
initial
dataa_exp_all_one_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_exp_all_one_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_exp_all_one_ff_p1 <= dataa_exp_all_one[10];
// synopsys translate_off
initial
dataa_exp_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_exp_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_exp_not_zero_ff_p1 <= dataa_exp_not_zero[10];
// synopsys translate_off
initial
dataa_man_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_man_not_zero_ff_p1 <= dataa_man_not_zero[25];
// synopsys translate_off
initial
dataa_man_not_zero_ff_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_not_zero_ff_p2 <= 1'b0;
else if (clk_en == 1'b1) dataa_man_not_zero_ff_p2 <= dataa_man_not_zero[51];
// synopsys translate_off
initial
datab_exp_all_one_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_exp_all_one_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_exp_all_one_ff_p1 <= datab_exp_all_one[10];
// synopsys translate_off
initial
datab_exp_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_exp_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_exp_not_zero_ff_p1 <= datab_exp_not_zero[10];
// synopsys translate_off
initial
datab_man_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_man_not_zero_ff_p1 <= datab_man_not_zero[25];
// synopsys translate_off
initial
datab_man_not_zero_ff_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_not_zero_ff_p2 <= 1'b0;
else if (clk_en == 1'b1) datab_man_not_zero_ff_p2 <= datab_man_not_zero[51];
// synopsys translate_off
initial
delay_exp2_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp2_bias <= 13'b0;
else if (clk_en == 1'b1) delay_exp2_bias <= delay_exp_bias;
// synopsys translate_off
initial
delay_exp3_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp3_bias <= 13'b0;
else if (clk_en == 1'b1) delay_exp3_bias <= delay_exp2_bias;
// synopsys translate_off
initial
delay_exp_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp_bias <= 13'b0;
else if (clk_en == 1'b1) delay_exp_bias <= wire_exp_bias_subtr_result;
// synopsys translate_off
initial
delay_man_product_msb = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb <= delay_man_product_msb_p1;
// synopsys translate_off
initial
delay_man_product_msb2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb2 <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb2 <= delay_man_product_msb;
// synopsys translate_off
initial
delay_man_product_msb_p0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb_p0 <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb_p0 <= wire_man_product2_mult_result[105];
// synopsys translate_off
initial
delay_man_product_msb_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb_p1 <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb_p1 <= delay_man_product_msb_p0;
// synopsys translate_off
initial
delay_round = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_round <= 53'b0;
else if (clk_en == 1'b1) delay_round <= ((man_round_p2[52:0] & {53{(~ man_round_p2[53])}}) | (man_round_p2[53:1] & {53{man_round_p2[53]}}));
// synopsys translate_off
initial
exp_add_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_add_p1 <= 12'b0;
else if (clk_en == 1'b1) exp_add_p1 <= wire_exp_add_adder_result;
// synopsys translate_off
initial
exp_adj_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_adj_p1 <= 13'b0;
else if (clk_en == 1'b1) exp_adj_p1 <= delay_exp3_bias;
// synopsys translate_off
initial
exp_adj_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_adj_p2 <= 13'b0;
else if (clk_en == 1'b1) exp_adj_p2 <= wire_exp_adj_adder_result;
// synopsys translate_off
initial
exp_bias_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_bias_p1 <= 12'b0;
else if (clk_en == 1'b1) exp_bias_p1 <= exp_add_p1[11:0];
// synopsys translate_off
initial
exp_bias_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_bias_p2 <= 12'b0;
else if (clk_en == 1'b1) exp_bias_p2 <= exp_bias_p1;
// synopsys translate_off
initial
exp_bias_p3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_bias_p3 <= 12'b0;
else if (clk_en == 1'b1) exp_bias_p3 <= exp_bias_p2;
// synopsys translate_off
initial
exp_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_ff <= 11'b0;
else if (clk_en == 1'b1) exp_result_ff <= ((inf_num & {11{((exp_is_inf | input_is_infinity_ff5) | input_is_nan_ff5)}}) | ((exp_adj_p2[10:0] & {11{(~ exp_is_zero)}}) & {11{input_not_zero_ff5}}));
// synopsys translate_off
initial
input_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_0 <= ((dataa_exp_all_one_ff_p1 & (~ (dataa_man_not_zero_ff_p1 | dataa_man_not_zero_ff_p2))) | (datab_exp_all_one_ff_p1 & (~ (datab_man_not_zero_ff_p1 | datab_man_not_zero_ff_p2))));
// synopsys translate_off
initial
input_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_1 <= input_is_infinity_dffe_0;
// synopsys translate_off
initial
input_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_2 <= input_is_infinity_dffe_1;
// synopsys translate_off
initial
input_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_3 <= input_is_infinity_dffe_2;
// synopsys translate_off
initial
input_is_infinity_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff1 <= input_is_infinity_dffe_3;
// synopsys translate_off
initial
input_is_infinity_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff2 <= input_is_infinity_ff1;
// synopsys translate_off
initial
input_is_infinity_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff3 <= input_is_infinity_ff2;
// synopsys translate_off
initial
input_is_infinity_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff4 <= input_is_infinity_ff3;
// synopsys translate_off
initial
input_is_infinity_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff5 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff5 <= input_is_infinity_ff4;
// synopsys translate_off
initial
input_is_nan_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_0 <= ((dataa_exp_all_one_ff_p1 & (dataa_man_not_zero_ff_p1 | dataa_man_not_zero_ff_p2)) | (datab_exp_all_one_ff_p1 & (datab_man_not_zero_ff_p1 | datab_man_not_zero_ff_p2)));
// synopsys translate_off
initial
input_is_nan_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_1 <= input_is_nan_dffe_0;
// synopsys translate_off
initial
input_is_nan_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_2 <= input_is_nan_dffe_1;
// synopsys translate_off
initial
input_is_nan_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_3 <= input_is_nan_dffe_2;
// synopsys translate_off
initial
input_is_nan_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff1 <= input_is_nan_dffe_3;
// synopsys translate_off
initial
input_is_nan_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff2 <= input_is_nan_ff1;
// synopsys translate_off
initial
input_is_nan_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff3 <= input_is_nan_ff2;
// synopsys translate_off
initial
input_is_nan_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff4 <= input_is_nan_ff3;
// synopsys translate_off
initial
input_is_nan_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff5 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff5 <= input_is_nan_ff4;
// synopsys translate_off
initial
input_not_zero_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_0 <= (dataa_exp_not_zero_ff_p1 & datab_exp_not_zero_ff_p1);
// synopsys translate_off
initial
input_not_zero_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_1 <= input_not_zero_dffe_0;
// synopsys translate_off
initial
input_not_zero_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_2 <= input_not_zero_dffe_1;
// synopsys translate_off
initial
input_not_zero_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_3 <= input_not_zero_dffe_2;
// synopsys translate_off
initial
input_not_zero_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff1 <= input_not_zero_dffe_3;
// synopsys translate_off
initial
input_not_zero_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff2 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff2 <= input_not_zero_ff1;
// synopsys translate_off
initial
input_not_zero_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff3 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff3 <= input_not_zero_ff2;
// synopsys translate_off
initial
input_not_zero_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff4 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff4 <= input_not_zero_ff3;
// synopsys translate_off
initial
input_not_zero_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff5 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff5 <= input_not_zero_ff4;
// synopsys translate_off
initial
lsb_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lsb_dffe <= 1'b0;
else if (clk_en == 1'b1) lsb_dffe <= lsb_bit;
// synopsys translate_off
initial
man_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_ff <= 52'b0;
else if (clk_en == 1'b1) man_result_ff <= {((((((delay_round[51] & input_not_zero_ff5) & (~ input_is_infinity_ff5)) & (~ exp_is_inf)) & (~ exp_is_zero)) | (input_is_infinity_ff5 & (~ input_not_zero_ff5))) | input_is_nan_ff5), (((((delay_round[50:0] & {51{input_not_zero_ff5}}) & {51{(~ input_is_infinity_ff5)}}) & {51{(~ exp_is_inf)}}) & {51{(~ exp_is_zero)}}) & {51{(~ input_is_nan_ff5)}})};
// synopsys translate_off
initial
man_round_carry = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_carry <= 1'b0;
else if (clk_en == 1'b1) man_round_carry <= man_round_carry_p0;
// synopsys translate_off
initial
man_round_carry_p0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_carry_p0 <= 1'b0;
else if (clk_en == 1'b1) man_round_carry_p0 <= round_carry;
// synopsys translate_off
initial
man_round_p = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p <= 53'b0;
else if (clk_en == 1'b1) man_round_p <= man_shift_full[53:1];
// synopsys translate_off
initial
man_round_p0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p0 <= 53'b0;
else if (clk_en == 1'b1) man_round_p0 <= man_round_p;
// synopsys translate_off
initial
man_round_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p1 <= 53'b0;
else if (clk_en == 1'b1) man_round_p1 <= man_round_p0;
// synopsys translate_off
initial
man_round_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p2 <= 54'b0;
else if (clk_en == 1'b1) man_round_p2 <= wire_man_round_adder_result;
// synopsys translate_off
initial
round_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_dffe <= 1'b0;
else if (clk_en == 1'b1) round_dffe <= round_bit;
// synopsys translate_off
initial
sign_node_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff0 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff0 <= (dataa[63] ^ datab[63]);
// synopsys translate_off
initial
sign_node_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff1 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff1 <= sign_node_ff0[0:0];
// synopsys translate_off
initial
sign_node_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff2 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff2 <= sign_node_ff1[0:0];
// synopsys translate_off
initial
sign_node_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff3 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff3 <= sign_node_ff2[0:0];
// synopsys translate_off
initial
sign_node_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff4 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff4 <= sign_node_ff3[0:0];
// synopsys translate_off
initial
sign_node_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff5 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff5 <= sign_node_ff4[0:0];
// synopsys translate_off
initial
sign_node_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff6 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff6 <= sign_node_ff5[0:0];
// synopsys translate_off
initial
sign_node_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff7 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff7 <= sign_node_ff6[0:0];
// synopsys translate_off
initial
sign_node_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff8 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff8 <= sign_node_ff7[0:0];
// synopsys translate_off
initial
sign_node_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff9 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff9 <= sign_node_ff8[0:0];
// synopsys translate_off
initial
sign_node_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff10 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff10 <= sign_node_ff9[0:0];
// synopsys translate_off
initial
sticky_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_dffe <= 1'b0;
else if (clk_en == 1'b1) sticky_dffe <= sticky_bit[51];
lpm_add_sub exp_add_adder
(
.aclr(aclr),
.cin(1'b0),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({1'b0, dataa[62:52]}),
.datab({1'b0, datab[62:52]}),
.overflow(),
.result(wire_exp_add_adder_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
exp_add_adder.lpm_pipeline = 1,
exp_add_adder.lpm_width = 12,
exp_add_adder.lpm_type = "lpm_add_sub";
lpm_add_sub exp_adj_adder
(
.cin(1'b0),
.cout(),
.dataa(exp_adj_p1),
.datab({expmod[12:0]}),
.overflow(),
.result(wire_exp_adj_adder_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
exp_adj_adder.lpm_pipeline = 0,
exp_adj_adder.lpm_width = 13,
exp_adj_adder.lpm_type = "lpm_add_sub";
lpm_add_sub exp_bias_subtr
(
.cout(),
.dataa({1'b0, exp_bias_p3}),
.datab({bias[12:0]}),
.overflow(),
.result(wire_exp_bias_subtr_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
exp_bias_subtr.lpm_direction = "SUB",
exp_bias_subtr.lpm_pipeline = 0,
exp_bias_subtr.lpm_representation = "UNSIGNED",
exp_bias_subtr.lpm_width = 13,
exp_bias_subtr.lpm_type = "lpm_add_sub";
lpm_add_sub man_round_adder
(
.cout(),
.dataa({1'b0, man_round_p1}),
.datab({53'b00000000000000000000000000000000000000000000000000000, man_round_carry}),
.overflow(),
.result(wire_man_round_adder_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
man_round_adder.lpm_pipeline = 0,
man_round_adder.lpm_width = 54,
man_round_adder.lpm_type = "lpm_add_sub";
lpm_mult man_product2_mult
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({1'b1, dataa[51:0]}),
.datab({1'b1, datab[51:0]}),
.result(wire_man_product2_mult_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
man_product2_mult.lpm_pipeline = 5,
man_product2_mult.lpm_representation = "UNSIGNED",
man_product2_mult.lpm_widtha = 53,
man_product2_mult.lpm_widthb = 53,
man_product2_mult.lpm_widthp = 106,
man_product2_mult.lpm_widths = 1,
man_product2_mult.lpm_type = "lpm_mult",
man_product2_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign
aclr = 1'b0,
bias = {{3{1'b0}}, {10{1'b1}}},
clk_en = 1'b1,
dataa_exp_all_one = {(dataa[62] & dataa_exp_all_one[9]), (dataa[61] & dataa_exp_all_one[8]), (dataa[60] & dataa_exp_all_one[7]), (dataa[59] & dataa_exp_all_one[6]), (dataa[58] & dataa_exp_all_one[5]), (dataa[57] & dataa_exp_all_one[4]), (dataa[56] & dataa_exp_all_one[3]), (dataa[55] & dataa_exp_all_one[2]), (dataa[54] & dataa_exp_all_one[1]), (dataa[53] & dataa_exp_all_one[0]), dataa[52]},
dataa_exp_not_zero = {(dataa[62] | dataa_exp_not_zero[9]), (dataa[61] | dataa_exp_not_zero[8]), (dataa[60] | dataa_exp_not_zero[7]), (dataa[59] | dataa_exp_not_zero[6]), (dataa[58] | dataa_exp_not_zero[5]), (dataa[57] | dataa_exp_not_zero[4]), (dataa[56] | dataa_exp_not_zero[3]), (dataa[55] | dataa_exp_not_zero[2]), (dataa[54] | dataa_exp_not_zero[1]), (dataa[53] | dataa_exp_not_zero[0]), dataa[52]},
dataa_man_not_zero = {(dataa[51] | dataa_man_not_zero[50]), (dataa[50] | dataa_man_not_zero[49]), (dataa[49] | dataa_man_not_zero[48]), (dataa[48] | dataa_man_not_zero[47]), (dataa[47] | dataa_man_not_zero[46]), (dataa[46] | dataa_man_not_zero[45]), (dataa[45] | dataa_man_not_zero[44]), (dataa[44] | dataa_man_not_zero[43]), (dataa[43] | dataa_man_not_zero[42]), (dataa[42] | dataa_man_not_zero[41]), (dataa[41] | dataa_man_not_zero[40]), (dataa[40] | dataa_man_not_zero[39]), (dataa[39] | dataa_man_not_zero[38]), (dataa[38] | dataa_man_not_zero[37]), (dataa[37] | dataa_man_not_zero[36]), (dataa[36] | dataa_man_not_zero[35]), (dataa[35] | dataa_man_not_zero[34]), (dataa[34] | dataa_man_not_zero[33]), (dataa[33] | dataa_man_not_zero[32]), (dataa[32] | dataa_man_not_zero[31]), (dataa[31] | dataa_man_not_zero[30]), (dataa[30] | dataa_man_not_zero[29]), (dataa[29] | dataa_man_not_zero[28]), (dataa[28] | dataa_man_not_zero[27]), (dataa[27] | dataa_man_not_zero[26]), dataa[26], (dataa[25] | dataa_man_not_zero[24]), (dataa[24] | dataa_man_not_zero[23]), (dataa[23] | dataa_man_not_zero[22]), (dataa[22] | dataa_man_not_zero[21]), (dataa[21] | dataa_man_not_zero[20]), (dataa[20] | dataa_man_not_zero[19]), (dataa[19] | dataa_man_not_zero[18]), (dataa[18] | dataa_man_not_zero[17]), (dataa[17] | dataa_man_not_zero[16]), (dataa[16] | dataa_man_not_zero[15]), (dataa[15] | dataa_man_not_zero[14]), (dataa[14] | dataa_man_not_zero[13]), (dataa[13] | dataa_man_not_zero[12]), (dataa[12] | dataa_man_not_zero[11]), (dataa[11] | dataa_man_not_zero[10]), (dataa[10] | dataa_man_not_zero[9]), (dataa[9] | dataa_man_not_zero[8]), (dataa[8] | dataa_man_not_zero[7]), (dataa[7] | dataa_man_not_zero[6]), (dataa[6] | dataa_man_not_zero[5]), (dataa[5] | dataa_man_not_zero[4]), (dataa[4] | dataa_man_not_zero[3]), (dataa[3] | dataa_man_not_zero[2]), (dataa[2] | dataa_man_not_zero[1]), (dataa[1] | dataa_man_not_zero[0]), dataa[0]},
datab_exp_all_one = {(datab[62] & datab_exp_all_one[9]), (datab[61] & datab_exp_all_one[8]), (datab[60] & datab_exp_all_one[7]), (datab[59] & datab_exp_all_one[6]), (datab[58] & datab_exp_all_one[5]), (datab[57] & datab_exp_all_one[4]), (datab[56] & datab_exp_all_one[3]), (datab[55] & datab_exp_all_one[2]), (datab[54] & datab_exp_all_one[1]), (datab[53] & datab_exp_all_one[0]), datab[52]},
datab_exp_not_zero = {(datab[62] | datab_exp_not_zero[9]), (datab[61] | datab_exp_not_zero[8]), (datab[60] | datab_exp_not_zero[7]), (datab[59] | datab_exp_not_zero[6]), (datab[58] | datab_exp_not_zero[5]), (datab[57] | datab_exp_not_zero[4]), (datab[56] | datab_exp_not_zero[3]), (datab[55] | datab_exp_not_zero[2]), (datab[54] | datab_exp_not_zero[1]), (datab[53] | datab_exp_not_zero[0]), datab[52]},
datab_man_not_zero = {(datab[51] | datab_man_not_zero[50]), (datab[50] | datab_man_not_zero[49]), (datab[49] | datab_man_not_zero[48]), (datab[48] | datab_man_not_zero[47]), (datab[47] | datab_man_not_zero[46]), (datab[46] | datab_man_not_zero[45]), (datab[45] | datab_man_not_zero[44]), (datab[44] | datab_man_not_zero[43]), (datab[43] | datab_man_not_zero[42]), (datab[42] | datab_man_not_zero[41]), (datab[41] | datab_man_not_zero[40]), (datab[40] | datab_man_not_zero[39]), (datab[39] | datab_man_not_zero[38]), (datab[38] | datab_man_not_zero[37]), (datab[37] | datab_man_not_zero[36]), (datab[36] | datab_man_not_zero[35]), (datab[35] | datab_man_not_zero[34]), (datab[34] | datab_man_not_zero[33]), (datab[33] | datab_man_not_zero[32]), (datab[32] | datab_man_not_zero[31]), (datab[31] | datab_man_not_zero[30]), (datab[30] | datab_man_not_zero[29]), (datab[29] | datab_man_not_zero[28]), (datab[28] | datab_man_not_zero[27]), (datab[27] | datab_man_not_zero[26]), datab[26], (datab[25] | datab_man_not_zero[24]), (datab[24] | datab_man_not_zero[23]), (datab[23] | datab_man_not_zero[22]), (datab[22] | datab_man_not_zero[21]), (datab[21] | datab_man_not_zero[20]), (datab[20] | datab_man_not_zero[19]), (datab[19] | datab_man_not_zero[18]), (datab[18] | datab_man_not_zero[17]), (datab[17] | datab_man_not_zero[16]), (datab[16] | datab_man_not_zero[15]), (datab[15] | datab_man_not_zero[14]), (datab[14] | datab_man_not_zero[13]), (datab[13] | datab_man_not_zero[12]), (datab[12] | datab_man_not_zero[11]), (datab[11] | datab_man_not_zero[10]), (datab[10] | datab_man_not_zero[9]), (datab[9] | datab_man_not_zero[8]), (datab[8] | datab_man_not_zero[7]), (datab[7] | datab_man_not_zero[6]), (datab[6] | datab_man_not_zero[5]), (datab[5] | datab_man_not_zero[4]), (datab[4] | datab_man_not_zero[3]), (datab[3] | datab_man_not_zero[2]), (datab[2] | datab_man_not_zero[1]), (datab[1] | datab_man_not_zero[0]), datab[0]},
exp_is_inf = (((~ exp_adj_p2[12]) & exp_adj_p2[11]) | ((~ exp_adj_p2[11]) & result_exp_all_one[10])),
exp_is_zero = (exp_adj_p2[12] | (~ result_exp_not_zero[11])),
expmod = {11'b00000000000, (delay_man_product_msb2 & man_round_p2[53]), (delay_man_product_msb2 ^ man_round_p2[53])},
inf_num = {11{1'b1}},
lsb_bit = man_shift_full[1],
man_shift_full = ((wire_man_product2_mult_result[104:51] & {54{(~ wire_man_product2_mult_result[105])}}) | (wire_man_product2_mult_result[105:52] & {54{wire_man_product2_mult_result[105]}})),
result = {sign_node_ff10[0:0], exp_result_ff[10:0], man_result_ff[51:0]},
result_exp_all_one = {(result_exp_all_one[9] & exp_adj_p2[10]), (result_exp_all_one[8] & exp_adj_p2[9]), (result_exp_all_one[7] & exp_adj_p2[8]), (result_exp_all_one[6] & exp_adj_p2[7]), (result_exp_all_one[5] & exp_adj_p2[6]), (result_exp_all_one[4] & exp_adj_p2[5]), (result_exp_all_one[3] & exp_adj_p2[4]), (result_exp_all_one[2] & exp_adj_p2[3]), (result_exp_all_one[1] & exp_adj_p2[2]), (result_exp_all_one[0] & exp_adj_p2[1]), exp_adj_p2[0]},
result_exp_not_zero = {(result_exp_not_zero[10] | exp_adj_p2[11]), (result_exp_not_zero[9] | exp_adj_p2[10]), (result_exp_not_zero[8] | exp_adj_p2[9]), (result_exp_not_zero[7] | exp_adj_p2[8]), (result_exp_not_zero[6] | exp_adj_p2[7]), (result_exp_not_zero[5] | exp_adj_p2[6]), (result_exp_not_zero[4] | exp_adj_p2[5]), (result_exp_not_zero[3] | exp_adj_p2[4]), (result_exp_not_zero[2] | exp_adj_p2[3]), (result_exp_not_zero[1] | exp_adj_p2[2]), (result_exp_not_zero[0] | exp_adj_p2[1]), exp_adj_p2[0]},
round_bit = man_shift_full[0],
round_carry = (round_dffe & (lsb_dffe | sticky_dffe)),
sticky_bit = {(sticky_bit[50] | (wire_man_product2_mult_result[105] & wire_man_product2_mult_result[51])), (sticky_bit[49] | wire_man_product2_mult_result[50]), (sticky_bit[48] | wire_man_product2_mult_result[49]), (sticky_bit[47] | wire_man_product2_mult_result[48]), (sticky_bit[46] | wire_man_product2_mult_result[47]), (sticky_bit[45] | wire_man_product2_mult_result[46]), (sticky_bit[44] | wire_man_product2_mult_result[45]), (sticky_bit[43] | wire_man_product2_mult_result[44]), (sticky_bit[42] | wire_man_product2_mult_result[43]), (sticky_bit[41] | wire_man_product2_mult_result[42]), (sticky_bit[40] | wire_man_product2_mult_result[41]), (sticky_bit[39] | wire_man_product2_mult_result[40]), (sticky_bit[38] | wire_man_product2_mult_result[39]), (sticky_bit[37] | wire_man_product2_mult_result[38]), (sticky_bit[36] | wire_man_product2_mult_result[37]), (sticky_bit[35] | wire_man_product2_mult_result[36]), (sticky_bit[34] | wire_man_product2_mult_result[35]), (sticky_bit[33] | wire_man_product2_mult_result[34]), (sticky_bit[32] | wire_man_product2_mult_result[33]), (sticky_bit[31] | wire_man_product2_mult_result[32]), (sticky_bit[30] | wire_man_product2_mult_result[31]), (sticky_bit[29] | wire_man_product2_mult_result[30]), (sticky_bit[28] | wire_man_product2_mult_result[29]), (sticky_bit[27] | wire_man_product2_mult_result[28]), (sticky_bit[26] | wire_man_product2_mult_result[27]), (sticky_bit[25] | wire_man_product2_mult_result[26]), (sticky_bit[24] | wire_man_product2_mult_result[25]), (sticky_bit[23] | wire_man_product2_mult_result[24]), (sticky_bit[22] | wire_man_product2_mult_result[23]), (sticky_bit[21] | wire_man_product2_mult_result[22]), (sticky_bit[20] | wire_man_product2_mult_result[21]), (sticky_bit[19] | wire_man_product2_mult_result[20]), (sticky_bit[18] | wire_man_product2_mult_result[19]), (sticky_bit[17] | wire_man_product2_mult_result[18]), (sticky_bit[16] | wire_man_product2_mult_result[17]), (sticky_bit[15] | wire_man_product2_mult_result[16]), (sticky_bit[14] | wire_man_product2_mult_result[15]
), (sticky_bit[13] | wire_man_product2_mult_result[14]), (sticky_bit[12] | wire_man_product2_mult_result[13]), (sticky_bit[11] | wire_man_product2_mult_result[12]), (sticky_bit[10] | wire_man_product2_mult_result[11]), (sticky_bit[9] | wire_man_product2_mult_result[10]), (sticky_bit[8] | wire_man_product2_mult_result[9]), (sticky_bit[7] | wire_man_product2_mult_result[8]), (sticky_bit[6] | wire_man_product2_mult_result[7]), (sticky_bit[5] | wire_man_product2_mult_result[6]), (sticky_bit[4] | wire_man_product2_mult_result[5]), (sticky_bit[3] | wire_man_product2_mult_result[4]), (sticky_bit[2] | wire_man_product2_mult_result[3]), (sticky_bit[1] | wire_man_product2_mult_result[2]), (sticky_bit[0] | wire_man_product2_mult_result[1]), wire_man_product2_mult_result[0]};
endmodule //fp_mult_v1_altfp_mult_ogj
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fp_mult_v1 (
clock,
dataa,
datab,
result);
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
fp_mult_v1_altfp_mult_ogj fp_mult_v1_altfp_mult_ogj_component (
.dataa (dataa),
.datab (datab),
.clock (clock),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT STRING "Double"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
// Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_mult"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "11"
// Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: dataa 0 0 64 0 INPUT NODEFVAL dataa[63..0]
// Retrieval info: USED_PORT: datab 0 0 64 0 INPUT NODEFVAL datab[63..0]
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL result[63..0]
// Retrieval info: CONNECT: @dataa 0 0 64 0 dataa 0 0 64 0
// Retrieval info: CONNECT: @datab 0 0 64 0 datab 0 0 64 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_mult_v1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_mult_v1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_mult_v1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_mult_v1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_mult_v1_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_mult_v1_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/08 19:17:16
// Design Name:
// Module Name: timing_signal_generator
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
* top module
* @parameter clr_n
*/
module timing_signal_generator
#(parameter CYCLE = 5, LEN = 4)
(
input clr_n,
input on,
input off,
input [3:0] power,
output [(LEN-1):0] T
);
// power[1]: Hz select
// power[0]: on/off
wire [(LEN-1):0] clk_group, Tp;
clock_generator #(.CYCLE(CYCLE), .LEN(LEN)) CLK (
.clk(clk_group));
timing_signal #(.LEN(LEN)) SIG (
.clk(clk_group[power[3:1]]&power[0]),
.clr_n(clr_n),
.Tp(Tp));
control_unit #(.LEN(LEN)) UNIT (
.on(on),
.off(off),
.clr_n(clr_n),
.Tp(Tp),
.T(T));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:08:40 11/19/2015
// Design Name:
// Module Name: EX_MEM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module EX_MEM(
input clock,
input reset,
input debugEnable,
input debugReset,
input[4:0] writeRegister,
input[31:0] writeData,
input[31:0] aluOut,
input regWrite,
input memToReg,
input [3:0]memWrite,
input [1:0] memReadWidth,
input eop,
output reg[4:0] writeRegisterOut,
output reg[31:0] writeDataOut,
output reg[31:0] aluOutOut,
output reg regWriteOut,
output reg memToRegOut,
output reg [3:0]memWriteOut,
output reg [1:0] memReadWidthOut,
output reg eopOut
);
always @(negedge clock,posedge reset)begin
if(reset)begin
writeRegisterOut<=0;
writeDataOut<=0;
aluOutOut<=0;
regWriteOut<=0;
memToRegOut<=0;
memWriteOut<=0;
memReadWidthOut<=0;
eopOut<=0;
end
else if(debugReset)begin
writeRegisterOut<=0;
writeDataOut<=0;
aluOutOut<=0;
regWriteOut<=0;
memToRegOut<=0;
memWriteOut<=0;
memReadWidthOut<=0;
eopOut<=0;
end
else if(debugEnable) begin
writeRegisterOut<=writeRegister;
writeDataOut<=writeData;
aluOutOut<=aluOut;
regWriteOut<=regWrite;
memToRegOut<=memToReg;
memWriteOut<=memWrite;
memReadWidthOut<=memReadWidth;
eopOut<=eop;
end
end
endmodule
|
// megafunction wizard: %ALTFP_EXP%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_EXP
// ============================================================
// File Name: fp_exp.v
// Megafunction Name(s):
// ALTFP_EXP
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_exp CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" PIPELINE=17 ROUNDING="TO_NEAREST" WIDTH_EXP=8 WIDTH_MAN=23 clock data result
//VERSION_BEGIN 13.1 cbx_altfp_exp 2013:10:23:18:05:48:SJ cbx_altmult_opt 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_clshift 2013:10:23:18:05:48:SJ cbx_lpm_compare 2013:10:23:18:05:48:SJ cbx_lpm_mult 2013:10:23:18:05:48:SJ cbx_lpm_mux 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_padd 2013:10:23:18:05:48:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ cbx_util_mgl 2013:10:23:18:05:48:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_add_sub 9 lpm_clshift 1 lpm_compare 3 lpm_mult 5 lpm_mux 3 mux21 124 reg 745
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_exp_altfp_exp_5fc
(
clock,
data,
result) ;
input clock;
input [31:0] data;
output [31:0] result;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes0;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes1;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes2;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes3;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes4;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes5;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes6;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes7;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes8;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes9;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes10;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes11;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes12;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes13;
reg [0:0] barrel_shifter_underflow_dffe2_15_pipes14;
reg [0:0] distance_overflow_dffe2_15_pipes0;
reg [0:0] distance_overflow_dffe2_15_pipes1;
reg [0:0] distance_overflow_dffe2_15_pipes2;
reg [0:0] distance_overflow_dffe2_15_pipes3;
reg [0:0] distance_overflow_dffe2_15_pipes4;
reg [0:0] distance_overflow_dffe2_15_pipes5;
reg [0:0] distance_overflow_dffe2_15_pipes6;
reg [0:0] distance_overflow_dffe2_15_pipes7;
reg [0:0] distance_overflow_dffe2_15_pipes8;
reg [0:0] distance_overflow_dffe2_15_pipes9;
reg [0:0] distance_overflow_dffe2_15_pipes10;
reg [0:0] distance_overflow_dffe2_15_pipes11;
reg [0:0] distance_overflow_dffe2_15_pipes12;
reg [0:0] distance_overflow_dffe2_15_pipes13;
reg [0:0] distance_overflow_dffe2_15_pipes14;
reg [7:0] exp_value_b4_bias_dffe_0;
reg [7:0] exp_value_b4_bias_dffe_1;
reg [7:0] exp_value_b4_bias_dffe_10;
reg [7:0] exp_value_b4_bias_dffe_2;
reg [7:0] exp_value_b4_bias_dffe_3;
reg [7:0] exp_value_b4_bias_dffe_4;
reg [7:0] exp_value_b4_bias_dffe_5;
reg [7:0] exp_value_b4_bias_dffe_6;
reg [7:0] exp_value_b4_bias_dffe_7;
reg [7:0] exp_value_b4_bias_dffe_8;
reg [7:0] exp_value_b4_bias_dffe_9;
reg [8:0] exp_value_dffe1;
reg extra_ln2_dffe_0;
reg extra_ln2_dffe_1;
reg extra_ln2_dffe_2;
reg extra_ln2_dffe_3;
reg extra_ln2_dffe_4;
reg extra_ln2_dffe_5;
reg [22:0] fraction_dffe1;
reg [0:0] input_is_infinity_16_pipes0;
reg [0:0] input_is_infinity_16_pipes1;
reg [0:0] input_is_infinity_16_pipes2;
reg [0:0] input_is_infinity_16_pipes3;
reg [0:0] input_is_infinity_16_pipes4;
reg [0:0] input_is_infinity_16_pipes5;
reg [0:0] input_is_infinity_16_pipes6;
reg [0:0] input_is_infinity_16_pipes7;
reg [0:0] input_is_infinity_16_pipes8;
reg [0:0] input_is_infinity_16_pipes9;
reg [0:0] input_is_infinity_16_pipes10;
reg [0:0] input_is_infinity_16_pipes11;
reg [0:0] input_is_infinity_16_pipes12;
reg [0:0] input_is_infinity_16_pipes13;
reg [0:0] input_is_infinity_16_pipes14;
reg [0:0] input_is_infinity_16_pipes15;
reg [0:0] input_is_nan_16_pipes0;
reg [0:0] input_is_nan_16_pipes1;
reg [0:0] input_is_nan_16_pipes2;
reg [0:0] input_is_nan_16_pipes3;
reg [0:0] input_is_nan_16_pipes4;
reg [0:0] input_is_nan_16_pipes5;
reg [0:0] input_is_nan_16_pipes6;
reg [0:0] input_is_nan_16_pipes7;
reg [0:0] input_is_nan_16_pipes8;
reg [0:0] input_is_nan_16_pipes9;
reg [0:0] input_is_nan_16_pipes10;
reg [0:0] input_is_nan_16_pipes11;
reg [0:0] input_is_nan_16_pipes12;
reg [0:0] input_is_nan_16_pipes13;
reg [0:0] input_is_nan_16_pipes14;
reg [0:0] input_is_nan_16_pipes15;
reg [0:0] input_is_zero_16_pipes0;
reg [0:0] input_is_zero_16_pipes1;
reg [0:0] input_is_zero_16_pipes2;
reg [0:0] input_is_zero_16_pipes3;
reg [0:0] input_is_zero_16_pipes4;
reg [0:0] input_is_zero_16_pipes5;
reg [0:0] input_is_zero_16_pipes6;
reg [0:0] input_is_zero_16_pipes7;
reg [0:0] input_is_zero_16_pipes8;
reg [0:0] input_is_zero_16_pipes9;
reg [0:0] input_is_zero_16_pipes10;
reg [0:0] input_is_zero_16_pipes11;
reg [0:0] input_is_zero_16_pipes12;
reg [0:0] input_is_zero_16_pipes13;
reg [0:0] input_is_zero_16_pipes14;
reg [0:0] input_is_zero_16_pipes15;
reg man_overflow_dffe15;
reg [61:0] man_prod_dffe14;
reg [22:0] man_round_dffe15;
reg [30:0] result_pipe_dffe16;
reg round_up_dffe15;
reg [0:0] sign_dffe0;
reg [0:0] sign_dffe1;
reg [0:0] sign_dffe2;
reg [0:0] sign_dffe3;
reg [0:0] sign_dffe4;
reg [0:0] sign_dffe5;
reg [0:0] sign_dffe6;
reg [0:0] sign_dffe7;
reg [0:0] sign_dffe8;
reg [0:0] sign_dffe9;
reg [0:0] sign_dffe10;
reg [0:0] sign_dffe11;
reg [0:0] sign_dffe12;
reg [0:0] sign_dffe13;
reg [0:0] sign_dffe14;
reg [0:0] sign_dffe15;
reg [0:0] tbl1_compare_dffe11_4_pipes0;
reg [0:0] tbl1_compare_dffe11_4_pipes1;
reg [0:0] tbl1_compare_dffe11_4_pipes2;
reg [0:0] tbl1_compare_dffe11_4_pipes3;
reg [30:0] tbl1_tbl2_prod_dffe12;
reg [30:0] tbl3_taylor_prod_dffe12;
reg [37:0] x_fixed_dffe_0;
reg [37:0] x_fixed_dffe_1;
reg [37:0] x_fixed_dffe_2;
reg [37:0] x_fixed_dffe_3;
reg [37:0] x_fixed_dffe_4;
reg [37:0] xf_pre_2_dffe10;
reg [37:0] xf_pre_dffe9;
reg [7:0] xi_exp_value_dffe4;
reg [45:0] xi_ln2_prod_dffe7;
reg [20:0] xi_prod_dffe3;
wire [8:0] wire_exp_minus_bias_result;
wire [8:0] wire_exp_value_add_bias_result;
wire [8:0] wire_exp_value_man_over_result;
wire [7:0] wire_invert_exp_value_result;
wire [22:0] wire_man_round_result;
wire [30:0] wire_one_minus_xf_result;
wire [37:0] wire_x_fixed_minus_xiln2_result;
wire [30:0] wire_xf_minus_ln2_result;
wire [7:0] wire_xi_add_one_result;
wire [37:0] wire_rbarrel_shift_result;
wire wire_distance_overflow_comp_agb;
wire wire_tbl1_compare_ageb;
wire wire_underflow_compare_agb;
wire [61:0] wire_man_prod_result;
wire [63:0] wire_tbl1_tbl2_prod_result;
wire [61:0] wire_tbl3_taylor_prod_result;
wire [45:0] wire_xi_ln2_prod_result;
wire [20:0] wire_xi_prod_result;
wire [31:0] wire_table_one_result;
wire [20:0] wire_table_three_result;
wire [25:0] wire_table_two_result;
wire wire_cin_to_bias_dataout;
wire [7:0]wire_exp_result_mux_prea_dataout;
wire [7:0]wire_exp_value_b4_biasa_dataout;
wire [5:0]wire_exp_value_selecta_dataout;
wire [7:0]wire_exp_value_to_compare_muxa_dataout;
wire [7:0]wire_exp_value_to_ln2a_dataout;
wire [30:0]wire_extra_ln2_muxa_dataout;
wire [22:0]wire_man_result_muxa_dataout;
wire [30:0]wire_xf_muxa_dataout;
wire aclr;
wire [4:0] addr_val_more_than_one;
wire [37:0] barrel_shifter_data;
wire [5:0] barrel_shifter_distance;
wire barrel_shifter_underflow;
wire barrel_shifter_underflow_wi;
wire clk_en;
wire distance_overflow;
wire [7:0] distance_overflow_val_w;
wire distance_overflow_wi;
wire [7:0] exp_bias;
wire [7:0] exp_bias_all_ones_w;
wire [7:0] exp_data_all_one_w;
wire [7:0] exp_data_not_zero_w;
wire [7:0] exp_invert;
wire [7:0] exp_one;
wire [7:0] exp_out_all_one_w;
wire [7:0] exp_out_not_zero_w;
wire [7:0] exp_result_out;
wire [7:0] exp_result_w;
wire [8:0] exp_value;
wire [8:0] exp_value_wi;
wire [8:0] exp_value_wo;
wire [7:0] exp_w;
wire extra_ln2;
wire [22:0] fraction;
wire [22:0] fraction_wi;
wire [22:0] fraction_wo;
wire gnd_w;
wire guard_bit;
wire input_is_infinity_wi;
wire input_is_infinity_wo;
wire input_is_nan_wi;
wire input_is_nan_wo;
wire input_is_zero_wi;
wire input_is_zero_wo;
wire [37:0] ln2_w;
wire [22:0] man_data_not_zero_w;
wire man_overflow;
wire man_overflow_wi;
wire man_overflow_wo;
wire [61:0] man_prod_result;
wire [61:0] man_prod_shifted;
wire [61:0] man_prod_wi;
wire [61:0] man_prod_wire;
wire [61:0] man_prod_wo;
wire [22:0] man_result_all_ones;
wire [22:0] man_result_w;
wire [22:0] man_round_wi;
wire [22:0] man_round_wo;
wire nan_w;
wire negative_infinity;
wire [8:0] one_over_ln2_w;
wire overflow_w;
wire positive_infinity;
wire [30:0] result_pipe_wi;
wire [30:0] result_pipe_wo;
wire result_underflow_w;
wire round_bit;
wire round_up;
wire round_up_wi;
wire round_up_wo;
wire shifted_value;
wire sign_w;
wire [4:0] sticky_bits;
wire [1023:0] table_one_data;
wire [31:0] table_one_out;
wire [671:0] table_three_data;
wire [31:0] table_three_out;
wire [20:0] table_three_out_tmp;
wire [831:0] table_two_data;
wire [31:0] table_two_out;
wire [25:0] table_two_out_tmp;
wire tbl1_compare_wi;
wire tbl1_compare_wo;
wire [30:0] tbl1_tbl2_prod_wi;
wire [30:0] tbl1_tbl2_prod_wo;
wire [30:0] tbl3_taylor_prod_wi;
wire [30:0] tbl3_taylor_prod_wo;
wire [7:0] underflow_compare_val_w;
wire underflow_w;
wire [37:0] x_fixed;
wire [30:0] xf;
wire [37:0] xf_pre;
wire [37:0] xf_pre_2_wi;
wire [37:0] xf_pre_2_wo;
wire [37:0] xf_pre_wi;
wire [37:0] xf_pre_wo;
wire [7:0] xi_exp_value;
wire [7:0] xi_exp_value_wi;
wire [7:0] xi_exp_value_wo;
wire [45:0] xi_ln2_prod_wi;
wire [45:0] xi_ln2_prod_wo;
wire [20:0] xi_prod_wi;
wire [20:0] xi_prod_wo;
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes0 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes0 <= barrel_shifter_underflow_wi;
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes1 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes1 <= barrel_shifter_underflow_dffe2_15_pipes0[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes2 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes2 <= barrel_shifter_underflow_dffe2_15_pipes1[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes3 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes3 <= barrel_shifter_underflow_dffe2_15_pipes2[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes4 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes4 <= barrel_shifter_underflow_dffe2_15_pipes3[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes5 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes5 <= barrel_shifter_underflow_dffe2_15_pipes4[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes6 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes6 <= barrel_shifter_underflow_dffe2_15_pipes5[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes7 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes7 <= barrel_shifter_underflow_dffe2_15_pipes6[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes8 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes8 <= barrel_shifter_underflow_dffe2_15_pipes7[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes9 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes9 <= barrel_shifter_underflow_dffe2_15_pipes8[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes10 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes10 <= barrel_shifter_underflow_dffe2_15_pipes9[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes11 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes11 <= barrel_shifter_underflow_dffe2_15_pipes10[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes12 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes12 <= barrel_shifter_underflow_dffe2_15_pipes11[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes13 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes13 <= barrel_shifter_underflow_dffe2_15_pipes12[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_15_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_15_pipes14 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_15_pipes14 <= barrel_shifter_underflow_dffe2_15_pipes13[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes0 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes0 <= distance_overflow_wi;
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes1 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes1 <= distance_overflow_dffe2_15_pipes0[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes2 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes2 <= distance_overflow_dffe2_15_pipes1[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes3 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes3 <= distance_overflow_dffe2_15_pipes2[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes4 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes4 <= distance_overflow_dffe2_15_pipes3[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes5 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes5 <= distance_overflow_dffe2_15_pipes4[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes6 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes6 <= distance_overflow_dffe2_15_pipes5[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes7 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes7 <= distance_overflow_dffe2_15_pipes6[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes8 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes8 <= distance_overflow_dffe2_15_pipes7[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes9 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes9 <= distance_overflow_dffe2_15_pipes8[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes10 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes10 <= distance_overflow_dffe2_15_pipes9[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes11 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes11 <= distance_overflow_dffe2_15_pipes10[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes12 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes12 <= distance_overflow_dffe2_15_pipes11[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes13 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes13 <= distance_overflow_dffe2_15_pipes12[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_15_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_15_pipes14 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_15_pipes14 <= distance_overflow_dffe2_15_pipes13[0:0];
// synopsys translate_off
initial
exp_value_b4_bias_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_0 <= 8'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_0 <= wire_exp_value_b4_biasa_dataout;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_1 <= 8'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_1 <= exp_value_b4_bias_dffe_0;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_10 <= 8'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_10 <= exp_value_b4_bias_dffe_9;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_2 <= 8'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_2 <= exp_value_b4_bias_dffe_1;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_3 <= 8'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_3 <= exp_value_b4_bias_dffe_2;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_4 <= 8'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_4 <= exp_value_b4_bias_dffe_3;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_5 <= 8'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_5 <= exp_value_b4_bias_dffe_4;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_6 <= 8'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_6 <= exp_value_b4_bias_dffe_5;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_7 <= 8'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_7 <= exp_value_b4_bias_dffe_6;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_8 <= 8'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_8 <= exp_value_b4_bias_dffe_7;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_9 <= 8'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_9 <= exp_value_b4_bias_dffe_8;
// synopsys translate_off
initial
exp_value_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_dffe1 <= 9'b0;
else if (clk_en == 1'b1) exp_value_dffe1 <= exp_value_wi;
// synopsys translate_off
initial
extra_ln2_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_0 <= extra_ln2;
// synopsys translate_off
initial
extra_ln2_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_1 <= extra_ln2_dffe_0;
// synopsys translate_off
initial
extra_ln2_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_2 <= extra_ln2_dffe_1;
// synopsys translate_off
initial
extra_ln2_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_3 <= extra_ln2_dffe_2;
// synopsys translate_off
initial
extra_ln2_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_4 <= extra_ln2_dffe_3;
// synopsys translate_off
initial
extra_ln2_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_5 <= extra_ln2_dffe_4;
// synopsys translate_off
initial
fraction_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) fraction_dffe1 <= 23'b0;
else if (clk_en == 1'b1) fraction_dffe1 <= fraction_wi;
// synopsys translate_off
initial
input_is_infinity_16_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes0 <= input_is_infinity_wi;
// synopsys translate_off
initial
input_is_infinity_16_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes1 <= input_is_infinity_16_pipes0[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes2 <= input_is_infinity_16_pipes1[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes3 <= input_is_infinity_16_pipes2[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes4 <= input_is_infinity_16_pipes3[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes5 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes5 <= input_is_infinity_16_pipes4[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes6 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes6 <= input_is_infinity_16_pipes5[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes7 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes7 <= input_is_infinity_16_pipes6[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes8 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes8 <= input_is_infinity_16_pipes7[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes9 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes9 <= input_is_infinity_16_pipes8[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes10 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes10 <= input_is_infinity_16_pipes9[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes11 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes11 <= input_is_infinity_16_pipes10[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes12 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes12 <= input_is_infinity_16_pipes11[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes13 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes13 <= input_is_infinity_16_pipes12[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes14 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes14 <= input_is_infinity_16_pipes13[0:0];
// synopsys translate_off
initial
input_is_infinity_16_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_16_pipes15 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_16_pipes15 <= input_is_infinity_16_pipes14[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes0 <= input_is_nan_wi;
// synopsys translate_off
initial
input_is_nan_16_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes1 <= input_is_nan_16_pipes0[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes2 <= input_is_nan_16_pipes1[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes3 <= input_is_nan_16_pipes2[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes4 <= input_is_nan_16_pipes3[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes5 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes5 <= input_is_nan_16_pipes4[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes6 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes6 <= input_is_nan_16_pipes5[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes7 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes7 <= input_is_nan_16_pipes6[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes8 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes8 <= input_is_nan_16_pipes7[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes9 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes9 <= input_is_nan_16_pipes8[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes10 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes10 <= input_is_nan_16_pipes9[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes11 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes11 <= input_is_nan_16_pipes10[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes12 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes12 <= input_is_nan_16_pipes11[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes13 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes13 <= input_is_nan_16_pipes12[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes14 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes14 <= input_is_nan_16_pipes13[0:0];
// synopsys translate_off
initial
input_is_nan_16_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_16_pipes15 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_16_pipes15 <= input_is_nan_16_pipes14[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes0 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes0 <= input_is_zero_wi;
// synopsys translate_off
initial
input_is_zero_16_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes1 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes1 <= input_is_zero_16_pipes0[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes2 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes2 <= input_is_zero_16_pipes1[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes3 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes3 <= input_is_zero_16_pipes2[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes4 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes4 <= input_is_zero_16_pipes3[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes5 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes5 <= input_is_zero_16_pipes4[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes6 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes6 <= input_is_zero_16_pipes5[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes7 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes7 <= input_is_zero_16_pipes6[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes8 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes8 <= input_is_zero_16_pipes7[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes9 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes9 <= input_is_zero_16_pipes8[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes10 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes10 <= input_is_zero_16_pipes9[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes11 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes11 <= input_is_zero_16_pipes10[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes12 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes12 <= input_is_zero_16_pipes11[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes13 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes13 <= input_is_zero_16_pipes12[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes14 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes14 <= input_is_zero_16_pipes13[0:0];
// synopsys translate_off
initial
input_is_zero_16_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_16_pipes15 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_16_pipes15 <= input_is_zero_16_pipes14[0:0];
// synopsys translate_off
initial
man_overflow_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_overflow_dffe15 <= 1'b0;
else if (clk_en == 1'b1) man_overflow_dffe15 <= man_overflow_wi;
// synopsys translate_off
initial
man_prod_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_prod_dffe14 <= 62'b0;
else if (clk_en == 1'b1) man_prod_dffe14 <= man_prod_wi;
// synopsys translate_off
initial
man_round_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_dffe15 <= 23'b0;
else if (clk_en == 1'b1) man_round_dffe15 <= man_round_wi;
// synopsys translate_off
initial
result_pipe_dffe16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_pipe_dffe16 <= 31'b0;
else if (clk_en == 1'b1) result_pipe_dffe16 <= result_pipe_wi;
// synopsys translate_off
initial
round_up_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_up_dffe15 <= 1'b0;
else if (clk_en == 1'b1) round_up_dffe15 <= round_up_wi;
// synopsys translate_off
initial
sign_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe0 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe0 <= sign_w;
// synopsys translate_off
initial
sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe1 <= sign_dffe0[0:0];
// synopsys translate_off
initial
sign_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe2 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe2 <= sign_dffe1[0:0];
// synopsys translate_off
initial
sign_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe3 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe3 <= sign_dffe2[0:0];
// synopsys translate_off
initial
sign_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe4 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe4 <= sign_dffe3[0:0];
// synopsys translate_off
initial
sign_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe5 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe5 <= sign_dffe4[0:0];
// synopsys translate_off
initial
sign_dffe6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe6 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe6 <= sign_dffe5[0:0];
// synopsys translate_off
initial
sign_dffe7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe7 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe7 <= sign_dffe6[0:0];
// synopsys translate_off
initial
sign_dffe8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe8 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe8 <= sign_dffe7[0:0];
// synopsys translate_off
initial
sign_dffe9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe9 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe9 <= sign_dffe8[0:0];
// synopsys translate_off
initial
sign_dffe10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe10 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe10 <= sign_dffe9[0:0];
// synopsys translate_off
initial
sign_dffe11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe11 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe11 <= sign_dffe10[0:0];
// synopsys translate_off
initial
sign_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe12 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe12 <= sign_dffe11[0:0];
// synopsys translate_off
initial
sign_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe13 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe13 <= sign_dffe12[0:0];
// synopsys translate_off
initial
sign_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe14 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe14 <= sign_dffe13[0:0];
// synopsys translate_off
initial
sign_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe15 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe15 <= sign_dffe14[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_4_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_4_pipes0 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_4_pipes0 <= tbl1_compare_wi;
// synopsys translate_off
initial
tbl1_compare_dffe11_4_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_4_pipes1 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_4_pipes1 <= tbl1_compare_dffe11_4_pipes0[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_4_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_4_pipes2 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_4_pipes2 <= tbl1_compare_dffe11_4_pipes1[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_4_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_4_pipes3 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_4_pipes3 <= tbl1_compare_dffe11_4_pipes2[0:0];
// synopsys translate_off
initial
tbl1_tbl2_prod_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_tbl2_prod_dffe12 <= 31'b0;
else if (clk_en == 1'b1) tbl1_tbl2_prod_dffe12 <= tbl1_tbl2_prod_wi;
// synopsys translate_off
initial
tbl3_taylor_prod_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl3_taylor_prod_dffe12 <= 31'b0;
else if (clk_en == 1'b1) tbl3_taylor_prod_dffe12 <= tbl3_taylor_prod_wi;
// synopsys translate_off
initial
x_fixed_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_0 <= 38'b0;
else if (clk_en == 1'b1) x_fixed_dffe_0 <= x_fixed;
// synopsys translate_off
initial
x_fixed_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_1 <= 38'b0;
else if (clk_en == 1'b1) x_fixed_dffe_1 <= x_fixed_dffe_0;
// synopsys translate_off
initial
x_fixed_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_2 <= 38'b0;
else if (clk_en == 1'b1) x_fixed_dffe_2 <= x_fixed_dffe_1;
// synopsys translate_off
initial
x_fixed_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_3 <= 38'b0;
else if (clk_en == 1'b1) x_fixed_dffe_3 <= x_fixed_dffe_2;
// synopsys translate_off
initial
x_fixed_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_4 <= 38'b0;
else if (clk_en == 1'b1) x_fixed_dffe_4 <= x_fixed_dffe_3;
// synopsys translate_off
initial
xf_pre_2_dffe10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xf_pre_2_dffe10 <= 38'b0;
else if (clk_en == 1'b1) xf_pre_2_dffe10 <= xf_pre_2_wi;
// synopsys translate_off
initial
xf_pre_dffe9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xf_pre_dffe9 <= 38'b0;
else if (clk_en == 1'b1) xf_pre_dffe9 <= xf_pre_wi;
// synopsys translate_off
initial
xi_exp_value_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xi_exp_value_dffe4 <= 8'b0;
else if (clk_en == 1'b1) xi_exp_value_dffe4 <= xi_exp_value_wi;
// synopsys translate_off
initial
xi_ln2_prod_dffe7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xi_ln2_prod_dffe7 <= 46'b0;
else if (clk_en == 1'b1) xi_ln2_prod_dffe7 <= xi_ln2_prod_wi;
// synopsys translate_off
initial
xi_prod_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xi_prod_dffe3 <= 21'b0;
else if (clk_en == 1'b1) xi_prod_dffe3 <= xi_prod_wi;
lpm_add_sub exp_minus_bias
(
.cout(),
.dataa({1'b0, exp_w}),
.datab({1'b0, exp_bias}),
.overflow(),
.result(wire_exp_minus_bias_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_minus_bias.lpm_direction = "SUB",
exp_minus_bias.lpm_representation = "SIGNED",
exp_minus_bias.lpm_width = 9,
exp_minus_bias.lpm_type = "lpm_add_sub";
lpm_add_sub exp_value_add_bias
(
.aclr(aclr),
.cin(wire_cin_to_bias_dataout),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({1'b0, exp_value_b4_bias_dffe_10}),
.datab({1'b0, exp_bias[7:1], (~ extra_ln2_dffe_5)}),
.overflow(),
.result(wire_exp_value_add_bias_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_value_add_bias.lpm_direction = "ADD",
exp_value_add_bias.lpm_pipeline = 1,
exp_value_add_bias.lpm_representation = "SIGNED",
exp_value_add_bias.lpm_width = 9,
exp_value_add_bias.lpm_type = "lpm_add_sub";
lpm_add_sub exp_value_man_over
(
.cout(),
.dataa(wire_exp_value_add_bias_result),
.datab({{8{1'b0}}, man_overflow_wo}),
.overflow(),
.result(wire_exp_value_man_over_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_value_man_over.lpm_direction = "ADD",
exp_value_man_over.lpm_representation = "SIGNED",
exp_value_man_over.lpm_width = 9,
exp_value_man_over.lpm_type = "lpm_add_sub";
lpm_add_sub invert_exp_value
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({8{1'b0}}),
.datab(exp_value[7:0]),
.overflow(),
.result(wire_invert_exp_value_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
invert_exp_value.lpm_direction = "SUB",
invert_exp_value.lpm_pipeline = 1,
invert_exp_value.lpm_representation = "SIGNED",
invert_exp_value.lpm_width = 8,
invert_exp_value.lpm_type = "lpm_add_sub";
lpm_add_sub man_round
(
.cout(),
.dataa(man_round_wo),
.datab({{22{1'b0}}, round_up_wo}),
.overflow(),
.result(wire_man_round_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_round.lpm_direction = "ADD",
man_round.lpm_representation = "SIGNED",
man_round.lpm_width = 23,
man_round.lpm_type = "lpm_add_sub";
lpm_add_sub one_minus_xf
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({1'b1, {30{1'b0}}}),
.datab(wire_extra_ln2_muxa_dataout),
.overflow(),
.result(wire_one_minus_xf_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
one_minus_xf.lpm_direction = "SUB",
one_minus_xf.lpm_pipeline = 1,
one_minus_xf.lpm_representation = "SIGNED",
one_minus_xf.lpm_width = 31,
one_minus_xf.lpm_type = "lpm_add_sub";
lpm_add_sub x_fixed_minus_xiln2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(x_fixed_dffe_4),
.datab({1'b0, xi_ln2_prod_wo[45:9]}),
.overflow(),
.result(wire_x_fixed_minus_xiln2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_fixed_minus_xiln2.lpm_direction = "SUB",
x_fixed_minus_xiln2.lpm_pipeline = 1,
x_fixed_minus_xiln2.lpm_representation = "SIGNED",
x_fixed_minus_xiln2.lpm_width = 38,
x_fixed_minus_xiln2.lpm_type = "lpm_add_sub";
lpm_add_sub xf_minus_ln2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(xf_pre[30:0]),
.datab({{2{1'b0}}, ln2_w[37:9]}),
.overflow(),
.result(wire_xf_minus_ln2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
xf_minus_ln2.lpm_direction = "SUB",
xf_minus_ln2.lpm_pipeline = 1,
xf_minus_ln2.lpm_representation = "SIGNED",
xf_minus_ln2.lpm_width = 31,
xf_minus_ln2.lpm_type = "lpm_add_sub";
lpm_add_sub xi_add_one
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(xi_exp_value),
.datab(8'b00000001),
.overflow(),
.result(wire_xi_add_one_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
xi_add_one.lpm_direction = "ADD",
xi_add_one.lpm_pipeline = 1,
xi_add_one.lpm_representation = "SIGNED",
xi_add_one.lpm_width = 8,
xi_add_one.lpm_type = "lpm_add_sub";
lpm_clshift rbarrel_shift
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(barrel_shifter_data),
.direction(exp_value_wo[8]),
.distance(barrel_shifter_distance),
.overflow(),
.result(wire_rbarrel_shift_result),
.underflow());
defparam
rbarrel_shift.lpm_pipeline = 2,
rbarrel_shift.lpm_shifttype = "LOGICAL",
rbarrel_shift.lpm_width = 38,
rbarrel_shift.lpm_widthdist = 6,
rbarrel_shift.lpm_type = "lpm_clshift";
lpm_compare distance_overflow_comp
(
.aeb(),
.agb(wire_distance_overflow_comp_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(wire_exp_value_to_compare_muxa_dataout),
.datab(distance_overflow_val_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
distance_overflow_comp.lpm_representation = "UNSIGNED",
distance_overflow_comp.lpm_width = 8,
distance_overflow_comp.lpm_type = "lpm_compare";
lpm_compare tbl1_compare
(
.aeb(),
.agb(),
.ageb(wire_tbl1_compare_ageb),
.alb(),
.aleb(),
.aneb(),
.dataa(xf[28:24]),
.datab(addr_val_more_than_one)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
tbl1_compare.lpm_representation = "UNSIGNED",
tbl1_compare.lpm_width = 5,
tbl1_compare.lpm_type = "lpm_compare";
lpm_compare underflow_compare
(
.aeb(),
.agb(wire_underflow_compare_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(wire_exp_value_to_compare_muxa_dataout),
.datab(underflow_compare_val_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
underflow_compare.lpm_representation = "UNSIGNED",
underflow_compare.lpm_width = 8,
underflow_compare.lpm_type = "lpm_compare";
lpm_mult man_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(tbl1_tbl2_prod_wo),
.datab(tbl3_taylor_prod_wo),
.result(wire_man_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_prod.lpm_pipeline = 1,
man_prod.lpm_representation = "UNSIGNED",
man_prod.lpm_widtha = 31,
man_prod.lpm_widthb = 31,
man_prod.lpm_widthp = 62,
man_prod.lpm_type = "lpm_mult",
man_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult tbl1_tbl2_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(table_one_out),
.datab(table_two_out),
.result(wire_tbl1_tbl2_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
tbl1_tbl2_prod.lpm_pipeline = 1,
tbl1_tbl2_prod.lpm_representation = "UNSIGNED",
tbl1_tbl2_prod.lpm_widtha = 32,
tbl1_tbl2_prod.lpm_widthb = 32,
tbl1_tbl2_prod.lpm_widthp = 64,
tbl1_tbl2_prod.lpm_type = "lpm_mult",
tbl1_tbl2_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult tbl3_taylor_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(table_three_out),
.datab({1'b1, {15{1'b0}}, xf[13:0]}),
.result(wire_tbl3_taylor_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
tbl3_taylor_prod.lpm_pipeline = 1,
tbl3_taylor_prod.lpm_representation = "UNSIGNED",
tbl3_taylor_prod.lpm_widtha = 32,
tbl3_taylor_prod.lpm_widthb = 30,
tbl3_taylor_prod.lpm_widthp = 62,
tbl3_taylor_prod.lpm_type = "lpm_mult",
tbl3_taylor_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult xi_ln2_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_exp_value_to_ln2a_dataout),
.datab(ln2_w),
.result(wire_xi_ln2_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
xi_ln2_prod.lpm_pipeline = 2,
xi_ln2_prod.lpm_representation = "UNSIGNED",
xi_ln2_prod.lpm_widtha = 8,
xi_ln2_prod.lpm_widthb = 38,
xi_ln2_prod.lpm_widthp = 46,
xi_ln2_prod.lpm_type = "lpm_mult",
xi_ln2_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult xi_prod
(
.dataa(x_fixed[37:26]),
.datab(one_over_ln2_w),
.result(wire_xi_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0),
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
xi_prod.lpm_representation = "UNSIGNED",
xi_prod.lpm_widtha = 12,
xi_prod.lpm_widthb = 9,
xi_prod.lpm_widthp = 21,
xi_prod.lpm_type = "lpm_mult",
xi_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mux table_one
(
.data(table_one_data),
.result(wire_table_one_result),
.sel(xf[28:24])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
table_one.lpm_size = 32,
table_one.lpm_width = 32,
table_one.lpm_widths = 5,
table_one.lpm_type = "lpm_mux";
lpm_mux table_three
(
.data(table_three_data),
.result(wire_table_three_result),
.sel(xf[18:14])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
table_three.lpm_size = 32,
table_three.lpm_width = 21,
table_three.lpm_widths = 5,
table_three.lpm_type = "lpm_mux";
lpm_mux table_two
(
.data(table_two_data),
.result(wire_table_two_result),
.sel(xf[23:19])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
table_two.lpm_size = 32,
table_two.lpm_width = 26,
table_two.lpm_widths = 5,
table_two.lpm_type = "lpm_mux";
assign
wire_cin_to_bias_dataout = shifted_value;
assign wire_exp_result_mux_prea_dataout = (((((barrel_shifter_underflow | overflow_w) | input_is_zero_wo) | nan_w) | positive_infinity) === 1'b1) ? exp_one : exp_result_w;
assign wire_exp_value_b4_biasa_dataout = (sign_dffe3[0:0] === 1'b1) ? exp_invert : xi_exp_value;
assign wire_exp_value_selecta_dataout = (exp_value_wo[8] === 1'b1) ? wire_invert_exp_value_result[5:0] : exp_value_wo[5:0];
assign wire_exp_value_to_compare_muxa_dataout = (exp_value_wo[8] === 1'b1) ? wire_invert_exp_value_result : exp_value_wo[7:0];
assign wire_exp_value_to_ln2a_dataout = (sign_dffe4[0:0] === 1'b1) ? wire_xi_add_one_result : xi_exp_value_wo;
assign wire_extra_ln2_muxa_dataout = (extra_ln2_dffe_0 === 1'b1) ? wire_xf_minus_ln2_result : xf_pre_wo[30:0];
assign wire_man_result_muxa_dataout = (((((overflow_w | underflow_w) | nan_w) | input_is_zero_wo) | input_is_infinity_wo) === 1'b1) ? {nan_w, {22{1'b0}}} : wire_man_round_result;
assign wire_xf_muxa_dataout = (sign_dffe10[0:0] === 1'b1) ? wire_one_minus_xf_result : xf_pre_2_wo[30:0];
assign
aclr = 1'b0,
addr_val_more_than_one = 5'b10111,
barrel_shifter_data = {{8{1'b0}}, 1'b1, fraction_wo, {6{1'b0}}},
barrel_shifter_distance = wire_exp_value_selecta_dataout,
barrel_shifter_underflow = barrel_shifter_underflow_dffe2_15_pipes14[0:0],
barrel_shifter_underflow_wi = (wire_underflow_compare_agb & exp_value_wo[8]),
clk_en = 1'b1,
distance_overflow = distance_overflow_dffe2_15_pipes14[0:0],
distance_overflow_val_w = 8'b00000110,
distance_overflow_wi = (wire_distance_overflow_comp_agb & (~ exp_value_wo[8])),
exp_bias = 8'b01111111,
exp_bias_all_ones_w = {8{1'b1}},
exp_data_all_one_w = {(data[30] & exp_data_all_one_w[6]), (data[29] & exp_data_all_one_w[5]), (data[28] & exp_data_all_one_w[4]), (data[27] & exp_data_all_one_w[3]), (data[26] & exp_data_all_one_w[2]), (data[25] & exp_data_all_one_w[1]), (data[24] & exp_data_all_one_w[0]), data[23]},
exp_data_not_zero_w = {(data[30] | exp_data_not_zero_w[6]), (data[29] | exp_data_not_zero_w[5]), (data[28] | exp_data_not_zero_w[4]), (data[27] | exp_data_not_zero_w[3]), (data[26] | exp_data_not_zero_w[2]), (data[25] | exp_data_not_zero_w[1]), (data[24] | exp_data_not_zero_w[0]), data[23]},
exp_invert = (xi_exp_value ^ exp_bias_all_ones_w),
exp_one = {((overflow_w | nan_w) | positive_infinity), {7{1'b1}}},
exp_out_all_one_w = {(exp_result_w[7] & exp_out_all_one_w[6]), (exp_result_w[6] & exp_out_all_one_w[5]), (exp_result_w[5] & exp_out_all_one_w[4]), (exp_result_w[4] & exp_out_all_one_w[3]), (exp_result_w[3] & exp_out_all_one_w[2]), (exp_result_w[2] & exp_out_all_one_w[1]), (exp_result_w[1] & exp_out_all_one_w[0]), exp_result_w[0]},
exp_out_not_zero_w = {(exp_result_w[7] | exp_out_not_zero_w[6]), (exp_result_w[6] | exp_out_not_zero_w[5]), (exp_result_w[5] | exp_out_not_zero_w[4]), (exp_result_w[4] | exp_out_not_zero_w[3]), (exp_result_w[3] | exp_out_not_zero_w[2]), (exp_result_w[2] | exp_out_not_zero_w[1]), (exp_result_w[1] | exp_out_not_zero_w[0]), exp_result_w[0]},
exp_result_out = (wire_exp_result_mux_prea_dataout & {8{(~ ((underflow_w & (~ barrel_shifter_underflow)) | negative_infinity))}}),
exp_result_w = wire_exp_value_man_over_result[7:0],
exp_value = wire_exp_minus_bias_result,
exp_value_wi = exp_value,
exp_value_wo = exp_value_dffe1,
exp_w = data[30:23],
extra_ln2 = ((~ xf_pre[37]) & sign_dffe8[0:0]),
fraction = {data[22:0]},
fraction_wi = fraction,
fraction_wo = fraction_dffe1,
gnd_w = 1'b0,
guard_bit = man_prod_result[35],
input_is_infinity_wi = (exp_data_all_one_w[7] & (~ man_data_not_zero_w[22])),
input_is_infinity_wo = input_is_infinity_16_pipes15[0:0],
input_is_nan_wi = (exp_data_all_one_w[7] & man_data_not_zero_w[22]),
input_is_nan_wo = input_is_nan_16_pipes15[0:0],
input_is_zero_wi = (~ exp_data_not_zero_w[7]),
input_is_zero_wo = input_is_zero_16_pipes15[0:0],
ln2_w = 38'b10110001011100100001011111110111110100,
man_data_not_zero_w = {(data[22] | man_data_not_zero_w[21]), (data[21] | man_data_not_zero_w[20]), (data[20] | man_data_not_zero_w[19]), (data[19] | man_data_not_zero_w[18]), (data[18] | man_data_not_zero_w[17]), (data[17] | man_data_not_zero_w[16]), (data[16] | man_data_not_zero_w[15]), (data[15] | man_data_not_zero_w[14]), (data[14] | man_data_not_zero_w[13]), (data[13] | man_data_not_zero_w[12]), (data[12] | man_data_not_zero_w[11]), (data[11] | man_data_not_zero_w[10]), (data[10] | man_data_not_zero_w[9]), (data[9] | man_data_not_zero_w[8]), (data[8] | man_data_not_zero_w[7]), (data[7] | man_data_not_zero_w[6]), (data[6] | man_data_not_zero_w[5]), (data[5] | man_data_not_zero_w[4]), (data[4] | man_data_not_zero_w[3]), (data[3] | man_data_not_zero_w[2]), (data[2] | man_data_not_zero_w[1]), (data[1] | man_data_not_zero_w[0]), data[0]},
man_overflow = (round_up & man_result_all_ones[22]),
man_overflow_wi = man_overflow,
man_overflow_wo = man_overflow_dffe15,
man_prod_result = ((man_prod_shifted & {62{man_prod_wo[59]}}) | (man_prod_wire & {62{(~ man_prod_wo[59])}})),
man_prod_shifted = {gnd_w, man_prod_wo[61:1]},
man_prod_wi = wire_man_prod_result,
man_prod_wire = man_prod_wo,
man_prod_wo = man_prod_dffe14,
man_result_all_ones = {(man_round_wi[22] & man_result_all_ones[21]), (man_round_wi[21] & man_result_all_ones[20]), (man_round_wi[20] & man_result_all_ones[19]), (man_round_wi[19] & man_result_all_ones[18]), (man_round_wi[18] & man_result_all_ones[17]), (man_round_wi[17] & man_result_all_ones[16]), (man_round_wi[16] & man_result_all_ones[15]), (man_round_wi[15] & man_result_all_ones[14]), (man_round_wi[14] & man_result_all_ones[13]), (man_round_wi[13] & man_result_all_ones[12]), (man_round_wi[12] & man_result_all_ones[11]), (man_round_wi[11] & man_result_all_ones[10]), (man_round_wi[10] & man_result_all_ones[9]), (man_round_wi[9] & man_result_all_ones[8]), (man_round_wi[8] & man_result_all_ones[7]), (man_round_wi[7] & man_result_all_ones[6]), (man_round_wi[6] & man_result_all_ones[5]), (man_round_wi[5] & man_result_all_ones[4]), (man_round_wi[4] & man_result_all_ones[3]), (man_round_wi[3] & man_result_all_ones[2]), (man_round_wi[2] & man_result_all_ones[1]), (man_round_wi[1] & man_result_all_ones[0]), man_round_wi[0]},
man_result_w = wire_man_result_muxa_dataout,
man_round_wi = man_prod_result[57:35],
man_round_wo = man_round_dffe15,
nan_w = input_is_nan_wo,
negative_infinity = (sign_dffe15[0:0] & input_is_infinity_wo),
one_over_ln2_w = 9'b101110001,
overflow_w = ((((~ sign_dffe15[0:0]) & (((distance_overflow | wire_exp_value_add_bias_result[8]) | exp_out_all_one_w[7]) | wire_exp_value_man_over_result[8])) & (~ underflow_w)) & (~ input_is_nan_wo)),
positive_infinity = ((~ sign_dffe15[0:0]) & input_is_infinity_wo),
result = {1'b0, result_pipe_wo},
result_pipe_wi = {exp_result_out, man_result_w},
result_pipe_wo = result_pipe_dffe16,
result_underflow_w = ((~ exp_out_not_zero_w[7]) & (((~ wire_exp_value_man_over_result[8]) & (~ sign_dffe15[0:0])) | sign_dffe15[0:0])),
round_bit = man_prod_result[34],
round_up = (round_bit & (guard_bit | sticky_bits[4])),
round_up_wi = round_up,
round_up_wo = round_up_dffe15,
shifted_value = (tbl1_compare_wo | man_prod_wo[59]),
sign_w = data[31],
sticky_bits = {(man_prod_result[29] | sticky_bits[3]), (man_prod_result[30] | sticky_bits[2]), (man_prod_result[31] | sticky_bits[1]), (man_prod_result[32] | sticky_bits[0]), man_prod_result[33]},
table_one_data = {32'b10101000100111100001011100110110, 32'b10100011011011100000001001111010, 32'b10011110011001101100101000011001, 32'b10011001100001110010110000111101, 32'b10010100110011011111000011111001, 32'b10010000001110011110100111111000, 32'b10001011110010011111001000110010, 32'b10000111011111001110110110100011, 32'b10000011010100011100100100000011, 32'b11111110100011101111001100001100, 32'b11110110101110011111100100100000, 32'b11101111001000101010111011111100, 32'b11100111110001110010111011000010, 32'b11100000101001011010000110001001, 32'b11011001101111000011111011100100, 32'b11010011000010010100110001110000, 32'b11001100100010110001110101101010, 32'b11000110010000000001001000111011, 32'b11000000001001101001100000011010, 32'b10111010001111010010100010011110, 32'b10110100100000100100100101100101, 32'b10101110111101001000101110110000, 32'b10101001100100101000110000000110, 32'b10100100010110101111000111100001, 32'b10011111010011000110111101010101, 32'b10011010011001011100000010111000, 32'b10010101101001011010110001011001, 32'b10010001000010110000001000101101, 32'b10001100100101001001101110000011, 32'b10001000010000010101101010111011, 32'b10000100000100000010101100000000, 32'b10000000000000000000000000000000},
table_one_out = wire_table_one_result,
table_three_data = {21'b111110000001111000001, 21'b111100000001110000100, 21'b111010000001101001001, 21'b111000000001100010000, 21'b110110000001011011001, 21'b110100000001010100100, 21'b110010000001001110001, 21'b110000000001001000000, 21'b101110000001000010001, 21'b101100000000111100100, 21'b101010000000110111001, 21'b101000000000110010000, 21'b100110000000101101001, 21'b100100000000101000100, 21'b100010000000100100001, 21'b100000000000100000000, 21'b011110000000011100001, 21'b011100000000011000100, 21'b011010000000010101001, 21'b011000000000010010000, 21'b010110000000001111001, 21'b010100000000001100100, 21'b010010000000001010001, 21'b010000000000001000000, 21'b001110000000000110001, 21'b001100000000000100100, 21'b001010000000000011001, 21'b001000000000000010000, 21'b000110000000000001001, 21'b000100000000000000100, 21'b000010000000000000001, {21{1'b0}}},
table_three_out = {1'b1, {10{1'b0}}, table_three_out_tmp},
table_three_out_tmp = wire_table_three_result,
table_two_data = {26'b11111011110010101100010101, 26'b11110011100011001101101010, 26'b11101011010100001111111011, 26'b11100011000101110011000111, 26'b11011010110111110111001100, 26'b11010010101010011100001000, 26'b11001010011101100001111000, 26'b11000010010001001000011011, 26'b10111010000101001111101110, 26'b10110001111001110111110000, 26'b10101001101111000000011110, 26'b10100001100100101001110111, 26'b10011001011010110011111000, 26'b10010001010001011110100000, 26'b10001001001000101001101100, 26'b10000001000000010101011010, 26'b01111000111000100001101001, 26'b01110000110001001110010101, 26'b01101000101010011011011110, 26'b01100000100100001001000001, 26'b01011000011110010110111100, 26'b01010000011001000101001110, 26'b01001000010100010011110011, 26'b01000000010000000010101011, 26'b00111000001100010001110010, 26'b00110000001001000001001000, 26'b00101000000110010000101001, 26'b00100000000100000000010101, 26'b00011000000010010000001001, 26'b00010000000001000000000010, 26'b00001000000000010000000000, {26{1'b0}}},
table_two_out = {1'b1, {5{1'b0}}, table_two_out_tmp},
table_two_out_tmp = wire_table_two_result,
tbl1_compare_wi = wire_tbl1_compare_ageb,
tbl1_compare_wo = tbl1_compare_dffe11_4_pipes3[0:0],
tbl1_tbl2_prod_wi = wire_tbl1_tbl2_prod_result[63:33],
tbl1_tbl2_prod_wo = tbl1_tbl2_prod_dffe12,
tbl3_taylor_prod_wi = wire_tbl3_taylor_prod_result[61:31],
tbl3_taylor_prod_wo = tbl3_taylor_prod_dffe12,
underflow_compare_val_w = 8'b00011101,
underflow_w = (((((result_underflow_w | barrel_shifter_underflow) | (sign_dffe15[0:0] & (distance_overflow | (~ wire_exp_value_add_bias_result[8])))) & (~ input_is_zero_wo)) & (~ input_is_infinity_wo)) & (~ input_is_nan_wo)),
x_fixed = wire_rbarrel_shift_result,
xf = wire_xf_muxa_dataout,
xf_pre = wire_x_fixed_minus_xiln2_result,
xf_pre_2_wi = xf_pre_wo,
xf_pre_2_wo = xf_pre_2_dffe10,
xf_pre_wi = xf_pre,
xf_pre_wo = xf_pre_dffe9,
xi_exp_value = xi_prod_wo[18:11],
xi_exp_value_wi = xi_exp_value,
xi_exp_value_wo = xi_exp_value_dffe4,
xi_ln2_prod_wi = wire_xi_ln2_prod_result,
xi_ln2_prod_wo = xi_ln2_prod_dffe7,
xi_prod_wi = wire_xi_prod_result,
xi_prod_wo = xi_prod_dffe3;
endmodule //fp_exp_altfp_exp_5fc
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fp_exp (
clock,
data,
result);
input clock;
input [31:0] data;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_exp_altfp_exp_5fc fp_exp_altfp_exp_5fc_component (
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_exp"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "17"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.cmp TRUE TRUE
// Retrieval info: LIB_FILE: lpm
|
module EmitOneCH
(
input Transmit_CLK, //100M
input RX_Gate, //Transmit Enable
input [7:0] EmitDelay, //7th bit for Transmit Enable, 6:0 for Delay
input [5:0] Emit_Width, //Emit pulse width
output reg TXP,
output reg TXN
);
reg [6:0] Emit_Counter;
reg [6:0] Delay_Counter;
always @(posedge Transmit_CLK or negedge RX_Gate)
begin
if(~RX_Gate)
begin
Emit_Counter <= 7'd0;
Delay_Counter <= 8'd0;
TXP <= 1'b1;
TXN <= 1'b1;
end
else
begin
if(Delay_Counter < EmitDelay[6:0] ) begin
Delay_Counter <= Delay_Counter + 1'b1;
TXP <= 1'b1;
TXN <= 1'b1;
end
else begin
if(~EmitDelay[7]) begin //enble Emit
if(Emit_Counter <Emit_Width)begin // Positive Pulse
TXP <= 1'b1;
TXN <= 1'b0;
Emit_Counter <= Emit_Counter + 1'b1;
end
else if(Emit_Counter <{Emit_Width,1'b0})begin // Negetive Pulse
TXP <= 1'b0;
TXN <= 1'b1;
Emit_Counter <= Emit_Counter + 1'b1;
end
/*
else if(Emit_Counter <({Emit_Width,1'b0}+Emit_Width))begin // Positive Pulse
TXP <= 1'b1;
TXN <= 1'b0;
Emit_Counter <= Emit_Counter + 1'b1;
end
else if(Emit_Counter <{Emit_Width,2'b0})begin // Negetive Pulse
TXP <= 1'b0;
TXN <= 1'b1;
Emit_Counter <= Emit_Counter + 1'b1;
end
*/
else if(Emit_Counter <({Emit_Width,2'b0}+Emit_Width))begin //Return to Zero (RTZ)
TXP <= 1'b0;
TXN <= 1'b0;
Emit_Counter <= Emit_Counter + 1'b1;
end
else begin
TXP <= 1'b1;
TXN <= 1'b1;
end
end
else begin //disable Emit
TXP <= 1'b1;
TXN <= 1'b1;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O22A_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O22A_PP_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O22A_PP_BLACKBOX_V
|
(** * StlcProp: Properties of STLC *)
Require Export Stlc.
Module STLCProp.
Import STLC.
(** In this chapter, we develop the fundamental theory of the Simply
Typed Lambda Calculus -- in particular, the type safety
theorem. *)
(* ###################################################################### *)
(** * Canonical Forms *)
Lemma canonical_forms_bool : forall t,
empty |- t \in TBool ->
value t ->
(t = ttrue) \/ (t = tfalse).
Proof.
intros t HT HVal.
inversion HVal; intros; subst; try inversion HT; auto.
Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Proof.
intros t T1 T2 HT HVal.
inversion HVal; intros; subst; try inversion HT; subst; auto.
exists x0. exists t0. auto.
Qed.
(* ###################################################################### *)
(** * Progress *)
(** As before, the _progress_ theorem tells us that closed, well-typed
terms are not stuck: either a well-typed term is a value, or it
can take an evaluation step. The proof is a relatively
straightforward extension of the progress proof we saw in the
[Types] chapter. *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
(** _Proof_: by induction on the derivation of [|- t \in T].
- The last rule of the derivation cannot be [T_Var], since a
variable is never well typed in an empty context.
- The [T_True], [T_False], and [T_Abs] cases are trivial, since in
each of these cases we know immediately that [t] is a value.
- If the last rule of the derivation was [T_App], then [t = t1
t2], and we know that [t1] and [t2] are also well typed in the
empty context; in particular, there exists a type [T2] such that
[|- t1 \in T2 -> T] and [|- t2 \in T2]. By the induction
hypothesis, either [t1] is a value or it can take an evaluation
step.
- If [t1] is a value, we now consider [t2], which by the other
induction hypothesis must also either be a value or take an
evaluation step.
- Suppose [t2] is a value. Since [t1] is a value with an
arrow type, it must be a lambda abstraction; hence [t1
t2] can take a step by [ST_AppAbs].
- Otherwise, [t2] can take a step, and hence so can [t1
t2] by [ST_App2].
- If [t1] can take a step, then so can [t1 t2] by [ST_App1].
- If the last rule of the derivation was [T_If], then [t = if t1
then t2 else t3], where [t1] has type [Bool]. By the IH, [t1]
either is a value or takes a step.
- If [t1] is a value, then since it has type [Bool] it must be
either [true] or [false]. If it is [true], then [t] steps
to [t2]; otherwise it steps to [t3].
- Otherwise, [t1] takes a step, and therefore so does [t] (by
[ST_If]).
*)
Proof with eauto.
intros t T Ht.
remember (@empty ty) as Gamma.
has_type_cases (induction Ht) Case; subst Gamma...
Case "T_Var".
(* contradictory: variables cannot be typed in an
empty context *)
inversion H.
Case "T_App".
(* [t] = [t1 t2]. Proceed by cases on whether [t1] is a
value or steps... *)
right. destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is also a value".
assert (exists x0 t0, t1 = tabs x0 T11 t0).
eapply canonical_forms_fun; eauto.
destruct H1 as [x0 [t0 Heq]]. subst.
exists ([x0:=t2]t0)...
SSCase "t2 steps".
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_If".
right. destruct IHHt1...
SCase "t1 is a value".
destruct (canonical_forms_bool t1); subst; eauto.
SCase "t1 also steps".
inversion H as [t1' Hstp]. exists (tif t1' t2 t3)...
Qed.
(** **** Exercise: 3 stars, optional (progress_from_term_ind) *)
(** Show that progress can also be proved by induction on terms
instead of induction on typing derivations. *)
Theorem progress' : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof with auto.
intros t.
t_cases (induction t) Case; intros T Ht; auto.
inversion Ht. subst. inversion H1.
Case "tapp".
right.
inversion Ht.
apply IHt1 in H2.
apply IHt2 in H4.
inversion Ht.
subst.
destruct H2.
destruct H4.
assert (exists x0 t0, t1 = tabs x0 T0 t0).
apply canonical_forms_fun with (T2:=T)...
destruct H1. destruct H1. subst. exists ([x0:=t2] x1)...
inversion H0. exists (tapp t1 x0)...
inversion H. exists (tapp x0 t2)...
Case "tif".
right.
inversion Ht.
apply IHt1 in H3.
inversion Ht.
subst.
destruct H3.
apply canonical_forms_bool in H11.
destruct H11.
exists (t2).
rewrite H0.
auto.
exists t3.
rewrite H0.
auto.
assumption.
inversion H.
exists (tif x0 t2 t3).
auto.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Preservation *)
(** The other half of the type soundness property is the preservation
of types during reduction. For this, we need to develop some
technical machinery for reasoning about variables and
substitution. Working from top to bottom (the high-level property
we are actually interested in to the lowest-level technical lemmas
that are needed by various cases of the more interesting proofs),
the story goes like this:
- The _preservation theorem_ is proved by induction on a typing
derivation, pretty much as we did in the [Types] chapter. The
one case that is significantly different is the one for the
[ST_AppAbs] rule, which is defined using the substitution
operation. To see that this step preserves typing, we need to
know that the substitution itself does. So we prove a...
- _substitution lemma_, stating that substituting a (closed)
term [s] for a variable [x] in a term [t] preserves the type
of [t]. The proof goes by induction on the form of [t] and
requires looking at all the different cases in the definition
of substitition. This time, the tricky cases are the ones for
variables and for function abstractions. In both cases, we
discover that we need to take a term [s] that has been shown
to be well-typed in some context [Gamma] and consider the same
term [s] in a slightly different context [Gamma']. For this
we prove a...
- _context invariance_ lemma, showing that typing is preserved
under "inessential changes" to the context [Gamma] -- in
particular, changes that do not affect any of the free
variables of the term. For this, we need a careful definition
of
- the _free variables_ of a term -- i.e., the variables occuring
in the term that are not in the scope of a function
abstraction that binds them.
*)
(* ###################################################################### *)
(** ** Free Occurrences *)
(** A variable [x] _appears free in_ a term _t_ if [t] contains some
occurrence of [x] that is not under an abstraction labeled [x]. For example:
- [y] appears free, but [x] does not, in [\x:T->U. x y]
- both [x] and [y] appear free in [(\x:T->U. x y) x]
- no variables appear free in [\x:T->U. \y:T. x y] *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3).
Tactic Notation "afi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "afi_var"
| Case_aux c "afi_app1" | Case_aux c "afi_app2"
| Case_aux c "afi_abs"
| Case_aux c "afi_if1" | Case_aux c "afi_if2"
| Case_aux c "afi_if3" ].
Hint Constructors appears_free_in.
(** A term in which no variables appear free is said to be _closed_. *)
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
(* ###################################################################### *)
(** ** Substitution *)
(** We first need a technical lemma connecting free variables and
typing contexts. If a variable [x] appears free in a term [t],
and if we know [t] is well typed in context [Gamma], then it must
be the case that [Gamma] assigns a type to [x]. *)
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
(** _Proof_: We show, by induction on the proof that [x] appears free
in [t], that, for all contexts [Gamma], if [t] is well typed
under [Gamma], then [Gamma] assigns some type to [x].
- If the last rule used was [afi_var], then [t = x], and from
the assumption that [t] is well typed under [Gamma] we have
immediately that [Gamma] assigns a type to [x].
- If the last rule used was [afi_app1], then [t = t1 t2] and [x]
appears free in [t1]. Since [t] is well typed under [Gamma],
we can see from the typing rules that [t1] must also be, and
the IH then tells us that [Gamma] assigns [x] a type.
- Almost all the other cases are similar: [x] appears free in a
subterm of [t], and since [t] is well typed under [Gamma], we
know the subterm of [t] in which [x] appears is well typed
under [Gamma] as well, and the IH gives us exactly the
conclusion we want.
- The only remaining case is [afi_abs]. In this case [t =
\y:T11.t12], and [x] appears free in [t12]; we also know that
[x] is different from [y]. The difference from the previous
cases is that whereas [t] is well typed under [Gamma], its
body [t12] is well typed under [(Gamma, y:T11)], so the IH
allows us to conclude that [x] is assigned some type by the
extended context [(Gamma, y:T11)]. To conclude that [Gamma]
assigns a type to [x], we appeal to lemma [extend_neq], noting
that [x] and [y] are different variables. *)
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
afi_cases (induction H) Case;
intros; try solve [inversion H0; eauto].
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite extend_neq in H7; assumption.
Qed.
(** Next, we'll need the fact that any term [t] which is well typed in
the empty context is closed -- that is, it has no free variables. *)
(** **** Exercise: 2 stars, optional (typable_empty__closed) *)
Corollary typable_empty__closed : forall t T,
empty |- t \in T ->
closed t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Sometimes, when we have a proof [Gamma |- t : T], we will need to
replace [Gamma] by a different context [Gamma']. When is it safe
to do this? Intuitively, it must at least be the case that
[Gamma'] assigns the same types as [Gamma] to all the variables
that appear free in [t]. In fact, this is the only condition that
is needed. *)
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
(** _Proof_: By induction on the derivation of [Gamma |- t \in T].
- If the last rule in the derivation was [T_Var], then [t = x]
and [Gamma x = T]. By assumption, [Gamma' x = T] as well, and
hence [Gamma' |- t \in T] by [T_Var].
- If the last rule was [T_Abs], then [t = \y:T11. t12], with [T
= T11 -> T12] and [Gamma, y:T11 |- t12 \in T12]. The induction
hypothesis is that for any context [Gamma''], if [Gamma,
y:T11] and [Gamma''] assign the same types to all the free
variables in [t12], then [t12] has type [T12] under [Gamma''].
Let [Gamma'] be a context which agrees with [Gamma] on the
free variables in [t]; we must show [Gamma' |- \y:T11. t12 \in
T11 -> T12].
By [T_Abs], it suffices to show that [Gamma', y:T11 |- t12 \in
T12]. By the IH (setting [Gamma'' = Gamma', y:T11]), it
suffices to show that [Gamma, y:T11] and [Gamma', y:T11] agree
on all the variables that appear free in [t12].
Any variable occurring free in [t12] must either be [y], or
some other variable. [Gamma, y:T11] and [Gamma', y:T11]
clearly agree on [y]. Otherwise, we note that any variable
other than [y] which occurs free in [t12] also occurs free in
[t = \y:T11. t12], and by assumption [Gamma] and [Gamma']
agree on all such variables, and hence so do [Gamma, y:T11]
and [Gamma', y:T11].
- If the last rule was [T_App], then [t = t1 t2], with [Gamma |-
t1 \in T2 -> T] and [Gamma |- t2 \in T2]. One induction
hypothesis states that for all contexts [Gamma'], if [Gamma']
agrees with [Gamma] on the free variables in [t1], then [t1]
has type [T2 -> T] under [Gamma']; there is a similar IH for
[t2]. We must show that [t1 t2] also has type [T] under
[Gamma'], given the assumption that [Gamma'] agrees with
[Gamma] on all the free variables in [t1 t2]. By [T_App], it
suffices to show that [t1] and [t2] each have the same type
under [Gamma'] as under [Gamma]. However, we note that all
free variables in [t1] are also free in [t1 t2], and similarly
for free variables in [t2]; hence the desired result follows
by the two IHs.
*)
Proof with eauto.
intros.
generalize dependent Gamma'.
has_type_cases (induction H) Case; intros; auto.
Case "T_Var".
apply T_Var. rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [extend Gamma x T11] *)
unfold extend. destruct (eq_id_dec x0 x1)...
Case "T_App".
apply T_App with T11...
Qed.
(** Now we come to the conceptual heart of the proof that reduction
preserves types -- namely, the observation that _substitution_
preserves types.
Formally, the so-called _Substitution Lemma_ says this: suppose we
have a term [t] with a free variable [x], and suppose we've been
able to assign a type [T] to [t] under the assumption that [x] has
some type [U]. Also, suppose that we have some other term [v] and
that we've shown that [v] has type [U]. Then, since [v] satisfies
the assumption we made about [x] when typing [t], we should be
able to substitute [v] for each of the occurrences of [x] in [t]
and obtain a new term that still has type [T]. *)
(** _Lemma_: If [Gamma,x:U |- t \in T] and [|- v \in U], then [Gamma |-
[x:=v]t \in T]. *)
Lemma substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
(** One technical subtlety in the statement of the lemma is that we
assign [v] the type [U] in the _empty_ context -- in other words,
we assume [v] is closed. This assumption considerably simplifies
the [T_Abs] case of the proof (compared to assuming [Gamma |- v \in
U], which would be the other reasonable assumption at this point)
because the context invariance lemma then tells us that [v] has
type [U] in any context at all -- we don't have to worry about
free variables in [v] clashing with the variable being introduced
into the context by [T_Abs].
_Proof_: We prove, by induction on [t], that, for all [T] and
[Gamma], if [Gamma,x:U |- t \in T] and [|- v \in U], then [Gamma |-
[x:=v]t \in T].
- If [t] is a variable, there are two cases to consider, depending
on whether [t] is [x] or some other variable.
- If [t = x], then from the fact that [Gamma, x:U |- x \in T] we
conclude that [U = T]. We must show that [[x:=v]x = v] has
type [T] under [Gamma], given the assumption that [v] has
type [U = T] under the empty context. This follows from
context invariance: if a closed term has type [T] in the
empty context, it has that type in any context.
- If [t] is some variable [y] that is not equal to [x], then
we need only note that [y] has the same type under [Gamma,
x:U] as under [Gamma].
- If [t] is an abstraction [\y:T11. t12], then the IH tells us,
for all [Gamma'] and [T'], that if [Gamma',x:U |- t12 \in T']
and [|- v \in U], then [Gamma' |- [x:=v]t12 \in T'].
The substitution in the conclusion behaves differently,
depending on whether [x] and [y] are the same variable name.
First, suppose [x = y]. Then, by the definition of
substitution, [[x:=v]t = t], so we just need to show [Gamma |-
t \in T]. But we know [Gamma,x:U |- t : T], and since the
variable [y] does not appear free in [\y:T11. t12], the
context invariance lemma yields [Gamma |- t \in T].
Second, suppose [x <> y]. We know [Gamma,x:U,y:T11 |- t12 \in
T12] by inversion of the typing relation, and [Gamma,y:T11,x:U
|- t12 \in T12] follows from this by the context invariance
lemma, so the IH applies, giving us [Gamma,y:T11 |- [x:=v]t12 \in
T12]. By [T_Abs], [Gamma |- \y:T11. [x:=v]t12 \in T11->T12], and
by the definition of substitution (noting that [x <> y]),
[Gamma |- \y:T11. [x:=v]t12 \in T11->T12] as required.
- If [t] is an application [t1 t2], the result follows
straightforwardly from the definition of substitution and the
induction hypotheses.
- The remaining cases are similar to the application case.
Another technical note: This proof is a rare case where an
induction on terms, rather than typing derivations, yields a
simpler argument. The reason for this is that the assumption
[extend Gamma x U |- t \in T] is not completely generic, in
the sense that one of the "slots" in the typing relation -- namely
the context -- is not just a variable, and this means that Coq's
native induction tactic does not give us the induction hypothesis
that we want. It is possible to work around this, but the needed
generalization is a little tricky. The term [t], on the other
hand, _is_ completely generic. *)
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma. generalize dependent T.
t_cases (induction t) Case; intros T Gamma H;
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
Case "tvar".
rename i into y. destruct (eq_id_dec x y).
SCase "x=y".
subst.
rewrite extend_eq in H2.
inversion H2; subst. clear H2.
eapply context_invariance... intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
apply T_Var. rewrite extend_neq in H2...
Case "tabs".
rename i into y. apply T_Abs.
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
(** The substitution lemma can be viewed as a kind of "commutation"
property. Intuitively, it says that substitution and typing can
be done in either order: we can either assign types to the terms
[t] and [v] separately (under suitable contexts) and then combine
them using substitution, or we can substitute first and then
assign a type to [ [x:=v] t ] -- the result is the same either
way. *)
(* ###################################################################### *)
(** ** Main Theorem *)
(** We now have the tools we need to prove preservation: if a closed
term [t] has type [T], and takes an evaluation step to [t'], then [t']
is also a closed term with type [T]. In other words, the small-step
evaluation relation preserves types.
*)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
(** _Proof_: by induction on the derivation of [|- t \in T].
- We can immediately rule out [T_Var], [T_Abs], [T_True], and
[T_False] as the final rules in the derivation, since in each of
these cases [t] cannot take a step.
- If the last rule in the derivation was [T_App], then [t = t1
t2]. There are three cases to consider, one for each rule that
could have been used to show that [t1 t2] takes a step to [t'].
- If [t1 t2] takes a step by [ST_App1], with [t1] stepping to
[t1'], then by the IH [t1'] has the same type as [t1], and
hence [t1' t2] has the same type as [t1 t2].
- The [ST_App2] case is similar.
- If [t1 t2] takes a step by [ST_AppAbs], then [t1 =
\x:T11.t12] and [t1 t2] steps to [[x:=t2]t12]; the
desired result now follows from the fact that substitution
preserves types.
- If the last rule in the derivation was [T_If], then [t = if t1
then t2 else t3], and there are again three cases depending on
how [t] steps.
- If [t] steps to [t2] or [t3], the result is immediate, since
[t2] and [t3] have the same type as [t].
- Otherwise, [t] steps by [ST_If], and the desired conclusion
follows directly from the induction hypothesis.
*)
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HE; subst Gamma; subst;
try solve [inversion HE; subst; auto].
Case "T_App".
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [eauto] takes care of them *)
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
Qed.
(** **** Exercise: 2 stars (subject_expansion_stlc) *)
(** An exercise in the [Types] chapter asked about the subject
expansion property for the simple language of arithmetic and
boolean expressions. Does this property hold for STLC? That is,
is it always the case that, if [t ==> t'] and [has_type t' T],
then [empty |- t \in T]? If so, prove it. If not, give a
counter-example not involving conditionals.
(* FILL IN HERE *)
[]
*)
(* ###################################################################### *)
(** * Type Soundness *)
(** **** Exercise: 2 stars, optional (type_soundness) *)
(** Put progress and preservation together and show that a well-typed
term can _never_ reach a stuck state. *)
Definition stuck (t:tm) : Prop :=
(normal_form step) t /\ ~ value t.
Corollary soundness : forall t t' T,
empty |- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T Hhas_type Hmulti. unfold stuck.
intros [Hnf Hnot_val]. unfold normal_form in Hnf.
induction Hmulti.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** * Uniqueness of Types *)
(** **** Exercise: 3 stars (types_unique) *)
(** Another pleasant property of the STLC is that types are
unique: a given term (in a given context) has at most one
type. *)
(** Formalize this statement and prove it. *)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 1 star (progress_preservation_statement) *)
(** Without peeking, write down the progress and preservation
theorems for the simply typed lambda-calculus. *)
(** [] *)
(** **** Exercise: 2 stars (stlc_variation1) *)
(** Suppose we add a new term [zap] with the following reduction rule:
--------- (ST_Zap)
t ==> zap
and the following typing rule:
---------------- (T_Zap)
Gamma |- zap : T
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars (stlc_variation2) *)
(** Suppose instead that we add a new term [foo] with the following reduction rules:
----------------- (ST_Foo1)
(\x:A. x) ==> foo
------------ (ST_Foo2)
foo ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars (stlc_variation3) *)
(** Suppose instead that we remove the rule [ST_App1] from the [step]
relation. Which of the following properties of the STLC remain
true in the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars, optional (stlc_variation4) *)
(** Suppose instead that we add the following new rule to the reduction relation:
---------------------------------- (ST_FunnyIfTrue)
(if true then t1 else t2) ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
(** **** Exercise: 2 stars, optional (stlc_variation5) *)
(** Suppose instead that we add the following new rule to the typing relation:
Gamma |- t1 \in Bool->Bool->Bool
Gamma |- t2 \in Bool
------------------------------ (T_FunnyApp)
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
(** **** Exercise: 2 stars, optional (stlc_variation6) *)
(** Suppose instead that we add the following new rule to the typing relation:
Gamma |- t1 \in Bool
Gamma |- t2 \in Bool
--------------------- (T_FunnyApp')
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
(** **** Exercise: 2 stars, optional (stlc_variation7) *)
(** Suppose we add the following new rule to the typing
relation of the STLC:
------------------- (T_FunnyAbs)
|- \x:Bool.t \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
End STLCProp.
(* ###################################################################### *)
(* ###################################################################### *)
(** ** Exercise: STLC with Arithmetic *)
(** To see how the STLC might function as the core of a real
programming language, let's extend it with a concrete base
type of numbers and some constants and primitive
operators. *)
Module STLCArith.
(** To types, we add a base type of natural numbers (and remove
booleans, for brevity) *)
Inductive ty : Type :=
| TArrow : ty -> ty -> ty
| TNat : ty.
(** To terms, we add natural number constants, along with
successor, predecessor, multiplication, and zero-testing... *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "tnat"
| Case_aux c "tsucc" | Case_aux c "tpred"
| Case_aux c "tmult" | Case_aux c "tif0" ].
(** **** Exercise: 4 stars (stlc_arith) *)
(** Finish formalizing the definition and properties of the STLC extended
with arithmetic. Specifically:
- Copy the whole development of STLC that we went through above (from
the definition of values through the Progress theorem), and
paste it into the file at this point.
- Extend the definitions of the [subst] operation and the [step]
relation to include appropriate clauses for the arithmetic operators.
- Extend the proofs of all the properties (up to [soundness]) of
the original STLC to deal with the new syntactic forms. Make
sure Coq accepts the whole file. *)
(* FILL IN HERE *)
(** [] *)
End STLCArith.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41O_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A41O_BEHAVIORAL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41O_BEHAVIORAL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pipe_drp.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_pipe_drp.v
// Description : PIPE DRP Module for 7 Series Transceiver
// Version : 20.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE DRP Module ---------------------------------------------------
module pcie3_7x_0_pipe_drp #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR Gen3 enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter LOAD_CNT_MAX = 2'd1, // Load max count
parameter INDEX_MAX = 5'd21 // Index max count
)
(
//---------- Input -------------------------------------
input DRP_CLK,
input DRP_RST_N,
input DRP_GTXRESET,
input [ 1:0] DRP_RATE,
input DRP_X16X20_MODE,
input DRP_X16,
input DRP_START,
input [15:0] DRP_DO,
input DRP_RDY,
//---------- Output ------------------------------------
output [ 8:0] DRP_ADDR,
output DRP_EN,
output [15:0] DRP_DI,
output DRP_WE,
output DRP_DONE,
output [ 6:0] DRP_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] load_cnt = 2'd0;
reg [ 4:0] index = 5'd0;
reg mode = 1'd0;
reg [ 8:0] addr_reg = 9'd0;
reg [15:0] di_reg = 16'd0;
//---------- Output Registers --------------------------
reg done = 1'd0;
reg [ 6:0] fsm = 7'd1;
//---------- DRP Address -------------------------------
// DRP access for *RXCDR_EIDLE includes
// - [11] RXCDR_HOLD_DURING_EIDLE
// - [12] RXCDR_FR_RESET_ON_EIDLE
// - [13] RXCDR_PH_RESET_ON_EIDLE
//------------------------------------------------------
localparam ADDR_PCS_RSVD_ATTR = 9'h06F;
localparam ADDR_TXOUT_DIV = 9'h088;
localparam ADDR_RXOUT_DIV = 9'h088;
localparam ADDR_TX_DATA_WIDTH = 9'h06B;
localparam ADDR_TX_INT_DATAWIDTH = 9'h06B;
localparam ADDR_RX_DATA_WIDTH = 9'h011;
localparam ADDR_RX_INT_DATAWIDTH = 9'h011;
localparam ADDR_TXBUF_EN = 9'h01C;
localparam ADDR_RXBUF_EN = 9'h09D;
localparam ADDR_TX_XCLK_SEL = 9'h059;
localparam ADDR_RX_XCLK_SEL = 9'h059;
localparam ADDR_CLK_CORRECT_USE = 9'h044;
localparam ADDR_TX_DRIVE_MODE = 9'h019;
localparam ADDR_RXCDR_EIDLE = 9'h0A7;
localparam ADDR_RX_DFE_LPM_EIDLE = 9'h01E;
localparam ADDR_PMA_RSV_A = 9'h099;
localparam ADDR_PMA_RSV_B = 9'h09A;
localparam ADDR_RXCDR_CFG_A = 9'h0A8;
localparam ADDR_RXCDR_CFG_B = 9'h0A9;
localparam ADDR_RXCDR_CFG_C = 9'h0AA;
localparam ADDR_RXCDR_CFG_D = 9'h0AB;
localparam ADDR_RXCDR_CFG_E = 9'h0AC;
localparam ADDR_RXCDR_CFG_F = 9'h0AD; // GTH only
//---------- DRP Mask ----------------------------------
localparam MASK_PCS_RSVD_ATTR = 16'b1111111111111001; // Unmask bit [ 2: 1]
localparam MASK_TXOUT_DIV = 16'b1111111110001111; // Unmask bit [ 6: 4]
localparam MASK_RXOUT_DIV = 16'b1111111111111000; // Unmask bit [ 2: 0]
localparam MASK_TX_DATA_WIDTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
localparam MASK_TX_INT_DATAWIDTH = 16'b1111111111101111; // Unmask bit [ 4]
localparam MASK_RX_DATA_WIDTH = 16'b1100011111111111; // Unmask bit [13:11]
localparam MASK_X16X20_RX_DATA_WIDTH = 16'b1111011111111111; // Unmask bit [ 11] // for x16 or x20 mode only
localparam MASK_RX_INT_DATAWIDTH = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_TXBUF_EN = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_RXBUF_EN = 16'b1111111111111101; // Unmask bit [ 1]
localparam MASK_TX_XCLK_SEL = 16'b1111111101111111; // Unmask bit [ 7]
localparam MASK_RX_XCLK_SEL = 16'b1111111110111111; // Unmask bit [ 6]
localparam MASK_CLK_CORRECT_USE = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_TX_DRIVE_MODE = 16'b1111111111100000; // Unmask bit [ 4:0]
localparam MASK_RXCDR_EIDLE = 16'b1111011111111111; // Unmask bit [ 11]
localparam MASK_RX_DFE_LPM_EIDLE = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_PMA_RSV_A = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_PMA_RSV_B = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_A = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_B = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_C = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_D = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_E_GTX = 16'b1111111100000000; // Unmask bit [ 7: 0]
localparam MASK_RXCDR_CFG_E_GTH = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_F_GTX = 16'b1111111111111111; // Unmask bit [ ]
localparam MASK_RXCDR_CFG_F_GTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
//---------- DRP Data for PCIe Gen1 and Gen2 -----------
localparam GEN12_TXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000100000 : 16'b0000000000010000; // Divide by 4 or 2
localparam GEN12_RXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000010 : 16'b0000000000000001; // Divide by 4 or 2
localparam GEN12_TX_DATA_WIDTH = 16'b0000000000000011; // 2-byte (16-bit) external data width
localparam GEN12_TX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
localparam GEN12_RX_DATA_WIDTH = 16'b0001100000000000; // 2-byte (16-bit) external data width
localparam GEN12_RX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
localparam GEN12_TXBUF_EN = 16'b0100000000000000; // Use TX buffer if PCIE_TXBUF_EN == "TRUE"
localparam GEN12_RXBUF_EN = 16'b0000000000000010; // Use RX buffer
localparam GEN12_TX_XCLK_SEL = 16'b0000000000000000; // Use TXOUT if PCIE_TXBUF_EN == "TRUE"
localparam GEN12_RX_XCLK_SEL = 16'b0000000000000000; // Use RXREC
localparam GEN12_CLK_CORRECT_USE = 16'b0100000000000000; // Use clock correction
localparam GEN12_TX_DRIVE_MODE = 16'b0000000000000001; // Use PIPE Gen1 and Gen2 mode
localparam GEN12_RXCDR_EIDLE = 16'b0000100000000000; // Hold RXCDR during electrical idle
localparam GEN12_RX_DFE_LPM_EIDLE = 16'b0100000000000000; // Hold RX DFE or LPM during electrical idle
localparam GEN12_PMA_RSV_A_GTX = 16'b1000010010000000; // 16'h8480
localparam GEN12_PMA_RSV_B_GTX = 16'b0000000000000001; // 16'h0001
localparam GEN12_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
localparam GEN12_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
//----------
localparam GEN12_RXCDR_CFG_A_GTX = 16'h0020; // 16'h0020
localparam GEN12_RXCDR_CFG_B_GTX = 16'h1020; // 16'h1020
localparam GEN12_RXCDR_CFG_C_GTX = 16'h23FF; // 16'h23FF
localparam GEN12_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
localparam GEN12_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
localparam GEN12_RXCDR_CFG_E_GTX = 16'h0003; // 16'h0003
localparam GEN12_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
//----------
localparam GEN12_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
localparam GEN12_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
localparam GEN12_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC208
localparam GEN12_RXCDR_CFG_C_GTH = 16'h2000; // 16'h2000
localparam GEN12_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE
localparam GEN12_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0020
localparam GEN12_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000
//---------- DRP Data for PCIe Gen3 --------------------
localparam GEN3_TXOUT_DIV = 16'b0000000000000000; // Divide by 1
localparam GEN3_RXOUT_DIV = 16'b0000000000000000; // Divide by 1
localparam GEN3_TX_DATA_WIDTH = 16'b0000000000000100; // 4-byte (32-bit) external data width
localparam GEN3_TX_INT_DATAWIDTH = 16'b0000000000010000; // 4-byte (32-bit) internal data width
localparam GEN3_RX_DATA_WIDTH = 16'b0010000000000000; // 4-byte (32-bit) external data width
localparam GEN3_RX_INT_DATAWIDTH = 16'b0100000000000000; // 4-byte (32-bit) internal data width
localparam GEN3_TXBUF_EN = 16'b0000000000000000; // Bypass TX buffer
localparam GEN3_RXBUF_EN = 16'b0000000000000000; // Bypass RX buffer
localparam GEN3_TX_XCLK_SEL = 16'b0000000010000000; // Use TXUSR
localparam GEN3_RX_XCLK_SEL = 16'b0000000001000000; // Use RXUSR
localparam GEN3_CLK_CORRECT_USE = 16'b0000000000000000; // Bypass clock correction
localparam GEN3_TX_DRIVE_MODE = 16'b0000000000000010; // Use PIPE Gen3 mode
localparam GEN3_RXCDR_EIDLE = 16'b0000000000000000; // Disable Hold RXCDR during electrical idle
localparam GEN3_RX_DFE_LPM_EIDLE = 16'b0000000000000000; // Disable RX DFE or LPM during electrical idle
localparam GEN3_PMA_RSV_A_GTX = 16'b0111000010000000; // 16'h7080
localparam GEN3_PMA_RSV_B_GTX = 16'b0000000000011110; // 16'h001E
localparam GEN3_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
localparam GEN3_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
//----------
localparam GEN3_RXCDR_CFG_A_GTX = 16'h0080; // 16'h0080
localparam GEN3_RXCDR_CFG_B_GTX = 16'h1010; // 16'h1010
localparam GEN3_RXCDR_CFG_C_GTX = 16'h0BFF; // 16'h0BFF
localparam GEN3_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
localparam GEN3_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
localparam GEN3_RXCDR_CFG_E_GTX = 16'h000B; // 16'h000B
localparam GEN3_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
//----------
//localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
//localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
//localparam GEN3_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC848
//localparam GEN3_RXCDR_CFG_C_GTH = 16'h2000; // 16'h1000
//localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
//localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
//localparam GEN3_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0010
//localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
//localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
//----------
localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
localparam GEN3_RXCDR_CFG_B_GTH = 16'hC848; // 16'hC848
localparam GEN3_RXCDR_CFG_C_GTH = 16'h1000; // 16'h1000
localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
localparam GEN3_RXCDR_CFG_E_GTH = 16'h0010; // 16'h0010
localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
//---------- DRP Data for PCIe Gen1, Gen2 and Gen3 -----
localparam GEN123_PCS_RSVD_ATTR_A = 16'b0000000000000000; // Auto TX and RX sync mode
localparam GEN123_PCS_RSVD_ATTR_M_TX = 16'b0000000000000010; // Manual TX sync mode
localparam GEN123_PCS_RSVD_ATTR_M_RX = 16'b0000000000000100; // Manual RX sync mode
//---------- DRP Data for x16 --------------------------
localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width
//---------- DRP Data for x20 --------------------------
localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width
//---------- DRP Data ----------------------------------
wire [15:0] data_txout_div;
wire [15:0] data_rxout_div;
wire [15:0] data_tx_data_width;
wire [15:0] data_tx_int_datawidth;
wire [15:0] data_rx_data_width;
wire [15:0] data_rx_int_datawidth;
wire [15:0] data_txbuf_en;
wire [15:0] data_rxbuf_en;
wire [15:0] data_tx_xclk_sel;
wire [15:0] data_rx_xclk_sel;
wire [15:0] data_clk_correction_use;
wire [15:0] data_tx_drive_mode;
wire [15:0] data_rxcdr_eidle;
wire [15:0] data_rx_dfe_lpm_eidle;
wire [15:0] data_pma_rsv_a;
wire [15:0] data_pma_rsv_b;
wire [15:0] data_rxcdr_cfg_a;
wire [15:0] data_rxcdr_cfg_b;
wire [15:0] data_rxcdr_cfg_c;
wire [15:0] data_rxcdr_cfg_d;
wire [15:0] data_rxcdr_cfg_e;
wire [15:0] data_rxcdr_cfg_f;
wire [15:0] data_pcs_rsvd_attr_a;
wire [15:0] data_pcs_rsvd_attr_m_tx;
wire [15:0] data_pcs_rsvd_attr_m_rx;
wire [15:0] data_pcs_rsvd_attr_m;
wire [15:0] data_x16x20_rx_datawidth;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 7'b0000001;
localparam FSM_LOAD = 7'b0000010;
localparam FSM_READ = 7'b0000100;
localparam FSM_RRDY = 7'b0001000;
localparam FSM_WRITE = 7'b0010000;
localparam FSM_WRDY = 7'b0100000;
localparam FSM_DONE = 7'b1000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
//---------- 1st Stage FF --------------------------
gtxreset_reg1 <= 1'd0;
rate_reg1 <= 2'd0;
x16x20_mode_reg1 <= 1'd0;
x16_reg1 <= 1'd0;
do_reg1 <= 16'd0;
rdy_reg1 <= 1'd0;
start_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gtxreset_reg2 <= 1'd0;
rate_reg2 <= 2'd0;
x16x20_mode_reg2 <= 1'd0;
x16_reg2 <= 1'd0;
do_reg2 <= 16'd0;
rdy_reg2 <= 1'd0;
start_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gtxreset_reg1 <= DRP_GTXRESET;
rate_reg1 <= DRP_RATE;
x16x20_mode_reg1 <= DRP_X16X20_MODE;
x16_reg1 <= DRP_X16;
do_reg1 <= DRP_DO;
rdy_reg1 <= DRP_RDY;
start_reg1 <= DRP_START;
//---------- 2nd Stage FF --------------------------
gtxreset_reg2 <= gtxreset_reg1;
rate_reg2 <= rate_reg1;
x16x20_mode_reg2 <= x16x20_mode_reg1;
x16_reg2 <= x16_reg1;
do_reg2 <= do_reg1;
rdy_reg2 <= rdy_reg1;
start_reg2 <= start_reg1;
end
end
//---------- Select DRP Data ---------------------------------------------------
assign data_txout_div = (rate_reg2 == 2'd2) ? GEN3_TXOUT_DIV : GEN12_TXOUT_DIV;
assign data_rxout_div = (rate_reg2 == 2'd2) ? GEN3_RXOUT_DIV : GEN12_RXOUT_DIV;
assign data_tx_data_width = (rate_reg2 == 2'd2) ? GEN3_TX_DATA_WIDTH : GEN12_TX_DATA_WIDTH;
assign data_tx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_TX_INT_DATAWIDTH : GEN12_TX_INT_DATAWIDTH;
assign data_rx_data_width = (rate_reg2 == 2'd2) ? GEN3_RX_DATA_WIDTH : GEN12_RX_DATA_WIDTH;
assign data_rx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_RX_INT_DATAWIDTH : GEN12_RX_INT_DATAWIDTH;
assign data_txbuf_en = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TXBUF_EN : GEN12_TXBUF_EN;
assign data_rxbuf_en = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RXBUF_EN : GEN12_RXBUF_EN;
assign data_tx_xclk_sel = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TX_XCLK_SEL : GEN12_TX_XCLK_SEL;
assign data_rx_xclk_sel = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RX_XCLK_SEL : GEN12_RX_XCLK_SEL;
assign data_clk_correction_use = (rate_reg2 == 2'd2) ? GEN3_CLK_CORRECT_USE : GEN12_CLK_CORRECT_USE;
assign data_tx_drive_mode = (rate_reg2 == 2'd2) ? GEN3_TX_DRIVE_MODE : GEN12_TX_DRIVE_MODE;
assign data_rxcdr_eidle = (rate_reg2 == 2'd2) ? GEN3_RXCDR_EIDLE : GEN12_RXCDR_EIDLE;
assign data_rx_dfe_lpm_eidle = (rate_reg2 == 2'd2) ? GEN3_RX_DFE_LPM_EIDLE : GEN12_RX_DFE_LPM_EIDLE;
assign data_pma_rsv_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_A_GTH : GEN3_PMA_RSV_A_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_A_GTH : GEN12_PMA_RSV_A_GTX);
assign data_pma_rsv_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_B_GTH : GEN3_PMA_RSV_B_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_B_GTH : GEN12_PMA_RSV_B_GTX);
assign data_rxcdr_cfg_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_A_GTH_A : GEN3_RXCDR_CFG_A_GTH_S) : GEN3_RXCDR_CFG_A_GTX) :
((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN12_RXCDR_CFG_A_GTH_A : GEN12_RXCDR_CFG_A_GTH_S) : GEN12_RXCDR_CFG_A_GTX);
assign data_rxcdr_cfg_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_B_GTH : GEN3_RXCDR_CFG_B_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_B_GTH : GEN12_RXCDR_CFG_B_GTX);
assign data_rxcdr_cfg_c = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_C_GTH : GEN3_RXCDR_CFG_C_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_C_GTH : GEN12_RXCDR_CFG_C_GTX);
assign data_rxcdr_cfg_d = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTH_AUX : GEN3_RXCDR_CFG_D_GTH) : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S)) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_D_GTH : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S));
assign data_rxcdr_cfg_e = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_E_GTH : GEN3_RXCDR_CFG_E_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_E_GTH : GEN12_RXCDR_CFG_E_GTX);
assign data_rxcdr_cfg_f = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_F_GTH_AUX : GEN3_RXCDR_CFG_F_GTH) : GEN3_RXCDR_CFG_F_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_F_GTH : GEN12_RXCDR_CFG_F_GTX);
assign data_pcs_rsvd_attr_a = GEN123_PCS_RSVD_ATTR_A;
assign data_pcs_rsvd_attr_m_tx = PCIE_TXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_TX;
assign data_pcs_rsvd_attr_m_rx = PCIE_RXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_RX;
assign data_pcs_rsvd_attr_m = data_pcs_rsvd_attr_m_tx | data_pcs_rsvd_attr_m_rx;
assign data_x16x20_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
//---------- Load Counter ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
load_cnt <= 2'd0;
else
//---------- Increment Load Counter ----------------
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
load_cnt <= load_cnt + 2'd1;
//---------- Hold Load Counter ---------------------
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
load_cnt <= load_cnt;
//---------- Reset Load Counter --------------------
else
load_cnt <= 2'd0;
end
//---------- Update DRP Address and Data ---------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
else
begin
case (index)
//--------------------------------------------------
5'd0:
begin
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR :
x16x20_mode_reg2 ? ADDR_RX_DATA_WIDTH : ADDR_TXOUT_DIV;
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_a) :
x16x20_mode_reg2 ? ((do_reg2 & MASK_X16X20_RX_DATA_WIDTH) | data_x16x20_rx_datawidth) :
((do_reg2 & MASK_TXOUT_DIV) | data_txout_div);
end
//--------------------------------------------------
5'd1:
begin
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR : ADDR_RXOUT_DIV;
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_m) :
((do_reg2 & MASK_RXOUT_DIV) | data_rxout_div);
end
//--------------------------------------------------
5'd2 :
begin
addr_reg <= ADDR_TX_DATA_WIDTH;
di_reg <= (do_reg2 & MASK_TX_DATA_WIDTH) | data_tx_data_width;
end
//--------------------------------------------------
5'd3 :
begin
addr_reg <= ADDR_TX_INT_DATAWIDTH;
di_reg <= (do_reg2 & MASK_TX_INT_DATAWIDTH) | data_tx_int_datawidth;
end
//--------------------------------------------------
5'd4 :
begin
addr_reg <= ADDR_RX_DATA_WIDTH;
di_reg <= (do_reg2 & MASK_RX_DATA_WIDTH) | data_rx_data_width;
end
//--------------------------------------------------
5'd5 :
begin
addr_reg <= ADDR_RX_INT_DATAWIDTH;
di_reg <= (do_reg2 & MASK_RX_INT_DATAWIDTH) | data_rx_int_datawidth;
end
//--------------------------------------------------
5'd6 :
begin
addr_reg <= ADDR_TXBUF_EN;
di_reg <= (do_reg2 & MASK_TXBUF_EN) | data_txbuf_en;
end
//--------------------------------------------------
5'd7 :
begin
addr_reg <= ADDR_RXBUF_EN;
di_reg <= (do_reg2 & MASK_RXBUF_EN) | data_rxbuf_en;
end
//--------------------------------------------------
5'd8 :
begin
addr_reg <= ADDR_TX_XCLK_SEL;
di_reg <= (do_reg2 & MASK_TX_XCLK_SEL) | data_tx_xclk_sel;
end
//--------------------------------------------------
5'd9 :
begin
addr_reg <= ADDR_RX_XCLK_SEL;
di_reg <= (do_reg2 & MASK_RX_XCLK_SEL) | data_rx_xclk_sel;
end
//--------------------------------------------------
5'd10 :
begin
addr_reg <= ADDR_CLK_CORRECT_USE;
di_reg <= (do_reg2 & MASK_CLK_CORRECT_USE) | data_clk_correction_use;
end
//--------------------------------------------------
5'd11 :
begin
addr_reg <= ADDR_TX_DRIVE_MODE;
di_reg <= (do_reg2 & MASK_TX_DRIVE_MODE) | data_tx_drive_mode;
end
//--------------------------------------------------
5'd12 :
begin
addr_reg <= ADDR_RXCDR_EIDLE;
di_reg <= (do_reg2 & MASK_RXCDR_EIDLE) | data_rxcdr_eidle;
end
//--------------------------------------------------
5'd13 :
begin
addr_reg <= ADDR_RX_DFE_LPM_EIDLE;
di_reg <= (do_reg2 & MASK_RX_DFE_LPM_EIDLE) | data_rx_dfe_lpm_eidle;
end
//--------------------------------------------------
5'd14 :
begin
addr_reg <= ADDR_PMA_RSV_A;
di_reg <= (do_reg2 & MASK_PMA_RSV_A) | data_pma_rsv_a;
end
//--------------------------------------------------
5'd15 :
begin
addr_reg <= ADDR_PMA_RSV_B;
di_reg <= (do_reg2 & MASK_PMA_RSV_B) | data_pma_rsv_b;
end
//--------------------------------------------------
5'd16 :
begin
addr_reg <= ADDR_RXCDR_CFG_A;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_A) | data_rxcdr_cfg_a;
end
//--------------------------------------------------
5'd17 :
begin
addr_reg <= ADDR_RXCDR_CFG_B;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_B) | data_rxcdr_cfg_b;
end
//--------------------------------------------------
5'd18 :
begin
addr_reg <= ADDR_RXCDR_CFG_C;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_C) | data_rxcdr_cfg_c;
end
//--------------------------------------------------
5'd19 :
begin
addr_reg <= ADDR_RXCDR_CFG_D;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_D) | data_rxcdr_cfg_d;
end
//--------------------------------------------------
5'd20 :
begin
addr_reg <= ADDR_RXCDR_CFG_E;
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_E_GTH : MASK_RXCDR_CFG_E_GTX)) | data_rxcdr_cfg_e;
end
//--------------------------------------------------
5'd21 :
begin
addr_reg <= ADDR_RXCDR_CFG_F;
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_F_GTH : MASK_RXCDR_CFG_F_GTX)) | data_rxcdr_cfg_f;
end
//--------------------------------------------------
default :
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
endcase
end
end
//---------- PIPE DRP FSM ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Reset or Rate Change --------------
if (start_reg2)
begin
fsm <= FSM_LOAD;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
//---------- GTXRESET --------------------------
else if ((gtxreset_reg2 && !gtxreset_reg1) && ((PCIE_TXSYNC_MODE == 0) || (PCIE_RXSYNC_MODE == 0)) && (PCIE_USE_MODE == "1.0"))
begin
fsm <= FSM_LOAD;
index <= 5'd0;
mode <= 1'd1;
done <= 1'd0;
end
//---------- Idle ------------------------------
else
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd1;
end
end
//---------- Load DRP Address ---------------------
FSM_LOAD :
begin
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP ------------------------------
FSM_READ :
begin
fsm <= FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP Ready ------------------------
FSM_RRDY :
begin
fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP -----------------------------
FSM_WRITE :
begin
fsm <= FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP Ready -----------------------
FSM_WRDY :
begin
fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- DRP Done ------------------------------
FSM_DONE :
begin
if ((index == INDEX_MAX) || (mode && (index == 5'd1)) || (x16x20_mode_reg2 && (index == 5'd0)))
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
fsm <= FSM_LOAD;
index <= index + 5'd1;
mode <= mode;
done <= 1'd0;
end
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
endcase
end
end
//---------- PIPE DRP Output ---------------------------------------------------
assign DRP_ADDR = addr_reg;
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
assign DRP_DI = di_reg;
assign DRP_WE = (fsm == FSM_WRITE);
assign DRP_DONE = done;
assign DRP_FSM = fsm;
endmodule
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`include "consts.vh"
`timescale 1ns/1ps
module top_test ();
reg clk;
reg reset;
initial clk = 0;
parameter half_cycle = 5;
localparam cycle = 2 * half_cycle;
localparam timeout = 100;
always #(half_cycle) clk = ~clk;
wire [(`STR_LEN * 8) - 1:0] s;
top top(.clk(clk), .reset(reset));
inst_decoder id(.str(s),
.jump_target(top.dpath.jump_target),
.branch_target(top.dpath.branch_target),
.inst(top.dpath.inst));
integer i;
initial begin
$dumpvars();
i = 0;
/* toggle reset */
#(cycle);
reset = 1;
#(cycle);
reset = 0;
#(cycle);
while (top.dpath.cp.tohost == 0 && i < timeout) begin
#(cycle);
i = i + 1;
$display("C %10d: pc=[%08x] [%s] W[r%2d=%08x][%b] R[r%2d=%08x] R[r%2d=%08x] inst=[%08x] %s",
i, top.dpath.pc, top.stall ? "S" : " ",
top.dpath.ex_wd, top.dpath.rf_wdata, top.dpath.rf_wr_en,
top.dpath.ex_rs1, top.dpath.rf_rd1,
top.dpath.ex_rs2, top.dpath.rf_rd2,
top.dpath.inst,
top.stall ? "" : s);
end
if (i == timeout) begin
$display("*** TIMEOUT ***");
$finish();
end
if (top.dpath.cp.tohost == 1) begin
$display("*** SUCCESS (tohost = 1) ***");
end else begin
$display("*** FAILURE (tohost = %d) ***", top.dpath.cp.tohost);
end
$finish();
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module pulse_gen640_core
#(
parameter ABUSWIDTH = 16,
parameter CLKDV = 4, //only 4 will work for now
parameter OUTPUT_SIZE =2
)
(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire PULSE_CLK,
input wire PULSE_CLK160,
input wire PULSE_CLK320,
input wire EXT_START,
output wire [OUTPUT_SIZE-1:0] PULSE,
output wire DEBUG
);
localparam VERSION = 1;
wire SOFT_RST;
wire START;
reg CONF_EN;
reg [31:0] CONF_DELAY;
reg [31:0] CONF_WIDTH;
reg [31:0] CONF_REPEAT;
//reg [CLKDV*4-1:0] CONF_PHASE;
reg [15:0] CONF_PHASE;
reg CONF_DONE;
always@(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_DONE};
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {7'b0, CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= CONF_DELAY[7:0];
else if(BUS_ADD == 4)
BUS_DATA_OUT <= CONF_DELAY[15:8];
else if(BUS_ADD == 5)
BUS_DATA_OUT <= CONF_DELAY[23:16];
else if(BUS_ADD == 6)
BUS_DATA_OUT <= CONF_DELAY[31:24];
else if(BUS_ADD == 7)
BUS_DATA_OUT <= CONF_WIDTH[7:0];
else if(BUS_ADD == 8)
BUS_DATA_OUT <= CONF_WIDTH[15:8];
else if(BUS_ADD == 9)
BUS_DATA_OUT <= CONF_WIDTH[23:16];
else if(BUS_ADD == 10)
BUS_DATA_OUT <= CONF_WIDTH[31:24];
else if(BUS_ADD == 11)
BUS_DATA_OUT <= CONF_REPEAT[7:0];
else if(BUS_ADD == 12)
BUS_DATA_OUT <= CONF_REPEAT[15:8];
else if(BUS_ADD == 13)
BUS_DATA_OUT <= CONF_REPEAT[23:16];
else if(BUS_ADD == 14)
BUS_DATA_OUT <= CONF_REPEAT[31:24];
else if(BUS_ADD == 15)
BUS_DATA_OUT <= CONF_PHASE[7:0];
else if(BUS_ADD == 16)
BUS_DATA_OUT <= CONF_PHASE[15:8];
// debug
else if(BUS_ADD == 17)
BUS_DATA_OUT <= CNT[7:0];
else if(BUS_ADD == 18)
BUS_DATA_OUT <= CNT[15:8];
else if(BUS_ADD == 19)
BUS_DATA_OUT <= CNT[23:16];
else if(BUS_ADD == 20)
BUS_DATA_OUT <= CNT[31:24];
else if(BUS_ADD == 21)
BUS_DATA_OUT <= {6'b0,PULSE_REF, CNT[32]};
else
BUS_DATA_OUT <= 8'b0;
end
end
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign START = (BUS_ADD==1 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
CONF_DELAY <= 0;
CONF_WIDTH <= 0;
CONF_REPEAT <= 1;
end
else if(BUS_WR) begin
if(BUS_ADD == 2)
CONF_EN <= BUS_DATA_IN[0];
else if(BUS_ADD == 3)
CONF_DELAY[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 4)
CONF_DELAY[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 5)
CONF_DELAY[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 6)
CONF_DELAY[31:24] <= BUS_DATA_IN;
else if(BUS_ADD == 7)
CONF_WIDTH[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 8)
CONF_WIDTH[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 9)
CONF_WIDTH[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 10)
CONF_WIDTH[31:24] <= BUS_DATA_IN;
else if(BUS_ADD == 11)
CONF_REPEAT[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 12)
CONF_REPEAT[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 13)
CONF_REPEAT[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 14)
CONF_REPEAT[31:24] <= BUS_DATA_IN;
else if(BUS_ADD == 15)
CONF_PHASE[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 16)
CONF_PHASE[15:8] <= BUS_DATA_IN;
end
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(PULSE_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(PULSE_CLK), .pulse_out(START_SYNC));
wire EXT_START_SYNC;
reg [2:0] EXT_START_FF;
always @(posedge PULSE_CLK) // first stage
begin
EXT_START_FF[0] <= EXT_START;
EXT_START_FF[1] <= EXT_START_FF[0];
EXT_START_FF[2] <= EXT_START_FF[1];
end
assign EXT_START_SYNC = !EXT_START_FF[2] & EXT_START_FF[1];
reg [31:0] CNT;
wire [32:0] LAST_CNT;
assign LAST_CNT = CONF_DELAY + CONF_WIDTH;
reg [31:0] REAPAT_CNT;
always @ (posedge PULSE_CLK) begin
if (RST_SYNC)
REAPAT_CNT <= 0;
else if(START_SYNC || (EXT_START_SYNC && CONF_EN))
REAPAT_CNT <= CONF_REPEAT;
else if(REAPAT_CNT != 0 && CNT == 1)
REAPAT_CNT <= REAPAT_CNT - 1;
end
always @ (posedge PULSE_CLK) begin
if (RST_SYNC)
CNT <= 0; //IS THIS RIGHT?
else if(START_SYNC || (EXT_START_SYNC && CONF_EN))
CNT <= 1;
else if(CNT == LAST_CNT && REAPAT_CNT != 0)
CNT <= 1;
else if(CNT == LAST_CNT && CONF_REPEAT==0)
CNT <= 1;
else if(CNT == LAST_CNT && REAPAT_CNT == 0)
CNT <= 0;
else if(CNT != 0)
CNT <= CNT + 1;
end
reg [CLKDV*4-1:0] PULSE_DES;
reg PULSE_REF;
always @ (posedge PULSE_CLK) begin
if(RST_SYNC || START_SYNC || (EXT_START_SYNC && CONF_EN)) begin
PULSE_DES <= 0;
PULSE_REF<=0;
end
else if(CNT == CONF_DELAY && CNT > 0) begin
PULSE_REF<=1;
PULSE_DES <= CONF_PHASE;
end
else if(CNT == CONF_DELAY+1) begin
PULSE_DES <= 16'b1111111111111111;
PULSE_REF<=1;
end
else if(CNT == LAST_CNT) begin
PULSE_DES <= 0;
PULSE_REF<=0;
end
end
assign DEBUG = PULSE_REF;
wire PULSE_CLK_PULSE;
reg [1:0] PULSE_CLK_FF;
always @ (posedge PULSE_CLK160)
PULSE_CLK_FF[1:0] <= {PULSE_CLK_FF[0],PULSE_CLK};
assign PULSE_CLK_PULSE = PULSE_CLK & ~PULSE_CLK_FF[0];
reg [CLKDV*4-1:0] PULSE_DES_DIV;
always @ (negedge PULSE_CLK160) begin
if(RST_SYNC || START_SYNC || (EXT_START_SYNC && CONF_EN))
PULSE_DES_DIV <= 0;
else if (PULSE_CLK_PULSE==1)
PULSE_DES_DIV <= PULSE_DES;
else
PULSE_DES_DIV[CLKDV*4-2:0] <= {PULSE_DES_DIV[CLKDV*4-1],PULSE_DES_DIV[CLKDV*4-1],
PULSE_DES_DIV[CLKDV*4-1],PULSE_DES_DIV[CLKDV*4-1:4]};
end
genvar i;
generate
for (i=0; i<2; i=i+1) begin
OSERDESE2 # (
.DATA_RATE_OQ("DDR"),
.DATA_WIDTH(4),
.SERDES_MODE("MASTER")
) i_OSERDESE2_0 (
.OQ(PULSE[i]),
.OFB(),
.TQ(),
.TFB(),
.SHIFTOUT1(),
.SHIFTOUT2(),
.CLK(PULSE_CLK320),
.CLKDIV(PULSE_CLK160),
.D1(PULSE_DES_DIV[0]),
.D2(PULSE_DES_DIV[1]),
.D3(PULSE_DES_DIV[2]),
.D4(PULSE_DES_DIV[3]),
.D5(),
.D6(),
.D7(),
.D8(),
.TCE(0),
.OCE(1),
.TBYTEIN(),
.TBYTEOUT(),
.RST(RST_SYNC),
.SHIFTIN1(),
.SHIFTIN2(),
.T1(0),
.T2(0),
.T3(0),
.T4(0)
);
end
endgenerate
wire DONE;
assign DONE = (CNT == 0);
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(PULSE_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
wire EXT_START_SYNC_BUS;
cdc_pulse_sync ex_start_pulse_sync (.clk_in(PULSE_CLK), .pulse_in(EXT_START && CONF_EN), .clk_out(BUS_CLK), .pulse_out(EXT_START_SYNC_BUS));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START || EXT_START_SYNC_BUS)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/11 15:27:34
// Design Name:
// Module Name: lab5_2_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab5_2_1(
input in,reset,clk,
output reg z
);
reg [1:0] state,nextstate;
parameter S0 = 0,S1 = 1,S2 = 2,S3 = 3;
always @(posedge clk or posedge reset)
if(reset)
state = S0;
else
state = nextstate;
always @(state)
begin
case(state)
S0: z = 0;
S1: z = 0;
S2: z = 0;
S3: z = 1;
endcase
end
always @(state or in)
begin
case(state)
S0:
begin
if(in)
nextstate = S1;
else
nextstate = S0;
end
S1:
begin
if(in)
nextstate = S2;
else
nextstate = S1;
end
S2:
begin
if(in)
nextstate = S3;
else
nextstate = S2;
end
S3:
begin
if(in)
nextstate = S1;
else
nextstate = S3;
end
endcase
end
endmodule
|
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: xgmii_loopback.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module xgmii_loopback (
data0x,
data1x,
sel,
result);
input [65:0] data0x;
input [65:0] data1x;
input sel;
output [65:0] result;
wire [65:0] sub_wire0;
wire [65:0] sub_wire3 = data1x[65:0];
wire [65:0] result = sub_wire0[65:0];
wire [65:0] sub_wire1 = data0x[65:0];
wire [131:0] sub_wire2 = {sub_wire3, sub_wire1};
wire sub_wire4 = sel;
wire sub_wire5 = sub_wire4;
lpm_mux LPM_MUX_component (
.data (sub_wire2),
.sel (sub_wire5),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_size = 2,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 66,
LPM_MUX_component.lpm_widths = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "66"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
// Retrieval info: USED_PORT: data0x 0 0 66 0 INPUT NODEFVAL "data0x[65..0]"
// Retrieval info: USED_PORT: data1x 0 0 66 0 INPUT NODEFVAL "data1x[65..0]"
// Retrieval info: USED_PORT: result 0 0 66 0 OUTPUT NODEFVAL "result[65..0]"
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
// Retrieval info: CONNECT: @data 0 0 66 0 data0x 0 0 66 0
// Retrieval info: CONNECT: @data 0 0 66 66 data1x 0 0 66 0
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
// Retrieval info: CONNECT: result 0 0 66 0 @result 0 0 66 0
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_loopback.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_loopback.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_loopback.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_loopback.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_loopback_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL xgmii_loopback_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_EP.v
// Version : 2.4
//--
//-- Description: Endpoint Programmed I/O module.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO_EP #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
input clk,
input rst_n,
// AXIS TX
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_src_dsc,
//AXIS RX
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
output req_compl_o,
output compl_done_o,
input [15:0] cfg_completer_id,
input cfg_bus_mstr_enable
);
// Local wires
wire [10:0] rd_addr;
wire [3:0] rd_be;
wire [31:0] rd_data;
wire [10:0] wr_addr;
wire [7:0] wr_be;
wire [31:0] wr_data;
wire wr_en;
wire wr_busy;
wire req_compl;
wire req_compl_wd;
wire compl_done;
wire [2:0] req_tc;
wire req_td;
wire req_ep;
wire [1:0] req_attr;
wire [9:0] req_len;
wire [15:0] req_rid;
wire [7:0] req_tag;
wire [7:0] req_be;
wire [12:0] req_addr;
//
// ENDPOINT MEMORY : 8KB memory aperture implemented in FPGA BlockRAM(*)
//
PIO_EP_MEM_ACCESS EP_MEM (
.clk(clk), // I
.rst_n(rst_n), // I
// Read Port
.rd_addr_i(rd_addr), // I [10:0]
.rd_be_i(rd_be), // I [3:0]
.rd_data_o(rd_data), // O [31:0]
// Write Port
.wr_addr_i(wr_addr), // I [10:0]
.wr_be_i(wr_be), // I [7:0]
.wr_data_i(wr_data), // I [31:0]
.wr_en_i(wr_en), // I
.wr_busy_o(wr_busy) // O
);
//
// Local-Link Receive Controller
//
PIO_64_RX_ENGINE #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) EP_RX (
.clk(clk), // I
.rst_n(rst_n), // I
// AXIS RX
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tkeep( m_axis_rx_tkeep ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
// Handshake with Tx engine
.req_compl_o(req_compl), // O
.req_compl_wd_o(req_compl_wd), // O
.compl_done_i(compl_done), // I
.req_tc_o(req_tc), // O [2:0]
.req_td_o(req_td), // O
.req_ep_o(req_ep), // O
.req_attr_o(req_attr), // O [1:0]
.req_len_o(req_len), // O [9:0]
.req_rid_o(req_rid), // O [15:0]
.req_tag_o(req_tag), // O [7:0]
.req_be_o(req_be), // O [7:0]
.req_addr_o(req_addr), // O [12:0]
// Memory Write Port
.wr_addr_o(wr_addr), // O [10:0]
.wr_be_o(wr_be), // O [7:0]
.wr_data_o(wr_data), // O [31:0]
.wr_en_o(wr_en), // O
.wr_busy_i(wr_busy) // I
);
//
// Local-Link Transmit Controller
//
PIO_64_TX_ENGINE #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
)EP_TX(
.clk(clk), // I
.rst_n(rst_n), // I
// AXIS Tx
.s_axis_tx_tready( s_axis_tx_tready ), // I
.s_axis_tx_tdata( s_axis_tx_tdata ), // O
.s_axis_tx_tkeep( s_axis_tx_tkeep ), // O
.s_axis_tx_tlast( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid( s_axis_tx_tvalid ), // O
.tx_src_dsc( tx_src_dsc ), // O
// Handshake with Rx engine
.req_compl_i(req_compl), // I
.req_compl_wd_i(req_compl_wd), // I
.compl_done_o(compl_done), // 0
.req_tc_i(req_tc), // I [2:0]
.req_td_i(req_td), // I
.req_ep_i(req_ep), // I
.req_attr_i(req_attr), // I [1:0]
.req_len_i(req_len), // I [9:0]
.req_rid_i(req_rid), // I [15:0]
.req_tag_i(req_tag), // I [7:0]
.req_be_i(req_be), // I [7:0]
.req_addr_i(req_addr), // I [12:0]
// Read Port
.rd_addr_o(rd_addr), // O [10:0]
.rd_be_o(rd_be), // O [3:0]
.rd_data_i(rd_data), // I [31:0]
.completer_id_i(cfg_completer_id), // I [15:0]
.cfg_bus_mstr_enable_i(cfg_bus_mstr_enable) // I
);
assign req_compl_o = req_compl;
assign compl_done_o = compl_done;
endmodule // PIO_EP
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_BLACKBOX_V
`define SKY130_FD_SC_HVL__EINVP_BLACKBOX_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__einvp (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_8_V
`define SKY130_FD_SC_HD__FILL_8_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fill_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fill_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_BLACKBOX_V
`define SKY130_FD_SC_HDLL__CONB_BLACKBOX_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__conb (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31A_2_V
`define SKY130_FD_SC_LS__O31A_2_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o31a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o31a_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31A_2_V
|
/* verilator lint_off WIDTH */
/* verilator lint_off UNUSED */
/* verilator lint_off COMBDLY */
module arithbox (arithop,calc_sz,ci,co,af,ai,sa,sb,opa,opb,resa,cmp);
input [3:0] arithop;
input [3:0] calc_sz;
input [31:0] opa,opb;
output reg [31:0] resa;
input ci,ai;
output reg co,af,sa,sb,cmp;
wire [4:0] af2,af3,af4,af5;
assign af2 = opa[3:0]+opb[3:0];
assign af3 = opa[3:0]+opb[3:0]+ci;
assign af4 = opa[3:0]-opb[3:0];
assign af5 = opa[3:0]-opb[3:0]-ci;
always @(*)
case (arithop)
4'b0000 : if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] + opb[31:0]; sa<=opa[31]; sb<=opb[31]; af <= af2[4]; cmp <=0; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] + opb[15:0]; sa<=opa[15]; sb<=opb[15]; af <= af2[4]; resa[31:16] <= opa[31:16]; cmp <=0; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] + opb[ 7:0]; sa<=opa[ 7]; sb<=opb[ 7]; af <= af2[4]; resa[31: 8] <= opa[31: 8]; cmp <=0; end // add
4'b0001 : begin resa[31:0] <= opa[31:0] | opb[31:0]; sa<= 1 ; sb<= 0 ; af <= ai ; co <= 0; cmp <=0; end // or
4'b0010 : if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] + opb[31:0] + ci; sa<=opa[31]; sb<=opb[31]; af <= af3[4]; cmp <=0; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] + opb[15:0] + ci; sa<=opa[15]; sb<=opb[15]; af <= af3[4]; resa[31:16] <= opa[31:16]; cmp <=0; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] + opb[ 7:0] + ci; sa<=opa[ 7]; sb<=opb[ 7]; af <= af3[4]; resa[31: 8] <= opa[31: 8]; cmp <=0; end // adc
4'b0011 : if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] - opb[31:0] - ci; sa<=opa[31]; sb<=~opb[31];af <= af5[4]; cmp <=0; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] - opb[15:0] - ci; sa<=opa[15]; sb<=~opb[15];af <= af5[4]; resa[31:16] <= opa[31:16]; cmp <=0; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] - opb[ 7:0] - ci; sa<=opa[ 7]; sb<=~opb[ 7];af <= af5[4]; resa[31: 8] <= opa[31: 8]; cmp <=0; end // sbc & cmp
4'b0100 : begin resa[31:0] <= opa[31:0] & opb[31:0]; sa<=1 ; sb<= 0 ; af <= ai ; co <= 0; cmp <= 0; end // and
4'b0111 : begin
if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] - opb[31:0]; sa<=opa[31]; sb<=~opb[31]; af <= af4[4]; cmp <=1; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] - opb[15:0]; sa<=opa[15]; sb<=~opb[15]; af <= af4[4]; cmp <=1; resa[31:16] <= opa[31:16]; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] - opb[ 7:0]; sa<=opa[ 7]; sb<=~opb[ 7]; af <= af4[4]; cmp <=1; resa[31: 8] <= opa[31: 8]; end // sub
end
4'b0101 : if (calc_sz==4) begin {co,resa[31:0]} <= opa[31:0] - opb[31:0]; sa<=opa[31]; sb<=~opb[31]; af <= af4[4]; cmp <=0; end else
if (calc_sz==2) begin {co,resa[15:0]} <= opa[15:0] - opb[15:0]; sa<=opa[15]; sb<=~opb[15]; af <= af4[4]; cmp <=0; resa[31:16] <= opa[31:16]; end else
begin {co,resa[ 7:0]} <= opa[ 7:0] - opb[ 7:0]; sa<=opa[ 7]; sb<=~opb[ 7]; af <= af4[4]; cmp <=0; resa[31: 8] <= opa[31: 8]; end // sub
4'b0110 : begin resa[31:0] <= opa[31:0] ^ opb[31:0]; sa<= 1 ; sb<= 0 ; af <= ai; co <= 0; cmp <=0; end // xor
default : begin resa[31:0] <= opa[31:0] ; sa <= 0 ; sb<= 0 ; af <= ai; co <= ci; cmp <=1; end
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S4S_TB_V
`define SKY130_FD_SC_LP__DLYMETAL6S4S_TB_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlymetal6s4s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__dlymetal6s4s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S4S_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CONB_SYMBOL_V
`define SKY130_FD_SC_HD__CONB_SYMBOL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__conb (
//# {{data|Data Signals}}
output HI,
output LO
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CONB_SYMBOL_V
|
module ROM_TEST #(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 1,
// How much to increment the address to move 1 full data width.
parameter ADDRESS_STEP = 1,
// Max address for this memory
parameter MAX_ADDRESS = 63
) (
input rst,
input clk,
// Memory connection
input [DATA_WIDTH-1:0] read_data,
output reg [ADDR_WIDTH-1:0] read_address,
// INIT ROM
// When the memory is first initialized, it is expected to match the ROM
// port.
input [DATA_WIDTH-1:0] rom_read_data,
output reg [ADDR_WIDTH-1:0] rom_read_address,
// When an iteration is complete, success will be 1 for 1 cycle
output reg loop_complete,
// If an error occurs during a test, error will be 1 for each cycle
// with an error.
output reg error,
// error_state will contain the state of test FSM when the error occured.
output reg [7:0] error_state,
// error_address will be the read address where the error occurred.
output reg [ADDR_WIDTH-1:0] error_address,
// expected_data will be the read value expected.
output reg [DATA_WIDTH-1:0] expected_data,
// actual_data will be the read value read.
output reg [DATA_WIDTH-1:0] actual_data
);
reg [7:0] state;
reg [DATA_WIDTH-1:0] test_value;
reg [1:0] delay = 1'b0;
localparam START = 8'd1,
VERIFY_INIT = 8'd2;
always @(posedge clk) begin
if(rst) begin
state <= START;
error <= 0;
end else begin
case(state)
START: begin
loop_complete <= 0;
state <= VERIFY_INIT;
read_address <= 0;
rom_read_address <= 0;
error <= 0;
end
VERIFY_INIT: begin
if(delay == 0) begin
if(rom_read_data != read_data) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= rom_read_data;
actual_data <= read_data;
end else begin
error <= 0;
end
end
else if (delay == 1) begin
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
rom_read_address <= rom_read_address + ADDRESS_STEP;
end else begin
rom_read_address <= 0;
read_address <= 0;
loop_complete <= 1;
state <= START;
end
end
delay <= delay + 1;
end
endcase
end
end
endmodule
|
/*
* This file was generated by the scsynth tool, and is availablefor use under
* the MIT license. More information can be found at
* https://github.com/arminalaghi/scsynth/
*/
module MReSC_wrapper_example( //handles stochastic/binary conversion for ReSC
input [11:0] x_1_bin, //binary value of input 1
input [11:0] x_2_bin, //binary value of input 2
input [11:0] x_3_bin, //binary value of input 3
input start, //signal to start counting
output reg done, //signal that a number has been computed
output reg [11:0] z_bin, //binary value of output
input clk,
input reset
);
//the weights of the Bernstein polynomial
reg [11:0] w0_bin = 12'd4016;
reg [11:0] w1_bin = 12'd886;
reg [11:0] w2_bin = 12'd3400;
reg [11:0] w3_bin = 12'd2597;
reg [11:0] w4_bin = 12'd3915;
reg [11:0] w5_bin = 12'd2013;
reg [11:0] w6_bin = 12'd1549;
reg [11:0] w7_bin = 12'd689;
reg [11:0] w8_bin = 12'd3510;
reg [11:0] w9_bin = 12'd2941;
reg [11:0] w10_bin = 12'd926;
reg [11:0] w11_bin = 12'd667;
reg [11:0] w12_bin = 12'd3308;
reg [11:0] w13_bin = 12'd2028;
reg [11:0] w14_bin = 12'd3058;
reg [11:0] w15_bin = 12'd1473;
reg [11:0] w16_bin = 12'd1903;
reg [11:0] w17_bin = 12'd424;
reg [11:0] w18_bin = 12'd2207;
reg [11:0] w19_bin = 12'd516;
reg [11:0] w20_bin = 12'd1977;
reg [11:0] w21_bin = 12'd48;
reg [11:0] w22_bin = 12'd1547;
reg [11:0] w23_bin = 12'd1191;
reg [11:0] w24_bin = 12'd1791;
reg [11:0] w25_bin = 12'd2198;
reg [11:0] w26_bin = 12'd2759;
reg [11:0] w27_bin = 12'd3354;
reg [11:0] w28_bin = 12'd3202;
reg [11:0] w29_bin = 12'd3623;
reg [11:0] w30_bin = 12'd3602;
reg [11:0] w31_bin = 12'd1773;
reg [11:0] w32_bin = 12'd795;
reg [11:0] w33_bin = 12'd3687;
reg [11:0] w34_bin = 12'd3720;
reg [11:0] w35_bin = 12'd1179;
reg [11:0] w36_bin = 12'd105;
reg [11:0] w37_bin = 12'd1164;
reg [11:0] w38_bin = 12'd3313;
reg [11:0] w39_bin = 12'd126;
reg [11:0] w40_bin = 12'd3433;
reg [11:0] w41_bin = 12'd3055;
reg [11:0] w42_bin = 12'd4047;
reg [11:0] w43_bin = 12'd363;
reg [11:0] w44_bin = 12'd3902;
reg [11:0] w45_bin = 12'd1602;
reg [11:0] w46_bin = 12'd3629;
reg [11:0] w47_bin = 12'd2363;
reg [11:0] w48_bin = 12'd1906;
reg [11:0] w49_bin = 12'd911;
reg [11:0] w50_bin = 12'd319;
reg [11:0] w51_bin = 12'd553;
reg [11:0] w52_bin = 12'd40;
reg [11:0] w53_bin = 12'd3336;
reg [11:0] w54_bin = 12'd1319;
reg [11:0] w55_bin = 12'd3993;
reg [11:0] w56_bin = 12'd3628;
reg [11:0] w57_bin = 12'd956;
reg [11:0] w58_bin = 12'd119;
reg [11:0] w59_bin = 12'd1159;
reg [11:0] w60_bin = 12'd198;
reg [11:0] w61_bin = 12'd1292;
reg [11:0] w62_bin = 12'd979;
reg [11:0] w63_bin = 12'd2858;
reg [11:0] w64_bin = 12'd2368;
reg [11:0] w65_bin = 12'd2136;
reg [11:0] w66_bin = 12'd3679;
reg [11:0] w67_bin = 12'd3205;
reg [11:0] w68_bin = 12'd3081;
reg [11:0] w69_bin = 12'd244;
reg [11:0] w70_bin = 12'd746;
reg [11:0] w71_bin = 12'd220;
wire [2:0] x_1_stoch;
wire [4:0] x_2_stoch;
wire [1:0] x_3_stoch;
wire [71:0] w_stoch;
wire z_stoch;
wire init;
wire running;
//RNGs for binary->stochastic conversion
wire [11:0] randx_1_0;
LFSR_12_bit_added_zero_example rand_gen_x_1_0 (
.seed (12'd0),
.data (randx_1_0),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_1_stoch[0] = randx_1_0 < x_1_bin;
wire [11:0] randx_1_1;
LFSR_12_bit_added_zero_example rand_gen_x_1_1 (
.seed (12'd585),
.data (randx_1_1),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_1_stoch[1] = randx_1_1 < x_1_bin;
wire [11:0] randx_1_2;
LFSR_12_bit_added_zero_example rand_gen_x_1_2 (
.seed (12'd1170),
.data (randx_1_2),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_1_stoch[2] = randx_1_2 < x_1_bin;
wire [11:0] randx_2_0;
LFSR_12_bit_added_zero_example rand_gen_x_2_0 (
.seed (12'd0),
.data (randx_2_0),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_2_stoch[0] = randx_2_0 < x_2_bin;
wire [11:0] randx_2_1;
LFSR_12_bit_added_zero_example rand_gen_x_2_1 (
.seed (12'd372),
.data (randx_2_1),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_2_stoch[1] = randx_2_1 < x_2_bin;
wire [11:0] randx_2_2;
LFSR_12_bit_added_zero_example rand_gen_x_2_2 (
.seed (12'd745),
.data (randx_2_2),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_2_stoch[2] = randx_2_2 < x_2_bin;
wire [11:0] randx_2_3;
LFSR_12_bit_added_zero_example rand_gen_x_2_3 (
.seed (12'd1117),
.data (randx_2_3),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_2_stoch[3] = randx_2_3 < x_2_bin;
wire [11:0] randx_2_4;
LFSR_12_bit_added_zero_example rand_gen_x_2_4 (
.seed (12'd1489),
.data (randx_2_4),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_2_stoch[4] = randx_2_4 < x_2_bin;
wire [11:0] randx_3_0;
LFSR_12_bit_added_zero_example rand_gen_x_3_0 (
.seed (12'd0),
.data (randx_3_0),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_3_stoch[0] = randx_3_0 < x_3_bin;
wire [11:0] randx_3_1;
LFSR_12_bit_added_zero_example rand_gen_x_3_1 (
.seed (12'd819),
.data (randx_3_1),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign x_3_stoch[1] = randx_3_1 < x_3_bin;
wire [11:0] randw;
LFSR_12_bit_added_zero_example rand_gen_w (
.seed (12'd2731),
.data (randw),
.enable (running),
.restart (init),
.clk (clk),
.reset (reset)
);
assign w_stoch[0] = randw < w0_bin;
assign w_stoch[1] = randw < w1_bin;
assign w_stoch[2] = randw < w2_bin;
assign w_stoch[3] = randw < w3_bin;
assign w_stoch[4] = randw < w4_bin;
assign w_stoch[5] = randw < w5_bin;
assign w_stoch[6] = randw < w6_bin;
assign w_stoch[7] = randw < w7_bin;
assign w_stoch[8] = randw < w8_bin;
assign w_stoch[9] = randw < w9_bin;
assign w_stoch[10] = randw < w10_bin;
assign w_stoch[11] = randw < w11_bin;
assign w_stoch[12] = randw < w12_bin;
assign w_stoch[13] = randw < w13_bin;
assign w_stoch[14] = randw < w14_bin;
assign w_stoch[15] = randw < w15_bin;
assign w_stoch[16] = randw < w16_bin;
assign w_stoch[17] = randw < w17_bin;
assign w_stoch[18] = randw < w18_bin;
assign w_stoch[19] = randw < w19_bin;
assign w_stoch[20] = randw < w20_bin;
assign w_stoch[21] = randw < w21_bin;
assign w_stoch[22] = randw < w22_bin;
assign w_stoch[23] = randw < w23_bin;
assign w_stoch[24] = randw < w24_bin;
assign w_stoch[25] = randw < w25_bin;
assign w_stoch[26] = randw < w26_bin;
assign w_stoch[27] = randw < w27_bin;
assign w_stoch[28] = randw < w28_bin;
assign w_stoch[29] = randw < w29_bin;
assign w_stoch[30] = randw < w30_bin;
assign w_stoch[31] = randw < w31_bin;
assign w_stoch[32] = randw < w32_bin;
assign w_stoch[33] = randw < w33_bin;
assign w_stoch[34] = randw < w34_bin;
assign w_stoch[35] = randw < w35_bin;
assign w_stoch[36] = randw < w36_bin;
assign w_stoch[37] = randw < w37_bin;
assign w_stoch[38] = randw < w38_bin;
assign w_stoch[39] = randw < w39_bin;
assign w_stoch[40] = randw < w40_bin;
assign w_stoch[41] = randw < w41_bin;
assign w_stoch[42] = randw < w42_bin;
assign w_stoch[43] = randw < w43_bin;
assign w_stoch[44] = randw < w44_bin;
assign w_stoch[45] = randw < w45_bin;
assign w_stoch[46] = randw < w46_bin;
assign w_stoch[47] = randw < w47_bin;
assign w_stoch[48] = randw < w48_bin;
assign w_stoch[49] = randw < w49_bin;
assign w_stoch[50] = randw < w50_bin;
assign w_stoch[51] = randw < w51_bin;
assign w_stoch[52] = randw < w52_bin;
assign w_stoch[53] = randw < w53_bin;
assign w_stoch[54] = randw < w54_bin;
assign w_stoch[55] = randw < w55_bin;
assign w_stoch[56] = randw < w56_bin;
assign w_stoch[57] = randw < w57_bin;
assign w_stoch[58] = randw < w58_bin;
assign w_stoch[59] = randw < w59_bin;
assign w_stoch[60] = randw < w60_bin;
assign w_stoch[61] = randw < w61_bin;
assign w_stoch[62] = randw < w62_bin;
assign w_stoch[63] = randw < w63_bin;
assign w_stoch[64] = randw < w64_bin;
assign w_stoch[65] = randw < w65_bin;
assign w_stoch[66] = randw < w66_bin;
assign w_stoch[67] = randw < w67_bin;
assign w_stoch[68] = randw < w68_bin;
assign w_stoch[69] = randw < w69_bin;
assign w_stoch[70] = randw < w70_bin;
assign w_stoch[71] = randw < w71_bin;
MReSC_example ReSC (
.x_1 (x_1_stoch),
.x_2 (x_2_stoch),
.x_3 (x_3_stoch),
.w (w_stoch),
.z (z_stoch)
);
reg [11:0] count; //count clock cycles
wire [11:0] neg_one;
assign neg_one = -1;
//Finite state machine. States:
//0: finished, in need of resetting
//1: initialized, start counting when start signal falls
//2: running
reg [1:0] cs; //current FSM state
reg [1:0] ns; //next FSM state
assign init = cs == 1;
assign running = cs == 2;
always @(posedge clk or posedge reset) begin
if (reset) cs <= 0;
else begin
cs <= ns;
if (running) begin
if (count == neg_one) done <= 1;
count <= count + 1;
z_bin <= z_bin + z_stoch;
end
end
end
always @(*) begin
case (cs)
0: if (start) ns = 1; else ns = 0;
1: if (start) ns = 1; else ns = 2;
2: if (done) ns = 0; else ns = 2;
default ns = 0;
endcase
end
always @(posedge init) begin
count <= 0;
z_bin <= 0;
done <= 0;
end
endmodule
|
`timescale 1ns / 1ns
module eth_rx
(input c, // must be the 50 MHz RMII reference clock
input [1:0] phy_rxd,
input phy_rxdv,
output [7:0] d,
output dv,
output erx); // end of RX
wire [1:0] rmii_d;
sync #(2) rmii_d_sync_r
(.in(phy_rxd), .clk(c), .out(rmii_d));
wire rmii_dv;
sync rmii_dv_sync_r
(.in(phy_rxdv), .clk(c), .out(rmii_dv));
wire rmii_dv_d1;
d1 rxdv_d1_r(.d(rmii_dv), .c(c), .q(rmii_dv_d1));
wire [7:0] rxd_shift;
r #(8) rxd_shift_r
(.c(c), .d({rmii_d, rxd_shift[7:2]}), .rst(1'b0), .en(1'b1), .q(rxd_shift));
wire shift_cnt_rst;
wire [1:0] shift_cnt;
r #(2) shift_cnt_r
(.c(c), .d(shift_cnt+1'b1), .en(1'b1), .rst(shift_cnt_rst), .q(shift_cnt));
assign d = rxd_shift;
localparam SW = 3, CW = 3;
localparam ST_IDLE = 3'd0;
localparam ST_PREAMBLE = 3'd1;
localparam ST_PAYLOAD = 3'd2;
localparam ST_STOP = 3'd3;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
always @* begin
case (state)
ST_IDLE:
if (rmii_dv && d == 8'h55) ctrl = { ST_PREAMBLE, 3'b000 };
else ctrl = { ST_IDLE , 3'b000 };
ST_PREAMBLE:
if (rmii_dv && d == 8'h55) ctrl = { ST_PREAMBLE, 3'b000 };
else if (rmii_dv && d == 8'hd5) ctrl = { ST_PAYLOAD , 3'b100 };
else ctrl = { ST_IDLE , 3'b000 };
ST_PAYLOAD:
if (rmii_dv | rmii_dv_d1) ctrl = { ST_PAYLOAD , 3'b001 };
else ctrl = { ST_STOP , 3'b010 };
ST_STOP: ctrl = { ST_IDLE , 3'b000 }; // fcs ?
default: ctrl = { ST_IDLE , 3'b000 };
endcase
end
assign dv = state == ST_PAYLOAD & &shift_cnt;
assign erx = ctrl[1];
assign shift_cnt_rst = ctrl[2];
endmodule
`ifdef test_eth_rx
module eth_rx_tb();
wire c;
sim_clk #(50) clk_50(c);
wire [1:0] rmii_txd, rmii_rxd;
wire rmii_rst, mdc, mdio;
wire rmii_txen, rmii_rxdv;
fake_rmii_phy #(.INPUT_FILE_NAME("tb_packets.dat")) phy
(.refclk(c), .rst(rmii_rst), .mdc(mdc), .mdio(mdio),
.txd(rmii_txd), .txen(rmii_txen),
.rxd(rmii_rxd), .rxdv(rmii_rxdv));
wire [7:0] rxd;
wire rxdv, erx;
eth_rx dut
(.c(c), .phy_rxd(rmii_rxd), .phy_rxdv(rmii_rxdv),
.d(rxd), .dv(rxdv), .erx(erx));
initial begin
$dumpfile("eth_rx.lxt");
$dumpvars();
#100000;
$finish();
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr ();
// Module supplies
supply1 VPWR ;
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_V
|
(** * Induction: Proof by Induction *)
(* ################################################################# *)
(** * Separate Compilation *)
(** Before getting started on this chapter, we need to import
all of our definitions from the previous chapter: *)
From LF Require Export Basics.
(** For this [Require Export] command to work, Coq needs to be
able to find a compiled version of [Basics.v], called [Basics.vo],
in a directory associated with the prefix [LF]. This file is
analogous to the [.class] files compiled from [.java] source files
and the [.o] files compiled from [.c] files.
First create a file named [_CoqProject] containing the following
line (if you obtained the whole volume "Logical Foundations" as a
single archive, a [_CoqProject] should already exist and you can
skip this step):
[-Q . LF]
This maps the current directory ("[.]", which contains [Basics.v],
[Induction.v], etc.) to the prefix (or "logical directory")
"[LF]". PG and CoqIDE read [_CoqProject] automatically, so they
know to where to look for the file [Basics.vo] corresponding to
the library [LF.Basics].
Once [_CoqProject] is thus created, there are various ways to
build [Basics.vo]:
- In Proof General: The compilation can be made to happen
automatically when you submit the [Require] line above to PG,
by setting the emacs variable [coq-compile-before-require] to
[t]. You can also use the menu option "Coq -> Auto
Compilation -> Compile Before Require".
- In CoqIDE: Open [Basics.v]; then, in the "Compile" menu, click
on "Compile Buffer".
- From the command line: Generate a [Makefile] using the
[coq_makefile] utility, that comes installed with Coq (if you
obtained the whole volume as a single archive, a [Makefile]
should already exist and you can skip this step):
[coq_makefile -f _CoqProject *.v -o Makefile]
Note: You should rerun that command whenever you add or remove
Coq files to the directory.
Now you can compile [Basics.v] by running [make] with the
corresponding [.vo] file as a target:
[make Basics.vo]
All files in the directory can be compiled by giving no
arguments:
[make]
Under the hood, [make] uses the Coq compiler, [coqc]. You can
also run [coqc] directly:
[coqc -Q . LF Basics.v]
But [make] also calculates dependencies between source files to
compile them in the right order, so [make] should generally be
prefered over explicit [coqc].
If you have trouble (e.g., if you get complaints about missing
identifiers later in the file), it may be because the "load path"
for Coq is not set up correctly. The [Print LoadPath.] command
may be helpful in sorting out such issues.
In particular, if you see a message like
[Compiled library Foo makes inconsistent assumptions over
library Bar]
check whether you have multiple installations of Coq on your
machine. It may be that commands (like [coqc]) that you execute
in a terminal window are getting a different version of Coq than
commands executed by Proof General or CoqIDE.
- Another common reason is that the library [Bar] was modified and
recompiled without also recompiling [Foo] which depends on it.
Recompile [Foo], or everything if too many files are
affected. (Using the third solution above: [make clean; make].)
One more tip for CoqIDE users: If you see messages like [Error:
Unable to locate library Basics], a likely reason is
inconsistencies between compiling things _within CoqIDE_ vs _using
[coqc] from the command line_. This typically happens when there
are two incompatible versions of [coqc] installed on your
system (one associated with CoqIDE, and one associated with [coqc]
from the terminal). The workaround for this situation is
compiling using CoqIDE only (i.e. choosing "make" from the menu),
and avoiding using [coqc] directly at all. *)
(* ################################################################# *)
(** * Proof by Induction *)
(** We can prove that [0] is a neutral element for [+] on the left
using just [reflexivity]. But the proof that it is also a neutral
element on the _right_ ... *)
Theorem plus_n_O_firsttry : forall n:nat,
n = n + 0.
(** ... can't be done in the same simple way. Just applying
[reflexivity] doesn't work, since the [n] in [n + 0] is an arbitrary
unknown number, so the [match] in the definition of [+] can't be
simplified. *)
Proof.
intros n.
simpl. (* Does nothing! *)
Abort.
(** And reasoning by cases using [destruct n] doesn't get us much
further: the branch of the case analysis where we assume [n = 0]
goes through fine, but in the branch where [n = S n'] for some [n'] we
get stuck in exactly the same way. *)
Theorem plus_n_O_secondtry : forall n:nat,
n = n + 0.
Proof.
intros n. destruct n as [| n'] eqn:E.
- (* n = 0 *)
reflexivity. (* so far so good... *)
- (* n = S n' *)
simpl. (* ...but here we are stuck again *)
Abort.
(** We could use [destruct n'] to get one step further, but,
since [n] can be arbitrarily large, we'll never get all the there
if we just go on like this. *)
(** To prove interesting facts about numbers, lists, and other
inductively defined sets, we often need a more powerful reasoning
principle: _induction_.
Recall (from high school, a discrete math course, etc.) the
_principle of induction over natural numbers_: If [P(n)] is some
proposition involving a natural number [n] and we want to show
that [P] holds for all numbers [n], we can reason like this:
- show that [P(O)] holds;
- show that, for any [n'], if [P(n')] holds, then so does
[P(S n')];
- conclude that [P(n)] holds for all [n].
In Coq, the steps are the same: we begin with the goal of proving
[P(n)] for all [n] and break it down (by applying the [induction]
tactic) into two separate subgoals: one where we must show [P(O)]
and another where we must show [P(n') -> P(S n')]. Here's how
this works for the theorem at hand: *)
Theorem plus_n_O : forall n:nat, n = n + 0.
Proof.
intros n. induction n as [| n' IHn'].
- (* n = 0 *) reflexivity.
- (* n = S n' *) simpl. rewrite <- IHn'. reflexivity. Qed.
(** Like [destruct], the [induction] tactic takes an [as...]
clause that specifies the names of the variables to be introduced
in the subgoals. Since there are two subgoals, the [as...] clause
has two parts, separated by [|]. (Strictly speaking, we can omit
the [as...] clause and Coq will choose names for us. In practice,
this is a bad idea, as Coq's automatic choices tend to be
confusing.)
In the first subgoal, [n] is replaced by [0]. No new variables
are introduced (so the first part of the [as...] is empty), and
the goal becomes [0 = 0 + 0], which follows by simplification.
In the second subgoal, [n] is replaced by [S n'], and the
assumption [n' + 0 = n'] is added to the context with the name
[IHn'] (i.e., the Induction Hypothesis for [n']). These two names
are specified in the second part of the [as...] clause. The goal
in this case becomes [S n' = (S n') + 0], which simplifies to
[S n' = S (n' + 0)], which in turn follows from [IHn']. *)
Theorem minus_n_n : forall n,
minus n n = 0.
Proof.
(* WORKED IN CLASS *)
intros n. induction n as [| n' IHn'].
- (* n = 0 *)
simpl. reflexivity.
- (* n = S n' *)
simpl. rewrite -> IHn'. reflexivity. Qed.
(** (The use of the [intros] tactic in these proofs is actually
redundant. When applied to a goal that contains quantified
variables, the [induction] tactic will automatically move them
into the context as needed.) *)
(** **** Exercise: 2 stars, standard, especially useful (basic_induction)
Prove the following using induction. You might need previously
proven results. *)
Theorem mult_0_r : forall n:nat,
n * 0 = 0.
Proof.
intros n.
induction n as [|n' IHn'].
- simpl. reflexivity.
- simpl. rewrite -> IHn'. reflexivity.
Qed.
Theorem plus_n_Sm : forall n m : nat,
S (n + m) = n + (S m).
Proof.
intros n m.
induction n as [|n' IHn'].
- simpl. reflexivity.
- simpl. rewrite -> IHn'. reflexivity.
Qed.
Theorem plus_comm : forall n m : nat,
n + m = m + n.
Proof.
intros n m.
induction n as [|n' IHn'].
- simpl. rewrite <- plus_n_O. reflexivity.
- simpl. rewrite -> IHn'. rewrite <- plus_n_Sm. reflexivity.
Qed.
Theorem plus_assoc : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
intros n m p.
induction n as [|n' IHn'].
- simpl. reflexivity.
- simpl. rewrite <- IHn'. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard (double_plus)
Consider the following function, which doubles its argument: *)
Fixpoint double (n:nat) :=
match n with
| O => O
| S n' => S (S (double n'))
end.
(** Use induction to prove this simple fact about [double]: *)
Lemma double_plus : forall n, double n = n + n .
Proof.
intros n.
induction n as [|n' IHn'].
- reflexivity.
- simpl. rewrite -> IHn'. rewrite -> plus_n_Sm. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (evenb_S)
One inconvenient aspect of our definition of [evenb n] is the
recursive call on [n - 2]. This makes proofs about [evenb n]
harder when done by induction on [n], since we may need an
induction hypothesis about [n - 2]. The following lemma gives an
alternative characterization of [evenb (S n)] that works better
with induction: *)
Theorem evenb_S : forall n : nat,
evenb (S n) = negb (evenb n).
Proof.
intros n.
induction n as [|n' IHn'].
- simpl. reflexivity.
- rewrite -> IHn'. rewrite -> negb_involutive. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star, standard, optional (destruct_induction)
Briefly explain the difference between the tactics [destruct] and
[induction].
- destruct only destruct a variable of inductive type into its
constructors.
- induction, on top of that, introduces an extra assumption about the
theorem hold for the preceding iteration.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_destruct_induction : option (nat*string) := None.
(** [] *)
(* ################################################################# *)
(** * Proofs Within Proofs *)
(** In Coq, as in informal mathematics, large proofs are often
broken into a sequence of theorems, with later proofs referring to
earlier theorems. But sometimes a proof will require some
miscellaneous fact that is too trivial and of too little general
interest to bother giving it its own top-level name. In such
cases, it is convenient to be able to simply state and prove the
needed "sub-theorem" right at the point where it is used. The
[assert] tactic allows us to do this. *)
Theorem mult_0_plus' : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
assert (H: 0 + n = n). { reflexivity. }
rewrite -> H.
reflexivity. Qed.
(** The [assert] tactic introduces two sub-goals. The first is
the assertion itself; by prefixing it with [H:] we name the
assertion [H]. (We can also name the assertion with [as] just as
we did above with [destruct] and [induction], i.e., [assert (0 + n
= n) as H].) Note that we surround the proof of this assertion
with curly braces [{ ... }], both for readability and so that,
when using Coq interactively, we can see more easily when we have
finished this sub-proof. The second goal is the same as the one
at the point where we invoke [assert] except that, in the context,
we now have the assumption [H] that [0 + n = n]. That is,
[assert] generates one subgoal where we must prove the asserted
fact and a second subgoal where we can use the asserted fact to
make progress on whatever we were trying to prove in the first
place. *)
(** For example, suppose we want to prove that [(n + m) + (p + q)
= (m + n) + (p + q)]. The only difference between the two sides of
the [=] is that the arguments [m] and [n] to the first inner [+]
are swapped, so it seems we should be able to use the
commutativity of addition ([plus_comm]) to rewrite one into the
other. However, the [rewrite] tactic is not very smart about
_where_ it applies the rewrite. There are three uses of [+] here,
and it turns out that doing [rewrite -> plus_comm] will affect
only the _outer_ one... *)
Theorem plus_rearrange_firsttry : forall n m p q : nat,
(n + m) + (p + q) = (m + n) + (p + q).
Proof.
intros n m p q.
(* We just need to swap (n + m) for (m + n)... seems
like plus_comm should do the trick! *)
rewrite -> plus_comm.
(* Doesn't work... Coq rewrites the wrong plus! :-( *)
Abort.
(** To use [plus_comm] at the point where we need it, we can introduce
a local lemma stating that [n + m = m + n] (for the _particular_ [m]
and [n] that we are talking about here), prove this lemma using
[plus_comm], and then use it to do the desired rewrite. *)
Theorem plus_rearrange : forall n m p q : nat,
(n + m) + (p + q) = (m + n) + (p + q).
Proof.
intros n m p q.
assert (H: n + m = m + n).
{ rewrite -> plus_comm. reflexivity. }
rewrite -> H. reflexivity. Qed.
(* ################################################################# *)
(** * Formal vs. Informal Proof *)
(** "_Informal proofs are algorithms; formal proofs are code_." *)
(** What constitutes a successful proof of a mathematical claim?
The question has challenged philosophers for millennia, but a
rough and ready definition could be this: A proof of a
mathematical proposition [P] is a written (or spoken) text that
instills in the reader or hearer the certainty that [P] is true --
an unassailable argument for the truth of [P]. That is, a proof
is an act of communication.
Acts of communication may involve different sorts of readers. On
one hand, the "reader" can be a program like Coq, in which case
the "belief" that is instilled is that [P] can be mechanically
derived from a certain set of formal logical rules, and the proof
is a recipe that guides the program in checking this fact. Such
recipes are _formal_ proofs.
Alternatively, the reader can be a human being, in which case the
proof will be written in English or some other natural language,
and will thus necessarily be _informal_. Here, the criteria for
success are less clearly specified. A "valid" proof is one that
makes the reader believe [P]. But the same proof may be read by
many different readers, some of whom may be convinced by a
particular way of phrasing the argument, while others may not be.
Some readers may be particularly pedantic, inexperienced, or just
plain thick-headed; the only way to convince them will be to make
the argument in painstaking detail. But other readers, more
familiar in the area, may find all this detail so overwhelming
that they lose the overall thread; all they want is to be told the
main ideas, since it is easier for them to fill in the details for
themselves than to wade through a written presentation of them.
Ultimately, there is no universal standard, because there is no
single way of writing an informal proof that is guaranteed to
convince every conceivable reader.
In practice, however, mathematicians have developed a rich set of
conventions and idioms for writing about complex mathematical
objects that -- at least within a certain community -- make
communication fairly reliable. The conventions of this stylized
form of communication give a fairly clear standard for judging
proofs good or bad.
Because we are using Coq in this course, we will be working
heavily with formal proofs. But this doesn't mean we can
completely forget about informal ones! Formal proofs are useful
in many ways, but they are _not_ very efficient ways of
communicating ideas between human beings. *)
(** For example, here is a proof that addition is associative: *)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof. intros n m p. induction n as [| n' IHn']. reflexivity.
simpl. rewrite -> IHn'. reflexivity. Qed.
(** Coq is perfectly happy with this. For a human, however, it
is difficult to make much sense of it. We can use comments and
bullets to show the structure a little more clearly... *)
Theorem plus_assoc'' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
intros n m p. induction n as [| n' IHn'].
- (* n = 0 *)
reflexivity.
- (* n = S n' *)
simpl. rewrite -> IHn'. reflexivity. Qed.
(** ... and if you're used to Coq you may be able to step
through the tactics one after the other in your mind and imagine
the state of the context and goal stack at each point, but if the
proof were even a little bit more complicated this would be next
to impossible.
A (pedantic) mathematician might write the proof something like
this: *)
(** - _Theorem_: For any [n], [m] and [p],
n + (m + p) = (n + m) + p.
_Proof_: By induction on [n].
- First, suppose [n = 0]. We must show that
0 + (m + p) = (0 + m) + p.
This follows directly from the definition of [+].
- Next, suppose [n = S n'], where
n' + (m + p) = (n' + m) + p.
We must now show that
(S n') + (m + p) = ((S n') + m) + p.
By the definition of [+], this follows from
S (n' + (m + p)) = S ((n' + m) + p),
which is immediate from the induction hypothesis. _Qed_. *)
(** The overall form of the proof is basically similar, and of
course this is no accident: Coq has been designed so that its
[induction] tactic generates the same sub-goals, in the same
order, as the bullet points that a mathematician would write. But
there are significant differences of detail: the formal proof is
much more explicit in some ways (e.g., the use of [reflexivity])
but much less explicit in others (in particular, the "proof state"
at any given point in the Coq proof is completely implicit,
whereas the informal proof reminds the reader several times where
things stand). *)
(** **** Exercise: 2 stars, advanced, especially useful (plus_comm_informal)
Translate your solution for [plus_comm] into an informal proof:
Theorem: Addition is commutative. In other words,
for all natural number n, m, n + m = m + n.
Proof: By induction on n,
- First, suppose n = 0, we need to prove 0 + m = m + 0.
By definition of +, the LHS can be written as m.
By plus_n_O, m = m + 0.
- Next, suppose n' + m = m + n', we now show S n' + m = m + S n'.
By definition of +, the LHS can be written as S (n' + m).
By inductive hypothesis, the LHS can be writen as S (m + n'),
By plus_n_Sm, S (m + n') = m + S n'.
Qed.
( for reference only:
Theorem plus_comm : forall n m : nat,
n + m = m + n.
Proof.
intros n m.
induction n as [|n' IHn'].
- simpl. rewrite <- plus_n_O. reflexivity.
- simpl. rewrite -> IHn'. rewrite <- plus_n_Sm. reflexivity.
Qed.
)
*)
(* Do not modify the following line: *)
Definition manual_grade_for_plus_comm_informal : option (nat*string) := None.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (eqb_refl_informal)
Write an informal proof of the following theorem, using the
informal proof of [plus_assoc] as a model. Don't just
paraphrase the Coq tactics into English!
Theorem: [true = n =? n] for any [n].
Proof: By induction on n:
- For n = 0, 0 = 0 holds.
- For n = S n', suppose true = n' =? n'.
We need to prove true = S n' =? S n'
By definition of =?, S n' =? S n' = n' =? n'.
By inductive assumption, true = n' =? n'. Thus finishes the proof.
Qed.
*)
(** [] *)
(* ################################################################# *)
(** * More Exercises *)
(** **** Exercise: 3 stars, standard, especially useful (mult_comm)
Use [assert] to help prove [plus_swap]. You don't need to
use induction yet. *)
Theorem plus_swap : forall n m p : nat,
n + (m + p) = m + (n + p).
Proof.
intros n m p.
rewrite <- plus_comm.
rewrite <- plus_assoc.
assert (H: p + n = n + p). { rewrite <- plus_comm. reflexivity. }
rewrite <- H.
reflexivity.
Qed.
(** Now prove commutativity of multiplication. You will probably
want to define and prove a "helper" theorem to be used
in the proof of this one. Hint: what is [n * (1 + k)]? *)
Lemma mult_m_Sn: forall m n : nat,
m * S n = m + m * n.
Proof.
intros m n.
induction m.
- simpl. reflexivity.
- simpl. rewrite -> plus_assoc. rewrite -> IHm. rewrite -> plus_assoc.
assert (H: n + (m + m * n) = m + (n + m * n)).
{ rewrite -> plus_swap. reflexivity. }
rewrite <- plus_assoc. rewrite <- plus_assoc.
rewrite -> H.
reflexivity.
Qed.
Theorem mult_comm : forall m n : nat,
m * n = n * m.
Proof.
intros m n.
induction n.
- simpl. rewrite -> mult_0_r. reflexivity.
- simpl. rewrite -> mult_m_Sn. rewrite IHn. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (more_exercises)
Take a piece of paper. For each of the following theorems, first
_think_ about whether (a) it can be proved using only
simplification and rewriting, (b) it also requires case
analysis ([destruct]), or (c) it also requires induction. Write
down your prediction. Then fill in the proof. (There is no need
to turn in your piece of paper; this is just to encourage you to
reflect before you hack!) *)
Check leb.
(* should be provable using induction *)
Theorem leb_refl : forall n:nat,
true = (n <=? n).
Proof.
intros n.
induction n.
- reflexivity.
- simpl. rewrite IHn. reflexivity.
Qed.
(* should be provable with simplification *)
Theorem zero_nbeq_S : forall n:nat,
0 =? (S n) = false.
Proof.
intros.
simpl. reflexivity.
Qed.
(* should be provable by destructing b *)
Theorem andb_false_r : forall b : bool,
andb b false = false.
Proof.
intros.
destruct b.
- simpl. reflexivity.
- simpl. reflexivity.
Qed.
(* should be provable by induction on p *)
Theorem plus_ble_compat_l : forall n m p : nat,
n <=? m = true -> (p + n) <=? (p + m) = true.
Proof.
intros.
induction p.
- simpl. rewrite H. simpl. reflexivity.
- simpl. rewrite IHp. reflexivity.
Qed.
(* should be proved by simplification *)
Theorem S_nbeq_0 : forall n:nat,
(S n) =? 0 = false.
Proof. intros. simpl. reflexivity. Qed.
(* should be proved by induction (or perhaps simplification is enough) *)
Theorem mult_1_l : forall n:nat, 1 * n = n.
Proof. intros. simpl. rewrite <- plus_n_O. reflexivity. Qed.
(* just destruct everything *)
Theorem all3_spec : forall b c : bool,
orb
(andb b c)
(orb (negb b)
(negb c))
= true.
Proof.
destruct b.
- destruct c.
+ simpl. reflexivity.
+ simpl. reflexivity.
- destruct c.
+ simpl. reflexivity.
+ simpl. reflexivity.
Qed.
(* induction *)
Theorem mult_plus_distr_r : forall n m p : nat,
(n + m) * p = (n * p) + (m * p).
Proof.
intros n m p.
induction p.
- rewrite -> mult_0_r. rewrite -> mult_0_r. rewrite -> mult_0_r. reflexivity.
- rewrite -> mult_m_Sn. rewrite -> mult_m_Sn. rewrite -> mult_m_Sn.
assert (H: (n+n*p) + (m+m*p) = (n+m) + (n*p+m*p)).
{ rewrite -> plus_assoc.
assert (H1: n + n*p + m = n + (n*p + m)). { rewrite plus_assoc. reflexivity. }
rewrite H1.
assert (H2: n*p + m = m + n*p). { rewrite <- plus_comm. reflexivity. }
rewrite H2.
rewrite plus_assoc.
rewrite plus_assoc.
reflexivity.
}
rewrite H.
rewrite IHp.
reflexivity.
Qed.
(* induction *)
Theorem mult_assoc : forall n m p : nat,
n * (m * p) = (n * m) * p.
Proof.
intros n m p.
induction n as [|n' IHn'].
- simpl. reflexivity.
- simpl. rewrite -> IHn'. rewrite -> mult_plus_distr_r. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (eqb_refl) *)
Theorem eqb_refl : forall n : nat,
true = (n =? n).
Proof.
intros n.
induction n as [|n' IHn'].
- simpl. reflexivity.
- simpl. rewrite <- IHn'. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (plus_swap')
The [replace] tactic allows you to specify a particular subterm to
rewrite and what you want it rewritten to: [replace (t) with (u)]
replaces (all copies of) expression [t] in the goal by expression
[u], and generates [t = u] as an additional subgoal. This is often
useful when a plain [rewrite] acts on the wrong part of the goal.
Use the [replace] tactic to do a proof of [plus_swap'], just like
[plus_swap] but without needing [assert]. *)
Theorem plus_swap' : forall n m p : nat,
n + (m + p) = m + (n + p).
Proof.
intros n m p.
rewrite <- plus_comm.
rewrite <- plus_assoc.
replace (p + n) with (n + p).
reflexivity.
rewrite <- plus_comm.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, standard, especially useful (binary_commute)
Recall the [incr] and [bin_to_nat] functions that you
wrote for the [binary] exercise in the [Basics] chapter. Prove
that the following diagram commutes:
incr
bin ----------------------> bin
| |
bin_to_nat | | bin_to_nat
| |
v v
nat ----------------------> nat
S
That is, incrementing a binary number and then converting it to
a (unary) natural number yields the same result as first converting
it to a natural number and then incrementing.
Name your theorem [bin_to_nat_pres_incr] ("pres" for "preserves").
Before you start working on this exercise, copy the definitions of
[incr] and [bin_to_nat] from your solution to the [binary]
exercise here so that this file can be graded on its own. If you
want to change your original definitions to make the property
easier to prove, feel free to do so! *)
Theorem binary_commute : forall b : bin,
bin_to_nat (incr b) = S (bin_to_nat b).
Proof.
intros b.
induction b.
- simpl. reflexivity.
- simpl incr. simpl bin_to_nat. rewrite <- plus_n_O.
reflexivity.
- simpl incr. simpl bin_to_nat. rewrite <- plus_n_O. rewrite <- plus_n_O.
rewrite IHb. simpl "+".
assert (H: bin_to_nat b + S (bin_to_nat b) = S (bin_to_nat b + bin_to_nat b)).
{ rewrite plus_n_Sm. reflexivity. }
rewrite H. reflexivity.
Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_binary_commute : option (nat*string) := None.
(** [] *)
(** **** Exercise: 5 stars, advanced (binary_inverse)
This is a further continuation of the previous exercises about
binary numbers. You may find you need to go back and change your
earlier definitions to get things to work here.
(a) First, write a function to convert natural numbers to binary
numbers. *)
Fixpoint half (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => S (half n')
end.
Compute half 8.
Compute half 11.
Module BinaryPlayground.
Inductive bin' : Type :=
| Ep
| T1 (zeroes: nat) (b: bin').
Fixpoint bin'_len (b: bin') : nat :=
match b with
| Ep => 0 (* should be -1 but we can't represent it *)
| T1 n Ep => n
| T1 n b => n + S (bin'_len b)
end.
Fixpoint bin'_to_nat(b: bin') : nat :=
match b with
| Ep => 0
| T1 n b' => exp 2 (bin'_len b) + bin'_to_nat b'
end.
(* 0b = 0 *)
Compute bin'_to_nat Ep.
(* 0b1 = 1 *)
Compute bin'_to_nat(T1 0 Ep).
(* 0b10 = 2 *)
Compute bin'_to_nat(T1 1 Ep).
(* 0b101001101 = 333 *)
Compute bin'_to_nat(
T1 1 (T1 2 (T1 0 (T1 1 (T1 0 Ep))))
).
End BinaryPlayground.
Fixpoint nat_to_bin (n:nat) : bin :=
match n with
| O => Z
| S n => incr (nat_to_bin n)
end.
(** Prove that, if we start with any [nat], convert it to binary, and
convert it back, we get the same [nat] we started with. (Hint: If
your definition of [nat_to_bin] involved any extra functions, you
may need to prove a subsidiary lemma showing how such functions
relate to [nat_to_bin].) *)
Theorem nat_bin_nat : forall n, bin_to_nat (nat_to_bin n) = n.
Proof.
intro n.
induction n.
- simpl. reflexivity.
- simpl. rewrite binary_commute. rewrite IHn.
reflexivity.
Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_binary_inverse_a : option (nat*string) := None.
(** (b) One might naturally expect that we should also prove the
opposite direction -- that starting with a binary number,
converting to a natural, and then back to binary should yield
the same number we started with. However, this is not the
case! Explain (in a comment) what the problem is. *)
(*
This binary representation can express invalid state. Or put in other words,
number doesn't always have unique representation in this system.
Preceding zeroes doesn't change the value of the number, like this:
- B0 (B0 Z) = Z
- B1 (B0 (B0 Z)) = B1 Z
*)
Compute bin_to_nat (B1 (B0 (B0 Z))) =? bin_to_nat (B1 Z).
(* Do not modify the following line: *)
Definition manual_grade_for_binary_inverse_b : option (nat*string) := None.
(** (c) Define a normalization function -- i.e., a function
[normalize] going directly from [bin] to [bin] (i.e., _not_ by
converting to [nat] and back) such that, for any binary number
[b], converting [b] to a natural and then back to binary yields
[(normalize b)]. Prove it. (Warning: This part is a bit
tricky -- you may end up defining several auxiliary lemmas.
One good way to find out what you need is to start by trying
to prove the main statement, see where you get stuck, and see
if you can find a lemma -- perhaps requiring its own inductive
proof -- that will allow the main proof to make progress.) Don't
define this using [nat_to_bin] and [bin_to_nat]! *)
Definition double_b(b : bin) : bin :=
match b with
| Z => Z
| n => B0 n
end.
Fixpoint normalize(b : bin) : bin :=
match b with
| Z => Z
| B1 n => B1 (normalize n)
| B0 n => double_b (normalize n)
end.
Compute normalize (B0 (B1 (B0 (B0 Z)))).
Compute normalize (normalize (B0 (B1 (B0 (B0 Z))))).
Compute normalize (B1 (B0 (B0 (B1 (B0 (B0 Z)))))).
(* 2n+2 = 2(n+1) *)
Lemma incr_twice : forall b,
incr (incr (double_b b)) = (double_b (incr b)).
Proof.
intro b.
induction b.
- simpl. reflexivity.
- simpl. reflexivity.
- simpl. reflexivity.
Qed.
Lemma incr_normalize_commute: forall b,
normalize (incr b) = incr (normalize b).
Proof.
intros.
induction b.
- simpl. reflexivity.
- simpl. induction (normalize b).
+ simpl. reflexivity.
+ simpl. reflexivity.
+ simpl. reflexivity.
- simpl. rewrite IHb. destruct (normalize b).
+ simpl. reflexivity.
+ simpl. reflexivity.
+ simpl. reflexivity.
Qed.
Lemma nat_to_bin_2x : forall n,
nat_to_bin (n + n) = double_b (nat_to_bin n).
Proof.
intros.
induction n.
- simpl. reflexivity.
- simpl "+". rewrite <- plus_n_Sm. repeat simpl nat_to_bin.
rewrite IHn. repeat rewrite <- incr_normalize_commute.
rewrite incr_twice. reflexivity.
Qed.
Lemma incr_double_normalize_b: forall b,
incr (double_b (normalize b)) = B1 (normalize b).
Proof.
intros.
induction (normalize b).
- simpl. reflexivity.
- simpl. reflexivity.
- simpl. reflexivity.
Qed.
Theorem bin_nat_bin : forall b, nat_to_bin (bin_to_nat b) = normalize b.
Proof.
intro b.
induction b.
- simpl. reflexivity.
- simpl bin_to_nat. rewrite <- plus_n_O.
rewrite nat_to_bin_2x. rewrite IHb.
simpl. reflexivity.
- simpl. rewrite <- plus_n_O.
rewrite nat_to_bin_2x. rewrite IHb.
rewrite incr_double_normalize_b.
reflexivity.
Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_binary_inverse_c : option (nat*string) := None.
(** [] *)
(* 2020-09-09 20:51 *)
|
`timescale 1 ns / 1 ps
module window_broadcaster #
(
parameter integer C_HBITS = 12,
parameter integer C_WBITS = 12,
parameter integer C_SBITS = 32,
parameter integer C_MASTER_NUM = 1
)
(
input wire [C_WBITS-1 : 0] s_left,
input wire [C_WBITS-1 : 0] s_width,
input wire [C_HBITS-1 : 0] s_top,
input wire [C_HBITS-1 : 0] s_height,
input wire [C_SBITS-1 : 0] s_stride,
output wire [C_WBITS-1 : 0] m0_left,
output wire [C_WBITS-1 : 0] m0_width,
output wire [C_HBITS-1 : 0] m0_top,
output wire [C_HBITS-1 : 0] m0_height,
output wire [C_SBITS-1 : 0] m0_stride,
output wire [C_WBITS-1 : 0] m1_left,
output wire [C_WBITS-1 : 0] m1_width,
output wire [C_HBITS-1 : 0] m1_top,
output wire [C_HBITS-1 : 0] m1_height,
output wire [C_SBITS-1 : 0] m1_stride,
output wire [C_WBITS-1 : 0] m2_left,
output wire [C_WBITS-1 : 0] m2_width,
output wire [C_HBITS-1 : 0] m2_top,
output wire [C_HBITS-1 : 0] m2_height,
output wire [C_SBITS-1 : 0] m2_stride,
output wire [C_WBITS-1 : 0] m3_left,
output wire [C_WBITS-1 : 0] m3_width,
output wire [C_HBITS-1 : 0] m3_top,
output wire [C_HBITS-1 : 0] m3_height,
output wire [C_SBITS-1 : 0] m3_stride,
output wire [C_WBITS-1 : 0] m4_left,
output wire [C_WBITS-1 : 0] m4_width,
output wire [C_HBITS-1 : 0] m4_top,
output wire [C_HBITS-1 : 0] m4_height,
output wire [C_SBITS-1 : 0] m4_stride,
output wire [C_WBITS-1 : 0] m5_left,
output wire [C_WBITS-1 : 0] m5_width,
output wire [C_HBITS-1 : 0] m5_top,
output wire [C_HBITS-1 : 0] m5_height,
output wire [C_SBITS-1 : 0] m5_stride,
output wire [C_WBITS-1 : 0] m6_left,
output wire [C_WBITS-1 : 0] m6_width,
output wire [C_HBITS-1 : 0] m6_top,
output wire [C_HBITS-1 : 0] m6_height,
output wire [C_SBITS-1 : 0] m6_stride,
output wire [C_WBITS-1 : 0] m7_left,
output wire [C_WBITS-1 : 0] m7_width,
output wire [C_HBITS-1 : 0] m7_top,
output wire [C_HBITS-1 : 0] m7_height,
output wire [C_SBITS-1 : 0] m7_stride
);
localparam integer C_MAX_OUT = 8;
wire [C_WBITS-1 : 0] m_left [C_MAX_OUT-1:0];
wire [C_WBITS-1 : 0] m_width [C_MAX_OUT-1:0];
wire [C_HBITS-1 : 0] m_top [C_MAX_OUT-1:0];
wire [C_HBITS-1 : 0] m_height[C_MAX_OUT-1:0];
wire [C_SBITS-1 : 0] m_stride[C_MAX_OUT-1:0];
`define ASSIGN_SINGLE_O(i) \
assign m``i``_left = m_left [i]; \
assign m``i``_width = m_width [i]; \
assign m``i``_top = m_top [i]; \
assign m``i``_height = m_height[i]; \
assign m``i``_stride = m_stride[i];
`ASSIGN_SINGLE_O(0)
`ASSIGN_SINGLE_O(1)
`ASSIGN_SINGLE_O(2)
`ASSIGN_SINGLE_O(3)
`ASSIGN_SINGLE_O(4)
`ASSIGN_SINGLE_O(5)
`ASSIGN_SINGLE_O(6)
`ASSIGN_SINGLE_O(7)
generate
genvar i;
for (i=0; i < C_MAX_OUT; i = i+1) begin: single_output
if (i < C_MASTER_NUM) begin
assign m_left [i] = s_left ;
assign m_top [i] = s_top ;
assign m_width [i] = s_width ;
assign m_height[i] = s_height;
assign m_stride[i] = s_stride;
end
else begin
assign m_left [i] = 0;
assign m_top [i] = 0;
assign m_width [i] = 0;
assign m_height[i] = 0;
assign m_stride[i] = 0;
end
end
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
`include "lo_read.v"
`include "lo_passthru.v"
`include "lo_simulate.v"
`include "hi_read_tx.v"
`include "hi_read_rx_xcorr.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "util.v"
module fpga(
spcki, miso, mosi, ncs,
pck0i, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk, adc_noe,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg
);
input spcki, mosi, ncs;
output miso;
input pck0i, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk, adc_noe;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
//assign pck0 = pck0i;
IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(
.O(pck0),
.I(pck0i)
);
//assign spck = spcki;
IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(
.O(spck),
.I(spcki)
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] divisor;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0];
4'b0010: divisor <= shift_reg[7:0];
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the low-frequency configuration:
wire lo_is_125khz;
assign lo_is_125khz = conf_word[3];
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation;
assign hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848;
assign hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop;
assign hi_read_rx_xcorr_snoop = conf_word[1];
// Divide the expected subcarrier frequency for hi_read_rx_xcorr by 4
wire hi_read_rx_xcorr_quarter;
assign hi_read_rx_xcorr_quarter = conf_word[2];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type;
assign hi_simulate_mod_type = conf_word[2:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
lo_read lr(
pck0, ck_1356meg, ck_1356megb,
lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
adc_d, lr_adc_clk,
lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,
cross_hi, cross_lo,
lr_dbg,
lo_is_125khz, divisor
);
lo_passthru lp(
pck0, ck_1356meg, ck_1356megb,
lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
adc_d, lp_adc_clk,
lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk,
cross_hi, cross_lo,
lp_dbg, divisor
);
lo_simulate ls(
pck0, ck_1356meg, ck_1356megb,
ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,
adc_d, ls_adc_clk,
ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,
cross_hi, cross_lo,
ls_dbg, divisor
);
hi_read_tx ht(
pck0, ck_1356meg, ck_1356megb,
ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
adc_d, ht_adc_clk,
ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
cross_hi, cross_lo,
ht_dbg,
hi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
pck0, ck_1356meg, ck_1356megb,
hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
adc_d, hrxc_adc_clk,
hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
cross_hi, cross_lo,
hrxc_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_simulate hs(
pck0, ck_1356meg, ck_1356megb,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
cross_hi, cross_lo,
hs_dbg,
hi_simulate_mod_type
);
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
hisn_dbg,
hi_simulate_mod_type
);
// Major modes:
// 000 -- LF reader (generic)
// 001 -- LF simulated tag (generic)
// 010 -- HF reader, transmitting to tag; modulation depth selectable
// 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 100 -- HF simulated tag
// 101 -- HF ISO14443-A
// 110 -- LF passthrough
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, lp_pwr_oe4, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0);
mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: DCACHE.v
// Version: 1.1 bug fix
// History: 1.0 first release of 30 Mai 2015
// Date: 7 October 2015
//
// Copyright (C) 2015 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// DCACHE the data cache of M32632
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DCACHE( BCLK, MCLK, WRCFG, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW, QWATWO,
WAMUX, ENWR, IC_PREQ, FILLRAM, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR, MCR_FLAGS,
PACKET, SIZE, VADR, WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET, HLDA,
ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
input BCLK;
input MCLK;
input WRCFG;
input MDONE;
input BRESET;
input PTB_WR;
input PTB_SEL;
input IO_READY;
input REG_OUT;
input PSR_USER;
input WRITE;
input READ;
input ZTEST;
input RMW;
input QWATWO;
input WAMUX;
input ENWR;
input IC_PREQ;
input FILLRAM;
input [1:0] CFG;
input [1:0] CINVAL;
input [27:4] DMA_AA;
input [63:0] DP_Q;
input [31:0] DRAM_Q;
input [31:12] IC_VA;
input [3:0] ICTODC;
input [31:0] IO_Q;
input [1:0] IVAR;
input [3:0] MCR_FLAGS;
input [3:0] PACKET;
input [1:0] SIZE;
input [31:0] VADR;
input [11:2] WADDR;
input [2:0] WCTRL;
input [2:0] RWVAL;
input [40:2] DBG_IN;
input ENDRAM;
output IO_RD;
output IO_WR;
output DRAM_ACC;
output DRAM_WR;
output INIT_RUN;
output [1:0] PTE_STAT;
output KDET;
output HLDA;
output RWVFLAG;
output [5:0] ACC_STAT;
output [31:0] DP_DI;
output [3:1] IACC_STAT;
output [1:0] IC_SIGS;
output [27:4] KOLLI_A;
output [23:0] MMU_DIN;
output reg [27:0] DRAM_A;
output reg [35:0] DRAM_DI;
output reg [31:0] IO_A;
output reg [3:0] IO_BE;
output reg [31:0] IO_DI;
output DBG_HIT;
reg [31:0] DFFE_IOR;
reg [31:0] CAPDAT;
reg [31:0] VADR_R;
reg AUX_ALT;
reg DFF_QWEXT;
wire [27:4] ADDR;
wire ADR_EQU;
wire AUX_DAT;
wire CA_HIT;
wire CA_SET;
wire CUPDATE;
wire DMA_MUX;
wire [3:0] ENBYTE;
wire HIT_ALL;
wire INIT_CA_RUN;
wire IO_ACC;
wire IO_SPACE;
wire KOMUX;
wire MMU_HIT;
wire NEW_PTB;
wire PTB_ONE;
wire [27:0] PTE_ADR;
wire [31:12] RADR;
wire [11:4] TAGA;
wire [23:0] UPDATE_C;
wire [31:0] UPDATE_M;
wire USE_CA;
wire USER;
wire WB_ACC;
wire WEMV;
wire WR_MRAM;
wire [31:0] WRDATA;
wire VIRT_A;
wire PTE_MUX;
wire WE_CV;
wire [23:0] DAT_CV;
wire [4:0] WADR_CV;
wire WRSET0;
wire [3:0] BE_SET;
wire [31:0] DAT_SET;
wire [9:0] A_SET;
wire WRSET1;
wire SEL_PTB1;
wire CI;
wire [27:0] ADR_MX;
wire LD_DRAM_A;
wire VIRTUELL;
wire NEW_PTB_RUN;
wire KILL;
wire LAST_MUX;
wire [31:0] SET_DAT;
wire [31:0] ALT_DAT;
wire [31:0] DAT_MV;
wire [3:0] RADR_MV;
wire [3:0] WADR_MV;
wire [31:0] LAST_DAT;
wire WRCRAM0;
wire WRCRAM1;
wire PROT_ERROR;
wire AUX_QW;
wire PD_MUX;
wire [19:0] PTE_DAT;
wire PKEEP;
// +++++++++++++++++++ Memories ++++++++++++++++++++
reg [7:0] DATA0_D [0:1023]; // Data Set 0 : 4 kBytes
reg [7:0] DATA0_C [0:1023];
reg [7:0] DATA0_B [0:1023];
reg [7:0] DATA0_A [0:1023];
reg [31:0] SET_DAT0;
reg [7:0] DATA1_D [0:1023]; // Data Set 1 : 4 kBytes
reg [7:0] DATA1_C [0:1023];
reg [7:0] DATA1_B [0:1023];
reg [7:0] DATA1_A [0:1023];
reg [31:0] SET_DAT1;
reg [15:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 16 bits
reg [15:0] TAG0;
reg [15:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 16 bits
reg [15:0] TAG1;
reg [23:0] CA_VALID [0:31]; // Valid bits for Data Set 0 and 1 : 32 entries of 24 bits
reg [23:0] CVALID;
reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
reg [35:0] MMU_Q;
reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
reg [31:0] MVALID;
assign ADR_EQU = ({RADR[27:12],VADR_R[11:4]} == DRAM_A[27:4]); // Limited to 256 MB
assign ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;
assign RADR = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;
assign ADR_MX = PTE_MUX ? PTE_ADR : {RADR[27:12],VADR_R[11:2],USE_CA,CA_SET} ;
assign KOLLI_A = DMA_MUX ? DMA_AA : DRAM_A[27:4] ;
assign SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;
assign VIRT_A = ~CINVAL[0] & VIRTUELL;
assign USER = ~MCR_FLAGS[3] & PSR_USER;
assign DAT_SET = WRITE ? WRDATA : DRAM_Q ;
assign BE_SET = ENBYTE | {~WRITE,~WRITE,~WRITE,~WRITE};
assign ADDR = KDET ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ;
assign A_SET = WAMUX ? WADDR : VADR_R[11:2] ;
assign TAGA = KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;
assign INIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;
assign LAST_MUX = AUX_ALT | AUX_DAT | AUX_QW;
assign LAST_DAT = LAST_MUX ? ALT_DAT : SET_DAT ;
assign LD_DRAM_A = ~(DRAM_ACC | PKEEP);
assign ACC_STAT[4] = IO_ACC;
assign ACC_STAT[5] = CA_HIT;
always @(posedge BCLK)
if (IO_ACC)
begin
IO_BE <= ENBYTE;
IO_DI <= WRDATA;
IO_A <= {RADR[31:12],VADR_R[11:0]};
end
always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[27:0] <= ADR_MX[27:0];
always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
always @(posedge BCLK)
begin
DRAM_DI <= {(PD_MUX ? PTE_DAT[19:16] : ENBYTE),WRDATA[31:16],
(PD_MUX ? PTE_DAT[15:0] : WRDATA[15:0])};
AUX_ALT <= DFF_QWEXT | IO_RD;
DFF_QWEXT <= IO_RD & SIZE[0] & SIZE[1];
VADR_R <= VADR;
end
always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
always @(posedge BCLK) CVALID <= CA_VALID[TAGA[11:7]];
always @(negedge BCLK) if (WE_CV) CA_VALID[WADR_CV] <= DAT_CV;
// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
always @(posedge BCLK) TAG0 <= TAGSET_0[TAGA];
always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= RADR[27:12];
// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++
always @(posedge BCLK) TAG1 <= TAGSET_1[TAGA];
always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= RADR[27:12];
// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++
always @(posedge BCLK)
begin
SET_DAT0[31:24] <= DATA0_D[VADR[11:2]];
SET_DAT0[23:16] <= DATA0_C[VADR[11:2]];
SET_DAT0[15:8] <= DATA0_B[VADR[11:2]];
SET_DAT0[7:0] <= DATA0_A[VADR[11:2]];
end
always @(posedge MCLK)
if (WRSET0)
begin
if (BE_SET[3]) DATA0_D[A_SET] <= DAT_SET[31:24];
if (BE_SET[2]) DATA0_C[A_SET] <= DAT_SET[23:16];
if (BE_SET[1]) DATA0_B[A_SET] <= DAT_SET[15:8];
if (BE_SET[0]) DATA0_A[A_SET] <= DAT_SET[7:0];
end
// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++
always @(posedge BCLK)
begin
SET_DAT1[31:24] <= DATA1_D[VADR[11:2]];
SET_DAT1[23:16] <= DATA1_C[VADR[11:2]];
SET_DAT1[15:8] <= DATA1_B[VADR[11:2]];
SET_DAT1[7:0] <= DATA1_A[VADR[11:2]];
end
always @(posedge MCLK)
if (WRSET1)
begin
if (BE_SET[3]) DATA1_D[A_SET] <= DAT_SET[31:24];
if (BE_SET[2]) DATA1_C[A_SET] <= DAT_SET[23:16];
if (BE_SET[1]) DATA1_B[A_SET] <= DAT_SET[15:8];
if (BE_SET[0]) DATA1_A[A_SET] <= DAT_SET[7:0];
end
DCACHE_SM DC_SM(
.BCLK(BCLK),
.BRESET(BRESET),
.VIRTUELL(VIRTUELL),
.IO_SPACE(IO_SPACE),
.MDONE(MDONE),
.MMU_HIT(MMU_HIT),
.CA_HIT(CA_HIT),
.READ(READ),
.WRITE(WRITE),
.ZTEST(ZTEST),
.RMW(RMW),
.QWATWO(QWATWO),
.USE_CA(USE_CA),
.PTB_WR(PTB_WR),
.PTB_SEL(PTB_SEL),
.SEL_PTB1(SEL_PTB1),
.IO_READY(IO_READY),
.USER(USER),
.PROTECT(ACC_STAT[3]),
.PROT_ERROR(PROT_ERROR),
.ENWR(ENWR),
.WB_ACC(WB_ACC),
.ADR_EQU(ADR_EQU),
.IC_PREQ(IC_PREQ),
.CAPDAT(CAPDAT[31:0]),
.CPU_OUT(DP_Q[59:44]),
.FILLRAM(FILLRAM),
.IC_VA(IC_VA),
.ICTODC(ICTODC),
.VADR_R(VADR_R[31:12]),
.NEW_PTB(NEW_PTB),
.PTB_ONE(PTB_ONE),
.DRAM_ACC(DRAM_ACC),
.DRAM_WR(DRAM_WR),
.IO_ACC(IO_ACC),
.IO_RD(IO_RD),
.IO_WR(IO_WR),
.PTE_STAT(PTE_STAT),
.ABORT(ACC_STAT[1]),
.WR_MRAM(WR_MRAM),
.CUPDATE(CUPDATE),
.AUX_DAT(AUX_DAT),
.PTE_MUX(PTE_MUX),
.ACC_OK(ACC_STAT[0]),
.ABO_LEVEL1(ACC_STAT[2]),
.IACC_STAT(IACC_STAT),
.KOMUX(KOMUX),
.KDET(KDET),
.HIT_ALL(HIT_ALL),
.DMA_MUX(DMA_MUX),
.HLDA(HLDA),
.RWVAL(RWVAL[1:0]),
.RWVFLAG(RWVFLAG),
.IC_SIGS(IC_SIGS),
.MMU_DIN(MMU_DIN),
.PD_MUX(PD_MUX),
.PKEEP(PKEEP),
.PTE_ADR(PTE_ADR),
.PTE_DAT(PTE_DAT));
CA_MATCH DCA_COMPARE(
.INVAL_L(CINVAL[0]),
.CI(CI),
.MMU_HIT(MMU_HIT),
.WRITE(WRITE),
.KDET(KDET),
.ADDR(ADDR),
.CFG(CFG),
.ENDRAM(ENDRAM),
.CVALID(CVALID),
.TAG0(TAG0),
.TAG1(TAG1),
.CA_HIT(CA_HIT),
.CA_SET(CA_SET),
.WB_ACC(WB_ACC),
.USE_CA(USE_CA),
.IOSEL(RADR[31:28]),
.IO_SPACE(IO_SPACE),
.KILL(KILL),
.DC_ILO(RWVAL[2]),
.UPDATE(UPDATE_C));
DCA_CONTROL DCA_CTRL(
.BCLK(BCLK),
.MCLK(MCLK),
.BRESET(BRESET),
.CA_SET(CA_SET),
.HIT_ALL(HIT_ALL),
.UPDATE(UPDATE_C),
.VADR_R(ADDR[11:7]),
.DRAM_ACC(DRAM_ACC),
.CUPDATE(CUPDATE),
.KILL(KILL),
.WRITE(WRITE),
.WRCFG(WRCFG),
.WCTRL(WCTRL[1:0]),
.INVAL_A(CINVAL[1]),
.DAT_CV(DAT_CV),
.WADR_CV(WADR_CV),
.WE_CV(WE_CV),
.INIT_CA_RUN(INIT_CA_RUN),
.WRCRAM0(WRCRAM0),
.WRCRAM1(WRCRAM1),
.WRSET0(WRSET0),
.WRSET1(WRSET1));
MMU_MATCH MMU_COMPARE(
.USER(USER),
.WRITE(WRITE),
.READ(READ),
.RMW(RMW),
.IVAR(IVAR),
.MCR_FLAGS(MCR_FLAGS[2:0]),
.MMU_VA(MMU_Q[35:20]),
.MVALID(MVALID),
.VADR_R(VADR_R[31:12]),
.MMU_HIT(MMU_HIT),
.PROT_ERROR(PROT_ERROR),
.VIRTUELL(VIRTUELL),
.CI(CI),
.SEL_PTB1(SEL_PTB1),
.UPDATE(UPDATE_M));
MMU_UP MMU_CTRL(
.BCLK(BCLK),
.BRESET(BRESET),
.NEW_PTB(NEW_PTB),
.IVAR(IVAR[1]),
.PTB1(PTB_ONE),
.WR_MRAM(WR_MRAM),
.MVALID(MVALID),
.UPDATE(UPDATE_M),
.VADR(VADR[19:16]),
.VADR_R(VADR_R[19:16]),
.WE_MV(WEMV),
.NEW_PTB_RUN(NEW_PTB_RUN),
.DAT_MV(DAT_MV),
.RADR_MV(RADR_MV),
.WADR_MV(WADR_MV));
// +++++++++++++++++++++++++ MMU Valid +++++++++++++++++++++
always @(posedge BCLK) MVALID <= MMU_VALID[RADR_MV];
always @(negedge BCLK) if (WEMV) MMU_VALID[WADR_MV] <= DAT_MV;
// +++++++++++++++++++++++++ MMU Tags ++++++++++++++++++++++
always @(posedge BCLK) MMU_Q <= MMU_TAGS[VADR[19:12]];
always @(negedge BCLK) if (WR_MRAM) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};
RD_ALIGNER RD_ALI(
.BCLK(BCLK),
.ACC_OK(ACC_STAT[0]),
.REG_OUT(REG_OUT),
.PACKET(PACKET),
.RDDATA(LAST_DAT),
.SIZE(SIZE),
.CA_HIT(CA_HIT),
.DP_DI(DP_DI),
.AUX_QW(AUX_QW));
WR_ALIGNER WR_ALI(
.DP_Q(DP_Q),
.PACKET(PACKET),
.SIZE(SIZE),
.ENBYTE(ENBYTE),
.WRDATA(WRDATA));
DEBUG_AE DBGAE(
.DBG_IN(DBG_IN),
.READ(READ),
.WRITE(WRITE),
.USER(USER),
.VIRTUELL(VIRTUELL),
.ACC_OK(ACC_STAT[0]),
.VADR_R(VADR_R[31:2]),
.MMU_Q(MMU_Q[19:0]),
.ENBYTE(ENBYTE),
.DBG_HIT(DBG_HIT));
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
/*
* Helper module for synchronizing a counter from one clock domain to another
* using gray code. To work correctly the counter must not change its value by
* more than one in one clock cycle in the source domain. I.e. the value may
* change by either -1, 0 or +1.
*/
module sync_gray (
input in_clk,
input in_resetn,
input [DATA_WIDTH-1:0] in_count,
input out_resetn,
input out_clk,
output [DATA_WIDTH-1:0] out_count
);
// Bit-width of the counter
parameter DATA_WIDTH = 1;
// Whether the input and output clock are asynchronous, if set to 0 the
// synchronizer will be bypassed and out_count will be in_count.
parameter ASYNC_CLK = 1;
reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
reg [DATA_WIDTH-1:0] out_count_m = 'h0;
function [DATA_WIDTH-1:0] g2b;
input [DATA_WIDTH-1:0] g;
reg [DATA_WIDTH-1:0] b;
integer i;
begin
b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i - 1)
b[i] = b[i + 1] ^ g[i];
g2b = b;
end
endfunction
function [DATA_WIDTH-1:0] b2g;
input [DATA_WIDTH-1:0] b;
reg [DATA_WIDTH-1:0] g;
integer i;
begin
g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
g[i] = b[i + 1] ^ b[i];
b2g = g;
end
endfunction
always @(posedge in_clk) begin
if (in_resetn == 1'b0) begin
cdc_sync_stage0 <= 'h00;
end else begin
cdc_sync_stage0 <= b2g(in_count);
end
end
always @(posedge out_clk) begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'h00;
cdc_sync_stage2 <= 'h00;
out_count_m <= 'h00;
end else begin
cdc_sync_stage1 <= cdc_sync_stage0;
cdc_sync_stage2 <= cdc_sync_stage1;
out_count_m <= g2b(cdc_sync_stage2);
end
end
assign out_count = ASYNC_CLK ? out_count_m : in_count;
endmodule
|
/* 同步 FIFO 4*128 */
// 一种4bit 128深度的 同步FIFO设计
// @`13
// 2017年6月6日
// 哈尔滨工业大学（威海） EDA课程设计
module fifo(clock, reset, read, write, fifo_in, digitron_out, fifo_empty, fifo_full);
parameter DEPTH = 128; // 128 深
parameter DEPTH_BINARY = 7; // 深度的二进制位数
parameter WIDTH = 4; // 4bit宽
parameter MAX_CONT = 7'b1111111; // 计数器最大值127 [0~127]
// LED 灯的二进制表示
// 根据 《数字系统设计与Verilog DHL (6th Edition)》P153 所提供的7段数码管电路图
/*
—— a
| | f b
—— g
| | e c
—— d
*/
// Len_N = abcdefg
// 使用一个七段数码管基于16进制显示 4bit 数据
parameter
digitron_0 = 7'b1111110,
digitron_1 = 7'b0110000,
digitron_2 = 7'b1101101,
digitron_3 = 7'b0000110,
digitron_4 = 7'b0110011,
digitron_5 = 7'b1011011,
digitron_6 = 7'b1011111,
digitron_7 = 7'b1110000,
digitron_8 = 7'b1111111,
digitron_9 = 7'b1111011,
digitron_a = 7'b1100111,
digitron_b = 7'b0011111,
digitron_c = 7'b1001110,
digitron_d = 7'b0111101,
digitron_e = 7'b0110000,
digitron_f = 7'b1001111;
input clock,reset,read,write; // 时钟，重置，读开关，写开关
input [WIDTH-1:0]fifo_in; // FIFO 数据输入
output [6:0] digitron_out; // 数码管 FIFO 数据输出
output fifo_empty,fifo_full; // 空标志,满标志
reg div; // 驱动信号
reg [23:0] clock_count; // 时钟计数器
reg [6:0] digitron_out; // 数据输出寄存器
reg [WIDTH-1:0]fifo_out; // 数据输出寄存器
reg [WIDTH-1:0]ram[DEPTH-1:0]; // 128深度 8宽度的 RAM 寄存器
reg [DEPTH_BINARY-1:0]read_ptr,write_ptr,counter; // 读指针，写指针，计数器 长度为2^7
wire fifo_empty,fifo_full; // 空标志,满标志
initial
begin
counter = 0;
read_ptr = 0;
write_ptr = 0;
fifo_out = 0;
div = 0;
clock_count = 0;
digitron_out = digitron_0;
end
always@(posedge clock)
begin
if(clock_count == 24'b111111111111111111111111)
begin
div =~ div;
clock_count <= 0;
end
else
begin
clock_count <= clock_count+1;
end
end
assign fifo_empty = (counter == 0); //标志位赋值
assign fifo_full = (counter == DEPTH-1);
always@(posedge div) // 时钟同步驱动
if(reset) // Reset 重置FIFO
begin
read_ptr = 0;
write_ptr = 0;
counter = 0;
fifo_out = 0;
end
else
case({read,write}) // 相应读写开关
2'b00:; //没有读写指令
2'b01: //写指令，数据输入FIFO
begin
if (counter < DEPTH - 1) // 判断是否可写
begin
ram[write_ptr] = fifo_in;
counter = counter + 1;
write_ptr = (write_ptr == DEPTH-1)?0:write_ptr + 1;
end
end
2'b10: //读指令，数据读出FIFO
begin
if (counter > 0) // 判断是否可读
begin
fifo_out = ram[read_ptr];
case(fifo_out)
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
counter = counter - 1;
read_ptr = (read_ptr == DEPTH-1)?0:read_ptr + 1;
end
end
2'b11: //读写指令同时，数据可以直接输出
begin
if(counter == 0)
begin
fifo_out = fifo_in; // 直接输出
case(fifo_out) // todo : 去除case的冗余代码 2017.6.13
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
end
else
begin
ram[write_ptr]=fifo_in;
fifo_out=ram[read_ptr];
case(fifo_out) // todo : 去除case的冗余代码 2017.6.13
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
write_ptr=(write_ptr==DEPTH-1)?0:write_ptr+1;
read_ptr=(read_ptr==DEPTH-1)?0:write_ptr+1;
end
end
endcase
endmodule
// module debouncing(
// BJ_CLK, //采集时钟
// RESET, //系统复位信号 [低电平有效]
// BUTTON_IN, //按键输入信号
// BUTTON_OUT //消抖后的输出信号
// );
// input BJ_CLK;
// input RESET;
// input BUTTON_IN;
// output BUTTON_OUT;
// reg BUTTON_IN_Q, BUTTON_IN_2Q, BUTTON_IN_3Q;
// always @(posedge BJ_CLK or negedge RESET)
// begin
// if(~RESET)
// begin
// BUTTON_IN_Q <= 1'b1;
// BUTTON_IN_2Q <= 1'b1;
// BUTTON_IN_3Q <= 1'b1;
// end
// else
// begin
// BUTTON_IN_Q <= BUTTON_IN;
// BUTTON_IN_2Q <= BUTTON_IN_Q;
// BUTTON_IN_3Q <= BUTTON_IN_2Q;
// end
// end
// wire BUTTON_OUT = BUTTON_IN_2Q | BUTTON_IN_3Q;
// endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__OR2_FUNCTIONAL_PP_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or2 (
VPWR,
VGND,
X ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
// Local signals
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2_FUNCTIONAL_PP_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'd1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 0;
count <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 0;
count <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= top_plus_1;
count <= count + 5'd1;
end
2'b01 : if(count>0)
begin
bottom <= bottom + 4'd1;
count <= count - 5'd1;
end
2'b11 : begin
bottom <= bottom + 4'd1;
top <= top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & (count==fifo_depth))
overrun <= 1'b1;
end // always
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.0
// \ \ Application: MIG
// / / Filename: ddr2_mig.v
// /___/ /\ Date Last Modified: $Date: 2009/02/03 18:46:29 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// Top-level module. Simple model for what the user might use
// Typically, the user will only instantiate MEM_INTERFACE_TOP in their
// code, and generate all backend logic (test bench) separately.
// In addition to the memory controller, the module instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
//Reference:
//Revision History:
// Rev 1.1 - Parameter USE_DM_PORT added. PK. 6/25/08
// Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
// Rev 1.3 - Parameter IODELAY_GRP added. PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
(* X_CORE_INFO = "mig_v3_0_ddr2_v5, Coregen 11.1" , CORE_GENERATION_INFO = "ddr2_v5,mig_v3_0,{component_name=ddr2_mig, BANK_WIDTH=2, CKE_WIDTH=1, CLK_WIDTH=2, COL_WIDTH=10, CS_NUM=1, CS_WIDTH=1, DM_WIDTH=8, DQ_WIDTH=64, DQ_PER_DQS=8, DQS_WIDTH=8, ODT_WIDTH=1, ROW_WIDTH=13, ADDITIVE_LAT=0, BURST_LEN=4, BURST_TYPE=0, CAS_LAT=4, ECC_ENABLE=0, MULTI_BANK_EN=1, TWO_T_TIME_EN=1, ODT_TYPE=1, REDUCE_DRV=0, REG_ENABLE=0, TREFI_NS=7800, TRAS=40000, TRCD=15000, TRFC=105000, TRP=15000, TRTP=7500, TWR=15000, TWTR=7500, DDR2_CLK_PERIOD=3750, RST_ACT_LOW=1}" *)
module ddr2_mig #
(
parameter BANK_WIDTH = 2,
// # of memory bank addr bits.
parameter CKE_WIDTH = 1,
// # of memory clock enable outputs.
parameter CLK_WIDTH = 2,
// # of clock outputs.
parameter COL_WIDTH = 10,
// # of memory column bits.
parameter CS_NUM = 1,
// # of separate memory chip selects.
parameter CS_WIDTH = 1,
// # of total memory chip selects.
parameter CS_BITS = 0,
// set to log2(CS_NUM) (rounded up).
parameter DM_WIDTH = 8,
// # of data mask bits.
parameter DQ_WIDTH = 64,
// # of data width.
parameter DQ_PER_DQS = 8,
// # of DQ data bits per strobe.
parameter DQS_WIDTH = 8,
// # of DQS strobes.
parameter DQ_BITS = 6,
// set to log2(DQS_WIDTH*DQ_PER_DQS).
parameter DQS_BITS = 3,
// set to log2(DQS_WIDTH).
parameter ODT_WIDTH = 1,
// # of memory on-die term enables.
parameter ROW_WIDTH = 13,
// # of memory row and # of addr bits.
parameter ADDITIVE_LAT = 0,
// additive write latency.
parameter BURST_LEN = 4,
// burst length (in double words).
parameter BURST_TYPE = 0,
// burst type (=0 seq; =1 interleaved).
parameter CAS_LAT = 4,
// CAS latency.
parameter ECC_ENABLE = 0,
// enable ECC (=1 enable).
parameter APPDATA_WIDTH = 128,
// # of usr read/write data bus bits.
parameter MULTI_BANK_EN = 1,
// Keeps multiple banks open. (= 1 enable).
parameter TWO_T_TIME_EN = 1,
// 2t timing for unbuffered dimms.
parameter ODT_TYPE = 1,
// ODT (=0(none),=1(75),=2(150),=3(50)).
parameter REDUCE_DRV = 0,
// reduced strength mem I/O (=1 yes).
parameter REG_ENABLE = 0,
// registered addr/ctrl (=1 yes).
parameter TREFI_NS = 7800,
// auto refresh interval (ns).
parameter TRAS = 40000,
// active->precharge delay.
parameter TRCD = 15000,
// active->read/write delay.
parameter TRFC = 105000,
// refresh->refresh, refresh->active delay.
parameter TRP = 15000,
// precharge->command delay.
parameter TRTP = 7500,
// read->precharge delay.
parameter TWR = 15000,
// used to determine write->precharge.
parameter TWTR = 7500,
// write->read delay.
parameter HIGH_PERFORMANCE_MODE = "TRUE",
// # = TRUE, the IODELAY performance mode is set
// to high.
// # = FALSE, the IODELAY performance mode is set
// to low.
parameter SIM_ONLY = 0,
// = 1 to skip SDRAM power up delay.
parameter DEBUG_EN = 0,
// Enable debug signals/controls.
// When this parameter is changed from 0 to 1,
// make sure to uncomment the coregen commands
// in ise_flow.bat or create_ise.bat files in
// par folder.
parameter CLK_PERIOD = 3750,
// Core/Memory clock period (in ps).
parameter CLK_TYPE = "SINGLE_ENDED",
// # = "DIFFERENTIAL " ->; Differential input clocks ,
// # = "SINGLE_ENDED" -> Single ended input clocks.
parameter DLL_FREQ_MODE = "HIGH",
// DCM Frequency range.
parameter RST_ACT_LOW = 1
// =1 for active low reset, =0 for active high.
)
(
inout [DQ_WIDTH-1:0] ddr2_dq,
output [ROW_WIDTH-1:0] ddr2_a,
output [BANK_WIDTH-1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [CS_WIDTH-1:0] ddr2_cs_n,
output [ODT_WIDTH-1:0] ddr2_odt,
output [CKE_WIDTH-1:0] ddr2_cke,
output [DM_WIDTH-1:0] ddr2_dm,
input sys_clk,
input idly_clk_200,
input sys_rst_n,
output phy_init_done,
output rst0_tb,
output clk0_tb,
input usr_clk, // jb
output app_wdf_afull,
output app_af_afull,
output rd_data_valid,
input app_wdf_wren,
input app_af_wren,
input [30:0] app_af_addr,
input [2:0] app_af_cmd,
output [(APPDATA_WIDTH)-1:0] rd_data_fifo_out,
input [(APPDATA_WIDTH)-1:0] app_wdf_data,
input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
inout [DQS_WIDTH-1:0] ddr2_dqs,
inout [DQS_WIDTH-1:0] ddr2_dqs_n,
output [CLK_WIDTH-1:0] ddr2_ck,
output [CLK_WIDTH-1:0] ddr2_ck_n
, input sp_refresh_disable
);
//***************************************************************************
// IODELAY Group Name: Replication and placement of IDELAYCTRLs will be
// handled automatically by software tools if IDELAYCTRLs have same refclk,
// reset and rdy nets. Designs with a unique RESET will commonly create a
// unique RDY. Constraint IODELAY_GROUP is associated to a set of IODELAYs
// with an IDELAYCTRL. The parameter IODELAY_GRP value can be any string.
//***************************************************************************
localparam IODELAY_GRP = "IODELAY_MIG";
initial
$display("Xilinx DDR2 MIGed controller at %m\n");
wire sys_clk_p;
wire sys_clk_n;
wire clk200_p;
wire clk200_n;
wire rst0;
wire rst90;
wire rstdiv0;
wire rst200;
wire clk0;
wire clk90;
wire clkdiv0;
wire clk200;
wire idelay_ctrl_rdy;
//Debug signals
wire [3:0] dbg_calib_done;
wire [3:0] dbg_calib_err;
wire [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt;
wire [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt;
wire [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt;
wire [DQS_WIDTH-1:0] dbg_calib_rd_data_sel;
wire [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly;
wire [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly;
wire dbg_idel_up_all;
wire dbg_idel_down_all;
wire dbg_idel_up_dq;
wire dbg_idel_down_dq;
wire dbg_idel_up_dqs;
wire dbg_idel_down_dqs;
wire dbg_idel_up_gate;
wire dbg_idel_down_gate;
wire [DQ_BITS-1:0] dbg_sel_idel_dq;
wire dbg_sel_all_idel_dq;
wire [DQS_BITS:0] dbg_sel_idel_dqs;
wire dbg_sel_all_idel_dqs;
wire [DQS_BITS:0] dbg_sel_idel_gate;
wire dbg_sel_all_idel_gate;
// Debug signals (optional use)
//***********************************
// PHY Debug Port demo
//***********************************
wire [35:0] cs_control0;
wire [35:0] cs_control1;
wire [35:0] cs_control2;
wire [35:0] cs_control3;
wire [191:0] vio0_in;
wire [95:0] vio1_in;
wire [99:0] vio2_in;
wire [31:0] vio3_out;
//***************************************************************************
assign rst0_tb = rst0;
assign clk0_tb = clk0;
assign sys_clk_p = 1'b1;
assign sys_clk_n = 1'b0;
assign clk200_p = 1'b1;
assign clk200_n = 1'b0;
ddr2_idelay_ctrl #
(
.IODELAY_GRP (IODELAY_GRP)
)
u_ddr2_idelay_ctrl
(
.rst200 (rst200),
.clk200 (clk200),
.idelay_ctrl_rdy (idelay_ctrl_rdy)
);
ddr2_infrastructure #
(
.CLK_PERIOD (CLK_PERIOD),
.CLK_TYPE (CLK_TYPE),
.DLL_FREQ_MODE (DLL_FREQ_MODE),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_ddr2_infrastructure
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk (sys_clk),
.clk200_p (clk200_p),
.clk200_n (clk200_n),
.idly_clk_200 (idly_clk_200),
.sys_rst_n (sys_rst_n),
.rst0 (rst0),
.rst90 (rst90),
.rstdiv0 (rstdiv0),
.rst200 (rst200),
.clk0 (clk0),
.clk90 (clk90),
.clkdiv0 (clkdiv0),
.clk200 (clk200),
.idelay_ctrl_rdy (idelay_ctrl_rdy)
);
ddr2_top #
(
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CLK_WIDTH (CLK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_NUM (CS_NUM),
.CS_WIDTH (CS_WIDTH),
.CS_BITS (CS_BITS),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_WIDTH (DQS_WIDTH),
.DQ_BITS (DQ_BITS),
.DQS_BITS (DQS_BITS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.BURST_LEN (BURST_LEN),
.BURST_TYPE (BURST_TYPE),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.APPDATA_WIDTH (APPDATA_WIDTH),
.MULTI_BANK_EN (MULTI_BANK_EN),
.TWO_T_TIME_EN (TWO_T_TIME_EN),
.ODT_TYPE (ODT_TYPE),
.REDUCE_DRV (REDUCE_DRV),
.REG_ENABLE (REG_ENABLE),
.TREFI_NS (TREFI_NS),
.TRAS (TRAS),
.TRCD (TRCD),
.TRFC (TRFC),
.TRP (TRP),
.TRTP (TRTP),
.TWR (TWR),
.TWTR (TWTR),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IODELAY_GRP (IODELAY_GRP),
.SIM_ONLY (SIM_ONLY),
.DEBUG_EN (DEBUG_EN),
.CLK_PERIOD (CLK_PERIOD),
.FPGA_SPEED_GRADE (1),
.USE_DM_PORT (1)
)
u_ddr2_top_0
(
.ddr2_dq (ddr2_dq),
.ddr2_a (ddr2_a),
.ddr2_ba (ddr2_ba),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_odt (ddr2_odt),
.ddr2_cke (ddr2_cke),
.ddr2_dm (ddr2_dm),
.phy_init_done (phy_init_done),
.rst0 (rst0),
.rst90 (rst90),
.rstdiv0 (rstdiv0),
.clk0 (clk0),
.usr_clk (usr_clk), // jb
.clk90 (clk90),
.clkdiv0 (clkdiv0),
.app_wdf_afull (app_wdf_afull),
.app_af_afull (app_af_afull),
.rd_data_valid (rd_data_valid),
.app_wdf_wren (app_wdf_wren),
.app_af_wren (app_af_wren),
.app_af_addr (app_af_addr),
.app_af_cmd (app_af_cmd),
.rd_data_fifo_out (rd_data_fifo_out),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.ddr2_dqs (ddr2_dqs),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_ck (ddr2_ck),
.rd_ecc_error (),
.ddr2_ck_n (ddr2_ck_n),
.dbg_calib_done (dbg_calib_done),
.dbg_calib_err (dbg_calib_err),
.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
.dbg_calib_rden_dly (dbg_calib_rden_dly),
.dbg_calib_gate_dly (dbg_calib_gate_dly),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_dq (dbg_idel_up_dq),
.dbg_idel_down_dq (dbg_idel_down_dq),
.dbg_idel_up_dqs (dbg_idel_up_dqs),
.dbg_idel_down_dqs (dbg_idel_down_dqs),
.dbg_idel_up_gate (dbg_idel_up_gate),
.dbg_idel_down_gate (dbg_idel_down_gate),
.dbg_sel_idel_dq (dbg_sel_idel_dq),
.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
.dbg_sel_idel_dqs (dbg_sel_idel_dqs),
.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
.dbg_sel_idel_gate (dbg_sel_idel_gate),
.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate)
, .sp_refresh_disable(sp_refresh_disable)
);
//*****************************************************************
// Hooks to prevent sim/syn compilation errors (mainly for VHDL - but
// keep it also in Verilog version of code) w/ floating inputs if
// DEBUG_EN = 0.
//*****************************************************************
generate
if (DEBUG_EN == 0) begin: gen_dbg_tie_off
assign dbg_idel_up_all = 'b0;
assign dbg_idel_down_all = 'b0;
assign dbg_idel_up_dq = 'b0;
assign dbg_idel_down_dq = 'b0;
assign dbg_idel_up_dqs = 'b0;
assign dbg_idel_down_dqs = 'b0;
assign dbg_idel_up_gate = 'b0;
assign dbg_idel_down_gate = 'b0;
assign dbg_sel_idel_dq = 'b0;
assign dbg_sel_all_idel_dq = 'b0;
assign dbg_sel_idel_dqs = 'b0;
assign dbg_sel_all_idel_dqs = 'b0;
assign dbg_sel_idel_gate = 'b0;
assign dbg_sel_all_idel_gate = 'b0;
end else begin: gen_dbg_enable
`ifdef XILINX_DDR2_CHIPSCOPE
//*****************************************************************
// PHY Debug Port example - see MIG User's Guide, XAPP858 or
// Answer Record 29443
// This logic supports up to 32 DQ and 8 DQS I/O
// NOTES:
// 1. PHY Debug Port demo connects to 4 VIO modules:
// - 3 VIO modules with only asynchronous inputs
// * Monitor IDELAY taps for DQ, DQS, DQS Gate
// * Calibration status
// - 1 VIO module with synchronous outputs
// * Allow dynamic adjustment o f IDELAY taps
// 2. User may need to modify this code to incorporate other
// chipscope-related modules in their larger design (e.g.
// if they have other ILA/VIO modules, they will need to
// for example instantiate a larger ICON module). In addition
// user may want to instantiate more VIO modules to control
// IDELAY for more DQ, DQS than is shown here
//*****************************************************************
icon4 u_icon
(
.control0 (cs_control0),
.control1 (cs_control1),
.control2 (cs_control2),
.control3 (cs_control3)
);
//*****************************************************************
// VIO ASYNC input: Display current IDELAY setting for up to 32
// DQ taps (32x6) = 192
//*****************************************************************
vio_async_in192 u_vio0
(
.control (cs_control0),
.async_in (vio0_in)
);
//*****************************************************************
// VIO ASYNC input: Display current IDELAY setting for up to 8 DQS
// and DQS Gate taps (8x6x2) = 96
//*****************************************************************
vio_async_in96 u_vio1
(
.control (cs_control1),
.async_in (vio1_in)
);
//*****************************************************************
// VIO ASYNC input: Display other calibration results
//*****************************************************************
vio_async_in100 u_vio2
(
.control (cs_control2),
.async_in (vio2_in)
);
//*****************************************************************
// VIO SYNC output: Dynamically change IDELAY taps
//*****************************************************************
vio_sync_out32 u_vio3
(
.control (cs_control3),
.clk (clkdiv0),
.sync_out (vio3_out)
);
//*****************************************************************
// Bit assignments:
// NOTE: Not all VIO, ILA inputs/outputs may be used - these will
// be dependent on the user's particular bit width
//*****************************************************************
if (DQ_WIDTH <= 32) begin: gen_dq_le_32
assign vio0_in[(6*DQ_WIDTH)-1:0]
= dbg_calib_dq_tap_cnt[(6*DQ_WIDTH)-1:0];
end else begin: gen_dq_gt_32
assign vio0_in = dbg_calib_dq_tap_cnt[191:0];
end
if (DQS_WIDTH <= 8) begin: gen_dqs_le_8
assign vio1_in[(6*DQS_WIDTH)-1:0]
= dbg_calib_dqs_tap_cnt[(6*DQS_WIDTH)-1:0];
assign vio1_in[(12*DQS_WIDTH)-1:(6*DQS_WIDTH)]
= dbg_calib_gate_tap_cnt[(6*DQS_WIDTH)-1:0];
end else begin: gen_dqs_gt_32
assign vio1_in[47:0] = dbg_calib_dqs_tap_cnt[47:0];
assign vio1_in[95:48] = dbg_calib_gate_tap_cnt[47:0];
end
//dbg_calib_rd_data_sel
if (DQS_WIDTH <= 8) begin: gen_rdsel_le_8
assign vio2_in[(DQS_WIDTH)+7:8]
= dbg_calib_rd_data_sel[(DQS_WIDTH)-1:0];
end else begin: gen_rdsel_gt_32
assign vio2_in[15:8]
= dbg_calib_rd_data_sel[7:0];
end
//dbg_calib_rden_dly
if (DQS_WIDTH <= 8) begin: gen_calrd_le_8
assign vio2_in[(5*DQS_WIDTH)+19:20]
= dbg_calib_rden_dly[(5*DQS_WIDTH)-1:0];
end else begin: gen_calrd_gt_32
assign vio2_in[59:20]
= dbg_calib_rden_dly[39:0];
end
//dbg_calib_gate_dly
if (DQS_WIDTH <= 8) begin: gen_calgt_le_8
assign vio2_in[(5*DQS_WIDTH)+59:60]
= dbg_calib_gate_dly[(5*DQS_WIDTH)-1:0];
end else begin: gen_calgt_gt_32
assign vio2_in[99:60]
= dbg_calib_gate_dly[39:0];
end
//dbg_sel_idel_dq
if (DQ_BITS <= 5) begin: gen_selid_le_5
assign dbg_sel_idel_dq[DQ_BITS-1:0]
= vio3_out[DQ_BITS+7:8];
end else begin: gen_selid_gt_32
assign dbg_sel_idel_dq[4:0]
= vio3_out[12:8];
end
//dbg_sel_idel_dqs
if (DQS_BITS <= 3) begin: gen_seldqs_le_3
assign dbg_sel_idel_dqs[DQS_BITS:0]
= vio3_out[(DQS_BITS+16):16];
end else begin: gen_seldqs_gt_32
assign dbg_sel_idel_dqs[3:0]
= vio3_out[19:16];
end
//dbg_sel_idel_gate
if (DQS_BITS <= 3) begin: gen_gtdqs_le_3
assign dbg_sel_idel_gate[DQS_BITS:0]
= vio3_out[(DQS_BITS+21):21];
end else begin: gen_gtdqs_gt_32
assign dbg_sel_idel_gate[3:0]
= vio3_out[24:21];
end
`endif // `ifdef XILINX_DDR2_CHIPSCOPE
assign vio2_in[3:0] = dbg_calib_done;
assign vio2_in[7:4] = dbg_calib_err;
assign dbg_idel_up_all = vio3_out[0];
assign dbg_idel_down_all = vio3_out[1];
assign dbg_idel_up_dq = vio3_out[2];
assign dbg_idel_down_dq = vio3_out[3];
assign dbg_idel_up_dqs = vio3_out[4];
assign dbg_idel_down_dqs = vio3_out[5];
assign dbg_idel_up_gate = vio3_out[6];
assign dbg_idel_down_gate = vio3_out[7];
assign dbg_sel_all_idel_dq = vio3_out[15];
assign dbg_sel_all_idel_dqs = vio3_out[20];
assign dbg_sel_all_idel_gate = vio3_out[25];
end
endgenerate
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_1clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Single clock, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module ram_1clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLK,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
`include "functions.vh"
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLK) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_BLACKBOX_V
`define SKY130_FD_SC_HVL__INV_BLACKBOX_V
/**
* inv: Inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__inv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:55:10 10/10/2013
// Design Name:
// Module Name: mod_fsm_barra
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fsm_barra(clk, start_barra, bussy_barra, barra_y, speed, up_sync, down_sync);
//Definicion de las variables
input clk, start_barra, up_sync, down_sync;
input [4:0] speed;//Revisar esto
output bussy_barra;
output reg [9:0] barra_y;
reg comenzar;
reg [2:0]state;
//Definimos los estados de la FSM
parameter STATE_0 = 0;
parameter STATE_1 = 1;
parameter STATE_2 = 2;
//Limite de la pantalla
parameter LIMIT_MAX = 429;
initial
begin
comenzar <= 0;
end
always@(posedge clk)
begin
case(state)//Se va recorriendo estado por estado
STATE_0:
begin
if (start_barra)
begin
comenzar <= 1;
state <= STATE_1;
end
end
STATE_1:
begin
barra_y <= barra_y - speed*up_sync;
barra_y <= barra_y + speed*down_sync;
state <= STATE_2;
end
STATE_2:
begin
if (barra_y >= LIMIT_MAX)
begin
barra_y <= LIMIT_MAX;
end
else if(barra_y <= 0)
begin
barra_y <= 0;
end
end
endcase
end
//Se definen los valores de salida
assign bussy_barra = ((state == STATE_0)||(state == STATE_1))&&(comenzar == 1);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:27:52 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_sync_ref_0_0 -prefix
// system_vga_sync_ref_0_0_ system_vga_sync_ref_1_0_stub.v
// Design : system_vga_sync_ref_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync_ref,Vivado 2016.4" *)
module system_vga_sync_ref_0_0(clk, rst, hsync, vsync, start, active, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,hsync,vsync,start,active,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
input hsync;
input vsync;
output start;
output active;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
//
// Designed by Qiang Wu
//
`timescale 1ns/1ps
`include "NF_2.1_defines.v"
`include "reg_defines_reference_router.v"
`include "registers.v"
module ppu(
input clk,
input core_sp_clk,
input reset,
// for input switch
input [63:0] in_data0,
input [15:0] in_pkt_route0,
input in_wr0,
input in_req0,
output in_ack0,
input [63:0] in_data1,
input [15:0] in_pkt_route1,
input in_wr1,
input in_req1,
output in_ack1,
input [63:0] in_data2,
input [15:0] in_pkt_route2,
input in_wr2,
input in_req2,
output in_ack2,
input [63:0] in_data3,
input [15:0] in_pkt_route3,
input in_wr3,
input in_req3,
output in_ack3,
// for output switch
output [63:0] out_data0,
output [15:0] out_pkt_route0,
output out_wr0,
output out_req0,
input out_ack0,
output out_bop0,
output out_eop0,
input out_rdy0,
output [63:0] out_data1,
output [15:0] out_pkt_route1,
output out_wr1,
output out_req1,
input out_ack1,
output out_bop1,
output out_eop1,
input out_rdy1,
output [63:0] out_data2,
output [15:0] out_pkt_route2,
output out_wr2,
output out_req2,
input out_ack2,
output out_bop2,
output out_eop2,
input out_rdy2,
output [63:0] out_data3,
output [15:0] out_pkt_route3,
output out_wr3,
output out_req3,
input out_ack3,
output out_bop3,
output out_eop3,
input out_rdy3,
//for monitor
output [31:0] pp_mem_addr,
//output [31:0] instruction_sec_mon,
//output [31:0] prog_counter_sec_mon,
input pkt_drop
);
wire [63:0] pb_in_data0;
wire [15:0] pb_in_pkt_route0;
wire pb_in_wr0;
wire pb_in_req0;
wire pb_in_ack0;
wire pb_in_empty0;
wire [63:0] pb_in_data1;
wire [15:0] pb_in_pkt_route1;
wire pb_in_wr1;
wire pb_in_req1;
wire pb_in_ack1;
wire pb_in_empty1;
wire [63:0] pb_in_data2;
wire [15:0] pb_in_pkt_route2;
wire pb_in_wr2;
wire pb_in_req2;
wire pb_in_ack2;
wire pb_in_empty2;
wire [63:0] pb_in_data3;
wire [15:0] pb_in_pkt_route3;
wire pb_in_wr3;
wire pb_in_req3;
wire pb_in_ack3;
wire pb_in_empty3;
wire [63:0] pb_out_data0;
wire [15:0] pb_out_pkt_route0;
wire pb_out_wr0;
wire pb_out_req0;
wire pb_out_ack0;
wire [1:0] pb_out_neighbor0;
wire pb_out_bop0;
wire pb_out_eop0;
wire pb_out_rdy0;
wire [63:0] pb_out_data1;
wire [15:0] pb_out_pkt_route1;
wire pb_out_wr1;
wire pb_out_req1;
wire pb_out_ack1;
wire [1:0] pb_out_neighbor1;
wire pb_out_bop1;
wire pb_out_eop1;
wire pb_out_rdy1;
wire [63:0] pb_out_data2;
wire [15:0] pb_out_pkt_route2;
wire pb_out_wr2;
wire pb_out_req2;
wire pb_out_ack2;
wire [1:0] pb_out_neighbor2;
wire pb_out_bop2;
wire pb_out_eop2;
wire pb_out_rdy2;
wire [63:0] pb_out_data3;
wire [15:0] pb_out_pkt_route3;
wire pb_out_wr3;
wire pb_out_req3;
wire pb_out_ack3;
wire [1:0] pb_out_neighbor3;
wire pb_out_bop3;
wire pb_out_eop3;
wire pb_out_rdy3;
wire [10:2] pm_addr0;
wire [31:0] pm_data_in0;
wire [31:0] pm_data_out0;
wire pm_we0;
wire pm_req0;
wire pm_done0;
wire pm_wr_pkt_len0;
wire [7:0] pm_pkt_len0;
wire [10:2] pm_addr1;
wire [31:0] pm_data_in1;
wire [31:0] pm_data_out1;
wire pm_we1;
wire pm_req1;
wire pm_done1;
wire pm_wr_pkt_len1;
wire [7:0] pm_pkt_len1;
wire [10:2] pm_addr2;
wire [31:0] pm_data_in2;
wire [31:0] pm_data_out2;
wire pm_we2;
wire pm_req2;
wire pm_done2;
wire pm_wr_pkt_len2;
wire [7:0] pm_pkt_len2;
wire [10:2] pm_addr3;
wire [31:0] pm_data_in3;
wire [31:0] pm_data_out3;
wire pm_we3;
wire pm_req3;
wire pm_done3;
wire pm_wr_pkt_len3;
wire [7:0] pm_pkt_len3;
wire [10:2] pm_addr;
wire [31:0] pm_data_in;
wire [31:0] pm_data_out;
wire [3:0] pm_req;
wire pm_we;
wire pm_done;
wire pm_wr_pkt_len;
wire [7:0] pm_pkt_len;
assign pm_req[0] = pm_req0;
assign pm_req[1] = pm_req1;
assign pm_req[2] = pm_req2;
assign pm_req[3] = pm_req3;
wire [13:2] lr_addr;
wire [31:0] lr_data_in;
wire [31:0] lr_data_out;
wire [3:0] lr_bs;
wire [31:0] sp_data_in;
wire [31:0] sp_data_out;
wire [31:0] sp_mem_addr;
wire [3:0] sp_bs;
wire sp_we;
reg sp_ack;
reg sp_pkt_done;
wire local_reset;
//monitor
assign local_reset = (pkt_drop|reset);
wire [239:0] TRIG1;
wire [239:0] TRIG2;
wire [239:0] TRIG3;
wire [239:0] TRIG4;
wire [239:0] TRIG5;
wire [239:0] TRIG6;
wire [239:0] TRIG7;
wire [239:0] TRIG8;
//wire [239:0] TRIG9;
//wire [239:0] TRIG10;
in_switch in_switch(
.clk (clk),
.reset (reset),
.TRIG0 (TRIG1),
.in_data0 (in_data0),
.in_pkt_route0 (in_pkt_route0),
.in_wr0 (in_wr0),
.in_req0 (in_req0),
.in_ack0 (in_ack0),
.in_data1 (in_data1),
.in_pkt_route1 (in_pkt_route1),
.in_wr1 (in_wr1),
.in_req1 (in_req1),
.in_ack1 (in_ack1),
.in_data2 (in_data2),
.in_pkt_route2 (in_pkt_route2),
.in_wr2 (in_wr2),
.in_req2 (in_req2),
.in_ack2 (in_ack2),
.in_data3 (in_data3),
.in_pkt_route3 (in_pkt_route3),
.in_wr3 (in_wr3),
.in_req3 (in_req3),
.in_ack3 (in_ack3),
.pb_in_data0 (pb_in_data0),
.pb_in_pkt_route0 (pb_in_pkt_route0),
.pb_in_wr0 (pb_in_wr0),
.pb_in_req0 (pb_in_req0),
.pb_in_ack0 (pb_in_ack0),
.pb_in_empty0 (pb_in_empty0),
.pb_in_data1 (pb_in_data1),
.pb_in_pkt_route1 (pb_in_pkt_route1),
.pb_in_wr1 (pb_in_wr1),
.pb_in_req1 (pb_in_req1),
.pb_in_ack1 (pb_in_ack1),
.pb_in_empty1 (pb_in_empty1),
.pb_in_data2 (pb_in_data2),
.pb_in_pkt_route2 (pb_in_pkt_route2),
.pb_in_wr2 (pb_in_wr2),
.pb_in_req2 (pb_in_req2),
.pb_in_ack2 (pb_in_ack2),
.pb_in_empty2 (pb_in_empty2),
.pb_in_data3 (pb_in_data3),
.pb_in_pkt_route3 (pb_in_pkt_route3),
.pb_in_wr3 (pb_in_wr3),
.pb_in_req3 (pb_in_req3),
.pb_in_ack3 (pb_in_ack3),
.pb_in_empty3 (pb_in_empty3)
);
out_switch out_switch(
.clk (clk),
.reset (reset),
.TRIG0 (TRIG6),
.pb_out_data0 (pb_out_data0),
.pb_out_pkt_route0 (pb_out_pkt_route0),
.pb_out_wr0 (pb_out_wr0),
.pb_out_req0 (pb_out_req0),
.pb_out_ack0 (pb_out_ack0),
.pb_out_neighbor0 (pb_out_neighbor0),
.pb_out_bop0 (pb_out_bop0),
.pb_out_eop0 (pb_out_eop0),
.pb_out_rdy0 (pb_out_rdy0),
.pb_out_data1 (pb_out_data1),
.pb_out_pkt_route1 (pb_out_pkt_route1),
.pb_out_wr1 (pb_out_wr1),
.pb_out_req1 (pb_out_req1),
.pb_out_ack1 (pb_out_ack1),
.pb_out_neighbor1 (pb_out_neighbor1),
.pb_out_bop1 (pb_out_bop1),
.pb_out_eop1 (pb_out_eop1),
.pb_out_rdy1 (pb_out_rdy1),
.pb_out_data2 (pb_out_data2),
.pb_out_pkt_route2 (pb_out_pkt_route2),
.pb_out_wr2 (pb_out_wr2),
.pb_out_req2 (pb_out_req2),
.pb_out_ack2 (pb_out_ack2),
.pb_out_neighbor2 (pb_out_neighbor2),
.pb_out_bop2 (pb_out_bop2),
.pb_out_eop2 (pb_out_eop2),
.pb_out_rdy2 (pb_out_rdy2),
.pb_out_data3 (pb_out_data3),
.pb_out_pkt_route3 (pb_out_pkt_route3),
.pb_out_wr3 (pb_out_wr3),
.pb_out_req3 (pb_out_req3),
.pb_out_ack3 (pb_out_ack3),
.pb_out_neighbor3 (pb_out_neighbor3),
.pb_out_bop3 (pb_out_bop3),
.pb_out_eop3 (pb_out_eop3),
.pb_out_rdy3 (pb_out_rdy3),
.out_data0 (out_data0),
.out_pkt_route0 (out_pkt_route0),
.out_wr0 (out_wr0),
.out_req0 (out_req0),
.out_ack0 (out_ack0),
.out_bop0 (out_bop0),
.out_eop0 (out_eop0),
.out_rdy0 (out_rdy0),
.out_data1 (out_data1),
.out_pkt_route1 (out_pkt_route1),
.out_wr1 (out_wr1),
.out_req1 (out_req1),
.out_ack1 (out_ack1),
.out_bop1 (out_bop1),
.out_eop1 (out_eop1),
.out_rdy1 (out_rdy1),
.out_data2 (out_data2),
.out_pkt_route2 (out_pkt_route2),
.out_wr2 (out_wr2),
.out_req2 (out_req2),
.out_ack2 (out_ack2),
.out_bop2 (out_bop2),
.out_eop2 (out_eop2),
.out_rdy2 (out_rdy2),
.out_data3 (out_data3),
.out_pkt_route3 (out_pkt_route3),
.out_wr3 (out_wr3),
.out_req3 (out_req3),
.out_ack3 (out_ack3),
.out_bop3 (out_bop3),
.out_eop3 (out_eop3),
.out_rdy3 (out_rdy3)
);
packet_buffer pb0(
.clk (clk),
.reset (reset),
.TRIG0 (TRIG2),
.in_data (pb_in_data0),
.in_pkt_route (pb_in_pkt_route0),
.in_wr (pb_in_wr0),
.in_req (pb_in_req0),
.in_ack (pb_in_ack0),
.in_empty (pb_in_empty0),
.out_data (pb_out_data0),
.out_pkt_route (pb_out_pkt_route0),
.out_wr (pb_out_wr0),
.out_req (pb_out_req0),
.out_ack (pb_out_ack0),
.out_neighbor (pb_out_neighbor0),
.out_bop (pb_out_bop0),
.out_eop (pb_out_eop0),
.out_rdy (pb_out_rdy0),
.proc_addr (pm_addr0),
.proc_data_in (pm_data_in0),
.proc_data_out (pm_data_out0),
.proc_we (pm_we0),
.proc_req (pm_req0),
.proc_done (pm_done0),
.proc_wr_pkt_len(pm_wr_pkt_len0),
.proc_pkt_len (pm_pkt_len0)
);
packet_buffer pb1(
.clk (clk),
.reset (reset),
.TRIG0 (TRIG3),
.in_data (pb_in_data1),
.in_pkt_route (pb_in_pkt_route1),
.in_wr (pb_in_wr1),
.in_req (pb_in_req1),
.in_ack (pb_in_ack1),
.in_empty (pb_in_empty1),
.out_data (pb_out_data1),
.out_pkt_route (pb_out_pkt_route1),
.out_wr (pb_out_wr1),
.out_req (pb_out_req1),
.out_ack (pb_out_ack1),
.out_neighbor (pb_out_neighbor1),
.out_bop (pb_out_bop1),
.out_eop (pb_out_eop1),
.out_rdy (pb_out_rdy1),
.proc_addr (pm_addr1),
.proc_data_in (pm_data_in1),
.proc_data_out (pm_data_out1),
.proc_we (pm_we1),
.proc_req (pm_req1),
.proc_done (pm_done1),
.proc_wr_pkt_len(pm_wr_pkt_len1),
.proc_pkt_len (pm_pkt_len1)
);
packet_buffer pb2(
.clk (clk),
.reset (reset),
.TRIG0 (TRIG4),
.in_data (pb_in_data2),
.in_pkt_route (pb_in_pkt_route2),
.in_wr (pb_in_wr2),
.in_req (pb_in_req2),
.in_ack (pb_in_ack2),
.in_empty (pb_in_empty2),
.out_data (pb_out_data2),
.out_pkt_route (pb_out_pkt_route2),
.out_wr (pb_out_wr2),
.out_req (pb_out_req2),
.out_ack (pb_out_ack2),
.out_neighbor (pb_out_neighbor2),
.out_bop (pb_out_bop2),
.out_eop (pb_out_eop2),
.out_rdy (pb_out_rdy2),
.proc_addr (pm_addr2),
.proc_data_in (pm_data_in2),
.proc_data_out (pm_data_out2),
.proc_we (pm_we2),
.proc_req (pm_req2),
.proc_done (pm_done2),
.proc_wr_pkt_len(pm_wr_pkt_len2),
.proc_pkt_len (pm_pkt_len2)
);
packet_buffer pb3(
.clk (clk),
.reset (reset),
.TRIG0 (TRIG5),
.in_data (pb_in_data3),
.in_pkt_route (pb_in_pkt_route3),
.in_wr (pb_in_wr3),
.in_req (pb_in_req3),
.in_ack (pb_in_ack3),
.in_empty (pb_in_empty3),
.out_data (pb_out_data3),
.out_pkt_route (pb_out_pkt_route3),
.out_wr (pb_out_wr3),
.out_req (pb_out_req3),
.out_ack (pb_out_ack3),
.out_neighbor (pb_out_neighbor3),
.out_bop (pb_out_bop3),
.out_eop (pb_out_eop3),
.out_rdy (pb_out_rdy3),
.proc_addr (pm_addr3),
.proc_data_in (pm_data_in3),
.proc_data_out (pm_data_out3),
.proc_we (pm_we3),
.proc_req (pm_req3),
.proc_done (pm_done3),
.proc_wr_pkt_len(pm_wr_pkt_len3),
.proc_pkt_len (pm_pkt_len3)
);
lr0 lr0(
.clk (clk),
.addr (lr_addr[13:2]),
.data_in (lr_data_in),
.data_out (lr_data_out),
.we (lr_bs),
.en (1'b1),
.reset (reset)
);
reg [1:0] curr_pb;
reg [1:0] curr_pb_next;
wire [1:0] curr_pb_plus_1;
assign curr_pb_plus_1 = (curr_pb == 2'b11) ? 0 : curr_pb + 1'b1;
reg sp_state;
reg sp_state_next;
always @(posedge clk)
begin
if(reset) begin
curr_pb <= 0;
sp_state <= 0;
end else begin
curr_pb <= curr_pb_next;
sp_state <= sp_state_next;
end
end
parameter SP_IDLE = 1'b0,
SP_PROC = 1'b1;
always @(*) begin
sp_ack = 0;
sp_state_next = sp_state;
case(sp_state)
SP_IDLE: begin
curr_pb_next = curr_pb;
if(pm_req[curr_pb]) begin
sp_state_next = SP_PROC;
end else begin
curr_pb_next = curr_pb_plus_1;
end
end
SP_PROC: begin
sp_ack = 1;
if(sp_pkt_done) begin
sp_state_next = SP_IDLE;
end
end
endcase
end
assign pm_addr0 = (curr_pb == 2'b00) ? pm_addr : 0 ;
assign pm_addr1 = (curr_pb == 2'b01) ? pm_addr : 0 ;
assign pm_addr2 = (curr_pb == 2'b10) ? pm_addr : 0 ;
assign pm_addr3 = (curr_pb == 2'b11) ? pm_addr : 0 ;
assign pm_data_in0 = (curr_pb == 2'b00) ? pm_data_in : 0;
assign pm_data_in1 = (curr_pb == 2'b01) ? pm_data_in : 0;
assign pm_data_in2 = (curr_pb == 2'b10) ? pm_data_in : 0;
assign pm_data_in3 = (curr_pb == 2'b11) ? pm_data_in : 0;
assign pm_data_out = (curr_pb == 2'b00) ? pm_data_out0 :
(curr_pb == 2'b01) ? pm_data_out1 :
(curr_pb == 2'b10) ? pm_data_out2 :
(curr_pb == 2'b11) ? pm_data_out3 : 0 ;
assign pm_we0 = (curr_pb == 2'b00) ? pm_we : 0 ;
assign pm_we1 = (curr_pb == 2'b01) ? pm_we : 0 ;
assign pm_we2 = (curr_pb == 2'b10) ? pm_we : 0 ;
assign pm_we3 = (curr_pb == 2'b11) ? pm_we : 0 ;
assign pm_done0 = (curr_pb == 2'b00) ? pm_done : 0 ;
assign pm_done1 = (curr_pb == 2'b01) ? pm_done : 0 ;
assign pm_done2 = (curr_pb == 2'b10) ? pm_done : 0 ;
assign pm_done3 = (curr_pb == 2'b11) ? pm_done : 0 ;
assign pm_wr_pkt_len0 = (curr_pb == 2'b00) ? pm_wr_pkt_len : 0 ;
assign pm_wr_pkt_len1 = (curr_pb == 2'b01) ? pm_wr_pkt_len : 0 ;
assign pm_wr_pkt_len2 = (curr_pb == 2'b10) ? pm_wr_pkt_len : 0 ;
assign pm_wr_pkt_len3 = (curr_pb == 2'b11) ? pm_wr_pkt_len : 0 ;
assign pm_pkt_len0 = (curr_pb == 2'b00) ? sp_data_out[7:0] : 0;
assign pm_pkt_len1 = (curr_pb == 2'b01) ? sp_data_out[7:0] : 0;
assign pm_pkt_len2 = (curr_pb == 2'b10) ? sp_data_out[7:0] : 0;
assign pm_pkt_len3 = (curr_pb == 2'b11) ? sp_data_out[7:0] : 0;
// memory selection
// 0x00000000 - 0x00000800 localram
// 0x10000000 - 0x10000000 packetmem
// 0x20000000 - 0x20000000 packet_done
//monitor
assign pp_mem_addr = sp_mem_addr;
//
assign lr_addr = (sp_mem_addr[29:28] == 2'b00) ? sp_mem_addr[13:2] : 0 ;
assign lr_data_in = (sp_mem_addr[29:28] == 2'b00) ? sp_data_out : 0 ;
assign lr_bs = (sp_mem_addr[29:28] == 2'b00) ? {4{sp_we}} : 0 ;
assign pm_addr = (sp_mem_addr[29:28] == 2'b01) ? sp_mem_addr[12:2] : 0 ;
assign pm_data_in = (sp_mem_addr[29:28] == 2'b01) ? sp_data_out : 0 ;
assign pm_we = (sp_mem_addr[29:28] == 2'b01) ? sp_we : 0 ;
assign pm_done = sp_pkt_done;
assign pm_wr_pkt_len = (sp_mem_addr[30:28] == 3'b011) ? 1 : 0 ; // made a change here by hari
assign sp_data_in = (sp_mem_addr[29:28] == 2'b00) ? lr_data_out :
(sp_mem_addr[29:28] == 2'b01) ? pm_data_out : 0 ;
always @(posedge core_sp_clk) begin
if(sp_mem_addr[30:28] == 3'b011) begin // made a change here by hari
sp_pkt_done <= 1;
end else begin
sp_pkt_done <= 0;
end
end
yf32_core service_processor(
.CLK_I (core_sp_clk),
.RST_I (reset),
.ADR_O (sp_mem_addr),
.DAT_I (sp_data_in),
.DAT_O (sp_data_out),
.WE_O (sp_we),
.SEL_O (sp_bs),
.STB_O (),
.ACK_I (sp_ack),
.CYC_O (),
// .INS_O (instruction_sec_mon),
// .PC_O (prog_counter_sec_mon),
.INT_I (1'b0)
);
/*
plasma uut (
.clk(core_sp_clk),
.reset(reset),
//.uart_write(uart_write),
.uart_read(1'b0),
//.opcode_test_check(instruction),
//.pc_future_test_check(pc_future_test_check),
.address(sp_mem_addr),
.byte_we(sp_bs),
.data_write(sp_data_out),
.data_read(sp_data_in),
.mem_pause_in(sp_ack)
//.gpio0_out(gpio0_out),
//.gpioA_in(gpioA_in)
);
*/
wire [35:0] CONTROL0;
wire [239:0] TRIG0;
/*
chipscope_icon_v1_03_a cs_icon (
.CONTROL0(CONTROL0)
);
chipscope_ila_v1_02_a cs_ila (
.CONTROL(CONTROL0),
.CLK(clk),
.TRIG0(TRIG0),
.TRIG1(TRIG1),
.TRIG2(TRIG2),
.TRIG3(TRIG3),
.TRIG4(TRIG4),
.TRIG5(TRIG5),
.TRIG6(TRIG6),
.TRIG7(TRIG7),
.TRIG8(TRIG8)
// .TRIG9(TRIG9),
// .TRIG10(TRIG10)
);
*/
assign TRIG0[0] = in_wr0;
assign TRIG0[1] = in_req0;
assign TRIG0[2] = in_ack0;
assign TRIG0[3] = in_wr1;
assign TRIG0[4] = in_req1;
assign TRIG0[5] = in_ack1;
assign TRIG0[6] = in_wr2;
assign TRIG0[7] = in_req2;
assign TRIG0[8] = in_ack2;
assign TRIG0[9] = in_wr3;
assign TRIG0[10] = in_req3;
assign TRIG0[11] = in_ack3;
assign TRIG0[21] = out_wr0;
assign TRIG0[22] = out_req0;
assign TRIG0[23] = out_ack0;
assign TRIG0[24] = out_bop0;
assign TRIG0[25] = out_eop0;
assign TRIG0[26] = out_rdy0;
assign TRIG0[27] = out_wr1;
assign TRIG0[28] = out_req1;
assign TRIG0[29] = out_ack1;
assign TRIG0[30] = out_bop1;
assign TRIG0[31] = out_eop1;
assign TRIG0[32] = out_rdy1;
assign TRIG0[33] = out_wr2;
assign TRIG0[34] = out_req2;
assign TRIG0[35] = out_ack2;
assign TRIG0[36] = out_bop2;
assign TRIG0[37] = out_eop2;
assign TRIG0[38] = out_rdy2;
assign TRIG0[39] = out_wr3;
assign TRIG0[40] = out_req3;
assign TRIG0[41] = out_ack3;
assign TRIG0[42] = out_bop3;
assign TRIG0[43] = out_eop3;
assign TRIG0[44] = out_rdy3;
assign TRIG0[50] = pb_in_wr0;
assign TRIG0[51] = pb_in_req0;
assign TRIG0[52] = pb_in_ack0;
assign TRIG0[53] = pb_in_empty0;
assign TRIG0[54] = pb_in_wr1;
assign TRIG0[55] = pb_in_req1;
assign TRIG0[56] = pb_in_ack1;
assign TRIG0[57] = pb_in_empty1;
assign TRIG0[58] = pb_in_wr2;
assign TRIG0[59] = pb_in_req2;
assign TRIG0[60] = pb_in_ack2;
assign TRIG0[61] = pb_in_empty2;
assign TRIG0[62] = pb_in_wr3;
assign TRIG0[63] = pb_in_req3;
assign TRIG0[64] = pb_in_ack3;
assign TRIG0[65] = pb_in_empty3;
assign TRIG0[70] = pb_out_wr0;
assign TRIG0[71] = pb_out_req0;
assign TRIG0[72] = pb_out_ack0;
assign TRIG0[74:73] = pb_out_neighbor0;
assign TRIG0[75] = pb_out_bop0;
assign TRIG0[76] = pb_out_eop0;
assign TRIG0[77] = pb_out_rdy0;
assign TRIG0[80] = pb_out_wr1;
assign TRIG0[81] = pb_out_req1;
assign TRIG0[82] = pb_out_ack1;
assign TRIG0[84:83] = pb_out_neighbor1;
assign TRIG0[85] = pb_out_bop1;
assign TRIG0[86] = pb_out_eop1;
assign TRIG0[87] = pb_out_rdy1;
assign TRIG0[90] = pb_out_wr2;
assign TRIG0[91] = pb_out_req2;
assign TRIG0[92] = pb_out_ack2;
assign TRIG0[94:93] = pb_out_neighbor2;
assign TRIG0[95] = pb_out_bop2;
assign TRIG0[96] = pb_out_eop2;
assign TRIG0[97] = pb_out_rdy2;
assign TRIG0[100] = pb_out_wr3;
assign TRIG0[101] = pb_out_req3;
assign TRIG0[102] = pb_out_ack3;
assign TRIG0[104:103] = pb_out_neighbor3;
assign TRIG0[105] = pb_out_bop3;
assign TRIG0[106] = pb_out_eop3;
assign TRIG0[107] = pb_out_rdy3;
assign TRIG0[111:110] = sp_state;
assign TRIG0[113:112] = curr_pb;
assign TRIG7[31:0] = pm_data_in0;
assign TRIG7[63:32] = pm_data_out0;
assign TRIG7[131:100] = pm_data_in1;
assign TRIG7[163:132] = pm_data_out1;
assign TRIG8[31:0] = pm_data_in2;
assign TRIG8[63:32] = pm_data_out2;
assign TRIG8[131:100] = pm_data_in3;
assign TRIG8[163:132] = pm_data_out3;
endmodule
|
// date:2016/3/15
//engineer: zhaishaomin
// module function: output inst_word according to coming pc ,
// if missed , it will stall the pipeline and gen a msg to find the requested cache block
// including the origal inst_word
module inst_cache (//input
clk,
rst,
// from pc
v_pc,
pc,
//from ic_download
inst_4word,
v_inst_4word,
//output
// to local mem or OUT_req upload
v_ic_req,
local_or_OUT, //1:local ,0:OUT_req
req_msg,
v_inst,
inst
);
//input
input clk;
input rst;
// from pc
input v_pc;
input [31:0] pc;
//from ic_download
input [127:0] inst_4word;
input v_inst_4word;
//output
// to local mem or OUT_req upload
output v_ic_req;
output local_or_OUT; //1:local ,0:OUT_req
output [47:0] req_msg;
output v_inst;
output [31:0] inst;
/////////////////////////////////////////////////////////////////////
////////////////inst cache data and tag//////////////////////////////
reg tag_we;
reg tag_re;
reg data_we;
reg data_re;
reg [5:0] state_tag_in;
wire [5:0] state_tag_out;
reg [31:0] seled_addr;
reg [127:0]data_write;
wire [127:0]data_read;
reg [31:0] inst1;
reg [31:0] inst2;
reg v_inst;
reg local_or_OUT;
reg [47:0] req_msg;
reg inst1_inst2;
reg v_ic_req;
SP_BRAM_SRd #(32,6,5) tag_ram(.clk(clk), .we(tag_we), .re(tag_re), .a(seled_addr[8:4]), .di(state_tag_in), .dout(state_tag_out));
SP_BRAM_SRd #(32,128,5) data_ram(.clk(clk), .we(data_we), .re(data_re), .a(seled_addr[8:4]), .di(data_write), .dout(data_read));
/////////////////////////////////////////////////////////////////////
/////////////////inst cache fsm//////////////////////////////////////
//paramter
parameter inst_idle=2'b00;
parameter inst_comp_tag=2'b01;
parameter inst_gen_req=2'b10;
parameter inst_wait_rep=2'b11;
parameter local_id=2'b00;
parameter instreq_cmd=5'b00110;
reg [1:0] inst_cstate;
reg [1:0] inst_nstate;
always@(posedge clk)
begin
if(rst)
inst_cstate<=2'b00;
else
inst_cstate<=inst_nstate;
end
//fsm always block
always@(*)
begin
//default values
v_inst=1'b0;
v_ic_req=1'b0;
tag_we=1'b0;
tag_re=1'b0;
data_we=1'b0;
data_re=1'b0;
state_tag_in=5'b00000;
seled_addr=32'h0000;
data_write=128'h0000;
local_or_OUT=1'b0;
req_msg=48'h0000;
inst_nstate=inst_cstate;
inst1 = data_read[31:0];
inst2 = inst_4word[31:0];
inst1_inst2=1'b0;
/////////////////////////////////////////////////
/*read out correct word(32-bit) from cache (to if_id)*/
case(pc[3:2])
2'b00:inst1 = data_read[31:0];
2'b01:inst1 = data_read[63:32];
2'b10:inst1 = data_read[95:64];
2'b11:inst1 = data_read[127:96];
endcase
/////////////////////////////////////////////////
/* read inst_word directly from inst_4word (to if_id) */
case(pc[3:2])
2'b00:inst2 = inst_4word[31:0];
2'b01:inst2 = inst_4word[63:32];
2'b10:inst2 = inst_4word[95:64];
2'b11:inst2 = inst_4word[127:96];
endcase
case(inst_cstate)
inst_idle:
begin
if(v_pc)
inst_nstate=inst_comp_tag;
end
inst_comp_tag:
begin
tag_re=1'b1;
data_re=1'b1;
if(pc[12:9]==state_tag_out[3:0])
// tag equals
begin // [5:4] 00 inv, 01 wait inst rep , 10 valid
if(state_tag_out[5:4]==2'b10)//read hit
begin
//gen read hit ctrl signals
v_inst=1'b1;
inst1_inst2=1'b0;
inst_nstate=inst_idle;
end
/* else if(state_tag_out[5:4]==2'b01) // state is inv ,so read miss
// NOTE:the core only allow one outstanding cache access,
// so there won't be a case that cpu aceesses see apending state!
begin
if(pc[12:11]==local_id)
begin
req_local_remote=1'b0;
end // local 0 ;remote 1; default :remote ?
nstate=inst_gen_req;
// oneORmore=1'b0;
end */
end
else// tag miss
begin
// gen new tag to tag ram
tag_we=1'b1;
/*new tag*/
state_tag_in = {2'b01,pc[12:9]};
inst_nstate=inst_gen_req;
end
end
inst_gen_req:
begin
if(pc[12:11]==local_id)
begin
local_or_OUT=1'b0;
end // local 0 ;remote 1; default :remote ?
req_msg={pc[12:11],1'b1,local_id,1'b0,instreq_cmd,5'b00000,pc};
v_ic_req=1'b1;
inst_nstate=inst_wait_rep;
end
inst_wait_rep:
begin
if(v_inst_4word)
begin
tag_re=1'b1;
data_write=inst_4word;
data_we=1'b1;
inst1_inst2=1'b1;
v_inst=1'b1;
// gen new tag to tag ram
tag_we=1'b1;
/*new tag*/
state_tag_in = {2'b10,pc[12:9]}; // 10 means valid
end
end
endcase
end
assign inst=inst1_inst2?inst2:inst1;
endmodule
|
module LED (input clk, input enable, input [3:0] val, input [2:0] sidx, output reg[7:0] digit, output reg[7:0] segment);
always @(posedge clk)
begin
if (enable)
begin
case (sidx)
3'd0: begin digit <= 8'b11111110; end
3'd1: begin digit <= 8'b11111101; end
3'd2: begin digit <= 8'b11111011; end
3'd3: begin digit <= 8'b11110111; end
3'd4: begin digit <= 8'b11101111; end
3'd5: begin digit <= 8'b11011111; end
3'd6: begin digit <= 8'b10111111; end
3'd7: begin digit <= 8'b01111111; end
default: begin digit <= 8'b11111111; end
endcase
case (val)
3'b000: begin segment <= 8'b00000011; end
3'b001: begin segment <= 8'b10011111; end
3'b010: begin segment <= 8'b00100101; end
3'b011: begin segment <= 8'b00001101; end
3'b100: begin segment <= 8'b10011001; end
3'b101: begin segment <= 8'b01001001; end
3'b110: begin segment <= 8'b01000001; end
3'b111: begin segment <= 8'b00011111; end
4'b1000: begin segment <= 8'b00000001; end
4'b1001: begin segment <= 8'b00001001; end
default: begin segment <= 8'b11111111; end
endcase
end
end
endmodule
|
/*main function
1)receiving packet from input module and ppc module,and forwarding packets to rdma module
*/
module DISPATHER_OUTPUT(
input clk,
input reset,
input in_input_pkt_wr,// the packet write request of input moudle to dispather_output module
input [133:0] in_input_pkt,//// the packet of input moudle to dispather_output module
input in_input_valid_wr,//the valid flag write request of input moudle to dispather_output module
input in_input_valid,//// the valid flag of input moudle to dispather_output module
output out_input_pkt_almostfull,
input in_ppc_pkt_wr,//the packet write request of ppc moudle to dispather_output module
input [133:0] in_ppc_pkt,// the packet of ppc moudle to dispather_output module
input in_ppc_valid_wr,//the valid flag write request of ppc moudle to dispather_output module
input in_ppc_valid,// the valid flag of ppc moudle to dispather_output module
output out_ppc_pkt_almostfull,
output reg out_rdma_pkt_wr,//the packet write request of dispather_output moudle to rdma module
output reg [133:0] out_rdma_pkt,// the packet of dispather_output moudle to rdma module
output reg out_rdma_valid_wr,//the valid flag write request of dispather_output moudle to rdma module
output reg out_rdma_valid,//the valid flag of dispather_output moudle to rdma module
input in_rdma_pkt_almostfull
);
wire in_input_valid_q;
wire in_input_valid_empty;
reg out_input_valid_rd;
wire [7:0] out_input_pkt_usedw;
assign out_input_pkt_almostfull = out_input_pkt_usedw[7];
reg out_input_pkt_rd;
wire [133:0]in_input_pkt_q;
wire in_ppc_valid_q;
wire in_ppc_valid_empty;
reg out_ppc_valid_rd;
wire out_ppc_pkt_empty;
wire [7:0] out_ppc_pkt_usedw;
assign out_ppc_pkt_almostfull = out_ppc_pkt_usedw[7];
reg out_ppc_pkt_rd;
wire [133:0]in_ppc_pkt_q;
reg ppc_input;//1:input 0:ppc
reg [2:0] current_state;
parameter idle_s = 3'd0,
send_ppc_s = 3'd1,
send_input_s = 3'd2,
discard_input_s=3'd3,
discard_ppc_s=3'd4;
always@(posedge clk or negedge reset) begin
if(!reset) begin
out_rdma_pkt_wr<= 1'b0;
out_rdma_pkt<= 134'b0;
out_rdma_valid_wr<= 1'b0;
out_rdma_valid<=1'b0;
ppc_input<=1'b0;
out_input_valid_rd<=1'b0;
out_input_pkt_rd<=1'b0;
out_ppc_valid_rd<=1'b0;
out_ppc_pkt_rd<=1'b0;
current_state<=idle_s;
end
else begin
case(current_state)
idle_s: begin
out_rdma_pkt_wr<= 1'b0;
out_rdma_valid_wr<= 1'b0;
out_rdma_valid<=1'b0;
if(in_rdma_pkt_almostfull==1'b0) begin
case({in_input_valid_empty,in_ppc_valid_empty})
2'b00: begin//both PPC and INPUT have pkt
if(ppc_input==1'b0) begin//get pkt from PPC Module
out_input_valid_rd<=1'b0;
out_input_pkt_rd<=1'b0;
out_ppc_valid_rd<=1'b1;
out_ppc_pkt_rd<=1'b1;
current_state<=send_ppc_s;
end
else begin
out_input_valid_rd<=1'b1;
out_input_pkt_rd<=1'b1;
out_ppc_valid_rd<=1'b0;
out_ppc_pkt_rd<=1'b0;
current_state<=send_input_s;
end
end
2'b01: begin//only INPUT has pkt
out_input_valid_rd<=1'b1;
out_input_pkt_rd<=1'b1;
out_ppc_valid_rd<=1'b0;
out_ppc_pkt_rd<=1'b0;
current_state<=send_input_s;
end
2'b10: begin//only ppc has pkt
out_input_valid_rd<=1'b0;
out_input_pkt_rd<=1'b0;
out_ppc_valid_rd<=1'b1;
out_ppc_pkt_rd<=1'b1;
current_state<=send_ppc_s;
end
default: begin
out_input_valid_rd<=1'b0;
out_input_pkt_rd<=1'b0;
out_ppc_valid_rd<=1'b0;
out_ppc_pkt_rd<=1'b0;
current_state<=idle_s;
end
endcase
end
else begin
out_input_valid_rd<=1'b0;
out_input_pkt_rd<=1'b0;
out_ppc_valid_rd<=1'b0;
out_ppc_pkt_rd<=1'b0;
current_state<=idle_s;
end
end
send_input_s:begin
out_input_valid_rd<=1'b0;
out_rdma_pkt_wr<=1'b1;
out_rdma_pkt<=in_input_pkt_q;
ppc_input<=1'b0;//get pkt from PPC��Module next time
if(in_input_pkt_q[133:132]==2'b10) begin
out_input_pkt_rd<=1'b0;
out_rdma_valid_wr<=1'b1;
out_rdma_valid<=1'b1;
current_state<=idle_s;
end
else begin
out_input_pkt_rd<=1'b1;
out_rdma_valid_wr<=1'b0;
current_state<=send_input_s;
end
end
send_ppc_s:begin
out_ppc_valid_rd<=1'b0;
out_rdma_pkt_wr<=1'b1;
out_rdma_pkt<=in_ppc_pkt_q;
ppc_input<=1'b1;//get pkt from INPUT��Module next time
if(in_ppc_pkt_q[133:132]==2'b10) begin
out_ppc_pkt_rd<=1'b0;
out_rdma_valid_wr<=1'b1;
current_state<=idle_s;
end
else begin
out_ppc_pkt_rd<=1'b1;
out_rdma_valid_wr<=1'b0;
current_state<=send_ppc_s;
end
end
discard_input_s:begin
out_input_valid_rd<=1'b0;
if(in_ppc_pkt_q[133:132]==2'b10) begin
out_input_pkt_rd<=1'b0;
current_state<=idle_s;
end
else begin
out_input_pkt_rd<=1'b1;
current_state<=discard_input_s;
end
end
discard_ppc_s:begin
out_ppc_valid_rd<=1'b0;
if(in_ppc_pkt_q[133:132]==2'b10) begin
out_ppc_valid_rd<=1'b0;
current_state<=idle_s;
end
else begin
out_ppc_pkt_rd<=1'b1;
current_state<=discard_ppc_s;
end
end
default: begin
out_rdma_pkt_wr<= 1'b0;
out_rdma_valid_wr<= 1'b0;
out_rdma_valid<=1'b0;
out_input_valid_rd<=1'b0;
out_input_pkt_rd<=1'b0;
out_ppc_valid_rd<=1'b0;
out_ppc_pkt_rd<=1'b0;
current_state<=idle_s;
end
endcase
end
end
//--------------------------------From INPUT Module-------------------------
fifo_64_1 FIFO_VALID_input (
.aclr(!reset),
.data(in_input_valid),
.clock(clk),
.rdreq(out_input_valid_rd),
.wrreq(in_input_valid_wr),
.q(in_input_valid_q),
.empty(in_input_valid_empty)
);
fifo_256_134 FIFO_PKT_input (
.aclr(!reset),
.data(in_input_pkt),
.clock(clk),
.rdreq(out_input_pkt_rd),
.wrreq(in_input_pkt_wr),
.q(in_input_pkt_q),
.usedw(out_input_pkt_usedw)
);
//--------------------------------From PPC Module-------------------------
fifo_64_1 FIFO_VALID_PPC (
.aclr(!reset),
.data(in_ppc_valid),
.clock(clk),
.rdreq(out_ppc_valid_rd),
.wrreq(in_ppc_valid_wr),
.q(in_ppc_valid_q),
.empty(in_ppc_valid_empty)
);
fifo_256_134 FIFO_PKT_PPC (
.aclr(!reset),
.data(in_ppc_pkt),
.clock(clk),
.rdreq(out_ppc_pkt_rd),
.wrreq(in_ppc_pkt_wr),
.q(in_ppc_pkt_q),
.usedw(out_ppc_pkt_usedw),
.empty(out_ppc_pkt_empty)
);
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF.v,v 1.11 2009/08/21 23:55:43 harikr Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Bi-Directional Buffer
// /___/ /\ Filename : IOBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/22/06 - CR#226003 - Added integer, real parameter type
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// End Revision
`timescale 1 ps / 1 ps
module IOBUF (O, IO, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
inout IO;
input I, T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
buf B1 (O, IO);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IOBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE);
$finish;
end
endcase
end // initial begin
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Thu Jun 22 05:51:07 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../highlow.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.4 2006/06/22 07:20:00 wig Exp $
// $Date: 2006/06/22 07:20:00 $
// $Log: ent_a.v,v $
// Revision 1.4 2006/06/22 07:20:00 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
//
// Generator: mix_0.pl Revision: 1.45 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_a
//
// No user `defines in this module
module ent_a
//
// Generated Module inst_a
//
(
low_bit_a // Ground bit port
);
// Generated Module Inputs:
input low_bit_a;
// Generated Wires:
wire low_bit_a;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire mix_logic1_0;
wire [3:0] mix_logic1_bus_1;
wire mix_logic0_1;
wire [3:0] mix_logic0_bus_2;
wire [6:0] mix_logic0_bus_3;
wire [3:0] part_zero;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign mix_logic1_0 = 1'b1;
assign mix_logic1_bus_1 = 4'b1111;
assign mix_logic0_1 = 1'b0;
assign mix_logic0_bus_2 = 4'b0000;
assign mix_logic0_bus_3 = 7'b0000000;
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.high_bus_3_0(mix_logic1_bus_1), // Ground wire_low port
.low_bit_aa(mix_logic0_1),
.mix_logic0_bus_2(mix_logic0_bus_2), // Ground port
.mix_logic1_0(mix_logic1_0), // Wire bit to high
.part_zero(part_zero) // Wire two bits to port
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.low_bus_6_0(mix_logic0_bus_3), // Wide low port
.port_part_zero_u({ 2'b00, part_zero[3:2] }) // __W_PORT // Wire two bits to low // // Wire two bits to port // __I_COMBINE_SPLICES
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/////////////////////////////////////////////////////////////////////
//// ////
//// AES SBOX (ROM) ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: aes_sbox.v,v 1.1.1.1 2002/11/09 11:22:38 rudi Exp $
//
// $Date: 2002/11/09 11:22:38 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: aes_sbox.v,v $
// Revision 1.1.1.1 2002/11/09 11:22:38 rudi
// Initial Checkin
//
//
//
//
//
//
`timescale 1ns / 10ps
module aes_sbox(a,d);
input [7:0] a;
output [7:0] d;
reg [7:0] d;
always @(a)
case(a) // synopsys full_case parallel_case
8'h00: d=8'h63;
8'h01: d=8'h7c;
8'h02: d=8'h77;
8'h03: d=8'h7b;
8'h04: d=8'hf2;
8'h05: d=8'h6b;
8'h06: d=8'h6f;
8'h07: d=8'hc5;
8'h08: d=8'h30;
8'h09: d=8'h01;
8'h0a: d=8'h67;
8'h0b: d=8'h2b;
8'h0c: d=8'hfe;
8'h0d: d=8'hd7;
8'h0e: d=8'hab;
8'h0f: d=8'h76;
8'h10: d=8'hca;
8'h11: d=8'h82;
8'h12: d=8'hc9;
8'h13: d=8'h7d;
8'h14: d=8'hfa;
8'h15: d=8'h59;
8'h16: d=8'h47;
8'h17: d=8'hf0;
8'h18: d=8'had;
8'h19: d=8'hd4;
8'h1a: d=8'ha2;
8'h1b: d=8'haf;
8'h1c: d=8'h9c;
8'h1d: d=8'ha4;
8'h1e: d=8'h72;
8'h1f: d=8'hc0;
8'h20: d=8'hb7;
8'h21: d=8'hfd;
8'h22: d=8'h93;
8'h23: d=8'h26;
8'h24: d=8'h36;
8'h25: d=8'h3f;
8'h26: d=8'hf7;
8'h27: d=8'hcc;
8'h28: d=8'h34;
8'h29: d=8'ha5;
8'h2a: d=8'he5;
8'h2b: d=8'hf1;
8'h2c: d=8'h71;
8'h2d: d=8'hd8;
8'h2e: d=8'h31;
8'h2f: d=8'h15;
8'h30: d=8'h04;
8'h31: d=8'hc7;
8'h32: d=8'h23;
8'h33: d=8'hc3;
8'h34: d=8'h18;
8'h35: d=8'h96;
8'h36: d=8'h05;
8'h37: d=8'h9a;
8'h38: d=8'h07;
8'h39: d=8'h12;
8'h3a: d=8'h80;
8'h3b: d=8'he2;
8'h3c: d=8'heb;
8'h3d: d=8'h27;
8'h3e: d=8'hb2;
8'h3f: d=8'h75;
8'h40: d=8'h09;
8'h41: d=8'h83;
8'h42: d=8'h2c;
8'h43: d=8'h1a;
8'h44: d=8'h1b;
8'h45: d=8'h6e;
8'h46: d=8'h5a;
8'h47: d=8'ha0;
8'h48: d=8'h52;
8'h49: d=8'h3b;
8'h4a: d=8'hd6;
8'h4b: d=8'hb3;
8'h4c: d=8'h29;
8'h4d: d=8'he3;
8'h4e: d=8'h2f;
8'h4f: d=8'h84;
8'h50: d=8'h53;
8'h51: d=8'hd1;
8'h52: d=8'h00;
8'h53: d=8'hed;
8'h54: d=8'h20;
8'h55: d=8'hfc;
8'h56: d=8'hb1;
8'h57: d=8'h5b;
8'h58: d=8'h6a;
8'h59: d=8'hcb;
8'h5a: d=8'hbe;
8'h5b: d=8'h39;
8'h5c: d=8'h4a;
8'h5d: d=8'h4c;
8'h5e: d=8'h58;
8'h5f: d=8'hcf;
8'h60: d=8'hd0;
8'h61: d=8'hef;
8'h62: d=8'haa;
8'h63: d=8'hfb;
8'h64: d=8'h43;
8'h65: d=8'h4d;
8'h66: d=8'h33;
8'h67: d=8'h85;
8'h68: d=8'h45;
8'h69: d=8'hf9;
8'h6a: d=8'h02;
8'h6b: d=8'h7f;
8'h6c: d=8'h50;
8'h6d: d=8'h3c;
8'h6e: d=8'h9f;
8'h6f: d=8'ha8;
8'h70: d=8'h51;
8'h71: d=8'ha3;
8'h72: d=8'h40;
8'h73: d=8'h8f;
8'h74: d=8'h92;
8'h75: d=8'h9d;
8'h76: d=8'h38;
8'h77: d=8'hf5;
8'h78: d=8'hbc;
8'h79: d=8'hb6;
8'h7a: d=8'hda;
8'h7b: d=8'h21;
8'h7c: d=8'h10;
8'h7d: d=8'hff;
8'h7e: d=8'hf3;
8'h7f: d=8'hd2;
8'h80: d=8'hcd;
8'h81: d=8'h0c;
8'h82: d=8'h13;
8'h83: d=8'hec;
8'h84: d=8'h5f;
8'h85: d=8'h97;
8'h86: d=8'h44;
8'h87: d=8'h17;
8'h88: d=8'hc4;
8'h89: d=8'ha7;
8'h8a: d=8'h7e;
8'h8b: d=8'h3d;
8'h8c: d=8'h64;
8'h8d: d=8'h5d;
8'h8e: d=8'h19;
8'h8f: d=8'h73;
8'h90: d=8'h60;
8'h91: d=8'h81;
8'h92: d=8'h4f;
8'h93: d=8'hdc;
8'h94: d=8'h22;
8'h95: d=8'h2a;
8'h96: d=8'h90;
8'h97: d=8'h88;
8'h98: d=8'h46;
8'h99: d=8'hee;
8'h9a: d=8'hb8;
8'h9b: d=8'h14;
8'h9c: d=8'hde;
8'h9d: d=8'h5e;
8'h9e: d=8'h0b;
8'h9f: d=8'hdb;
8'ha0: d=8'he0;
8'ha1: d=8'h32;
8'ha2: d=8'h3a;
8'ha3: d=8'h0a;
8'ha4: d=8'h49;
8'ha5: d=8'h06;
8'ha6: d=8'h24;
8'ha7: d=8'h5c;
8'ha8: d=8'hc2;
8'ha9: d=8'hd3;
8'haa: d=8'hac;
8'hab: d=8'h62;
8'hac: d=8'h91;
8'had: d=8'h95;
8'hae: d=8'he4;
8'haf: d=8'h79;
8'hb0: d=8'he7;
8'hb1: d=8'hc8;
8'hb2: d=8'h37;
8'hb3: d=8'h6d;
8'hb4: d=8'h8d;
8'hb5: d=8'hd5;
8'hb6: d=8'h4e;
8'hb7: d=8'ha9;
8'hb8: d=8'h6c;
8'hb9: d=8'h56;
8'hba: d=8'hf4;
8'hbb: d=8'hea;
8'hbc: d=8'h65;
8'hbd: d=8'h7a;
8'hbe: d=8'hae;
8'hbf: d=8'h08;
8'hc0: d=8'hba;
8'hc1: d=8'h78;
8'hc2: d=8'h25;
8'hc3: d=8'h2e;
8'hc4: d=8'h1c;
8'hc5: d=8'ha6;
8'hc6: d=8'hb4;
8'hc7: d=8'hc6;
8'hc8: d=8'he8;
8'hc9: d=8'hdd;
8'hca: d=8'h74;
8'hcb: d=8'h1f;
8'hcc: d=8'h4b;
8'hcd: d=8'hbd;
8'hce: d=8'h8b;
8'hcf: d=8'h8a;
8'hd0: d=8'h70;
8'hd1: d=8'h3e;
8'hd2: d=8'hb5;
8'hd3: d=8'h66;
8'hd4: d=8'h48;
8'hd5: d=8'h03;
8'hd6: d=8'hf6;
8'hd7: d=8'h0e;
8'hd8: d=8'h61;
8'hd9: d=8'h35;
8'hda: d=8'h57;
8'hdb: d=8'hb9;
8'hdc: d=8'h86;
8'hdd: d=8'hc1;
8'hde: d=8'h1d;
8'hdf: d=8'h9e;
8'he0: d=8'he1;
8'he1: d=8'hf8;
8'he2: d=8'h98;
8'he3: d=8'h11;
8'he4: d=8'h69;
8'he5: d=8'hd9;
8'he6: d=8'h8e;
8'he7: d=8'h94;
8'he8: d=8'h9b;
8'he9: d=8'h1e;
8'hea: d=8'h87;
8'heb: d=8'he9;
8'hec: d=8'hce;
8'hed: d=8'h55;
8'hee: d=8'h28;
8'hef: d=8'hdf;
8'hf0: d=8'h8c;
8'hf1: d=8'ha1;
8'hf2: d=8'h89;
8'hf3: d=8'h0d;
8'hf4: d=8'hbf;
8'hf5: d=8'he6;
8'hf6: d=8'h42;
8'hf7: d=8'h68;
8'hf8: d=8'h41;
8'hf9: d=8'h99;
8'hfa: d=8'h2d;
8'hfb: d=8'h0f;
8'hfc: d=8'hb0;
8'hfd: d=8'h54;
8'hfe: d=8'hbb;
8'hff: d=8'h16;
endcase
endmodule
|
// megafunction wizard: %ALTPLL_RECONFIG%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll_reconfig
// ============================================================
// File Name: pll_hdmi_reconf.v
// Megafunction Name(s):
// altpll_reconfig
//
// Simulation Library Files(s):
// altera_mf;cyclone10lp;lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
//altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone 10 LP" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset reset_rom_address rom_address_out rom_data_in write_from_rom write_param write_rom_ena
//VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altpll_reconfig 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 8 lpm_decode 1 lut 3 reg 102
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"ADV_NETLIST_OPT_ALLOWED=\"NEVER_ALLOW\";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1"} *)
module pll_hdmi_reconf_pllrcfg_hk11
(
busy,
clock,
counter_param,
counter_type,
data_in,
data_out,
pll_areset,
pll_areset_in,
pll_configupdate,
pll_scanclk,
pll_scanclkena,
pll_scandata,
pll_scandataout,
pll_scandone,
read_param,
reconfig,
reset,
reset_rom_address,
rom_address_out,
rom_data_in,
write_from_rom,
write_param,
write_rom_ena) /* synthesis synthesis_clearbox=2 */;
output busy;
input clock;
input [2:0] counter_param;
input [3:0] counter_type;
input [8:0] data_in;
output [8:0] data_out;
output pll_areset;
input pll_areset_in;
output pll_configupdate;
output pll_scanclk;
output pll_scanclkena;
output pll_scandata;
input pll_scandataout;
input pll_scandone;
input read_param;
input reconfig;
input reset;
input reset_rom_address;
output [7:0] rom_address_out;
input rom_data_in;
input write_from_rom;
input write_param;
output write_rom_ena;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [2:0] counter_param;
tri0 [3:0] counter_type;
tri0 [8:0] data_in;
tri0 pll_areset_in;
tri0 pll_scandataout;
tri0 pll_scandone;
tri0 read_param;
tri0 reconfig;
tri0 reset_rom_address;
tri0 rom_data_in;
tri0 write_from_rom;
tri0 write_param;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_altsyncram4_q_a;
wire wire_le_comb10_combout;
wire wire_le_comb8_combout;
wire wire_le_comb9_combout;
reg [7:0] addr_from_rom;
reg [7:0] addr_from_rom2;
reg areset_init_state_1;
reg areset_state;
reg C0_data_state;
reg C0_ena_state;
reg C1_data_state;
reg C1_ena_state;
reg C2_data_state;
reg C2_ena_state;
reg C3_data_state;
reg C3_ena_state;
reg C4_data_state;
reg C4_ena_state;
reg configupdate2_state;
reg configupdate3_state;
reg configupdate_state;
reg [2:0] counter_param_latch_reg;
reg [3:0] counter_type_latch_reg;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg idle_state;
reg [0:0] nominal_data0;
reg [0:0] nominal_data1;
reg [0:0] nominal_data2;
reg [0:0] nominal_data3;
reg [0:0] nominal_data4;
reg [0:0] nominal_data5;
reg [0:0] nominal_data6;
reg [0:0] nominal_data7;
reg [0:0] nominal_data8;
reg [0:0] nominal_data9;
reg [0:0] nominal_data10;
reg [0:0] nominal_data11;
reg [0:0] nominal_data12;
reg [0:0] nominal_data13;
reg [0:0] nominal_data14;
reg [0:0] nominal_data15;
reg [0:0] nominal_data16;
reg [0:0] nominal_data17;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_data_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_data_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_first_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_first_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_init_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_init_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_last_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_last_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_counter_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_init_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_post_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_seq_data_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_seq_ena_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_wait_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg reset_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg rom_data_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg rom_first_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg rom_init_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg rom_last_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg rom_second_last_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg rom_second_state;
reg [0:0] shift_reg0;
reg [0:0] shift_reg1;
reg [0:0] shift_reg2;
reg [0:0] shift_reg3;
reg [0:0] shift_reg4;
reg [0:0] shift_reg5;
reg [0:0] shift_reg6;
reg [0:0] shift_reg7;
reg [0:0] shift_reg8;
reg [0:0] shift_reg9;
reg [0:0] shift_reg10;
reg [0:0] shift_reg11;
reg [0:0] shift_reg12;
reg [0:0] shift_reg13;
reg [0:0] shift_reg14;
reg [0:0] shift_reg15;
reg [0:0] shift_reg16;
reg [0:0] shift_reg17;
wire [17:0] wire_shift_reg_ena;
reg tmp_nominal_data_out_state;
reg tmp_seq_ena_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg write_data_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg write_init_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg write_init_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg write_nominal_state;
wire [8:0] wire_add_sub5_result;
wire [7:0] wire_add_sub6_result;
wire wire_cmpr7_aeb;
wire [7:0] wire_cntr1_q;
wire [7:0] wire_cntr12_q;
wire [5:0] wire_cntr13_q;
wire [7:0] wire_cntr14_q;
wire [4:0] wire_cntr15_q;
wire [7:0] wire_cntr16_q;
wire [7:0] wire_cntr2_q;
wire [4:0] wire_cntr3_q;
wire [4:0] wire_decode11_eq;
wire addr_counter_enable;
wire [7:0] addr_counter_out;
wire addr_counter_sload;
wire [7:0] addr_counter_sload_value;
wire [7:0] addr_decoder_out;
wire [7:0] c0_wire;
wire [7:0] c1_wire;
wire [7:0] c2_wire;
wire [7:0] c3_wire;
wire [7:0] c4_wire;
wire [7:0] const_scan_chain_size;
wire [2:0] counter_param_latch;
wire [3:0] counter_type_latch;
wire [2:0] cuda_combout_wire;
wire dummy_scandataout;
wire [2:0] encode_out;
wire input_latch_enable;
wire power_up;
wire read_addr_counter_done;
wire read_addr_counter_enable;
wire [7:0] read_addr_counter_out;
wire read_addr_counter_sload;
wire [7:0] read_addr_counter_sload_value;
wire [7:0] read_addr_decoder_out;
wire read_nominal_out;
wire reconfig_addr_counter_enable;
wire [7:0] reconfig_addr_counter_out;
wire reconfig_addr_counter_sload;
wire [7:0] reconfig_addr_counter_sload_value;
wire reconfig_done;
wire reconfig_post_done;
wire reconfig_width_counter_done;
wire reconfig_width_counter_enable;
wire reconfig_width_counter_sload;
wire [5:0] reconfig_width_counter_sload_value;
wire rom_width_counter_done;
wire rom_width_counter_enable;
wire rom_width_counter_sload;
wire [7:0] rom_width_counter_sload_value;
wire rotate_addr_counter_enable;
wire [7:0] rotate_addr_counter_out;
wire rotate_addr_counter_sload;
wire [7:0] rotate_addr_counter_sload_value;
wire [4:0] rotate_decoder_wires;
wire rotate_width_counter_done;
wire rotate_width_counter_enable;
wire rotate_width_counter_sload;
wire [4:0] rotate_width_counter_sload_value;
wire [7:0] scan_cache_address;
wire scan_cache_in;
wire scan_cache_out;
wire scan_cache_write_enable;
wire sel_param_bypass_LF_unused;
wire sel_param_c;
wire sel_param_high_i_postscale;
wire sel_param_low_r;
wire sel_param_nominal_count;
wire sel_param_odd_CP_unused;
wire sel_type_c0;
wire sel_type_c1;
wire sel_type_c2;
wire sel_type_c3;
wire sel_type_c4;
wire sel_type_cplf;
wire sel_type_m;
wire sel_type_n;
wire sel_type_vco;
wire [7:0] seq_addr_wire;
wire [5:0] seq_sload_value;
wire shift_reg_clear;
wire shift_reg_load_enable;
wire shift_reg_load_nominal_enable;
wire shift_reg_serial_in;
wire shift_reg_serial_out;
wire shift_reg_shift_enable;
wire shift_reg_shift_nominal_enable;
wire [7:0] shift_reg_width_select;
wire w1565w;
wire w1592w;
wire w64w;
wire width_counter_done;
wire width_counter_enable;
wire width_counter_sload;
wire [4:0] width_counter_sload_value;
wire [4:0] width_decoder_out;
wire [7:0] width_decoder_select;
altsyncram altsyncram4
(
.address_a(scan_cache_address),
.clock0(clock),
.data_a({scan_cache_in}),
.eccstatus(),
.q_a(wire_altsyncram4_q_a),
.q_b(),
.wren_a(scan_cache_write_enable)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr0(1'b0),
.aclr1(1'b0),
.address_b({1{1'b1}}),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a({1{1'b1}}),
.byteena_b({1{1'b1}}),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_b({1{1'b1}}),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_b(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
altsyncram4.numwords_a = 144,
altsyncram4.operation_mode = "SINGLE_PORT",
altsyncram4.width_a = 1,
altsyncram4.width_byteena_a = 1,
altsyncram4.widthad_a = 8,
altsyncram4.intended_device_family = "Cyclone 10 LP",
altsyncram4.lpm_type = "altsyncram";
cyclone10lp_lcell_comb le_comb10
(
.combout(wire_le_comb10_combout),
.cout(),
.dataa(encode_out[0]),
.datab(encode_out[1]),
.datac(encode_out[2]),
.cin(1'b0),
.datad(1'b0)
);
defparam
le_comb10.dont_touch = "on",
le_comb10.lut_mask = 16'hF0F0,
le_comb10.sum_lutc_input = "datac",
le_comb10.lpm_type = "cyclone10lp_lcell_comb";
cyclone10lp_lcell_comb le_comb8
(
.combout(wire_le_comb8_combout),
.cout(),
.dataa(encode_out[0]),
.datab(encode_out[1]),
.datac(encode_out[2]),
.cin(1'b0),
.datad(1'b0)
);
defparam
le_comb8.dont_touch = "on",
le_comb8.lut_mask = 16'hAAAA,
le_comb8.sum_lutc_input = "datac",
le_comb8.lpm_type = "cyclone10lp_lcell_comb";
cyclone10lp_lcell_comb le_comb9
(
.combout(wire_le_comb9_combout),
.cout(),
.dataa(encode_out[0]),
.datab(encode_out[1]),
.datac(encode_out[2]),
.cin(1'b0),
.datad(1'b0)
);
defparam
le_comb9.dont_touch = "on",
le_comb9.lut_mask = 16'hCCCC,
le_comb9.sum_lutc_input = "datac",
le_comb9.lpm_type = "cyclone10lp_lcell_comb";
// synopsys translate_off
initial
addr_from_rom = 0;
// synopsys translate_on
always @ ( posedge clock)
addr_from_rom <= read_addr_counter_out;
// synopsys translate_off
initial
addr_from_rom2 = 0;
// synopsys translate_on
always @ ( posedge clock)
addr_from_rom2 <= addr_from_rom;
// synopsys translate_off
initial
areset_init_state_1 = 0;
// synopsys translate_on
always @ ( posedge clock)
areset_init_state_1 <= pll_scandone;
// synopsys translate_off
initial
areset_state = 0;
// synopsys translate_on
always @ ( posedge clock)
areset_state <= (areset_init_state_1 & (~ reset));
// synopsys translate_off
initial
C0_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C0_data_state <= (C0_ena_state | (C0_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C0_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C0_ena_state <= (C1_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C1_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C1_data_state <= (C1_ena_state | (C1_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C1_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C1_ena_state <= (C2_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C2_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C2_data_state <= (C2_ena_state | (C2_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C2_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C2_ena_state <= (C3_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C3_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C3_data_state <= (C3_ena_state | (C3_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C3_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C3_ena_state <= (C4_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C4_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C4_data_state <= (C4_ena_state | (C4_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C4_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C4_ena_state <= reconfig_init_state;
// synopsys translate_off
initial
configupdate2_state = 0;
// synopsys translate_on
always @ ( posedge clock)
configupdate2_state <= configupdate_state;
// synopsys translate_off
initial
configupdate3_state = 0;
// synopsys translate_on
always @ ( negedge clock)
configupdate3_state <= configupdate2_state;
// synopsys translate_off
initial
configupdate_state = 0;
// synopsys translate_on
always @ ( posedge clock)
configupdate_state <= reconfig_post_state;
// synopsys translate_off
initial
counter_param_latch_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) counter_param_latch_reg <= 3'b0;
else if (input_latch_enable == 1'b1) counter_param_latch_reg <= counter_param;
// synopsys translate_off
initial
counter_type_latch_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) counter_type_latch_reg <= 4'b0;
else if (input_latch_enable == 1'b1) counter_type_latch_reg <= counter_type;
// synopsys translate_off
initial
idle_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) idle_state <= 1'b0;
else idle_state <= (((((((((((((idle_state & (~ read_param)) & (~ write_param)) & (~ reconfig)) & (~ write_from_rom)) | read_last_state) | (write_data_state & width_counter_done)) | (write_nominal_state & width_counter_done)) | read_last_nominal_state) | (reconfig_wait_state & reconfig_done)) | ((rom_data_state & rom_width_counter_done) & (~ reset_rom_address))) | (rom_second_last_state & (~ reset_rom_address))) | (rom_last_state & (~ reset_rom_address))) | reset_state);
// synopsys translate_off
initial
nominal_data0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data0 <= 1'b0;
else nominal_data0 <= wire_add_sub6_result[0];
// synopsys translate_off
initial
nominal_data1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data1 <= 1'b0;
else nominal_data1 <= wire_add_sub6_result[1];
// synopsys translate_off
initial
nominal_data2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data2 <= 1'b0;
else nominal_data2 <= wire_add_sub6_result[2];
// synopsys translate_off
initial
nominal_data3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data3 <= 1'b0;
else nominal_data3 <= wire_add_sub6_result[3];
// synopsys translate_off
initial
nominal_data4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data4 <= 1'b0;
else nominal_data4 <= wire_add_sub6_result[4];
// synopsys translate_off
initial
nominal_data5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data5 <= 1'b0;
else nominal_data5 <= wire_add_sub6_result[5];
// synopsys translate_off
initial
nominal_data6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data6 <= 1'b0;
else nominal_data6 <= wire_add_sub6_result[6];
// synopsys translate_off
initial
nominal_data7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data7 <= 1'b0;
else nominal_data7 <= wire_add_sub6_result[7];
// synopsys translate_off
initial
nominal_data8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data8 <= 1'b0;
else nominal_data8 <= data_in[0];
// synopsys translate_off
initial
nominal_data9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data9 <= 1'b0;
else nominal_data9 <= data_in[1];
// synopsys translate_off
initial
nominal_data10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data10 <= 1'b0;
else nominal_data10 <= data_in[2];
// synopsys translate_off
initial
nominal_data11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data11 <= 1'b0;
else nominal_data11 <= data_in[3];
// synopsys translate_off
initial
nominal_data12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data12 <= 1'b0;
else nominal_data12 <= data_in[4];
// synopsys translate_off
initial
nominal_data13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data13 <= 1'b0;
else nominal_data13 <= data_in[5];
// synopsys translate_off
initial
nominal_data14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data14 <= 1'b0;
else nominal_data14 <= data_in[6];
// synopsys translate_off
initial
nominal_data15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data15 <= 1'b0;
else nominal_data15 <= data_in[7];
// synopsys translate_off
initial
nominal_data16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data16 <= 1'b0;
else nominal_data16 <= data_in[8];
// synopsys translate_off
initial
nominal_data17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data17 <= 1'b0;
else nominal_data17 <= wire_cmpr7_aeb;
// synopsys translate_off
initial
read_data_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_data_nominal_state <= 1'b0;
else read_data_nominal_state <= ((read_first_nominal_state & (~ width_counter_done)) | (read_data_nominal_state & (~ width_counter_done)));
// synopsys translate_off
initial
read_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_data_state <= 1'b0;
else read_data_state <= ((read_first_state & (~ width_counter_done)) | (read_data_state & (~ width_counter_done)));
// synopsys translate_off
initial
read_first_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_first_nominal_state <= 1'b0;
else read_first_nominal_state <= read_init_nominal_state;
// synopsys translate_off
initial
read_first_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_first_state <= 1'b0;
else read_first_state <= read_init_state;
// synopsys translate_off
initial
read_init_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_init_nominal_state <= 1'b0;
else read_init_nominal_state <= ((idle_state & read_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]));
// synopsys translate_off
initial
read_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_init_state <= 1'b0;
else read_init_state <= ((idle_state & read_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])));
// synopsys translate_off
initial
read_last_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_last_nominal_state <= 1'b0;
else read_last_nominal_state <= ((read_first_nominal_state & width_counter_done) | (read_data_nominal_state & width_counter_done));
// synopsys translate_off
initial
read_last_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_last_state <= 1'b0;
else read_last_state <= ((read_first_state & width_counter_done) | (read_data_state & width_counter_done));
// synopsys translate_off
initial
reconfig_counter_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_counter_state <= 1'b0;
else reconfig_counter_state <= ((((((((((reconfig_init_state | C0_data_state) | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state) | C0_ena_state) | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state);
// synopsys translate_off
initial
reconfig_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_init_state <= 1'b0;
else reconfig_init_state <= (idle_state & reconfig);
// synopsys translate_off
initial
reconfig_post_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_post_state <= 1'b0;
else reconfig_post_state <= ((reconfig_seq_data_state & reconfig_width_counter_done) | (reconfig_post_state & (~ reconfig_post_done)));
// synopsys translate_off
initial
reconfig_seq_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_seq_data_state <= 1'b0;
else reconfig_seq_data_state <= (reconfig_seq_ena_state | (reconfig_seq_data_state & (~ reconfig_width_counter_done)));
// synopsys translate_off
initial
reconfig_seq_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_seq_ena_state <= 1'b0;
else reconfig_seq_ena_state <= tmp_seq_ena_state;
// synopsys translate_off
initial
reconfig_wait_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_wait_state <= 1'b0;
else reconfig_wait_state <= ((reconfig_post_state & reconfig_post_done) | (reconfig_wait_state & (~ reconfig_done)));
// synopsys translate_off
initial
reset_state = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reset_state <= {1{1'b1}};
else reset_state <= power_up;
// synopsys translate_off
initial
rom_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) rom_data_state <= 1'b0;
else rom_data_state <= (rom_second_state | ((rom_data_state & (~ read_addr_counter_done)) & (~ reset_rom_address)));
// synopsys translate_off
initial
rom_first_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) rom_first_state <= 1'b0;
else rom_first_state <= rom_init_state;
// synopsys translate_off
initial
rom_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) rom_init_state <= 1'b0;
else rom_init_state <= (((((idle_state & write_from_rom) | (rom_first_state & reset_rom_address)) | (rom_second_state & reset_rom_address)) | (rom_data_state & reset_rom_address)) | (rom_second_last_state & reset_rom_address));
// synopsys translate_off
initial
rom_last_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) rom_last_state <= 1'b0;
else rom_last_state <= (rom_second_last_state & (~ reset_rom_address));
// synopsys translate_off
initial
rom_second_last_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) rom_second_last_state <= 1'b0;
else rom_second_last_state <= ((rom_data_state & read_addr_counter_done) & (~ reset_rom_address));
// synopsys translate_off
initial
rom_second_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) rom_second_state <= 1'b0;
else rom_second_state <= (rom_first_state & (~ reset_rom_address));
// synopsys translate_off
initial
shift_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg0 <= 1'b0;
else if (wire_shift_reg_ena[0:0] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg0 <= 1'b0;
else shift_reg0 <= ((((shift_reg_load_nominal_enable & nominal_data17[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg_serial_in)) | (shift_reg_shift_nominal_enable & shift_reg_serial_in));
// synopsys translate_off
initial
shift_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg1 <= 1'b0;
else if (wire_shift_reg_ena[1:1] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg1 <= 1'b0;
else shift_reg1 <= ((((shift_reg_load_nominal_enable & nominal_data16[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg0[0:0])) | (shift_reg_shift_nominal_enable & shift_reg0[0:0]));
// synopsys translate_off
initial
shift_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg2 <= 1'b0;
else if (wire_shift_reg_ena[2:2] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg2 <= 1'b0;
else shift_reg2 <= ((((shift_reg_load_nominal_enable & nominal_data15[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg1[0:0])) | (shift_reg_shift_nominal_enable & shift_reg1[0:0]));
// synopsys translate_off
initial
shift_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg3 <= 1'b0;
else if (wire_shift_reg_ena[3:3] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg3 <= 1'b0;
else shift_reg3 <= ((((shift_reg_load_nominal_enable & nominal_data14[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg2[0:0])) | (shift_reg_shift_nominal_enable & shift_reg2[0:0]));
// synopsys translate_off
initial
shift_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg4 <= 1'b0;
else if (wire_shift_reg_ena[4:4] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg4 <= 1'b0;
else shift_reg4 <= ((((shift_reg_load_nominal_enable & nominal_data13[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg3[0:0])) | (shift_reg_shift_nominal_enable & shift_reg3[0:0]));
// synopsys translate_off
initial
shift_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg5 <= 1'b0;
else if (wire_shift_reg_ena[5:5] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg5 <= 1'b0;
else shift_reg5 <= ((((shift_reg_load_nominal_enable & nominal_data12[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg4[0:0])) | (shift_reg_shift_nominal_enable & shift_reg4[0:0]));
// synopsys translate_off
initial
shift_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg6 <= 1'b0;
else if (wire_shift_reg_ena[6:6] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg6 <= 1'b0;
else shift_reg6 <= ((((shift_reg_load_nominal_enable & nominal_data11[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg5[0:0])) | (shift_reg_shift_nominal_enable & shift_reg5[0:0]));
// synopsys translate_off
initial
shift_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg7 <= 1'b0;
else if (wire_shift_reg_ena[7:7] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg7 <= 1'b0;
else shift_reg7 <= ((((shift_reg_load_nominal_enable & nominal_data10[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg6[0:0])) | (shift_reg_shift_nominal_enable & shift_reg6[0:0]));
// synopsys translate_off
initial
shift_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg8 <= 1'b0;
else if (wire_shift_reg_ena[8:8] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg8 <= 1'b0;
else shift_reg8 <= ((((shift_reg_load_nominal_enable & nominal_data9[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg7[0:0])) | (shift_reg_shift_nominal_enable & shift_reg7[0:0]));
// synopsys translate_off
initial
shift_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg9 <= 1'b0;
else if (wire_shift_reg_ena[9:9] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg9 <= 1'b0;
else shift_reg9 <= ((((shift_reg_load_nominal_enable & nominal_data8[0:0]) | (shift_reg_load_enable & data_in[8])) | (shift_reg_shift_enable & shift_reg8[0:0])) | (shift_reg_shift_nominal_enable & shift_reg8[0:0]));
// synopsys translate_off
initial
shift_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg10 <= 1'b0;
else if (wire_shift_reg_ena[10:10] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg10 <= 1'b0;
else shift_reg10 <= ((((shift_reg_load_nominal_enable & nominal_data7[0:0]) | (shift_reg_load_enable & data_in[7])) | (shift_reg_shift_enable & shift_reg9[0:0])) | (shift_reg_shift_nominal_enable & shift_reg9[0:0]));
// synopsys translate_off
initial
shift_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg11 <= 1'b0;
else if (wire_shift_reg_ena[11:11] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg11 <= 1'b0;
else shift_reg11 <= ((((shift_reg_load_nominal_enable & nominal_data6[0:0]) | (shift_reg_load_enable & data_in[6])) | (shift_reg_shift_enable & shift_reg10[0:0])) | (shift_reg_shift_nominal_enable & shift_reg10[0:0]));
// synopsys translate_off
initial
shift_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg12 <= 1'b0;
else if (wire_shift_reg_ena[12:12] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg12 <= 1'b0;
else shift_reg12 <= ((((shift_reg_load_nominal_enable & nominal_data5[0:0]) | (shift_reg_load_enable & data_in[5])) | (shift_reg_shift_enable & shift_reg11[0:0])) | (shift_reg_shift_nominal_enable & shift_reg11[0:0]));
// synopsys translate_off
initial
shift_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg13 <= 1'b0;
else if (wire_shift_reg_ena[13:13] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg13 <= 1'b0;
else shift_reg13 <= ((((shift_reg_load_nominal_enable & nominal_data4[0:0]) | (shift_reg_load_enable & data_in[4])) | (shift_reg_shift_enable & shift_reg12[0:0])) | (shift_reg_shift_nominal_enable & shift_reg12[0:0]));
// synopsys translate_off
initial
shift_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg14 <= 1'b0;
else if (wire_shift_reg_ena[14:14] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg14 <= 1'b0;
else shift_reg14 <= ((((shift_reg_load_nominal_enable & nominal_data3[0:0]) | (shift_reg_load_enable & data_in[3])) | (shift_reg_shift_enable & shift_reg13[0:0])) | (shift_reg_shift_nominal_enable & shift_reg13[0:0]));
// synopsys translate_off
initial
shift_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg15 <= 1'b0;
else if (wire_shift_reg_ena[15:15] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg15 <= 1'b0;
else shift_reg15 <= ((((shift_reg_load_nominal_enable & nominal_data2[0:0]) | (shift_reg_load_enable & data_in[2])) | (shift_reg_shift_enable & shift_reg14[0:0])) | (shift_reg_shift_nominal_enable & shift_reg14[0:0]));
// synopsys translate_off
initial
shift_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg16 <= 1'b0;
else if (wire_shift_reg_ena[16:16] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg16 <= 1'b0;
else shift_reg16 <= ((((shift_reg_load_nominal_enable & nominal_data1[0:0]) | (shift_reg_load_enable & data_in[1])) | (shift_reg_shift_enable & shift_reg15[0:0])) | (shift_reg_shift_nominal_enable & shift_reg15[0:0]));
// synopsys translate_off
initial
shift_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg17 <= 1'b0;
else if (wire_shift_reg_ena[17:17] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg17 <= 1'b0;
else shift_reg17 <= ((((shift_reg_load_nominal_enable & nominal_data0[0:0]) | (shift_reg_load_enable & data_in[0])) | (shift_reg_shift_enable & shift_reg16[0:0])) | (shift_reg_shift_nominal_enable & shift_reg16[0:0]));
assign
wire_shift_reg_ena = {18{((((shift_reg_load_enable | shift_reg_shift_enable) | shift_reg_load_nominal_enable) | shift_reg_shift_nominal_enable) | shift_reg_clear)}};
// synopsys translate_off
initial
tmp_nominal_data_out_state = 0;
// synopsys translate_on
always @ ( posedge clock)
tmp_nominal_data_out_state <= ((read_last_nominal_state & (~ idle_state)) | (tmp_nominal_data_out_state & idle_state));
// synopsys translate_off
initial
tmp_seq_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
tmp_seq_ena_state <= (reconfig_counter_state & (C0_data_state & rotate_width_counter_done));
// synopsys translate_off
initial
write_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_data_state <= 1'b0;
else write_data_state <= (write_init_state | (write_data_state & (~ width_counter_done)));
// synopsys translate_off
initial
write_init_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_init_nominal_state <= 1'b0;
else write_init_nominal_state <= ((idle_state & write_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]));
// synopsys translate_off
initial
write_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_init_state <= 1'b0;
else write_init_state <= ((idle_state & write_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])));
// synopsys translate_off
initial
write_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_nominal_state <= 1'b0;
else write_nominal_state <= (write_init_nominal_state | (write_nominal_state & (~ width_counter_done)));
lpm_add_sub add_sub5
(
.cin(1'b0),
.cout(),
.dataa({1'b0, shift_reg8[0:0], shift_reg7[0:0], shift_reg6[0:0], shift_reg5[0:0], shift_reg4[0:0], shift_reg3[0:0], shift_reg2[0:0], shift_reg1[0:0]}),
.datab({1'b0, shift_reg17[0:0], shift_reg16[0:0], shift_reg15[0:0], shift_reg14[0:0], shift_reg13[0:0], shift_reg12[0:0], shift_reg11[0:0], shift_reg10[0:0]}),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_width = 9,
add_sub5.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub6
(
.cin(data_in[0]),
.cout(),
.dataa({data_in[8:1]}),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0),
.datab({8{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_width = 8,
add_sub6.lpm_type = "lpm_add_sub";
lpm_compare cmpr7
(
.aeb(wire_cmpr7_aeb),
.agb(),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa({data_in[7:0]}),
.datab(8'b00000001)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr7.lpm_width = 8,
cmpr7.lpm_type = "lpm_compare";
lpm_counter cntr1
(
.clock(clock),
.cnt_en(addr_counter_enable),
.cout(),
.data(addr_counter_sload_value),
.eq(),
.q(wire_cntr1_q),
.sload(addr_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr1.lpm_direction = "DOWN",
cntr1.lpm_modulus = 144,
cntr1.lpm_port_updown = "PORT_UNUSED",
cntr1.lpm_width = 8,
cntr1.lpm_type = "lpm_counter";
lpm_counter cntr12
(
.clock(clock),
.cnt_en(reconfig_addr_counter_enable),
.cout(),
.data(reconfig_addr_counter_sload_value),
.eq(),
.q(wire_cntr12_q),
.sload(reconfig_addr_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr12.lpm_direction = "DOWN",
cntr12.lpm_modulus = 144,
cntr12.lpm_port_updown = "PORT_UNUSED",
cntr12.lpm_width = 8,
cntr12.lpm_type = "lpm_counter";
lpm_counter cntr13
(
.clock(clock),
.cnt_en(reconfig_width_counter_enable),
.cout(),
.data(reconfig_width_counter_sload_value),
.eq(),
.q(wire_cntr13_q),
.sload(reconfig_width_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr13.lpm_direction = "DOWN",
cntr13.lpm_port_updown = "PORT_UNUSED",
cntr13.lpm_width = 6,
cntr13.lpm_type = "lpm_counter";
lpm_counter cntr14
(
.clock(clock),
.cnt_en(rom_width_counter_enable),
.cout(),
.data(rom_width_counter_sload_value),
.eq(),
.q(wire_cntr14_q),
.sload(rom_width_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr14.lpm_direction = "DOWN",
cntr14.lpm_port_updown = "PORT_UNUSED",
cntr14.lpm_width = 8,
cntr14.lpm_type = "lpm_counter";
lpm_counter cntr15
(
.clock(clock),
.cnt_en(rotate_width_counter_enable),
.cout(),
.data(rotate_width_counter_sload_value),
.eq(),
.q(wire_cntr15_q),
.sload(rotate_width_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr15.lpm_direction = "DOWN",
cntr15.lpm_port_updown = "PORT_UNUSED",
cntr15.lpm_width = 5,
cntr15.lpm_type = "lpm_counter";
lpm_counter cntr16
(
.clock(clock),
.cnt_en(rotate_addr_counter_enable),
.cout(),
.data(rotate_addr_counter_sload_value),
.eq(),
.q(wire_cntr16_q),
.sload(rotate_addr_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr16.lpm_direction = "DOWN",
cntr16.lpm_modulus = 144,
cntr16.lpm_port_updown = "PORT_UNUSED",
cntr16.lpm_width = 8,
cntr16.lpm_type = "lpm_counter";
lpm_counter cntr2
(
.clock(clock),
.cnt_en(read_addr_counter_enable),
.cout(),
.data(read_addr_counter_sload_value),
.eq(),
.q(wire_cntr2_q),
.sload(read_addr_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr2.lpm_direction = "UP",
cntr2.lpm_port_updown = "PORT_UNUSED",
cntr2.lpm_width = 8,
cntr2.lpm_type = "lpm_counter";
lpm_counter cntr3
(
.clock(clock),
.cnt_en(width_counter_enable),
.cout(),
.data(width_counter_sload_value),
.eq(),
.q(wire_cntr3_q),
.sload(width_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr3.lpm_direction = "DOWN",
cntr3.lpm_port_updown = "PORT_UNUSED",
cntr3.lpm_width = 5,
cntr3.lpm_type = "lpm_counter";
lpm_decode decode11
(
.data(cuda_combout_wire),
.eq(wire_decode11_eq)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0),
.enable(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
decode11.lpm_decodes = 5,
decode11.lpm_width = 3,
decode11.lpm_type = "lpm_decode";
assign
addr_counter_enable = (write_data_state | write_nominal_state),
addr_counter_out = wire_cntr1_q,
addr_counter_sload = (write_init_state | write_init_nominal_state),
addr_counter_sload_value = (addr_decoder_out & {8{(write_init_state | write_init_nominal_state)}}),
addr_decoder_out = ((((((((((((((((((((((((((((((((((({{7{1'b0}}, (sel_type_cplf & sel_param_bypass_LF_unused)} | {{6{1'b0}}, {2{(sel_type_cplf & sel_param_c)}}}) | {{4{1'b0}}, (sel_type_cplf & sel_param_low_r), {3{1'b0}}}) | {{4{1'b0}}, (sel_type_vco & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_vco & sel_param_high_i_postscale)}) | {{4{1'b0}}, {3{(sel_type_cplf & sel_param_odd_CP_unused)}}, 1'b0}) | {{3{1'b0}}, (sel_type_cplf & sel_param_high_i_postscale), {3{1'b0}}, (sel_type_cplf & sel_param_high_i_postscale)}) | {{3{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), 1'b0}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_high_i_postscale)}}, 1'b0, (sel_type_n & sel_param_high_i_postscale), 1'b0}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_odd_CP_unused)}}, 1'b0, {2{(sel_type_n & sel_param_odd_CP_unused)}}}) | {{2{1'b0}}, (sel_type_n & sel_param_low_r), {3{1'b0}}, {2{(sel_type_n & sel_param_low_r)}}}) | {{2{1'b0}}, (sel_type_n & sel_param_nominal_count), {3{1'b0}}, {2{(sel_type_n & sel_param_nominal_count)}}}) | {{2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), 1'b0, {2{(sel_type_m & sel_param_high_i_postscale)}}, {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_m & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_m & sel_param_odd_CP_unused)}) | {{2{1'b0}}, {2{(sel_type_m & sel_param_low_r)}}, 1'b0, (sel_type_m & sel_param_low_r), 1'b0, (sel_type_m & sel_param_low_r)}) | {{2{1'b0}}, {2{(sel_type_m & sel_param_nominal_count)}}, 1'b0, (sel_type_m & sel_param_nominal_count), 1'b0, (sel_type_m & sel_param_nominal_count)}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0}) | {{2{1'b0}}, {5{(sel_type_c0 & sel_param_high_i_postscale)}}, 1'b0}) | {{2{1'b0}}, {6{(sel_type_c0 & sel_param_odd_CP_unused)}}}) | {1'b0, (sel_type_c0 & sel_param_low_r
), {3{1'b0}}, {3{(sel_type_c0 & sel_param_low_r)}}}) | {1'b0, (sel_type_c1 & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_c1 & sel_param_bypass_LF_unused), {3{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_high_i_postscale), 1'b0, (sel_type_c1 & sel_param_high_i_postscale), {4{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_odd_CP_unused), 1'b0, (sel_type_c1 & sel_param_odd_CP_unused), {3{1'b0}}, (sel_type_c1 & sel_param_odd_CP_unused)}) | {1'b0, (sel_type_c1 & sel_param_low_r), 1'b0, {2{(sel_type_c1 & sel_param_low_r)}}, {2{1'b0}}, (sel_type_c1 & sel_param_low_r)}) | {1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0, {2{(sel_type_c2 & sel_param_bypass_LF_unused)}}, 1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0}) | {1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}, {3{1'b0}}, (sel_type_c2 & sel_param_high_i_postscale), 1'b0}) | {1'b0, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}, {3{1'b0}}, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_low_r)}}, 1'b0, (sel_type_c2 & sel_param_low_r), 1'b0, {2{(sel_type_c2 & sel_param_low_r)}}}) | {1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, {2{1'b0}}}) | {1'b0, {3{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, (sel_type_c3 & sel_param_high_i_postscale), {2{1'b0}}}) | {1'b0, {3{(sel_type_c3 & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_c3 & sel_param_odd_CP_unused), 1'b0, (sel_type_c3 & sel_param_odd_CP_unused)}) | {1'b0, {5{(sel_type_c3 & sel_param_low_r)}}, 1'b0, (sel_type_c3 & sel_param_low_r)}) | {1'b0, {6{(sel_type_c4 & sel_param_bypass_LF_unused)}}, 1'b0}) | {(sel_type_c4 & sel_param_high_i_postscale), {4{1'b0}}, {2{(sel_type_c4 & sel_param_high_i_postscale)}}, 1'b0}) | {(sel_type_c4 & sel_param_odd_CP_unused), {4{1'b0}}, {3{(sel_type_c4 & sel_param_odd_CP_unused)}}}) | {(sel_type_c4 & sel_param_low_r), {3{1'b0}}, {4{(sel_type_c4 & sel_param_low_r)}}}),
busy = ((~ idle_state) | areset_state),
c0_wire = 8'b01000111,
c1_wire = 8'b01011001,
c2_wire = 8'b01101011,
c3_wire = 8'b01111101,
c4_wire = 8'b10001111,
const_scan_chain_size = 8'b10001111,
counter_param_latch = counter_param_latch_reg,
counter_type_latch = counter_type_latch_reg,
cuda_combout_wire = {wire_le_comb10_combout, wire_le_comb9_combout, wire_le_comb8_combout},
data_out = {((shift_reg8[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[8] & read_nominal_out)), ((shift_reg7[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[7] & read_nominal_out)), ((shift_reg6[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[6] & read_nominal_out)), ((shift_reg5[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[5] & read_nominal_out)), ((shift_reg4[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[4] & read_nominal_out)), ((shift_reg3[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[3] & read_nominal_out)), ((shift_reg2[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[2] & read_nominal_out)), ((shift_reg1[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[1] & read_nominal_out)), ((shift_reg0[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[0] & read_nominal_out))},
dummy_scandataout = pll_scandataout,
encode_out = {C4_ena_state, (C2_ena_state | C3_ena_state), (C1_ena_state | C3_ena_state)},
input_latch_enable = (idle_state & (write_param | read_param)),
pll_areset = (pll_areset_in | (areset_state & reconfig_wait_state)),
pll_configupdate = (configupdate_state & (~ configupdate3_state)),
pll_scanclk = clock,
pll_scanclkena = ((rotate_width_counter_enable & (~ rotate_width_counter_done)) | reconfig_seq_data_state),
pll_scandata = (scan_cache_out & ((rotate_width_counter_enable | reconfig_seq_data_state) | reconfig_post_state)),
power_up = ((((((((((((((((((((((((((~ reset_state) & (~ idle_state)) & (~ read_init_state)) & (~ read_first_state)) & (~ read_data_state)) & (~ read_last_state)) & (~ read_init_nominal_state)) & (~ read_first_nominal_state)) & (~ read_data_nominal_state)) & (~ read_last_nominal_state)) & (~ write_init_state)) & (~ write_data_state)) & (~ write_init_nominal_state)) & (~ write_nominal_state)) & (~ reconfig_init_state)) & (~ reconfig_counter_state)) & (~ reconfig_seq_ena_state)) & (~ reconfig_seq_data_state)) & (~ reconfig_post_state)) & (~ reconfig_wait_state)) & (~ rom_init_state)) & (~ rom_first_state)) & (~ rom_second_state)) & (~ rom_data_state)) & (~ rom_second_last_state)) & (~ rom_last_state)),
read_addr_counter_done = (((((((wire_cntr2_q[0] & wire_cntr2_q[1]) & wire_cntr2_q[2]) & wire_cntr2_q[3]) & (~ wire_cntr2_q[4])) & (~ wire_cntr2_q[5])) & (~ wire_cntr2_q[6])) & wire_cntr2_q[7]),
read_addr_counter_enable = ((((read_first_state | read_data_state) | read_first_nominal_state) | read_data_nominal_state) | ((rom_data_state | rom_first_state) | rom_second_state)),
read_addr_counter_out = wire_cntr2_q,
read_addr_counter_sload = ((read_init_state | read_init_nominal_state) | rom_init_state),
read_addr_counter_sload_value = (read_addr_decoder_out & {8{(read_init_state | read_init_nominal_state)}}),
read_addr_decoder_out = ((((((((((((((((((((((((((((((((((({8{1'b0}} | {{6{1'b0}}, (sel_type_cplf & sel_param_c), 1'b0}) | {{5{1'b0}}, (sel_type_cplf & sel_param_low_r), {2{1'b0}}}) | {{4{1'b0}}, (sel_type_vco & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_vco & sel_param_high_i_postscale)}) | {{4{1'b0}}, (sel_type_cplf & sel_param_odd_CP_unused), 1'b0, (sel_type_cplf & sel_param_odd_CP_unused), 1'b0}) | {{4{1'b0}}, {4{(sel_type_cplf & sel_param_high_i_postscale)}}}) | {{3{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), 1'b0}) | {{3{1'b0}}, (sel_type_n & sel_param_high_i_postscale), {2{1'b0}}, {2{(sel_type_n & sel_param_high_i_postscale)}}}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_odd_CP_unused)}}, 1'b0, {2{(sel_type_n & sel_param_odd_CP_unused)}}}) | {{3{1'b0}}, {3{(sel_type_n & sel_param_low_r)}}, {2{1'b0}}}) | {{3{1'b0}}, (sel_type_n & sel_param_nominal_count), {2{1'b0}}, (sel_type_n & sel_param_nominal_count), 1'b0}) | {{2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), 1'b0, (sel_type_m & sel_param_high_i_postscale)}) | {{2{1'b0}}, (sel_type_m & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_m & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_m & sel_param_odd_CP_unused)}) | {{2{1'b0}}, (sel_type_m & sel_param_low_r), 1'b0, {3{(sel_type_m & sel_param_low_r)}}, 1'b0}) | {{2{1'b0}}, (sel_type_m & sel_param_nominal_count), {2{1'b0}}, (sel_type_m & sel_param_nominal_count), {2{1'b0}}}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_high_i_postscale)}}, 1'b0, {3{(sel_type_c0 & sel_param_high_i_postscale)}}}) | {{2{1'b0}}, {6{(sel_type_c0 & sel_param_odd_CP_unused)}}}) | {1'b0, (sel_type_c0 & sel_param_low_r), {6{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_bypass_LF_unused
), {2{1'b0}}, (sel_type_c1 & sel_param_bypass_LF_unused), {3{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_c1 & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_c1 & sel_param_high_i_postscale)}) | {1'b0, (sel_type_c1 & sel_param_odd_CP_unused), 1'b0, (sel_type_c1 & sel_param_odd_CP_unused), {3{1'b0}}, (sel_type_c1 & sel_param_odd_CP_unused)}) | {1'b0, (sel_type_c1 & sel_param_low_r), 1'b0, (sel_type_c1 & sel_param_low_r), {2{1'b0}}, (sel_type_c1 & sel_param_low_r), 1'b0}) | {1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0, {2{(sel_type_c2 & sel_param_bypass_LF_unused)}}, 1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0}) | {1'b0, (sel_type_c2 & sel_param_high_i_postscale), 1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}, 1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}, {3{1'b0}}, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_low_r)}}, {2{1'b0}}, (sel_type_c2 & sel_param_low_r), {2{1'b0}}}) | {1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, {2{1'b0}}}) | {1'b0, {2{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, {2{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, (sel_type_c3 & sel_param_high_i_postscale)}) | {1'b0, {3{(sel_type_c3 & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_c3 & sel_param_odd_CP_unused), 1'b0, (sel_type_c3 & sel_param_odd_CP_unused)}) | {1'b0, {3{(sel_type_c3 & sel_param_low_r)}}, 1'b0, {2{(sel_type_c3 & sel_param_low_r)}}, 1'b0}) | {1'b0, {6{(sel_type_c4 & sel_param_bypass_LF_unused)}}, 1'b0}) | {1'b0, {7{(sel_type_c4 & sel_param_high_i_postscale)}}}) | {(sel_type_c4 & sel_param_odd_CP_unused), {4{1'b0}}, {3{(sel_type_c4 & sel_param_odd_CP_unused)}}}) | {(sel_type_c4 & sel_param_low_r), {3{1'b0}}, (sel_type_c4 & sel_param_low_r), {3{1'b0}}}),
read_nominal_out = tmp_nominal_data_out_state,
reconfig_addr_counter_enable = reconfig_seq_data_state,
reconfig_addr_counter_out = wire_cntr12_q,
reconfig_addr_counter_sload = reconfig_seq_ena_state,
reconfig_addr_counter_sload_value = ({8{reconfig_seq_ena_state}} & seq_addr_wire),
reconfig_done = ((~ pll_scandone) & (dummy_scandataout | (~ dummy_scandataout))),
reconfig_post_done = pll_scandone,
reconfig_width_counter_done = ((((((~ wire_cntr13_q[0]) & (~ wire_cntr13_q[1])) & (~ wire_cntr13_q[2])) & (~ wire_cntr13_q[3])) & (~ wire_cntr13_q[4])) & (~ wire_cntr13_q[5])),
reconfig_width_counter_enable = reconfig_seq_data_state,
reconfig_width_counter_sload = reconfig_seq_ena_state,
reconfig_width_counter_sload_value = ({6{reconfig_seq_ena_state}} & seq_sload_value),
rom_address_out = (read_addr_counter_out & {8{((rom_first_state | rom_second_state) | rom_data_state)}}),
rom_width_counter_done = ((((((((~ wire_cntr14_q[0]) & (~ wire_cntr14_q[1])) & (~ wire_cntr14_q[2])) & (~ wire_cntr14_q[3])) & (~ wire_cntr14_q[4])) & (~ wire_cntr14_q[5])) & (~ wire_cntr14_q[6])) & (~ wire_cntr14_q[7])),
rom_width_counter_enable = ((rom_data_state | rom_last_state) | rom_second_last_state),
rom_width_counter_sload = rom_init_state,
rom_width_counter_sload_value = const_scan_chain_size,
rotate_addr_counter_enable = ((((C0_data_state | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state),
rotate_addr_counter_out = wire_cntr16_q,
rotate_addr_counter_sload = ((((C0_ena_state | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state),
rotate_addr_counter_sload_value = (((((c0_wire & {8{rotate_decoder_wires[0]}}) | (c1_wire & {8{rotate_decoder_wires[1]}})) | (c2_wire & {8{rotate_decoder_wires[2]}})) | (c3_wire & {8{rotate_decoder_wires[3]}})) | (c4_wire & {8{rotate_decoder_wires[4]}})),
rotate_decoder_wires = wire_decode11_eq,
rotate_width_counter_done = (((((~ wire_cntr15_q[0]) & (~ wire_cntr15_q[1])) & (~ wire_cntr15_q[2])) & (~ wire_cntr15_q[3])) & (~ wire_cntr15_q[4])),
rotate_width_counter_enable = ((((C0_data_state | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state),
rotate_width_counter_sload = ((((C0_ena_state | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state),
rotate_width_counter_sload_value = 5'b10010,
scan_cache_address = (((((addr_counter_out & {8{addr_counter_enable}}) | (rotate_addr_counter_out & {8{rotate_addr_counter_enable}})) | (reconfig_addr_counter_out & {8{reconfig_addr_counter_enable}})) | ((read_addr_counter_out & {8{read_addr_counter_enable}}) & {8{(~ (rom_data_state | rom_first_state))}})) | ({8{(rom_width_counter_enable & ((rom_data_state | rom_second_last_state) | rom_last_state))}} & addr_from_rom2)),
scan_cache_in = ((shift_reg_serial_out & (~ (((rom_first_state | rom_data_state) | rom_second_last_state) | rom_last_state))) | (rom_data_in & (((rom_first_state | rom_data_state) | rom_second_last_state) | rom_last_state))),
scan_cache_out = wire_altsyncram4_q_a[0],
scan_cache_write_enable = ((((write_data_state | write_nominal_state) | rom_data_state) | rom_second_last_state) | rom_last_state),
sel_param_bypass_LF_unused = (((~ counter_param_latch[0]) & (~ counter_param_latch[1])) & counter_param_latch[2]),
sel_param_c = (((~ counter_param_latch[0]) & counter_param_latch[1]) & (~ counter_param_latch[2])),
sel_param_high_i_postscale = (((~ counter_param_latch[0]) & (~ counter_param_latch[1])) & (~ counter_param_latch[2])),
sel_param_low_r = ((counter_param_latch[0] & (~ counter_param_latch[1])) & (~ counter_param_latch[2])),
sel_param_nominal_count = ((counter_param_latch[0] & counter_param_latch[1]) & counter_param_latch[2]),
sel_param_odd_CP_unused = ((counter_param_latch[0] & (~ counter_param_latch[1])) & counter_param_latch[2]),
sel_type_c0 = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & counter_type_latch[2]) & (~ counter_type_latch[3])),
sel_type_c1 = (((counter_type_latch[0] & (~ counter_type_latch[1])) & counter_type_latch[2]) & (~ counter_type_latch[3])),
sel_type_c2 = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & counter_type_latch[2]) & (~ counter_type_latch[3])),
sel_type_c3 = (((counter_type_latch[0] & counter_type_latch[1]) & counter_type_latch[2]) & (~ counter_type_latch[3])),
sel_type_c4 = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & counter_type_latch[3]),
sel_type_cplf = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
sel_type_m = (((counter_type_latch[0] & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
sel_type_n = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
sel_type_vco = (((counter_type_latch[0] & counter_type_latch[1]) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
seq_addr_wire = 8'b00110101,
seq_sload_value = 6'b110110,
shift_reg_clear = (read_init_state | read_init_nominal_state),
shift_reg_load_enable = ((idle_state & write_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]))),
shift_reg_load_nominal_enable = ((idle_state & write_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])),
shift_reg_serial_in = scan_cache_out,
shift_reg_serial_out = ((((((((shift_reg17[0:0] & shift_reg_width_select[0]) | (shift_reg17[0:0] & shift_reg_width_select[1])) | (shift_reg17[0:0] & shift_reg_width_select[2])) | (shift_reg17[0:0] & shift_reg_width_select[3])) | (shift_reg17[0:0] & shift_reg_width_select[4])) | (shift_reg17[0:0] & shift_reg_width_select[5])) | (shift_reg17[0:0] & shift_reg_width_select[6])) | (shift_reg17[0:0] & shift_reg_width_select[7])),
shift_reg_shift_enable = ((read_data_state | read_last_state) | write_data_state),
shift_reg_shift_nominal_enable = ((read_data_nominal_state | read_last_nominal_state) | write_nominal_state),
shift_reg_width_select = width_decoder_select,
w1565w = 1'b0,
w1592w = 1'b0,
w64w = 1'b0,
width_counter_done = (((((~ wire_cntr3_q[0]) & (~ wire_cntr3_q[1])) & (~ wire_cntr3_q[2])) & (~ wire_cntr3_q[3])) & (~ wire_cntr3_q[4])),
width_counter_enable = ((((read_first_state | read_data_state) | write_data_state) | read_data_nominal_state) | write_nominal_state),
width_counter_sload = (((read_init_state | write_init_state) | read_init_nominal_state) | write_init_nominal_state),
width_counter_sload_value = width_decoder_out,
width_decoder_out = ((((({5{1'b0}} | {width_decoder_select[2], {3{1'b0}}, width_decoder_select[2]}) | {{4{1'b0}}, width_decoder_select[3]}) | {{2{1'b0}}, {3{width_decoder_select[5]}}}) | {{3{1'b0}}, width_decoder_select[6], 1'b0}) | {{2{1'b0}}, width_decoder_select[7], {2{1'b0}}}),
width_decoder_select = {((sel_type_cplf & sel_param_low_r) | (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) | (sel_type_n & sel_param_low_r)) | (sel_type_m & sel_param_high_i_postscale)) | (sel_type_m & sel_param_low_r)) | (sel_type_c0 & sel_param_high_i_postscale)) | (sel_type_c0 & sel_param_low_r)) | (sel_type_c1 & sel_param_high_i_postscale)) | (sel_type_c1 & sel_param_low_r)) | (sel_type_c2 & sel_param_high_i_postscale)) | (sel_type_c2 & sel_param_low_r)) | (sel_type_c3 & sel_param_high_i_postscale)) | (sel_type_c3 & sel_param_low_r)) | (sel_type_c4 & sel_param_high_i_postscale)) | (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) | (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) | (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) | (sel_type_n & sel_param_bypass_LF_unused)) | (sel_type_n & sel_param_odd_CP_unused)) | (sel_type_m & sel_param_bypass_LF_unused)) | (sel_type_m & sel_param_odd_CP_unused)) | (sel_type_c0 & sel_param_bypass_LF_unused)) | (sel_type_c0 & sel_param_odd_CP_unused)) | (sel_type_c1 & sel_param_bypass_LF_unused)) | (sel_type_c1 & sel_param_odd_CP_unused)) | (sel_type_c2 & sel_param_bypass_LF_unused)) | (sel_type_c2 & sel_param_odd_CP_unused)) | (sel_type_c3 & sel_param_bypass_LF_unused)) | (sel_type_c3 & sel_param_odd_CP_unused)) | (sel_type_c4 & sel_param_bypass_LF_unused)) | (sel_type_c4 & sel_param_odd_CP_unused))},
write_rom_ena = ((rom_first_state | rom_second_state) | (rom_data_state & (~ rom_width_counter_done)));
endmodule //pll_hdmi_reconf_pllrcfg_hk11
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_hdmi_reconf (
clock,
counter_param,
counter_type,
data_in,
pll_areset_in,
pll_scandataout,
pll_scandone,
read_param,
reconfig,
reset,
reset_rom_address,
rom_data_in,
write_from_rom,
write_param,
busy,
data_out,
pll_areset,
pll_configupdate,
pll_scanclk,
pll_scanclkena,
pll_scandata,
rom_address_out,
write_rom_ena)/* synthesis synthesis_clearbox = 2 */;
input clock;
input [2:0] counter_param;
input [3:0] counter_type;
input [8:0] data_in;
input pll_areset_in;
input pll_scandataout;
input pll_scandone;
input read_param;
input reconfig;
input reset;
input reset_rom_address;
input rom_data_in;
input write_from_rom;
input write_param;
output busy;
output [8:0] data_out;
output pll_areset;
output pll_configupdate;
output pll_scanclk;
output pll_scanclkena;
output pll_scandata;
output [7:0] rom_address_out;
output write_rom_ena;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 pll_areset_in;
tri0 reset_rom_address;
tri0 rom_data_in;
tri0 write_from_rom;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [8:0] sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire sub_wire6;
wire [7:0] sub_wire7;
wire sub_wire8;
wire busy = sub_wire0;
wire [8:0] data_out = sub_wire1[8:0];
wire pll_areset = sub_wire2;
wire pll_configupdate = sub_wire3;
wire pll_scanclk = sub_wire4;
wire pll_scanclkena = sub_wire5;
wire pll_scandata = sub_wire6;
wire [7:0] rom_address_out = sub_wire7[7:0];
wire write_rom_ena = sub_wire8;
pll_hdmi_reconf_pllrcfg_hk11 pll_hdmi_reconf_pllrcfg_hk11_component (
.clock (clock),
.counter_param (counter_param),
.counter_type (counter_type),
.data_in (data_in),
.pll_areset_in (pll_areset_in),
.pll_scandataout (pll_scandataout),
.pll_scandone (pll_scandone),
.read_param (read_param),
.reconfig (reconfig),
.reset (reset),
.reset_rom_address (reset_rom_address),
.rom_data_in (rom_data_in),
.write_from_rom (write_from_rom),
.write_param (write_param),
.busy (sub_wire0),
.data_out (sub_wire1),
.pll_areset (sub_wire2),
.pll_configupdate (sub_wire3),
.pll_scanclk (sub_wire4),
.pll_scanclkena (sub_wire5),
.pll_scandata (sub_wire6),
.rom_address_out (sub_wire7),
.write_rom_ena (sub_wire8))/* synthesis synthesis_clearbox=2
clearbox_macroname = altpll_reconfig
clearbox_defparam = "init_from_external_rom_checkbox_checked=YES;intended_device_family=Cyclone 10 LP;" */;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_NAME STRING ""
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_INIT_FILE STRING "0"
// Retrieval info: CONSTANT: INIT_FROM_EXTERNAL_ROM_CHECKBOX_CHECKED STRING "YES"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]"
// Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]"
// Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]"
// Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]"
// Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset"
// Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in"
// Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate"
// Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk"
// Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena"
// Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata"
// Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout"
// Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone"
// Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
// Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
// Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
// Retrieval info: USED_PORT: reset_rom_address 0 0 0 0 INPUT GND "reset_rom_address"
// Retrieval info: USED_PORT: rom_address_out 0 0 8 0 OUTPUT NODEFVAL "rom_address_out[7..0]"
// Retrieval info: USED_PORT: rom_data_in 0 0 0 0 INPUT GND "rom_data_in"
// Retrieval info: USED_PORT: write_from_rom 0 0 0 0 INPUT GND "write_from_rom"
// Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
// Retrieval info: USED_PORT: write_rom_ena 0 0 0 0 OUTPUT NODEFVAL "write_rom_ena"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0
// Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0
// Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0
// Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0
// Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0
// Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0
// Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
// Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
// Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
// Retrieval info: CONNECT: @reset_rom_address 0 0 0 0 reset_rom_address 0 0 0 0
// Retrieval info: CONNECT: @rom_data_in 0 0 0 0 rom_data_in 0 0 0 0
// Retrieval info: CONNECT: @write_from_rom 0 0 0 0 write_from_rom 0 0 0 0
// Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0
// Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0
// Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0
// Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0
// Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0
// Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0
// Retrieval info: CONNECT: rom_address_out 0 0 8 0 @rom_address_out 0 0 8 0
// Retrieval info: CONNECT: write_rom_ena 0 0 0 0 @write_rom_ena 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_hdmi_reconf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_hdmi_reconf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_hdmi_reconf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_hdmi_reconf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_hdmi_reconf_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_hdmi_reconf_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: cyclone10lp
// Retrieval info: LIB_FILE: lpm
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLCLKP_FUNCTIONAL_PP_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dlclkp (
VPWR,
VGND,
GCLK,
GATE,
CLK
);
// Module ports
input VPWR;
input VGND;
output GCLK;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
// Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_hs__u_dl_p_pg u_dl_p_pg0 (m0 , GATE, clkn, VPWR, VGND);
and and0 (GCLK , m0, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLCLKP_FUNCTIONAL_PP_V
|
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