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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O41A_BEHAVIORAL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o41a (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_BEHAVIORAL_V
|
// wasca.v
// Generated using ACDS version 18.1 646
`timescale 1 ps / 1 ps
module wasca (
input wire [24:0] abus_avalon_sdram_bridge_0_abus_address, // abus_avalon_sdram_bridge_0_abus.address
input wire abus_avalon_sdram_bridge_0_abus_read, // .read
inout wire [15:0] abus_avalon_sdram_bridge_0_abus_data, // .data
input wire [2:0] abus_avalon_sdram_bridge_0_abus_chipselect, // .chipselect
output wire abus_avalon_sdram_bridge_0_abus_direction, // .direction
output wire abus_avalon_sdram_bridge_0_abus_interrupt_disable_out, // .interrupt_disable_out
output wire abus_avalon_sdram_bridge_0_abus_interrupt, // .interrupt
input wire [1:0] abus_avalon_sdram_bridge_0_abus_writebyteenable_n, // .writebyteenable_n
input wire abus_avalon_sdram_bridge_0_abus_reset, // .reset
output wire [12:0] abus_avalon_sdram_bridge_0_sdram_addr, // abus_avalon_sdram_bridge_0_sdram.addr
output wire [1:0] abus_avalon_sdram_bridge_0_sdram_ba, // .ba
output wire abus_avalon_sdram_bridge_0_sdram_cas_n, // .cas_n
output wire abus_avalon_sdram_bridge_0_sdram_cke, // .cke
output wire abus_avalon_sdram_bridge_0_sdram_cs_n, // .cs_n
inout wire [15:0] abus_avalon_sdram_bridge_0_sdram_dq, // .dq
output wire [1:0] abus_avalon_sdram_bridge_0_sdram_dqm, // .dqm
output wire abus_avalon_sdram_bridge_0_sdram_ras_n, // .ras_n
output wire abus_avalon_sdram_bridge_0_sdram_we_n, // .we_n
output wire abus_avalon_sdram_bridge_0_sdram_clk, // .clk
output wire buffered_spi_mosi, // buffered_spi.mosi
output wire buffered_spi_clk, // .clk
input wire buffered_spi_miso, // .miso
output wire buffered_spi_cs, // .cs
input wire buffered_spi_sync_miso, // .sync_miso
output wire buffered_spi_sync_mosi, // .sync_mosi
input wire clk_clk, // clk.clk
output wire clock_116_mhz_clk, // clock_116_mhz.clk
output wire heartbeat_heartbeat_out, // heartbeat.heartbeat_out
input wire reset_reset_n, // reset.reset_n
input wire reset_controller_0_reset_in1_reset, // reset_controller_0_reset_in1.reset
input wire uart_0_external_connection_rxd, // uart_0_external_connection.rxd
output wire uart_0_external_connection_txd // .txd
);
wire nios2_gen2_0_debug_reset_request_reset; // nios2_gen2_0:debug_reset_request -> [buffered_spi_0:reset, heartbeat_0:reset, mm_interconnect_0:buffered_spi_0_reset_reset_bridge_in_reset_reset, performance_counter_0:reset_n, reset_controller_0:reset_in0]
wire [31:0] nios2_gen2_0_data_master_readdata; // mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
wire nios2_gen2_0_data_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
wire nios2_gen2_0_data_master_debugaccess; // nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
wire [26:0] nios2_gen2_0_data_master_address; // nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
wire [3:0] nios2_gen2_0_data_master_byteenable; // nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
wire nios2_gen2_0_data_master_read; // nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
wire nios2_gen2_0_data_master_write; // nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
wire [31:0] nios2_gen2_0_data_master_writedata; // nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
wire [31:0] nios2_gen2_0_instruction_master_readdata; // mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
wire nios2_gen2_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
wire [19:0] nios2_gen2_0_instruction_master_address; // nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
wire nios2_gen2_0_instruction_master_read; // nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
wire [15:0] mm_interconnect_0_buffered_spi_0_avalon_readdata; // buffered_spi_0:avalon_readdata -> mm_interconnect_0:buffered_spi_0_avalon_readdata
wire mm_interconnect_0_buffered_spi_0_avalon_waitrequest; // buffered_spi_0:avalon_waitrequest -> mm_interconnect_0:buffered_spi_0_avalon_waitrequest
wire [13:0] mm_interconnect_0_buffered_spi_0_avalon_address; // mm_interconnect_0:buffered_spi_0_avalon_address -> buffered_spi_0:avalon_address
wire mm_interconnect_0_buffered_spi_0_avalon_read; // mm_interconnect_0:buffered_spi_0_avalon_read -> buffered_spi_0:avalon_read
wire mm_interconnect_0_buffered_spi_0_avalon_readdatavalid; // buffered_spi_0:avalon_readdatavalid -> mm_interconnect_0:buffered_spi_0_avalon_readdatavalid
wire mm_interconnect_0_buffered_spi_0_avalon_write; // mm_interconnect_0:buffered_spi_0_avalon_write -> buffered_spi_0:avalon_write
wire [15:0] mm_interconnect_0_buffered_spi_0_avalon_writedata; // mm_interconnect_0:buffered_spi_0_avalon_writedata -> buffered_spi_0:avalon_writedata
wire [15:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_readdata; // abus_avalon_sdram_bridge_0:avalon_regs_readdata -> mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_readdata
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_waitrequest; // abus_avalon_sdram_bridge_0:avalon_regs_waitrequest -> mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_waitrequest
wire [7:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_address; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_address -> abus_avalon_sdram_bridge_0:avalon_regs_address
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_read; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_read -> abus_avalon_sdram_bridge_0:avalon_regs_read
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid; // abus_avalon_sdram_bridge_0:avalon_regs_readdatavalid -> mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_write; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_write -> abus_avalon_sdram_bridge_0:avalon_regs_write
wire [15:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_writedata; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_regs_writedata -> abus_avalon_sdram_bridge_0:avalon_regs_writedata
wire [15:0] mm_interconnect_0_heartbeat_0_avalon_regs_readdata; // heartbeat_0:avalon_regs_readdata -> mm_interconnect_0:heartbeat_0_avalon_regs_readdata
wire mm_interconnect_0_heartbeat_0_avalon_regs_waitrequest; // heartbeat_0:avalon_regs_waitrequest -> mm_interconnect_0:heartbeat_0_avalon_regs_waitrequest
wire [7:0] mm_interconnect_0_heartbeat_0_avalon_regs_address; // mm_interconnect_0:heartbeat_0_avalon_regs_address -> heartbeat_0:avalon_regs_address
wire mm_interconnect_0_heartbeat_0_avalon_regs_read; // mm_interconnect_0:heartbeat_0_avalon_regs_read -> heartbeat_0:avalon_regs_read
wire mm_interconnect_0_heartbeat_0_avalon_regs_readdatavalid; // heartbeat_0:avalon_regs_readdatavalid -> mm_interconnect_0:heartbeat_0_avalon_regs_readdatavalid
wire mm_interconnect_0_heartbeat_0_avalon_regs_write; // mm_interconnect_0:heartbeat_0_avalon_regs_write -> heartbeat_0:avalon_regs_write
wire [15:0] mm_interconnect_0_heartbeat_0_avalon_regs_writedata; // mm_interconnect_0:heartbeat_0_avalon_regs_writedata -> heartbeat_0:avalon_regs_writedata
wire [15:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_readdata; // abus_avalon_sdram_bridge_0:avalon_sdram_readdata -> mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_readdata
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest; // abus_avalon_sdram_bridge_0:avalon_sdram_waitrequest -> mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest
wire [25:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_address; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_address -> abus_avalon_sdram_bridge_0:avalon_sdram_address
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_read; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_read -> abus_avalon_sdram_bridge_0:avalon_sdram_read
wire [1:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_byteenable; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_byteenable -> abus_avalon_sdram_bridge_0:avalon_sdram_byteenable
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid; // abus_avalon_sdram_bridge_0:avalon_sdram_readdatavalid -> mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid
wire mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_write; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_write -> abus_avalon_sdram_bridge_0:avalon_sdram_write
wire [15:0] mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_writedata; // mm_interconnect_0:abus_avalon_sdram_bridge_0_avalon_sdram_writedata -> abus_avalon_sdram_bridge_0:avalon_sdram_writedata
wire [31:0] mm_interconnect_0_performance_counter_0_control_slave_readdata; // performance_counter_0:readdata -> mm_interconnect_0:performance_counter_0_control_slave_readdata
wire [2:0] mm_interconnect_0_performance_counter_0_control_slave_address; // mm_interconnect_0:performance_counter_0_control_slave_address -> performance_counter_0:address
wire mm_interconnect_0_performance_counter_0_control_slave_begintransfer; // mm_interconnect_0:performance_counter_0_control_slave_begintransfer -> performance_counter_0:begintransfer
wire mm_interconnect_0_performance_counter_0_control_slave_write; // mm_interconnect_0:performance_counter_0_control_slave_write -> performance_counter_0:write
wire [31:0] mm_interconnect_0_performance_counter_0_control_slave_writedata; // mm_interconnect_0:performance_counter_0_control_slave_writedata -> performance_counter_0:writedata
wire [31:0] mm_interconnect_0_onchip_flash_0_data_readdata; // onchip_flash_0:avmm_data_readdata -> mm_interconnect_0:onchip_flash_0_data_readdata
wire mm_interconnect_0_onchip_flash_0_data_waitrequest; // onchip_flash_0:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_0_data_waitrequest
wire [14:0] mm_interconnect_0_onchip_flash_0_data_address; // mm_interconnect_0:onchip_flash_0_data_address -> onchip_flash_0:avmm_data_addr
wire mm_interconnect_0_onchip_flash_0_data_read; // mm_interconnect_0:onchip_flash_0_data_read -> onchip_flash_0:avmm_data_read
wire mm_interconnect_0_onchip_flash_0_data_readdatavalid; // onchip_flash_0:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_0_data_readdatavalid
wire [3:0] mm_interconnect_0_onchip_flash_0_data_burstcount; // mm_interconnect_0:onchip_flash_0_data_burstcount -> onchip_flash_0:avmm_data_burstcount
wire [31:0] mm_interconnect_0_altpll_1_pll_slave_readdata; // altpll_1:readdata -> mm_interconnect_0:altpll_1_pll_slave_readdata
wire [1:0] mm_interconnect_0_altpll_1_pll_slave_address; // mm_interconnect_0:altpll_1_pll_slave_address -> altpll_1:address
wire mm_interconnect_0_altpll_1_pll_slave_read; // mm_interconnect_0:altpll_1_pll_slave_read -> altpll_1:read
wire mm_interconnect_0_altpll_1_pll_slave_write; // mm_interconnect_0:altpll_1_pll_slave_write -> altpll_1:write
wire [31:0] mm_interconnect_0_altpll_1_pll_slave_writedata; // mm_interconnect_0:altpll_1_pll_slave_writedata -> altpll_1:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [12:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_uart_0_s1_chipselect; // mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
wire [15:0] mm_interconnect_0_uart_0_s1_readdata; // uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
wire [2:0] mm_interconnect_0_uart_0_s1_address; // mm_interconnect_0:uart_0_s1_address -> uart_0:address
wire mm_interconnect_0_uart_0_s1_read; // mm_interconnect_0:uart_0_s1_read -> uart_0:read_n
wire mm_interconnect_0_uart_0_s1_begintransfer; // mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
wire mm_interconnect_0_uart_0_s1_write; // mm_interconnect_0:uart_0_s1_write -> uart_0:write_n
wire [15:0] mm_interconnect_0_uart_0_s1_writedata; // mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata; // nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest; // nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
wire [3:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
wire irq_mapper_receiver0_irq; // uart_0:irq -> irq_mapper:receiver0_irq
wire [31:0] nios2_gen2_0_irq_irq; // irq_mapper:sender_irq -> nios2_gen2_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [abus_avalon_sdram_bridge_0:reset, irq_mapper:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, nios2_gen2_0:reset_n, onchip_flash_0:reset_n, onchip_memory2_0:reset, rst_translator:in_reset, uart_0:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire reset_controller_0_reset_out_reset; // reset_controller_0:reset_out -> [rst_controller:reset_in0, rst_controller_002:reset_in0]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [altpll_1:reset, mm_interconnect_0:altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset]
abus_avalon_sdram_bridge abus_avalon_sdram_bridge_0 (
.abus_address (abus_avalon_sdram_bridge_0_abus_address), // abus.address
.abus_read (abus_avalon_sdram_bridge_0_abus_read), // .read
.abus_data (abus_avalon_sdram_bridge_0_abus_data), // .data
.abus_chipselect (abus_avalon_sdram_bridge_0_abus_chipselect), // .chipselect
.abus_direction (abus_avalon_sdram_bridge_0_abus_direction), // .direction
.abus_interrupt_disable_out (abus_avalon_sdram_bridge_0_abus_interrupt_disable_out), // .interrupt_disable_out
.abus_interrupt (abus_avalon_sdram_bridge_0_abus_interrupt), // .interrupt
.abus_write (abus_avalon_sdram_bridge_0_abus_writebyteenable_n), // .writebyteenable_n
.saturn_reset (abus_avalon_sdram_bridge_0_abus_reset), // .reset
.avalon_sdram_read (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_read), // avalon_sdram.read
.avalon_sdram_write (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_write), // .write
.avalon_sdram_waitrequest (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest), // .waitrequest
.avalon_sdram_address (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_address), // .address
.avalon_sdram_writedata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_writedata), // .writedata
.avalon_sdram_readdata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_readdata), // .readdata
.avalon_sdram_readdatavalid (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid), // .readdatavalid
.avalon_sdram_byteenable (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_byteenable), // .byteenable
.avalon_regs_read (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_read), // avalon_regs.read
.avalon_regs_write (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_write), // .write
.avalon_regs_waitrequest (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_waitrequest), // .waitrequest
.avalon_regs_address (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_address), // .address
.avalon_regs_writedata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_writedata), // .writedata
.avalon_regs_readdata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_readdata), // .readdata
.avalon_regs_readdatavalid (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid), // .readdatavalid
.reset (rst_controller_reset_out_reset), // reset.reset
.clock (clock_116_mhz_clk), // clock.clk
.sdram_addr (abus_avalon_sdram_bridge_0_sdram_addr), // sdram.addr
.sdram_ba (abus_avalon_sdram_bridge_0_sdram_ba), // .ba
.sdram_cas_n (abus_avalon_sdram_bridge_0_sdram_cas_n), // .cas_n
.sdram_cke (abus_avalon_sdram_bridge_0_sdram_cke), // .cke
.sdram_cs_n (abus_avalon_sdram_bridge_0_sdram_cs_n), // .cs_n
.sdram_dq (abus_avalon_sdram_bridge_0_sdram_dq), // .dq
.sdram_dqm (abus_avalon_sdram_bridge_0_sdram_dqm), // .dqm
.sdram_ras_n (abus_avalon_sdram_bridge_0_sdram_ras_n), // .ras_n
.sdram_we_n (abus_avalon_sdram_bridge_0_sdram_we_n), // .we_n
.sdram_clk (abus_avalon_sdram_bridge_0_sdram_clk) // .clk
);
wasca_altpll_1 altpll_1 (
.clk (clk_clk), // inclk_interface.clk
.reset (rst_controller_001_reset_out_reset), // inclk_interface_reset.reset
.read (mm_interconnect_0_altpll_1_pll_slave_read), // pll_slave.read
.write (mm_interconnect_0_altpll_1_pll_slave_write), // .write
.address (mm_interconnect_0_altpll_1_pll_slave_address), // .address
.readdata (mm_interconnect_0_altpll_1_pll_slave_readdata), // .readdata
.writedata (mm_interconnect_0_altpll_1_pll_slave_writedata), // .writedata
.c0 (clock_116_mhz_clk), // c0.clk
.scandone (), // (terminated)
.scandataout (), // (terminated)
.c1 (), // (terminated)
.c2 (), // (terminated)
.c3 (), // (terminated)
.c4 (), // (terminated)
.areset (1'b0), // (terminated)
.locked (), // (terminated)
.phasedone (), // (terminated)
.phasecounterselect (3'b000), // (terminated)
.phaseupdown (1'b0), // (terminated)
.phasestep (1'b0), // (terminated)
.scanclk (1'b0), // (terminated)
.scanclkena (1'b0), // (terminated)
.scandata (1'b0), // (terminated)
.configupdate (1'b0) // (terminated)
);
buffered_spi buffered_spi_0 (
.reset (nios2_gen2_0_debug_reset_request_reset), // reset.reset
.avalon_read (mm_interconnect_0_buffered_spi_0_avalon_read), // avalon.read
.avalon_write (mm_interconnect_0_buffered_spi_0_avalon_write), // .write
.avalon_address (mm_interconnect_0_buffered_spi_0_avalon_address), // .address
.avalon_waitrequest (mm_interconnect_0_buffered_spi_0_avalon_waitrequest), // .waitrequest
.avalon_writedata (mm_interconnect_0_buffered_spi_0_avalon_writedata), // .writedata
.avalon_readdata (mm_interconnect_0_buffered_spi_0_avalon_readdata), // .readdata
.avalon_readdatavalid (mm_interconnect_0_buffered_spi_0_avalon_readdatavalid), // .readdatavalid
.spi_mosi (buffered_spi_mosi), // conduit_end.mosi
.spi_clk (buffered_spi_clk), // .clk
.spi_miso (buffered_spi_miso), // .miso
.spi_cs (buffered_spi_cs), // .cs
.spi_sync_miso (buffered_spi_sync_miso), // .sync_miso
.spi_sync_mosi (buffered_spi_sync_mosi), // .sync_mosi
.clock (clock_116_mhz_clk) // clock.clk
);
heartbeat heartbeat_0 (
.reset (nios2_gen2_0_debug_reset_request_reset), // reset.reset
.avalon_regs_read (mm_interconnect_0_heartbeat_0_avalon_regs_read), // avalon_regs.read
.avalon_regs_write (mm_interconnect_0_heartbeat_0_avalon_regs_write), // .write
.avalon_regs_waitrequest (mm_interconnect_0_heartbeat_0_avalon_regs_waitrequest), // .waitrequest
.avalon_regs_address (mm_interconnect_0_heartbeat_0_avalon_regs_address), // .address
.avalon_regs_writedata (mm_interconnect_0_heartbeat_0_avalon_regs_writedata), // .writedata
.avalon_regs_readdata (mm_interconnect_0_heartbeat_0_avalon_regs_readdata), // .readdata
.avalon_regs_readdatavalid (mm_interconnect_0_heartbeat_0_avalon_regs_readdatavalid), // .readdatavalid
.clock (clock_116_mhz_clk), // clock.clk
.heartbeat_out (heartbeat_heartbeat_out) // heartbeat.heartbeat_out
);
wasca_nios2_gen2_0 nios2_gen2_0 (
.clk (clock_116_mhz_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.d_address (nios2_gen2_0_data_master_address), // data_master.address
.d_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.d_read (nios2_gen2_0_data_master_read), // .read
.d_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_gen2_0_data_master_write), // .write
.d_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_gen2_0_instruction_master_address), // instruction_master.address
.i_read (nios2_gen2_0_instruction_master_read), // .read
.i_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.irq (nios2_gen2_0_irq_irq), // irq.irq
.debug_reset_request (nios2_gen2_0_debug_reset_request_reset), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
altera_onchip_flash #(
.INIT_FILENAME ("wasca_onchip_flash_0.hex"),
.INIT_FILENAME_SIM ("wasca_onchip_flash_0.dat"),
.DEVICE_FAMILY ("MAX 10"),
.PART_NAME ("10M08SCE144C8G"),
.DEVICE_ID ("08"),
.SECTOR1_START_ADDR (0),
.SECTOR1_END_ADDR (4095),
.SECTOR2_START_ADDR (4096),
.SECTOR2_END_ADDR (8191),
.SECTOR3_START_ADDR (8192),
.SECTOR3_END_ADDR (23039),
.SECTOR4_START_ADDR (0),
.SECTOR4_END_ADDR (0),
.SECTOR5_START_ADDR (0),
.SECTOR5_END_ADDR (0),
.MIN_VALID_ADDR (0),
.MAX_VALID_ADDR (23039),
.MIN_UFM_VALID_ADDR (0),
.MAX_UFM_VALID_ADDR (23039),
.SECTOR1_MAP (1),
.SECTOR2_MAP (2),
.SECTOR3_MAP (4),
.SECTOR4_MAP (0),
.SECTOR5_MAP (0),
.ADDR_RANGE1_END_ADDR (8191),
.ADDR_RANGE2_END_ADDR (23039),
.ADDR_RANGE1_OFFSET (512),
.ADDR_RANGE2_OFFSET (21504),
.ADDR_RANGE3_OFFSET (0),
.AVMM_DATA_ADDR_WIDTH (15),
.AVMM_DATA_DATA_WIDTH (32),
.AVMM_DATA_BURSTCOUNT_WIDTH (4),
.SECTOR_READ_PROTECTION_MODE (31),
.FLASH_SEQ_READ_DATA_COUNT (2),
.FLASH_ADDR_ALIGNMENT_BITS (1),
.FLASH_READ_CYCLE_MAX_INDEX (4),
.FLASH_RESET_CYCLE_MAX_INDEX (29),
.FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX (139),
.FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX (40603248),
.FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX (35382),
.PARALLEL_MODE (1),
.READ_AND_WRITE_MODE (0),
.WRAPPING_BURST_MODE (0),
.IS_DUAL_BOOT ("False"),
.IS_ERAM_SKIP ("True"),
.IS_COMPRESSED_IMAGE ("True")
) onchip_flash_0 (
.clock (clock_116_mhz_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // nreset.reset_n
.avmm_data_addr (mm_interconnect_0_onchip_flash_0_data_address), // data.address
.avmm_data_read (mm_interconnect_0_onchip_flash_0_data_read), // .read
.avmm_data_readdata (mm_interconnect_0_onchip_flash_0_data_readdata), // .readdata
.avmm_data_waitrequest (mm_interconnect_0_onchip_flash_0_data_waitrequest), // .waitrequest
.avmm_data_readdatavalid (mm_interconnect_0_onchip_flash_0_data_readdatavalid), // .readdatavalid
.avmm_data_burstcount (mm_interconnect_0_onchip_flash_0_data_burstcount), // .burstcount
.avmm_data_writedata (32'b00000000000000000000000000000000), // (terminated)
.avmm_data_write (1'b0), // (terminated)
.avmm_csr_addr (1'b0), // (terminated)
.avmm_csr_read (1'b0), // (terminated)
.avmm_csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.avmm_csr_write (1'b0), // (terminated)
.avmm_csr_readdata () // (terminated)
);
wasca_onchip_memory2_0 onchip_memory2_0 (
.clk (clock_116_mhz_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.freeze (1'b0) // (terminated)
);
wasca_performance_counter_0 performance_counter_0 (
.clk (clock_116_mhz_clk), // clk.clk
.reset_n (~nios2_gen2_0_debug_reset_request_reset), // reset.reset_n
.address (mm_interconnect_0_performance_counter_0_control_slave_address), // control_slave.address
.begintransfer (mm_interconnect_0_performance_counter_0_control_slave_begintransfer), // .begintransfer
.readdata (mm_interconnect_0_performance_counter_0_control_slave_readdata), // .readdata
.write (mm_interconnect_0_performance_counter_0_control_slave_write), // .write
.writedata (mm_interconnect_0_performance_counter_0_control_slave_writedata) // .writedata
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) reset_controller_0 (
.reset_in0 (nios2_gen2_0_debug_reset_request_reset), // reset_in0.reset
.reset_in1 (reset_controller_0_reset_in1_reset), // reset_in1.reset
.clk (clock_116_mhz_clk), // clk.clk
.reset_out (reset_controller_0_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
wasca_uart_0 uart_0 (
.clk (clock_116_mhz_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_uart_0_s1_address), // s1.address
.begintransfer (mm_interconnect_0_uart_0_s1_begintransfer), // .begintransfer
.chipselect (mm_interconnect_0_uart_0_s1_chipselect), // .chipselect
.read_n (~mm_interconnect_0_uart_0_s1_read), // .read_n
.write_n (~mm_interconnect_0_uart_0_s1_write), // .write_n
.writedata (mm_interconnect_0_uart_0_s1_writedata), // .writedata
.readdata (mm_interconnect_0_uart_0_s1_readdata), // .readdata
.rxd (uart_0_external_connection_rxd), // external_connection.export
.txd (uart_0_external_connection_txd), // .export
.irq (irq_mapper_receiver0_irq) // irq.irq
);
wasca_mm_interconnect_0 mm_interconnect_0 (
.altpll_1_c0_clk (clock_116_mhz_clk), // altpll_1_c0.clk
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // altpll_1_inclk_interface_reset_reset_bridge_in_reset.reset
.buffered_spi_0_reset_reset_bridge_in_reset_reset (nios2_gen2_0_debug_reset_request_reset), // buffered_spi_0_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_gen2_0_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_data_master_address (nios2_gen2_0_data_master_address), // nios2_gen2_0_data_master.address
.nios2_gen2_0_data_master_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.nios2_gen2_0_data_master_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.nios2_gen2_0_data_master_read (nios2_gen2_0_data_master_read), // .read
.nios2_gen2_0_data_master_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.nios2_gen2_0_data_master_write (nios2_gen2_0_data_master_write), // .write
.nios2_gen2_0_data_master_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.nios2_gen2_0_data_master_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.nios2_gen2_0_instruction_master_address (nios2_gen2_0_instruction_master_address), // nios2_gen2_0_instruction_master.address
.nios2_gen2_0_instruction_master_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.nios2_gen2_0_instruction_master_read (nios2_gen2_0_instruction_master_read), // .read
.nios2_gen2_0_instruction_master_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.abus_avalon_sdram_bridge_0_avalon_regs_address (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_address), // abus_avalon_sdram_bridge_0_avalon_regs.address
.abus_avalon_sdram_bridge_0_avalon_regs_write (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_write), // .write
.abus_avalon_sdram_bridge_0_avalon_regs_read (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_read), // .read
.abus_avalon_sdram_bridge_0_avalon_regs_readdata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_readdata), // .readdata
.abus_avalon_sdram_bridge_0_avalon_regs_writedata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_writedata), // .writedata
.abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid), // .readdatavalid
.abus_avalon_sdram_bridge_0_avalon_regs_waitrequest (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_regs_waitrequest), // .waitrequest
.abus_avalon_sdram_bridge_0_avalon_sdram_address (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_address), // abus_avalon_sdram_bridge_0_avalon_sdram.address
.abus_avalon_sdram_bridge_0_avalon_sdram_write (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_write), // .write
.abus_avalon_sdram_bridge_0_avalon_sdram_read (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_read), // .read
.abus_avalon_sdram_bridge_0_avalon_sdram_readdata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_readdata), // .readdata
.abus_avalon_sdram_bridge_0_avalon_sdram_writedata (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_writedata), // .writedata
.abus_avalon_sdram_bridge_0_avalon_sdram_byteenable (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_byteenable), // .byteenable
.abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid), // .readdatavalid
.abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest (mm_interconnect_0_abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest), // .waitrequest
.altpll_1_pll_slave_address (mm_interconnect_0_altpll_1_pll_slave_address), // altpll_1_pll_slave.address
.altpll_1_pll_slave_write (mm_interconnect_0_altpll_1_pll_slave_write), // .write
.altpll_1_pll_slave_read (mm_interconnect_0_altpll_1_pll_slave_read), // .read
.altpll_1_pll_slave_readdata (mm_interconnect_0_altpll_1_pll_slave_readdata), // .readdata
.altpll_1_pll_slave_writedata (mm_interconnect_0_altpll_1_pll_slave_writedata), // .writedata
.buffered_spi_0_avalon_address (mm_interconnect_0_buffered_spi_0_avalon_address), // buffered_spi_0_avalon.address
.buffered_spi_0_avalon_write (mm_interconnect_0_buffered_spi_0_avalon_write), // .write
.buffered_spi_0_avalon_read (mm_interconnect_0_buffered_spi_0_avalon_read), // .read
.buffered_spi_0_avalon_readdata (mm_interconnect_0_buffered_spi_0_avalon_readdata), // .readdata
.buffered_spi_0_avalon_writedata (mm_interconnect_0_buffered_spi_0_avalon_writedata), // .writedata
.buffered_spi_0_avalon_readdatavalid (mm_interconnect_0_buffered_spi_0_avalon_readdatavalid), // .readdatavalid
.buffered_spi_0_avalon_waitrequest (mm_interconnect_0_buffered_spi_0_avalon_waitrequest), // .waitrequest
.heartbeat_0_avalon_regs_address (mm_interconnect_0_heartbeat_0_avalon_regs_address), // heartbeat_0_avalon_regs.address
.heartbeat_0_avalon_regs_write (mm_interconnect_0_heartbeat_0_avalon_regs_write), // .write
.heartbeat_0_avalon_regs_read (mm_interconnect_0_heartbeat_0_avalon_regs_read), // .read
.heartbeat_0_avalon_regs_readdata (mm_interconnect_0_heartbeat_0_avalon_regs_readdata), // .readdata
.heartbeat_0_avalon_regs_writedata (mm_interconnect_0_heartbeat_0_avalon_regs_writedata), // .writedata
.heartbeat_0_avalon_regs_readdatavalid (mm_interconnect_0_heartbeat_0_avalon_regs_readdatavalid), // .readdatavalid
.heartbeat_0_avalon_regs_waitrequest (mm_interconnect_0_heartbeat_0_avalon_regs_waitrequest), // .waitrequest
.nios2_gen2_0_debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // nios2_gen2_0_debug_mem_slave.address
.nios2_gen2_0_debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.nios2_gen2_0_debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.nios2_gen2_0_debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.nios2_gen2_0_debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.nios2_gen2_0_debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.nios2_gen2_0_debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.nios2_gen2_0_debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.onchip_flash_0_data_address (mm_interconnect_0_onchip_flash_0_data_address), // onchip_flash_0_data.address
.onchip_flash_0_data_read (mm_interconnect_0_onchip_flash_0_data_read), // .read
.onchip_flash_0_data_readdata (mm_interconnect_0_onchip_flash_0_data_readdata), // .readdata
.onchip_flash_0_data_burstcount (mm_interconnect_0_onchip_flash_0_data_burstcount), // .burstcount
.onchip_flash_0_data_readdatavalid (mm_interconnect_0_onchip_flash_0_data_readdatavalid), // .readdatavalid
.onchip_flash_0_data_waitrequest (mm_interconnect_0_onchip_flash_0_data_waitrequest), // .waitrequest
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.performance_counter_0_control_slave_address (mm_interconnect_0_performance_counter_0_control_slave_address), // performance_counter_0_control_slave.address
.performance_counter_0_control_slave_write (mm_interconnect_0_performance_counter_0_control_slave_write), // .write
.performance_counter_0_control_slave_readdata (mm_interconnect_0_performance_counter_0_control_slave_readdata), // .readdata
.performance_counter_0_control_slave_writedata (mm_interconnect_0_performance_counter_0_control_slave_writedata), // .writedata
.performance_counter_0_control_slave_begintransfer (mm_interconnect_0_performance_counter_0_control_slave_begintransfer), // .begintransfer
.uart_0_s1_address (mm_interconnect_0_uart_0_s1_address), // uart_0_s1.address
.uart_0_s1_write (mm_interconnect_0_uart_0_s1_write), // .write
.uart_0_s1_read (mm_interconnect_0_uart_0_s1_read), // .read
.uart_0_s1_readdata (mm_interconnect_0_uart_0_s1_readdata), // .readdata
.uart_0_s1_writedata (mm_interconnect_0_uart_0_s1_writedata), // .writedata
.uart_0_s1_begintransfer (mm_interconnect_0_uart_0_s1_begintransfer), // .begintransfer
.uart_0_s1_chipselect (mm_interconnect_0_uart_0_s1_chipselect) // .chipselect
);
wasca_irq_mapper irq_mapper (
.clk (clock_116_mhz_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (nios2_gen2_0_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (reset_controller_0_reset_out_reset), // reset_in0.reset
.clk (clock_116_mhz_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("both"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (reset_controller_0_reset_out_reset), // reset_in0.reset
.clk (clock_116_mhz_clk), // clk.clk
.reset_out (), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_dft_creg.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "sys.h"
`include "iop.h"
`include "ctu.h"
module ctu_dft_creg (/*AUTOARG*/
// Outputs
creg_jtag_scratch_data, creg_jtag_rdrtrn_data, creg_jtag_rdrtrn_vld,
tap_iob_stall, tap_iob_vld, tap_iob_data, rt_ack, rt_data_out,
// Inputs
io_tck, jbus_clk, jbus_rst_l, io_pwron_rst_l, test_mode_pin,
bist_mode_pin, start_clk_jl, jtag_creg_addr, jtag_creg_data,
jtag_creg_rd_en, jtag_creg_wr_en, jtag_creg_addr_en,
jtag_creg_data_en, jtag_creg_rdrtrn_complete, iob_tap_vld,
iob_tap_data, iob_tap_stall, rt_valid, rt_addr_data, rt_read_write,
rt_high_low, rt_data_in, bist_jtag_result
);
//global inputs
input io_tck;
input jbus_clk;
input jbus_rst_l;
input io_pwron_rst_l;
input test_mode_pin;
input bist_mode_pin;
// clspn
input start_clk_jl;
//jtag block interface
input [39:0] jtag_creg_addr;
input [63:0] jtag_creg_data;
input jtag_creg_rd_en;
input jtag_creg_wr_en;
input jtag_creg_addr_en;
input jtag_creg_data_en;
output [63:0] creg_jtag_scratch_data;
output [63:0] creg_jtag_rdrtrn_data;
output creg_jtag_rdrtrn_vld;
input jtag_creg_rdrtrn_complete;
//iob interface
output tap_iob_stall;
input iob_tap_vld;
input [7:0] iob_tap_data;
output tap_iob_vld;
output [7:0] tap_iob_data;
input iob_tap_stall;
// ramtest signals
input rt_valid;
input rt_addr_data;
input rt_read_write;
input rt_high_low;
input [31:0] rt_data_in;
output rt_ack;
output [31:0] rt_data_out;
// bist
input [(`CTU_BIST_CNT*2)-1:0] bist_jtag_result;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire [63:0] creg_jtag_scratch_data;
wire [63:0] creg_jtag_rdrtrn_data;
wire creg_jtag_rdrtrn_vld;
wire tap_iob_stall;
wire tap_iob_vld;
wire [7:0] tap_iob_data;
wire rt_ack;
reg [31:0] rt_data_out;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
//inputs from jtag_block synchronized to jbus_clk
wire jtag_creg_rd_en_sync;
wire jtag_creg_wr_en_sync;
wire jtag_creg_addr_en_sync;
wire jtag_creg_data_en_sync;
wire [39:0] jtag_creg_addr_sync;
wire [63:0] jtag_creg_data_sync;
wire jtag_creg_rdrtrn_complete_sync;
wire [39:0] jtag_addr_reg;
wire [63:0] jtag_data_reg;
wire [63:0] scratch_reg;
wire [63:0] rdrtrn_reg;
wire rdrtrn_reg_vld;
wire [7:0] rt_addr_high;
wire [31:0] rt_addr_low;
wire [31:0] rt_data_high;
wire [31:0] rt_data_low;
wire [7:0] ramtest_addr_high;
wire [31:0] ramtest_addr_low;
wire [31:0] ramtest_data_high;
wire [31:0] ramtest_data_low;
wire ramtest_rw;
wire [63:0] ramtest_rdrtrn;
wire ramtest_req;
wire ramtest_rd_pend;
wire jtag_rd_req;
wire jtag_wr_req;
wire jtag_rd_pend;
wire csr_ack_req;
wire [`UCB_BUF_HI-`UCB_BUF_LO:0] csr_buf_id;
wire [`UCB_THR_HI-`UCB_THR_LO:0] csr_thr_id;
wire [39:0] next_jtag_addr_reg;
wire [63:0] next_jtag_data_reg;
wire [63:0] next_scratch_reg;
wire [63:0] next_rdrtrn_reg;
wire next_rdrtrn_reg_vld;
reg [7:0] next_rt_addr_high;
reg [31:0] next_rt_addr_low;
reg [31:0] next_rt_data_high;
reg [31:0] next_rt_data_low;
wire [7:0] next_ramtest_addr_high;
wire [31:0] next_ramtest_addr_low;
wire [31:0] next_ramtest_data_high;
wire [31:0] next_ramtest_data_low;
wire next_ramtest_rw;
wire [63:0] next_ramtest_rdrtrn;
wire next_ramtest_req;
wire next_ramtest_rd_pend;
wire next_jtag_rd_req;
wire next_jtag_wr_req;
wire next_jtag_rd_pend;
wire next_csr_ack_req;
wire [`UCB_BUF_HI-`UCB_BUF_LO:0] next_csr_buf_id;
wire [`UCB_THR_HI-`UCB_THR_LO:0] next_csr_thr_id;
wire next_rt_ack;
wire jtag_addr_reg_en;
wire jtag_data_reg_en;
wire scratch_reg_en;
wire rdrtrn_reg_en;
wire rt_addr_high_en;
wire rt_addr_low_en;
wire rt_data_high_en;
wire rt_data_low_en;
wire ramtest_addr_high_en;
wire ramtest_addr_low_en;
wire ramtest_data_high_en;
wire ramtest_data_low_en;
wire ramtest_rw_en;
wire ramtest_rdrtrn_en;
wire csr_buf_id_en;
wire csr_thr_id_en;
wire [63:0] scratch_reg_sync;
wire [63:0] rdrtrn_reg_sync;
wire rdrtrn_reg_vld_sync;
wire jtag_creg_wr_en_sync_d1;
wire jtag_creg_rd_en_sync_d1;
wire ucbout_write_pulse;
wire ucbout_read_pulse;
wire ucbout_ack_pulse;
reg [63:0] ucbout_data;
reg [39:0] ucbout_addr;
reg [`UCB_SIZE_HI-`UCB_SIZE_LO:0] ucbout_size;
reg [`UCB_BUF_HI-`UCB_BUF_LO:0] ucbout_buf_id;
reg [`UCB_THR_HI-`UCB_THR_LO:0] ucbout_thr_id;
reg [`UCB_PKT_HI-`UCB_PKT_LO:0] ucbout_request_code;
reg [15:0] ucbout_vec;
wire [127:0] ucbout_buf;
wire ucbout_outdata_busy;
wire ucbout_outdata_wr;
wire [127:0] ucbin_buf;
wire ucbin_buf_vld;
wire [3:0] ucbin_request;
wire [63:0] ucbin_data;
wire ucbin_rdrtrn_req;
wire ucbin_write_req;
wire ucbin_read_req;
wire rt_valid_sync;
wire rt_valid_sync_d1;
wire rt_valid_negedge;
wire req_acpt;
wire ack_acpt;
wire ramtest_rd_pend_sync;
wire ramtest_rd_pend_sync_d1;
wire ramtest_rd_pend_sync_negedge;
wire [63:0] ramtest_rdrtrn_sync;
wire rt_read_write_d1;
wire rt_read_write_negedge;
wire start_clk_jl_sync;
//*******************************************************************************
// Registers
//*******************************************************************************
//---------------------------
// Address Register
//---------------------------
// jbus_clk (assume tck period always longer than jbus_clk - no handshake needed)
assign next_jtag_addr_reg = jtag_creg_addr_sync;
assign jtag_addr_reg_en = jtag_creg_addr_en_sync;
//---------------------------
// Address Register
//---------------------------
// jbus_clk (assume tck period always longer than jbus_clk - no handshake needed)
assign next_jtag_data_reg = jtag_creg_data_sync;
assign jtag_data_reg_en = jtag_creg_data_en_sync;
// Handshake Protocol for jbus_clk -> tck domain
// ---------------------------------------------
// Since the write enable in jbus_clk will go away before the logic at tck
// is able to flop it and do anything with it. Therefore, at jbus_clk, we execute
// a handshake protocol:
// - writing the rdrtrn_reg register sets the valid bit (jbus_clk)
// which is cleared when jtag has finished reading it (tck)
//---------------------------
// Read Return Data
//---------------------------
// tck domain
assign creg_jtag_rdrtrn_vld = start_clk_jl_sync //wait until jbus_clk starts toggling
& rdrtrn_reg_vld_sync;
assign creg_jtag_rdrtrn_data = rdrtrn_reg_sync;
// jbus_clk domain
assign next_rdrtrn_reg = ucbin_data;
assign rdrtrn_reg_en = jtag_rd_pend & ucbin_rdrtrn_req;
assign next_rdrtrn_reg_vld = ~jtag_creg_rdrtrn_complete_sync
& ( (jtag_rd_pend & ucbin_rdrtrn_req)
| rdrtrn_reg_vld);
//---------------------------
// Scratch Register
//---------------------------
// tck domain
assign creg_jtag_scratch_data = scratch_reg_sync;
// jbus_clk domain
// - because tap only has one R/W register, not doing address match and
// assume all reads and writes are to the scatch
assign next_scratch_reg = ucbin_data;
assign scratch_reg_en = ucbin_write_req;
//*******************************************************************************
// RAMTEST
// - test_mode_pin assertion makes RAMTEST ports availabel
//*******************************************************************************
//------------
// tck domain
//------------
assign rt_addr_high_en = test_mode_pin & rt_valid & rt_addr_data & rt_high_low;
always @ ( /*AUTOSENSE*/rt_addr_high or rt_addr_high_en or rt_data_in) begin
if (rt_addr_high_en)
next_rt_addr_high = rt_data_in[7:0];
else
next_rt_addr_high = rt_addr_high;
end
assign rt_addr_low_en = test_mode_pin & rt_valid & rt_addr_data & ~rt_high_low;
always @ ( /*AUTOSENSE*/rt_addr_low or rt_addr_low_en or rt_data_in) begin
if (rt_addr_low_en)
next_rt_addr_low = rt_data_in;
else
next_rt_addr_low= rt_addr_low;
end
assign rt_data_high_en = test_mode_pin & rt_valid & ~rt_addr_data & rt_high_low;
always @ ( /*AUTOSENSE*/rt_data_high or rt_data_high_en or rt_data_in) begin
if (rt_data_high_en)
next_rt_data_high = rt_data_in;
else
next_rt_data_high = rt_data_high;
end
assign rt_data_low_en = test_mode_pin & rt_valid & ~rt_addr_data & ~rt_high_low;
always @ ( /*AUTOSENSE*/rt_data_in or rt_data_low or rt_data_low_en) begin
if (rt_data_low_en)
next_rt_data_low = rt_data_in;
else
next_rt_data_low = rt_data_low;
end
assign ramtest_rd_pend_sync_negedge = ~ramtest_rd_pend_sync & ramtest_rd_pend_sync_d1;
assign rt_read_write_negedge = test_mode_pin & ~rt_read_write & rt_read_write_d1;
assign next_rt_ack = start_clk_jl_sync //wait until jbus_clk starts toggling
& ( (~rt_ack & ramtest_rd_pend_sync_negedge)
| ( rt_ack & ~rt_read_write_negedge));
always @ ( /*AUTOSENSE*/bist_jtag_result or bist_mode_pin
or ramtest_rdrtrn_sync or rt_high_low or test_mode_pin) begin
if (test_mode_pin & bist_mode_pin)
rt_data_out = { {32-(`CTU_BIST_CNT*2){1'b0}}, bist_jtag_result };
else begin
if (rt_high_low)
rt_data_out = ramtest_rdrtrn_sync[63:32];
else
rt_data_out = ramtest_rdrtrn_sync[31: 0];
end
end
//------------
// jbus_clk
//------------
// use falling edge of rt_valid to sync transfer of addr and data from tck to jbus clk domain
assign rt_valid_negedge = test_mode_pin & ~rt_valid_sync & rt_valid_sync_d1;
// request and info registers
assign next_ramtest_addr_high = rt_addr_high;
assign ramtest_addr_high_en = rt_valid_negedge;
assign next_ramtest_addr_low = rt_addr_low;
assign ramtest_addr_low_en = rt_valid_negedge;
assign next_ramtest_data_high = rt_data_high;
assign ramtest_data_high_en = rt_valid_negedge;
assign next_ramtest_data_low = rt_data_low;
assign ramtest_data_low_en = rt_valid_negedge;
assign next_ramtest_rw = rt_read_write;
assign ramtest_rw_en = rt_valid_negedge;
// read return data
assign next_ramtest_rdrtrn = ucbin_data;
assign ramtest_rdrtrn_en = ramtest_rd_pend & ucbin_rdrtrn_req;
//*******************************************************************************
// IOB Interface Logic
// - jbus clk domain
//*******************************************************************************
//-------------
// outbound ucb
//-------------
ucb_bus_out #(8,64) u_ucb_out
( // outputs
.vld (tap_iob_vld),
.data (tap_iob_data),
.outdata_buf_busy (ucbout_outdata_busy),
// inputs
.clk (jbus_clk),
.rst_l (jbus_rst_l),
.stall (iob_tap_stall),
.outdata_buf_in (ucbout_buf),
.outdata_vec_in (ucbout_vec),
.outdata_buf_wr (ucbout_outdata_wr)
);
// ramtest request
assign next_ramtest_req = rt_valid_negedge
| ramtest_req & ~req_acpt;
assign next_ramtest_rd_pend = ramtest_req & ramtest_rw & req_acpt
| ramtest_rd_pend & ~ucbin_rdrtrn_req;
// jtag request
assign next_jtag_rd_req = jtag_creg_rd_en_sync & ~jtag_creg_rd_en_sync_d1
| jtag_rd_req & ~req_acpt;
assign next_jtag_wr_req = jtag_creg_wr_en_sync & ~jtag_creg_wr_en_sync_d1
| jtag_wr_req & ~req_acpt;
assign next_jtag_rd_pend = jtag_rd_req & req_acpt
| jtag_rd_pend & ~ucbin_rdrtrn_req;
// generate read or write valid pulse if busy signal unasserted and not servicing iob read request
assign ucbout_read_pulse = ~ucbout_outdata_busy
& ~csr_ack_req
& (jtag_rd_req | (ramtest_req & ramtest_rw));
assign ucbout_write_pulse = ~ucbout_outdata_busy
& ~csr_ack_req
& (jtag_wr_req | (ramtest_req & ~ramtest_rw));
assign ucbout_ack_pulse = ~ucbout_outdata_busy & csr_ack_req;
// accept request - assume never running jtag and ramtest mode concurrently
assign req_acpt = ucbout_read_pulse | ucbout_write_pulse;
assign ack_acpt = ucbout_ack_pulse;
// issue request
assign ucbout_outdata_wr = ucbout_read_pulse | ucbout_write_pulse | ucbout_ack_pulse;
always @ ( /*AUTOSENSE*/csr_ack_req or ucbout_write_pulse) begin
if (csr_ack_req) begin
ucbout_vec = 16'hffff;
ucbout_request_code = `UCB_READ_ACK;
end
else if (ucbout_write_pulse) begin
ucbout_vec = 16'hffff;
ucbout_request_code = `UCB_WRITE_REQ;
end
else begin // read
ucbout_vec = 16'h00ff;
ucbout_request_code = `UCB_READ_REQ;
end
end
always @ ( /*AUTOSENSE*/csr_ack_req or csr_buf_id or csr_thr_id
or jtag_addr_reg or jtag_data_reg or ramtest_addr_high
or ramtest_addr_low or ramtest_data_high or ramtest_data_low
or ramtest_req or scratch_reg) begin
if (csr_ack_req) begin
ucbout_data = scratch_reg;
ucbout_addr = {40{1'b0}};
ucbout_size = {(`UCB_SIZE_HI-`UCB_SIZE_LO+1){1'b0}};
ucbout_buf_id = csr_buf_id;
ucbout_thr_id = csr_thr_id;
end
else if (ramtest_req) begin
ucbout_data = {ramtest_data_high, ramtest_data_low};
ucbout_addr = {ramtest_addr_high[7:0], ramtest_addr_low};
ucbout_size = `PCX_SZ_8B;
ucbout_buf_id = `UCB_BID_TAP;
ucbout_thr_id = {(`UCB_THR_HI-`UCB_THR_LO+1){1'b0}};
end
else begin
ucbout_data = jtag_data_reg;
ucbout_addr = jtag_addr_reg;
ucbout_size = `PCX_SZ_8B;
ucbout_buf_id = `UCB_BID_TAP;
ucbout_thr_id = {(`UCB_THR_HI-`UCB_THR_LO+1){1'b0}};
end
end
assign ucbout_buf = { ucbout_data,
{9{1'b0}},
ucbout_addr,
ucbout_size,
ucbout_buf_id,
ucbout_thr_id,
ucbout_request_code};
//------------
// inbound ucb
//------------
ucb_bus_in #(8,64) u_ucb_in
( // outputs
.stall (tap_iob_stall),
.indata_buf_vld (ucbin_buf_vld),
.indata_buf (ucbin_buf),
// inputs
.rst_l (jbus_rst_l),
.clk (jbus_clk),
.vld (iob_tap_vld),
.data (iob_tap_data),
.stall_a1 (csr_ack_req)
);
// decode the request coming in.
// there are three which we care about
// 1. write requests - always write to scratch reg
// 2. read returns
// 3. write acks -- these will be discarded
// 4. read request -- always ack with scratch_reg
assign ucbin_request = ucbin_buf[`UCB_PKT_HI:`UCB_PKT_LO];
//assign ucbin_address = ucbin_buf[`UCB_ADDR_HI:`UCB_ADDR_LO];
assign ucbin_data = ucbin_buf[`UCB_DATA_HI:`UCB_DATA_LO];
assign ucbin_rdrtrn_req = ucbin_buf_vld & ucbin_request == `UCB_READ_ACK;
assign ucbin_write_req = ucbin_buf_vld & ucbin_request == `UCB_WRITE_REQ;
assign ucbin_read_req = ucbin_buf_vld & ucbin_request == `UCB_READ_REQ;
// read return to iob
assign csr_thr_id_en = ucbin_read_req;
assign next_csr_thr_id = ucbin_buf[`UCB_THR_HI:`UCB_THR_LO];
assign csr_buf_id_en = ucbin_read_req;
assign next_csr_buf_id = ucbin_buf[`UCB_BUF_HI:`UCB_BUF_LO];
assign next_csr_ack_req = ucbin_read_req
| csr_ack_req & ~ack_acpt;
//*******************************************************************************
// Synchronizers
//*******************************************************************************
//------------------
// tck -> jbus_clk
//------------------
ctu_synchronizer u_jtag_creg_rd_en_sync
( .syncdata (jtag_creg_rd_en_sync),
.presyncdata (jtag_creg_rd_en),
.clk (jbus_clk)
);
ctu_synchronizer u_jtag_creg_wr_en_sync
( .syncdata (jtag_creg_wr_en_sync),
.presyncdata (jtag_creg_wr_en),
.clk (jbus_clk)
);
ctu_synchronizer u_jtag_creg_addr_en_sync
( .syncdata (jtag_creg_addr_en_sync),
.presyncdata (jtag_creg_addr_en),
.clk (jbus_clk)
);
ctu_synchronizer u_jtag_creg_data_en_sync
( .syncdata (jtag_creg_data_en_sync),
.presyncdata (jtag_creg_data_en),
.clk (jbus_clk)
);
ctu_synchronizer #(40) u_jtag_creg_addr_sync
( .syncdata (jtag_creg_addr_sync),
.presyncdata (jtag_creg_addr),
.clk (jbus_clk)
);
ctu_synchronizer #(64) u_jtag_creg_data_sync
( .syncdata (jtag_creg_data_sync),
.presyncdata (jtag_creg_data),
.clk (jbus_clk)
);
ctu_synchronizer u_sync_jtag_creg_rdrtrn_complete
( .presyncdata (jtag_creg_rdrtrn_complete),
.syncdata (jtag_creg_rdrtrn_complete_sync),
.clk (jbus_clk)
);
ctu_synchronizer u_sync_rt_valid
( .presyncdata (rt_valid),
.syncdata (rt_valid_sync),
.clk (jbus_clk)
);
//------------------
// jbus_clk -> tck
//------------------
ctu_synchronizer #(64) u_sync_rdrtrn_reg
( .presyncdata (rdrtrn_reg),
.syncdata (rdrtrn_reg_sync),
.clk (io_tck)
);
ctu_synchronizer #(64) u_sync_scratch_reg
( .presyncdata (scratch_reg),
.syncdata (scratch_reg_sync),
.clk (io_tck)
);
ctu_synchronizer u_sync_rdrtrn_reg_vld
( .presyncdata (rdrtrn_reg_vld),
.syncdata (rdrtrn_reg_vld_sync),
.clk (io_tck)
);
ctu_synchronizer u_sync_ramtest_rd_pend
( .presyncdata (ramtest_rd_pend),
.syncdata (ramtest_rd_pend_sync),
.clk (io_tck)
);
ctu_synchronizer #(64) u_sync_ramtest_rdrtrn
( .presyncdata (ramtest_rdrtrn),
.syncdata (ramtest_rdrtrn_sync),
.clk (io_tck)
);
ctu_synchronizer u_sync_start_clk_jl
( .presyncdata (start_clk_jl),
.syncdata (start_clk_jl_sync),
.clk (io_tck)
);
//*******************************************************************************
// Async DFFRL Instantiations
//*******************************************************************************
// tck
dffrl_async_ns #(8) u_dffrl_async_rt_addr_high
( .din (next_rt_addr_high),
.clk (io_tck),
.rst_l (io_pwron_rst_l),
.q (rt_addr_high)
);
dffrl_async_ns #(32) u_dffrl_async_rt_addr_low
( .din (next_rt_addr_low),
.clk (io_tck),
.rst_l (io_pwron_rst_l),
.q (rt_addr_low)
);
dffrl_async_ns #(32) u_dffrl_async_rt_data_high
( .din (next_rt_data_high),
.clk (io_tck),
.rst_l (io_pwron_rst_l),
.q (rt_data_high)
);
dffrl_async_ns #(32) u_dffrl_async_rt_data_low
( .din (next_rt_data_low),
.clk (io_tck),
.rst_l (io_pwron_rst_l),
.q (rt_data_low)
);
dffrl_async_ns #(1) u_dffrl_async_rt_ack
( .din (next_rt_ack),
.clk (io_tck),
.rst_l (io_pwron_rst_l),
.q (rt_ack)
);
//*******************************************************************************
// DFF Instantiations
//*******************************************************************************
// jbus_clk
dff_ns u_dff_jtag_creg_wr_en_sync_d1
( .din (jtag_creg_wr_en_sync),
.clk (jbus_clk),
.q (jtag_creg_wr_en_sync_d1)
);
dff_ns u_dff_jtag_creg_rd_en_sync_d1
( .din (jtag_creg_rd_en_sync),
.clk (jbus_clk),
.q (jtag_creg_rd_en_sync_d1)
);
dff_ns u_dff_rt_valid_sync_d1
( .din (rt_valid_sync),
.clk (jbus_clk),
.q (rt_valid_sync_d1)
);
// tck
dff_ns u_dff_ramtest_rd_pend_sync_d1
( .din (ramtest_rd_pend_sync),
.clk (io_tck),
.q (ramtest_rd_pend_sync_d1)
);
dff_ns u_dff_rt_read_write_d1
( .din (rt_read_write),
.clk (io_tck),
.q (rt_read_write_d1)
);
//*******************************************************************************
// DFFRL Instantiations
//*******************************************************************************
// jbus_clk
dffrl_ns u_dffrl_rdrtrn_reg_vld
( .din (next_rdrtrn_reg_vld),
.q (rdrtrn_reg_vld),
.rst_l (jbus_rst_l),
.clk (jbus_clk)
);
dffrl_ns u_dffrl_ramtest_req
( .din (next_ramtest_req),
.q (ramtest_req),
.rst_l (jbus_rst_l),
.clk (jbus_clk)
);
dffrl_ns u_dffrl_ramtest_rd_pend
( .din (next_ramtest_rd_pend),
.q (ramtest_rd_pend),
.rst_l (jbus_rst_l),
.clk (jbus_clk)
);
dffrl_ns u_dffrl_jtag_rd_req
( .din (next_jtag_rd_req),
.q (jtag_rd_req),
.rst_l (jbus_rst_l),
.clk (jbus_clk)
);
dffrl_ns u_dffrl_jtag_wr_req
( .din (next_jtag_wr_req),
.q (jtag_wr_req),
.rst_l (jbus_rst_l),
.clk (jbus_clk)
);
dffrl_ns u_dffrl_jtag_rd_pend
( .din (next_jtag_rd_pend),
.q (jtag_rd_pend),
.rst_l (jbus_rst_l),
.clk (jbus_clk)
);
dffrl_ns u_dffrl_csr_ack_req
( .din (next_csr_ack_req),
.q (csr_ack_req),
.rst_l (jbus_rst_l),
.clk (jbus_clk)
);
//*******************************************************************************
// DFFRLE Instantiations
//*******************************************************************************
// jbus_clk
dffrle_ns #(40) u_dffrle_jtag_addr_reg
( .din (next_jtag_addr_reg),
.clk (jbus_clk),
.rst_l (jbus_rst_l),
.en (jtag_addr_reg_en),
.q (jtag_addr_reg)
);
dffrle_ns #(64) u_dffrle_jtag_data_reg
( .din (next_jtag_data_reg),
.clk (jbus_clk),
.rst_l (jbus_rst_l),
.en (jtag_data_reg_en),
.q (jtag_data_reg)
);
dffrle_ns #(64) u_dffrle_scratch_reg
( .din (next_scratch_reg),
.rst_l (jbus_rst_l),
.clk (jbus_clk),
.en (scratch_reg_en),
.q (scratch_reg)
);
dffrle_ns #(64) u_dffrle_rdrtrn_reg
( .din (next_rdrtrn_reg),
.rst_l (jbus_rst_l),
.clk (jbus_clk),
.en (rdrtrn_reg_en),
.q (rdrtrn_reg)
);
dffrle_ns #(8) u_dffrle_ramtest_addr_high
( .din (next_ramtest_addr_high),
.clk (jbus_clk),
.rst_l (jbus_rst_l),
.en (ramtest_addr_high_en),
.q (ramtest_addr_high)
);
dffrle_ns #(32) u_dffrle_ramtest_addr_low
( .din (next_ramtest_addr_low),
.clk (jbus_clk),
.rst_l (jbus_rst_l),
.en (ramtest_addr_low_en),
.q (ramtest_addr_low)
);
dffrle_ns #(32) u_dffrle_ramtest_data_high
( .din (next_ramtest_data_high),
.clk (jbus_clk),
.rst_l (jbus_rst_l),
.en (ramtest_data_high_en),
.q (ramtest_data_high)
);
dffrle_ns #(32) u_dffrle_ramtest_data_low
( .din (next_ramtest_data_low),
.clk (jbus_clk),
.rst_l (jbus_rst_l),
.en (ramtest_data_low_en),
.q (ramtest_data_low)
);
dffrle_ns #(1) u_dffrle_ramtest_rw
( .din (next_ramtest_rw),
.clk (jbus_clk),
.rst_l (jbus_rst_l),
.en (ramtest_rw_en),
.q (ramtest_rw)
);
dffrle_ns #(64) u_dffrle_ramtest_rdrtrn
( .din (next_ramtest_rdrtrn),
.clk (jbus_clk),
.rst_l (jbus_rst_l),
.en (ramtest_rdrtrn_en),
.q (ramtest_rdrtrn)
);
dffrle_ns #(`UCB_BUF_HI-`UCB_BUF_LO+1) u_dffrle_csr_buf_id
( .din (next_csr_buf_id),
.clk (jbus_clk),
.rst_l (jbus_rst_l),
.en (csr_buf_id_en),
.q (csr_buf_id)
);
dffrle_ns #(`UCB_THR_HI-`UCB_THR_LO+1) u_dffrle_csr_thr_id
( .din (next_csr_thr_id),
.clk (jbus_clk),
.rst_l (jbus_rst_l),
.en (csr_thr_id_en),
.q (csr_thr_id)
);
//*******************************************************************************
// Rule Checks
//*******************************************************************************
//synopsys translate_off
always @ ( /*AUTOSENSE*/ramtest_rd_pend or rt_valid_negedge) begin
if (ramtest_rd_pend && rt_valid_negedge)
$display ("%d %m: ERROR - new ramtest request received before previous ramtest read has completed",
$time);
end
always @ ( /*AUTOSENSE*/jtag_rd_req or jtag_wr_req) begin
if (jtag_rd_req & jtag_wr_req)
$display ("%d %m: ERROR - concurrent jtag read and write request to IOB",
$time);
end
//synopsys translate_on
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
(** * MoreCoq: More About Coq's Tactics *)
Require Export Poly.
(** This chapter introduces several more proof strategies and
tactics that, together, allow us to prove theorems about the
functional programs we have been writing. In particular, we'll
reason about functions that work with natural numbers and lists.
In particular, we will see:
- how to use auxiliary lemmas, in both forwards and backwards reasoning;
- how to reason about data constructors, which are injective and disjoint;
- how to create a strong induction hypotheses (and when
strengthening is required); and
- how to reason by case analysis.
*)
(* ###################################################### *)
(** * The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n;o] = [n;p] ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with
"[rewrite -> eq2. reflexivity.]" as we have
done several times above. But we can achieve the
same effect in a single step by using the
[apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q;o] = [r;p]) ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
intros H1 H2.
apply H1.
apply H2.
Qed.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
Abort.
(** In this case we can use the [symmetry] tactic, which switches the
left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will perform simplification first. *)
apply H. Qed.
(** **** Exercise: 3 stars (apply_exercise1) *)
(** Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
intros l l' H.
rewrite -> H.
symmetry.
apply rev_involutive.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
[rewrite] changes the goal by [A] = [B].
[apply] change the goal by [A] -> [B].
*)
(** [] *)
(* ###################################################### *)
(** * The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall (X:Type) (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c;d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: [apply trans_eq with [c,d]]. *)
(** **** Exercise: 3 stars, optional (apply_with_exercise) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
intros n m o p.
intros H1 H2.
apply trans_eq with m.
apply H2.
apply H1.
Qed.
(** [] *)
(* ###################################################### *)
(** * The [inversion] tactic *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic called [inversion] that allows us to exploit
these principles in proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n;m] = [o;o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
intros X x y z l j.
intros H1 H2.
inversion H2.
reflexivity.
Qed.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
intros X x y z l j.
intros H1 H2.
inversion H1.
Qed.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication is an instance of a more general fact about
constructors and functions, which we will often find useful: *)
Theorem f_equal : forall (A B : Type) (f: A -> B) (x y: A),
x = y -> f x = f y.
Proof. intros A B f x y eq. rewrite eq. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (practice) *)
(** A couple more nontrivial but not-too-complicated proofs to work
together in class, or for you to work as exercises. *)
Theorem beq_nat_0_l : forall n,
beq_nat 0 n = true -> n = 0.
Proof.
intros n.
intros H.
destruct n.
reflexivity.
inversion H.
Qed.
Theorem beq_nat_0_r : forall n,
beq_nat n 0 = true -> n = 0.
Proof.
intros n.
intros H.
destruct n.
reflexivity.
inversion H.
Qed.
(** [] *)
(* ###################################################### *)
(** * Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars (plus_n_n_injective) *)
(** Practice using "in" variants in this exercise. *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n.
induction n as [| n'].
Case "n = 0".
intros m H.
destruct m.
reflexivity.
inversion H.
Case "n = S n'".
intros m H.
destruct m.
inversion H.
rewrite <- plus_n_Sm in H.
rewrite <- plus_n_Sm in H.
inversion H.
apply IHn' in H1.
apply f_equal.
apply H1.
Qed.
(** [] *)
(* ###################################################### *)
(** * Varying the Induction Hypothesis *)
(** Sometimes it is important to control the exact form of the
induction hypothesis when carrying out inductive proofs in Coq.
In particular, we need to be careful about which of the
assumptions we move (using [intros]) from the goal to the context
before invoking the [induction] tactic. For example, suppose
we want to show that the [double] function is injective -- i.e.,
that it always maps different arguments to different results:
Theorem double_injective: forall n m, double n = double m -> n = m.
The way we _start_ this proof is a little bit delicate: if we
begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'". apply f_equal.
(* Here we are stuck. The induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the goal is not provable. *)
Abort.
(** What went wrong? *)
(** The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context --
intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we know
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.) *)
(** To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for _every_ [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O".
(* The 0 case is trivial *)
inversion eq.
SCase "m = S m'".
apply f_equal.
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
apply IHn'. inversion eq. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** The proof of this theorem (left as an exercise) has to be treated similarly: *)
(** **** Exercise: 2 stars (beq_nat_true) *)
Theorem beq_nat_true : forall n m,
beq_nat n m = true -> n = m.
Proof.
intros n.
induction n as [| n'].
Case "n = 0".
intros m H.
destruct m.
reflexivity.
inversion H.
Case "n = S n'".
intros m H.
destruct m.
inversion H.
simpl in H.
apply IHn' in H.
apply f_equal.
apply H.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (beq_nat_true_informal) *)
(** Give a careful informal proof of [beq_nat_true], being as explicit
as possible about quantifiers. *)
(**
_Proof_: By induction on [n].
- First, suppose [n = 0]. We must show
beq_nat 0 m = true -> 0 = m.
This follows directly from the definition of [beq_nat].
- Next, suppose [n = S n'], where
beq_nat n' m = true -> n = m, forall m.
We must show
beq_nat (S n') m = true -> (S n') = m.
By the definition of [beq_nat], this follows from
beq_nat (S n') (S m') = true -> (S n') = (S m').
By the definition of [beq_nat], this follows from
beq_nat n' m' = true -> n' = m'.
which is immediate from the induction hypothesis. *)
(** [] *)
(** The strategy of doing fewer [intros] before an [induction] doesn't
always work directly; sometimes a little _rearrangement_ of
quantified variables is needed. Suppose, for example, that we
wanted to prove [double_injective] by induction on [m] instead of
[n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
(* Stuck again here, just like before. *)
Abort.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
apply IHm'. inversion eq. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [double n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** Here's another illustration of [inversion] and using an
appropriately general induction hypothesis. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
Case "l = []".
intros n eq. rewrite <- eq. reflexivity.
Case "l = v' :: l'".
intros n eq. simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. apply IHl'. inversion eq. reflexivity. Qed.
(** It might be tempting to start proving the above theorem
by introducing [n] and [eq] at the outset. However, this leads
to an induction hypothesis that is not strong enough. Compare
the above to the following (aborted) attempt: *)
Theorem length_snoc_bad : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l n eq. induction l as [| v' l'].
Case "l = []".
rewrite <- eq. reflexivity.
Case "l = v' :: l'".
simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. Abort. (* apply IHl'. *) (* The IH doesn't apply! *)
(** As in the double examples, the problem is that by
introducing [n] before doing induction on [l], the induction
hypothesis is specialized to one particular natural number, namely
[n]. In the induction case, however, we need to be able to use
the induction hypothesis on some other natural number [n'].
Retaining the more general form of the induction hypothesis thus
gives us more flexibility.
In general, a good rule of thumb is to make the induction hypothesis
as general as possible. *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index n l = None.
Proof.
intros n X l.
generalize dependent n.
induction l as [| v' l'].
Case "l = []".
reflexivity.
Case "l = v' :: l'".
intros n H.
destruct n.
inversion H.
simpl.
apply IHl'.
inversion H.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index n l = None].
_Proof_: By induction on [l].
- First, suppose [l = nil]. We must show
length nil = n -> index n nil = None, forall n.
This follows directly from the definition of [index].
- Next, suppose [l = v' :: l'], where
length l' = n -> index n l' = None, forall n.
We must show
length (v' :: l') = n -> index n (v' :: l') = None.
By the definition of [length], this follows from
length (v' :: l') = S n' -> index (S n') (v' :: l') = None.
By the definition of [index], this follows from
length l' = n' -> index n' l' = None.
which is immediate from the induction hypothesis.
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_more) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
intros n X v l.
generalize dependent n.
induction l as [| v' l'].
Case "l = []".
destruct n.
reflexivity.
intros H.
inversion H.
Case "l = v' :: l'".
intros n H.
destruct n.
inversion H.
simpl.
apply f_equal.
apply IHl'.
inversion H.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]
from [Lists]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
intros X l1 l2 x.
induction l1 as [| v' l'].
Case "l1 = []".
intros n H.
apply H.
Case "l1 = v' :: l'".
intros n H.
destruct n.
inversion H.
apply f_equal.
apply IHl'.
inversion H.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
intros X n l.
generalize dependent n.
induction l as [| v' l'].
Case "l = []".
destruct n.
reflexivity.
intros H.
inversion H.
Case "l = v' :: l'".
intros n H.
destruct n.
inversion H.
simpl.
rewrite <- plus_n_Sm.
apply f_equal.
rewrite <- IHl'.
symmetry.
apply app_length_cons with v'.
reflexivity.
inversion H.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (double_induction) *)
(** Prove the following principle of induction over two naturals. *)
Theorem double_induction: forall (P : nat -> nat -> Prop),
P 0 0 ->
(forall m, P m 0 -> P (S m) 0) ->
(forall n, P 0 n -> P 0 (S n)) ->
(forall m n, P m n -> P (S m) (S n)) ->
forall m n, P m n.
Proof.
intros P H1 H2 H3 H4 m.
induction m as [| m'].
Case "m = O".
induction n as [| n'].
SCase "n = O".
apply H1.
SCase "n = S n'".
apply H3.
apply IHn'.
Case "m = S m'".
induction n as [| n'].
SCase "n = O".
apply H2.
apply IHm'.
SCase "n = S n'".
apply H4.
apply IHm'.
Qed.
(** [] *)
(* ###################################################### *)
(** * Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false". destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity. Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases.
In general, the [destruct] tactic can be used to perform case
analysis of the results of arbitrary computations. If [e] is an
expression whose type is some inductively defined type [T], then,
for each constructor [c] of [T], [destruct e] generates a subgoal
in which all occurrences of [e] (in the goal and in the context)
are replaced by [c].
*)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
intros X x1 x2 k1 k2 f.
unfold override.
destruct (beq_nat k1 k2).
reflexivity.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (combine_split) *)
(** Complete the proof below *)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
intros X Y l.
induction l as [| v' l'].
Case "l = []".
intros l1 l2 H.
inversion H.
reflexivity.
Case "l = v' :: l'".
destruct v'.
intros l1 l2 H.
inversion H.
simpl.
apply f_equal.
destruct (split l') as [l1' l2'].
apply IHl'.
reflexivity.
Qed.
(** [] *)
(** Sometimes, doing a [destruct] on a compound expression (a
non-variable) will erase information we need to complete a proof. *)
(** For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Abort.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep some
memory of this expression and how it was destructed, because we
need to be able to reason that since, in this branch of the case
analysis, [beq_nat n 3 = true], it must be that [n = 3], from
which it follows that [n] is odd.
What we would really like is to substitute away all existing
occurences of [beq_nat n 3], but at the same time add an equation
to the context that records which case we are in. The [eqn:]
qualifier allows us to introduce such an equation (with whatever
name we choose). *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3) eqn:Heqe3.
(* Now we have the same state as at the point where we got stuck
above, except that the context contains an extra equality
assumption, which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_true in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the body of the
function we are reasoning about, we can use [eqn:] again in the
same way, allow us to finish the proof. *)
destruct (beq_nat n 5) eqn:Heqe5.
SCase "e5 = true".
apply beq_nat_true in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (destruct_eqn_practice) *)
Theorem bool_fn_applied_thrice :
forall (f : bool -> bool) (b : bool),
f (f (f b)) = f b.
Proof.
intros f b.
destruct b eqn:H1.
destruct (f true) eqn:H2.
rewrite -> H2.
apply H2.
destruct (f false) eqn:H3.
apply H2.
apply H3.
destruct (f false) eqn:H2.
destruct (f true) eqn:H3.
apply H3.
apply H2.
rewrite -> H2.
apply H2.
Qed.
(** [] *)
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
intros X x1 k1 k2 f.
intros H.
unfold override.
destruct (beq_nat k1 k2) eqn:H1.
apply beq_nat_true in H1.
symmetry.
rewrite <- H1.
apply H.
reflexivity.
Qed.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics. We'll
introduce a few more as we go along through the coming lectures,
and later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [destruct... eqn:...]:
specify the name of an equation to be added to the context,
recording the result of the case analysis
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
- [generalize dependent x]:
move the variable [x] (and anything else that depends on it)
from the context back to an explicit hypothesis in the goal
formula
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (beq_nat_sym) *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
intros n.
induction n as [| n'].
Case "n = 0".
destruct m.
reflexivity.
reflexivity.
Case "n = S n'".
destruct m.
reflexivity.
apply IHn'.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (beq_nat_sym_informal) *)
(** Give an informal proof of this lemma that corresponds to your
formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
_Proof_: By induction on [n].
- First, suppose [n = 0]. We must show
beq_nat 0 m = beq_nat m 0.
This follows directly from the definition of [beq_nat].
- Next, suppose [n = S n'], where
beq_nat n' m = beq_nat m n', forall m.
We must show
beq_nat (S n') m = beq_nat m (S n').
By the definition of [beq_nat], this follows from
beq_nat (S n') (S m') = beq_nat (S m') (S n').
By the definition of [beq_nat], this follows from
beq_nat n' m' = beq_nat m' n'.
which is immediate from the induction hypothesis.
[]
*)
(** **** Exercise: 3 stars, optional (beq_nat_trans) *)
Theorem beq_nat_trans : forall n m p,
beq_nat n m = true ->
beq_nat m p = true ->
beq_nat n p = true.
Proof.
intros n m p.
intros H1 H2.
apply beq_nat_true in H1.
apply beq_nat_true in H2.
rewrite -> H1.
rewrite <- H2.
symmetry.
apply beq_nat_refl.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (split_combine) *)
(** We have just proven that for all lists of pairs, [combine] is the
inverse of [split]. How would you formalize the statement that
[split] is the inverse of [combine]? When is this property true?
Complete the definition of [split_combine_statement] below with a
property that states that [split] is the inverse of
[combine]. Then, prove that the property holds. (Be sure to leave
your induction hypothesis general by not doing [intros] on more
things than necessary. Hint: what property do you need of [l1]
and [l2] for [split] [combine l1 l2 = (l1,l2)] to be true?) *)
Definition split_combine_statement : Prop :=
forall (X : Type) (l1 l2 : list X),
length l1 = length l2 -> split (combine l1 l2) = (l1,l2).
Theorem split_combine : split_combine_statement.
Proof.
induction l1 as [| v' l'].
Case "l1 = []".
destruct l2.
reflexivity.
intros H.
inversion H.
Case "l1 = v' :: l'".
intros l2 H.
destruct l2.
inversion H.
simpl.
rewrite -> IHl'.
reflexivity.
inversion H.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (override_permute) *)
Theorem override_permute : forall (X:Type) x1 x2 k1 k2 k3 (f : nat->X),
beq_nat k2 k1 = false ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
intros X x1 x2 k1 k2 k3 f H.
unfold override.
destruct (beq_nat k1 k3) eqn:H1.
apply beq_nat_true in H1.
rewrite <- H1.
rewrite -> H.
reflexivity.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (filter_exercise) *)
(** This one is a bit challenging. Pay attention to the form of your IH. *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
induction l as [| v' l'].
Case "l = []".
intros lf H.
inversion H.
Case "l = v' :: l'".
intros lf H.
simpl in H.
destruct (test v') eqn:H1.
inversion H.
rewrite <- H2.
apply H1.
apply IHl' in H.
apply H.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (forall_exists_challenge) *)
(** Define two recursive [Fixpoints], [forallb] and [existsb]. The
first checks whether every element in a list satisfies a given
predicate:
forallb oddb [1;3;5;7;9] = true
forallb negb [false;false] = true
forallb evenb [0;2;4;5] = false
forallb (beq_nat 5) [] = true
The second checks whether there exists an element in the list that
satisfies a given predicate:
existsb (beq_nat 5) [0;2;3;6] = false
existsb (andb true) [true;true;false] = true
existsb oddb [1;0;0;0;0;3] = true
existsb evenb [] = false
Next, define a _nonrecursive_ version of [existsb] -- call it
[existsb'] -- using [forallb] and [negb].
Prove theorem [existsb_existsb'] that [existsb'] and [existsb] have
the same behavior.
*)
Fixpoint forallb {X : Type} (f : X -> bool) (l : list X) : bool :=
match l with
| nil => true
| h :: t => if f h then forallb f t else false
end.
Example test_forallb1 : forallb oddb [1;3;5;7;9] = true.
Proof. reflexivity. Qed.
Example test_forallb2 : forallb negb [false;false] = true.
Proof. reflexivity. Qed.
Example test_forallb3 : forallb evenb [0;2;4;5] = false.
Proof. reflexivity. Qed.
Example test_forallb4 : forallb (beq_nat 5) [] = true.
Proof. reflexivity. Qed.
Fixpoint existsb {X : Type} (f : X -> bool) (l : list X) : bool :=
match l with
| nil => false
| h :: t => if f h then true else existsb f t
end.
Example test_existsb1 : existsb (beq_nat 5) [0;2;3;6] = false.
Proof. reflexivity. Qed.
Example test_existsb2 : existsb (andb true) [true;true;false] = true.
Proof. reflexivity. Qed.
Example test_existsb3 : existsb oddb [1;0;0;0;0;3] = true.
Proof. reflexivity. Qed.
Example test_existsb4 : existsb evenb [] = false.
Proof. reflexivity. Qed.
Definition existsb' {X : Type} (f : X -> bool) (l : list X) : bool :=
negb (forallb (fun x => negb (f x)) l).
Theorem existsb_existsb' : forall {X : Type} (f : X -> bool) (l : list X),
existsb f l = existsb' f l.
Proof.
induction l as [| v' l'].
Case "l = []".
reflexivity.
Case "l = v' :: l'".
unfold existsb'.
simpl.
destruct (f v').
reflexivity.
apply IHl'.
Qed.
(** [] *)
(** $Date: 2014-12-31 16:01:37 -0500 (Wed, 31 Dec 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_0_V
`define SKY130_FD_SC_LP__A22OI_0_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22oi_0 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22oi_0 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_0_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22OI_2_V
`define SKY130_FD_SC_MS__A22OI_2_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a22oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a22oi_2 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22OI_2_V
|
(** * More Logic *)
Require Export MyProp.
(* ############################################################ *)
(** * Existential Quantification *)
(** Another critical logical connective is _existential
quantification_. We can express it with the following
definition: *)
Inductive ex (X:Type) (P : X->Prop) : Prop :=
ex_intro : forall (witness:X), P witness -> ex X P.
(** That is, [ex] is a family of propositions indexed by a type [X]
and a property [P] over [X]. In order to give evidence for the
assertion "there exists an [x] for which the property [P] holds"
we must actually name a _witness_ -- a specific value [x] -- and
then give evidence for [P x], i.e., evidence that [x] has the
property [P].
*)
(** *** *)
(** Coq's [Notation] facility can be used to introduce more
familiar notation for writing existentially quantified
propositions, exactly parallel to the built-in syntax for
universally quantified propositions. Instead of writing [ex nat
ev] to express the proposition that there exists some number that
is even, for example, we can write [exists x:nat, ev x]. (It is
not necessary to understand exactly how the [Notation] definition
works.) *)
Notation "'exists' x , p" := (ex _ (fun x => p))
(at level 200, x ident, right associativity) : type_scope.
Notation "'exists' x : X , p" := (ex _ (fun x:X => p))
(at level 200, x ident, right associativity) : type_scope.
(** *** *)
(** We can use the usual set of tactics for
manipulating existentials. For example, to prove an
existential, we can [apply] the constructor [ex_intro]. Since the
premise of [ex_intro] involves a variable ([witness]) that does
not appear in its conclusion, we need to explicitly give its value
when we use [apply]. *)
Example exists_example_1 : exists n, n + (n * n) = 6.
Proof.
apply ex_intro with (witness:=2).
reflexivity. Qed.
(** Note that we have to explicitly give the witness. *)
(** *** *)
(** Or, instead of writing [apply ex_intro with (witness:=e)] all the
time, we can use the convenient shorthand [exists e], which means
the same thing. *)
Example exists_example_1' : exists n, n + (n * n) = 6.
Proof.
exists 2.
reflexivity. Qed.
(** *** *)
(** Conversely, if we have an existential hypothesis in the
context, we can eliminate it with [inversion]. Note the use
of the [as...] pattern to name the variable that Coq
introduces to name the witness value and get evidence that
the hypothesis holds for the witness. (If we don't
explicitly choose one, Coq will just call it [witness], which
makes proofs confusing.) *)
Theorem exists_example_2 : forall n,
(exists m, n = 4 + m) ->
(exists o, n = 2 + o).
Proof.
intros n H.
inversion H as [m Hm].
exists (2 + m).
apply Hm. Qed.
(** Here is another example of how to work with existentials. *)
Lemma exists_example_3 :
exists (n:nat), even n /\ beautiful n.
Proof.
(* WORKED IN CLASS *)
exists 8.
split.
unfold even. simpl. reflexivity.
apply b_sum with (n:=3) (m:=5).
apply b_3. apply b_5.
Qed.
(** **** Exercise: 1 star, optional (english_exists) *)
(** In English, what does the proposition
ex nat (fun n => beautiful (S n))
]]
mean? *)
(* There is at least one n whose successor is a beautiful number
More meaningfully, there is at least one beautiful number above 0 *)
(*
*)
(** **** Exercise: 1 star (dist_not_exists) *)
(** Prove that "[P] holds for all [x]" implies "there is no [x] for
which [P] does not hold." *)
Theorem dist_not_exists : forall (X:Type) (P : X -> Prop),
(forall x, P x) -> ~ (exists x, ~ P x).
Proof. intros. intro. SearchAbout exist. inversion H0. apply H1. apply H. Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (not_exists_dist) *)
(** (The other direction of this theorem requires the classical "law
of the excluded middle".) *)
Theorem not_exists_dist :
excluded_middle ->
forall (X:Type) (P : X -> Prop),
~ (exists x, ~ P x) -> (forall x, P x).
Proof. intros. apply classic_ex_middle in H. unfold classic in H.
firstorder. apply H. unfold not in *. apply H0.
Qed.
(** [] *)
(** **** Exercise: 2 stars (dist_exists_or) *)
(** Prove that existential quantification distributes over
disjunction. *)
Theorem dist_exists_or : forall (X:Type) (P Q : X -> Prop),
(exists x, P x \/ Q x) <-> (exists x, P x) \/ (exists x, Q x).
Proof. split; intros.
Case "->". inversion H. inversion H0; [apply or_introl | apply or_intror];
exists witness; exact H1.
Case "<-". destruct H; inversion H; exists witness.
apply or_introl. exact H0.
apply or_intror. exact H0.
Qed.
(** [] *)
(* ###################################################### *)
(** * Evidence-carrying booleans. *)
(** So far we've seen two different forms of equality predicates:
[eq], which produces a [Prop], and
the type-specific forms, like [beq_nat], that produce [boolean]
values. The former are more convenient to reason about, but
we've relied on the latter to let us use equality tests
in _computations_. While it is straightforward to write lemmas
(e.g. [beq_nat_true] and [beq_nat_false]) that connect the two forms,
using these lemmas quickly gets tedious.
*)
(** *** *)
(**
It turns out that we can get the benefits of both forms at once
by using a construct called [sumbool]. *)
Inductive sumbool (A B : Prop) : Set :=
| left : A -> sumbool A B
| right : B -> sumbool A B.
Notation "{ A } + { B }" := (sumbool A B) : type_scope.
Arguments left {A} {B} a.
Arguments right {A} {B} b.
(** Think of [sumbool] as being like the [boolean] type, but instead
of its values being just [true] and [false], they carry _evidence_
of truth or falsity. This means that when we [destruct] them, we
are left with the relevant evidence as a hypothesis -- just as with [or].
(In fact, the definition of [sumbool] is almost the same as for [or].
The only difference is that values of [sumbool] are declared to be in
[Set] rather than in [Prop]; this is a technical distinction
that allows us to compute with them.) *)
(** *** *)
(** Here's how we can define a [sumbool] for equality on [nat]s *)
Theorem eq_nat_dec : forall n m : nat, {n = m} + {n <> m}.
Proof.
(* WORKED IN CLASS *)
intros n.
induction n as [|n'].
Case "n = 0".
intros m.
destruct m as [|m'].
SCase "m = 0".
left. reflexivity.
SCase "m = S m'".
right. intros contra. inversion contra.
Case "n = S n'".
intros m.
destruct m as [|m'].
SCase "m = 0".
right. intros contra. inversion contra.
SCase "m = S m'".
destruct IHn' with (m := m') as [eq | neq].
left. apply f_equal. apply eq.
right. intros Heq. inversion Heq as [Heq']. apply neq. apply Heq'.
Defined.
(** Read as a theorem, this says that equality on [nat]s is decidable:
that is, given two [nat] values, we can always produce either
evidence that they are equal or evidence that they are not.
Read computationally, [eq_nat_dec] takes two [nat] values and returns
a [sumbool] constructed with [left] if they are equal and [right]
if they are not; this result can be tested with a [match] or, better,
with an [if-then-else], just like a regular [boolean].
(Notice that we ended this proof with [Defined] rather than [Qed].
The only difference this makes is that the proof becomes _transparent_,
meaning that its definition is available when Coq tries to do reductions,
which is important for the computational interpretation.)
*)
(** *** *)
(**
Here's a simple example illustrating the advantages of the [sumbool] form. *)
Definition override' {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if eq_nat_dec k k' then x else f k'.
Theorem override_same' : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override' f k1 x1) k2 = f k2.
Proof.
intros X x1 k1 k2 f. intros Hx1.
unfold override'.
destruct (eq_nat_dec k1 k2). (* observe what appears as a hypothesis *)
Case "k1 = k2".
rewrite <- e.
symmetry. apply Hx1.
Case "k1 <> k2".
reflexivity. Qed.
(** Compare this to the more laborious proof (in MoreCoq.v) for the
version of [override] defined using [beq_nat], where we had to
use the auxiliary lemma [beq_nat_true] to convert a fact about booleans
to a Prop. *)
(** **** Exercise: 1 star (override_shadow') *)
Theorem override_shadow' : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override' (override' f k1 x2) k1 x1) k2 = (override' f k1 x1) k2.
Proof. intros. unfold override'. destruct (eq_nat_dec k1 k2); reflexivity. Qed.
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (all_forallb) *)
(** Inductively define a property [all] of lists, parameterized by a
type [X] and a property [P : X -> Prop], such that [all X P l]
asserts that [P] is true for every element of the list [l]. *)
Inductive all (X : Type) (P : X -> Prop) : list X -> Prop :=
| allnil : all X P []
| allcons : forall x xs, P x -> all X P xs -> all X P (x :: xs).
Arguments all {X} P xs.
Arguments allnil {X} {P}.
Arguments allcons {X} {P} {x} {xs} px pxs.
(** Recall the function [forallb], from the exercise
[forall_exists_challenge] in chapter [Poly]: *)
Fixpoint forallb {X : Type} (test : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| x :: l' => andb (test x) (forallb test l')
end.
(** Using the property [all], write down a specification for [forallb],
and prove that it satisfies the specification. Try to make your
specification as precise as possible.
Are there any important properties of the function [forallb] which
are not captured by your specification? *)
Theorem forallb_all : forall X (pred : X -> Prop)
(test : forall x, {pred x} + {~ (pred x)})
(l : list X),
{all pred l} + {~ (all pred l)}.
Proof. intros. induction l as [|y ys].
Case "l = []". left. apply allnil.
Case "l = y :: ys". destruct IHys.
SCase "IHxs : all test ys". destruct (test y) eqn:ty.
SSCase "test y = true". left. apply allcons. exact p. exact a.
SSCase "test y = false".
right. intro. inversion H. destruct n. exact H2.
SCase "IHxs : ~ all test ys". right. intro. inversion H.
apply n. apply H3.
Defined.
Arguments forallb_all {X} {pred} test l.
Eval compute in forallb_all (eq_nat_dec 10) [10; 10; 10; 10].
(** [] *)
(** **** Exercise: 4 stars, advanced (filter_challenge) *)
(** One of the main purposes of Coq is to prove that programs match
their specifications. To this end, let's prove that our
definition of [filter] matches a specification. Here is the
specification, written out informally in English.
Suppose we have a set [X], a function [test: X->bool], and a list
[l] of type [list X]. Suppose further that [l] is an "in-order
merge" of two lists, [l1] and [l2], such that every item in [l1]
satisfies [test] and no item in [l2] satisfies test. Then [filter
test l = l1].
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[1,4,6,2,3]
is an in-order merge of
[1,6,2]
and
[4,3].
Your job is to translate this specification into a Coq theorem and
prove it. (Hint: You'll need to begin by defining what it means
for one list to be a merge of two others. Do this with an
inductive relation, not a [Fixpoint].) *)
Theorem filter_spec : forall (t : nat -> bool) (l : list nat),
all (fun x => t x = true) (filter t l) /\ subseq (filter t l) l.
Proof. split; intros.
Case "p1". induction l as [|y ys]; simpl.
SCase "l = []". apply allnil.
SCase "l = y :: ys". destruct (t y) eqn:ty.
SSCase "t y = true". apply allcons. exact ty. apply IHys.
SSCase "t y = false". apply IHys.
Case "p2". induction l as [|y ys]; simpl.
SCase "l = []". apply sub_refl.
SCase "l = y :: ys". destruct (t y) eqn:ty.
SSCase "t y = true". apply sub_cons2. apply IHys.
SSCase "t y = false". apply sub_cons1. apply IHys.
Qed.
(* I'd generalize it, but subseq is specific to nats right now *)
(* on pain of really weird inversions *)
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (filter_challenge_2) *)
(** A different way to formally characterize the behavior of [filter]
goes like this: Among all subsequences of [l] with the property
that [test] evaluates to [true] on all their members, [filter test
l] is the longest. Express this claim formally and prove it. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, advanced (no_repeats) *)
(** The following inductively defined proposition... *)
Inductive appears_in {X:Type} (a:X) : list X -> Prop :=
| ai_here : forall l, appears_in a (a::l)
| ai_later : forall b l, appears_in a l -> appears_in a (b::l).
(** ...gives us a precise way of saying that a value [a] appears at
least once as a member of a list [l].
Here's a pair of warm-ups about [appears_in].
*)
Lemma app_nil_r : forall X (xs : list X), xs ++ [] = xs.
Proof. induction xs. reflexivity. simpl. rewrite IHxs. reflexivity. Qed.
Lemma appears_in_app : forall (X:Type) (xs ys : list X) (x:X),
appears_in x (xs ++ ys) -> appears_in x xs \/ appears_in x ys.
Proof. induction xs as [|x' xs']; intros; simpl in *.
Case "xs = []". right. apply H.
Case "xs = x' :: xs'". inversion H; subst.
SCase "H : ai_here x (x :: xs ++ ys)". left. apply ai_here.
SCase "H : ai_later x' (xs ++ ys)". apply IHxs' in H1. destruct H1.
SSCase "H0 : right (appears_in x xs)". left. apply ai_later. apply H0.
SSCase "H0 : appears_in x ys". right. apply H0.
Qed.
Lemma app_appears_in : forall (X:Type) (xs ys : list X) (x:X),
appears_in x xs \/ appears_in x ys -> appears_in x (xs ++ ys).
Proof. induction xs as [|x' xs']; intros.
Case "xs = []". destruct H.
SCase "H : appears_in x []". inversion H.
SCase "H : appears_in x ys". apply H.
Case "xs = x' :: xs'". destruct H; simpl.
SCase "H : appears_in x (x' :: xs')". inversion H; subst.
SSCase "H : appears_in x' (x' :: xs')". apply ai_here.
SSCase "H : ai_later x' (appears_in x xs')".
simpl. apply ai_later. apply IHxs'. left. apply H1.
SCase "H : appears_in x ys".
apply ai_later. apply IHxs'. right. apply H.
Qed.
(** Now use [appears_in] to define a proposition [disjoint X l1 l2],
which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in common. *)
Definition disjoint : forall X, list X -> list X -> Prop := fun X xs ys =>
all (fun x => ~ (appears_in x ys)) xs \/ all (fun y => ~ (appears_in y xs)) ys.
Arguments disjoint {X} xs ys.
(** Next, use [appears_in] to define an inductive proposition
[no_repeats X l], which should be provable exactly when [l] is a
list (with elements of type [X]) where every member is different
from every other. For example, [no_repeats nat [1,2,3,4]] and
[no_repeats bool []] should be provable, while [no_repeats nat
[1,2,1]] and [no_repeats bool [true,true]] should not be. *)
(** Finally, state and prove one or more interesting theorems relating
[disjoint], [no_repeats] and [++] (list append). *)
Inductive no_repeats (X : Type) : list X -> Prop :=
| norepnil : no_repeats X []
| norepcons : forall (x : X) (xs : list X),
no_repeats X xs -> ~ (appears_in x xs) ->
no_repeats X (x :: xs).
Arguments no_repeats {X} xs.
Arguments norepcons {X} {x} {xs} p1 p2.
Arguments norepnil {X}.
Definition Decideable1 {X : Type} (P : X -> Prop) : Type :=
forall x, {P x} + {~ (P x)}.
Definition Decideable2 {X Y : Type} (P : X -> Y -> Prop) : Type :=
forall x y, {P x y} + {~ (P x y)}.
Theorem appears_in_proc : forall X (f : forall (x y : X), {x = y} + {x <> y})
(x : X) (l : list X),
{appears_in x l} + {~ appears_in x l}.
Proof. intros. induction l as [|y ys].
Case "l = []". right. intro. inversion H.
Case "l = x' :: xs". destruct IHys as [IHys|IHys].
SCase "IHys : appears_in x ys". left. apply ai_later. apply IHys.
SCase "IHys : ~ appears_in x ys". destruct (f x y).
SSCase "x = y". left. rewrite e. apply ai_here.
SSCase "x <> y". right. intro. inversion H; contradiction.
Defined.
Arguments appears_in_proc {X} f x l.
Theorem dup_no_repeats : forall X (x : X) (l : list X), ~ (no_repeats (x :: x :: l)).
Proof. intros. intro. inversion H. apply H3. apply ai_here. Qed.
Theorem no_repeats_proc : forall X (f : forall (x y : X), {x = y} + {x <> y}),
Decideable1 (@no_repeats X).
Proof. unfold Decideable1. intros X f l. induction l as [|x xs].
Case "l = []". left. apply norepnil.
Case "l = x :: xs". destruct xs as [|y ys].
SCase "xs = []".
left. apply norepcons. apply norepnil. intro. inversion H; subst.
SCase "xs = y :: ys". destruct IHxs as [IHxs | IHxs].
SSCase "IHxs : no_repeats (y :: ys)". destruct (f x y).
SSSCase "x = y". right. rewrite e. apply dup_no_repeats.
SSSCase "x <> y". destruct (appears_in_proc f x ys).
SSSSCase "appears_in x ys". right. intro. inversion H; subst.
apply H3. apply ai_later. apply a.
SSSSCase "~ appears_in x ys". left.
apply norepcons. apply IHxs. intro. inversion H. contradiction n.
apply n0. apply H1.
SSCase "IHxs : ~ no_repeats (y :: ys)". right. intro. destruct (f x y).
SSSCase "x = y". inversion H; subst. apply H3. apply ai_here.
SSSCase "x <> y". inversion H; subst. destruct (appears_in_proc f x ys).
apply H3. apply ai_later. apply a.
apply IHxs. apply H2.
Defined.
Arguments no_repeats_proc {X} f x.
(** [] *)
(** **** Exercise: 3 stars (nostutter) *)
(** Formulating inductive definitions of predicates is an important
skill you'll need in this course. Try to solve this exercise
without any help at all (except from your study group partner, if
you have one).
We say that a list of numbers "stutters" if it repeats the same
number consecutively. The predicate "[nostutter mylist]" means
that [mylist] does not stutter. Formulate an inductive definition
for [nostutter]. (This is different from the [no_repeats]
predicate in the exercise above; the sequence [1,4,1] repeats but
does not stutter.) *)
Inductive nostutter: list nat -> Prop :=
| nostutnil : nostutter []
| nostutcons : forall n xs, Some n <> hd_opt xs -> nostutter xs -> nostutter (n :: xs).
Arguments nostutcons {n} {xs} p1 p2.
(** Make sure each of these tests succeeds, but you are free
to change the proof if the given one doesn't work for you.
Your definition might be different from mine and still correct,
in which case the examples might need a different proof.
The suggested proofs for the examples (in comments) use a number
of tactics we haven't talked about, to try to make them robust
with respect to different possible ways of defining [nostutter].
You should be able to just uncomment and use them as-is, but if
you prefer you can also prove each example with more basic
tactics. *)
Example test_nostutter_1: nostutter [3;1;4;1;5;6].
Proof. repeat constructor; simplify_eq. Qed.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_2: nostutter [].
Proof. repeat constructor; simplify_eq. Qed.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_3: nostutter [5].
Proof. repeat constructor; simplify_eq. Qed.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_4: not (nostutter [3;1;1;4]).
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto.
Qed.
(*
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto. Qed.
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (pigeonhole principle) *)
(** The "pigeonhole principle" states a basic fact about counting:
if you distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As is often the case,
this apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** First a pair of useful lemmas (we already proved these for lists
of naturals, but not for arbitrary lists). *)
Lemma app_length : forall (X:Type) (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof. induction l1; simpl in *; intros.
reflexivity. rewrite IHl1. reflexivity.
Qed.
Lemma appears_in_app_split : forall (X:Type) (x:X) (l:list X),
appears_in x l ->
exists l1, exists l2, l = l1 ++ (x::l2).
Proof. intros X x l; generalize dependent x; induction l as [|y ys];
intros; inversion H; subst.
exists []. exists ys. reflexivity.
apply IHys in H1. inversion H1. inversion H0.
exists (y :: witness). exists witness0. simpl. rewrite H2. reflexivity.
Qed.
(** Now define a predicate [repeats] (analogous to [no_repeats] in the
exercise above), such that [repeats X l] asserts that [l] contains
at least one repeated element (of type [X]). *)
Inductive repeats {X:Type} : list X -> Prop :=
| rephere : forall x xs, appears_in x xs -> repeats (x :: xs)
| replater : forall x xs, repeats xs -> repeats (x :: xs).
(** Now here's a way to formalize the pigeonhole principle. List [l2]
represents a list of pigeonhole labels, and list [l1] represents
the labels assigned to a list of items: if there are more items
than labels, at least two items must have the same label. This
proof is much easier if you use the [excluded_middle] hypothesis
to show that [appears_in] is decidable, i.e. [forall x
l, (appears_in x l) \/ ~ (appears_in x l)]. However, it is also
possible to make the proof go through _without_ assuming that
[appears_in] is decidable; if you can manage to do this, you will
not need the [excluded_middle] hypothesis. *)
Lemma len0_nil {X : Type} : forall (l : list X), length l = 0 <-> l = [].
Proof. split; intros; destruct l; inversion H; firstorder. Qed.
Definition dec_eq (X : Type) : Type := forall x y : X, {x = y} + {x <> y}.
Lemma apr_uncons : forall X (a b : X) l, appears_in a (b :: l) ->
a <> b -> appears_in a l.
Proof. intros. induction l; inversion H; subst.
contradiction H0. contradiction H0. reflexivity. inversion H2.
apply ai_later. apply IHl. apply ai_here. apply H2.
Qed.
Lemma appear_remove_redundant : forall X (a b : X) l1 l2,
dec_eq X ->
a <> b ->
appears_in a (l1 ++ b :: l2) ->
appears_in a (l1 ++ l2).
Proof. induction l1; intros; simpl in *.
apply apr_uncons in H0. apply H0. apply H.
destruct (X0 a x); subst. apply ai_here.
apply ai_later. apply IHl1. apply X0. apply H.
apply apr_uncons with (b := x). apply H0. apply n.
Qed.
Theorem Pigeonhole_Principle: forall (X : Type) (l1 l2 : list X)
(f : dec_eq X),
(forall x, appears_in x l1 -> appears_in x l2) ->
length l2 < length l1 ->
repeats l1.
Proof. unfold excluded_middle, lt, dec_eq.
induction l1 as [|y ys].
Case "l1 = []". intros l2 f H Hlen. inversion Hlen.
Case "l1 = y :: ys". intros l2 f H Hlen.
assert (Decideable2 (@appears_in X)). unfold Decideable2.
apply appears_in_proc. apply f.
unfold Decideable2 in *.
destruct (X0 y ys).
apply rephere. apply a.
apply replater. assert (Hl2: exists pre, exists post, l2 = pre ++ y :: post).
apply appears_in_app_split. apply H. apply ai_here.
inversion Hl2. inversion H0.
apply (IHys (witness ++ witness0)).
apply f. intros. destruct (f x y).
apply ex_falso_quodlibet. apply n. subst. apply H2.
subst. firstorder. clear H1.
apply appear_remove_redundant with (b := y).
unfold dec_eq. apply f.
apply n0. apply H. apply ai_later. apply H2.
rewrite <- app_length_cons with (x := y); subst.
inversion Hlen; firstorder; subst.
Qed.
(** [] *)
(* $Date: 2014-02-22 09:43:41 -0500 (Sat, 22 Feb 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_1_V
`define SKY130_FD_SC_LS__DLRBP_1_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$PR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4BB_4_V
`define SKY130_FD_SC_MS__OR4BB_4_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4bb_4 (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4bb_4 (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4BB_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUF_PP_SYMBOL_V
`define SKY130_FD_SC_LP__LSBUF_PP_SYMBOL_V
/**
* lsbuf: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input DESTPWR,
input DESTVPB,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUF_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32OI_TB_V
`define SKY130_FD_SC_HDLL__A32OI_TB_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a32oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hdll__a32oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32OI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_G_TB_V
`define SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_G_TB_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_pwrgood_pp_g.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 UDP_IN = 1'b1;
#80 VGND = 1'b1;
#100 UDP_IN = 1'b0;
#120 VGND = 1'b0;
#140 VGND = 1'b1;
#160 UDP_IN = 1'b1;
#180 VGND = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_hvl__udp_pwrgood_pp$G dut (.UDP_IN(UDP_IN), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_G_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BO_4_V
`define SKY130_FD_SC_LS__A21BO_4_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BO_4_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Mar 28 05:22:50 2017
// Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/sidxb/FPGA/ee2020/ee2020.runs/dds_compiler_0_synth_1/dds_compiler_0_sim_netlist.v
// Design : dds_compiler_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "dds_compiler_0,dds_compiler_v6_0_13,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "dds_compiler_v6_0_13,Vivado 2016.4" *)
(* NotValidForBitStream *)
module dds_compiler_0
(aclk,
s_axis_phase_tvalid,
s_axis_phase_tdata,
m_axis_data_tvalid,
m_axis_data_tdata);
(* x_interface_info = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) input aclk;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TVALID" *) input s_axis_phase_tvalid;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TDATA" *) input [23:0]s_axis_phase_tdata;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID" *) output m_axis_data_tvalid;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA" *) output [15:0]m_axis_data_tdata;
wire aclk;
wire [15:0]m_axis_data_tdata;
wire m_axis_data_tvalid;
wire [23:0]s_axis_phase_tdata;
wire s_axis_phase_tvalid;
wire NLW_U0_debug_axi_resync_in_UNCONNECTED;
wire NLW_U0_debug_core_nd_UNCONNECTED;
wire NLW_U0_debug_phase_nd_UNCONNECTED;
wire NLW_U0_event_phase_in_invalid_UNCONNECTED;
wire NLW_U0_event_pinc_invalid_UNCONNECTED;
wire NLW_U0_event_poff_invalid_UNCONNECTED;
wire NLW_U0_event_s_config_tlast_missing_UNCONNECTED;
wire NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED;
wire NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED;
wire NLW_U0_event_s_phase_tlast_missing_UNCONNECTED;
wire NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED;
wire NLW_U0_m_axis_data_tlast_UNCONNECTED;
wire NLW_U0_m_axis_phase_tlast_UNCONNECTED;
wire NLW_U0_m_axis_phase_tvalid_UNCONNECTED;
wire NLW_U0_s_axis_config_tready_UNCONNECTED;
wire NLW_U0_s_axis_phase_tready_UNCONNECTED;
wire [0:0]NLW_U0_debug_axi_chan_in_UNCONNECTED;
wire [21:0]NLW_U0_debug_axi_pinc_in_UNCONNECTED;
wire [21:0]NLW_U0_debug_axi_poff_in_UNCONNECTED;
wire [21:0]NLW_U0_debug_phase_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_data_tuser_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_phase_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_phase_tuser_UNCONNECTED;
(* C_ACCUMULATOR_WIDTH = "22" *)
(* C_AMPLITUDE = "1" *)
(* C_CHANNELS = "1" *)
(* C_CHAN_WIDTH = "1" *)
(* C_DEBUG_INTERFACE = "0" *)
(* C_HAS_ACLKEN = "0" *)
(* C_HAS_ARESETN = "0" *)
(* C_HAS_M_DATA = "1" *)
(* C_HAS_M_PHASE = "0" *)
(* C_HAS_PHASEGEN = "1" *)
(* C_HAS_PHASE_OUT = "0" *)
(* C_HAS_SINCOS = "1" *)
(* C_HAS_S_CONFIG = "0" *)
(* C_HAS_S_PHASE = "1" *)
(* C_HAS_TLAST = "0" *)
(* C_HAS_TREADY = "0" *)
(* C_LATENCY = "8" *)
(* C_MEM_TYPE = "1" *)
(* C_MODE_OF_OPERATION = "0" *)
(* C_MODULUS = "10000" *)
(* C_M_DATA_HAS_TUSER = "0" *)
(* C_M_DATA_TDATA_WIDTH = "16" *)
(* C_M_DATA_TUSER_WIDTH = "1" *)
(* C_M_PHASE_HAS_TUSER = "0" *)
(* C_M_PHASE_TDATA_WIDTH = "1" *)
(* C_M_PHASE_TUSER_WIDTH = "1" *)
(* C_NEGATIVE_COSINE = "0" *)
(* C_NEGATIVE_SINE = "0" *)
(* C_NOISE_SHAPING = "0" *)
(* C_OPTIMISE_GOAL = "1" *)
(* C_OUTPUTS_REQUIRED = "0" *)
(* C_OUTPUT_FORM = "0" *)
(* C_OUTPUT_WIDTH = "12" *)
(* C_PHASE_ANGLE_WIDTH = "12" *)
(* C_PHASE_INCREMENT = "3" *)
(* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_PHASE_OFFSET = "0" *)
(* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_POR_MODE = "0" *)
(* C_RESYNC = "0" *)
(* C_S_CONFIG_SYNC_MODE = "0" *)
(* C_S_CONFIG_TDATA_WIDTH = "1" *)
(* C_S_PHASE_HAS_TUSER = "0" *)
(* C_S_PHASE_TDATA_WIDTH = "24" *)
(* C_S_PHASE_TUSER_WIDTH = "1" *)
(* C_USE_DSP48 = "0" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
dds_compiler_0_dds_compiler_v6_0_13 U0
(.aclk(aclk),
.aclken(1'b1),
.aresetn(1'b1),
.debug_axi_chan_in(NLW_U0_debug_axi_chan_in_UNCONNECTED[0]),
.debug_axi_pinc_in(NLW_U0_debug_axi_pinc_in_UNCONNECTED[21:0]),
.debug_axi_poff_in(NLW_U0_debug_axi_poff_in_UNCONNECTED[21:0]),
.debug_axi_resync_in(NLW_U0_debug_axi_resync_in_UNCONNECTED),
.debug_core_nd(NLW_U0_debug_core_nd_UNCONNECTED),
.debug_phase(NLW_U0_debug_phase_UNCONNECTED[21:0]),
.debug_phase_nd(NLW_U0_debug_phase_nd_UNCONNECTED),
.event_phase_in_invalid(NLW_U0_event_phase_in_invalid_UNCONNECTED),
.event_pinc_invalid(NLW_U0_event_pinc_invalid_UNCONNECTED),
.event_poff_invalid(NLW_U0_event_poff_invalid_UNCONNECTED),
.event_s_config_tlast_missing(NLW_U0_event_s_config_tlast_missing_UNCONNECTED),
.event_s_config_tlast_unexpected(NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED),
.event_s_phase_chanid_incorrect(NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED),
.event_s_phase_tlast_missing(NLW_U0_event_s_phase_tlast_missing_UNCONNECTED),
.event_s_phase_tlast_unexpected(NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tlast(NLW_U0_m_axis_data_tlast_UNCONNECTED),
.m_axis_data_tready(1'b0),
.m_axis_data_tuser(NLW_U0_m_axis_data_tuser_UNCONNECTED[0]),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_phase_tdata(NLW_U0_m_axis_phase_tdata_UNCONNECTED[0]),
.m_axis_phase_tlast(NLW_U0_m_axis_phase_tlast_UNCONNECTED),
.m_axis_phase_tready(1'b0),
.m_axis_phase_tuser(NLW_U0_m_axis_phase_tuser_UNCONNECTED[0]),
.m_axis_phase_tvalid(NLW_U0_m_axis_phase_tvalid_UNCONNECTED),
.s_axis_config_tdata(1'b0),
.s_axis_config_tlast(1'b0),
.s_axis_config_tready(NLW_U0_s_axis_config_tready_UNCONNECTED),
.s_axis_config_tvalid(1'b0),
.s_axis_phase_tdata(s_axis_phase_tdata),
.s_axis_phase_tlast(1'b0),
.s_axis_phase_tready(NLW_U0_s_axis_phase_tready_UNCONNECTED),
.s_axis_phase_tuser(1'b0),
.s_axis_phase_tvalid(s_axis_phase_tvalid));
endmodule
(* C_ACCUMULATOR_WIDTH = "22" *) (* C_AMPLITUDE = "1" *) (* C_CHANNELS = "1" *)
(* C_CHAN_WIDTH = "1" *) (* C_DEBUG_INTERFACE = "0" *) (* C_HAS_ACLKEN = "0" *)
(* C_HAS_ARESETN = "0" *) (* C_HAS_M_DATA = "1" *) (* C_HAS_M_PHASE = "0" *)
(* C_HAS_PHASEGEN = "1" *) (* C_HAS_PHASE_OUT = "0" *) (* C_HAS_SINCOS = "1" *)
(* C_HAS_S_CONFIG = "0" *) (* C_HAS_S_PHASE = "1" *) (* C_HAS_TLAST = "0" *)
(* C_HAS_TREADY = "0" *) (* C_LATENCY = "8" *) (* C_MEM_TYPE = "1" *)
(* C_MODE_OF_OPERATION = "0" *) (* C_MODULUS = "10000" *) (* C_M_DATA_HAS_TUSER = "0" *)
(* C_M_DATA_TDATA_WIDTH = "16" *) (* C_M_DATA_TUSER_WIDTH = "1" *) (* C_M_PHASE_HAS_TUSER = "0" *)
(* C_M_PHASE_TDATA_WIDTH = "1" *) (* C_M_PHASE_TUSER_WIDTH = "1" *) (* C_NEGATIVE_COSINE = "0" *)
(* C_NEGATIVE_SINE = "0" *) (* C_NOISE_SHAPING = "0" *) (* C_OPTIMISE_GOAL = "1" *)
(* C_OUTPUTS_REQUIRED = "0" *) (* C_OUTPUT_FORM = "0" *) (* C_OUTPUT_WIDTH = "12" *)
(* C_PHASE_ANGLE_WIDTH = "12" *) (* C_PHASE_INCREMENT = "3" *) (* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_PHASE_OFFSET = "0" *) (* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) (* C_POR_MODE = "0" *)
(* C_RESYNC = "0" *) (* C_S_CONFIG_SYNC_MODE = "0" *) (* C_S_CONFIG_TDATA_WIDTH = "1" *)
(* C_S_PHASE_HAS_TUSER = "0" *) (* C_S_PHASE_TDATA_WIDTH = "24" *) (* C_S_PHASE_TUSER_WIDTH = "1" *)
(* C_USE_DSP48 = "0" *) (* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "dds_compiler_v6_0_13" *)
(* downgradeipidentifiedwarnings = "yes" *)
module dds_compiler_0_dds_compiler_v6_0_13
(aclk,
aclken,
aresetn,
s_axis_phase_tvalid,
s_axis_phase_tready,
s_axis_phase_tdata,
s_axis_phase_tlast,
s_axis_phase_tuser,
s_axis_config_tvalid,
s_axis_config_tready,
s_axis_config_tdata,
s_axis_config_tlast,
m_axis_data_tvalid,
m_axis_data_tready,
m_axis_data_tdata,
m_axis_data_tlast,
m_axis_data_tuser,
m_axis_phase_tvalid,
m_axis_phase_tready,
m_axis_phase_tdata,
m_axis_phase_tlast,
m_axis_phase_tuser,
event_pinc_invalid,
event_poff_invalid,
event_phase_in_invalid,
event_s_phase_tlast_missing,
event_s_phase_tlast_unexpected,
event_s_phase_chanid_incorrect,
event_s_config_tlast_missing,
event_s_config_tlast_unexpected,
debug_axi_pinc_in,
debug_axi_poff_in,
debug_axi_resync_in,
debug_axi_chan_in,
debug_core_nd,
debug_phase,
debug_phase_nd);
input aclk;
input aclken;
input aresetn;
input s_axis_phase_tvalid;
output s_axis_phase_tready;
input [23:0]s_axis_phase_tdata;
input s_axis_phase_tlast;
input [0:0]s_axis_phase_tuser;
input s_axis_config_tvalid;
output s_axis_config_tready;
input [0:0]s_axis_config_tdata;
input s_axis_config_tlast;
output m_axis_data_tvalid;
input m_axis_data_tready;
output [15:0]m_axis_data_tdata;
output m_axis_data_tlast;
output [0:0]m_axis_data_tuser;
output m_axis_phase_tvalid;
input m_axis_phase_tready;
output [0:0]m_axis_phase_tdata;
output m_axis_phase_tlast;
output [0:0]m_axis_phase_tuser;
output event_pinc_invalid;
output event_poff_invalid;
output event_phase_in_invalid;
output event_s_phase_tlast_missing;
output event_s_phase_tlast_unexpected;
output event_s_phase_chanid_incorrect;
output event_s_config_tlast_missing;
output event_s_config_tlast_unexpected;
output [21:0]debug_axi_pinc_in;
output [21:0]debug_axi_poff_in;
output debug_axi_resync_in;
output [0:0]debug_axi_chan_in;
output debug_core_nd;
output [21:0]debug_phase;
output debug_phase_nd;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire event_s_phase_tlast_missing;
wire [11:0]\^m_axis_data_tdata ;
wire m_axis_data_tvalid;
wire [23:0]s_axis_phase_tdata;
wire s_axis_phase_tvalid;
wire NLW_i_synth_debug_axi_resync_in_UNCONNECTED;
wire NLW_i_synth_debug_core_nd_UNCONNECTED;
wire NLW_i_synth_debug_phase_nd_UNCONNECTED;
wire NLW_i_synth_event_phase_in_invalid_UNCONNECTED;
wire NLW_i_synth_event_pinc_invalid_UNCONNECTED;
wire NLW_i_synth_event_poff_invalid_UNCONNECTED;
wire NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED;
wire NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED;
wire NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED;
wire NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED;
wire NLW_i_synth_m_axis_data_tlast_UNCONNECTED;
wire NLW_i_synth_m_axis_phase_tlast_UNCONNECTED;
wire NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED;
wire NLW_i_synth_s_axis_config_tready_UNCONNECTED;
wire NLW_i_synth_s_axis_phase_tready_UNCONNECTED;
wire [0:0]NLW_i_synth_debug_axi_chan_in_UNCONNECTED;
wire [21:0]NLW_i_synth_debug_axi_pinc_in_UNCONNECTED;
wire [21:0]NLW_i_synth_debug_axi_poff_in_UNCONNECTED;
wire [21:0]NLW_i_synth_debug_phase_UNCONNECTED;
wire [14:11]NLW_i_synth_m_axis_data_tdata_UNCONNECTED;
wire [0:0]NLW_i_synth_m_axis_data_tuser_UNCONNECTED;
wire [0:0]NLW_i_synth_m_axis_phase_tdata_UNCONNECTED;
wire [0:0]NLW_i_synth_m_axis_phase_tuser_UNCONNECTED;
assign debug_axi_chan_in[0] = \<const0> ;
assign debug_axi_pinc_in[21] = \<const0> ;
assign debug_axi_pinc_in[20] = \<const0> ;
assign debug_axi_pinc_in[19] = \<const0> ;
assign debug_axi_pinc_in[18] = \<const0> ;
assign debug_axi_pinc_in[17] = \<const0> ;
assign debug_axi_pinc_in[16] = \<const0> ;
assign debug_axi_pinc_in[15] = \<const0> ;
assign debug_axi_pinc_in[14] = \<const0> ;
assign debug_axi_pinc_in[13] = \<const0> ;
assign debug_axi_pinc_in[12] = \<const0> ;
assign debug_axi_pinc_in[11] = \<const0> ;
assign debug_axi_pinc_in[10] = \<const0> ;
assign debug_axi_pinc_in[9] = \<const0> ;
assign debug_axi_pinc_in[8] = \<const0> ;
assign debug_axi_pinc_in[7] = \<const0> ;
assign debug_axi_pinc_in[6] = \<const0> ;
assign debug_axi_pinc_in[5] = \<const0> ;
assign debug_axi_pinc_in[4] = \<const0> ;
assign debug_axi_pinc_in[3] = \<const0> ;
assign debug_axi_pinc_in[2] = \<const0> ;
assign debug_axi_pinc_in[1] = \<const0> ;
assign debug_axi_pinc_in[0] = \<const0> ;
assign debug_axi_poff_in[21] = \<const0> ;
assign debug_axi_poff_in[20] = \<const0> ;
assign debug_axi_poff_in[19] = \<const0> ;
assign debug_axi_poff_in[18] = \<const0> ;
assign debug_axi_poff_in[17] = \<const0> ;
assign debug_axi_poff_in[16] = \<const0> ;
assign debug_axi_poff_in[15] = \<const0> ;
assign debug_axi_poff_in[14] = \<const0> ;
assign debug_axi_poff_in[13] = \<const0> ;
assign debug_axi_poff_in[12] = \<const0> ;
assign debug_axi_poff_in[11] = \<const0> ;
assign debug_axi_poff_in[10] = \<const0> ;
assign debug_axi_poff_in[9] = \<const0> ;
assign debug_axi_poff_in[8] = \<const0> ;
assign debug_axi_poff_in[7] = \<const0> ;
assign debug_axi_poff_in[6] = \<const0> ;
assign debug_axi_poff_in[5] = \<const0> ;
assign debug_axi_poff_in[4] = \<const0> ;
assign debug_axi_poff_in[3] = \<const0> ;
assign debug_axi_poff_in[2] = \<const0> ;
assign debug_axi_poff_in[1] = \<const0> ;
assign debug_axi_poff_in[0] = \<const0> ;
assign debug_axi_resync_in = \<const0> ;
assign debug_core_nd = \<const0> ;
assign debug_phase[21] = \<const0> ;
assign debug_phase[20] = \<const0> ;
assign debug_phase[19] = \<const0> ;
assign debug_phase[18] = \<const0> ;
assign debug_phase[17] = \<const0> ;
assign debug_phase[16] = \<const0> ;
assign debug_phase[15] = \<const0> ;
assign debug_phase[14] = \<const0> ;
assign debug_phase[13] = \<const0> ;
assign debug_phase[12] = \<const0> ;
assign debug_phase[11] = \<const0> ;
assign debug_phase[10] = \<const0> ;
assign debug_phase[9] = \<const0> ;
assign debug_phase[8] = \<const0> ;
assign debug_phase[7] = \<const0> ;
assign debug_phase[6] = \<const0> ;
assign debug_phase[5] = \<const0> ;
assign debug_phase[4] = \<const0> ;
assign debug_phase[3] = \<const0> ;
assign debug_phase[2] = \<const0> ;
assign debug_phase[1] = \<const0> ;
assign debug_phase[0] = \<const0> ;
assign debug_phase_nd = \<const0> ;
assign event_phase_in_invalid = \<const0> ;
assign event_pinc_invalid = \<const0> ;
assign event_poff_invalid = \<const0> ;
assign event_s_config_tlast_missing = \<const0> ;
assign event_s_config_tlast_unexpected = \<const0> ;
assign event_s_phase_chanid_incorrect = \<const0> ;
assign event_s_phase_tlast_unexpected = \<const0> ;
assign m_axis_data_tdata[15] = \^m_axis_data_tdata [11];
assign m_axis_data_tdata[14] = \^m_axis_data_tdata [11];
assign m_axis_data_tdata[13] = \^m_axis_data_tdata [11];
assign m_axis_data_tdata[12] = \^m_axis_data_tdata [11];
assign m_axis_data_tdata[11:0] = \^m_axis_data_tdata [11:0];
assign m_axis_data_tlast = \<const0> ;
assign m_axis_data_tuser[0] = \<const0> ;
assign m_axis_phase_tdata[0] = \<const0> ;
assign m_axis_phase_tlast = \<const0> ;
assign m_axis_phase_tuser[0] = \<const0> ;
assign m_axis_phase_tvalid = \<const0> ;
assign s_axis_config_tready = \<const1> ;
assign s_axis_phase_tready = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
(* C_ACCUMULATOR_WIDTH = "22" *)
(* C_AMPLITUDE = "1" *)
(* C_CHANNELS = "1" *)
(* C_CHAN_WIDTH = "1" *)
(* C_DEBUG_INTERFACE = "0" *)
(* C_HAS_ACLKEN = "0" *)
(* C_HAS_ARESETN = "0" *)
(* C_HAS_M_DATA = "1" *)
(* C_HAS_M_PHASE = "0" *)
(* C_HAS_PHASEGEN = "1" *)
(* C_HAS_PHASE_OUT = "0" *)
(* C_HAS_SINCOS = "1" *)
(* C_HAS_S_CONFIG = "0" *)
(* C_HAS_S_PHASE = "1" *)
(* C_HAS_TLAST = "0" *)
(* C_HAS_TREADY = "0" *)
(* C_LATENCY = "8" *)
(* C_MEM_TYPE = "1" *)
(* C_MODE_OF_OPERATION = "0" *)
(* C_MODULUS = "10000" *)
(* C_M_DATA_HAS_TUSER = "0" *)
(* C_M_DATA_TDATA_WIDTH = "16" *)
(* C_M_DATA_TUSER_WIDTH = "1" *)
(* C_M_PHASE_HAS_TUSER = "0" *)
(* C_M_PHASE_TDATA_WIDTH = "1" *)
(* C_M_PHASE_TUSER_WIDTH = "1" *)
(* C_NEGATIVE_COSINE = "0" *)
(* C_NEGATIVE_SINE = "0" *)
(* C_NOISE_SHAPING = "0" *)
(* C_OPTIMISE_GOAL = "1" *)
(* C_OUTPUTS_REQUIRED = "0" *)
(* C_OUTPUT_FORM = "0" *)
(* C_OUTPUT_WIDTH = "12" *)
(* C_PHASE_ANGLE_WIDTH = "12" *)
(* C_PHASE_INCREMENT = "3" *)
(* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_PHASE_OFFSET = "0" *)
(* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_POR_MODE = "0" *)
(* C_RESYNC = "0" *)
(* C_S_CONFIG_SYNC_MODE = "0" *)
(* C_S_CONFIG_TDATA_WIDTH = "1" *)
(* C_S_PHASE_HAS_TUSER = "0" *)
(* C_S_PHASE_TDATA_WIDTH = "24" *)
(* C_S_PHASE_TUSER_WIDTH = "1" *)
(* C_USE_DSP48 = "0" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
dds_compiler_0_dds_compiler_v6_0_13_viv i_synth
(.aclk(aclk),
.aclken(1'b0),
.aresetn(1'b0),
.debug_axi_chan_in(NLW_i_synth_debug_axi_chan_in_UNCONNECTED[0]),
.debug_axi_pinc_in(NLW_i_synth_debug_axi_pinc_in_UNCONNECTED[21:0]),
.debug_axi_poff_in(NLW_i_synth_debug_axi_poff_in_UNCONNECTED[21:0]),
.debug_axi_resync_in(NLW_i_synth_debug_axi_resync_in_UNCONNECTED),
.debug_core_nd(NLW_i_synth_debug_core_nd_UNCONNECTED),
.debug_phase(NLW_i_synth_debug_phase_UNCONNECTED[21:0]),
.debug_phase_nd(NLW_i_synth_debug_phase_nd_UNCONNECTED),
.event_phase_in_invalid(NLW_i_synth_event_phase_in_invalid_UNCONNECTED),
.event_pinc_invalid(NLW_i_synth_event_pinc_invalid_UNCONNECTED),
.event_poff_invalid(NLW_i_synth_event_poff_invalid_UNCONNECTED),
.event_s_config_tlast_missing(NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED),
.event_s_config_tlast_unexpected(NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED),
.event_s_phase_chanid_incorrect(NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED),
.event_s_phase_tlast_missing(event_s_phase_tlast_missing),
.event_s_phase_tlast_unexpected(NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED),
.m_axis_data_tdata({\^m_axis_data_tdata [11],NLW_i_synth_m_axis_data_tdata_UNCONNECTED[14:11],\^m_axis_data_tdata [10:0]}),
.m_axis_data_tlast(NLW_i_synth_m_axis_data_tlast_UNCONNECTED),
.m_axis_data_tready(1'b0),
.m_axis_data_tuser(NLW_i_synth_m_axis_data_tuser_UNCONNECTED[0]),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_phase_tdata(NLW_i_synth_m_axis_phase_tdata_UNCONNECTED[0]),
.m_axis_phase_tlast(NLW_i_synth_m_axis_phase_tlast_UNCONNECTED),
.m_axis_phase_tready(1'b0),
.m_axis_phase_tuser(NLW_i_synth_m_axis_phase_tuser_UNCONNECTED[0]),
.m_axis_phase_tvalid(NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED),
.s_axis_config_tdata(1'b0),
.s_axis_config_tlast(1'b0),
.s_axis_config_tready(NLW_i_synth_s_axis_config_tready_UNCONNECTED),
.s_axis_config_tvalid(1'b0),
.s_axis_phase_tdata({1'b0,1'b0,s_axis_phase_tdata[21:0]}),
.s_axis_phase_tlast(1'b0),
.s_axis_phase_tready(NLW_i_synth_s_axis_phase_tready_UNCONNECTED),
.s_axis_phase_tuser(1'b0),
.s_axis_phase_tvalid(s_axis_phase_tvalid));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`pragma protect key_block
UeUQOSqc517u4Gp21W1qcB44JkXjttQw3I9etxLnnrt3tkJ0d4uxhbBwSkc7IM9w0xxr7owGLR37
1Ii0/OYJsQ==
`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
kOXgzYTJC4GxJCP3UAJekjjYLOXKC9b70sFPvaIFCHz6zbI3mz+JUFPTpADGukAuJQCKiXWwYOBZ
MmBb8JugLkKE+O1iqIjgnplEt9Bnnc0cPnUeT9o1Q0bWLLOKk75pVanxsTWyvGhO5t3dBcHf76mm
DceLRrUeM7AAXcHNQP8=
`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
JeQtyj3Kal6oTj33H4A+stJ+V3DCiNJv8J7k4H0+dLfFYYJJ3jbUoUt90xE3PJrsmjZDUKwDIVOX
HWBDaCL3u44dq/L0M441Q3RfpW9QQqU0ai34/xEtkAvplg6Oe3ludzsYQZ7T2bjYDyh8NSDEu4PD
/ngBWkp/hfXUBkMQq3g=
`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
D+mEShAo+idVddojD4Ocf30d3PeQsjyupmNQjqsNdbpJFSb9AWyTI4HLKIImT0S50Zgb6LGKxa9h
26g8vXL3CdbVdP5O8FpM1809Abu5sfhEOCwdvtKWRwLRZt1+A/6C8nMHuYTLwrt4lXg1bU5c54n9
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v0t8M5z/+3rsLJl0oKiKofyP/dx+okR3PXDIyw==
`pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
tcnuNu53+hchNr+pZ1NtakfiTYoR6SYivYJdM66R8/4XDELZLm46FZjh8e2MDPfDIe0TPxgXssIK
JBpdVvHEF3sN4ne8BH5Hig1m+5eYblKUujpGtmIpXovQKiu33+xi9YvN+S91R0i8O+wIG5Y8ZtSd
416fkpAXIqKUgtlCKXBPfNKh6pXB2wSYbWz3TlPOiCZhgXOn24ftBdQmq794Zo6QdyiBWEIqcHvf
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vafnOBmYmG/WIJ2D8gT8zcjKCOuzkEZD4/6LHw==
`pragma protect key_keyowner="Xilinx", key_keyname="xilinx_2016_05", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
CtAJ5i2Ss06xmVLrV4Tdrt3cQho/pCz9fbTCKJxQdDrBclu8FdA7n6uV/sbGH0tMaSievrFx2Jcw
lrfRQgsQbFyxSpn5PUFRabLV3UXwVpPqRPFv60hHW8dL6EBKTJRiEKGMFV/9GNtBclnQParE68gy
UWIYfWYlfU8odNKh63v3UlbKBdSSTudb0Ul16UHMxR9rOEcIVol8aLIxFF0XFN3SbjvZQYMrSrda
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LeUIPZxac7VkB/2/ioqm/Wqs+AR5+6YLStbDqg==
`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="base64", line_length=76, bytes=256)
`pragma protect key_block
H8/etVeod00xf5zMtWASof34IY7kAuSNlm7hO03B2H5FCcGK57Vb00Vt+MXmVOj3QvuEppkVfoRp
aiWdCvZQV4M2bjp8f3Db3s0ZMmSIt2zuc51k8zY1Y0nKWdWJH7FLeuQP4LkGpnxHCW1Wm19I4bK5
aE2Q5/aO8B6YbemoR7nMR8N/K0A4nYkOVGYsveU0f84h2V2yyL9LeJxQXfpBx9YHGPHob93Y8+O+
A/4Mcp63CNtn8VN4KLTG4jE2EiPkwENrbxfKRirxg965PcBxYIjSAYCBaCj3FAM6upsW3dLMtVwG
qGwFjMA4RWtrgulDz+M7h5KHp8mr1g08XMe2ig==
`pragma protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa"
`pragma protect encoding = (enctype="base64", line_length=76, bytes=256)
`pragma protect key_block
oUWxF3b8JRlOah1OMNSV5ZyimPbJt3uiy7FUd4TIJVQGabL/Hii1gWyfQhCW9H8Ah8GFuInV3D+f
flpO3ypa8cTIXTO/HTtjz6qbYG2ebBBFBQuiDScJaNN5MCBVGd85AgKN/PVxlNrp4Efqsi9DqVov
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nqXoT2i/VGrEGjSw0dBBHEHLIT1bpfl2lcmshw==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 94736)
`pragma protect data_block
tTkNZDFmf5VAS6NmaYyO52EQoG7u1iYvgAg7mEhFz4Kz7VuUIWM3THQEgWuN5N9ub3SPLz7QeUJl
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PrY=
`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//__________________________________________________uart_rx
`define IDLE 1'd0
`define RECV_BIT 1'd1
//__________Test Bench
`define BIT_TMR_MAX 10'd869 // #10240 <-- 115200 : tb #1738
//`define BIT_TMR_MAX 14'd10417//14'b10100010110000 // 14'd10416 #10417
//______________________________________________________________________
// `define BIT_INDEX_MAX 4'd9
module uart_rx(
input clk,
input rst,
input rxd,
output [7:0] data_rx,
output busy
);
//____________________________________________________________Global
reg [8:0] rxdata;
assign data_rx[7:0] = rxdata[8:1];
reg busy_reg;
assign busy = busy_reg;
reg [9:0] bitTmr;
reg [3:0] bitIndex;
reg rxState;
reg [9:0] bitCnt_0;
reg [9:0] bitCnt_1;
/*
wire rxBit;
assign rxBit =( (rxState != `RECV_BIT) ? dummy :
( (bitIndex == 1) ? rxdata[0] :
( (bitIndex == 2) ? rxdata[1] :
( (bitIndex == 3) ? rxdata[2] :
( (bitIndex == 4) ? rxdata[3] :
( (bitIndex == 5) ? rxdata[4] :
( (bitIndex == 6) ? rxdata[5] :
( (bitIndex == 7) ? rxdata[6] :
(bitIndex == 8) ? rxdata[7] :
dummy //when bitIndex == 0 : start signal(0) is not data
)
)
)
)
)
)
)
);
*/
always@(posedge clk) begin
if(rst)
begin
rxState <= `IDLE;
busy_reg <= 0;
end
else
begin
case(rxState)
`IDLE :
begin
bitIndex <= 0;
bitTmr <= 0;
bitCnt_0 <= 0;
bitCnt_1 <= 0;
if( rxd == 0 )
begin
rxState <= `RECV_BIT;
end
else
rxState <= `IDLE;
end
`RECV_BIT :
begin
if (bitTmr == `BIT_TMR_MAX-1)
begin
bitTmr <= 0;
bitCnt_0 <= 0;
bitCnt_1 <= 0;
if (bitIndex == 4'd9-1)
begin
// done!
busy_reg <= 1;
rxState <= `IDLE;
end
else
begin
busy_reg <= 0;
bitIndex <= bitIndex + 1'b1;
rxState <= `RECV_BIT;
end
end
else
begin
if(rxd == 0)
bitCnt_0 <= bitCnt_0 + 1'b1;
else
bitCnt_1 <= bitCnt_1 + 1'b1;
if( bitCnt_0 > bitCnt_1 )
rxdata[bitIndex] <= 0;
else
rxdata[bitIndex] <= 1;
bitTmr <= bitTmr + 1'b1;
rxState <= `RECV_BIT;
end
end
default :
begin
rxState <= `IDLE;
busy_reg <= 0;
end
endcase
end
end
endmodule
|
module omega_network_ff(clk, push, d_in, valid, d_out, control);
parameter WIDTH = 8;
parameter IN_PORTS = 8;
parameter OUT_PORTS = IN_PORTS;
parameter ADDR_WIDTH_PORTS = log2(OUT_PORTS-1);
input clk;
input [0:IN_PORTS-1] push;
input [IN_PORTS*WIDTH-1:0] d_in;
output [0:OUT_PORTS-1] valid;
output [OUT_PORTS*WIDTH-1:0] d_out;
input [ADDR_WIDTH_PORTS-1:0] control;
genvar g1, g2;
wire [WIDTH:0] stage [0:ADDR_WIDTH_PORTS][0:IN_PORTS-1];
generate
for(g1 = 0; g1 < IN_PORTS; g1 = g1 + 1) begin: generate_start
assign stage[0][g1][0] = push[g1];
assign stage[0][g1][WIDTH:1] = d_in[(g1+1)*WIDTH-1 -:WIDTH];
end
for(g1 = 0; g1 < ADDR_WIDTH_PORTS; g1 = g1 + 1) begin: generate_stage
for(g2 = 0; g2 < IN_PORTS/2; g2 = g2 + 1) begin: generate_switch
basic_switch_ff #(WIDTH+1) sw(clk, stage[g1][g2], stage[g1][g2+IN_PORTS/2], stage[g1+1][g2*2], stage[g1+1][g2*2+1], control[ADDR_WIDTH_PORTS-1-g1]);
end
end
for(g1 = 0; g1 < IN_PORTS; g1 = g1 + 1) begin: generate_end
assign valid[g1] = stage[ADDR_WIDTH_PORTS][g1][0];
assign d_out[(g1+1)*WIDTH-1 -:WIDTH] = stage[ADDR_WIDTH_PORTS][g1][WIDTH:1];
end
endgenerate
`include "log2.vh"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB8TO1_4_V
`define SKY130_FD_SC_HDLL__MUXB8TO1_4_V
/**
* muxb8to1: Buffered 8-input multiplexer.
*
* Verilog wrapper for muxb8to1 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__muxb8to1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__muxb8to1_4 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input [7:0] D ;
input [7:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__muxb8to1 base (
.Z(Z),
.D(D),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__muxb8to1_4 (
Z,
D,
S
);
output Z;
input [7:0] D;
input [7:0] S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__muxb8to1 base (
.Z(Z),
.D(D),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB8TO1_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLRTP_FUNCTIONAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_pg/sky130_fd_sc_hs__u_dl_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrtp (
VPWR ,
VGND ,
Q ,
RESET_B,
D ,
GATE
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hs__u_dl_p_r_pg `UNIT_DELAY u_dl_p_r_pg0 (buf_Q , D, GATE, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_FUNCTIONAL_V
|
`timescale 1ns / 1ps
`define PHASE 20 // 20ns per phase, 40ns per cycle, 25MHz
module PolarisCPU(
// MISC DIAGNOSTICS
output fence_o,
output trap_o,
output [3:0] cause_o,
output [63:0] mepc_o,
output mpie_o,
output mie_o,
input irq_i,
// I MASTER
input iack_i,
input [31:0] idat_i,
output [63:0] iadr_o,
output istb_o,
// D MASTER
input dack_i,
input [63:0] ddat_i,
output [63:0] ddat_o,
output [63:0] dadr_o,
output dwe_o,
output dcyc_o,
output dstb_o,
output [1:0] dsiz_o,
output dsigned_o,
// CSR ACCESS
output [11:0] cadr_o,
output coe_o,
output cwe_o,
input cvalid_i,
output [63:0] cdat_o,
input [63:0] cdat_i,
// SYSCON
input clk_i,
input reset_i
);
// Sequencer outputs
wire pc_mbvec, pc_pcPlus4;
wire ft0_o;
wire iadr_pc;
wire ir_idat;
// Sequencer inputs
reg ft0;
// Internal working wires and registers
reg rst;
reg [63:0] pc, ia;
wire [63:0] pc_mux, ia_mux;
reg [31:0] ir;
wire [31:0] ir_mux;
reg xt0, xt1, xt2, xt3, xt4;
wire xt0_o, xt1_o, xt2_o, xt3_o, xt4_o;
wire [4:0] ra_mux;
wire ra_ir1, ra_ir2, ra_ird;
wire rdat_alu, rdat_pc;
wire [63:0] rdat_i, rdat_o;
wire rwe_o;
reg [63:0] alua, alub;
wire [63:0] alua_mux, alub_mux;
wire alua_rdat, alua_0, alua_ia;
wire alub_rdat, alub_imm12i, alub_imm12s, alub_imm20u, alub_imm20uj;
wire [63:0] imm12i, imm12s, imm12sb;
wire pc_alu;
wire cflag_i;
wire sum_en;
wire and_en;
wire xor_en;
wire invB_en;
wire lsh_en;
wire rsh_en;
wire ltu_en, lts_en;
wire [63:0] aluResult, aluXResult;
wire cflag_o;
wire vflag_o;
wire zflag_o;
wire [3:0] rmask_i;
wire sx32_en;
wire alua_alua;
wire alub_alub;
wire [63:0] imm20u, imm20uj;
wire ia_pc;
wire dadr_alu;
wire dcyc_1;
wire dstb_1;
wire dsiz_fn3;
wire rdat_ddat;
wire ddat_rdat;
wire [7:0] ccr_mux;
reg [7:0] ccr;
wire ccr_alu;
wire alub_imm12sb;
reg trap;
wire mcause_2, mcause_3, mcause_11;
wire pc_mtvec;
reg [63:0] mepc;
wire [63:0] mepc_mux;
wire mepc_ia;
wire pc_mepc;
wire mie, mpie;
wire mie_0, mie_mpie;
wire mpie_mie, mpie_1;
wire rdat_cdat, cdat_rdat;
wire coe_1, cwe_1;
wire cdat_imm5;
wire cdat_alu;
wire alub_imm5;
wire alua_cdat;
wire icvalid_i;
wire [63:0] icdat_i;
wire [63:0] mtvec_i;
wire take_irq;
wire mepc_pc;
wire mcause_irq_o;
wire cvalid = icvalid_i | cvalid_i;
wire [63:0] ucdat_i = icdat_i | cdat_i;
wire rdNotZero = |ir[11:7];
wire r1NotZero = |ir[19:15];
wire [63:0] imm5 = {59'b0, ir[19:15]};
assign coe_o = coe_1 & rdNotZero;
assign cwe_o = cwe_1 & r1NotZero;
assign cadr_o = ir[31:20];
assign cdat_o = (cdat_rdat ? rdat_o : 0) |
(cdat_alu ? aluXResult : 0) |
(cdat_imm5 ? imm5 : 0);
wire ltFlag = aluXResult[63] ^ vflag_o;
assign ccr_mux = ccr_alu ? {cflag_o, ~cflag_o, ~ltFlag, ltFlag, 2'b00, ~zflag_o, zflag_o} : ccr;
assign dsigned_o = dsiz_fn3 & ~ir[14];
assign dsiz_o = dsiz_fn3 ? ir[13:12] : 2'b00;
assign dcyc_o = dcyc_1;
assign dstb_o = dstb_1;
assign dadr_o = (dadr_alu ? aluXResult : 64'd0);
assign ddat_o = (ddat_rdat ? rdat_o : 0);
assign aluXResult = (sx32_en ? {{32{aluResult[31]}}, aluResult[31:0]} : aluResult);
assign imm12i = {{52{ir[31]}}, ir[31:20]};
assign imm12s = {{52{ir[31]}}, ir[31:25], ir[11:7]};
assign imm12sb = {{51{ir[31]}}, ir[31], ir[7], ir[30:25], ir[11:8], 1'b0};
assign imm20u = {{32{ir[31]}}, ir[31:12], 12'd0};
assign imm20uj = {{43{ir[31]}}, ir[31], ir[19:12], ir[20], ir[30:21], 1'b0};
assign alua_alua = ~|{alua_rdat, alua_0, alua_ia, alua_cdat};
assign alub_alub = ~|{alub_rdat, alub_imm12i, alub_imm12s, alub_imm12sb, alub_imm20u, alub_imm20uj, alub_imm5};
assign alua_mux = // ignore alua_0 since that will force alua=0.
(alua_ia ? ia : 0) |
(alua_rdat ? rdat_o : 0) |
(alua_cdat ? ucdat_i : 0) |
(alua_alua ? alua : 0);
assign alub_mux =
(alub_rdat ? rdat_o : 0) |
(alub_imm12i ? imm12i : 0) |
(alub_imm12s ? imm12s : 0) |
(alub_imm12sb ? imm12sb : 0) |
(alub_imm20u ? imm20u : 0) |
(alub_imm20uj ? imm20uj : 0) |
(alub_imm5 ? imm5 : 0) |
(alub_alub ? alub : 0);
assign rdat_i = (rdat_alu ? aluXResult : 0) |
(rdat_ddat ? ddat_i : 0) |
(rdat_cdat ? ucdat_i : 0) |
(rdat_pc ? pc : 0);
assign ra_mux = (ra_ir1 ? ir[19:15] : 0) |
(ra_ir2 ? ir[24:20] : 0) |
(ra_ird ? ir[11:7] : 0); // Defaults to 0
wire pc_pc = ~|{pc_mbvec,pc_pcPlus4,pc_alu,pc_mtvec,pc_mepc};
assign pc_mux = (pc_mbvec ? 64'hFFFF_FFFF_FFFF_FF00 : 64'h0) |
(pc_pcPlus4 ? pc + 4 : 64'h0) |
(pc_alu ? aluXResult : 64'h0) |
(pc_mtvec ? mtvec_i : 64'h0) |
(pc_mepc ? mepc_o : 64'h0) |
(pc_pc ? pc : 64'h0); // base case
wire ia_ia = ~ia_pc;
assign ia_mux = (ia_pc ? pc : 0) |
(ia_ia ? ia : 0);
assign iadr_o = iadr_pc ? pc : 0;
wire ir_ir = ~ir_idat;
assign ir_mux = (ir_idat ? idat_i : 0) |
(ir_ir ? ir : 0); // base case
always @(posedge clk_i) begin
rst <= reset_i;
pc <= pc_mux;
ia <= ia_mux;
ft0 <= ft0_o;
xt0 <= xt0_o;
xt1 <= xt1_o;
xt2 <= xt2_o;
xt3 <= xt3_o;
xt4 <= xt4_o;
ir <= ir_mux;
alua <= alua_mux;
alub <= alub_mux;
ccr <= ccr_mux;
trap <= trap_o;
end
Sequencer s(
.xt0_o(xt0_o),
.xt1_o(xt1_o),
.xt2_o(xt2_o),
.xt3_o(xt3_o),
.xt0(xt0),
.xt1(xt1),
.xt2(xt2),
.xt3(xt3),
.ft0(ft0),
.istb_o(istb_o),
.iadr_pc(iadr_pc),
.iack_i(iack_i),
.pc_mbvec(pc_mbvec),
.pc_pcPlus4(pc_pcPlus4),
.ir_idat(ir_idat),
.ir(ir),
.ft0_o(ft0_o),
.rdat_pc(rdat_pc),
.sum_en(sum_en),
.pc_alu(pc_alu),
.ra_ir1(ra_ir1),
.ra_ir2(ra_ir2),
.ra_ird(ra_ird),
.alua_rdat(alua_rdat),
.alub_rdat(alub_rdat),
.alub_imm12i(alub_imm12i),
.rwe_o(rwe_o),
.rdat_alu(rdat_alu),
.and_en(and_en),
.xor_en(xor_en),
.invB_en(invB_en),
.lsh_en(lsh_en),
.rsh_en(rsh_en),
.cflag_i(cflag_i),
.sx32_en(sx32_en),
.alua_0(alua_0),
.alub_imm20u(alub_imm20u),
.ia_pc(ia_pc),
.alua_ia(alua_ia),
.dadr_alu(dadr_alu),
.dcyc_1(dcyc_1),
.dstb_1(dstb_1),
.dsiz_fn3(dsiz_fn3),
.rdat_ddat(rdat_ddat),
.dack_i(dack_i),
.ddat_rdat(ddat_rdat),
.alub_imm12s(alub_imm12s),
.dwe_o(dwe_o),
.alub_imm20uj(alub_imm20uj),
.ccr_alu(ccr_alu),
.alub_imm12sb(alub_imm12sb),
.xt4_o(xt4_o),
.xt4(xt4),
.ccr(ccr),
.fence_o(fence_o),
.trap_o(trap_o),
.trap(trap),
.mcause_2(mcause_2),
.mcause_3(mcause_3),
.mcause_11(mcause_11),
.pc_mtvec(pc_mtvec),
.mepc_ia(mepc_ia),
.pc_mepc(pc_mepc),
.mpie_mie(mpie_mie),
.mpie_1(mpie_1),
.mie_mpie(mie_mpie),
.mie_0(mie_0),
.csrok_i(cvalid),
.rdat_cdat(rdat_cdat),
.coe_o(coe_1),
.cdat_rdat(cdat_rdat),
.cwe_o(cwe_1),
.cdat_imm5(cdat_imm5),
.cdat_alu(cdat_alu),
.alub_imm5(alub_imm5),
.alua_cdat(alua_cdat),
.take_irq(take_irq),
.mepc_pc(mepc_pc),
.mcause_irq_o(mcause_irq_o),
.ltu_en(ltu_en),
.lts_en(lts_en),
.rst(rst)
);
xrs xrs(
.clk_i(clk_i),
.ra_i(ra_mux),
.rdat_i(rdat_i),
.rdat_o(rdat_o),
.rmask_i({4{rwe_o}})
);
alu alu(
.inA_i(alua),
.inB_i(alub),
.cflag_i(cflag_i),
.sum_en_i(sum_en),
.and_en_i(and_en),
.xor_en_i(xor_en),
.invB_en_i(invB_en),
.lsh_en_i(lsh_en),
.rsh_en_i(rsh_en),
.ltu_en_i(ltu_en),
.lts_en_i(lts_en),
.out_o(aluResult),
.cflag_o(cflag_o),
.vflag_o(vflag_o),
.zflag_o(zflag_o)
);
CSRs csrs(
.cadr_i(cadr_o),
.cvalid_o(icvalid_i),
.cdat_o(icdat_i),
.cdat_i(cdat_o),
.coe_i(coe_o),
.cwe_i(cwe_o),
.mie_0(mie_0),
.mie_mpie(mie_mpie),
.mpie_mie(mpie_mie),
.mpie_1(mpie_1),
.mtvec_o(mtvec_i),
.mepc_o(mepc_o),
.mie_o(mie_o),
.mpie_o(mpie_o),
.ft0_i(ft0),
.tick_i(1'b0), // for now
.mcause_2(mcause_2),
.mcause_3(mcause_3),
.mcause_11(mcause_11),
.mepc_ia(mepc_ia),
.mepc_pc(mepc_pc),
.ia_i(ia),
.pc_i(pc),
.cause_o(cause_o),
.irq_i(irq_i),
.take_irq_o(take_irq),
.mcause_irq_i(mcause_irq_o),
.reset_i(reset_i),
.clk_i(clk_i)
);
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:58:17 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_8 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_11 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_12 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_14 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_17 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module CORDIC_Arch3_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
overflow_flag, underflow_flag, zero_flag, busy, data_output );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag, zero_flag, busy;
wire enab_d_ff_RB1, enab_RB3, enab_d_ff5_data_out, ready_add_subt,
d_ff1_operation_out, d_ff3_sign_out, enab_d_ff4_Yn, enab_d_ff4_Xn,
fmtted_Result_31_, ITER_CONT_net3562083, ITER_CONT_N5, ITER_CONT_N4,
ITER_CONT_N3, inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_SGF,
inst_FPU_PIPELINED_FPADDSUB_N60, inst_FPU_PIPELINED_FPADDSUB_N59,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB__19_net_,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2,
inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2,
inst_FPU_PIPELINED_FPADDSUB__6_net_,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_INIT,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_INIT,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_INIT,
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5,
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6,
inst_FPU_PIPELINED_FPADDSUB_enable_Pipeline_input,
d_ff5_data_out_net3561862, reg_Z0_net3561862,
reg_val_muxZ_2stage_net3561862, reg_shift_y_net3561862,
d_ff4_Xn_net3561862, d_ff4_Yn_net3561862, d_ff4_Zn_net3561862,
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3562047,
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957,
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898,
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939,
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921,
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898,
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939,
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939,
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939,
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921,
inst_FPU_PIPELINED_FPADDSUB_array_comparators_GTComparator_N0,
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0, n529,
n539, n540, n541, n542, n543, n544, n545, n546, n547, n548, n549,
n550, n551, n553, n554, n555, n556, n557, n558, n559, n561, n562,
n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573,
n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584,
n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595,
n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, n606,
n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617,
n618, n619, n620, n621, n622, n623, n625, n626,
DP_OP_33J163_122_2179_n28, DP_OP_33J163_122_2179_n18,
DP_OP_33J163_122_2179_n17, DP_OP_33J163_122_2179_n16,
DP_OP_33J163_122_2179_n15, DP_OP_33J163_122_2179_n14,
DP_OP_33J163_122_2179_n8, DP_OP_33J163_122_2179_n7,
DP_OP_33J163_122_2179_n6, DP_OP_33J163_122_2179_n5,
DP_OP_33J163_122_2179_n4, DP_OP_33J163_122_2179_n3,
DP_OP_33J163_122_2179_n2, DP_OP_33J163_122_2179_n1, intadd_399_CI,
intadd_399_n3, intadd_399_n2, intadd_399_n1, intadd_400_CI,
intadd_400_n3, intadd_400_n2, intadd_400_n1, intadd_401_CI,
intadd_401_SUM_2_, intadd_401_SUM_1_, intadd_401_SUM_0_,
intadd_401_n3, intadd_401_n2, intadd_401_n1, n630, n631, n632, n633,
n634, n635, n636, n637, n638, n639, n640, n641, n642, n643, n644,
n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655,
n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666,
n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677,
n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688,
n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699,
n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710,
n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732,
n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743,
n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754,
n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765,
n766, n767, n768, n769, n770, n771, n772, n773, n774, n775, n776,
n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787,
n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798,
n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809,
n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820,
n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842,
n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930,
n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941,
n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952,
n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963,
n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985,
n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996,
n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246,
n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256,
n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296,
n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366,
n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376,
n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386,
n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396,
n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406,
n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416,
n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426,
n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436,
n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446,
n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456,
n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466,
n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476,
n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486,
n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496,
n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506,
n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516,
n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526,
n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536,
n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576,
n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606,
n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779;
wire [3:0] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] first_mux_X;
wire [31:0] d_ff_Yn;
wire [31:0] first_mux_Y;
wire [31:0] d_ff_Zn;
wire [31:0] first_mux_Z;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [7:0] sh_exp_x;
wire [7:0] sh_exp_y;
wire [25:4] data_out_LUT;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [31:0] result_add_subt;
wire [30:0] mux_sal;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
wire [31:0] inst_FPU_PIPELINED_FPADDSUB_formatted_number_W;
wire [25:1] inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF;
wire [25:2] inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SFG;
wire [7:0] inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW;
wire [25:0] inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR;
wire [7:0] inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW;
wire [51:0] inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR;
wire [25:0] inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR;
wire [4:2] inst_FPU_PIPELINED_FPADDSUB_shft_value_mux_o_EWR;
wire [4:0] inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR;
wire [4:0] inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW;
wire [4:0] inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW;
wire [27:0] inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW;
wire [27:0] inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW;
wire [30:0] inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW;
wire [31:0] inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW;
wire [3:0] inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7;
wire [2:0] inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(n1741), .ENCLK(ITER_CONT_net3562083), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 d_ff5_data_out_clk_gate_Q_reg ( .CLK(
clk), .EN(enab_d_ff5_data_out), .ENCLK(d_ff5_data_out_net3561862),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_17 reg_Z0_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff_RB1), .ENCLK(reg_Z0_net3561862), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_14 reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
reg_val_muxZ_2stage_net3561862), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_12 reg_shift_y_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_RB3), .ENCLK(reg_shift_y_net3561862), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_11 d_ff4_Xn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Xn), .ENCLK(d_ff4_Xn_net3561862), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 d_ff4_Yn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Yn), .ENCLK(d_ff4_Yn_net3561862), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_8 d_ff4_Zn_clk_gate_Q_reg ( .CLK(clk),
.EN(n631), .ENCLK(d_ff4_Zn_net3561862), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n626), .ENCLK(
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3562047), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]),
.ENCLK(inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_2 inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]),
.ENCLK(inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB__19_net_), .ENCLK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]),
.ENCLK(inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_3 inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB_enable_Pipeline_input),
.ENCLK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_4 inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6),
.ENCLK(inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5),
.ENCLK(inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(inst_FPU_PIPELINED_FPADDSUB__6_net_), .ENCLK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .TE(1'b0) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_Ready_reg_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1700), .Q(ready_add_subt) );
DFFRXLTS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n1777), .Q(
inst_CORDIC_FSM_v3_state_reg[6]), .QN(n1669) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n1775), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n1775), .Q(
inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(data_in[31]), .CK(reg_Z0_net3561862), .RN(
n1775), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(data_in[30]), .CK(reg_Z0_net3561862), .RN(
n1775), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(data_in[29]), .CK(reg_Z0_net3561862), .RN(
n1775), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(data_in[28]), .CK(reg_Z0_net3561862), .RN(
n1775), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(data_in[27]), .CK(reg_Z0_net3561862), .RN(
n1775), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(data_in[26]), .CK(reg_Z0_net3561862), .RN(
n1774), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(data_in[25]), .CK(reg_Z0_net3561862), .RN(
n1774), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(data_in[24]), .CK(reg_Z0_net3561862), .RN(
n1774), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(data_in[23]), .CK(reg_Z0_net3561862), .RN(
n1774), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(data_in[22]), .CK(reg_Z0_net3561862), .RN(
n1774), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(data_in[21]), .CK(reg_Z0_net3561862), .RN(
n1774), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(data_in[20]), .CK(reg_Z0_net3561862), .RN(
n1774), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(data_in[19]), .CK(reg_Z0_net3561862), .RN(
n1774), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(data_in[18]), .CK(reg_Z0_net3561862), .RN(
n1774), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(data_in[17]), .CK(reg_Z0_net3561862), .RN(
n1774), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(data_in[16]), .CK(reg_Z0_net3561862), .RN(
n1777), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(data_in[15]), .CK(reg_Z0_net3561862), .RN(
n1776), .Q(d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(data_in[14]), .CK(reg_Z0_net3561862), .RN(
n1777), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(data_in[13]), .CK(reg_Z0_net3561862), .RN(
n1776), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(data_in[12]), .CK(reg_Z0_net3561862), .RN(
n802), .Q(d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(data_in[11]), .CK(reg_Z0_net3561862), .RN(
n529), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(data_in[10]), .CK(reg_Z0_net3561862), .RN(
n529), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(data_in[9]), .CK(reg_Z0_net3561862), .RN(n529),
.Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(data_in[8]), .CK(reg_Z0_net3561862), .RN(n529),
.Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(data_in[7]), .CK(reg_Z0_net3561862), .RN(n529),
.Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(data_in[6]), .CK(reg_Z0_net3561862), .RN(n1773), .Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(data_in[5]), .CK(reg_Z0_net3561862), .RN(n1773), .Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(data_in[4]), .CK(reg_Z0_net3561862), .RN(n1773), .Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(data_in[3]), .CK(reg_Z0_net3561862), .RN(n1773), .Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(data_in[2]), .CK(reg_Z0_net3561862), .RN(n1773), .Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(data_in[1]), .CK(reg_Z0_net3561862), .RN(n1773), .Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(data_in[0]), .CK(reg_Z0_net3561862), .RN(n1773), .Q(d_ff1_Z[0]) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(shift_region_flag[0]), .CK(
reg_Z0_net3561862), .RN(n1773), .Q(d_ff1_shift_region_flag_out[0]),
.QN(n690) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(sh_exp_y[7]), .CK(reg_shift_y_net3561862), .RN(n1772), .Q(d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(sh_exp_y[6]), .CK(reg_shift_y_net3561862), .RN(n1772), .Q(d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(sh_exp_y[5]), .CK(reg_shift_y_net3561862), .RN(n1772), .Q(d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(sh_exp_y[4]), .CK(reg_shift_y_net3561862), .RN(n1772), .Q(d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(sh_exp_y[3]), .CK(reg_shift_y_net3561862), .RN(n1772), .Q(d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(sh_exp_y[2]), .CK(reg_shift_y_net3561862), .RN(n1772), .Q(d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(sh_exp_y[1]), .CK(reg_shift_y_net3561862), .RN(n1772), .Q(d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(sh_exp_y[0]), .CK(reg_shift_y_net3561862), .RN(n1772), .Q(d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(sh_exp_x[7]), .CK(reg_shift_y_net3561862), .RN(n1772), .Q(d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(sh_exp_x[6]), .CK(reg_shift_y_net3561862), .RN(n1772), .Q(d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(sh_exp_x[5]), .CK(reg_shift_y_net3561862), .RN(n1771), .Q(d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(sh_exp_x[4]), .CK(reg_shift_y_net3561862), .RN(n1771), .Q(d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(sh_exp_x[3]), .CK(reg_shift_y_net3561862), .RN(n1771), .Q(d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(sh_exp_x[2]), .CK(reg_shift_y_net3561862), .RN(n1771), .Q(d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(sh_exp_x[1]), .CK(reg_shift_y_net3561862), .RN(n1771), .Q(d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(sh_exp_x[0]), .CK(reg_shift_y_net3561862), .RN(n1771), .Q(d_ff3_sh_x_out[23]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n551), .CK(reg_shift_y_net3561862), .RN(
n1771), .Q(d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(data_out_LUT[25]), .CK(
reg_shift_y_net3561862), .RN(n1771), .Q(d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n542), .CK(reg_shift_y_net3561862), .RN(
n1771), .Q(d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n543), .CK(reg_shift_y_net3561862), .RN(
n1771), .Q(d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n544), .CK(reg_shift_y_net3561862), .RN(
n1770), .Q(d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n559), .CK(reg_shift_y_net3561862), .RN(
n1770), .Q(d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n557), .CK(reg_shift_y_net3561862), .RN(
n1770), .Q(d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n545), .CK(reg_shift_y_net3561862), .RN(
n1770), .Q(d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n554), .CK(reg_shift_y_net3561862), .RN(
n1770), .Q(d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n548), .CK(reg_shift_y_net3561862), .RN(
n1770), .Q(d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n555), .CK(reg_shift_y_net3561862), .RN(n1770), .Q(d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n1593), .CK(reg_shift_y_net3561862), .RN(
n1770), .Q(d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n553), .CK(reg_shift_y_net3561862), .RN(n1770), .Q(d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n549), .CK(reg_shift_y_net3561862), .RN(n1770), .Q(d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n547), .CK(reg_shift_y_net3561862), .RN(n1769), .Q(d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(data_out_LUT[4]), .CK(reg_shift_y_net3561862),
.RN(n1769), .Q(d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n558), .CK(reg_shift_y_net3561862), .RN(n1769), .Q(d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n550), .CK(reg_shift_y_net3561862), .RN(n1769), .Q(d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n556), .CK(reg_shift_y_net3561862), .RN(n1769), .Q(d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n546), .CK(reg_shift_y_net3561862), .RN(n1769), .Q(d_ff3_LUT_out[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n1779),
.CK(inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3562047), .RN(
n1700), .Q(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .CK(
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3562047), .RN(n1700),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(busy),
.CK(inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3562047), .RN(
n1700), .Q(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3562047), .RN(n1730),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1700),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1701),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1701),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1701),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1701),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Xn_net3561862), .RN(n1769), .Q(d_ff_Xn[23]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(first_mux_X[23]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1769), .Q(d_ff2_X[23]), .QN(
n1638) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Yn_net3561862), .RN(n1769), .Q(d_ff_Yn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(first_mux_Y[23]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1769), .Q(d_ff2_Y[23]), .QN(
n1639) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Zn_net3561862), .RN(n1768), .Q(d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(first_mux_Z[23]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1768), .Q(d_ff2_Z[23]) );
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Xn_net3561862), .RN(n1768), .Q(d_ff_Xn[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Yn_net3561862), .RN(n1768), .Q(d_ff_Yn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Zn_net3561862), .RN(n1768), .Q(d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(first_mux_Z[24]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1768), .Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Xn_net3561862), .RN(n1767), .Q(d_ff_Xn[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Yn_net3561862), .RN(n1767), .Q(d_ff_Yn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Zn_net3561862), .RN(n1767), .Q(d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(first_mux_Z[25]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1767), .Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Xn_net3561862), .RN(n1767), .Q(d_ff_Xn[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Yn_net3561862), .RN(n1767), .Q(d_ff_Yn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Zn_net3561862), .RN(n1766), .Q(d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(first_mux_Z[26]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1766), .Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Xn_net3561862), .RN(n1766), .Q(d_ff_Xn[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Yn_net3561862), .RN(n1766), .Q(d_ff_Yn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Zn_net3561862), .RN(n1766), .Q(d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(first_mux_Z[27]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1765), .Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Xn_net3561862), .RN(n1765), .Q(d_ff_Xn[28]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(first_mux_X[28]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1765), .Q(d_ff2_X[28]), .QN(
n1695) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Yn_net3561862), .RN(n1765), .Q(d_ff_Yn[28]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(first_mux_Y[28]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1765), .Q(d_ff2_Y[28]), .QN(
n1696) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Zn_net3561862), .RN(n1765), .Q(d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(first_mux_Z[28]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1765), .Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Xn_net3561862), .RN(n1765), .Q(d_ff_Xn[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Yn_net3561862), .RN(n1764), .Q(d_ff_Yn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Zn_net3561862), .RN(n1764), .Q(d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(first_mux_Z[29]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1764), .Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Xn_net3561862), .RN(n1764), .Q(d_ff_Xn[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(first_mux_X[30]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1764), .Q(d_ff2_X[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Yn_net3561862), .RN(n1764), .Q(d_ff_Yn[30]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(first_mux_Y[30]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1764), .Q(d_ff2_Y[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Zn_net3561862), .RN(n1763), .Q(d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(first_mux_Z[30]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1763), .Q(d_ff2_Z[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(
n589), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1702), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .QN(n1651) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1703), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1703), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1703), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1703), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1703), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1704), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]), .QN(n1652) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1704), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]), .QN(n1668) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1704), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]), .QN(n1694) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1704), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]), .QN(n1693) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1704), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[28]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1704), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[29]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1704), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[30]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1705), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1705),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1705),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1705),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1705),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1705),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1705),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1705),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1705),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1705),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1722), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n804),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n806),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1706),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1722), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1722),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n1722), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1706),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1722), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1722),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n1722), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1706),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1722), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1722),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n1722), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1706),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1723), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1723),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n1723), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1706),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1723), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1723),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n1723), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1706),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1723), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1723),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n1723), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1706),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1724), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1724),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n1723), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_SGF), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1730),
.Q(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM), .QN(n1625) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1732), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n1665) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Xn_net3561862), .RN(n1763), .Q(d_ff_Xn[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(first_mux_X[22]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1763), .Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(d_ff2_X[22]), .CK(reg_shift_y_net3561862), .RN(n1763), .Q(d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Yn_net3561862), .RN(n1763), .Q(d_ff_Yn[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(first_mux_Y[22]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1763), .Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(d_ff2_Y[22]), .CK(reg_shift_y_net3561862), .RN(n1763), .Q(d_ff3_sh_y_out[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Zn_net3561862), .RN(n1763), .Q(d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(first_mux_Z[22]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1762), .Q(d_ff2_Z[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1707), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1725),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1730), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n1641) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Xn_net3561862), .RN(n1762), .Q(d_ff_Xn[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(first_mux_X[15]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1762), .Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(d_ff2_X[15]), .CK(reg_shift_y_net3561862), .RN(n1762), .Q(d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Yn_net3561862), .RN(n1762), .Q(d_ff_Yn[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(first_mux_Y[15]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1762), .Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(d_ff2_Y[15]), .CK(reg_shift_y_net3561862), .RN(n1762), .Q(d_ff3_sh_y_out[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Zn_net3561862), .RN(n1762), .Q(d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(first_mux_Z[15]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1762), .Q(d_ff2_Z[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1707), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1724),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1731), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n1658) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Xn_net3561862), .RN(n1761), .Q(d_ff_Xn[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(first_mux_X[18]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1761), .Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(d_ff2_X[18]), .CK(reg_shift_y_net3561862), .RN(n1761), .Q(d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Yn_net3561862), .RN(n1761), .Q(d_ff_Yn[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(first_mux_Y[18]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1761), .Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(d_ff2_Y[18]), .CK(reg_shift_y_net3561862), .RN(n1761), .Q(d_ff3_sh_y_out[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Zn_net3561862), .RN(n1761), .Q(d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(first_mux_Z[18]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1761), .Q(d_ff2_Z[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1708), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1725),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1708),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1732), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n1664) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Xn_net3561862), .RN(n1761), .Q(d_ff_Xn[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(first_mux_X[21]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1760), .Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(d_ff2_X[21]), .CK(reg_shift_y_net3561862), .RN(n1760), .Q(d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Yn_net3561862), .RN(n1760), .Q(d_ff_Yn[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(first_mux_Y[21]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1760), .Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(d_ff2_Y[21]), .CK(reg_shift_y_net3561862), .RN(n1760), .Q(d_ff3_sh_y_out[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Zn_net3561862), .RN(n1760), .Q(d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(first_mux_Z[21]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1760), .Q(d_ff2_Z[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1708), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1725),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1731), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n1655) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Xn_net3561862), .RN(n1760), .Q(d_ff_Xn[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(first_mux_X[19]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1760), .Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(d_ff2_X[19]), .CK(reg_shift_y_net3561862), .RN(n1759), .Q(d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Yn_net3561862), .RN(n1759), .Q(d_ff_Yn[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(first_mux_Y[19]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1759), .Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(d_ff2_Y[19]), .CK(reg_shift_y_net3561862), .RN(n1759), .Q(d_ff3_sh_y_out[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Zn_net3561862), .RN(n1759), .Q(d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(first_mux_Z[19]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1759), .Q(d_ff2_Z[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1708), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1725),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1709),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1731), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n1666) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Xn_net3561862), .RN(n1759), .Q(d_ff_Xn[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(first_mux_X[20]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1759), .Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(d_ff2_X[20]), .CK(reg_shift_y_net3561862), .RN(n1759), .Q(d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Yn_net3561862), .RN(n1758), .Q(d_ff_Yn[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(first_mux_Y[20]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1758), .Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(d_ff2_Y[20]), .CK(reg_shift_y_net3561862), .RN(n1758), .Q(d_ff3_sh_y_out[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Zn_net3561862), .RN(n1758), .Q(d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(first_mux_Z[20]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1758), .Q(d_ff2_Z[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1709), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1725),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1731), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n1656) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Xn_net3561862), .RN(n1758), .Q(d_ff_Xn[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(first_mux_X[17]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1758), .Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(d_ff2_X[17]), .CK(reg_shift_y_net3561862), .RN(n1758), .Q(d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Yn_net3561862), .RN(n1758), .Q(d_ff_Yn[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(first_mux_Y[17]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1757), .Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(d_ff2_Y[17]), .CK(reg_shift_y_net3561862), .RN(n1757), .Q(d_ff3_sh_y_out[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Zn_net3561862), .RN(n1757), .Q(d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(first_mux_Z[17]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1757), .Q(d_ff2_Z[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1709), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1725),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1728), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n1615) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Xn_net3561862), .RN(n1757), .Q(d_ff_Xn[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(first_mux_X[4]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1757), .Q(d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(d_ff2_X[4]), .CK(reg_shift_y_net3561862),
.RN(n1757), .Q(d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Yn_net3561862), .RN(n1757), .Q(d_ff_Yn[4]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(first_mux_Y[4]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1757), .Q(d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(d_ff2_Y[4]), .CK(reg_shift_y_net3561862),
.RN(n1756), .Q(d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Zn_net3561862), .RN(n1756), .Q(d_ff_Zn[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(first_mux_Z[4]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1756), .Q(d_ff2_Z[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1710), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1724),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Xn_net3561862), .RN(n1756), .Q(d_ff_Xn[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(first_mux_X[6]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1756), .Q(d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(d_ff2_X[6]), .CK(reg_shift_y_net3561862),
.RN(n1756), .Q(d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Yn_net3561862), .RN(n1756), .Q(d_ff_Yn[6]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(first_mux_Y[6]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1756), .Q(d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(d_ff2_Y[6]), .CK(reg_shift_y_net3561862),
.RN(n1756), .Q(d_ff3_sh_y_out[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Zn_net3561862), .RN(n1755), .Q(d_ff_Zn[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(first_mux_Z[6]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1755), .Q(d_ff2_Z[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1710), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1724),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1633), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1729), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n1604) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Xn_net3561862), .RN(n1755), .Q(d_ff_Xn[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(first_mux_X[13]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1755), .Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(d_ff2_X[13]), .CK(reg_shift_y_net3561862), .RN(n1755), .Q(d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Yn_net3561862), .RN(n1755), .Q(d_ff_Yn[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(first_mux_Y[13]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1755), .Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(d_ff2_Y[13]), .CK(reg_shift_y_net3561862), .RN(n1755), .Q(d_ff3_sh_y_out[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Zn_net3561862), .RN(n1754), .Q(d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(first_mux_Z[13]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1754), .Q(d_ff2_Z[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1711), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1711),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1731), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n1642) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Xn_net3561862), .RN(n1754), .Q(d_ff_Xn[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(first_mux_X[16]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1754), .Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(d_ff2_X[16]), .CK(reg_shift_y_net3561862), .RN(n1754), .Q(d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Yn_net3561862), .RN(n1754), .Q(d_ff_Yn[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(first_mux_Y[16]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1754), .Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(d_ff2_Y[16]), .CK(reg_shift_y_net3561862), .RN(n1754), .Q(d_ff3_sh_y_out[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Zn_net3561862), .RN(n1754), .Q(d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(first_mux_Z[16]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1753), .Q(d_ff2_Z[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1711), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1711),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1632), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1729), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n1597) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Xn_net3561862), .RN(n1753), .Q(d_ff_Xn[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(first_mux_X[8]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1753), .Q(d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(d_ff2_X[8]), .CK(reg_shift_y_net3561862),
.RN(n1753), .Q(d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Yn_net3561862), .RN(n1753), .Q(d_ff_Yn[8]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(first_mux_Y[8]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1753), .Q(d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(d_ff2_Y[8]), .CK(reg_shift_y_net3561862),
.RN(n1753), .Q(d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Zn_net3561862), .RN(n1753), .Q(d_ff_Zn[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(first_mux_Z[8]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1753), .Q(d_ff2_Z[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1712), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1712),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1631), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1729), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n1599) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Xn_net3561862), .RN(n1752), .Q(d_ff_Xn[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(first_mux_X[11]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1752), .Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(d_ff2_X[11]), .CK(reg_shift_y_net3561862), .RN(n1752), .Q(d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Yn_net3561862), .RN(n1752), .Q(d_ff_Yn[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(first_mux_Y[11]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1752), .Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(d_ff2_Y[11]), .CK(reg_shift_y_net3561862), .RN(n1752), .Q(d_ff3_sh_y_out[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Zn_net3561862), .RN(n1752), .Q(d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(first_mux_Z[11]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1752), .Q(d_ff2_Z[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1713), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1713),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1730), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n1627) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Xn_net3561862), .RN(n1752), .Q(d_ff_Xn[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(first_mux_X[14]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1751), .Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(d_ff2_X[14]), .CK(reg_shift_y_net3561862), .RN(n1751), .Q(d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Yn_net3561862), .RN(n1751), .Q(d_ff_Yn[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(first_mux_Y[14]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1751), .Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(d_ff2_Y[14]), .CK(reg_shift_y_net3561862), .RN(n1751), .Q(d_ff3_sh_y_out[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Zn_net3561862), .RN(n1751), .Q(d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(first_mux_Z[14]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1751), .Q(d_ff2_Z[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1713), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1713),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Xn_net3561862), .RN(n1751), .Q(d_ff_Xn[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(first_mux_X[10]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1751), .Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(d_ff2_X[10]), .CK(reg_shift_y_net3561862), .RN(n1750), .Q(d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Yn_net3561862), .RN(n1750), .Q(d_ff_Yn[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(first_mux_Y[10]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1750), .Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(d_ff2_Y[10]), .CK(reg_shift_y_net3561862), .RN(n1750), .Q(d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Zn_net3561862), .RN(n1750), .Q(d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(first_mux_Z[10]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1750), .Q(d_ff2_Z[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1714), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1714),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1629), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1729), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n1605) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Xn_net3561862), .RN(n1750), .Q(d_ff_Xn[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(first_mux_X[12]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1750), .Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(d_ff2_X[12]), .CK(reg_shift_y_net3561862), .RN(n1750), .Q(d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Yn_net3561862), .RN(n1749), .Q(d_ff_Yn[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(first_mux_Y[12]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1749), .Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(d_ff2_Y[12]), .CK(reg_shift_y_net3561862), .RN(n1749), .Q(d_ff3_sh_y_out[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Zn_net3561862), .RN(n1749), .Q(d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(first_mux_Z[12]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1749), .Q(d_ff2_Z[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_INIT), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1714), .Q(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1714),
.Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1715),
.Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1715), .Q(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1715),
.Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n1715), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Xn_net3561862), .RN(n1749), .Q(d_ff_Xn[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(first_mux_X[31]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1749), .Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(d_ff2_X[31]), .CK(reg_shift_y_net3561862), .RN(n1749), .Q(d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Yn_net3561862), .RN(n1749), .Q(d_ff_Yn[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(first_mux_Y[31]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1748), .Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(d_ff2_Y[31]), .CK(reg_shift_y_net3561862), .RN(n1748), .Q(d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Zn_net3561862), .RN(n1748), .Q(d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(first_mux_Z[31]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1748), .Q(d_ff2_Z[31]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(d_ff2_Z[31]), .CK(reg_shift_y_net3561862),
.RN(n1748), .Q(d_ff3_sign_out) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_INIT), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1715), .Q(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1730),
.Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1730),
.Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1726),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1727),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]) );
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1727),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n1719), .Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n801),
.Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n1721), .Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n804),
.Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1732),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[51]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1732),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n800),
.Q(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Xn_net3561862), .RN(n1748), .Q(d_ff_Xn[0]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(first_mux_X[0]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1748), .Q(d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(d_ff2_X[0]), .CK(reg_shift_y_net3561862),
.RN(n1748), .Q(d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Yn_net3561862), .RN(n1748), .Q(d_ff_Yn[0]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(first_mux_Y[0]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1747), .Q(d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(d_ff2_Y[0]), .CK(reg_shift_y_net3561862),
.RN(n1747), .Q(d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Zn_net3561862), .RN(n1747), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(first_mux_Z[0]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1747), .Q(d_ff2_Z[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1719), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1724),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1732), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1732),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1732),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1728), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n1620) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Xn_net3561862), .RN(n1747), .Q(d_ff_Xn[1]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(first_mux_X[1]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1747), .Q(d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(d_ff2_X[1]), .CK(reg_shift_y_net3561862),
.RN(n1747), .Q(d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Yn_net3561862), .RN(n1747), .Q(d_ff_Yn[1]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(first_mux_Y[1]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1747), .Q(d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(d_ff2_Y[1]), .CK(reg_shift_y_net3561862),
.RN(n1746), .Q(d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Zn_net3561862), .RN(n1746), .Q(d_ff_Zn[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(first_mux_Z[1]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1746), .Q(d_ff2_Z[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n800), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1724),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1733), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1733),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1733),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Xn_net3561862), .RN(n1746), .Q(d_ff_Xn[2]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(first_mux_X[2]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1746), .Q(d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(d_ff2_X[2]), .CK(reg_shift_y_net3561862),
.RN(n1746), .Q(d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Yn_net3561862), .RN(n1746), .Q(d_ff_Yn[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(first_mux_Y[2]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1746), .Q(d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(d_ff2_Y[2]), .CK(reg_shift_y_net3561862),
.RN(n1746), .Q(d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Zn_net3561862), .RN(n1745), .Q(d_ff_Zn[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(first_mux_Z[2]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1745), .Q(d_ff2_Z[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n806), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1724),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1733), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1733),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1733),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Xn_net3561862), .RN(n1745), .Q(d_ff_Xn[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(first_mux_X[3]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1745), .Q(d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(d_ff2_X[3]), .CK(reg_shift_y_net3561862),
.RN(n1745), .Q(d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Yn_net3561862), .RN(n1745), .Q(d_ff_Yn[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(first_mux_Y[3]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1745), .Q(d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(d_ff2_Y[3]), .CK(reg_shift_y_net3561862),
.RN(n1745), .Q(d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Zn_net3561862), .RN(n1744), .Q(d_ff_Zn[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(first_mux_Z[3]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1744), .Q(d_ff2_Z[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n801), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1724),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1734), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1734),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1733),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Xn_net3561862), .RN(n1744), .Q(d_ff_Xn[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(first_mux_X[5]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1744), .Q(d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(d_ff2_X[5]), .CK(reg_shift_y_net3561862),
.RN(n1744), .Q(d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Yn_net3561862), .RN(n1744), .Q(d_ff_Yn[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(first_mux_Y[5]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1744), .Q(d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(d_ff2_Y[5]), .CK(reg_shift_y_net3561862),
.RN(n1744), .Q(d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Zn_net3561862), .RN(n1744), .Q(d_ff_Zn[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(first_mux_Z[5]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1743), .Q(d_ff2_Z[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n566), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n804),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .QN(n1648) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1717), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1724),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1734), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1734),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1734),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Xn_net3561862), .RN(n1743), .Q(d_ff_Xn[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(first_mux_X[7]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1743), .Q(d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(d_ff2_X[7]), .CK(reg_shift_y_net3561862),
.RN(n1743), .Q(d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Yn_net3561862), .RN(n1743), .Q(d_ff_Yn[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(first_mux_Y[7]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1743), .Q(d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(d_ff2_Y[7]), .CK(reg_shift_y_net3561862),
.RN(n1743), .Q(d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Zn_net3561862), .RN(n1743), .Q(d_ff_Zn[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(first_mux_Z[7]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1743), .Q(d_ff2_Z[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n568), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1717),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .QN(n1649) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1717), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1717),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1735), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1735),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1735),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1628), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1729), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n1600) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Xn_net3561862), .RN(n1742), .Q(d_ff_Xn[9]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(first_mux_X[9]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1742), .Q(d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(d_ff2_X[9]), .CK(reg_shift_y_net3561862),
.RN(n1742), .Q(d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Yn_net3561862), .RN(n1742), .Q(d_ff_Yn[9]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(first_mux_Y[9]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1742), .Q(d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(d_ff2_Y[9]), .CK(reg_shift_y_net3561862),
.RN(n1742), .Q(d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Zn_net3561862), .RN(n1742), .Q(d_ff_Zn[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(first_mux_Z[9]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1742), .Q(d_ff2_Z[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1717), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1718),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1718), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1736),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1736),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_INIT), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1718), .Q(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1718),
.Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1718),
.Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1718), .Q(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1718),
.Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM), .CK(
inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .RN(n1718), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1718), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1740),
.Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1721), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1737),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1737),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1719), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1736),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1736),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n800), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1737),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1737),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n806), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1736),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1736),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n801), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1736),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1735),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n804), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1738),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1738),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1716), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1737),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1737),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1735), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1735),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1735),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1734), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1734),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1734),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1720), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1738),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1738),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1720), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1739),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1739),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1720), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1739),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1739),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1720), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1739),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1739),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1720), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1739),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1738),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1720), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1738),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1738),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1720),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1720),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1732), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n1697) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_net3561939), .RN(n1720), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_net3561939), .RN(n1740),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_net3561939), .RN(n1740),
.Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]) );
CMPR32X2TS intadd_401_U4 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24]),
.B(n1668), .C(intadd_401_CI), .CO(intadd_401_n3), .S(intadd_401_SUM_0_) );
CMPR32X2TS intadd_401_U3 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]),
.B(n1694), .C(intadd_401_n3), .CO(intadd_401_n2), .S(intadd_401_SUM_1_) );
CMPR32X2TS intadd_401_U2 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26]),
.B(n1693), .C(intadd_401_n2), .CO(intadd_401_n1), .S(intadd_401_SUM_2_) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(reg_shift_y_net3561862), .RN(
n1742), .Q(d_ff3_LUT_out[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1732),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .QN(n1657) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1731),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .QN(n1654) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1727),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n1645) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n1775), .Q(
inst_CORDIC_FSM_v3_state_reg[2]), .QN(n1635) );
DFFRX1TS VAR_CONT_temp_reg_0_ ( .D(n540), .CK(clk), .RN(n1777), .Q(
cont_var_out[0]), .QN(n1612) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n1775), .Q(
inst_CORDIC_FSM_v3_state_reg[1]), .QN(n1607) );
DFFRX2TS ITER_CONT_temp_reg_0_ ( .D(n1596), .CK(ITER_CONT_net3562083), .RN(
n529), .Q(cont_iter_out[0]), .QN(n1596) );
DFFRX2TS ITER_CONT_temp_reg_3_ ( .D(ITER_CONT_N5), .CK(ITER_CONT_net3562083),
.RN(n1776), .Q(cont_iter_out[3]), .QN(n1594) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(ITER_CONT_N4), .CK(ITER_CONT_net3562083),
.RN(n1777), .Q(cont_iter_out[2]), .QN(n1593) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(mux_sal[23]), .CK(
d_ff5_data_out_net3561862), .RN(n1768), .Q(data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(mux_sal[24]), .CK(
d_ff5_data_out_net3561862), .RN(n1768), .Q(data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(mux_sal[25]), .CK(
d_ff5_data_out_net3561862), .RN(n1767), .Q(data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(mux_sal[26]), .CK(
d_ff5_data_out_net3561862), .RN(n1766), .Q(data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(mux_sal[27]), .CK(
d_ff5_data_out_net3561862), .RN(n1766), .Q(data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(mux_sal[28]), .CK(
d_ff5_data_out_net3561862), .RN(n1765), .Q(data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(mux_sal[29]), .CK(
d_ff5_data_out_net3561862), .RN(n1764), .Q(data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(mux_sal[30]), .CK(
d_ff5_data_out_net3561862), .RN(n1764), .Q(data_output[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1716),
.Q(underflow_flag) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_GTComparator_N0), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1740),
.Q(overflow_flag) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(mux_sal[22]), .CK(
d_ff5_data_out_net3561862), .RN(n1763), .Q(data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(mux_sal[15]), .CK(
d_ff5_data_out_net3561862), .RN(n1762), .Q(data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(mux_sal[18]), .CK(
d_ff5_data_out_net3561862), .RN(n1761), .Q(data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(mux_sal[21]), .CK(
d_ff5_data_out_net3561862), .RN(n1760), .Q(data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(mux_sal[19]), .CK(
d_ff5_data_out_net3561862), .RN(n1759), .Q(data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(mux_sal[20]), .CK(
d_ff5_data_out_net3561862), .RN(n1758), .Q(data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(mux_sal[17]), .CK(
d_ff5_data_out_net3561862), .RN(n1757), .Q(data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(mux_sal[4]), .CK(
d_ff5_data_out_net3561862), .RN(n1756), .Q(data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(mux_sal[6]), .CK(
d_ff5_data_out_net3561862), .RN(n1755), .Q(data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(mux_sal[13]), .CK(
d_ff5_data_out_net3561862), .RN(n1755), .Q(data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(mux_sal[16]), .CK(
d_ff5_data_out_net3561862), .RN(n1754), .Q(data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(mux_sal[8]), .CK(
d_ff5_data_out_net3561862), .RN(n1753), .Q(data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(mux_sal[11]), .CK(
d_ff5_data_out_net3561862), .RN(n1752), .Q(data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(mux_sal[14]), .CK(
d_ff5_data_out_net3561862), .RN(n1751), .Q(data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(mux_sal[10]), .CK(
d_ff5_data_out_net3561862), .RN(n1750), .Q(data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(mux_sal[12]), .CK(
d_ff5_data_out_net3561862), .RN(n1749), .Q(data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(fmtted_Result_31_), .CK(
d_ff5_data_out_net3561862), .RN(n1748), .Q(data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(mux_sal[0]), .CK(
d_ff5_data_out_net3561862), .RN(n1747), .Q(data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(mux_sal[1]), .CK(
d_ff5_data_out_net3561862), .RN(n1746), .Q(data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(mux_sal[2]), .CK(
d_ff5_data_out_net3561862), .RN(n1745), .Q(data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(mux_sal[3]), .CK(
d_ff5_data_out_net3561862), .RN(n1745), .Q(data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(mux_sal[5]), .CK(
d_ff5_data_out_net3561862), .RN(n1744), .Q(data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(mux_sal[7]), .CK(
d_ff5_data_out_net3561862), .RN(n1743), .Q(data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(mux_sal[9]), .CK(
d_ff5_data_out_net3561862), .RN(n1742), .Q(data_output[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1718),
.Q(zero_flag) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_5), .CK(
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3562047), .RN(n1700),
.Q(busy) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1726),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n1661) );
CMPR32X2TS DP_OP_33J163_122_2179_U4 ( .A(DP_OP_33J163_122_2179_n28), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]), .C(
DP_OP_33J163_122_2179_n4), .CO(DP_OP_33J163_122_2179_n3), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_33J163_122_2179_U6 ( .A(DP_OP_33J163_122_2179_n15), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]), .C(
DP_OP_33J163_122_2179_n6), .CO(DP_OP_33J163_122_2179_n5), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_33J163_122_2179_U8 ( .A(DP_OP_33J163_122_2179_n17), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]), .C(
DP_OP_33J163_122_2179_n8), .CO(DP_OP_33J163_122_2179_n7), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1726),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFSX4TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(
n1625), .CK(inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_net3561957), .SN(n1716), .Q(DP_OP_33J163_122_2179_n28), .QN(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2) );
DFFSXLTS R_0 ( .D(n1698), .CK(
inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .SN(
n1715), .Q(n1778) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1727),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n1643) );
DFFSX1TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n1777), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_shft_value_mux_o_EWR[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1715),
.Q(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ (
.D(n541), .CK(clk), .RN(n1700), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(
n621), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1704), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1725),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS VAR_CONT_temp_reg_1_ ( .D(n539), .CK(clk), .RN(n1776), .Q(
cont_var_out[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n598), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1716),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .QN(n1663) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n600), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1717),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .QN(n1662) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1726),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1726),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1735), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1735), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1736), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1735), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1734), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n564), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1719),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .QN(n634) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1730),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1730),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1737), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1739), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1739), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1738), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1737), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1736), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1733), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1733), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1733), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1731),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3562047), .RN(n1730),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n1621) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_net3562047), .RN(n1700),
.Q(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(
n603), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1714), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .QN(n1673) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1731),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(
n576), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1707), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .QN(n638) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(
n574), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1711), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .QN(n655) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(
n582), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1708), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .QN(n639) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(
n617), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1703), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .QN(n1674) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(
n609), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1711), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .QN(n1671) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(first_mux_X[27]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1766), .Q(d_ff2_X[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1736), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(first_mux_Y[27]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1766), .Q(d_ff2_Y[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n602), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1717),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .QN(n1680) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(
n620), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1703), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .QN(n1681) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1732), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1740), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1738), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1739), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1738), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1737), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1737), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(
n584), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1702), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .QN(n1650) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1727),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(
n581), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1709), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .QN(n657) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n569), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1712),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .QN(n656) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(
n579), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1707), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .QN(n649) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(
n572), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1712), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .QN(n650) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(
n578), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1709), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .QN(n648) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(
n586), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1702), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .QN(n635) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(
n587), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1702), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .QN(n651) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n596), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n800),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .QN(n1689) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n594), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1719),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .QN(n1688) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n601), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1712),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .QN(n1683) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(
n611), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1707), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .QN(n1685) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(
n608), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1707), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .QN(n1690) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(
n573), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1714), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .QN(n630) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1713),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(
n580), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1708), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .QN(n659) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1716),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1721),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1714),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n563), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n806),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .QN(n652) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(first_mux_X[29]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1765), .Q(d_ff2_X[29]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n562), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n800),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .QN(n636) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(first_mux_Y[29]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1764), .Q(d_ff2_Y[29]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1730), .Q(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n1776), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(operation), .CK(reg_Z0_net3561862),
.RN(n1773), .Q(d_ff1_operation_out) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(
n591), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1702), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .QN(n1637) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(
n623), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1704), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .QN(n1603) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1717),
.Q(result_add_subt[9]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1717),
.Q(result_add_subt[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n801),
.Q(result_add_subt[5]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n804),
.Q(result_add_subt[3]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n806),
.Q(result_add_subt[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n801),
.Q(result_add_subt[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n804),
.Q(result_add_subt[0]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[31]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1715),
.Q(result_add_subt[31]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1714),
.Q(result_add_subt[12]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[10]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1713),
.Q(result_add_subt[10]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1713),
.Q(result_add_subt[14]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[11]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1712),
.Q(result_add_subt[11]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1712),
.Q(result_add_subt[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1711),
.Q(result_add_subt[16]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1710),
.Q(result_add_subt[13]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1710),
.Q(result_add_subt[6]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1710),
.Q(result_add_subt[4]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1709),
.Q(result_add_subt[17]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1709),
.Q(result_add_subt[20]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1708),
.Q(result_add_subt[19]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1708),
.Q(result_add_subt[21]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1707),
.Q(result_add_subt[18]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1707),
.Q(result_add_subt[15]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[22]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1706),
.Q(result_add_subt[22]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[30]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1702),
.Q(result_add_subt[30]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[29]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1702),
.Q(result_add_subt[29]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[28]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1701),
.Q(result_add_subt[28]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[27]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1701),
.Q(result_add_subt[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[26]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1701),
.Q(result_add_subt[26]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[25]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1701),
.Q(result_add_subt[25]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1701),
.Q(result_add_subt[24]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[23]), .CK(
inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_net3561898), .RN(n1701),
.Q(result_add_subt[23]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(first_mux_X[24]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1768), .Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(first_mux_X[26]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1767), .Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(first_mux_X[25]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1767), .Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(first_mux_Y[26]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1766), .Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(first_mux_Y[25]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1767), .Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(first_mux_Y[24]), .CK(
reg_val_muxZ_2stage_net3561862), .RN(n1768), .Q(d_ff2_Y[24]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[18]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1726),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1728), .Q(
inst_FPU_PIPELINED_FPADDSUB_N60), .QN(n1626) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(
n592), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1715), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n719), .CK(inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1729), .Q(
inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .QN(n633) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[3]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1725),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n1653) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1728),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1713),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n597), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1710),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .QN(n1672) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1712),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n599), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1710),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .QN(n1670) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1710),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1712),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ (
.D(n1779), .CK(clk), .RN(n1700), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(
n661) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(
n614), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1708), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .QN(n1676) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(
n606), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1711), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .QN(n1675) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n595), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n804),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .QN(n1677) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[13]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1727),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_shft_value_mux_o_EWR[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n804),
.Q(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n1640) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1731),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .QN(n1659) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(
n1001), .CK(inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921),
.RN(n1706), .Q(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(
n610), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1709), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .QN(n1684) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(
n618), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1703), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .QN(n1686) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(
n619), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1703), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .QN(n1691) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(
n604), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1712), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .QN(n1687) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1731),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .QN(n1667) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(
n585), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1702), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .QN(n653) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_N59), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1725),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[0]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1728), .Q(
inst_FPU_PIPELINED_FPADDSUB_N59), .QN(n1601) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(
n588), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1702), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .QN(n640) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n570), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1717),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .QN(n637) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(
n583), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1707), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .QN(n660) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(
n575), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1713), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .QN(n658) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n1775), .Q(
inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(
n612), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1708), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .QN(n1610) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(
n613), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1709), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .QN(n1678) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(
n605), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1714), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .QN(n1682) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1726),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n1595) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(
n615), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1706), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .QN(n1679) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(
n607), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1713), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .QN(n1611) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n593), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1721),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .QN(n1692) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(shift_region_flag[1]), .CK(
reg_Z0_net3561862), .RN(n1773), .Q(d_ff1_shift_region_flag_out[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(
n590), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1702), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .QN(n1636) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(
n622), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1704), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .QN(n1622) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ (
.D(n625), .CK(clk), .RN(n1700), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1729), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n1614) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1630), .CK(inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1729), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n1598) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1728), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n1616) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1728), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n1619) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1728), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n1618) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[9]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1729), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n1617) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(
n616), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1703), .Q(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .QN(n1609) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(
n577), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1711), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .QN(n1644) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(
n571), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1714), .Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .QN(n1634) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n565), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1710),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .QN(n1606) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n567), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1710),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .QN(n1608) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n561), .CK(inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_net3561898), .RN(n1721),
.Q(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .QN(n654) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1709),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1707),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1711),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1720),
.Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[1]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1725),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n1623) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_shft_value_mux_o_EWR[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_net3561921), .RN(n1729),
.Q(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n647) );
DFFRX2TS ITER_CONT_temp_reg_1_ ( .D(ITER_CONT_N3), .CK(ITER_CONT_net3562083),
.RN(n798), .Q(cont_iter_out[1]), .QN(n1613) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[16]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1726),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[17]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1726),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[19]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1727),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .QN(n1660) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[21]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1727),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n1646) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[14]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1726),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n1602) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[8]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1728),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[2]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1728), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n1624) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[24]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1727),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .QN(n1647) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4]), .CK(
inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_net3561939), .RN(n1734), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[20]), .CK(
inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_net3561921), .RN(n1727),
.Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]) );
CMPR32X2TS DP_OP_33J163_122_2179_U9 ( .A(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
DP_OP_33J163_122_2179_n28), .C(DP_OP_33J163_122_2179_n18), .CO(
DP_OP_33J163_122_2179_n8), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_33J163_122_2179_U7 ( .A(DP_OP_33J163_122_2179_n16), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]), .C(
DP_OP_33J163_122_2179_n7), .CO(DP_OP_33J163_122_2179_n6), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_33J163_122_2179_U5 ( .A(DP_OP_33J163_122_2179_n14), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]), .C(
DP_OP_33J163_122_2179_n5), .CO(DP_OP_33J163_122_2179_n4), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_33J163_122_2179_U3 ( .A(DP_OP_33J163_122_2179_n28), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]), .C(
DP_OP_33J163_122_2179_n3), .CO(DP_OP_33J163_122_2179_n2), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_33J163_122_2179_U2 ( .A(DP_OP_33J163_122_2179_n28), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]), .C(
DP_OP_33J163_122_2179_n2), .CO(DP_OP_33J163_122_2179_n1), .S(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS intadd_400_U4 ( .A(d_ff2_Y[24]), .B(n662), .C(intadd_400_CI),
.CO(intadd_400_n3), .S(sh_exp_y[1]) );
CMPR32X2TS intadd_399_U4 ( .A(n662), .B(d_ff2_X[24]), .C(intadd_399_CI),
.CO(intadd_399_n3), .S(sh_exp_x[1]) );
CMPR32X2TS intadd_400_U3 ( .A(d_ff2_Y[25]), .B(n1593), .C(intadd_400_n3),
.CO(intadd_400_n2), .S(sh_exp_y[2]) );
CMPR32X2TS intadd_399_U3 ( .A(d_ff2_X[25]), .B(n1593), .C(intadd_399_n3),
.CO(intadd_399_n2), .S(sh_exp_x[2]) );
CMPR32X2TS intadd_400_U2 ( .A(d_ff2_Y[26]), .B(n1594), .C(intadd_400_n2),
.CO(intadd_400_n1), .S(sh_exp_y[3]) );
CMPR32X2TS intadd_399_U2 ( .A(d_ff2_X[26]), .B(n1594), .C(intadd_399_n2),
.CO(intadd_399_n1), .S(sh_exp_x[3]) );
INVX3TS U982 ( .A(n1501), .Y(n1506) );
AOI222X1TS U983 ( .A0(n846), .A1(d_ff2_X[30]), .B0(n845), .B1(d_ff2_Y[30]),
.C0(n887), .C1(d_ff2_Z[30]), .Y(n844) );
NAND2X1TS U984 ( .A(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
n661), .Y(n1581) );
AOI21X2TS U985 ( .A0(n1247), .A1(n1246), .B0(n774), .Y(n1255) );
INVX2TS U986 ( .A(n1026), .Y(n1514) );
AOI222X4TS U987 ( .A0(n1586), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n1699), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n1002), .Y(
n1053) );
INVX4TS U988 ( .A(n677), .Y(n632) );
OR2X2TS U989 ( .A(cont_iter_out[2]), .B(n1485), .Y(n688) );
CLKINVX6TS U990 ( .A(n724), .Y(n677) );
INVX2TS U991 ( .A(n1487), .Y(n1531) );
NOR2X6TS U992 ( .A(n734), .B(n733), .Y(n1026) );
NOR2X1TS U993 ( .A(n995), .B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM),
.Y(n719) );
NOR2X1TS U994 ( .A(n1315), .B(n1317), .Y(n1100) );
OAI21X1TS U995 ( .A0(n1361), .A1(n1369), .B0(n1362), .Y(n1339) );
OAI21X1TS U996 ( .A0(n1371), .A1(n1106), .B0(n1105), .Y(n1353) );
NOR2XLTS U997 ( .A(n1462), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]),
.Y(n1463) );
NOR2XLTS U998 ( .A(n1655), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .Y(
n1227) );
OR2X1TS U999 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B(
n872), .Y(n646) );
AOI21X2TS U1000 ( .A0(n1163), .A1(n1162), .B0(n1161), .Y(n1187) );
OAI21XLTS U1001 ( .A0(n713), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(n1647), .Y(n714) );
NOR2X1TS U1002 ( .A(n917), .B(n914), .Y(n915) );
NAND2BX1TS U1003 ( .AN(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(
n1377) );
OAI21XLTS U1004 ( .A0(n1048), .A1(n681), .B0(n736), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]) );
OAI21XLTS U1005 ( .A0(ack_cordic), .A1(n858), .B0(n848), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
OAI21XLTS U1006 ( .A0(n686), .A1(n1074), .B0(n876), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[0]) );
OAI21XLTS U1007 ( .A0(n1024), .A1(n632), .B0(n758), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]) );
NOR2XLTS U1008 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_GTComparator_N0), .B(
n917), .Y(inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[30]) );
OAI21XLTS U1009 ( .A0(n1053), .A1(n680), .B0(n1031), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]) );
OAI21XLTS U1010 ( .A0(n1058), .A1(n681), .B0(n1057), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]) );
OAI21XLTS U1011 ( .A0(n1041), .A1(n681), .B0(n1007), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]) );
OAI21XLTS U1012 ( .A0(n1046), .A1(n681), .B0(n1045), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]) );
NOR2XLTS U1013 ( .A(n819), .B(n551), .Y(ITER_CONT_N5) );
OAI21XLTS U1014 ( .A0(n982), .A1(n686), .B0(n880), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[25]) );
OAI21XLTS U1015 ( .A0(n1575), .A1(n1613), .B0(n1577), .Y(n548) );
NOR2X2TS U1016 ( .A(n1538), .B(n1537), .Y(n631) );
BUFX3TS U1017 ( .A(n1508), .Y(n1501) );
OAI21X1TS U1018 ( .A0(n1053), .A1(n632), .B0(n1040), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]) );
INVX4TS U1019 ( .A(n677), .Y(n678) );
AO22X1TS U1020 ( .A0(n1017), .A1(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[3]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]), .B1(n1586), .Y(
inst_FPU_PIPELINED_FPADDSUB_shft_value_mux_o_EWR[3]) );
AO22X1TS U1021 ( .A0(n1017), .A1(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[4]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n1586), .Y(
inst_FPU_PIPELINED_FPADDSUB_shft_value_mux_o_EWR[4]) );
NOR2X4TS U1022 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
n707), .Y(n789) );
OR2X4TS U1023 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_GTComparator_N0), .Y(
n641) );
BUFX6TS U1024 ( .A(n1501), .Y(n1507) );
BUFX8TS U1025 ( .A(n1482), .Y(n1508) );
AOI32X4TS U1026 ( .A0(n1481), .A1(n1480), .A2(n1479), .B0(n1478), .B1(n1481),
.Y(n1482) );
OAI21X1TS U1027 ( .A0(beg_fsm_cordic), .A1(n1536), .B0(n859), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
OAI21X1TS U1028 ( .A0(n1309), .A1(n1308), .B0(n1307), .Y(n1312) );
OAI21X1TS U1029 ( .A0(n1589), .A1(n1696), .B0(n1588), .Y(sh_exp_y[5]) );
OAI21X1TS U1030 ( .A0(n1592), .A1(n1695), .B0(n1591), .Y(sh_exp_x[5]) );
INVX4TS U1031 ( .A(n1519), .Y(n1517) );
INVX4TS U1032 ( .A(n1519), .Y(n1515) );
INVX4TS U1033 ( .A(n813), .Y(n1533) );
INVX1TS U1034 ( .A(n1059), .Y(n1062) );
INVX3TS U1035 ( .A(n1086), .Y(n868) );
NAND3X1TS U1036 ( .A(n1683), .B(n1442), .C(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .Y(n1443) );
NOR2X1TS U1037 ( .A(n1656), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .Y(
n1199) );
OAI21X1TS U1038 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1(n1676), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .Y(n1461) );
OAI21X1TS U1039 ( .A0(n642), .A1(n676), .B0(n1034), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]) );
OAI21X1TS U1040 ( .A0(n1047), .A1(n681), .B0(n994), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]) );
OAI21X1TS U1041 ( .A0(n988), .A1(n681), .B0(n987), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]) );
OAI21X1TS U1042 ( .A0(n1024), .A1(n723), .B0(n1022), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]) );
OAI21X1TS U1043 ( .A0(n1042), .A1(n680), .B0(n1000), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]) );
OAI21X1TS U1044 ( .A0(n1014), .A1(n680), .B0(n1013), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]) );
OAI21X1TS U1045 ( .A0(n1011), .A1(n680), .B0(n1010), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]) );
OAI21X1TS U1046 ( .A0(n1054), .A1(n681), .B0(n1027), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]) );
OAI21X1TS U1047 ( .A0(n1011), .A1(n678), .B0(n750), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]) );
OAI21X1TS U1048 ( .A0(n1038), .A1(n681), .B0(n753), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]) );
OAI21X1TS U1049 ( .A0(n1035), .A1(n680), .B0(n748), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]) );
OAI21X1TS U1050 ( .A0(n1041), .A1(n678), .B0(n1037), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]) );
OAI21X1TS U1051 ( .A0(n1052), .A1(n680), .B0(n1051), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]) );
OAI21X1TS U1052 ( .A0(n642), .A1(n680), .B0(n919), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]) );
OAI211X1TS U1053 ( .A0(n1052), .A1(n687), .B0(n988), .C0(n926), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]) );
OAI31X1TS U1054 ( .A0(n786), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .A2(n785), .B0(n784), .Y(n793) );
NAND2BX1TS U1055 ( .AN(n911), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n784) );
AOI21X2TS U1056 ( .A0(n1208), .A1(n1207), .B0(n772), .Y(n1184) );
INVX2TS U1057 ( .A(n694), .Y(n695) );
AOI21X2TS U1058 ( .A0(n1264), .A1(n1263), .B0(n771), .Y(n1217) );
AOI31X1TS U1059 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]),
.A1(n711), .A2(n1645), .B0(n710), .Y(n706) );
NAND3BX1TS U1060 ( .AN(n913), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n914) );
OAI21X2TS U1061 ( .A0(n1273), .A1(n1270), .B0(n1271), .Y(n1264) );
AOI21X2TS U1062 ( .A0(n1281), .A1(n1280), .B0(n770), .Y(n1273) );
OAI21X1TS U1063 ( .A0(n685), .A1(n1074), .B0(n871), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[1]) );
AOI31X1TS U1064 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]),
.A1(n715), .A2(n700), .B0(n1061), .Y(n705) );
NAND3BX1TS U1065 ( .AN(n912), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n913) );
AOI21X2TS U1066 ( .A0(n1298), .A1(n1297), .B0(n769), .Y(n1290) );
NOR2X1TS U1067 ( .A(d_ff2_Y[29]), .B(n1588), .Y(n1587) );
OAI21X1TS U1068 ( .A0(n1654), .A1(n1086), .B0(n1085), .Y(n1087) );
NOR2X1TS U1069 ( .A(d_ff2_X[29]), .B(n1591), .Y(n1590) );
NAND3X1TS U1070 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n912) );
AOI21X2TS U1071 ( .A0(n1002), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .B0(n918), .Y(n642)
);
OAI21X1TS U1072 ( .A0(n1086), .A1(n929), .B0(n780), .Y(n781) );
OAI21X1TS U1073 ( .A0(n1086), .A1(n931), .B0(n778), .Y(n779) );
OAI21X2TS U1074 ( .A0(n1156), .A1(n1153), .B0(n1154), .Y(n1298) );
OAI21X1TS U1075 ( .A0(n1086), .A1(n1657), .B0(n1079), .Y(n1080) );
INVX2TS U1076 ( .A(n1524), .Y(n1516) );
BUFX3TS U1077 ( .A(n1531), .Y(n1528) );
INVX2TS U1078 ( .A(n1524), .Y(n1520) );
AOI21X2TS U1079 ( .A0(n1137), .A1(n768), .B0(n767), .Y(n1156) );
OAI2BB2XLTS U1080 ( .B0(n1447), .B1(n1455), .A0N(n1446), .A1N(n1445), .Y(
n1451) );
INVX2TS U1081 ( .A(n1524), .Y(n1535) );
INVX2TS U1082 ( .A(n1524), .Y(n1522) );
OAI21X1TS U1083 ( .A0(n1533), .A1(n1643), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n918) );
NAND3BX1TS U1084 ( .AN(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]),
.B(n715), .C(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(
n716) );
INVX3TS U1085 ( .A(n813), .Y(n1017) );
INVX3TS U1086 ( .A(n813), .Y(n1002) );
NAND3X1TS U1087 ( .A(n1541), .B(n1077), .C(n1538), .Y(n1585) );
INVX2TS U1088 ( .A(n1579), .Y(n1578) );
NAND3X1TS U1089 ( .A(n1741), .B(n1574), .C(n1544), .Y(n848) );
OAI21X1TS U1090 ( .A0(n1541), .A1(n1553), .B0(n854), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
INVX1TS U1091 ( .A(n1539), .Y(n1542) );
NOR2X1TS U1092 ( .A(n1139), .B(n1140), .Y(n768) );
OAI211X1TS U1093 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .A1(n1683), .B0(n1442), .C0(n1445), .Y(n1457) );
AOI222X1TS U1094 ( .A0(n901), .A1(d_ff2_X[25]), .B0(n845), .B1(d_ff2_Y[25]),
.C0(n896), .C1(d_ff2_Z[25]), .Y(n840) );
AOI222X1TS U1095 ( .A0(n1545), .A1(d_ff2_X[26]), .B0(n845), .B1(d_ff2_Y[26]),
.C0(n896), .C1(d_ff2_Z[26]), .Y(n847) );
NAND3BX1TS U1096 ( .AN(inst_CORDIC_FSM_v3_state_reg[0]), .B(
inst_CORDIC_FSM_v3_state_reg[3]), .C(n855), .Y(n854) );
AOI21X2TS U1097 ( .A0(n1339), .A1(n760), .B0(n759), .Y(n1098) );
OAI211X2TS U1098 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .A1(
n1682), .B0(n1453), .C0(n1438), .Y(n1455) );
INVX2TS U1099 ( .A(n1153), .Y(n1155) );
NAND3X1TS U1100 ( .A(n1691), .B(n1416), .C(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .Y(n1418) );
NOR2X1TS U1101 ( .A(n1440), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]),
.Y(n1441) );
OAI221XLTS U1102 ( .A0(n637), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]),
.B0(n650), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .C0(n1382),
.Y(n1383) );
OAI221XLTS U1103 ( .A0(n1497), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .B0(n1496), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .C0(n1388), .Y(
n1393) );
OAI221XLTS U1104 ( .A0(n636), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]),
.B0(n654), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .C0(n1390),
.Y(n1391) );
OAI21X1TS U1105 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1(n1448), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .Y(n1449) );
OAI221XLTS U1106 ( .A0(n649), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .B0(n1636), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .C0(n1396), .Y(
n1401) );
OAI221XLTS U1107 ( .A0(n635), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .B0(n653), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .C0(n1398), .Y(
n1399) );
OAI211X2TS U1108 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .A1(
n1678), .B0(n1473), .C0(n1458), .Y(n1467) );
NOR2X1TS U1109 ( .A(n1544), .B(n814), .Y(ITER_CONT_N3) );
NAND2X2TS U1110 ( .A(n702), .B(n701), .Y(n905) );
NOR2X1TS U1111 ( .A(n1476), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]),
.Y(n1415) );
INVX3TS U1112 ( .A(n663), .Y(n665) );
OAI221XLTS U1113 ( .A0(n656), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]),
.B0(n639), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .C0(n1404),
.Y(n1409) );
OR2X2TS U1114 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B(
n941), .Y(n645) );
NOR2X4TS U1115 ( .A(n1091), .B(n877), .Y(n878) );
OAI21X1TS U1116 ( .A0(d_ff1_operation_out), .A1(
d_ff1_shift_region_flag_out[1]), .B0(n1488), .Y(n1486) );
INVX3TS U1117 ( .A(n1546), .Y(n1567) );
CLKAND2X2TS U1118 ( .A(n1642), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]),
.Y(n1196) );
OAI21X1TS U1119 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .A1(n1609), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .Y(n1469) );
NAND2BX1TS U1120 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .Y(n1474) );
NAND2BX1TS U1121 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .Y(n1442) );
NAND2BX1TS U1122 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .Y(n1464) );
NAND2BX1TS U1123 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .Y(n1458) );
NAND2BX1TS U1124 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .Y(n1417) );
NAND2BX1TS U1125 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .Y(n1416) );
NAND2BX1TS U1126 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .Y(n1438) );
NAND2BX1TS U1127 ( .AN(n1669), .B(n808), .Y(n797) );
INVX3TS U1128 ( .A(n1546), .Y(n830) );
NOR3X4TS U1129 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n906) );
CLKAND2X2TS U1130 ( .A(n1605), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]),
.Y(n1188) );
OR2X4TS U1131 ( .A(n1612), .B(cont_var_out[1]), .Y(n1546) );
NAND3BX1TS U1132 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(n1635), .C(n1607), .Y(n818) );
NOR2X4TS U1133 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n702) );
NAND4X4TS U1134 ( .A(n910), .B(n718), .C(n717), .D(n716), .Y(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[0]) );
OAI21X1TS U1135 ( .A0(n1020), .A1(n680), .B0(n1019), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]) );
OAI21X4TS U1136 ( .A0(n1184), .A1(n1181), .B0(n1182), .Y(n1225) );
OAI21X2TS U1137 ( .A0(n1220), .A1(n1199), .B0(n1198), .Y(n1211) );
AOI21X4TS U1138 ( .A0(n1240), .A1(n1239), .B0(n1238), .Y(n1250) );
OAI21X2TS U1139 ( .A0(n1228), .A1(n1227), .B0(n1226), .Y(n1240) );
CLKAND2X2TS U1140 ( .A(n1666), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]),
.Y(n1238) );
AOI21X2TS U1141 ( .A0(n1211), .A1(n1201), .B0(n1200), .Y(n1228) );
CLKAND2X2TS U1142 ( .A(n1658), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]),
.Y(n1200) );
AOI21X2TS U1143 ( .A0(n1284), .A1(n1193), .B0(n1192), .Y(n1276) );
CLKAND2X2TS U1144 ( .A(n1627), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]),
.Y(n1192) );
NAND2BXLTS U1145 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .Y(n1428) );
NAND2BXLTS U1146 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .Y(n1444) );
OAI21X2TS U1147 ( .A0(n1127), .A1(n1118), .B0(n1117), .Y(n1163) );
NOR2X1TS U1148 ( .A(n1131), .B(n1114), .Y(n1116) );
OAI21X2TS U1149 ( .A0(n1098), .A1(n764), .B0(n763), .Y(n1137) );
NOR2X1TS U1150 ( .A(n1123), .B(n1101), .Y(n762) );
NAND2X1TS U1151 ( .A(n1305), .B(n1170), .Y(n1139) );
AOI21X1TS U1152 ( .A0(n1173), .A1(n1147), .B0(n1146), .Y(n1160) );
CLKAND2X2TS U1153 ( .A(n1600), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]),
.Y(n1146) );
NAND2X1TS U1154 ( .A(n1172), .B(n1147), .Y(n1157) );
AOI221X1TS U1155 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .A1(
n1603), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .B1(n1622),
.C0(n1421), .Y(n1423) );
AOI211X1TS U1156 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .A1(
n1509), .B0(n1422), .C0(n1420), .Y(n1475) );
AOI211X1TS U1157 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .A1(
n1644), .B0(n1467), .C0(n1468), .Y(n1459) );
INVX2TS U1158 ( .A(n789), .Y(n787) );
OAI221X1TS U1159 ( .A0(n640), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B0(n659), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .C0(n1397), .Y(
n1400) );
OAI221X1TS U1160 ( .A0(n1499), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .B0(n658), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .C0(n1387), .Y(
n1394) );
OAI221X1TS U1161 ( .A0(n657), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B0(n1637), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .C0(n1403), .Y(
n1410) );
OR2X1TS U1162 ( .A(n1081), .B(n1088), .Y(n1090) );
AND3X1TS U1163 ( .A(n732), .B(n731), .C(n730), .Y(n1011) );
INVX2TS U1164 ( .A(n1331), .Y(n1332) );
INVX2TS U1165 ( .A(n1330), .Y(n1333) );
AND3X1TS U1166 ( .A(n728), .B(n727), .C(n726), .Y(n1014) );
OAI21XLTS U1167 ( .A0(n1306), .A1(n1168), .B0(n1304), .Y(n1171) );
OAI21XLTS U1168 ( .A0(n1309), .A1(n1175), .B0(n1174), .Y(n1178) );
INVX2TS U1169 ( .A(n1173), .Y(n1174) );
INVX2TS U1170 ( .A(n1172), .Y(n1175) );
AND3X1TS U1171 ( .A(n739), .B(n738), .C(n737), .Y(n1035) );
AND3X1TS U1172 ( .A(n756), .B(n755), .C(n754), .Y(n1046) );
INVX4TS U1173 ( .A(n1030), .Y(n675) );
AND3X1TS U1174 ( .A(n998), .B(n997), .C(n996), .Y(n1042) );
AND3X1TS U1175 ( .A(n1005), .B(n1004), .C(n1003), .Y(n1041) );
OAI21XLTS U1176 ( .A0(n1323), .A1(n1131), .B0(n1130), .Y(n1134) );
INVX2TS U1177 ( .A(n1315), .Y(n1328) );
INVX2TS U1178 ( .A(n1339), .Y(n1352) );
OAI21XLTS U1179 ( .A0(n1352), .A1(n1349), .B0(n1350), .Y(n1343) );
XOR2X1TS U1180 ( .A(DP_OP_33J163_122_2179_n28), .B(n689), .Y(
DP_OP_33J163_122_2179_n18) );
XNOR2X2TS U1181 ( .A(DP_OP_33J163_122_2179_n1), .B(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n916) );
OAI21XLTS U1182 ( .A0(n1306), .A1(n1139), .B0(n1138), .Y(n1143) );
OAI21XLTS U1183 ( .A0(n1309), .A1(n1157), .B0(n1160), .Y(n1150) );
AND3X1TS U1184 ( .A(n746), .B(n745), .C(n744), .Y(n1513) );
INVX2TS U1185 ( .A(n1026), .Y(n687) );
AND3X1TS U1186 ( .A(n743), .B(n742), .C(n741), .Y(n1512) );
OAI21X1TS U1187 ( .A0(n1293), .A1(n1191), .B0(n1190), .Y(n1284) );
NOR2XLTS U1188 ( .A(n1604), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .Y(
n1191) );
INVX4TS U1189 ( .A(n1030), .Y(n676) );
AND3X1TS U1190 ( .A(n722), .B(n721), .C(n720), .Y(n1048) );
AND3X1TS U1191 ( .A(n985), .B(n984), .C(n983), .Y(n1047) );
AND3X1TS U1192 ( .A(n922), .B(n921), .C(n920), .Y(n1052) );
AOI2BB1XLTS U1193 ( .A0N(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .A1N(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_GTComparator_N0), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[31]) );
MX2X1TS U1194 ( .A(n1261), .B(n1260), .S0(n1324), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[25]) );
AOI2BB2XLTS U1195 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .B1(
n1431), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .A1N(n1430),
.Y(n1432) );
OAI21XLTS U1196 ( .A0(n1114), .A1(n1130), .B0(n1113), .Y(n1115) );
OAI21XLTS U1197 ( .A0(n1101), .A1(n1124), .B0(n1102), .Y(n761) );
OAI21X1TS U1198 ( .A0(n1145), .A1(n1307), .B0(n1144), .Y(n1173) );
NOR2X1TS U1199 ( .A(n1308), .B(n1145), .Y(n1172) );
INVX2TS U1200 ( .A(ready_add_subt), .Y(n1538) );
INVX2TS U1201 ( .A(n1101), .Y(n1103) );
INVX2TS U1202 ( .A(n1123), .Y(n1125) );
INVX2TS U1203 ( .A(n1317), .Y(n1319) );
INVX2TS U1204 ( .A(n1327), .Y(n1316) );
INVX2TS U1205 ( .A(n1349), .Y(n1351) );
CLKAND2X2TS U1206 ( .A(n1665), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]),
.Y(n1256) );
INVX2TS U1207 ( .A(n1340), .Y(n1342) );
CLKBUFX2TS U1208 ( .A(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .Y(n1374) );
INVX2TS U1209 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(
n917) );
INVX2TS U1210 ( .A(n1140), .Y(n1142) );
AOI2BB2X1TS U1211 ( .B0(n1424), .B1(n1475), .A0N(n1423), .A1N(n1422), .Y(
n1481) );
NAND4XLTS U1212 ( .A(n1414), .B(n1413), .C(n1412), .D(n1411), .Y(n1483) );
AO22XLTS U1213 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .A1(
n670), .B0(n673), .B1(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]),
.Y(n1082) );
AO22XLTS U1214 ( .A0(n670), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .B0(n673), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .Y(n1089) );
BUFX3TS U1215 ( .A(n1507), .Y(n1493) );
INVX2TS U1216 ( .A(n1508), .Y(n1502) );
NAND2BXLTS U1217 ( .AN(busy), .B(n1586), .Y(
inst_FPU_PIPELINED_FPADDSUB__6_net_) );
MX2X1TS U1218 ( .A(inst_FPU_PIPELINED_FPADDSUB_N60), .B(n1375), .S0(n1374),
.Y(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[1]) );
AOI222X1TS U1219 ( .A0(n846), .A1(d_ff2_X[29]), .B0(n845), .B1(d_ff2_Y[29]),
.C0(n887), .C1(d_ff2_Z[29]), .Y(n843) );
MX2X1TS U1220 ( .A(n1338), .B(n1337), .S0(n1374), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[6]) );
AOI222X1TS U1221 ( .A0(n1571), .A1(d_ff2_X[27]), .B0(n845), .B1(d_ff2_Y[27]),
.C0(n887), .C1(d_ff2_Z[27]), .Y(n842) );
AOI222X1TS U1222 ( .A0(n1571), .A1(d_ff2_X[24]), .B0(n845), .B1(d_ff2_Y[24]),
.C0(n896), .C1(d_ff2_Z[24]), .Y(n841) );
AO22XLTS U1223 ( .A0(n1002), .A1(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[2]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]), .B1(n1586), .Y(
inst_FPU_PIPELINED_FPADDSUB_shft_value_mux_o_EWR[2]) );
MX2X1TS U1224 ( .A(n1167), .B(n1166), .S0(n1231), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[13]) );
MX2X1TS U1225 ( .A(n1122), .B(n1121), .S0(n1231), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[9]) );
MX2X1TS U1226 ( .A(n1368), .B(n1367), .S0(n1374), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[3]) );
MX2X1TS U1227 ( .A(n1269), .B(n1268), .S0(n1324), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[18]) );
OR2X1TS U1228 ( .A(d_ff_Xn[25]), .B(n832), .Y(first_mux_X[25]) );
OR2X1TS U1229 ( .A(d_ff_Xn[26]), .B(n832), .Y(first_mux_X[26]) );
OR2X1TS U1230 ( .A(d_ff_Xn[24]), .B(n835), .Y(first_mux_X[24]) );
CLKAND2X2TS U1231 ( .A(n683), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[24]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[22]) );
CLKAND2X2TS U1232 ( .A(n683), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[17]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[15]) );
CLKAND2X2TS U1233 ( .A(n684), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[20]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[18]) );
CLKAND2X2TS U1234 ( .A(n684), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[23]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[21]) );
CLKAND2X2TS U1235 ( .A(n683), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[21]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[19]) );
CLKAND2X2TS U1236 ( .A(n682), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[22]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[20]) );
CLKAND2X2TS U1237 ( .A(n683), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[19]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[17]) );
CLKAND2X2TS U1238 ( .A(n682), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[6]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[4]) );
CLKAND2X2TS U1239 ( .A(n682), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[8]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[6]) );
CLKAND2X2TS U1240 ( .A(n683), .B(n1633), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[13]) );
CLKAND2X2TS U1241 ( .A(n683), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[18]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[16]) );
CLKAND2X2TS U1242 ( .A(n682), .B(n1632), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[8]) );
CLKAND2X2TS U1243 ( .A(n684), .B(n1631), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[11]) );
CLKAND2X2TS U1244 ( .A(n684), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[16]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[14]) );
CLKAND2X2TS U1245 ( .A(n683), .B(n1630), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[10]) );
CLKAND2X2TS U1246 ( .A(n684), .B(n1629), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[12]) );
CLKAND2X2TS U1247 ( .A(n684), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[2]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[0]) );
CLKAND2X2TS U1248 ( .A(n684), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[3]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[1]) );
CLKAND2X2TS U1249 ( .A(n682), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[4]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[2]) );
CLKAND2X2TS U1250 ( .A(n682), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[5]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[3]) );
CLKAND2X2TS U1251 ( .A(n682), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[7]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[5]) );
CLKAND2X2TS U1252 ( .A(n682), .B(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[9]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[7]) );
CLKAND2X2TS U1253 ( .A(n684), .B(n1628), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[9]) );
AO22XLTS U1254 ( .A0(n846), .A1(d_ff3_sh_y_out[30]), .B0(n1566), .B1(
d_ff3_sh_x_out[30]), .Y(n623) );
OR2X1TS U1255 ( .A(d_ff_Xn[29]), .B(n832), .Y(first_mux_X[29]) );
MX2X1TS U1256 ( .A(n1180), .B(n1179), .S0(n1231), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[11]) );
MX2X1TS U1257 ( .A(n1136), .B(n1135), .S0(n1231), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[8]) );
MX2X1TS U1258 ( .A(n1326), .B(n1325), .S0(n1324), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[7]) );
MX2X1TS U1259 ( .A(n1360), .B(n1359), .S0(n1374), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[4]) );
MX2X1TS U1260 ( .A(n1373), .B(n1372), .S0(n1374), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[2]) );
CLKAND2X2TS U1261 ( .A(n1370), .B(n1369), .Y(n1373) );
AO22XLTS U1262 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(
n661), .B1(n1580), .Y(n1582) );
AO22XLTS U1263 ( .A0(n1571), .A1(d_ff3_sh_y_out[31]), .B0(n1566), .B1(
d_ff3_sh_x_out[31]), .Y(n1379) );
MX2X1TS U1264 ( .A(n1314), .B(n1313), .S0(n1324), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[10]) );
MX2X1TS U1265 ( .A(n1348), .B(n1347), .S0(n1374), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[5]) );
AO22XLTS U1266 ( .A0(n1527), .A1(d_ff_Yn[9]), .B0(n1526), .B1(d_ff_Xn[9]),
.Y(mux_sal[9]) );
AO22XLTS U1267 ( .A0(n1525), .A1(d_ff_Yn[7]), .B0(n1526), .B1(d_ff_Xn[7]),
.Y(mux_sal[7]) );
AO22XLTS U1268 ( .A0(n1525), .A1(d_ff_Yn[5]), .B0(n1529), .B1(d_ff_Xn[5]),
.Y(mux_sal[5]) );
AO22XLTS U1269 ( .A0(n1525), .A1(d_ff_Yn[3]), .B0(n1529), .B1(d_ff_Xn[3]),
.Y(mux_sal[3]) );
AO22XLTS U1270 ( .A0(n1525), .A1(d_ff_Yn[2]), .B0(n1529), .B1(d_ff_Xn[2]),
.Y(mux_sal[2]) );
AO22XLTS U1271 ( .A0(n1525), .A1(d_ff_Yn[1]), .B0(n1529), .B1(d_ff_Xn[1]),
.Y(mux_sal[1]) );
AO22XLTS U1272 ( .A0(n1525), .A1(d_ff_Yn[0]), .B0(n1528), .B1(d_ff_Xn[0]),
.Y(mux_sal[0]) );
AO22XLTS U1273 ( .A0(n1527), .A1(d_ff_Yn[12]), .B0(n1526), .B1(d_ff_Xn[12]),
.Y(mux_sal[12]) );
AO22XLTS U1274 ( .A0(n1527), .A1(d_ff_Yn[10]), .B0(n1526), .B1(d_ff_Xn[10]),
.Y(mux_sal[10]) );
AO22XLTS U1275 ( .A0(n1527), .A1(d_ff_Yn[14]), .B0(n1526), .B1(d_ff_Xn[14]),
.Y(mux_sal[14]) );
AO22XLTS U1276 ( .A0(n1527), .A1(d_ff_Yn[11]), .B0(n1526), .B1(d_ff_Xn[11]),
.Y(mux_sal[11]) );
AO22XLTS U1277 ( .A0(n1525), .A1(d_ff_Yn[8]), .B0(n1526), .B1(d_ff_Xn[8]),
.Y(mux_sal[8]) );
AO22XLTS U1278 ( .A0(n1527), .A1(d_ff_Yn[16]), .B0(n1526), .B1(d_ff_Xn[16]),
.Y(mux_sal[16]) );
AO22XLTS U1279 ( .A0(n1527), .A1(d_ff_Yn[13]), .B0(n1526), .B1(d_ff_Xn[13]),
.Y(mux_sal[13]) );
AO22XLTS U1280 ( .A0(n1525), .A1(d_ff_Yn[6]), .B0(n1529), .B1(d_ff_Xn[6]),
.Y(mux_sal[6]) );
AO22XLTS U1281 ( .A0(n1525), .A1(d_ff_Yn[4]), .B0(n1529), .B1(d_ff_Xn[4]),
.Y(mux_sal[4]) );
AO22XLTS U1282 ( .A0(n1527), .A1(d_ff_Yn[17]), .B0(n1528), .B1(d_ff_Xn[17]),
.Y(mux_sal[17]) );
AO22XLTS U1283 ( .A0(n1530), .A1(d_ff_Yn[20]), .B0(n1531), .B1(d_ff_Xn[20]),
.Y(mux_sal[20]) );
AO22XLTS U1284 ( .A0(n1530), .A1(d_ff_Yn[19]), .B0(n1528), .B1(d_ff_Xn[19]),
.Y(mux_sal[19]) );
AO22XLTS U1285 ( .A0(n1530), .A1(d_ff_Yn[21]), .B0(n1529), .B1(d_ff_Xn[21]),
.Y(mux_sal[21]) );
AO22XLTS U1286 ( .A0(n1527), .A1(d_ff_Yn[18]), .B0(n1528), .B1(d_ff_Xn[18]),
.Y(mux_sal[18]) );
AO22XLTS U1287 ( .A0(n1527), .A1(d_ff_Yn[15]), .B0(n1526), .B1(d_ff_Xn[15]),
.Y(mux_sal[15]) );
AO22XLTS U1288 ( .A0(n1530), .A1(d_ff_Yn[22]), .B0(n1528), .B1(d_ff_Xn[22]),
.Y(mux_sal[22]) );
AND2X2TS U1289 ( .A(n916), .B(n915), .Y(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_GTComparator_N0) );
NOR3X6TS U1290 ( .A(n916), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n812), .Y(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0) );
OR4X2TS U1291 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(n811), .Y(n812)
);
AO22XLTS U1292 ( .A0(n1532), .A1(d_ff_Yn[30]), .B0(n1531), .B1(d_ff_Xn[30]),
.Y(mux_sal[30]) );
AO22XLTS U1293 ( .A0(n1532), .A1(d_ff_Yn[29]), .B0(n1531), .B1(d_ff_Xn[29]),
.Y(mux_sal[29]) );
AO22XLTS U1294 ( .A0(n1530), .A1(d_ff_Yn[28]), .B0(n1531), .B1(d_ff_Xn[28]),
.Y(mux_sal[28]) );
AO22XLTS U1295 ( .A0(n1530), .A1(d_ff_Yn[27]), .B0(n1531), .B1(d_ff_Xn[27]),
.Y(mux_sal[27]) );
AO22XLTS U1296 ( .A0(n1530), .A1(d_ff_Yn[26]), .B0(n1531), .B1(d_ff_Xn[26]),
.Y(mux_sal[26]) );
AO22XLTS U1297 ( .A0(n1530), .A1(d_ff_Yn[25]), .B0(n1531), .B1(d_ff_Xn[25]),
.Y(mux_sal[25]) );
AO22XLTS U1298 ( .A0(n1530), .A1(d_ff_Yn[24]), .B0(n1529), .B1(d_ff_Xn[24]),
.Y(mux_sal[24]) );
AO22XLTS U1299 ( .A0(n1530), .A1(d_ff_Yn[23]), .B0(n1528), .B1(d_ff_Xn[23]),
.Y(mux_sal[23]) );
MX2X1TS U1300 ( .A(n1303), .B(n1302), .S0(n1324), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[14]) );
OAI21XLTS U1301 ( .A0(n819), .A1(n1077), .B0(n809), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
MX2X1TS U1302 ( .A(n1152), .B(n1151), .S0(n1231), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[12]) );
OAI222X1TS U1303 ( .A0(n1514), .A1(n642), .B0(n723), .B1(n1513), .C0(n678),
.C1(n1512), .Y(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]) );
AO22XLTS U1304 ( .A0(n1522), .A1(d_ff1_Z[9]), .B0(n1519), .B1(d_ff_Zn[9]),
.Y(first_mux_Z[9]) );
AO22XLTS U1305 ( .A0(n1535), .A1(d_ff1_Z[7]), .B0(n1519), .B1(d_ff_Zn[7]),
.Y(first_mux_Z[7]) );
AO22XLTS U1306 ( .A0(n1518), .A1(d_ff1_Z[5]), .B0(n1519), .B1(d_ff_Zn[5]),
.Y(first_mux_Z[5]) );
OR2X1TS U1307 ( .A(d_ff_Xn[5]), .B(n1518), .Y(first_mux_X[5]) );
AO22XLTS U1308 ( .A0(n1518), .A1(d_ff1_Z[3]), .B0(n1519), .B1(d_ff_Zn[3]),
.Y(first_mux_Z[3]) );
OR2X1TS U1309 ( .A(d_ff_Xn[3]), .B(n1518), .Y(first_mux_X[3]) );
AO22XLTS U1310 ( .A0(n1518), .A1(d_ff1_Z[2]), .B0(n688), .B1(d_ff_Zn[2]),
.Y(first_mux_Z[2]) );
OR2X1TS U1311 ( .A(d_ff_Xn[2]), .B(n1518), .Y(first_mux_X[2]) );
AO22XLTS U1312 ( .A0(n1516), .A1(d_ff1_Z[1]), .B0(n1524), .B1(d_ff_Zn[1]),
.Y(first_mux_Z[1]) );
OR2X1TS U1313 ( .A(d_ff_Xn[1]), .B(n835), .Y(first_mux_X[1]) );
AO22XLTS U1314 ( .A0(n1534), .A1(d_ff1_Z[0]), .B0(n688), .B1(d_ff_Zn[0]),
.Y(first_mux_Z[0]) );
NAND4BX1TS U1315 ( .AN(n788), .B(n706), .C(n705), .D(n704), .Y(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[1]) );
MX2X1TS U1316 ( .A(n1254), .B(n1253), .S0(n1324), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[24]) );
MX2X1TS U1317 ( .A(n1244), .B(n1243), .S0(n1324), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[23]) );
MX2X1TS U1318 ( .A(n1233), .B(n1232), .S0(n1231), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[22]) );
MX2X1TS U1319 ( .A(n1205), .B(n1204), .S0(n1231), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[21]) );
MX2X1TS U1320 ( .A(n1213), .B(n1212), .S0(n1231), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[20]) );
MX2X1TS U1321 ( .A(n1222), .B(n1221), .S0(n1231), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[19]) );
MX2X1TS U1322 ( .A(n1278), .B(n1277), .S0(n1324), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[17]) );
MX2X1TS U1323 ( .A(n1286), .B(n1285), .S0(n1324), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[16]) );
MX2X1TS U1324 ( .A(n1295), .B(n1294), .S0(n1324), .Y(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_SGF[15]) );
AO22XLTS U1325 ( .A0(n1534), .A1(d_ff1_Z[31]), .B0(n1524), .B1(d_ff_Zn[31]),
.Y(first_mux_Z[31]) );
AO22XLTS U1326 ( .A0(n1535), .A1(d_ff1_Z[12]), .B0(n1521), .B1(d_ff_Zn[12]),
.Y(first_mux_Z[12]) );
OR2X1TS U1327 ( .A(d_ff_Xn[12]), .B(n835), .Y(first_mux_X[12]) );
AO22XLTS U1328 ( .A0(n1520), .A1(d_ff1_Z[10]), .B0(n1521), .B1(d_ff_Zn[10]),
.Y(first_mux_Z[10]) );
OR2X1TS U1329 ( .A(d_ff_Xn[10]), .B(n835), .Y(first_mux_X[10]) );
AO22XLTS U1330 ( .A0(n1522), .A1(d_ff1_Z[14]), .B0(n1521), .B1(d_ff_Zn[14]),
.Y(first_mux_Z[14]) );
OR2X1TS U1331 ( .A(d_ff_Xn[14]), .B(n835), .Y(first_mux_X[14]) );
AO22XLTS U1332 ( .A0(n1516), .A1(d_ff1_Z[11]), .B0(n1521), .B1(d_ff_Zn[11]),
.Y(first_mux_Z[11]) );
AO22XLTS U1333 ( .A0(n1518), .A1(d_ff1_Z[8]), .B0(n1519), .B1(d_ff_Zn[8]),
.Y(first_mux_Z[8]) );
AO22XLTS U1334 ( .A0(n1520), .A1(d_ff1_Z[16]), .B0(n1521), .B1(d_ff_Zn[16]),
.Y(first_mux_Z[16]) );
OR2X1TS U1335 ( .A(d_ff_Xn[16]), .B(n835), .Y(first_mux_X[16]) );
AO22XLTS U1336 ( .A0(n1516), .A1(d_ff1_Z[13]), .B0(n1521), .B1(d_ff_Zn[13]),
.Y(first_mux_Z[13]) );
OR2X1TS U1337 ( .A(d_ff_Xn[13]), .B(n832), .Y(first_mux_X[13]) );
AO22XLTS U1338 ( .A0(n1518), .A1(d_ff1_Z[6]), .B0(n1519), .B1(d_ff_Zn[6]),
.Y(first_mux_Z[6]) );
AO22XLTS U1339 ( .A0(n1518), .A1(d_ff1_Z[4]), .B0(n1519), .B1(d_ff_Zn[4]),
.Y(first_mux_Z[4]) );
AO22XLTS U1340 ( .A0(n1535), .A1(d_ff1_Z[17]), .B0(n1521), .B1(d_ff_Zn[17]),
.Y(first_mux_Z[17]) );
OR2X1TS U1341 ( .A(d_ff_Xn[17]), .B(n835), .Y(first_mux_X[17]) );
AO22XLTS U1342 ( .A0(n1534), .A1(d_ff1_Z[20]), .B0(n1523), .B1(d_ff_Zn[20]),
.Y(first_mux_Z[20]) );
OR2X1TS U1343 ( .A(d_ff_Xn[20]), .B(n835), .Y(first_mux_X[20]) );
AO22XLTS U1344 ( .A0(n1534), .A1(d_ff1_Z[19]), .B0(n1521), .B1(d_ff_Zn[19]),
.Y(first_mux_Z[19]) );
OR2X1TS U1345 ( .A(d_ff_Xn[19]), .B(n835), .Y(first_mux_X[19]) );
AO22XLTS U1346 ( .A0(n1516), .A1(d_ff1_Z[21]), .B0(n1523), .B1(d_ff_Zn[21]),
.Y(first_mux_Z[21]) );
AO22XLTS U1347 ( .A0(n1534), .A1(d_ff1_Z[18]), .B0(n1521), .B1(d_ff_Zn[18]),
.Y(first_mux_Z[18]) );
AO22XLTS U1348 ( .A0(n1534), .A1(d_ff1_Z[15]), .B0(n1521), .B1(d_ff_Zn[15]),
.Y(first_mux_Z[15]) );
AO22XLTS U1349 ( .A0(n1522), .A1(d_ff1_Z[22]), .B0(n1523), .B1(d_ff_Zn[22]),
.Y(first_mux_Z[22]) );
AO22XLTS U1350 ( .A0(n1534), .A1(d_ff1_Z[30]), .B0(n1524), .B1(d_ff_Zn[30]),
.Y(first_mux_Z[30]) );
AO22XLTS U1351 ( .A0(n1534), .A1(d_ff1_Z[29]), .B0(n1523), .B1(d_ff_Zn[29]),
.Y(first_mux_Z[29]) );
AO22XLTS U1352 ( .A0(n1534), .A1(d_ff1_Z[28]), .B0(n1523), .B1(d_ff_Zn[28]),
.Y(first_mux_Z[28]) );
OR2X1TS U1353 ( .A(d_ff_Xn[28]), .B(n832), .Y(first_mux_X[28]) );
AO22XLTS U1354 ( .A0(n1534), .A1(d_ff1_Z[27]), .B0(n1523), .B1(d_ff_Zn[27]),
.Y(first_mux_Z[27]) );
AO22XLTS U1355 ( .A0(n1520), .A1(d_ff1_Z[26]), .B0(n1523), .B1(d_ff_Zn[26]),
.Y(first_mux_Z[26]) );
AO22XLTS U1356 ( .A0(n1522), .A1(d_ff1_Z[25]), .B0(n1523), .B1(d_ff_Zn[25]),
.Y(first_mux_Z[25]) );
AO22XLTS U1357 ( .A0(n1535), .A1(d_ff1_Z[24]), .B0(n1523), .B1(d_ff_Zn[24]),
.Y(first_mux_Z[24]) );
AO22XLTS U1358 ( .A0(n1520), .A1(d_ff1_Z[23]), .B0(n1523), .B1(d_ff_Zn[23]),
.Y(first_mux_Z[23]) );
XOR2XLTS U1359 ( .A(intadd_401_n1), .B(n1376), .Y(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[4]) );
OAI31X1TS U1360 ( .A0(cont_iter_out[3]), .A1(cont_iter_out[1]), .A2(n1593),
.B0(n794), .Y(n550) );
OR2X1TS U1361 ( .A(n557), .B(n1578), .Y(n544) );
CLKAND2X2TS U1362 ( .A(n1543), .B(n1594), .Y(n551) );
OAI21XLTS U1363 ( .A0(cont_iter_out[0]), .A1(n1638), .B0(intadd_399_CI), .Y(
sh_exp_x[0]) );
AO21XLTS U1364 ( .A0(intadd_399_n1), .A1(d_ff2_X[27]), .B0(n1592), .Y(
sh_exp_x[4]) );
XOR2XLTS U1365 ( .A(d_ff2_X[30]), .B(n1590), .Y(sh_exp_x[7]) );
OAI21XLTS U1366 ( .A0(cont_iter_out[0]), .A1(n1639), .B0(intadd_400_CI), .Y(
sh_exp_y[0]) );
AO21XLTS U1367 ( .A0(intadd_400_n1), .A1(d_ff2_Y[27]), .B0(n1589), .Y(
sh_exp_y[4]) );
XOR2XLTS U1368 ( .A(d_ff2_Y[30]), .B(n1587), .Y(sh_exp_y[7]) );
NOR2X4TS U1369 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n776) );
INVX2TS U1370 ( .A(n1091), .Y(n1092) );
OA21XLTS U1371 ( .A0(n944), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[51]), .B0(n943), .Y(n643)
);
OA21XLTS U1372 ( .A0(n944), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]), .B0(n943), .Y(n644)
);
INVX2TS U1373 ( .A(cont_iter_out[1]), .Y(n662) );
INVX2TS U1374 ( .A(n647), .Y(n663) );
INVX2TS U1375 ( .A(n663), .Y(n664) );
INVX2TS U1376 ( .A(n1092), .Y(n666) );
INVX2TS U1377 ( .A(n666), .Y(n667) );
INVX2TS U1378 ( .A(n646), .Y(n668) );
INVX2TS U1379 ( .A(n646), .Y(n669) );
INVX2TS U1380 ( .A(n645), .Y(n670) );
INVX2TS U1381 ( .A(n645), .Y(n671) );
INVX2TS U1382 ( .A(n777), .Y(n672) );
INVX2TS U1383 ( .A(n672), .Y(n673) );
INVX2TS U1384 ( .A(n672), .Y(n674) );
INVX2TS U1385 ( .A(n723), .Y(n679) );
INVX2TS U1386 ( .A(n679), .Y(n680) );
INVX2TS U1387 ( .A(n679), .Y(n681) );
INVX2TS U1388 ( .A(n641), .Y(n682) );
INVX2TS U1389 ( .A(n641), .Y(n683) );
INVX2TS U1390 ( .A(n641), .Y(n684) );
OAI21X1TS U1391 ( .A0(n941), .A1(n1657), .B0(n940), .Y(n942) );
OAI21XLTS U1392 ( .A0(cont_iter_out[0]), .A1(n559), .B0(n1579), .Y(n543) );
CLKBUFX3TS U1393 ( .A(n799), .Y(n798) );
OAI221X1TS U1394 ( .A0(n1509), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .B0(n1498), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .C0(n1395), .Y(n1402) );
INVX2TS U1395 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .Y(n1509) );
OAI211X1TS U1396 ( .A0(n1075), .A1(n1074), .B0(n1073), .C0(n1072), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[4]) );
OAI211XLTS U1397 ( .A0(n814), .A1(n795), .B0(n794), .C0(n1485), .Y(n549) );
NAND3X2TS U1398 ( .A(n1594), .B(n1596), .C(n662), .Y(n1485) );
INVX2TS U1399 ( .A(n644), .Y(n685) );
INVX2TS U1400 ( .A(n643), .Y(n686) );
OAI21X2TS U1401 ( .A0(n944), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .B0(n943), .Y(n975)
);
NOR2X4TS U1402 ( .A(n1593), .B(n1594), .Y(n1574) );
NOR2BX2TS U1403 ( .AN(n1541), .B(n1539), .Y(n1580) );
NAND4X2TS U1404 ( .A(n816), .B(n1607), .C(n1635), .D(
inst_CORDIC_FSM_v3_state_reg[4]), .Y(n1541) );
NAND2X4TS U1405 ( .A(n667), .B(n665), .Y(n982) );
BUFX3TS U1406 ( .A(n803), .Y(n804) );
BUFX3TS U1407 ( .A(n803), .Y(n801) );
OAI2BB2XLTS U1408 ( .B0(n1492), .B1(n1636), .A0N(n1494), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[29]) );
OAI21X1TS U1409 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n695), .Y(n696)
);
AOI32X1TS U1410 ( .A0(n1685), .A1(n1464), .A2(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .B1(n1610), .Y(n1465) );
AOI21X2TS U1411 ( .A0(n776), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .B0(n932), .Y(n1070)
);
OAI221X1TS U1412 ( .A0(n634), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]),
.B0(n651), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .C0(n1389),
.Y(n1392) );
BUFX3TS U1413 ( .A(n1716), .Y(n1740) );
OAI221X1TS U1414 ( .A0(n648), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B0(n1503), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .C0(n1405), .Y(
n1408) );
OAI21X2TS U1415 ( .A0(n1602), .A1(n919), .B0(n751), .Y(n1029) );
OAI221X1TS U1416 ( .A0(n1491), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .B0(n652), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .C0(n1381), .Y(n1384) );
AOI211XLTS U1417 ( .A0(n1583), .A1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(
n1580), .C0(n834), .Y(
inst_FPU_PIPELINED_FPADDSUB_enable_Pipeline_input) );
NOR2X1TS U1418 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n786) );
NAND2X4TS U1419 ( .A(n665), .B(n1091), .Y(n1074) );
BUFX3TS U1420 ( .A(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .Y(n1091)
);
CLKBUFX3TS U1421 ( .A(n805), .Y(n802) );
NAND3X2TS U1422 ( .A(n925), .B(n924), .C(n923), .Y(n1050) );
NOR2X4TS U1423 ( .A(n1596), .B(n1613), .Y(n1544) );
AOI21X2TS U1424 ( .A0(n776), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .B0(n930), .Y(n1075)
);
OAI21X2TS U1425 ( .A0(n944), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .B0(n943), .Y(n971)
);
OR2X2TS U1426 ( .A(n944), .B(n776), .Y(n943) );
NOR3X2TS U1427 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(n1635), .C(n856),
.Y(inst_CORDIC_FSM_v3_state_next[3]) );
OR2X1TS U1428 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[23]) );
OR2X1TS U1429 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[25]) );
OR2X1TS U1430 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[26]) );
OR2X1TS U1431 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[27]) );
OR2X1TS U1432 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[28]) );
OR2X1TS U1433 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[29]) );
OAI32X4TS U1434 ( .A0(n690), .A1(d_ff1_operation_out), .A2(
d_ff1_shift_region_flag_out[1]), .B0(d_ff1_shift_region_flag_out[0]),
.B1(n1488), .Y(n1489) );
NOR3BX2TS U1435 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(n833), .Y(ready_cordic) );
OAI221XLTS U1436 ( .A0(n638), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .B0(n655), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .C0(n1380), .Y(
n1385) );
OAI21XLTS U1437 ( .A0(n1574), .A1(cont_iter_out[1]), .B0(n860), .Y(n558) );
AOI21X2TS U1438 ( .A0(cont_iter_out[2]), .A1(n1594), .B0(n810), .Y(n860) );
OAI21X2TS U1439 ( .A0(n1595), .A1(n919), .B0(n725), .Y(n993) );
OAI21X2TS U1440 ( .A0(n813), .A1(n1653), .B0(n740), .Y(n1033) );
NOR2XLTS U1441 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n904) );
BUFX3TS U1442 ( .A(n803), .Y(n806) );
NOR2X4TS U1443 ( .A(n1741), .B(rst), .Y(n803) );
OR2X1TS U1444 ( .A(n1600), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .Y(
n1147) );
OAI21XLTS U1445 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1(n1675), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .Y(n1439) );
OA22X1TS U1446 ( .A0(n1611), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]),
.B0(n1448), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .Y(n1453)
);
AOI21X2TS U1447 ( .A0(n776), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .B0(n942), .Y(n967)
);
AOI21X2TS U1448 ( .A0(n776), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .B0(n936), .Y(n964)
);
NOR2X2TS U1449 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n1349) );
NOR2X2TS U1450 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n1340) );
AOI211X2TS U1451 ( .A0(n776), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B0(n1081), .C0(n873),
.Y(n961) );
AOI211X2TS U1452 ( .A0(n776), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .B0(n1081), .C0(n867),
.Y(n978) );
OAI21XLTS U1453 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .A1(n1431),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .Y(n1430) );
NOR2X1TS U1454 ( .A(n1597), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .Y(
n1145) );
NOR2X4TS U1455 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B(
n694), .Y(n790) );
OAI21XLTS U1456 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n1581), .B0(n1377), .Y(n625) );
OAI211XLTS U1457 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n661), .B0(n1581), .C0(n1377), .Y(n626) );
BUFX3TS U1458 ( .A(n849), .Y(n1557) );
BUFX3TS U1459 ( .A(n881), .Y(n1555) );
OR2X1TS U1460 ( .A(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n689) );
OAI21XLTS U1461 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1(n1688),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .Y(n1427) );
NOR2X4TS U1462 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B(
n785), .Y(n693) );
NAND2X1TS U1463 ( .A(n1617), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .Y(
n1307) );
INVX2TS U1464 ( .A(n908), .Y(n707) );
OR2X1TS U1465 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .Y(n1170) );
INVX2TS U1466 ( .A(n1361), .Y(n1363) );
OAI21X2TS U1467 ( .A0(n1217), .A1(n1214), .B0(n1215), .Y(n1208) );
OAI21X2TS U1468 ( .A0(n1290), .A1(n1287), .B0(n1288), .Y(n1281) );
OAI21XLTS U1469 ( .A0(n1126), .A1(n1123), .B0(n1124), .Y(n1104) );
OAI21XLTS U1470 ( .A0(n1366), .A1(n1355), .B0(n1354), .Y(n1358) );
BUFX3TS U1471 ( .A(n1557), .Y(n881) );
INVX2TS U1472 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .Y(n807) );
NOR2XLTS U1473 ( .A(n1546), .B(n1538), .Y(enab_d_ff4_Yn) );
OR2X1TS U1474 ( .A(d_ff_Xn[7]), .B(n835), .Y(first_mux_X[7]) );
OR2X1TS U1475 ( .A(d_ff_Xn[6]), .B(n1518), .Y(first_mux_X[6]) );
OR2X1TS U1476 ( .A(d_ff_Xn[27]), .B(n832), .Y(first_mux_X[27]) );
OR2X1TS U1477 ( .A(
inst_FPU_PIPELINED_FPADDSUB_array_comparators_LTComparator_N0), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(
inst_FPU_PIPELINED_FPADDSUB_formatted_number_W[24]) );
OAI21XLTS U1478 ( .A0(cont_iter_out[1]), .A1(n1576), .B0(n860), .Y(n556) );
NOR3X2TS U1479 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n1067) );
NOR2X2TS U1480 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n701) );
NOR2BX4TS U1481 ( .AN(n906), .B(n905), .Y(n715) );
INVX2TS U1482 ( .A(n715), .Y(n691) );
NOR2X4TS U1483 ( .A(n691), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n1063) );
NOR2X2TS U1484 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n700) );
INVX2TS U1485 ( .A(n700), .Y(n692) );
NOR2X2TS U1486 ( .A(n692), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(n1059) );
NAND2X4TS U1487 ( .A(n1063), .B(n1059), .Y(n699) );
NOR2X4TS U1488 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .B(
n699), .Y(n698) );
NAND2X4TS U1489 ( .A(n1067), .B(n698), .Y(n785) );
NAND2X4TS U1490 ( .A(n786), .B(n693), .Y(n694) );
NAND2X4TS U1491 ( .A(n790), .B(n1595), .Y(n911) );
NOR3X4TS U1492 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .C(n911), .Y(n908)
);
OA21XLTS U1493 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .B0(n908), .Y(n697)
);
NAND2BX2TS U1494 ( .AN(n697), .B(n696), .Y(n788) );
INVX2TS U1495 ( .A(n698), .Y(n1066) );
NOR2X1TS U1496 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
n1066), .Y(n711) );
NAND2BX1TS U1497 ( .AN(n785), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n1064) );
OAI2BB1X1TS U1498 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]),
.A1N(n715), .B0(n1064), .Y(n710) );
NOR2X2TS U1499 ( .A(n1602), .B(n699), .Y(n1061) );
OAI31X1TS U1500 ( .A0(n1660), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(n701), .Y(n703)
);
NAND2X1TS U1501 ( .A(n703), .B(n702), .Y(n704) );
AOI21X1TS U1502 ( .A0(n1623), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n708) );
OAI22X2TS U1503 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(
n784), .B0(n708), .B1(n787), .Y(n709) );
AOI211X2TS U1504 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]),
.A1(n711), .B0(n710), .C0(n709), .Y(n910) );
NOR4X1TS U1505 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .D(n1066), .Y(n712)
);
AOI22X1TS U1506 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(
n712), .B0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n790),
.Y(n718) );
AOI21X1TS U1507 ( .A0(n1646), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n713) );
AOI21X1TS U1508 ( .A0(n714), .A1(n1643), .B0(n1061), .Y(n717) );
BUFX3TS U1509 ( .A(n1621), .Y(n1015) );
OR2X2TS U1510 ( .A(n1625), .B(n1015), .Y(n919) );
INVX2TS U1511 ( .A(n919), .Y(n1001) );
NAND2X1TS U1512 ( .A(n1023), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n722) );
BUFX3TS U1513 ( .A(n1621), .Y(n995) );
INVX2TS U1514 ( .A(n719), .Y(n813) );
NAND2X1TS U1515 ( .A(n1533), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n721) );
NAND2X1TS U1516 ( .A(n995), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n720) );
AOI22X4TS U1517 ( .A0(n1533), .A1(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[1]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]), .B1(n1015), .Y(
n734) );
OAI22X2TS U1518 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]),
.A1(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[0]), .B1(n813), .Y(n729)
);
NAND2X1TS U1519 ( .A(n734), .B(n729), .Y(n723) );
INVX2TS U1520 ( .A(n729), .Y(n733) );
NAND2X2TS U1521 ( .A(n734), .B(n733), .Y(n724) );
AOI22X1TS U1522 ( .A0(n1002), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n1015), .Y(n725)
);
NAND2X1TS U1523 ( .A(n1023), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n728) );
NAND2X1TS U1524 ( .A(n1533), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n727) );
NAND2X1TS U1525 ( .A(n995), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n726) );
NOR2X4TS U1526 ( .A(n734), .B(n729), .Y(n1030) );
NAND2X1TS U1527 ( .A(n1001), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n732) );
NAND2X1TS U1528 ( .A(n1533), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n731) );
NAND2X1TS U1529 ( .A(n995), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n730) );
OAI22X1TS U1530 ( .A0(n1014), .A1(n675), .B0(n1011), .B1(n687), .Y(n735) );
AOI21X1TS U1531 ( .A0(n677), .A1(n993), .B0(n735), .Y(n736) );
INVX2TS U1532 ( .A(n919), .Y(n1023) );
NAND2X1TS U1533 ( .A(n1001), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n739) );
NAND2X1TS U1534 ( .A(n1002), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n738) );
NAND2X1TS U1535 ( .A(n995), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n737) );
AOI22X1TS U1536 ( .A0(n1699), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n1015), .Y(n740) );
NAND2X1TS U1537 ( .A(n1699), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n743) );
NAND2X1TS U1538 ( .A(n1002), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n742) );
NAND2X1TS U1539 ( .A(n1015), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n741) );
NAND2X1TS U1540 ( .A(n1699), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n746) );
NAND2X1TS U1541 ( .A(n1017), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n745) );
NAND2X1TS U1542 ( .A(n1015), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n744) );
OAI22X1TS U1543 ( .A0(n1512), .A1(n676), .B0(n1513), .B1(n1514), .Y(n747) );
AOI21X1TS U1544 ( .A0(n677), .A1(n1033), .B0(n747), .Y(n748) );
BUFX3TS U1545 ( .A(n1621), .Y(n1586) );
AOI222X4TS U1546 ( .A0(n1586), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n1023), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n1017), .Y(
n1058) );
OAI22X1TS U1547 ( .A0(n1058), .A1(n676), .B0(n1014), .B1(n687), .Y(n749) );
AOI21X1TS U1548 ( .A0(n679), .A1(n993), .B0(n749), .Y(n750) );
INVX2TS U1549 ( .A(n919), .Y(n1699) );
AOI222X4TS U1550 ( .A0(n1586), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(n1017), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n1001), .Y(
n1038) );
AOI22X1TS U1551 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]),
.A1(n1017), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]),
.B1(n1015), .Y(n751) );
AOI222X4TS U1552 ( .A0(n1586), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]), .B0(n1017), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n1023), .Y(
n1020) );
AOI222X4TS U1553 ( .A0(n1586), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n1017), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(n1001), .Y(
n1024) );
OAI22X1TS U1554 ( .A0(n1020), .A1(n675), .B0(n1024), .B1(n1514), .Y(n752) );
AOI21X1TS U1555 ( .A0(n677), .A1(n1029), .B0(n752), .Y(n753) );
NAND2X1TS U1556 ( .A(n1001), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n756) );
NAND2X1TS U1557 ( .A(n1533), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n755) );
NAND2X1TS U1558 ( .A(n995), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n754) );
OAI22X1TS U1559 ( .A0(n1046), .A1(n676), .B0(n1020), .B1(n687), .Y(n757) );
AOI21X1TS U1560 ( .A0(n679), .A1(n1029), .B0(n757), .Y(n758) );
NOR2X1TS U1561 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n1361) );
NAND2X1TS U1562 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n1369) );
NAND2X1TS U1563 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n1362) );
NOR2X1TS U1564 ( .A(n1349), .B(n1340), .Y(n760) );
NAND2X1TS U1565 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n1350) );
NAND2X1TS U1566 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n1341) );
OAI21X1TS U1567 ( .A0(n1340), .A1(n1350), .B0(n1341), .Y(n759) );
NOR2X1TS U1568 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n1315) );
NOR2X2TS U1569 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n1317) );
NOR2X2TS U1570 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n1123) );
NOR2X2TS U1571 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n1101) );
NAND2X1TS U1572 ( .A(n1100), .B(n762), .Y(n764) );
NAND2X1TS U1573 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n1327) );
NAND2X1TS U1574 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n1318) );
OAI21X1TS U1575 ( .A0(n1317), .A1(n1327), .B0(n1318), .Y(n1099) );
NAND2X1TS U1576 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n1124) );
NAND2X1TS U1577 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n1102) );
AOI21X1TS U1578 ( .A0(n1099), .A1(n762), .B0(n761), .Y(n763) );
NOR2X1TS U1579 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .Y(n1168) );
INVX2TS U1580 ( .A(n1168), .Y(n1305) );
NOR2X2TS U1581 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n1140) );
NAND2X1TS U1582 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .Y(n1304) );
INVX2TS U1583 ( .A(n1304), .Y(n766) );
NAND2X1TS U1584 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .Y(n1169) );
INVX2TS U1585 ( .A(n1169), .Y(n765) );
AOI21X1TS U1586 ( .A0(n1170), .A1(n766), .B0(n765), .Y(n1138) );
NAND2X1TS U1587 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n1141) );
OAI21X1TS U1588 ( .A0(n1138), .A1(n1140), .B0(n1141), .Y(n767) );
NOR2X1TS U1589 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n1153) );
NAND2X1TS U1590 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n1154) );
OR2X1TS U1591 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n1297) );
NAND2X1TS U1592 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n1296) );
INVX2TS U1593 ( .A(n1296), .Y(n769) );
NOR2X1TS U1594 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n1287) );
NAND2X1TS U1595 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n1288) );
OR2X1TS U1596 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n1280) );
NAND2X1TS U1597 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n1279) );
INVX2TS U1598 ( .A(n1279), .Y(n770) );
NOR2X1TS U1599 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n1270) );
NAND2X1TS U1600 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n1271) );
OR2X1TS U1601 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n1263) );
NAND2X1TS U1602 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n1262) );
INVX2TS U1603 ( .A(n1262), .Y(n771) );
NOR2X1TS U1604 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n1214) );
NAND2X1TS U1605 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n1215) );
OR2X1TS U1606 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n1207) );
NAND2X1TS U1607 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n1206) );
INVX2TS U1608 ( .A(n1206), .Y(n772) );
NOR2X1TS U1609 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n1181) );
NAND2X1TS U1610 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n1182) );
OR2X1TS U1611 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n1224) );
NAND2X1TS U1612 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n1223) );
INVX2TS U1613 ( .A(n1223), .Y(n773) );
AOI21X4TS U1614 ( .A0(n1225), .A1(n1224), .B0(n773), .Y(n1237) );
NOR2X1TS U1615 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n1234) );
NAND2X1TS U1616 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n1235) );
OAI21X4TS U1617 ( .A0(n1237), .A1(n1234), .B0(n1235), .Y(n1247) );
OR2X1TS U1618 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n1246) );
NAND2X1TS U1619 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n1245) );
INVX2TS U1620 ( .A(n1245), .Y(n774) );
NAND2X1TS U1621 ( .A(n1255), .B(n1697), .Y(n775) );
BUFX3TS U1622 ( .A(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .Y(n1231) );
NOR2BX1TS U1623 ( .AN(n775), .B(n1231), .Y(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_SGF) );
NAND2X1TS U1624 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(n1640), .Y(n872) );
NAND2X1TS U1625 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]),
.B(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .Y(n877) );
INVX2TS U1626 ( .A(n877), .Y(n1088) );
NAND3X2TS U1627 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .C(n664), .Y(
n1086) );
INVX1TS U1628 ( .A(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]), .Y(n931)
);
NAND2BX2TS U1629 ( .AN(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n941) );
NOR2BX1TS U1630 ( .AN(n776), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n777) );
AOI22X1TS U1631 ( .A0(n670), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B0(n673), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .Y(n778) );
AOI211X1TS U1632 ( .A0(n669), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .B0(n1088), .C0(n779),
.Y(n782) );
INVX1TS U1633 ( .A(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[51]), .Y(n929)
);
AOI22X1TS U1634 ( .A0(n670), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .B0(n673), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .Y(n780) );
AOI211X1TS U1635 ( .A0(n669), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .B0(n1088), .C0(n781),
.Y(n783) );
MXI2X1TS U1636 ( .A(n782), .B(n783), .S0(
inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .Y(n1630) );
MXI2X1TS U1637 ( .A(n783), .B(n782), .S0(n666), .Y(n1631) );
NOR3X1TS U1638 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .B(
n787), .C(n1623), .Y(n1060) );
AOI211X1TS U1639 ( .A0(n789), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .B0(n788), .C0(n1060), .Y(n792) );
NAND2X1TS U1640 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .B(
n790), .Y(n791) );
NAND3BX1TS U1641 ( .AN(n793), .B(n792), .C(n791), .Y(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[4]) );
NOR2X1TS U1642 ( .A(cont_iter_out[0]), .B(cont_iter_out[1]), .Y(n814) );
NAND2X1TS U1643 ( .A(n1593), .B(cont_iter_out[3]), .Y(n795) );
NAND2X1TS U1644 ( .A(n1544), .B(n1593), .Y(n794) );
INVX2TS U1645 ( .A(n1574), .Y(n559) );
INVX2TS U1646 ( .A(n795), .Y(n810) );
NAND2X1TS U1647 ( .A(n559), .B(cont_iter_out[0]), .Y(n1579) );
NOR2X1TS U1648 ( .A(n810), .B(n1578), .Y(n1575) );
OAI211X1TS U1649 ( .A0(cont_iter_out[3]), .A1(n1596), .B0(n1593), .C0(n1613),
.Y(n1577) );
OAI31X4TS U1650 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[3]), .A2(n1596),
.B0(n559), .Y(n1576) );
OAI21XLTS U1651 ( .A0(n1613), .A1(n1576), .B0(n795), .Y(n554) );
NOR3X1TS U1652 ( .A(inst_CORDIC_FSM_v3_state_reg[3]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n818), .Y(n796) );
NAND2X1TS U1653 ( .A(n796), .B(n807), .Y(n833) );
NOR2X1TS U1654 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[7]), .Y(n808) );
NAND2BX1TS U1655 ( .AN(n797), .B(n796), .Y(n1077) );
INVX2TS U1656 ( .A(n1077), .Y(n1741) );
NAND2X1TS U1657 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .B(n1652), .Y(n815) );
OAI21XLTS U1658 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .A1(
n1652), .B0(n815), .Y(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[0]) );
OAI21XLTS U1659 ( .A0(n1574), .A1(n1613), .B0(n1576), .Y(n553) );
CLKBUFX3TS U1660 ( .A(n803), .Y(n800) );
BUFX3TS U1661 ( .A(n806), .Y(n1713) );
BUFX3TS U1662 ( .A(n800), .Y(n1703) );
BUFX3TS U1663 ( .A(n1716), .Y(n1712) );
CLKBUFX3TS U1664 ( .A(n1719), .Y(n1715) );
BUFX3TS U1665 ( .A(n1719), .Y(n1702) );
BUFX3TS U1666 ( .A(n806), .Y(n1708) );
BUFX3TS U1667 ( .A(n1721), .Y(n1704) );
BUFX3TS U1668 ( .A(n1721), .Y(n1711) );
BUFX3TS U1669 ( .A(n801), .Y(n1705) );
BUFX3TS U1670 ( .A(n1716), .Y(n1722) );
BUFX3TS U1671 ( .A(n801), .Y(n1725) );
BUFX3TS U1672 ( .A(n1716), .Y(n1709) );
BUFX3TS U1673 ( .A(n806), .Y(n1723) );
BUFX3TS U1674 ( .A(n800), .Y(n1739) );
BUFX3TS U1675 ( .A(n1719), .Y(n1738) );
BUFX3TS U1676 ( .A(n1721), .Y(n1737) );
BUFX3TS U1677 ( .A(n803), .Y(n1719) );
BUFX3TS U1678 ( .A(n803), .Y(n1736) );
INVX2TS U1679 ( .A(rst), .Y(n529) );
BUFX3TS U1680 ( .A(n798), .Y(n1776) );
BUFX3TS U1681 ( .A(n1776), .Y(n1771) );
CLKBUFX2TS U1682 ( .A(n529), .Y(n805) );
BUFX3TS U1683 ( .A(n802), .Y(n1749) );
BUFX3TS U1684 ( .A(n805), .Y(n1750) );
BUFX3TS U1685 ( .A(n802), .Y(n1751) );
BUFX3TS U1686 ( .A(n802), .Y(n1752) );
BUFX3TS U1687 ( .A(n805), .Y(n1753) );
CLKBUFX2TS U1688 ( .A(n529), .Y(n799) );
BUFX3TS U1689 ( .A(n799), .Y(n1754) );
BUFX3TS U1690 ( .A(n799), .Y(n1755) );
BUFX3TS U1691 ( .A(n798), .Y(n1756) );
BUFX3TS U1692 ( .A(n799), .Y(n1757) );
BUFX3TS U1693 ( .A(n802), .Y(n1777) );
BUFX3TS U1694 ( .A(n1777), .Y(n1774) );
BUFX3TS U1695 ( .A(n798), .Y(n1758) );
BUFX3TS U1696 ( .A(n798), .Y(n1759) );
BUFX3TS U1697 ( .A(n798), .Y(n1760) );
BUFX3TS U1698 ( .A(n798), .Y(n1761) );
BUFX3TS U1699 ( .A(n798), .Y(n1763) );
BUFX3TS U1700 ( .A(n803), .Y(n1721) );
BUFX3TS U1701 ( .A(n798), .Y(n1764) );
BUFX3TS U1702 ( .A(n799), .Y(n1765) );
BUFX3TS U1703 ( .A(n798), .Y(n1766) );
BUFX3TS U1704 ( .A(n1776), .Y(n1767) );
BUFX3TS U1705 ( .A(n800), .Y(n1726) );
BUFX3TS U1706 ( .A(n1777), .Y(n1775) );
BUFX3TS U1707 ( .A(n1777), .Y(n1773) );
BUFX3TS U1708 ( .A(n1719), .Y(n1727) );
BUFX3TS U1709 ( .A(n804), .Y(n1720) );
BUFX3TS U1710 ( .A(n802), .Y(n1748) );
BUFX3TS U1711 ( .A(n806), .Y(n1732) );
BUFX3TS U1712 ( .A(n1776), .Y(n1768) );
BUFX3TS U1713 ( .A(n802), .Y(n1747) );
BUFX3TS U1714 ( .A(n802), .Y(n1746) );
BUFX3TS U1715 ( .A(n801), .Y(n1701) );
BUFX3TS U1716 ( .A(n805), .Y(n1745) );
BUFX3TS U1717 ( .A(n800), .Y(n1731) );
BUFX3TS U1718 ( .A(n1719), .Y(n1730) );
BUFX3TS U1719 ( .A(n799), .Y(n1762) );
BUFX3TS U1720 ( .A(n1721), .Y(n1733) );
BUFX3TS U1721 ( .A(n1721), .Y(n1728) );
BUFX3TS U1722 ( .A(n806), .Y(n1700) );
BUFX3TS U1723 ( .A(n805), .Y(n1742) );
BUFX3TS U1724 ( .A(n1777), .Y(n1772) );
BUFX3TS U1725 ( .A(n801), .Y(n1735) );
BUFX3TS U1726 ( .A(n802), .Y(n1744) );
CLKBUFX3TS U1727 ( .A(n803), .Y(n1716) );
BUFX3TS U1728 ( .A(n804), .Y(n1724) );
BUFX3TS U1729 ( .A(n803), .Y(n1734) );
BUFX3TS U1730 ( .A(n801), .Y(n1729) );
BUFX3TS U1731 ( .A(n1776), .Y(n1769) );
BUFX3TS U1732 ( .A(n805), .Y(n1743) );
BUFX3TS U1733 ( .A(n1776), .Y(n1770) );
BUFX3TS U1734 ( .A(n1716), .Y(n1717) );
NAND2X1TS U1735 ( .A(cont_iter_out[2]), .B(n1544), .Y(n1543) );
NOR2X1TS U1736 ( .A(n1594), .B(n1543), .Y(n819) );
NAND2X1TS U1737 ( .A(n808), .B(n807), .Y(n817) );
NOR3X1TS U1738 ( .A(inst_CORDIC_FSM_v3_state_reg[3]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n817), .Y(n816) );
NAND2BX1TS U1739 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(n816), .Y(n856)
);
OR3X1TS U1740 ( .A(n856), .B(n1607), .C(inst_CORDIC_FSM_v3_state_reg[2]),
.Y(n809) );
INVX2TS U1741 ( .A(ready_cordic), .Y(n858) );
NAND2X1TS U1742 ( .A(n858), .B(n848), .Y(enab_d_ff5_data_out) );
NAND2X1TS U1743 ( .A(n860), .B(n1579), .Y(n545) );
OR4X2TS U1744 ( .A(inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[0]), .D(
inst_FPU_PIPELINED_FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n811) );
BUFX3TS U1745 ( .A(n1740), .Y(n1714) );
BUFX3TS U1746 ( .A(n1740), .Y(n1707) );
BUFX3TS U1747 ( .A(n1740), .Y(n1710) );
BUFX3TS U1748 ( .A(n1740), .Y(n1706) );
BUFX3TS U1749 ( .A(n1740), .Y(n1718) );
NAND2X1TS U1750 ( .A(n1638), .B(cont_iter_out[0]), .Y(intadd_399_CI) );
NAND2X1TS U1751 ( .A(n1639), .B(cont_iter_out[0]), .Y(intadd_400_CI) );
INVX2TS U1752 ( .A(intadd_401_SUM_0_), .Y(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[1]) );
INVX2TS U1753 ( .A(intadd_401_SUM_1_), .Y(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[2]) );
INVX2TS U1754 ( .A(intadd_401_SUM_2_), .Y(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_EXP_EW[3]) );
INVX2TS U1755 ( .A(n815), .Y(intadd_401_CI) );
NAND2X1TS U1756 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .Y(n1540) );
INVX2TS U1757 ( .A(n1540), .Y(n1551) );
BUFX3TS U1758 ( .A(n1551), .Y(n1553) );
NOR2X1TS U1759 ( .A(n818), .B(n817), .Y(n855) );
NOR2X1TS U1760 ( .A(d_ff2_Y[27]), .B(intadd_400_n1), .Y(n1589) );
OR3X1TS U1761 ( .A(d_ff2_Y[28]), .B(d_ff2_Y[27]), .C(intadd_400_n1), .Y(
n1588) );
NOR2X1TS U1762 ( .A(d_ff2_X[27]), .B(intadd_399_n1), .Y(n1592) );
OR3X1TS U1763 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(intadd_399_n1), .Y(
n1591) );
NAND2X1TS U1764 ( .A(cont_var_out[1]), .B(n1612), .Y(n1537) );
INVX2TS U1765 ( .A(n1537), .Y(n849) );
BUFX3TS U1766 ( .A(n849), .Y(n829) );
BUFX3TS U1767 ( .A(n1551), .Y(n891) );
AOI222X1TS U1768 ( .A0(n830), .A1(d_ff2_X[11]), .B0(n829), .B1(d_ff2_Y[11]),
.C0(n891), .C1(d_ff2_Z[11]), .Y(n820) );
INVX2TS U1769 ( .A(n820), .Y(n572) );
AOI222X1TS U1770 ( .A0(n830), .A1(d_ff2_X[6]), .B0(n829), .B1(d_ff2_Y[6]),
.C0(n1553), .C1(d_ff2_Z[6]), .Y(n821) );
INVX2TS U1771 ( .A(n821), .Y(n567) );
AOI222X1TS U1772 ( .A0(n830), .A1(d_ff2_X[10]), .B0(n829), .B1(d_ff2_Y[10]),
.C0(n891), .C1(d_ff2_Z[10]), .Y(n822) );
INVX2TS U1773 ( .A(n822), .Y(n571) );
AOI222X1TS U1774 ( .A0(n830), .A1(d_ff2_X[13]), .B0(n829), .B1(d_ff2_Y[13]),
.C0(n891), .C1(d_ff2_Z[13]), .Y(n823) );
INVX2TS U1775 ( .A(n823), .Y(n574) );
AOI222X1TS U1776 ( .A0(n830), .A1(d_ff2_X[7]), .B0(n829), .B1(d_ff2_Y[7]),
.C0(n891), .C1(d_ff2_Z[7]), .Y(n824) );
INVX2TS U1777 ( .A(n824), .Y(n568) );
AOI222X1TS U1778 ( .A0(n830), .A1(d_ff2_X[8]), .B0(n829), .B1(d_ff2_Y[8]),
.C0(n891), .C1(d_ff2_Z[8]), .Y(n825) );
INVX2TS U1779 ( .A(n825), .Y(n569) );
AOI222X1TS U1780 ( .A0(n830), .A1(d_ff2_X[3]), .B0(n829), .B1(d_ff2_Y[3]),
.C0(n1553), .C1(d_ff2_Z[3]), .Y(n826) );
INVX2TS U1781 ( .A(n826), .Y(n564) );
AOI222X1TS U1782 ( .A0(n830), .A1(d_ff2_X[9]), .B0(n829), .B1(d_ff2_Y[9]),
.C0(n891), .C1(d_ff2_Z[9]), .Y(n827) );
INVX2TS U1783 ( .A(n827), .Y(n570) );
AOI222X1TS U1784 ( .A0(n830), .A1(d_ff2_X[12]), .B0(n829), .B1(d_ff2_Y[12]),
.C0(n891), .C1(d_ff2_Z[12]), .Y(n828) );
INVX2TS U1785 ( .A(n828), .Y(n573) );
AOI222X1TS U1786 ( .A0(n830), .A1(d_ff2_X[14]), .B0(n829), .B1(d_ff2_Y[14]),
.C0(n891), .C1(d_ff2_Z[14]), .Y(n831) );
INVX2TS U1787 ( .A(n831), .Y(n575) );
INVX2TS U1788 ( .A(n688), .Y(n832) );
INVX2TS U1789 ( .A(n1377), .Y(n1583) );
NOR3BX1TS U1790 ( .AN(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[7]), .C(n833), .Y(n1539) );
INVX2TS U1791 ( .A(n1581), .Y(n834) );
INVX2TS U1792 ( .A(n688), .Y(n835) );
INVX2TS U1793 ( .A(n688), .Y(n1518) );
INVX2TS U1794 ( .A(n1546), .Y(n846) );
BUFX3TS U1795 ( .A(n849), .Y(n845) );
BUFX3TS U1796 ( .A(n1551), .Y(n887) );
AOI222X1TS U1797 ( .A0(n846), .A1(d_ff3_sh_y_out[1]), .B0(n845), .B1(
d_ff3_sh_x_out[1]), .C0(n887), .C1(d_ff3_LUT_out[1]), .Y(n836) );
INVX2TS U1798 ( .A(n836), .Y(n594) );
AOI222X1TS U1799 ( .A0(n1571), .A1(d_ff2_X[31]), .B0(n845), .B1(d_ff2_Y[31]),
.C0(n887), .C1(d_ff2_Z[31]), .Y(n837) );
INVX2TS U1800 ( .A(n837), .Y(n592) );
AOI222X1TS U1801 ( .A0(n1571), .A1(d_ff2_X[28]), .B0(n845), .B1(d_ff2_Y[28]),
.C0(n887), .C1(d_ff2_Z[28]), .Y(n838) );
INVX2TS U1802 ( .A(n838), .Y(n589) );
AOI222X1TS U1803 ( .A0(n1545), .A1(d_ff3_sh_y_out[0]), .B0(n845), .B1(
d_ff3_sh_x_out[0]), .C0(n887), .C1(d_ff3_LUT_out[0]), .Y(n839) );
INVX2TS U1804 ( .A(n839), .Y(n593) );
BUFX3TS U1805 ( .A(n1551), .Y(n896) );
INVX2TS U1806 ( .A(n840), .Y(n586) );
INVX2TS U1807 ( .A(n841), .Y(n585) );
INVX2TS U1808 ( .A(n842), .Y(n588) );
INVX2TS U1809 ( .A(n843), .Y(n590) );
INVX2TS U1810 ( .A(n844), .Y(n591) );
INVX2TS U1811 ( .A(n847), .Y(n587) );
INVX2TS U1812 ( .A(n1546), .Y(n1571) );
AOI222X1TS U1813 ( .A0(n846), .A1(d_ff2_X[1]), .B0(n1555), .B1(d_ff2_Y[1]),
.C0(n1553), .C1(d_ff2_Z[1]), .Y(n850) );
INVX2TS U1814 ( .A(n850), .Y(n562) );
AOI222X1TS U1815 ( .A0(n901), .A1(d_ff2_X[5]), .B0(n1557), .B1(d_ff2_Y[5]),
.C0(n1553), .C1(d_ff2_Z[5]), .Y(n851) );
INVX2TS U1816 ( .A(n851), .Y(n566) );
AOI222X1TS U1817 ( .A0(n1571), .A1(d_ff2_X[4]), .B0(n1557), .B1(d_ff2_Y[4]),
.C0(n1553), .C1(d_ff2_Z[4]), .Y(n852) );
INVX2TS U1818 ( .A(n852), .Y(n565) );
AOI222X1TS U1819 ( .A0(n1545), .A1(d_ff2_X[2]), .B0(n849), .B1(d_ff2_Y[2]),
.C0(n1553), .C1(d_ff2_Z[2]), .Y(n853) );
INVX2TS U1820 ( .A(n853), .Y(n563) );
INVX2TS U1821 ( .A(n854), .Y(enab_RB3) );
NAND3BX1TS U1822 ( .AN(inst_CORDIC_FSM_v3_state_reg[3]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n855), .Y(n1536) );
OAI31X1TS U1823 ( .A0(inst_CORDIC_FSM_v3_state_reg[2]), .A1(n1607), .A2(n856), .B0(n1536), .Y(enab_d_ff_RB1) );
NOR4X1TS U1824 ( .A(inst_CORDIC_FSM_v3_state_next[3]), .B(n1741), .C(
enab_RB3), .D(enab_d_ff_RB1), .Y(n857) );
AOI32X1TS U1825 ( .A0(n1580), .A1(n858), .A2(n857), .B0(ready_cordic), .B1(
ack_cordic), .Y(n859) );
OAI21X1TS U1826 ( .A0(n1574), .A1(n1613), .B0(n860), .Y(n557) );
INVX2TS U1827 ( .A(n1546), .Y(n901) );
BUFX3TS U1828 ( .A(n1551), .Y(n1573) );
AOI222X1TS U1829 ( .A0(n846), .A1(d_ff3_sh_y_out[8]), .B0(n881), .B1(
d_ff3_sh_x_out[8]), .C0(n1573), .C1(d_ff3_LUT_out[8]), .Y(n861) );
INVX2TS U1830 ( .A(n861), .Y(n601) );
AOI222X1TS U1831 ( .A0(n1545), .A1(d_ff3_sh_y_out[9]), .B0(n881), .B1(
d_ff3_sh_x_out[9]), .C0(n1573), .C1(d_ff3_LUT_out[9]), .Y(n862) );
INVX2TS U1832 ( .A(n862), .Y(n602) );
AOI222X1TS U1833 ( .A0(n901), .A1(d_ff3_sh_y_out[6]), .B0(n881), .B1(
d_ff3_sh_x_out[6]), .C0(n1573), .C1(d_ff3_LUT_out[6]), .Y(n863) );
INVX2TS U1834 ( .A(n863), .Y(n599) );
AOI222X1TS U1835 ( .A0(n1571), .A1(d_ff3_sh_y_out[10]), .B0(n881), .B1(
d_ff3_sh_x_out[10]), .C0(n1573), .C1(d_ff3_LUT_out[10]), .Y(n864) );
INVX2TS U1836 ( .A(n864), .Y(n603) );
AOI222X1TS U1837 ( .A0(n846), .A1(d_ff3_sh_y_out[21]), .B0(n881), .B1(
d_ff3_sh_x_out[21]), .C0(n1573), .C1(d_ff3_LUT_out[21]), .Y(n865) );
INVX2TS U1838 ( .A(n865), .Y(n614) );
AOI222X1TS U1839 ( .A0(n1545), .A1(d_ff3_sh_y_out[12]), .B0(n881), .B1(
d_ff3_sh_x_out[12]), .C0(n1573), .C1(d_ff3_LUT_out[12]), .Y(n866) );
INVX2TS U1840 ( .A(n866), .Y(n605) );
NOR2BX2TS U1841 ( .AN(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .B(n776),
.Y(n944) );
NAND2X2TS U1842 ( .A(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n940) );
NOR2X2TS U1843 ( .A(n940), .B(n1640), .Y(n1081) );
OAI22X1TS U1844 ( .A0(n941), .A1(n1659), .B0(n872), .B1(n929), .Y(n867) );
AOI22X1TS U1845 ( .A0(n868), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .B0(n668), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .Y(n870) );
AOI22X1TS U1846 ( .A0(n671), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .B0(n674), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .Y(n869) );
OAI211X1TS U1847 ( .A0(n978), .A1(n664), .B0(n870), .C0(n869), .Y(n927) );
NOR2X2TS U1848 ( .A(n667), .B(n877), .Y(n972) );
AOI21X1TS U1849 ( .A0(n927), .A1(n1092), .B0(n972), .Y(n871) );
OAI22X1TS U1850 ( .A0(n941), .A1(n1667), .B0(n872), .B1(n931), .Y(n873) );
AOI22X1TS U1851 ( .A0(n674), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]), .B0(n868), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .Y(n875) );
AOI22X1TS U1852 ( .A0(n671), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .B0(n669), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .Y(n874) );
OAI211X1TS U1853 ( .A0(n961), .A1(n665), .B0(n875), .C0(n874), .Y(n879) );
AOI21X1TS U1854 ( .A0(n879), .A1(n1092), .B0(n972), .Y(n876) );
AOI21X1TS U1855 ( .A0(n666), .A1(n879), .B0(n878), .Y(n880) );
AOI222X1TS U1856 ( .A0(n901), .A1(d_ff3_sh_y_out[4]), .B0(n1555), .B1(
d_ff3_sh_x_out[4]), .C0(n887), .C1(d_ff3_LUT_out[4]), .Y(n882) );
INVX2TS U1857 ( .A(n882), .Y(n597) );
AOI222X1TS U1858 ( .A0(n1571), .A1(d_ff3_sh_y_out[2]), .B0(n1555), .B1(
d_ff3_sh_x_out[2]), .C0(n887), .C1(d_ff3_LUT_out[2]), .Y(n883) );
INVX2TS U1859 ( .A(n883), .Y(n595) );
AOI222X1TS U1860 ( .A0(n898), .A1(d_ff3_sh_y_out[23]), .B0(n1555), .B1(
d_ff3_sh_x_out[23]), .C0(n1573), .C1(d_ff3_LUT_out[23]), .Y(n884) );
INVX2TS U1861 ( .A(n884), .Y(n616) );
INVX2TS U1862 ( .A(n1546), .Y(n898) );
BUFX3TS U1863 ( .A(n1555), .Y(n897) );
AOI222X1TS U1864 ( .A0(n898), .A1(d_ff2_X[23]), .B0(n897), .B1(d_ff2_Y[23]),
.C0(n896), .C1(d_ff2_Z[23]), .Y(n885) );
INVX2TS U1865 ( .A(n885), .Y(n584) );
AOI222X1TS U1866 ( .A0(n898), .A1(d_ff2_X[15]), .B0(n897), .B1(d_ff2_Y[15]),
.C0(n891), .C1(d_ff2_Z[15]), .Y(n886) );
INVX2TS U1867 ( .A(n886), .Y(n576) );
AOI222X1TS U1868 ( .A0(n898), .A1(d_ff2_X[0]), .B0(n897), .B1(d_ff2_Y[0]),
.C0(n887), .C1(d_ff2_Z[0]), .Y(n888) );
INVX2TS U1869 ( .A(n888), .Y(n561) );
AOI222X1TS U1870 ( .A0(n898), .A1(d_ff2_X[17]), .B0(n897), .B1(d_ff2_Y[17]),
.C0(n896), .C1(d_ff2_Z[17]), .Y(n889) );
INVX2TS U1871 ( .A(n889), .Y(n578) );
AOI222X1TS U1872 ( .A0(n898), .A1(d_ff2_X[19]), .B0(n897), .B1(d_ff2_Y[19]),
.C0(n896), .C1(d_ff2_Z[19]), .Y(n890) );
INVX2TS U1873 ( .A(n890), .Y(n580) );
AOI222X1TS U1874 ( .A0(n898), .A1(d_ff2_X[16]), .B0(n897), .B1(d_ff2_Y[16]),
.C0(n891), .C1(d_ff2_Z[16]), .Y(n892) );
INVX2TS U1875 ( .A(n892), .Y(n577) );
AOI222X1TS U1876 ( .A0(n898), .A1(d_ff2_X[20]), .B0(n897), .B1(d_ff2_Y[20]),
.C0(n896), .C1(d_ff2_Z[20]), .Y(n893) );
INVX2TS U1877 ( .A(n893), .Y(n581) );
AOI222X1TS U1878 ( .A0(n1545), .A1(d_ff2_X[21]), .B0(n897), .B1(d_ff2_Y[21]),
.C0(n896), .C1(d_ff2_Z[21]), .Y(n894) );
INVX2TS U1879 ( .A(n894), .Y(n582) );
AOI222X1TS U1880 ( .A0(n901), .A1(d_ff2_X[22]), .B0(n897), .B1(d_ff2_Y[22]),
.C0(n896), .C1(d_ff2_Z[22]), .Y(n895) );
INVX2TS U1881 ( .A(n895), .Y(n583) );
AOI222X1TS U1882 ( .A0(n1571), .A1(d_ff2_X[18]), .B0(n897), .B1(d_ff2_Y[18]),
.C0(n896), .C1(d_ff2_Z[18]), .Y(n899) );
INVX2TS U1883 ( .A(n899), .Y(n579) );
INVX2TS U1884 ( .A(n1546), .Y(n1545) );
BUFX3TS U1885 ( .A(n1555), .Y(n1566) );
AOI222X1TS U1886 ( .A0(n1545), .A1(d_ff3_sh_y_out[25]), .B0(n1566), .B1(
d_ff3_sh_x_out[25]), .C0(n1573), .C1(d_ff3_LUT_out[25]), .Y(n900) );
INVX2TS U1887 ( .A(n900), .Y(n618) );
AOI222X1TS U1888 ( .A0(n846), .A1(d_ff3_sh_y_out[24]), .B0(n1566), .B1(
d_ff3_sh_x_out[24]), .C0(n1573), .C1(d_ff3_LUT_out[24]), .Y(n902) );
INVX2TS U1889 ( .A(n902), .Y(n617) );
AOI222X1TS U1890 ( .A0(n901), .A1(d_ff3_sh_y_out[26]), .B0(n1566), .B1(
d_ff3_sh_x_out[26]), .C0(n1553), .C1(d_ff3_LUT_out[26]), .Y(n903) );
INVX2TS U1891 ( .A(n903), .Y(n619) );
OAI22X1TS U1892 ( .A0(n906), .A1(n905), .B0(n904), .B1(n1066), .Y(n907) );
AOI21X1TS U1893 ( .A0(n908), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n907), .Y(n909)
);
OAI211X1TS U1894 ( .A0(n911), .A1(n1661), .B0(n910), .C0(n909), .Y(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[2]) );
NAND2X1TS U1895 ( .A(n1023), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n922) );
NAND2X1TS U1896 ( .A(n1002), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n921) );
NAND2X1TS U1897 ( .A(n995), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n920) );
AOI22X1TS U1898 ( .A0(n1023), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .B0(n1017), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n988) );
NAND2X1TS U1899 ( .A(n1699), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n925) );
NAND2X1TS U1900 ( .A(n1002), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n924) );
NAND2X1TS U1901 ( .A(n995), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n923) );
AOI22X1TS U1902 ( .A0(n1030), .A1(n1050), .B0(n1002), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n926) );
AOI21X1TS U1903 ( .A0(n1091), .A1(n927), .B0(n878), .Y(n928) );
OAI21X1TS U1904 ( .A0(n982), .A1(n685), .B0(n928), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[24]) );
OAI21X1TS U1905 ( .A0(n941), .A1(n929), .B0(n940), .Y(n930) );
OAI21X1TS U1906 ( .A0(n941), .A1(n931), .B0(n940), .Y(n932) );
AOI22X1TS U1907 ( .A0(n868), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B0(n668), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .Y(n934) );
AOI22X1TS U1908 ( .A0(n671), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .B0(n674), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .Y(n933) );
OAI211X1TS U1909 ( .A0(n1070), .A1(n665), .B0(n934), .C0(n933), .Y(n1071) );
AOI21X1TS U1910 ( .A0(n1091), .A1(n1071), .B0(n878), .Y(n935) );
OAI21X1TS U1911 ( .A0(n982), .A1(n1075), .B0(n935), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[21]) );
OAI21X1TS U1912 ( .A0(n941), .A1(n1654), .B0(n940), .Y(n936) );
AOI22X1TS U1913 ( .A0(n868), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .B0(n668), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .Y(n938) );
AOI22X1TS U1914 ( .A0(n671), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .B0(n674), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .Y(n937) );
OAI211X1TS U1915 ( .A0(n964), .A1(n664), .B0(n938), .C0(n937), .Y(n973) );
AOI21X1TS U1916 ( .A0(n1091), .A1(n973), .B0(n878), .Y(n939) );
OAI21X1TS U1917 ( .A0(n982), .A1(n975), .B0(n939), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[23]) );
AOI22X1TS U1918 ( .A0(n671), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .B1(n674), .Y(n946)
);
AOI22X1TS U1919 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .A1(
n868), .B0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .B1(n668),
.Y(n945) );
OAI211X1TS U1920 ( .A0(n971), .A1(n665), .B0(n946), .C0(n945), .Y(n948) );
NAND2X1TS U1921 ( .A(n948), .B(n667), .Y(n947) );
INVX2TS U1922 ( .A(n972), .Y(n1072) );
OAI211X1TS U1923 ( .A0(n967), .A1(n1074), .B0(n947), .C0(n1072), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[6]) );
AOI21X1TS U1924 ( .A0(n1091), .A1(n948), .B0(n878), .Y(n949) );
OAI21X1TS U1925 ( .A0(n967), .A1(n982), .B0(n949), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[19]) );
AOI22X1TS U1926 ( .A0(n671), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .B0(n674), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .Y(n951) );
AOI22X1TS U1927 ( .A0(n868), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .B0(n668), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .Y(n950) );
OAI211X1TS U1928 ( .A0(n975), .A1(n665), .B0(n951), .C0(n950), .Y(n962) );
NAND2X1TS U1929 ( .A(n962), .B(n1092), .Y(n952) );
OAI211X1TS U1930 ( .A0(n964), .A1(n1074), .B0(n952), .C0(n1072), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[7]) );
AOI22X1TS U1931 ( .A0(n673), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .B0(n868), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .Y(n954) );
AOI22X1TS U1932 ( .A0(n670), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .B0(n668), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .Y(n953) );
OAI211X1TS U1933 ( .A0(n686), .A1(n665), .B0(n954), .C0(n953), .Y(n959) );
NAND2X1TS U1934 ( .A(n959), .B(n633), .Y(n955) );
OAI211X1TS U1935 ( .A0(n961), .A1(n1074), .B0(n955), .C0(n1072), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[9]) );
AOI22X1TS U1936 ( .A0(n671), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .B0(n674), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .Y(n957) );
AOI22X1TS U1937 ( .A0(n868), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .B0(n668), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .Y(n956) );
OAI211X1TS U1938 ( .A0(n685), .A1(n665), .B0(n957), .C0(n956), .Y(n976) );
NAND2X1TS U1939 ( .A(n976), .B(n1092), .Y(n958) );
OAI211X1TS U1940 ( .A0(n978), .A1(n1074), .B0(n958), .C0(n1072), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[8]) );
AOI21X1TS U1941 ( .A0(n1091), .A1(n959), .B0(n878), .Y(n960) );
OAI21X1TS U1942 ( .A0(n982), .A1(n961), .B0(n960), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[16]) );
AOI21X1TS U1943 ( .A0(n1091), .A1(n962), .B0(n878), .Y(n963) );
OAI21X1TS U1944 ( .A0(n982), .A1(n964), .B0(n963), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[18]) );
AOI22X1TS U1945 ( .A0(n868), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .B0(n668), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .Y(n966) );
AOI22X1TS U1946 ( .A0(n671), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .B0(n674), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .Y(n965) );
OAI211X1TS U1947 ( .A0(n967), .A1(n665), .B0(n966), .C0(n965), .Y(n969) );
AOI21X1TS U1948 ( .A0(n1091), .A1(n969), .B0(n878), .Y(n968) );
OAI21X1TS U1949 ( .A0(n982), .A1(n971), .B0(n968), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[22]) );
AOI21X1TS U1950 ( .A0(n969), .A1(n633), .B0(n972), .Y(n970) );
OAI21X1TS U1951 ( .A0(n971), .A1(n1074), .B0(n970), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[3]) );
AOI21X1TS U1952 ( .A0(n973), .A1(n1092), .B0(n972), .Y(n974) );
OAI21X1TS U1953 ( .A0(n975), .A1(n1074), .B0(n974), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[2]) );
AOI21X1TS U1954 ( .A0(n666), .A1(n976), .B0(n878), .Y(n977) );
OAI21X1TS U1955 ( .A0(n982), .A1(n978), .B0(n977), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[17]) );
AOI22X1TS U1956 ( .A0(n868), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .B0(n669), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .Y(n980) );
AOI22X1TS U1957 ( .A0(n671), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .B0(n674), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .Y(n979) );
OAI211X1TS U1958 ( .A0(n1075), .A1(n665), .B0(n980), .C0(n979), .Y(n1068) );
AOI21X1TS U1959 ( .A0(n666), .A1(n1068), .B0(n878), .Y(n981) );
OAI21X1TS U1960 ( .A0(n982), .A1(n1070), .B0(n981), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[20]) );
NAND2X1TS U1961 ( .A(n1023), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n985) );
NAND2X1TS U1962 ( .A(n1017), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n984) );
NAND2X1TS U1963 ( .A(n995), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n983) );
OAI22X1TS U1964 ( .A0(n1047), .A1(n676), .B0(n1052), .B1(n632), .Y(n986) );
AOI21X1TS U1965 ( .A0(n1026), .A1(n1050), .B0(n986), .Y(n987) );
INVX2TS U1966 ( .A(n1050), .Y(n991) );
OAI22X1TS U1967 ( .A0(n1048), .A1(n1514), .B0(n1047), .B1(n632), .Y(n989) );
AOI21X1TS U1968 ( .A0(n1030), .A1(n993), .B0(n989), .Y(n990) );
OAI21X1TS U1969 ( .A0(n991), .A1(n680), .B0(n990), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]) );
OAI22X1TS U1970 ( .A0(n1011), .A1(n676), .B0(n1048), .B1(n678), .Y(n992) );
AOI21X1TS U1971 ( .A0(n1026), .A1(n993), .B0(n992), .Y(n994) );
NAND2X1TS U1972 ( .A(n1001), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n998) );
NAND2X1TS U1973 ( .A(n1533), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n997) );
NAND2X1TS U1974 ( .A(n995), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n996) );
OAI22X1TS U1975 ( .A0(n1513), .A1(n676), .B0(n1035), .B1(n678), .Y(n999) );
AOI21X1TS U1976 ( .A0(n1026), .A1(n1033), .B0(n999), .Y(n1000) );
NAND2X1TS U1977 ( .A(n1699), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n1005) );
NAND2X1TS U1978 ( .A(n1533), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n1004) );
NAND2X1TS U1979 ( .A(n1015), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1003) );
OAI22X1TS U1980 ( .A0(n1035), .A1(n687), .B0(n1042), .B1(n678), .Y(n1006) );
AOI21X1TS U1981 ( .A0(n1030), .A1(n1033), .B0(n1006), .Y(n1007) );
AOI22X1TS U1982 ( .A0(n1699), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n1015), .Y(n1008) );
OAI2BB1X1TS U1983 ( .A0N(n1533), .A1N(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(n1008), .Y(
n1056) );
OAI22X1TS U1984 ( .A0(n1058), .A1(n1514), .B0(n1014), .B1(n632), .Y(n1009)
);
AOI21X1TS U1985 ( .A0(n1030), .A1(n1056), .B0(n1009), .Y(n1010) );
OAI22X1TS U1986 ( .A0(n1053), .A1(n675), .B0(n1058), .B1(n678), .Y(n1012) );
AOI21X1TS U1987 ( .A0(n1026), .A1(n1056), .B0(n1012), .Y(n1013) );
AOI22X1TS U1988 ( .A0(n1023), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n1015), .Y(
n1016) );
OAI2BB1X1TS U1989 ( .A0N(n1533), .A1N(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(n1016), .Y(n1044) );
OAI22X1TS U1990 ( .A0(n1041), .A1(n675), .B0(n1046), .B1(n632), .Y(n1018) );
AOI21X1TS U1991 ( .A0(n1026), .A1(n1044), .B0(n1018), .Y(n1019) );
OAI22X1TS U1992 ( .A0(n1046), .A1(n687), .B0(n1020), .B1(n632), .Y(n1021) );
AOI21X1TS U1993 ( .A0(n1030), .A1(n1044), .B0(n1021), .Y(n1022) );
AOI222X4TS U1994 ( .A0(n1586), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n1001), .C0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n1002), .Y(
n1054) );
OAI22X1TS U1995 ( .A0(n1024), .A1(n676), .B0(n1038), .B1(n632), .Y(n1025) );
AOI21X1TS U1996 ( .A0(n1026), .A1(n1029), .B0(n1025), .Y(n1027) );
OAI22X1TS U1997 ( .A0(n1038), .A1(n1514), .B0(n1054), .B1(n632), .Y(n1028)
);
AOI21X1TS U1998 ( .A0(n1030), .A1(n1029), .B0(n1028), .Y(n1031) );
OAI22X1TS U1999 ( .A0(n1512), .A1(n687), .B0(n1513), .B1(n678), .Y(n1032) );
AOI21X1TS U2000 ( .A0(n679), .A1(n1033), .B0(n1032), .Y(n1034) );
OAI22X1TS U2001 ( .A0(n1035), .A1(n675), .B0(n1042), .B1(n687), .Y(n1036) );
AOI21X1TS U2002 ( .A0(n679), .A1(n1044), .B0(n1036), .Y(n1037) );
OAI22X1TS U2003 ( .A0(n1038), .A1(n675), .B0(n1054), .B1(n1514), .Y(n1039)
);
AOI21X1TS U2004 ( .A0(n679), .A1(n1056), .B0(n1039), .Y(n1040) );
OAI22X1TS U2005 ( .A0(n1042), .A1(n675), .B0(n1041), .B1(n687), .Y(n1043) );
AOI21X1TS U2006 ( .A0(n677), .A1(n1044), .B0(n1043), .Y(n1045) );
OAI22X1TS U2007 ( .A0(n1048), .A1(n676), .B0(n1047), .B1(n1514), .Y(n1049)
);
AOI21X1TS U2008 ( .A0(n677), .A1(n1050), .B0(n1049), .Y(n1051) );
OAI22X1TS U2009 ( .A0(n1054), .A1(n675), .B0(n1053), .B1(n1514), .Y(n1055)
);
AOI21X1TS U2010 ( .A0(n677), .A1(n1056), .B0(n1055), .Y(n1057) );
AOI211X1TS U2011 ( .A0(n1063), .A1(n1062), .B0(n1061), .C0(n1060), .Y(n1065)
);
OAI211X1TS U2012 ( .A0(n1067), .A1(n1066), .B0(n1065), .C0(n1064), .Y(
inst_FPU_PIPELINED_FPADDSUB_LZD_raw_out_EWR[3]) );
NAND2X1TS U2013 ( .A(n1068), .B(n633), .Y(n1069) );
OAI211X1TS U2014 ( .A0(n1070), .A1(n1074), .B0(n1069), .C0(n1072), .Y(
inst_FPU_PIPELINED_FPADDSUB_sftr_odat_SHT2_SWR[5]) );
NAND2X1TS U2015 ( .A(n1071), .B(n667), .Y(n1073) );
NOR2BX1TS U2016 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1076) );
XOR2X1TS U2017 ( .A(DP_OP_33J163_122_2179_n28), .B(n1076), .Y(
DP_OP_33J163_122_2179_n14) );
NOR3XLTS U2018 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .C(n1538), .Y(
enab_d_ff4_Xn) );
INVX2TS U2019 ( .A(n1585), .Y(n1584) );
NAND2X1TS U2020 ( .A(n1584), .B(cont_var_out[1]), .Y(n1078) );
OAI211XLTS U2021 ( .A0(n1584), .A1(n1546), .B0(n1537), .C0(n1078), .Y(n539)
);
AOI22X1TS U2022 ( .A0(n670), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .B0(n673), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .Y(n1079) );
AOI211X1TS U2023 ( .A0(n669), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .B0(n1088), .C0(n1080), .Y(n1084) );
AOI211X1TS U2024 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .A1(
n669), .B0(n1090), .C0(n1082), .Y(n1083) );
MXI2X1TS U2025 ( .A(n1084), .B(n1083), .S0(
inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .Y(n1628) );
MXI2X1TS U2026 ( .A(n1084), .B(n1083), .S0(n633), .Y(n1629) );
AOI22X1TS U2027 ( .A0(n670), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .B0(n673), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .Y(n1085) );
AOI211X1TS U2028 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .A1(
n669), .B0(n1088), .C0(n1087), .Y(n1094) );
AOI211X1TS U2029 ( .A0(n669), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .B0(n1090), .C0(n1089), .Y(n1093) );
MXI2X1TS U2030 ( .A(n1094), .B(n1093), .S0(n666), .Y(n1632) );
MXI2X1TS U2031 ( .A(n1094), .B(n1093), .S0(n1092), .Y(n1633) );
NOR2BX1TS U2032 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1095) );
XOR2X1TS U2033 ( .A(DP_OP_33J163_122_2179_n28), .B(n1095), .Y(
DP_OP_33J163_122_2179_n15) );
NOR2BX1TS U2034 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1096) );
XOR2X1TS U2035 ( .A(DP_OP_33J163_122_2179_n28), .B(n1096), .Y(
DP_OP_33J163_122_2179_n16) );
NOR2BX1TS U2036 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1097) );
XOR2X1TS U2037 ( .A(DP_OP_33J163_122_2179_n28), .B(n1097), .Y(
DP_OP_33J163_122_2179_n17) );
INVX2TS U2038 ( .A(n1098), .Y(n1329) );
AOI21X1TS U2039 ( .A0(n1329), .A1(n1100), .B0(n1099), .Y(n1126) );
NAND2X1TS U2040 ( .A(n1103), .B(n1102), .Y(n1119) );
XNOR2X1TS U2041 ( .A(n1104), .B(n1119), .Y(n1122) );
NAND2X1TS U2042 ( .A(n1626), .B(n1601), .Y(n1371) );
NOR2XLTS U2043 ( .A(n1624), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .Y(
n1106) );
NAND2X1TS U2044 ( .A(n1624), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .Y(
n1105) );
NOR2X1TS U2045 ( .A(n1620), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .Y(
n1355) );
NOR2X1TS U2046 ( .A(n1616), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .Y(
n1108) );
NOR2X1TS U2047 ( .A(n1355), .B(n1108), .Y(n1110) );
NAND2X1TS U2048 ( .A(n1620), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .Y(
n1354) );
NAND2X1TS U2049 ( .A(n1616), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .Y(
n1107) );
OAI21X1TS U2050 ( .A0(n1108), .A1(n1354), .B0(n1107), .Y(n1109) );
AOI21X2TS U2051 ( .A0(n1353), .A1(n1110), .B0(n1109), .Y(n1127) );
NOR2X1TS U2052 ( .A(n1619), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .Y(
n1330) );
NOR2X1TS U2053 ( .A(n1615), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .Y(
n1112) );
NOR2X1TS U2054 ( .A(n1330), .B(n1112), .Y(n1129) );
NOR2X1TS U2055 ( .A(n1618), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .Y(
n1131) );
NOR2X1TS U2056 ( .A(n1614), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .Y(
n1114) );
NAND2X1TS U2057 ( .A(n1129), .B(n1116), .Y(n1118) );
NAND2X1TS U2058 ( .A(n1619), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .Y(
n1331) );
NAND2X1TS U2059 ( .A(n1615), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .Y(
n1111) );
OAI21X1TS U2060 ( .A0(n1112), .A1(n1331), .B0(n1111), .Y(n1128) );
NAND2X1TS U2061 ( .A(n1618), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .Y(
n1130) );
NAND2X1TS U2062 ( .A(n1614), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .Y(
n1113) );
AOI21X1TS U2063 ( .A0(n1128), .A1(n1116), .B0(n1115), .Y(n1117) );
INVX2TS U2064 ( .A(n1163), .Y(n1309) );
INVX2TS U2065 ( .A(n1119), .Y(n1120) );
XOR2X1TS U2066 ( .A(n1309), .B(n1120), .Y(n1121) );
NAND2X1TS U2067 ( .A(n1125), .B(n1124), .Y(n1132) );
XOR2X1TS U2068 ( .A(n1126), .B(n1132), .Y(n1136) );
INVX2TS U2069 ( .A(n1127), .Y(n1346) );
AOI21X1TS U2070 ( .A0(n1346), .A1(n1129), .B0(n1128), .Y(n1323) );
INVX2TS U2071 ( .A(n1132), .Y(n1133) );
XNOR2X1TS U2072 ( .A(n1134), .B(n1133), .Y(n1135) );
INVX2TS U2073 ( .A(n1137), .Y(n1306) );
NAND2X1TS U2074 ( .A(n1142), .B(n1141), .Y(n1148) );
XNOR2X1TS U2075 ( .A(n1143), .B(n1148), .Y(n1152) );
NOR2X1TS U2076 ( .A(n1617), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .Y(
n1308) );
NAND2X1TS U2077 ( .A(n1597), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .Y(
n1144) );
INVX2TS U2078 ( .A(n1148), .Y(n1149) );
XNOR2X1TS U2079 ( .A(n1150), .B(n1149), .Y(n1151) );
NAND2X1TS U2080 ( .A(n1155), .B(n1154), .Y(n1164) );
XOR2X1TS U2081 ( .A(n1156), .B(n1164), .Y(n1167) );
NOR2X1TS U2082 ( .A(n1598), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .Y(
n1159) );
NOR2X2TS U2083 ( .A(n1157), .B(n1159), .Y(n1162) );
NAND2X1TS U2084 ( .A(n1598), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]),
.Y(n1158) );
OAI21X2TS U2085 ( .A0(n1160), .A1(n1159), .B0(n1158), .Y(n1161) );
INVX2TS U2086 ( .A(n1164), .Y(n1165) );
XOR2X1TS U2087 ( .A(n1187), .B(n1165), .Y(n1166) );
NAND2X1TS U2088 ( .A(n1170), .B(n1169), .Y(n1176) );
XNOR2X1TS U2089 ( .A(n1171), .B(n1176), .Y(n1180) );
INVX2TS U2090 ( .A(n1176), .Y(n1177) );
XNOR2X1TS U2091 ( .A(n1178), .B(n1177), .Y(n1179) );
INVX2TS U2092 ( .A(n1181), .Y(n1183) );
NAND2X1TS U2093 ( .A(n1183), .B(n1182), .Y(n1202) );
XOR2X1TS U2094 ( .A(n1184), .B(n1202), .Y(n1205) );
NOR2X1TS U2095 ( .A(n1599), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .Y(
n1186) );
NAND2X1TS U2096 ( .A(n1599), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]),
.Y(n1185) );
OAI21X4TS U2097 ( .A0(n1187), .A1(n1186), .B0(n1185), .Y(n1301) );
OR2X1TS U2098 ( .A(n1605), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .Y(
n1189) );
AOI21X4TS U2099 ( .A0(n1301), .A1(n1189), .B0(n1188), .Y(n1293) );
NAND2X1TS U2100 ( .A(n1604), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]),
.Y(n1190) );
OR2X1TS U2101 ( .A(n1627), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .Y(
n1193) );
NOR2X1TS U2102 ( .A(n1641), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .Y(
n1195) );
NAND2X1TS U2103 ( .A(n1641), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]),
.Y(n1194) );
OAI21X4TS U2104 ( .A0(n1276), .A1(n1195), .B0(n1194), .Y(n1267) );
OR2X1TS U2105 ( .A(n1642), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .Y(
n1197) );
AOI21X4TS U2106 ( .A0(n1267), .A1(n1197), .B0(n1196), .Y(n1220) );
NAND2X1TS U2107 ( .A(n1656), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]),
.Y(n1198) );
OR2X1TS U2108 ( .A(n1658), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .Y(
n1201) );
INVX2TS U2109 ( .A(n1202), .Y(n1203) );
XOR2X1TS U2110 ( .A(n1228), .B(n1203), .Y(n1204) );
NAND2X1TS U2111 ( .A(n1207), .B(n1206), .Y(n1209) );
XNOR2X1TS U2112 ( .A(n1208), .B(n1209), .Y(n1213) );
INVX2TS U2113 ( .A(n1209), .Y(n1210) );
XNOR2X1TS U2114 ( .A(n1211), .B(n1210), .Y(n1212) );
INVX2TS U2115 ( .A(n1214), .Y(n1216) );
NAND2X1TS U2116 ( .A(n1216), .B(n1215), .Y(n1218) );
XOR2X1TS U2117 ( .A(n1217), .B(n1218), .Y(n1222) );
INVX2TS U2118 ( .A(n1218), .Y(n1219) );
XOR2X1TS U2119 ( .A(n1220), .B(n1219), .Y(n1221) );
NAND2X1TS U2120 ( .A(n1224), .B(n1223), .Y(n1229) );
XNOR2X1TS U2121 ( .A(n1225), .B(n1229), .Y(n1233) );
NAND2X1TS U2122 ( .A(n1655), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]),
.Y(n1226) );
INVX2TS U2123 ( .A(n1229), .Y(n1230) );
XNOR2X1TS U2124 ( .A(n1240), .B(n1230), .Y(n1232) );
INVX2TS U2125 ( .A(n1234), .Y(n1236) );
NAND2X1TS U2126 ( .A(n1236), .B(n1235), .Y(n1241) );
XOR2X1TS U2127 ( .A(n1237), .B(n1241), .Y(n1244) );
OR2X1TS U2128 ( .A(n1666), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .Y(
n1239) );
INVX2TS U2129 ( .A(n1241), .Y(n1242) );
XOR2X1TS U2130 ( .A(n1250), .B(n1242), .Y(n1243) );
BUFX3TS U2131 ( .A(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .Y(n1324) );
NAND2X1TS U2132 ( .A(n1246), .B(n1245), .Y(n1251) );
XNOR2X1TS U2133 ( .A(n1247), .B(n1251), .Y(n1254) );
NOR2X1TS U2134 ( .A(n1664), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .Y(
n1249) );
NAND2X1TS U2135 ( .A(n1664), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]),
.Y(n1248) );
OAI21X4TS U2136 ( .A0(n1250), .A1(n1249), .B0(n1248), .Y(n1258) );
INVX2TS U2137 ( .A(n1251), .Y(n1252) );
XNOR2X1TS U2138 ( .A(n1258), .B(n1252), .Y(n1253) );
XOR2X1TS U2139 ( .A(n1255), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n1261) );
OR2X1TS U2140 ( .A(n1665), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .Y(
n1257) );
AOI21X1TS U2141 ( .A0(n1258), .A1(n1257), .B0(n1256), .Y(n1259) );
XOR2X1TS U2142 ( .A(n1259), .B(n1697), .Y(n1260) );
NAND2X1TS U2143 ( .A(n1263), .B(n1262), .Y(n1265) );
XNOR2X1TS U2144 ( .A(n1264), .B(n1265), .Y(n1269) );
INVX2TS U2145 ( .A(n1265), .Y(n1266) );
XNOR2X1TS U2146 ( .A(n1267), .B(n1266), .Y(n1268) );
INVX2TS U2147 ( .A(n1270), .Y(n1272) );
NAND2X1TS U2148 ( .A(n1272), .B(n1271), .Y(n1274) );
XOR2X1TS U2149 ( .A(n1273), .B(n1274), .Y(n1278) );
INVX2TS U2150 ( .A(n1274), .Y(n1275) );
XOR2X1TS U2151 ( .A(n1276), .B(n1275), .Y(n1277) );
NAND2X1TS U2152 ( .A(n1280), .B(n1279), .Y(n1282) );
XNOR2X1TS U2153 ( .A(n1281), .B(n1282), .Y(n1286) );
INVX2TS U2154 ( .A(n1282), .Y(n1283) );
XNOR2X1TS U2155 ( .A(n1284), .B(n1283), .Y(n1285) );
INVX2TS U2156 ( .A(n1287), .Y(n1289) );
NAND2X1TS U2157 ( .A(n1289), .B(n1288), .Y(n1291) );
XOR2X1TS U2158 ( .A(n1290), .B(n1291), .Y(n1295) );
INVX2TS U2159 ( .A(n1291), .Y(n1292) );
XOR2X1TS U2160 ( .A(n1293), .B(n1292), .Y(n1294) );
NAND2X1TS U2161 ( .A(n1297), .B(n1296), .Y(n1299) );
XNOR2X1TS U2162 ( .A(n1298), .B(n1299), .Y(n1303) );
INVX2TS U2163 ( .A(n1299), .Y(n1300) );
XNOR2X1TS U2164 ( .A(n1301), .B(n1300), .Y(n1302) );
NAND2X1TS U2165 ( .A(n1305), .B(n1304), .Y(n1310) );
XOR2X1TS U2166 ( .A(n1306), .B(n1310), .Y(n1314) );
INVX2TS U2167 ( .A(n1310), .Y(n1311) );
XNOR2X1TS U2168 ( .A(n1312), .B(n1311), .Y(n1313) );
AOI21X1TS U2169 ( .A0(n1329), .A1(n1328), .B0(n1316), .Y(n1320) );
NAND2X1TS U2170 ( .A(n1319), .B(n1318), .Y(n1321) );
XOR2X1TS U2171 ( .A(n1320), .B(n1321), .Y(n1326) );
INVX2TS U2172 ( .A(n1321), .Y(n1322) );
XOR2X1TS U2173 ( .A(n1323), .B(n1322), .Y(n1325) );
NAND2X1TS U2174 ( .A(n1328), .B(n1327), .Y(n1334) );
XNOR2X1TS U2175 ( .A(n1329), .B(n1334), .Y(n1338) );
AOI21X1TS U2176 ( .A0(n1346), .A1(n1333), .B0(n1332), .Y(n1336) );
INVX2TS U2177 ( .A(n1334), .Y(n1335) );
XOR2X1TS U2178 ( .A(n1336), .B(n1335), .Y(n1337) );
NAND2X1TS U2179 ( .A(n1342), .B(n1341), .Y(n1344) );
XNOR2X1TS U2180 ( .A(n1343), .B(n1344), .Y(n1348) );
INVX2TS U2181 ( .A(n1344), .Y(n1345) );
XNOR2X1TS U2182 ( .A(n1346), .B(n1345), .Y(n1347) );
NAND2X1TS U2183 ( .A(n1351), .B(n1350), .Y(n1356) );
XOR2X1TS U2184 ( .A(n1352), .B(n1356), .Y(n1360) );
INVX2TS U2185 ( .A(n1353), .Y(n1366) );
INVX2TS U2186 ( .A(n1356), .Y(n1357) );
XNOR2X1TS U2187 ( .A(n1358), .B(n1357), .Y(n1359) );
NAND2X1TS U2188 ( .A(n1363), .B(n1362), .Y(n1364) );
XOR2X1TS U2189 ( .A(n1364), .B(n1369), .Y(n1368) );
INVX2TS U2190 ( .A(n1364), .Y(n1365) );
XOR2X1TS U2191 ( .A(n1366), .B(n1365), .Y(n1367) );
OR2X1TS U2192 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n1370) );
XOR2X1TS U2193 ( .A(n1373), .B(n1371), .Y(n1372) );
XNOR2X1TS U2194 ( .A(inst_FPU_PIPELINED_FPADDSUB_N60), .B(n1601), .Y(n1375)
);
XOR2X1TS U2195 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27]), .Y(n1376) );
AOI22X1TS U2196 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(
n1377), .B1(n661), .Y(n1779) );
NOR2BX1TS U2197 ( .AN(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(
inst_FPU_PIPELINED_FPADDSUB__19_net_) );
XOR2X1TS U2198 ( .A(d_ff3_sign_out), .B(cont_var_out[0]), .Y(n1378) );
XNOR2X1TS U2199 ( .A(n1379), .B(n1378), .Y(n1698) );
XNOR2X1TS U2200 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .B(n1778),
.Y(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_INIT) );
INVX2TS U2201 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .Y(n1505) );
AOI22X1TS U2202 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .B0(n1505), .B1(n1650),
.Y(n1386) );
AOI22X1TS U2203 ( .A0(n638), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]),
.B0(n655), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .Y(n1380)
);
INVX2TS U2204 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .Y(n1491) );
AOI22X1TS U2205 ( .A0(n1634), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .B0(n652), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .Y(n1381) );
AOI22X1TS U2206 ( .A0(n637), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]),
.B0(n650), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .Y(n1382)
);
NOR4X1TS U2207 ( .A(n1386), .B(n1385), .C(n1384), .D(n1383), .Y(n1414) );
INVX2TS U2208 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .Y(n1499) );
AOI22X1TS U2209 ( .A0(n1649), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]),
.B0(n658), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .Y(n1387)
);
INVX2TS U2210 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .Y(n1497) );
INVX2TS U2211 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .Y(n1496) );
AOI22X1TS U2212 ( .A0(n1648), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]),
.B0(n1606), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .Y(n1388)
);
AOI22X1TS U2213 ( .A0(n634), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]),
.B0(n651), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .Y(n1389)
);
AOI22X1TS U2214 ( .A0(n636), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]),
.B0(n654), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .Y(n1390)
);
NOR4X1TS U2215 ( .A(n1394), .B(n1393), .C(n1392), .D(n1391), .Y(n1413) );
INVX2TS U2216 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .Y(n1498) );
AOI22X1TS U2217 ( .A0(n1509), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .B0(n1608), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .Y(n1395) );
AOI22X1TS U2218 ( .A0(n649), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]),
.B0(n1636), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .Y(n1396)
);
AOI22X1TS U2219 ( .A0(n640), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]),
.B0(n659), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .Y(n1397)
);
AOI22X1TS U2220 ( .A0(n635), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]),
.B0(n653), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .Y(n1398)
);
NOR4X1TS U2221 ( .A(n1402), .B(n1401), .C(n1400), .D(n1399), .Y(n1412) );
AOI22X1TS U2222 ( .A0(n657), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]),
.B0(n1637), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .Y(n1403)
);
AOI22X1TS U2223 ( .A0(n656), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]),
.B0(n639), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .Y(n1404)
);
INVX2TS U2224 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .Y(n1503) );
AOI22X1TS U2225 ( .A0(n648), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]),
.B0(n1503), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .Y(n1405)
);
AOI22X1TS U2226 ( .A0(n660), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]),
.B0(n630), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .Y(n1406)
);
OAI221XLTS U2227 ( .A0(n660), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .B0(n630), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .C0(n1406), .Y(
n1407) );
NOR4X1TS U2228 ( .A(n1410), .B(n1409), .C(n1408), .D(n1407), .Y(n1411) );
NOR2BX1TS U2229 ( .AN(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_INIT), .B(n1483),
.Y(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_INIT) );
NOR2X1TS U2230 ( .A(n1686), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]),
.Y(n1476) );
AOI22X1TS U2231 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .A1(n1686), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B1(n1415), .Y(n1419) );
OAI21X1TS U2232 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .A1(n1691), .B0(n1416), .Y(n1477) );
OAI211X1TS U2233 ( .A0(n1419), .A1(n1477), .B0(n1418), .C0(n1417), .Y(n1424)
);
NOR2X1TS U2234 ( .A(n1603), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]),
.Y(n1422) );
NOR2X1TS U2235 ( .A(n1622), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]),
.Y(n1420) );
NOR3X1TS U2236 ( .A(n1651), .B(n1420), .C(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .Y(n1421) );
NOR2X1TS U2237 ( .A(n1684), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]),
.Y(n1462) );
NOR2X1TS U2238 ( .A(n1687), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]),
.Y(n1440) );
AOI21X1TS U2239 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .A1(n1491), .B0(n1440), .Y(n1445) );
OAI2BB1X1TS U2240 ( .A0N(n1497), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .Y(n1425) );
OAI22X1TS U2241 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .A1(n1425),
.B0(n1497), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .Y(n1437)
);
OAI2BB1X1TS U2242 ( .A0N(n1499), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .Y(n1426) );
OAI22X1TS U2243 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .A1(n1426),
.B0(n1499), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .Y(n1436)
);
INVX2TS U2244 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .Y(n1431) );
OAI2BB2XLTS U2245 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .B1(
n1427), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1N(n1688),
.Y(n1429) );
OAI211X1TS U2246 ( .A0(n1431), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .B0(n1429), .C0(n1428), .Y(n1433) );
AOI222X1TS U2247 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .A1(n1496), .B0(n1433), .B1(n1432), .C0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .C1(
n1497), .Y(n1435) );
AOI22X1TS U2248 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .A1(n1499),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .B1(n1498), .Y(n1434)
);
OAI32X1TS U2249 ( .A0(n1437), .A1(n1436), .A2(n1435), .B0(n1434), .B1(n1436),
.Y(n1456) );
INVX2TS U2250 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .Y(n1448) );
OAI2BB2XLTS U2251 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B1(
n1439), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1N(n1675),
.Y(n1452) );
AOI22X1TS U2252 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .A1(n1687), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .B1(n1441), .Y(n1447) );
AOI21X1TS U2253 ( .A0(n1444), .A1(n1443), .B0(n1455), .Y(n1446) );
OAI2BB2XLTS U2254 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .B1(
n1449), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1N(n1448),
.Y(n1450) );
AOI211X1TS U2255 ( .A0(n1453), .A1(n1452), .B0(n1451), .C0(n1450), .Y(n1454)
);
OAI31X1TS U2256 ( .A0(n1457), .A1(n1456), .A2(n1455), .B0(n1454), .Y(n1460)
);
OA22X1TS U2257 ( .A0(n1679), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]),
.B0(n1609), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .Y(n1473)
);
OAI21X1TS U2258 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .A1(n1685), .B0(n1464), .Y(n1468) );
NAND3BX1TS U2259 ( .AN(n1462), .B(n1460), .C(n1459), .Y(n1480) );
OAI2BB2XLTS U2260 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B1(
n1461), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1N(n1676),
.Y(n1472) );
AOI22X1TS U2261 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .A1(n1684), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .B1(n1463), .Y(n1466) );
OAI32X1TS U2262 ( .A0(n1468), .A1(n1467), .A2(n1466), .B0(n1465), .B1(n1467),
.Y(n1471) );
OAI2BB2XLTS U2263 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .B1(
n1469), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .A1N(n1505),
.Y(n1470) );
AOI211X1TS U2264 ( .A0(n1473), .A1(n1472), .B0(n1471), .C0(n1470), .Y(n1479)
);
NAND4BBX1TS U2265 ( .AN(n1477), .BN(n1476), .C(n1475), .D(n1474), .Y(n1478)
);
INVX2TS U2266 ( .A(n1508), .Y(n1511) );
AOI21X1TS U2267 ( .A0(n1483), .A1(n1504), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .Y(n1484) );
AOI21X1TS U2268 ( .A0(n1778), .A1(n1502), .B0(n1484), .Y(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_INIT) );
AOI32X1TS U2269 ( .A0(cont_iter_out[3]), .A1(n1485), .A2(n1613), .B0(
cont_iter_out[2]), .B1(n1485), .Y(data_out_LUT[4]) );
OAI22X1TS U2270 ( .A0(cont_iter_out[3]), .A1(n1543), .B0(cont_iter_out[2]),
.B1(n1544), .Y(data_out_LUT[25]) );
NAND2X1TS U2271 ( .A(d_ff1_operation_out), .B(d_ff1_shift_region_flag_out[1]), .Y(n1488) );
XOR2X1TS U2272 ( .A(n690), .B(n1486), .Y(n1487) );
BUFX3TS U2273 ( .A(n1531), .Y(n1529) );
INVX2TS U2274 ( .A(n1529), .Y(n1525) );
AOI22X1TS U2275 ( .A0(n1525), .A1(d_ff_Yn[31]), .B0(d_ff_Xn[31]), .B1(n1529),
.Y(n1490) );
XNOR2X1TS U2276 ( .A(n1490), .B(n1489), .Y(fmtted_Result_31_) );
AOI22X1TS U2277 ( .A0(n1482), .A1(n1692), .B0(n654), .B1(n1502), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[0]) );
AOI22X1TS U2278 ( .A0(n1482), .A1(n1688), .B0(n636), .B1(n1504), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[1]) );
AOI22X1TS U2279 ( .A0(n1482), .A1(n1677), .B0(n652), .B1(n1511), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[2]) );
AOI22X1TS U2280 ( .A0(n1482), .A1(n1689), .B0(n634), .B1(n1510), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[3]) );
AOI22X1TS U2281 ( .A0(n1482), .A1(n1672), .B0(n1496), .B1(n1492), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[4]) );
INVX2TS U2282 ( .A(n1508), .Y(n1492) );
AOI22X1TS U2283 ( .A0(n1482), .A1(n1663), .B0(n1497), .B1(n1511), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[5]) );
AOI22X1TS U2284 ( .A0(n1482), .A1(n1670), .B0(n1498), .B1(n1494), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[6]) );
AOI22X1TS U2285 ( .A0(n1493), .A1(n1662), .B0(n1499), .B1(n1510), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[7]) );
AOI22X1TS U2286 ( .A0(n1493), .A1(n1683), .B0(n656), .B1(n1492), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[8]) );
AOI22X1TS U2287 ( .A0(n1493), .A1(n1680), .B0(n637), .B1(n1494), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[9]) );
AOI22X1TS U2288 ( .A0(n1493), .A1(n1673), .B0(n1491), .B1(n1502), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[10]) );
AOI22X1TS U2289 ( .A0(n1493), .A1(n1687), .B0(n650), .B1(n1504), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[11]) );
AOI22X1TS U2290 ( .A0(n1493), .A1(n1682), .B0(n630), .B1(n1511), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[12]) );
AOI22X1TS U2291 ( .A0(n1493), .A1(n1675), .B0(n655), .B1(n1510), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[13]) );
AOI22X1TS U2292 ( .A0(n1493), .A1(n1611), .B0(n658), .B1(n1492), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[14]) );
AOI22X1TS U2293 ( .A0(n1493), .A1(n1690), .B0(n638), .B1(n1494), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[15]) );
INVX2TS U2294 ( .A(n1508), .Y(n1494) );
AOI22X1TS U2295 ( .A0(n1493), .A1(n1671), .B0(n1503), .B1(n1492), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[16]) );
BUFX3TS U2296 ( .A(n1501), .Y(n1495) );
AOI22X1TS U2297 ( .A0(n1495), .A1(n1684), .B0(n648), .B1(n1494), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[17]) );
AOI22X1TS U2298 ( .A0(n1495), .A1(n1685), .B0(n649), .B1(n1502), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[18]) );
AOI22X1TS U2299 ( .A0(n1495), .A1(n1610), .B0(n659), .B1(n1504), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[19]) );
AOI22X1TS U2300 ( .A0(n1495), .A1(n1678), .B0(n657), .B1(n1511), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[20]) );
AOI22X1TS U2301 ( .A0(n1495), .A1(n1676), .B0(n639), .B1(n1510), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[21]) );
AOI22X1TS U2302 ( .A0(n1495), .A1(n1679), .B0(n660), .B1(n1492), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[22]) );
AOI22X1TS U2303 ( .A0(n1495), .A1(n1505), .B0(n1650), .B1(n1494), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[23]) );
AOI22X1TS U2304 ( .A0(n1495), .A1(n1674), .B0(n653), .B1(n1502), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[24]) );
AOI22X1TS U2305 ( .A0(n1495), .A1(n1686), .B0(n635), .B1(n1504), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[25]) );
INVX2TS U2306 ( .A(n1508), .Y(n1504) );
AOI22X1TS U2307 ( .A0(n1495), .A1(n1691), .B0(n651), .B1(n1502), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[26]) );
BUFX3TS U2308 ( .A(n1501), .Y(n1500) );
AOI22X1TS U2309 ( .A0(n1500), .A1(n1681), .B0(n640), .B1(n1504), .Y(
inst_FPU_PIPELINED_FPADDSUB_DmP_INIT_EWSW[27]) );
AOI22X1TS U2310 ( .A0(n1500), .A1(n654), .B0(n1692), .B1(n1511), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[0]) );
AOI22X1TS U2311 ( .A0(n1500), .A1(n636), .B0(n1688), .B1(n1510), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[1]) );
AOI22X1TS U2312 ( .A0(n1500), .A1(n652), .B0(n1677), .B1(n1492), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[2]) );
AOI22X1TS U2313 ( .A0(n1500), .A1(n634), .B0(n1689), .B1(n1494), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[3]) );
AOI22X1TS U2314 ( .A0(n1500), .A1(n1496), .B0(n1672), .B1(n1502), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[4]) );
AOI22X1TS U2315 ( .A0(n1500), .A1(n1497), .B0(n1663), .B1(n1504), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[5]) );
AOI22X1TS U2316 ( .A0(n1500), .A1(n1498), .B0(n1670), .B1(n1511), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[6]) );
AOI22X1TS U2317 ( .A0(n1500), .A1(n1499), .B0(n1662), .B1(n1511), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[7]) );
AOI22X1TS U2318 ( .A0(n1500), .A1(n656), .B0(n1683), .B1(n1510), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[8]) );
AOI22X1TS U2319 ( .A0(n1508), .A1(n637), .B0(n1680), .B1(n1492), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[9]) );
AOI22X1TS U2320 ( .A0(n1508), .A1(n1634), .B0(n1673), .B1(n1494), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[10]) );
AOI22X1TS U2321 ( .A0(n1501), .A1(n650), .B0(n1687), .B1(n1502), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[11]) );
AOI22X1TS U2322 ( .A0(n1501), .A1(n630), .B0(n1682), .B1(n1504), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[12]) );
AOI22X1TS U2323 ( .A0(n1508), .A1(n655), .B0(n1675), .B1(n1511), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[13]) );
AOI22X1TS U2324 ( .A0(n1501), .A1(n658), .B0(n1611), .B1(n1510), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[14]) );
AOI22X1TS U2325 ( .A0(n1501), .A1(n638), .B0(n1690), .B1(n1492), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[15]) );
AOI22X1TS U2326 ( .A0(n1501), .A1(n1503), .B0(n1671), .B1(n1494), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[16]) );
AOI22X1TS U2327 ( .A0(n1501), .A1(n648), .B0(n1684), .B1(n1510), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[17]) );
AOI22X1TS U2328 ( .A0(n1482), .A1(n649), .B0(n1685), .B1(n1506), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[18]) );
AOI22X1TS U2329 ( .A0(n1507), .A1(n659), .B0(n1610), .B1(n1506), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[19]) );
AOI22X1TS U2330 ( .A0(n1507), .A1(n657), .B0(n1678), .B1(n1506), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[20]) );
AOI22X1TS U2331 ( .A0(n1507), .A1(n639), .B0(n1676), .B1(n1506), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[21]) );
AOI22X1TS U2332 ( .A0(n1507), .A1(n660), .B0(n1679), .B1(n1506), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[22]) );
AOI22X1TS U2333 ( .A0(n1507), .A1(n1650), .B0(n1505), .B1(n1506), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[23]) );
AOI22X1TS U2334 ( .A0(n1507), .A1(n653), .B0(n1674), .B1(n1506), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[24]) );
AOI22X1TS U2335 ( .A0(n1507), .A1(n635), .B0(n1686), .B1(n1506), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[25]) );
AOI22X1TS U2336 ( .A0(n1507), .A1(n651), .B0(n1691), .B1(n1506), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[26]) );
AOI22X1TS U2337 ( .A0(n1507), .A1(n640), .B0(n1681), .B1(n1506), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[27]) );
INVX2TS U2338 ( .A(n1508), .Y(n1510) );
OAI2BB2XLTS U2339 ( .B0(n1510), .B1(n1509), .A0N(n1504), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U2340 ( .B0(n1511), .B1(n1637), .A0N(n1502), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .Y(
inst_FPU_PIPELINED_FPADDSUB_DMP_INIT_EWSW[30]) );
OAI22X1TS U2341 ( .A0(n1512), .A1(n681), .B0(n642), .B1(n632), .Y(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]) );
BUFX3TS U2342 ( .A(n688), .Y(n1519) );
NOR2BX1TS U2343 ( .AN(d_ff_Yn[0]), .B(n1515), .Y(first_mux_Y[0]) );
NOR2BX1TS U2344 ( .AN(d_ff_Yn[1]), .B(n1515), .Y(first_mux_Y[1]) );
NOR2BX1TS U2345 ( .AN(d_ff_Yn[2]), .B(n1515), .Y(first_mux_Y[2]) );
NOR2BX1TS U2346 ( .AN(d_ff_Yn[3]), .B(n1515), .Y(first_mux_Y[3]) );
NOR2BX1TS U2347 ( .AN(d_ff_Yn[4]), .B(n1515), .Y(first_mux_Y[4]) );
NOR2BX1TS U2348 ( .AN(d_ff_Yn[5]), .B(n1515), .Y(first_mux_Y[5]) );
NOR2BX1TS U2349 ( .AN(d_ff_Yn[6]), .B(n1515), .Y(first_mux_Y[6]) );
NOR2BX1TS U2350 ( .AN(d_ff_Yn[7]), .B(n1515), .Y(first_mux_Y[7]) );
NOR2BX1TS U2351 ( .AN(d_ff_Yn[8]), .B(n1515), .Y(first_mux_Y[8]) );
NOR2BX1TS U2352 ( .AN(d_ff_Yn[9]), .B(n1515), .Y(first_mux_Y[9]) );
BUFX3TS U2353 ( .A(n688), .Y(n1524) );
NOR2BX1TS U2354 ( .AN(d_ff_Yn[10]), .B(n1516), .Y(first_mux_Y[10]) );
NOR2BX1TS U2355 ( .AN(d_ff_Yn[11]), .B(n1535), .Y(first_mux_Y[11]) );
NOR2BX1TS U2356 ( .AN(d_ff_Yn[12]), .B(n1522), .Y(first_mux_Y[12]) );
NOR2BX1TS U2357 ( .AN(d_ff_Yn[13]), .B(n1520), .Y(first_mux_Y[13]) );
NOR2BX1TS U2358 ( .AN(d_ff_Yn[14]), .B(n1516), .Y(first_mux_Y[14]) );
NOR2BX1TS U2359 ( .AN(d_ff_Yn[15]), .B(n1535), .Y(first_mux_Y[15]) );
NOR2BX1TS U2360 ( .AN(d_ff_Yn[16]), .B(n1522), .Y(first_mux_Y[16]) );
NOR2BX1TS U2361 ( .AN(d_ff_Yn[17]), .B(n1520), .Y(first_mux_Y[17]) );
NOR2BX1TS U2362 ( .AN(d_ff_Yn[18]), .B(n1516), .Y(first_mux_Y[18]) );
NOR2BX1TS U2363 ( .AN(d_ff_Yn[19]), .B(n1535), .Y(first_mux_Y[19]) );
NOR2BX1TS U2364 ( .AN(d_ff_Yn[20]), .B(n1517), .Y(first_mux_Y[20]) );
NOR2BX1TS U2365 ( .AN(d_ff_Yn[21]), .B(n1517), .Y(first_mux_Y[21]) );
NOR2BX1TS U2366 ( .AN(d_ff_Yn[22]), .B(n1517), .Y(first_mux_Y[22]) );
NOR2BX1TS U2367 ( .AN(d_ff_Yn[23]), .B(n1517), .Y(first_mux_Y[23]) );
NOR2BX1TS U2368 ( .AN(d_ff_Yn[24]), .B(n1517), .Y(first_mux_Y[24]) );
NOR2BX1TS U2369 ( .AN(d_ff_Yn[25]), .B(n1517), .Y(first_mux_Y[25]) );
NOR2BX1TS U2370 ( .AN(d_ff_Yn[26]), .B(n1517), .Y(first_mux_Y[26]) );
NOR2BX1TS U2371 ( .AN(d_ff_Yn[27]), .B(n1517), .Y(first_mux_Y[27]) );
NOR2BX1TS U2372 ( .AN(d_ff_Yn[28]), .B(n1517), .Y(first_mux_Y[28]) );
NOR2BX1TS U2373 ( .AN(d_ff_Yn[29]), .B(n1517), .Y(first_mux_Y[29]) );
INVX2TS U2374 ( .A(n1524), .Y(n1534) );
NOR2BX1TS U2375 ( .AN(d_ff_Yn[30]), .B(n1516), .Y(first_mux_Y[30]) );
NOR2BX1TS U2376 ( .AN(d_ff_Yn[31]), .B(n1522), .Y(first_mux_Y[31]) );
BUFX3TS U2377 ( .A(n1524), .Y(n1521) );
BUFX3TS U2378 ( .A(n1524), .Y(n1523) );
BUFX3TS U2379 ( .A(n1531), .Y(n1526) );
INVX2TS U2380 ( .A(n1528), .Y(n1527) );
INVX2TS U2381 ( .A(n1528), .Y(n1530) );
INVX2TS U2382 ( .A(n1528), .Y(n1532) );
NOR2BX1TS U2383 ( .AN(d_ff_Xn[0]), .B(n1522), .Y(first_mux_X[0]) );
NOR2BX1TS U2384 ( .AN(d_ff_Xn[4]), .B(n1520), .Y(first_mux_X[4]) );
NOR2BX1TS U2385 ( .AN(d_ff_Xn[8]), .B(n1516), .Y(first_mux_X[8]) );
NOR2BX1TS U2386 ( .AN(d_ff_Xn[9]), .B(n1520), .Y(first_mux_X[9]) );
NOR2BX1TS U2387 ( .AN(d_ff_Xn[11]), .B(n1535), .Y(first_mux_X[11]) );
NOR2BX1TS U2388 ( .AN(d_ff_Xn[15]), .B(n1516), .Y(first_mux_X[15]) );
NOR2BX1TS U2389 ( .AN(d_ff_Xn[18]), .B(n1522), .Y(first_mux_X[18]) );
NOR2BX1TS U2390 ( .AN(d_ff_Xn[21]), .B(n1520), .Y(first_mux_X[21]) );
NOR2BX1TS U2391 ( .AN(d_ff_Xn[22]), .B(n1535), .Y(first_mux_X[22]) );
NOR2BX1TS U2392 ( .AN(d_ff_Xn[23]), .B(n1522), .Y(first_mux_X[23]) );
NOR2BX1TS U2393 ( .AN(d_ff_Xn[30]), .B(n1520), .Y(first_mux_X[30]) );
NOR2BX1TS U2394 ( .AN(d_ff_Xn[31]), .B(n1535), .Y(first_mux_X[31]) );
NOR2BX1TS U2395 ( .AN(beg_fsm_cordic), .B(n1536), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U2396 ( .A0(n631), .A1(n1542), .B0(n1541), .B1(n1540), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U2397 ( .AN(n631), .B(n1542), .Y(inst_CORDIC_FSM_v3_state_next[6])
);
OA21XLTS U2399 ( .A0(cont_iter_out[2]), .A1(n1544), .B0(n1543), .Y(
ITER_CONT_N4) );
AOI22X1TS U2400 ( .A0(n1567), .A1(d_ff3_sh_y_out[29]), .B0(n1557), .B1(
d_ff3_sh_x_out[29]), .Y(n1547) );
NAND2X1TS U2401 ( .A(n1553), .B(d_ff3_LUT_out[27]), .Y(n1549) );
NAND2X1TS U2402 ( .A(n1547), .B(n1549), .Y(n622) );
AOI22X1TS U2403 ( .A0(n1567), .A1(d_ff3_sh_y_out[28]), .B0(n1557), .B1(
d_ff3_sh_x_out[28]), .Y(n1548) );
NAND2X1TS U2404 ( .A(n1548), .B(n1549), .Y(n621) );
AOI22X1TS U2405 ( .A0(n1567), .A1(d_ff3_sh_y_out[27]), .B0(n1557), .B1(
d_ff3_sh_x_out[27]), .Y(n1550) );
NAND2X1TS U2406 ( .A(n1550), .B(n1549), .Y(n620) );
BUFX3TS U2407 ( .A(n1551), .Y(n1570) );
AOI22X1TS U2408 ( .A0(n1567), .A1(d_ff3_sh_y_out[22]), .B0(n1566), .B1(
d_ff3_sh_x_out[22]), .Y(n1552) );
OAI2BB1X1TS U2409 ( .A0N(n1570), .A1N(d_ff3_LUT_out[19]), .B0(n1552), .Y(
n615) );
AOI22X1TS U2410 ( .A0(n1567), .A1(d_ff3_sh_y_out[20]), .B0(n1566), .B1(
d_ff3_sh_x_out[20]), .Y(n1554) );
NAND2X1TS U2411 ( .A(n1553), .B(d_ff3_LUT_out[15]), .Y(n1561) );
NAND2X1TS U2412 ( .A(n1554), .B(n1561), .Y(n613) );
AOI22X1TS U2413 ( .A0(n1567), .A1(d_ff3_sh_y_out[19]), .B0(n1555), .B1(
d_ff3_sh_x_out[19]), .Y(n1556) );
OAI2BB1X1TS U2414 ( .A0N(n1570), .A1N(d_ff3_LUT_out[19]), .B0(n1556), .Y(
n612) );
AOI22X1TS U2415 ( .A0(n1567), .A1(d_ff3_sh_y_out[18]), .B0(n1557), .B1(
d_ff3_sh_x_out[18]), .Y(n1558) );
OAI2BB1X1TS U2416 ( .A0N(n1570), .A1N(d_ff3_LUT_out[13]), .B0(n1558), .Y(
n611) );
AOI22X1TS U2417 ( .A0(n1567), .A1(d_ff3_sh_y_out[17]), .B0(n1566), .B1(
d_ff3_sh_x_out[17]), .Y(n1559) );
NAND2X1TS U2418 ( .A(n1559), .B(n1561), .Y(n610) );
AOI22X1TS U2419 ( .A0(n901), .A1(d_ff3_sh_y_out[16]), .B0(n849), .B1(
d_ff3_sh_x_out[16]), .Y(n1560) );
OAI2BB1X1TS U2420 ( .A0N(n1570), .A1N(d_ff3_LUT_out[3]), .B0(n1560), .Y(n609) );
AOI22X1TS U2421 ( .A0(n901), .A1(d_ff3_sh_y_out[15]), .B0(n849), .B1(
d_ff3_sh_x_out[15]), .Y(n1562) );
NAND2X1TS U2422 ( .A(n1562), .B(n1561), .Y(n608) );
AOI22X1TS U2423 ( .A0(n1567), .A1(d_ff3_sh_y_out[14]), .B0(n1566), .B1(
d_ff3_sh_x_out[14]), .Y(n1563) );
OAI2BB1X1TS U2424 ( .A0N(n1570), .A1N(d_ff3_LUT_out[5]), .B0(n1563), .Y(n607) );
AOI22X1TS U2425 ( .A0(n846), .A1(d_ff3_sh_y_out[13]), .B0(n849), .B1(
d_ff3_sh_x_out[13]), .Y(n1564) );
OAI2BB1X1TS U2426 ( .A0N(n1570), .A1N(d_ff3_LUT_out[13]), .B0(n1564), .Y(
n606) );
AOI22X1TS U2427 ( .A0(n1545), .A1(d_ff3_sh_y_out[11]), .B0(n849), .B1(
d_ff3_sh_x_out[11]), .Y(n1565) );
OAI2BB1X1TS U2428 ( .A0N(n1570), .A1N(d_ff3_LUT_out[7]), .B0(n1565), .Y(n604) );
AOI22X1TS U2429 ( .A0(n1567), .A1(d_ff3_sh_y_out[7]), .B0(n1566), .B1(
d_ff3_sh_x_out[7]), .Y(n1568) );
OAI2BB1X1TS U2430 ( .A0N(n1570), .A1N(d_ff3_LUT_out[7]), .B0(n1568), .Y(n600) );
AOI22X1TS U2431 ( .A0(n1545), .A1(d_ff3_sh_y_out[5]), .B0(n849), .B1(
d_ff3_sh_x_out[5]), .Y(n1569) );
OAI2BB1X1TS U2432 ( .A0N(n1570), .A1N(d_ff3_LUT_out[5]), .B0(n1569), .Y(n598) );
AOI22X1TS U2433 ( .A0(n901), .A1(d_ff3_sh_y_out[3]), .B0(n1557), .B1(
d_ff3_sh_x_out[3]), .Y(n1572) );
OAI2BB1X1TS U2434 ( .A0N(n1573), .A1N(d_ff3_LUT_out[3]), .B0(n1572), .Y(n596) );
AOI22X1TS U2435 ( .A0(cont_iter_out[1]), .A1(n1576), .B0(n1574), .B1(n662),
.Y(n555) );
AOI22X1TS U2436 ( .A0(cont_iter_out[1]), .A1(n1576), .B0(n1575), .B1(n1613),
.Y(n547) );
OAI2BB1X1TS U2437 ( .A0N(cont_iter_out[1]), .A1N(n545), .B0(n1577), .Y(n546)
);
AOI22X1TS U2438 ( .A0(cont_iter_out[1]), .A1(n1579), .B0(n1578), .B1(n1613),
.Y(n542) );
OAI22X1TS U2439 ( .A0(n1583), .A1(n1582), .B0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(
n1581), .Y(n541) );
AOI22X1TS U2440 ( .A0(cont_var_out[0]), .A1(n1585), .B0(n1584), .B1(n1612),
.Y(n540) );
XNOR2X1TS U2442 ( .A(d_ff2_Y[29]), .B(n1588), .Y(sh_exp_y[6]) );
XNOR2X1TS U2443 ( .A(d_ff2_X[29]), .B(n1591), .Y(sh_exp_x[6]) );
initial $sdf_annotate("CORDIC_Arch3_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
|
/*
* RawaPro.v
*
* Created on: 09/10/2012
* Author: Lord_Rafa
*/
`timescale 1ns / 1ps
module RawaPro (
// inputs:
top_HC_ADC_DOUT,
top_HC_ADC_PENIRQ_N,
top_HC_RX_CLK,
top_HC_RX_COL,
top_HC_RX_CRS,
top_HC_RX_D,
top_HC_RX_DV,
top_HC_RX_ERR,
top_HC_SD_DAT,
top_HC_TX_CLK,
top_HC_UART_RXD,
top_button,
top_clkin_50,
top_reset_n,
// outputs:
top_HC_ADC_CS_N,
top_HC_ADC_DCLK,
top_HC_ADC_DIN,
top_HC_DEN,
top_HC_ETH_RESET_N,
top_HC_HD,
top_HC_ID_I2CDAT,
top_HC_ID_I2CSCL,
top_HC_LCD_DATA,
top_HC_MDC,
top_HC_MDIO,
top_HC_SCEN,
top_HC_SDA,
top_HC_SD_CLK,
top_HC_SD_CMD,
top_HC_SD_DAT3,
top_HC_TX_D,
top_HC_TX_EN,
top_HC_UART_TXD,
top_HC_VD,
top_clk_to_offchip_video,
top_flash_cs_n,
top_flash_oe_n,
top_flash_reset_n,
top_flash_ssram_a,
top_flash_ssram_d,
top_flash_wr_n,
top_led,
top_mem_addr,
top_mem_ba,
top_mem_cas_n,
top_mem_cke,
top_mem_clk,
top_mem_clk_n,
top_mem_cs_n,
top_mem_dm,
top_mem_dq,
top_mem_dqs,
top_mem_ras_n,
top_mem_we_n,
top_ssram_adsc_n,
top_ssram_bw_n,
top_ssram_bwe_n,
top_ssram_ce_n,
top_ssram_clk,
top_ssram_oe_n,
top_HC_TD_D,
top_HC_TD_HS,
top_HC_TD_VS,
top_HC_TD_27MHZ,
top_HC_TD_RESET,
top_HC_I2C_SCLK,
top_HC_I2C_SDAT,
top_HC_GREST
);
output top_HC_ADC_CS_N;
output top_HC_ADC_DCLK;
output top_HC_ADC_DIN;
output top_HC_DEN;
output top_HC_ETH_RESET_N;
output top_HC_HD;
inout top_HC_ID_I2CDAT;
output top_HC_ID_I2CSCL;
output [ 7: 0] top_HC_LCD_DATA;
output top_HC_MDC;
inout top_HC_MDIO;
output top_HC_SCEN;
inout top_HC_SDA;
output top_HC_SD_CLK;
output top_HC_SD_CMD;
output top_HC_SD_DAT3;
output [ 3: 0] top_HC_TX_D;
output top_HC_TX_EN;
output top_HC_UART_TXD;
output top_HC_VD;
output top_clk_to_offchip_video;
output top_flash_cs_n;
output top_flash_oe_n;
output top_flash_reset_n;
output [ 23: 1] top_flash_ssram_a;
inout [ 31: 0] top_flash_ssram_d;
output top_flash_wr_n;
output [ 3: 0] top_led;
output [ 12: 0] top_mem_addr;
output [ 1: 0] top_mem_ba;
output top_mem_cas_n;
output top_mem_cke;
inout top_mem_clk;
inout top_mem_clk_n;
output top_mem_cs_n;
output [ 1: 0] top_mem_dm;
inout [ 15: 0] top_mem_dq;
inout [ 1: 0] top_mem_dqs;
output top_mem_ras_n;
output top_mem_we_n;
output top_ssram_adsc_n;
output [ 3: 0] top_ssram_bw_n;
output top_ssram_bwe_n;
output top_ssram_ce_n;
output top_ssram_clk;
output top_ssram_oe_n;
input top_HC_ADC_DOUT;
input top_HC_ADC_PENIRQ_N;
input top_HC_RX_CLK;
input top_HC_RX_COL;
input top_HC_RX_CRS;
input [ 3: 0] top_HC_RX_D;
input top_HC_RX_DV;
input top_HC_RX_ERR;
input top_HC_SD_DAT;
input top_HC_TX_CLK;
input top_HC_UART_RXD;
input [ 3: 0] top_button;
input top_clkin_50;
input top_reset_n;
//TV Decoder
input [7:0] top_HC_TD_D;
input top_HC_TD_HS;
input top_HC_TD_VS;
input top_HC_TD_27MHZ;
output top_HC_TD_RESET;
// Audio and TV decoder I2C
output top_HC_I2C_SCLK;
inout top_HC_I2C_SDAT;
output top_HC_GREST;
wire top_CDn_to_the_el_camino_sd_card_controller;
wire top_HC_ADC_CS_N;
wire top_HC_ADC_DCLK;
wire top_HC_ADC_DIN;
wire top_HC_DEN;
wire top_HC_ETH_RESET_N;
wire top_HC_HD;
wire top_HC_ID_I2CDAT;
wire top_HC_ID_I2CSCL;
wire [ 7: 0] top_HC_LCD_DATA;
wire top_HC_MDC;
wire top_HC_MDIO;
wire top_HC_SCEN;
wire top_HC_SDA;
wire top_HC_SD_CLK;
wire top_HC_SD_CMD;
wire top_HC_SD_DAT3;
wire [ 3: 0] top_HC_TX_D;
wire top_HC_TX_EN;
wire top_HC_UART_TXD;
wire top_HC_VD;
wire top_SCLK_from_the_touch_panel_spi;
wire top_SS_n_from_the_touch_panel_spi;
wire top_WP_to_the_el_camino_sd_card_controller;
wire top_clk_to_offchip_video;
wire top_ddr_sdram_aux_full_rate_clk_out;
wire top_ddr_sdram_aux_half_rate_clk_out;
wire top_ddr_sdram_phy_clk_out;
wire top_flash_cs_n;
wire top_flash_oe_n;
wire top_flash_reset_n;
wire [ 23: 1] top_flash_ssram_a;
wire [ 31: 0] top_flash_ssram_d;
wire top_flash_wr_n;
wire [ 3: 0] top_in_port_to_the_button_pio;
wire [ 3: 0] top_led;
wire top_local_init_done_from_the_ddr_sdram;
wire top_local_refresh_ack_from_the_ddr_sdram;
wire top_local_wdata_req_from_the_ddr_sdram;
wire [ 12: 0] top_mem_addr;
wire [ 1: 0] top_mem_ba;
wire top_mem_cas_n;
wire top_mem_cke;
wire top_mem_clk;
wire top_mem_clk_n;
wire top_mem_cs_n;
wire [ 1: 0] top_mem_dm;
wire [ 15: 0] top_mem_dq;
wire [ 1: 0] top_mem_dqs;
wire top_mem_ras_n;
wire top_mem_we_n;
wire top_out_port_from_the_lcd_i2c_en;
wire top_out_port_from_the_lcd_i2c_scl;
wire top_peripheral_clk;
wire top_remote_update_clk;
wire top_reset_phy_clk_n_from_the_ddr_sdram;
wire top_ssram_adsc_n;
wire [ 3: 0] top_ssram_bw_n;
wire top_ssram_bwe_n;
wire top_ssram_ce_n;
wire top_ssram_clk;
wire top_ssram_oe_n;
wire h_sync;
wire v_sync;
wire video_in_valid;
wire video_in_locked;
wire [7:0] video_in_data;
wire lcd_base_clock;
wire lcd_clock; // *3 of the base clock
wire [23:0] LCD_DATA;
wire LCD_BLANK;
wire LCD_HS;
wire LCD_VS;
wire clk_100;
wire clk_33;
wire clk_120;
wire clk_40;
wire [3:0] led_pio_wire;
wire dmy;
SistemaPrincipal SistemaPrincipal_instance (
//*******************Reloj Principal*******************
.sys_clk_clk (top_clkin_50),
.reset_reset_n (top_reset_n),
//-----------------------------------------------------
//******************Relojes de Salida******************
.clk_100_clk (clk_100),
.clk_33_clk (clk_33),
.altpll_0_areset_conduit_export (0),
//-----------------------------------------------------
//******************Entrada de Video*******************
.bidir_port_to_and_from_the_av_i2c_data_pio (top_HC_I2C_SDAT),
.out_port_from_the_av_i2c_clk_pio (top_HC_I2C_SCLK),
.out_port_from_the_td_reset_pio (top_HC_TD_RESET),
.video_in_vid_clk (top_HC_TD_27MHZ),
.video_in_vid_data (video_in_data),
.video_in_vid_datavalid (video_in_valid),
.video_in_vid_locked (video_in_locked),
//-----------------------------------------------------
//*******************Salida de Video*******************
.out_port_from_the_lcd_i2c_en (top_out_port_from_the_lcd_i2c_en),
.out_port_from_the_lcd_i2c_scl (top_out_port_from_the_lcd_i2c_scl),
.bidir_port_to_and_from_the_lcd_i2c_sdat (top_HC_SDA),
.video_out_vid_clk (lcd_base_clock),
.video_out_vid_data (LCD_DATA),
.video_out_vid_datavalid (LCD_BLANK),
.video_out_vid_h_sync (LCD_HS),
.video_out_vid_v_sync (LCD_VS),
//-----------------------------------------------------
//*********************Memoria RAM*********************
.ddr_sdram_memory_mem_addr (top_mem_addr),
.ddr_sdram_memory_mem_ba (top_mem_ba),
.ddr_sdram_memory_mem_cas_n (top_mem_cas_n),
.ddr_sdram_memory_mem_cke (top_mem_cke),
.ddr_sdram_memory_mem_clk_n (top_mem_clk_n),
.ddr_sdram_memory_mem_clk (top_mem_clk),
.ddr_sdram_memory_mem_cs_n (top_mem_cs_n),
.ddr_sdram_memory_mem_dm (top_mem_dm),
.ddr_sdram_memory_mem_dq (top_mem_dq),
.ddr_sdram_memory_mem_dqs (top_mem_dqs),
.ddr_sdram_memory_mem_ras_n (top_mem_ras_n),
.ddr_sdram_memory_mem_we_n (top_mem_we_n),
.ddr_sdram_external_connection_reset_phy_clk_n (top_reset_phy_clk_n_from_the_ddr_sdram),
//-----------------------------------------------------
//************************Otros************************
.key_pio_export (top_in_port_to_the_button_pio),
.led_pio_export (led_pio_wire)
//-----------------------------------------------------
);
assign video_in_data = top_HC_TD_D;
assign video_in_valid = 1'b1;
assign video_in_locked = 1'b1;
vga_serial u_lcd_serial(
.data(LCD_DATA), .blank(LCD_BLANK), .hs(LCD_HS), .vs(LCD_VS),
.clk3(lcd_clock), .data3(top_HC_LCD_DATA), .blank3(top_HC_DEN), .hs3(h_sync), .vs3(v_sync)
);
assign lcd_clock = clk_100;
assign lcd_base_clock = clk_33;
assign top_clk_to_offchip_video = lcd_clock;
assign top_HC_HD = h_sync;
assign top_HC_VD = v_sync;
assign top_CDn_to_the_el_camino_sd_card_controller = 1'b0;
assign top_WP_to_the_el_camino_sd_card_controller = 1'b0;
assign top_HC_SCEN = top_out_port_from_the_lcd_i2c_en;
assign top_HC_ADC_DCLK = ~top_out_port_from_the_lcd_i2c_en ? top_out_port_from_the_lcd_i2c_scl: 0;
assign top_HC_GREST = 1'b1;
assign top_led = led_pio_wire;
assign top_HC_ETH_RESET_N = 1'b0;
assign top_in_port_to_the_button_pio = top_button;
endmodule
|
module EX(
input rst,
input[`RegDataWidth-1:0] shamt,
input[`ALUTypeWidth-1:0] AluType_EX,
input[`ALUOpWidth-1:0] AluOp_EX,
input AluSrcA_EX,
input AluSrcB_EX,
input RegDes_EX,
input ImmSigned_EX,
input is_jal_EX,
input[`RegAddrWidth-1:0] rt_EX,
input[`RegAddrWidth-1:0] rd_EX,
input[`RegDataWidth-1:0] imm_signed_EX,
input[`RegDataWidth-1:0] imm_unsigned_EX,
input[`RegDataWidth-1:0] hi,
input[`RegDataWidth-1:0] lo,
input[`RegDataWidth-1:0] rdata_1,
input[`RegDataWidth-1:0] rdata_2,
input[`InstAddrWidth-1:0] pc_plus4_EX,
// forwarded data
input[`RegDataWidth-1:0] data_out_MEM,
input[`RegDataWidth-1:0] data_out_WB,
input[`RegDataWidth-1:0] hi_MEM,
input[`RegDataWidth-1:0] hi_WB,
input[`RegDataWidth-1:0] lo_MEM,
input[`RegDataWidth-1:0] lo_WB,
// forward info
input[1:0] FWA,
input[1:0] FWB,
input[1:0] FWhi,
input[1:0] FWlo,
output[`RegAddrWidth-1:0] target_EX,
output is_Overflow,
output[`RegDataWidth-1:0] data_out_EX,
output we_hi,
output we_lo,
output[`RegDataWidth-1:0] hi_EX,
output[`RegDataWidth-1:0] lo_EX,
output[`RegDataWidth-1:0] rdata_2_EX
);
wire[`RegDataWidth-1:0] rdata_1_EX;
wire[`RegDataWidth-1:0] lo_in;
wire[`RegDataWidth-1:0] hi_in;
wire[`RegDataWidth-1:0] imm;
wire[`RegDataWidth-1:0] srcA;
wire[`RegDataWidth-1:0] srcB;
wire[`RegDataWidth-1:0] lo_temp;
wire[`RegDataWidth-1:0] hi_temp;
mux2x1 #(.data_width(`RegDataWidth)) imm_mux(
.in_0(imm_unsigned_EX),
.in_1(imm_signed_EX),
.slct(ImmSigned_EX),
.out(imm)
);
// Forwarding
mux4x1 #(.data_width(`RegDataWidth)) forwardA(
.in_00(rdata_1),
.in_01(data_out_MEM),
.in_10(data_out_WB),
.slct(FWA),
.out(rdata_1_EX)
);
mux4x1 #(.data_width(`RegDataWidth)) forwardB(
.in_00(rdata_2),
.in_01(data_out_MEM),
.in_10(data_out_WB),
.slct(FWB),
.out(rdata_2_EX)
);
mux4x1 #(.data_width(`RegDataWidth)) forwardHi(
.in_00(hi),
.in_01(hi_MEM),
.in_10(hi_WB),
.slct(FWhi),
.out(hi_in)
);
mux4x1 #(.data_width(`RegDataWidth)) forwardLo(
.in_00(lo),
.in_01(lo_MEM),
.in_10(lo_WB),
.slct(FWlo),
.out(lo_in)
);
mux2x1 #(.data_width(`RegDataWidth)) srcA_mux(
.in_0(shamt),
.in_1(rdata_1_EX),
.slct(AluSrcA_EX),
.out(srcA)
);
mux2x1 #(.data_width(`RegDataWidth)) srcB_mux(
.in_0(rdata_2_EX),
.in_1(imm),
.slct(AluSrcB_EX),
.out(srcB)
);
wire[`RegAddrWidth-1:0] target_temp;
wire[`RegAddrWidth-1:0] constant_31;
assign constant_31 = 31;
mux2x1 #(.data_width(`RegAddrWidth)) target_temp_mux(
.in_0(rt_EX),
.in_1(rd_EX),
.slct(RegDes_EX),
.out(target_temp)
);
mux2x1 #(.data_width(`RegAddrWidth)) target_mux(
.in_0(target_temp),
.in_1(constant_31),
.slct(is_jal_EX),
.out(target_EX)
);
wire[`RegDataWidth-1:0] temp_data_out_EX;
ALU arith_logic_unit(
.rst(rst),
.srcA(srcA),
.srcB(srcB),
.AluType(AluType_EX),
.AluOp(AluOp_EX),
.hi_in(hi_in),
.lo_in(lo_in),
.is_Overflow(is_Overflow),
.data_out(temp_data_out_EX),
.we_hi(we_hi),
.we_lo(we_lo),
.hi_out(hi_temp),
.lo_out(lo_temp)
);
mux2x1 #(.data_width(`RegDataWidth)) data_out_mix(
.in_0(temp_data_out_EX),
.in_1(pc_plus4_EX),
.slct(is_jal_EX),
.out(data_out_EX)
);
mux2x1 #(.data_width(`RegDataWidth)) hi_mux(
.in_0(hi),
.in_1(hi_temp),
.slct(we_hi),
.out(hi_EX)
);
mux2x1 #(.data_width(`RegDataWidth)) lo_mux(
.in_0(lo),
.in_1(lo_temp),
.slct(we_lo),
.out(lo_EX)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : ddr2_mig.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Top-level module. This module can be instantiated in the
// system and interconnect as shown in user design wrapper file (user top module).
// In addition to the memory controller, the module instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Debug logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module ddr2_mig #
(
parameter RST_ACT_LOW = 1,
// =1 for active low reset,
// =0 for active high.
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter CK_WIDTH = 1,
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1,
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1,
// # of CKE outputs to memory.
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DQ_CNT_WIDTH = 4,
// = ceil(log2(DQ_WIDTH))
parameter DQ_PER_DM = 8,
parameter DM_WIDTH = 2,
// # of DM (data mask)
parameter DQ_WIDTH = 16,
// # of DQ (data)
parameter DQS_WIDTH = 2,
parameter DQS_CNT_WIDTH = 1,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter ECC = "OFF",
parameter DATA_WIDTH = 16,
parameter ECC_TEST = "OFF",
parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
//Possible Parameters
//1.BANK_ROW_COLUMN : Address mapping is
// in form of Bank Row Column.
//2.ROW_BANK_COLUMN : Address mapping is
// in the form of Row Bank Column.
//3.TG_TEST : Scrambles Address bits
// for distributed Addressing.
//parameter nBANK_MACHS = 4,
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ODT_WIDTH = 1,
// # of ODT outputs to memory.
parameter ROW_WIDTH = 13,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 27,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
parameter USE_CS_PORT = 1,
// # = 1, When Chip Select (CS#) output is enabled
// = 0, When Chip Select (CS#) output is disabled
// If CS_N disabled, user must connect
// DRAM CS_N input(s) to ground
parameter USE_DM_PORT = 1,
// # = 1, When Data Mask option is enabled
// = 0, When Data Mask option is disbaled
// When Data Mask option is disabled in
// MIG Controller Options page, the logic
// related to Data Mask should not get
// synthesized
parameter USE_ODT_PORT = 1,
// # = 1, When ODT output is enabled
// = 0, When ODT output is disabled
parameter PHY_CONTROL_MASTER_BANK = 0,
// The bank index where master PHY_CONTROL resides,
// equal to the PLL residing bank
parameter MEM_DENSITY = "1Gb",
// Indicates the density of the Memory part
// Added for the sake of Vivado simulations
parameter MEM_SPEEDGRADE = "25E",
// Indicates the Speed grade of Memory Part
// Added for the sake of Vivado simulations
parameter MEM_DEVICE_WIDTH = 16,
// Indicates the device width of the Memory Part
// Added for the sake of Vivado simulations
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter AL = "0",
// DDR3 SDRAM:
// Additive Latency (Mode Register 1).
// # = "0", "CL-1", "CL-2".
// DDR2 SDRAM:
// Additive Latency (Extended Mode Register).
parameter nAL = 0,
// # Additive Latency in number of clock
// cycles.
parameter BURST_MODE = "8",
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
parameter BURST_TYPE = "SEQ",
// DDR3 SDRAM: Burst Type (Mode Register 0).
// DDR2 SDRAM: Burst Type (Mode Register).
// # = "SEQ" - (Sequential),
// = "INT" - (Interleaved).
parameter CL = 5,
// in number of clock cycles
// DDR3 SDRAM: CAS Latency (Mode Register 0).
// DDR2 SDRAM: CAS Latency (Mode Register).
parameter OUTPUT_DRV = "HIGH",
// Output Drive Strength (Extended Mode Register).
// # = "HIGH" - FULL,
// = "LOW" - REDUCED.
parameter RTT_NOM = "50",
// RTT (Nominal) (Extended Mode Register).
// = "150" - 150 Ohms,
// = "75" - 75 Ohms,
// = "50" - 50 Ohms.
parameter ADDR_CMD_MODE = "1T" ,
// # = "1T", "2T".
parameter REG_CTRL = "OFF",
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 3000,
// Input Clock Period
parameter CLKFBOUT_MULT = 4,
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
parameter CLKOUT0_PHASE = 0.0,
// Phase for PLL output clock (CLKOUT0)
parameter CLKOUT0_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT0)
parameter CLKOUT1_DIVIDE = 4,
// VCO output divisor for PLL output clock (CLKOUT1)
parameter CLKOUT2_DIVIDE = 64,
// VCO output divisor for PLL output clock (CLKOUT2)
parameter CLKOUT3_DIVIDE = 16,
// VCO output divisor for PLL output clock (CLKOUT3)
parameter MMCM_VCO = 1200,
// Max Freq (MHz) of MMCM VCO
parameter MMCM_MULT_F = 14,
// write MMCM VCO multiplier
parameter MMCM_DIVCLK_DIVIDE = 1,
// write MMCM VCO divisor
//***************************************************************************
// Memory Timing Parameters. These parameters varies based on the selected
// memory part.
//***************************************************************************
parameter tCKE = 7500,
// memory tCKE paramter in pS
parameter tFAW = 45000,
// memory tRAW paramter in pS.
parameter tPRDI = 1_000_000,
// memory tPRDI paramter in pS.
parameter tRAS = 40000,
// memory tRAS paramter in pS.
parameter tRCD = 15000,
// memory tRCD paramter in pS.
parameter tREFI = 7800000,
// memory tREFI paramter in pS.
parameter tRFC = 127500,
// memory tRFC paramter in pS.
parameter tRP = 12500,
// memory tRP paramter in pS.
parameter tRRD = 10000,
// memory tRRD paramter in pS.
parameter tRTP = 7500,
// memory tRTP paramter in pS.
parameter tWTR = 7500,
// memory tWTR paramter in pS.
parameter tZQI = 128_000_000,
// memory tZQI paramter in nS.
parameter tZQCS = 64,
// memory tZQCS paramter in clock cycles.
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "FAST",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
parameter SIMULATION = "TRUE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000,
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'b0101,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter PHY_0_BITLANES = 48'hFFC_3F7_FFF_3FE,
parameter PHY_1_BITLANES = 48'h000_000_000_000,
parameter PHY_2_BITLANES = 48'h000_000_000_000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_03,
parameter ADDR_MAP
= 192'h000_000_000_010_033_01A_019_032_03A_034_018_036_012_011_017_015,
parameter BANK_MAP = 36'h013_016_01B,
parameter CAS_MAP = 12'h039,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_038,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_035,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_037,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h014,
parameter WE_MAP = 12'h03B,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02_00,
parameter DATA0_MAP = 96'h008_004_009_007_005_001_006_003,
parameter DATA1_MAP = 96'h022_028_020_024_027_025_026_021,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_029_002,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter SLOT_0_CONFIG = 8'b0000_0001,
// Mapping of Ranks.
parameter SLOT_1_CONFIG = 8'b0000_0000,
// Mapping of Ranks.
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IBUF_LPWR_MODE = "OFF",
// to phy_top
parameter DATA_IO_IDLE_PWRDWN = "ON",
// # = "ON", "OFF"
parameter BANK_TYPE = "HR_IO",
// # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "HR_LP",
// # = "HP_LP", "HR_LP", "DEFAULT"
parameter CKE_ODT_AUX = "FALSE",
parameter USER_REFRESH = "OFF",
parameter WRLVL = "OFF",
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter ORDERING = "STRICT",
// # = "NORM", "STRICT", "RELAXED".
parameter CALIB_ROW_ADD = 16'h0000,
// Calibration row address will be used for
// calibration read and write operations
parameter CALIB_COL_ADD = 12'h000,
// Calibration column address will be used for
// calibration read and write operations
parameter CALIB_BA_ADD = 3'h0,
// Calibration bank address will be used for
// calibration read and write operations
parameter TCQ = 100,
parameter IODELAY_GRP0 = "DDR2_IODELAY_MIG0",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency (200MHz).
parameter SYSCLK_TYPE = "NO_BUFFER",
// System clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter REFCLK_TYPE = "NO_BUFFER",
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter CMD_PIPE_PLUS1 = "ON",
// add pipeline stage between MC and PHY
parameter DRAM_TYPE = "DDR2",
parameter CAL_WIDTH = "HALF",
parameter STARVE_LIMIT = 2,
// # = 2,3,4.
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0,
// IODELAYCTRL reference clock frequency
parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination for idelay
// reference clock input pins
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 3000,
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 4,
// # of memory CKs per fabric CLK
parameter DIFF_TERM_SYSCLK = "TRUE",
// Differential Termination for System
// clock input pins
//***************************************************************************
// Debug parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Temparature monitor parameter
//***************************************************************************
parameter TEMP_MON_CONTROL = "EXTERNAL"
// # = "INTERNAL", "EXTERNAL"
// parameter RST_ACT_LOW = 1
// =1 for active low reset,
// =0 for active high.
)
(
// Inouts
inout [DQ_WIDTH-1:0] ddr2_dq,
inout [DQS_WIDTH-1:0] ddr2_dqs_n,
inout [DQS_WIDTH-1:0] ddr2_dqs_p,
// Outputs
output [ROW_WIDTH-1:0] ddr2_addr,
output [BANK_WIDTH-1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [CK_WIDTH-1:0] ddr2_ck_p,
output [CK_WIDTH-1:0] ddr2_ck_n,
output [CKE_WIDTH-1:0] ddr2_cke,
output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n,
output [DM_WIDTH-1:0] ddr2_dm,
output [ODT_WIDTH-1:0] ddr2_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// Single-ended iodelayctrl clk (reference clock)
input clk_ref_i,
// user interface signals
input [ADDR_WIDTH-1:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [(nCK_PER_CLK*2*PAYLOAD_WIDTH)-1:0] app_wdf_data,
input app_wdf_end,
input [(nCK_PER_CLK*2*PAYLOAD_WIDTH/8)-1:0] app_wdf_mask,
input app_wdf_wren,
output [(nCK_PER_CLK*2*PAYLOAD_WIDTH)-1:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
input app_ref_req,
input app_zq_req,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
output ui_clk,
output ui_clk_sync_rst,
output init_calib_complete,
input [11:0] device_temp_i,
// The 12 MSB bits of the temperature sensor transfer
// function need to be connected to this port. This port
// will be synchronized w.r.t. to fabric clock internally.
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS);
localparam RANK_WIDTH = clogb2(RANKS);
localparam ECC_WIDTH = (ECC == "OFF")?
0 : (DATA_WIDTH <= 4)?
4 : (DATA_WIDTH <= 10)?
5 : (DATA_WIDTH <= 26)?
6 : (DATA_WIDTH <= 57)?
7 : (DATA_WIDTH <= 120)?
8 : (DATA_WIDTH <= 247)?
9 : 10;
localparam DATA_BUF_OFFSET_WIDTH = 1;
localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)
+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH
+ DATA_BUF_OFFSET_WIDTH;
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
localparam TEMP_MON_EN = (SIMULATION == "TRUE") ? "ON" : "OFF";
// Enable or disable the temp monitor module
localparam tTEMPSAMPLE = 10000000; // sample every 10 us
localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock
localparam TAPSPERKCLK = 56;
// Wire declarations
wire [BM_CNT_WIDTH-1:0] bank_mach_next;
wire clk;
wire [1:0] clk_ref;
wire [1:0] iodelay_ctrl_rdy;
wire clk_ref_in;
wire sys_rst_o;
wire clk_div2;
wire rst_div2;
wire freq_refclk ;
wire mem_refclk ;
wire pll_lock ;
wire sync_pulse;
wire mmcm_ps_clk;
wire poc_sample_pd;
wire psen;
wire psincdec;
wire psdone;
wire iddr_rst;
wire ref_dll_lock;
wire rst_phaser_ref;
wire pll_locked;
wire rst;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err;
wire ddr2_reset_n;
wire ddr2_parity;
wire sys_clk_p;
wire sys_clk_n;
wire mmcm_clk;
wire clk_ref_p;
wire clk_ref_n;
wire [11:0] device_temp;
// Debug port signals
wire dbg_idel_down_all;
wire dbg_idel_down_cpt;
wire dbg_idel_up_all;
wire dbg_idel_up_cpt;
wire dbg_sel_all_idel_cpt;
wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt;
wire dbg_sel_pi_incdec;
wire [DQS_CNT_WIDTH:0] dbg_byte_sel;
wire dbg_pi_f_inc;
wire dbg_pi_f_dec;
wire [5:0] dbg_pi_counter_read_val;
wire [8:0] dbg_po_counter_read_val;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt;
wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt;
wire [255:0] dbg_calib_top;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt;
wire [(6*RANKS)-1:0] dbg_rd_data_offset;
wire [255:0] dbg_phy_rdlvl;
wire [99:0] dbg_phy_wrcal;
wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt;
wire [255:0] dbg_phy_wrlvl;
wire [255:0] dbg_phy_init;
wire [255:0] dbg_prbs_rdlvl;
wire [255:0] dbg_dqs_found_cal;
wire dbg_pi_phaselock_start;
wire dbg_pi_phaselocked_done;
wire dbg_pi_phaselock_err;
wire dbg_pi_dqsfound_start;
wire dbg_pi_dqsfound_done;
wire dbg_pi_dqsfound_err;
wire dbg_wrcal_start;
wire dbg_wrcal_done;
wire dbg_wrcal_err;
wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes;
wire [11:0] dbg_pi_phase_locked_phy4lanes;
wire dbg_oclkdelay_calib_start;
wire dbg_oclkdelay_calib_done;
wire [255:0] dbg_phy_oclkdelay_cal;
wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data;
wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect;
wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata;
wire dbg_rddata_valid;
wire [1:0] dbg_rdlvl_done;
wire [1:0] dbg_rdlvl_err;
wire [1:0] dbg_rdlvl_start;
wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt;
wire [5:0] dbg_tap_cnt_during_wrlvl;
wire dbg_wl_edge_detect_valid;
wire dbg_wrlvl_done;
wire dbg_wrlvl_err;
wire dbg_wrlvl_start;
reg [63:0] dbg_rddata_r;
reg dbg_rddata_valid_r;
wire [53:0] ocal_tap_cnt;
wire [4:0] dbg_dqs;
wire [8:0] dbg_bit;
wire [8:0] rd_data_edge_detect_r;
wire [53:0] wl_po_fine_cnt;
wire [26:0] wl_po_coarse_cnt;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2;
wire [5:0] dbg_data_offset;
wire [5:0] dbg_data_offset_1;
wire [5:0] dbg_data_offset_2;
wire [390:0] ddr2_ila_wrpath_int;
wire [1023:0] ddr2_ila_rdpath_int;
wire [119:0] ddr2_ila_basic_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int;
//***************************************************************************
assign ui_clk = clk;
assign ui_clk_sync_rst = rst;
assign sys_clk_p = 1'b0;
assign sys_clk_n = 1'b0;
assign clk_ref_p = 1'b0;
assign clk_ref_n = 1'b0;
generate
if (REFCLK_TYPE == "USE_SYSTEM_CLOCK")
assign clk_ref_in = mmcm_clk;
else
assign clk_ref_in = clk_ref_i;
endgenerate
mig_7series_v4_0_iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP0 (IODELAY_GRP0),
.REFCLK_TYPE (REFCLK_TYPE),
.SYSCLK_TYPE (SYSCLK_TYPE),
.SYS_RST_PORT (SYS_RST_PORT),
.RST_ACT_LOW (RST_ACT_LOW),
.DIFF_TERM_REFCLK (DIFF_TERM_REFCLK)
)
u_iodelay_ctrl
(
// Outputs
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.sys_rst_o (sys_rst_o),
.clk_ref (clk_ref),
// Inputs
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.clk_ref_i (clk_ref_in),
.sys_rst (sys_rst)
);
mig_7series_v4_0_clk_ibuf #
(
.SYSCLK_TYPE (SYSCLK_TYPE),
.DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK)
)
u_ddr2_clk_ibuf
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk_i (sys_clk_i),
.mmcm_clk (mmcm_clk)
);
// Temperature monitoring logic
generate
if (TEMP_MON_EN == "ON") begin: temp_mon_enabled
mig_7series_v4_0_tempmon #
(
.TCQ (TCQ),
.TEMP_MON_CONTROL (TEMP_MON_CONTROL),
.XADC_CLK_PERIOD (XADC_CLK_PERIOD),
.tTEMPSAMPLE (tTEMPSAMPLE)
)
u_tempmon
(
.clk (clk),
.xadc_clk (clk_ref[0]),
.rst (rst),
.device_temp_i (device_temp_i),
.device_temp (device_temp)
);
end else begin: temp_mon_disabled
assign device_temp = 'b0;
end
endgenerate
mig_7series_v4_0_infrastructure #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLKIN_PERIOD (CLKIN_PERIOD),
.SYSCLK_TYPE (SYSCLK_TYPE),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.MMCM_VCO (MMCM_VCO),
.MMCM_MULT_F (MMCM_MULT_F),
.MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),
.RST_ACT_LOW (RST_ACT_LOW),
.tCK (tCK),
.MEM_TYPE (DRAM_TYPE)
)
u_ddr2_infrastructure
(
// Outputs
.rstdiv0 (rst),
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.mem_refclk (mem_refclk),
.freq_refclk (freq_refclk),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
// .auxout_clk (),
.ui_addn_clk_0 (),
.ui_addn_clk_1 (),
.ui_addn_clk_2 (),
.ui_addn_clk_3 (),
.ui_addn_clk_4 (),
.pll_locked (pll_locked),
.mmcm_locked (),
.rst_phaser_ref (rst_phaser_ref),
// Inputs
.psen (psen),
.psincdec (psincdec),
.mmcm_clk (mmcm_clk),
.sys_rst (sys_rst_o),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.ref_dll_lock (ref_dll_lock)
);
mig_7series_v4_0_memc_ui_top_std #
(
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.ECC_TEST (ECC_TEST),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.IODELAY_GRP0 (IODELAY_GRP0),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.CL (CL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.IDELAY_ADJ ("OFF"),
.FINE_PER_BIT ("OFF"),
.CENTER_COMP_MODE ("OFF"),
.PI_VAL_ADJ ("OFF"),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK),
.TAPSPERKCLK (TAPSPERKCLK),
.SKIP_CALIB ("FALSE"),
.FPGA_VOLT_TYPE ("N")
)
u_memc_ui_top_std
(
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_locked),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
.psen (psen),
.psincdec (psincdec),
.rst (rst),
.rst_phaser_ref (rst_phaser_ref),
.ref_dll_lock (ref_dll_lock),
// Memory interface ports
.ddr_dq (ddr2_dq),
.ddr_dqs_n (ddr2_dqs_n),
.ddr_dqs (ddr2_dqs_p),
.ddr_addr (ddr2_addr),
.ddr_ba (ddr2_ba),
.ddr_cas_n (ddr2_cas_n),
.ddr_ck_n (ddr2_ck_n),
.ddr_ck (ddr2_ck_p),
.ddr_cke (ddr2_cke),
.ddr_cs_n (ddr2_cs_n),
.ddr_dm (ddr2_dm),
.ddr_odt (ddr2_odt),
.ddr_ras_n (ddr2_ras_n),
.ddr_reset_n (ddr2_reset_n),
.ddr_parity (ddr2_parity),
.ddr_we_n (ddr2_we_n),
.bank_mach_next (bank_mach_next),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_hi_pri (1'b0),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_mask (app_wdf_mask),
.app_wdf_wren (app_wdf_wren),
.app_ecc_multiple_err (app_ecc_multiple_err),
.app_ecc_single_err (app_ecc_single_err),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.app_raw_not_ecc ({2*nCK_PER_CLK{1'b0}}),
.app_correct_en_i (1'b1),
.device_temp (device_temp),
.calib_tap_req (),
.calib_tap_load (1'b0),
.calib_tap_addr (7'b0),
.calib_tap_val (8'b0),
.calib_tap_load_done (1'b0),
// Debug logic ports
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.init_calib_complete (init_calib_complete),
.dbg_poc (dbg_poc)
);
//*********************************************************************
// Resetting all RTL debug inputs as the debug ports are not enabled
//*********************************************************************
assign dbg_idel_down_all = 1'b0;
assign dbg_idel_down_cpt = 1'b0;
assign dbg_idel_up_all = 1'b0;
assign dbg_idel_up_cpt = 1'b0;
assign dbg_sel_all_idel_cpt = 1'b0;
assign dbg_sel_idel_cpt = 'b0;
assign dbg_byte_sel = 'd0;
assign dbg_sel_pi_incdec = 1'b0;
assign dbg_pi_f_inc = 1'b0;
assign dbg_pi_f_dec = 1'b0;
assign dbg_po_f_inc = 'b0;
assign dbg_po_f_dec = 'b0;
assign dbg_po_f_stg23_sel = 'b0;
assign dbg_sel_po_incdec = 'b0;
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: DES Sbox 4
-- Description: Sbox 4 del algoritmo DES
-- Dependencies: -- none
-- Parameters: -- none
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 05 de Junio 2015
*/
module des_sbox4
(
// -- inputs --------------------------------------------------------- >>>>>
input wire [0:5] right_xor_key_segment_din,
// -- outputs -------------------------------------------------------- >>>>>
output reg [0:3] sbox_dout
);
always @(*)
case ({right_xor_key_segment_din[0], right_xor_key_segment_din[5]})
2'b00:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd7;
4'd1: sbox_dout = 4'd13;
4'd2: sbox_dout = 4'd14;
4'd3: sbox_dout = 4'd3;
4'd4: sbox_dout = 4'd0;
4'd5: sbox_dout = 4'd6;
4'd6: sbox_dout = 4'd9;
4'd7: sbox_dout = 4'd10;
4'd8: sbox_dout = 4'd1;
4'd9: sbox_dout = 4'd2;
4'd10: sbox_dout = 4'd8;
4'd11: sbox_dout = 4'd5;
4'd12: sbox_dout = 4'd11;
4'd13: sbox_dout = 4'd12;
4'd14: sbox_dout = 4'd4;
4'd15: sbox_dout = 4'd15;
endcase
2'b01:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd13;
4'd1: sbox_dout = 4'd8;
4'd2: sbox_dout = 4'd11;
4'd3: sbox_dout = 4'd5;
4'd4: sbox_dout = 4'd6;
4'd5: sbox_dout = 4'd15;
4'd6: sbox_dout = 4'd0;
4'd7: sbox_dout = 4'd3;
4'd8: sbox_dout = 4'd4;
4'd9: sbox_dout = 4'd7;
4'd10: sbox_dout = 4'd2;
4'd11: sbox_dout = 4'd12;
4'd12: sbox_dout = 4'd1;
4'd13: sbox_dout = 4'd10;
4'd14: sbox_dout = 4'd14;
4'd15: sbox_dout = 4'd9;
endcase
2'b10:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd10;
4'd1: sbox_dout = 4'd6;
4'd2: sbox_dout = 4'd9;
4'd3: sbox_dout = 4'd0;
4'd4: sbox_dout = 4'd12;
4'd5: sbox_dout = 4'd11;
4'd6: sbox_dout = 4'd7;
4'd7: sbox_dout = 4'd13;
4'd8: sbox_dout = 4'd15;
4'd9: sbox_dout = 4'd1;
4'd10: sbox_dout = 4'd3;
4'd11: sbox_dout = 4'd14;
4'd12: sbox_dout = 4'd5;
4'd13: sbox_dout = 4'd2;
4'd14: sbox_dout = 4'd8;
4'd15: sbox_dout = 4'd4;
endcase
2'b11:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd3;
4'd1: sbox_dout = 4'd15;
4'd2: sbox_dout = 4'd0;
4'd3: sbox_dout = 4'd6;
4'd4: sbox_dout = 4'd10;
4'd5: sbox_dout = 4'd1;
4'd6: sbox_dout = 4'd13;
4'd7: sbox_dout = 4'd8;
4'd8: sbox_dout = 4'd9;
4'd9: sbox_dout = 4'd4;
4'd10: sbox_dout = 4'd5;
4'd11: sbox_dout = 4'd11;
4'd12: sbox_dout = 4'd12;
4'd13: sbox_dout = 4'd7;
4'd14: sbox_dout = 4'd2;
4'd15: sbox_dout = 4'd14;
endcase
endcase // right_xor_key_segment_din[0], right_xor_key_segment_din[5]
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
des_sbox4 sbox4
(
// -- inputs ------------------------------------------------- >>>>>
.right_xor_key_segment_din (right_xor_key_segment),
// -- outputs ------------------------------------------------ >>>>>
sbox_dout (sbox_dout)
);
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31OI_4_V
`define SKY130_FD_SC_HDLL__A31OI_4_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a31oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a31oi_4 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31OI_4_V
|
`include "parameters_rs232.v"
module sim_rs232;
// Inputs
reg reset_n;
reg clk;
reg [7:0] tx_data;
reg tx_start;
reg cts;
reg rxd;
reg rx_ack;
// Outputs
wire tx_ready;
wire txd;
wire rts;
wire [7:0] rx_data;
wire rx_ready;
wire [`rs232_state_tx_width-1:0] rs232_state_tx;
wire [`rs232_state_rx_width-1:0] rs232_state_rx;
// Instantiate the Unit Under Test (UUT)
rs232 uut (
.reset_n(reset_n),
.clk(clk),
.tx_ready(tx_ready),
.tx_data(tx_data),
.tx_start(tx_start),
.cts(cts),
.txd(txd),
.rts(rts),
.rxd(rxd),
.rx_data(rx_data),
.rx_ready(rx_ready),
.rx_ack(rx_ack),
.rs232_state_tx(rs232_state_tx),
.rs232_state_rx(rs232_state_rx)
);
`include "rs232_states.v"
// TRANSMITTER
task start_tx;
begin
@(posedge clk);
$display("time: %d : start timer", $time);
if (tx_ready)
tx_start = 1;
#30
tx_start = 0;
end
endtask
// RECEIVER
task start_rx;
begin
@(posedge clk) begin
case (rs232_state_rx)
RS232_STATE_RX_RTS:
begin
rxd <= #`DEL 0;
$display("time: %d : start rx ", $time);
end
//RS232_STATE_RX_STOPa:
default:
begin
rxd <= #`DEL 1;
$display("time: %d : stop rx ", $time);
end
// default:
endcase
//$finish;
end
end
endtask
initial begin
// Initialize Inputs
reset_n = 0;
clk = 0;
tx_data = 0;
tx_start = 0;
cts = 0;
rxd = 1;
rx_ack = 0;
// Wait 100 ns for global reset to finish
#100;
reset_n = 1;
#100;
// Add stimulus here
// TRANSMITTER
cts = 1; // host requests data
#100;
tx_data = `data_width'h15;
#100;
start_tx;
#200;
// start_rx;
$display("time: %d : end ", $time);
end
always @(posedge clk) begin
case (rs232_state_rx)
RS232_STATE_RX_RTS:
begin
rxd <= #`DEL 0;
$display("time: %d : start rx ", $time);
#700
rxd <= #`DEL 1;
#500
rxd <= #`DEL 0;
end
RS232_STATE_RX_STOPa:
begin
rxd <= #`DEL 1;
$display("time: %d : stop rx ", $time);
end
RS232_STATE_RX_STOPb:
begin
if (rx_ready)
begin
rx_ack <= #`DEL 1;
$display("time: %d : ack rx ", $time);
end
end
RS232_STATE_RX_IDLE:
begin
rx_ack <= #`DEL 0;
//$display("time: %d : ack rx ", $time);
end
// default:
endcase
end
always #10 clk = ~clk; // 50Mhz main clock // period 20ns
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:33:17 05/25/2015
// Design Name: OneShot
// Module Name: C:/Users/dagosttv.ROSE-HULMAN/Documents/School/ECE/ECE398/CAN-Bus-Controller-/One-ShotTest.v
// Project Name: CAN_Controller
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: OneShot
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module OneShotTest;
// Inputs
reg pulse;
reg clk;
reg rst;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
OneShot uut (
.pulse(pulse),
.clk(clk),
.rst(rst),
.out(out)
);
initial begin
// Initialize Inputs
pulse = 0;
clk = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
#10;
pulse = 1;
#100; $stop;
// Add stimulus here
end
always #1.25 clk=~clk;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_PP_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_BEHAVIORAL_PP_V
|
module Control(
input [5:0] opcode,
input clk,
output reg reg_dst,
output reg jump,
output reg branch,
output reg ctrl_mem_read,
output reg mem_to_reg,
output reg ctrl_mem_write,
output reg alu_src,
output reg reg_write,
output reg [1:0] alu_op
);
// Control signals from FIgure 4.18, 4.22, & Ref Sheet
always@(posedge clk)
begin
// Initalize signals to 0 to reduce redundancy in if statements
{reg_dst, alu_src, mem_to_reg, reg_write, ctrl_mem_read, ctrl_mem_write, branch, jump, alu_op} = 10'b0000000000;
// R-type
if (opcode == 6'b000000) begin
reg_dst <= 1;
reg_write <= 1;
alu_op <= 2'b10;
end
// Load word
else if (opcode == 6'b100011) begin
alu_src <= 1;
mem_to_reg <= 1;
reg_write <= 1;
ctrl_mem_read <= 1;
end
// Store word
else if (opcode == 6'b101011) begin
alu_src <= 1;
ctrl_mem_write <= 1;
end
// Branch equal
else if (opcode == 6'b000100) begin
branch <= 1;
alu_op <= 2'b01;
end
// Addi
if (opcode == 6'b001000) begin
alu_src <= 1;
reg_write <= 1;
// alu_op <= 2'b10;
end
// Jump
else if (opcode == 6'b000010) begin
jump <= 1;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PIO_EP.v
// Version : 1.11
//
// Description: Endpoint Programmed I/O module.
// Consists of Receive and Transmit modules and a Memory Aperture
//
//------------------------------------------------------------------------------
`timescale 1ps/1ps
module PIO_EP #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width
parameter TCQ = 1
) (
input clk,
input rst_n,
// AXIS TX
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_src_dsc,
//AXIS RX
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
output req_compl,
output compl_done,
input [15:0] cfg_completer_id
);
// Local wires
wire [10:0] rd_addr;
wire [3:0] rd_be;
wire [31:0] rd_data;
wire [10:0] wr_addr;
wire [7:0] wr_be;
wire [31:0] wr_data;
wire wr_en;
wire wr_busy;
wire req_compl_int;
wire req_compl_wd;
wire compl_done_int;
wire [2:0] req_tc;
wire req_td;
wire req_ep;
wire [1:0] req_attr;
wire [9:0] req_len;
wire [15:0] req_rid;
wire [7:0] req_tag;
wire [7:0] req_be;
wire [12:0] req_addr;
//
// ENDPOINT MEMORY : 8KB memory aperture implemented in FPGA BlockRAM(*)
//
PIO_EP_MEM_ACCESS #(
.TCQ( TCQ )
) EP_MEM_inst (
.clk(clk), // I
.rst_n(rst_n), // I
// Read Port
.rd_addr(rd_addr), // I [10:0]
.rd_be(rd_be), // I [3:0]
.rd_data(rd_data), // O [31:0]
// Write Port
.wr_addr(wr_addr), // I [10:0]
.wr_be(wr_be), // I [7:0]
.wr_data(wr_data), // I [31:0]
.wr_en(wr_en), // I
.wr_busy(wr_busy) // O
);
//
// Local-Link Receive Controller
//
PIO_RX_ENGINE #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH ),
.TCQ( TCQ )
) EP_RX_inst (
.clk(clk), // I
.rst_n(rst_n), // I
// AXIS RX
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tkeep( m_axis_rx_tkeep ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
// Handshake with Tx engine
.req_compl(req_compl_int), // O
.req_compl_wd(req_compl_wd), // O
.compl_done(compl_done_int), // I
.req_tc(req_tc), // O [2:0]
.req_td(req_td), // O
.req_ep(req_ep), // O
.req_attr(req_attr), // O [1:0]
.req_len(req_len), // O [9:0]
.req_rid(req_rid), // O [15:0]
.req_tag(req_tag), // O [7:0]
.req_be(req_be), // O [7:0]
.req_addr(req_addr), // O [12:0]
// Memory Write Port
.wr_addr(wr_addr), // O [10:0]
.wr_be(wr_be), // O [7:0]
.wr_data(wr_data), // O [31:0]
.wr_en(wr_en), // O
.wr_busy(wr_busy) // I
);
//
// Local-Link Transmit Controller
//
PIO_TX_ENGINE #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH ),
.TCQ( TCQ )
)EP_TX_inst(
.clk(clk), // I
.rst_n(rst_n), // I
// AXIS Tx
.s_axis_tx_tready( s_axis_tx_tready ), // I
.s_axis_tx_tdata( s_axis_tx_tdata ), // O
.s_axis_tx_tkeep( s_axis_tx_tkeep ), // O
.s_axis_tx_tlast( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid( s_axis_tx_tvalid ), // O
.tx_src_dsc( tx_src_dsc ), // O
// Handshake with Rx engine
.req_compl(req_compl_int), // I
.req_compl_wd(req_compl_wd), // I
.compl_done(compl_done_int), // 0
.req_tc(req_tc), // I [2:0]
.req_td(req_td), // I
.req_ep(req_ep), // I
.req_attr(req_attr), // I [1:0]
.req_len(req_len), // I [9:0]
.req_rid(req_rid), // I [15:0]
.req_tag(req_tag), // I [7:0]
.req_be(req_be), // I [7:0]
.req_addr(req_addr), // I [12:0]
// Read Port
.rd_addr(rd_addr), // O [10:0]
.rd_be(rd_be), // O [3:0]
.rd_data(rd_data), // I [31:0]
.completer_id(cfg_completer_id) // I [15:0]
);
assign req_compl = req_compl_int;
assign compl_done = compl_done_int;
endmodule // PIO_EP
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2019 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2019.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / RAM32X16DR8
// /___/ /\ Filename : RAM32X16DR8.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAM32X16DR8 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output DOA,
output DOB,
output DOC,
output DOD,
output DOE,
output DOF,
output DOG,
output [1:0] DOH,
input [5:0] ADDRA,
input [5:0] ADDRB,
input [5:0] ADDRC,
input [5:0] ADDRD,
input [5:0] ADDRE,
input [5:0] ADDRF,
input [5:0] ADDRG,
input [4:0] ADDRH,
input [1:0] DIA,
input [1:0] DIB,
input [1:0] DIC,
input [1:0] DID,
input [1:0] DIE,
input [1:0] DIF,
input [1:0] DIG,
input [1:0] DIH,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM32X16DR8";
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "RAM32X16DR8_dr.v"
`else
reg [0:0] IS_WCLK_INVERTED_REG = IS_WCLK_INVERTED;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
wire WCLK_in;
wire WE_in;
wire [1:0] DIA_in;
wire [1:0] DIB_in;
wire [1:0] DIC_in;
wire [1:0] DID_in;
wire [1:0] DIE_in;
wire [1:0] DIF_in;
wire [1:0] DIG_in;
wire [1:0] DIH_in;
wire [4:0] ADDRH_in;
wire [5:0] ADDRA_in;
wire [5:0] ADDRB_in;
wire [5:0] ADDRC_in;
wire [5:0] ADDRD_in;
wire [5:0] ADDRE_in;
wire [5:0] ADDRF_in;
wire [5:0] ADDRG_in;
`ifdef XIL_TIMING
wire [4:0] ADDRH_dly;
wire [1:0] DIA_dly;
wire [1:0] DIB_dly;
wire [1:0] DIC_dly;
wire [1:0] DID_dly;
wire [1:0] DIE_dly;
wire [1:0] DIF_dly;
wire [1:0] DIG_dly;
wire [1:0] DIH_dly;
wire WCLK_dly;
wire WE_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign ADDRA_in = ADDRA;
assign ADDRB_in = ADDRB;
assign ADDRC_in = ADDRC;
assign ADDRD_in = ADDRD;
assign ADDRE_in = ADDRE;
assign ADDRF_in = ADDRF;
assign ADDRG_in = ADDRG;
assign ADDRH_in = ADDRH_dly;
assign DIA_in = DIA_dly;
assign DIB_in = DIB_dly;
assign DIC_in = DIC_dly;
assign DID_in = DID_dly;
assign DIE_in = DIE_dly;
assign DIF_in = DIF_dly;
assign DIG_in = DIG_dly;
assign DIH_in = DIH_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_REG;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
`else
assign ADDRA_in = ADDRA;
assign ADDRB_in = ADDRB;
assign ADDRC_in = ADDRC;
assign ADDRD_in = ADDRD;
assign ADDRE_in = ADDRE;
assign ADDRF_in = ADDRF;
assign ADDRG_in = ADDRG;
assign ADDRH_in = ADDRH;
assign DIA_in = DIA;
assign DIB_in = DIB;
assign DIC_in = DIC;
assign DID_in = DID;
assign DIE_in = DIE;
assign DIF_in = DIF;
assign DIG_in = DIG;
assign DIH_in = DIH;
assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_REG;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
`ifndef XIL_XECLIB
initial begin
trig_attr = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
// begin behavioral model
reg [63:0] mem_a, mem_b, mem_c, mem_d;
reg [63:0] mem_e, mem_f, mem_g, mem_h;
reg [5:0] addr_in1, addr_in2;
always @(ADDRH_in) begin
addr_in1 = 2 * ADDRH_in;
addr_in2 = 2 * ADDRH_in + 1;
end
always @(posedge WCLK_in)
if (WE_in) begin
mem_a[addr_in1] <= #100 DIA_in[0];
mem_a[addr_in2] <= #100 DIA_in[1];
mem_b[addr_in1] <= #100 DIB_in[0];
mem_b[addr_in2] <= #100 DIB_in[1];
mem_c[addr_in1] <= #100 DIC_in[0];
mem_c[addr_in2] <= #100 DIC_in[1];
mem_d[addr_in1] <= #100 DID_in[0];
mem_d[addr_in2] <= #100 DID_in[1];
mem_e[addr_in1] <= #100 DIE_in[0];
mem_e[addr_in2] <= #100 DIE_in[1];
mem_f[addr_in1] <= #100 DIF_in[0];
mem_f[addr_in2] <= #100 DIF_in[1];
mem_g[addr_in1] <= #100 DIG_in[0];
mem_g[addr_in2] <= #100 DIG_in[1];
mem_h[addr_in1] <= #100 DIH_in[0];
mem_h[addr_in2] <= #100 DIH_in[1];
end
assign DOA = mem_a[ADDRA_in];
assign DOB = mem_b[ADDRB_in];
assign DOC = mem_c[ADDRC_in];
assign DOD = mem_d[ADDRD_in];
assign DOE = mem_e[ADDRE_in];
assign DOF = mem_f[ADDRF_in];
assign DOG = mem_g[ADDRG_in];
assign DOH[0] = mem_h[2*ADDRH_in];
assign DOH[1] = mem_h[2*ADDRH_in + 1];
// end behavioral model
`ifdef XIL_TIMING
always @(notifier) begin
mem_a[addr_in1] <= 1'bx;
mem_a[addr_in2] <= 1'bx;
mem_b[addr_in1] <= 1'bx;
mem_b[addr_in2] <= 1'bx;
mem_c[addr_in1] <= 1'bx;
mem_c[addr_in2] <= 1'bx;
mem_d[addr_in1] <= 1'bx;
mem_d[addr_in2] <= 1'bx;
mem_e[addr_in1] <= 1'bx;
mem_e[addr_in2] <= 1'bx;
mem_f[addr_in1] <= 1'bx;
mem_f[addr_in2] <= 1'bx;
mem_g[addr_in1] <= 1'bx;
mem_g[addr_in2] <= 1'bx;
mem_h[addr_in1] <= 1'bx;
mem_h[addr_in2] <= 1'bx;
end
assign sh_clk_en_p = ~IS_WCLK_INVERTED_REG;
assign sh_clk_en_n = IS_WCLK_INVERTED_REG;
assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_REG;
assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_REG;
specify
(WCLK => DOA) = (0:0:0, 0:0:0);
(WCLK => DOB) = (0:0:0, 0:0:0);
(WCLK => DOC) = (0:0:0, 0:0:0);
(WCLK => DOD) = (0:0:0, 0:0:0);
(WCLK => DOE) = (0:0:0, 0:0:0);
(WCLK => DOF) = (0:0:0, 0:0:0);
(WCLK => DOG) = (0:0:0, 0:0:0);
(WCLK => DOH[0]) = (0:0:0, 0:0:0);
(WCLK => DOH[1]) = (0:0:0, 0:0:0);
(ADDRA *> DOA) = (0:0:0, 0:0:0);
(ADDRB *> DOB) = (0:0:0, 0:0:0);
(ADDRC *> DOC) = (0:0:0, 0:0:0);
(ADDRD *> DOD) = (0:0:0, 0:0:0);
(ADDRE *> DOE) = (0:0:0, 0:0:0);
(ADDRF *> DOF) = (0:0:0, 0:0:0);
(ADDRG *> DOG) = (0:0:0, 0:0:0);
(ADDRH *> DOH[0]) = (0:0:0, 0:0:0);
(ADDRH *> DOH[1]) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[0]);
$setuphold (negedge WCLK, negedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[1]);
$setuphold (negedge WCLK, negedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[2]);
$setuphold (negedge WCLK, negedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[3]);
$setuphold (negedge WCLK, negedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[4]);
$setuphold (negedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]);
$setuphold (negedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]);
$setuphold (negedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]);
$setuphold (negedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]);
$setuphold (negedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]);
$setuphold (negedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]);
$setuphold (negedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]);
$setuphold (negedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]);
$setuphold (negedge WCLK, negedge DIE[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly[0]);
$setuphold (negedge WCLK, negedge DIE[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly[1]);
$setuphold (negedge WCLK, negedge DIF[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly[0]);
$setuphold (negedge WCLK, negedge DIF[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly[1]);
$setuphold (negedge WCLK, negedge DIG[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly[0]);
$setuphold (negedge WCLK, negedge DIG[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly[1]);
$setuphold (negedge WCLK, negedge DIH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly[0]);
$setuphold (negedge WCLK, negedge DIH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly[1]);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[0]);
$setuphold (negedge WCLK, posedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[1]);
$setuphold (negedge WCLK, posedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[2]);
$setuphold (negedge WCLK, posedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[3]);
$setuphold (negedge WCLK, posedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[4]);
$setuphold (negedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]);
$setuphold (negedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]);
$setuphold (negedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]);
$setuphold (negedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]);
$setuphold (negedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]);
$setuphold (negedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]);
$setuphold (negedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]);
$setuphold (negedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]);
$setuphold (negedge WCLK, posedge DIE[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly[0]);
$setuphold (negedge WCLK, posedge DIE[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly[1]);
$setuphold (negedge WCLK, posedge DIF[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly[0]);
$setuphold (negedge WCLK, posedge DIF[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly[1]);
$setuphold (negedge WCLK, posedge DIG[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly[0]);
$setuphold (negedge WCLK, posedge DIG[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly[1]);
$setuphold (negedge WCLK, posedge DIH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly[0]);
$setuphold (negedge WCLK, posedge DIH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly[1]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[0]);
$setuphold (posedge WCLK, negedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[1]);
$setuphold (posedge WCLK, negedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[2]);
$setuphold (posedge WCLK, negedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[3]);
$setuphold (posedge WCLK, negedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[4]);
$setuphold (posedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]);
$setuphold (posedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]);
$setuphold (posedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]);
$setuphold (posedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]);
$setuphold (posedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]);
$setuphold (posedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]);
$setuphold (posedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]);
$setuphold (posedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]);
$setuphold (posedge WCLK, negedge DIE[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly[0]);
$setuphold (posedge WCLK, negedge DIE[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly[1]);
$setuphold (posedge WCLK, negedge DIF[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly[0]);
$setuphold (posedge WCLK, negedge DIF[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly[1]);
$setuphold (posedge WCLK, negedge DIG[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly[0]);
$setuphold (posedge WCLK, negedge DIG[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly[1]);
$setuphold (posedge WCLK, negedge DIH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly[0]);
$setuphold (posedge WCLK, negedge DIH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly[1]);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[0]);
$setuphold (posedge WCLK, posedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[1]);
$setuphold (posedge WCLK, posedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[2]);
$setuphold (posedge WCLK, posedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[3]);
$setuphold (posedge WCLK, posedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[4]);
$setuphold (posedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]);
$setuphold (posedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]);
$setuphold (posedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]);
$setuphold (posedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]);
$setuphold (posedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]);
$setuphold (posedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]);
$setuphold (posedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]);
$setuphold (posedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]);
$setuphold (posedge WCLK, posedge DIE[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly[0]);
$setuphold (posedge WCLK, posedge DIE[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly[1]);
$setuphold (posedge WCLK, posedge DIF[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly[0]);
$setuphold (posedge WCLK, posedge DIF[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly[1]);
$setuphold (posedge WCLK, posedge DIG[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly[0]);
$setuphold (posedge WCLK, posedge DIG[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly[1]);
$setuphold (posedge WCLK, posedge DIH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly[0]);
$setuphold (posedge WCLK, posedge DIH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly[1]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_rptr_vddcom.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_rptr_vddcom(vdd18,vdd_com);
input vdd18;
output vdd_com;
endmodule
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
`timescale 1ns/1ns
module RX_SPW (
input rx_din,
input rx_sin,
input rx_resetn,
output rx_error,
output reg rx_got_bit,
output rx_got_null,
output rx_got_nchar,
output rx_got_time_code,
output rx_got_fct,
output rx_got_fct_fsm,
output [8:0] rx_data_flag,
output rx_buffer_write,
output [7:0] rx_time_out,
output rx_tick_out
);
wire [5:0] counter_neg/* synthesis syn_replicate = 0 */;
wire posedge_clk;
wire negedge_clk;
wire bit_c_0;//N
wire bit_c_1;//P
wire bit_c_2;//N
wire bit_c_3;//P
wire bit_d_0;//N
wire bit_d_1;//P
wire bit_d_2;//N
wire bit_d_3;//P
wire bit_d_4;//N
wire bit_d_5;//P
wire bit_d_6;//N
wire bit_d_7;//P
wire bit_d_8;//N
wire bit_d_9;//P
wire [1:0] state_data_process;
wire is_control/* synthesis dont_replicate */;
wire last_is_control;
wire last_is_data;
wire last_is_timec;
wire [2:0] control_p_r/* synthesis dont_replicate */;
wire [7:0] timecode/* synthesis dont_replicate */;
wire [2:0] control_l_r/* synthesis dont_replicate */;
wire [8:0] dta_timec_p/* synthesis dont_replicate */;
reg ready_control;
reg ready_data;
wire ready_control_p_r;
wire ready_data_p_r;
wire parity_rec_c;
wire parity_rec_d;
wire parity_rec_c_gen;
wire parity_rec_d_gen;
wire rx_error_c;
wire rx_error_d;
wire posedge_p/* synthesis syn_replicate = 0 */;
reg f_time;
//CLOCK RECOVERY
assign posedge_clk = posedge_p;
assign negedge_clk = (f_time)?!posedge_p:1'b0;
assign rx_time_out = timecode;
buf (posedge_p,rx_din ^ rx_sin);
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
f_time <= 1'b0;
end
else
begin
f_time <= 1'b1;
end
end
always@(*)
begin
rx_got_bit = 1'b0;
if(rx_din | rx_sin)
begin
rx_got_bit = 1'b1;
end
end
always@(*)
begin
ready_control = 1'b0;
ready_data = 1'b0;
if(is_control && counter_neg == 6'd4 && !posedge_p)
begin
ready_control = 1'b1;
ready_data = 1'b0;
end
else if(!is_control && counter_neg == 6'd32 && !posedge_p)
begin
ready_control = 1'b0;
ready_data = 1'b1;
end
end
rx_buffer_fsm buffer_fsm(
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.last_is_data(last_is_data),
.last_is_timec(last_is_timec),
.last_is_control(last_is_control),
.rx_got_null(rx_got_null),
.rx_got_nchar(rx_got_nchar),
.rx_got_time_code(rx_got_time_code)
);
rx_data_buffer_data_w buffer_data_flag(
.negedge_clk(negedge_clk),
.rx_resetn(rx_resetn),
.state_data_process(state_data_process),
.control(control_p_r),
.last_is_timec(last_is_timec),
.last_is_data(last_is_data),
.last_is_control(last_is_control),
.rx_buffer_write(rx_buffer_write),
.rx_tick_out(rx_tick_out)
);
rx_control_data_rdy control_data_rdy(
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.rx_error_c(rx_error_c),
.rx_error_d(rx_error_d),
.control(control_p_r),
.control_l_r(control_l_r[2:0]),
.is_control(is_control),
.counter_neg(counter_neg),
.last_is_control(last_is_control),
.rx_error(rx_error),
.ready_control_p_r(ready_control_p_r),
.ready_data_p_r(ready_data_p_r),
.rx_got_fct_fsm(rx_got_fct_fsm)
);
rx_data_control_p data_control(
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.bit_c_3(bit_c_3),
.bit_c_2(bit_c_2),
.bit_c_1(bit_c_1),
.bit_c_0(bit_c_0),
.bit_d_9(bit_d_9),
.bit_d_8(bit_d_8),
.bit_d_0(bit_d_0),
.bit_d_1(bit_d_1),
.bit_d_2(bit_d_2),
.bit_d_3(bit_d_3),
.bit_d_4(bit_d_4),
.bit_d_5(bit_d_5),
.bit_d_6(bit_d_6),
.bit_d_7(bit_d_7),
.last_is_control(last_is_control),
.last_is_data(last_is_data),
.is_control(is_control),
.counter_neg(counter_neg),
.dta_timec_p(dta_timec_p),
.parity_rec_d(parity_rec_d),
.parity_rec_d_gen(parity_rec_d_gen),
.control_p_r(control_p_r),
.control_l_r(control_l_r),
.parity_rec_c(parity_rec_c),
.parity_rec_c_gen(parity_rec_c_gen)
);
bit_capture_data capture_d(
.negedge_clk(negedge_clk),
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.bit_d_0(bit_d_0),//N
.bit_d_1(bit_d_1),//P
.bit_d_2(bit_d_2),//N
.bit_d_3(bit_d_3),//P
.bit_d_4(bit_d_4),//N
.bit_d_5(bit_d_5),//P
.bit_d_6(bit_d_6),//N
.bit_d_7(bit_d_7),//P
.bit_d_8(bit_d_8),//N
.bit_d_9(bit_d_9)//P
);
bit_capture_control capture_c(
.negedge_clk(negedge_clk),
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.bit_c_0(bit_c_0),
.bit_c_1(bit_c_1),
.bit_c_2(bit_c_2),
.bit_c_3(bit_c_3)
);
counter_neg cnt_neg(
.negedge_clk(negedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.is_control(is_control),
.counter_neg(counter_neg)
);
rx_data_receive rx_dtarcv (
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.ready_control_p_r(ready_control_p_r),
.ready_data_p_r(ready_data_p_r),
.ready_control(ready_control),
.ready_data(ready_data),
.parity_rec_c(parity_rec_c),
.parity_rec_d(parity_rec_d),
.parity_rec_c_gen(parity_rec_c_gen),
.parity_rec_d_gen(parity_rec_d_gen),
.control_p_r(control_p_r),
.dta_timec_p(dta_timec_p),
.control_l_r(control_l_r),
.state_data_process(state_data_process),
.last_is_control(last_is_control),
.last_is_data(last_is_data),
.last_is_timec(last_is_timec),
.rx_error_c(rx_error_c),
.rx_error_d(rx_error_d),
.rx_got_fct(rx_got_fct),
.rx_data_flag(rx_data_flag),
.timecode(timecode)
);
endmodule
|
`timescale 1ns / 1ps
module dff_async_rst_tb;
// Inputs
reg clk;
reg rst;
reg d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_async_rst uut (
.clk(clk),
.rst(rst),
.d(d),
.q(q)
);
task expect;
input exp_out;
if (q !== exp_out) begin
$display("TEST FAILED");
$display("At time %0d rst=%0b, d=%0b, q=%0b",
$time, rst, d, q );
$display("q should be %0b", exp_out );
$finish;
end
else begin
$display("At time %0d rst=%0b, d=%0b, q=%0b",
$time, rst, d, q );
end
endtask
// Clock and async reset stimulus
initial begin
clk = 1'b0;
rst = 1'b1;
// hold async reset for next 2 cc
repeat(4) #10 clk = ~clk;
// deassert reset
rst = 1'b0;
// clock forever
forever #10 clk = ~clk;
end
// Stimulus
initial begin
// Initialize Input d to 1 to observe effect of reset
d = 1'b1;
// Observe effect of async reset
@(negedge clk);
expect(1'b0);
// wait for reset to deassert
@(negedge rst);
// as d is still set to 1, we should get q as 1 next
@(negedge clk)
expect(1'b1);
// set d to 0, we should get q as 0 next
d = 1'b0;
@(negedge clk);
expect(1'b0);
$display("TEST PASSED");
$finish;
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_req_requires (clock, reset, enable, req_trigger, req_follower, resp_leader,
resp_trigger, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter min_cks = 1;
parameter max_cks = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input req_trigger, req_follower;
input resp_trigger, resp_leader;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_REQ_REQUIRES";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_req_requires_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_req_requires
|
`include "timescale.v"
module fb_txcounters (MTxClk, Reset,
StateIdle, StatePreamble, StateSoC, StateNumb, StateDist, StateDelay, StateDelayDist,
StateData, StateCrc, StateFrmCrc,
StartData, CrcNibCnt,
TotalNibCnt, NibCnt, CrcStateEnd, PreambleStateEnd, FrmCrcStateEnd, TxRamAddr
);
input MTxClk; // Tx clock
input Reset; // Reset
input StateIdle; // Idle state
input StatePreamble; // Preamble state
input StateSoC; // SoC state
input StateNumb;
input [1:0] StateDist;
input StateDelay;
input [1:0] StateDelayDist;
input [1:0] StateData; // Data state
input [1:0] StartData; // Start Data state
input StateCrc; // CRC state
input StateFrmCrc;
output [3: 0] CrcNibCnt; // total Nibble counter
output [15:0] TotalNibCnt; // total Nibble counter
output [15:0] NibCnt; // Nibble counter
output CrcStateEnd;
output PreambleStateEnd;
output FrmCrcStateEnd;
output [7: 0] TxRamAddr;
wire ResetNibCnt;
wire IncrementNibCnt;
wire ResetTotalNibCnt;
wire IncrementTotalNibCnt;
reg [15:0] TotalNibCnt;
reg [15:0] NibCnt;
reg [3: 0] CrcNibCnt;
reg [3: 0] PreambleNibCnt;
reg [3: 0] FrmCrcNibCnt;
reg [7: 0] TxRamAddr;
assign IncrementNibCnt = (|StateData) ;
assign ResetNibCnt = StateIdle | StateSoC & StartData[0] | StateCrc & StartData[0]| StateCrc;
// Nibble Counter started from each slave data( only for data, no SoC no CRC)
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
NibCnt <= 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= 16'h0;
else
if(IncrementNibCnt)
NibCnt <= NibCnt + 16'd1;
end
end
assign IncrementTotalNibCnt = StatePreamble | StateSoC | StateNumb | (|StateDist) | StateDelay | (|StateDelayDist)| (|StateData) | StateCrc ;
assign ResetTotalNibCnt = StateIdle;
// Total Nibble Counter for the whole frame incl.(Preamble, SoC, SlaveDate, SlaveCRC, NO FrameCRC)
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TotalNibCnt <= 16'h0;
else
begin
if(ResetTotalNibCnt)
TotalNibCnt <= 16'h0;
else
if(IncrementTotalNibCnt)
TotalNibCnt <= TotalNibCnt + 16'd1;
end
end
wire IncrementCrcNibCnt;
wire ResetCrcNibCnt;
assign IncrementCrcNibCnt = StateCrc ;
assign ResetCrcNibCnt = (|StateData);
assign CrcStateEnd = CrcNibCnt[0] ; // CRC always has two nibbles
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
CrcNibCnt <= 4'b0;
else
begin
if(ResetCrcNibCnt)
CrcNibCnt <= 4'b0;
else
if(IncrementCrcNibCnt)
CrcNibCnt <= CrcNibCnt + 4'b0001;
end
end
wire IncrementFrmCrcNibCnt;
wire ResetFrmCrcNibCnt;
assign IncrementFrmCrcNibCnt = StateFrmCrc ;
assign ResetFrmCrcNibCnt = StateCrc ;
assign FrmCrcStateEnd = FrmCrcNibCnt[0] ; // CRC always has two nibbles
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
FrmCrcNibCnt <= 4'b0;
else
begin
if(ResetFrmCrcNibCnt)
FrmCrcNibCnt <= 4'b0;
else
if(IncrementFrmCrcNibCnt)
FrmCrcNibCnt <= FrmCrcNibCnt + 4'b0001;
end
end
wire IncrementPreambleNibCnt;
wire ResetPreambleNibCnt;
assign IncrementPreambleNibCnt = StatePreamble ;
assign ResetPreambleNibCnt = StateIdle;
assign PreambleStateEnd = (PreambleNibCnt == 4'b0010);
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
PreambleNibCnt <= 4'b0;
else
begin
if(ResetPreambleNibCnt)
PreambleNibCnt <= 4'b0;
else
if(IncrementPreambleNibCnt)
PreambleNibCnt <= PreambleNibCnt + 4'b0001;
end
end
wire IncrementTxRamAddr;
wire ResetTxRamAddr;
assign IncrementTxRamAddr = StateData[0];
assign ResetTxRamAddr = StateIdle | StatePreamble | StateSoC;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxRamAddr <= 8'b0;
else
begin
if(ResetTxRamAddr)
TxRamAddr <= 8'b0;
else
if(IncrementTxRamAddr)
TxRamAddr <= TxRamAddr + 8'b0001;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__NOR2_BEHAVIORAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX4_SYMBOL_V
`define SKY130_FD_SC_HD__MUX4_SYMBOL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__mux4 (
//# {{data|Data Signals}}
input A0,
input A1,
input A2,
input A3,
output X ,
//# {{control|Control Signals}}
input S0,
input S1
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX4_SYMBOL_V
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Sep 5 14:58:25 EDT 2016
//
// Method conflict info:
// Method: in_ports_0_putRoutedFlit
// Conflict-free: in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
// Conflicts: in_ports_0_putRoutedFlit
//
// Method: in_ports_0_getNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
//
// Method: in_ports_1_putRoutedFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
// Conflicts: in_ports_1_putRoutedFlit
//
// Method: in_ports_1_getNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
//
// Method: in_ports_2_putRoutedFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
// Conflicts: in_ports_2_putRoutedFlit
//
// Method: in_ports_2_getNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
//
// Method: in_ports_3_putRoutedFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
// Conflicts: in_ports_3_putRoutedFlit
//
// Method: in_ports_3_getNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
//
// Method: in_ports_4_putRoutedFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
// Conflicts: in_ports_4_putRoutedFlit
//
// Method: in_ports_4_getNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_0_putNonFullVCs,
// out_ports_1_getFlit,
// out_ports_1_putNonFullVCs,
// out_ports_2_getFlit,
// out_ports_2_putNonFullVCs,
// out_ports_3_getFlit,
// out_ports_3_putNonFullVCs,
// out_ports_4_getFlit,
// out_ports_4_putNonFullVCs
//
// Method: out_ports_0_getFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Sequenced after (restricted): out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
//
// Method: out_ports_0_putNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
// Sequenced before (restricted): out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Conflicts: out_ports_0_putNonFullVCs
//
// Method: out_ports_1_getFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Sequenced after (restricted): out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
//
// Method: out_ports_1_putNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
// Sequenced before (restricted): out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Conflicts: out_ports_1_putNonFullVCs
//
// Method: out_ports_2_getFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Sequenced after (restricted): out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
//
// Method: out_ports_2_putNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
// Sequenced before (restricted): out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Conflicts: out_ports_2_putNonFullVCs
//
// Method: out_ports_3_getFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Sequenced after (restricted): out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
//
// Method: out_ports_3_putNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_4_putNonFullVCs
// Sequenced before (restricted): out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Conflicts: out_ports_3_putNonFullVCs
//
// Method: out_ports_4_getFlit
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Sequenced after (restricted): out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs,
// out_ports_4_putNonFullVCs
//
// Method: out_ports_4_putNonFullVCs
// Conflict-free: in_ports_0_putRoutedFlit,
// in_ports_0_getNonFullVCs,
// in_ports_1_putRoutedFlit,
// in_ports_1_getNonFullVCs,
// in_ports_2_putRoutedFlit,
// in_ports_2_getNonFullVCs,
// in_ports_3_putRoutedFlit,
// in_ports_3_getNonFullVCs,
// in_ports_4_putRoutedFlit,
// in_ports_4_getNonFullVCs,
// out_ports_0_putNonFullVCs,
// out_ports_1_putNonFullVCs,
// out_ports_2_putNonFullVCs,
// out_ports_3_putNonFullVCs
// Sequenced before (restricted): out_ports_0_getFlit,
// out_ports_1_getFlit,
// out_ports_2_getFlit,
// out_ports_3_getFlit,
// out_ports_4_getFlit
// Conflicts: out_ports_4_putNonFullVCs
//
//
// Ports:
// Name I/O size props
// in_ports_0_getNonFullVCs O 2
// in_ports_1_getNonFullVCs O 2
// in_ports_2_getNonFullVCs O 2
// in_ports_3_getNonFullVCs O 2
// in_ports_4_getNonFullVCs O 2
// out_ports_0_getFlit O 133
// out_ports_1_getFlit O 133
// out_ports_2_getFlit O 133
// out_ports_3_getFlit O 133
// out_ports_4_getFlit O 133
// CLK I 1 clock
// RST_N I 1 reset
// in_ports_0_putRoutedFlit_flit_in I 136
// in_ports_1_putRoutedFlit_flit_in I 136
// in_ports_2_putRoutedFlit_flit_in I 136
// in_ports_3_putRoutedFlit_flit_in I 136
// in_ports_4_putRoutedFlit_flit_in I 136
// out_ports_0_putNonFullVCs_nonFullVCs I 2
// out_ports_1_putNonFullVCs_nonFullVCs I 2
// out_ports_2_putNonFullVCs_nonFullVCs I 2
// out_ports_3_putNonFullVCs_nonFullVCs I 2
// out_ports_4_putNonFullVCs_nonFullVCs I 2
// EN_in_ports_0_putRoutedFlit I 1
// EN_in_ports_1_putRoutedFlit I 1
// EN_in_ports_2_putRoutedFlit I 1
// EN_in_ports_3_putRoutedFlit I 1
// EN_in_ports_4_putRoutedFlit I 1
// EN_out_ports_0_putNonFullVCs I 1
// EN_out_ports_1_putNonFullVCs I 1
// EN_out_ports_2_putNonFullVCs I 1
// EN_out_ports_3_putNonFullVCs I 1
// EN_out_ports_4_putNonFullVCs I 1
// EN_in_ports_0_getNonFullVCs I 1 unused
// EN_in_ports_1_getNonFullVCs I 1 unused
// EN_in_ports_2_getNonFullVCs I 1 unused
// EN_in_ports_3_getNonFullVCs I 1 unused
// EN_in_ports_4_getNonFullVCs I 1 unused
// EN_out_ports_0_getFlit I 1 unused
// EN_out_ports_1_getFlit I 1 unused
// EN_out_ports_2_getFlit I 1 unused
// EN_out_ports_3_getFlit I 1 unused
// EN_out_ports_4_getFlit I 1 unused
//
// Combinational paths from inputs to outputs:
// (out_ports_0_putNonFullVCs_nonFullVCs,
// out_ports_1_putNonFullVCs_nonFullVCs,
// out_ports_2_putNonFullVCs_nonFullVCs,
// out_ports_3_putNonFullVCs_nonFullVCs,
// out_ports_4_putNonFullVCs_nonFullVCs,
// EN_out_ports_0_putNonFullVCs,
// EN_out_ports_1_putNonFullVCs,
// EN_out_ports_2_putNonFullVCs,
// EN_out_ports_3_putNonFullVCs,
// EN_out_ports_4_putNonFullVCs) -> out_ports_0_getFlit
// (out_ports_0_putNonFullVCs_nonFullVCs,
// out_ports_1_putNonFullVCs_nonFullVCs,
// out_ports_2_putNonFullVCs_nonFullVCs,
// out_ports_3_putNonFullVCs_nonFullVCs,
// out_ports_4_putNonFullVCs_nonFullVCs,
// EN_out_ports_0_putNonFullVCs,
// EN_out_ports_1_putNonFullVCs,
// EN_out_ports_2_putNonFullVCs,
// EN_out_ports_3_putNonFullVCs,
// EN_out_ports_4_putNonFullVCs) -> out_ports_1_getFlit
// (out_ports_0_putNonFullVCs_nonFullVCs,
// out_ports_1_putNonFullVCs_nonFullVCs,
// out_ports_2_putNonFullVCs_nonFullVCs,
// out_ports_3_putNonFullVCs_nonFullVCs,
// out_ports_4_putNonFullVCs_nonFullVCs,
// EN_out_ports_0_putNonFullVCs,
// EN_out_ports_1_putNonFullVCs,
// EN_out_ports_2_putNonFullVCs,
// EN_out_ports_3_putNonFullVCs,
// EN_out_ports_4_putNonFullVCs) -> out_ports_2_getFlit
// (out_ports_0_putNonFullVCs_nonFullVCs,
// out_ports_1_putNonFullVCs_nonFullVCs,
// out_ports_2_putNonFullVCs_nonFullVCs,
// out_ports_3_putNonFullVCs_nonFullVCs,
// out_ports_4_putNonFullVCs_nonFullVCs,
// EN_out_ports_0_putNonFullVCs,
// EN_out_ports_1_putNonFullVCs,
// EN_out_ports_2_putNonFullVCs,
// EN_out_ports_3_putNonFullVCs,
// EN_out_ports_4_putNonFullVCs) -> out_ports_3_getFlit
// (out_ports_0_putNonFullVCs_nonFullVCs,
// out_ports_1_putNonFullVCs_nonFullVCs,
// out_ports_2_putNonFullVCs_nonFullVCs,
// out_ports_3_putNonFullVCs_nonFullVCs,
// out_ports_4_putNonFullVCs_nonFullVCs,
// EN_out_ports_0_putNonFullVCs,
// EN_out_ports_1_putNonFullVCs,
// EN_out_ports_2_putNonFullVCs,
// EN_out_ports_3_putNonFullVCs,
// EN_out_ports_4_putNonFullVCs) -> out_ports_4_getFlit
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkIQRouterCoreSimple(CLK,
RST_N,
in_ports_0_putRoutedFlit_flit_in,
EN_in_ports_0_putRoutedFlit,
EN_in_ports_0_getNonFullVCs,
in_ports_0_getNonFullVCs,
in_ports_1_putRoutedFlit_flit_in,
EN_in_ports_1_putRoutedFlit,
EN_in_ports_1_getNonFullVCs,
in_ports_1_getNonFullVCs,
in_ports_2_putRoutedFlit_flit_in,
EN_in_ports_2_putRoutedFlit,
EN_in_ports_2_getNonFullVCs,
in_ports_2_getNonFullVCs,
in_ports_3_putRoutedFlit_flit_in,
EN_in_ports_3_putRoutedFlit,
EN_in_ports_3_getNonFullVCs,
in_ports_3_getNonFullVCs,
in_ports_4_putRoutedFlit_flit_in,
EN_in_ports_4_putRoutedFlit,
EN_in_ports_4_getNonFullVCs,
in_ports_4_getNonFullVCs,
EN_out_ports_0_getFlit,
out_ports_0_getFlit,
out_ports_0_putNonFullVCs_nonFullVCs,
EN_out_ports_0_putNonFullVCs,
EN_out_ports_1_getFlit,
out_ports_1_getFlit,
out_ports_1_putNonFullVCs_nonFullVCs,
EN_out_ports_1_putNonFullVCs,
EN_out_ports_2_getFlit,
out_ports_2_getFlit,
out_ports_2_putNonFullVCs_nonFullVCs,
EN_out_ports_2_putNonFullVCs,
EN_out_ports_3_getFlit,
out_ports_3_getFlit,
out_ports_3_putNonFullVCs_nonFullVCs,
EN_out_ports_3_putNonFullVCs,
EN_out_ports_4_getFlit,
out_ports_4_getFlit,
out_ports_4_putNonFullVCs_nonFullVCs,
EN_out_ports_4_putNonFullVCs);
input CLK;
input RST_N;
// action method in_ports_0_putRoutedFlit
input [135 : 0] in_ports_0_putRoutedFlit_flit_in;
input EN_in_ports_0_putRoutedFlit;
// actionvalue method in_ports_0_getNonFullVCs
input EN_in_ports_0_getNonFullVCs;
output [1 : 0] in_ports_0_getNonFullVCs;
// action method in_ports_1_putRoutedFlit
input [135 : 0] in_ports_1_putRoutedFlit_flit_in;
input EN_in_ports_1_putRoutedFlit;
// actionvalue method in_ports_1_getNonFullVCs
input EN_in_ports_1_getNonFullVCs;
output [1 : 0] in_ports_1_getNonFullVCs;
// action method in_ports_2_putRoutedFlit
input [135 : 0] in_ports_2_putRoutedFlit_flit_in;
input EN_in_ports_2_putRoutedFlit;
// actionvalue method in_ports_2_getNonFullVCs
input EN_in_ports_2_getNonFullVCs;
output [1 : 0] in_ports_2_getNonFullVCs;
// action method in_ports_3_putRoutedFlit
input [135 : 0] in_ports_3_putRoutedFlit_flit_in;
input EN_in_ports_3_putRoutedFlit;
// actionvalue method in_ports_3_getNonFullVCs
input EN_in_ports_3_getNonFullVCs;
output [1 : 0] in_ports_3_getNonFullVCs;
// action method in_ports_4_putRoutedFlit
input [135 : 0] in_ports_4_putRoutedFlit_flit_in;
input EN_in_ports_4_putRoutedFlit;
// actionvalue method in_ports_4_getNonFullVCs
input EN_in_ports_4_getNonFullVCs;
output [1 : 0] in_ports_4_getNonFullVCs;
// actionvalue method out_ports_0_getFlit
input EN_out_ports_0_getFlit;
output [132 : 0] out_ports_0_getFlit;
// action method out_ports_0_putNonFullVCs
input [1 : 0] out_ports_0_putNonFullVCs_nonFullVCs;
input EN_out_ports_0_putNonFullVCs;
// actionvalue method out_ports_1_getFlit
input EN_out_ports_1_getFlit;
output [132 : 0] out_ports_1_getFlit;
// action method out_ports_1_putNonFullVCs
input [1 : 0] out_ports_1_putNonFullVCs_nonFullVCs;
input EN_out_ports_1_putNonFullVCs;
// actionvalue method out_ports_2_getFlit
input EN_out_ports_2_getFlit;
output [132 : 0] out_ports_2_getFlit;
// action method out_ports_2_putNonFullVCs
input [1 : 0] out_ports_2_putNonFullVCs_nonFullVCs;
input EN_out_ports_2_putNonFullVCs;
// actionvalue method out_ports_3_getFlit
input EN_out_ports_3_getFlit;
output [132 : 0] out_ports_3_getFlit;
// action method out_ports_3_putNonFullVCs
input [1 : 0] out_ports_3_putNonFullVCs_nonFullVCs;
input EN_out_ports_3_putNonFullVCs;
// actionvalue method out_ports_4_getFlit
input EN_out_ports_4_getFlit;
output [132 : 0] out_ports_4_getFlit;
// action method out_ports_4_putNonFullVCs
input [1 : 0] out_ports_4_putNonFullVCs_nonFullVCs;
input EN_out_ports_4_putNonFullVCs;
// signals for module outputs
wire [132 : 0] out_ports_0_getFlit,
out_ports_1_getFlit,
out_ports_2_getFlit,
out_ports_3_getFlit,
out_ports_4_getFlit;
wire [1 : 0] in_ports_0_getNonFullVCs,
in_ports_1_getNonFullVCs,
in_ports_2_getNonFullVCs,
in_ports_3_getNonFullVCs,
in_ports_4_getNonFullVCs;
// inlined wires
wire [132 : 0] hasFlitsToSend_perIn$wget,
hasFlitsToSend_perIn_1$wget,
hasFlitsToSend_perIn_2$wget,
hasFlitsToSend_perIn_3$wget,
hasFlitsToSend_perIn_4$wget;
// register inPortVL
reg [2 : 0] inPortVL;
wire [2 : 0] inPortVL$D_IN;
wire inPortVL$EN;
// register inPortVL_1
reg [2 : 0] inPortVL_1;
wire [2 : 0] inPortVL_1$D_IN;
wire inPortVL_1$EN;
// register inPortVL_2
reg [2 : 0] inPortVL_2;
wire [2 : 0] inPortVL_2$D_IN;
wire inPortVL_2$EN;
// register inPortVL_3
reg [2 : 0] inPortVL_3;
wire [2 : 0] inPortVL_3$D_IN;
wire inPortVL_3$EN;
// register inPortVL_4
reg [2 : 0] inPortVL_4;
wire [2 : 0] inPortVL_4$D_IN;
wire inPortVL_4$EN;
// register lockedVL
reg lockedVL;
wire lockedVL$D_IN, lockedVL$EN;
// register lockedVL_1
reg lockedVL_1;
wire lockedVL_1$D_IN, lockedVL_1$EN;
// register lockedVL_2
reg lockedVL_2;
wire lockedVL_2$D_IN, lockedVL_2$EN;
// register lockedVL_3
reg lockedVL_3;
wire lockedVL_3$D_IN, lockedVL_3$EN;
// register lockedVL_4
reg lockedVL_4;
wire lockedVL_4$D_IN, lockedVL_4$EN;
// register selectedIO_reg_0
reg selectedIO_reg_0;
wire selectedIO_reg_0$D_IN, selectedIO_reg_0$EN;
// register selectedIO_reg_0_1
reg selectedIO_reg_0_1;
wire selectedIO_reg_0_1$D_IN, selectedIO_reg_0_1$EN;
// register selectedIO_reg_0_2
reg selectedIO_reg_0_2;
wire selectedIO_reg_0_2$D_IN, selectedIO_reg_0_2$EN;
// register selectedIO_reg_0_3
reg selectedIO_reg_0_3;
wire selectedIO_reg_0_3$D_IN, selectedIO_reg_0_3$EN;
// register selectedIO_reg_0_4
reg selectedIO_reg_0_4;
wire selectedIO_reg_0_4$D_IN, selectedIO_reg_0_4$EN;
// register selectedIO_reg_1
reg selectedIO_reg_1;
wire selectedIO_reg_1$D_IN, selectedIO_reg_1$EN;
// register selectedIO_reg_1_1
reg selectedIO_reg_1_1;
wire selectedIO_reg_1_1$D_IN, selectedIO_reg_1_1$EN;
// register selectedIO_reg_1_2
reg selectedIO_reg_1_2;
wire selectedIO_reg_1_2$D_IN, selectedIO_reg_1_2$EN;
// register selectedIO_reg_1_3
reg selectedIO_reg_1_3;
wire selectedIO_reg_1_3$D_IN, selectedIO_reg_1_3$EN;
// register selectedIO_reg_1_4
reg selectedIO_reg_1_4;
wire selectedIO_reg_1_4$D_IN, selectedIO_reg_1_4$EN;
// register selectedIO_reg_2
reg selectedIO_reg_2;
wire selectedIO_reg_2$D_IN, selectedIO_reg_2$EN;
// register selectedIO_reg_2_1
reg selectedIO_reg_2_1;
wire selectedIO_reg_2_1$D_IN, selectedIO_reg_2_1$EN;
// register selectedIO_reg_2_2
reg selectedIO_reg_2_2;
wire selectedIO_reg_2_2$D_IN, selectedIO_reg_2_2$EN;
// register selectedIO_reg_2_3
reg selectedIO_reg_2_3;
wire selectedIO_reg_2_3$D_IN, selectedIO_reg_2_3$EN;
// register selectedIO_reg_2_4
reg selectedIO_reg_2_4;
wire selectedIO_reg_2_4$D_IN, selectedIO_reg_2_4$EN;
// register selectedIO_reg_3
reg selectedIO_reg_3;
wire selectedIO_reg_3$D_IN, selectedIO_reg_3$EN;
// register selectedIO_reg_3_1
reg selectedIO_reg_3_1;
wire selectedIO_reg_3_1$D_IN, selectedIO_reg_3_1$EN;
// register selectedIO_reg_3_2
reg selectedIO_reg_3_2;
wire selectedIO_reg_3_2$D_IN, selectedIO_reg_3_2$EN;
// register selectedIO_reg_3_3
reg selectedIO_reg_3_3;
wire selectedIO_reg_3_3$D_IN, selectedIO_reg_3_3$EN;
// register selectedIO_reg_3_4
reg selectedIO_reg_3_4;
wire selectedIO_reg_3_4$D_IN, selectedIO_reg_3_4$EN;
// register selectedIO_reg_4
reg selectedIO_reg_4;
wire selectedIO_reg_4$D_IN, selectedIO_reg_4$EN;
// register selectedIO_reg_4_1
reg selectedIO_reg_4_1;
wire selectedIO_reg_4_1$D_IN, selectedIO_reg_4_1$EN;
// register selectedIO_reg_4_2
reg selectedIO_reg_4_2;
wire selectedIO_reg_4_2$D_IN, selectedIO_reg_4_2$EN;
// register selectedIO_reg_4_3
reg selectedIO_reg_4_3;
wire selectedIO_reg_4_3$D_IN, selectedIO_reg_4_3$EN;
// register selectedIO_reg_4_4
reg selectedIO_reg_4_4;
wire selectedIO_reg_4_4$D_IN, selectedIO_reg_4_4$EN;
// ports of submodule flitBuffers
wire [131 : 0] flitBuffers$deq, flitBuffers$enq_data_in;
wire flitBuffers$EN_deq,
flitBuffers$EN_enq,
flitBuffers$notEmpty,
flitBuffers$notFull;
// ports of submodule flitBuffers_1
wire [131 : 0] flitBuffers_1$deq, flitBuffers_1$enq_data_in;
wire flitBuffers_1$EN_deq,
flitBuffers_1$EN_enq,
flitBuffers_1$notEmpty,
flitBuffers_1$notFull;
// ports of submodule flitBuffers_2
wire [131 : 0] flitBuffers_2$deq, flitBuffers_2$enq_data_in;
wire flitBuffers_2$EN_deq,
flitBuffers_2$EN_enq,
flitBuffers_2$notEmpty,
flitBuffers_2$notFull;
// ports of submodule flitBuffers_3
wire [131 : 0] flitBuffers_3$deq, flitBuffers_3$enq_data_in;
wire flitBuffers_3$EN_deq,
flitBuffers_3$EN_enq,
flitBuffers_3$notEmpty,
flitBuffers_3$notFull;
// ports of submodule flitBuffers_4
wire [131 : 0] flitBuffers_4$deq, flitBuffers_4$enq_data_in;
wire flitBuffers_4$EN_deq,
flitBuffers_4$EN_enq,
flitBuffers_4$notEmpty,
flitBuffers_4$notFull;
// ports of submodule outPortFIFOs
wire [2 : 0] outPortFIFOs$enq_sendData, outPortFIFOs$first;
wire outPortFIFOs$EN_clear, outPortFIFOs$EN_deq, outPortFIFOs$EN_enq;
// ports of submodule outPortFIFOs_1
wire [2 : 0] outPortFIFOs_1$enq_sendData, outPortFIFOs_1$first;
wire outPortFIFOs_1$EN_clear, outPortFIFOs_1$EN_deq, outPortFIFOs_1$EN_enq;
// ports of submodule outPortFIFOs_2
wire [2 : 0] outPortFIFOs_2$enq_sendData, outPortFIFOs_2$first;
wire outPortFIFOs_2$EN_clear, outPortFIFOs_2$EN_deq, outPortFIFOs_2$EN_enq;
// ports of submodule outPortFIFOs_3
wire [2 : 0] outPortFIFOs_3$enq_sendData, outPortFIFOs_3$first;
wire outPortFIFOs_3$EN_clear, outPortFIFOs_3$EN_deq, outPortFIFOs_3$EN_enq;
// ports of submodule outPortFIFOs_4
wire [2 : 0] outPortFIFOs_4$enq_sendData, outPortFIFOs_4$first;
wire outPortFIFOs_4$EN_clear, outPortFIFOs_4$EN_deq, outPortFIFOs_4$EN_enq;
// ports of submodule routerAlloc
wire [24 : 0] routerAlloc$allocate, routerAlloc$allocate_alloc_input;
wire routerAlloc$EN_allocate, routerAlloc$EN_next;
// remaining internal signals
reg [131 : 0] IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d845,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d846,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d847,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d848;
reg IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d433,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d495,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d557,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d619,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d855,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d856,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d857,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d858,
IF_outPortFIFOs_1_first__8_EQ_0_9_THEN_simple__ETC___d88,
IF_outPortFIFOs_2_first__7_EQ_0_8_THEN_simple__ETC___d67,
IF_outPortFIFOs_3_first__7_EQ_0_8_THEN_simple__ETC___d47,
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d27,
IF_outPortFIFOs_first__8_EQ_0_9_THEN_simple_cr_ETC___d108;
wire [131 : 0] IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d390,
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d844;
wire [3 : 0] outport_encoder___d828,
outport_encoder___d829,
outport_encoder___d830,
outport_encoder___d831,
outport_encoder___d832;
wire [2 : 0] IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d693,
IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d694,
IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d695,
IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d696,
IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d689,
IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d690,
IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d691,
IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d692,
IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d697,
IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d698,
IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d699,
IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d700,
active_in__h35433,
active_in__h36374,
active_in__h37315,
active_in__h38256;
wire IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d347,
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d348,
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d349,
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d360,
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d361,
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d362,
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d363,
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d854,
IF_outport_encoder_03_BIT_3_04_THEN_NOT_outpor_ETC___d654,
IF_outport_encoder_03_BIT_3_04_THEN_NOT_outpor_ETC___d668,
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d652,
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d656,
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d662,
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d669,
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d671,
IF_outport_encoder_24_BIT_3_25_THEN_NOT_outpor_ETC___d653,
IF_outport_encoder_24_BIT_3_25_THEN_NOT_outpor_ETC___d665,
IF_outport_encoder_24_BIT_3_25_THEN_NOT_outpor_ETC___d667,
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d659,
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d663,
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d672,
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d683,
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d685,
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d792,
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d809,
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d810,
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d811,
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d791,
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d801,
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d803,
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d805,
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d807,
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d651,
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d655,
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d676,
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d684,
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d686;
// actionvalue method in_ports_0_getNonFullVCs
assign in_ports_0_getNonFullVCs = { 1'd0, flitBuffers$notFull } ;
// actionvalue method in_ports_1_getNonFullVCs
assign in_ports_1_getNonFullVCs = { 1'd0, flitBuffers_1$notFull } ;
// actionvalue method in_ports_2_getNonFullVCs
assign in_ports_2_getNonFullVCs = { 1'd0, flitBuffers_2$notFull } ;
// actionvalue method in_ports_3_getNonFullVCs
assign in_ports_3_getNonFullVCs = { 1'd0, flitBuffers_3$notFull } ;
// actionvalue method in_ports_4_getNonFullVCs
assign in_ports_4_getNonFullVCs = { 1'd0, flitBuffers_4$notFull } ;
// actionvalue method out_ports_0_getFlit
assign out_ports_0_getFlit =
{ IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d791 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d363,
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d844 } ;
// actionvalue method out_ports_1_getFlit
assign out_ports_1_getFlit =
{ IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d801 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d433,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d845 } ;
// actionvalue method out_ports_2_getFlit
assign out_ports_2_getFlit =
{ IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d803 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d495,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d846 } ;
// actionvalue method out_ports_3_getFlit
assign out_ports_3_getFlit =
{ IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d805 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d557,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d847 } ;
// actionvalue method out_ports_4_getFlit
assign out_ports_4_getFlit =
{ IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d807 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d619,
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d848 } ;
// submodule flitBuffers
mkInputQueue flitBuffers(.CLK(CLK),
.RST_N(RST_N),
.enq_data_in(flitBuffers$enq_data_in),
.EN_enq(flitBuffers$EN_enq),
.EN_deq(flitBuffers$EN_deq),
.deq(flitBuffers$deq),
.notEmpty(flitBuffers$notEmpty),
.notFull(flitBuffers$notFull));
// submodule flitBuffers_1
mkInputQueue flitBuffers_1(.CLK(CLK),
.RST_N(RST_N),
.enq_data_in(flitBuffers_1$enq_data_in),
.EN_enq(flitBuffers_1$EN_enq),
.EN_deq(flitBuffers_1$EN_deq),
.deq(flitBuffers_1$deq),
.notEmpty(flitBuffers_1$notEmpty),
.notFull(flitBuffers_1$notFull));
// submodule flitBuffers_2
mkInputQueue flitBuffers_2(.CLK(CLK),
.RST_N(RST_N),
.enq_data_in(flitBuffers_2$enq_data_in),
.EN_enq(flitBuffers_2$EN_enq),
.EN_deq(flitBuffers_2$EN_deq),
.deq(flitBuffers_2$deq),
.notEmpty(flitBuffers_2$notEmpty),
.notFull(flitBuffers_2$notFull));
// submodule flitBuffers_3
mkInputQueue flitBuffers_3(.CLK(CLK),
.RST_N(RST_N),
.enq_data_in(flitBuffers_3$enq_data_in),
.EN_enq(flitBuffers_3$EN_enq),
.EN_deq(flitBuffers_3$EN_deq),
.deq(flitBuffers_3$deq),
.notEmpty(flitBuffers_3$notEmpty),
.notFull(flitBuffers_3$notFull));
// submodule flitBuffers_4
mkInputQueue flitBuffers_4(.CLK(CLK),
.RST_N(RST_N),
.enq_data_in(flitBuffers_4$enq_data_in),
.EN_enq(flitBuffers_4$EN_enq),
.EN_deq(flitBuffers_4$EN_deq),
.deq(flitBuffers_4$deq),
.notEmpty(flitBuffers_4$notEmpty),
.notFull(flitBuffers_4$notFull));
// submodule outPortFIFOs
mkOutPortFIFO outPortFIFOs(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs$enq_sendData),
.EN_enq(outPortFIFOs$EN_enq),
.EN_deq(outPortFIFOs$EN_deq),
.EN_clear(outPortFIFOs$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_1
mkOutPortFIFO outPortFIFOs_1(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_1$enq_sendData),
.EN_enq(outPortFIFOs_1$EN_enq),
.EN_deq(outPortFIFOs_1$EN_deq),
.EN_clear(outPortFIFOs_1$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_1$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_2
mkOutPortFIFO outPortFIFOs_2(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_2$enq_sendData),
.EN_enq(outPortFIFOs_2$EN_enq),
.EN_deq(outPortFIFOs_2$EN_deq),
.EN_clear(outPortFIFOs_2$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_2$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_3
mkOutPortFIFO outPortFIFOs_3(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_3$enq_sendData),
.EN_enq(outPortFIFOs_3$EN_enq),
.EN_deq(outPortFIFOs_3$EN_deq),
.EN_clear(outPortFIFOs_3$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_3$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule outPortFIFOs_4
mkOutPortFIFO outPortFIFOs_4(.CLK(CLK),
.RST_N(RST_N),
.enq_sendData(outPortFIFOs_4$enq_sendData),
.EN_enq(outPortFIFOs_4$EN_enq),
.EN_deq(outPortFIFOs_4$EN_deq),
.EN_clear(outPortFIFOs_4$EN_clear),
.RDY_enq(),
.RDY_deq(),
.first(outPortFIFOs_4$first),
.RDY_first(),
.notFull(),
.RDY_notFull(),
.notEmpty(),
.RDY_notEmpty(),
.count(),
.RDY_count(),
.RDY_clear());
// submodule routerAlloc
mkSepRouterAllocator routerAlloc(.pipeline(1'd0),
.CLK(CLK),
.RST_N(RST_N),
.allocate_alloc_input(routerAlloc$allocate_alloc_input),
.EN_allocate(routerAlloc$EN_allocate),
.EN_next(routerAlloc$EN_next),
.allocate(routerAlloc$allocate));
// inlined wires
assign hasFlitsToSend_perIn$wget = { 1'd1, flitBuffers$deq } ;
assign hasFlitsToSend_perIn_1$wget = { 1'd1, flitBuffers_1$deq } ;
assign hasFlitsToSend_perIn_2$wget = { 1'd1, flitBuffers_2$deq } ;
assign hasFlitsToSend_perIn_3$wget = { 1'd1, flitBuffers_3$deq } ;
assign hasFlitsToSend_perIn_4$wget = { 1'd1, flitBuffers_4$deq } ;
// register inPortVL
assign inPortVL$D_IN = 3'h0 ;
assign inPortVL$EN = 1'b0 ;
// register inPortVL_1
assign inPortVL_1$D_IN = 3'h0 ;
assign inPortVL_1$EN = 1'b0 ;
// register inPortVL_2
assign inPortVL_2$D_IN = 3'h0 ;
assign inPortVL_2$EN = 1'b0 ;
// register inPortVL_3
assign inPortVL_3$D_IN = 3'h0 ;
assign inPortVL_3$EN = 1'b0 ;
// register inPortVL_4
assign inPortVL_4$D_IN = 3'h0 ;
assign inPortVL_4$EN = 1'b0 ;
// register lockedVL
assign lockedVL$D_IN = 1'b0 ;
assign lockedVL$EN = 1'b0 ;
// register lockedVL_1
assign lockedVL_1$D_IN = 1'b0 ;
assign lockedVL_1$EN = 1'b0 ;
// register lockedVL_2
assign lockedVL_2$D_IN = 1'b0 ;
assign lockedVL_2$EN = 1'b0 ;
// register lockedVL_3
assign lockedVL_3$D_IN = 1'b0 ;
assign lockedVL_3$EN = 1'b0 ;
// register lockedVL_4
assign lockedVL_4$D_IN = 1'b0 ;
assign lockedVL_4$EN = 1'b0 ;
// register selectedIO_reg_0
assign selectedIO_reg_0$D_IN = 1'b0 ;
assign selectedIO_reg_0$EN = 1'b0 ;
// register selectedIO_reg_0_1
assign selectedIO_reg_0_1$D_IN = 1'b0 ;
assign selectedIO_reg_0_1$EN = 1'b0 ;
// register selectedIO_reg_0_2
assign selectedIO_reg_0_2$D_IN = 1'b0 ;
assign selectedIO_reg_0_2$EN = 1'b0 ;
// register selectedIO_reg_0_3
assign selectedIO_reg_0_3$D_IN = 1'b0 ;
assign selectedIO_reg_0_3$EN = 1'b0 ;
// register selectedIO_reg_0_4
assign selectedIO_reg_0_4$D_IN = 1'b0 ;
assign selectedIO_reg_0_4$EN = 1'b0 ;
// register selectedIO_reg_1
assign selectedIO_reg_1$D_IN = 1'b0 ;
assign selectedIO_reg_1$EN = 1'b0 ;
// register selectedIO_reg_1_1
assign selectedIO_reg_1_1$D_IN = 1'b0 ;
assign selectedIO_reg_1_1$EN = 1'b0 ;
// register selectedIO_reg_1_2
assign selectedIO_reg_1_2$D_IN = 1'b0 ;
assign selectedIO_reg_1_2$EN = 1'b0 ;
// register selectedIO_reg_1_3
assign selectedIO_reg_1_3$D_IN = 1'b0 ;
assign selectedIO_reg_1_3$EN = 1'b0 ;
// register selectedIO_reg_1_4
assign selectedIO_reg_1_4$D_IN = 1'b0 ;
assign selectedIO_reg_1_4$EN = 1'b0 ;
// register selectedIO_reg_2
assign selectedIO_reg_2$D_IN = 1'b0 ;
assign selectedIO_reg_2$EN = 1'b0 ;
// register selectedIO_reg_2_1
assign selectedIO_reg_2_1$D_IN = 1'b0 ;
assign selectedIO_reg_2_1$EN = 1'b0 ;
// register selectedIO_reg_2_2
assign selectedIO_reg_2_2$D_IN = 1'b0 ;
assign selectedIO_reg_2_2$EN = 1'b0 ;
// register selectedIO_reg_2_3
assign selectedIO_reg_2_3$D_IN = 1'b0 ;
assign selectedIO_reg_2_3$EN = 1'b0 ;
// register selectedIO_reg_2_4
assign selectedIO_reg_2_4$D_IN = 1'b0 ;
assign selectedIO_reg_2_4$EN = 1'b0 ;
// register selectedIO_reg_3
assign selectedIO_reg_3$D_IN = 1'b0 ;
assign selectedIO_reg_3$EN = 1'b0 ;
// register selectedIO_reg_3_1
assign selectedIO_reg_3_1$D_IN = 1'b0 ;
assign selectedIO_reg_3_1$EN = 1'b0 ;
// register selectedIO_reg_3_2
assign selectedIO_reg_3_2$D_IN = 1'b0 ;
assign selectedIO_reg_3_2$EN = 1'b0 ;
// register selectedIO_reg_3_3
assign selectedIO_reg_3_3$D_IN = 1'b0 ;
assign selectedIO_reg_3_3$EN = 1'b0 ;
// register selectedIO_reg_3_4
assign selectedIO_reg_3_4$D_IN = 1'b0 ;
assign selectedIO_reg_3_4$EN = 1'b0 ;
// register selectedIO_reg_4
assign selectedIO_reg_4$D_IN = 1'b0 ;
assign selectedIO_reg_4$EN = 1'b0 ;
// register selectedIO_reg_4_1
assign selectedIO_reg_4_1$D_IN = 1'b0 ;
assign selectedIO_reg_4_1$EN = 1'b0 ;
// register selectedIO_reg_4_2
assign selectedIO_reg_4_2$D_IN = 1'b0 ;
assign selectedIO_reg_4_2$EN = 1'b0 ;
// register selectedIO_reg_4_3
assign selectedIO_reg_4_3$D_IN = 1'b0 ;
assign selectedIO_reg_4_3$EN = 1'b0 ;
// register selectedIO_reg_4_4
assign selectedIO_reg_4_4$D_IN = 1'b0 ;
assign selectedIO_reg_4_4$EN = 1'b0 ;
// submodule flitBuffers
assign flitBuffers$enq_data_in = in_ports_0_putRoutedFlit_flit_in[134:3] ;
assign flitBuffers$EN_enq =
EN_in_ports_0_putRoutedFlit &&
in_ports_0_putRoutedFlit_flit_in[135] ;
assign flitBuffers$EN_deq = outport_encoder___d832[3] ;
// submodule flitBuffers_1
assign flitBuffers_1$enq_data_in = in_ports_1_putRoutedFlit_flit_in[134:3] ;
assign flitBuffers_1$EN_enq =
EN_in_ports_1_putRoutedFlit &&
in_ports_1_putRoutedFlit_flit_in[135] ;
assign flitBuffers_1$EN_deq = outport_encoder___d831[3] ;
// submodule flitBuffers_2
assign flitBuffers_2$enq_data_in = in_ports_2_putRoutedFlit_flit_in[134:3] ;
assign flitBuffers_2$EN_enq =
EN_in_ports_2_putRoutedFlit &&
in_ports_2_putRoutedFlit_flit_in[135] ;
assign flitBuffers_2$EN_deq = outport_encoder___d830[3] ;
// submodule flitBuffers_3
assign flitBuffers_3$enq_data_in = in_ports_3_putRoutedFlit_flit_in[134:3] ;
assign flitBuffers_3$EN_enq =
EN_in_ports_3_putRoutedFlit &&
in_ports_3_putRoutedFlit_flit_in[135] ;
assign flitBuffers_3$EN_deq = outport_encoder___d829[3] ;
// submodule flitBuffers_4
assign flitBuffers_4$enq_data_in = in_ports_4_putRoutedFlit_flit_in[134:3] ;
assign flitBuffers_4$EN_enq =
EN_in_ports_4_putRoutedFlit &&
in_ports_4_putRoutedFlit_flit_in[135] ;
assign flitBuffers_4$EN_deq = outport_encoder___d828[3] ;
// submodule outPortFIFOs
assign outPortFIFOs$enq_sendData = in_ports_0_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs$EN_enq =
EN_in_ports_0_putRoutedFlit &&
in_ports_0_putRoutedFlit_flit_in[135] ;
assign outPortFIFOs$EN_deq = outport_encoder___d832[3] ;
assign outPortFIFOs$EN_clear = 1'b0 ;
// submodule outPortFIFOs_1
assign outPortFIFOs_1$enq_sendData = in_ports_1_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_1$EN_enq =
EN_in_ports_1_putRoutedFlit &&
in_ports_1_putRoutedFlit_flit_in[135] ;
assign outPortFIFOs_1$EN_deq = outport_encoder___d831[3] ;
assign outPortFIFOs_1$EN_clear = 1'b0 ;
// submodule outPortFIFOs_2
assign outPortFIFOs_2$enq_sendData = in_ports_2_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_2$EN_enq =
EN_in_ports_2_putRoutedFlit &&
in_ports_2_putRoutedFlit_flit_in[135] ;
assign outPortFIFOs_2$EN_deq = outport_encoder___d830[3] ;
assign outPortFIFOs_2$EN_clear = 1'b0 ;
// submodule outPortFIFOs_3
assign outPortFIFOs_3$enq_sendData = in_ports_3_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_3$EN_enq =
EN_in_ports_3_putRoutedFlit &&
in_ports_3_putRoutedFlit_flit_in[135] ;
assign outPortFIFOs_3$EN_deq = outport_encoder___d829[3] ;
assign outPortFIFOs_3$EN_clear = 1'b0 ;
// submodule outPortFIFOs_4
assign outPortFIFOs_4$enq_sendData = in_ports_4_putRoutedFlit_flit_in[2:0] ;
assign outPortFIFOs_4$EN_enq =
EN_in_ports_4_putRoutedFlit &&
in_ports_4_putRoutedFlit_flit_in[135] ;
assign outPortFIFOs_4$EN_deq = outport_encoder___d828[3] ;
assign outPortFIFOs_4$EN_clear = 1'b0 ;
// submodule routerAlloc
assign routerAlloc$allocate_alloc_input =
{ flitBuffers_4$notEmpty &&
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d27 &&
outPortFIFOs_4$first == 3'd4,
flitBuffers_4$notEmpty &&
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d27 &&
outPortFIFOs_4$first == 3'd3,
flitBuffers_4$notEmpty &&
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d27 &&
outPortFIFOs_4$first == 3'd2,
flitBuffers_4$notEmpty &&
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d27 &&
outPortFIFOs_4$first == 3'd1,
flitBuffers_4$notEmpty &&
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d27 &&
outPortFIFOs_4$first == 3'd0,
flitBuffers_3$notEmpty &&
IF_outPortFIFOs_3_first__7_EQ_0_8_THEN_simple__ETC___d47 &&
outPortFIFOs_3$first == 3'd4,
flitBuffers_3$notEmpty &&
IF_outPortFIFOs_3_first__7_EQ_0_8_THEN_simple__ETC___d47 &&
outPortFIFOs_3$first == 3'd3,
flitBuffers_3$notEmpty &&
IF_outPortFIFOs_3_first__7_EQ_0_8_THEN_simple__ETC___d47 &&
outPortFIFOs_3$first == 3'd2,
flitBuffers_3$notEmpty &&
IF_outPortFIFOs_3_first__7_EQ_0_8_THEN_simple__ETC___d47 &&
outPortFIFOs_3$first == 3'd1,
flitBuffers_3$notEmpty &&
IF_outPortFIFOs_3_first__7_EQ_0_8_THEN_simple__ETC___d47 &&
outPortFIFOs_3$first == 3'd0,
flitBuffers_2$notEmpty &&
IF_outPortFIFOs_2_first__7_EQ_0_8_THEN_simple__ETC___d67 &&
outPortFIFOs_2$first == 3'd4,
flitBuffers_2$notEmpty &&
IF_outPortFIFOs_2_first__7_EQ_0_8_THEN_simple__ETC___d67 &&
outPortFIFOs_2$first == 3'd3,
flitBuffers_2$notEmpty &&
IF_outPortFIFOs_2_first__7_EQ_0_8_THEN_simple__ETC___d67 &&
outPortFIFOs_2$first == 3'd2,
flitBuffers_2$notEmpty &&
IF_outPortFIFOs_2_first__7_EQ_0_8_THEN_simple__ETC___d67 &&
outPortFIFOs_2$first == 3'd1,
flitBuffers_2$notEmpty &&
IF_outPortFIFOs_2_first__7_EQ_0_8_THEN_simple__ETC___d67 &&
outPortFIFOs_2$first == 3'd0,
flitBuffers_1$notEmpty &&
IF_outPortFIFOs_1_first__8_EQ_0_9_THEN_simple__ETC___d88 &&
outPortFIFOs_1$first == 3'd4,
flitBuffers_1$notEmpty &&
IF_outPortFIFOs_1_first__8_EQ_0_9_THEN_simple__ETC___d88 &&
outPortFIFOs_1$first == 3'd3,
flitBuffers_1$notEmpty &&
IF_outPortFIFOs_1_first__8_EQ_0_9_THEN_simple__ETC___d88 &&
outPortFIFOs_1$first == 3'd2,
flitBuffers_1$notEmpty &&
IF_outPortFIFOs_1_first__8_EQ_0_9_THEN_simple__ETC___d88 &&
outPortFIFOs_1$first == 3'd1,
flitBuffers_1$notEmpty &&
IF_outPortFIFOs_1_first__8_EQ_0_9_THEN_simple__ETC___d88 &&
outPortFIFOs_1$first == 3'd0,
flitBuffers$notEmpty &&
IF_outPortFIFOs_first__8_EQ_0_9_THEN_simple_cr_ETC___d108 &&
outPortFIFOs$first == 3'd4,
flitBuffers$notEmpty &&
IF_outPortFIFOs_first__8_EQ_0_9_THEN_simple_cr_ETC___d108 &&
outPortFIFOs$first == 3'd3,
flitBuffers$notEmpty &&
IF_outPortFIFOs_first__8_EQ_0_9_THEN_simple_cr_ETC___d108 &&
outPortFIFOs$first == 3'd2,
flitBuffers$notEmpty &&
IF_outPortFIFOs_first__8_EQ_0_9_THEN_simple_cr_ETC___d108 &&
outPortFIFOs$first == 3'd1,
flitBuffers$notEmpty &&
IF_outPortFIFOs_first__8_EQ_0_9_THEN_simple_cr_ETC___d108 &&
outPortFIFOs$first == 3'd0 } ;
assign routerAlloc$EN_allocate = 1'd1 ;
assign routerAlloc$EN_next = 1'd1 ;
// remaining internal signals
module_outport_encoder instance_outport_encoder_0(.outport_encoder_vec({ { 1'd1 &&
routerAlloc$allocate[9],
1'd1 &&
routerAlloc$allocate[8],
1'd1 &&
routerAlloc$allocate[7] },
1'd1 &&
routerAlloc$allocate[6],
1'd1 &&
routerAlloc$allocate[5] }),
.outport_encoder(outport_encoder___d831));
module_outport_encoder instance_outport_encoder_1(.outport_encoder_vec({ { 1'd1 &&
routerAlloc$allocate[4],
1'd1 &&
routerAlloc$allocate[3],
1'd1 &&
routerAlloc$allocate[2] },
1'd1 &&
routerAlloc$allocate[1],
1'd1 &&
routerAlloc$allocate[0] }),
.outport_encoder(outport_encoder___d832));
module_outport_encoder instance_outport_encoder_2(.outport_encoder_vec({ { 1'd1 &&
routerAlloc$allocate[14],
1'd1 &&
routerAlloc$allocate[13],
1'd1 &&
routerAlloc$allocate[12] },
1'd1 &&
routerAlloc$allocate[11],
1'd1 &&
routerAlloc$allocate[10] }),
.outport_encoder(outport_encoder___d830));
module_outport_encoder instance_outport_encoder_3(.outport_encoder_vec({ { 1'd1 &&
routerAlloc$allocate[19],
1'd1 &&
routerAlloc$allocate[18],
1'd1 &&
routerAlloc$allocate[17] },
1'd1 &&
routerAlloc$allocate[16],
1'd1 &&
routerAlloc$allocate[15] }),
.outport_encoder(outport_encoder___d829));
module_outport_encoder instance_outport_encoder_4(.outport_encoder_vec({ { 1'd1 &&
routerAlloc$allocate[24],
1'd1 &&
routerAlloc$allocate[23],
1'd1 &&
routerAlloc$allocate[22] },
1'd1 &&
routerAlloc$allocate[21],
1'd1 &&
routerAlloc$allocate[20] }),
.outport_encoder(outport_encoder___d828));
assign IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d347 =
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d811 ?
!outport_encoder___d829[3] ||
!hasFlitsToSend_perIn_3$wget[132] :
outport_encoder___d828[3] &&
outport_encoder___d828[2:0] == 3'd0 &&
!hasFlitsToSend_perIn_4$wget[132] ;
assign IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d348 =
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d810 ?
!outport_encoder___d830[3] ||
!hasFlitsToSend_perIn_2$wget[132] :
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d347 ;
assign IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d349 =
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d809 ?
!outport_encoder___d831[3] ||
!hasFlitsToSend_perIn_1$wget[132] :
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d348 ;
assign IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d360 =
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d811 ?
outport_encoder___d829[3] && hasFlitsToSend_perIn_3$wget[132] :
!outport_encoder___d828[3] ||
outport_encoder___d828[2:0] != 3'd0 ||
hasFlitsToSend_perIn_4$wget[132] ;
assign IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d361 =
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d810 ?
outport_encoder___d830[3] && hasFlitsToSend_perIn_2$wget[132] :
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d360 ;
assign IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d362 =
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d809 ?
outport_encoder___d831[3] && hasFlitsToSend_perIn_1$wget[132] :
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d361 ;
assign IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d363 =
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d792 ?
outport_encoder___d832[3] && hasFlitsToSend_perIn$wget[132] :
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d362 ;
assign IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d390 =
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d810 ?
hasFlitsToSend_perIn_2$wget[131:0] :
(IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d811 ?
hasFlitsToSend_perIn_3$wget[131:0] :
hasFlitsToSend_perIn_4$wget[131:0]) ;
assign IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d844 =
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d792 ?
hasFlitsToSend_perIn$wget[131:0] :
(IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d809 ?
hasFlitsToSend_perIn_1$wget[131:0] :
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d390) ;
assign IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d854 =
IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d792 ?
!outport_encoder___d832[3] || !hasFlitsToSend_perIn$wget[132] :
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d349 ;
assign IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d693 =
outport_encoder___d830[3] ?
((outport_encoder___d830[2:0] == 3'd1) ?
3'd2 :
IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d697) :
IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d697 ;
assign IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d694 =
outport_encoder___d830[3] ?
((outport_encoder___d830[2:0] == 3'd2) ?
outport_encoder___d830[2:0] :
IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d698) :
IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d698 ;
assign IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d695 =
outport_encoder___d830[3] ?
((outport_encoder___d830[2:0] == 3'd3) ?
3'd2 :
IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d699) :
IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d699 ;
assign IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d696 =
outport_encoder___d830[3] ?
((outport_encoder___d830[2:0] == 3'd4) ?
3'd2 :
IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d700) :
IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d700 ;
assign IF_outport_encoder_03_BIT_3_04_THEN_NOT_outpor_ETC___d654 =
outport_encoder___d830[3] ?
outport_encoder___d830[2:0] != 3'd0 &&
(!outport_encoder___d831[3] ||
outport_encoder___d831[2:0] != 3'd0) :
!outport_encoder___d831[3] ||
outport_encoder___d831[2:0] != 3'd0 ;
assign IF_outport_encoder_03_BIT_3_04_THEN_NOT_outpor_ETC___d668 =
outport_encoder___d830[3] ?
outport_encoder___d830[2:0] != 3'd0 &&
outport_encoder___d831[3] &&
outport_encoder___d831[2:0] == 3'd0 :
outport_encoder___d831[3] &&
outport_encoder___d831[2:0] == 3'd0 ;
assign IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d652 =
outport_encoder___d830[3] ?
outport_encoder___d830[2:0] == 3'd0 ||
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d651 :
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d651 ;
assign IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d656 =
outport_encoder___d830[3] ?
outport_encoder___d830[2:0] == 3'd1 ||
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d655 :
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d655 ;
assign IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d662 =
outport_encoder___d830[3] ?
outport_encoder___d830[2:0] == 3'd4 ||
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d686 :
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d686 ;
assign IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d669 =
outport_encoder___d830[3] ?
outport_encoder___d830[2:0] == 3'd3 ||
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d676 :
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d676 ;
assign IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d671 =
outport_encoder___d830[3] ?
outport_encoder___d830[2:0] == 3'd2 ||
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d684 :
IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d684 ;
assign IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d689 =
outport_encoder___d829[3] ?
((outport_encoder___d829[2:0] == 3'd1) ?
3'd3 :
IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d693) :
IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d693 ;
assign IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d690 =
outport_encoder___d829[3] ?
((outport_encoder___d829[2:0] == 3'd2) ?
3'd3 :
IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d694) :
IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d694 ;
assign IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d691 =
outport_encoder___d829[3] ?
((outport_encoder___d829[2:0] == 3'd3) ?
outport_encoder___d829[2:0] :
IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d695) :
IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d695 ;
assign IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d692 =
outport_encoder___d829[3] ?
((outport_encoder___d829[2:0] == 3'd4) ?
3'd3 :
IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d696) :
IF_outport_encoder_03_BIT_3_04_THEN_IF_outport_ETC___d696 ;
assign IF_outport_encoder_24_BIT_3_25_THEN_NOT_outpor_ETC___d653 =
outport_encoder___d829[3] ?
outport_encoder___d829[2:0] != 3'd0 &&
IF_outport_encoder_03_BIT_3_04_THEN_NOT_outpor_ETC___d654 :
IF_outport_encoder_03_BIT_3_04_THEN_NOT_outpor_ETC___d654 ;
assign IF_outport_encoder_24_BIT_3_25_THEN_NOT_outpor_ETC___d665 =
outport_encoder___d829[3] ?
outport_encoder___d829[2:0] != 3'd0 &&
IF_outport_encoder_03_BIT_3_04_THEN_NOT_outpor_ETC___d668 :
IF_outport_encoder_03_BIT_3_04_THEN_NOT_outpor_ETC___d668 ;
assign IF_outport_encoder_24_BIT_3_25_THEN_NOT_outpor_ETC___d667 =
outport_encoder___d829[3] ?
outport_encoder___d829[2:0] != 3'd0 &&
outport_encoder___d830[3] &&
outport_encoder___d830[2:0] == 3'd0 :
outport_encoder___d830[3] &&
outport_encoder___d830[2:0] == 3'd0 ;
assign IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d659 =
outport_encoder___d829[3] ?
outport_encoder___d829[2:0] == 3'd2 ||
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d671 :
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d671 ;
assign IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d663 =
outport_encoder___d829[3] ?
outport_encoder___d829[2:0] == 3'd4 ||
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d662 :
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d662 ;
assign IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d672 =
outport_encoder___d829[3] ?
outport_encoder___d829[2:0] == 3'd0 ||
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d652 :
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d652 ;
assign IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d683 =
outport_encoder___d829[3] ?
outport_encoder___d829[2:0] == 3'd1 ||
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d656 :
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d656 ;
assign IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d685 =
outport_encoder___d829[3] ?
outport_encoder___d829[2:0] == 3'd3 ||
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d669 :
IF_outport_encoder_03_BIT_3_04_THEN_outport_en_ETC___d669 ;
assign IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d792 =
outport_encoder___d828[3] ?
outport_encoder___d828[2:0] != 3'd0 &&
IF_outport_encoder_24_BIT_3_25_THEN_NOT_outpor_ETC___d653 :
IF_outport_encoder_24_BIT_3_25_THEN_NOT_outpor_ETC___d653 ;
assign IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d809 =
outport_encoder___d828[3] ?
outport_encoder___d828[2:0] != 3'd0 &&
IF_outport_encoder_24_BIT_3_25_THEN_NOT_outpor_ETC___d665 :
IF_outport_encoder_24_BIT_3_25_THEN_NOT_outpor_ETC___d665 ;
assign IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d810 =
outport_encoder___d828[3] ?
outport_encoder___d828[2:0] != 3'd0 &&
IF_outport_encoder_24_BIT_3_25_THEN_NOT_outpor_ETC___d667 :
IF_outport_encoder_24_BIT_3_25_THEN_NOT_outpor_ETC___d667 ;
assign IF_outport_encoder_45_BIT_3_46_THEN_NOT_outpor_ETC___d811 =
outport_encoder___d828[3] ?
outport_encoder___d828[2:0] != 3'd0 &&
outport_encoder___d829[3] &&
outport_encoder___d829[2:0] == 3'd0 :
outport_encoder___d829[3] &&
outport_encoder___d829[2:0] == 3'd0 ;
assign IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d791 =
outport_encoder___d828[3] ?
outport_encoder___d828[2:0] == 3'd0 ||
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d672 :
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d672 ;
assign IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d801 =
outport_encoder___d828[3] ?
outport_encoder___d828[2:0] == 3'd1 ||
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d683 :
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d683 ;
assign IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d803 =
outport_encoder___d828[3] ?
outport_encoder___d828[2:0] == 3'd2 ||
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d659 :
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d659 ;
assign IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d805 =
outport_encoder___d828[3] ?
outport_encoder___d828[2:0] == 3'd3 ||
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d685 :
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d685 ;
assign IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d807 =
outport_encoder___d828[3] ?
outport_encoder___d828[2:0] == 3'd4 ||
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d663 :
IF_outport_encoder_24_BIT_3_25_THEN_outport_en_ETC___d663 ;
assign IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d697 =
outport_encoder___d831[3] ?
((outport_encoder___d831[2:0] == 3'd1) ?
outport_encoder___d831[2:0] :
3'd0) :
3'd0 ;
assign IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d698 =
outport_encoder___d831[3] ?
((outport_encoder___d831[2:0] == 3'd2) ? 3'd1 : 3'd0) :
3'd0 ;
assign IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d699 =
outport_encoder___d831[3] ?
((outport_encoder___d831[2:0] == 3'd3) ? 3'd1 : 3'd0) :
3'd0 ;
assign IF_outport_encoder_82_BIT_3_83_THEN_IF_outport_ETC___d700 =
outport_encoder___d831[3] ?
((outport_encoder___d831[2:0] == 3'd4) ? 3'd1 : 3'd0) :
3'd0 ;
assign IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d651 =
outport_encoder___d831[3] ?
outport_encoder___d831[2:0] == 3'd0 ||
outport_encoder___d832[3] &&
outport_encoder___d832[2:0] == 3'd0 :
outport_encoder___d832[3] &&
outport_encoder___d832[2:0] == 3'd0 ;
assign IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d655 =
outport_encoder___d831[3] ?
outport_encoder___d831[2:0] == 3'd1 ||
outport_encoder___d832[3] &&
outport_encoder___d832[2:0] == 3'd1 :
outport_encoder___d832[3] &&
outport_encoder___d832[2:0] == 3'd1 ;
assign IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d676 =
outport_encoder___d831[3] ?
outport_encoder___d831[2:0] == 3'd3 ||
outport_encoder___d832[3] &&
outport_encoder___d832[2:0] == 3'd3 :
outport_encoder___d832[3] &&
outport_encoder___d832[2:0] == 3'd3 ;
assign IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d684 =
outport_encoder___d831[3] ?
outport_encoder___d831[2:0] == 3'd2 ||
outport_encoder___d832[3] &&
outport_encoder___d832[2:0] == 3'd2 :
outport_encoder___d832[3] &&
outport_encoder___d832[2:0] == 3'd2 ;
assign IF_outport_encoder_82_BIT_3_83_THEN_outport_en_ETC___d686 =
outport_encoder___d831[3] ?
outport_encoder___d831[2:0] == 3'd4 ||
outport_encoder___d832[3] &&
outport_encoder___d832[2:0] == 3'd4 :
outport_encoder___d832[3] &&
outport_encoder___d832[2:0] == 3'd4 ;
assign active_in__h35433 =
outport_encoder___d828[3] ?
((outport_encoder___d828[2:0] == 3'd1) ?
3'd4 :
IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d689) :
IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d689 ;
assign active_in__h36374 =
outport_encoder___d828[3] ?
((outport_encoder___d828[2:0] == 3'd2) ?
3'd4 :
IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d690) :
IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d690 ;
assign active_in__h37315 =
outport_encoder___d828[3] ?
((outport_encoder___d828[2:0] == 3'd3) ?
3'd4 :
IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d691) :
IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d691 ;
assign active_in__h38256 =
outport_encoder___d828[3] ?
((outport_encoder___d828[2:0] == 3'd4) ?
outport_encoder___d828[2:0] :
IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d692) :
IF_outport_encoder_24_BIT_3_25_THEN_IF_outport_ETC___d692 ;
always@(outPortFIFOs_4$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_4$first)
3'd0:
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d27 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d27 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d27 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d27 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_4_first_EQ_0_THEN_simple_credi_ETC___d27 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs_3$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_3$first)
3'd0:
IF_outPortFIFOs_3_first__7_EQ_0_8_THEN_simple__ETC___d47 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_3_first__7_EQ_0_8_THEN_simple__ETC___d47 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_3_first__7_EQ_0_8_THEN_simple__ETC___d47 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_3_first__7_EQ_0_8_THEN_simple__ETC___d47 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_3_first__7_EQ_0_8_THEN_simple__ETC___d47 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs_2$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_2$first)
3'd0:
IF_outPortFIFOs_2_first__7_EQ_0_8_THEN_simple__ETC___d67 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_2_first__7_EQ_0_8_THEN_simple__ETC___d67 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_2_first__7_EQ_0_8_THEN_simple__ETC___d67 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_2_first__7_EQ_0_8_THEN_simple__ETC___d67 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_2_first__7_EQ_0_8_THEN_simple__ETC___d67 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs_1$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs_1$first)
3'd0:
IF_outPortFIFOs_1_first__8_EQ_0_9_THEN_simple__ETC___d88 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_1_first__8_EQ_0_9_THEN_simple__ETC___d88 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_1_first__8_EQ_0_9_THEN_simple__ETC___d88 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_1_first__8_EQ_0_9_THEN_simple__ETC___d88 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_1_first__8_EQ_0_9_THEN_simple__ETC___d88 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(outPortFIFOs$first or
EN_out_ports_4_putNonFullVCs or
out_ports_4_putNonFullVCs_nonFullVCs or
EN_out_ports_0_putNonFullVCs or
out_ports_0_putNonFullVCs_nonFullVCs or
EN_out_ports_1_putNonFullVCs or
out_ports_1_putNonFullVCs_nonFullVCs or
EN_out_ports_2_putNonFullVCs or
out_ports_2_putNonFullVCs_nonFullVCs or
EN_out_ports_3_putNonFullVCs or
out_ports_3_putNonFullVCs_nonFullVCs)
begin
case (outPortFIFOs$first)
3'd0:
IF_outPortFIFOs_first__8_EQ_0_9_THEN_simple_cr_ETC___d108 =
EN_out_ports_0_putNonFullVCs &&
out_ports_0_putNonFullVCs_nonFullVCs[0];
3'd1:
IF_outPortFIFOs_first__8_EQ_0_9_THEN_simple_cr_ETC___d108 =
EN_out_ports_1_putNonFullVCs &&
out_ports_1_putNonFullVCs_nonFullVCs[0];
3'd2:
IF_outPortFIFOs_first__8_EQ_0_9_THEN_simple_cr_ETC___d108 =
EN_out_ports_2_putNonFullVCs &&
out_ports_2_putNonFullVCs_nonFullVCs[0];
3'd3:
IF_outPortFIFOs_first__8_EQ_0_9_THEN_simple_cr_ETC___d108 =
EN_out_ports_3_putNonFullVCs &&
out_ports_3_putNonFullVCs_nonFullVCs[0];
default: IF_outPortFIFOs_first__8_EQ_0_9_THEN_simple_cr_ETC___d108 =
EN_out_ports_4_putNonFullVCs &&
out_ports_4_putNonFullVCs_nonFullVCs[0];
endcase
end
always@(active_in__h35433 or
outport_encoder___d828 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d832 or
hasFlitsToSend_perIn$wget or
outport_encoder___d831 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d830 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d829 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h35433)
3'd0:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d433 =
outport_encoder___d832[3] && hasFlitsToSend_perIn$wget[132];
3'd1:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d433 =
outport_encoder___d831[3] && hasFlitsToSend_perIn_1$wget[132];
3'd2:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d433 =
outport_encoder___d830[3] && hasFlitsToSend_perIn_2$wget[132];
3'd3:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d433 =
outport_encoder___d829[3] && hasFlitsToSend_perIn_3$wget[132];
default: IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d433 =
active_in__h35433 != 3'd4 ||
outport_encoder___d828[3] &&
hasFlitsToSend_perIn_4$wget[132];
endcase
end
always@(active_in__h36374 or
outport_encoder___d828 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d832 or
hasFlitsToSend_perIn$wget or
outport_encoder___d831 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d830 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d829 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h36374)
3'd0:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d495 =
outport_encoder___d832[3] && hasFlitsToSend_perIn$wget[132];
3'd1:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d495 =
outport_encoder___d831[3] && hasFlitsToSend_perIn_1$wget[132];
3'd2:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d495 =
outport_encoder___d830[3] && hasFlitsToSend_perIn_2$wget[132];
3'd3:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d495 =
outport_encoder___d829[3] && hasFlitsToSend_perIn_3$wget[132];
default: IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d495 =
active_in__h36374 != 3'd4 ||
outport_encoder___d828[3] &&
hasFlitsToSend_perIn_4$wget[132];
endcase
end
always@(active_in__h37315 or
outport_encoder___d828 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d832 or
hasFlitsToSend_perIn$wget or
outport_encoder___d831 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d830 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d829 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h37315)
3'd0:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d557 =
outport_encoder___d832[3] && hasFlitsToSend_perIn$wget[132];
3'd1:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d557 =
outport_encoder___d831[3] && hasFlitsToSend_perIn_1$wget[132];
3'd2:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d557 =
outport_encoder___d830[3] && hasFlitsToSend_perIn_2$wget[132];
3'd3:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d557 =
outport_encoder___d829[3] && hasFlitsToSend_perIn_3$wget[132];
default: IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d557 =
active_in__h37315 != 3'd4 ||
outport_encoder___d828[3] &&
hasFlitsToSend_perIn_4$wget[132];
endcase
end
always@(active_in__h38256 or
outport_encoder___d828 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d832 or
hasFlitsToSend_perIn$wget or
outport_encoder___d831 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d830 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d829 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h38256)
3'd0:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d619 =
outport_encoder___d832[3] && hasFlitsToSend_perIn$wget[132];
3'd1:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d619 =
outport_encoder___d831[3] && hasFlitsToSend_perIn_1$wget[132];
3'd2:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d619 =
outport_encoder___d830[3] && hasFlitsToSend_perIn_2$wget[132];
3'd3:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d619 =
outport_encoder___d829[3] && hasFlitsToSend_perIn_3$wget[132];
default: IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d619 =
active_in__h38256 != 3'd4 ||
outport_encoder___d828[3] &&
hasFlitsToSend_perIn_4$wget[132];
endcase
end
always@(active_in__h35433 or
outport_encoder___d828 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d832 or
hasFlitsToSend_perIn$wget or
outport_encoder___d831 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d830 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d829 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h35433)
3'd0:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d855 =
!outport_encoder___d832[3] || !hasFlitsToSend_perIn$wget[132];
3'd1:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d855 =
!outport_encoder___d831[3] || !hasFlitsToSend_perIn_1$wget[132];
3'd2:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d855 =
!outport_encoder___d830[3] || !hasFlitsToSend_perIn_2$wget[132];
3'd3:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d855 =
!outport_encoder___d829[3] || !hasFlitsToSend_perIn_3$wget[132];
default: IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d855 =
active_in__h35433 == 3'd4 &&
(!outport_encoder___d828[3] ||
!hasFlitsToSend_perIn_4$wget[132]);
endcase
end
always@(active_in__h36374 or
outport_encoder___d828 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d832 or
hasFlitsToSend_perIn$wget or
outport_encoder___d831 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d830 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d829 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h36374)
3'd0:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d856 =
!outport_encoder___d832[3] || !hasFlitsToSend_perIn$wget[132];
3'd1:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d856 =
!outport_encoder___d831[3] || !hasFlitsToSend_perIn_1$wget[132];
3'd2:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d856 =
!outport_encoder___d830[3] || !hasFlitsToSend_perIn_2$wget[132];
3'd3:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d856 =
!outport_encoder___d829[3] || !hasFlitsToSend_perIn_3$wget[132];
default: IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d856 =
active_in__h36374 == 3'd4 &&
(!outport_encoder___d828[3] ||
!hasFlitsToSend_perIn_4$wget[132]);
endcase
end
always@(active_in__h37315 or
outport_encoder___d828 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d832 or
hasFlitsToSend_perIn$wget or
outport_encoder___d831 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d830 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d829 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h37315)
3'd0:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d857 =
!outport_encoder___d832[3] || !hasFlitsToSend_perIn$wget[132];
3'd1:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d857 =
!outport_encoder___d831[3] || !hasFlitsToSend_perIn_1$wget[132];
3'd2:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d857 =
!outport_encoder___d830[3] || !hasFlitsToSend_perIn_2$wget[132];
3'd3:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d857 =
!outport_encoder___d829[3] || !hasFlitsToSend_perIn_3$wget[132];
default: IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d857 =
active_in__h37315 == 3'd4 &&
(!outport_encoder___d828[3] ||
!hasFlitsToSend_perIn_4$wget[132]);
endcase
end
always@(active_in__h38256 or
outport_encoder___d828 or
hasFlitsToSend_perIn_4$wget or
outport_encoder___d832 or
hasFlitsToSend_perIn$wget or
outport_encoder___d831 or
hasFlitsToSend_perIn_1$wget or
outport_encoder___d830 or
hasFlitsToSend_perIn_2$wget or
outport_encoder___d829 or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h38256)
3'd0:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d858 =
!outport_encoder___d832[3] || !hasFlitsToSend_perIn$wget[132];
3'd1:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d858 =
!outport_encoder___d831[3] || !hasFlitsToSend_perIn_1$wget[132];
3'd2:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d858 =
!outport_encoder___d830[3] || !hasFlitsToSend_perIn_2$wget[132];
3'd3:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d858 =
!outport_encoder___d829[3] || !hasFlitsToSend_perIn_3$wget[132];
default: IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d858 =
active_in__h38256 == 3'd4 &&
(!outport_encoder___d828[3] ||
!hasFlitsToSend_perIn_4$wget[132]);
endcase
end
always@(active_in__h35433 or
hasFlitsToSend_perIn_4$wget or
hasFlitsToSend_perIn$wget or
hasFlitsToSend_perIn_1$wget or
hasFlitsToSend_perIn_2$wget or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h35433)
3'd0:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d845 =
hasFlitsToSend_perIn$wget[131:0];
3'd1:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d845 =
hasFlitsToSend_perIn_1$wget[131:0];
3'd2:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d845 =
hasFlitsToSend_perIn_2$wget[131:0];
3'd3:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d845 =
hasFlitsToSend_perIn_3$wget[131:0];
3'd4:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d845 =
hasFlitsToSend_perIn_4$wget[131:0];
default: IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d845 =
hasFlitsToSend_perIn_4$wget[131:0];
endcase
end
always@(active_in__h36374 or
hasFlitsToSend_perIn_4$wget or
hasFlitsToSend_perIn$wget or
hasFlitsToSend_perIn_1$wget or
hasFlitsToSend_perIn_2$wget or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h36374)
3'd0:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d846 =
hasFlitsToSend_perIn$wget[131:0];
3'd1:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d846 =
hasFlitsToSend_perIn_1$wget[131:0];
3'd2:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d846 =
hasFlitsToSend_perIn_2$wget[131:0];
3'd3:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d846 =
hasFlitsToSend_perIn_3$wget[131:0];
3'd4:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d846 =
hasFlitsToSend_perIn_4$wget[131:0];
default: IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d846 =
hasFlitsToSend_perIn_4$wget[131:0];
endcase
end
always@(active_in__h37315 or
hasFlitsToSend_perIn_4$wget or
hasFlitsToSend_perIn$wget or
hasFlitsToSend_perIn_1$wget or
hasFlitsToSend_perIn_2$wget or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h37315)
3'd0:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d847 =
hasFlitsToSend_perIn$wget[131:0];
3'd1:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d847 =
hasFlitsToSend_perIn_1$wget[131:0];
3'd2:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d847 =
hasFlitsToSend_perIn_2$wget[131:0];
3'd3:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d847 =
hasFlitsToSend_perIn_3$wget[131:0];
3'd4:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d847 =
hasFlitsToSend_perIn_4$wget[131:0];
default: IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d847 =
hasFlitsToSend_perIn_4$wget[131:0];
endcase
end
always@(active_in__h38256 or
hasFlitsToSend_perIn_4$wget or
hasFlitsToSend_perIn$wget or
hasFlitsToSend_perIn_1$wget or
hasFlitsToSend_perIn_2$wget or hasFlitsToSend_perIn_3$wget)
begin
case (active_in__h38256)
3'd0:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d848 =
hasFlitsToSend_perIn$wget[131:0];
3'd1:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d848 =
hasFlitsToSend_perIn_1$wget[131:0];
3'd2:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d848 =
hasFlitsToSend_perIn_2$wget[131:0];
3'd3:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d848 =
hasFlitsToSend_perIn_3$wget[131:0];
3'd4:
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d848 =
hasFlitsToSend_perIn_4$wget[131:0];
default: IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d848 =
hasFlitsToSend_perIn_4$wget[131:0];
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
inPortVL <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_2 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_3 <= `BSV_ASSIGNMENT_DELAY 3'd0;
inPortVL_4 <= `BSV_ASSIGNMENT_DELAY 3'd0;
lockedVL <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
lockedVL_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_2_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_2_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_2_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_2_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_3_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_3_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_3_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_3_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_4_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_4_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_4_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
selectedIO_reg_4_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (inPortVL$EN) inPortVL <= `BSV_ASSIGNMENT_DELAY inPortVL$D_IN;
if (inPortVL_1$EN)
inPortVL_1 <= `BSV_ASSIGNMENT_DELAY inPortVL_1$D_IN;
if (inPortVL_2$EN)
inPortVL_2 <= `BSV_ASSIGNMENT_DELAY inPortVL_2$D_IN;
if (inPortVL_3$EN)
inPortVL_3 <= `BSV_ASSIGNMENT_DELAY inPortVL_3$D_IN;
if (inPortVL_4$EN)
inPortVL_4 <= `BSV_ASSIGNMENT_DELAY inPortVL_4$D_IN;
if (lockedVL$EN) lockedVL <= `BSV_ASSIGNMENT_DELAY lockedVL$D_IN;
if (lockedVL_1$EN)
lockedVL_1 <= `BSV_ASSIGNMENT_DELAY lockedVL_1$D_IN;
if (lockedVL_2$EN)
lockedVL_2 <= `BSV_ASSIGNMENT_DELAY lockedVL_2$D_IN;
if (lockedVL_3$EN)
lockedVL_3 <= `BSV_ASSIGNMENT_DELAY lockedVL_3$D_IN;
if (lockedVL_4$EN)
lockedVL_4 <= `BSV_ASSIGNMENT_DELAY lockedVL_4$D_IN;
if (selectedIO_reg_0$EN)
selectedIO_reg_0 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_0$D_IN;
if (selectedIO_reg_0_1$EN)
selectedIO_reg_0_1 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_0_1$D_IN;
if (selectedIO_reg_0_2$EN)
selectedIO_reg_0_2 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_0_2$D_IN;
if (selectedIO_reg_0_3$EN)
selectedIO_reg_0_3 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_0_3$D_IN;
if (selectedIO_reg_0_4$EN)
selectedIO_reg_0_4 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_0_4$D_IN;
if (selectedIO_reg_1$EN)
selectedIO_reg_1 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_1$D_IN;
if (selectedIO_reg_1_1$EN)
selectedIO_reg_1_1 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_1_1$D_IN;
if (selectedIO_reg_1_2$EN)
selectedIO_reg_1_2 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_1_2$D_IN;
if (selectedIO_reg_1_3$EN)
selectedIO_reg_1_3 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_1_3$D_IN;
if (selectedIO_reg_1_4$EN)
selectedIO_reg_1_4 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_1_4$D_IN;
if (selectedIO_reg_2$EN)
selectedIO_reg_2 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_2$D_IN;
if (selectedIO_reg_2_1$EN)
selectedIO_reg_2_1 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_2_1$D_IN;
if (selectedIO_reg_2_2$EN)
selectedIO_reg_2_2 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_2_2$D_IN;
if (selectedIO_reg_2_3$EN)
selectedIO_reg_2_3 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_2_3$D_IN;
if (selectedIO_reg_2_4$EN)
selectedIO_reg_2_4 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_2_4$D_IN;
if (selectedIO_reg_3$EN)
selectedIO_reg_3 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_3$D_IN;
if (selectedIO_reg_3_1$EN)
selectedIO_reg_3_1 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_3_1$D_IN;
if (selectedIO_reg_3_2$EN)
selectedIO_reg_3_2 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_3_2$D_IN;
if (selectedIO_reg_3_3$EN)
selectedIO_reg_3_3 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_3_3$D_IN;
if (selectedIO_reg_3_4$EN)
selectedIO_reg_3_4 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_3_4$D_IN;
if (selectedIO_reg_4$EN)
selectedIO_reg_4 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_4$D_IN;
if (selectedIO_reg_4_1$EN)
selectedIO_reg_4_1 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_4_1$D_IN;
if (selectedIO_reg_4_2$EN)
selectedIO_reg_4_2 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_4_2$D_IN;
if (selectedIO_reg_4_3$EN)
selectedIO_reg_4_3 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_4_3$D_IN;
if (selectedIO_reg_4_4$EN)
selectedIO_reg_4_4 <= `BSV_ASSIGNMENT_DELAY selectedIO_reg_4_4$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
inPortVL = 3'h2;
inPortVL_1 = 3'h2;
inPortVL_2 = 3'h2;
inPortVL_3 = 3'h2;
inPortVL_4 = 3'h2;
lockedVL = 1'h0;
lockedVL_1 = 1'h0;
lockedVL_2 = 1'h0;
lockedVL_3 = 1'h0;
lockedVL_4 = 1'h0;
selectedIO_reg_0 = 1'h0;
selectedIO_reg_0_1 = 1'h0;
selectedIO_reg_0_2 = 1'h0;
selectedIO_reg_0_3 = 1'h0;
selectedIO_reg_0_4 = 1'h0;
selectedIO_reg_1 = 1'h0;
selectedIO_reg_1_1 = 1'h0;
selectedIO_reg_1_2 = 1'h0;
selectedIO_reg_1_3 = 1'h0;
selectedIO_reg_1_4 = 1'h0;
selectedIO_reg_2 = 1'h0;
selectedIO_reg_2_1 = 1'h0;
selectedIO_reg_2_2 = 1'h0;
selectedIO_reg_2_3 = 1'h0;
selectedIO_reg_2_4 = 1'h0;
selectedIO_reg_3 = 1'h0;
selectedIO_reg_3_1 = 1'h0;
selectedIO_reg_3_2 = 1'h0;
selectedIO_reg_3_3 = 1'h0;
selectedIO_reg_3_4 = 1'h0;
selectedIO_reg_4 = 1'h0;
selectedIO_reg_4_1 = 1'h0;
selectedIO_reg_4_2 = 1'h0;
selectedIO_reg_4_3 = 1'h0;
selectedIO_reg_4_4 = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N) if (EN_out_ports_0_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_0_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_1_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_1_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_2_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_2_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_3_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_3_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_4_putNonFullVCs) $write("");
if (RST_N) if (EN_out_ports_4_putNonFullVCs) $write("");
if (RST_N)
if (EN_out_ports_0_getFlit &&
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d791 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d854)
$display("Dynamic assertion failed: \"IQRouterSimple.bsv\", line 619, column 47\nOutput selected invalid flit!");
if (RST_N)
if (EN_out_ports_0_getFlit &&
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d791 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_NOT_out_ETC___d854)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_1_getFlit &&
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d801 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d855)
$display("Dynamic assertion failed: \"IQRouterSimple.bsv\", line 619, column 47\nOutput selected invalid flit!");
if (RST_N)
if (EN_out_ports_1_getFlit &&
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d801 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d855)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_2_getFlit &&
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d803 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d856)
$display("Dynamic assertion failed: \"IQRouterSimple.bsv\", line 619, column 47\nOutput selected invalid flit!");
if (RST_N)
if (EN_out_ports_2_getFlit &&
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d803 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d856)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_3_getFlit &&
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d805 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d857)
$display("Dynamic assertion failed: \"IQRouterSimple.bsv\", line 619, column 47\nOutput selected invalid flit!");
if (RST_N)
if (EN_out_ports_3_getFlit &&
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d805 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d857)
$finish(32'd0);
if (RST_N)
if (EN_out_ports_4_getFlit &&
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d807 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d858)
$display("Dynamic assertion failed: \"IQRouterSimple.bsv\", line 619, column 47\nOutput selected invalid flit!");
if (RST_N)
if (EN_out_ports_4_getFlit &&
IF_outport_encoder_45_BIT_3_46_THEN_outport_en_ETC___d807 &&
IF_IF_outport_encoder_45_BIT_3_46_THEN_IF_outp_ETC___d858)
$finish(32'd0);
end
// synopsys translate_on
endmodule // mkIQRouterCoreSimple
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module dcache_core_data_ram
(
// Inputs
input clk0_i
,input rst0_i
,input [ 10:0] addr0_i
,input [ 31:0] data0_i
,input [ 3:0] wr0_i
,input clk1_i
,input rst1_i
,input [ 10:0] addr1_i
,input [ 31:0] data1_i
,input [ 3:0] wr1_i
// Outputs
,output [ 31:0] data0_o
,output [ 31:0] data1_o
);
//-----------------------------------------------------------------
// Dual Port RAM 8KB
// Mode: Read First
//-----------------------------------------------------------------
/* verilator lint_off MULTIDRIVEN */
reg [31:0] ram [2047:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;
// Synchronous write
always @ (posedge clk0_i)
begin
if (wr0_i[0])
ram[addr0_i][7:0] <= data0_i[7:0];
if (wr0_i[1])
ram[addr0_i][15:8] <= data0_i[15:8];
if (wr0_i[2])
ram[addr0_i][23:16] <= data0_i[23:16];
if (wr0_i[3])
ram[addr0_i][31:24] <= data0_i[31:24];
ram_read0_q <= ram[addr0_i];
end
always @ (posedge clk1_i)
begin
if (wr1_i[0])
ram[addr1_i][7:0] <= data1_i[7:0];
if (wr1_i[1])
ram[addr1_i][15:8] <= data1_i[15:8];
if (wr1_i[2])
ram[addr1_i][23:16] <= data1_i[23:16];
if (wr1_i[3])
ram[addr1_i][31:24] <= data1_i[31:24];
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule
|
`timescale 1 ns / 1 ps
module scale_1d #
(
parameter integer C_M_WIDTH = 12,
parameter integer C_S_WIDTH = 10,
parameter integer C_S_ADDR_WIDTH = 32
)
(
input wire clk,
input wire resetn,
input wire [C_S_WIDTH-1:0] s_width,
input wire [C_M_WIDTH-1:0] m_width,
input wire start,
output wire o_valid,
output wire [C_S_WIDTH-1:0] s_index,
output wire [C_M_WIDTH-1:0] m_index,
output wire o_last,
input wire o_ready,
input wire [C_S_ADDR_WIDTH-1:0] s_base_addr,
input wire [C_S_ADDR_WIDTH-1:0] s_off_addr,
input wire [C_S_ADDR_WIDTH-1:0] s_inc_addr,
output reg [C_S_ADDR_WIDTH-1:0] s_addr
);
localparam integer C_CNT_WIDTH = C_M_WIDTH + C_S_WIDTH;
wire progress;
assign progress = ~o_valid || o_ready;
wire next;
assign next = o_valid && o_ready;
reg [C_CNT_WIDTH-1 : 0] s_cnt;
reg [C_CNT_WIDTH-1 : 0] m_cnt;
reg [C_S_WIDTH-1 : 0] s_idx;
assign s_index = s_idx;
reg [C_M_WIDTH-1 : 0] m_idx;
assign m_index = m_idx;
reg running;
always @(posedge clk) begin
if (resetn == 0) begin
running <= 0;
end
else if (start) begin
running <= 1;
end
else if (next && m_idx == m_width - 1) begin
running <= 0;
end
end
assign o_valid = (running && s_cnt >= m_cnt);
always @(posedge clk) begin
if (resetn == 0) begin
s_cnt <= 0;
s_idx <= 0;
s_addr <= 0;
m_cnt <= 0;
m_idx <= 0;
end
else if (start) begin
s_cnt <= m_width;
s_idx <= 0;
s_addr <= s_base_addr + s_off_addr;
m_cnt <= s_width;
m_idx <= 0;
end
else if (running) begin
if (progress) begin
if (s_cnt <= m_cnt) begin
s_cnt <= s_cnt + m_width;
s_idx <= s_idx + 1;
s_addr <= s_addr + s_inc_addr;
end
if (s_cnt >= m_cnt) begin
m_cnt <= m_cnt + s_width;
m_idx <= m_idx + 1;
end
end
end
end
reg last;
assign o_last = last;
always @(posedge clk) begin
if (resetn == 0) begin
last <= 0;
end
else if (start) begin
last <= 0;
end
else if (next && m_idx == m_width - 2) begin
last <= 1;
end
end
endmodule
|
//
// Designed by Qiang Wu
// 16K bytes, 32bit interface
`timescale 1ns/1ps
module nexthop(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [13:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
RAMB16_S4 localram0(
.DO (data_out[3:0]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[3:0]),
.EN (en),
.SSR (reset),
.WE (we[0])
);
defparam localram0.INIT_00 = 256'h0000000000000000000000000000000000000000000000011111111111111111;
defparam localram0.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram1(
.DO (data_out[7:4]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[7:4]),
.EN (en),
.SSR (reset),
.WE (we[0])
);
defparam localram1.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram2(
.DO (data_out[11:8]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[11:8]),
.EN (en),
.SSR (reset),
.WE (we[1])
);
defparam localram2.INIT_00 = 256'h0000000000000000000000000000000000000000000000044C00C404CC488000;
defparam localram2.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram3(
.DO (data_out[15:12]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[15:12]),
.EN (en),
.SSR (reset),
.WE (we[1])
);
defparam localram3.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram4(
.DO (data_out[19:16]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[19:16]),
.EN (en),
.SSR (reset),
.WE (we[2])
);
defparam localram4.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram5(
.DO (data_out[23:20]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[23:20]),
.EN (en),
.SSR (reset),
.WE (we[2])
);
defparam localram5.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram6(
.DO (data_out[27:24]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[27:24]),
.EN (en),
.SSR (reset),
.WE (we[3])
);
defparam localram6.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram7(
.DO (data_out[31:28]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[31:28]),
.EN (en),
.SSR (reset),
.WE (we[3])
);
defparam localram7.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
endmodule
|
`default_nettype none
`timescale 1ns / 1ns
module tb;
reg clk, clk_pll, resetn = 0;
wire Pulse, Sync, Block, RS232_Rx, RS232_Tx;
// wire J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10;
// wire J4_3, J4_4, J4_5, J4_6, J4_7, J4_8, J4_9;
pulse_gen test(
.clk(clk),
.clk_pll(clk_pll),
.RS232_Rx(RS232_Rx),
.RS232_Tx(RS232_Tx),
// .resetn(resetn),
.Pulse(Pulse),
.Sync(Sync),
.Block(Block)
// .J1_4(J1_4),
// .J1_5(J1_5),
// .J1_6(J1_6),
// .J1_7(J1_7),
// .J1_8(J1_8),
// .J1_9(J1_9),
// .J1_10(J1_10),
// .J4_3(J4_3),
// .J4_4(J4_4),
// .J4_5(J4_5),
// .J4_6(J4_6),
// .J4_7(J4_7),
// .J4_8(J4_8),
// .J4_9(J4_9)
);
initial begin
$dumpfile("Sim/pulse_gen_sim_tb.vcd");
// $dumpvars(0, test);
$dumpvars(1, Pulse, Sync, Block);
clk = 1'b0;
clk_pll = 1'b1;
// #1 resetn = 1;
// #50 resetn = 0;
// #150000 P1 = 1;
// #1500000 P1 = 0;
#5000000 $finish;
// #35000000 $finish;
end
always begin
#4.975 clk_pll <= ~clk_pll;
end
always begin
#41.667 clk <= ~clk;
end
endmodule // tb
|
(* *********************************************************************)
(* *)
(* The Compcert verified compiler *)
(* *)
(* Xavier Leroy, INRIA Paris-Rocquencourt *)
(* *)
(* Copyright Institut National de Recherche en Informatique et en *)
(* Automatique. All rights reserved. This file is distributed *)
(* under the terms of the INRIA Non-Commercial License Agreement. *)
(* *)
(* *********************************************************************)
(** Bounded and unbounded iterators *)
Require Import Axioms.
Require Import Coqlib.
Require Import Wfsimpl.
(** This modules defines several Coq encodings of a general "while" loop.
The loop is presented in functional style as the iteration
of a [step] function of type [A -> B + A]:
<<
let rec iterate step a =
match step a with
| inl b -> b
| inr a' -> iterate step a'
>>
This iteration cannot be defined directly in Coq using [Fixpoint],
because Coq is a logic of total functions, and therefore we must
guarantee termination of the loop.
*)
(** * Terminating iteration *)
(** We first implement the case where termination is guaranteed because
the current state [a] decreases at each iteration. *)
Module WfIter.
Section ITERATION.
Variables A B: Type.
Variable step: A -> B + A.
Variable ord: A -> A -> Prop.
Hypothesis ord_wf: well_founded ord.
Hypothesis step_decr: forall a a', step a = inr _ a' -> ord a' a.
Definition step_info (a: A) : {b | step a = inl _ b} + {a' | step a = inr _ a' & ord a' a}.
Proof.
caseEq (step a); intros. left; exists b; auto. right; exists a0; auto.
Defined.
Definition iterate_F (a: A) (rec: forall a', ord a' a -> B) : B :=
match step_info a with
| inl (exist b P) => b
| inr (exist2 a' P Q) => rec a' Q
end.
Definition iterate (a: A) : B := Fix ord_wf iterate_F a.
(** We now prove an invariance property [iterate_prop], similar to the Hoare
logic rule for "while" loops. *)
Variable P: A -> Prop.
Variable Q: B -> Prop.
Hypothesis step_prop:
forall a : A, P a ->
match step a with inl b => Q b | inr a' => P a' end.
Lemma iterate_prop:
forall a, P a -> Q (iterate a).
Proof.
intros a0. pattern a0. apply well_founded_ind with (R := ord). auto.
intros. unfold iterate; rewrite unroll_Fix. unfold iterate_F.
destruct (step_info x) as [[b U] | [a' U V]].
exploit step_prop; eauto. rewrite U; auto.
apply H. auto. exploit step_prop; eauto. rewrite U; auto.
Qed.
End ITERATION.
End WfIter.
(** * Bounded iteration *)
(** The presentation of iteration shown above is predicated on the existence
of a well-founded ordering that decreases at each step of the iteration.
In several parts of the CompCert development, it is very painful to define
such a well-founded ordering and to prove decrease, even though we know our
iterations always terminate.
In the presentation below, we choose instead to bound the number of iterations
by an arbitrary constant. [iterate] then becomes a function that can fail,
of type [A -> option B]. The [None] result denotes failure to reach
a result in the number of iterations prescribed, or, in other terms,
failure to find a solution to the dataflow problem. The compiler
passes that exploit dataflow analysis (the [Constprop], [CSE] and
[Allocation] passes) will, in this case, either fail ([Allocation])
or turn off the optimization pass ([Constprop] and [CSE]).
Since we know (informally) that our computations terminate, we can
take a very large constant as the maximal number of iterations.
Failure will therefore never happen in practice, but of
course our proofs also cover the failure case and show that
nothing bad happens in this hypothetical case either. *)
Module PrimIter.
Section ITERATION.
Variables A B: Type.
Variable step: A -> B + A.
Definition num_iterations := 1000000000000%positive.
(** The simple definition of bounded iteration is:
<<
Fixpoint iterate (niter: nat) (a: A) {struct niter} : option B :=
match niter with
| O => None
| S niter' =>
match step a with
| inl b => b
| inr a' => iterate niter' a'
end
end.
>>
This function is structural recursive over the parameter [niter]
(number of iterations), represented here as a Peano integer (type [nat]).
However, we want to use very large values of [niter]. As Peano integers,
these values would be much too large to fit in memory. Therefore,
we must express iteration counts as a binary integer (type [positive]).
However, Peano induction over type [positive] is not structural recursion,
so we cannot define [iterate] as a Coq fixpoint and must use
Noetherian recursion instead. *)
Definition iter_step (x: positive)
(next: forall y, Plt y x -> A -> option B)
(s: A) : option B :=
match peq x xH with
| left EQ => None
| right NOTEQ =>
match step s with
| inl res => Some res
| inr s' => next (Ppred x) (Ppred_Plt x NOTEQ) s'
end
end.
Definition iter: positive -> A -> option B := Fix Plt_wf iter_step.
(** The [iterate] function is defined as [iter] up to
[num_iterations] through the loop. *)
Definition iterate := iter num_iterations.
(** We now prove the invariance property [iterate_prop]. *)
Variable P: A -> Prop.
Variable Q: B -> Prop.
Hypothesis step_prop:
forall a : A, P a ->
match step a with inl b => Q b | inr a' => P a' end.
Lemma iter_prop:
forall n a b, P a -> iter n a = Some b -> Q b.
Proof.
apply (well_founded_ind Plt_wf
(fun p => forall a b, P a -> iter p a = Some b -> Q b)).
intros. unfold iter in H1. rewrite unroll_Fix in H1. unfold iter_step in H1.
destruct (peq x 1). discriminate.
specialize (step_prop a H0).
destruct (step a) as [b'|a'] eqn:?.
inv H1. auto.
apply H with (Ppred x) a'. apply Ppred_Plt; auto. auto. auto.
Qed.
Lemma iterate_prop:
forall a b, iterate a = Some b -> P a -> Q b.
Proof.
intros. apply iter_prop with num_iterations a; assumption.
Qed.
End ITERATION.
End PrimIter.
(** * General iteration *)
(* An implementation using classical logic and unbounded iteration,
in the style of Yves Bertot's paper, "Extending the Calculus
of Constructions with Tarski's fix-point theorem".
As in the bounded case, the [iterate] function returns an option type.
[None] means that iteration does not terminate.
[Some b] means that iteration terminates with the result [b]. *)
Require Import Classical.
Require Import ClassicalDescription.
Require Import Max.
Module GenIter.
Section ITERATION.
Variables A B: Type.
Variable step: A -> B + A.
Definition B_le (x y: option B) : Prop := x = None \/ y = x.
Definition F_le (x y: A -> option B) : Prop := forall a, B_le (x a) (y a).
Definition F_iter (next: A -> option B) (a: A) : option B :=
match step a with
| inl b => Some b
| inr a' => next a'
end.
Lemma F_iter_monot:
forall f g, F_le f g -> F_le (F_iter f) (F_iter g).
Proof.
intros; red; intros. unfold F_iter.
destruct (step a) as [b | a']. red; auto. apply H.
Qed.
Fixpoint iter (n: nat) : A -> option B :=
match n with
| O => (fun a => None)
| S m => F_iter (iter m)
end.
Lemma iter_monot:
forall p q, (p <= q)%nat -> F_le (iter p) (iter q).
Proof.
induction p; intros.
simpl. red; intros; red; auto.
destruct q. elimtype False; omega.
simpl. apply F_iter_monot. apply IHp. omega.
Qed.
Lemma iter_either:
forall a,
(exists n, exists b, iter n a = Some b) \/
(forall n, iter n a = None).
Proof.
intro a. elim (classic (forall n, iter n a = None)); intro.
right; assumption.
left. generalize (not_all_ex_not nat (fun n => iter n a = None) H).
intros [n D]. exists n. generalize D.
case (iter n a); intros. exists b; auto. congruence.
Qed.
Definition converges_to (a: A) (b: option B) : Prop :=
exists n, forall m, (n <= m)%nat -> iter m a = b.
Lemma converges_to_Some:
forall a n b, iter n a = Some b -> converges_to a (Some b).
Proof.
intros. exists n. intros.
assert (B_le (iter n a) (iter m a)). apply iter_monot. auto.
elim H1; intro; congruence.
Qed.
Lemma converges_to_exists:
forall a, exists b, converges_to a b.
Proof.
intros. elim (iter_either a).
intros [n [b EQ]]. exists (Some b). apply converges_to_Some with n. assumption.
intro. exists (@None B). exists O. intros. auto.
Qed.
Lemma converges_to_unique:
forall a b, converges_to a b -> forall b', converges_to a b' -> b = b'.
Proof.
intros a b [n C] b' [n' C'].
rewrite <- (C (max n n')). rewrite <- (C' (max n n')). auto.
apply le_max_r. apply le_max_l.
Qed.
Lemma converges_to_exists_uniquely:
forall a, exists! b, converges_to a b .
Proof.
intro. destruct (converges_to_exists a) as [b CT].
exists b. split. assumption. exact (converges_to_unique _ _ CT).
Qed.
Definition iterate (a: A) : option B :=
proj1_sig (constructive_definite_description (converges_to a) (converges_to_exists_uniquely a)).
Lemma converges_to_iterate:
forall a b, converges_to a b -> iterate a = b.
Proof.
intros. unfold iterate.
destruct (constructive_definite_description (converges_to a) (converges_to_exists_uniquely a)) as [b' P].
simpl. apply converges_to_unique with a; auto.
Qed.
Lemma iterate_converges_to:
forall a, converges_to a (iterate a).
Proof.
intros. unfold iterate.
destruct (constructive_definite_description (converges_to a) (converges_to_exists_uniquely a)) as [b' P].
simpl; auto.
Qed.
(** Invariance property. *)
Variable P: A -> Prop.
Variable Q: B -> Prop.
Hypothesis step_prop:
forall a : A, P a ->
match step a with inl b => Q b | inr a' => P a' end.
Lemma iter_prop:
forall n a b, P a -> iter n a = Some b -> Q b.
Proof.
induction n; intros until b; intro H; simpl.
congruence.
unfold F_iter. generalize (step_prop a H).
case (step a); intros. congruence.
apply IHn with a0; auto.
Qed.
Lemma iterate_prop:
forall a b, iterate a = Some b -> P a -> Q b.
Proof.
intros. destruct (iterate_converges_to a) as [n IT].
rewrite H in IT. apply iter_prop with n a. auto. apply IT. auto.
Qed.
End ITERATION.
End GenIter.
|
// fpgaTop_ml605.v - ssiegel 2009-03-17
// 2012-02-11 ssiegel Added MDIO port
// 2014-01-26 ssiegel Added UART port
module fpgaTop(
input wire sys0_clkp, // sys0 Clock +
input wire sys0_clkn, // sys0 Clock -
input wire sys1_clkp, // sys1 Clock +
input wire sys1_clkn, // sys1 Clock -
input wire pci0_clkp, // PCIe Clock +
input wire pci0_clkn, // PCIe Clock -
input wire pci0_reset_n, // PCIe Reset
output wire [3:0] pci_exp_txp, // PCIe lanes...
output wire [3:0] pci_exp_txn,
input wire [3:0] pci_exp_rxp,
input wire [3:0] pci_exp_rxn,
output wire [12:0] led, // LEDs ml605
output wire [ 3:0] lcd_db, // LCD databus
output wire lcd_e, // LCD enable
output wire lcd_rs, // LCD register-select
output wire lcd_rw, // LCD read-not-write
input wire ppsExtIn, // PPS in
output wire ppsOut, // PPS out
output wire upads_rts, // USB UART...
output wire upads_tx,
input wire upads_cts_arg,
input wire upads_rx_arg,
output wire gmii_rstn, // Alaska GMII...
output wire gmii_gtx_clk,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
input wire gmii_rx_clk,
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire mdio_mdc, // Alaska MDIO...
inout wire mdio_mdd,
output wire [23:0] flash_addr,
inout wire [15:0] flash_io_dq,
input wire flash_wait,
output wire flash_we_n,
output wire flash_oe_n,
output wire flash_ce_n,
inout wire [63:0] ddr3_dq, // DDR3 DRAM...
output wire [12:0] ddr3_addr,
output wire [2:0] ddr3_ba,
output wire ddr3_ras_n,
output wire ddr3_cas_n,
output wire ddr3_we_n,
output wire ddr3_reset_n,
output wire [0:0] ddr3_cs_n,
output wire [0:0] ddr3_odt,
output wire [0:0] ddr3_cke,
output wire [7:0] ddr3_dm,
inout wire [7:0] ddr3_dqs_p,
inout wire [7:0] ddr3_dqs_n,
output wire [0:0] ddr3_ck_p,
output wire [0:0] ddr3_ck_n,
output wire flp_com_sclk, // FMC150 in LPC Slot...
output wire flp_com_sdc2m,
output wire flp_cdc_csb,
output wire flp_dac_csb,
input wire flp_cdc_sdi,
input wire flp_dac_sdi,
// input wire [3:0] flp_sdi_sdm2c,
// output wire [3:0] flp_csb
output wire flp_cdc_rstn,
output wire flp_cdc_pdn,
// output wire dac0_txena, //TODO These 7
// output wire dac0_dclkp,
// output wire dac0_dclkn,
// output wire dac0_framep,
// output wire dac0_framen,
// output wire [7:0] dac0_dap,
// output wire [7:0] dac0_dan,
//output wire flp_mon_rstn,
//output wire flp_mon_intn,
//output wire flp_adc_rstn,
input wire flp_cdc_clk_p,
input wire flp_cdc_clk_n,
//input wire flp_cdc_pllstat,
output wire flp_cdc_refen
);
//FIXME:
assign flp_cdc_pdn = 1'b1;
assign flp_cdc_refen = 1'b1;
wire flpCDC_sclkn, flpCDC_sclkgate;
wire flpDAC_sclkn, flpDAC_sclkgate;
assign flp_com_sclk = (flpCDC_sclkn && flpCDC_sclkgate) || (flpDAC_sclkn && flpDAC_sclkgate);
wire flpCDC_com_sdc2m, flpDAC_com_sdc2m;
assign flp_com_sdc2m = (flpCDC_com_sdc2m && flpCDC_sclkgate) || (flpDAC_com_sdc2m && flpDAC_sclkgate);
// Instance and connect mkFTop...
mkFTop_ml605 ftop(
.sys0_clkp (sys0_clkp),
.sys0_clkn (sys0_clkn),
.sys1_clkp (sys1_clkp),
.sys1_clkn (sys1_clkn),
.pci0_clkp (pci0_clkp),
.pci0_clkn (pci0_clkn),
.pci0_rstn (pci0_reset_n),
.pcie_rxp_i (pci_exp_rxp),
.pcie_rxn_i (pci_exp_rxn),
.pcie_txp (pci_exp_txp),
.pcie_txn (pci_exp_txn),
.led (led),
.lcd_db (lcd_db),
.lcd_e (lcd_e),
.lcd_rs (lcd_rs),
.lcd_rw (lcd_rw),
.gps_ppsSyncIn_x (ppsExtIn),
.gps_ppsSyncOut (ppsOut),
.upads_rts (upads_rts),
.upads_tx (upads_tx),
.upads_cts_arg (upads_cts_arg),
.upads_rx_arg (upads_rx_arg),
.gmii_rstn (gmii_rstn),
.gmii_tx_txd (gmii_txd),
.gmii_tx_tx_en (gmii_tx_en),
.gmii_tx_tx_er (gmii_tx_er),
.gmii_rx_rxd_i (gmii_rxd),
.gmii_rx_rx_dv_i (gmii_rx_dv),
.gmii_rx_rx_er_i (gmii_rx_er),
.gmii_tx_tx_clk (gmii_gtx_clk),
.gmii_rx_clk (gmii_rx_clk),
.mdio_mdc (mdio_mdc),
.mdio_mdd (mdio_mdd),
.flash_addr (flash_addr),
.flash_io_dq (flash_io_dq),
.flash_fwait_i (flash_wait),
.flash_we_n (flash_we_n),
.flash_oe_n (flash_oe_n),
.flash_ce_n (flash_ce_n),
.dram_io_dq (ddr3_dq),
.dram_addr (ddr3_addr),
.dram_ba (ddr3_ba),
.dram_ras_n (ddr3_ras_n),
.dram_cas_n (ddr3_cas_n),
.dram_we_n (ddr3_we_n),
.dram_reset_n (ddr3_reset_n),
.dram_cs_n (ddr3_cs_n),
.dram_odt (ddr3_odt),
.dram_cke (ddr3_cke),
.dram_dm (ddr3_dm),
.dram_io_dqs_p (ddr3_dqs_p),
.dram_io_dqs_n (ddr3_dqs_n),
.dram_ck_p (ddr3_ck_p),
.dram_ck_n (ddr3_ck_n),
.flpCDC_sclkn (flpCDC_sclkn), // Use the inverted clock for slow-balanced setup/hold
.flpCDC_sclkgate (flpCDC_sclkgate),
.flpCDC_sdo (flpCDC_com_sdc2m),
.flpCDC_csb (flp_cdc_csb),
.flpCDC_sdi_arg (flp_cdc_sdi),
.flpDAC_sclkn (flpDAC_sclkn), // Use the inverted clock for slow-balanced setup/hold
.flpDAC_sclkgate (flpDAC_sclkgate),
.flpDAC_sdo (flpDAC_com_sdc2m),
.flpDAC_csb (flp_dac_csb),
.flpDAC_sdi_arg (flp_dac_sdi),
// .dac0_txena (dac0_txena), //TODO These 7
// .dac0_dclkp (dac0_dclkp),
// .dac0_dclkn (dac0_dclkn),
// .dac0_framep (dac0_framep),
// .dac0_framen (dac0_framen),
// .dac0_dap (dac0_dap),
// .dac0_dan (dac0_dan),
.flpCDC_srst (flp_cdc_rstn), // The srst from SPICore32 active-low
//.flp_cdc_pdn (flp_cdc_pdn),
//.flp_mon_rstn (flp_mon_rstn),
//.flp_mon_intn (flp_mon_intn),
//.flp_adc_rstn (flp_adc_rstn),
.flp_cdc_clk_p (flp_cdc_clk_p),
.flp_cdc_clk_n (flp_cdc_clk_n)
//.flp_cdc_pllstat (flp_cdc_pllstat),
//.flp_cdc_refen (flp_cdc_refen)
);
endmodule
|
//#############################################################################
//# Function: Dual data rate input buffer (2 cycle delay) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_iddr #(parameter DW = 1 // width of data inputs
)
(
input clk, // clock
input ce0, // 1st cycle enable
input ce1, // 2nd cycle enable
input [DW/2-1:0] din, // data input sampled on both edges of clock
output reg [DW-1:0] dout // iddr aligned
);
//regs("sl"=stable low, "sh"=stable high)
reg [DW/2-1:0] din_sl;
reg [DW/2-1:0] din_sh;
reg ce0_negedge;
//########################
// Pipeline valid for negedge
//########################
always @ (negedge clk)
ce0_negedge <= ce0;
//########################
// Dual edge sampling
//########################
always @ (posedge clk)
if(ce0)
din_sl[DW/2-1:0] <= din[DW/2-1:0];
always @ (negedge clk)
if(ce0_negedge)
din_sh[DW/2-1:0] <= din[DW/2-1:0];
//########################
// Aign pipeline
//########################
always @ (posedge clk)
if(ce1)
dout[DW-1:0] <= {din_sh[DW/2-1:0],
din_sl[DW/2-1:0]};
endmodule // oh_iddr
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:41:39 04/21/2015
// Design Name: e_finder
// Module Name: H:/Users/ll024/Downloads/PrimeFactorization (1)/PrimeFactorization/PrimeFactorization/test_e_finder.v
// Project Name: PrimeFactorization
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: e_finder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_e_finder;
// Inputs
reg clk;
reg [7:0] boundary;
// Outputs
wire [64:0] e;
wire done;
// Instantiate the Unit Under Test (UUT)
e_finder uut (
.clk(clk),
.boundary(boundary),
.e(e),
.done(done)
);
always #1 clk = ~clk;
initial begin
// Initialize Inputs
clk = 1;
boundary = 100;
// Wait 100 ns for global reset to finish
#3000;
// Add stimulus here
end
endmodule
|
`define RC4_KEYREAD 4'h0
`define RC4_KSA1 4'h1
`define RC4_KSA2 4'h2
`define RC4_KSA3 4'h3
`define RC4_NEED 4'h7
`define RC4_PRGA1 4'h4
`define RC4_PRGA2 4'h5
`define RC4_PRGA3 4'h6
module rc4_old(ready, k, clk, rst, keyinput, need);
// parameters
parameter keylength = 8;
// outputs
output reg ready; // enable when generate prga
output reg [7:0] k; // value extracts from stream
// inputs
input clk;
input rst;
input [7:0] keyinput; // one byte of key per cycle
input need;
// internal
reg [7:0] key[0:keylength-1];
reg [3:0] state;
reg [7:0] stream[0:255];
reg [7:0] stream_temp;
reg [7:0] i;
reg [7:0] j;
reg [7:0] tmp;
initial begin
ready = 1;
state = `RC4_KEYREAD;
i = 8'h00;
j = 8'h00;
end
always @ (posedge clk) begin
if (rst) begin
ready = 0;
state = `RC4_KEYREAD;
i = 8'h00;
j = 8'h00;
end
case (state)
// read key every cylce until key length
`RC4_KEYREAD: begin
if (i == keylength) begin
state = `RC4_KSA1;
i = 8'h00;
end else begin
$display("key[%d] = %02X", i, keyinput);
key[i] = keyinput;
i = i + 8'h01;
end
end
// KSA 1
// initialize stream
`RC4_KSA1: begin
stream[i] = i;
if (i == 8'hff) begin
state = `RC4_KSA2;
i = 8'h00;
end else begin
i = i + 8'h01;
end
end
// KSA 2
// calcule j for use in next cycle
`RC4_KSA2: begin
state = `RC4_KSA3;
stream_temp = stream[i];
j = j + stream[i] + key[i % keylength];
end
// KSA 3
// swap values in stream
`RC4_KSA3: begin
stream[i] = stream[j];
// stream[j] = stream[i];
stream[j] = stream_temp;
if (i == 8'hff) begin
// ready to use prga
// state = `RC4_PRGA1;
state = `RC4_NEED;
i = 8'h01;
j = stream[1];
end else begin
state = `RC4_KSA2;
i = i + 8'h01;
end
end
`RC4_NEED: begin
if (need) state = `RC4_PRGA1;
end
// PRGA 1
// save data for swap
`RC4_PRGA1: begin
ready = 0;
state = `RC4_PRGA2;
stream_temp = stream[i];
end
// PRGA 2
// swap values in stream
`RC4_PRGA2: begin
state = `RC4_PRGA3;
stream[i] = stream[j];
// stream[j] = stream[i];
stream[j] = stream_temp;
tmp = stream[i] + stream[j];
end
// PRGA 3
// take k and then output
`RC4_PRGA3: begin
ready = 1;
k = stream[tmp];
// state = `RC4_PRGA1;
state = `RC4_NEED;
if (i == 8'hff) j = j + stream[0];
else j = j + stream[i + 1];
i = i + 1;
end
default: begin
end
endcase
end
endmodule
|
//syscontrol handles the startup of the FGPA,
//after fpga config, it automatically does a global system reset and asserts boot.
//the boot signal puts gary in a special mode so that the bootrom
//is mapped into the system memory map. The firmware in the bootrom
//then loads the kickstart via the diskcontroller into the kickstart ram area.
//When kickstart has been loaded, the bootrom asserts bootdone by selecting both cia's at once.
//This resets the system for a second time but it also de-asserts boot.
//Thus, the system now boots as a regular amiga.
//Subsequent resets by asserting mrst will not assert boot again.
//
// JB:
// 2008-07-11 - reset to bootloader
// 2009-03-13 - shorter reset
// 2009-08-17 - reset generator modification
module minimig_syscontrol
(
input clk, //bus clock
input clk7_en,
input cnt, //pulses for counting
input mrst, //master/user reset input
output reset //global synchronous system reset
);
//local signals
reg smrst0, smrst1; //registered input
reg [2:0] rst_cnt = 0; //reset timer SHOULD BE CLEARED BY CONFIG
wire _rst; //local reset signal
//asynchronous mrst input synchronizer
always @(posedge clk) begin
if (clk7_en) begin
smrst0 <= mrst;
smrst1 <= smrst0;
end
end
//reset timer and mrst control
always @(posedge clk) begin
if (clk7_en) begin
if (smrst1)
rst_cnt <= 3'd0;
else if (!_rst && cnt)
rst_cnt <= rst_cnt + 3'd1;
end
end
assign _rst = rst_cnt[2];
//global reset output
assign reset = ~_rst;
endmodule
|
/* verilator lint_off COMBDLY */
module shiftbox (shiftop,calc_sz,ci,co,opa,opb,resa,resb,resa4,resb4,co4);
input [3:0] shiftop;
input [3:0] calc_sz;
input [31:0] opa,opb;
output reg [31:0] resa,resb;
output reg [31:0] resa4,resb4;
input ci;
output reg co,co4;
always @(*)
case (shiftop)
4'b0000 : if (calc_sz==4) begin resa <= {opa[30:0],opa[31]}; co<=ci; resb<=opb; end else // rol without ci
if (calc_sz==2) begin resa[15:0] <= {opa[14:0],opa[15]}; co<=ci; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin resa[ 7:0] <= {opa[ 6:0],opa[ 7]}; co<=ci; resb<=opb; resa[31: 8]<=opa[31: 8]; end
4'b0001 : if (calc_sz==4) begin resa <= {opa[0],opa[31:1]}; co<=ci; resb<=opb; end else // ror without ci
if (calc_sz==2) begin resa[15:0] <= {opa[0],opa[15:1]}; co<=ci; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin resa[ 7:0] <= {opa[0],opa[ 7:1]}; co<=ci; resb<=opb; resa[31: 8]<=opa[31: 8]; end
4'b0010 : if (calc_sz==4) begin {co,resa[31:0]} <= {opa[31:0],ci}; resb<=opb; end else // rol with ci = rcl
if (calc_sz==2) begin {co,resa[15:0]} <= {opa[15:0],ci}; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin {co,resa[ 7:0]} <= {opa[ 7:0],ci}; resb<=opb; resa[31: 8]<=opa[31: 8]; end
4'b0011 : if (calc_sz==4) begin {co,resa[31:0]} <= {opa[0],ci,opa[31:1]}; resb<=opb; end else // ror with ci = rcr
if (calc_sz==2) begin {co,resa[15:0]} <= {opa[0],ci,opa[15:1]}; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin {co,resa[ 7:0]} <= {opa[0],ci,opa[ 7:1]}; resb<=opb; resa[31: 8]<=opa[31: 8]; end
4'b0100,
4'b0110 : if (calc_sz==4) begin {co,resa[31:0]} <= {opa[31:0],1'b0}; resb<=opb; end else // shl,sal with ci
if (calc_sz==2) begin {co,resa[15:0]} <= {opa[15:0],1'b0}; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin {co,resa[ 7:0]} <= {opa[ 7:0],1'b0}; resb<=opb; resa[31: 8]<=opa[31: 8]; end
4'b0101 : if (calc_sz==4) begin resa[31:0] <= {1'b0,opa[31:1]}; co<=ci; resb<=opb; end else // shr
if (calc_sz==2) begin resa[15:0] <= {1'b0,opa[15:1]}; co<=ci; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin resa[ 7:0] <= {1'b0,opa[ 7:1]}; co<=ci; resb<=opb; resa[31: 8]<=opa[31: 8]; end
4'b0111 : if (calc_sz==4) begin resa[31:0] <= {opa[31],opa[31:1]}; co<=ci; resb<=opb; end else // sar
if (calc_sz==2) begin resa[15:0] <= {opa[15],opa[15:1]}; co<=ci; resb<=opb; resa[31:16]<=opa[31:16]; end else
begin resa[ 7:0] <= {opa[ 7],opa[ 7:1]}; co<=ci; resb<=opb; resa[31: 8]<=opa[31: 8]; end
4'b1000 : if (calc_sz==4) begin {resb[31:0],co} <= {opa[0],opb[31:0]}; resa[31:0] <= {opa[31],opa[31:1]}; end else // shrd
begin {resb[15:0],co} <= {opa[0],opb[15:0]}; resa[15:0] <= {opa[15],opa[15:1]}; resa[31:16]<=opa[31:16]; resb[31:16]<=opb[31:16]; end
4'b1001 : if (calc_sz==4) begin {co,resb[31:0]} <= {opb[31:0],opa[31]}; resa[31:0] <= {opa[30:0],opa[0]}; end else // shld
begin {co,resb[15:0]} <= {opb[15:0],opa[15]}; resa[15:0] <= {opa[14:0],opa[0]}; resa[31:16]<=opa[31:16]; resb[31:16]<=opb[31:16];end
default : begin co<=ci; resb<=opb; resa <= opa; end
endcase
always @(*)
case (shiftop)
4'b0000 : if (calc_sz==4) begin resa4 <= {opa[27:0],opa[31:28]}; co4<=ci; resb4<=opb; end else // rol without ci
if (calc_sz==2) begin resa4[15:0] <= {opa[11:0],opa[15:12]}; co4<=ci; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin resa4[ 7:0] <= {opa[ 3:0],opa[ 7:4]}; co4<=ci; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
4'b0001 : if (calc_sz==4) begin resa4 <= {opa[3:0],opa[31:4]}; co4<=ci; resb4<=opb; end else // ror without ci
if (calc_sz==2) begin resa4[15:0] <= {opa[3:0],opa[15:4]}; co4<=ci; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin resa4[ 7:0] <= {opa[3:0],opa[ 7:4]}; co4<=ci; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
4'b0010 : if (calc_sz==4) begin {co4,resa4[31:0]} <= {opa[28:0],ci,opa[31:29]}; resb4<=opb; end else // rol with ci = rcl
if (calc_sz==2) begin {co4,resa4[15:0]} <= {opa[12:0],ci,opa[15:13]}; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin {co4,resa4[ 7:0]} <= {opa[ 4:0],ci,opa[ 7: 5]}; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
4'b0011 : if (calc_sz==4) begin {co4,resa4[31:0]} <= {opa[3:0],ci,opa[31:4]}; resb4<=opb; end else // ror with ci = rcr
if (calc_sz==2) begin {co4,resa4[15:0]} <= {opa[3:0],ci,opa[15:4]}; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin {co4,resa4[ 7:0]} <= {opa[3:0],ci,opa[ 7:4]}; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
4'b0100,
4'b0110 : if (calc_sz==4) begin {co4,resa4[31:0]} <= {opa[28:0],4'b0000}; resb4<=opb; end else // shl,sal with ci
if (calc_sz==2) begin {co4,resa4[15:0]} <= {opa[12:0],4'b0000}; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin {co4,resa4[ 7:0]} <= {opa[ 4:0],4'b0000}; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
4'b0101 : if (calc_sz==4) begin resa4[31:0] <= {4'b0000,opa[31:4]}; co4<=ci; resb4<=opb; end else // shr
if (calc_sz==2) begin resa4[15:0] <= {4'b0000,opa[15:4]}; co4<=ci; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin resa4[ 7:0] <= {4'b0000,opa[ 7:4]}; co4<=ci; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
4'b0111 : if (calc_sz==4) begin resa4[31:0] <= {opa[31],opa[31],opa[31],opa[31],opa[31:4]}; co4<=ci; resb4<=opb; end else // sar
if (calc_sz==2) begin resa4[15:0] <= {opa[15],opa[15],opa[15],opa[15],opa[15:4]}; co4<=ci; resb4<=opb; resa4[31:16]<=opa[31:16]; end else
begin resa4[ 7:0] <= {opa[ 7],opa[ 7],opa[ 7],opa[ 7],opa[ 7:4]}; co4<=ci; resb4<=opb; resa4[31: 8]<=opa[31: 8]; end
4'b1000 : if (calc_sz==4) begin resa4[31:0] <= {opa[31],opa[31],opa[31],opa[31],opa[31:4]}; {resb4[31:0],co4} <= {opa[3:0],opb[31:3]}; end else // shrd
begin resa4[15:0] <= {opa[15],opa[15],opa[15],opa[15],opa[15:4]}; {resb4[15:0],co4} <= {opa[3:0],opb[15:3]}; resa4[31:16]<=opa[31:16]; resb4[31:16]<=opb[31:16]; end
4'b1001 : if (calc_sz==4) begin resa4[31:0] <= {opa[27:0],opa[0],opa[0],opa[0],opa[0]}; {co4,resb4[31:0]} <= {opb[28:0],opa[31:28]}; end else // shld
begin resa4[15:0] <= {opa[11:0],opa[0],opa[0],opa[0],opa[0]}; {co4,resb4[15:0]} <= {opb[12:0],opa[15:12]}; resa4[31:16]<=opa[31:16]; resb4[31:16]<=opb[31:16]; end
default : begin co4<=ci; resb4<=opb; resa4 <= opa; end
endcase
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 23:00:32 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_1/zqynq_lab_1_design_axi_gpio_1_1_stub.v
// Design : zqynq_lab_1_design_axi_gpio_1_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.2" *)
module zqynq_lab_1_design_axi_gpio_1_1(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[4:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output ip2intc_irpt;
input [4:0]gpio_io_i;
endmodule
|
module key_expansion(key_in, rk_delayed_out, round_cnt, rk_last_out, clk, input_sel, sbox_sel, last_out_sel, bit_out_sel, rcon_en);
input [7:0] key_in;
output [7:0] rk_delayed_out;
output [7:0] rk_last_out;
input [3:0] round_cnt;
input clk;
input input_sel, sbox_sel, last_out_sel, bit_out_sel;
input [7:0] rcon_en;
reg [7:0] r15, r14, r13, r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0, r_redun;
wire [7:0] rcon_sbox_o, sbox_o, rcon_o, sbox_in, mux_in_o, mux_bit_o, rcon_num;
function [7:0] rcon;
input [3:0] x;
casex (x)
4'b0000: rcon = 8'h01;
4'b0001: rcon = 8'h02;
4'b0010: rcon = 8'h04;
4'b0011: rcon = 8'h08;
4'b0100: rcon = 8'h10;
4'b0101: rcon = 8'h20;
4'b0110: rcon = 8'h40;
4'b0111: rcon = 8'h80;
4'b1000: rcon = 8'h1b;
4'b1001: rcon = 8'h36;
default: rcon = 8'h01;
endcase
endfunction
assign rcon_num = rcon(round_cnt);
assign rcon_sbox_o = sbox_o ^ rcon_o;
assign rcon_o = rcon_en & rcon_num;
assign rk_delayed_out = r12;
mux2_1 mux_in (rk_last_out, key_in, mux_in_o, input_sel);
mux2_1 mux_sbox (r13, r_redun, sbox_in, sbox_sel);
mux2_1 mux_bit ((r4 ^ rk_last_out), r4, mux_bit_o, bit_out_sel);
mux2_1 mux_last_out (r0, ( r0 ^ rcon_sbox_o), rk_last_out, last_out_sel);
bSbox sbox (sbox_in, sbox_o);
always @ (posedge clk)
begin
r15 <= mux_in_o;
r14 <= r15;
r13 <= r14;
r12 <= r13;
r11 <= r12;
r10 <= r11;
r9 <= r10;
r8 <= r9;
r7 <= r8;
r6 <= r7;
r5 <= r6;
r4 <= r5;
r3 <= mux_bit_o;
r2 <= r3;
r1 <= r2;
r0 <= r1;
end
always @ (posedge clk)
begin
if (rcon_en == 8'hff)
begin
r_redun <= r12;
end
end
endmodule
|
module decode(clk, regwritew,regwritew2, forwardad,forwardad2, forwardbd,forwardbd2, instrd,instrd2, resultw,resultw2, writeregw, writeregw2,aluoutm, aluoutm2,pcplus4d,pcplus4d2,
pcbranchd, pcbranchd2,equald,equald2, mux1out, mux1out2,mux2out, mux2out2,rsd,rsd2, rtd, rtd2,rdd,rdd2, signimmd,signimmd2,signextd,signextd2);
input clk, regwritew,regwritew2;
input [1:0] forwardad, forwardad2,forwardbd,forwardbd2;
input [31:0] instrd,instrd2, resultw,resultw2, aluoutm, aluoutm2,pcplus4d,pcplus4d2;
input [4:0] writeregw,writeregw2;
output [31:0] pcbranchd,pcbranchd2;
output reg equald,equald2;
output [31:0] mux1out,mux1out2, mux2out,mux2out2;
output reg [4:0] rsd,rsd2, rtd,rtd2, rdd,rdd2;
output [31:0] signimmd, signimmd2,signextd,signextd2;
wire [31:0] rd1,rd1_2, rd2, rd2_2,signimmsll2,signimmsll2_2;
wire [25:0] signssl,signssl2;
assign signextd = {pcplus4d[31:26], signssl};
assign signextd2 ={pcplus4d[31:26], signssl2};
initial begin
equald <= 0;
rsd <= 0;
rtd <= 0;
rdd <= 0;
end
// Decode - Cycle 2
// Reg File, Sign Ext, Shift Left, ALU
regfile rf(clk, regwritew,regwritew2, instrd[25:21],instrd2[25:21], instrd[20:16],instrd2[20:16],
writeregw,writeregw2, resultw,resultw2, rd1,rd1_2, rd2,rd2_2);
signext se(instrd[15:0], signimmd);
sl2 sll2(signimmd, signimmsll2);
sl226 sel2(instrd[25:0],signssl);
adder addersl2pcplus4(signimmsll2, pcplus4d-32'h4, pcbranchd);
signext se2(instrd2[15:0], signimmd2);
sl2 sll2_2(signimmd2, signimmsll2_2);
sl226 sel2_2(instrd2[25:0],signssl2);
adder addersl2pcplus4_2(signimmsll2_2, pcplus4d-32'h4, pcbranchd2);
mux3 #(32) muxrd1(rd1, aluoutm, aluoutm2, forwardad, mux1out);
mux3 #(32) muxrd2(rd2, aluoutm, aluoutm2, forwardbd, mux2out);
mux3 #(32) muxrd1_2(rd1_2, aluoutm2, aluoutm, forwardad2, mux1out2);
mux3 #(32) muxrd2_2(rd2_2, aluoutm2, aluoutm, forwardbd2, mux2out2);
always @(*) begin
equald = (mux1out==mux2out) ? 1:0;
rsd = instrd[25:21];
rtd = instrd[20:16];
rdd = instrd[15:11];
equald2 = (mux1out2==mux2out2)?1:0;
rsd2 = instrd2[25:21];
rtd2 = instrd2[20:16];
rdd2 = instrd2[15:11];
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:29:40 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_1/zynq_design_1_axi_gpio_0_1_stub.v
// Design : zynq_design_1_axi_gpio_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.2" *)
module zynq_design_1_axi_gpio_0_1(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output [7:0]gpio_io_o;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_jbusgif.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp_dramif
//
//-----------------------------------------------------------------------------
`include "sys.h"
module ctu_clsp_jbusgif(/*AUTOARG*/
// Outputs
ctu_dram02_jbus_cken, ctu_dram13_jbus_cken, ctu_jbi_jbus_cken,
ctu_iob_jbus_cken, ctu_jbusl_jbus_cken, ctu_jbusr_jbus_cken,
ctu_misc_jbus_cken, ctu_efc_jbus_cken, ctu_dbg_jbus_cken,
jbus_grst_out_l, jbus_arst_l, jbus_gdbginit_out_l, jbus_adbginit_l,
// Inputs
io_pwron_rst_l, start_clk_jl, testmode_l, jbus_gclk, jbus_grst_jl_l,
jbus_dbginit_jl_l, ctu_dram02_cken_jl, ctu_dram13_cken_jl,
ctu_iob_cken_jl, ctu_efc_cken_jl, ctu_dbg_cken_jl, ctu_jbusl_cken_jl,
ctu_jbusr_cken_jl, ctu_jbi_cken_jl, ctu_misc_cken_jl,
jtag_clsp_force_cken_jbus
);
input io_pwron_rst_l;
input start_clk_jl;
input testmode_l;
input jbus_gclk;
input jbus_grst_jl_l;
input jbus_dbginit_jl_l;
input ctu_dram02_cken_jl;
input ctu_dram13_cken_jl;
input ctu_iob_cken_jl;
input ctu_efc_cken_jl;
input ctu_dbg_cken_jl;
input ctu_jbusl_cken_jl;
input ctu_jbusr_cken_jl;
input ctu_jbi_cken_jl;
input ctu_misc_cken_jl;
input jtag_clsp_force_cken_jbus;
output ctu_dram02_jbus_cken;
output ctu_dram13_jbus_cken;
output ctu_jbi_jbus_cken;
output ctu_iob_jbus_cken;
output ctu_jbusl_jbus_cken;
output ctu_jbusr_jbus_cken;
output ctu_misc_jbus_cken;
output ctu_efc_jbus_cken;
output ctu_dbg_jbus_cken;
output jbus_grst_out_l;
output jbus_arst_l;
output jbus_gdbginit_out_l;
output jbus_adbginit_l;
wire ctu_dram02_cken_muxed;
wire ctu_dram13_cken_muxed;
wire ctu_iob_cken_muxed;
wire ctu_efc_cken_muxed;
wire ctu_dbg_cken_muxed;
wire ctu_jbusl_cken_muxed;
wire ctu_jbusr_cken_muxed;
wire ctu_jbi_cken_muxed;
wire ctu_misc_cken_muxed;
wire force_cken;
// -----------------------------------------
//
// Global signals
//
// -----------------------------------------
// The following flops needs to be non-scanable:
assign jbus_arst_l = io_pwron_rst_l ;
assign jbus_adbginit_l = io_pwron_rst_l ;
dffrl_async_ns u_dram_dbginit_l(
.din (jbus_dbginit_jl_l & start_clk_jl),
.clk (jbus_gclk),
.rst_l (io_pwron_rst_l),
.q (jbus_gdbginit_out_l));
dffrl_async_ns u_jbus_grst_l(
.din (jbus_grst_jl_l & start_clk_jl),
.clk (jbus_gclk),
.rst_l (io_pwron_rst_l),
.q (jbus_grst_out_l));
// Gated cken with testmode_l
assign force_cken = jtag_clsp_force_cken_jbus | ~testmode_l;
assign ctu_dram02_cken_muxed = force_cken ? 1'b1: (ctu_dram02_cken_jl & start_clk_jl);
assign ctu_dram13_cken_muxed = force_cken ? 1'b1: (ctu_dram13_cken_jl & start_clk_jl);
assign ctu_iob_cken_muxed = force_cken ? 1'b1: (ctu_iob_cken_jl & start_clk_jl);
assign ctu_jbi_cken_muxed = force_cken ? 1'b1: (ctu_jbi_cken_jl & start_clk_jl);
assign ctu_efc_cken_muxed = force_cken ? 1'b1: (ctu_efc_cken_jl & start_clk_jl);
assign ctu_jbusr_cken_muxed = force_cken? 1'b1: ((start_clk_jl & ctu_jbusr_cken_jl) | ~start_clk_jl);
assign ctu_jbusl_cken_muxed = force_cken? 1'b1: ((start_clk_jl & ctu_jbusl_cken_jl) | ~start_clk_jl);
assign ctu_dbg_cken_muxed = force_cken ? 1'b1: ((start_clk_jl & ctu_dbg_cken_jl) | ~start_clk_jl);
assign ctu_misc_cken_muxed = force_cken? 1'b1: ((start_clk_jl & ctu_misc_cken_jl) | ~start_clk_jl);
dffrl_async_ns u_ctu_dram02_jbus_cken_nsr(
.din (ctu_dram02_cken_muxed),
.clk (jbus_gclk),
.rst_l (io_pwron_rst_l),
.q (ctu_dram02_jbus_cken));
dffrl_async_ns u_ctu_dram13_jbus_cken_nsr(
.din (ctu_dram13_cken_muxed),
.clk (jbus_gclk),
.rst_l (io_pwron_rst_l),
.q (ctu_dram13_jbus_cken));
dffrl_async_ns u_ctu_iob_cken_muxed_nsr(
.din (ctu_iob_cken_muxed),
.clk (jbus_gclk),
.rst_l (io_pwron_rst_l),
.q (ctu_iob_jbus_cken));
dffrl_async_ns u_ctu_jbi_cken_muxed_nsr(
.din (ctu_jbi_cken_muxed),
.clk (jbus_gclk),
.rst_l (io_pwron_rst_l),
.q (ctu_jbi_jbus_cken));
dffsl_async_ns u_ctu_jbusr_cken_muxed_nsr(
.din (ctu_jbusr_cken_muxed),
.clk (jbus_gclk),
.set_l (io_pwron_rst_l),
.q (ctu_jbusr_jbus_cken));
dffsl_async_ns u_ctu_jbusl_cken_muxed_nsr(
.din (ctu_jbusl_cken_muxed),
.clk (jbus_gclk),
.set_l (io_pwron_rst_l),
.q (ctu_jbusl_jbus_cken));
dffrl_async_ns u_ctu_efc_cken_muxed_nsr(
.din (ctu_efc_cken_muxed),
.clk (jbus_gclk),
.rst_l (io_pwron_rst_l),
.q (ctu_efc_jbus_cken));
dffsl_async_ns u_ctu_dbg_cken_muxed_nsr(
.din (ctu_dbg_cken_muxed),
.clk (jbus_gclk),
.set_l (io_pwron_rst_l),
.q (ctu_dbg_jbus_cken));
dffsl_async_ns u_ctu_misc_cken_muxed_nsr(
.din (ctu_misc_cken_muxed),
.clk (jbus_gclk),
.set_l (io_pwron_rst_l),
.q (ctu_misc_jbus_cken));
endmodule // jbus_f
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's definitions ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Parameters of the OR1200 core ////
//// ////
//// To Do: ////
//// - add parameters that are missing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_defines.v,v $
// Revision 1.44 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.43 2005/01/07 09:23:39 andreje
// l.ff1 and l.cmov instructions added
//
// Revision 1.42 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.41 2004/05/09 20:03:20 lampret
// By default l.cust5 insns are disabled
//
// Revision 1.40 2004/05/09 19:49:04 lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.39 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
// Revision 1.38 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.35.4.6 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
// Revision 1.35.4.5 2004/01/15 06:46:38 markom
// interface to debug changed; no more opselect; stb-ack protocol
//
// Revision 1.35.4.4 2004/01/11 22:45:46 andreje
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
//
// Revision 1.35.4.3 2003/12/17 13:43:38 simons
// Exception prefix configuration changed.
//
// Revision 1.35.4.2 2003/12/05 00:05:03 lampret
// Static exception prefix.
//
// Revision 1.35.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.35 2003/04/24 00:16:07 lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.34 2003/04/20 22:23:57 lampret
// No functional change. Only added customization for exception vectors.
//
// Revision 1.33 2003/04/07 20:56:07 lampret
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
//
// Revision 1.32 2003/04/07 01:26:57 lampret
// RFRAM defines comments updated. Altera LPM option added.
//
// Revision 1.31 2002/12/08 08:57:56 lampret
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
//
// Revision 1.30 2002/10/28 15:09:22 mohor
// Previous check-in was done by mistake.
//
// Revision 1.29 2002/10/28 15:03:50 mohor
// Signal scanb_sen renamed to scanb_en.
//
// Revision 1.28 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.27 2002/09/16 03:13:23 lampret
// Removed obsolete comment.
//
// Revision 1.26 2002/09/08 05:52:16 lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.25 2002/09/07 19:16:10 lampret
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
//
// Revision 1.24 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.23 2002/09/04 00:50:34 lampret
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
//
// Revision 1.22 2002/09/03 22:28:21 lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.21 2002/08/22 02:18:55 lampret
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
//
// Revision 1.20 2002/08/18 21:59:45 lampret
// Disable SB until it is tested
//
// Revision 1.19 2002/08/18 19:53:08 lampret
// Added store buffer.
//
// Revision 1.18 2002/08/15 06:04:11 lampret
// Fixed Xilinx trace buffer address. REported by Taylor Su.
//
// Revision 1.17 2002/08/12 05:31:44 lampret
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
//
// Revision 1.16 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.15 2002/06/08 16:20:21 lampret
// Added defines for enabling generic FF based memory macro for register file.
//
// Revision 1.14 2002/03/29 16:24:06 lampret
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
//
// Revision 1.13 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.12 2002/03/28 19:25:42 lampret
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
//
// Revision 1.11 2002/03/28 19:13:17 lampret
// Updated defines.
//
// Revision 1.10 2002/03/14 00:30:24 lampret
// Added alternative for critical path in DU.
//
// Revision 1.9 2002/03/11 01:26:26 lampret
// Fixed async loop. Changed multiplier type for ASIC.
//
// Revision 1.8 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.7 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.6 2002/01/19 14:10:22 lampret
// Fixed OR1200_XILINX_RAM32X1D.
//
// Revision 1.5 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.4 2002/01/14 09:44:12 lampret
// Default ASIC configuration does not sample WB inputs.
//
// Revision 1.3 2002/01/08 00:51:08 lampret
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
//
// Revision 1.2 2002/01/03 21:23:03 lampret
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.20 2001/12/04 05:02:36 lampret
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
//
// Revision 1.19 2001/11/27 19:46:57 lampret
// Now FPGA and ASIC target are separate.
//
// Revision 1.18 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
// Revision 1.17 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.16 2001/11/20 21:30:38 lampret
// Added OR1200_REGISTERED_INPUTS.
//
// Revision 1.15 2001/11/19 14:29:48 simons
// Cashes disabled.
//
// Revision 1.14 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.13 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.12 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.11 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.8 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.3 2001/08/17 08:01:19 lampret
// IC enable/disable.
//
// Revision 1.2 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
//
// Dump VCD
//
//`define OR1200_VCD_DUMP
//
// Generate debug messages during simulation
//
//`define OR1200_VERBOSE
`define OR1200_ASIC
////////////////////////////////////////////////////////
//
// Typical configuration for an ASIC
//
`ifdef OR1200_ASIC
//
// Target ASIC memories
//
//`define OR1200_ARTISAN_SSP
//`define OR1200_ARTISAN_SDP
//`define OR1200_ARTISAN_STP
// `define OR1200_VIRTUALSILICON_SSP
//`define OR1200_VIRTUALSILICON_STP_T1
//`define OR1200_VIRTUALSILICON_STP_T2
//
// Do not implement Data cache
//
// `define OR1200_NO_DC
//
// Do not implement Insn cache
//
// `define OR1200_NO_IC
//
// Do not implement Data MMU
//
// `define OR1200_NO_DMMU
//
// Do not implement Insn MMU
//
// `define OR1200_NO_IMMU
//
// Select between ASIC optimized and generic multiplier
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
//
// Size/type of insn/data cache if implemented
//
// `define OR1200_IC_1W_512B
// `define OR1200_IC_1W_4KB
`define OR1200_IC_1W_8KB
// `define OR1200_DC_1W_4KB
`define OR1200_DC_1W_8KB
`else
/////////////////////////////////////////////////////////
//
// Typical configuration for an FPGA
//
//
// Target FPGA memories
//
//`define OR1200_ALTERA_LPM
//`define OR1200_XILINX_RAMB16
//`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
//
// Do not implement Data MMU
//
// `define OR1200_NO_DMMU
//
// Do not implement Insn MMU
//
// `define OR1200_NO_IMMU
//
// Select between ASIC and generic multiplier
//
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
//
// Size/type of insn/data cache if implemented
// (consider available FPGA memory resources)
//
//`define OR1200_IC_1W_512B
//`define OR1200_IC_1W_4KB
`define OR1200_IC_1W_8KB
//`define OR1200_DC_1W_4KB
`define OR1200_DC_1W_8KB
`endif
//////////////////////////////////////////////////////////
//
// Do not change below unless you know what you are doing
//
//
// Enable RAM BIST
//
// At the moment this only works for Virtual Silicon
// single port RAMs. For other RAMs it has not effect.
// Special wrapper for VS RAMs needs to be provided
// with scan flops to facilitate bist scan.
//
//`define OR1200_BIST
//
// Register OR1200 WISHBONE outputs
// (must be defined/enabled)
//
`define OR1200_REGISTERED_OUTPUTS
//
// Register OR1200 WISHBONE inputs
//
// (must be undefined/disabled)
//
//`define OR1200_REGISTERED_INPUTS
//
// Disable bursts if they are not supported by the
// memory subsystem (only affect cache line fill)
//
//`define OR1200_NO_BURSTS
//
//
// WISHBONE retry counter range
//
// 2^value range for retry counter. Retry counter
// is activated whenever *wb_rty_i is asserted and
// until retry counter expires, corresponding
// WISHBONE interface is deactivated.
//
// To disable retry counters and *wb_rty_i all together,
// undefine this macro.
//
//`define OR1200_WB_RETRY 7
//
// WISHBONE Consecutive Address Burst
//
// This was used prior to WISHBONE B3 specification
// to identify bursts. It is no longer needed but
// remains enabled for compatibility with old designs.
//
// To remove *wb_cab_o ports undefine this macro.
//
`define OR1200_WB_CAB
//
// WISHBONE B3 compatible interface
//
// This follows the WISHBONE B3 specification.
// It is not enabled by default because most
// designs still don't use WB b3.
//
// To enable *wb_cti_o/*wb_bte_o ports,
// define this macro.
//
//`define OR1200_WB_B3
//
// Enable additional synthesis directives if using
// _Synopsys_ synthesis tool
//
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
//
// Enables default statement in some case blocks
// and disables Synopsys synthesis directive full_case
//
// By default it is enabled. When disabled it
// can increase clock frequency.
//
`define OR1200_CASE_DEFAULT
//
// Operand width / register file address width
//
// (DO NOT CHANGE)
//
`define OR1200_OPERAND_WIDTH 32
`define OR1200_REGFILE_ADDR_WIDTH 5
//
// l.add/l.addi/l.and and optional l.addc/l.addic
// also set (compare) flag when result of their
// operation equals zero
//
// At the time of writing this, default or32
// C/C++ compiler doesn't generate code that
// would benefit from this optimization.
//
// By default this optimization is disabled to
// save area.
//
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
//
// Implement l.addc/l.addic instructions
//
// By default implementation of l.addc/l.addic
// instructions is enabled in case you need them.
// If you don't use them, then disable implementation
// to save area.
//
`define OR1200_IMPL_ADDC
//
// Implement carry bit SR[CY]
//
// By default implementation of SR[CY] is enabled
// to be compliant with the simulator. However
// SR[CY] is explicitly only used by l.addc/l.addic
// instructions and if these two insns are not
// implemented there is not much point having SR[CY].
//
`define OR1200_IMPL_CY
//
// Implement optional l.div/l.divu instructions
//
// By default divide instructions are not implemented
// to save area and increase clock frequency. or32 C/C++
// compiler can use soft library for division.
//
// To implement divide, multiplier needs to be implemented.
//
`define OR1200_IMPL_DIV
//
// Implement rotate in the ALU
//
// At the time of writing this, or32
// C/C++ compiler doesn't generate rotate
// instructions. However or32 assembler
// can assemble code that uses rotate insn.
// This means that rotate instructions
// must be used manually inserted.
//
// By default implementation of rotate
// is disabled to save area and increase
// clock frequency.
//
`define OR1200_IMPL_ALU_ROTATE
//
// Type of ALU compare to implement
//
// Try either one to find what yields
// higher clock frequencyin your case.
//
//`define OR1200_IMPL_ALU_COMP1
`define OR1200_IMPL_ALU_COMP2
//
// Implement multiplier
//
// By default multiplier is implemented
//
`define OR1200_MULT_IMPLEMENTED
//
// Implement multiply-and-accumulate
//
// By default MAC is implemented. To
// implement MAC, multiplier needs to be
// implemented.
//
`define OR1200_MAC_IMPLEMENTED
//
// Low power, slower multiplier
//
// Select between low-power (larger) multiplier
// and faster multiplier. The actual difference
// is only AND logic that prevents distribution
// of operands into the multiplier when instruction
// in execution is not multiply instruction
//
//`define OR1200_LOWPWR_MULT
//
// Clock ratio RISC clock versus WB clock
//
// If you plan to run WB:RISC clock fixed to 1:1, disable
// both defines
//
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
// and use clmode to set ratio
//
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
// clmode to set ratio
//
`define OR1200_CLKDIV_2_SUPPORTED
`define OR1200_CLKDIV_4_SUPPORTED
//
// Type of register file RAM
//
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
//`define OR1200_RFRAM_TWOPORT
//
// Memory macro dual port (see or1200_dpram_32x32.v)
//`define OR1200_RFRAM_DUALPORT
//
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
`define OR1200_RFRAM_GENERIC
//
// Type of mem2reg aligner to implement.
//
// Once OR1200_IMPL_MEM2REG2 yielded faster
// circuit, however with today tools it will
// most probably give you slower circuit.
//
`define OR1200_IMPL_MEM2REG1
//`define OR1200_IMPL_MEM2REG2
//
// ALUOPs
//
`define OR1200_ALUOP_WIDTH 4
`define OR1200_ALUOP_NOP 4'd4
/* Order defined by arith insns that have two source operands both in regs
(see binutils/include/opcode/or32.h) */
`define OR1200_ALUOP_ADD 4'd0
`define OR1200_ALUOP_ADDC 4'd1
`define OR1200_ALUOP_SUB 4'd2
`define OR1200_ALUOP_AND 4'd3
`define OR1200_ALUOP_OR 4'd4
`define OR1200_ALUOP_XOR 4'd5
`define OR1200_ALUOP_MUL 4'd6
`define OR1200_ALUOP_CUST5 4'd7
`define OR1200_ALUOP_SHROT 4'd8
`define OR1200_ALUOP_DIV 4'd9
`define OR1200_ALUOP_DIVU 4'd10
/* Order not specifically defined. */
`define OR1200_ALUOP_IMM 4'd11
`define OR1200_ALUOP_MOVHI 4'd12
`define OR1200_ALUOP_COMP 4'd13
`define OR1200_ALUOP_MTSR 4'd14
`define OR1200_ALUOP_MFSR 4'd15
`define OR1200_ALUOP_CMOV 4'd14
`define OR1200_ALUOP_FF1 4'd15
//
// MACOPs
//
`define OR1200_MACOP_WIDTH 2
`define OR1200_MACOP_NOP 2'b00
`define OR1200_MACOP_MAC 2'b01
`define OR1200_MACOP_MSB 2'b10
//
// Shift/rotate ops
//
`define OR1200_SHROTOP_WIDTH 2
`define OR1200_SHROTOP_NOP 2'd0
`define OR1200_SHROTOP_SLL 2'd0
`define OR1200_SHROTOP_SRL 2'd1
`define OR1200_SHROTOP_SRA 2'd2
`define OR1200_SHROTOP_ROR 2'd3
// Execution cycles per instruction
`define OR1200_MULTICYCLE_WIDTH 2
`define OR1200_ONE_CYCLE 2'd0
`define OR1200_TWO_CYCLES 2'd1
// Operand MUX selects
`define OR1200_SEL_WIDTH 2
`define OR1200_SEL_RF 2'd0
`define OR1200_SEL_IMM 2'd1
`define OR1200_SEL_EX_FORW 2'd2
`define OR1200_SEL_WB_FORW 2'd3
//
// BRANCHOPs
//
`define OR1200_BRANCHOP_WIDTH 3
`define OR1200_BRANCHOP_NOP 3'd0
`define OR1200_BRANCHOP_J 3'd1
`define OR1200_BRANCHOP_JR 3'd2
`define OR1200_BRANCHOP_BAL 3'd3
`define OR1200_BRANCHOP_BF 3'd4
`define OR1200_BRANCHOP_BNF 3'd5
`define OR1200_BRANCHOP_RFE 3'd6
//
// LSUOPs
//
// Bit 0: sign extend
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
// Bit 3: 0 load, 1 store
`define OR1200_LSUOP_WIDTH 4
`define OR1200_LSUOP_NOP 4'b0000
`define OR1200_LSUOP_LBZ 4'b0010
`define OR1200_LSUOP_LBS 4'b0011
`define OR1200_LSUOP_LHZ 4'b0100
`define OR1200_LSUOP_LHS 4'b0101
`define OR1200_LSUOP_LWZ 4'b0110
`define OR1200_LSUOP_LWS 4'b0111
`define OR1200_LSUOP_LD 4'b0001
`define OR1200_LSUOP_SD 4'b1000
`define OR1200_LSUOP_SB 4'b1010
`define OR1200_LSUOP_SH 4'b1100
`define OR1200_LSUOP_SW 4'b1110
// FETCHOPs
`define OR1200_FETCHOP_WIDTH 1
`define OR1200_FETCHOP_NOP 1'b0
`define OR1200_FETCHOP_LW 1'b1
//
// Register File Write-Back OPs
//
// Bit 0: register file write enable
// Bits 2-1: write-back mux selects
`define OR1200_RFWBOP_WIDTH 3
`define OR1200_RFWBOP_NOP 3'b000
`define OR1200_RFWBOP_ALU 3'b001
`define OR1200_RFWBOP_LSU 3'b011
`define OR1200_RFWBOP_SPRS 3'b101
`define OR1200_RFWBOP_LR 3'b111
// Compare instructions
`define OR1200_COP_SFEQ 3'b000
`define OR1200_COP_SFNE 3'b001
`define OR1200_COP_SFGT 3'b010
`define OR1200_COP_SFGE 3'b011
`define OR1200_COP_SFLT 3'b100
`define OR1200_COP_SFLE 3'b101
`define OR1200_COP_X 3'b111
`define OR1200_SIGNED_COMPARE 'd3
`define OR1200_COMPOP_WIDTH 4
//
// TAGs for instruction bus
//
`define OR1200_ITAG_IDLE 4'h0 // idle bus
`define OR1200_ITAG_NI 4'h1 // normal insn
`define OR1200_ITAG_BE 4'hb // Bus error exception
`define OR1200_ITAG_PE 4'hc // Page fault exception
`define OR1200_ITAG_TE 4'hd // TLB miss exception
//
// TAGs for data bus
//
`define OR1200_DTAG_IDLE 4'h0 // idle bus
`define OR1200_DTAG_ND 4'h1 // normal data
`define OR1200_DTAG_AE 4'ha // Alignment exception
`define OR1200_DTAG_BE 4'hb // Bus error exception
`define OR1200_DTAG_PE 4'hc // Page fault exception
`define OR1200_DTAG_TE 4'hd // TLB miss exception
//////////////////////////////////////////////
//
// ORBIS32 ISA specifics
//
// SHROT_OP position in machine word
`define OR1200_SHROTOP_POS 7:6
// ALU instructions multicycle field in machine word
`define OR1200_ALUMCYC_POS 9:8
//
// Instruction opcode groups (basic)
//
`define OR1200_OR32_J 6'b000000
`define OR1200_OR32_JAL 6'b000001
`define OR1200_OR32_BNF 6'b000011
`define OR1200_OR32_BF 6'b000100
`define OR1200_OR32_NOP 6'b000101
`define OR1200_OR32_MOVHI 6'b000110
`define OR1200_OR32_XSYNC 6'b001000
`define OR1200_OR32_RFE 6'b001001
/* */
`define OR1200_OR32_JR 6'b010001
`define OR1200_OR32_JALR 6'b010010
`define OR1200_OR32_MACI 6'b010011
/* */
`define OR1200_OR32_LWZ 6'b100001
`define OR1200_OR32_LBZ 6'b100011
`define OR1200_OR32_LBS 6'b100100
`define OR1200_OR32_LHZ 6'b100101
`define OR1200_OR32_LHS 6'b100110
`define OR1200_OR32_ADDI 6'b100111
`define OR1200_OR32_ADDIC 6'b101000
`define OR1200_OR32_ANDI 6'b101001
`define OR1200_OR32_ORI 6'b101010
`define OR1200_OR32_XORI 6'b101011
`define OR1200_OR32_MULI 6'b101100
`define OR1200_OR32_MFSPR 6'b101101
`define OR1200_OR32_SH_ROTI 6'b101110
`define OR1200_OR32_SFXXI 6'b101111
/* */
`define OR1200_OR32_MTSPR 6'b110000
`define OR1200_OR32_MACMSB 6'b110001
/* */
`define OR1200_OR32_SW 6'b110101
`define OR1200_OR32_SB 6'b110110
`define OR1200_OR32_SH 6'b110111
`define OR1200_OR32_ALU 6'b111000
`define OR1200_OR32_SFXX 6'b111001
//`define OR1200_OR32_CUST5 6'b111100
/////////////////////////////////////////////////////
//
// Exceptions
//
//
// Exception vectors per OR1K architecture:
// 0xPPPPP100 - reset
// 0xPPPPP200 - bus error
// ... etc
// where P represents exception prefix.
//
// Exception vectors can be customized as per
// the following formula:
// 0xPPPPPNVV - exception N
//
// P represents exception prefix
// N represents exception N
// VV represents length of the individual vector space,
// usually it is 8 bits wide and starts with all bits zero
//
//
// PPPPP and VV parts
//
// Sum of these two defines needs to be 28
//
`define OR1200_EXCEPT_EPH0_P 20'h00000
`define OR1200_EXCEPT_EPH1_P 20'hF0000
`define OR1200_EXCEPT_V 8'h00
//
// N part width
//
`define OR1200_EXCEPT_WIDTH 4
//
// Definition of exception vectors
//
// To avoid implementation of a certain exception,
// simply comment out corresponding line
//
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd
`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc
`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7
`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6
`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5
`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4
`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3
`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2
`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1
`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0
/////////////////////////////////////////////////////
//
// SPR groups
//
// Bits that define the group
`define OR1200_SPR_GROUP_BITS 15:11
// Width of the group bits
`define OR1200_SPR_GROUP_WIDTH 5
// Bits that define offset inside the group
`define OR1200_SPR_OFS_BITS 10:0
// List of groups
`define OR1200_SPR_GROUP_SYS 5'd00
`define OR1200_SPR_GROUP_DMMU 5'd01
`define OR1200_SPR_GROUP_IMMU 5'd02
`define OR1200_SPR_GROUP_DC 5'd03
`define OR1200_SPR_GROUP_IC 5'd04
`define OR1200_SPR_GROUP_MAC 5'd05
`define OR1200_SPR_GROUP_DU 5'd06
`define OR1200_SPR_GROUP_PM 5'd08
`define OR1200_SPR_GROUP_PIC 5'd09
`define OR1200_SPR_GROUP_TT 5'd10
/////////////////////////////////////////////////////
//
// System group
//
//
// System registers
//
`define OR1200_SPR_CFGR 7'd0
`define OR1200_SPR_RF 6'd32 // 1024 >> 5
`define OR1200_SPR_NPC 11'd16
`define OR1200_SPR_SR 11'd17
`define OR1200_SPR_PPC 11'd18
`define OR1200_SPR_EPCR 11'd32
`define OR1200_SPR_EEAR 11'd48
`define OR1200_SPR_ESR 11'd64
//
// SR bits
//
`define OR1200_SR_WIDTH 16
`define OR1200_SR_SM 0
`define OR1200_SR_TEE 1
`define OR1200_SR_IEE 2
`define OR1200_SR_DCE 3
`define OR1200_SR_ICE 4
`define OR1200_SR_DME 5
`define OR1200_SR_IME 6
`define OR1200_SR_LEE 7
`define OR1200_SR_CE 8
`define OR1200_SR_F 9
`define OR1200_SR_CY 10 // Unused
`define OR1200_SR_OV 11 // Unused
`define OR1200_SR_OVE 12 // Unused
`define OR1200_SR_DSX 13 // Unused
`define OR1200_SR_EPH 14
`define OR1200_SR_FO 15
`define OR1200_SR_CID 31:28 // Unimplemented
//
// Bits that define offset inside the group
//
`define OR1200_SPROFS_BITS 10:0
//
// Default Exception Prefix
//
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
//
`define OR1200_SR_EPH_DEF 1'b0
/////////////////////////////////////////////////////
//
// Power Management (PM)
//
// Define it if you want PM implemented
`define OR1200_PM_IMPLEMENTED
// Bit positions inside PMR (don't change)
`define OR1200_PM_PMR_SDF 3:0
`define OR1200_PM_PMR_DME 4
`define OR1200_PM_PMR_SME 5
`define OR1200_PM_PMR_DCGE 6
`define OR1200_PM_PMR_UNUSED 31:7
// PMR offset inside PM group of registers
`define OR1200_PM_OFS_PMR 11'b0
// PM group
`define OR1200_SPRGRP_PM 5'd8
// Define if PMR can be read/written at any address inside PM group
`define OR1200_PM_PARTIAL_DECODING
// Define if reading PMR is allowed
`define OR1200_PM_READREGS
// Define if unused PMR bits should be zero
`define OR1200_PM_UNUSED_ZERO
/////////////////////////////////////////////////////
//
// Debug Unit (DU)
//
// Define it if you want DU implemented
`define OR1200_DU_IMPLEMENTED
//
// Define if you want HW Breakpoints
// (if HW breakpoints are not implemented
// only default software trapping is
// possible with l.trap insn - this is
// however already enough for use
// with or32 gdb)
//
`define OR1200_DU_HWBKPTS
// Number of DVR/DCR pairs if HW breakpoints enabled
`define OR1200_DU_DVRDCR_PAIRS 8
// Define if you want trace buffer
//`define OR1200_DU_TB_IMPLEMENTED
//
// Address offsets of DU registers inside DU group
//
// To not implement a register, doq not define its address
//
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DVR0 11'd0
`define OR1200_DU_DVR1 11'd1
`define OR1200_DU_DVR2 11'd2
`define OR1200_DU_DVR3 11'd3
`define OR1200_DU_DVR4 11'd4
`define OR1200_DU_DVR5 11'd5
`define OR1200_DU_DVR6 11'd6
`define OR1200_DU_DVR7 11'd7
`define OR1200_DU_DCR0 11'd8
`define OR1200_DU_DCR1 11'd9
`define OR1200_DU_DCR2 11'd10
`define OR1200_DU_DCR3 11'd11
`define OR1200_DU_DCR4 11'd12
`define OR1200_DU_DCR5 11'd13
`define OR1200_DU_DCR6 11'd14
`define OR1200_DU_DCR7 11'd15
`endif
`define OR1200_DU_DMR1 11'd16
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DMR2 11'd17
`define OR1200_DU_DWCR0 11'd18
`define OR1200_DU_DWCR1 11'd19
`endif
`define OR1200_DU_DSR 11'd20
`define OR1200_DU_DRR 11'd21
`ifdef OR1200_DU_TB_IMPLEMENTED
`define OR1200_DU_TBADR 11'h0ff
`define OR1200_DU_TBIA 11'h1xx
`define OR1200_DU_TBIM 11'h2xx
`define OR1200_DU_TBAR 11'h3xx
`define OR1200_DU_TBTS 11'h4xx
`endif
// Position of offset bits inside SPR address
`define OR1200_DUOFS_BITS 10:0
// DCR bits
`define OR1200_DU_DCR_DP 0
`define OR1200_DU_DCR_CC 3:1
`define OR1200_DU_DCR_SC 4
`define OR1200_DU_DCR_CT 7:5
// DMR1 bits
`define OR1200_DU_DMR1_CW0 1:0
`define OR1200_DU_DMR1_CW1 3:2
`define OR1200_DU_DMR1_CW2 5:4
`define OR1200_DU_DMR1_CW3 7:6
`define OR1200_DU_DMR1_CW4 9:8
`define OR1200_DU_DMR1_CW5 11:10
`define OR1200_DU_DMR1_CW6 13:12
`define OR1200_DU_DMR1_CW7 15:14
`define OR1200_DU_DMR1_CW8 17:16
`define OR1200_DU_DMR1_CW9 19:18
`define OR1200_DU_DMR1_CW10 21:20
`define OR1200_DU_DMR1_ST 22
`define OR1200_DU_DMR1_BT 23
`define OR1200_DU_DMR1_DXFW 24
`define OR1200_DU_DMR1_ETE 25
// DMR2 bits
`define OR1200_DU_DMR2_WCE0 0
`define OR1200_DU_DMR2_WCE1 1
`define OR1200_DU_DMR2_AWTC 12:2
`define OR1200_DU_DMR2_WGB 23:13
// DWCR bits
`define OR1200_DU_DWCR_COUNT 15:0
`define OR1200_DU_DWCR_MATCH 31:16
// DSR bits
`define OR1200_DU_DSR_WIDTH 14
`define OR1200_DU_DSR_RSTE 0
`define OR1200_DU_DSR_BUSEE 1
`define OR1200_DU_DSR_DPFE 2
`define OR1200_DU_DSR_IPFE 3
`define OR1200_DU_DSR_TTE 4
`define OR1200_DU_DSR_AE 5
`define OR1200_DU_DSR_IIE 6
`define OR1200_DU_DSR_IE 7
`define OR1200_DU_DSR_DME 8
`define OR1200_DU_DSR_IME 9
`define OR1200_DU_DSR_RE 10
`define OR1200_DU_DSR_SCE 11
`define OR1200_DU_DSR_BE 12
`define OR1200_DU_DSR_TE 13
// DRR bits
`define OR1200_DU_DRR_RSTE 0
`define OR1200_DU_DRR_BUSEE 1
`define OR1200_DU_DRR_DPFE 2
`define OR1200_DU_DRR_IPFE 3
`define OR1200_DU_DRR_TTE 4
`define OR1200_DU_DRR_AE 5
`define OR1200_DU_DRR_IIE 6
`define OR1200_DU_DRR_IE 7
`define OR1200_DU_DRR_DME 8
`define OR1200_DU_DRR_IME 9
`define OR1200_DU_DRR_RE 10
`define OR1200_DU_DRR_SCE 11
`define OR1200_DU_DRR_BE 12
`define OR1200_DU_DRR_TE 13
// Define if reading DU regs is allowed
`define OR1200_DU_READREGS
// Define if unused DU registers bits should be zero
`define OR1200_DU_UNUSED_ZERO
// Define if IF/LSU status is not needed by devel i/f
`define OR1200_DU_STATUS_UNIMPLEMENTED
/////////////////////////////////////////////////////
//
// Programmable Interrupt Controller (PIC)
//
// Define it if you want PIC implemented
`define OR1200_PIC_IMPLEMENTED
// Define number of interrupt inputs (2-31)
`define OR1200_PIC_INTS 20
// Address offsets of PIC registers inside PIC group
`define OR1200_PIC_OFS_PICMR 2'd0
`define OR1200_PIC_OFS_PICSR 2'd2
// Position of offset bits inside SPR address
`define OR1200_PICOFS_BITS 1:0
// Define if you want these PIC registers to be implemented
`define OR1200_PIC_PICMR
`define OR1200_PIC_PICSR
// Define if reading PIC registers is allowed
`define OR1200_PIC_READREGS
// Define if unused PIC register bits should be zero
`define OR1200_PIC_UNUSED_ZERO
/////////////////////////////////////////////////////
//
// Tick Timer (TT)
//
// Define it if you want TT implemented
`define OR1200_TT_IMPLEMENTED
// Address offsets of TT registers inside TT group
`define OR1200_TT_OFS_TTMR 1'd0
`define OR1200_TT_OFS_TTCR 1'd1
// Position of offset bits inside SPR group
`define OR1200_TTOFS_BITS 0
// Define if you want these TT registers to be implemented
`define OR1200_TT_TTMR
`define OR1200_TT_TTCR
// TTMR bits
`define OR1200_TT_TTMR_TP 27:0
`define OR1200_TT_TTMR_IP 28
`define OR1200_TT_TTMR_IE 29
`define OR1200_TT_TTMR_M 31:30
// Define if reading TT registers is allowed
`define OR1200_TT_READREGS
//////////////////////////////////////////////
//
// MAC
//
`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable
//////////////////////////////////////////////
//
// Data MMU (DMMU)
//
//
// Address that selects between TLB TR and MR
//
`define OR1200_DTLB_TM_ADDR 7
//
// DTLBMR fields
//
`define OR1200_DTLBMR_V_BITS 0
`define OR1200_DTLBMR_CID_BITS 4:1
`define OR1200_DTLBMR_RES_BITS 11:5
`define OR1200_DTLBMR_VPN_BITS 31:13
//
// DTLBTR fields
//
`define OR1200_DTLBTR_CC_BITS 0
`define OR1200_DTLBTR_CI_BITS 1
`define OR1200_DTLBTR_WBC_BITS 2
`define OR1200_DTLBTR_WOM_BITS 3
`define OR1200_DTLBTR_A_BITS 4
`define OR1200_DTLBTR_D_BITS 5
`define OR1200_DTLBTR_URE_BITS 6
`define OR1200_DTLBTR_UWE_BITS 7
`define OR1200_DTLBTR_SRE_BITS 8
`define OR1200_DTLBTR_SWE_BITS 9
`define OR1200_DTLBTR_RES_BITS 11:10
`define OR1200_DTLBTR_PPN_BITS 31:13
//
// DTLB configuration
//
`define OR1200_DMMU_PS 13 // 13 for 8KB page size
`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries
`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13
`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19
`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13
`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12
`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20
`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20
`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit
`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI
//
// Cache inhibit while DMMU is not enabled/implemented
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !dcpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30]
// cache inhibited 2GB-4GB (default) dcpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_DMMU_CI dcpu_adr_i[31]
//////////////////////////////////////////////
//
// Insn MMU (IMMU)
//
//
// Address that selects between TLB TR and MR
//
`define OR1200_ITLB_TM_ADDR 7
//
// ITLBMR fields
//
`define OR1200_ITLBMR_V_BITS 0
`define OR1200_ITLBMR_CID_BITS 4:1
`define OR1200_ITLBMR_RES_BITS 11:5
`define OR1200_ITLBMR_VPN_BITS 31:13
//
// ITLBTR fields
//
`define OR1200_ITLBTR_CC_BITS 0
`define OR1200_ITLBTR_CI_BITS 1
`define OR1200_ITLBTR_WBC_BITS 2
`define OR1200_ITLBTR_WOM_BITS 3
`define OR1200_ITLBTR_A_BITS 4
`define OR1200_ITLBTR_D_BITS 5
`define OR1200_ITLBTR_SXE_BITS 6
`define OR1200_ITLBTR_UXE_BITS 7
`define OR1200_ITLBTR_RES_BITS 11:8
`define OR1200_ITLBTR_PPN_BITS 31:13
//
// ITLB configuration
//
`define OR1200_IMMU_PS 13 // 13 for 8KB page size
`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries
`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13
`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19
`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13
`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12
`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20
`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20
`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit
`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI
//
// Cache inhibit while IMMU is not enabled/implemented
// Note: all combinations that use icpu_adr_i cause async loop
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !icpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30]
// cache inhibited 2GB-4GB (default) icpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_IMMU_CI 1'b0
/////////////////////////////////////////////////
//
// Insn cache (IC)
//
// 3 for 8 bytes, 4 for 16 bytes etc
`define OR1200_ICLS 4
//
// IC configurations
//
`ifdef OR1200_IC_1W_512B
`define OR1200_ICSIZE 9 // 512
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5
`define OR1200_ICTAG_W 24
`endif
`ifdef OR1200_IC_1W_4KB
`define OR1200_ICSIZE 12 // 4096
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8
`define OR1200_ICTAG_W 21
`endif
`ifdef OR1200_IC_1W_8KB
`define OR1200_ICSIZE 13 // 8192
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
`define OR1200_ICTAG_W 20
`endif
/////////////////////////////////////////////////
//
// Data cache (DC)
//
// 3 for 8 bytes, 4 for 16 bytes etc
`define OR1200_DCLS 4
// Define to perform store refill (potential performance penalty)
// `define OR1200_DC_STORE_REFILL
//
// DC configurations
//
`ifdef OR1200_DC_1W_4KB
`define OR1200_DCSIZE 12 // 4096
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8
`define OR1200_DCTAG_W 21
`endif
`ifdef OR1200_DC_1W_8KB
`define OR1200_DCSIZE 13 // 8192
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
`define OR1200_DCTAG_W 20
`endif
/////////////////////////////////////////////////
//
// Store buffer (SB)
//
//
// Store buffer
//
// It will improve performance by "caching" CPU stores
// using store buffer. This is most important for function
// prologues because DC can only work in write though mode
// and all stores would have to complete external WB writes
// to memory.
// Store buffer is between DC and data BIU.
// All stores will be stored into store buffer and immediately
// completed by the CPU, even though actual external writes
// will be performed later. As a consequence store buffer masks
// all data bus errors related to stores (data bus errors
// related to loads are delivered normally).
// All pending CPU loads will wait until store buffer is empty to
// ensure strict memory model. Right now this is necessary because
// we don't make destinction between cached and cache inhibited
// address space, so we simply empty store buffer until loads
// can begin.
//
// It makes design a bit bigger, depending what is the number of
// entries in SB FIFO. Number of entries can be changed further
// down.
//
//`define OR1200_SB_IMPLEMENTED
//
// Number of store buffer entries
//
// Verified number of entries are 4 and 8 entries
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
// always match 2**OR1200_SB_LOG.
// To disable store buffer, undefine
// OR1200_SB_IMPLEMENTED.
//
`define OR1200_SB_LOG 2 // 2 or 3
`define OR1200_SB_ENTRIES 4 // 4 or 8
/////////////////////////////////////////////////
//
// Quick Embedded Memory (QMEM)
//
//
// Quick Embedded Memory
//
// Instantiation of dedicated insn/data memory (RAM or ROM).
// Insn fetch has effective throughput 1insn / clock cycle.
// Data load takes two clock cycles / access, data store
// takes 1 clock cycle / access (if there is no insn fetch)).
// Memory instantiation is shared between insn and data,
// meaning if insn fetch are performed, data load/store
// performance will be lower.
//
// Main reason for QMEM is to put some time critical functions
// into this memory and to have predictable and fast access
// to these functions. (soft fpu, context switch, exception
// handlers, stack, etc)
//
// It makes design a bit bigger and slower. QMEM sits behind
// IMMU/DMMU so all addresses are physical (so the MMUs can be
// used with QMEM and QMEM is seen by the CPU just like any other
// memory in the system). IC/DC are sitting behind QMEM so the
// whole design timing might be worse with QMEM implemented.
//
//`define OR1200_QMEM_IMPLEMENTED -- Disabled by WJP !!!
//
// Base address and mask of QMEM
//
// Base address defines first address of QMEM. Mask defines
// QMEM range in address space. Actual size of QMEM is however
// determined with instantiated RAM/ROM. However bigger
// mask will reserve more address space for QMEM, but also
// make design faster, while more tight mask will take
// less address space but also make design slower. If
// instantiated RAM/ROM is smaller than space reserved with
// the mask, instatiated RAM/ROM will also be shadowed
// at higher addresses in reserved space.
//
//`define OR1200_QMEM_IADDR 32'h0080_0000 -- Disabled by WJP !!!
//`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB -- Disabled by WJP !!!
//`define OR1200_QMEM_DADDR 32'h0080_0000 -- Disabled by WJP !!!
//`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB -- Disabled by WJP !!!
//
// QMEM interface byte-select capability
//
// To enable qmem_sel* ports, define this macro.
//
//`define OR1200_QMEM_BSEL
//
// QMEM interface acknowledge
//
// To enable qmem_ack port, define this macro.
//
//`define OR1200_QMEM_ACK
/////////////////////////////////////////////////////
//
// VR, UPR and Configuration Registers
//
//
// VR, UPR and configuration registers are optional. If
// implemented, operating system can automatically figure
// out how to use the processor because it knows
// what units are available in the processor and how they
// are configured.
//
// This section must be last in or1200_defines.v file so
// that all units are already configured and thus
// configuration registers are properly set.
//
// Define if you want configuration registers implemented
`define OR1200_CFGR_IMPLEMENTED
// Define if you want full address decode inside SYS group
`define OR1200_SYS_FULL_DECODE
// Offsets of VR, UPR and CFGR registers
`define OR1200_SPRGRP_SYS_VR 4'h0
`define OR1200_SPRGRP_SYS_UPR 4'h1
`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2
`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3
`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4
`define OR1200_SPRGRP_SYS_DCCFGR 4'h5
`define OR1200_SPRGRP_SYS_ICCFGR 4'h6
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
// VR fields
`define OR1200_VR_REV_BITS 5:0
`define OR1200_VR_RES1_BITS 15:6
`define OR1200_VR_CFG_BITS 23:16
`define OR1200_VR_REV_BITS 5:0
`define OR1200_VR_VER_BITS 31:24
// VR values
`define OR1200_VR_REV 6'h01
`define OR1200_VR_RES1 10'h000
`define OR1200_VR_CFG 8'h00
`define OR1200_VR_VER 8'h12
// UPR fields
`define OR1200_UPR_UP_BITS 0
`define OR1200_UPR_DCP_BITS 1
`define OR1200_UPR_ICP_BITS 2
`define OR1200_UPR_DMP_BITS 3
`define OR1200_UPR_IMP_BITS 4
`define OR1200_UPR_MP_BITS 5
`define OR1200_UPR_DUP_BITS 6
`define OR1200_UPR_PCUP_BITS 7
`define OR1200_UPR_PMP_BITS 8
`define OR1200_UPR_PICP_BITS 9
`define OR1200_UPR_TTP_BITS 10
`define OR1200_UPR_RES1_BITS 23:11
`define OR1200_UPR_CUP_BITS 31:24
// UPR values
`define OR1200_UPR_UP 1'b1
`ifdef OR1200_NO_DC
`define OR1200_UPR_DCP 1'b0
`else
`define OR1200_UPR_DCP 1'b1
`endif
`ifdef OR1200_NO_IC
`define OR1200_UPR_ICP 1'b0
`else
`define OR1200_UPR_ICP 1'b1
`endif
`ifdef OR1200_NO_DMMU
`define OR1200_UPR_DMP 1'b0
`else
`define OR1200_UPR_DMP 1'b1
`endif
`ifdef OR1200_NO_IMMU
`define OR1200_UPR_IMP 1'b0
`else
`define OR1200_UPR_IMP 1'b1
`endif
`define OR1200_UPR_MP 1'b1 // MAC always present
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_DUP 1'b1
`else
`define OR1200_UPR_DUP 1'b0
`endif
`define OR1200_UPR_PCUP 1'b0 // Performance counters not present
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_PMP 1'b1
`else
`define OR1200_UPR_PMP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_PICP 1'b1
`else
`define OR1200_UPR_PICP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_TTP 1'b1
`else
`define OR1200_UPR_TTP 1'b0
`endif
`define OR1200_UPR_RES1 13'h0000
`define OR1200_UPR_CUP 8'h00
// CPUCFGR fields
`define OR1200_CPUCFGR_NSGF_BITS 3:0
`define OR1200_CPUCFGR_HGF_BITS 4
`define OR1200_CPUCFGR_OB32S_BITS 5
`define OR1200_CPUCFGR_OB64S_BITS 6
`define OR1200_CPUCFGR_OF32S_BITS 7
`define OR1200_CPUCFGR_OF64S_BITS 8
`define OR1200_CPUCFGR_OV64S_BITS 9
`define OR1200_CPUCFGR_RES1_BITS 31:10
// CPUCFGR values
`define OR1200_CPUCFGR_NSGF 4'h0
`define OR1200_CPUCFGR_HGF 1'b0
`define OR1200_CPUCFGR_OB32S 1'b1
`define OR1200_CPUCFGR_OB64S 1'b0
`define OR1200_CPUCFGR_OF32S 1'b0
`define OR1200_CPUCFGR_OF64S 1'b0
`define OR1200_CPUCFGR_OV64S 1'b0
`define OR1200_CPUCFGR_RES1 22'h000000
// DMMUCFGR fields
`define OR1200_DMMUCFGR_NTW_BITS 1:0
`define OR1200_DMMUCFGR_NTS_BITS 4:2
`define OR1200_DMMUCFGR_NAE_BITS 7:5
`define OR1200_DMMUCFGR_CRI_BITS 8
`define OR1200_DMMUCFGR_PRI_BITS 9
`define OR1200_DMMUCFGR_TEIRI_BITS 10
`define OR1200_DMMUCFGR_HTR_BITS 11
`define OR1200_DMMUCFGR_RES1_BITS 31:12
// DMMUCFGR values
`ifdef OR1200_NO_DMMU
`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_RES1 20'h00000
`else
`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl.
`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_DMMUCFGR_RES1 20'h00000
`endif
// IMMUCFGR fields
`define OR1200_IMMUCFGR_NTW_BITS 1:0
`define OR1200_IMMUCFGR_NTS_BITS 4:2
`define OR1200_IMMUCFGR_NAE_BITS 7:5
`define OR1200_IMMUCFGR_CRI_BITS 8
`define OR1200_IMMUCFGR_PRI_BITS 9
`define OR1200_IMMUCFGR_TEIRI_BITS 10
`define OR1200_IMMUCFGR_HTR_BITS 11
`define OR1200_IMMUCFGR_RES1_BITS 31:12
// IMMUCFGR values
`ifdef OR1200_NO_IMMU
`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_RES1 20'h00000
`else
`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl
`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_IMMUCFGR_RES1 20'h00000
`endif
// DCCFGR fields
`define OR1200_DCCFGR_NCW_BITS 2:0
`define OR1200_DCCFGR_NCS_BITS 6:3
`define OR1200_DCCFGR_CBS_BITS 7
`define OR1200_DCCFGR_CWS_BITS 8
`define OR1200_DCCFGR_CCRI_BITS 9
`define OR1200_DCCFGR_CBIRI_BITS 10
`define OR1200_DCCFGR_CBPRI_BITS 11
`define OR1200_DCCFGR_CBLRI_BITS 12
`define OR1200_DCCFGR_CBFRI_BITS 13
`define OR1200_DCCFGR_CBWBRI_BITS 14
`define OR1200_DCCFGR_RES1_BITS 31:15
// DCCFGR values
`ifdef OR1200_NO_DC
`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant
`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant
`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CCRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBIRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBFRI 1'b1 // Irrelevant
`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_RES1 17'h00000
`else
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl.
`define OR1200_DCCFGR_RES1 17'h00000
`endif
// ICCFGR fields
`define OR1200_ICCFGR_NCW_BITS 2:0
`define OR1200_ICCFGR_NCS_BITS 6:3
`define OR1200_ICCFGR_CBS_BITS 7
`define OR1200_ICCFGR_CWS_BITS 8
`define OR1200_ICCFGR_CCRI_BITS 9
`define OR1200_ICCFGR_CBIRI_BITS 10
`define OR1200_ICCFGR_CBPRI_BITS 11
`define OR1200_ICCFGR_CBLRI_BITS 12
`define OR1200_ICCFGR_CBFRI_BITS 13
`define OR1200_ICCFGR_CBWBRI_BITS 14
`define OR1200_ICCFGR_RES1_BITS 31:15
// ICCFGR values
`ifdef OR1200_NO_IC
`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant
`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant
`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`else
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`endif
// DCFGR fields
`define OR1200_DCFGR_NDP_BITS 2:0
`define OR1200_DCFGR_WPCI_BITS 3
`define OR1200_DCFGR_RES1_BITS 31:4
// DCFGR values
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DCFGR_NDP 3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
`ifdef OR1200_DU_DWCR0
`define OR1200_DCFGR_WPCI 1'b1
`else
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`else
`define OR1200_DCFGR_NDP 3'h0 // Zero DVR/DCR pairs
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`define OR1200_DCFGR_RES1 28'h0000000
|
/*
* Titor - System - Minimal system to test the underlying processor
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_FSM_VGA
`else
`define INC_FSM_VGA
`timescale 1 ns / 100 ps
module FSM_VGA(
VGA_hsync,
VGA_vsync,
pixel_blank,
screen_row, screen_column,
reset,
clk
);
`include "definition/Definition.v"
output VGA_hsync;
output VGA_vsync;
output pixel_blank;
input clk;
input reset;
reg [WORD-1:0] pixel_row;
reg [WORD-1:0] pixel_column;
output wire [WORD-1:0] screen_row;
output wire [WORD-1:0] screen_column;
reg [WORD-1:0] state_vertical;
reg [WORD-1:0] state_horizontal;
wire active_row;
wire active_column;
wire [WORD-1:0] division;
// these values are simply doubled because I don't care about proper clock domains if the screen will still work
// some necessary constants for the 640 X 480 controller
localparam PIXEL_H = SCREEN_WIDTH,
PIXEL_V = SCREEN_HEIGHT,
FRONT_PORCH_H = 16,
FRONT_PORCH_V = 10,
PULSE_H = 96,
PULSE_V = 2,
BACK_PORCH_H = 48,
BACK_PORCH_V = 29;
localparam SYNC_H = (PIXEL_H + FRONT_PORCH_H + PULSE_H + BACK_PORCH_H),
SYNC_V = (PIXEL_V + FRONT_PORCH_V + PULSE_V + BACK_PORCH_V);
localparam MODE_0_H = 0,
MODE_0_V = 0,
MODE_1_H = MODE_0_H + PIXEL_H,
MODE_1_V = MODE_0_V + PIXEL_V,
MODE_2_H = MODE_1_H + FRONT_PORCH_H,
MODE_2_V = MODE_1_V + FRONT_PORCH_V,
MODE_3_H = MODE_2_H + PULSE_H,
MODE_3_V = MODE_2_V + PULSE_V;
localparam STATE_PIXEL = 0,
STATE_FRONT_PORCH = 1,
STATE_PULSE = 2,
STATE_BACK_PORCH = 3;
assign pixel_blank = !((state_horizontal == STATE_PIXEL) && (state_vertical == STATE_PIXEL));
assign VGA_hsync = !(state_horizontal==STATE_PULSE);
assign VGA_vsync = !(state_vertical ==STATE_PULSE);
// the "real" position of the electron gun
// these positions truly indicate what position is being displayed so long as pixel_blank is false
// otherwise the positions are invalid
always @(*) begin
if(state_vertical == STATE_PIXEL) pixel_row <= screen_row;
else pixel_row <= 0;
if(state_horizontal == STATE_PIXEL) pixel_column <= screen_column;
else pixel_column <= 0;
end
// VGA state-like classification machine
// this has two pieces that take in counters (specifically radix counters) and pop out a state based on them
always @(*) begin
if(screen_column < MODE_1_H) state_horizontal <= STATE_PIXEL;
else if(screen_column < MODE_2_H) state_horizontal <= STATE_FRONT_PORCH;
else if(screen_column < MODE_3_H) state_horizontal <= STATE_PULSE;
else state_horizontal <= STATE_BACK_PORCH;
if(screen_row < MODE_1_V) state_vertical <= STATE_PIXEL;
else if(screen_row < MODE_2_V) state_vertical <= STATE_FRONT_PORCH;
else if(screen_row < MODE_3_V) state_vertical <= STATE_PULSE;
else state_vertical <= STATE_BACK_PORCH;
end
wire [4-1:0] carry;
assign carry[0] = 1;
// chain of radix counters: screen_row <- screen column <- clock divide
Radix_Counter #(SYNC_V) counter_screen_row(
.carry_in(carry[2]),
.carry_out(carry[3]),
.count(screen_row),
.reset(reset),
.clk(clk)
);
Radix_Counter #(SYNC_H) counter_screen_column(
.carry_in(carry[1]),
.carry_out(carry[2]),
.count(screen_column),
.reset(reset),
.clk(clk)
);
Radix_Counter #(VGA_SLOW) counter_divide(
.carry_in(carry[0]),
.carry_out(carry[1]),
.count(division),
.reset(reset),
.clk(clk)
);
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4B_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR4B_BLACKBOX_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4B_BLACKBOX_V
|
`default_nettype none
// ============================================================================
module iserdes_sdr_ddr_test #
(
parameter DATA_WIDTH = 8,
parameter DATA_RATE = "SDR"
)
(
// Clock and reset
input wire CLK,
input wire RST,
// Data pin
inout wire IO_DAT,
// Error indicator
output wire O_ERROR
);
// ============================================================================
// IOB
wire iob_o;
wire iob_i;
OBUFT obuf
(
.I (iob_o),
.T (1'b0),
.O (IO_DAT)
);
IBUF ibuf
(
.I (IO_DAT),
.O (iob_i)
);
// ============================================================================
wire tx_stb;
wire [DATA_WIDTH-1:0] tx_dat;
wire rx_stb;
wire [DATA_WIDTH-1:0] rx_dat;
wire rx_bitslip;
wire s_clk;
// Transmitter
transmitter #
(
.WIDTH (DATA_WIDTH),
.MODE (DATA_RATE)
)
transmitter
(
.CLK (CLK),
.RST (RST),
.O_STB (tx_stb),
.O_DAT (tx_dat),
.S_CLK (s_clk),
.S_DAT (iob_o)
);
// Receiver
receiver #
(
.WIDTH (DATA_WIDTH),
.MODE (DATA_RATE)
)
receiver
(
.CLK (CLK),
.RST (RST),
.I_CLK (s_clk),
.I_DAT (iob_i),
.O_STB (rx_stb),
.O_DAT (rx_dat),
.O_BITSLIP (rx_bitslip)
);
// The comparator module generates bitslip signal for the receiver. However
// the bitslip can shift only modulo DATA_WIDTH. Therefore additional delay is
// added which can delay the transmitted data that we compare to by a number
// of full words.
// Count bitslip pulses to know how much to delay words
reg [3:0] rx_bitslip_cnt;
always @(posedge CLK)
if (RST)
rx_bitslip_cnt <= 0;
else if (rx_bitslip) begin
if (rx_bitslip_cnt == (2*DATA_WIDTH - 1))
rx_bitslip_cnt <= 0;
else
rx_bitslip_cnt <= rx_bitslip_cnt + 1;
end
// Word delay
reg [1:0] tx_dly_cnt;
reg [DATA_WIDTH-1:0] tx_dat_dly_a;
reg [DATA_WIDTH-1:0] tx_dat_dly_b;
reg [DATA_WIDTH-1:0] tx_dat_dly_c;
reg [DATA_WIDTH-1:0] tx_dat_dly_d;
wire [DATA_WIDTH-1:0] tx_dat_dly;
always @(posedge CLK)
if (RST)
tx_dly_cnt <= 0;
else if(rx_bitslip && rx_bitslip_cnt == (2*DATA_WIDTH - 1))
tx_dly_cnt <= tx_dly_cnt + 1;
always @(posedge CLK)
if (tx_stb) begin
tx_dat_dly_d <= tx_dat_dly_c;
tx_dat_dly_c <= tx_dat_dly_b;
tx_dat_dly_b <= tx_dat_dly_a;
tx_dat_dly_a <= tx_dat;
end
assign tx_dat_dly = (tx_dly_cnt == 0) ? tx_dat_dly_a :
(tx_dly_cnt == 1) ? tx_dat_dly_b :
(tx_dly_cnt == 2) ? tx_dat_dly_c :
/*(tx_dly_cnt == 3) ?*/tx_dat_dly_d;
// Comparator
comparator #
(
.WIDTH (DATA_WIDTH)
)
comparator
(
.CLK (CLK),
.RST (RST),
.TX_STB (tx_stb),
.TX_DAT (tx_dat_dly),
.RX_STB (rx_stb),
.RX_DAT (rx_dat),
.RX_BITSLIP (rx_bitslip),
.O_ERROR (O_ERROR)
);
endmodule
|
Require Import List.
Require Import InfSeqExt.infseq.
Require Import InfSeqExt.map.
Require Import InfSeqExt.exteq.
Require Import StructTact.StructTactics.
Require Import StructTact.Util.
Require Import Cheerios.Cheerios.
Require Import Chord.Chord.
Require Import Chord.ChordSerialized.
Require Import Chord.ChordSerializedSimulations.
Require Import Chord.ChordCorrectPhaseOne.
Require Import Chord.SystemReachable.
Require Import Chord.SystemPointers.
Require Import Chord.QueriesEventuallyStop.
Definition serialize_occurrence (occ : ChordSemantics.occurrence) :=
{| occ_gst := serialize_global_state (ChordSemantics.occ_gst occ);
occ_label := (ChordSemantics.occ_label occ) |}.
Definition revert_occurrence (occ : ChordSerializedSemantics.occurrence) :=
{| ChordSemantics.occ_gst := revert_global_state (ChordSerializedSemantics.occ_gst occ);
ChordSemantics.occ_label := (ChordSerializedSemantics.occ_label occ) |}.
Definition revert_serialize_occurrence o :=
serialize_occurrence (revert_occurrence o).
Inductive reachable_st_serialized : global_state -> Prop :=
reachableInitS : forall gst,
initial_st (revert_global_state gst) -> reachable_st_serialized gst
| reachableStepS : forall gst gst',
reachable_st_serialized gst ->
ChordSerializedSemantics.step_dynamic gst gst' ->
reachable_st_serialized gst'.
Lemma revert_reachable : forall ex : infseq occurrence,
reachable_st_serialized (occ_gst (infseq.hd ex)) ->
reachable_st (ChordSemantics.occ_gst (infseq.hd (map revert_occurrence ex))).
Proof.
intros.
destruct ex.
simpl in *.
induction H.
- constructor.
assumption.
- eapply reachableStep; eauto.
apply step_dynamic_serialized_step_dynamic.
assumption.
Qed.
Lemma revert_lb_execution : forall ex,
lb_execution ex ->
ChordSemantics.lb_execution (map revert_occurrence ex).
Proof.
cofix.
intros.
do 2 (destruct ex; rewrite map_Cons).
constructor; inv H.
- apply serialized_labeled_step_labeled_step.
assumption.
- rewrite <- map_Cons.
apply revert_lb_execution.
assumption.
Qed.
Definition blocked_by (gst : global_state) (s h : addr) : Prop :=
In h (nodes gst) /\
In s (nodes gst) /\
exists st__h st__s dstp q m,
sigma gst h = Some st__h /\
sigma gst s = Some st__s /\
cur_request st__h = Some (dstp, q, m) /\
addr_of dstp = s /\
In (h, m) (delayed_queries st__s).
Definition circular_wait occ :=
has_cycle (blocked_by (occ_gst occ)).
Definition live_node (gst : global_state) (h : addr) : Prop :=
In h (nodes gst) /\
~ In h (failed_nodes gst) /\
exists st,
sigma gst h = Some st /\
joined st = true.
Definition dead_node (gst : global_state) (h : addr) : Prop :=
In h (nodes gst) /\
In h (failed_nodes gst) /\
exists st,
sigma gst h = Some st.
Definition best_succ (gst : global_state) (h s : addr) : Prop :=
exists st xs ys,
live_node gst h /\
sigma gst h = Some st /\
List.map ChordIDSpace.addr_of (succ_list st) = xs ++ s :: ys /\
(forall o, In o xs -> dead_node gst o) /\
live_node gst s.
Definition first_succ_is_best_succ (gst : global_state) (h : addr) :=
exists st s rest,
sigma gst h = Some st /\
succ_list st = s :: rest /\
best_succ gst h (addr_of s).
Definition all_first_succs_best (gst : global_state) :=
forall h,
live_node gst h ->
first_succ_is_best_succ gst h.
Definition phase_one (o : occurrence) : Prop :=
all_first_succs_best (occ_gst o).
Lemma phase_one_extensional : extensional (continuously (now phase_one)).
Proof.
apply extensional_continuously.
unfold extensional, now.
intros.
do 2 break_match.
find_apply_lem_hyp exteq_inversion.
break_and. subst_max.
assumption.
Qed.
Lemma revert_circular_wait : forall ex,
always (~_ now circular_wait) ex ->
always (~_ now QueriesEventuallyStop.circular_wait) (map revert_occurrence ex).
Proof.
apply always_map.
intros.
eapply not_tl_map; eauto.
unfold now. destruct s0.
rewrite map_Cons.
unfold QueriesEventuallyStop.circular_wait, circular_wait,
QueriesEventuallyStop.blocked_by, blocked_by, has_cycle.
intros. break_exists.
eauto.
Qed.
Lemma revert_serialize_msgs : forall gst,
serialize_global_state (revert_global_state gst) = gst ->
List.map serialize_msg (List.map revert_msg (msgs gst)) = msgs gst.
Proof.
unfold serialize_global_state, revert_global_state. simpl.
intros.
find_reverse_rewrite.
simpl.
rewrite serialize_revert_msgs.
reflexivity.
Qed.
Lemma revert_serialize_trace : forall gst,
serialize_global_state (revert_global_state gst) = gst ->
List.map serialize_event
(List.map revert_event (trace gst)) = trace gst.
Proof.
destruct gst.
unfold serialize_global_state, revert_global_state. simpl.
intros.
find_inversion.
rewrite serialize_revert_events.
reflexivity.
Qed.
Lemma serialize_send_revert_serialize : forall l h,
List.map serialize_event
(List.map revert_event
(List.map e_send (List.map serialize_msg (List.map (ChordSemantics.send h) l)))) =
List.map e_send (List.map serialize_msg (List.map (ChordSemantics.send h) l)).
Proof.
induction l.
- reflexivity.
- intros.
simpl. repeat break_let.
unfold revert_msg, revert_payload.
rewrite serialize_deserialize_top_id.
rewrite IHl.
reflexivity.
Qed.
Lemma revert_serialize_start_handler_msgs : forall h k d l0 l,
start_handler h (k :: nil) = (d, l0, l) ->
List.map serialize_msg (List.map revert_msg (List.map (send h) l0))
= List.map (send h) l0.
Proof.
unfold start_handler.
intros. repeat break_let.
find_inversion.
rewrite map_send_serialize.
rewrite serialize_revert_msgs.
reflexivity.
Qed.
Lemma revert_serialize_start_handler_events : forall h k d l0 l,
start_handler h (k :: nil) = (d, l0, l) ->
List.map serialize_event
(List.map revert_event (List.map e_send (List.map (send h) l0))) =
List.map e_send (List.map (send h) l0).
Proof.
unfold start_handler.
intros. repeat break_let.
find_inversion.
rewrite map_send_serialize.
rewrite serialize_send_revert_serialize.
reflexivity.
Qed.
Lemma revert_serialize_timeout_handler : forall h st t st' ms newts clearedts,
timeout_handler h st t = (st', ms, newts, clearedts) ->
List.map serialize_msg (List.map revert_msg (List.map (send h) ms)) = List.map (send h) ms.
Proof.
unfold timeout_handler, serialize_res.
intros.
repeat break_let.
find_inversion.
rewrite map_send_serialize.
rewrite serialize_revert_msgs.
reflexivity.
Qed.
Lemma revert_serialize_recv_handler : forall a0 a1 d p st ms newts clearedts,
recv_handler a0 a1 d p = (st, ms, newts, clearedts) ->
List.map serialize_msg (List.map revert_msg (List.map (send a1) ms)) = List.map (send a1) ms.
Proof.
unfold recv_handler, serialize_res.
intros.
repeat break_let.
find_inversion.
rewrite map_send_serialize.
rewrite serialize_revert_msgs.
reflexivity.
Qed.
Lemma revert_serialize_msgs_l_aux : forall xs m ys,
List.map serialize_msg (List.map revert_msg (xs ++ m :: ys)) = xs ++ m :: ys ->
List.map serialize_msg (List.map revert_msg xs) = xs.
Proof.
induction xs.
- reflexivity.
- intros. simpl.
rewrite (IHxs m ys); inversion H.
+ repeat find_rewrite.
reflexivity.
+ simpl in *.
repeat find_rewrite.
reflexivity.
Qed.
Lemma revert_serialize_msgs_mid_aux : forall xs m ys,
List.map serialize_msg (List.map revert_msg (xs ++ m :: ys)) = xs ++ m :: ys ->
serialize_msg (revert_msg m) = m.
Proof.
induction xs.
- simpl. intros.
inversion H.
repeat find_rewrite.
reflexivity.
- intros. simpl.
rewrite (IHxs m ys); inversion H.
+ repeat find_rewrite.
reflexivity.
+ simpl in *.
repeat find_rewrite.
reflexivity.
Qed.
Lemma revert_serialize_msgs_r_aux : forall xs m ys,
List.map serialize_msg (List.map revert_msg (xs ++ m :: ys)) = xs ++ m :: ys ->
List.map serialize_msg (List.map revert_msg ys) = ys.
Proof.
induction xs.
- simpl. intros.
inversion H.
repeat find_rewrite.
reflexivity.
- intros. simpl.
rewrite (IHxs m ys); inversion H.
+ repeat find_rewrite.
reflexivity.
+ simpl in *.
repeat find_rewrite.
reflexivity.
Qed.
Lemma revert_serialize_msgs_l : forall gst xs m ys,
serialize_global_state (revert_global_state gst) = gst ->
msgs gst = xs ++ m :: ys ->
List.map serialize_msg (List.map revert_msg xs) = xs.
Proof.
unfold serialize_global_state, revert_global_state. simpl in *.
intros.
destruct gst. simpl in *.
find_inversion.
erewrite revert_serialize_msgs_l_aux; eauto.
Qed.
Lemma revert_serialize_msgs_mid : forall gst xs m ys,
serialize_global_state (revert_global_state gst) = gst ->
msgs gst = xs ++ m :: ys ->
serialize_msg (revert_msg m) = m.
Proof.
unfold serialize_global_state, revert_global_state. simpl in *.
intros.
destruct gst. simpl in *.
find_inversion.
erewrite revert_serialize_msgs_mid_aux; eauto.
Qed.
Lemma revert_serialize_msgs_r : forall gst xs m ys,
serialize_global_state (revert_global_state gst) = gst ->
msgs gst = xs ++ m :: ys ->
List.map serialize_msg (List.map revert_msg ys) = ys.
Proof.
unfold serialize_global_state, revert_global_state. simpl in *.
intros.
destruct gst. simpl in *.
find_inversion.
erewrite revert_serialize_msgs_r_aux; eauto.
Qed.
Lemma reachable_revert_serialize_global_state : forall gst,
reachable_st_serialized gst ->
serialize_global_state (revert_global_state gst) = gst.
Proof.
intros.
induction H.
- unfold initial_st in H.
intuition.
unfold serialize_global_state, revert_global_state.
destruct gst. simpl in *.
do 2 find_apply_lem_hyp map_eq_nil.
subst_max.
reflexivity.
- inv_prop step_dynamic;
subst_max.
+ unfold update_for_start. repeat break_let.
unfold serialize_global_state, revert_global_state. simpl.
repeat rewrite map_app.
erewrite revert_serialize_start_handler_msgs;
eauto.
erewrite revert_serialize_start_handler_events;
eauto.
rewrite revert_serialize_msgs; try assumption.
rewrite revert_serialize_trace; try assumption.
reflexivity.
+ unfold fail_node.
unfold serialize_global_state, revert_global_state. simpl.
rewrite revert_serialize_msgs; try assumption.
rewrite revert_serialize_trace; try assumption.
reflexivity.
+ unfold apply_handler_result, serialize_global_state, revert_global_state.
simpl.
repeat rewrite map_app.
erewrite revert_serialize_timeout_handler;
eauto.
rewrite revert_serialize_msgs; try assumption.
rewrite revert_serialize_trace; try assumption.
reflexivity.
+ unfold apply_handler_result, serialize_global_state, revert_global_state.
simpl.
repeat rewrite map_app.
rewrite (revert_serialize_msgs_l gst xs m ys) at 1; try assumption.
rewrite (revert_serialize_msgs_r gst xs m ys) at 1; try assumption.
erewrite revert_serialize_trace; eauto.
simpl.
erewrite revert_serialize_msgs_mid; eauto.
destruct m. destruct p. simpl in *.
erewrite revert_serialize_recv_handler; eauto.
+ unfold update_msgs_and_trace, serialize_global_state, revert_global_state.
simpl.
repeat rewrite map_app.
erewrite revert_serialize_msgs; eauto.
erewrite revert_serialize_trace; eauto.
simpl.
unfold client_payload in *. break_exists. intuition.
unfold revert_payload.
match goal with
| H : serialize_top _ = _ |- _ => rewrite <- H
end.
rewrite serialize_deserialize_top_id.
reflexivity.
+ unfold update_msgs_and_trace, serialize_global_state, revert_global_state.
simpl.
repeat rewrite map_app. simpl.
erewrite revert_serialize_msgs_l; eauto.
erewrite revert_serialize_msgs_mid; eauto.
erewrite revert_serialize_msgs_r; eauto.
erewrite revert_serialize_trace; eauto.
Qed.
Lemma revert_serialize_exteq : forall ex,
reachable_st_serialized (occ_gst (infseq.hd ex)) ->
lb_execution ex ->
exteq (map serialize_occurrence (map revert_occurrence ex)) ex.
Proof.
cofix.
intros.
destruct ex. do 2 rewrite map_Cons.
unfold serialize_occurrence, revert_occurrence. simpl.
erewrite reachable_revert_serialize_global_state; eauto.
destruct o.
constructor.
apply revert_serialize_exteq.
- destruct ex. simpl in *.
inv_prop lb_execution.
eapply reachableStepS; eauto.
eapply labeled_step_is_unlabeled_step; eauto.
- eapply lb_execution_invar; eauto.
Qed.
Lemma reachable_enabled' : forall l o,
ChordSemantics.l_enabled l o -> l_enabled l (serialize_occurrence o).
Proof.
unfold ChordSemantics.l_enabled, ChordSemantics.enabled, l_enabled, enabled.
intros.
break_exists.
exists (serialize_global_state x).
apply labeled_step_serialized_labeled_step.
assumption.
Qed.
Lemma lb_execution_enabled : forall ex l,
reachable_st_serialized (occ_gst (infseq.hd ex)) ->
lb_execution ex ->
eventually (now (ChordSemantics.l_enabled l)) (map revert_occurrence ex) ->
eventually (now (l_enabled l)) ex.
Proof.
intros.
assert (G : extensional (eventually (now (l_enabled l)))).
{ apply extensional_eventually.
unfold extensional.
intros.
destruct s1, s2.
inv_prop exteq.
subst_max.
unfold now in *. repeat break_match.
assumption. }
unfold extensional in *.
apply (G (map serialize_occurrence (map revert_occurrence ex))).
- eapply revert_serialize_exteq; eauto.
- eapply eventually_map; eauto.
intros.
destruct s. simpl in *.
apply reachable_enabled'.
assumption.
Qed.
Lemma revert_always_eventually_enabled : forall ex l,
reachable_st_serialized (occ_gst (infseq.hd ex)) ->
lb_execution ex ->
always (eventually (now (ChordSemantics.l_enabled l))) (map revert_occurrence ex) ->
always (eventually (now (l_enabled l))) ex.
Proof.
cofix.
constructor.
- inv_prop always.
apply lb_execution_enabled; assumption.
- destruct ex. rewrite map_Cons in *.
apply revert_always_eventually_enabled.
+ simpl.
destruct ex.
simpl in *.
inv_prop lb_execution. simpl in *.
eapply reachableStepS; eauto.
* eapply labeled_step_is_unlabeled_step. eauto.
* eapply lb_execution_invar. eauto.
+ inv_prop always.
assumption.
Qed.
Lemma revert_strong_local_fairness : forall ex,
reachable_st_serialized (occ_gst (infseq.hd ex)) ->
lb_execution ex ->
strong_local_fairness ex ->
ChordSemantics.strong_local_fairness (map revert_occurrence ex).
Proof.
unfold strong_local_fairness, ChordSemantics.strong_local_fairness.
intros.
assert (inf_occurred l ex).
- match goal with
| H : context[inf_occurred] |- _ => apply H
end.
unfold inf_enabled, inf_often.
unfold ChordSemantics.inf_enabled, inf_often in *.
apply revert_always_eventually_enabled;
assumption.
- unfold ChordSemantics.inf_occurred, inf_often.
unfold inf_occurred, inf_often in *.
eapply always_map; eauto.
intros.
eapply eventually_map; eauto.
unfold occurred, ChordSemantics.occurred.
destruct s0. rewrite map_Cons.
tauto.
Qed.
Lemma serialize_continuously_phase_one : forall ex : infseq ChordSemantics.occurrence,
continuously (now ChordCorrectPhaseOne.phase_one) ex ->
continuously (now phase_one)
(map serialize_occurrence ex).
Proof.
intros.
eapply continuously_map; eauto.
intros.
destruct s. simpl in *. auto.
Qed.
(* top-level correctness property *)
Theorem chord_serialized_phase_one_continuously :
forall ex,
reachable_st_serialized (occ_gst (infseq.hd ex)) ->
lb_execution ex ->
strong_local_fairness ex ->
always (~_ (now circular_wait)) ex ->
continuously (now phase_one) ex.
Proof.
intros.
match goal with
| _ : _ |- continuously ?P _ =>
assert (G : extensional (continuously P)) by (exact phase_one_extensional)
end.
unfold extensional in G.
apply (G (map serialize_occurrence (map revert_occurrence ex))).
- eapply revert_serialize_exteq; eauto.
- apply serialize_continuously_phase_one.
apply ChordCorrectPhaseOne.phase_one_continuously.
+ apply revert_lb_execution.
assumption.
+ apply revert_reachable.
assumption.
+ apply revert_strong_local_fairness;
assumption.
+ apply revert_circular_wait. assumption.
Qed.
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Wed Mar 19 14:18:40 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/lab_2/part_3/ip/bram/bram/bram_stub.v
// Design : bram
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module bram(clka, wea, addra, dina, clkb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[10:0],dina[15:0],clkb,addrb[10:0],doutb[15:0]" */;
input clka;
input [0:0]wea;
input [10:0]addra;
input [15:0]dina;
input clkb;
input [10:0]addrb;
output [15:0]doutb;
endmodule
|
/**
\file "celem-test.v"
Drive a single C-element with phase-shifted clocks
Expect to see missing keeper diagnostics.
$Id: inverters.v,v 1.3 2010/04/06 00:08:35 fang Exp $
*/
`timescale 1ns/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in0, in1;
reg out;
clk_gen #(.HALF_PERIOD(1)) clk0(in0);
clk_gen #(.HALF_PERIOD(1), .PHASE_SHIFT(0.5)) clk1(in1);
// prsim stuff
initial
begin
// @haco@ celem.haco-c
$prsim_options("-f fast-weak-keepers");
$prsim("celem.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("weak-rules on");
$prsim_cmd("keeper-check-fail warn");
$to_prsim("TOP.in0", "in0");
$to_prsim("TOP.in1", "in1");
$from_prsim("out","TOP.out");
end
initial #15 $finish;
always @(in0)
begin
$display("at time %7.3f, observed in0 %b", $realtime,in0);
end
always @(in1)
begin
$display("at time %7.3f, observed in1 %b", $realtime,in1);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NOR4_BEHAVIORAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4_BEHAVIORAL_PP_V
|
`timescale 1ns/10ps
module cpu5_testbench();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:35];
wire [31:0] iaddrbus, daddrbus;
reg [31:0] iaddrbusout[0:35], daddrbusout[0:35];
wire [31:0] databus;
reg [31:0] databusk, databusin[0:35], databusout[0:35];
reg clk, reset;
reg clkd;
reg [31:0] dontcare;
reg [24*8:1] iname[0:35];
integer error, k, ntests;
parameter Rformat = 6'b000000;
parameter ADDI = 6'b000011;
parameter SUBI = 6'b000010;
parameter XORI = 6'b000001;
parameter ANDI = 6'b001111;
parameter ORI = 6'b001100;
parameter LW = 6'b011110;
parameter SW = 6'b011111;
parameter BEQ = 6'b110000;
parameter BNE = 6'b110001;
parameter ADD = 6'b000011;
parameter SUB = 6'b000010;
parameter XOR = 6'b000001;
parameter AND = 6'b000111;
parameter OR = 6'b000100;
parameter SLT = 6'b110110;
parameter SLE = 6'b110111;
cpu5 dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
// This test file runs the following program.
iname[0] = "ADDI R20, R0, #-1";
iname[1] = "ADDI R21, R0, #1";
iname[2] = "ADDI R22, R0, #2";
iname[3] = "LW R24, 0(R20)";
iname[4] = "LW R25, 0(R21)";
iname[5] = "SW 1000(R22), R20";
iname[6] = "SW 2(R0), R21";
iname[7] = "ADD R26, R24, R25";
iname[8] = "SUBI R17, R24, 6420";
iname[9] = "SUB R27, R24, R25";
iname[10] = "ANDI R18, R24, #0";
iname[11] = "AND R28, R24, R0";
iname[12] = "XORI R19, R24, 6420";
iname[13] = "XOR R29, R24, R25";
iname[14] = "ORI R20, R24, 6420";
iname[15] = "OR R30, R24, R25";
iname[16] = "SW 0(R26), R26";
iname[17] = "SW 0(R17), R27";
iname[18] = "SW 1000(R18), R28";
iname[19] = "SW 0(R19), R29";
iname[20] = "SW 0(R20), R30";
iname[21] = "SLT R1, R0, R21"; // Setting R1 to 32'h00000001 (since, R0 < R21).
iname[22] = "ADDI R5, R0, #1";
iname[23] = "ADDI R6, R0, #1";
iname[24] = "BNE R0, R1, #10"; // Branching to (32'h00000060 + 32'h00000004 + 32'h00000028 = 32'h0000008C) since, R0 != R1.
iname[25] = "ADDI R8, R0, #1"; // Delay Slot
//Branched Location - 32'h0000008C //
iname[26] = "SLE R2, R0, R0"; // Setting R2 to 32'h00000001 (since, R0 = R0).
iname[27] = "NOP";
iname[28] = "NOP";
iname[29] = "BEQ R0, R2, #25"; // NOT Branching since, R2 != R0.
iname[30] = "NOP"; // Delay Slot
iname[31] = "BEQ R2, R2, #10"; // Branching to (32h'0000000A0 + 32'h00000004 + 32'h00000028 = 32'h000000CC)
iname[32] = "ADDI R20, R0, #1"; // Delay Slot
//Branched Location - 32'h000000CC //
iname[33] = "NOP";
iname[34] = "NOP";
iname[35] = "NOP";
dontcare = 32'hx;
//* ADDI R20, R0, #-1
iaddrbusout[0] = 32'h00000000;
// opcode source1 dest Immediate...
instrbusin[0]={ADDI, 5'b00000, 5'b10100, 16'hFFFF};
daddrbusout[0] = dontcare;
databusin[0] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[0] = dontcare;
//* ADDI R21, R0, #1
iaddrbusout[1] = 32'h00000004;
// opcode source1 dest Immediate...
instrbusin[1]={ADDI, 5'b00000, 5'b10101, 16'h0001};
daddrbusout[1] = dontcare;
databusin[1] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[1] = dontcare;
//* ADDI R22, R0, #2
iaddrbusout[2] = 32'h00000008;
// opcode source1 dest Immediate...
instrbusin[2]={ADDI, 5'b00000, 5'b10110, 16'h0002};
daddrbusout[2] = dontcare;
databusin[2] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[2] = dontcare;
//* LW R24, 0(R20)
iaddrbusout[3] = 32'h0000000C;
// opcode source1 dest Immediate...
instrbusin[3]={LW, 5'b10100, 5'b11000, 16'h0000};
daddrbusout[3] = 32'hFFFFFFFF;
databusin[3] = 32'hCCCCCCCC;
databusout[3] = dontcare;
//* LW R25, 0(R21)
iaddrbusout[4] = 32'h00000010;
// opcode source1 dest Immediate...
instrbusin[4]={LW, 5'b10101, 5'b11001, 16'h0000};
daddrbusout[4] = 32'h00000001;
databusin[4] = 32'hAAAAAAAA;
databusout[4] = dontcare;
//* SW 1000(R22), R20
iaddrbusout[5] = 32'h00000014;
// opcode source1 dest Immediate...
instrbusin[5]={SW, 5'b10110, 5'b10100, 16'h1000};
daddrbusout[5] = 32'h00001002;
databusin[5] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[5] = 32'hFFFFFFFF;
//* SW 2(R0), R21
iaddrbusout[6] = 32'h00000018;
// opcode source1 dest Immediate...
instrbusin[6]={SW, 5'b00000, 5'b10101, 16'h0002};
daddrbusout[6] = 32'h00000002;
databusin[6] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[6] = 32'h00000001;
//* ADD R26, R24, R25
iaddrbusout[7] = 32'h0000001C;
// opcode source1 source2 dest shift Function...
instrbusin[7]={Rformat, 5'b11000, 5'b11001, 5'b11010, 5'b00000, ADD};
daddrbusout[7] = dontcare;
databusin[7] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[7] = dontcare;
//* SUBI R17, R24, 6420
iaddrbusout[8] = 32'h00000020;
// opcode source1 dest Immediate...
instrbusin[8]={SUBI, 5'b11000, 5'b10001, 16'h6420};
daddrbusout[8] = dontcare;
databusin[8] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[8] = dontcare;
//* SUB R27, R24, R25
iaddrbusout[9] = 32'h00000024;
// opcode source1 source2 dest shift Function...
instrbusin[9]={Rformat, 5'b11000, 5'b11001, 5'b11011, 5'b00000, SUB};
daddrbusout[9] = dontcare;
databusin[9] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[9] = dontcare;
//* ANDI R18, R24, #0
iaddrbusout[10] = 32'h00000028;
// opcode source1 dest Immediate...
instrbusin[10]={ANDI, 5'b11000, 5'b10010, 16'h0000};
daddrbusout[10] = dontcare;
databusin[10] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[10] = dontcare;
//* AND R28, R24, R0
iaddrbusout[11] = 32'h0000002C;
// opcode source1 source2 dest shift Function...
instrbusin[11]={Rformat, 5'b11000, 5'b00000, 5'b11100, 5'b00000, AND};
daddrbusout[11] = dontcare;
databusin[11] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[11] = dontcare;
//* XORI R19, R24, 6420
iaddrbusout[12] = 32'h00000030;
// opcode source1 dest Immediate...
instrbusin[12]={XORI, 5'b11000, 5'b10011, 16'h6420};
daddrbusout[12] = dontcare;
databusin[12] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[12] = dontcare;
//* XOR R29, R24, R25
iaddrbusout[13] = 32'h00000034;
// opcode source1 source2 dest shift Function...
instrbusin[13]={Rformat, 5'b11000, 5'b11001, 5'b11101, 5'b00000, XOR};
daddrbusout[13] = dontcare;
databusin[13] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[13] = dontcare;
//* ORI R20, R24, 6420
iaddrbusout[14] = 32'h00000038;
// opcode source1 dest Immediate...
instrbusin[14]={ORI, 5'b11000, 5'b10100, 16'h6420};
daddrbusout[14] = dontcare;
databusin[14] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[14] = dontcare;
//* OR R30, R24, R25
iaddrbusout[15] = 32'h0000003C;
// opcode source1 source2 dest shift Function...
instrbusin[15]={Rformat, 5'b11000, 5'b11001, 5'b11110, 5'b00000, OR};
daddrbusout[15] = dontcare;
databusin[15] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[15] = dontcare;
//* SW 0(R26), R26
iaddrbusout[16] = 32'h00000040;
// opcode source1 dest Immediate...
instrbusin[16]={SW, 5'b11010, 5'b11010, 16'h0000};
daddrbusout[16] = 32'h77777776;
databusin[16] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[16] = 32'h77777776;
//18* SW 0(R17), R27
iaddrbusout[17] = 32'h00000044;
// opcode source1 dest Immediate...
instrbusin[17]={SW, 5'b10001, 5'b11011, 16'h0000};
daddrbusout[17] = 32'hCCCC68AC;
databusin[17] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[17] = 32'h22222222;
//19* SW 1000(R18), R28
iaddrbusout[18] = 32'h00000048;
// opcode source1 dest Immediate...
instrbusin[18]={SW, 5'b10010, 5'b11100, 16'h1000};
daddrbusout[18] = 32'h00001000;
databusin[18] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[18] = 32'h00000000;
//20* SW 0(R19), R29
iaddrbusout[19] = 32'h0000004C;
// opcode source1 dest Immediate...
instrbusin[19]={SW, 5'b10011, 5'b11101, 16'h0000};
daddrbusout[19] = 32'hCCCCA8EC;
databusin[19] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[19] = 32'h66666666;
//21* SW 0(R20), R30
iaddrbusout[20] = 32'h00000050;
// opcode source1 dest Immediate...
instrbusin[20]={SW, 5'b10100, 5'b11110, 16'h0000};
daddrbusout[20] = 32'hCCCCECEC;
databusin[20] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[20] = 32'hEEEEEEEE;
//22* SLT R1, R0, R21
iaddrbusout[21] = 32'h00000054;
// opcode source1 source2 dest shift Function...
instrbusin[21]={Rformat, 5'b00000, 5'b10101, 5'b00001, 5'b00000, SLT};
daddrbusout[21] = dontcare;
databusin[21] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[21] = dontcare;
//* ADDI R5, R0, #1
iaddrbusout[22] = 32'h00000058;
// opcode source1 dest Immediate...
instrbusin[22]={ADDI, 5'b00000, 5'b00101, 16'h0001};
daddrbusout[22] = dontcare;
databusin[22] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[22] = dontcare;
//* ADDI R6, R0, #1
iaddrbusout[23] = 32'h0000005C;
// opcode source1 dest Immediate...
instrbusin[23]={ADDI, 5'b00000, 5'b00110, 16'h0001};
daddrbusout[23] = dontcare;
databusin[23] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[23] = dontcare;
//* BNE R0, R1, #10
iaddrbusout[24] = 32'h00000060;
// opcode source1 dest Immediate...
instrbusin[24]={BNE, 5'b00001, 5'b00000, 16'h000A};
daddrbusout[24] = dontcare;
databusin[24] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[24] = dontcare;
//* ADDI R8, R0, #1
iaddrbusout[25] = 32'h00000064;
// opcode source1 dest Immediate...
instrbusin[25]={ADDI, 5'b00000, 5'b01000, 16'h0001};
daddrbusout[25] = dontcare;
databusin[25] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[25] = dontcare;
//* SLE R2, R0, R0
iaddrbusout[26] = 32'h0000008C;
// opcode source1 source2 dest shift Function...
instrbusin[26]={Rformat, 5'b00000, 5'b00000, 5'b00010, 5'b00000, SLE};
daddrbusout[26] = dontcare;
databusin[26] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[26] = dontcare;
//* NOP
iaddrbusout[27] = 32'h00000090;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[27] = 32'b00000000000000000000000000000000;
daddrbusout[27] = dontcare;
databusin[27] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[27] = dontcare;
//* NOP
iaddrbusout[28] = 32'h00000094;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[28] = 32'b00000000000000000000000000000000;
daddrbusout[28] = dontcare;
databusin[28] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[28] = dontcare;
//* BEQ R0, R2, #25
iaddrbusout[29] = 32'h00000098;
// opcode source1 dest Immediate...
instrbusin[29]={BEQ, 5'b00010, 5'b00000, 16'h0019};
daddrbusout[29] = dontcare;
databusin[29] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[29] = dontcare;
//* NOP
iaddrbusout[30] = 32'h0000009C;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[30] = 32'b00000000000000000000000000000000;
daddrbusout[30] = dontcare;
databusin[30] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[30] = dontcare;
//* BEQ R2, R2, #10
iaddrbusout[31] = 32'h000000A0;
// opcode source1 dest Immediate...
instrbusin[31]={BEQ, 5'b00010, 5'b00010, 16'h000A};
daddrbusout[31] = dontcare;
databusin[31] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[31] = dontcare;
//* ADDI R20, R0, #1
iaddrbusout[32] = 32'h000000A4;
// opcode source1 dest Immediate...
instrbusin[32]={ADDI, 5'b00000, 5'b10100, 16'h0001};
daddrbusout[32] = dontcare;
databusin[32] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[32] = dontcare;
//* NOP
iaddrbusout[33] = 32'h000000CC;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[33] = 32'b00000000000000000000000000000000;
daddrbusout[33] = dontcare;
databusin[33] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[33] = dontcare;
//* NOP
iaddrbusout[34] = 32'h000000D0;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[34] = 32'b00000000000000000000000000000000;
daddrbusout[34] = dontcare;
databusin[34] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[34] = dontcare;
//* NOP
iaddrbusout[35] = 32'h000000D4;
// oooooosssssdddddiiiiiiiiiiiiiiii
instrbusin[35] = 32'b00000000000000000000000000000000;
daddrbusout[35] = dontcare;
databusin[35] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[35] = dontcare;
// (no. instructions) + (no. loads) + 2*(no. stores) = 35 + 2 + 2*7 = 51
ntests = 51;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 32'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
databusk = 32'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 35; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: urn_gen
// Description: This module implements a 64-bit Tausworthe generator.
// A new, uniformly distributed random number is generated
// on every rising clock edge out of reset.
//////////////////////////////////////////////////////////////////////////////////
module urn_gen(
input clk,
input rst,
output [63:0] urn
);
// Initialize registers to an arbitrary, know value for repeatability
reg [63:0] s1 = 64'd1234;
reg [63:0] s2 = 64'd5678;
reg [63:0] s3 = 64'd9012;
reg [63:0] urn_reg = 64'd0;
wire [63:0] b1,b2,b3;
wire [63:0] new_s1,new_s2,new_s3;
assign urn = urn_reg;
assign b1 = (((s1 << 13) ^ s1) >> 19);
assign new_s1 = (((s1 & 64'hfffffffffffffffe) << 12) ^ b1);
assign b2 = (((s2 << 2 ) ^ s2) >> 25);
assign new_s2 = (((s2 & 64'hfffffffffffffff8) << 4 ) ^ b2);
assign b3 = (((s3 << 3 ) ^ s3) >> 11);
assign new_s3 = (((s3 & 64'hfffffffffffffff0) << 17) ^ b3);
always @(posedge clk)
begin
if (rst)
begin
// Initialize registers to an arbitrary, know value for repeatability
s1 <= 64'd1234;
s2 <= 64'd5678;
s3 <= 64'd9012;
urn_reg <= 64'd0;
end
else
begin
urn_reg <= new_s1 ^ new_s2 ^ new_s3;
s1 <= new_s1;
s2 <= new_s2;
s3 <= new_s3;
end
end
endmodule
|
// megafunction wizard: %LPM_FIFO+%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_32x128.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 148 04/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_32x128 (
data,
wrreq,
rdreq,
clock,
aclr,
q,
full,
empty,
usedw);
input [31:0] data;
input wrreq;
input rdreq;
input clock;
input aclr;
output [31:0] q;
output full;
output empty;
output [6:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128_wave*.jpg FALSE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_BEHAVIORAL_V
|
/* This module implements the VGA controller. It assumes a 25MHz clock is supplied as input.
*
* General approach:
* Go through each line of the screen and read the colour each pixel on that line should have from
* the Video memory. To do that for each (x,y) pixel on the screen convert (x,y) coordinate to
* a memory_address at which the pixel colour is stored in Video memory. Once the pixel colour is
* read from video memory its brightness is first increased before it is forwarded to the VGA DAC.
*/
module vga_controller( vga_clock, resetn, pixel_colour, memory_address,
VGA_R, VGA_G, VGA_B,
VGA_HS, VGA_VS, VGA_BLANK,
VGA_SYNC, VGA_CLK);
/* Screen resolution and colour depth parameters. */
parameter BITS_PER_COLOUR_CHANNEL = 1;
/* The number of bits per colour channel used to represent the colour of each pixel. A value
* of 1 means that Red, Green and Blue colour channels will use 1 bit each to represent the intensity
* of the respective colour channel. For BITS_PER_COLOUR_CHANNEL=1, the adapter can display 8 colours.
* In general, the adapter is able to use 2^(3*BITS_PER_COLOUR_CHANNEL) colours. The number of colours is
* limited by the screen resolution and the amount of on-chip memory available on the target device.
*/
parameter MONOCHROME = "FALSE";
/* Set this parameter to "TRUE" if you only wish to use black and white colours. Doing so will reduce
* the amount of memory you will use by a factor of 3. */
parameter RESOLUTION = "320x240";
/* Set this parameter to "160x120" or "320x240". It will cause the VGA adapter to draw each dot on
* the screen by using a block of 4x4 pixels ("160x120" resolution) or 2x2 pixels ("320x240" resolution).
* It effectively reduces the screen resolution to an integer fraction of 640x480. It was necessary
* to reduce the resolution for the Video Memory to fit within the on-chip memory limits.
*/
parameter USING_DE1 = "TRUE";
/* If set to "TRUE" it adjust the offset of the drawing mechanism to account for the differences
* between the DE2 and DE1 VGA digital to analogue converters. Set to "TRUE" if and only if
* you are running your circuit on a DE1 board. */
//--- Timing parameters.
/* Recall that the VGA specification requires a few more rows and columns are drawn
* when refreshing the screen than are actually present on the screen. This is necessary to
* generate the vertical and the horizontal syncronization signals. If you wish to use a
* display mode other than 640x480 you will need to modify the parameters below as well
* as change the frequency of the clock driving the monitor (VGA_CLK).
*/
parameter C_VERT_NUM_PIXELS = 11'd480;
parameter C_VERT_SYNC_START = 11'd493;
parameter C_VERT_SYNC_END = 11'd494; //(C_VERT_SYNC_START + 2 - 1);
parameter C_VERT_TOTAL_COUNT = 11'd525;
parameter C_HORZ_NUM_PIXELS = 11'd640;
parameter C_HORZ_SYNC_START = 11'd659;
parameter C_HORZ_SYNC_END = 11'd754; //(C_HORZ_SYNC_START + 96 - 1);
parameter C_HORZ_TOTAL_COUNT = 11'd800;
/*****************************************************************************/
/* Declare inputs and outputs. */
/*****************************************************************************/
input vga_clock, resetn;
input [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] pixel_colour;
output [((RESOLUTION == "320x240") ? (16) : (14)):0] memory_address;
output reg [9:0] VGA_R;
output reg [9:0] VGA_G;
output reg [9:0] VGA_B;
output reg VGA_HS;
output reg VGA_VS;
output reg VGA_BLANK;
output VGA_SYNC, VGA_CLK;
/*****************************************************************************/
/* Local Signals. */
/*****************************************************************************/
reg VGA_HS1;
reg VGA_VS1;
reg VGA_BLANK1;
reg [9:0] xCounter, yCounter;
wire xCounter_clear;
wire yCounter_clear;
wire vcc;
reg [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
reg [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
/* Inputs to the converter. */
/*****************************************************************************/
/* Controller implementation. */
/*****************************************************************************/
assign vcc =1'b1;
/* A counter to scan through a horizontal line. */
always @(posedge vga_clock or negedge resetn)
begin
if (!resetn)
xCounter <= 10'd0;
else if (xCounter_clear)
xCounter <= 10'd0;
else
begin
xCounter <= xCounter + 1'b1;
end
end
assign xCounter_clear = (xCounter == (C_HORZ_TOTAL_COUNT-1));
/* A counter to scan vertically, indicating the row currently being drawn. */
always @(posedge vga_clock or negedge resetn)
begin
if (!resetn)
yCounter <= 10'd0;
else if (xCounter_clear && yCounter_clear)
yCounter <= 10'd0;
else if (xCounter_clear) //Increment when x counter resets
yCounter <= yCounter + 1'b1;
end
assign yCounter_clear = (yCounter == (C_VERT_TOTAL_COUNT-1));
/* Convert the xCounter/yCounter location from screen pixels (640x480) to our
* local dots (320x240 or 160x120). Here we effectively divide x/y coordinate by 2 or 4,
* depending on the resolution. */
always @(*)
begin
if (RESOLUTION == "320x240")
begin
x = xCounter[9:1];
y = yCounter[8:1];
end
else
begin
x = xCounter[9:2];
y = yCounter[8:2];
end
end
/* Change the (x,y) coordinate into a memory address. */
vga_address_translator controller_translator(
.x(x), .y(y), .mem_address(memory_address) );
defparam controller_translator.RESOLUTION = RESOLUTION;
/* Generate the vertical and horizontal synchronization pulses. */
always @(posedge vga_clock)
begin
//- Sync Generator (ACTIVE LOW)
if (USING_DE1 == "TRUE")
VGA_HS1 <= ~((xCounter >= C_HORZ_SYNC_START-2) && (xCounter <= C_HORZ_SYNC_END-2));
else
VGA_HS1 <= ~((xCounter >= C_HORZ_SYNC_START) && (xCounter <= C_HORZ_SYNC_END));
VGA_VS1 <= ~((yCounter >= C_VERT_SYNC_START) && (yCounter <= C_VERT_SYNC_END));
//- Current X and Y is valid pixel range
VGA_BLANK1 <= ((xCounter < C_HORZ_NUM_PIXELS) && (yCounter < C_VERT_NUM_PIXELS));
//- Add 1 cycle delay
VGA_HS <= VGA_HS1;
VGA_VS <= VGA_VS1;
VGA_BLANK <= VGA_BLANK1;
end
/* VGA sync should be 1 at all times. */
assign VGA_SYNC = vcc;
/* Generate the VGA clock signal. */
assign VGA_CLK = vga_clock;
/* Brighten the colour output. */
// The colour input is first processed to brighten the image a little. Setting the top
// bits to correspond to the R,G,B colour makes the image a bit dull. To brighten the image,
// each bit of the colour is replicated through the 10 DAC colour input bits. For example,
// when BITS_PER_COLOUR_CHANNEL is 2 and the red component is set to 2'b10, then the
// VGA_R input to the DAC will be set to 10'b1010101010.
integer index;
integer sub_index;
wire on_screen;
assign on_screen = (USING_DE1 == "TRUE") ?
(({1'b0, xCounter} >= 2) & ({1'b0, xCounter} < C_HORZ_NUM_PIXELS+2) & ({1'b0, yCounter} < C_VERT_NUM_PIXELS)) :
(({1'b0, xCounter} >= 0) & ({1'b0, xCounter} < C_HORZ_NUM_PIXELS+2) & ({1'b0, yCounter} < C_VERT_NUM_PIXELS));
always @(pixel_colour or on_screen)
begin
VGA_R <= 'b0;
VGA_G <= 'b0;
VGA_B <= 'b0;
if (MONOCHROME == "FALSE")
begin
for (index = 10-BITS_PER_COLOUR_CHANNEL; index >= 0; index = index - BITS_PER_COLOUR_CHANNEL)
begin
for (sub_index = BITS_PER_COLOUR_CHANNEL - 1; sub_index >= 0; sub_index = sub_index - 1)
begin
VGA_R[sub_index+index] <= on_screen & pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL*2];
VGA_G[sub_index+index] <= on_screen & pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL];
VGA_B[sub_index+index] <= on_screen & pixel_colour[sub_index];
end
end
end
else
begin
for (index = 0; index < 10; index = index + 1)
begin
VGA_R[index] <= on_screen & pixel_colour[0:0];
VGA_G[index] <= on_screen & pixel_colour[0:0];
VGA_B[index] <= on_screen & pixel_colour[0:0];
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__A211O_PP_SYMBOL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a211o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_PP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 19 10:21:53 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: video_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module video_pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 2,
altpll_component.clk0_duty_cycle = 60,
altpll_component.clk0_multiply_by = 3,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20202,
altpll_component.intended_device_family = "Cyclone 10 LP",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=video_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "60.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "74.250000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "49.500"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "75.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "video_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "60"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20202"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL video_pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD2_PP_BLACKBOX_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD2_PP_BLACKBOX_V
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "include/mbus_def.v"
module mbus_ctrl_layer_wrapper
(
input CLK_EXT,
input CLKIN,
input RESETn,
input DIN,
output CLKOUT,
output DOUT,
input [`ADDR_WIDTH-1:0] TX_ADDR,
input [`DATA_WIDTH-1:0] TX_DATA,
input TX_PEND,
input TX_REQ,
input TX_PRIORITY,
output TX_ACK,
output [`ADDR_WIDTH:0] RX_ADDR,
output [`DATA_WIDTH:0] RX_DATA,
output RX_REQ,
input RX_ACK,
output RX_BROADCAST,
output RX_FAIL,
output RX_PEND,
output TX_FAIL,
output TX_SUCC,
input TX_RESP_ACK
);
parameter ADDRESS = 20'haaaaa;
wire w_m0wc0_clk_out;
wire w_m0wc0;
wire ext_int_to_wire;
wire ext_int_to_bus;
wire clr_ext_int;
wire clr_busy;
mbus_ctrl_wrapper #(.ADDRESS(ADDRESS)) m0
(
.CLK_EXT (CLK_EXT),
.RESETn (RESETn),
.CLKIN (CLKIN),
.CLKOUT (w_m0wc0_clk_out),
.DIN (DIN),
.DOUT (w_m0wc0),
.TX_ADDR (TX_ADDR),
.TX_DATA (TX_DATA),
.TX_PEND (TX_PEND),
.TX_REQ (TX_REQ),
.TX_PRIORITY (TX_PRIORITY),
.TX_ACK (TX_ACK),
.RX_ADDR (RX_ADDR),
.RX_DATA (RX_DATA),
.RX_REQ (RX_REQ),
.RX_ACK (RX_ACK),
.RX_BROADCAST (RX_BROADCAST),
.RX_FAIL (RX_FAIL),
.RX_PEND (RX_PEND),
.TX_FAIL (TX_FAIL),
.TX_SUCC (TX_SUCC),
.TX_RESP_ACK (TX_RESP_ACK),
.THRESHOLD (20'h05fff),
.MBC_RESET (1'b0),
.LRC_SLEEP (),
.LRC_CLKENB (),
.LRC_RESET (),
.LRC_ISOLATE (),
.EXTERNAL_INT (ext_int_to_bus), //?
.CLR_EXT_INT (clr_ext_int),
.CLR_BUSY (clr_busy),
.SLEEP_REQUEST_TO_SLEEP_CTRL()
);
// always on wire controller
mbus_master_wire_ctrl wc0
(
.RESETn (RESETn),
.RELEASE_ISO_FROM_SLEEP_CTRL (1'b0),
.DOUT_FROM_BUS (w_m0wc0),
.CLKOUT_FROM_BUS (w_m0wc0_clk_out),
.DOUT (DOUT),
.CLKOUT (CLKOUT),
.EXTERNAL_INT (ext_int_to_wire)
);
// always on interrupt controller
mbus_int_ctrl mic0
(
.CLKIN (CLKIN),
.RESETn (RESETn),
.MBC_ISOLATE (1'b0),
.SC_CLR_BUSY (1'b0),
.MBUS_CLR_BUSY (clr_busy),
.REQ_INT (1'b0),
.MBC_SLEEP (1'b0),
.LRC_SLEEP (1'b0),
.EXTERNAL_INT_TO_WIRE (ext_int_to_wire),
.EXTERNAL_INT_TO_BUS (ext_int_to_bus),
.CLR_EXT_INT (clr_ext_int)
);
endmodule
|
module uart_ctrl (
clk,
reset_,
tx,
rx,
addr,
cs,
req,
rnw,
wr_data,
rd_data,
rdy);
input clk;
input reset_;
output tx; // Transmit to host computer
input rx; // Receive from host computer
// This circuit provides software control over the RS-232 universal asynchronus
// receiver/transmitter. It exposes these software accessible registers:
//
// Transmit byte (read/write):
// [7:0] Write a value to this register to have it transmitted to the
// host computer. Has no effect if the transmitter is not ready
// at the time the register is written.
//
// Transmit ready (read):
// [0] When 1, the transmitter is ready to accept a new byte to be
// transmitted. 0 indicates the transmitter is still busy with a
// previous byte.
//
// Receive byte (read):
// [7:0] The last byte received from the host computer.
//
// Receive byte ready (read/write):
// [0] 1 indicates that the receive byte value is valid and ready to
// be consumed by software. Write any value to this register to
// clear the ready indicator.
//
// Transmit byte count high (read):
// [7:0] The high ([15:8]) bits of the number of bytes transmitted to the
// host computer.
//
// Transmit byte count low (read):
// [7:0] The low ([8:0]) bits of the number of bytes transmitted to the
// host computer.
//
// Recieve byte count high (read):
// [7:0] The high ([15:8]) bits of the number of bytes received from the
// host computer.
//
// Receive byte count low (read):
// [7:0] The low ([7:0]) bits of the number of bytes received from the
// host computer.
// Local IO bus
input [7:0] addr;
input cs;
input req;
inout rnw;
input [7:0] wr_data;
output [7:0] rd_data;
output rdy;
reg rdy;
reg [7:0] rd_data;
wire wr_enable;
wire rd_enable;
reg tx_enable;
reg [7:0] tx_data;
reg [7:0] rx_data_reg;
reg [15:0] tx_count;
reg [15:0] rx_count;
wire tx_ready;
wire [7:0] rx_data;
reg rx_ready;
// Software addressable registers
parameter TX_BYTE_REG = 8'd0;
parameter TX_BYTE_RDY_REG = 8'd1;
parameter RX_BYTE_REG = 8'd2;
parameter RX_BYTE_RDY_REG = 8'd3;
parameter TX_BYTE_CNT_HI_REG = 8'd4;
parameter TX_BYTE_CNT_LO_REG = 8'd5;
parameter RX_BYTE_CNT_HI_REG = 8'd6;
parameter RX_BYTE_CNT_LO_REG = 8'd7;
assign wr_enable = cs && !rnw && req;
assign rd_enable = cs && rnw && req;
// Transmit data register
always@ (posedge clk or negedge reset_)
if (!reset_)
tx_data <= 8'd0;
else if (wr_enable && addr == TX_BYTE_REG)
tx_data <= wr_data;
// Transmit enable generation
always@ (posedge clk or negedge reset_)
if (!reset_)
tx_enable <= 1'b0;
else if (wr_enable && addr == TX_BYTE_REG)
tx_enable <= 1'b1;
else
tx_enable <= 1'b0;
// Receive data register
always@ (posedge clk or negedge reset_)
if (!reset_)
rx_data_reg <= 8'h00;
else if (rx_enable)
rx_data_reg <= rx_data;
// Receive ready readback
always@ (posedge clk or negedge reset_)
if (!reset_)
rx_ready <= 1'b0;
else if (wr_enable && addr == RX_BYTE_RDY_REG)
rx_ready <= 1'b0;
else if (rx_enable)
rx_ready <= 1'b1;
// Transmit byte count
always@ (posedge clk or negedge reset_)
if (!reset_)
tx_count <= 16'd0;
else if (tx_enable)
tx_count <= tx_count + 16'd1;
// Receive byte count
always@ (posedge clk or negedge reset_)
if (!reset_)
rx_count <= 16'd0;
else if (rx_enable)
rx_count <= rx_count + 16'd1;
// Register readback
always@ (posedge clk or negedge reset_)
if (!reset_)
rd_data <= 8'd0;
else if (rd_enable)
rd_data <= (addr == TX_BYTE_RDY_REG) ? {7'd0, tx_ready} :
(addr == TX_BYTE_REG) ? tx_data :
(addr == RX_BYTE_REG) ? rx_data_reg :
(addr == RX_BYTE_RDY_REG) ? {7'd0, rx_ready} :
(addr == TX_BYTE_CNT_HI_REG) ? tx_count[15:8] :
(addr == TX_BYTE_CNT_LO_REG) ? tx_count[7:0] :
(addr == RX_BYTE_CNT_HI_REG) ? rx_count[15:8] :
(addr == RX_BYTE_CNT_LO_REG) ? rx_count[7:0] :
8'd0;
// Module ready generation
always@ (posedge clk or negedge reset_)
if (!reset_)
rdy <= 1'b0;
else
rdy <= req;
// UART instantiation
uart uart(
.clk32(clk),
.reset_(reset_),
.rx(rx),
.tx(tx),
.txdata(tx_data),
.rxdata(rx_data),
.rx_enable(rx_enable),
.tx_enable(tx_enable),
.tx_ready(tx_ready)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// usbSlave.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module usbSlave(
clk_i,
rst_i,
address_i,
data_i,
data_o,
we_i,
strobe_i,
ack_o,
usbClk,
slaveVBusDetIntOut,
slaveNAKSentIntOut,
slaveSOFRxedIntOut,
slaveResetEventIntOut,
slaveResumeIntOut,
slaveTransDoneIntOut,
USBWireDataIn,
USBWireDataInTick,
USBWireDataOut,
USBWireDataOutTick,
USBWireCtrlOut,
USBFullSpeed,
USBDPlusPullup,
USBDMinusPullup,
vBusDetect
);
parameter EP0_FIFO_DEPTH = 64;
parameter EP0_FIFO_ADDR_WIDTH = 6;
parameter EP1_FIFO_DEPTH = 64;
parameter EP1_FIFO_ADDR_WIDTH = 6;
parameter EP2_FIFO_DEPTH = 64;
parameter EP2_FIFO_ADDR_WIDTH = 6;
parameter EP3_FIFO_DEPTH = 64;
parameter EP3_FIFO_ADDR_WIDTH = 6;
input clk_i; //Wishbone bus clock. Maximum 5*usbClk=240MHz
input rst_i; //Wishbone bus sync reset. Synchronous to 'clk_i'. Resets all logic
input [7:0] address_i; //Wishbone bus address in
input [7:0] data_i; //Wishbone bus data in
output [7:0] data_o; //Wishbone bus data out
input we_i; //Wishbone bus write enable in
input strobe_i; //Wishbone bus strobe in
output ack_o; //Wishbone bus acknowledge out
input usbClk; //usb clock. 48Mhz +/-0.25%
output slaveSOFRxedIntOut;
output slaveResetEventIntOut;
output slaveResumeIntOut;
output slaveTransDoneIntOut;
output slaveNAKSentIntOut;
output slaveVBusDetIntOut;
input [1:0] USBWireDataIn;
output [1:0] USBWireDataOut;
output USBWireDataOutTick;
output USBWireDataInTick;
output USBWireCtrlOut;
output USBFullSpeed;
output USBDPlusPullup;
output USBDMinusPullup;
input vBusDetect;
wire clk_i;
wire rst_i;
wire [7:0] address_i;
wire [7:0] data_i;
wire [7:0] data_o;
wire we_i;
wire strobe_i;
wire ack_o;
wire usbClk;
wire slaveSOFRxedIntOut;
wire slaveResetEventIntOut;
wire slaveResumeIntOut;
wire slaveTransDoneIntOut;
wire slaveNAKSentIntOut;
wire slaveVBusDetIntOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBWireCtrlOut;
wire USBFullSpeed;
wire USBDPlusPullup;
wire USBDMinusPullup;
wire vBusDetect;
//internal wiring
wire slaveControlSel;
wire hostSlaveMuxSel;
wire [7:0] dataFromSlaveControl;
wire [7:0] dataFromHostSlaveMux;
wire [7:0] RxCtrlOut;
wire [7:0] RxDataFromSIE;
wire RxDataOutWEn;
wire fullSpeedBitRateFromSlave;
wire fullSpeedPolarityFromSlave;
wire SIEPortWEnFromSlave;
wire SIEPortTxRdy;
wire [7:0] SIEPortDataInFromSlave;
wire [7:0] SIEPortCtrlInFromSlave;
wire [1:0] connectState;
wire resumeDetected;
wire [7:0] SIEPortDataInToSIE;
wire SIEPortWEnToSIE;
wire [7:0] SIEPortCtrlInToSIE;
wire fullSpeedPolarityToSIE;
wire fullSpeedBitRateToSIE;
wire connectSlaveToHost;
wire noActivityTimeOut;
wire TxFifoEP0REn;
wire TxFifoEP1REn;
wire TxFifoEP2REn;
wire TxFifoEP3REn;
wire [7:0] TxFifoEP0Data;
wire [7:0] TxFifoEP1Data;
wire [7:0] TxFifoEP2Data;
wire [7:0] TxFifoEP3Data;
wire TxFifoEP0Empty;
wire TxFifoEP1Empty;
wire TxFifoEP2Empty;
wire TxFifoEP3Empty;
wire RxFifoEP0WEn;
wire RxFifoEP1WEn;
wire RxFifoEP2WEn;
wire RxFifoEP3WEn;
wire RxFifoEP0Full;
wire RxFifoEP1Full;
wire RxFifoEP2Full;
wire RxFifoEP3Full;
wire [7:0] slaveRxFifoData;
wire [7:0] dataFromEP0RxFifo;
wire [7:0] dataFromEP1RxFifo;
wire [7:0] dataFromEP2RxFifo;
wire [7:0] dataFromEP3RxFifo;
wire [7:0] dataFromEP0TxFifo;
wire [7:0] dataFromEP1TxFifo;
wire [7:0] dataFromEP2TxFifo;
wire [7:0] dataFromEP3TxFifo;
wire slaveEP0RxFifoSel;
wire slaveEP1RxFifoSel;
wire slaveEP2RxFifoSel;
wire slaveEP3RxFifoSel;
wire slaveEP0TxFifoSel;
wire slaveEP1TxFifoSel;
wire slaveEP2TxFifoSel;
wire slaveEP3TxFifoSel;
wire rstSyncToBusClk;
wire rstSyncToUsbClk;
wire noActivityTimeOutEnableToSIE;
wire noActivityTimeOutEnableFromHost;
wire noActivityTimeOutEnableFromSlave;
// This is not a bug.
// USBFullSpeed controls the PHY edge speed.
// The only time that the PHY needs to operate with low speed edge rate is
// when the host is directly connected to a low speed device. And when this is true, fullSpeedPolarity
// will be low. When the host is connected to a low speed device via a hub, then speed can be full or low
// but according to spec edge speed must be full rate edge speed.
assign USBFullSpeed = fullSpeedPolarityToSIE;
//assign USBFullSpeed = fullSpeedBitRateToSIE;
assign USBDPlusPullup = (USBFullSpeed & connectSlaveToHost);
assign USBDMinusPullup = (~USBFullSpeed & connectSlaveToHost);
usbSlaveControl u_usbSlaveControl(
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.RxByteStatus(RxCtrlOut),
.RxData(RxDataFromSIE),
.RxDataValid(RxDataOutWEn),
.SIERxTimeOut(noActivityTimeOut),
.SIERxTimeOutEn(noActivityTimeOutEnableFromSlave),
.RxFifoData(slaveRxFifoData),
.connectSlaveToHost(connectSlaveToHost),
.fullSpeedRate(fullSpeedBitRateFromSlave),
.fullSpeedPol(fullSpeedPolarityFromSlave),
.SCTxPortEn(SIEPortWEnFromSlave),
.SCTxPortRdy(SIEPortTxRdy),
.SCTxPortData(SIEPortDataInFromSlave),
.SCTxPortCtrl(SIEPortCtrlInFromSlave),
.vBusDetect(vBusDetect),
.connectStateIn(connectState),
.resumeDetectedIn(resumeDetected),
.busAddress(address_i[4:0]),
.busDataIn(data_i),
.busDataOut(dataFromSlaveControl),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.SOFRxedIntOut(slaveSOFRxedIntOut),
.resetEventIntOut(slaveResetEventIntOut),
.resumeIntOut(slaveResumeIntOut),
.transDoneIntOut(slaveTransDoneIntOut),
.NAKSentIntOut(slaveNAKSentIntOut),
.vBusDetIntOut(slaveVBusDetIntOut),
.slaveControlSelect(slaveControlSel),
.TxFifoEP0REn(TxFifoEP0REn),
.TxFifoEP1REn(TxFifoEP1REn),
.TxFifoEP2REn(TxFifoEP2REn),
.TxFifoEP3REn(TxFifoEP3REn),
.TxFifoEP0Data(TxFifoEP0Data),
.TxFifoEP1Data(TxFifoEP1Data),
.TxFifoEP2Data(TxFifoEP2Data),
.TxFifoEP3Data(TxFifoEP3Data),
.TxFifoEP0Empty(TxFifoEP0Empty),
.TxFifoEP1Empty(TxFifoEP1Empty),
.TxFifoEP2Empty(TxFifoEP2Empty),
.TxFifoEP3Empty(TxFifoEP3Empty),
.RxFifoEP0WEn(RxFifoEP0WEn),
.RxFifoEP1WEn(RxFifoEP1WEn),
.RxFifoEP2WEn(RxFifoEP2WEn),
.RxFifoEP3WEn(RxFifoEP3WEn),
.RxFifoEP0Full(RxFifoEP0Full),
.RxFifoEP1Full(RxFifoEP1Full),
.RxFifoEP2Full(RxFifoEP2Full),
.RxFifoEP3Full(RxFifoEP3Full)
);
wishBoneBI u_wishBoneBI (
.address(address_i),
.dataIn(data_i),
.dataOut(data_o),
.writeEn(we_i),
.strobe_i(strobe_i),
.ack_o(ack_o),
.clk(clk_i),
.rst(rstSyncToBusClk),
.hostControlSel(),
.hostRxFifoSel(),
.hostTxFifoSel(),
.slaveControlSel(slaveControlSel),
.slaveEP0RxFifoSel(slaveEP0RxFifoSel),
.slaveEP1RxFifoSel(slaveEP1RxFifoSel),
.slaveEP2RxFifoSel(slaveEP2RxFifoSel),
.slaveEP3RxFifoSel(slaveEP3RxFifoSel),
.slaveEP0TxFifoSel(slaveEP0TxFifoSel),
.slaveEP1TxFifoSel(slaveEP1TxFifoSel),
.slaveEP2TxFifoSel(slaveEP2TxFifoSel),
.slaveEP3TxFifoSel(slaveEP3TxFifoSel),
.hostSlaveMuxSel(hostSlaveMuxSel),
.dataFromHostControl(8'h00),
.dataFromHostRxFifo(8'h00),
.dataFromHostTxFifo(8'h00),
.dataFromSlaveControl(dataFromSlaveControl),
.dataFromEP0RxFifo(dataFromEP0RxFifo),
.dataFromEP1RxFifo(dataFromEP1RxFifo),
.dataFromEP2RxFifo(dataFromEP2RxFifo),
.dataFromEP3RxFifo(dataFromEP3RxFifo),
.dataFromEP0TxFifo(dataFromEP0TxFifo),
.dataFromEP1TxFifo(dataFromEP1TxFifo),
.dataFromEP2TxFifo(dataFromEP2TxFifo),
.dataFromEP3TxFifo(dataFromEP3TxFifo),
.dataFromHostSlaveMux(dataFromHostSlaveMux)
);
assign SIEPortCtrlInToSIE = SIEPortCtrlInFromSlave;
assign SIEPortDataInToSIE = SIEPortDataInFromSlave;
assign SIEPortWEnToSIE = SIEPortWEnFromSlave;
assign fullSpeedPolarityToSIE = fullSpeedPolarityFromSlave;
assign fullSpeedBitRateToSIE = fullSpeedBitRateFromSlave;
assign noActivityTimeOutEnableToSIE = noActivityTimeOutEnableFromSlave;
hostSlaveMuxBI u_hostSlaveMuxBI (
.dataIn(data_i),
.dataOut(dataFromHostSlaveMux),
.address(address_i[0]),
.writeEn(we_i),
.strobe_i(strobe_i),
.usbClk(usbClk),
.busClk(clk_i),
.hostSlaveMuxSel(hostSlaveMuxSel),
.hostMode(),
.rstFromWire(rst_i),
.rstSyncToBusClkOut(rstSyncToBusClk),
.rstSyncToUsbClkOut(rstSyncToUsbClk)
);
usbSerialInterfaceEngine u_usbSerialInterfaceEngine(
.clk(usbClk),
.rst(rstSyncToUsbClk),
.USBWireDataIn(USBWireDataIn),
.USBWireDataOut(USBWireDataOut),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.connectState(connectState),
.resumeDetected(resumeDetected),
.RxCtrlOut(RxCtrlOut),
.RxDataOutWEn(RxDataOutWEn),
.RxDataOut(RxDataFromSIE),
.SIEPortCtrlIn(SIEPortCtrlInToSIE),
.SIEPortDataIn(SIEPortDataInToSIE),
.SIEPortTxRdy(SIEPortTxRdy),
.SIEPortWEn(SIEPortWEnToSIE),
.fullSpeedPolarity(fullSpeedPolarityToSIE),
.fullSpeedBitRate(fullSpeedBitRateToSIE),
.noActivityTimeOut(noActivityTimeOut),
.noActivityTimeOutEnable(noActivityTimeOutEnableToSIE)
);
//---Slave fifos
TxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP0REn),
.fifoEmpty(TxFifoEP0Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP0TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP0TxFifo),
.fifoDataOut(TxFifoEP0Data) );
TxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP1REn),
.fifoEmpty(TxFifoEP1Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP1TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP1TxFifo),
.fifoDataOut(TxFifoEP1Data) );
TxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP2REn),
.fifoEmpty(TxFifoEP2Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP2TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP2TxFifo),
.fifoDataOut(TxFifoEP2Data) );
TxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3TxFifo (
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoREn(TxFifoEP3REn),
.fifoEmpty(TxFifoEP3Empty),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP3TxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP3TxFifo),
.fifoDataOut(TxFifoEP3Data) );
RxFifo #(EP0_FIFO_DEPTH, EP0_FIFO_ADDR_WIDTH) EP0RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP0WEn),
.fifoFull(RxFifoEP0Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP0RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP0RxFifo),
.fifoDataIn(slaveRxFifoData) );
RxFifo #(EP1_FIFO_DEPTH, EP1_FIFO_ADDR_WIDTH) EP1RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP1WEn),
.fifoFull(RxFifoEP1Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP1RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP1RxFifo),
.fifoDataIn(slaveRxFifoData) );
RxFifo #(EP2_FIFO_DEPTH, EP2_FIFO_ADDR_WIDTH) EP2RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP2WEn),
.fifoFull(RxFifoEP2Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP2RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP2RxFifo),
.fifoDataIn(slaveRxFifoData) );
RxFifo #(EP3_FIFO_DEPTH, EP3_FIFO_ADDR_WIDTH) EP3RxFifo(
.usbClk(usbClk),
.busClk(clk_i),
.rstSyncToBusClk(rstSyncToBusClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.fifoWEn(RxFifoEP3WEn),
.fifoFull(RxFifoEP3Full),
.busAddress(address_i[2:0]),
.busWriteEn(we_i),
.busStrobe_i(strobe_i),
.busFifoSelect(slaveEP3RxFifoSel),
.busDataIn(data_i),
.busDataOut(dataFromEP3RxFifo),
.fifoDataIn(slaveRxFifoData) );
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 3
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module blk_mem_gen_1 (
clka,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [18 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [9 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [9 : 0] douta;
blk_mem_gen_v8_3_3 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("blk_mem_gen_1.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(10),
.C_READ_WIDTH_A(10),
.C_WRITE_DEPTH_A(307200),
.C_READ_DEPTH_A(307200),
.C_ADDRA_WIDTH(19),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(10),
.C_READ_WIDTH_B(10),
.C_WRITE_DEPTH_B(307200),
.C_READ_DEPTH_B(307200),
.C_ADDRB_WIDTH(19),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("84"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 4.847786 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(19'B0),
.dinb(10'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(10'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// system_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.18.10:44:14
`timescale 1 ps / 1 ps
module system_mm_interconnect_0 (
input wire acl_iface_kernel_clk_clk, // acl_iface_kernel_clk.clk
input wire Gray_Processing_system_clock_reset_reset_reset_bridge_in_reset_reset, // Gray_Processing_system_clock_reset_reset_reset_bridge_in_reset.reset
input wire [29:0] Gray_Processing_system_avm_memgmem0_port_0_0_rw_address, // Gray_Processing_system_avm_memgmem0_port_0_0_rw.address
output wire Gray_Processing_system_avm_memgmem0_port_0_0_rw_waitrequest, // .waitrequest
input wire [4:0] Gray_Processing_system_avm_memgmem0_port_0_0_rw_burstcount, // .burstcount
input wire [31:0] Gray_Processing_system_avm_memgmem0_port_0_0_rw_byteenable, // .byteenable
input wire Gray_Processing_system_avm_memgmem0_port_0_0_rw_read, // .read
output wire [255:0] Gray_Processing_system_avm_memgmem0_port_0_0_rw_readdata, // .readdata
output wire Gray_Processing_system_avm_memgmem0_port_0_0_rw_readdatavalid, // .readdatavalid
input wire Gray_Processing_system_avm_memgmem0_port_0_0_rw_write, // .write
input wire [255:0] Gray_Processing_system_avm_memgmem0_port_0_0_rw_writedata, // .writedata
output wire [29:0] acl_iface_kernel_mem0_address, // acl_iface_kernel_mem0.address
output wire acl_iface_kernel_mem0_write, // .write
output wire acl_iface_kernel_mem0_read, // .read
input wire [255:0] acl_iface_kernel_mem0_readdata, // .readdata
output wire [255:0] acl_iface_kernel_mem0_writedata, // .writedata
output wire [4:0] acl_iface_kernel_mem0_burstcount, // .burstcount
output wire [31:0] acl_iface_kernel_mem0_byteenable, // .byteenable
input wire acl_iface_kernel_mem0_readdatavalid, // .readdatavalid
input wire acl_iface_kernel_mem0_waitrequest, // .waitrequest
output wire acl_iface_kernel_mem0_debugaccess // .debugaccess
);
wire gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_waitrequest; // acl_iface_kernel_mem0_translator:uav_waitrequest -> Gray_Processing_system_avm_memgmem0_port_0_0_rw_translator:uav_waitrequest
wire [9:0] gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_burstcount; // Gray_Processing_system_avm_memgmem0_port_0_0_rw_translator:uav_burstcount -> acl_iface_kernel_mem0_translator:uav_burstcount
wire [255:0] gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_writedata; // Gray_Processing_system_avm_memgmem0_port_0_0_rw_translator:uav_writedata -> acl_iface_kernel_mem0_translator:uav_writedata
wire [29:0] gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_address; // Gray_Processing_system_avm_memgmem0_port_0_0_rw_translator:uav_address -> acl_iface_kernel_mem0_translator:uav_address
wire gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_lock; // Gray_Processing_system_avm_memgmem0_port_0_0_rw_translator:uav_lock -> acl_iface_kernel_mem0_translator:uav_lock
wire gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_write; // Gray_Processing_system_avm_memgmem0_port_0_0_rw_translator:uav_write -> acl_iface_kernel_mem0_translator:uav_write
wire gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_read; // Gray_Processing_system_avm_memgmem0_port_0_0_rw_translator:uav_read -> acl_iface_kernel_mem0_translator:uav_read
wire [255:0] gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdata; // acl_iface_kernel_mem0_translator:uav_readdata -> Gray_Processing_system_avm_memgmem0_port_0_0_rw_translator:uav_readdata
wire gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_debugaccess; // Gray_Processing_system_avm_memgmem0_port_0_0_rw_translator:uav_debugaccess -> acl_iface_kernel_mem0_translator:uav_debugaccess
wire [31:0] gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_byteenable; // Gray_Processing_system_avm_memgmem0_port_0_0_rw_translator:uav_byteenable -> acl_iface_kernel_mem0_translator:uav_byteenable
wire gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdatavalid; // acl_iface_kernel_mem0_translator:uav_readdatavalid -> Gray_Processing_system_avm_memgmem0_port_0_0_rw_translator:uav_readdatavalid
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (1),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) gray_processing_system_avm_memgmem0_port_0_0_rw_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (Gray_Processing_system_clock_reset_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_read), // .read
.uav_write (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Gray_Processing_system_avm_memgmem0_port_0_0_rw_address), // avalon_anti_master_0.address
.av_waitrequest (Gray_Processing_system_avm_memgmem0_port_0_0_rw_waitrequest), // .waitrequest
.av_burstcount (Gray_Processing_system_avm_memgmem0_port_0_0_rw_burstcount), // .burstcount
.av_byteenable (Gray_Processing_system_avm_memgmem0_port_0_0_rw_byteenable), // .byteenable
.av_read (Gray_Processing_system_avm_memgmem0_port_0_0_rw_read), // .read
.av_readdata (Gray_Processing_system_avm_memgmem0_port_0_0_rw_readdata), // .readdata
.av_readdatavalid (Gray_Processing_system_avm_memgmem0_port_0_0_rw_readdatavalid), // .readdatavalid
.av_write (Gray_Processing_system_avm_memgmem0_port_0_0_rw_write), // .write
.av_writedata (Gray_Processing_system_avm_memgmem0_port_0_0_rw_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (256),
.UAV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) acl_iface_kernel_mem0_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (Gray_Processing_system_clock_reset_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_read), // .read
.uav_write (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (gray_processing_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (acl_iface_kernel_mem0_address), // avalon_anti_slave_0.address
.av_write (acl_iface_kernel_mem0_write), // .write
.av_read (acl_iface_kernel_mem0_read), // .read
.av_readdata (acl_iface_kernel_mem0_readdata), // .readdata
.av_writedata (acl_iface_kernel_mem0_writedata), // .writedata
.av_burstcount (acl_iface_kernel_mem0_burstcount), // .burstcount
.av_byteenable (acl_iface_kernel_mem0_byteenable), // .byteenable
.av_readdatavalid (acl_iface_kernel_mem0_readdatavalid), // .readdatavalid
.av_waitrequest (acl_iface_kernel_mem0_waitrequest), // .waitrequest
.av_debugaccess (acl_iface_kernel_mem0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O32AI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O32AI_BEHAVIORAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O32AI_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32OI_2_V
`define SKY130_FD_SC_HDLL__A32OI_2_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a32oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a32oi_2 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32OI_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_BEHAVIORAL_PP_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: txc_engine_ultrascale.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TXC Engine takes unformatted completions, formats
// these packets into AXI-style packets. These packets must meet max-request,
// max-payload, and payload termination requirements (see Read Completion
// Boundary). The TXC Engine does not check these requirements during operation,
// but may do so during simulation.
//
// This Engine is capable of operating at "line rate".
//
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "ultrascale.vh"
module txc_engine_ultrascale
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_PAYLOAD_DWORDS = 256
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY
);
localparam C_VENDOR = "XILINX";
localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
localparam C_MAX_HDR_WIDTH = 128; // It's really 96... But it gets trimmed
localparam C_MAX_HDR_DWORDS = C_MAX_HDR_WIDTH/32;
localparam C_MAX_ALIGN_DWORDS = 0;
localparam C_MAX_NONPAY_DWORDS = C_MAX_HDR_DWORDS + C_MAX_ALIGN_DWORDS;
//
localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
/*AUTOWIRE*/
/*AUTOINPUT*/
///*AUTOOUTPUT*/
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
wire wTxDataReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxData;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
wire wTxDataStartFlag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataWordValid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataWordReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxcPkt;
wire wTxcPktEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktEndOffset;
wire wTxcPktStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktStartOffset;
wire wTxcPktValid;
wire wTxcPktReady;
txc_formatter_ultrascale
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH))
txc_formatter_inst
(
// Outputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
tx_engine
#(
.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
txc_engine_inst
(
// Outputs
.TX_HDR_READY (wTxHdrReady),
.TX_DATA_READY (TXC_DATA_READY),
.TX_PKT (wTxcPkt[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (wTxcPktStartFlag),
.TX_PKT_START_OFFSET (wTxcPktStartOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (wTxcPktEndFlag),
.TX_PKT_END_OFFSET (wTxcPktEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (wTxcPktValid),
// Inputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_DATA_VALID (TXC_DATA_VALID),
.TX_DATA (TXC_DATA[C_DATA_WIDTH-1:0]),
.TX_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TX_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TX_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_READY (wTxcPktReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
txc_translation_layer
#(
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT)
/*AUTOINSTPARAM*/)
txc_trans_inst
(
// Outputs
.TXC_PKT_READY (wTxcPktReady),
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.TXC_PKT (wTxcPkt),
.TXC_PKT_VALID (wTxcPktValid),
.TXC_PKT_START_FLAG (wTxcPktStartFlag),
.TXC_PKT_START_OFFSET (wTxcPktStartOffset),
.TXC_PKT_END_FLAG (wTxcPktEndFlag),
.TXC_PKT_END_OFFSET (wTxcPktEndOffset),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY)
/*AUTOINST*/);
endmodule // txc_engine_ultrascale
module txc_formatter_ultrascale
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_HDR_WIDTH = `UPKT_TXC_MAXHDR_W
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXC
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
// Interface: TX HDR
output TX_HDR_VALID,
output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
output TX_HDR_NOPAYLOAD,
input TX_HDR_READY
);
wire [`UPKT_TXC_MAXHDR_W-1:0] wHdr;
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
// Generic Header Fields
// ATYPE Should be copied from the request parameters, but we only use 0
assign wHdr[`UPKT_TXC_ADDRLOW_R] = TXC_META_ADDR;
assign wHdr[`UPKT_TXC_RSVD0_R] = `UPKT_TXC_RSVD0_W'd0;
assign wHdr[`UPKT_TXC_ATYPE_R] = `UPKT_TXC_ATYPE_W'd0;
assign wHdr[`UPKT_TXC_RSVD1_R] = `UPKT_TXC_RSVD1_W'd0;
assign wHdr[`UPKT_TXC_BYTECNT_R] = {1'b0,TXC_META_BYTE_COUNT};
assign wHdr[`UPKT_TXC_LOCKED_R] = `UPKT_TXC_LOCKED_W'd0;
assign wHdr[`UPKT_TXC_RSVD2_R] = `UPKT_TXC_RSVD2_W'd0;
assign wHdr[`UPKT_TXC_LENGTH_R] = {1'b0, TXC_META_LENGTH};
assign wHdr[`UPKT_TXC_STATUS_R] = `UPKT_TXC_STATUS_W'd0;
assign wHdr[`UPKT_TXC_EP_R] = TXC_META_EP;
assign wHdr[`UPKT_TXC_RSVD3_R] = `UPKT_TXC_RSVD3_W'd0;
assign wHdr[`UPKT_TXC_REQID_R] = TXC_META_REQUESTER_ID;
assign wHdr[`UPKT_TXC_TAG_R] = TXC_META_TAG;
assign wHdr[`UPKT_TXC_CPLID_R] = CONFIG_COMPLETER_ID;
assign wHdr[`UPKT_TXC_CPLIDEN_R] = 1'b0;
assign wHdr[`UPKT_TXC_TC_R] = TXC_META_TC;
assign wHdr[`UPKT_TXC_ATTR_R] = TXC_META_ATTR;
assign wHdr[`UPKT_TXC_TD_R] = `UPKT_TXC_TD_W'd0;
assign wTxHdrNopayload = ~wTxType[`TRLS_TYPE_PAY_I];
assign wTxHdrNonpayLen = 3;
assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`UPKT_TXC_LENGTH_I +: `SIG_LEN_W];
assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_TYPE_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(
// Outputs
.WR_DATA_READY (TXC_META_READY),
.RD_DATA ({wTxHdr,wTxType}),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA ({32'b0,wHdr,TXC_META_TYPE}),
.WR_DATA_VALID (TXC_META_VALID),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wTxHdrReady),
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
.RD_DATA_VALID (TX_HDR_VALID),
// Inputs
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
.WR_DATA_VALID (wTxHdrValid),
.RD_DATA_READY (TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
module txc_translation_layer
#(
parameter C_PCI_DATA_WIDTH = 10'd128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: TXC Classic
output TXC_PKT_READY,
input [C_PCI_DATA_WIDTH-1:0] TXC_PKT,
input TXC_PKT_VALID,
input TXC_PKT_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_START_OFFSET,
input TXC_PKT_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_END_OFFSET,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER
);
localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0;
localparam C_OUTPUT_STAGES = C_PIPELINE_OUTPUT != 0? 1:0;
wire wTxcPktReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxcPkt;
wire wTxcPktValid;
wire wTxcPktStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktStartOffset;
wire wTxcPktEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktEndOffset;
wire wSAxisCcTReady;
wire wSAxisCcTValid;
wire wSAxisCcTLast;
wire [C_PCI_DATA_WIDTH-1:0] wSAxisCcTData;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wSAxisCcTKeep;
wire [`SIG_CC_TUSER_W-1:0] wSAxisCcTUser;
/*ASSIGN TXC -> CC*/
assign wTxcPktReady = wSAxisCcTReady;
assign wSAxisCcTValid = wTxcPktValid;
assign wSAxisCcTLast = wTxcPktEndFlag;
assign wSAxisCcTData = wTxcPkt;
assign S_AXIS_CC_TUSER = `SIG_CC_TUSER_W'd0; // Do not enable parity bits, and no discontinues
pipeline
#(
// Parameters
.C_DEPTH (C_INPUT_STAGES),
.C_WIDTH (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(
// Outputs
.WR_DATA_READY (TXC_PKT_READY),
.RD_DATA ({wTxcPkt,wTxcPktStartFlag,wTxcPktStartOffset,wTxcPktEndFlag,wTxcPktEndOffset}),
.RD_DATA_VALID (wTxcPktValid),
// Inputs
.WR_DATA ({TXC_PKT,TXC_PKT_START_FLAG,TXC_PKT_START_OFFSET,
TXC_PKT_END_FLAG,TXC_PKT_END_OFFSET}),
.WR_DATA_VALID (TXC_PKT_VALID),
.RD_DATA_READY (wTxcPktReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
offset_to_mask
#(
// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
otom_inst
(
// Outputs
.MASK (wSAxisCcTKeep),
// Inputs
.OFFSET_ENABLE (wTxcPktEndFlag),
.OFFSET (wTxcPktEndOffset)
/*AUTOINST*/);
pipeline
#(
// Parameters
.C_DEPTH (C_OUTPUT_STAGES),
.C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wSAxisCcTReady),
.RD_DATA ({S_AXIS_CC_TDATA,S_AXIS_CC_TLAST,S_AXIS_CC_TKEEP}),
.RD_DATA_VALID (S_AXIS_CC_TVALID),
// Inputs
.WR_DATA ({wSAxisCcTData,wSAxisCcTLast,wSAxisCcTKeep}),
.WR_DATA_VALID (wSAxisCcTValid),
.RD_DATA_READY (S_AXIS_CC_TREADY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/" "../../common/")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_TB_V
`define SKY130_FD_SC_LS__OR3B_TB_V
/**
* or3b: 3-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or3b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C_N = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C_N = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ls__or3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O2BB2A_BEHAVIORAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_BEHAVIORAL_PP_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Feb 08 00:48:14 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Zybo-Open-Source-Video-IP-Toolbox/video_processing_examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_stub.v
// Design : system_vga_color_test_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_color_test,Vivado 2016.4" *)
module system_vga_color_test_0_0(clk_25, xaddr, yaddr, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_25,xaddr[9:0],yaddr[9:0],rgb[23:0]" */;
input clk_25;
input [9:0]xaddr;
input [9:0]yaddr;
output [23:0]rgb;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_FUNCTIONAL_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_lh (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__SDFRBP_BEHAVIORAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_r_no_pg/sky130_fd_sc_hs__u_df_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfrbp (
RESET_B,
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
VPWR ,
VGND
);
// Module ports
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input VPWR ;
input VGND ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_r_no_pg u_df_p_r_no_pg0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRBP_BEHAVIORAL_V
|
`timescale 1ns/1ns
module atto_basic_tb();
reg clka;
reg rsta;
// input channels
reg [47:0] north_channel_din;
reg [1:0] north_diff_pair_din;
reg [47:0] east_channel_din;
reg [1:0] east_diff_pair_din;
reg [47:0] pe_channel_din;
reg [1:0] pe_diff_pair_din;
// output channels
wire [47:0] south_channel_dout;
wire [1:0] south_diff_pair_dout;
wire [47:0] west_channel_dout;
wire [1:0] west_diff_pair_dout;
wire [39:0] pe_channel_dout;
wire [1:0] pe_diff_pair_dout;
wire r2pe_ack_dout;
// UUT /////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
atto UUT
(
.clka(clka),
.rsta(rsta),
// input channels
.north_channel_din (north_channel_din),
.north_diff_pair_din(north_diff_pair_din),
.east_channel_din (east_channel_din),
.east_diff_pair_din (east_diff_pair_din),
.pe_channel_din (pe_channel_din),
.pe_diff_pair_din (pe_diff_pair_din),
// output channels
.south_channel_dout (south_channel_dout),
.south_diff_pair_dout (south_diff_pair_dout),
.west_channel_dout (west_channel_dout),
.west_diff_pair_dout (west_diff_pair_dout),
.pe_channel_dout (pe_channel_dout),
.pe_diff_pair_dout (pe_diff_pair_dout),
.r2pe_ack_dout (r2pe_ack_dout)
);
////////////////////////////////////////////////////////////////////////////////
// clk generator
always
begin
#(10)
clka = ~clka;
end
// stimuli
initial
begin
// initial values
clka = 1'b0;
rsta = 1'b1;
north_channel_din = 48'b0;
north_diff_pair_din = 2'b10;
east_channel_din = 48'b0;
east_diff_pair_din = 2'b10;
pe_channel_din = 48'b0;
pe_diff_pair_din = 2'b10;
// stimuli
repeat (20)
@(negedge clka);
// out of reset
rsta = 1'b0;
repeat (10)
@(negedge clka);
// North only Request ////////////////////////////////////////////////// out :: south
////////////////////////////////////////////////////////////////////////
north_channel_din = 48'h210000000000;
north_diff_pair_din = 2'b01;
@(negedge clka);
// East only Request /////////////////////////////////////////////////// out :: west
////////////////////////////////////////////////////////////////////////
east_channel_din = 48'h121111111111;
east_diff_pair_din = 2'b01;
@(negedge clka);
// PE only Request ///////////////////////////////////////////////////// out :: south - west
////////////////////////////////////////////////////////////////////////
pe_channel_din = 48'h333333333333;
pe_diff_pair_din = 2'b01;
@(negedge clka);
// North - East Request //////////////////////////////////////////////// out :: east --> west
//////////////////////////////////////////////////////////////////////// north --> south
north_channel_din = 48'h120000000000;
north_diff_pair_din = 2'b10;
east_channel_din = 48'h121111111111;
east_diff_pair_din = 2'b10;
@(negedge clka);
// End of stimuli //////////////////////////////////////////////////////
repeat (30)
@(negedge clka);
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4BB_4_V
`define SKY130_FD_SC_MS__NOR4BB_4_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4bb_4 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4bb_4 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4BB_4_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Simple Asynchronous Serial Comm. Device ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/sasc/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: sasc_top.v,v 1.2 2006/03/30 02:47:07 rudi Exp $
//
// $Date: 2006/03/30 02:47:07 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: sasc_top.v,v $
// Revision 1.2 2006/03/30 02:47:07 rudi
// Thanks to Darren O'Connor of SPEC, Inc. for fixing a bug
// with the DPLL and data alignment:
//
// You were right that it was a problem with the dpll. I found
// that it was possible to get two baud clocks (rx_sio_ce) during
// one bit period. I fixed the problem by delaying the input data
// signal with a shift register and using that in the equations
// for the "change" variable that controls the DPLL FSM.
//
// Revision 1.1.1.1 2002/09/16 16:16:42 rudi
// Initial Checkin
//
//
//
//
//
//
//
//
`timescale 1ns / 100ps
/*
Serial IO Interface
===============================
RTS I Request To Send
CTS O Clear to send
TD I Transmit Data
RD O Receive Data
*/
module sasc_top( clk, rst_n,
// SIO
rxd_i, txd_o, cts_i, rts_o,
// External Baud Rate Generator
sio_ce, sio_ce_x4,
// Internal Interface
din_i, dout_o, re_i, we_i, full_o, empty_o);
input clk;
input rst_n;
input rxd_i;
output txd_o;
input cts_i;
output rts_o;
input sio_ce;
input sio_ce_x4;
input [7:0] din_i;
output [7:0] dout_o;
input re_i, we_i;
output full_o, empty_o;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
parameter START_BIT = 1'b0,
STOP_BIT = 1'b1,
IDLE_BIT = 1'b1;
wire [7:0] txd_p;
reg load;
wire load_e;
reg [9:0] hold_reg;
wire txf_empty;
reg txd_o;
reg shift_en;
reg [3:0] tx_bit_cnt;
reg rxd_s, rxd_r;
wire start;
reg [3:0] rx_bit_cnt;
reg rx_go;
reg [9:0] rxr;
reg rx_valid, rx_valid_r;
wire rx_we;
wire rxf_full;
reg rts_o;
reg txf_empty_r;
reg shift_en_r;
reg rxd_r1;
reg change;
reg rx_sio_ce_d, rx_sio_ce_r1, rx_sio_ce_r2, rx_sio_ce;
reg [1:0] dpll_state, dpll_next_state;
reg [5:0] rxd_dly; //New input delay used to ensure no baud clocks
// occur twice in one baud period
///////////////////////////////////////////////////////////////////
//
// IO Fifo's
//
sasc_fifo4 tx_fifo( .clk( clk ),
.rst_n( rst_n ),
.clr( 1'b0 ),
.din( din_i ),
.we( we_i ),
.dout( txd_p ),
.re( load_e ),
.full( full_o ),
.empty( txf_empty )
);
sasc_fifo4 rx_fifo( .clk( clk ),
.rst_n( rst_n ),
.clr( 1'b0 ),
.din( rxr[9:2] ),
.we( rx_we ),
.dout( dout_o ),
.re( re_i ),
.full( rxf_full ),
.empty( empty_o )
);
///////////////////////////////////////////////////////////////////
//
// Transmit Logic
//
always @(posedge clk)
if(!rst_n) txf_empty_r <= 1'b1;
else
if(sio_ce) txf_empty_r <= txf_empty;
always @(posedge clk)
load <= !txf_empty_r & !shift_en & !cts_i;
assign load_e = load & sio_ce;
always @(posedge clk)
if(load_e) hold_reg <= {STOP_BIT, txd_p, START_BIT};
else
if(shift_en & sio_ce) hold_reg <= {IDLE_BIT, hold_reg[9:1]};
always @(posedge clk)
if(!rst_n) txd_o <= IDLE_BIT;
else
if(sio_ce)
if(shift_en | shift_en_r) txd_o <= hold_reg[0];
else txd_o <= IDLE_BIT;
always @(posedge clk)
if(!rst_n) tx_bit_cnt <= 4'h9;
else
if(load_e) tx_bit_cnt <= 4'h0;
else
if(shift_en & sio_ce) tx_bit_cnt <= tx_bit_cnt + 4'h1;
always @(posedge clk)
shift_en <= (tx_bit_cnt != 4'h9);
always @(posedge clk)
if(!rst_n) shift_en_r <= 1'b0;
else
if(sio_ce) shift_en_r <= shift_en;
///////////////////////////////////////////////////////////////////
//
// Recieve Logic
//
always @(posedge clk)
begin
rxd_dly[5:1] <= rxd_dly[4:0];
rxd_dly[0] <= rxd_i;
rxd_s <= rxd_dly[5]; // rxd_s = delay 1
rxd_r <= rxd_s; // rxd_r = delay 2
end
assign start = (rxd_r == IDLE_BIT) & (rxd_s == START_BIT);
always @(posedge clk)
if(!rst_n) rx_bit_cnt <= 4'ha;
else
if(!rx_go & start) rx_bit_cnt <= 4'h0;
else
if(rx_go & rx_sio_ce) rx_bit_cnt <= rx_bit_cnt + 4'h1;
always @(posedge clk)
rx_go <= (rx_bit_cnt != 4'ha);
always @(posedge clk)
rx_valid <= (rx_bit_cnt == 4'h9);
always @(posedge clk)
rx_valid_r <= rx_valid;
assign rx_we = !rx_valid_r & rx_valid & !rxf_full;
always @(posedge clk)
if(rx_go & rx_sio_ce) rxr <= {rxd_s, rxr[9:1]};
always @(posedge clk)
rts_o <= rxf_full;
///////////////////////////////////////////////////////////////////
//
// Reciever DPLL
//
// Uses 4x baud clock to lock to incoming stream
// Edge detector
always @(posedge clk)
if(sio_ce_x4) rxd_r1 <= rxd_s;
always @(posedge clk)
if(!rst_n)
change <= 1'b0;
else if ((rxd_dly[1] != rxd_r1) || (rxd_dly[1] != rxd_s))
change <= 1'b1;
else if(sio_ce_x4)
change <= 1'b0;
// DPLL FSM
always @(posedge clk or negedge rst_n)
if(!rst_n) dpll_state <= 2'h1;
else
if(sio_ce_x4) dpll_state <= dpll_next_state;
always @(dpll_state or change)
begin
rx_sio_ce_d = 1'b0;
case(dpll_state)
2'h0:
if(change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h1;
2'h1:begin
rx_sio_ce_d = 1'b1;
if(change) dpll_next_state = 3'h3;
else dpll_next_state = 3'h2;
end
2'h2:
if(change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h3;
2'h3:
if(change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h0;
endcase
end
// Compensate for sync registers at the input - allign sio
// clock enable to be in the middle between two bit changes ...
always @(posedge clk)
rx_sio_ce_r1 <= rx_sio_ce_d;
always @(posedge clk)
rx_sio_ce_r2 <= rx_sio_ce_r1;
always @(posedge clk)
rx_sio_ce <= rx_sio_ce_r1 & !rx_sio_ce_r2;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 14
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zqynq_lab_1_design_xbar_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *)
input wire [0 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *)
output wire [0 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI AWID [11:0] [35:24], xilinx.com:interface:aximm:1.0 M03_AXI AWID [11:0] [47:36]" *)
output wire [47 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96]" *)
output wire [127 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24]" *)
output wire [31 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9]" *)
output wire [11 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6]" *)
output wire [7 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3]" *)
output wire [3 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12]" *)
output wire [15 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]" *)
output wire [11 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12]" *)
output wire [15 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12]" *)
output wire [15 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96]" *)
output wire [127 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12]" *)
output wire [15 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3]" *)
output wire [3 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI BID [11:0] [35:24], xilinx.com:interface:aximm:1.0 M03_AXI BID [11:0] [47:36]" *)
input wire [47 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]" *)
input wire [7 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]" *)
input wire [3 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]" *)
output wire [3 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI ARID [11:0] [35:24], xilinx.com:interface:aximm:1.0 M03_AXI ARID [11:0] [47:36]" *)
output wire [47 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96]" *)
output wire [127 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24]" *)
output wire [31 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9]" *)
output wire [11 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6]" *)
output wire [7 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3]" *)
output wire [3 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12]" *)
output wire [15 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]" *)
output wire [11 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12]" *)
output wire [15 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12]" *)
output wire [15 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [11:0] [23:12], xilinx.com:interface:aximm:1.0 M02_AXI RID [11:0] [35:24], xilinx.com:interface:aximm:1.0 M03_AXI RID [11:0] [47:36]" *)
input wire [47 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96]" *)
input wire [127 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]" *)
input wire [7 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3]" *)
input wire [3 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]" *)
input wire [3 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]" *)
output wire [3 : 0] m_axi_rready;
axi_crossbar_v2_1_14_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(4),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(256'H0000000040000000000000004280000000000000412100000000000041200000),
.C_M_AXI_ADDR_WIDTH(128'H0000000d000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H0000000c),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(128'H00000001000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(128'H00000001000000010000000100000001),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(32'H00000000),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000008),
.C_S_AXI_READ_ACCEPTANCE(32'H00000008),
.C_M_AXI_WRITE_ISSUING(128'H00000008000000080000000800000008),
.C_M_AXI_READ_ISSUING(128'H00000008000000080000000800000008),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(128'H00000000000000000000000000000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(4'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(4'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/02/2013 08:41:31 PM
// Design Name:
// Module Name: maxis_controller
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module maxis_controller # (
parameter TCQ = 1,
parameter M_AXIS_TDATA_WIDTH = 64,
parameter OUTSTANDING_READS = 5
) (
input axis_clk,
input axis_aresetn,
output [M_AXIS_TDATA_WIDTH-1:0] m_axis_cc_tdata,
output [32:0] m_axis_cc_tuser,
output m_axis_cc_tlast,
output [M_AXIS_TDATA_WIDTH/32-1:0] m_axis_cc_tkeep,
output m_axis_cc_tvalid,
input [3:0] m_axis_cc_tready,
input axi_cpld_valid,
output axi_cpld_ready,
input [31:0] axi_cpld_data,
output tag_mang_read_en,
input [2:0] tag_mang_tc_rd,
input [2:0] tag_mang_attr_rd,
input [15:0] tag_mang_requester_id_rd,
input [6:0] tag_mang_lower_addr_rd,
input tag_mang_completer_func_rd,
input [7:0] tag_mang_tag_rd,
input [3:0] tag_mang_first_be_rd,
input completion_ur_req,
input [7:0] completion_ur_tag,
input [6:0] completion_ur_lower_addr,
input [3:0] completion_ur_first_be,
input [15:0] completion_ur_requester_id,
input [2:0] completion_ur_tc,
input [2:0] completion_ur_attr,
output reg completion_ur_done
);
localparam IDLE = 5'b00001;
localparam TLP_BEAT1_64 = 5'b00010;
localparam TLP_BEAT1_128 = 5'b00010;
localparam TLP_BEAT1_256 = 5'b00010;
localparam TLP_BEAT2_64 = 5'b00100;
localparam TLP_BEAT1_UR_64 = 5'b01000;
localparam TLP_BEAT1_UR_128 = 5'b01000;
localparam TLP_BEAT1_UR_256 = 5'b01000;
localparam TLP_BEAT2_UR_64 = 5'b10000;
reg [4:0] maxis_sm;
reg [2:0] tag_mang_byte_count;
reg [2:0] completion_ur_byte_count;
reg [OUTSTANDING_READS-1:0] tag_mang_read_id_r;
reg axi_cpld_ready_r;
reg tag_mang_read_en_r;
reg [31:0] axi_cpld_data_r;
reg m_axis_cc_tvalid_r;
reg m_axis_cc_tlast_r;
reg [M_AXIS_TDATA_WIDTH-1:0] m_axis_cc_tdata_r;
reg [M_AXIS_TDATA_WIDTH/32-1:0] m_axis_cc_tkeep_r;
wire [31:0] dw1_header_32;
wire [31:0] dw2_header_32;
wire [31:0] dw3_header_32;
wire [31:0] dw1_header_32_ur;
wire [31:0] dw2_header_32_ur;
wire [31:0] dw3_header_32_ur;
generate
if ( M_AXIS_TDATA_WIDTH == 64 ) begin: M_AXIS_TDATA_WIDTH_64
always @(posedge axis_clk)
if (!axis_aresetn) begin
maxis_sm <= #TCQ IDLE;
axi_cpld_ready_r <= #TCQ 1'b0;
m_axis_cc_tvalid_r <= #TCQ 1'b0;
m_axis_cc_tlast_r <= #TCQ 1'b0;
m_axis_cc_tkeep_r <= #TCQ 2'h3;
completion_ur_done <= #TCQ 1'b0;
end
else
case (maxis_sm)
IDLE : begin
if ( axi_cpld_valid ) begin
axi_cpld_ready_r <= #TCQ 1'b0;
maxis_sm <= #TCQ TLP_BEAT1_64;
end else if ( completion_ur_req & ~completion_ur_done ) begin
maxis_sm <= #TCQ TLP_BEAT1_UR_64;
axi_cpld_ready_r <= #TCQ 1'b0;
end else begin
axi_cpld_ready_r <= #TCQ 1'b1;
end
m_axis_cc_tvalid_r <= #TCQ 1'b0;
completion_ur_done <= #TCQ 1'b0;
m_axis_cc_tkeep_r <= #TCQ 2'h3;
end
TLP_BEAT1_64 : begin
if ( (m_axis_cc_tready[0] == 1'b1 ) & m_axis_cc_tvalid ) begin
maxis_sm <= #TCQ TLP_BEAT2_64;
m_axis_cc_tdata_r <= #TCQ { axi_cpld_data_r, dw3_header_32 };
m_axis_cc_tlast_r <= #TCQ 1'b1;
end else begin
m_axis_cc_tdata_r <= #TCQ { dw2_header_32, dw1_header_32 };
end
m_axis_cc_tvalid_r <= #TCQ 1'b1;
end
TLP_BEAT2_64 : begin
if ( (m_axis_cc_tready[0] == 1'b1 ) & m_axis_cc_tvalid & !completion_ur_req ) begin
maxis_sm <= #TCQ IDLE;
m_axis_cc_tvalid_r <= #TCQ 1'b0;
m_axis_cc_tlast_r <= #TCQ 1'b0;
axi_cpld_ready_r <= #TCQ 1'b1;
end else if ( (m_axis_cc_tready[0] == 1'b1 ) & m_axis_cc_tvalid & completion_ur_req ) begin
maxis_sm <= #TCQ TLP_BEAT1_UR_64;
axi_cpld_ready_r <= #TCQ 1'b0;
m_axis_cc_tvalid_r <= #TCQ 1'b0;
m_axis_cc_tlast_r <= #TCQ 1'b0;
end
m_axis_cc_tdata_r <= #TCQ { axi_cpld_data_r, dw3_header_32 };
end
TLP_BEAT1_UR_64 : begin
if ( (m_axis_cc_tready[0] == 1'b1 ) & m_axis_cc_tvalid ) begin
maxis_sm <= #TCQ TLP_BEAT2_UR_64;
m_axis_cc_tdata_r <= #TCQ { 32'd0, dw3_header_32_ur };
m_axis_cc_tlast_r <= #TCQ 1'b1;
m_axis_cc_tkeep_r <= #TCQ 2'h1;
end else begin
m_axis_cc_tdata_r <= #TCQ { dw2_header_32_ur, dw1_header_32_ur };
end
m_axis_cc_tvalid_r <= #TCQ 1'b1;
end
TLP_BEAT2_UR_64 : begin
if ( (m_axis_cc_tready[0] == 1'b1 ) & m_axis_cc_tvalid ) begin
maxis_sm <= #TCQ IDLE;
m_axis_cc_tvalid_r <= #TCQ 1'b0;
m_axis_cc_tlast_r <= #TCQ 1'b0;
axi_cpld_ready_r <= #TCQ 1'b1;
completion_ur_done <= #TCQ 1'b1;
m_axis_cc_tkeep_r <= #TCQ 2'h3;
end else begin
m_axis_cc_tvalid_r <= #TCQ 1'b1;
end
end
default: begin // Fault Recovery
maxis_sm <= #TCQ IDLE;
end
endcase
end else if (M_AXIS_TDATA_WIDTH == 128) begin: M_AXIS_TDATA_WIDTH_128
always @(posedge axis_clk)
if (!axis_aresetn) begin
maxis_sm <= #TCQ IDLE;
axi_cpld_ready_r <= #TCQ 1'b0;
m_axis_cc_tvalid_r <= #TCQ 1'b0;
m_axis_cc_tlast_r <= #TCQ 1'b0;
m_axis_cc_tkeep_r <= #TCQ 4'hF;
completion_ur_done <= #TCQ 1'b0;
end
else
case (maxis_sm)
IDLE : begin
if ( axi_cpld_valid ) begin
axi_cpld_ready_r <= #TCQ 1'b0;
maxis_sm <= #TCQ TLP_BEAT1_128;
m_axis_cc_tkeep_r <= #TCQ 4'hF;
end else if ( completion_ur_req & ~completion_ur_done ) begin
axi_cpld_ready_r <= #TCQ 1'b0;
maxis_sm <= #TCQ TLP_BEAT1_UR_128;
m_axis_cc_tkeep_r <= #TCQ 4'h7; //no payload for UR Completion
end else begin
axi_cpld_ready_r <= #TCQ 1'b1;
end
m_axis_cc_tvalid_r <= #TCQ 1'b0;
completion_ur_done <= #TCQ 1'b0;
end
TLP_BEAT1_128 : begin
if ( (m_axis_cc_tready[0] == 1'b1 ) & m_axis_cc_tvalid & completion_ur_req ) begin
maxis_sm <= #TCQ TLP_BEAT1_UR_128;
m_axis_cc_tlast_r <= #TCQ 1'b0;
m_axis_cc_tvalid_r <= #TCQ 1'b0;
m_axis_cc_tkeep_r <= #TCQ 4'h7; //no payload for UR Completion
end else if ( (m_axis_cc_tready[0] == 1'b1 ) & m_axis_cc_tvalid ) begin
maxis_sm <= #TCQ IDLE;
m_axis_cc_tlast_r <= #TCQ 1'b0;
m_axis_cc_tvalid_r <= #TCQ 1'b0;
end else begin
m_axis_cc_tlast_r <= #TCQ 1'b1;
m_axis_cc_tvalid_r <= #TCQ 1'b1;
end
m_axis_cc_tdata_r <= #TCQ { axi_cpld_data_r, dw3_header_32, dw2_header_32, dw1_header_32 };
end
TLP_BEAT1_UR_128 : begin
if ( (m_axis_cc_tready[0] == 1'b1 ) & m_axis_cc_tvalid ) begin
maxis_sm <= #TCQ IDLE;
m_axis_cc_tlast_r <= #TCQ 1'b0;
m_axis_cc_tvalid_r <= #TCQ 1'b0;
completion_ur_done <= #TCQ 1'b1;
end else begin
m_axis_cc_tlast_r <= #TCQ 1'b1;
m_axis_cc_tvalid_r <= #TCQ 1'b1;
end
m_axis_cc_tdata_r <= #TCQ { 32'd0, dw3_header_32_ur, dw2_header_32_ur, dw1_header_32_ur };
end
default: begin // Fault Recovery
maxis_sm <= #TCQ IDLE;
end
endcase
end else if (M_AXIS_TDATA_WIDTH == 256) begin: M_AXIS_TDATA_WIDTH_256
always @(posedge axis_clk)
if (!axis_aresetn) begin
maxis_sm <= #TCQ IDLE;
axi_cpld_ready_r <= #TCQ 1'b0;
m_axis_cc_tvalid_r <= #TCQ 1'b0;
m_axis_cc_tlast_r <= #TCQ 1'b0;
m_axis_cc_tkeep_r <= #TCQ 8'h0F;
completion_ur_done <= #TCQ 1'b0;
end
else
case (maxis_sm)
IDLE : begin
if ( axi_cpld_valid ) begin
axi_cpld_ready_r <= #TCQ 1'b0;
maxis_sm <= #TCQ TLP_BEAT1_256;
m_axis_cc_tkeep_r <= #TCQ 8'h0F;
end else if ( completion_ur_req & ~completion_ur_done ) begin
axi_cpld_ready_r <= #TCQ 1'b0;
maxis_sm <= #TCQ TLP_BEAT1_UR_256;
m_axis_cc_tkeep_r <= #TCQ 8'h07;
end else begin
axi_cpld_ready_r <= #TCQ 1'b1;
end
m_axis_cc_tvalid_r <= #TCQ 1'b0;
completion_ur_done <= #TCQ 1'b0;
end
TLP_BEAT1_256 : begin
if ( (m_axis_cc_tready[0] == 1'b1 ) & m_axis_cc_tvalid & completion_ur_req ) begin
maxis_sm <= #TCQ TLP_BEAT1_UR_256;
m_axis_cc_tlast_r <= #TCQ 1'b0;
m_axis_cc_tvalid_r <= #TCQ 1'b0;
m_axis_cc_tkeep_r <= #TCQ 8'h07;
end else if ( (m_axis_cc_tready[0] == 1'b1 ) & m_axis_cc_tvalid ) begin
maxis_sm <= #TCQ IDLE;
m_axis_cc_tlast_r <= #TCQ 1'b0;
m_axis_cc_tvalid_r <= #TCQ 1'b0;
end else begin
m_axis_cc_tlast_r <= #TCQ 1'b1;
m_axis_cc_tvalid_r <= #TCQ 1'b1;
end
m_axis_cc_tdata_r <= #TCQ { axi_cpld_data_r, dw3_header_32, dw2_header_32, dw1_header_32 };
end
TLP_BEAT1_UR_256 : begin
if ( (m_axis_cc_tready[0] == 1'b1 ) & m_axis_cc_tvalid ) begin
maxis_sm <= #TCQ IDLE;
m_axis_cc_tlast_r <= #TCQ 1'b0;
m_axis_cc_tvalid_r <= #TCQ 1'b0;
completion_ur_done <= #TCQ 1'b1;
end else begin
m_axis_cc_tlast_r <= #TCQ 1'b1;
m_axis_cc_tvalid_r <= #TCQ 1'b1;
end
m_axis_cc_tdata_r <= #TCQ { 32'd0, dw3_header_32_ur, dw2_header_32_ur, dw1_header_32_ur };
end
default: begin // Fault Recovery
maxis_sm <= #TCQ IDLE;
end
endcase
end
endgenerate
always @(posedge axis_clk) begin
if (axi_cpld_valid & axi_cpld_ready) begin
axi_cpld_data_r <= #TCQ axi_cpld_data;
end
end
assign tag_mang_read_en = (axi_cpld_valid & axi_cpld_ready) ? 1'b1 : 1'b0;
always @( tag_mang_first_be_rd )
casex ( tag_mang_first_be_rd )
4'b1xx1: tag_mang_byte_count <= 3'b100;
4'b01x1: tag_mang_byte_count <= 3'b011;
4'b1x10: tag_mang_byte_count <= 3'b011;
4'b0011: tag_mang_byte_count <= 3'b010;
4'b0110: tag_mang_byte_count <= 3'b010;
4'b1100: tag_mang_byte_count <= 3'b010;
4'b0001: tag_mang_byte_count <= 3'b001;
4'b0010: tag_mang_byte_count <= 3'b001;
4'b0100: tag_mang_byte_count <= 3'b001;
4'b1000: tag_mang_byte_count <= 3'b001;
4'b0000: tag_mang_byte_count <= 3'b001;
default: tag_mang_byte_count <= 3'b000;
endcase
always @( completion_ur_first_be )
casex ( completion_ur_first_be )
4'b1xx1: completion_ur_byte_count <= 3'b100;
4'b01x1: completion_ur_byte_count <= 3'b011;
4'b1x10: completion_ur_byte_count <= 3'b011;
4'b0011: completion_ur_byte_count <= 3'b010;
4'b0110: completion_ur_byte_count <= 3'b010;
4'b1100: completion_ur_byte_count <= 3'b010;
4'b0001: completion_ur_byte_count <= 3'b001;
4'b0010: completion_ur_byte_count <= 3'b001;
4'b0100: completion_ur_byte_count <= 3'b001;
4'b1000: completion_ur_byte_count <= 3'b001;
4'b0000: completion_ur_byte_count <= 3'b001;
default: completion_ur_byte_count <= 3'b000;
endcase
assign tag_mang_read_id = tag_mang_read_id_r;
assign axi_cpld_ready = axi_cpld_ready_r;
// assign tag_mang_read_en = tag_mang_read_en_r;
assign dw1_header_32 = { 13'd0 ,tag_mang_byte_count, 9'd0, tag_mang_lower_addr_rd };
assign dw2_header_32 = { tag_mang_requester_id_rd, 16'd1 };
assign dw3_header_32 = { 1'b0, tag_mang_attr_rd, tag_mang_tc_rd, 1'd0, 16'd0, tag_mang_tag_rd };
assign dw1_header_32_ur = { 13'd0 ,completion_ur_byte_count, 9'd0, completion_ur_lower_addr };
assign dw2_header_32_ur = { completion_ur_requester_id, 5'd1 ,11'd0 }; //Sets the UR bit
assign dw3_header_32_ur = { 1'b0, completion_ur_attr, completion_ur_tc, 1'd0, 16'd0, completion_ur_tag };
assign m_axis_cc_tuser = 32'd0;
assign m_axis_cc_tkeep = m_axis_cc_tkeep_r;
assign m_axis_cc_tlast = m_axis_cc_tlast_r;
assign m_axis_cc_tdata = m_axis_cc_tdata_r;
assign m_axis_cc_tvalid = m_axis_cc_tvalid_r;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BAI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O21BAI_FUNCTIONAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21bai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BAI_FUNCTIONAL_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file lookuptable3.v when simulating
// the core, lookuptable3. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module lookuptable3(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [12 : 0] addra;
input [27 : 0] dina;
output [27 : 0] douta;
input clkb;
input [0 : 0] web;
input [14 : 0] addrb;
input [6 : 0] dinb;
output [6 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(15),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("lookuptable3.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(32768),
.C_READ_WIDTH_A(28),
.C_READ_WIDTH_B(7),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(32768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(28),
.C_WRITE_WIDTH_B(7),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
`include "MU/tristate.v"
`include "MU/d-flipflop.v"
`include "MU/Mux.v" //`
module Register(Bus_in,clk,reset,r_in,r_out,Bus_out);
input Bus_in,clk,reset,r_in,r_out;
output Bus_out;
wire Flip_out,D,qb;
Mux M(Flip_out,Bus_in,r_in,D);
//not dnot(Bus_out, D);
dff F(Flip_out, qb, clk,reset, D);
//not n1(Bus_out, ~Flip_out);
tristate tr(Bus_out, Flip_out, r_out);
endmodule
/*
module RegisterTest;
Register r1(Bus_in, clk, reset, r_in, r_out, Bus_out);
reg Bus_in, clk, reset, r_in, r_out;
output Bus_out;
initial
begin
$display("\t\t %5s | %5s | %5s |----| %5s | %5s |", "RESET", "RIN", "ROUT", "BUSIN", "BOUT");
$monitor($time, ": %5b | %5b | %5b |----| %5b | %5b |", reset, r_in, r_out, Bus_in, Bus_out);
reset = 1; clk = 1;
#10 r_in = 0; r_out = 0; Bus_in = 0; reset = 0; //No Stroring and no retrieval
#10 r_in = 0; r_out = 0; Bus_in = 1; //No Stroring and no retrieval
#10 r_in = 1; r_out = 0; Bus_in = 0; //Storing But no Retreival
#10 r_in = 0; r_out = 1; Bus_in = 0; //No Storing But Retrieval
#10 r_in = 0; r_out = 1; Bus_in = 1; //No Storing But Retrieval
#10 r_in = 1; r_out = 1; Bus_in = 1; //Storing and Retreival
#10 r_in = 1; r_out = 1; Bus_in = 0; //Storing and Retreival
#10 r_in = 1; r_out = 0; Bus_in = 1; //Storing But no Retreival
#10 r_in = 0; r_out = 1; Bus_in = 0; //No Storing But Retrieval
#10 r_in = 0; r_out = 1; Bus_in = 1; //No Storing But Retrieval
#10 r_in = 1; r_out = 1; Bus_in = 0; //Storing and Retreival
//#10 r_in = 1; r_out = 1; Bus_in = 1;
//#10 r_in = 0; r_out = 1; Bus_in = 0; //No Storing but Retrieval
//#10 r_in = 0; r_out = 1; Bus_in = 0;
$finish();
end
always
begin: CLOCKGEN
#5 clk = ~clk;
end
endmodule
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFXBP_PP_BLACKBOX_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfxbp (
CLK ,
D ,
Q ,
Q_N ,
VPWR,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXBP_PP_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx(/*AUTOARG*/
// Outputs
pcx_spc7_grant_px, pcx_spc6_grant_px, pcx_spc5_grant_px,
pcx_spc4_grant_px, pcx_spc3_grant_px, pcx_spc2_grant_px,
pcx_spc1_grant_px, pcx_spc0_grant_px, pcx_sctag3_data_rdy_px1,
pcx_sctag3_data_px2, pcx_sctag3_atm_px1, pcx_sctag2_data_rdy_px1,
pcx_sctag2_data_px2, pcx_sctag2_atm_px1, pcx_sctag1_data_rdy_px1,
pcx_sctag1_data_px2, pcx_sctag1_atm_px1, pcx_sctag0_data_rdy_px1,
pcx_sctag0_data_px2, pcx_sctag0_atm_px1, pcx_scache2_dat_px2_so_1,
pcx_scache1_dat_px2_so_1, pcx_scache0_dat_px2_so_1,
pcx_iodata_px2_so_1, pcx_io_data_rdy_px2, pcx_io_data_px2,
pcx_fpio_data_rdy_px2, pcx_fpio_data_px2, pcx_buf_top_pt0_so_0,
arst_l_buf_fpio_inff,
// Inputs
spc7_pcx_req_pq, spc7_pcx_atom_pq, spc6_pcx_req_pq,
spc6_pcx_atom_pq, spc5_pcx_req_pq, spc5_pcx_atom_pq,
spc4_pcx_req_pq, spc4_pcx_atom_pq, spc3_pcx_req_pq,
spc3_pcx_atom_pq, spc2_pcx_req_pq, spc2_pcx_atom_pq,
spc1_pcx_req_pq, spc1_pcx_atom_pq, spc0_pcx_req_pq,
spc0_pcx_atom_pq, si_1, si_0, se_buf5_top, se_buf5_bottom,
se_buf4_top, se_buf4_bottom, se_buf3_top, se_buf3_middle,
se_buf3_bottom, se_buf2_top, se_buf2_middle, se_buf2_bottom,
se_buf1_top, se_buf1_middle, se_buf1_bottom, se_buf0_middle,
sctag3_pcx_stall_pq, sctag2_pcx_stall_pq, sctag1_pcx_stall_pq,
sctag0_pcx_stall_pq, rst_l_buf2_middle, rst_l_buf1_middle, rclk,
pt1_so_1, io_pcx_stall_pq, cpx_buf_top_pt0_so_1, cmp_arst_l,
ccx_clk_hdr_so_1, adbginit_l_buf2_middle, adbginit_l_buf1_middle,
spc0_pcx_data_pa, spc1_pcx_data_pa, spc2_pcx_data_pa,
spc3_pcx_data_pa, spc4_pcx_data_pa, spc5_pcx_data_pa,
spc6_pcx_data_pa, spc7_pcx_data_pa
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output arst_l_buf_fpio_inff; // From pcx_buf_top of pcx_buf_top.v
output pcx_buf_top_pt0_so_0; // From pcx_buf_top of pcx_buf_top.v
output [`PCX_WIDTH-1:0]pcx_fpio_data_px2; // From pcx_buf_top of pcx_buf_top.v
output pcx_fpio_data_rdy_px2; // From pcx_buf_top of pcx_buf_top.v
output [`PCX_WIDTH-1:0]pcx_io_data_px2; // From pcx_buf_top of pcx_buf_top.v
output pcx_io_data_rdy_px2; // From pcx_buf_top of pcx_buf_top.v
output pcx_iodata_px2_so_1; // From pcx_buf_top of pcx_buf_top.v
output pcx_scache0_dat_px2_so_1;// From pcx_buf_top of pcx_buf_top.v
output pcx_scache1_dat_px2_so_1;// From pcx_buf_top of pcx_buf_top.v
output pcx_scache2_dat_px2_so_1;// From pcx_buf_top of pcx_buf_top.v
output pcx_sctag0_atm_px1; // From pcx_buf_top of pcx_buf_top.v
output [`PCX_WIDTH-1:0]pcx_sctag0_data_px2; // From pcx_buf_top of pcx_buf_top.v
output pcx_sctag0_data_rdy_px1;// From pcx_buf_top of pcx_buf_top.v
output pcx_sctag1_atm_px1; // From pcx_buf_top of pcx_buf_top.v
output [`PCX_WIDTH-1:0]pcx_sctag1_data_px2; // From pcx_buf_top of pcx_buf_top.v
output pcx_sctag1_data_rdy_px1;// From pcx_buf_top of pcx_buf_top.v
output pcx_sctag2_atm_px1; // From pcx_buf_top of pcx_buf_top.v
output [`PCX_WIDTH-1:0]pcx_sctag2_data_px2; // From pcx_buf_top of pcx_buf_top.v
output pcx_sctag2_data_rdy_px1;// From pcx_buf_top of pcx_buf_top.v
output pcx_sctag3_atm_px1; // From pcx_buf_top of pcx_buf_top.v
output [`PCX_WIDTH-1:0]pcx_sctag3_data_px2; // From pcx_buf_top of pcx_buf_top.v
output pcx_sctag3_data_rdy_px1;// From pcx_buf_top of pcx_buf_top.v
output [4:0] pcx_spc0_grant_px; // From pcx_buf_top of pcx_buf_top.v
output [4:0] pcx_spc1_grant_px; // From pcx_buf_top of pcx_buf_top.v
output [4:0] pcx_spc2_grant_px; // From pcx_buf_top of pcx_buf_top.v
output [4:0] pcx_spc3_grant_px; // From pcx_buf_top of pcx_buf_top.v
output [4:0] pcx_spc4_grant_px; // From pcx_buf_top of pcx_buf_top.v
output [4:0] pcx_spc5_grant_px; // From pcx_buf_top of pcx_buf_top.v
output [4:0] pcx_spc6_grant_px; // From pcx_buf_top of pcx_buf_top.v
output [4:0] pcx_spc7_grant_px; // From pcx_buf_top of pcx_buf_top.v
// End of automatics
input [`PCX_WIDTH-1:0] spc0_pcx_data_pa;
input [`PCX_WIDTH-1:0] spc1_pcx_data_pa;
input [`PCX_WIDTH-1:0] spc2_pcx_data_pa;
input [`PCX_WIDTH-1:0] spc3_pcx_data_pa;
input [`PCX_WIDTH-1:0] spc4_pcx_data_pa;
input [`PCX_WIDTH-1:0] spc5_pcx_data_pa;
input [`PCX_WIDTH-1:0] spc6_pcx_data_pa;
input [`PCX_WIDTH-1:0] spc7_pcx_data_pa;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l_buf1_middle; // To arb3 of ccx_arb.v, ...
input adbginit_l_buf2_middle; // To arb0 of ccx_arb.v, ...
input ccx_clk_hdr_so_1; // To pcx_buf_top of pcx_buf_top.v
input cmp_arst_l; // To pcx_buf_top of pcx_buf_top.v
input cpx_buf_top_pt0_so_1; // To pcx_buf_top of pcx_buf_top.v
input io_pcx_stall_pq; // To pcx_buf_top of pcx_buf_top.v
input pt1_so_1; // To pcx_buf_top of pcx_buf_top.v
input rclk; // To pcx_dp_array of pcx_dp_array.v, ...
input rst_l_buf1_middle; // To arb3 of ccx_arb.v, ...
input rst_l_buf2_middle; // To arb0 of ccx_arb.v, ...
input sctag0_pcx_stall_pq; // To pcx_buf_top of pcx_buf_top.v
input sctag1_pcx_stall_pq; // To pcx_buf_top of pcx_buf_top.v
input sctag2_pcx_stall_pq; // To arb2 of ccx_arb.v
input sctag3_pcx_stall_pq; // To pcx_buf_top of pcx_buf_top.v
input se_buf0_middle; // To pcx_buf_top of pcx_buf_top.v
input se_buf1_bottom; // To pcx_dp_array of pcx_dp_array.v, ...
input se_buf1_middle; // To arb3 of ccx_arb.v, ...
input se_buf1_top; // To pcx_dp_array of pcx_dp_array.v, ...
input se_buf2_bottom; // To pcx_buf_top of pcx_buf_top.v
input se_buf2_middle; // To arb0 of ccx_arb.v, ...
input se_buf2_top; // To pcx_buf_top of pcx_buf_top.v
input se_buf3_bottom; // To pcx_buf_top of pcx_buf_top.v
input se_buf3_middle; // To pcx_buf_top of pcx_buf_top.v
input se_buf3_top; // To pcx_buf_top of pcx_buf_top.v
input se_buf4_bottom; // To pcx_buf_top of pcx_buf_top.v
input se_buf4_top; // To pcx_buf_top of pcx_buf_top.v
input se_buf5_bottom; // To pcx_buf_top of pcx_buf_top.v
input se_buf5_top; // To pcx_buf_top of pcx_buf_top.v
input si_0; // To pcx_dp_array of pcx_dp_array.v
input si_1; // To pcx_dp_array of pcx_dp_array.v
input spc0_pcx_atom_pq; // To pcx_buf_top of pcx_buf_top.v
input [4:0] spc0_pcx_req_pq; // To pcx_buf_top of pcx_buf_top.v
input spc1_pcx_atom_pq; // To pcx_buf_top of pcx_buf_top.v
input [4:0] spc1_pcx_req_pq; // To pcx_buf_top of pcx_buf_top.v
input spc2_pcx_atom_pq; // To pcx_buf_top of pcx_buf_top.v
input [4:0] spc2_pcx_req_pq; // To pcx_buf_top of pcx_buf_top.v
input spc3_pcx_atom_pq; // To pcx_buf_top of pcx_buf_top.v
input [4:0] spc3_pcx_req_pq; // To pcx_buf_top of pcx_buf_top.v
input spc4_pcx_atom_pq; // To pcx_buf_top of pcx_buf_top.v
input [4:0] spc4_pcx_req_pq; // To pcx_buf_top of pcx_buf_top.v
input spc5_pcx_atom_pq; // To pcx_buf_top of pcx_buf_top.v
input [4:0] spc5_pcx_req_pq; // To pcx_buf_top of pcx_buf_top.v
input spc6_pcx_atom_pq; // To pcx_buf_top of pcx_buf_top.v
input [4:0] spc6_pcx_req_pq; // To pcx_buf_top of pcx_buf_top.v
input spc7_pcx_atom_pq; // To pcx_buf_top of pcx_buf_top.v
input [4:0] spc7_pcx_req_pq; // To pcx_buf_top of pcx_buf_top.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] arbpc0_pcxdp_grant_arbbf_pa;// From arb0 of ccx_arb.v
wire [7:0] arbpc0_pcxdp_grant_pa; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc0_pcxdp_q0_hold_arbbf_pa;// From arb0 of ccx_arb.v
wire [7:0] arbpc0_pcxdp_q0_hold_pa_l;// From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc0_pcxdp_qsel0_arbbf_pa;// From arb0 of ccx_arb.v
wire [7:0] arbpc0_pcxdp_qsel0_pa; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc0_pcxdp_qsel1_arbbf_pa;// From arb0 of ccx_arb.v
wire [7:0] arbpc0_pcxdp_qsel1_pa_l;// From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc0_pcxdp_shift_arbbf_px;// From arb0 of ccx_arb.v
wire [7:0] arbpc0_pcxdp_shift_px; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc1_pcxdp_grant_arbbf_pa;// From arb1 of ccx_arb.v
wire [7:0] arbpc1_pcxdp_grant_pa; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc1_pcxdp_q0_hold_arbbf_pa;// From arb1 of ccx_arb.v
wire [7:0] arbpc1_pcxdp_q0_hold_pa_l;// From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc1_pcxdp_qsel0_arbbf_pa;// From arb1 of ccx_arb.v
wire [7:0] arbpc1_pcxdp_qsel0_pa; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc1_pcxdp_qsel1_arbbf_pa;// From arb1 of ccx_arb.v
wire [7:0] arbpc1_pcxdp_qsel1_pa_l;// From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc1_pcxdp_shift_arbbf_px;// From arb1 of ccx_arb.v
wire [7:0] arbpc1_pcxdp_shift_px; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc2_pcxdp_grant_arbbf_pa;// From arb2 of ccx_arb.v
wire [7:0] arbpc2_pcxdp_grant_pa; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc2_pcxdp_q0_hold_arbbf_pa;// From arb2 of ccx_arb.v
wire [7:0] arbpc2_pcxdp_q0_hold_pa_l;// From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc2_pcxdp_qsel0_arbbf_pa;// From arb2 of ccx_arb.v
wire [7:0] arbpc2_pcxdp_qsel0_pa; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc2_pcxdp_qsel1_arbbf_pa;// From arb2 of ccx_arb.v
wire [7:0] arbpc2_pcxdp_qsel1_pa_l;// From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc2_pcxdp_shift_arbbf_px;// From arb2 of ccx_arb.v
wire [7:0] arbpc2_pcxdp_shift_px; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc3_pcxdp_grant_arbbf_pa;// From arb3 of ccx_arb.v
wire [7:0] arbpc3_pcxdp_grant_pa; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc3_pcxdp_q0_hold_arbbf_pa;// From arb3 of ccx_arb.v
wire [7:0] arbpc3_pcxdp_q0_hold_pa_l;// From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc3_pcxdp_qsel0_arbbf_pa;// From arb3 of ccx_arb.v
wire [7:0] arbpc3_pcxdp_qsel0_pa; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc3_pcxdp_qsel1_arbbf_pa;// From arb3 of ccx_arb.v
wire [7:0] arbpc3_pcxdp_qsel1_pa_l;// From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc3_pcxdp_shift_arbbf_px;// From arb3 of ccx_arb.v
wire [7:0] arbpc3_pcxdp_shift_px; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc4_pcxdp_grant_arbbf_pa;// From arb4 of ccx_arb.v
wire [7:0] arbpc4_pcxdp_grant_pa; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc4_pcxdp_q0_hold_arbbf_pa;// From arb4 of ccx_arb.v
wire [7:0] arbpc4_pcxdp_q0_hold_pa_l;// From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc4_pcxdp_qsel0_arbbf_pa;// From arb4 of ccx_arb.v
wire [7:0] arbpc4_pcxdp_qsel0_pa; // From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc4_pcxdp_qsel1_arbbf_pa;// From arb4 of ccx_arb.v
wire [7:0] arbpc4_pcxdp_qsel1_pa_l;// From pcx_buf_top of pcx_buf_top.v
wire [7:0] arbpc4_pcxdp_shift_arbbf_px;// From arb4 of ccx_arb.v
wire [7:0] arbpc4_pcxdp_shift_px; // From pcx_buf_top of pcx_buf_top.v
wire io_pcx_stall_bufp3_pq; // From pcx_buf_top of pcx_buf_top.v
wire pcx_arb0_so_0; // From arb0 of ccx_arb.v
wire pcx_arb1_so_0; // From arb1 of ccx_arb.v
wire pcx_arb2_so_0; // From arb2 of ccx_arb.v
wire pcx_arb3_so_0; // From arb3 of ccx_arb.v
wire pcx_arb4_so_0; // From arb4 of ccx_arb.v
wire pcx_dp_array02_so_1; // From pcx_dp_array of pcx_dp_array.v
wire pcx_dp_array134_so_0; // From pcx_dp_array of pcx_dp_array.v
wire [`PCX_WIDTH-1:0]pcx_fpio_data_px_l; // From pcx_dp_array of pcx_dp_array.v
wire pcx_fpio_data_rdy_arb_px;// From arb4 of ccx_arb.v
wire pcx_scache0_atom_px; // From arb0 of ccx_arb.v
wire [`PCX_WIDTH-1:0]pcx_scache0_data_px_l; // From pcx_dp_array of pcx_dp_array.v
wire pcx_scache0_data_rdy_arb_px;// From arb0 of ccx_arb.v
wire pcx_scache1_atom_px; // From arb1 of ccx_arb.v
wire [`PCX_WIDTH-1:0]pcx_scache1_data_px_l; // From pcx_dp_array of pcx_dp_array.v
wire pcx_scache1_data_rdy_arb_px;// From arb1 of ccx_arb.v
wire pcx_scache2_atom_px; // From arb2 of ccx_arb.v
wire [`PCX_WIDTH-1:0]pcx_scache2_data_px_l; // From pcx_dp_array of pcx_dp_array.v
wire pcx_scache2_data_rdy_arb_px;// From arb2 of ccx_arb.v
wire pcx_scache3_atom_px; // From arb3 of ccx_arb.v
wire [`PCX_WIDTH-1:0]pcx_scache3_data_px_l; // From pcx_dp_array of pcx_dp_array.v
wire pcx_scache3_data_rdy_arb_px;// From arb3 of ccx_arb.v
wire [4:0] pcx_spc0_grant_pa; // From arb0 of ccx_arb.v, ...
wire [4:0] pcx_spc1_grant_pa; // From arb0 of ccx_arb.v, ...
wire [4:0] pcx_spc2_grant_pa; // From arb0 of ccx_arb.v, ...
wire [4:0] pcx_spc3_grant_pa; // From arb0 of ccx_arb.v, ...
wire [4:0] pcx_spc4_grant_pa; // From arb0 of ccx_arb.v, ...
wire [4:0] pcx_spc5_grant_pa; // From arb0 of ccx_arb.v, ...
wire [4:0] pcx_spc6_grant_pa; // From arb0 of ccx_arb.v, ...
wire [4:0] pcx_spc7_grant_pa; // From arb0 of ccx_arb.v, ...
wire scache0_pcx_stall_bufp1_pq;// From pcx_buf_top of pcx_buf_top.v
wire scache3_pcx_stall_bufp3_pq;// From pcx_buf_top of pcx_buf_top.v
wire sctag1_pcx_stall_bufp1_pq;// From pcx_buf_top of pcx_buf_top.v
wire spc0_pcx_atom_bufp1_pq; // From pcx_buf_top of pcx_buf_top.v
wire [`PCX_WIDTH-1:0]spc0_pcx_data_buf_pa; // From pcx_buf_top of pcx_buf_top.v
wire [4:0] spc0_pcx_req_bufp1_pq; // From pcx_buf_top of pcx_buf_top.v
wire spc1_pcx_atom_bufp1_pq; // From pcx_buf_top of pcx_buf_top.v
wire [`PCX_WIDTH-1:0]spc1_pcx_data_buf_pa; // From pcx_buf_top of pcx_buf_top.v
wire [4:0] spc1_pcx_req_bufp1_pq; // From pcx_buf_top of pcx_buf_top.v
wire spc2_pcx_atom_bufp1_pq; // From pcx_buf_top of pcx_buf_top.v
wire [`PCX_WIDTH-1:0]spc2_pcx_data_buf_pa; // From pcx_buf_top of pcx_buf_top.v
wire [4:0] spc2_pcx_req_bufp1_pq; // From pcx_buf_top of pcx_buf_top.v
wire spc3_pcx_atom_bufp1_pq; // From pcx_buf_top of pcx_buf_top.v
wire [`PCX_WIDTH-1:0]spc3_pcx_data_buf_pa; // From pcx_buf_top of pcx_buf_top.v
wire [4:0] spc3_pcx_req_bufp1_pq; // From pcx_buf_top of pcx_buf_top.v
wire spc4_pcx_atom_bufp1_pq; // From pcx_buf_top of pcx_buf_top.v
wire [`PCX_WIDTH-1:0]spc4_pcx_data_buf_pa; // From pcx_buf_top of pcx_buf_top.v
wire [4:0] spc4_pcx_req_bufp1_pq; // From pcx_buf_top of pcx_buf_top.v
wire spc5_pcx_atom_bufp3_pq; // From pcx_buf_top of pcx_buf_top.v
wire [`PCX_WIDTH-1:0]spc5_pcx_data_buf_pa; // From pcx_buf_top of pcx_buf_top.v
wire [4:0] spc5_pcx_req_bufp3_pq; // From pcx_buf_top of pcx_buf_top.v
wire spc6_pcx_atom_bufp3_pq; // From pcx_buf_top of pcx_buf_top.v
wire [`PCX_WIDTH-1:0]spc6_pcx_data_buf_pa; // From pcx_buf_top of pcx_buf_top.v
wire [4:0] spc6_pcx_req_bufp3_pq; // From pcx_buf_top of pcx_buf_top.v
wire spc7_pcx_atom_bufp3_pq; // From pcx_buf_top of pcx_buf_top.v
wire [`PCX_WIDTH-1:0]spc7_pcx_data_buf_pa; // From pcx_buf_top of pcx_buf_top.v
wire [4:0] spc7_pcx_req_bufp3_pq; // From pcx_buf_top of pcx_buf_top.v
// End of automatics
/*
pcx_dp_array AUTO_TEMPLATE(
//.scan_out_0(pcx_dp_array134_so_0),
//.si_0(si_0),
.arbpc0_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa_l[7:0]),
.arbpc1_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa_l[7:0]),
.arbpc2_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa_l[7:0]),
.arbpc3_pcxdp_q0_hold_pa(arbpc3_pcxdp_q0_hold_pa_l[7:0]),
.arbpc4_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa_l[7:0]),
.arbpc0_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa_l[7:0]),
.arbpc1_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa_l[7:0]),
.arbpc2_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa_l[7:0]),
.arbpc3_pcxdp_qsel1_pa(arbpc3_pcxdp_qsel1_pa_l[7:0]),
.arbpc4_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa_l[7:0]),
.spc0_pcx_data_pa(spc0_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc1_pcx_data_pa(spc1_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc2_pcx_data_pa(spc2_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc3_pcx_data_pa(spc3_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc4_pcx_data_pa(spc4_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc5_pcx_data_pa(spc5_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc6_pcx_data_pa(spc6_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc7_pcx_data_pa(spc7_pcx_data_buf_pa[`PCX_WIDTH-1:0]));
*/
pcx_dp_array pcx_dp_array(/*AUTOINST*/
// Outputs
.pcx_dp_array02_so_1(pcx_dp_array02_so_1),
.pcx_dp_array134_so_0(pcx_dp_array134_so_0),
.pcx_fpio_data_px_l(pcx_fpio_data_px_l[`PCX_WIDTH-1:0]),
.pcx_scache0_data_px_l(pcx_scache0_data_px_l[`PCX_WIDTH-1:0]),
.pcx_scache1_data_px_l(pcx_scache1_data_px_l[`PCX_WIDTH-1:0]),
.pcx_scache2_data_px_l(pcx_scache2_data_px_l[`PCX_WIDTH-1:0]),
.pcx_scache3_data_px_l(pcx_scache3_data_px_l[`PCX_WIDTH-1:0]),
// Inputs
.arbpc0_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[7:0]),
.arbpc0_pcxdp_q0_hold_pa(arbpc0_pcxdp_q0_hold_pa_l[7:0]), // Templated
.arbpc0_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[7:0]),
.arbpc0_pcxdp_qsel1_pa(arbpc0_pcxdp_qsel1_pa_l[7:0]), // Templated
.arbpc0_pcxdp_shift_px(arbpc0_pcxdp_shift_px[7:0]),
.arbpc1_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[7:0]),
.arbpc1_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa_l[7:0]), // Templated
.arbpc1_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[7:0]),
.arbpc1_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa_l[7:0]), // Templated
.arbpc1_pcxdp_shift_px(arbpc1_pcxdp_shift_px[7:0]),
.arbpc2_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[7:0]),
.arbpc2_pcxdp_q0_hold_pa(arbpc2_pcxdp_q0_hold_pa_l[7:0]), // Templated
.arbpc2_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[7:0]),
.arbpc2_pcxdp_qsel1_pa(arbpc2_pcxdp_qsel1_pa_l[7:0]), // Templated
.arbpc2_pcxdp_shift_px(arbpc2_pcxdp_shift_px[7:0]),
.arbpc3_pcxdp_grant_pa(arbpc3_pcxdp_grant_pa[7:0]),
.arbpc3_pcxdp_q0_hold_pa(arbpc3_pcxdp_q0_hold_pa_l[7:0]), // Templated
.arbpc3_pcxdp_qsel0_pa(arbpc3_pcxdp_qsel0_pa[7:0]),
.arbpc3_pcxdp_qsel1_pa(arbpc3_pcxdp_qsel1_pa_l[7:0]), // Templated
.arbpc3_pcxdp_shift_px(arbpc3_pcxdp_shift_px[7:0]),
.arbpc4_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[7:0]),
.arbpc4_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa_l[7:0]), // Templated
.arbpc4_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[7:0]),
.arbpc4_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa_l[7:0]), // Templated
.arbpc4_pcxdp_shift_px(arbpc4_pcxdp_shift_px[7:0]),
.rclk (rclk),
.se_buf1_bottom(se_buf1_bottom),
.se_buf1_top(se_buf1_top),
.si_0 (si_0),
.si_1 (si_1),
.spc0_pcx_data_pa(spc0_pcx_data_buf_pa[`PCX_WIDTH-1:0]), // Templated
.spc1_pcx_data_pa(spc1_pcx_data_buf_pa[`PCX_WIDTH-1:0]), // Templated
.spc2_pcx_data_pa(spc2_pcx_data_buf_pa[`PCX_WIDTH-1:0]), // Templated
.spc3_pcx_data_pa(spc3_pcx_data_buf_pa[`PCX_WIDTH-1:0]), // Templated
.spc4_pcx_data_pa(spc4_pcx_data_buf_pa[`PCX_WIDTH-1:0]), // Templated
.spc5_pcx_data_pa(spc5_pcx_data_buf_pa[`PCX_WIDTH-1:0]), // Templated
.spc6_pcx_data_pa(spc6_pcx_data_buf_pa[`PCX_WIDTH-1:0]), // Templated
.spc7_pcx_data_pa(spc7_pcx_data_buf_pa[`PCX_WIDTH-1:0])); // Templated
/*
ccx_arb AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbpc@_pcxdp_grant_arbbf_pa[7:0]),
.arb_dp_q0_hold_a (arbpc@_pcxdp_q0_hold_arbbf_pa[7:0]),
.arb_dp_qsel0_a (arbpc@_pcxdp_qsel0_arbbf_pa[7:0]),
.arb_dp_qsel1_a (arbpc@_pcxdp_qsel1_arbbf_pa[7:0]),
.arb_dp_shift_x (arbpc@_pcxdp_shift_arbbf_px[7:0]),
.arb_src0_grant_a (pcx_spc0_grant_pa[@]),
.arb_src1_grant_a (pcx_spc1_grant_pa[@]),
.arb_src2_grant_a (pcx_spc2_grant_pa[@]),
.arb_src3_grant_a (pcx_spc3_grant_pa[@]),
.arb_src4_grant_a (pcx_spc4_grant_pa[@]),
.arb_src5_grant_a (pcx_spc5_grant_pa[@]),
.arb_src6_grant_a (pcx_spc6_grant_pa[@]),
.arb_src7_grant_a (pcx_spc7_grant_pa[@]),
.ccx_dest_data_rdy_x (pcx_scache@_data_rdy_arb_px),
.ccx_dest_atom_x (pcx_scache@_atom_px),
.scan_out (pcx_arb0_so_0),
// Inputs
.src0_arb_atom_q (spc0_pcx_atom_bufp1_pq),
.src0_arb_req_q (spc0_pcx_req_bufp1_pq[@]),
.src1_arb_atom_q (spc1_pcx_atom_bufp1_pq),
.src1_arb_req_q (spc1_pcx_req_bufp1_pq[@]),
.src2_arb_atom_q (spc2_pcx_atom_bufp1_pq),
.src2_arb_req_q (spc2_pcx_req_bufp1_pq[@]),
.src3_arb_atom_q (spc3_pcx_atom_bufp1_pq),
.src3_arb_req_q (spc3_pcx_req_bufp1_pq[@]),
.src4_arb_atom_q (spc4_pcx_atom_bufp1_pq),
.src4_arb_req_q (spc4_pcx_req_bufp1_pq[@]),
.src5_arb_atom_q (spc5_pcx_atom_bufp3_pq),
.src5_arb_req_q (spc5_pcx_req_bufp3_pq[@]),
.src6_arb_atom_q (spc6_pcx_atom_bufp3_pq),
.src6_arb_req_q (spc6_pcx_req_bufp3_pq[@]),
.src7_arb_atom_q (spc7_pcx_atom_bufp3_pq),
.src7_arb_req_q (spc7_pcx_req_bufp3_pq[@]),
.stall1_q (scache@_pcx_stall_bufp1_pq),
.stall2_q (1'b0),
.adbginit_l (adbginit_l_buf2_middle),
.reset_l (rst_l_buf2_middle),
//.tmb_l (tmb_l),
.scan_in (pcx_dp_array134_so_0),
.se (se_buf2_middle));
*/
//
ccx_arb arb0(/*AUTOINST*/
// Outputs
.arb_dp_grant_a (arbpc0_pcxdp_grant_arbbf_pa[7:0]), // Templated
.arb_dp_q0_hold_a (arbpc0_pcxdp_q0_hold_arbbf_pa[7:0]), // Templated
.arb_dp_qsel0_a (arbpc0_pcxdp_qsel0_arbbf_pa[7:0]), // Templated
.arb_dp_qsel1_a (arbpc0_pcxdp_qsel1_arbbf_pa[7:0]), // Templated
.arb_dp_shift_x (arbpc0_pcxdp_shift_arbbf_px[7:0]), // Templated
.arb_src0_grant_a (pcx_spc0_grant_pa[0]), // Templated
.arb_src1_grant_a (pcx_spc1_grant_pa[0]), // Templated
.arb_src2_grant_a (pcx_spc2_grant_pa[0]), // Templated
.arb_src3_grant_a (pcx_spc3_grant_pa[0]), // Templated
.arb_src4_grant_a (pcx_spc4_grant_pa[0]), // Templated
.arb_src5_grant_a (pcx_spc5_grant_pa[0]), // Templated
.arb_src6_grant_a (pcx_spc6_grant_pa[0]), // Templated
.arb_src7_grant_a (pcx_spc7_grant_pa[0]), // Templated
.ccx_dest_atom_x (pcx_scache0_atom_px), // Templated
.ccx_dest_data_rdy_x (pcx_scache0_data_rdy_arb_px), // Templated
.scan_out (pcx_arb0_so_0), // Templated
// Inputs
.adbginit_l (adbginit_l_buf2_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf2_middle), // Templated
.src0_arb_atom_q (spc0_pcx_atom_bufp1_pq), // Templated
.src0_arb_req_q (spc0_pcx_req_bufp1_pq[0]), // Templated
.src1_arb_atom_q (spc1_pcx_atom_bufp1_pq), // Templated
.src1_arb_req_q (spc1_pcx_req_bufp1_pq[0]), // Templated
.src2_arb_atom_q (spc2_pcx_atom_bufp1_pq), // Templated
.src2_arb_req_q (spc2_pcx_req_bufp1_pq[0]), // Templated
.src3_arb_atom_q (spc3_pcx_atom_bufp1_pq), // Templated
.src3_arb_req_q (spc3_pcx_req_bufp1_pq[0]), // Templated
.src4_arb_atom_q (spc4_pcx_atom_bufp1_pq), // Templated
.src4_arb_req_q (spc4_pcx_req_bufp1_pq[0]), // Templated
.src5_arb_atom_q (spc5_pcx_atom_bufp3_pq), // Templated
.src5_arb_req_q (spc5_pcx_req_bufp3_pq[0]), // Templated
.src6_arb_atom_q (spc6_pcx_atom_bufp3_pq), // Templated
.src6_arb_req_q (spc6_pcx_req_bufp3_pq[0]), // Templated
.src7_arb_atom_q (spc7_pcx_atom_bufp3_pq), // Templated
.src7_arb_req_q (spc7_pcx_req_bufp3_pq[0]), // Templated
.stall1_q (scache0_pcx_stall_bufp1_pq), // Templated
.stall2_q (1'b0), // Templated
.scan_in (pcx_dp_array134_so_0), // Templated
.se (se_buf2_middle)); // Templated
/*
ccx_arb AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbpc@_pcxdp_grant_arbbf_pa[7:0]),
.arb_dp_q0_hold_a (arbpc@_pcxdp_q0_hold_arbbf_pa[7:0]),
.arb_dp_qsel0_a (arbpc@_pcxdp_qsel0_arbbf_pa[7:0]),
.arb_dp_qsel1_a (arbpc@_pcxdp_qsel1_arbbf_pa[7:0]),
.arb_dp_shift_x (arbpc@_pcxdp_shift_arbbf_px[7:0]),
.arb_src0_grant_a (pcx_spc0_grant_pa[@]),
.arb_src1_grant_a (pcx_spc1_grant_pa[@]),
.arb_src2_grant_a (pcx_spc2_grant_pa[@]),
.arb_src3_grant_a (pcx_spc3_grant_pa[@]),
.arb_src4_grant_a (pcx_spc4_grant_pa[@]),
.arb_src5_grant_a (pcx_spc5_grant_pa[@]),
.arb_src6_grant_a (pcx_spc6_grant_pa[@]),
.arb_src7_grant_a (pcx_spc7_grant_pa[@]),
.ccx_dest_data_rdy_x (pcx_scache@_data_rdy_arb_px),
.ccx_dest_atom_x (pcx_scache@_atom_px),
.scan_out (pcx_arb1_so_0),
// Inputs
.src0_arb_atom_q (spc0_pcx_atom_bufp1_pq),
.src0_arb_req_q (spc0_pcx_req_bufp1_pq[@]),
.src1_arb_atom_q (spc1_pcx_atom_bufp1_pq),
.src1_arb_req_q (spc1_pcx_req_bufp1_pq[@]),
.src2_arb_atom_q (spc2_pcx_atom_bufp1_pq),
.src2_arb_req_q (spc2_pcx_req_bufp1_pq[@]),
.src3_arb_atom_q (spc3_pcx_atom_bufp1_pq),
.src3_arb_req_q (spc3_pcx_req_bufp1_pq[@]),
.src4_arb_atom_q (spc4_pcx_atom_bufp1_pq),
.src4_arb_req_q (spc4_pcx_req_bufp1_pq[@]),
.src5_arb_atom_q (spc5_pcx_atom_bufp3_pq),
.src5_arb_req_q (spc5_pcx_req_bufp3_pq[@]),
.src6_arb_atom_q (spc6_pcx_atom_bufp3_pq),
.src6_arb_req_q (spc6_pcx_req_bufp3_pq[@]),
.src7_arb_atom_q (spc7_pcx_atom_bufp3_pq),
.src7_arb_req_q (spc7_pcx_req_bufp3_pq[@]),
.stall1_q (sctag@_pcx_stall_bufp1_pq),
.stall2_q (1'b0),
.adbginit_l (adbginit_l_buf2_middle),
.reset_l (rst_l_buf2_middle),
//.tmb_l (tmb_l),
.scan_in (pcx_arb0_so_0),
.se (se_buf2_middle));
*/
ccx_arb arb1(/*AUTOINST*/
// Outputs
.arb_dp_grant_a (arbpc1_pcxdp_grant_arbbf_pa[7:0]), // Templated
.arb_dp_q0_hold_a (arbpc1_pcxdp_q0_hold_arbbf_pa[7:0]), // Templated
.arb_dp_qsel0_a (arbpc1_pcxdp_qsel0_arbbf_pa[7:0]), // Templated
.arb_dp_qsel1_a (arbpc1_pcxdp_qsel1_arbbf_pa[7:0]), // Templated
.arb_dp_shift_x (arbpc1_pcxdp_shift_arbbf_px[7:0]), // Templated
.arb_src0_grant_a (pcx_spc0_grant_pa[1]), // Templated
.arb_src1_grant_a (pcx_spc1_grant_pa[1]), // Templated
.arb_src2_grant_a (pcx_spc2_grant_pa[1]), // Templated
.arb_src3_grant_a (pcx_spc3_grant_pa[1]), // Templated
.arb_src4_grant_a (pcx_spc4_grant_pa[1]), // Templated
.arb_src5_grant_a (pcx_spc5_grant_pa[1]), // Templated
.arb_src6_grant_a (pcx_spc6_grant_pa[1]), // Templated
.arb_src7_grant_a (pcx_spc7_grant_pa[1]), // Templated
.ccx_dest_atom_x (pcx_scache1_atom_px), // Templated
.ccx_dest_data_rdy_x (pcx_scache1_data_rdy_arb_px), // Templated
.scan_out (pcx_arb1_so_0), // Templated
// Inputs
.adbginit_l (adbginit_l_buf2_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf2_middle), // Templated
.src0_arb_atom_q (spc0_pcx_atom_bufp1_pq), // Templated
.src0_arb_req_q (spc0_pcx_req_bufp1_pq[1]), // Templated
.src1_arb_atom_q (spc1_pcx_atom_bufp1_pq), // Templated
.src1_arb_req_q (spc1_pcx_req_bufp1_pq[1]), // Templated
.src2_arb_atom_q (spc2_pcx_atom_bufp1_pq), // Templated
.src2_arb_req_q (spc2_pcx_req_bufp1_pq[1]), // Templated
.src3_arb_atom_q (spc3_pcx_atom_bufp1_pq), // Templated
.src3_arb_req_q (spc3_pcx_req_bufp1_pq[1]), // Templated
.src4_arb_atom_q (spc4_pcx_atom_bufp1_pq), // Templated
.src4_arb_req_q (spc4_pcx_req_bufp1_pq[1]), // Templated
.src5_arb_atom_q (spc5_pcx_atom_bufp3_pq), // Templated
.src5_arb_req_q (spc5_pcx_req_bufp3_pq[1]), // Templated
.src6_arb_atom_q (spc6_pcx_atom_bufp3_pq), // Templated
.src6_arb_req_q (spc6_pcx_req_bufp3_pq[1]), // Templated
.src7_arb_atom_q (spc7_pcx_atom_bufp3_pq), // Templated
.src7_arb_req_q (spc7_pcx_req_bufp3_pq[1]), // Templated
.stall1_q (sctag1_pcx_stall_bufp1_pq), // Templated
.stall2_q (1'b0), // Templated
.scan_in (pcx_arb0_so_0), // Templated
.se (se_buf2_middle)); // Templated
/*
ccx_arb AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbpc@_pcxdp_grant_arbbf_pa[7:0]),
.arb_dp_q0_hold_a (arbpc@_pcxdp_q0_hold_arbbf_pa[7:0]),
.arb_dp_qsel0_a (arbpc@_pcxdp_qsel0_arbbf_pa[7:0]),
.arb_dp_qsel1_a (arbpc@_pcxdp_qsel1_arbbf_pa[7:0]),
.arb_dp_shift_x (arbpc@_pcxdp_shift_arbbf_px[7:0]),
.arb_src0_grant_a (pcx_spc0_grant_pa[@]),
.arb_src1_grant_a (pcx_spc1_grant_pa[@]),
.arb_src2_grant_a (pcx_spc2_grant_pa[@]),
.arb_src3_grant_a (pcx_spc3_grant_pa[@]),
.arb_src4_grant_a (pcx_spc4_grant_pa[@]),
.arb_src5_grant_a (pcx_spc5_grant_pa[@]),
.arb_src6_grant_a (pcx_spc6_grant_pa[@]),
.arb_src7_grant_a (pcx_spc7_grant_pa[@]),
.ccx_dest_data_rdy_x (pcx_scache@_data_rdy_arb_px),
.ccx_dest_atom_x (pcx_scache@_atom_px),
.scan_out (pcx_arb2_so_0),
// Inputs
.src0_arb_atom_q (spc0_pcx_atom_bufp1_pq),
.src0_arb_req_q (spc0_pcx_req_bufp1_pq[@]),
.src1_arb_atom_q (spc1_pcx_atom_bufp1_pq),
.src1_arb_req_q (spc1_pcx_req_bufp1_pq[@]),
.src2_arb_atom_q (spc2_pcx_atom_bufp1_pq),
.src2_arb_req_q (spc2_pcx_req_bufp1_pq[@]),
.src3_arb_atom_q (spc3_pcx_atom_bufp1_pq),
.src3_arb_req_q (spc3_pcx_req_bufp1_pq[@]),
.src4_arb_atom_q (spc4_pcx_atom_bufp1_pq),
.src4_arb_req_q (spc4_pcx_req_bufp1_pq[@]),
.src5_arb_atom_q (spc5_pcx_atom_bufp3_pq),
.src5_arb_req_q (spc5_pcx_req_bufp3_pq[@]),
.src6_arb_atom_q (spc6_pcx_atom_bufp3_pq),
.src6_arb_req_q (spc6_pcx_req_bufp3_pq[@]),
.src7_arb_atom_q (spc7_pcx_atom_bufp3_pq),
.src7_arb_req_q (spc7_pcx_req_bufp3_pq[@]),
.stall1_q (sctag@_pcx_stall_pq),
.stall2_q (1'b0),
.adbginit_l (adbginit_l_buf2_middle),
.reset_l (rst_l_buf2_middle),
//.tmb_l (tmb_l),
.scan_in (pcx_arb1_so_0),
.se (se_buf2_middle));
*/
ccx_arb arb2(/*AUTOINST*/
// Outputs
.arb_dp_grant_a (arbpc2_pcxdp_grant_arbbf_pa[7:0]), // Templated
.arb_dp_q0_hold_a (arbpc2_pcxdp_q0_hold_arbbf_pa[7:0]), // Templated
.arb_dp_qsel0_a (arbpc2_pcxdp_qsel0_arbbf_pa[7:0]), // Templated
.arb_dp_qsel1_a (arbpc2_pcxdp_qsel1_arbbf_pa[7:0]), // Templated
.arb_dp_shift_x (arbpc2_pcxdp_shift_arbbf_px[7:0]), // Templated
.arb_src0_grant_a (pcx_spc0_grant_pa[2]), // Templated
.arb_src1_grant_a (pcx_spc1_grant_pa[2]), // Templated
.arb_src2_grant_a (pcx_spc2_grant_pa[2]), // Templated
.arb_src3_grant_a (pcx_spc3_grant_pa[2]), // Templated
.arb_src4_grant_a (pcx_spc4_grant_pa[2]), // Templated
.arb_src5_grant_a (pcx_spc5_grant_pa[2]), // Templated
.arb_src6_grant_a (pcx_spc6_grant_pa[2]), // Templated
.arb_src7_grant_a (pcx_spc7_grant_pa[2]), // Templated
.ccx_dest_atom_x (pcx_scache2_atom_px), // Templated
.ccx_dest_data_rdy_x (pcx_scache2_data_rdy_arb_px), // Templated
.scan_out (pcx_arb2_so_0), // Templated
// Inputs
.adbginit_l (adbginit_l_buf2_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf2_middle), // Templated
.src0_arb_atom_q (spc0_pcx_atom_bufp1_pq), // Templated
.src0_arb_req_q (spc0_pcx_req_bufp1_pq[2]), // Templated
.src1_arb_atom_q (spc1_pcx_atom_bufp1_pq), // Templated
.src1_arb_req_q (spc1_pcx_req_bufp1_pq[2]), // Templated
.src2_arb_atom_q (spc2_pcx_atom_bufp1_pq), // Templated
.src2_arb_req_q (spc2_pcx_req_bufp1_pq[2]), // Templated
.src3_arb_atom_q (spc3_pcx_atom_bufp1_pq), // Templated
.src3_arb_req_q (spc3_pcx_req_bufp1_pq[2]), // Templated
.src4_arb_atom_q (spc4_pcx_atom_bufp1_pq), // Templated
.src4_arb_req_q (spc4_pcx_req_bufp1_pq[2]), // Templated
.src5_arb_atom_q (spc5_pcx_atom_bufp3_pq), // Templated
.src5_arb_req_q (spc5_pcx_req_bufp3_pq[2]), // Templated
.src6_arb_atom_q (spc6_pcx_atom_bufp3_pq), // Templated
.src6_arb_req_q (spc6_pcx_req_bufp3_pq[2]), // Templated
.src7_arb_atom_q (spc7_pcx_atom_bufp3_pq), // Templated
.src7_arb_req_q (spc7_pcx_req_bufp3_pq[2]), // Templated
.stall1_q (sctag2_pcx_stall_pq), // Templated
.stall2_q (1'b0), // Templated
.scan_in (pcx_arb1_so_0), // Templated
.se (se_buf2_middle)); // Templated
/*
ccx_arb AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbpc@_pcxdp_grant_arbbf_pa[7:0]),
.arb_dp_q0_hold_a (arbpc@_pcxdp_q0_hold_arbbf_pa[7:0]),
.arb_dp_qsel0_a (arbpc@_pcxdp_qsel0_arbbf_pa[7:0]),
.arb_dp_qsel1_a (arbpc@_pcxdp_qsel1_arbbf_pa[7:0]),
.arb_dp_shift_x (arbpc@_pcxdp_shift_arbbf_px[7:0]),
.arb_src0_grant_a (pcx_spc0_grant_pa[@]),
.arb_src1_grant_a (pcx_spc1_grant_pa[@]),
.arb_src2_grant_a (pcx_spc2_grant_pa[@]),
.arb_src3_grant_a (pcx_spc3_grant_pa[@]),
.arb_src4_grant_a (pcx_spc4_grant_pa[@]),
.arb_src5_grant_a (pcx_spc5_grant_pa[@]),
.arb_src6_grant_a (pcx_spc6_grant_pa[@]),
.arb_src7_grant_a (pcx_spc7_grant_pa[@]),
.ccx_dest_data_rdy_x (pcx_scache@_data_rdy_arb_px),
.ccx_dest_atom_x (pcx_scache@_atom_px),
.scan_out (pcx_arb3_so_0),
// Inputs
.src0_arb_atom_q (spc0_pcx_atom_bufp1_pq),
.src0_arb_req_q (spc0_pcx_req_bufp1_pq[@]),
.src1_arb_atom_q (spc1_pcx_atom_bufp1_pq),
.src1_arb_req_q (spc1_pcx_req_bufp1_pq[@]),
.src2_arb_atom_q (spc2_pcx_atom_bufp1_pq),
.src2_arb_req_q (spc2_pcx_req_bufp1_pq[@]),
.src3_arb_atom_q (spc3_pcx_atom_bufp1_pq),
.src3_arb_req_q (spc3_pcx_req_bufp1_pq[@]),
.src4_arb_atom_q (spc4_pcx_atom_bufp1_pq),
.src4_arb_req_q (spc4_pcx_req_bufp1_pq[@]),
.src5_arb_atom_q (spc5_pcx_atom_bufp3_pq),
.src5_arb_req_q (spc5_pcx_req_bufp3_pq[@]),
.src6_arb_atom_q (spc6_pcx_atom_bufp3_pq),
.src6_arb_req_q (spc6_pcx_req_bufp3_pq[@]),
.src7_arb_atom_q (spc7_pcx_atom_bufp3_pq),
.src7_arb_req_q (spc7_pcx_req_bufp3_pq[@]),
.stall1_q (scache@_pcx_stall_bufp3_pq),
.stall2_q (1'b0),
.adbginit_l (adbginit_l_buf1_middle),
.reset_l (rst_l_buf1_middle),
//.tmb_l (tmb_l),
.scan_in (pcx_arb2_so_0),
.se (se_buf1_middle));
*/
ccx_arb arb3(/*AUTOINST*/
// Outputs
.arb_dp_grant_a (arbpc3_pcxdp_grant_arbbf_pa[7:0]), // Templated
.arb_dp_q0_hold_a (arbpc3_pcxdp_q0_hold_arbbf_pa[7:0]), // Templated
.arb_dp_qsel0_a (arbpc3_pcxdp_qsel0_arbbf_pa[7:0]), // Templated
.arb_dp_qsel1_a (arbpc3_pcxdp_qsel1_arbbf_pa[7:0]), // Templated
.arb_dp_shift_x (arbpc3_pcxdp_shift_arbbf_px[7:0]), // Templated
.arb_src0_grant_a (pcx_spc0_grant_pa[3]), // Templated
.arb_src1_grant_a (pcx_spc1_grant_pa[3]), // Templated
.arb_src2_grant_a (pcx_spc2_grant_pa[3]), // Templated
.arb_src3_grant_a (pcx_spc3_grant_pa[3]), // Templated
.arb_src4_grant_a (pcx_spc4_grant_pa[3]), // Templated
.arb_src5_grant_a (pcx_spc5_grant_pa[3]), // Templated
.arb_src6_grant_a (pcx_spc6_grant_pa[3]), // Templated
.arb_src7_grant_a (pcx_spc7_grant_pa[3]), // Templated
.ccx_dest_atom_x (pcx_scache3_atom_px), // Templated
.ccx_dest_data_rdy_x (pcx_scache3_data_rdy_arb_px), // Templated
.scan_out (pcx_arb3_so_0), // Templated
// Inputs
.adbginit_l (adbginit_l_buf1_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf1_middle), // Templated
.src0_arb_atom_q (spc0_pcx_atom_bufp1_pq), // Templated
.src0_arb_req_q (spc0_pcx_req_bufp1_pq[3]), // Templated
.src1_arb_atom_q (spc1_pcx_atom_bufp1_pq), // Templated
.src1_arb_req_q (spc1_pcx_req_bufp1_pq[3]), // Templated
.src2_arb_atom_q (spc2_pcx_atom_bufp1_pq), // Templated
.src2_arb_req_q (spc2_pcx_req_bufp1_pq[3]), // Templated
.src3_arb_atom_q (spc3_pcx_atom_bufp1_pq), // Templated
.src3_arb_req_q (spc3_pcx_req_bufp1_pq[3]), // Templated
.src4_arb_atom_q (spc4_pcx_atom_bufp1_pq), // Templated
.src4_arb_req_q (spc4_pcx_req_bufp1_pq[3]), // Templated
.src5_arb_atom_q (spc5_pcx_atom_bufp3_pq), // Templated
.src5_arb_req_q (spc5_pcx_req_bufp3_pq[3]), // Templated
.src6_arb_atom_q (spc6_pcx_atom_bufp3_pq), // Templated
.src6_arb_req_q (spc6_pcx_req_bufp3_pq[3]), // Templated
.src7_arb_atom_q (spc7_pcx_atom_bufp3_pq), // Templated
.src7_arb_req_q (spc7_pcx_req_bufp3_pq[3]), // Templated
.stall1_q (scache3_pcx_stall_bufp3_pq), // Templated
.stall2_q (1'b0), // Templated
.scan_in (pcx_arb2_so_0), // Templated
.se (se_buf1_middle)); // Templated
/*
ccx_arb AUTO_TEMPLATE(
// Outputs
.arb_dp_grant_a (arbpc@_pcxdp_grant_arbbf_pa[7:0]),
.arb_dp_q0_hold_a (arbpc@_pcxdp_q0_hold_arbbf_pa[7:0]),
.arb_dp_qsel0_a (arbpc@_pcxdp_qsel0_arbbf_pa[7:0]),
.arb_dp_qsel1_a (arbpc@_pcxdp_qsel1_arbbf_pa[7:0]),
.arb_dp_shift_x (arbpc@_pcxdp_shift_arbbf_px[7:0]),
.arb_src0_grant_a (pcx_spc0_grant_pa[@]),
.arb_src1_grant_a (pcx_spc1_grant_pa[@]),
.arb_src2_grant_a (pcx_spc2_grant_pa[@]),
.arb_src3_grant_a (pcx_spc3_grant_pa[@]),
.arb_src4_grant_a (pcx_spc4_grant_pa[@]),
.arb_src5_grant_a (pcx_spc5_grant_pa[@]),
.arb_src6_grant_a (pcx_spc6_grant_pa[@]),
.arb_src7_grant_a (pcx_spc7_grant_pa[@]),
.ccx_dest_data_rdy_x (pcx_fpio_data_rdy_arb_px),
.ccx_dest_atom_x (),
.scan_out (pcx_arb4_so_0),
// Inputs
.src0_arb_atom_q (spc0_pcx_atom_bufp1_pq),
.src0_arb_req_q (spc0_pcx_req_bufp1_pq[@]),
.src1_arb_atom_q (spc1_pcx_atom_bufp1_pq),
.src1_arb_req_q (spc1_pcx_req_bufp1_pq[@]),
.src2_arb_atom_q (spc2_pcx_atom_bufp1_pq),
.src2_arb_req_q (spc2_pcx_req_bufp1_pq[@]),
.src3_arb_atom_q (spc3_pcx_atom_bufp1_pq),
.src3_arb_req_q (spc3_pcx_req_bufp1_pq[@]),
.src4_arb_atom_q (spc4_pcx_atom_bufp1_pq),
.src4_arb_req_q (spc4_pcx_req_bufp1_pq[@]),
.src5_arb_atom_q (spc5_pcx_atom_bufp3_pq),
.src5_arb_req_q (spc5_pcx_req_bufp3_pq[@]),
.src6_arb_atom_q (spc6_pcx_atom_bufp3_pq),
.src6_arb_req_q (spc6_pcx_req_bufp3_pq[@]),
.src7_arb_atom_q (spc7_pcx_atom_bufp3_pq),
.src7_arb_req_q (spc7_pcx_req_bufp3_pq[@]),
.stall1_q (1'b0),
.stall2_q (io_pcx_stall_bufp3_pq),
.adbginit_l (adbginit_l_buf1_middle),
.reset_l (rst_l_buf1_middle),
//.tmb_l (tmb_l),
.scan_in (pcx_arb3_so_0),
.se (se_buf1_middle));
*/
//
ccx_arb arb4(/*AUTOINST*/
// Outputs
.arb_dp_grant_a (arbpc4_pcxdp_grant_arbbf_pa[7:0]), // Templated
.arb_dp_q0_hold_a (arbpc4_pcxdp_q0_hold_arbbf_pa[7:0]), // Templated
.arb_dp_qsel0_a (arbpc4_pcxdp_qsel0_arbbf_pa[7:0]), // Templated
.arb_dp_qsel1_a (arbpc4_pcxdp_qsel1_arbbf_pa[7:0]), // Templated
.arb_dp_shift_x (arbpc4_pcxdp_shift_arbbf_px[7:0]), // Templated
.arb_src0_grant_a (pcx_spc0_grant_pa[4]), // Templated
.arb_src1_grant_a (pcx_spc1_grant_pa[4]), // Templated
.arb_src2_grant_a (pcx_spc2_grant_pa[4]), // Templated
.arb_src3_grant_a (pcx_spc3_grant_pa[4]), // Templated
.arb_src4_grant_a (pcx_spc4_grant_pa[4]), // Templated
.arb_src5_grant_a (pcx_spc5_grant_pa[4]), // Templated
.arb_src6_grant_a (pcx_spc6_grant_pa[4]), // Templated
.arb_src7_grant_a (pcx_spc7_grant_pa[4]), // Templated
.ccx_dest_atom_x (), // Templated
.ccx_dest_data_rdy_x (pcx_fpio_data_rdy_arb_px), // Templated
.scan_out (pcx_arb4_so_0), // Templated
// Inputs
.adbginit_l (adbginit_l_buf1_middle), // Templated
.rclk (rclk),
.reset_l (rst_l_buf1_middle), // Templated
.src0_arb_atom_q (spc0_pcx_atom_bufp1_pq), // Templated
.src0_arb_req_q (spc0_pcx_req_bufp1_pq[4]), // Templated
.src1_arb_atom_q (spc1_pcx_atom_bufp1_pq), // Templated
.src1_arb_req_q (spc1_pcx_req_bufp1_pq[4]), // Templated
.src2_arb_atom_q (spc2_pcx_atom_bufp1_pq), // Templated
.src2_arb_req_q (spc2_pcx_req_bufp1_pq[4]), // Templated
.src3_arb_atom_q (spc3_pcx_atom_bufp1_pq), // Templated
.src3_arb_req_q (spc3_pcx_req_bufp1_pq[4]), // Templated
.src4_arb_atom_q (spc4_pcx_atom_bufp1_pq), // Templated
.src4_arb_req_q (spc4_pcx_req_bufp1_pq[4]), // Templated
.src5_arb_atom_q (spc5_pcx_atom_bufp3_pq), // Templated
.src5_arb_req_q (spc5_pcx_req_bufp3_pq[4]), // Templated
.src6_arb_atom_q (spc6_pcx_atom_bufp3_pq), // Templated
.src6_arb_req_q (spc6_pcx_req_bufp3_pq[4]), // Templated
.src7_arb_atom_q (spc7_pcx_atom_bufp3_pq), // Templated
.src7_arb_req_q (spc7_pcx_req_bufp3_pq[4]), // Templated
.stall1_q (1'b0), // Templated
.stall2_q (io_pcx_stall_bufp3_pq), // Templated
.scan_in (pcx_arb3_so_0), // Templated
.se (se_buf1_middle)); // Templated
/*
pcx_buf_top AUTO_TEMPLATE(
// Outputs
.pcx_scache0_atom_px1(pcx_sctag0_atm_px1),
.pcx_scache0_data_px2(pcx_sctag0_data_px2[`PCX_WIDTH-1:0]),
.pcx_scache0_data_rdy_px(pcx_sctag0_data_rdy_px1),
.pcx_scache1_atom_px1(pcx_sctag1_atm_px1),
.pcx_scache1_data_px2(pcx_sctag1_data_px2[`PCX_WIDTH-1:0]),
.pcx_scache1_data_rdy_px(pcx_sctag1_data_rdy_px1),
.pcx_scache2_atom_px1(pcx_sctag2_atm_px1),
.pcx_scache2_data_px2(pcx_sctag2_data_px2[`PCX_WIDTH-1:0]),
.pcx_scache2_data_rdy_px(pcx_sctag2_data_rdy_px1),
.pcx_scache3_atom_px1(pcx_sctag3_atm_px1),
.pcx_scache3_data_px2(pcx_sctag3_data_px2[`PCX_WIDTH-1:0]),
.pcx_scache3_data_rdy_px(pcx_sctag3_data_rdy_px1),
// Inputs
.si_0(pcx_arb4_so_0),
.si_1(pcx_dp_array02_so_1),
//.se(shiftenable),
.arbpc0_pcxdp_q0_hold_arbbf_pa_l(arbpc0_pcxdp_q0_hold_arbbf_pa[7:0]),
.arbpc1_pcxdp_q0_hold_arbbf_pa_l(arbpc1_pcxdp_q0_hold_arbbf_pa[7:0]),
.arbpc2_pcxdp_q0_hold_arbbf_pa_l(arbpc2_pcxdp_q0_hold_arbbf_pa[7:0]),
.arbpc3_pcxdp_q0_hold_arbbf_pa_l(arbpc3_pcxdp_q0_hold_arbbf_pa[7:0]),
.arbpc4_pcxdp_q0_hold_arbbf_pa_l(arbpc4_pcxdp_q0_hold_arbbf_pa[7:0]),
.arbpc0_pcxdp_qsel1_arbbf_pa_l(arbpc0_pcxdp_qsel1_arbbf_pa[7:0]),
.arbpc1_pcxdp_qsel1_arbbf_pa_l(arbpc1_pcxdp_qsel1_arbbf_pa[7:0]),
.arbpc2_pcxdp_qsel1_arbbf_pa_l(arbpc2_pcxdp_qsel1_arbbf_pa[7:0]),
.arbpc3_pcxdp_qsel1_arbbf_pa_l(arbpc3_pcxdp_qsel1_arbbf_pa[7:0]),
.arbpc4_pcxdp_qsel1_arbbf_pa_l(arbpc4_pcxdp_qsel1_arbbf_pa[7:0]),
.scache0_pcx_stall_pq(sctag0_pcx_stall_pq),
.scache3_pcx_stall_pq(sctag3_pcx_stall_pq));
*/
pcx_buf_top pcx_buf_top(/*AUTOINST*/
// Outputs
.arbpc0_pcxdp_grant_pa(arbpc0_pcxdp_grant_pa[7:0]),
.arbpc0_pcxdp_q0_hold_pa_l(arbpc0_pcxdp_q0_hold_pa_l[7:0]),
.arbpc0_pcxdp_qsel0_pa(arbpc0_pcxdp_qsel0_pa[7:0]),
.arbpc0_pcxdp_qsel1_pa_l(arbpc0_pcxdp_qsel1_pa_l[7:0]),
.arbpc0_pcxdp_shift_px(arbpc0_pcxdp_shift_px[7:0]),
.arbpc1_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[7:0]),
.arbpc1_pcxdp_q0_hold_pa_l(arbpc1_pcxdp_q0_hold_pa_l[7:0]),
.arbpc1_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[7:0]),
.arbpc1_pcxdp_qsel1_pa_l(arbpc1_pcxdp_qsel1_pa_l[7:0]),
.arbpc1_pcxdp_shift_px(arbpc1_pcxdp_shift_px[7:0]),
.arbpc2_pcxdp_grant_pa(arbpc2_pcxdp_grant_pa[7:0]),
.arbpc2_pcxdp_q0_hold_pa_l(arbpc2_pcxdp_q0_hold_pa_l[7:0]),
.arbpc2_pcxdp_qsel0_pa(arbpc2_pcxdp_qsel0_pa[7:0]),
.arbpc2_pcxdp_qsel1_pa_l(arbpc2_pcxdp_qsel1_pa_l[7:0]),
.arbpc2_pcxdp_shift_px(arbpc2_pcxdp_shift_px[7:0]),
.arbpc3_pcxdp_grant_pa(arbpc3_pcxdp_grant_pa[7:0]),
.arbpc3_pcxdp_q0_hold_pa_l(arbpc3_pcxdp_q0_hold_pa_l[7:0]),
.arbpc3_pcxdp_qsel0_pa(arbpc3_pcxdp_qsel0_pa[7:0]),
.arbpc3_pcxdp_qsel1_pa_l(arbpc3_pcxdp_qsel1_pa_l[7:0]),
.arbpc3_pcxdp_shift_px(arbpc3_pcxdp_shift_px[7:0]),
.arbpc4_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[7:0]),
.arbpc4_pcxdp_q0_hold_pa_l(arbpc4_pcxdp_q0_hold_pa_l[7:0]),
.arbpc4_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[7:0]),
.arbpc4_pcxdp_qsel1_pa_l(arbpc4_pcxdp_qsel1_pa_l[7:0]),
.arbpc4_pcxdp_shift_px(arbpc4_pcxdp_shift_px[7:0]),
.arst_l_buf_fpio_inff(arst_l_buf_fpio_inff),
.io_pcx_stall_bufp3_pq(io_pcx_stall_bufp3_pq),
.pcx_buf_top_pt0_so_0(pcx_buf_top_pt0_so_0),
.pcx_fpio_data_px2(pcx_fpio_data_px2[`PCX_WIDTH-1:0]),
.pcx_fpio_data_rdy_px2(pcx_fpio_data_rdy_px2),
.pcx_io_data_px2(pcx_io_data_px2[`PCX_WIDTH-1:0]),
.pcx_io_data_rdy_px2(pcx_io_data_rdy_px2),
.pcx_iodata_px2_so_1(pcx_iodata_px2_so_1),
.pcx_scache0_atom_px1(pcx_sctag0_atm_px1), // Templated
.pcx_scache0_dat_px2_so_1(pcx_scache0_dat_px2_so_1),
.pcx_scache0_data_px2(pcx_sctag0_data_px2[`PCX_WIDTH-1:0]), // Templated
.pcx_scache0_data_rdy_px(pcx_sctag0_data_rdy_px1), // Templated
.pcx_scache1_atom_px1(pcx_sctag1_atm_px1), // Templated
.pcx_scache1_dat_px2_so_1(pcx_scache1_dat_px2_so_1),
.pcx_scache1_data_px2(pcx_sctag1_data_px2[`PCX_WIDTH-1:0]), // Templated
.pcx_scache1_data_rdy_px(pcx_sctag1_data_rdy_px1), // Templated
.pcx_scache2_atom_px1(pcx_sctag2_atm_px1), // Templated
.pcx_scache2_dat_px2_so_1(pcx_scache2_dat_px2_so_1),
.pcx_scache2_data_px2(pcx_sctag2_data_px2[`PCX_WIDTH-1:0]), // Templated
.pcx_scache2_data_rdy_px(pcx_sctag2_data_rdy_px1), // Templated
.pcx_scache3_atom_px1(pcx_sctag3_atm_px1), // Templated
.pcx_scache3_data_px2(pcx_sctag3_data_px2[`PCX_WIDTH-1:0]), // Templated
.pcx_scache3_data_rdy_px(pcx_sctag3_data_rdy_px1), // Templated
.pcx_spc0_grant_px(pcx_spc0_grant_px[4:0]),
.pcx_spc1_grant_px(pcx_spc1_grant_px[4:0]),
.pcx_spc2_grant_px(pcx_spc2_grant_px[4:0]),
.pcx_spc3_grant_px(pcx_spc3_grant_px[4:0]),
.pcx_spc4_grant_px(pcx_spc4_grant_px[4:0]),
.pcx_spc5_grant_px(pcx_spc5_grant_px[4:0]),
.pcx_spc6_grant_px(pcx_spc6_grant_px[4:0]),
.pcx_spc7_grant_px(pcx_spc7_grant_px[4:0]),
.scache0_pcx_stall_bufp1_pq(scache0_pcx_stall_bufp1_pq),
.scache3_pcx_stall_bufp3_pq(scache3_pcx_stall_bufp3_pq),
.sctag1_pcx_stall_bufp1_pq(sctag1_pcx_stall_bufp1_pq),
.spc0_pcx_atom_bufp1_pq(spc0_pcx_atom_bufp1_pq),
.spc0_pcx_data_buf_pa(spc0_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc0_pcx_req_bufp1_pq(spc0_pcx_req_bufp1_pq[4:0]),
.spc1_pcx_atom_bufp1_pq(spc1_pcx_atom_bufp1_pq),
.spc1_pcx_data_buf_pa(spc1_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc1_pcx_req_bufp1_pq(spc1_pcx_req_bufp1_pq[4:0]),
.spc2_pcx_atom_bufp1_pq(spc2_pcx_atom_bufp1_pq),
.spc2_pcx_data_buf_pa(spc2_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc2_pcx_req_bufp1_pq(spc2_pcx_req_bufp1_pq[4:0]),
.spc3_pcx_atom_bufp1_pq(spc3_pcx_atom_bufp1_pq),
.spc3_pcx_data_buf_pa(spc3_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc3_pcx_req_bufp1_pq(spc3_pcx_req_bufp1_pq[4:0]),
.spc4_pcx_atom_bufp1_pq(spc4_pcx_atom_bufp1_pq),
.spc4_pcx_data_buf_pa(spc4_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc4_pcx_req_bufp1_pq(spc4_pcx_req_bufp1_pq[4:0]),
.spc5_pcx_atom_bufp3_pq(spc5_pcx_atom_bufp3_pq),
.spc5_pcx_data_buf_pa(spc5_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc5_pcx_req_bufp3_pq(spc5_pcx_req_bufp3_pq[4:0]),
.spc6_pcx_atom_bufp3_pq(spc6_pcx_atom_bufp3_pq),
.spc6_pcx_data_buf_pa(spc6_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc6_pcx_req_bufp3_pq(spc6_pcx_req_bufp3_pq[4:0]),
.spc7_pcx_atom_bufp3_pq(spc7_pcx_atom_bufp3_pq),
.spc7_pcx_data_buf_pa(spc7_pcx_data_buf_pa[`PCX_WIDTH-1:0]),
.spc7_pcx_req_bufp3_pq(spc7_pcx_req_bufp3_pq[4:0]),
// Inputs
.arbpc0_pcxdp_grant_arbbf_pa(arbpc0_pcxdp_grant_arbbf_pa[7:0]),
.arbpc0_pcxdp_q0_hold_arbbf_pa_l(arbpc0_pcxdp_q0_hold_arbbf_pa[7:0]), // Templated
.arbpc0_pcxdp_qsel0_arbbf_pa(arbpc0_pcxdp_qsel0_arbbf_pa[7:0]),
.arbpc0_pcxdp_qsel1_arbbf_pa_l(arbpc0_pcxdp_qsel1_arbbf_pa[7:0]), // Templated
.arbpc0_pcxdp_shift_arbbf_px(arbpc0_pcxdp_shift_arbbf_px[7:0]),
.arbpc1_pcxdp_grant_arbbf_pa(arbpc1_pcxdp_grant_arbbf_pa[7:0]),
.arbpc1_pcxdp_q0_hold_arbbf_pa_l(arbpc1_pcxdp_q0_hold_arbbf_pa[7:0]), // Templated
.arbpc1_pcxdp_qsel0_arbbf_pa(arbpc1_pcxdp_qsel0_arbbf_pa[7:0]),
.arbpc1_pcxdp_qsel1_arbbf_pa_l(arbpc1_pcxdp_qsel1_arbbf_pa[7:0]), // Templated
.arbpc1_pcxdp_shift_arbbf_px(arbpc1_pcxdp_shift_arbbf_px[7:0]),
.arbpc2_pcxdp_grant_arbbf_pa(arbpc2_pcxdp_grant_arbbf_pa[7:0]),
.arbpc2_pcxdp_q0_hold_arbbf_pa_l(arbpc2_pcxdp_q0_hold_arbbf_pa[7:0]), // Templated
.arbpc2_pcxdp_qsel0_arbbf_pa(arbpc2_pcxdp_qsel0_arbbf_pa[7:0]),
.arbpc2_pcxdp_qsel1_arbbf_pa_l(arbpc2_pcxdp_qsel1_arbbf_pa[7:0]), // Templated
.arbpc2_pcxdp_shift_arbbf_px(arbpc2_pcxdp_shift_arbbf_px[7:0]),
.arbpc3_pcxdp_grant_arbbf_pa(arbpc3_pcxdp_grant_arbbf_pa[7:0]),
.arbpc3_pcxdp_q0_hold_arbbf_pa_l(arbpc3_pcxdp_q0_hold_arbbf_pa[7:0]), // Templated
.arbpc3_pcxdp_qsel0_arbbf_pa(arbpc3_pcxdp_qsel0_arbbf_pa[7:0]),
.arbpc3_pcxdp_qsel1_arbbf_pa_l(arbpc3_pcxdp_qsel1_arbbf_pa[7:0]), // Templated
.arbpc3_pcxdp_shift_arbbf_px(arbpc3_pcxdp_shift_arbbf_px[7:0]),
.arbpc4_pcxdp_grant_arbbf_pa(arbpc4_pcxdp_grant_arbbf_pa[7:0]),
.arbpc4_pcxdp_q0_hold_arbbf_pa_l(arbpc4_pcxdp_q0_hold_arbbf_pa[7:0]), // Templated
.arbpc4_pcxdp_qsel0_arbbf_pa(arbpc4_pcxdp_qsel0_arbbf_pa[7:0]),
.arbpc4_pcxdp_qsel1_arbbf_pa_l(arbpc4_pcxdp_qsel1_arbbf_pa[7:0]), // Templated
.arbpc4_pcxdp_shift_arbbf_px(arbpc4_pcxdp_shift_arbbf_px[7:0]),
.ccx_clk_hdr_so_1(ccx_clk_hdr_so_1),
.cmp_arst_l (cmp_arst_l),
.cpx_buf_top_pt0_so_1(cpx_buf_top_pt0_so_1),
.io_pcx_stall_pq(io_pcx_stall_pq),
.pcx_fpio_data_px_l(pcx_fpio_data_px_l[`PCX_WIDTH-1:0]),
.pcx_fpio_data_rdy_arb_px(pcx_fpio_data_rdy_arb_px),
.pcx_scache0_atom_px(pcx_scache0_atom_px),
.pcx_scache0_data_px_l(pcx_scache0_data_px_l[`PCX_WIDTH-1:0]),
.pcx_scache0_data_rdy_arb_px(pcx_scache0_data_rdy_arb_px),
.pcx_scache1_atom_px(pcx_scache1_atom_px),
.pcx_scache1_data_px_l(pcx_scache1_data_px_l[`PCX_WIDTH-1:0]),
.pcx_scache1_data_rdy_arb_px(pcx_scache1_data_rdy_arb_px),
.pcx_scache2_atom_px(pcx_scache2_atom_px),
.pcx_scache2_data_px_l(pcx_scache2_data_px_l[`PCX_WIDTH-1:0]),
.pcx_scache2_data_rdy_arb_px(pcx_scache2_data_rdy_arb_px),
.pcx_scache3_atom_px(pcx_scache3_atom_px),
.pcx_scache3_data_px_l(pcx_scache3_data_px_l[`PCX_WIDTH-1:0]),
.pcx_scache3_data_rdy_arb_px(pcx_scache3_data_rdy_arb_px),
.pcx_spc0_grant_pa(pcx_spc0_grant_pa[4:0]),
.pcx_spc1_grant_pa(pcx_spc1_grant_pa[4:0]),
.pcx_spc2_grant_pa(pcx_spc2_grant_pa[4:0]),
.pcx_spc3_grant_pa(pcx_spc3_grant_pa[4:0]),
.pcx_spc4_grant_pa(pcx_spc4_grant_pa[4:0]),
.pcx_spc5_grant_pa(pcx_spc5_grant_pa[4:0]),
.pcx_spc6_grant_pa(pcx_spc6_grant_pa[4:0]),
.pcx_spc7_grant_pa(pcx_spc7_grant_pa[4:0]),
.pt1_so_1 (pt1_so_1),
.rclk (rclk),
.scache0_pcx_stall_pq(sctag0_pcx_stall_pq), // Templated
.scache3_pcx_stall_pq(sctag3_pcx_stall_pq), // Templated
.sctag1_pcx_stall_pq(sctag1_pcx_stall_pq),
.se_buf0_middle(se_buf0_middle),
.se_buf1_bottom(se_buf1_bottom),
.se_buf1_top (se_buf1_top),
.se_buf2_bottom(se_buf2_bottom),
.se_buf2_top (se_buf2_top),
.se_buf3_bottom(se_buf3_bottom),
.se_buf3_middle(se_buf3_middle),
.se_buf3_top (se_buf3_top),
.se_buf4_bottom(se_buf4_bottom),
.se_buf4_top (se_buf4_top),
.se_buf5_bottom(se_buf5_bottom),
.se_buf5_top (se_buf5_top),
.si_0 (pcx_arb4_so_0), // Templated
.si_1 (pcx_dp_array02_so_1), // Templated
.spc0_pcx_atom_pq(spc0_pcx_atom_pq),
.spc0_pcx_req_pq(spc0_pcx_req_pq[4:0]),
.spc1_pcx_atom_pq(spc1_pcx_atom_pq),
.spc1_pcx_req_pq(spc1_pcx_req_pq[4:0]),
.spc2_pcx_atom_pq(spc2_pcx_atom_pq),
.spc2_pcx_req_pq(spc2_pcx_req_pq[4:0]),
.spc3_pcx_atom_pq(spc3_pcx_atom_pq),
.spc3_pcx_req_pq(spc3_pcx_req_pq[4:0]),
.spc4_pcx_atom_pq(spc4_pcx_atom_pq),
.spc4_pcx_req_pq(spc4_pcx_req_pq[4:0]),
.spc5_pcx_atom_pq(spc5_pcx_atom_pq),
.spc5_pcx_req_pq(spc5_pcx_req_pq[4:0]),
.spc6_pcx_atom_pq(spc6_pcx_atom_pq),
.spc6_pcx_req_pq(spc6_pcx_req_pq[4:0]),
.spc7_pcx_atom_pq(spc7_pcx_atom_pq),
.spc7_pcx_req_pq(spc7_pcx_req_pq[4:0]),
.spc1_pcx_data_pa(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc3_pcx_data_pa(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc5_pcx_data_pa(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc7_pcx_data_pa(spc7_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc0_pcx_data_pa(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc2_pcx_data_pa(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc4_pcx_data_pa(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
.spc6_pcx_data_pa(spc6_pcx_data_pa[`PCX_WIDTH-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../../common/rtl")
// End:
|
// spam messages at 9600 baud over UART
module uart_hello
(
input wire clk50,
input wire uart_rts,
input wire uart_rxd,
output wire uart_cts,
output wire uart_txd
);
`define LEN 14
reg [8*`LEN:0] text = "Hello World!\r\n";
reg [7:0] data;
wire rst;
wire nextch;
integer idx, i;
initial begin
idx <= 0;
end
always @ (posedge clk50) begin
for (i = 0; i < 8; i = i + 1)
data[i] = text[8*(`LEN-1-idx) + i];
if (nextch)
idx = (idx + 1) % `LEN;
end
assign uart_cts = 0;
reset_delay r0(
.clk(clk50),
.rst(rst)
);
uart_transmitter t0(
.clk(clk50),
.rst(rst),
.data(data),
.nextch(nextch),
.txd(uart_txd)
);
endmodule
`timescale 1ns/1ns
module uart_hello_test();
reg clk50;
wire uart_rts;
wire uart_rxd;
wire uart_cts;
wire uart_txd;
initial begin
clk50 = 0;
end
always begin
#20 clk50 = ~clk50;
end
uart_hello u0(
.clk50(clk50),
.uart_rts(uart_rts),
.uart_rxd(uart_rxd),
.uart_cts(uart_cts),
.uart_txd(uart_txd)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A221OI_BEHAVIORAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_BEHAVIORAL_V
|
//-----------------------------------------------------------------------------
// Title : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : v6_emac_v1_5.v
// Version : 1.5
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//------------------------------------------------------------------------------
// Description: This wrapper file instantiates the full Virtex-6 Embedded
// Tri-Mode Ethernet MAC (EMAC) primitive, where:
//
// * all unused input ports on the primitive are tied to the
// appropriate logic level;
//
// * all unused output ports on the primitive are left
// unconnected;
//
// * the attributes are set based on the options selected
// from CORE Generator;
//
// * only used ports are connected to the ports of this
// wrapper file.
//
// This simplified wrapper should therefore be used as the
// instantiation template for the EMAC primitive in customer
// designs.
//------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//------------------------------------------------------------------------------
// Module declaration for the primitive-level wrapper
//------------------------------------------------------------------------------
(* X_CORE_INFO = "v6_emac_v1_5, Coregen 13.1" *)
(* CORE_GENERATION_INFO = "v6_emac_v1_5,v6_emac_v1_5,{c_has_mii=false,c_has_gmii=true,c_has_rgmii_v1_3=false,c_has_rgmii_v2_0=false,c_has_sgmii=false,c_has_gpcs=false,c_tri_speed=false,c_speed_10=false,c_speed_100=false,c_speed_1000=true,c_has_host=false,c_has_dcr=false,c_has_mdio=false,c_client_16=false,c_add_filter=false,c_has_clock_enable=false,c_serial_mode_switch_en=false,c_overclocking_rate_2000mbps=false,c_overclocking_rate_2500mbps=false,}" *)
module v6_emac_v1_5
(
// Client Receiver Interface
EMACCLIENTRXCLIENTCLKOUT,
CLIENTEMACRXCLIENTCLKIN,
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXDVLDMSW,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
// Client Transmitter Interface
EMACCLIENTTXCLIENTCLKOUT,
CLIENTEMACTXCLIENTCLKIN,
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
CLIENTEMACTXDVLDMSW,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
// MAC Control Interface
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
// Clock Signals
GTX_CLK,
PHYEMACTXGMIIMIICLKIN,
EMACPHYTXGMIIMIICLKOUT,
// GMII Interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
// MMCM Lock Indicator
MMCM_LOCKED,
// Asynchronous Reset
RESET
);
//--------------------------------------------------------------------------
// Port declarations
//--------------------------------------------------------------------------
// Client Receiver Interface
output EMACCLIENTRXCLIENTCLKOUT;
input CLIENTEMACRXCLIENTCLKIN;
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXDVLDMSW;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
// Client Transmitter Interface
output EMACCLIENTTXCLIENTCLKOUT;
input CLIENTEMACTXCLIENTCLKIN;
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
input CLIENTEMACTXDVLDMSW;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
// MAC Control Interface
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
// Clock Signals
input GTX_CLK;
output EMACPHYTXGMIIMIICLKOUT;
input PHYEMACTXGMIIMIICLKIN;
// GMII Interface
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
// MMCM Lock Indicator
input MMCM_LOCKED;
// Asynchronous Reset
input RESET;
//--------------------------------------------------------------------------
// Wire declarations
//--------------------------------------------------------------------------
wire [15:0] client_rx_data_i;
wire [15:0] client_tx_data_i;
//--------------------------------------------------------------------------
// Main body of code
//--------------------------------------------------------------------------
// Use the 8-bit client data interface
assign EMACCLIENTRXD = client_rx_data_i[7:0];
assign #4000 client_tx_data_i = {8'b00000000, CLIENTEMACTXD};
// Instantiate the Virtex-6 Embedded Tri-Mode Ethernet MAC
TEMAC_SINGLE #(
// PCS/PMA logic is not in use
.EMAC_PHYINITAUTONEG_ENABLE ("FALSE"),
.EMAC_PHYISOLATE ("FALSE"),
.EMAC_PHYLOOPBACKMSB ("FALSE"),
.EMAC_PHYPOWERDOWN ("FALSE"),
.EMAC_PHYRESET ("TRUE"),
.EMAC_GTLOOPBACK ("FALSE"),
.EMAC_UNIDIRECTION_ENABLE ("FALSE"),
.EMAC_LINKTIMERVAL (9'h000),
.EMAC_MDIO_IGNORE_PHYADZERO ("FALSE"),
// Configure the EMAC operating mode
// MDIO is not enabled
.EMAC_MDIO_ENABLE ("FALSE"),
// Speed is defaulted to 1000 Mb/s
.EMAC_SPEED_LSB ("FALSE"),
.EMAC_SPEED_MSB ("TRUE"),
// Clock Enable advanced clocking is not in use
.EMAC_USECLKEN ("FALSE"),
// Byte PHY advanced clocking is not supported. Do not modify.
.EMAC_BYTEPHY ("FALSE"),
// RGMII physical interface is not in use
.EMAC_RGMII_ENABLE ("FALSE"),
// SGMII physical interface is not in use
.EMAC_SGMII_ENABLE ("FALSE"),
.EMAC_1000BASEX_ENABLE ("FALSE"),
// The host interface is not enabled
.EMAC_HOST_ENABLE ("FALSE"),
// The Tx-side 8-bit client data interface is used
.EMAC_TX16BITCLIENT_ENABLE ("FALSE"),
// The Rx-side 8-bit client data interface is used
.EMAC_RX16BITCLIENT_ENABLE ("FALSE"),
// The address filter is not enabled
.EMAC_ADDRFILTER_ENABLE ("FALSE"),
// EMAC configuration defaults
// Rx Length/Type checking is enabled
.EMAC_LTCHECK_DISABLE ("FALSE"),
// Rx control frame length checking is enabled
.EMAC_CTRLLENCHECK_DISABLE ("FALSE"),
// Rx flow control is not enabled
.EMAC_RXFLOWCTRL_ENABLE ("FALSE"),
// Tx flow control is not enabled
.EMAC_TXFLOWCTRL_ENABLE ("FALSE"),
// Transmitter is not held in reset
.EMAC_TXRESET ("FALSE"),
// Transmitter Jumbo frames are not enabled
.EMAC_TXJUMBOFRAME_ENABLE ("FALSE"),
// Transmitter in-band FCS is not enabled
.EMAC_TXINBANDFCS_ENABLE ("FALSE"),
// Transmitter is enabled
.EMAC_TX_ENABLE ("TRUE"),
// Transmitter VLAN frames are not enabled
.EMAC_TXVLAN_ENABLE ("FALSE"),
// Transmitter full-duplex mode is enabled
.EMAC_TXHALFDUPLEX ("FALSE"),
// Transmitter IFG Adjust is not enabled
.EMAC_TXIFGADJUST_ENABLE ("FALSE"),
// Receiver is not held in reset
.EMAC_RXRESET ("FALSE"),
// Receiver Jumbo frames are not enabled
.EMAC_RXJUMBOFRAME_ENABLE ("FALSE"),
// Receiver in-band FCS is not enabled
.EMAC_RXINBANDFCS_ENABLE ("FALSE"),
// Receiver is enabled
.EMAC_RX_ENABLE ("TRUE"),
// Receiver VLAN frames are not enabled
.EMAC_RXVLAN_ENABLE ("FALSE"),
// Receiver full-duplex mode is enabled
.EMAC_RXHALFDUPLEX ("FALSE"),
// Configure the EMAC addressing
// Set the PAUSE address default
.EMAC_PAUSEADDR (48'hFFEEDDCCBBAA),
// Do not set the unicast address (address filter is unused)
.EMAC_UNICASTADDR (48'h000000000000),
// Do not set the DCR base address (DCR is unused)
.EMAC_DCRBASEADDR (8'h00)
)
v6_emac
(
.RESET (RESET),
.EMACCLIENTRXCLIENTCLKOUT (EMACCLIENTRXCLIENTCLKOUT),
.CLIENTEMACRXCLIENTCLKIN (CLIENTEMACRXCLIENTCLKIN),
.EMACCLIENTRXD (client_rx_data_i),
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXDVLDMSW (EMACCLIENTRXDVLDMSW),
.EMACCLIENTRXGOODFRAME (EMACCLIENTRXGOODFRAME),
.EMACCLIENTRXBADFRAME (EMACCLIENTRXBADFRAME),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
.EMACCLIENTTXCLIENTCLKOUT (EMACCLIENTTXCLIENTCLKOUT),
.CLIENTEMACTXCLIENTCLKIN (CLIENTEMACTXCLIENTCLKIN),
.CLIENTEMACTXD (client_tx_data_i),
.CLIENTEMACTXDVLD (CLIENTEMACTXDVLD),
.CLIENTEMACTXDVLDMSW (CLIENTEMACTXDVLDMSW),
.EMACCLIENTTXACK (EMACCLIENTTXACK),
.CLIENTEMACTXFIRSTBYTE (CLIENTEMACTXFIRSTBYTE),
.CLIENTEMACTXUNDERRUN (CLIENTEMACTXUNDERRUN),
.EMACCLIENTTXCOLLISION (EMACCLIENTTXCOLLISION),
.EMACCLIENTTXRETRANSMIT (EMACCLIENTTXRETRANSMIT),
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
.PHYEMACGTXCLK (GTX_CLK),
.EMACPHYTXGMIIMIICLKOUT (EMACPHYTXGMIIMIICLKOUT),
.PHYEMACTXGMIIMIICLKIN (PHYEMACTXGMIIMIICLKIN),
.PHYEMACRXCLK (GMII_RX_CLK),
.PHYEMACRXD (GMII_RXD),
.PHYEMACRXDV (GMII_RX_DV),
.PHYEMACRXER (GMII_RX_ER),
.EMACPHYTXCLK (),
.EMACPHYTXD (GMII_TXD),
.EMACPHYTXEN (GMII_TX_EN),
.EMACPHYTXER (GMII_TX_ER),
.PHYEMACMIITXCLK (1'b0),
.PHYEMACCOL (1'b0),
.PHYEMACCRS (1'b0),
.CLIENTEMACDCMLOCKED (MMCM_LOCKED),
.EMACCLIENTANINTERRUPT (),
.PHYEMACSIGNALDET (1'b0),
.PHYEMACPHYAD (5'b00000),
.EMACPHYENCOMMAALIGN (),
.EMACPHYLOOPBACKMSB (),
.EMACPHYMGTRXRESET (),
.EMACPHYMGTTXRESET (),
.EMACPHYPOWERDOWN (),
.EMACPHYSYNCACQSTATUS (),
.PHYEMACRXCLKCORCNT (3'b000),
.PHYEMACRXBUFSTATUS (2'b00),
.PHYEMACRXCHARISCOMMA (1'b0),
.PHYEMACRXCHARISK (1'b0),
.PHYEMACRXDISPERR (1'b0),
.PHYEMACRXNOTINTABLE (1'b0),
.PHYEMACRXRUNDISP (1'b0),
.PHYEMACTXBUFERR (1'b0),
.EMACPHYTXCHARDISPMODE (),
.EMACPHYTXCHARDISPVAL (),
.EMACPHYTXCHARISK (),
.EMACPHYMCLKOUT (),
.PHYEMACMCLKIN (1'b0),
.PHYEMACMDIN (1'b1),
.EMACPHYMDOUT (),
.EMACPHYMDTRI (),
.EMACSPEEDIS10100 (),
.HOSTCLK (1'b0),
.HOSTOPCODE (2'b00),
.HOSTREQ (1'b0),
.HOSTMIIMSEL (1'b0),
.HOSTADDR (10'b0000000000),
.HOSTWRDATA (32'h00000000),
.HOSTMIIMRDY (),
.HOSTRDDATA (),
.DCREMACCLK (1'b0),
.DCREMACABUS (10'h000),
.DCREMACREAD (1'b0),
.DCREMACWRITE (1'b0),
.DCREMACDBUS (32'h00000000),
.EMACDCRACK (),
.EMACDCRDBUS (),
.DCREMACENABLE (1'b0),
.DCRHOSTDONEIR ()
);
endmodule
|
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