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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlygate4sd2 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_FUNCTIONAL_V
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_cmdram_wrap.v
// Version : v1.0
// Description: command ram wrapper module: To manage the read/write
// addresses to cmdram module.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_cmdram_wrap #
(
parameter C_FAMILY = "virtex7",
parameter C_ATG_BASIC_AXI4 = 1 ,
parameter C_M_AXI_DATA_WIDTH = 32 ,
parameter C_RAMINIT_CMDRAM0_F = "NONE",
parameter C_RAMINIT_CMDRAM1_F = "NONE",
parameter C_RAMINIT_CMDRAM2_F = "NONE",
parameter C_RAMINIT_CMDRAM3_F = "NONE"
) (
input Clk ,
input rst_l ,
input [15:0 ] cmdram_we ,
input [15:0 ] aw_agen_addr ,
input reg0_m_enable_ff ,
input [9:0 ] reg0_mw_ptr_update , //maw_ptr_new
input [9:0 ] reg0_mr_ptr_update , //mar_ptr_new
input [9:0 ] mar_ptr_new_ff ,
input [15:0 ] ar_agen0_addr ,
input [63:0 ] slvram_wr_data ,
input arfifo_valid ,
input [71:0 ] arfifo_out ,
input [23:0 ] param_cmdr_submitcnt_ff ,
input [23:0 ] param_cmdw_submitcnt_ff ,
input [9:0 ] maw_ptr_new_ff ,
output [127:0] cmd_out_mr_i ,
output cmdram_mr_regslice_id_stable,
output [127:0] cmd_out_mw_regslice ,
output [127:0] cmd_out_mr_regslice ,
output [127:0] cmd_out_mw_regslice_ff ,
output [127:0] cmd_out_mr_regslice_ff ,
output cmdram_mw_regslice_id_stable
);
wire [9:0] maw_ptr_new = reg0_mw_ptr_update;
wire [9:0] mar_ptr_new = reg0_mr_ptr_update;
wire [127:0] cmd_out_mw_i;
wire [15:0] cmdram_addra = (reg0_m_enable_ff) ?
{ 4'b0001, maw_ptr_new[7:0], 4'b0000 } :
{ 3'b000, aw_agen_addr[12:4], 4'b0000 };
wire [15:0] cmdram_addrb = (reg0_m_enable_ff) ?
{ 4'b0000, mar_ptr_new[7:0], 4'b0000 } :
{ 3'b000, ar_agen0_addr[12:4], 4'b0000 };
wire [127:0] cmd_out_mw_raw;
wire [127:0] cmd_out_mr_raw;
generate if (C_ATG_BASIC_AXI4 == 0 ) begin : CMDRAM_FULLAXI
assign cmd_out_mw_i = cmd_out_mw_raw;
assign cmd_out_mr_i = cmd_out_mr_raw;
end
endgenerate
//
//Fixed controls for a basic axi4 support.
//
wire [2:0] size;
generate if(C_M_AXI_DATA_WIDTH == 32 ) begin : CMDWRAP_SISE32
assign size = 3'b010;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 64 ) begin : CMDWRAP_SISE64
assign size = 3'b011;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 128 ) begin : CMDWRAP_SISE128
assign size = 3'b100;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 256 ) begin : CMDWRAP_SISE256
assign size = 3'b101;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 512 ) begin : CMDWRAP_SISE512
assign size = 3'b110;
end
endgenerate
wire fixed_lock = 1'b0;
wire [1:0] fixed_burst = 2'b01;
wire [2:0] fixed_prot = 3'b010;
wire [3:0] fixed_cache = 4'h0;
wire [7:0] fixed_user = 7'h0;
wire [2:0] fixed_size = size;
wire [3:0] fixed_qos = 4'h0;
generate if (C_ATG_BASIC_AXI4 == 1 ) begin : CMDRAM_BASICAXI
assign cmd_out_mw_i = {
cmd_out_mw_raw[127],fixed_qos,fixed_user,fixed_cache,cmd_out_mw_raw[99:96],
cmd_out_mw_raw[95:64],
cmd_out_mw_raw[63:56],fixed_prot,cmd_out_mw_raw[52:47],fixed_size,fixed_burst,cmd_out_mw_raw[41],fixed_lock,cmd_out_mw_raw[39:32],
cmd_out_mw_raw[31:0]
};
assign cmd_out_mr_i = {
cmd_out_mr_raw[127],fixed_qos,fixed_user,fixed_cache,cmd_out_mr_raw[99:96],
cmd_out_mr_raw[95:64],
cmd_out_mr_raw[63:56],fixed_prot,cmd_out_mr_raw[52:47],fixed_size,fixed_burst,cmd_out_mr_raw[41],fixed_lock,cmd_out_mr_raw[39:32],
cmd_out_mr_raw[31:0]
};
end
endgenerate
axi_traffic_gen_v2_0_cmdram #(
.C_FAMILY (C_FAMILY ),
.C_INITRAM_0(C_RAMINIT_CMDRAM0_F),
.C_INITRAM_1(C_RAMINIT_CMDRAM1_F),
.C_INITRAM_2(C_RAMINIT_CMDRAM2_F),
.C_INITRAM_3(C_RAMINIT_CMDRAM3_F)
) Cmdram (
.reset (~rst_l ),
.clk_a (Clk ),
.we_a (cmdram_we[15:0] ),
.active (reg0_m_enable_ff ),
.addr_a_idle ({ 3'b000, aw_agen_addr[12:4], 4'b0000 } ),
.addr_a_active ( { 4'b0001, maw_ptr_new_ff[7:0], 4'b0000 }),
.wr_data_a ({ 2 { slvram_wr_data[63:0] } } ),
.rd_data_a (cmd_out_mw_raw[127:0] ),
.clk_b (Clk ),
.addr_b_idle_latch(arfifo_valid ),
.addr_b_idle ({ 3'b000, arfifo_out[12:4], 4'b0000 } ),
.addr_b_active ({ 4'b0000, mar_ptr_new_ff[7:0], 4'b0000 } ),
.rd_data_b (cmd_out_mr_raw[127:0] )
);
// id is a mix of submitcnt,mar_ptr -- so can ID new cmds even if just a repeat
wire [9:0] cmdram_mr_regslice_idin = {param_cmdr_submitcnt_ff[0],1'b0, mar_ptr_new_ff[7:0]};
wire [9:0] cmdram_mw_regslice_idin = {param_cmdw_submitcnt_ff[0],reg0_m_enable_ff, maw_ptr_new_ff[7:0]};
axi_traffic_gen_v2_0_regslice
#(
.DWIDTH (128 ),
.IDWIDTH (10 ),
.DATADEPTH(`REGSLICE_CMDRAM_MR_DATA),
.IDDEPTH (`REGSLICE_CMDRAM_MR_ID )
)
cmdram_regslice_r
(
.din (cmd_out_mr_i ),
.dout (cmd_out_mr_regslice_ff ),
.dout_early (cmd_out_mr_regslice ),
.idin (cmdram_mr_regslice_idin ),
.idout ( ),
.id_stable (cmdram_mr_regslice_id_stable),
.id_stable_ff( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
axi_traffic_gen_v2_0_regslice
#(
.DWIDTH (128 ),
.IDWIDTH (10 ),
.DATADEPTH(`REGSLICE_CMDRAM_MW_DATA),
.IDDEPTH (`REGSLICE_CMDRAM_MW_ID )
)
cmdram_regslice_w
(
.din (cmd_out_mw_i ),
.dout (cmd_out_mw_regslice_ff ),
.dout_early (cmd_out_mw_regslice ),
.idin (cmdram_mw_regslice_idin ),
.idout ( ),
.id_stable (cmdram_mw_regslice_id_stable),
.id_stable_ff( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file k7_prime_fifo_plain.v when simulating
// the core, k7_prime_fifo_plain. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module k7_prime_fifo_plain(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full
);
input rst;
input wr_clk;
input rd_clk;
input [71 : 0] din;
input wr_en;
input rd_en;
output [71 : 0] dout;
output full;
output empty;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(72),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(72),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(6),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(4),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(5),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(6),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(496),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(495),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(125),
.C_RD_PNTR_WIDTH(9),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(125),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.PROG_FULL(prog_full),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22O_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A22O_BLACKBOX_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a22o (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22O_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// serialInterface.v ////
//// ////
//// This file is part of the i2cSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Perform all serial to parallel, and parallel
//// to serial conversions. Perform device address matching
//// Handle arbitrary length I2C reads terminated by NAK
//// from host, and arbitrary length I2C writes terminated
//// by STOP from host
//// The second byte of a I2C write is always interpreted
//// as a register address, and becomes the base register address
//// for all read and write transactions.
//// I2C WRITE: devAddr, regAddr, data[regAddr], data[regAddr+1], ..... data[regAddr+N]
//// I2C READ: data[regAddr], data[regAddr+1], ..... data[regAddr+N]
//// Note that when regAddR reaches 255 it will automatically wrap round to 0
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "i2cSlave_define.v"
module serialInterface (clearStartStopDet, clk, dataIn, dataOut, regAddr, rst, scl, sdaIn, sdaOut, startStopDetState, writeEn, i2c_address);
input [7:1]i2c_address;
input clk;
input [7:0]dataIn;
input rst;
input scl;
input sdaIn;
input [1:0]startStopDetState;
output clearStartStopDet;
output [7:0]dataOut;
output [7:0]regAddr;
output sdaOut;
output writeEn;
reg clearStartStopDet, next_clearStartStopDet;
wire clk;
wire [7:0]dataIn;
reg [7:0]dataOut, next_dataOut;
reg [7:0]regAddr, next_regAddr;
wire rst;
wire scl;
wire sdaIn;
reg sdaOut, next_sdaOut;
wire [1:0]startStopDetState;
reg writeEn, next_writeEn;
// diagram signals declarations
reg [2:0]bitCnt, next_bitCnt;
reg [7:0]rxData, next_rxData;
reg [1:0]streamSt, next_streamSt;
reg [7:0]txData, next_txData;
// BINARY ENCODED state machine: SISt
// State codes definitions:
`define START 4'b0000
`define CHK_RD_WR 4'b0001
`define READ_RD_LOOP 4'b0010
`define READ_WT_HI 4'b0011
`define READ_CHK_LOOP_FIN 4'b0100
`define READ_WT_LO 4'b0101
`define READ_WT_ACK 4'b0110
`define WRITE_WT_LO 4'b0111
`define WRITE_WT_HI 4'b1000
`define WRITE_CHK_LOOP_FIN 4'b1001
`define WRITE_LOOP_WT_LO 4'b1010
`define WRITE_ST_LOOP 4'b1011
`define WRITE_WT_LO2 4'b1100
`define WRITE_WT_HI2 4'b1101
`define WRITE_CLR_WR 4'b1110
`define WRITE_CLR_ST_STOP 4'b1111
reg [3:0]CurrState_SISt, NextState_SISt;
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
// Machine: SISt
// NextState logic (combinatorial)
always @ (startStopDetState or streamSt or scl or txData or bitCnt or rxData or sdaIn or regAddr or dataIn or sdaOut or writeEn or dataOut or clearStartStopDet or CurrState_SISt)
begin
NextState_SISt <= CurrState_SISt;
// Set default values for outputs and signals
next_streamSt <= streamSt;
next_txData <= txData;
next_rxData <= rxData;
next_sdaOut <= sdaOut;
next_writeEn <= writeEn;
next_dataOut <= dataOut;
next_bitCnt <= bitCnt;
next_clearStartStopDet <= clearStartStopDet;
next_regAddr <= regAddr;
case (CurrState_SISt) // synopsys parallel_case full_case
`START:
begin
next_streamSt <= `STREAM_IDLE;
next_txData <= 8'h00;
next_rxData <= 8'h00;
next_sdaOut <= 1'b1;
next_writeEn <= 1'b0;
next_dataOut <= 8'h00;
next_bitCnt <= 3'b000;
next_clearStartStopDet <= 1'b0;
NextState_SISt <= `CHK_RD_WR;
end
`CHK_RD_WR:
begin
if (streamSt == `STREAM_READ)
begin
NextState_SISt <= `READ_RD_LOOP;
next_txData <= dataIn;
next_regAddr <= regAddr + 1'b1;
next_bitCnt <= 3'b001;
end
else
begin
NextState_SISt <= `WRITE_WT_HI;
next_rxData <= 8'h00;
end
end
`READ_RD_LOOP:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `READ_WT_HI;
next_sdaOut <= txData [7];
next_txData <= {txData [6:0], 1'b0};
end
end
`READ_WT_HI:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `READ_CHK_LOOP_FIN;
end
end
`READ_CHK_LOOP_FIN:
begin
if (bitCnt == 3'b000)
begin
NextState_SISt <= `READ_WT_LO;
end
else
begin
NextState_SISt <= `READ_RD_LOOP;
next_bitCnt <= bitCnt + 1'b1;
end
end
`READ_WT_LO:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `READ_WT_ACK;
next_sdaOut <= 1'b1;
end
end
`READ_WT_ACK:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `CHK_RD_WR;
if (sdaIn == `I2C_NAK)
next_streamSt <= `STREAM_IDLE;
end
end
`WRITE_WT_LO:
begin
if ((scl == 1'b0) && (startStopDetState == `STOP_DET ||
(streamSt == `STREAM_IDLE && startStopDetState == `NULL_DET)))
begin
NextState_SISt <= `WRITE_CLR_ST_STOP;
case (startStopDetState)
`NULL_DET:
next_bitCnt <= bitCnt + 1'b1;
`START_DET: begin
next_streamSt <= `STREAM_IDLE;
next_rxData <= 8'h00;
end
default: ;
endcase
next_streamSt <= `STREAM_IDLE;
next_clearStartStopDet <= 1'b1;
end
else if (scl == 1'b0)
begin
NextState_SISt <= `WRITE_ST_LOOP;
case (startStopDetState)
`NULL_DET:
next_bitCnt <= bitCnt + 1'b1;
`START_DET: begin
next_streamSt <= `STREAM_IDLE;
next_rxData <= 8'h00;
end
default: ;
endcase
end
end
`WRITE_WT_HI:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `WRITE_WT_LO;
next_rxData <= {rxData [6:0], sdaIn};
next_bitCnt <= 3'b000;
end
end
`WRITE_CHK_LOOP_FIN:
begin
if (bitCnt == 3'b111)
begin
NextState_SISt <= `WRITE_CLR_WR;
next_sdaOut <= `I2C_ACK;
case (streamSt)
`STREAM_IDLE: begin
if (rxData[7:1] == i2c_address &&
startStopDetState == `START_DET) begin
if (rxData[0] == 1'b1)
next_streamSt <= `STREAM_READ;
else
next_streamSt <= `STREAM_WRITE_ADDR;
end
else
next_sdaOut <= `I2C_NAK;
end
`STREAM_WRITE_ADDR: begin
next_streamSt <= `STREAM_WRITE_DATA;
next_regAddr <= rxData;
end
`STREAM_WRITE_DATA: begin
next_dataOut <= rxData;
next_writeEn <= 1'b1;
end
default:
next_streamSt <= streamSt;
endcase
end
else
begin
NextState_SISt <= `WRITE_ST_LOOP;
next_bitCnt <= bitCnt + 1'b1;
end
end
`WRITE_LOOP_WT_LO:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `WRITE_CHK_LOOP_FIN;
end
end
`WRITE_ST_LOOP:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `WRITE_LOOP_WT_LO;
next_rxData <= {rxData [6:0], sdaIn};
end
end
`WRITE_WT_LO2:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `CHK_RD_WR;
next_sdaOut <= 1'b1;
end
end
`WRITE_WT_HI2:
begin
next_clearStartStopDet <= 1'b0;
if (scl == 1'b1)
begin
NextState_SISt <= `WRITE_WT_LO2;
end
end
`WRITE_CLR_WR:
begin
if (writeEn == 1'b1)
next_regAddr <= regAddr + 1'b1;
next_writeEn <= 1'b0;
next_clearStartStopDet <= 1'b1;
NextState_SISt <= `WRITE_WT_HI2;
end
`WRITE_CLR_ST_STOP:
begin
next_clearStartStopDet <= 1'b0;
NextState_SISt <= `CHK_RD_WR;
end
endcase
end
// Current State Logic (sequential)
always @ (posedge clk)
begin
if (rst == 1'b1)
CurrState_SISt <= `START;
else
CurrState_SISt <= NextState_SISt;
end
// Registered outputs logic
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
sdaOut <= 1'b1;
writeEn <= 1'b0;
dataOut <= 8'h00;
clearStartStopDet <= 1'b0;
// regAddr <= // Initialization in the reset state or default value required!!
streamSt <= `STREAM_IDLE;
txData <= 8'h00;
rxData <= 8'h00;
bitCnt <= 3'b000;
end
else
begin
sdaOut <= next_sdaOut;
writeEn <= next_writeEn;
dataOut <= next_dataOut;
clearStartStopDet <= next_clearStartStopDet;
regAddr <= next_regAddr;
streamSt <= next_streamSt;
txData <= next_txData;
rxData <= next_rxData;
bitCnt <= next_bitCnt;
end
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module mult_16x16 (
input wire [15:0] A,
input wire [15:0] B,
output wire [31:0] Z
);
assign Z = A * B;
endmodule
module mult_20x18 (
input wire [19:0] A,
input wire [17:0] B,
output wire [37:0] Z
);
assign Z = A * B;
endmodule
module mult_8x8 (
input wire [ 7:0] A,
input wire [ 7:0] B,
output wire [15:0] Z
);
assign Z = A * B;
endmodule
module mult_10x9 (
input wire [ 9:0] A,
input wire [ 8:0] B,
output wire [18:0] Z
);
assign Z = A * B;
endmodule
module mult_8x8_s (
input wire signed [ 7:0] A,
input wire signed [ 7:0] B,
output wire signed [15:0] Z
);
assign Z = A * B;
endmodule
|
`timescale 1 ns / 1 ps
module quick_spi_soft #
(
parameter integer C_S_AXI_ID_WIDTH = 1,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 8,
parameter integer C_S_AXI_AWUSER_WIDTH = 0,
parameter integer C_S_AXI_ARUSER_WIDTH = 0,
parameter integer C_S_AXI_WUSER_WIDTH = 0,
parameter integer C_S_AXI_RUSER_WIDTH = 0,
parameter integer C_S_AXI_BUSER_WIDTH = 0,
parameter integer MEMORY_SIZE = 64,
parameter integer NUMBER_OF_SLAVES = 2
)
(
input wire s_axi_aclk,
input wire s_axi_aresetn,
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [7:0] s_axi_awlen,
input wire [2:0] s_axi_awsize,
input wire [1:0] s_axi_awburst,
input wire s_axi_awlock,
input wire [3:0] s_axi_awcache,
input wire [2:0] s_axi_awprot,
input wire [3:0] s_axi_awqos,
input wire [3:0] s_axi_awregion,
input wire [C_S_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_S_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [1:0] s_axi_bresp,
output wire [C_S_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [7:0] s_axi_arlen,
input wire [2:0] s_axi_arsize,
input wire [1:0] s_axi_arburst,
input wire s_axi_arlock,
input wire [3:0] s_axi_arcache,
input wire [2:0] s_axi_arprot,
input wire [3:0] s_axi_arqos,
input wire [3:0] s_axi_arregion,
input wire [C_S_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_S_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
output reg mosi,
input wire miso,
output reg sclk,
output reg[NUMBER_OF_SLAVES-1:0] ss_n,
output reg interrupt
);
reg [C_S_AXI_ADDR_WIDTH-1:0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1:0] axi_bresp;
reg [C_S_AXI_BUSER_WIDTH-1:0] axi_buser;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1:0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1:0] axi_rdata;
reg [1:0] axi_rresp;
reg axi_rlast;
reg [C_S_AXI_RUSER_WIDTH-1:0] axi_ruser;
reg axi_rvalid;
wire aw_wrap_en;
wire ar_wrap_en;
wire [31:0] aw_wrap_size;
wire [31:0] ar_wrap_size;
reg axi_awv_awr_flag;
reg axi_arv_arr_flag;
reg [7:0] axi_awlen_cntr;
reg [7:0] axi_arlen_cntr;
reg [1:0] axi_arburst;
reg [1:0] axi_awburst;
reg [7:0] axi_arlen;
reg [7:0] axi_awlen;
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32)+ 1;
localparam integer OPT_MEM_ADDR_BITS = 3;
wire [OPT_MEM_ADDR_BITS:0] memory_address;
reg [C_S_AXI_DATA_WIDTH-1:0] outgoing_data;
assign s_axi_awready = axi_awready;
assign s_axi_wready = axi_wready;
assign s_axi_bresp = axi_bresp;
assign s_axi_buser = axi_buser;
assign s_axi_bvalid = axi_bvalid;
assign s_axi_arready = axi_arready;
assign s_axi_rdata = axi_rdata;
assign s_axi_rresp = axi_rresp;
assign s_axi_rlast = axi_rlast;
assign s_axi_ruser = axi_ruser;
assign s_axi_rvalid = axi_rvalid;
assign s_axi_bid = s_axi_awid;
assign s_axi_rid = s_axi_arid;
assign aw_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_awlen));
assign ar_wrap_size = (C_S_AXI_DATA_WIDTH/8 * (axi_arlen));
assign aw_wrap_en = ((axi_awaddr & aw_wrap_size) == aw_wrap_size)? 1'b1: 1'b0;
assign ar_wrap_en = ((axi_araddr & ar_wrap_size) == ar_wrap_size)? 1'b1: 1'b0;
assign s_axi_buser = 0;
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_awready <= 1'b0;
axi_awv_awr_flag <= 1'b0;
end
else begin
if (~axi_awready && s_axi_awvalid && ~axi_awv_awr_flag && ~axi_arv_arr_flag) begin
axi_awready <= 1'b1;
axi_awv_awr_flag <= 1'b1;
end
else if (s_axi_wlast && axi_wready) begin
axi_awv_awr_flag <= 1'b0;
end
else begin
axi_awready <= 1'b0;
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_awaddr <= 0;
axi_awlen_cntr <= 0;
axi_awburst <= 0;
axi_awlen <= 0;
end
else begin
if (~axi_awready && s_axi_awvalid && ~axi_awv_awr_flag) begin
axi_awaddr <= s_axi_awaddr[C_S_AXI_ADDR_WIDTH-1:0];
axi_awburst <= s_axi_awburst;
axi_awlen <= s_axi_awlen;
axi_awlen_cntr <= 0;
end
else if((axi_awlen_cntr <= axi_awlen) && axi_wready && s_axi_wvalid) begin
axi_awlen_cntr <= axi_awlen_cntr + 1;
case (axi_awburst)
2'b00: begin
axi_awaddr <= axi_awaddr;
end
2'b01: begin
axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
2'b10:
if (aw_wrap_en) begin
axi_awaddr <= (axi_awaddr - aw_wrap_size);
end
else begin
axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_awaddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
default: begin
axi_awaddr <= axi_awaddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
end
endcase
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_wready <= 1'b0;
end
else begin
if (~axi_wready && s_axi_wvalid && axi_awv_awr_flag) begin
axi_wready <= 1'b1;
end
//else if (~axi_awv_awr_flag)
else if (s_axi_wlast && axi_wready) begin
axi_wready <= 1'b0;
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else begin
if (axi_awv_awr_flag && axi_wready && s_axi_wvalid && ~axi_bvalid && s_axi_wlast) begin
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0;
end
else begin
if (s_axi_bready && axi_bvalid) begin
axi_bvalid <= 1'b0;
end
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_arready <= 1'b0;
axi_arv_arr_flag <= 1'b0;
end
else begin
if (~axi_arready && s_axi_arvalid && ~axi_awv_awr_flag && ~axi_arv_arr_flag) begin
axi_arready <= 1'b1;
axi_arv_arr_flag <= 1'b1;
end
else if (axi_rvalid && s_axi_rready && axi_arlen_cntr == axi_arlen) begin
axi_arv_arr_flag <= 1'b0;
end
else begin
axi_arready <= 1'b0;
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_araddr <= 0;
axi_arlen_cntr <= 0;
axi_arburst <= 0;
axi_arlen <= 0;
axi_rlast <= 1'b0;
end
else begin
if (~axi_arready && s_axi_arvalid && ~axi_arv_arr_flag) begin
axi_araddr <= s_axi_araddr[C_S_AXI_ADDR_WIDTH - 1:0];
axi_arburst <= s_axi_arburst;
axi_arlen <= s_axi_arlen;
axi_arlen_cntr <= 0;
axi_rlast <= 1'b0;
end
else if((axi_arlen_cntr <= axi_arlen) && axi_rvalid && s_axi_rready) begin
axi_arlen_cntr <= axi_arlen_cntr + 1;
axi_rlast <= 1'b0;
case (axi_arburst)
2'b00: begin
axi_araddr <= axi_araddr;
end
2'b01: begin
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
2'b10:
if (ar_wrap_en) begin
axi_araddr <= (axi_araddr - ar_wrap_size);
end
else begin
axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB] + 1;
axi_araddr[ADDR_LSB-1:0] <= {ADDR_LSB{1'b0}};
end
default: begin
axi_araddr <= axi_araddr[C_S_AXI_ADDR_WIDTH - 1:ADDR_LSB]+1;
end
endcase
end
else if((axi_arlen_cntr == axi_arlen) && ~axi_rlast && axi_arv_arr_flag) begin
axi_rlast <= 1'b1;
end
else if (s_axi_rready) begin
axi_rlast <= 1'b0;
end
end
end
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else begin
if (axi_arv_arr_flag && ~axi_rvalid) begin
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0;
end
else if (axi_rvalid && s_axi_rready) begin
axi_rvalid <= 1'b0;
end
end
end
assign memory_address =
(axi_arv_arr_flag ?
axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] :
(axi_awv_awr_flag? axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]:0));
wire memory_write_enable = axi_wready && s_axi_wvalid;
wire memory_read_enable = axi_arv_arr_flag; //& ~axi_rvalid
reg[15:0] sclk_toggle_count;
reg spi_clock_phase;
localparam SM1_IDLE = 2'b00;
localparam SM1_SELECT_SLAVE = 2'b01;
localparam SM1_TRANSFER_DATA = 2'b10;
reg[1:0] sm1_state;
localparam SM2_WRITE = 2'b00;
localparam SM2_READ = 2'b01;
localparam SM2_WAIT = 2'b10;
localparam SM2_END_DATA_TRANSFER = 2'b11;
reg[1:0] sm2_state;
reg wait_after_read;
reg[15:0] num_toggles_to_wait;
reg [7:0] memory [0:MEMORY_SIZE-1];
wire CPOL = memory[0][0];
wire CPHA = memory[0][1];
wire burst = memory[0][3];
wire read = memory[0][4];
wire[7:0] slave = memory[1];
wire[7:0] num_clocks_to_skip = memory[2];
wire[15:0] outgoing_element_size = {memory[5], memory[4]};
wire[15:0] num_outgoing_elements = {memory[7], memory[6]};
wire[15:0] incoming_element_size = {memory[9], memory[8]};
wire[15:0] num_write_extra_toggles = {memory[11], memory[10]};
wire[15:0] num_read_extra_toggles = {memory[13], memory[12]};
reg[15:0] num_bits_read;
reg[15:0] num_bits_written;
reg[15:0] num_elements_written;
reg[3:0] incoming_byte_bit;
reg[3:0] outgoing_byte_bit;
reg[15:0] num_bytes_read;
reg[15:0] num_bytes_written;
localparam write_buffer_start = 14;
localparam read_buffer_start = 39;
localparam num_initial_axi_transfer_bytes = read_buffer_start;
reg[15:0] extra_toggle_count;
integer num_initial_axi_transfer_bytes_received;
integer i;
integer clock_count;
always @(posedge s_axi_aclk) begin
if (s_axi_aresetn == 1'b0) begin
for (i = 0; i < MEMORY_SIZE - 1; i = i + 1)
memory[i] <= 0;
clock_count <= 0;
num_initial_axi_transfer_bytes_received <= 0;
num_elements_written <= 0;
num_bits_read <= 0;
num_bits_written <= 0;
incoming_byte_bit <= 0;
outgoing_byte_bit <= 0;
num_bytes_read <= 0;
num_bytes_written <= 0;
extra_toggle_count <= 0;
wait_after_read <= 1'b0;
mosi <= 1'bz;
sclk <= 0;
ss_n <= {NUMBER_OF_SLAVES{1'b1}};
sclk_toggle_count <= 0;
spi_clock_phase <= 0;
interrupt <= 1'b0;
sm1_state <= SM1_IDLE;
sm2_state <= SM2_WRITE;
end
else begin
if(memory_write_enable) begin
if (s_axi_wstrb[0])
memory[(memory_address*4) + 0] <= s_axi_wdata[(0*8+7) -: 8];
if (s_axi_wstrb[1])
memory[(memory_address*4) + 1] <= s_axi_wdata[(1*8+7) -: 8];
if (s_axi_wstrb[2])
memory[(memory_address*4) + 2] <= s_axi_wdata[(2*8+7) -: 8];
if (s_axi_wstrb[3])
memory[(memory_address*4) + 3] <= s_axi_wdata[(3*8+7) -: 8];
num_initial_axi_transfer_bytes_received <=
num_initial_axi_transfer_bytes_received + s_axi_wstrb[0] + s_axi_wstrb[1] + s_axi_wstrb[2] + s_axi_wstrb[3];
end
else begin
if(num_initial_axi_transfer_bytes_received == read_buffer_start) begin
if(clock_count == num_clocks_to_skip) begin
clock_count <= 0;
case(sm1_state)
SM1_IDLE: begin
sclk <= CPOL;
spi_clock_phase <= CPHA;
interrupt <= 1'b0;
sm1_state <= SM1_SELECT_SLAVE;
end
SM1_SELECT_SLAVE: begin
ss_n[slave] <= 1'b0;
if(!CPHA) begin
outgoing_byte_bit <= outgoing_byte_bit + 1;
mosi <= memory[write_buffer_start + num_bytes_written][outgoing_byte_bit];
num_bits_written <= num_bits_written + 1;
if(outgoing_element_size == 1) begin
num_elements_written <= 1;
if(num_outgoing_elements == 1) begin
if(!num_write_extra_toggles) begin
if(read)
sm2_state <= SM2_READ;
else
sm2_state <= SM2_END_DATA_TRANSFER;
end
else
sm2_state <= SM2_WAIT;
end
else begin
if(read)
sm2_state <= SM2_READ;
else
sm2_state <= SM2_WRITE;
end
end
else
sm2_state <= SM2_WRITE;
end
sm1_state <= SM1_TRANSFER_DATA;
end
SM1_TRANSFER_DATA: begin
sclk <= ~sclk;
spi_clock_phase <= ~spi_clock_phase;
sclk_toggle_count <= sclk_toggle_count + 1;
case(sm2_state)
SM2_WRITE: begin
if(spi_clock_phase) begin
outgoing_byte_bit <= outgoing_byte_bit + 1;
if(outgoing_byte_bit == 7) begin
num_bytes_written <= num_bytes_written + 1;
outgoing_byte_bit <= 0;
end
mosi <= memory[write_buffer_start + num_bytes_written][outgoing_byte_bit];
num_bits_written <= num_bits_written + 1;
if(num_bits_written == outgoing_element_size - 1) begin
num_elements_written <= num_elements_written + 1;
if(burst) begin
if(num_elements_written == num_outgoing_elements - 1) begin
if(!num_write_extra_toggles)
sm2_state <= SM2_END_DATA_TRANSFER;
else
sm2_state <= SM2_WAIT;
end
else
num_bits_written <= 0;
end
else begin
if(!num_write_extra_toggles)
if(read)
sm2_state <= SM2_READ;
else
sm2_state <= SM2_END_DATA_TRANSFER;
else
sm2_state <= SM2_WAIT;
end
end
end
end
SM2_READ: begin
if(!spi_clock_phase) begin
incoming_byte_bit <= incoming_byte_bit + 1;
if(incoming_byte_bit == 7) begin
num_bytes_read <= num_bytes_read + 1;
incoming_byte_bit <= 0;
end
memory[read_buffer_start + num_bytes_read][incoming_byte_bit] <= miso;
num_bits_read <= num_bits_read + 1;
if(num_bits_read == incoming_element_size - 1) begin
if(!num_read_extra_toggles)
sm2_state <= SM2_END_DATA_TRANSFER;
else begin
wait_after_read <= 1'b1;
sm2_state <= SM2_WAIT;
end
end
end
end
SM2_WAIT: begin
extra_toggle_count <= extra_toggle_count + 1;
if(wait_after_read) begin
if(extra_toggle_count == (num_read_extra_toggles - 1)) begin
extra_toggle_count <= 0;
sm2_state <= SM2_END_DATA_TRANSFER;
end
end
else begin
if(extra_toggle_count == (num_write_extra_toggles - 1)) begin
extra_toggle_count <= 0;
if(read)
sm2_state <= SM2_READ;
else
sm2_state <= SM2_END_DATA_TRANSFER;
end
end
end
SM2_END_DATA_TRANSFER: begin
sclk <= CPOL;
spi_clock_phase <= CPHA;
sclk_toggle_count <= 0;
ss_n[slave] <= 1'b1;
mosi <= 1'bz;
num_bits_read <= 0;
num_bits_written <= 0;
if(num_elements_written == num_outgoing_elements) begin
num_initial_axi_transfer_bytes_received <= 0;
interrupt <= 1'b1;
num_elements_written <= 0;
num_bytes_written <= 0;
sm1_state <= SM1_IDLE;
end
else
sm1_state <= SM1_SELECT_SLAVE;
end
endcase
end
endcase
end
else
clock_count <= clock_count + 1;
end
end
end
end
always @(posedge s_axi_aclk) begin
if (memory_read_enable) begin
outgoing_data[(0*8+7) -: 8] <= memory[(memory_address*4) + 0];
outgoing_data[(1*8+7) -: 8] <= memory[(memory_address*4) + 1];
outgoing_data[(2*8+7) -: 8] <= memory[(memory_address*4) + 2];
outgoing_data[(3*8+7) -: 8] <= memory[(memory_address*4) + 3];
end
end
always @(outgoing_data, axi_rvalid) begin
if (axi_rvalid) begin
axi_rdata <= outgoing_data;
end
else begin
axi_rdata <= 32'h00000000;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4B_LP_V
`define SKY130_FD_SC_LP__AND4B_LP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4b_lp (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4b_lp (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4B_LP_V
|
module main;
string foo;
int error_count;
task check_char(input int idx, input [7:0] val);
if (foo[idx] !== val) begin
$display("FAILED: foo[%0d]==%02h, expecting %02h",
idx, foo[idx], val);
error_count = error_count+1;
end
endtask // check_char
initial begin
// These are the special charasters in strings as defined by
// IEEE Std 1800-2017: 5.9.1 Special characters in strings.
// The string assignment is governed by:
// IEEE Std 1800-2017: 6.16 String data type
foo = "abc";
foo = {foo, "\n\t\\\"\v\f\a\001\002\x03\x04"};
error_count = 0;
check_char(0, 8'h61); // 'a'
check_char(1, 8'h62); // 'b'
check_char(2, 8'h63); // 'c'
check_char(3, 8'h0a); // '\n'
check_char(4, 8'h09); // '\t'
check_char(5, 8'h5c); // '\\'
check_char(6, 8'h22); // '\"'
check_char(7, 8'h0b); // '\v'
check_char(8, 8'h0c); // '\f'
check_char(9, 8'h07); // '\a'
check_char(10, 8'h01); // '\001'
check_char(11, 8'h02); // '\002'
check_char(12, 8'h03); // '\x03'
check_char(13, 8'h04); // '\x04'
if (foo.len() !== 14) begin
$display("FAILED: foo.len() == %0d, should be 14", foo.len());
error_count = error_count+1;
end
if (error_count == 0) $display("PASSED");
end
endmodule // main
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:56:08 04/29/2015
// Design Name:
// Module Name: control_unit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module control_unit(
input [15:0] IR,
output reg [2:0] reg_read_adr1_d,
output reg [2:0] reg_read_adr2_d,
output reg [2:0] reg_write_adr_d,
output reg reg_write_d,
output reg ALU_source2_d,
output reg [7:0] ALU_con_d,
output reg [15:0] offset_register_d,
output reg mem_write_d,
output reg mem_to_reg_d,
output reg branch_d,
output reg [3:0] branch_condition_d,
output reg IEN_d,
output reg IOF_d,
output reg RTI_d
);
always @(*) begin
// 1. Inherent Instructions
casex (IR[15:12])
4'b0000: begin
reg_read_adr1_d = 3'h0;
reg_read_adr2_d = 3'h0;
reg_write_adr_d = 3'h0;
reg_write_d = 0;
ALU_source2_d = 0;
ALU_con_d = 8'h00;
offset_register_d = 16'h0000;
mem_write_d = 0;
mem_to_reg_d = 0;
branch_d = 0;
branch_condition_d = 4'h0;
case (IR[2:0])
// ION
3'b001: begin
IEN_d = 1;
IOF_d = 0;
RTI_d = 0;
end
// IOF
3'b010: begin
IOF_d = 1;
IEN_d = 0;
RTI_d = 0;
end
// RTI
3'b011: begin
RTI_d = 1;
IEN_d = 0;
IOF_d = 0;
end
endcase
end
// 2. Shift Instructions
4'b0001: begin
reg_read_adr1_d = IR[5:3];
reg_read_adr2_d = 3'h0;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
ALU_source2_d = 1;
offset_register_d = {12'h000, IR[9:6]};
mem_write_d = 0;
mem_to_reg_d = 0;
branch_d = 0;
branch_condition_d = 4'h0;
IEN_d = 0;
IOF_d = 0;
RTI_d = 0;
case (IR[11:10])
// LSL
2'b00: ALU_con_d = 8'he3;
// LSR
2'b01: ALU_con_d = 8'he4;
// ASR
2'b10: ALU_con_d = 8'he5;
// CSR
2'b11: ALU_con_d = 8'he6;
endcase
end
// 3. Add/Subtract Register Immediate Instructions
4'b001x: begin
reg_read_adr1_d = IR[5:3];
reg_read_adr2_d = 3'h0;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
ALU_source2_d = 1;
offset_register_d = {10'h000, IR[11:6]};
mem_write_d = 0;
mem_to_reg_d = 0;
branch_d = 0;
branch_condition_d = 4'h0;
IEN_d = 0;
IOF_d = 0;
RTI_d = 0;
case (IR[12])
// Add ADD
0: ALU_con_d = 8'hf7;
// Add SUB
1: ALU_con_d = 8'hf8;
endcase
end
// 4. Move/Compare/Add/Subtract Immediate Instructions
4'b010x: begin
reg_read_adr2_d = 3'h0;
ALU_source2_d = 1;
offset_register_d = {8'h00, IR[7:0]};
mem_write_d = 0;
mem_to_reg_d = 0;
branch_d = 0;
branch_condition_d = 4'h0;
IEN_d = 0;
IOF_d = 0;
RTI_d = 0;
case (IR[12:11])
// Move Imm MOV
2'b00: begin
reg_read_adr1_d = 3'h0;
ALU_con_d = 8'hcf;
reg_write_adr_d = IR[10:8];
reg_write_d = 1;
end
// Move Imm CMP
2'b01: begin
reg_read_adr1_d = IR[10:8];
ALU_con_d = 8'hf8;
reg_write_adr_d = 3'h0;
reg_write_d = 0;
end
// Move Imm ADD
2'b10: begin
reg_read_adr1_d = IR[10:8];
ALU_con_d = 8'hf7;
reg_write_adr_d = IR[10:8];
reg_write_d = 1;
end
// Move Imm SUB
2'b11: begin
reg_read_adr1_d = IR[10:8];
ALU_con_d = 8'hf8;
reg_write_adr_d = IR[10:8];
reg_write_d = 1;
end
endcase
end
// 5. ALU Instructions
4'b011x: begin
reg_read_adr1_d = 3'h0;
reg_read_adr2_d = 3'h0;
ALU_source2_d = 0;
offset_register_d = 16'h0000;
mem_write_d = 0;
mem_to_reg_d = 0;
branch_d = 0;
branch_condition_d = 4'h0;
IEN_d = 0;
IOF_d = 0;
RTI_d = 0;
case (IR[12:9])
// AND
4'h0: begin
ALU_con_d = 8'hc0;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
end
// OR
4'h1: begin
ALU_con_d = 8'hc1;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
end
// XOR
4'h2: begin
ALU_con_d = 8'hc2;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
end
// LSL
4'h3: begin
ALU_con_d = 8'he3;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
end
// LSR
4'h4: begin
ALU_con_d = 8'he4;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
end
// ASR
4'h5: begin
ALU_con_d = 8'he5;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
end
// CSR
4'h6: begin
ALU_con_d = 8'he6;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
end
// ADD
4'h7: begin
ALU_con_d = 8'hf7;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
end
// SUB
4'h8: begin
ALU_con_d = 8'hf8;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
end
// NEG
4'h9: begin
ALU_con_d = 8'hc9;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
end
// NOT
4'ha: begin
ALU_con_d = 8'hca;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
end
// CMP
4'hb: begin
ALU_con_d = 8'hf8;
reg_write_adr_d = 3'h0;
reg_write_d = 0;
end
// TST
4'hc: begin
ALU_con_d = 8'hf0;
reg_write_adr_d = 3'h0;
reg_write_d = 0;
end
endcase
end
// 6. Load/Store with Register Offset Instructions
4'b100x: begin
// LD/ST Reg LD
reg_read_adr1_d = IR[5:3];
reg_read_adr2_d = IR[8:6];
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
ALU_source2_d = 0;
ALU_con_d = 8'h07;
offset_register_d = 16'h0000;
mem_write_d = 0;
mem_to_reg_d = 1;
branch_d = 0;
branch_condition_d = 4'h0;
IEN_d = 0;
IOF_d = 0;
RTI_d = 0;
end
// 7. Load/Store with Immediate Offset Instructions
4'b101x: begin
reg_read_adr1_d = IR[5:3];
ALU_source2_d = 1;
ALU_con_d = 8'h07;
offset_register_d = {10'h000, IR[11:6]};
branch_d = 0;
branch_condition_d = 4'h0;
IEN_d = 0;
IOF_d = 0;
RTI_d = 0;
case (IR[12])
// LD/ST Imm LD
0: begin
reg_read_adr2_d = 3'h0;
reg_write_adr_d = IR[2:0];
reg_write_d = 1;
mem_write_d = 0;
mem_to_reg_d = 1;
end
// LD/ST Imm STR
1: begin
reg_read_adr2_d = IR[2:0];
reg_write_adr_d = 3'h0;
reg_write_d = 0;
mem_write_d = 1;
mem_to_reg_d = 0;
end
endcase
end
// 8. Conditional Branch Instructions
4'b110x: begin
reg_read_adr1_d = 3'h0;
reg_read_adr2_d = 3'h0;
reg_write_adr_d = 3'h0;
reg_write_d = 0;
ALU_source2_d = 1;
ALU_con_d = 8'h0f;
offset_register_d = {7'h00, IR[8:0]};
mem_write_d = 0;
mem_to_reg_d = 0;
branch_d = 1;
IEN_d = 0;
IOF_d = 0;
RTI_d = 0;
case (IR[12:9])
// BEQ
4'h0: branch_condition_d = 4'h0;
// BNE
4'h1: branch_condition_d = 4'h1;
// BCS
4'h2: branch_condition_d = 4'h2;
// BCC
4'h3: branch_condition_d = 4'h3;
// BMI
4'h4: branch_condition_d = 4'h4;
// BPL
4'h5: branch_condition_d = 4'h5;
// BVS
4'h6: branch_condition_d = 4'h6;
// BVC
4'h7: branch_condition_d = 4'h7;
// BHI
4'h8: branch_condition_d = 4'h8;
// BLS
4'h9: branch_condition_d = 4'h9;
// BGE
4'ha: branch_condition_d = 4'ha;
// BLT
4'hb: branch_condition_d = 4'hb;
// BGT
4'hc: branch_condition_d = 4'hc;
// BLE
4'hd: branch_condition_d = 4'hd;
endcase
end
// 9. Unconditional Branch Instruction
4'b1110: begin
// Uncond Branch OP
reg_read_adr1_d = 3'h0;
reg_read_adr2_d = 3'h0;
reg_write_adr_d = 3'h0;
reg_write_d = 0;
ALU_source2_d = 1;
ALU_con_d = 8'h0f;
offset_register_d = {4'h0, IR[11:0]};
mem_write_d = 0;
mem_to_reg_d = 0;
branch_d = 1;
branch_condition_d = 4'hf;
IEN_d = 0;
IOF_d = 0;
RTI_d = 0;
end
// 10. Move Long Immediate
4'b1111: begin
// Move Long OP
reg_read_adr1_d = 3'h0;
reg_read_adr2_d = 3'h0;
reg_write_adr_d = 3'h0;
reg_write_d = 1;
ALU_source2_d = 1;
ALU_con_d = 8'h0f;
offset_register_d = {4'h0, IR[11:0]};
mem_write_d = 0;
mem_to_reg_d = 0;
branch_d = 0;
branch_condition_d = 4'h0;
IEN_d = 0;
IOF_d = 0;
RTI_d = 0;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16.03.2017 13:00:32
// Design Name:
// Module Name: arb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module arb(
input clk25,
input uartrx,
output[11:0] outA,
output[11:0] outB
);
reg[63:0] freqA = 1000;
reg[63:0] freqB = 1000;
wire rxready;
wire[7:0] recv_data;
wire rxidle;
async_receiver uart(clk25, uartrx, rxready, recv_data, rxidle);
reg chan = 1;
reg[15:0] write_i = 0;
reg[7:0] msb = 0;
reg[1:0] rxstate = 0;
reg[31:0] phase_accA = 0;
reg[31:0] phase_accB = 0;
reg[15:0] writedata = 0;
reg writeen = 0;
reg[13:0] options = 0;
reg burst_modeA = 0;
reg burstA = 0;
reg burst_modeB = 0;
reg burstB = 0;
wire frame_ch1 = (msb[7:6] == 1);
wire frame_ch2 = (msb[7:6] == 2);
wire frame_opt = (msb[7:6] == 3);
wire[13:0] header_payload = {msb[5:0],recv_data};
wire[15:0] phaseoutA = phase_accA[31:16];
wire[15:0] phaseoutB = phase_accB[31:16];
always @(posedge clk25) begin
if(rxready) begin
msb <= recv_data;
rxstate = (rxstate==0)?1:(rxstate==1)?2:1;
if(rxstate == 2) begin
writedata <= {msb, recv_data};
writeen = !(frame_ch1 || frame_ch2);
freqA = frame_ch1 ? header_payload : freqA;
freqB = frame_ch2 ? header_payload : freqB;
options = frame_opt ? header_payload : options;
write_i = (writedata[15:14] != 0) ? 0 : write_i + 1;
chan = (frame_ch1) ? 0 : (frame_ch2) ? 1 : chan;
end else begin
options = 0;
writeen = 0;
end
end else begin
options = 0;
if(rxidle)
rxstate = 0;
end
burst_modeA = burst_modeA ? (options[1]==0) : (options[0]==1);
burstA <= burstA ? (phaseoutA < 65535) : (options[2]);
phase_accA = (burst_modeA && !burstA) ? 0 : phase_accA + ((freqA*1717987)/10000);
burst_modeB = burst_modeB ? (options[4]==0) : (options[3]==1);
burstB <= burstB ? (phaseoutB < 65535) : (options[5]);
phase_accB = (burst_modeB && !burstB) ? 0 : phase_accB + ((freqB*1717987)/10000);
end
blk_mem_gen_arb ddsram1(.clka(clk25), .ena(~chan), .wea(writeen), .addra(write_i), .dina(writedata[11:0]), .clkb(clk25), .enb(1'b1), .addrb(phaseoutA), .doutb(outA));
blk_mem_gen_arb ddsram2(.clka(clk25), .ena(chan), .wea(writeen), .addra(write_i), .dina(writedata[11:0]), .clkb(clk25), .enb(1'b1), .addrb(phaseoutB), .doutb(outB));
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:49:38 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n1652, Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP,
ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1,
left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2,
SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM,
SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n463, n464, n465, n466, n467,
n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478,
n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489,
n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, n500,
n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544,
n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599,
n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610,
n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621,
n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n769, n770, n771, n772, n773, n774, n775, n776,
n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787,
n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798,
n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809,
n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820,
n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842,
n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n866, n867, n868, n869, n870, n871, DP_OP_15J59_123_4652_n8,
DP_OP_15J59_123_4652_n7, DP_OP_15J59_123_4652_n6,
DP_OP_15J59_123_4652_n5, DP_OP_15J59_123_4652_n4, intadd_66_B_14_,
intadd_66_B_13_, intadd_66_B_12_, intadd_66_B_11_, intadd_66_B_10_,
intadd_66_B_9_, intadd_66_B_8_, intadd_66_B_7_, intadd_66_B_6_,
intadd_66_B_5_, intadd_66_B_4_, intadd_66_B_3_, intadd_66_B_2_,
intadd_66_B_1_, intadd_66_B_0_, intadd_66_CI, intadd_66_SUM_14_,
intadd_66_SUM_13_, intadd_66_SUM_12_, intadd_66_SUM_11_,
intadd_66_SUM_10_, intadd_66_SUM_9_, intadd_66_SUM_8_,
intadd_66_SUM_7_, intadd_66_SUM_6_, intadd_66_SUM_5_,
intadd_66_SUM_4_, intadd_66_SUM_3_, intadd_66_SUM_2_,
intadd_66_SUM_1_, intadd_66_SUM_0_, intadd_66_n15, intadd_66_n14,
intadd_66_n13, intadd_66_n12, intadd_66_n11, intadd_66_n10,
intadd_66_n9, intadd_66_n8, intadd_66_n7, intadd_66_n6, intadd_66_n5,
intadd_66_n4, intadd_66_n3, intadd_66_n2, intadd_66_n1,
intadd_67_A_4_, intadd_67_A_3_, intadd_67_B_4_, intadd_67_B_2_,
intadd_67_B_1_, intadd_67_B_0_, intadd_67_CI, intadd_67_SUM_4_,
intadd_67_SUM_3_, intadd_67_SUM_2_, intadd_67_SUM_1_,
intadd_67_SUM_0_, intadd_67_n5, intadd_67_n4, intadd_67_n3,
intadd_67_n2, intadd_67_n1, n872, n873, n874, n875, n876, n877, n878,
n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889,
n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900,
n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911,
n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922,
n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933,
n934, n935, n936, n937, n938, n939, n940, n941, n942, n943, n944,
n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955,
n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966,
n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999,
n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009,
n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019,
n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029,
n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039,
n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049,
n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059,
n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069,
n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079,
n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089,
n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099,
n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109,
n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119,
n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129,
n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159,
n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169,
n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239,
n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413,
n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423,
n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433,
n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443,
n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453,
n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463,
n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473,
n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483,
n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493,
n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503,
n1504, n1505, n1506, n1507, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584,
n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594,
n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604,
n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1651;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:2] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1620), .QN(
n889) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1619), .Q(
intAS) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1620),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n1618),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n1636),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n1623),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n1621), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n1617), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n1637), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n1634), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n1647), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n1644), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1634), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1639), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n1631), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n1633), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n1635), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n741), .CK(clk), .RN(n1624), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1637), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1640), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n1641), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n1621), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n1645), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n1647), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n1631), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n1633), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n916), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1626), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n1625), .QN(n897)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n1629), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n1628), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n1627), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n970), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n1630), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n916), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n1626), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n1625), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n1627), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n970), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n916), .Q(
DMP_SFG[2]), .QN(n1591) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n1630), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n916), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n1627), .Q(
DMP_SFG[3]), .QN(n1600) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1626), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n1625), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n1630), .Q(
DMP_SFG[4]), .QN(n1598) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1627), .Q(
DMP_SFG[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n1630), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n700), .CK(clk), .RN(n1626), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1625), .Q(
DMP_SFG[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n697), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n1626), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n1625), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n1626), .Q(
DMP_SFG[8]), .QN(n1546) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n1625), .Q(
DMP_SFG[9]), .QN(n1545) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n1627), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n970), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n1629), .Q(
DMP_SFG[10]), .QN(n1553) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n1630), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n916), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n1630), .Q(
DMP_SFG[11]), .QN(n1552) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n1628), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n1627), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n1628), .Q(
DMP_SFG[12]), .QN(n1559) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n970), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n1630), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n1627), .Q(
DMP_SFG[13]), .QN(n1558) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n916), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n1626), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n970), .Q(
DMP_SFG[14]), .QN(n1562) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n1625), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1629), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1627), .Q(
DMP_SFG[15]), .QN(n1580) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1626), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1625), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n1630), .Q(
DMP_SFG[16]), .QN(n1579) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1629), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n1629), .Q(
DMP_SFG[17]), .QN(n1593) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n1627), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n1630), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n1628), .Q(
DMP_SFG[18]), .QN(n1592) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n1626), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n1625), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n1621), .Q(
DMP_SFG[19]), .QN(n1602) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n1631), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n1633), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n1645), .Q(
DMP_SFG[20]), .QN(n1601) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n1635), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n1624), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1637), .Q(
DMP_SFG[21]), .QN(n1613) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n1617), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1637), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n1640), .Q(
DMP_SFG[22]), .QN(n1612) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1640), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1641), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1643), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n1646), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n1642), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1632), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n1634), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n1636), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n1644), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n1623), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n1638), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n1639), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n1643), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n1646), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n1647), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n1617), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n1631), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n1633), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n1635), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n1624), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n1637), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n1640), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n1641), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n1621), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n1645), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n1647), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n1634), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n1636), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n1618), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n1644), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n1623), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n1638), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1639), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1623), .QN(
n892) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1638), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1639), .QN(
n893) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1618), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n1635), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n1624), .QN(
n895) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n1617), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n1637), .QN(
n880) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n1640), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1641), .QN(
n894) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1637), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1640), .QN(
n878) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n1641), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n1621), .QN(
n896) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n1645), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n1632), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1634), .QN(
n891) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n1636), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1644), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1623),
.QN(n879) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1638), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n1639),
.QN(n898) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1643), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n1646),
.QN(n877) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n1642), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n581), .CK(clk), .RN(n1632),
.QN(n899) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n1624), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n1621), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n576), .CK(clk), .RN(n1638), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n574), .CK(clk), .RN(n1632), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n1638), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n1617), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n1631), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n1641), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n1618), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n1644), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n1641), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n1647), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .RN(n1640), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1633), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n550), .CK(clk), .RN(n1639), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n1638), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n1640), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n1636), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n1645), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1637), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n1637), .Q(
LZD_output_NRM2_EW[3]), .QN(n1563) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n1647), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1617), .Q(
LZD_output_NRM2_EW[2]), .QN(n1560) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n1635), .Q(
LZD_output_NRM2_EW[1]), .QN(n1554) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1624), .Q(
LZD_output_NRM2_EW[4]), .QN(n1564) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n1639), .Q(
DmP_mant_SFG_SWR[0]), .QN(n955) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[1]), .QN(n956) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n1646), .Q(
DmP_mant_SFG_SWR[2]), .QN(n958) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n1642), .Q(
DmP_mant_SFG_SWR[3]), .QN(n959) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n1632), .Q(
DmP_mant_SFG_SWR[4]), .QN(n960) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n483), .CK(clk), .RN(n1634), .Q(
DmP_mant_SFG_SWR[5]), .QN(n961) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1636), .Q(
DmP_mant_SFG_SWR[6]), .QN(n965) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n1618), .Q(
DmP_mant_SFG_SWR[7]), .QN(n966) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n479), .CK(clk), .RN(n1638), .Q(
DmP_mant_SFG_SWR[9]), .QN(n963) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n1641), .Q(
DmP_mant_SFG_SWR[16]), .QN(n962) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n1647), .Q(
DmP_mant_SFG_SWR[17]), .QN(n948) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n1631), .Q(
DmP_mant_SFG_SWR[18]), .QN(n949) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n1633), .Q(
DmP_mant_SFG_SWR[19]), .QN(n950) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n1635), .Q(
DmP_mant_SFG_SWR[20]), .QN(n951) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n1624), .Q(
DmP_mant_SFG_SWR[21]), .QN(n953) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n1617), .Q(
DmP_mant_SFG_SWR[22]), .QN(n954) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n1636), .Q(
DmP_mant_SFG_SWR[23]), .QN(n1597) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n1634), .Q(
DmP_mant_SFG_SWR[24]), .QN(n1610) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n1618), .Q(
DmP_mant_SFG_SWR[25]), .QN(n1614) );
CMPR32X2TS intadd_66_U16 ( .A(n1546), .B(intadd_66_B_0_), .C(intadd_66_CI),
.CO(intadd_66_n15), .S(intadd_66_SUM_0_) );
CMPR32X2TS intadd_66_U15 ( .A(n1545), .B(intadd_66_B_1_), .C(intadd_66_n15),
.CO(intadd_66_n14), .S(intadd_66_SUM_1_) );
CMPR32X2TS intadd_66_U14 ( .A(n1553), .B(intadd_66_B_2_), .C(intadd_66_n14),
.CO(intadd_66_n13), .S(intadd_66_SUM_2_) );
CMPR32X2TS intadd_66_U13 ( .A(n1552), .B(intadd_66_B_3_), .C(intadd_66_n13),
.CO(intadd_66_n12), .S(intadd_66_SUM_3_) );
CMPR32X2TS intadd_66_U12 ( .A(n1559), .B(intadd_66_B_4_), .C(intadd_66_n12),
.CO(intadd_66_n11), .S(intadd_66_SUM_4_) );
CMPR32X2TS intadd_66_U11 ( .A(n1558), .B(intadd_66_B_5_), .C(intadd_66_n11),
.CO(intadd_66_n10), .S(intadd_66_SUM_5_) );
CMPR32X2TS intadd_66_U10 ( .A(n1562), .B(intadd_66_B_6_), .C(intadd_66_n10),
.CO(intadd_66_n9), .S(intadd_66_SUM_6_) );
CMPR32X2TS intadd_66_U9 ( .A(n1580), .B(intadd_66_B_7_), .C(intadd_66_n9),
.CO(intadd_66_n8), .S(intadd_66_SUM_7_) );
CMPR32X2TS intadd_66_U8 ( .A(n1579), .B(intadd_66_B_8_), .C(intadd_66_n8),
.CO(intadd_66_n7), .S(intadd_66_SUM_8_) );
CMPR32X2TS intadd_66_U7 ( .A(n1593), .B(intadd_66_B_9_), .C(intadd_66_n7),
.CO(intadd_66_n6), .S(intadd_66_SUM_9_) );
CMPR32X2TS intadd_66_U6 ( .A(n1592), .B(intadd_66_B_10_), .C(intadd_66_n6),
.CO(intadd_66_n5), .S(intadd_66_SUM_10_) );
CMPR32X2TS intadd_66_U5 ( .A(n1602), .B(intadd_66_B_11_), .C(intadd_66_n5),
.CO(intadd_66_n4), .S(intadd_66_SUM_11_) );
CMPR32X2TS intadd_66_U4 ( .A(n1601), .B(intadd_66_B_12_), .C(intadd_66_n4),
.CO(intadd_66_n3), .S(intadd_66_SUM_12_) );
CMPR32X2TS intadd_66_U3 ( .A(n1613), .B(intadd_66_B_13_), .C(intadd_66_n3),
.CO(intadd_66_n2), .S(intadd_66_SUM_13_) );
CMPR32X2TS intadd_66_U2 ( .A(n1612), .B(intadd_66_B_14_), .C(intadd_66_n2),
.CO(intadd_66_n1), .S(intadd_66_SUM_14_) );
CMPR32X2TS intadd_67_U6 ( .A(n1591), .B(intadd_67_B_0_), .C(intadd_67_CI),
.CO(intadd_67_n5), .S(intadd_67_SUM_0_) );
CMPR32X2TS intadd_67_U5 ( .A(n1600), .B(intadd_67_B_1_), .C(intadd_67_n5),
.CO(intadd_67_n4), .S(intadd_67_SUM_1_) );
CMPR32X2TS intadd_67_U4 ( .A(n1598), .B(intadd_67_B_2_), .C(intadd_67_n4),
.CO(intadd_67_n3), .S(intadd_67_SUM_2_) );
CMPR32X2TS intadd_67_U3 ( .A(intadd_67_A_3_), .B(n921), .C(intadd_67_n3),
.CO(intadd_67_n2), .S(intadd_67_SUM_3_) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n781), .CK(clk), .RN(n1638), .Q(
Data_array_SWR[10]), .QN(n1609) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n1624), .Q(
DmP_EXP_EWSW[25]), .QN(n1608) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n1628), .Q(
DMP_EXP_EWSW[26]), .QN(n1607) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n1623), .Q(
DmP_EXP_EWSW[26]), .QN(n1603) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n971), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1599) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n1629), .Q(
DMP_EXP_EWSW[25]), .QN(n1595) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n1621), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1594) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n1616), .Q(
intDY_EWSW[0]), .QN(n1582) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n1647), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1578) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n972), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1577) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1621),
.Q(intDY_EWSW[27]), .QN(n1576) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1643),
.Q(intDY_EWSW[23]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n1639),
.Q(intDY_EWSW[28]), .QN(n1575) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n1620), .Q(
intDY_EWSW[7]), .QN(n1574) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n1616), .Q(
intDY_EWSW[4]), .QN(n1571) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n1622), .Q(
intDY_EWSW[2]), .QN(n1570) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n1619), .Q(
intDY_EWSW[9]), .QN(n1567) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n1640), .Q(
intDY_EWSW[6]), .QN(n1566) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n1620), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1561) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n1620),
.Q(intDX_EWSW[28]), .QN(n1556) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n1645), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1551) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n1644), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1549) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n1640), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1548) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n1636), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1543) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1619), .Q(
shift_value_SHT2_EWR[3]), .QN(n1542) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n1643), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1541) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n1633), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1540) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n1625),
.Q(intDX_EWSW[26]), .QN(n1539) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n1645), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1537) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n1646), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1536) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n1641), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1535) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n1625), .Q(
DMP_EXP_EWSW[24]), .QN(n1534) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n1640), .Q(
DmP_EXP_EWSW[24]), .QN(n1533) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n1622),
.Q(intDY_EWSW[19]), .QN(n1531) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n1616),
.Q(intDY_EWSW[16]), .QN(n1529) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n1617), .Q(
intDY_EWSW[5]), .QN(n1527) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n1635), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1525) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n1642), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1524) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n1635), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1522) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n532), .CK(clk), .RN(n1644), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1521) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n1646), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1519) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n1617), .Q(
Raw_mant_NRM_SWR[15]), .QN(n1518) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n1619),
.Q(intDY_EWSW[24]), .QN(n1515) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n1618), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1513) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n1637), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1511) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1622),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n559), .CK(clk), .RN(n1618), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n1631), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n505), .CK(clk), .RN(n1642), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n504), .CK(clk), .RN(n1640), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n503), .CK(clk), .RN(n1635), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n1645), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n501), .CK(clk), .RN(n1644), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n500), .CK(clk), .RN(n1638), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n1639), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n498), .CK(clk), .RN(n1623), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n497), .CK(clk), .RN(n1638), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n496), .CK(clk), .RN(n1639), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n495), .CK(clk), .RN(n1643), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n1646), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n493), .CK(clk), .RN(n1642), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n492), .CK(clk), .RN(n1632), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n491), .CK(clk), .RN(n1634), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n490), .CK(clk), .RN(n1636), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n489), .CK(clk), .RN(n1639), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n1644), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n510), .CK(clk), .RN(n1623), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n509), .CK(clk), .RN(n1642), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n508), .CK(clk), .RN(n1623), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n507), .CK(clk), .RN(n1624), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n506), .CK(clk), .RN(n1632), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n1633), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1623), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1638), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n1639), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n757), .CK(clk), .RN(n1623), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n756), .CK(clk), .RN(n1643), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n755), .CK(clk), .RN(n1646), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n511), .CK(clk), .RN(n1633), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n1642), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1632), .Q(
final_result_ieee[31]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1616), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1526) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n1635), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1590) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n1619), .Q(
intDY_EWSW[8]), .QN(n1586) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n1616),
.Q(intDY_EWSW[22]), .QN(n1530) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n1616),
.Q(intDY_EWSW[30]), .QN(n1588) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n1622),
.Q(intDY_EWSW[29]), .QN(n1532) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1622),
.Q(intDY_EWSW[26]), .QN(n1587) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1619),
.Q(intDY_EWSW[25]), .QN(n1581) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n1620),
.Q(intDY_EWSW[21]), .QN(n1569) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n1619),
.Q(intDY_EWSW[18]), .QN(n1589) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n915), .Q(
intDY_EWSW[17]), .QN(n1584) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n1622),
.Q(intDY_EWSW[15]), .QN(n1583) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n1619),
.Q(intDY_EWSW[14]), .QN(n1528) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n1641),
.Q(intDY_EWSW[13]), .QN(n1568) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n1636),
.Q(intDY_EWSW[12]), .QN(n1572) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n1616), .Q(
intDY_EWSW[3]), .QN(n1565) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n1646), .Q(
intDY_EWSW[1]), .QN(n1585) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n1622),
.Q(intDX_EWSW[25]), .QN(n1538) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n1620),
.Q(intDX_EWSW[24]), .QN(n1606) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n1621), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1514) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1620),
.Q(intDX_EWSW[16]), .QN(n1555) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n1623), .Q(
intDX_EWSW[7]), .QN(n1523) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n916), .Q(
intDX_EWSW[6]), .QN(n1550) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1616), .Q(
intDX_EWSW[5]), .QN(n1544) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n1622), .Q(
intDX_EWSW[4]), .QN(n1520) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n1620), .Q(
shift_value_SHT2_EWR[4]), .QN(n1547) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n794), .CK(clk), .RN(n1628), .Q(
Data_array_SWR[23]), .QN(n1596) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n785), .CK(clk), .RN(n1634), .Q(
Data_array_SWR[14]), .QN(n1605) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n783), .CK(clk), .RN(n1633), .Q(
Data_array_SWR[12]), .QN(n1604) );
DFFSX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n957), .CK(clk), .SN(n972), .Q(
n1649), .QN(n1648) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n1620), .Q(
n1516), .QN(n1611) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n1622), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n1620),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n1637),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1618),
.Q(intDX_EWSW[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n793), .CK(clk), .RN(n1620), .Q(
Data_array_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n796), .CK(clk), .RN(n1619), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n1641), .Q(
Data_array_SWR[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n1619), .Q(
intDX_EWSW[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n1637), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n1616),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n1640),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n1620), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n1644), .Q(
intDX_EWSW[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n1638), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n770), .CK(clk), .RN(n1638), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1647), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n784), .CK(clk), .RN(n1640), .Q(
Data_array_SWR[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n1619), .Q(
intDX_EWSW[0]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n1617), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n916), .Q(
intDX_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n1620),
.Q(intDX_EWSW[29]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n915), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n779), .CK(clk), .RN(n1622), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n790), .CK(clk), .RN(n1623), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n787), .CK(clk), .RN(n1624), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n1642), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n1643), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n777), .CK(clk), .RN(n1619), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1641), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n775), .CK(clk), .RN(n1638), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n776), .CK(clk), .RN(n1622), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n1626), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n970), .Q(
DMP_SFG[1]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1647),
.Q(intDX_EWSW[31]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n1632), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1517) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n1623),
.Q(intDY_EWSW[10]), .QN(n883) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n1630), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n1621), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n474), .CK(clk), .RN(n1645), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n1640), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n1637), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n477), .CK(clk), .RN(n1641), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n478), .CK(clk), .RN(n1623), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1622),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1627), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n1617), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n1631), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n1633), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n1616),
.Q(intDY_EWSW[11]), .QN(n1557) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n915), .Q(
intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n915), .Q(
intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1620),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1622),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n1642),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n1616), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n1622),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n1637),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n1619),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n780), .CK(clk), .RN(n1639), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n782), .CK(clk), .RN(n1646), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n792), .CK(clk), .RN(n916), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n789), .CK(clk), .RN(n1632), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n788), .CK(clk), .RN(n1631), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n791), .CK(clk), .RN(n1645), .Q(
Data_array_SWR[20]) );
DFFRX2TS inst_ShiftRegister_Q_reg_4_ ( .D(n867), .CK(clk), .RN(n1616), .Q(
n1652), .QN(n1651) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n1634), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1512) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1637), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1618), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1624), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n1642), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1643), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1632), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n1647), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n1634), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n1639), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n1636), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n1631), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n1616),
.Q(intDY_EWSW[20]), .QN(n1573) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n480), .CK(clk), .RN(n1644), .Q(
DmP_mant_SFG_SWR[8]), .QN(n964) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n1635), .Q(
DmP_EXP_EWSW[23]), .QN(n952) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n1631), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n774), .CK(clk), .RN(n916), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1616), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n1622), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n771), .CK(clk), .RN(n1618), .Q(
Data_array_SWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n1643), .Q(
DmP_EXP_EWSW[27]) );
ADDFX1TS DP_OP_15J59_123_4652_U7 ( .A(n1560), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J59_123_4652_n7), .CO(DP_OP_15J59_123_4652_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J59_123_4652_U6 ( .A(n1563), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J59_123_4652_n6), .CO(DP_OP_15J59_123_4652_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J59_123_4652_U5 ( .A(n1564), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J59_123_4652_n5), .CO(DP_OP_15J59_123_4652_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n549), .CK(clk), .RN(n1646), .Q(
OP_FLAG_SFG), .QN(n967) );
CMPR32X2TS DP_OP_15J59_123_4652_U8 ( .A(n1554), .B(DMP_exp_NRM2_EW[1]), .C(
DP_OP_15J59_123_4652_n8), .CO(DP_OP_15J59_123_4652_n7), .S(
exp_rslt_NRM2_EW1[1]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n1639), .Q(
Shift_reg_FLAGS_7[1]), .QN(n875) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n1645), .Q(
Shift_reg_FLAGS_7_6), .QN(n968) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n1641), .Q(
Shift_reg_FLAGS_7[0]) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n1616), .Q(
left_right_SHT2), .QN(n876) );
CMPR32X2TS intadd_67_U2 ( .A(intadd_67_A_4_), .B(intadd_67_B_4_), .C(
intadd_67_n2), .CO(intadd_67_n1), .S(intadd_67_SUM_4_) );
AOI222X1TS U897 ( .A0(n1438), .A1(left_right_SHT2), .B0(Data_array_SWR[7]),
.B1(n938), .C0(n1437), .C1(n1454), .Y(n1498) );
AOI222X4TS U898 ( .A0(Data_array_SWR[24]), .A1(n1432), .B0(
Data_array_SWR[20]), .B1(n1447), .C0(Data_array_SWR[16]), .C1(n1446),
.Y(n1475) );
AOI222X4TS U899 ( .A0(Data_array_SWR[21]), .A1(n1447), .B0(
Data_array_SWR[17]), .B1(n1446), .C0(Data_array_SWR[25]), .C1(n1432),
.Y(n1469) );
AOI222X4TS U900 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n909), .B0(n911), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1255), .C1(DmP_mant_SHT1_SW[17]), .Y(n1235) );
NOR2X4TS U901 ( .A(n1206), .B(n1265), .Y(n1207) );
AOI211X2TS U902 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1173), .B0(n1306), .C0(
n1172), .Y(n1188) );
OAI222X1TS U903 ( .A0(n1604), .A1(n1349), .B0(n944), .B1(n1339), .C0(n908),
.C1(n1338), .Y(n783) );
OAI222X1TS U904 ( .A0(n1609), .A1(n1349), .B0(n944), .B1(n1340), .C0(n908),
.C1(n1339), .Y(n781) );
OAI222X1TS U905 ( .A0(n1596), .A1(n1349), .B0(n944), .B1(n1329), .C0(n908),
.C1(n1328), .Y(n794) );
AOI211X1TS U906 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n1390), .B0(n1333), .C0(
n1266), .Y(n1327) );
NAND3X1TS U907 ( .A(n1158), .B(n1300), .C(Raw_mant_NRM_SWR[1]), .Y(n1294) );
OAI211X1TS U908 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1164), .B0(n1299), .C0(
n1549), .Y(n1165) );
OAI21X1TS U909 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1156), .Y(n1157) );
BUFX3TS U910 ( .A(n1048), .Y(n872) );
INVX3TS U911 ( .A(n1349), .Y(n1186) );
INVX3TS U912 ( .A(n906), .Y(n874) );
INVX1TS U913 ( .A(DMP_SFG[5]), .Y(intadd_67_A_3_) );
INVX1TS U914 ( .A(DMP_SFG[6]), .Y(intadd_67_A_4_) );
INVX1TS U915 ( .A(LZD_output_NRM2_EW[0]), .Y(n1288) );
OAI222X1TS U916 ( .A0(n1349), .A1(n1605), .B0(n944), .B1(n1338), .C0(n908),
.C1(n1332), .Y(n785) );
INVX3TS U917 ( .A(n1185), .Y(n944) );
BUFX3TS U918 ( .A(n1204), .Y(n908) );
CLKBUFX3TS U919 ( .A(n1191), .Y(n1270) );
AND2X2TS U920 ( .A(n1187), .B(n1349), .Y(n1185) );
AOI222X1TS U921 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n909), .B0(n911), .B1(n930),
.C0(n1255), .C1(n922), .Y(n1262) );
AOI222X1TS U922 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n910), .B0(n912), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1255), .C1(DmP_mant_SHT1_SW[18]), .Y(n1251) );
AOI222X1TS U923 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n910), .B0(n911), .B1(n928),
.C0(n1333), .C1(n924), .Y(n1246) );
AOI222X1TS U924 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n910), .B0(n912), .B1(
DmP_mant_SHT1_SW[19]), .C0(n1255), .C1(DmP_mant_SHT1_SW[20]), .Y(n1247) );
INVX3TS U925 ( .A(n1336), .Y(n910) );
NAND3X1TS U926 ( .A(n1179), .B(n1165), .C(n1295), .Y(n1306) );
INVX3TS U927 ( .A(n1151), .Y(n1094) );
INVX3TS U928 ( .A(n1151), .Y(n1380) );
INVX3TS U929 ( .A(n1147), .Y(n1074) );
INVX3TS U930 ( .A(n1147), .Y(n1378) );
NOR2X4TS U931 ( .A(n1047), .B(n968), .Y(n1048) );
AOI32X1TS U932 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1349), .A2(n1390), .B0(
shift_value_SHT2_EWR[2]), .B1(n1346), .Y(n1348) );
AO22XLTS U933 ( .A0(n1319), .A1(add_subt), .B0(n919), .B1(intAS), .Y(n830)
);
AOI211XLTS U934 ( .A0(intDY_EWSW[16]), .A1(n1555), .B0(n1034), .C0(n1104),
.Y(n1026) );
BUFX3TS U935 ( .A(n1319), .Y(n873) );
OAI211X2TS U936 ( .A0(intDX_EWSW[20]), .A1(n1573), .B0(n1039), .C0(n1025),
.Y(n1034) );
NAND2X2TS U937 ( .A(n931), .B(n1466), .Y(n1372) );
INVX3TS U938 ( .A(n885), .Y(n912) );
OAI211X2TS U939 ( .A0(intDX_EWSW[12]), .A1(n1572), .B0(n1020), .C0(n1006),
.Y(n1022) );
INVX3TS U940 ( .A(n1381), .Y(n1466) );
INVX3TS U941 ( .A(n1384), .Y(n1406) );
INVX3TS U942 ( .A(n1652), .Y(n1374) );
INVX3TS U943 ( .A(n1649), .Y(n1404) );
NAND4XLTS U944 ( .A(n1517), .B(n1512), .C(n1511), .D(n1540), .Y(n1303) );
NAND3X1TS U945 ( .A(n1541), .B(n1518), .C(n1513), .Y(n1292) );
INVX4TS U946 ( .A(rst), .Y(n916) );
NAND2X1TS U947 ( .A(n1156), .B(n1522), .Y(n1163) );
NAND2X1TS U948 ( .A(n1178), .B(n1514), .Y(n1171) );
AOI2BB2XLTS U949 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n967), .A0N(n1384), .A1N(
DmP_mant_SFG_SWR[12]), .Y(intadd_66_B_2_) );
AOI2BB2XLTS U950 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n967), .A0N(n1384), .A1N(
DmP_mant_SFG_SWR[14]), .Y(intadd_66_B_4_) );
AOI2BB2XLTS U951 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n967), .A0N(n967), .A1N(
DmP_mant_SFG_SWR[10]), .Y(intadd_66_CI) );
AOI222X1TS U952 ( .A0(DMP_SFG[7]), .A1(n918), .B0(DMP_SFG[7]), .B1(n1287),
.C0(n918), .C1(n1287), .Y(intadd_66_B_0_) );
NAND2BXLTS U953 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n997) );
AOI2BB2XLTS U954 ( .B0(intDX_EWSW[3]), .B1(n1565), .A0N(intDY_EWSW[2]),
.A1N(n999), .Y(n1000) );
NAND2BXLTS U955 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1012) );
NAND3XLTS U956 ( .A(n1586), .B(n1010), .C(intDX_EWSW[8]), .Y(n1011) );
NAND2BXLTS U957 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1031) );
NOR2XLTS U958 ( .A(n1042), .B(intDY_EWSW[24]), .Y(n984) );
NAND2BXLTS U959 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n985) );
NAND2BXLTS U960 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1010) );
NAND2BXLTS U961 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1006) );
NAND2BXLTS U962 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1025) );
CLKAND2X2TS U963 ( .A(n1446), .B(shift_value_SHT2_EWR[4]), .Y(n1439) );
NOR2XLTS U964 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(n1174) );
AOI32X1TS U965 ( .A0(n1512), .A1(n1184), .A2(n1167), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1184), .Y(n1168) );
NAND2X1TS U966 ( .A(n1166), .B(n1519), .Y(n1293) );
OAI2BB2XLTS U967 ( .B0(intDY_EWSW[22]), .B1(n1035), .A0N(intDX_EWSW[23]),
.A1N(n936), .Y(n1036) );
NAND2BXLTS U968 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n986) );
NAND3XLTS U969 ( .A(n1587), .B(n985), .C(intDX_EWSW[26]), .Y(n987) );
NAND2BXLTS U970 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1040) );
NAND3BXLTS U971 ( .AN(n1029), .B(n1027), .C(n1026), .Y(n1045) );
AOI222X4TS U972 ( .A0(Data_array_SWR[21]), .A1(n942), .B0(Data_array_SWR[17]), .B1(n940), .C0(Data_array_SWR[25]), .C1(n1471), .Y(n1415) );
NAND2BXLTS U973 ( .AN(n1275), .B(n1308), .Y(n1276) );
NAND3XLTS U974 ( .A(n1274), .B(exp_rslt_NRM2_EW1[4]), .C(n1273), .Y(n1275)
);
OR2X1TS U975 ( .A(n982), .B(n1271), .Y(n1282) );
NAND2BXLTS U976 ( .AN(n1308), .B(n979), .Y(n982) );
NAND4BXLTS U977 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n977), .C(n976), .D(n975),
.Y(n978) );
AO22XLTS U978 ( .A0(DmP_mant_SFG_SWR[7]), .A1(n967), .B0(n1406), .B1(n966),
.Y(n881) );
AOI31XLTS U979 ( .A0(n1169), .A1(Raw_mant_NRM_SWR[16]), .A2(n1541), .B0(
n1168), .Y(n1170) );
AO21XLTS U980 ( .A0(n1514), .A1(n1535), .B0(n1293), .Y(n1301) );
AOI221X1TS U981 ( .A0(n1530), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]), .B1(
n936), .C0(n1106), .Y(n1107) );
OAI21XLTS U982 ( .A0(n1549), .A1(n1336), .B0(n1233), .Y(n1234) );
AOI222X1TS U983 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n910), .B0(n912), .B1(n929),
.C0(n1255), .C1(DmP_mant_SHT1_SW[10]), .Y(n1240) );
AOI222X1TS U984 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n910), .B0(n912), .B1(n923),
.C0(n1255), .C1(n926), .Y(n1218) );
AOI222X1TS U985 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n910), .B0(n912), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1255), .C1(n923), .Y(n1214) );
AOI222X1TS U986 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n910), .B0(n912), .B1(n922),
.C0(n1255), .C1(DmP_mant_SHT1_SW[8]), .Y(n1224) );
AOI222X1TS U987 ( .A0(n1284), .A1(DMP_SFG[1]), .B0(n1284), .B1(n917), .C0(
DMP_SFG[1]), .C1(n917), .Y(intadd_67_B_0_) );
AOI222X1TS U988 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n909), .B0(n927), .B1(n1255), .C0(n911), .C1(n925), .Y(n1243) );
AOI222X1TS U989 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n910), .B0(n912), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1255), .C1(DmP_mant_SHT1_SW[16]), .Y(n1254) );
OAI21XLTS U990 ( .A0(n1537), .A1(n1336), .B0(n1229), .Y(n1230) );
OAI21XLTS U991 ( .A0(n1594), .A1(n1265), .B0(n1225), .Y(n1226) );
AOI2BB2XLTS U992 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n967), .A0N(n1384), .A1N(
DmP_mant_SFG_SWR[11]), .Y(intadd_66_B_1_) );
AO22XLTS U993 ( .A0(DmP_mant_SFG_SWR[3]), .A1(n1406), .B0(n967), .B1(n959),
.Y(n884) );
CLKAND2X2TS U994 ( .A(n1599), .B(n1278), .Y(n1279) );
NOR2XLTS U995 ( .A(n1281), .B(n1276), .Y(n1280) );
AOI222X1TS U996 ( .A0(n1434), .A1(n874), .B0(Data_array_SWR[8]), .B1(n901),
.C0(n1433), .C1(n1453), .Y(n1485) );
AOI2BB2XLTS U997 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n967), .A0N(n1384), .A1N(
DmP_mant_SFG_SWR[15]), .Y(intadd_66_B_5_) );
AOI2BB2XLTS U998 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n967), .A0N(n1384), .A1N(
DmP_mant_SFG_SWR[13]), .Y(intadd_66_B_3_) );
AO22XLTS U999 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n1406), .B0(n967), .B1(n963),
.Y(n882) );
NAND3XLTS U1000 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1526), .C(
n1561), .Y(n1310) );
OAI21XLTS U1001 ( .A0(n1535), .A1(n1336), .B0(n1335), .Y(n1337) );
OAI21XLTS U1002 ( .A0(n1524), .A1(n1159), .B0(n1294), .Y(n1160) );
NOR2XLTS U1003 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1154)
);
NAND4XLTS U1004 ( .A(n1296), .B(n1295), .C(n1294), .D(n1301), .Y(n1297) );
BUFX3TS U1005 ( .A(n1505), .Y(n1493) );
BUFX4TS U1006 ( .A(n1050), .Y(n1146) );
AO22XLTS U1007 ( .A0(n1318), .A1(intDY_EWSW[20]), .B0(n920), .B1(Data_Y[20]),
.Y(n808) );
AO22XLTS U1008 ( .A0(n947), .A1(DmP_EXP_EWSW[20]), .B0(n1377), .B1(
DmP_mant_SHT1_SW[20]), .Y(n569) );
AO22XLTS U1009 ( .A0(n947), .A1(DmP_EXP_EWSW[17]), .B0(n1377), .B1(
DmP_mant_SHT1_SW[17]), .Y(n575) );
AO22XLTS U1010 ( .A0(n947), .A1(DmP_EXP_EWSW[16]), .B0(n1377), .B1(
DmP_mant_SHT1_SW[16]), .Y(n577) );
AO22XLTS U1011 ( .A0(n947), .A1(DmP_EXP_EWSW[19]), .B0(n1377), .B1(
DmP_mant_SHT1_SW[19]), .Y(n571) );
AO22XLTS U1012 ( .A0(n947), .A1(DmP_EXP_EWSW[15]), .B0(n1377), .B1(
DmP_mant_SHT1_SW[15]), .Y(n579) );
AO22XLTS U1013 ( .A0(n947), .A1(DmP_EXP_EWSW[21]), .B0(n1377), .B1(
DmP_mant_SHT1_SW[21]), .Y(n567) );
AO22XLTS U1014 ( .A0(n1516), .A1(DmP_EXP_EWSW[2]), .B0(n1376), .B1(
DmP_mant_SHT1_SW[2]), .Y(n605) );
AO22XLTS U1015 ( .A0(n947), .A1(DmP_EXP_EWSW[22]), .B0(n1377), .B1(
DmP_mant_SHT1_SW[22]), .Y(n565) );
AO22XLTS U1016 ( .A0(n947), .A1(DmP_EXP_EWSW[18]), .B0(n1377), .B1(
DmP_mant_SHT1_SW[18]), .Y(n573) );
AO22XLTS U1017 ( .A0(n1516), .A1(DmP_EXP_EWSW[10]), .B0(n1376), .B1(
DmP_mant_SHT1_SW[10]), .Y(n589) );
AO22XLTS U1018 ( .A0(n1516), .A1(DmP_EXP_EWSW[8]), .B0(n1376), .B1(
DmP_mant_SHT1_SW[8]), .Y(n593) );
OAI21XLTS U1019 ( .A0(n1259), .A1(n944), .B0(n1258), .Y(n791) );
OAI211XLTS U1020 ( .A0(n1254), .A1(n944), .B0(n1253), .C0(n1252), .Y(n788)
);
OAI211XLTS U1021 ( .A0(n1224), .A1(n944), .B0(n1223), .C0(n1222), .Y(n780)
);
AOI2BB2XLTS U1022 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1341), .A0N(n1240),
.A1N(n908), .Y(n1222) );
AO22XLTS U1023 ( .A0(n1319), .A1(Data_X[19]), .B0(n1325), .B1(intDX_EWSW[19]), .Y(n843) );
AO22XLTS U1024 ( .A0(n920), .A1(Data_X[30]), .B0(n1325), .B1(intDX_EWSW[30]),
.Y(n832) );
AO22XLTS U1025 ( .A0(n1323), .A1(Data_X[10]), .B0(n1320), .B1(intDX_EWSW[10]), .Y(n852) );
AO22XLTS U1026 ( .A0(n1326), .A1(Data_X[2]), .B0(n1325), .B1(intDX_EWSW[2]),
.Y(n860) );
AO22XLTS U1027 ( .A0(n873), .A1(Data_X[22]), .B0(n1322), .B1(intDX_EWSW[22]),
.Y(n840) );
AO22XLTS U1028 ( .A0(n1326), .A1(Data_X[14]), .B0(n1320), .B1(intDX_EWSW[14]), .Y(n848) );
AO22XLTS U1029 ( .A0(n1326), .A1(Data_X[20]), .B0(n1318), .B1(intDX_EWSW[20]), .Y(n842) );
AO22XLTS U1030 ( .A0(n1321), .A1(Data_X[12]), .B0(n1317), .B1(intDX_EWSW[12]), .Y(n850) );
AO22XLTS U1031 ( .A0(n873), .A1(Data_Y[31]), .B0(n919), .B1(intDY_EWSW[31]),
.Y(n797) );
AO22XLTS U1032 ( .A0(n1322), .A1(intDY_EWSW[11]), .B0(n873), .B1(Data_Y[11]),
.Y(n817) );
OAI21XLTS U1033 ( .A0(n936), .A1(n1380), .B0(n1095), .Y(n730) );
AO22XLTS U1034 ( .A0(n1491), .A1(DmP_mant_SFG_SWR[10]), .B0(n1490), .B1(
n1487), .Y(n478) );
AO22XLTS U1035 ( .A0(n1491), .A1(DmP_mant_SFG_SWR[11]), .B0(n1490), .B1(
n1416), .Y(n477) );
AO22XLTS U1036 ( .A0(n1509), .A1(DmP_mant_SFG_SWR[12]), .B0(n1490), .B1(
n1488), .Y(n476) );
AO22XLTS U1037 ( .A0(n1491), .A1(DmP_mant_SFG_SWR[13]), .B0(n1490), .B1(
n1489), .Y(n475) );
AO22XLTS U1038 ( .A0(n1509), .A1(DmP_mant_SFG_SWR[14]), .B0(n1389), .B1(
n1492), .Y(n474) );
AO22XLTS U1039 ( .A0(n1491), .A1(DmP_mant_SFG_SWR[15]), .B0(n1495), .B1(
n1494), .Y(n473) );
AO22XLTS U1040 ( .A0(n1504), .A1(DMP_SHT2_EWSW[0]), .B0(n1388), .B1(
DMP_SFG[0]), .Y(n717) );
AO22XLTS U1041 ( .A0(n1324), .A1(intDY_EWSW[10]), .B0(n920), .B1(Data_Y[10]),
.Y(n818) );
AO22XLTS U1042 ( .A0(n873), .A1(Data_X[31]), .B0(n1322), .B1(intDX_EWSW[31]),
.Y(n831) );
AO22XLTS U1043 ( .A0(n1495), .A1(DMP_SHT2_EWSW[1]), .B0(n1372), .B1(
DMP_SFG[1]), .Y(n714) );
AO22XLTS U1044 ( .A0(n1389), .A1(DMP_SHT2_EWSW[7]), .B0(n1372), .B1(
DMP_SFG[7]), .Y(n696) );
OAI211XLTS U1045 ( .A0(n1214), .A1(n944), .B0(n1203), .C0(n1202), .Y(n775)
);
AOI2BB2XLTS U1046 ( .B0(n1648), .B1(intadd_66_SUM_8_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1402), .Y(n524) );
OAI211XLTS U1047 ( .A0(n1251), .A1(n944), .B0(n1249), .C0(n1248), .Y(n790)
);
AO22XLTS U1048 ( .A0(n1326), .A1(Data_X[27]), .B0(n1320), .B1(intDX_EWSW[27]), .Y(n835) );
AO22XLTS U1049 ( .A0(n1323), .A1(Data_X[29]), .B0(n1320), .B1(intDX_EWSW[29]), .Y(n833) );
AO22XLTS U1050 ( .A0(n1321), .A1(Data_X[18]), .B0(n1318), .B1(intDX_EWSW[18]), .Y(n844) );
AOI2BB2XLTS U1051 ( .B0(n1648), .B1(intadd_66_SUM_9_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1402), .Y(n523) );
AO22XLTS U1052 ( .A0(n1319), .A1(Data_X[0]), .B0(n1325), .B1(intDX_EWSW[0]),
.Y(n862) );
OAI211XLTS U1053 ( .A0(n1243), .A1(n944), .B0(n1242), .C0(n1241), .Y(n786)
);
AOI2BB2XLTS U1054 ( .B0(n1648), .B1(intadd_66_SUM_2_), .A0N(
Raw_mant_NRM_SWR[12]), .A1N(n1402), .Y(n530) );
AO22XLTS U1055 ( .A0(n1321), .A1(Data_X[9]), .B0(n919), .B1(intDX_EWSW[9]),
.Y(n853) );
AO22XLTS U1056 ( .A0(n1326), .A1(Data_X[1]), .B0(n1318), .B1(intDX_EWSW[1]),
.Y(n861) );
AO22XLTS U1057 ( .A0(n873), .A1(Data_X[11]), .B0(n1318), .B1(intDX_EWSW[11]),
.Y(n851) );
AO22XLTS U1058 ( .A0(n1326), .A1(Data_X[17]), .B0(n1317), .B1(intDX_EWSW[17]), .Y(n845) );
AOI2BB2XLTS U1059 ( .B0(n1648), .B1(intadd_66_SUM_10_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1648), .Y(n522) );
AO22XLTS U1060 ( .A0(n873), .A1(Data_X[8]), .B0(n1317), .B1(intDX_EWSW[8]),
.Y(n854) );
OAI21XLTS U1061 ( .A0(n1548), .A1(n1270), .B0(n1269), .Y(n793) );
AO22XLTS U1062 ( .A0(n1321), .A1(Data_X[15]), .B0(n919), .B1(intDX_EWSW[15]),
.Y(n847) );
AO22XLTS U1063 ( .A0(n873), .A1(Data_X[23]), .B0(n919), .B1(intDX_EWSW[23]),
.Y(n839) );
AO22XLTS U1064 ( .A0(n1321), .A1(Data_X[13]), .B0(n1322), .B1(intDX_EWSW[13]), .Y(n849) );
AO22XLTS U1065 ( .A0(n920), .A1(Data_X[21]), .B0(n1317), .B1(intDX_EWSW[21]),
.Y(n841) );
AO22XLTS U1066 ( .A0(n1319), .A1(Data_X[3]), .B0(n1322), .B1(intDX_EWSW[3]),
.Y(n859) );
OAI211XLTS U1067 ( .A0(n1349), .A1(n1547), .B0(n1290), .C0(n1162), .Y(n767)
);
NAND3XLTS U1068 ( .A(n945), .B(Shift_amount_SHT1_EWR[4]), .C(n1390), .Y(
n1162) );
AO22XLTS U1069 ( .A0(n1321), .A1(Data_X[4]), .B0(n1318), .B1(intDX_EWSW[4]),
.Y(n858) );
AO22XLTS U1070 ( .A0(n873), .A1(Data_X[5]), .B0(n1322), .B1(intDX_EWSW[5]),
.Y(n857) );
AO22XLTS U1071 ( .A0(n920), .A1(Data_X[6]), .B0(n1320), .B1(intDX_EWSW[6]),
.Y(n856) );
AO22XLTS U1072 ( .A0(n920), .A1(Data_X[7]), .B0(n1317), .B1(intDX_EWSW[7]),
.Y(n855) );
AO22XLTS U1073 ( .A0(n873), .A1(Data_X[16]), .B0(n919), .B1(intDX_EWSW[16]),
.Y(n846) );
AO22XLTS U1074 ( .A0(n1320), .A1(intDX_EWSW[24]), .B0(n1321), .B1(Data_X[24]), .Y(n838) );
AO22XLTS U1075 ( .A0(n1318), .A1(intDX_EWSW[25]), .B0(n1326), .B1(Data_X[25]), .Y(n837) );
AO22XLTS U1076 ( .A0(n1317), .A1(intDY_EWSW[1]), .B0(n1326), .B1(Data_Y[1]),
.Y(n827) );
AO22XLTS U1077 ( .A0(n1322), .A1(intDY_EWSW[3]), .B0(n873), .B1(Data_Y[3]),
.Y(n825) );
AO22XLTS U1078 ( .A0(n1322), .A1(intDY_EWSW[12]), .B0(n1321), .B1(Data_Y[12]), .Y(n816) );
AO22XLTS U1079 ( .A0(n1317), .A1(intDY_EWSW[13]), .B0(n920), .B1(Data_Y[13]),
.Y(n815) );
AO22XLTS U1080 ( .A0(n1325), .A1(intDY_EWSW[14]), .B0(n920), .B1(Data_Y[14]),
.Y(n814) );
AO22XLTS U1081 ( .A0(n1320), .A1(intDY_EWSW[15]), .B0(n920), .B1(Data_Y[15]),
.Y(n813) );
AO22XLTS U1082 ( .A0(n1318), .A1(intDY_EWSW[17]), .B0(n920), .B1(Data_Y[17]),
.Y(n811) );
AO22XLTS U1083 ( .A0(n919), .A1(intDY_EWSW[18]), .B0(n920), .B1(Data_Y[18]),
.Y(n810) );
AO22XLTS U1084 ( .A0(n1322), .A1(intDY_EWSW[21]), .B0(n920), .B1(Data_Y[21]),
.Y(n807) );
AO22XLTS U1085 ( .A0(n1320), .A1(intDY_EWSW[25]), .B0(n1326), .B1(Data_Y[25]), .Y(n803) );
AO22XLTS U1086 ( .A0(n919), .A1(intDY_EWSW[26]), .B0(n1321), .B1(Data_Y[26]),
.Y(n802) );
AO22XLTS U1087 ( .A0(n1325), .A1(intDY_EWSW[29]), .B0(n920), .B1(Data_Y[29]),
.Y(n799) );
AO22XLTS U1088 ( .A0(n1317), .A1(intDY_EWSW[30]), .B0(n1326), .B1(Data_Y[30]), .Y(n798) );
AO22XLTS U1089 ( .A0(n1325), .A1(intDY_EWSW[22]), .B0(n1321), .B1(Data_Y[22]), .Y(n806) );
AO22XLTS U1090 ( .A0(n919), .A1(intDY_EWSW[8]), .B0(n873), .B1(Data_Y[8]),
.Y(n820) );
NOR2XLTS U1091 ( .A(n1411), .B(SIGN_FLAG_SHT1SHT2), .Y(n1283) );
AO22XLTS U1092 ( .A0(final_result_ieee[10]), .A1(n1470), .B0(n1427), .B1(
n1488), .Y(n511) );
AO22XLTS U1093 ( .A0(n1427), .A1(n1494), .B0(final_result_ieee[13]), .B1(
n1470), .Y(n506) );
AO22XLTS U1094 ( .A0(n1427), .A1(n1487), .B0(final_result_ieee[8]), .B1(
n1470), .Y(n507) );
AO22XLTS U1095 ( .A0(n1427), .A1(n1492), .B0(final_result_ieee[12]), .B1(
n1470), .Y(n508) );
AO22XLTS U1096 ( .A0(n1427), .A1(n1416), .B0(final_result_ieee[9]), .B1(
n1470), .Y(n509) );
AO22XLTS U1097 ( .A0(n1427), .A1(n1489), .B0(final_result_ieee[11]), .B1(
n1470), .Y(n510) );
AO22XLTS U1098 ( .A0(n1322), .A1(intDY_EWSW[24]), .B0(n1326), .B1(Data_Y[24]), .Y(n804) );
AO22XLTS U1099 ( .A0(n1324), .A1(intDY_EWSW[5]), .B0(n873), .B1(Data_Y[5]),
.Y(n823) );
AO22XLTS U1100 ( .A0(n1325), .A1(intDY_EWSW[16]), .B0(n920), .B1(Data_Y[16]),
.Y(n812) );
AO22XLTS U1101 ( .A0(n1324), .A1(intDY_EWSW[19]), .B0(n920), .B1(Data_Y[19]),
.Y(n809) );
AO22XLTS U1102 ( .A0(n1325), .A1(intDX_EWSW[26]), .B0(n1321), .B1(Data_X[26]), .Y(n836) );
AO22XLTS U1103 ( .A0(n1323), .A1(Data_X[28]), .B0(n1325), .B1(intDX_EWSW[28]), .Y(n834) );
OAI21XLTS U1104 ( .A0(n1312), .A1(n983), .B0(n1310), .Y(n870) );
AOI2BB2XLTS U1105 ( .B0(beg_OP), .B1(n1526), .A0N(n1526), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n983) );
AO22XLTS U1106 ( .A0(n1320), .A1(intDY_EWSW[6]), .B0(n873), .B1(Data_Y[6]),
.Y(n822) );
AO22XLTS U1107 ( .A0(n1317), .A1(intDY_EWSW[9]), .B0(n1326), .B1(Data_Y[9]),
.Y(n819) );
AO22XLTS U1108 ( .A0(n919), .A1(intDY_EWSW[2]), .B0(n1321), .B1(Data_Y[2]),
.Y(n826) );
AO22XLTS U1109 ( .A0(n1320), .A1(intDY_EWSW[4]), .B0(n1326), .B1(Data_Y[4]),
.Y(n824) );
AO22XLTS U1110 ( .A0(n1317), .A1(intDY_EWSW[7]), .B0(n1326), .B1(Data_Y[7]),
.Y(n821) );
AO22XLTS U1111 ( .A0(n1324), .A1(intDY_EWSW[28]), .B0(n1321), .B1(Data_Y[28]), .Y(n800) );
AO22XLTS U1112 ( .A0(n1318), .A1(intDY_EWSW[23]), .B0(n1321), .B1(Data_Y[23]), .Y(n805) );
AO22XLTS U1113 ( .A0(n1324), .A1(intDY_EWSW[27]), .B0(n873), .B1(Data_Y[27]),
.Y(n801) );
AO22XLTS U1114 ( .A0(n1318), .A1(intDY_EWSW[0]), .B0(n1323), .B1(Data_Y[0]),
.Y(n828) );
AO21XLTS U1115 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1390), .B0(n1307), .Y(n513) );
AO21XLTS U1116 ( .A0(LZD_output_NRM2_EW[0]), .A1(n1390), .B0(n1334), .Y(n515) );
AOI2BB1XLTS U1117 ( .A0N(Shift_reg_FLAGS_7[1]), .A1N(LZD_output_NRM2_EW[3]),
.B0(n1351), .Y(n516) );
AO22XLTS U1118 ( .A0(n1504), .A1(SIGN_FLAG_SHT2), .B0(n1388), .B1(
SIGN_FLAG_SFG), .Y(n546) );
AO22XLTS U1119 ( .A0(n1491), .A1(n1385), .B0(n1490), .B1(OP_FLAG_SHT2), .Y(
n549) );
OAI21XLTS U1120 ( .A0(n1530), .A1(n1378), .B0(n1052), .Y(n566) );
OAI21XLTS U1121 ( .A0(n1569), .A1(n1378), .B0(n1060), .Y(n568) );
OAI21XLTS U1122 ( .A0(n1531), .A1(n1378), .B0(n1053), .Y(n572) );
OAI21XLTS U1123 ( .A0(n1589), .A1(n1378), .B0(n1065), .Y(n574) );
OAI21XLTS U1124 ( .A0(n1584), .A1(n1378), .B0(n1058), .Y(n576) );
OAI21XLTS U1125 ( .A0(n1583), .A1(n1074), .B0(n1073), .Y(n580) );
AO22XLTS U1126 ( .A0(n1516), .A1(DmP_EXP_EWSW[14]), .B0(n1377), .B1(n927),
.Y(n581) );
OAI21XLTS U1127 ( .A0(n1528), .A1(n1074), .B0(n1051), .Y(n582) );
AO22XLTS U1128 ( .A0(n1516), .A1(DmP_EXP_EWSW[13]), .B0(n1377), .B1(n925),
.Y(n583) );
OAI21XLTS U1129 ( .A0(n1568), .A1(n1074), .B0(n1059), .Y(n584) );
AO22XLTS U1130 ( .A0(n1516), .A1(DmP_EXP_EWSW[12]), .B0(n1377), .B1(n924),
.Y(n585) );
OAI21XLTS U1131 ( .A0(n1572), .A1(n1074), .B0(n1067), .Y(n586) );
AO22XLTS U1132 ( .A0(n1516), .A1(DmP_EXP_EWSW[11]), .B0(n1376), .B1(n928),
.Y(n587) );
OAI21XLTS U1133 ( .A0(n1113), .A1(n1074), .B0(n1070), .Y(n588) );
OAI21XLTS U1134 ( .A0(n883), .A1(n1074), .B0(n1061), .Y(n590) );
AO22XLTS U1135 ( .A0(n1516), .A1(DmP_EXP_EWSW[9]), .B0(n1376), .B1(n929),
.Y(n591) );
OAI21XLTS U1136 ( .A0(n1567), .A1(n1074), .B0(n1063), .Y(n592) );
OAI21XLTS U1137 ( .A0(n1586), .A1(n1074), .B0(n1068), .Y(n594) );
AO22XLTS U1138 ( .A0(n1516), .A1(DmP_EXP_EWSW[7]), .B0(n1376), .B1(n922),
.Y(n595) );
OAI21XLTS U1139 ( .A0(n1574), .A1(n1074), .B0(n1064), .Y(n596) );
AO22XLTS U1140 ( .A0(n1516), .A1(DmP_EXP_EWSW[6]), .B0(n1376), .B1(n930),
.Y(n597) );
OAI21XLTS U1141 ( .A0(n1566), .A1(n1074), .B0(n1057), .Y(n598) );
AO22XLTS U1142 ( .A0(n1516), .A1(DmP_EXP_EWSW[5]), .B0(n1376), .B1(n932),
.Y(n599) );
OAI21XLTS U1143 ( .A0(n1527), .A1(n1074), .B0(n1056), .Y(n600) );
AO22XLTS U1144 ( .A0(n1516), .A1(DmP_EXP_EWSW[4]), .B0(n1376), .B1(n926),
.Y(n601) );
OAI21XLTS U1145 ( .A0(n1571), .A1(n1074), .B0(n1055), .Y(n602) );
AO22XLTS U1146 ( .A0(n1516), .A1(DmP_EXP_EWSW[3]), .B0(n1376), .B1(n923),
.Y(n603) );
OAI21XLTS U1147 ( .A0(n1565), .A1(n1132), .B0(n1071), .Y(n604) );
OAI21XLTS U1148 ( .A0(n1570), .A1(n1132), .B0(n1069), .Y(n606) );
AO22XLTS U1149 ( .A0(n1516), .A1(DmP_EXP_EWSW[1]), .B0(n1376), .B1(n933),
.Y(n607) );
OAI21XLTS U1150 ( .A0(n1585), .A1(n1132), .B0(n1066), .Y(n608) );
AO22XLTS U1151 ( .A0(n947), .A1(DmP_EXP_EWSW[0]), .B0(n1386), .B1(n934), .Y(
n609) );
OAI21XLTS U1152 ( .A0(n1582), .A1(n1132), .B0(n1049), .Y(n610) );
AO22XLTS U1153 ( .A0(n1389), .A1(DMP_SHT2_EWSW[30]), .B0(n1388), .B1(
DMP_SFG[30]), .Y(n613) );
AO22XLTS U1154 ( .A0(n1495), .A1(DMP_SHT2_EWSW[28]), .B0(n1388), .B1(
DMP_SFG[28]), .Y(n623) );
AO22XLTS U1155 ( .A0(n1495), .A1(DMP_SHT2_EWSW[27]), .B0(n1388), .B1(
DMP_SFG[27]), .Y(n628) );
AO22XLTS U1156 ( .A0(n1495), .A1(DMP_SHT2_EWSW[26]), .B0(n1388), .B1(
DMP_SFG[26]), .Y(n633) );
AO22XLTS U1157 ( .A0(n1504), .A1(DMP_SHT2_EWSW[24]), .B0(n1388), .B1(
DMP_SFG[24]), .Y(n643) );
AO22XLTS U1158 ( .A0(n1509), .A1(DMP_SFG[22]), .B0(n1389), .B1(
DMP_SHT2_EWSW[22]), .Y(n651) );
AO22XLTS U1159 ( .A0(n1509), .A1(DMP_SFG[21]), .B0(n1389), .B1(
DMP_SHT2_EWSW[21]), .Y(n654) );
AO22XLTS U1160 ( .A0(n1491), .A1(DMP_SFG[20]), .B0(n1495), .B1(
DMP_SHT2_EWSW[20]), .Y(n657) );
AO22XLTS U1161 ( .A0(n1491), .A1(DMP_SFG[19]), .B0(n1389), .B1(
DMP_SHT2_EWSW[19]), .Y(n660) );
AO22XLTS U1162 ( .A0(n1509), .A1(DMP_SFG[18]), .B0(n1495), .B1(
DMP_SHT2_EWSW[18]), .Y(n663) );
AO22XLTS U1163 ( .A0(n1509), .A1(DMP_SFG[17]), .B0(n1504), .B1(
DMP_SHT2_EWSW[17]), .Y(n666) );
AO22XLTS U1164 ( .A0(n1371), .A1(n1370), .B0(ZERO_FLAG_EXP), .B1(n1050), .Y(
n721) );
OAI21XLTS U1165 ( .A0(n1588), .A1(n1380), .B0(n1085), .Y(n723) );
OAI21XLTS U1166 ( .A0(n1532), .A1(n1380), .B0(n1086), .Y(n724) );
OAI21XLTS U1167 ( .A0(n1575), .A1(n1380), .B0(n1083), .Y(n725) );
OAI21XLTS U1168 ( .A0(n1576), .A1(n1380), .B0(n1084), .Y(n726) );
OAI21XLTS U1169 ( .A0(n1530), .A1(n1094), .B0(n1077), .Y(n731) );
OAI21XLTS U1170 ( .A0(n1569), .A1(n1094), .B0(n1080), .Y(n732) );
OAI21XLTS U1171 ( .A0(n1531), .A1(n1094), .B0(n1089), .Y(n734) );
OAI21XLTS U1172 ( .A0(n1589), .A1(n1094), .B0(n1075), .Y(n735) );
OAI21XLTS U1173 ( .A0(n1529), .A1(n1094), .B0(n1088), .Y(n737) );
OAI21XLTS U1174 ( .A0(n1583), .A1(n1094), .B0(n1082), .Y(n738) );
OAI21XLTS U1175 ( .A0(n1528), .A1(n1094), .B0(n1079), .Y(n739) );
OAI21XLTS U1176 ( .A0(n1568), .A1(n1094), .B0(n1081), .Y(n740) );
OAI21XLTS U1177 ( .A0(n1572), .A1(n1094), .B0(n1078), .Y(n741) );
OAI21XLTS U1178 ( .A0(n1113), .A1(n1094), .B0(n1091), .Y(n742) );
OAI21XLTS U1179 ( .A0(n883), .A1(n1149), .B0(n1148), .Y(n743) );
OAI21XLTS U1180 ( .A0(n1567), .A1(n1149), .B0(n1141), .Y(n744) );
OAI21XLTS U1181 ( .A0(n1586), .A1(n1149), .B0(n1138), .Y(n745) );
OAI21XLTS U1182 ( .A0(n1574), .A1(n1149), .B0(n1140), .Y(n746) );
OAI21XLTS U1183 ( .A0(n1566), .A1(n1149), .B0(n1142), .Y(n747) );
OAI21XLTS U1184 ( .A0(n1527), .A1(n1149), .B0(n1144), .Y(n748) );
OAI21XLTS U1185 ( .A0(n1571), .A1(n1149), .B0(n1145), .Y(n749) );
OAI21XLTS U1186 ( .A0(n1570), .A1(n1149), .B0(n1143), .Y(n751) );
OAI21XLTS U1187 ( .A0(n1585), .A1(n1380), .B0(n1087), .Y(n752) );
OAI21XLTS U1188 ( .A0(n1582), .A1(n1094), .B0(n1090), .Y(n753) );
AO22XLTS U1189 ( .A0(n1315), .A1(busy), .B0(n1314), .B1(n931), .Y(n866) );
INVX3TS U1190 ( .A(n905), .Y(n1390) );
OR2X1TS U1191 ( .A(n905), .B(Shift_amount_SHT1_EWR[0]), .Y(n885) );
OR2X1TS U1192 ( .A(n906), .B(n1457), .Y(n886) );
OR2X1TS U1193 ( .A(shift_value_SHT2_EWR[4]), .B(n1426), .Y(n887) );
OR2X1TS U1194 ( .A(n874), .B(n1457), .Y(n888) );
OR3X1TS U1195 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1542), .Y(n890) );
INVX2TS U1196 ( .A(n945), .Y(n946) );
INVX2TS U1197 ( .A(n886), .Y(n900) );
INVX2TS U1198 ( .A(n886), .Y(n901) );
INVX2TS U1199 ( .A(n1323), .Y(n1324) );
INVX2TS U1200 ( .A(n1427), .Y(n902) );
INVX2TS U1201 ( .A(n1427), .Y(n903) );
INVX2TS U1202 ( .A(Shift_reg_FLAGS_7[1]), .Y(n904) );
INVX2TS U1203 ( .A(n875), .Y(n905) );
INVX2TS U1204 ( .A(n876), .Y(n906) );
INVX2TS U1205 ( .A(left_right_SHT2), .Y(n907) );
INVX2TS U1206 ( .A(n1336), .Y(n909) );
CLKINVX3TS U1207 ( .A(n885), .Y(n911) );
INVX2TS U1208 ( .A(n946), .Y(n913) );
INVX2TS U1209 ( .A(n913), .Y(n914) );
OAI21XLTS U1210 ( .A0(n1576), .A1(n1074), .B0(n1072), .Y(n560) );
OAI211XLTS U1211 ( .A0(n1194), .A1(n944), .B0(n1193), .C0(n1192), .Y(n772)
);
INVX2TS U1212 ( .A(rst), .Y(n915) );
OAI211XLTS U1213 ( .A0(n988), .A1(n1097), .B0(n987), .C0(n986), .Y(n993) );
OAI21X2TS U1214 ( .A0(intDX_EWSW[26]), .A1(n1587), .B0(n985), .Y(n1097) );
INVX2TS U1215 ( .A(n884), .Y(n917) );
INVX2TS U1216 ( .A(n882), .Y(n918) );
INVX2TS U1217 ( .A(n1323), .Y(n919) );
INVX4TS U1218 ( .A(n1324), .Y(n920) );
INVX2TS U1219 ( .A(n881), .Y(n921) );
NOR2X4TS U1220 ( .A(shift_value_SHT2_EWR[4]), .B(left_right_SHT2), .Y(n1454)
);
OAI21XLTS U1221 ( .A0(n1340), .A1(n908), .B0(n1264), .Y(n779) );
OAI21XLTS U1222 ( .A0(n1259), .A1(n908), .B0(n1237), .Y(n789) );
OAI211XLTS U1223 ( .A0(n1218), .A1(n908), .B0(n1217), .C0(n1216), .Y(n774)
);
OAI211XLTS U1224 ( .A0(n1214), .A1(n908), .B0(n1213), .C0(n1212), .Y(n773)
);
OAI211XLTS U1225 ( .A0(n1224), .A1(n908), .B0(n1221), .C0(n1220), .Y(n778)
);
OAI211XLTS U1226 ( .A0(n1262), .A1(n908), .B0(n1209), .C0(n1208), .Y(n777)
);
AOI221X1TS U1227 ( .A0(n1573), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1569), .C0(n1105), .Y(n1108) );
OAI21XLTS U1228 ( .A0(n1573), .A1(n1378), .B0(n1062), .Y(n570) );
OAI21XLTS U1229 ( .A0(n1573), .A1(n1094), .B0(n1093), .Y(n733) );
BUFX4TS U1230 ( .A(n1505), .Y(n1491) );
BUFX4TS U1231 ( .A(n1505), .Y(n1509) );
BUFX4TS U1232 ( .A(n1147), .Y(n1150) );
BUFX4TS U1233 ( .A(n1626), .Y(n1622) );
BUFX4TS U1234 ( .A(n1629), .Y(n1616) );
BUFX4TS U1235 ( .A(n1627), .Y(n1619) );
BUFX4TS U1236 ( .A(n1630), .Y(n1620) );
BUFX3TS U1237 ( .A(n915), .Y(n971) );
AOI222X4TS U1238 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n909), .B0(n912), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1255), .C1(DmP_mant_SHT1_SW[21]), .Y(n1267) );
INVX2TS U1239 ( .A(n896), .Y(n922) );
INVX2TS U1240 ( .A(n895), .Y(n923) );
BUFX4TS U1241 ( .A(n1649), .Y(n1408) );
INVX2TS U1242 ( .A(n898), .Y(n924) );
INVX2TS U1243 ( .A(n877), .Y(n925) );
INVX2TS U1244 ( .A(n880), .Y(n926) );
INVX2TS U1245 ( .A(n899), .Y(n927) );
INVX2TS U1246 ( .A(n879), .Y(n928) );
INVX2TS U1247 ( .A(n891), .Y(n929) );
INVX2TS U1248 ( .A(n878), .Y(n930) );
INVX2TS U1249 ( .A(n889), .Y(n931) );
INVX2TS U1250 ( .A(n894), .Y(n932) );
INVX2TS U1251 ( .A(n893), .Y(n933) );
INVX2TS U1252 ( .A(n892), .Y(n934) );
INVX2TS U1253 ( .A(n897), .Y(n935) );
AOI211X1TS U1254 ( .A0(n1177), .A1(n1176), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1183) );
INVX2TS U1255 ( .A(intDY_EWSW[23]), .Y(n936) );
INVX2TS U1256 ( .A(n888), .Y(n937) );
INVX2TS U1257 ( .A(n888), .Y(n938) );
INVX2TS U1258 ( .A(n887), .Y(n939) );
INVX2TS U1259 ( .A(n887), .Y(n940) );
INVX2TS U1260 ( .A(n890), .Y(n941) );
INVX2TS U1261 ( .A(n890), .Y(n942) );
INVX2TS U1262 ( .A(n1185), .Y(n943) );
INVX4TS U1263 ( .A(n1372), .Y(n1490) );
INVX3TS U1264 ( .A(n1649), .Y(n1402) );
INVX4TS U1265 ( .A(n1505), .Y(n1389) );
INVX4TS U1266 ( .A(n1505), .Y(n1504) );
INVX4TS U1267 ( .A(n1505), .Y(n1495) );
INVX2TS U1268 ( .A(n1651), .Y(n945) );
AOI222X4TS U1269 ( .A0(Data_array_SWR[24]), .A1(n1471), .B0(
Data_array_SWR[20]), .B1(n942), .C0(Data_array_SWR[16]), .C1(n940),
.Y(n1414) );
AOI222X4TS U1270 ( .A0(Data_array_SWR[14]), .A1(n940), .B0(
Data_array_SWR[22]), .B1(n1471), .C0(Data_array_SWR[18]), .C1(n942),
.Y(n1422) );
OAI211XLTS U1271 ( .A0(n1240), .A1(n943), .B0(n1239), .C0(n1238), .Y(n782)
);
AOI222X1TS U1272 ( .A0(n1429), .A1(n907), .B0(Data_array_SWR[9]), .B1(n901),
.C0(n1428), .C1(n1453), .Y(n1486) );
AOI222X1TS U1273 ( .A0(n1429), .A1(left_right_SHT2), .B0(Data_array_SWR[9]),
.B1(n938), .C0(n1428), .C1(n1454), .Y(n1496) );
AOI32X1TS U1274 ( .A0(n1589), .A1(n1031), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1531), .Y(n1032) );
AOI221X1TS U1275 ( .A0(n1589), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1531), .C0(n1104), .Y(n1109) );
AOI221X1TS U1276 ( .A0(n1588), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1584), .C0(n1103), .Y(n1110) );
AOI221X1TS U1277 ( .A0(intDX_EWSW[30]), .A1(n1588), .B0(intDX_EWSW[29]),
.B1(n1532), .C0(n990), .Y(n992) );
AOI221X1TS U1278 ( .A0(n883), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]), .B1(
n1113), .C0(n1112), .Y(n1118) );
AOI221X1TS U1279 ( .A0(n1570), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1565), .C0(n1121), .Y(n1126) );
AOI221X1TS U1280 ( .A0(n1528), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1583), .C0(n1115), .Y(n1116) );
AOI221X1TS U1281 ( .A0(n1572), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1568), .C0(n1114), .Y(n1117) );
OAI31XLTS U1282 ( .A0(n1371), .A1(n1136), .A2(n1380), .B0(n1135), .Y(n720)
);
NOR2X2TS U1283 ( .A(n952), .B(DMP_EXP_EWSW[23]), .Y(n1356) );
XNOR2X2TS U1284 ( .A(DMP_exp_NRM2_EW[0]), .B(n1288), .Y(n1272) );
XNOR2X2TS U1285 ( .A(DMP_exp_NRM2_EW[6]), .B(n980), .Y(n1308) );
XNOR2X2TS U1286 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J59_123_4652_n4), .Y(
n1274) );
AOI222X4TS U1287 ( .A0(n1286), .A1(intadd_67_A_4_), .B0(n1286), .B1(
intadd_67_B_4_), .C0(intadd_67_A_4_), .C1(intadd_67_B_4_), .Y(n1287)
);
AOI22X2TS U1288 ( .A0(n1403), .A1(DmP_mant_SFG_SWR[8]), .B0(n1406), .B1(n964), .Y(intadd_67_B_4_) );
NOR2X4TS U1289 ( .A(shift_value_SHT2_EWR[4]), .B(n874), .Y(n1453) );
BUFX4TS U1290 ( .A(n972), .Y(n1637) );
BUFX4TS U1291 ( .A(n971), .Y(n1623) );
BUFX4TS U1292 ( .A(n972), .Y(n1641) );
BUFX4TS U1293 ( .A(n971), .Y(n1639) );
BUFX4TS U1294 ( .A(n972), .Y(n1640) );
BUFX4TS U1295 ( .A(n971), .Y(n1638) );
BUFX3TS U1296 ( .A(n915), .Y(n972) );
NOR2XLTS U1297 ( .A(n1008), .B(intDY_EWSW[10]), .Y(n1009) );
NOR2X4TS U1298 ( .A(n1411), .B(n1410), .Y(n1427) );
OAI2BB1X2TS U1299 ( .A0N(n1280), .A1N(n1279), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1410) );
AOI222X1TS U1300 ( .A0(n1448), .A1(n907), .B0(n901), .B1(Data_array_SWR[5]),
.C0(n1449), .C1(n1453), .Y(n1482) );
AOI222X1TS U1301 ( .A0(n1448), .A1(n906), .B0(Data_array_SWR[5]), .B1(n938),
.C0(n1449), .C1(n1454), .Y(n1500) );
AOI222X1TS U1302 ( .A0(n1456), .A1(n874), .B0(n901), .B1(Data_array_SWR[4]),
.C0(n1455), .C1(n1453), .Y(n1481) );
AOI222X1TS U1303 ( .A0(n1456), .A1(n906), .B0(Data_array_SWR[4]), .B1(n938),
.C0(n1455), .C1(n1454), .Y(n1501) );
AOI222X1TS U1304 ( .A0(n1438), .A1(n874), .B0(Data_array_SWR[7]), .B1(n901),
.C0(n1437), .C1(n1453), .Y(n1484) );
AOI222X1TS U1305 ( .A0(n1443), .A1(n907), .B0(Data_array_SWR[6]), .B1(n901),
.C0(n1442), .C1(n1453), .Y(n1483) );
AOI222X1TS U1306 ( .A0(n1443), .A1(left_right_SHT2), .B0(Data_array_SWR[6]),
.B1(n938), .C0(n1442), .C1(n1454), .Y(n1499) );
OAI21XLTS U1307 ( .A0(n1332), .A1(n944), .B0(n1232), .Y(n787) );
AOI222X4TS U1308 ( .A0(Data_array_SWR[23]), .A1(n1471), .B0(
Data_array_SWR[19]), .B1(n942), .C0(Data_array_SWR[15]), .C1(n940),
.Y(n1418) );
AOI222X1TS U1309 ( .A0(n1434), .A1(left_right_SHT2), .B0(Data_array_SWR[8]),
.B1(n938), .C0(n1433), .C1(n1454), .Y(n1497) );
AOI221X1TS U1310 ( .A0(n1587), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]),
.B1(n1576), .C0(n1097), .Y(n1101) );
NOR2X2TS U1311 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1561), .Y(n1312) );
OAI21X2TS U1312 ( .A0(intDX_EWSW[18]), .A1(n1589), .B0(n1031), .Y(n1104) );
NOR3X1TS U1313 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1304) );
OAI211XLTS U1314 ( .A0(n1246), .A1(n943), .B0(n1245), .C0(n1244), .Y(n784)
);
NOR2X4TS U1315 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1446) );
OAI21XLTS U1316 ( .A0(intDX_EWSW[1]), .A1(n1585), .B0(intDX_EWSW[0]), .Y(
n996) );
OAI211XLTS U1317 ( .A0(intDX_EWSW[8]), .A1(n1586), .B0(n1010), .C0(n1013),
.Y(n1024) );
OAI21XLTS U1318 ( .A0(intDX_EWSW[13]), .A1(n1568), .B0(intDX_EWSW[12]), .Y(
n1007) );
OAI21XLTS U1319 ( .A0(intDX_EWSW[21]), .A1(n1569), .B0(intDX_EWSW[20]), .Y(
n1028) );
OAI21XLTS U1320 ( .A0(intDX_EWSW[3]), .A1(n1565), .B0(intDX_EWSW[2]), .Y(
n999) );
OAI211XLTS U1321 ( .A0(n1565), .A1(intDX_EWSW[3]), .B0(n998), .C0(n997), .Y(
n1001) );
INVX2TS U1322 ( .A(n1611), .Y(n947) );
AOI22X1TS U1323 ( .A0(n1314), .A1(n1648), .B0(n1315), .B1(n931), .Y(n957) );
NOR2XLTS U1324 ( .A(n1557), .B(intDX_EWSW[11]), .Y(n1008) );
OAI21XLTS U1325 ( .A0(intDX_EWSW[15]), .A1(n1583), .B0(intDX_EWSW[14]), .Y(
n1016) );
NOR2XLTS U1326 ( .A(n1029), .B(intDY_EWSW[16]), .Y(n1030) );
NOR2XLTS U1327 ( .A(n1272), .B(exp_rslt_NRM2_EW1[1]), .Y(n977) );
OAI21XLTS U1328 ( .A0(intDX_EWSW[23]), .A1(n936), .B0(intDX_EWSW[22]), .Y(
n1035) );
NOR2XLTS U1329 ( .A(n978), .B(n1274), .Y(n979) );
NOR2XLTS U1330 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1177) );
OAI21XLTS U1331 ( .A0(n1514), .A1(n1336), .B0(n1330), .Y(n1331) );
OAI21XLTS U1332 ( .A0(n1136), .A1(n1050), .B0(n1132), .Y(n1134) );
OAI21XLTS U1333 ( .A0(DmP_EXP_EWSW[25]), .A1(n1595), .B0(n1360), .Y(n1357)
);
OAI21XLTS U1334 ( .A0(n1519), .A1(n1265), .B0(n1260), .Y(n1261) );
OAI21XLTS U1335 ( .A0(n1529), .A1(n1378), .B0(n1054), .Y(n578) );
OAI21XLTS U1336 ( .A0(n1584), .A1(n1094), .B0(n1076), .Y(n736) );
OAI21XLTS U1337 ( .A0(n1565), .A1(n1149), .B0(n1139), .Y(n750) );
OAI211XLTS U1338 ( .A0(n1218), .A1(n943), .B0(n1199), .C0(n1198), .Y(n776)
);
OAI21XLTS U1339 ( .A0(n1329), .A1(n908), .B0(n1228), .Y(n792) );
NOR2XLTS U1340 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n969) );
AOI32X4TS U1341 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n969), .B1(n1561), .Y(n1315)
);
INVX2TS U1342 ( .A(n1315), .Y(n1314) );
BUFX3TS U1343 ( .A(n915), .Y(n1630) );
CLKBUFX2TS U1344 ( .A(n916), .Y(n970) );
BUFX3TS U1345 ( .A(n972), .Y(n1631) );
BUFX3TS U1346 ( .A(n971), .Y(n1632) );
BUFX3TS U1347 ( .A(n972), .Y(n1633) );
BUFX3TS U1348 ( .A(n971), .Y(n1634) );
BUFX3TS U1349 ( .A(n972), .Y(n1635) );
BUFX3TS U1350 ( .A(n971), .Y(n1636) );
BUFX3TS U1351 ( .A(n972), .Y(n1624) );
BUFX3TS U1352 ( .A(n915), .Y(n1627) );
BUFX3TS U1353 ( .A(n915), .Y(n1628) );
BUFX3TS U1354 ( .A(n916), .Y(n1629) );
BUFX3TS U1355 ( .A(n972), .Y(n1617) );
BUFX3TS U1356 ( .A(n916), .Y(n1625) );
BUFX3TS U1357 ( .A(n972), .Y(n1621) );
BUFX3TS U1358 ( .A(n971), .Y(n1618) );
BUFX3TS U1359 ( .A(n916), .Y(n1626) );
BUFX3TS U1360 ( .A(n971), .Y(n1643) );
BUFX3TS U1361 ( .A(n972), .Y(n1647) );
BUFX3TS U1362 ( .A(n971), .Y(n1646) );
BUFX3TS U1363 ( .A(n971), .Y(n1642) );
BUFX3TS U1364 ( .A(n972), .Y(n1645) );
BUFX3TS U1365 ( .A(n971), .Y(n1644) );
CLKBUFX2TS U1366 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1381) );
BUFX3TS U1367 ( .A(n1372), .Y(n1505) );
AND3X4TS U1368 ( .A(shift_value_SHT2_EWR[2]), .B(n1547), .C(
shift_value_SHT2_EWR[3]), .Y(n1471) );
NAND2X1TS U1369 ( .A(shift_value_SHT2_EWR[2]), .B(n1542), .Y(n1426) );
AOI22X1TS U1370 ( .A0(Data_array_SWR[22]), .A1(n941), .B0(Data_array_SWR[18]), .B1(n940), .Y(n1419) );
NAND2X1TS U1371 ( .A(n1446), .B(n1547), .Y(n1457) );
AOI22X1TS U1372 ( .A0(Data_array_SWR[14]), .A1(n937), .B0(Data_array_SWR[11]), .B1(n900), .Y(n973) );
OAI221X1TS U1373 ( .A0(left_right_SHT2), .A1(n1418), .B0(n874), .B1(n1419),
.C0(n973), .Y(n1416) );
INVX2TS U1374 ( .A(DP_OP_15J59_123_4652_n4), .Y(n974) );
NAND2X1TS U1375 ( .A(n1578), .B(n974), .Y(n980) );
INVX2TS U1376 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n976) );
INVX2TS U1377 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n975) );
INVX2TS U1378 ( .A(n980), .Y(n981) );
NAND2X1TS U1379 ( .A(n1577), .B(n981), .Y(n1277) );
XNOR2X1TS U1380 ( .A(DMP_exp_NRM2_EW[7]), .B(n1277), .Y(n1271) );
NAND2X2TS U1381 ( .A(n1282), .B(n1381), .Y(n1309) );
OA22X1TS U1382 ( .A0(n1309), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n758) );
OA22X1TS U1383 ( .A0(n1309), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n757) );
OA22X1TS U1384 ( .A0(n1309), .A1(n1274), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n756) );
OA22X1TS U1385 ( .A0(n1309), .A1(n1272), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n761) );
OA22X1TS U1386 ( .A0(n1309), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n759) );
OA22X1TS U1387 ( .A0(n1309), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n760) );
INVX4TS U1388 ( .A(n1374), .Y(busy) );
OAI21XLTS U1389 ( .A0(n945), .A1(n874), .B0(n1390), .Y(n829) );
NOR2X1TS U1390 ( .A(n1581), .B(intDX_EWSW[25]), .Y(n1042) );
AOI22X1TS U1391 ( .A0(intDX_EWSW[25]), .A1(n1581), .B0(intDX_EWSW[24]), .B1(
n984), .Y(n988) );
NOR2X1TS U1392 ( .A(n1588), .B(intDX_EWSW[30]), .Y(n991) );
NOR2X1TS U1393 ( .A(n1532), .B(intDX_EWSW[29]), .Y(n989) );
AOI211X1TS U1394 ( .A0(intDY_EWSW[28]), .A1(n1556), .B0(n991), .C0(n989),
.Y(n1041) );
NOR3X1TS U1395 ( .A(n1556), .B(n989), .C(intDY_EWSW[28]), .Y(n990) );
AOI2BB2X1TS U1396 ( .B0(n993), .B1(n1041), .A0N(n992), .A1N(n991), .Y(n1046)
);
NOR2X1TS U1397 ( .A(n1584), .B(intDX_EWSW[17]), .Y(n1029) );
INVX2TS U1398 ( .A(intDY_EWSW[11]), .Y(n1113) );
OAI22X1TS U1399 ( .A0(n883), .A1(intDX_EWSW[10]), .B0(n1113), .B1(
intDX_EWSW[11]), .Y(n1112) );
INVX2TS U1400 ( .A(n1112), .Y(n1013) );
OAI2BB1X1TS U1401 ( .A0N(n1544), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n994) );
OAI22X1TS U1402 ( .A0(intDY_EWSW[4]), .A1(n994), .B0(n1544), .B1(
intDY_EWSW[5]), .Y(n1005) );
OAI2BB1X1TS U1403 ( .A0N(n1523), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n995) );
OAI22X1TS U1404 ( .A0(intDY_EWSW[6]), .A1(n995), .B0(n1523), .B1(
intDY_EWSW[7]), .Y(n1004) );
OAI2BB2XLTS U1405 ( .B0(intDY_EWSW[0]), .B1(n996), .A0N(intDX_EWSW[1]),
.A1N(n1585), .Y(n998) );
AOI222X1TS U1406 ( .A0(intDY_EWSW[4]), .A1(n1520), .B0(n1001), .B1(n1000),
.C0(intDY_EWSW[5]), .C1(n1544), .Y(n1003) );
AOI22X1TS U1407 ( .A0(intDY_EWSW[7]), .A1(n1523), .B0(intDY_EWSW[6]), .B1(
n1550), .Y(n1002) );
OAI32X1TS U1408 ( .A0(n1005), .A1(n1004), .A2(n1003), .B0(n1002), .B1(n1004),
.Y(n1023) );
OA22X1TS U1409 ( .A0(n1528), .A1(intDX_EWSW[14]), .B0(n1583), .B1(
intDX_EWSW[15]), .Y(n1020) );
OAI2BB2XLTS U1410 ( .B0(intDY_EWSW[12]), .B1(n1007), .A0N(intDX_EWSW[13]),
.A1N(n1568), .Y(n1019) );
AOI22X1TS U1411 ( .A0(intDX_EWSW[11]), .A1(n1557), .B0(intDX_EWSW[10]), .B1(
n1009), .Y(n1015) );
AOI21X1TS U1412 ( .A0(n1012), .A1(n1011), .B0(n1022), .Y(n1014) );
OAI2BB2XLTS U1413 ( .B0(n1015), .B1(n1022), .A0N(n1014), .A1N(n1013), .Y(
n1018) );
OAI2BB2XLTS U1414 ( .B0(intDY_EWSW[14]), .B1(n1016), .A0N(intDX_EWSW[15]),
.A1N(n1583), .Y(n1017) );
AOI211X1TS U1415 ( .A0(n1020), .A1(n1019), .B0(n1018), .C0(n1017), .Y(n1021)
);
OAI31X1TS U1416 ( .A0(n1024), .A1(n1023), .A2(n1022), .B0(n1021), .Y(n1027)
);
OA22X1TS U1417 ( .A0(n1530), .A1(intDX_EWSW[22]), .B0(n936), .B1(
intDX_EWSW[23]), .Y(n1039) );
OAI2BB2XLTS U1418 ( .B0(intDY_EWSW[20]), .B1(n1028), .A0N(intDX_EWSW[21]),
.A1N(n1569), .Y(n1038) );
AOI22X1TS U1419 ( .A0(intDX_EWSW[17]), .A1(n1584), .B0(intDX_EWSW[16]), .B1(
n1030), .Y(n1033) );
OAI32X1TS U1420 ( .A0(n1104), .A1(n1034), .A2(n1033), .B0(n1032), .B1(n1034),
.Y(n1037) );
AOI211X1TS U1421 ( .A0(n1039), .A1(n1038), .B0(n1037), .C0(n1036), .Y(n1044)
);
NAND4BBX1TS U1422 ( .AN(n1097), .BN(n1042), .C(n1041), .D(n1040), .Y(n1043)
);
AOI32X1TS U1423 ( .A0(n1046), .A1(n1045), .A2(n1044), .B0(n1043), .B1(n1046),
.Y(n1047) );
AND2X2TS U1424 ( .A(Shift_reg_FLAGS_7_6), .B(n1047), .Y(n1147) );
INVX2TS U1425 ( .A(n1147), .Y(n1132) );
INVX2TS U1426 ( .A(Shift_reg_FLAGS_7_6), .Y(n1050) );
BUFX3TS U1427 ( .A(n1050), .Y(n1092) );
AOI22X1TS U1428 ( .A0(intDX_EWSW[0]), .A1(n1048), .B0(DmP_EXP_EWSW[0]), .B1(
n1092), .Y(n1049) );
BUFX3TS U1429 ( .A(n1146), .Y(n1133) );
AOI22X1TS U1430 ( .A0(intDX_EWSW[14]), .A1(n1048), .B0(DmP_EXP_EWSW[14]),
.B1(n1133), .Y(n1051) );
BUFX3TS U1431 ( .A(n1146), .Y(n1313) );
AOI22X1TS U1432 ( .A0(intDX_EWSW[22]), .A1(n1048), .B0(DmP_EXP_EWSW[22]),
.B1(n1313), .Y(n1052) );
AOI22X1TS U1433 ( .A0(intDX_EWSW[19]), .A1(n1048), .B0(DmP_EXP_EWSW[19]),
.B1(n1313), .Y(n1053) );
AOI22X1TS U1434 ( .A0(intDX_EWSW[16]), .A1(n872), .B0(DmP_EXP_EWSW[16]),
.B1(n1313), .Y(n1054) );
AOI22X1TS U1435 ( .A0(intDX_EWSW[4]), .A1(n872), .B0(DmP_EXP_EWSW[4]), .B1(
n1133), .Y(n1055) );
AOI22X1TS U1436 ( .A0(intDX_EWSW[5]), .A1(n872), .B0(DmP_EXP_EWSW[5]), .B1(
n1133), .Y(n1056) );
AOI22X1TS U1437 ( .A0(intDX_EWSW[6]), .A1(n872), .B0(DmP_EXP_EWSW[6]), .B1(
n1133), .Y(n1057) );
AOI22X1TS U1438 ( .A0(intDX_EWSW[17]), .A1(n872), .B0(DmP_EXP_EWSW[17]),
.B1(n1313), .Y(n1058) );
AOI22X1TS U1439 ( .A0(intDX_EWSW[13]), .A1(n872), .B0(DmP_EXP_EWSW[13]),
.B1(n1313), .Y(n1059) );
AOI22X1TS U1440 ( .A0(intDX_EWSW[21]), .A1(n872), .B0(DmP_EXP_EWSW[21]),
.B1(n1313), .Y(n1060) );
AOI22X1TS U1441 ( .A0(intDX_EWSW[10]), .A1(n872), .B0(DmP_EXP_EWSW[10]),
.B1(n1092), .Y(n1061) );
AOI22X1TS U1442 ( .A0(intDX_EWSW[20]), .A1(n872), .B0(DmP_EXP_EWSW[20]),
.B1(n1313), .Y(n1062) );
AOI22X1TS U1443 ( .A0(intDX_EWSW[9]), .A1(n872), .B0(DmP_EXP_EWSW[9]), .B1(
n1133), .Y(n1063) );
BUFX3TS U1444 ( .A(n872), .Y(n1151) );
AOI22X1TS U1445 ( .A0(intDX_EWSW[7]), .A1(n1151), .B0(DmP_EXP_EWSW[7]), .B1(
n1133), .Y(n1064) );
AOI22X1TS U1446 ( .A0(intDX_EWSW[18]), .A1(n1151), .B0(DmP_EXP_EWSW[18]),
.B1(n1313), .Y(n1065) );
AOI22X1TS U1447 ( .A0(intDX_EWSW[1]), .A1(n1151), .B0(DmP_EXP_EWSW[1]), .B1(
n1133), .Y(n1066) );
AOI22X1TS U1448 ( .A0(intDX_EWSW[12]), .A1(n1151), .B0(DmP_EXP_EWSW[12]),
.B1(n1133), .Y(n1067) );
AOI22X1TS U1449 ( .A0(intDX_EWSW[8]), .A1(n1151), .B0(DmP_EXP_EWSW[8]), .B1(
n1133), .Y(n1068) );
AOI22X1TS U1450 ( .A0(intDX_EWSW[2]), .A1(n1151), .B0(DmP_EXP_EWSW[2]), .B1(
n1133), .Y(n1069) );
AOI22X1TS U1451 ( .A0(intDX_EWSW[11]), .A1(n1151), .B0(DmP_EXP_EWSW[11]),
.B1(n1133), .Y(n1070) );
AOI22X1TS U1452 ( .A0(intDX_EWSW[3]), .A1(n1151), .B0(DmP_EXP_EWSW[3]), .B1(
n1133), .Y(n1071) );
AOI22X1TS U1453 ( .A0(DmP_EXP_EWSW[27]), .A1(n1313), .B0(intDX_EWSW[27]),
.B1(n1151), .Y(n1072) );
AOI22X1TS U1454 ( .A0(intDX_EWSW[15]), .A1(n1048), .B0(DmP_EXP_EWSW[15]),
.B1(n1313), .Y(n1073) );
BUFX3TS U1455 ( .A(n1147), .Y(n1137) );
AOI22X1TS U1456 ( .A0(intDX_EWSW[18]), .A1(n1150), .B0(DMP_EXP_EWSW[18]),
.B1(n1092), .Y(n1075) );
AOI22X1TS U1457 ( .A0(intDX_EWSW[17]), .A1(n1137), .B0(DMP_EXP_EWSW[17]),
.B1(n1092), .Y(n1076) );
AOI22X1TS U1458 ( .A0(intDX_EWSW[22]), .A1(n1150), .B0(DMP_EXP_EWSW[22]),
.B1(n1092), .Y(n1077) );
AOI22X1TS U1459 ( .A0(intDX_EWSW[12]), .A1(n1150), .B0(DMP_EXP_EWSW[12]),
.B1(n1146), .Y(n1078) );
AOI22X1TS U1460 ( .A0(intDX_EWSW[14]), .A1(n1150), .B0(DMP_EXP_EWSW[14]),
.B1(n1146), .Y(n1079) );
AOI22X1TS U1461 ( .A0(intDX_EWSW[21]), .A1(n1150), .B0(DMP_EXP_EWSW[21]),
.B1(n1092), .Y(n1080) );
AOI22X1TS U1462 ( .A0(intDX_EWSW[13]), .A1(n1150), .B0(DMP_EXP_EWSW[13]),
.B1(n1146), .Y(n1081) );
AOI22X1TS U1463 ( .A0(intDX_EWSW[15]), .A1(n1150), .B0(DMP_EXP_EWSW[15]),
.B1(n1146), .Y(n1082) );
AOI22X1TS U1464 ( .A0(intDX_EWSW[28]), .A1(n1137), .B0(DMP_EXP_EWSW[28]),
.B1(n1092), .Y(n1083) );
AOI22X1TS U1465 ( .A0(n935), .A1(n1313), .B0(intDX_EWSW[27]), .B1(n1137),
.Y(n1084) );
AOI22X1TS U1466 ( .A0(intDX_EWSW[30]), .A1(n1137), .B0(DMP_EXP_EWSW[30]),
.B1(n1092), .Y(n1085) );
AOI22X1TS U1467 ( .A0(intDX_EWSW[29]), .A1(n1150), .B0(DMP_EXP_EWSW[29]),
.B1(n1092), .Y(n1086) );
AOI22X1TS U1468 ( .A0(intDX_EWSW[1]), .A1(n1150), .B0(DMP_EXP_EWSW[1]), .B1(
n1050), .Y(n1087) );
AOI22X1TS U1469 ( .A0(intDX_EWSW[16]), .A1(n1137), .B0(DMP_EXP_EWSW[16]),
.B1(n1092), .Y(n1088) );
AOI22X1TS U1470 ( .A0(intDX_EWSW[19]), .A1(n1137), .B0(DMP_EXP_EWSW[19]),
.B1(n1092), .Y(n1089) );
AOI22X1TS U1471 ( .A0(intDX_EWSW[0]), .A1(n1137), .B0(DMP_EXP_EWSW[0]), .B1(
n1050), .Y(n1090) );
AOI22X1TS U1472 ( .A0(intDX_EWSW[11]), .A1(n1150), .B0(DMP_EXP_EWSW[11]),
.B1(n1092), .Y(n1091) );
AOI22X1TS U1473 ( .A0(intDX_EWSW[20]), .A1(n1137), .B0(DMP_EXP_EWSW[20]),
.B1(n1092), .Y(n1093) );
AOI22X1TS U1474 ( .A0(DMP_EXP_EWSW[23]), .A1(n1313), .B0(intDX_EWSW[23]),
.B1(n1137), .Y(n1095) );
OAI22X1TS U1475 ( .A0(n1585), .A1(intDX_EWSW[1]), .B0(n1581), .B1(
intDX_EWSW[25]), .Y(n1096) );
AOI221X1TS U1476 ( .A0(n1585), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1581), .C0(n1096), .Y(n1102) );
OAI22X1TS U1477 ( .A0(n1575), .A1(intDX_EWSW[28]), .B0(n1532), .B1(
intDX_EWSW[29]), .Y(n1098) );
AOI221X1TS U1478 ( .A0(n1575), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1532), .C0(n1098), .Y(n1100) );
AOI2BB2XLTS U1479 ( .B0(intDX_EWSW[7]), .B1(n1574), .A0N(n1574), .A1N(
intDX_EWSW[7]), .Y(n1099) );
NAND4XLTS U1480 ( .A(n1102), .B(n1101), .C(n1100), .D(n1099), .Y(n1131) );
OAI22X1TS U1481 ( .A0(n1588), .A1(intDX_EWSW[30]), .B0(n1584), .B1(
intDX_EWSW[17]), .Y(n1103) );
OAI22X1TS U1482 ( .A0(n1573), .A1(intDX_EWSW[20]), .B0(n1569), .B1(
intDX_EWSW[21]), .Y(n1105) );
OAI22X1TS U1483 ( .A0(n1530), .A1(intDX_EWSW[22]), .B0(n936), .B1(
intDX_EWSW[23]), .Y(n1106) );
NAND4XLTS U1484 ( .A(n1110), .B(n1109), .C(n1108), .D(n1107), .Y(n1130) );
OAI22X1TS U1485 ( .A0(n1515), .A1(intDX_EWSW[24]), .B0(n1567), .B1(
intDX_EWSW[9]), .Y(n1111) );
AOI221X1TS U1486 ( .A0(n1515), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1567), .C0(n1111), .Y(n1119) );
OAI22X1TS U1487 ( .A0(n1572), .A1(intDX_EWSW[12]), .B0(n1568), .B1(
intDX_EWSW[13]), .Y(n1114) );
OAI22X1TS U1488 ( .A0(n1528), .A1(intDX_EWSW[14]), .B0(n1583), .B1(
intDX_EWSW[15]), .Y(n1115) );
NAND4XLTS U1489 ( .A(n1119), .B(n1118), .C(n1117), .D(n1116), .Y(n1129) );
OAI22X1TS U1490 ( .A0(n1529), .A1(intDX_EWSW[16]), .B0(n1582), .B1(
intDX_EWSW[0]), .Y(n1120) );
AOI221X1TS U1491 ( .A0(n1529), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1582), .C0(n1120), .Y(n1127) );
OAI22X1TS U1492 ( .A0(n1570), .A1(intDX_EWSW[2]), .B0(n1565), .B1(
intDX_EWSW[3]), .Y(n1121) );
OAI22X1TS U1493 ( .A0(n1571), .A1(intDX_EWSW[4]), .B0(n1527), .B1(
intDX_EWSW[5]), .Y(n1122) );
AOI221X1TS U1494 ( .A0(n1571), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1527), .C0(n1122), .Y(n1125) );
OAI22X1TS U1495 ( .A0(n1586), .A1(intDX_EWSW[8]), .B0(n1566), .B1(
intDX_EWSW[6]), .Y(n1123) );
AOI221X1TS U1496 ( .A0(n1586), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1566), .C0(n1123), .Y(n1124) );
NAND4XLTS U1497 ( .A(n1127), .B(n1126), .C(n1125), .D(n1124), .Y(n1128) );
NOR4X1TS U1498 ( .A(n1131), .B(n1130), .C(n1129), .D(n1128), .Y(n1371) );
CLKXOR2X2TS U1499 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1369) );
INVX2TS U1500 ( .A(n1369), .Y(n1136) );
AOI22X1TS U1501 ( .A0(intDX_EWSW[31]), .A1(n1134), .B0(SIGN_FLAG_EXP), .B1(
n1133), .Y(n1135) );
INVX2TS U1502 ( .A(n872), .Y(n1149) );
AOI22X1TS U1503 ( .A0(intDX_EWSW[8]), .A1(n1137), .B0(DMP_EXP_EWSW[8]), .B1(
n1146), .Y(n1138) );
AOI22X1TS U1504 ( .A0(intDX_EWSW[3]), .A1(n1137), .B0(DMP_EXP_EWSW[3]), .B1(
n1146), .Y(n1139) );
AOI22X1TS U1505 ( .A0(intDX_EWSW[7]), .A1(n1150), .B0(DMP_EXP_EWSW[7]), .B1(
n1146), .Y(n1140) );
AOI22X1TS U1506 ( .A0(intDX_EWSW[9]), .A1(n1150), .B0(DMP_EXP_EWSW[9]), .B1(
n1146), .Y(n1141) );
AOI22X1TS U1507 ( .A0(intDX_EWSW[6]), .A1(n1150), .B0(DMP_EXP_EWSW[6]), .B1(
n1146), .Y(n1142) );
AOI22X1TS U1508 ( .A0(intDX_EWSW[2]), .A1(n1150), .B0(DMP_EXP_EWSW[2]), .B1(
n1146), .Y(n1143) );
AOI22X1TS U1509 ( .A0(intDX_EWSW[5]), .A1(n1147), .B0(DMP_EXP_EWSW[5]), .B1(
n1146), .Y(n1144) );
AOI22X1TS U1510 ( .A0(intDX_EWSW[4]), .A1(n1150), .B0(DMP_EXP_EWSW[4]), .B1(
n1146), .Y(n1145) );
AOI22X1TS U1511 ( .A0(intDX_EWSW[10]), .A1(n1147), .B0(DMP_EXP_EWSW[10]),
.B1(n1146), .Y(n1148) );
AOI222X1TS U1512 ( .A0(n1151), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1050), .C0(intDY_EWSW[23]), .C1(n1137), .Y(n1152) );
INVX2TS U1513 ( .A(n1152), .Y(n564) );
NAND2X2TS U1514 ( .A(n904), .B(n914), .Y(n1349) );
NOR2BX2TS U1515 ( .AN(n1304), .B(n1303), .Y(n1169) );
NOR2BX1TS U1516 ( .AN(n1169), .B(Raw_mant_NRM_SWR[18]), .Y(n1291) );
NOR2BX1TS U1517 ( .AN(n1291), .B(n1292), .Y(n1166) );
NOR2X2TS U1518 ( .A(Raw_mant_NRM_SWR[13]), .B(n1293), .Y(n1178) );
NOR2X2TS U1519 ( .A(Raw_mant_NRM_SWR[12]), .B(n1171), .Y(n1298) );
NAND2X1TS U1520 ( .A(n1298), .B(n1521), .Y(n1153) );
NOR2X1TS U1521 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1155)
);
NOR3X1TS U1522 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1153),
.Y(n1156) );
OAI22X1TS U1523 ( .A0(n1154), .A1(n1153), .B0(n1155), .B1(n1163), .Y(n1161)
);
NOR2X1TS U1524 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1158)
);
NOR2X2TS U1525 ( .A(Raw_mant_NRM_SWR[6]), .B(n1163), .Y(n1299) );
NAND2X1TS U1526 ( .A(n1299), .B(n1155), .Y(n1159) );
OAI21X1TS U1527 ( .A0(n1158), .A1(n1159), .B0(n1157), .Y(n1182) );
INVX2TS U1528 ( .A(n1159), .Y(n1300) );
OAI31X1TS U1529 ( .A0(n1161), .A1(n1182), .A2(n1160), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1290) );
INVX2TS U1530 ( .A(n1163), .Y(n1173) );
AOI22X1TS U1531 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1169), .B0(n1298), .B1(
Raw_mant_NRM_SWR[10]), .Y(n1179) );
OAI32X1TS U1532 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1524), .B0(n1548), .B1(Raw_mant_NRM_SWR[3]), .Y(n1164) );
NAND2X1TS U1533 ( .A(Raw_mant_NRM_SWR[12]), .B(n1178), .Y(n1295) );
NAND2X1TS U1534 ( .A(Raw_mant_NRM_SWR[14]), .B(n1166), .Y(n1184) );
AOI32X1TS U1535 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1511), .A2(n1543), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1511), .Y(n1167) );
OAI31X1TS U1536 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1171), .A2(n1525), .B0(
n1170), .Y(n1172) );
NAND2X2TS U1537 ( .A(n905), .B(n1188), .Y(n1336) );
NOR2BX1TS U1538 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1195) );
BUFX3TS U1539 ( .A(n1195), .Y(n1333) );
AOI22X1TS U1540 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n910), .B0(n1333), .B1(n934), .Y(n1194) );
NOR2X1TS U1541 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1175) );
AOI32X1TS U1542 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1175), .A2(n1174), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1175), .Y(n1176) );
INVX2TS U1543 ( .A(n1178), .Y(n1180) );
OAI31X1TS U1544 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1514), .A2(n1180), .B0(
n1179), .Y(n1181) );
NOR4BX2TS U1545 ( .AN(n1184), .B(n1183), .C(n1182), .D(n1181), .Y(n1206) );
NOR2X1TS U1546 ( .A(n1206), .B(n904), .Y(n1307) );
AOI21X1TS U1547 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n904), .B0(n1307), .Y(
n1187) );
BUFX3TS U1548 ( .A(n1186), .Y(n1346) );
NOR2X2TS U1549 ( .A(n1186), .B(n1187), .Y(n1343) );
NOR2X4TS U1550 ( .A(n1188), .B(n904), .Y(n1334) );
AOI22X1TS U1551 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1334), .B0(n1333), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1190) );
AOI22X1TS U1552 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n909), .B0(n911), .B1(n933),
.Y(n1189) );
NAND2X1TS U1553 ( .A(n1190), .B(n1189), .Y(n1215) );
AOI22X1TS U1554 ( .A0(n1346), .A1(Data_array_SWR[1]), .B0(n1343), .B1(n1215),
.Y(n1193) );
NAND2X1TS U1555 ( .A(n1206), .B(n1334), .Y(n1191) );
INVX2TS U1556 ( .A(n1270), .Y(n1341) );
NAND2X1TS U1557 ( .A(Raw_mant_NRM_SWR[23]), .B(n1341), .Y(n1192) );
BUFX3TS U1558 ( .A(n1195), .Y(n1255) );
AOI22X1TS U1559 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1334), .B0(n1333), .B1(
n930), .Y(n1197) );
AOI22X1TS U1560 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n909), .B0(n911), .B1(n932),
.Y(n1196) );
NAND2X1TS U1561 ( .A(n1197), .B(n1196), .Y(n1219) );
AOI22X1TS U1562 ( .A0(n1346), .A1(Data_array_SWR[5]), .B0(n1343), .B1(n1219),
.Y(n1199) );
NAND2X1TS U1563 ( .A(Raw_mant_NRM_SWR[19]), .B(n1341), .Y(n1198) );
AOI22X1TS U1564 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1334), .B0(n1333), .B1(
n932), .Y(n1201) );
AOI22X1TS U1565 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n909), .B0(n911), .B1(n926),
.Y(n1200) );
NAND2X1TS U1566 ( .A(n1201), .B(n1200), .Y(n1205) );
AOI22X1TS U1567 ( .A0(n1346), .A1(Data_array_SWR[4]), .B0(n1343), .B1(n1205),
.Y(n1203) );
NAND2X1TS U1568 ( .A(Raw_mant_NRM_SWR[20]), .B(n1341), .Y(n1202) );
INVX2TS U1569 ( .A(n1343), .Y(n1204) );
AOI22X1TS U1570 ( .A0(n1346), .A1(Data_array_SWR[6]), .B0(n1185), .B1(n1205),
.Y(n1209) );
INVX2TS U1571 ( .A(n1334), .Y(n1265) );
NAND2X1TS U1572 ( .A(Raw_mant_NRM_SWR[16]), .B(n1207), .Y(n1208) );
AOI22X1TS U1573 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1334), .B0(n1333), .B1(
n933), .Y(n1211) );
AOI22X1TS U1574 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n909), .B0(n911), .B1(n934),
.Y(n1210) );
NAND2X1TS U1575 ( .A(n1211), .B(n1210), .Y(n1342) );
AOI22X1TS U1576 ( .A0(n1346), .A1(Data_array_SWR[2]), .B0(n1185), .B1(n1342),
.Y(n1213) );
NAND2X1TS U1577 ( .A(Raw_mant_NRM_SWR[20]), .B(n1207), .Y(n1212) );
AOI22X1TS U1578 ( .A0(n1346), .A1(Data_array_SWR[3]), .B0(n1185), .B1(n1215),
.Y(n1217) );
NAND2X1TS U1579 ( .A(Raw_mant_NRM_SWR[19]), .B(n1207), .Y(n1216) );
AOI22X1TS U1580 ( .A0(n1346), .A1(Data_array_SWR[7]), .B0(n1185), .B1(n1219),
.Y(n1221) );
NAND2X1TS U1581 ( .A(Raw_mant_NRM_SWR[15]), .B(n1207), .Y(n1220) );
AOI22X1TS U1582 ( .A0(n1346), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1207), .Y(n1223) );
AOI22X1TS U1583 ( .A0(n911), .A1(DmP_mant_SHT1_SW[21]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1225) );
AOI21X1TS U1584 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n910), .B0(n1226), .Y(n1329)
);
OAI22X1TS U1585 ( .A0(n1247), .A1(n943), .B0(n1590), .B1(n1270), .Y(n1227)
);
AOI21X1TS U1586 ( .A0(n1186), .A1(Data_array_SWR[21]), .B0(n1227), .Y(n1228)
);
AOI22X1TS U1587 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1334), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1333), .Y(n1229) );
AOI21X1TS U1588 ( .A0(n927), .A1(n912), .B0(n1230), .Y(n1332) );
INVX2TS U1589 ( .A(n1207), .Y(n1256) );
OAI22X1TS U1590 ( .A0(n1235), .A1(n1204), .B0(n1536), .B1(n1256), .Y(n1231)
);
AOI21X1TS U1591 ( .A0(n1186), .A1(Data_array_SWR[16]), .B0(n1231), .Y(n1232)
);
AOI22X1TS U1592 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1334), .B0(n1333), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1233) );
AOI21X1TS U1593 ( .A0(n912), .A1(DmP_mant_SHT1_SW[18]), .B0(n1234), .Y(n1259) );
OAI22X1TS U1594 ( .A0(n1235), .A1(n943), .B0(n1536), .B1(n1270), .Y(n1236)
);
AOI21X1TS U1595 ( .A0(n1186), .A1(Data_array_SWR[18]), .B0(n1236), .Y(n1237)
);
AOI22X1TS U1596 ( .A0(n1346), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1207), .Y(n1239) );
OA22X1TS U1597 ( .A0(n1535), .A1(n1270), .B0(n1246), .B1(n1204), .Y(n1238)
);
AOI22X1TS U1598 ( .A0(n1186), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1207), .Y(n1242) );
OA22X1TS U1599 ( .A0(n1537), .A1(n1270), .B0(n1254), .B1(n1204), .Y(n1241)
);
AOI22X1TS U1600 ( .A0(n1346), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1207), .Y(n1245) );
OA22X1TS U1601 ( .A0(n1514), .A1(n1270), .B0(n1243), .B1(n1204), .Y(n1244)
);
AOI22X1TS U1602 ( .A0(n1186), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1207), .Y(n1249) );
OA22X1TS U1603 ( .A0(n1549), .A1(n1270), .B0(n1247), .B1(n1204), .Y(n1248)
);
AOI22X1TS U1604 ( .A0(n1346), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1207), .Y(n1253) );
OA22X1TS U1605 ( .A0(n1522), .A1(n1270), .B0(n1251), .B1(n1204), .Y(n1252)
);
OAI22X1TS U1606 ( .A0(n1267), .A1(n1204), .B0(n1548), .B1(n1256), .Y(n1257)
);
AOI21X1TS U1607 ( .A0(n1186), .A1(Data_array_SWR[20]), .B0(n1257), .Y(n1258)
);
AOI22X1TS U1608 ( .A0(n911), .A1(DmP_mant_SHT1_SW[8]), .B0(n1333), .B1(n929),
.Y(n1260) );
AOI21X1TS U1609 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n910), .B0(n1261), .Y(n1340) );
OAI22X1TS U1610 ( .A0(n1262), .A1(n943), .B0(n1513), .B1(n1270), .Y(n1263)
);
AOI21X1TS U1611 ( .A0(n1186), .A1(Data_array_SWR[8]), .B0(n1263), .Y(n1264)
);
OAI22X1TS U1612 ( .A0(n1594), .A1(n1336), .B0(n1524), .B1(n1265), .Y(n1266)
);
OAI22X1TS U1613 ( .A0(n1327), .A1(n1204), .B0(n1267), .B1(n943), .Y(n1268)
);
AOI21X1TS U1614 ( .A0(n1186), .A1(Data_array_SWR[22]), .B0(n1268), .Y(n1269)
);
INVX2TS U1615 ( .A(n1271), .Y(n1281) );
AND4X1TS U1616 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1272), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1273) );
INVX2TS U1617 ( .A(n1277), .Y(n1278) );
OAI2BB2XLTS U1618 ( .B0(n1410), .B1(n1281), .A0N(n1466), .A1N(
final_result_ieee[30]), .Y(n754) );
INVX2TS U1619 ( .A(n1282), .Y(n1411) );
OAI2BB2XLTS U1620 ( .B0(n1283), .B1(n1410), .A0N(n1466), .A1N(
final_result_ieee[31]), .Y(n543) );
INVX2TS U1621 ( .A(OP_FLAG_SFG), .Y(n1384) );
AOI22X1TS U1622 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n1406), .B0(n967), .B1(n958),
.Y(n1394) );
NAND2X1TS U1623 ( .A(n1394), .B(DMP_SFG[0]), .Y(n1397) );
INVX2TS U1624 ( .A(n1397), .Y(n1284) );
AOI22X1TS U1625 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n967), .B0(n1406), .B1(n965),
.Y(intadd_67_B_2_) );
BUFX3TS U1626 ( .A(n967), .Y(n1403) );
AOI21X1TS U1627 ( .A0(intadd_67_A_3_), .A1(n921), .B0(intadd_67_B_2_), .Y(
n1285) );
AOI2BB2X1TS U1628 ( .B0(DMP_SFG[4]), .B1(n1285), .A0N(intadd_67_A_3_), .A1N(
n921), .Y(n1286) );
INVX2TS U1629 ( .A(n1288), .Y(n1289) );
NAND2X1TS U1630 ( .A(n1551), .B(n1289), .Y(DP_OP_15J59_123_4652_n8) );
MX2X1TS U1631 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n611) );
MX2X1TS U1632 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n905),
.Y(n616) );
MX2X1TS U1633 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n621) );
MX2X1TS U1634 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n626) );
MX2X1TS U1635 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n631) );
MX2X1TS U1636 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n636) );
MX2X1TS U1637 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n641) );
MX2X1TS U1638 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n905),
.Y(n646) );
OAI2BB1X1TS U1639 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n875), .B0(n1290), .Y(
n512) );
OAI32X1TS U1640 ( .A0(n1390), .A1(Raw_mant_NRM_SWR[14]), .A2(n1292), .B0(
n1291), .B1(n1390), .Y(n1296) );
AOI21X1TS U1641 ( .A0(n1298), .A1(Raw_mant_NRM_SWR[10]), .B0(n1297), .Y(
n1351) );
AOI22X1TS U1642 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1300), .B0(n1299), .B1(
Raw_mant_NRM_SWR[5]), .Y(n1302) );
OAI211XLTS U1643 ( .A0(n1304), .A1(n1303), .B0(n1302), .C0(n1301), .Y(n1305)
);
OAI21X1TS U1644 ( .A0(n1306), .A1(n1305), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1347) );
OAI2BB1X1TS U1645 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1390), .B0(n1347),
.Y(n514) );
OA22X1TS U1646 ( .A0(n1309), .A1(n1308), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n755) );
OA21XLTS U1647 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1410),
.Y(n558) );
INVX2TS U1648 ( .A(n1312), .Y(n1311) );
AOI22X1TS U1649 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1311), .B1(n1526), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1650 ( .A(n1311), .B(n1310), .Y(n871) );
AOI22X1TS U1651 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1312), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1526), .Y(n1316) );
AO22XLTS U1652 ( .A0(n1314), .A1(Shift_reg_FLAGS_7_6), .B0(n1315), .B1(n1316), .Y(n869) );
AOI22X1TS U1653 ( .A0(n1315), .A1(n1313), .B0(n1611), .B1(n1314), .Y(n868)
);
AOI22X1TS U1654 ( .A0(n1315), .A1(n1611), .B0(n914), .B1(n1314), .Y(n867) );
CLKBUFX2TS U1655 ( .A(n1649), .Y(n1395) );
AOI22X1TS U1656 ( .A0(n1315), .A1(n1649), .B0(n1390), .B1(n1314), .Y(n864)
);
AOI22X1TS U1657 ( .A0(n1315), .A1(n1390), .B0(n1466), .B1(n1314), .Y(n863)
);
AND2X2TS U1658 ( .A(beg_OP), .B(n1316), .Y(n1319) );
INVX2TS U1659 ( .A(n1323), .Y(n1317) );
BUFX3TS U1660 ( .A(n1319), .Y(n1323) );
INVX2TS U1661 ( .A(n1323), .Y(n1318) );
BUFX3TS U1662 ( .A(n1319), .Y(n1326) );
BUFX3TS U1663 ( .A(n1319), .Y(n1321) );
INVX2TS U1664 ( .A(n1323), .Y(n1325) );
INVX2TS U1665 ( .A(n1323), .Y(n1320) );
INVX2TS U1666 ( .A(n1323), .Y(n1322) );
AOI21X1TS U1667 ( .A0(n910), .A1(Raw_mant_NRM_SWR[0]), .B0(n912), .Y(n1328)
);
OAI2BB2XLTS U1668 ( .B0(n1328), .B1(n944), .A0N(n1186), .A1N(
Data_array_SWR[25]), .Y(n796) );
OAI2BB2XLTS U1669 ( .B0(n1327), .B1(n944), .A0N(n1186), .A1N(
Data_array_SWR[24]), .Y(n795) );
AOI22X1TS U1670 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1334), .B0(n1333), .B1(
n925), .Y(n1330) );
AOI21X1TS U1671 ( .A0(n912), .A1(n924), .B0(n1331), .Y(n1338) );
AOI22X1TS U1672 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1334), .B0(n1333), .B1(
n928), .Y(n1335) );
AOI21X1TS U1673 ( .A0(n912), .A1(DmP_mant_SHT1_SW[10]), .B0(n1337), .Y(n1339) );
AOI22X1TS U1674 ( .A0(n1346), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1341), .Y(n1345) );
AOI22X1TS U1675 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n910), .B0(n1343), .B1(
n1342), .Y(n1344) );
NAND2X1TS U1676 ( .A(n1345), .B(n1344), .Y(n771) );
NAND2X1TS U1677 ( .A(n1348), .B(n1347), .Y(n770) );
AOI21X1TS U1678 ( .A0(n945), .A1(Shift_amount_SHT1_EWR[3]), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1350) );
OAI22X1TS U1679 ( .A0(n1351), .A1(n1350), .B0(n1349), .B1(n1542), .Y(n769)
);
INVX2TS U1680 ( .A(n1611), .Y(n1373) );
AOI21X1TS U1681 ( .A0(DMP_EXP_EWSW[23]), .A1(n952), .B0(n1356), .Y(n1352) );
AOI2BB2XLTS U1682 ( .B0(n1373), .B1(n1352), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1373), .Y(n766) );
NOR2X1TS U1683 ( .A(n1533), .B(DMP_EXP_EWSW[24]), .Y(n1355) );
AOI21X1TS U1684 ( .A0(DMP_EXP_EWSW[24]), .A1(n1533), .B0(n1355), .Y(n1353)
);
XNOR2X1TS U1685 ( .A(n1356), .B(n1353), .Y(n1354) );
AO22XLTS U1686 ( .A0(n1373), .A1(n1354), .B0(n1611), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n765) );
OAI22X1TS U1687 ( .A0(n1356), .A1(n1355), .B0(DmP_EXP_EWSW[24]), .B1(n1534),
.Y(n1359) );
NAND2X1TS U1688 ( .A(DmP_EXP_EWSW[25]), .B(n1595), .Y(n1360) );
XNOR2X1TS U1689 ( .A(n1359), .B(n1357), .Y(n1358) );
AO22XLTS U1690 ( .A0(n1373), .A1(n1358), .B0(n1386), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n764) );
AOI22X1TS U1691 ( .A0(DMP_EXP_EWSW[25]), .A1(n1608), .B0(n1360), .B1(n1359),
.Y(n1363) );
NOR2X1TS U1692 ( .A(n1603), .B(DMP_EXP_EWSW[26]), .Y(n1364) );
AOI21X1TS U1693 ( .A0(DMP_EXP_EWSW[26]), .A1(n1603), .B0(n1364), .Y(n1361)
);
XNOR2X1TS U1694 ( .A(n1363), .B(n1361), .Y(n1362) );
AO22XLTS U1695 ( .A0(n1373), .A1(n1362), .B0(n1375), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n763) );
OAI22X1TS U1696 ( .A0(n1364), .A1(n1363), .B0(DmP_EXP_EWSW[26]), .B1(n1607),
.Y(n1366) );
XNOR2X1TS U1697 ( .A(DmP_EXP_EWSW[27]), .B(n935), .Y(n1365) );
XOR2XLTS U1698 ( .A(n1366), .B(n1365), .Y(n1367) );
AO22XLTS U1699 ( .A0(n1373), .A1(n1367), .B0(n1376), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n762) );
OAI222X1TS U1700 ( .A0(n1378), .A1(n1606), .B0(n1534), .B1(
Shift_reg_FLAGS_7_6), .C0(n1515), .C1(n1380), .Y(n729) );
OAI222X1TS U1701 ( .A0(n1378), .A1(n1538), .B0(n1595), .B1(
Shift_reg_FLAGS_7_6), .C0(n1581), .C1(n1380), .Y(n728) );
OAI222X1TS U1702 ( .A0(n1378), .A1(n1539), .B0(n1607), .B1(
Shift_reg_FLAGS_7_6), .C0(n1587), .C1(n1380), .Y(n727) );
OAI21XLTS U1703 ( .A0(n1369), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1368) );
AOI21X1TS U1704 ( .A0(n1369), .A1(intDX_EWSW[31]), .B0(n1368), .Y(n1370) );
AO21XLTS U1705 ( .A0(OP_FLAG_EXP), .A1(n1050), .B0(n1370), .Y(n722) );
AO22XLTS U1706 ( .A0(n1373), .A1(DMP_EXP_EWSW[0]), .B0(n1377), .B1(
DMP_SHT1_EWSW[0]), .Y(n719) );
AO22XLTS U1707 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1374), .B1(
DMP_SHT2_EWSW[0]), .Y(n718) );
CLKBUFX2TS U1708 ( .A(n1372), .Y(n1388) );
AO22XLTS U1709 ( .A0(n1373), .A1(DMP_EXP_EWSW[1]), .B0(n1386), .B1(
DMP_SHT1_EWSW[1]), .Y(n716) );
AO22XLTS U1710 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n914), .B1(
DMP_SHT2_EWSW[1]), .Y(n715) );
AO22XLTS U1711 ( .A0(n1373), .A1(DMP_EXP_EWSW[2]), .B0(n1375), .B1(
DMP_SHT1_EWSW[2]), .Y(n713) );
AO22XLTS U1712 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1651), .B1(
DMP_SHT2_EWSW[2]), .Y(n712) );
AO22XLTS U1713 ( .A0(n1493), .A1(DMP_SFG[2]), .B0(n1490), .B1(
DMP_SHT2_EWSW[2]), .Y(n711) );
INVX4TS U1714 ( .A(n1611), .Y(n1383) );
AO22XLTS U1715 ( .A0(n1383), .A1(DMP_EXP_EWSW[3]), .B0(n1376), .B1(
DMP_SHT1_EWSW[3]), .Y(n710) );
AO22XLTS U1716 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n946), .B1(
DMP_SHT2_EWSW[3]), .Y(n709) );
AO22XLTS U1717 ( .A0(n1493), .A1(DMP_SFG[3]), .B0(n1490), .B1(
DMP_SHT2_EWSW[3]), .Y(n708) );
AO22XLTS U1718 ( .A0(n1383), .A1(DMP_EXP_EWSW[4]), .B0(n1377), .B1(
DMP_SHT1_EWSW[4]), .Y(n707) );
AO22XLTS U1719 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1374), .B1(
DMP_SHT2_EWSW[4]), .Y(n706) );
AO22XLTS U1720 ( .A0(n1493), .A1(DMP_SFG[4]), .B0(n1490), .B1(
DMP_SHT2_EWSW[4]), .Y(n705) );
AO22XLTS U1721 ( .A0(n1383), .A1(DMP_EXP_EWSW[5]), .B0(n1386), .B1(
DMP_SHT1_EWSW[5]), .Y(n704) );
AO22XLTS U1722 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n946), .B1(
DMP_SHT2_EWSW[5]), .Y(n703) );
AO22XLTS U1723 ( .A0(n1493), .A1(DMP_SFG[5]), .B0(n1490), .B1(
DMP_SHT2_EWSW[5]), .Y(n702) );
AO22XLTS U1724 ( .A0(n1383), .A1(DMP_EXP_EWSW[6]), .B0(n1375), .B1(
DMP_SHT1_EWSW[6]), .Y(n701) );
AO22XLTS U1725 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1651), .B1(
DMP_SHT2_EWSW[6]), .Y(n700) );
AO22XLTS U1726 ( .A0(n1493), .A1(DMP_SFG[6]), .B0(n1490), .B1(
DMP_SHT2_EWSW[6]), .Y(n699) );
AO22XLTS U1727 ( .A0(n1383), .A1(DMP_EXP_EWSW[7]), .B0(n1376), .B1(
DMP_SHT1_EWSW[7]), .Y(n698) );
AO22XLTS U1728 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n946), .B1(
DMP_SHT2_EWSW[7]), .Y(n697) );
AO22XLTS U1729 ( .A0(n1383), .A1(DMP_EXP_EWSW[8]), .B0(n1377), .B1(
DMP_SHT1_EWSW[8]), .Y(n695) );
AO22XLTS U1730 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1651), .B1(
DMP_SHT2_EWSW[8]), .Y(n694) );
AO22XLTS U1731 ( .A0(n1493), .A1(DMP_SFG[8]), .B0(n1389), .B1(
DMP_SHT2_EWSW[8]), .Y(n693) );
AO22XLTS U1732 ( .A0(n1383), .A1(DMP_EXP_EWSW[9]), .B0(n1611), .B1(
DMP_SHT1_EWSW[9]), .Y(n692) );
AO22XLTS U1733 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n946), .B1(
DMP_SHT2_EWSW[9]), .Y(n691) );
AO22XLTS U1734 ( .A0(n1493), .A1(DMP_SFG[9]), .B0(n1495), .B1(
DMP_SHT2_EWSW[9]), .Y(n690) );
AO22XLTS U1735 ( .A0(n1383), .A1(DMP_EXP_EWSW[10]), .B0(n1611), .B1(
DMP_SHT1_EWSW[10]), .Y(n689) );
AO22XLTS U1736 ( .A0(n913), .A1(DMP_SHT1_EWSW[10]), .B0(n1374), .B1(
DMP_SHT2_EWSW[10]), .Y(n688) );
AO22XLTS U1737 ( .A0(n1493), .A1(DMP_SFG[10]), .B0(n1504), .B1(
DMP_SHT2_EWSW[10]), .Y(n687) );
BUFX3TS U1738 ( .A(n1611), .Y(n1375) );
AO22XLTS U1739 ( .A0(n1383), .A1(DMP_EXP_EWSW[11]), .B0(n1375), .B1(
DMP_SHT1_EWSW[11]), .Y(n686) );
AO22XLTS U1740 ( .A0(n913), .A1(DMP_SHT1_EWSW[11]), .B0(n1374), .B1(
DMP_SHT2_EWSW[11]), .Y(n685) );
AO22XLTS U1741 ( .A0(n1493), .A1(DMP_SFG[11]), .B0(n1504), .B1(
DMP_SHT2_EWSW[11]), .Y(n684) );
AO22XLTS U1742 ( .A0(n1383), .A1(DMP_EXP_EWSW[12]), .B0(n1375), .B1(
DMP_SHT1_EWSW[12]), .Y(n683) );
AO22XLTS U1743 ( .A0(busy), .A1(DMP_SHT1_EWSW[12]), .B0(n1651), .B1(
DMP_SHT2_EWSW[12]), .Y(n682) );
AO22XLTS U1744 ( .A0(n1493), .A1(DMP_SFG[12]), .B0(n1490), .B1(
DMP_SHT2_EWSW[12]), .Y(n681) );
AO22XLTS U1745 ( .A0(n1383), .A1(DMP_EXP_EWSW[13]), .B0(n1375), .B1(
DMP_SHT1_EWSW[13]), .Y(n680) );
AO22XLTS U1746 ( .A0(busy), .A1(DMP_SHT1_EWSW[13]), .B0(n946), .B1(
DMP_SHT2_EWSW[13]), .Y(n679) );
AO22XLTS U1747 ( .A0(n1493), .A1(DMP_SFG[13]), .B0(n1490), .B1(
DMP_SHT2_EWSW[13]), .Y(n678) );
AO22XLTS U1748 ( .A0(n1383), .A1(DMP_EXP_EWSW[14]), .B0(n1375), .B1(
DMP_SHT1_EWSW[14]), .Y(n677) );
AO22XLTS U1749 ( .A0(busy), .A1(DMP_SHT1_EWSW[14]), .B0(n1374), .B1(
DMP_SHT2_EWSW[14]), .Y(n676) );
AO22XLTS U1750 ( .A0(n1493), .A1(DMP_SFG[14]), .B0(n1490), .B1(
DMP_SHT2_EWSW[14]), .Y(n675) );
AO22XLTS U1751 ( .A0(n1383), .A1(DMP_EXP_EWSW[15]), .B0(n1375), .B1(
DMP_SHT1_EWSW[15]), .Y(n674) );
AO22XLTS U1752 ( .A0(busy), .A1(DMP_SHT1_EWSW[15]), .B0(n1374), .B1(
DMP_SHT2_EWSW[15]), .Y(n673) );
AO22XLTS U1753 ( .A0(n1493), .A1(DMP_SFG[15]), .B0(n1490), .B1(
DMP_SHT2_EWSW[15]), .Y(n672) );
AO22XLTS U1754 ( .A0(n1383), .A1(DMP_EXP_EWSW[16]), .B0(n1375), .B1(
DMP_SHT1_EWSW[16]), .Y(n671) );
AO22XLTS U1755 ( .A0(n1652), .A1(DMP_SHT1_EWSW[16]), .B0(n1374), .B1(
DMP_SHT2_EWSW[16]), .Y(n670) );
AO22XLTS U1756 ( .A0(n1493), .A1(DMP_SFG[16]), .B0(n1490), .B1(
DMP_SHT2_EWSW[16]), .Y(n669) );
INVX4TS U1757 ( .A(n1611), .Y(n1387) );
AO22XLTS U1758 ( .A0(n1387), .A1(DMP_EXP_EWSW[17]), .B0(n1375), .B1(
DMP_SHT1_EWSW[17]), .Y(n668) );
AO22XLTS U1759 ( .A0(n1652), .A1(DMP_SHT1_EWSW[17]), .B0(n1374), .B1(
DMP_SHT2_EWSW[17]), .Y(n667) );
AO22XLTS U1760 ( .A0(n1387), .A1(DMP_EXP_EWSW[18]), .B0(n1375), .B1(
DMP_SHT1_EWSW[18]), .Y(n665) );
AO22XLTS U1761 ( .A0(n1652), .A1(DMP_SHT1_EWSW[18]), .B0(n1374), .B1(
DMP_SHT2_EWSW[18]), .Y(n664) );
AO22XLTS U1762 ( .A0(n1387), .A1(DMP_EXP_EWSW[19]), .B0(n1375), .B1(
DMP_SHT1_EWSW[19]), .Y(n662) );
AO22XLTS U1763 ( .A0(n1652), .A1(DMP_SHT1_EWSW[19]), .B0(n1374), .B1(
DMP_SHT2_EWSW[19]), .Y(n661) );
AO22XLTS U1764 ( .A0(n1387), .A1(DMP_EXP_EWSW[20]), .B0(n1375), .B1(
DMP_SHT1_EWSW[20]), .Y(n659) );
AO22XLTS U1765 ( .A0(n1652), .A1(DMP_SHT1_EWSW[20]), .B0(n1374), .B1(
DMP_SHT2_EWSW[20]), .Y(n658) );
AO22XLTS U1766 ( .A0(n1387), .A1(DMP_EXP_EWSW[21]), .B0(n1375), .B1(
DMP_SHT1_EWSW[21]), .Y(n656) );
AO22XLTS U1767 ( .A0(n1652), .A1(DMP_SHT1_EWSW[21]), .B0(n1651), .B1(
DMP_SHT2_EWSW[21]), .Y(n655) );
BUFX3TS U1768 ( .A(n1611), .Y(n1386) );
AO22XLTS U1769 ( .A0(n1387), .A1(DMP_EXP_EWSW[22]), .B0(n1386), .B1(
DMP_SHT1_EWSW[22]), .Y(n653) );
AO22XLTS U1770 ( .A0(n1652), .A1(DMP_SHT1_EWSW[22]), .B0(n946), .B1(
DMP_SHT2_EWSW[22]), .Y(n652) );
AO22XLTS U1771 ( .A0(n1387), .A1(DMP_EXP_EWSW[23]), .B0(n1386), .B1(
DMP_SHT1_EWSW[23]), .Y(n650) );
AO22XLTS U1772 ( .A0(n945), .A1(DMP_SHT1_EWSW[23]), .B0(n1651), .B1(
DMP_SHT2_EWSW[23]), .Y(n649) );
AO22XLTS U1773 ( .A0(n1495), .A1(DMP_SHT2_EWSW[23]), .B0(n1372), .B1(
DMP_SFG[23]), .Y(n648) );
AO22XLTS U1774 ( .A0(n1402), .A1(DMP_SFG[23]), .B0(n1395), .B1(
DMP_exp_NRM_EW[0]), .Y(n647) );
AO22XLTS U1775 ( .A0(n1387), .A1(DMP_EXP_EWSW[24]), .B0(n1386), .B1(
DMP_SHT1_EWSW[24]), .Y(n645) );
AO22XLTS U1776 ( .A0(n945), .A1(DMP_SHT1_EWSW[24]), .B0(n946), .B1(
DMP_SHT2_EWSW[24]), .Y(n644) );
AO22XLTS U1777 ( .A0(n1402), .A1(DMP_SFG[24]), .B0(n1395), .B1(
DMP_exp_NRM_EW[1]), .Y(n642) );
AO22XLTS U1778 ( .A0(n1387), .A1(DMP_EXP_EWSW[25]), .B0(n1386), .B1(
DMP_SHT1_EWSW[25]), .Y(n640) );
AO22XLTS U1779 ( .A0(n945), .A1(DMP_SHT1_EWSW[25]), .B0(n1651), .B1(
DMP_SHT2_EWSW[25]), .Y(n639) );
AO22XLTS U1780 ( .A0(n1504), .A1(DMP_SHT2_EWSW[25]), .B0(n1372), .B1(
DMP_SFG[25]), .Y(n638) );
AO22XLTS U1781 ( .A0(n1402), .A1(DMP_SFG[25]), .B0(n1395), .B1(
DMP_exp_NRM_EW[2]), .Y(n637) );
AO22XLTS U1782 ( .A0(n1387), .A1(DMP_EXP_EWSW[26]), .B0(n1386), .B1(
DMP_SHT1_EWSW[26]), .Y(n635) );
AO22XLTS U1783 ( .A0(n1652), .A1(DMP_SHT1_EWSW[26]), .B0(n946), .B1(
DMP_SHT2_EWSW[26]), .Y(n634) );
AO22XLTS U1784 ( .A0(n1402), .A1(DMP_SFG[26]), .B0(n1395), .B1(
DMP_exp_NRM_EW[3]), .Y(n632) );
AO22XLTS U1785 ( .A0(n1387), .A1(n935), .B0(n1386), .B1(DMP_SHT1_EWSW[27]),
.Y(n630) );
AO22XLTS U1786 ( .A0(n945), .A1(DMP_SHT1_EWSW[27]), .B0(n1651), .B1(
DMP_SHT2_EWSW[27]), .Y(n629) );
AO22XLTS U1787 ( .A0(n1402), .A1(DMP_SFG[27]), .B0(n1408), .B1(
DMP_exp_NRM_EW[4]), .Y(n627) );
AO22XLTS U1788 ( .A0(n1387), .A1(DMP_EXP_EWSW[28]), .B0(n1386), .B1(
DMP_SHT1_EWSW[28]), .Y(n625) );
AO22XLTS U1789 ( .A0(n913), .A1(DMP_SHT1_EWSW[28]), .B0(n914), .B1(
DMP_SHT2_EWSW[28]), .Y(n624) );
AO22XLTS U1790 ( .A0(n1402), .A1(DMP_SFG[28]), .B0(n1408), .B1(
DMP_exp_NRM_EW[5]), .Y(n622) );
AO22XLTS U1791 ( .A0(n1387), .A1(DMP_EXP_EWSW[29]), .B0(n1386), .B1(
DMP_SHT1_EWSW[29]), .Y(n620) );
AO22XLTS U1792 ( .A0(n945), .A1(DMP_SHT1_EWSW[29]), .B0(n1651), .B1(
DMP_SHT2_EWSW[29]), .Y(n619) );
AO22XLTS U1793 ( .A0(n1504), .A1(DMP_SHT2_EWSW[29]), .B0(n1372), .B1(
DMP_SFG[29]), .Y(n618) );
AO22XLTS U1794 ( .A0(n1402), .A1(DMP_SFG[29]), .B0(n1408), .B1(
DMP_exp_NRM_EW[6]), .Y(n617) );
AO22XLTS U1795 ( .A0(n1516), .A1(DMP_EXP_EWSW[30]), .B0(n1386), .B1(
DMP_SHT1_EWSW[30]), .Y(n615) );
AO22XLTS U1796 ( .A0(n913), .A1(DMP_SHT1_EWSW[30]), .B0(n1374), .B1(
DMP_SHT2_EWSW[30]), .Y(n614) );
AO22XLTS U1797 ( .A0(n1402), .A1(DMP_SFG[30]), .B0(n1408), .B1(
DMP_exp_NRM_EW[7]), .Y(n612) );
BUFX3TS U1798 ( .A(n1611), .Y(n1376) );
BUFX3TS U1799 ( .A(n1611), .Y(n1377) );
OAI222X1TS U1800 ( .A0(n1380), .A1(n1606), .B0(n1533), .B1(
Shift_reg_FLAGS_7_6), .C0(n1515), .C1(n1378), .Y(n563) );
OAI222X1TS U1801 ( .A0(n1380), .A1(n1538), .B0(n1608), .B1(
Shift_reg_FLAGS_7_6), .C0(n1581), .C1(n1378), .Y(n562) );
OAI222X1TS U1802 ( .A0(n1380), .A1(n1539), .B0(n1603), .B1(
Shift_reg_FLAGS_7_6), .C0(n1587), .C1(n1378), .Y(n561) );
INVX4TS U1803 ( .A(n1381), .Y(n1470) );
NAND2X1TS U1804 ( .A(n1411), .B(Shift_reg_FLAGS_7[0]), .Y(n1382) );
OAI2BB1X1TS U1805 ( .A0N(underflow_flag), .A1N(n1470), .B0(n1382), .Y(n559)
);
AO22XLTS U1806 ( .A0(n1387), .A1(ZERO_FLAG_EXP), .B0(n1611), .B1(
ZERO_FLAG_SHT1), .Y(n557) );
AO22XLTS U1807 ( .A0(n945), .A1(ZERO_FLAG_SHT1), .B0(n946), .B1(
ZERO_FLAG_SHT2), .Y(n556) );
AO22XLTS U1808 ( .A0(n1389), .A1(ZERO_FLAG_SHT2), .B0(n1372), .B1(
ZERO_FLAG_SFG), .Y(n555) );
AO22XLTS U1809 ( .A0(n1402), .A1(ZERO_FLAG_SFG), .B0(n1408), .B1(
ZERO_FLAG_NRM), .Y(n554) );
AO22XLTS U1810 ( .A0(n905), .A1(ZERO_FLAG_NRM), .B0(n1390), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n553) );
AO22XLTS U1811 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1470), .B1(zero_flag), .Y(n552) );
AO22XLTS U1812 ( .A0(n1383), .A1(OP_FLAG_EXP), .B0(n1611), .B1(OP_FLAG_SHT1),
.Y(n551) );
AO22XLTS U1813 ( .A0(n913), .A1(OP_FLAG_SHT1), .B0(n1374), .B1(OP_FLAG_SHT2),
.Y(n550) );
INVX2TS U1814 ( .A(n1384), .Y(n1385) );
AO22XLTS U1815 ( .A0(n1387), .A1(SIGN_FLAG_EXP), .B0(n1386), .B1(
SIGN_FLAG_SHT1), .Y(n548) );
AO22XLTS U1816 ( .A0(n913), .A1(SIGN_FLAG_SHT1), .B0(n914), .B1(
SIGN_FLAG_SHT2), .Y(n547) );
AO22XLTS U1817 ( .A0(n1402), .A1(SIGN_FLAG_SFG), .B0(n1395), .B1(
SIGN_FLAG_NRM), .Y(n545) );
AO22XLTS U1818 ( .A0(n905), .A1(SIGN_FLAG_NRM), .B0(n1390), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n544) );
AOI22X1TS U1819 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n1403), .B0(n1385), .B1(n955), .Y(n1392) );
AOI22X1TS U1820 ( .A0(n1404), .A1(n1392), .B0(n1524), .B1(n1649), .Y(n542)
);
AOI22X1TS U1821 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1403), .B0(n1385), .B1(n956), .Y(n1393) );
AOI22X1TS U1822 ( .A0(n1404), .A1(n1393), .B0(n1594), .B1(n1649), .Y(n541)
);
OAI21XLTS U1823 ( .A0(n1394), .A1(DMP_SFG[0]), .B0(n1397), .Y(n1396) );
AOI22X1TS U1824 ( .A0(n1404), .A1(n1396), .B0(n1548), .B1(n1395), .Y(n540)
);
XNOR2X1TS U1825 ( .A(DMP_SFG[1]), .B(n1397), .Y(n1398) );
XNOR2X1TS U1826 ( .A(n1398), .B(n917), .Y(n1399) );
AOI22X1TS U1827 ( .A0(n1404), .A1(n1399), .B0(n1590), .B1(n1649), .Y(n539)
);
AOI22X1TS U1828 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n967), .B0(n1406), .B1(n960),
.Y(intadd_67_CI) );
AOI2BB2XLTS U1829 ( .B0(n1648), .B1(intadd_67_SUM_0_), .A0N(
Raw_mant_NRM_SWR[4]), .A1N(n1402), .Y(n538) );
AOI22X1TS U1830 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1403), .B0(n1385), .B1(n961), .Y(intadd_67_B_1_) );
AOI22X1TS U1831 ( .A0(n1648), .A1(intadd_67_SUM_1_), .B0(n1549), .B1(n1649),
.Y(n537) );
AOI22X1TS U1832 ( .A0(n1648), .A1(intadd_67_SUM_2_), .B0(n1536), .B1(n1408),
.Y(n536) );
AOI22X1TS U1833 ( .A0(n1648), .A1(intadd_67_SUM_3_), .B0(n1522), .B1(n1408),
.Y(n535) );
AOI22X1TS U1834 ( .A0(n1648), .A1(intadd_67_SUM_4_), .B0(n1525), .B1(n1408),
.Y(n534) );
XNOR2X1TS U1835 ( .A(DMP_SFG[7]), .B(n918), .Y(n1400) );
XNOR2X1TS U1836 ( .A(intadd_67_n1), .B(n1400), .Y(n1401) );
AOI22X1TS U1837 ( .A0(n1648), .A1(n1401), .B0(n1537), .B1(n1408), .Y(n533)
);
AOI22X1TS U1838 ( .A0(n1648), .A1(intadd_66_SUM_0_), .B0(n1521), .B1(n1408),
.Y(n532) );
AOI22X1TS U1839 ( .A0(n1648), .A1(intadd_66_SUM_1_), .B0(n1514), .B1(n1408),
.Y(n531) );
AOI22X1TS U1840 ( .A0(n1404), .A1(intadd_66_SUM_3_), .B0(n1535), .B1(n1408),
.Y(n529) );
AOI22X1TS U1841 ( .A0(n1404), .A1(intadd_66_SUM_4_), .B0(n1519), .B1(n1408),
.Y(n528) );
AOI22X1TS U1842 ( .A0(n1404), .A1(intadd_66_SUM_5_), .B0(n1518), .B1(n1408),
.Y(n527) );
AOI22X1TS U1843 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n1403), .B0(n1406), .B1(
n962), .Y(intadd_66_B_6_) );
AOI22X1TS U1844 ( .A0(n1404), .A1(intadd_66_SUM_6_), .B0(n1513), .B1(n1395),
.Y(n526) );
AOI22X1TS U1845 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n1403), .B0(n1406), .B1(
n948), .Y(intadd_66_B_7_) );
AOI22X1TS U1846 ( .A0(n1404), .A1(intadd_66_SUM_7_), .B0(n1541), .B1(n1649),
.Y(n525) );
AOI22X1TS U1847 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n1403), .B0(n1406), .B1(
n949), .Y(intadd_66_B_8_) );
AOI22X1TS U1848 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n1403), .B0(n1406), .B1(
n950), .Y(intadd_66_B_9_) );
AOI22X1TS U1849 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1403), .B0(n1406), .B1(
n951), .Y(intadd_66_B_10_) );
AOI22X1TS U1850 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n1403), .B0(n1385), .B1(
n953), .Y(intadd_66_B_11_) );
AOI22X1TS U1851 ( .A0(n1404), .A1(intadd_66_SUM_11_), .B0(n1543), .B1(n1649),
.Y(n521) );
AOI22X1TS U1852 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n1403), .B0(n1385), .B1(
n954), .Y(intadd_66_B_12_) );
AOI22X1TS U1853 ( .A0(n1404), .A1(intadd_66_SUM_12_), .B0(n1540), .B1(n1649),
.Y(n520) );
AOI22X1TS U1854 ( .A0(DmP_mant_SFG_SWR[23]), .A1(n1403), .B0(n1385), .B1(
n1597), .Y(intadd_66_B_13_) );
AOI22X1TS U1855 ( .A0(n1404), .A1(intadd_66_SUM_13_), .B0(n1511), .B1(n1649),
.Y(n519) );
AOI22X1TS U1856 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1403), .B0(n1385), .B1(
n1610), .Y(intadd_66_B_14_) );
AOI22X1TS U1857 ( .A0(n1404), .A1(intadd_66_SUM_14_), .B0(n1512), .B1(n1649),
.Y(n518) );
AOI22X1TS U1858 ( .A0(DmP_mant_SFG_SWR[25]), .A1(n1385), .B0(n967), .B1(
n1614), .Y(n1407) );
XNOR2X1TS U1859 ( .A(intadd_66_n1), .B(n1407), .Y(n1409) );
AOI22X1TS U1860 ( .A0(n1648), .A1(n1409), .B0(n1517), .B1(n1408), .Y(n517)
);
AOI22X1TS U1861 ( .A0(Data_array_SWR[12]), .A1(n900), .B0(Data_array_SWR[13]), .B1(n937), .Y(n1412) );
OAI221X1TS U1862 ( .A0(n906), .A1(n1414), .B0(n907), .B1(n1415), .C0(n1412),
.Y(n1488) );
AOI22X1TS U1863 ( .A0(Data_array_SWR[12]), .A1(n937), .B0(Data_array_SWR[13]), .B1(n900), .Y(n1413) );
OAI221X1TS U1864 ( .A0(left_right_SHT2), .A1(n1415), .B0(n874), .B1(n1414),
.C0(n1413), .Y(n1489) );
AOI22X1TS U1865 ( .A0(Data_array_SWR[14]), .A1(n900), .B0(Data_array_SWR[11]), .B1(n937), .Y(n1417) );
OAI221X1TS U1866 ( .A0(n906), .A1(n1419), .B0(n907), .B1(n1418), .C0(n1417),
.Y(n1492) );
AOI22X1TS U1867 ( .A0(Data_array_SWR[23]), .A1(n941), .B0(Data_array_SWR[19]), .B1(n940), .Y(n1423) );
AOI22X1TS U1868 ( .A0(Data_array_SWR[10]), .A1(n900), .B0(Data_array_SWR[15]), .B1(n937), .Y(n1420) );
OAI221X1TS U1869 ( .A0(n906), .A1(n1422), .B0(n907), .B1(n1423), .C0(n1420),
.Y(n1487) );
AOI22X1TS U1870 ( .A0(Data_array_SWR[10]), .A1(n937), .B0(Data_array_SWR[15]), .B1(n900), .Y(n1421) );
OAI221X1TS U1871 ( .A0(left_right_SHT2), .A1(n1423), .B0(n874), .B1(n1422),
.C0(n1421), .Y(n1494) );
AOI22X1TS U1872 ( .A0(Data_array_SWR[17]), .A1(n942), .B0(Data_array_SWR[13]), .B1(n939), .Y(n1425) );
AOI22X1TS U1873 ( .A0(Data_array_SWR[21]), .A1(n1471), .B0(
Data_array_SWR[25]), .B1(n1439), .Y(n1424) );
NAND2X1TS U1874 ( .A(n1425), .B(n1424), .Y(n1429) );
NOR2X1TS U1875 ( .A(shift_value_SHT2_EWR[2]), .B(n1542), .Y(n1432) );
INVX2TS U1876 ( .A(n1426), .Y(n1447) );
INVX2TS U1877 ( .A(n1475), .Y(n1428) );
OAI2BB2XLTS U1878 ( .B0(n1486), .B1(n902), .A0N(final_result_ieee[7]), .A1N(
n1470), .Y(n505) );
OAI2BB2XLTS U1879 ( .B0(n1496), .B1(n903), .A0N(final_result_ieee[14]),
.A1N(n1470), .Y(n504) );
AOI22X1TS U1880 ( .A0(Data_array_SWR[12]), .A1(n940), .B0(Data_array_SWR[16]), .B1(n941), .Y(n1431) );
AOI22X1TS U1881 ( .A0(Data_array_SWR[24]), .A1(n1439), .B0(
Data_array_SWR[20]), .B1(n1471), .Y(n1430) );
NAND2X1TS U1882 ( .A(n1431), .B(n1430), .Y(n1434) );
INVX2TS U1883 ( .A(n1469), .Y(n1433) );
OAI2BB2XLTS U1884 ( .B0(n1485), .B1(n903), .A0N(final_result_ieee[6]), .A1N(
n1470), .Y(n503) );
OAI2BB2XLTS U1885 ( .B0(n1497), .B1(n903), .A0N(final_result_ieee[15]),
.A1N(n1470), .Y(n502) );
AOI22X1TS U1886 ( .A0(Data_array_SWR[15]), .A1(n942), .B0(Data_array_SWR[11]), .B1(n940), .Y(n1436) );
AOI22X1TS U1887 ( .A0(Data_array_SWR[23]), .A1(n1439), .B0(
Data_array_SWR[19]), .B1(n1471), .Y(n1435) );
NAND2X1TS U1888 ( .A(n1436), .B(n1435), .Y(n1438) );
AOI22X1TS U1889 ( .A0(Data_array_SWR[22]), .A1(n1447), .B0(
Data_array_SWR[18]), .B1(n1446), .Y(n1463) );
INVX2TS U1890 ( .A(n1463), .Y(n1437) );
OAI2BB2XLTS U1891 ( .B0(n1484), .B1(n903), .A0N(final_result_ieee[5]), .A1N(
n1470), .Y(n501) );
OAI2BB2XLTS U1892 ( .B0(n1498), .B1(n903), .A0N(final_result_ieee[16]),
.A1N(n1470), .Y(n500) );
AOI22X1TS U1893 ( .A0(Data_array_SWR[14]), .A1(n942), .B0(Data_array_SWR[10]), .B1(n939), .Y(n1441) );
AOI22X1TS U1894 ( .A0(Data_array_SWR[22]), .A1(n1439), .B0(
Data_array_SWR[18]), .B1(n1471), .Y(n1440) );
NAND2X1TS U1895 ( .A(n1441), .B(n1440), .Y(n1443) );
AOI22X1TS U1896 ( .A0(Data_array_SWR[23]), .A1(n1447), .B0(
Data_array_SWR[19]), .B1(n1446), .Y(n1460) );
INVX2TS U1897 ( .A(n1460), .Y(n1442) );
OAI2BB2XLTS U1898 ( .B0(n1483), .B1(n903), .A0N(final_result_ieee[4]), .A1N(
n1466), .Y(n499) );
OAI2BB2XLTS U1899 ( .B0(n1499), .B1(n903), .A0N(final_result_ieee[17]),
.A1N(n1466), .Y(n498) );
AOI22X1TS U1900 ( .A0(Data_array_SWR[21]), .A1(n1446), .B0(
Data_array_SWR[25]), .B1(n1447), .Y(n1452) );
AOI22X1TS U1901 ( .A0(Data_array_SWR[13]), .A1(n941), .B0(Data_array_SWR[9]),
.B1(n939), .Y(n1445) );
NAND2X1TS U1902 ( .A(Data_array_SWR[17]), .B(n1471), .Y(n1444) );
OAI211X1TS U1903 ( .A0(n1452), .A1(n1547), .B0(n1445), .C0(n1444), .Y(n1448)
);
AO22X1TS U1904 ( .A0(Data_array_SWR[24]), .A1(n1447), .B0(Data_array_SWR[20]), .B1(n1446), .Y(n1449) );
OAI2BB2XLTS U1905 ( .B0(n1482), .B1(n902), .A0N(final_result_ieee[3]), .A1N(
n1466), .Y(n497) );
OAI2BB2XLTS U1906 ( .B0(n1500), .B1(n902), .A0N(final_result_ieee[18]),
.A1N(n1466), .Y(n496) );
AOI22X1TS U1907 ( .A0(Data_array_SWR[12]), .A1(n942), .B0(Data_array_SWR[8]),
.B1(n939), .Y(n1451) );
AOI22X1TS U1908 ( .A0(Data_array_SWR[16]), .A1(n1471), .B0(
shift_value_SHT2_EWR[4]), .B1(n1449), .Y(n1450) );
NAND2X1TS U1909 ( .A(n1451), .B(n1450), .Y(n1456) );
INVX2TS U1910 ( .A(n1452), .Y(n1455) );
OAI2BB2XLTS U1911 ( .B0(n1481), .B1(n903), .A0N(final_result_ieee[2]), .A1N(
n1466), .Y(n495) );
OAI2BB2XLTS U1912 ( .B0(n1501), .B1(n903), .A0N(final_result_ieee[19]),
.A1N(n1466), .Y(n494) );
AOI22X1TS U1913 ( .A0(Data_array_SWR[15]), .A1(n1471), .B0(
Data_array_SWR[11]), .B1(n941), .Y(n1459) );
INVX2TS U1914 ( .A(n1457), .Y(n1472) );
AOI22X1TS U1915 ( .A0(Data_array_SWR[7]), .A1(n939), .B0(Data_array_SWR[3]),
.B1(n1472), .Y(n1458) );
OAI211X1TS U1916 ( .A0(n1460), .A1(n1547), .B0(n1459), .C0(n1458), .Y(n1464)
);
AOI22X1TS U1917 ( .A0(Data_array_SWR[22]), .A1(n937), .B0(n907), .B1(n1464),
.Y(n1480) );
OAI2BB2XLTS U1918 ( .B0(n1480), .B1(n902), .A0N(final_result_ieee[1]), .A1N(
n1466), .Y(n493) );
AOI22X1TS U1919 ( .A0(Data_array_SWR[14]), .A1(n1471), .B0(
Data_array_SWR[10]), .B1(n941), .Y(n1462) );
AOI22X1TS U1920 ( .A0(Data_array_SWR[6]), .A1(n939), .B0(Data_array_SWR[2]),
.B1(n1472), .Y(n1461) );
OAI211X1TS U1921 ( .A0(n1463), .A1(n1547), .B0(n1462), .C0(n1461), .Y(n1465)
);
AOI22X1TS U1922 ( .A0(Data_array_SWR[23]), .A1(n938), .B0(n907), .B1(n1465),
.Y(n1479) );
OAI2BB2XLTS U1923 ( .B0(n1479), .B1(n902), .A0N(final_result_ieee[0]), .A1N(
n1466), .Y(n492) );
AOI22X1TS U1924 ( .A0(Data_array_SWR[22]), .A1(n901), .B0(left_right_SHT2),
.B1(n1464), .Y(n1502) );
OAI2BB2XLTS U1925 ( .B0(n1502), .B1(n902), .A0N(final_result_ieee[20]),
.A1N(n1466), .Y(n491) );
AOI22X1TS U1926 ( .A0(Data_array_SWR[23]), .A1(n900), .B0(left_right_SHT2),
.B1(n1465), .Y(n1503) );
OAI2BB2XLTS U1927 ( .B0(n1503), .B1(n902), .A0N(final_result_ieee[21]),
.A1N(n1466), .Y(n490) );
AOI22X1TS U1928 ( .A0(Data_array_SWR[13]), .A1(n1471), .B0(Data_array_SWR[9]), .B1(n941), .Y(n1468) );
AOI22X1TS U1929 ( .A0(Data_array_SWR[5]), .A1(n939), .B0(Data_array_SWR[1]),
.B1(n1472), .Y(n1467) );
OAI211X1TS U1930 ( .A0(n1469), .A1(n1547), .B0(n1468), .C0(n1467), .Y(n1477)
);
AOI22X1TS U1931 ( .A0(Data_array_SWR[24]), .A1(n901), .B0(left_right_SHT2),
.B1(n1477), .Y(n1506) );
OAI2BB2XLTS U1932 ( .B0(n1506), .B1(n902), .A0N(final_result_ieee[22]),
.A1N(n1470), .Y(n489) );
AOI22X1TS U1933 ( .A0(Data_array_SWR[12]), .A1(n1471), .B0(Data_array_SWR[8]), .B1(n942), .Y(n1474) );
AOI22X1TS U1934 ( .A0(Data_array_SWR[4]), .A1(n940), .B0(Data_array_SWR[0]),
.B1(n1472), .Y(n1473) );
OAI211X1TS U1935 ( .A0(n1475), .A1(n1547), .B0(n1474), .C0(n1473), .Y(n1507)
);
AOI22X1TS U1936 ( .A0(Data_array_SWR[25]), .A1(n938), .B0(n907), .B1(n1507),
.Y(n1476) );
AOI22X1TS U1937 ( .A0(n1504), .A1(n1476), .B0(n1491), .B1(n955), .Y(n488) );
AOI22X1TS U1938 ( .A0(Data_array_SWR[24]), .A1(n938), .B0(n874), .B1(n1477),
.Y(n1478) );
AOI22X1TS U1939 ( .A0(n1389), .A1(n1478), .B0(n1509), .B1(n956), .Y(n487) );
AOI22X1TS U1940 ( .A0(n1495), .A1(n1479), .B0(n1509), .B1(n958), .Y(n486) );
AOI22X1TS U1941 ( .A0(n1504), .A1(n1480), .B0(n1491), .B1(n959), .Y(n485) );
AOI22X1TS U1942 ( .A0(n1389), .A1(n1481), .B0(n1509), .B1(n960), .Y(n484) );
AOI22X1TS U1943 ( .A0(n1389), .A1(n1482), .B0(n1509), .B1(n961), .Y(n483) );
AOI22X1TS U1944 ( .A0(n1504), .A1(n1483), .B0(n1491), .B1(n965), .Y(n482) );
AOI22X1TS U1945 ( .A0(n1495), .A1(n1484), .B0(n1509), .B1(n966), .Y(n481) );
AOI22X1TS U1946 ( .A0(n1389), .A1(n1485), .B0(n964), .B1(n1491), .Y(n480) );
AOI22X1TS U1947 ( .A0(n1495), .A1(n1486), .B0(n1491), .B1(n963), .Y(n479) );
AOI22X1TS U1948 ( .A0(n1504), .A1(n1496), .B0(n1509), .B1(n962), .Y(n472) );
AOI22X1TS U1949 ( .A0(n1495), .A1(n1497), .B0(n1491), .B1(n948), .Y(n471) );
AOI22X1TS U1950 ( .A0(n1389), .A1(n1498), .B0(n1491), .B1(n949), .Y(n470) );
AOI22X1TS U1951 ( .A0(n1504), .A1(n1499), .B0(n1509), .B1(n950), .Y(n469) );
AOI22X1TS U1952 ( .A0(n1389), .A1(n1500), .B0(n1491), .B1(n951), .Y(n468) );
AOI22X1TS U1953 ( .A0(n1495), .A1(n1501), .B0(n1505), .B1(n953), .Y(n467) );
AOI22X1TS U1954 ( .A0(n1504), .A1(n1502), .B0(n1505), .B1(n954), .Y(n466) );
AOI22X1TS U1955 ( .A0(n1504), .A1(n1503), .B0(n1505), .B1(n1597), .Y(n465)
);
AOI22X1TS U1956 ( .A0(n1389), .A1(n1506), .B0(n1505), .B1(n1610), .Y(n464)
);
AOI22X1TS U1957 ( .A0(Data_array_SWR[25]), .A1(n901), .B0(left_right_SHT2),
.B1(n1507), .Y(n1510) );
AOI22X1TS U1958 ( .A0(n1495), .A1(n1510), .B0(n1509), .B1(n1614), .Y(n463)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk20.tcl_GeArN16R6P4_syn.sdf");
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: mb2cpx_sm.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/***************************************************************************
* mb2cpx_sm.v State machine for the MicroBlaze FSL to SPARC CPX interface
*
* $Id: $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module mb2cpx_sm (
// Outputs
cpx_fsl_s_read,
cpx_shift_out,
cpx_spc_data_rdy_cx2,
// Inputs
rclk,
reset_l,
fsl_cpx_s_exists,
fsl_cpx_s_control,
atomic_txn
);
parameter CPX_GEAR_RATIO = (((`CPX_WIDTH+3-1)/`FSL_D_WIDTH)+1);
parameter CPX_FSL_EXTRA_BITS = (`FSL_D_WIDTH * CPX_GEAR_RATIO) -
(`PCX_WIDTH+3);
parameter [2:0] CPX_FIRST_COUNT = CPX_GEAR_RATIO - 2;
parameter pCPX_IDLE = 0,
pCPX_SHIFT = 1,
pCPX_AT_WAIT = 2;
parameter CPX_IDLE = 3'b001,
CPX_SHIFT = 3'b010,
CPX_AT_WAIT = 3'b100;
// Outputs
output cpx_fsl_s_read;
output cpx_shift_out;
output cpx_spc_data_rdy_cx2;
// Inputs
input rclk;
input reset_l;
input fsl_cpx_s_exists;
input fsl_cpx_s_control;
input atomic_txn;
// Wire definitions for outputs
reg cpx_fsl_s_read;
reg cpx_shift_out;
wire cpx_spc_data_rdy_cx2;
// State machine to control the shifting of data
reg [2:0] curr_state;
reg [2:0] next_state;
reg [2:0] curr_count;
reg [2:0] next_count;
reg atomic_first;
reg atomic_second;
reg next_atomic_first;
reg next_atomic_second;
reg next_shift_out;
reg atomic_second_d1;
reg atomic_second_d2;
reg cpx_shift_out_d1;
always @ (posedge rclk) begin // Start with a synchronous reset
if (!reset_l) begin
curr_state <= CPX_IDLE;
curr_count <= 3'b000;
atomic_first <= 1'b0;
atomic_second <= 1'b0;
cpx_shift_out <= 1'b0;
end
else begin
curr_state <= next_state;
curr_count <= next_count;
atomic_first <= next_atomic_first;
atomic_second <= next_atomic_second;
cpx_shift_out <= next_shift_out;
end
end
always @(posedge rclk) begin
atomic_second_d1 <= atomic_second;
atomic_second_d2 <= atomic_second_d1;
cpx_shift_out_d1 <= cpx_shift_out;
end
always @ (curr_state or fsl_cpx_s_exists or fsl_cpx_s_control or
curr_count or atomic_txn or atomic_first or atomic_second) begin
case (1)
curr_state[pCPX_IDLE] : begin
next_atomic_second = 1'b0;
next_shift_out = 1'b0;
if (fsl_cpx_s_exists && fsl_cpx_s_control) begin
next_state = CPX_SHIFT;
next_count = CPX_FIRST_COUNT;
next_atomic_first = atomic_txn;
cpx_fsl_s_read = 1'b1;
end
// Expect that the control bit will be set for the first
// 32-bit sub-word of each transaction. Just a double-check
// to ensure we are in sync. Drop any initial words without
// a control bit
else if (fsl_cpx_s_exists && !fsl_cpx_s_control) begin
next_state = CPX_IDLE;
next_count = 3'b000;
next_atomic_first = 1'b0;
cpx_fsl_s_read = 1'b1;
end
else begin
next_state = CPX_IDLE;
next_count = 3'b000;
next_atomic_first = 1'b0;
cpx_fsl_s_read = 1'b0;
end
end
curr_state[pCPX_SHIFT] : begin
if (fsl_cpx_s_exists && curr_count == 3'b000) begin
if (atomic_first) begin
next_state = CPX_AT_WAIT;
next_count = curr_count;
next_atomic_first = 1'b0;
next_atomic_second = atomic_first;
cpx_fsl_s_read = 1'b1;
next_shift_out = 1'b1;
end
else begin
next_state = CPX_IDLE;
next_count = CPX_FIRST_COUNT;
next_atomic_first = 1'b0;
next_atomic_second = 1'b0;
cpx_fsl_s_read = 1'b1;
next_shift_out = 1'b1;
end
end
else if (fsl_cpx_s_exists) begin
next_state = CPX_SHIFT;
next_count = curr_count - 3'b001;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
cpx_fsl_s_read = 1'b1;
next_shift_out = 1'b0;
end
else begin
next_state = CPX_SHIFT;
next_count = curr_count;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
cpx_fsl_s_read = 1'b0;
next_shift_out = 1'b0;
end
end
curr_state[pCPX_AT_WAIT] : begin
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_shift_out = 1'b0;
if (fsl_cpx_s_exists && fsl_cpx_s_control) begin
next_state = CPX_SHIFT;
next_count = CPX_FIRST_COUNT;
cpx_fsl_s_read = 1'b1;
end
// Expect that the control bit will be set for the first
// 32-bit sub-word of each transaction. Just a double-check
// to ensure we are in sync. Drop any initial words without
// a control bit
else if (fsl_cpx_s_exists && !fsl_cpx_s_control) begin
next_state = CPX_AT_WAIT;
next_count = 3'b000;
cpx_fsl_s_read = 1'b1;
end
else begin
next_state = CPX_AT_WAIT;
next_count = 3'b000;
cpx_fsl_s_read = 1'b0;
end
end
default : begin
next_state = CPX_IDLE;
next_count = 3'b000;
next_atomic_first = 1'b0;
next_atomic_second = 1'b0;
cpx_fsl_s_read = 1'b0;
next_shift_out = 1'b0;
end
endcase
end
// Outputs of the state machine
assign cpx_spc_data_rdy_cx2 = (!atomic_second && !atomic_second_d2 &&
cpx_shift_out_d1) ||
(atomic_second_d1 && cpx_shift_out);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_LP_V
`define SKY130_FD_SC_LP__CLKBUF_LP_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuf_lp (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkbuf_lp (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_LP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_xres4v2 ( TIE_WEAK_HI_H, XRES_H_N, TIE_HI_ESD, TIE_LO_ESD,
AMUXBUS_A, AMUXBUS_B, PAD, PAD_A_ESD_H, ENABLE_H, EN_VDDIO_SIG_H, INP_SEL_H, FILT_IN_H,
DISABLE_PULLUP_H, PULLUP_H, ENABLE_VDDIO
);
wire mode_vcchib;
output XRES_H_N;
inout AMUXBUS_A;
inout AMUXBUS_B;
inout PAD;
input DISABLE_PULLUP_H;
input ENABLE_H;
input EN_VDDIO_SIG_H;
input INP_SEL_H;
input FILT_IN_H;
inout PULLUP_H;
input ENABLE_VDDIO;
supply1 vccd;
supply1 vcchib;
supply1 vdda;
supply1 vddio;
supply1 vddio_q;
supply0 vssa;
supply0 vssd;
supply0 vssio;
supply0 vssio_q;
supply1 vswitch;
wire pwr_good_xres_tmp = 1;
wire pwr_good_xres_h_n = 1;
wire pwr_good_pullup = 1;
inout PAD_A_ESD_H;
output TIE_HI_ESD;
output TIE_LO_ESD;
inout TIE_WEAK_HI_H;
wire tmp1;
pullup (pull1) p1 (tmp1); tranif1 x_pull_1 (TIE_WEAK_HI_H, tmp1, pwr_good_pullup===0 ? 1'bx : 1);
tran p2 (PAD, PAD_A_ESD_H);
buf p4 (TIE_HI_ESD, vddio);
buf p5 (TIE_LO_ESD, vssio);
wire tmp;
pullup (pull1) p3 (tmp); tranif0 x_pull (PULLUP_H, tmp, pwr_good_pullup===0 || ^DISABLE_PULLUP_H===1'bx ? 1'bx : DISABLE_PULLUP_H);
parameter MAX_WARNING_COUNT = 100;
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_DELAY
parameter MIN_DELAY = 0;
parameter MAX_DELAY = 0;
`else
parameter MIN_DELAY = 50;
parameter MAX_DELAY = 600;
`endif
integer min_delay, max_delay;
initial begin
min_delay = MIN_DELAY;
max_delay = MAX_DELAY;
end
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_ENABLE_VDDIO_CHANGE_X
parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 1;
`else
parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 0;
`endif
integer disable_enable_vddio_change_x = DISABLE_ENABLE_VDDIO_CHANGE_X;
reg notifier_enable_h;
specify
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_DELAY
specparam DELAY = 0;
`else
specparam DELAY = 50;
`endif
if (INP_SEL_H==0 & ENABLE_H==0 & ENABLE_VDDIO==0 & EN_VDDIO_SIG_H==1) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==1 & ENABLE_VDDIO==1 & EN_VDDIO_SIG_H==1) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==1 & ENABLE_VDDIO==1 & EN_VDDIO_SIG_H==0) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==0 & ENABLE_VDDIO==0 & EN_VDDIO_SIG_H==0) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==1) (FILT_IN_H => XRES_H_N) = (0:0:0 , 0:0:0);
specparam tsetup = 0;
specparam thold = 5;
$setuphold (posedge ENABLE_VDDIO, posedge ENABLE_H, tsetup, thold, notifier_enable_h);
$setuphold (negedge ENABLE_H, negedge ENABLE_VDDIO, tsetup, thold, notifier_enable_h);
endspecify
reg corrupt_enable;
always @(notifier_enable_h)
begin
corrupt_enable <= 1'bx;
end
initial
begin
corrupt_enable = 1'b0;
end
always @(PAD or ENABLE_H or EN_VDDIO_SIG_H or ENABLE_VDDIO or INP_SEL_H or FILT_IN_H or pwr_good_xres_tmp or DISABLE_PULLUP_H or PULLUP_H or TIE_WEAK_HI_H)
begin
corrupt_enable <= 1'b0;
end
assign mode_vcchib = ENABLE_H && !EN_VDDIO_SIG_H;
wire xres_tmp = (pwr_good_xres_tmp===0 || ^PAD===1'bx || (mode_vcchib===1'bx ) ||(mode_vcchib!==1'b0 && ^ENABLE_VDDIO===1'bx) || (corrupt_enable===1'bx) ||
(mode_vcchib===1'b1 && ENABLE_VDDIO===0 && (disable_enable_vddio_change_x===0)))
? 1'bx : PAD;
wire x_on_xres_h_n = (pwr_good_xres_h_n===0
|| ^INP_SEL_H===1'bx
|| INP_SEL_H===1 && ^FILT_IN_H===1'bx
|| INP_SEL_H===0 && xres_tmp===1'bx);
assign #1 XRES_H_N = x_on_xres_h_n===1 ? 1'bx : (INP_SEL_H===1 ? FILT_IN_H : xres_tmp);
realtime t_pad_current_transition,t_pad_prev_transition;
realtime t_filt_in_h_current_transition,t_filt_in_h_prev_transition;
realtime pad_pulse_width, filt_in_h_pulse_width;
always @(PAD)
begin
if (^PAD !== 1'bx)
begin
t_pad_prev_transition = t_pad_current_transition;
t_pad_current_transition = $realtime;
pad_pulse_width = t_pad_current_transition - t_pad_prev_transition;
end
else
begin
t_pad_prev_transition = 0;
t_pad_current_transition = 0;
pad_pulse_width = 0;
end
end
always @(FILT_IN_H)
begin
if (^FILT_IN_H !== 1'bx)
begin
t_filt_in_h_prev_transition = t_filt_in_h_current_transition;
t_filt_in_h_current_transition = $realtime;
filt_in_h_pulse_width = t_filt_in_h_current_transition - t_filt_in_h_prev_transition;
end
else
begin
t_filt_in_h_prev_transition = 0;
t_filt_in_h_current_transition = 0;
filt_in_h_pulse_width = 0;
end
end
reg dis_err_msgs;
integer msg_count_pad, msg_count_filt_in_h;
event event_errflag_pad_pulse_width, event_errflag_filt_in_h_pulse_width;
initial
begin
dis_err_msgs = 1'b1;
msg_count_pad = 0; msg_count_filt_in_h = 0;
`ifdef SKY130_FD_IO_TOP_XRES4V2_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
always @(pad_pulse_width)
begin
if (!dis_err_msgs)
begin
if (INP_SEL_H===0 && (pad_pulse_width > min_delay) && (pad_pulse_width < max_delay))
begin
msg_count_pad = msg_count_pad + 1;
->event_errflag_pad_pulse_width;
if (msg_count_pad <= MAX_WARNING_COUNT)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Width of Input pulse for PAD input (= %3.2f ns) is found to be in \the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \%m",pad_pulse_width,min_delay,max_delay,$stime);
end
else
if (msg_count_pad == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
always @(filt_in_h_pulse_width)
begin
if (!dis_err_msgs)
begin
if (INP_SEL_H===1 && (filt_in_h_pulse_width > min_delay) && (filt_in_h_pulse_width < max_delay))
begin
msg_count_filt_in_h = msg_count_filt_in_h + 1;
->event_errflag_filt_in_h_pulse_width;
if (msg_count_filt_in_h <= MAX_WARNING_COUNT)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Width of Input pulse for FILT_IN_H input (= %3.2f ns) is found to be in \the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \%m",filt_in_h_pulse_width,min_delay,max_delay,$stime);
end
else
if (msg_count_filt_in_h == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:34:06 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_mid/bg_mid_sim_netlist.v
// Design : bg_mid
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bg_mid,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bg_mid
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [14:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [14:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [14:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [14:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "15" *)
(* C_ADDRB_WIDTH = "15" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "5" *)
(* C_COUNT_36K_BRAM = "5" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 7.0707579999999997 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bg_mid.mem" *)
(* C_INIT_FILE_NAME = "bg_mid.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "18560" *)
(* C_READ_DEPTH_B = "18560" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "18560" *)
(* C_WRITE_DEPTH_B = "18560" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
bg_mid_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[14:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[14:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "bindec" *)
module bg_mid_bindec
(ena_array,
addra);
output [4:0]ena_array;
input [2:0]addra;
wire [2:0]addra;
wire [4:0]ena_array;
LUT3 #(
.INIT(8'h01))
ENOUT
(.I0(addra[2]),
.I1(addra[0]),
.I2(addra[1]),
.O(ena_array[0]));
LUT3 #(
.INIT(8'h04))
ENOUT__0
(.I0(addra[2]),
.I1(addra[0]),
.I2(addra[1]),
.O(ena_array[1]));
LUT3 #(
.INIT(8'h04))
ENOUT__1
(.I0(addra[0]),
.I1(addra[1]),
.I2(addra[2]),
.O(ena_array[2]));
LUT3 #(
.INIT(8'h08))
ENOUT__2
(.I0(addra[1]),
.I1(addra[0]),
.I2(addra[2]),
.O(ena_array[3]));
LUT3 #(
.INIT(8'h04))
ENOUT__3
(.I0(addra[0]),
.I1(addra[2]),
.I2(addra[1]),
.O(ena_array[4]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bg_mid_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [14:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [14:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [4:0]ena_array;
wire ram_douta;
wire ram_ena_n_0;
wire \ramloop[1].ram.r_n_0 ;
wire \ramloop[1].ram.r_n_1 ;
wire \ramloop[1].ram.r_n_2 ;
wire \ramloop[1].ram.r_n_3 ;
wire \ramloop[2].ram.r_n_0 ;
wire \ramloop[3].ram.r_n_0 ;
wire \ramloop[4].ram.r_n_0 ;
wire \ramloop[5].ram.r_n_0 ;
wire \ramloop[5].ram.r_n_1 ;
wire \ramloop[5].ram.r_n_2 ;
wire \ramloop[5].ram.r_n_3 ;
wire \ramloop[5].ram.r_n_4 ;
wire \ramloop[5].ram.r_n_5 ;
wire \ramloop[5].ram.r_n_6 ;
wire \ramloop[5].ram.r_n_7 ;
wire \ramloop[6].ram.r_n_0 ;
wire \ramloop[6].ram.r_n_1 ;
wire \ramloop[6].ram.r_n_2 ;
wire \ramloop[6].ram.r_n_3 ;
wire \ramloop[6].ram.r_n_4 ;
wire \ramloop[6].ram.r_n_5 ;
wire \ramloop[6].ram.r_n_6 ;
wire \ramloop[6].ram.r_n_7 ;
wire \ramloop[7].ram.r_n_0 ;
wire \ramloop[7].ram.r_n_1 ;
wire \ramloop[7].ram.r_n_2 ;
wire \ramloop[7].ram.r_n_3 ;
wire \ramloop[7].ram.r_n_4 ;
wire \ramloop[7].ram.r_n_5 ;
wire \ramloop[7].ram.r_n_6 ;
wire \ramloop[7].ram.r_n_7 ;
wire \ramloop[8].ram.r_n_0 ;
wire \ramloop[8].ram.r_n_1 ;
wire \ramloop[8].ram.r_n_2 ;
wire \ramloop[8].ram.r_n_3 ;
wire \ramloop[8].ram.r_n_4 ;
wire \ramloop[8].ram.r_n_5 ;
wire \ramloop[8].ram.r_n_6 ;
wire \ramloop[8].ram.r_n_7 ;
wire \ramloop[9].ram.r_n_0 ;
wire \ramloop[9].ram.r_n_1 ;
wire \ramloop[9].ram.r_n_2 ;
wire \ramloop[9].ram.r_n_3 ;
wire \ramloop[9].ram.r_n_4 ;
wire \ramloop[9].ram.r_n_5 ;
wire \ramloop[9].ram.r_n_6 ;
wire \ramloop[9].ram.r_n_7 ;
wire [0:0]wea;
bg_mid_bindec \bindec_a.bindec_inst_a
(.addra(addra[14:12]),
.ena_array(ena_array));
bg_mid_blk_mem_gen_mux \has_mux_a.A
(.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram ({\ramloop[1].ram.r_n_0 ,\ramloop[1].ram.r_n_1 ,\ramloop[1].ram.r_n_2 ,\ramloop[1].ram.r_n_3 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0 (ram_douta),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1 (\ramloop[2].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2 (\ramloop[3].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3 (\ramloop[4].ram.r_n_0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ({\ramloop[8].ram.r_n_0 ,\ramloop[8].ram.r_n_1 ,\ramloop[8].ram.r_n_2 ,\ramloop[8].ram.r_n_3 ,\ramloop[8].ram.r_n_4 ,\ramloop[8].ram.r_n_5 ,\ramloop[8].ram.r_n_6 ,\ramloop[8].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }),
.DOADO({\ramloop[9].ram.r_n_0 ,\ramloop[9].ram.r_n_1 ,\ramloop[9].ram.r_n_2 ,\ramloop[9].ram.r_n_3 ,\ramloop[9].ram.r_n_4 ,\ramloop[9].ram.r_n_5 ,\ramloop[9].ram.r_n_6 ,\ramloop[9].ram.r_n_7 }),
.addra(addra[14:12]),
.clka(clka),
.douta(douta));
LUT1 #(
.INIT(2'h1))
ram_ena
(.I0(addra[14]),
.O(ram_ena_n_0));
bg_mid_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra[13:0]),
.\addra[14] (ram_ena_n_0),
.clka(clka),
.dina(dina[0]),
.\douta[0] (ram_douta),
.wea(wea));
bg_mid_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra[11:0]),
.clka(clka),
.dina(dina[3:0]),
.\douta[3] ({\ramloop[1].ram.r_n_0 ,\ramloop[1].ram.r_n_1 ,\ramloop[1].ram.r_n_2 ,\ramloop[1].ram.r_n_3 }),
.ena_array(ena_array[4]),
.wea(wea));
bg_mid_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra[13:0]),
.\addra[14] (ram_ena_n_0),
.clka(clka),
.dina(dina[1]),
.\douta[1] (\ramloop[2].ram.r_n_0 ),
.wea(wea));
bg_mid_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.addra(addra[13:0]),
.\addra[14] (ram_ena_n_0),
.clka(clka),
.dina(dina[2]),
.\douta[2] (\ramloop[3].ram.r_n_0 ),
.wea(wea));
bg_mid_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.addra(addra[13:0]),
.\addra[14] (ram_ena_n_0),
.clka(clka),
.dina(dina[3]),
.\douta[3] (\ramloop[4].ram.r_n_0 ),
.wea(wea));
bg_mid_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.addra(addra[11:0]),
.clka(clka),
.dina(dina[11:4]),
.\douta[11] ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }),
.ena_array(ena_array[0]),
.wea(wea));
bg_mid_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.addra(addra[11:0]),
.clka(clka),
.dina(dina[11:4]),
.\douta[11] ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }),
.ena_array(ena_array[1]),
.wea(wea));
bg_mid_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.addra(addra[11:0]),
.clka(clka),
.dina(dina[11:4]),
.\douta[11] ({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }),
.ena_array(ena_array[2]),
.wea(wea));
bg_mid_blk_mem_gen_prim_width__parameterized7 \ramloop[8].ram.r
(.addra(addra[11:0]),
.clka(clka),
.dina(dina[11:4]),
.\douta[11] ({\ramloop[8].ram.r_n_0 ,\ramloop[8].ram.r_n_1 ,\ramloop[8].ram.r_n_2 ,\ramloop[8].ram.r_n_3 ,\ramloop[8].ram.r_n_4 ,\ramloop[8].ram.r_n_5 ,\ramloop[8].ram.r_n_6 ,\ramloop[8].ram.r_n_7 }),
.ena_array(ena_array[3]),
.wea(wea));
bg_mid_blk_mem_gen_prim_width__parameterized8 \ramloop[9].ram.r
(.DOADO({\ramloop[9].ram.r_n_0 ,\ramloop[9].ram.r_n_1 ,\ramloop[9].ram.r_n_2 ,\ramloop[9].ram.r_n_3 ,\ramloop[9].ram.r_n_4 ,\ramloop[9].ram.r_n_5 ,\ramloop[9].ram.r_n_6 ,\ramloop[9].ram.r_n_7 }),
.addra(addra[11:0]),
.clka(clka),
.dina(dina[11:4]),
.ena_array(ena_array[4]),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module bg_mid_blk_mem_gen_mux
(douta,
DOADO,
addra,
clka,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1 ,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2 ,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3 ,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 ,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 );
output [11:0]douta;
input [7:0]DOADO;
input [2:0]addra;
input clka;
input [3:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 ;
wire [3:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 ;
wire [7:0]DOADO;
wire [2:0]addra;
wire clka;
wire [11:0]douta;
wire \douta[10]_INST_0_i_1_n_0 ;
wire \douta[10]_INST_0_i_2_n_0 ;
wire \douta[11]_INST_0_i_1_n_0 ;
wire \douta[11]_INST_0_i_2_n_0 ;
wire \douta[4]_INST_0_i_1_n_0 ;
wire \douta[4]_INST_0_i_2_n_0 ;
wire \douta[5]_INST_0_i_1_n_0 ;
wire \douta[5]_INST_0_i_2_n_0 ;
wire \douta[6]_INST_0_i_1_n_0 ;
wire \douta[6]_INST_0_i_2_n_0 ;
wire \douta[7]_INST_0_i_1_n_0 ;
wire \douta[7]_INST_0_i_2_n_0 ;
wire \douta[8]_INST_0_i_1_n_0 ;
wire \douta[8]_INST_0_i_2_n_0 ;
wire \douta[9]_INST_0_i_1_n_0 ;
wire \douta[9]_INST_0_i_2_n_0 ;
wire [2:0]sel_pipe;
wire [2:0]sel_pipe_d1;
LUT5 #(
.INIT(32'h04FF0400))
\douta[0]_INST_0
(.I0(sel_pipe_d1[0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram [0]),
.I2(sel_pipe_d1[1]),
.I3(sel_pipe_d1[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0 ),
.O(douta[0]));
MUXF7 \douta[10]_INST_0
(.I0(\douta[10]_INST_0_i_1_n_0 ),
.I1(\douta[10]_INST_0_i_2_n_0 ),
.O(douta[10]),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\douta[10]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [6]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 [6]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 [6]),
.O(\douta[10]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h04))
\douta[10]_INST_0_i_2
(.I0(sel_pipe_d1[0]),
.I1(DOADO[6]),
.I2(sel_pipe_d1[1]),
.O(\douta[10]_INST_0_i_2_n_0 ));
MUXF7 \douta[11]_INST_0
(.I0(\douta[11]_INST_0_i_1_n_0 ),
.I1(\douta[11]_INST_0_i_2_n_0 ),
.O(douta[11]),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\douta[11]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [7]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 [7]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 [7]),
.O(\douta[11]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h04))
\douta[11]_INST_0_i_2
(.I0(sel_pipe_d1[0]),
.I1(DOADO[7]),
.I2(sel_pipe_d1[1]),
.O(\douta[11]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'h04FF0400))
\douta[1]_INST_0
(.I0(sel_pipe_d1[0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram [1]),
.I2(sel_pipe_d1[1]),
.I3(sel_pipe_d1[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1 ),
.O(douta[1]));
LUT5 #(
.INIT(32'h04FF0400))
\douta[2]_INST_0
(.I0(sel_pipe_d1[0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram [2]),
.I2(sel_pipe_d1[1]),
.I3(sel_pipe_d1[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2 ),
.O(douta[2]));
LUT5 #(
.INIT(32'h04FF0400))
\douta[3]_INST_0
(.I0(sel_pipe_d1[0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram [3]),
.I2(sel_pipe_d1[1]),
.I3(sel_pipe_d1[2]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3 ),
.O(douta[3]));
MUXF7 \douta[4]_INST_0
(.I0(\douta[4]_INST_0_i_1_n_0 ),
.I1(\douta[4]_INST_0_i_2_n_0 ),
.O(douta[4]),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\douta[4]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [0]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 [0]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 [0]),
.O(\douta[4]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h04))
\douta[4]_INST_0_i_2
(.I0(sel_pipe_d1[0]),
.I1(DOADO[0]),
.I2(sel_pipe_d1[1]),
.O(\douta[4]_INST_0_i_2_n_0 ));
MUXF7 \douta[5]_INST_0
(.I0(\douta[5]_INST_0_i_1_n_0 ),
.I1(\douta[5]_INST_0_i_2_n_0 ),
.O(douta[5]),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\douta[5]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [1]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 [1]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 [1]),
.O(\douta[5]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h04))
\douta[5]_INST_0_i_2
(.I0(sel_pipe_d1[0]),
.I1(DOADO[1]),
.I2(sel_pipe_d1[1]),
.O(\douta[5]_INST_0_i_2_n_0 ));
MUXF7 \douta[6]_INST_0
(.I0(\douta[6]_INST_0_i_1_n_0 ),
.I1(\douta[6]_INST_0_i_2_n_0 ),
.O(douta[6]),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\douta[6]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [2]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 [2]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 [2]),
.O(\douta[6]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h04))
\douta[6]_INST_0_i_2
(.I0(sel_pipe_d1[0]),
.I1(DOADO[2]),
.I2(sel_pipe_d1[1]),
.O(\douta[6]_INST_0_i_2_n_0 ));
MUXF7 \douta[7]_INST_0
(.I0(\douta[7]_INST_0_i_1_n_0 ),
.I1(\douta[7]_INST_0_i_2_n_0 ),
.O(douta[7]),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\douta[7]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [3]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 [3]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 [3]),
.O(\douta[7]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h04))
\douta[7]_INST_0_i_2
(.I0(sel_pipe_d1[0]),
.I1(DOADO[3]),
.I2(sel_pipe_d1[1]),
.O(\douta[7]_INST_0_i_2_n_0 ));
MUXF7 \douta[8]_INST_0
(.I0(\douta[8]_INST_0_i_1_n_0 ),
.I1(\douta[8]_INST_0_i_2_n_0 ),
.O(douta[8]),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\douta[8]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [4]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 [4]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 [4]),
.O(\douta[8]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h04))
\douta[8]_INST_0_i_2
(.I0(sel_pipe_d1[0]),
.I1(DOADO[4]),
.I2(sel_pipe_d1[1]),
.O(\douta[8]_INST_0_i_2_n_0 ));
MUXF7 \douta[9]_INST_0
(.I0(\douta[9]_INST_0_i_1_n_0 ),
.I1(\douta[9]_INST_0_i_2_n_0 ),
.O(douta[9]),
.S(sel_pipe_d1[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\douta[9]_INST_0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [5]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 [5]),
.I4(sel_pipe_d1[0]),
.I5(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 [5]),
.O(\douta[9]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h04))
\douta[9]_INST_0_i_2
(.I0(sel_pipe_d1[0]),
.I1(DOADO[5]),
.I2(sel_pipe_d1[1]),
.O(\douta[9]_INST_0_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[0]),
.Q(sel_pipe_d1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[1]),
.Q(sel_pipe_d1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[2]),
.Q(sel_pipe_d1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clka),
.CE(1'b1),
.D(addra[0]),
.Q(sel_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clka),
.CE(1'b1),
.D(addra[1]),
.Q(sel_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]
(.C(clka),
.CE(1'b1),
.D(addra[2]),
.Q(sel_pipe[2]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_mid_blk_mem_gen_prim_width
(\douta[0] ,
clka,
\addra[14] ,
addra,
dina,
wea);
output [0:0]\douta[0] ;
input clka;
input \addra[14] ;
input [13:0]addra;
input [0:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire \addra[14] ;
wire clka;
wire [0:0]dina;
wire [0:0]\douta[0] ;
wire [0:0]wea;
bg_mid_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.\addra[14] (\addra[14] ),
.clka(clka),
.dina(dina),
.\douta[0] (\douta[0] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_mid_blk_mem_gen_prim_width__parameterized0
(\douta[3] ,
clka,
ena_array,
addra,
dina,
wea);
output [3:0]\douta[3] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [3:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [3:0]dina;
wire [3:0]\douta[3] ;
wire [0:0]ena_array;
wire [0:0]wea;
bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.\douta[3] (\douta[3] ),
.ena_array(ena_array),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_mid_blk_mem_gen_prim_width__parameterized1
(\douta[1] ,
clka,
\addra[14] ,
addra,
dina,
wea);
output [0:0]\douta[1] ;
input clka;
input \addra[14] ;
input [13:0]addra;
input [0:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire \addra[14] ;
wire clka;
wire [0:0]dina;
wire [0:0]\douta[1] ;
wire [0:0]wea;
bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram
(.addra(addra),
.\addra[14] (\addra[14] ),
.clka(clka),
.dina(dina),
.\douta[1] (\douta[1] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_mid_blk_mem_gen_prim_width__parameterized2
(\douta[2] ,
clka,
\addra[14] ,
addra,
dina,
wea);
output [0:0]\douta[2] ;
input clka;
input \addra[14] ;
input [13:0]addra;
input [0:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire \addra[14] ;
wire clka;
wire [0:0]dina;
wire [0:0]\douta[2] ;
wire [0:0]wea;
bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2 \prim_init.ram
(.addra(addra),
.\addra[14] (\addra[14] ),
.clka(clka),
.dina(dina),
.\douta[2] (\douta[2] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_mid_blk_mem_gen_prim_width__parameterized3
(\douta[3] ,
clka,
\addra[14] ,
addra,
dina,
wea);
output [0:0]\douta[3] ;
input clka;
input \addra[14] ;
input [13:0]addra;
input [0:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire \addra[14] ;
wire clka;
wire [0:0]dina;
wire [0:0]\douta[3] ;
wire [0:0]wea;
bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3 \prim_init.ram
(.addra(addra),
.\addra[14] (\addra[14] ),
.clka(clka),
.dina(dina),
.\douta[3] (\douta[3] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_mid_blk_mem_gen_prim_width__parameterized4
(\douta[11] ,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]\douta[11] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]\douta[11] ;
wire [0:0]ena_array;
wire [0:0]wea;
bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.\douta[11] (\douta[11] ),
.ena_array(ena_array),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_mid_blk_mem_gen_prim_width__parameterized5
(\douta[11] ,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]\douta[11] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]\douta[11] ;
wire [0:0]ena_array;
wire [0:0]wea;
bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.\douta[11] (\douta[11] ),
.ena_array(ena_array),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_mid_blk_mem_gen_prim_width__parameterized6
(\douta[11] ,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]\douta[11] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]\douta[11] ;
wire [0:0]ena_array;
wire [0:0]wea;
bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.\douta[11] (\douta[11] ),
.ena_array(ena_array),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_mid_blk_mem_gen_prim_width__parameterized7
(\douta[11] ,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]\douta[11] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]\douta[11] ;
wire [0:0]ena_array;
wire [0:0]wea;
bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.\douta[11] (\douta[11] ),
.ena_array(ena_array),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_mid_blk_mem_gen_prim_width__parameterized8
(DOADO,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]DOADO;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [7:0]DOADO;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [0:0]ena_array;
wire [0:0]wea;
bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8 \prim_init.ram
(.DOADO(DOADO),
.addra(addra),
.clka(clka),
.dina(dina),
.ena_array(ena_array),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_mid_blk_mem_gen_prim_wrapper_init
(\douta[0] ,
clka,
\addra[14] ,
addra,
dina,
wea);
output [0:0]\douta[0] ;
input clka;
input \addra[14] ;
input [13:0]addra;
input [0:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire \addra[14] ;
wire clka;
wire [0:0]dina;
wire [0:0]\douta[0] ;
wire [0:0]wea;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hFFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_01(256'hFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_02(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF43FFFFFFF),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF73FFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFF43FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hEFFEFFE63EFFEFFEFFEFFEFFFFFFFFFFFDFFDFFDFFDFFDFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FF7FF7FF7FF7FF7FF7FF7FFFFFFFFFF),
.INIT_08(256'hFEFFEFFEFFEFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF),
.INIT_09(256'hBFFBFFBFFBFFBFFBFFFFFFFF7FF7FF7FF7FF7FF27F7FF7FFFFFFFFFFEFFEFFEF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFA7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFDFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF96FFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFBFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFDFFFFFB7FFFFFFFFFFFFFFDFFFFFFF7FFFFFFFFFFFFFFFF),
.INIT_10(256'hFFFFFFFA7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_11(256'hFFEFFFFFFFFFFFFFFFFF7FBFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_12(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFF),
.INIT_13(256'hFFFFFFDFFFFFFFFFFFFFFFFFFFDFFFFFFFFFFFF97FFBFEFFFFFFFFFFFFFFFFFF),
.INIT_14(256'hFFFFFFFFFFFFFFFFFFFFFFF97FF7FFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFF),
.INIT_15(256'hFFFFFF737EFFF7FFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFF),
.INIT_16(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFBFFFFDF),
.INIT_17(256'hFFFFF7FFFFFFFFFFFFFFFFFFFFFDFFFFF7FFFFFFFFFFFFFFFFFFFFEA7FFFFFFF),
.INIT_18(256'hFFFBFFFFFF7FFFFFFDFFFBFDBFFFFFFBFF7FFFFB7FFFFFFFFFFFFFFFFFFFFFF7),
.INIT_19(256'hFFFFFEFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFEF7F),
.INIT_1A(256'hFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDBFFFFFFFFFFFFFFFFFFFF),
.INIT_1B(256'hFFFFFFFFFFFFFFF7FBFFFDFFFFFFF7FFFFFFFFFDFFBFFFFFFFFFFFFFFFFFFFFF),
.INIT_1C(256'hFF7FBF7FFFFF7FFFFFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF),
.INIT_1D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFEDBD7F),
.INIT_1E(256'hFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFFFFFFFFFFFFFFFFF7FDFFFFFFFFFFFFFF),
.INIT_1F(256'hFFFFFFFB7FFFFFFFFFFFEEFFFFFFDFFFFBFFDFFF7FFFFFFFFFFFFFFFFFFFFFFF),
.INIT_20(256'hFFFEFF7FFFFEEFFFFFFFFFFFFBFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_21(256'hFEFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF),
.INIT_22(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFBFFFD),
.INIT_23(256'hFFFFFFFFBFFFFFFFFFFFFFFA7FFFFFFFFFFFFFBFFF5F8FDBFFFFFFDFFFFFBFFF),
.INIT_24(256'hFFFFFFF97FDFFFFFFFFEFFFFFDFEFFFFFFFFBDFFFFFFFFBFFFFFFFFFFFFFFFFF),
.INIT_25(256'hFFBFEBFFFFFFBFEFFBF7FFDFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_26(256'hFEFF7FFDFBEEFFFFFFFFFFFBFFFFFFFFFFFFFFFBFFFF9FFFFFFFFFFB7FFFF7FF),
.INIT_27(256'hBBFFFFFF5FF7FFFFFFFFFFFFFFFFFFFFFFFFFDFA7FFFFEFFFFDFDF7FFFF6FFFE),
.INIT_28(256'hFFFFFFEFFFFFFFFFFFFFFEFA6FF7DFFFFFFFFD7BBEEFFFFFFFFEFFFFFEFFFFFF),
.INIT_29(256'hFFFFFFFB5FEFFFDF7FFFFFFFEFFF5BDFFFFFDFFFFFFFFFFFFFFFFFFFFFFEFFFF),
.INIT_2A(256'hFDFFFFFEFB7FFFFDFFFE7FFFFFFFFF7FBEFFFFFFF7FFFDFFFFFFFFFFFFFFFEFF),
.INIT_2B(256'hFFFFFFFFEFFFB7FFFFFBFFFD7DEFFFFFFFFFFFFFFFFFFFDFFFFBFFD97FFFFEFF),
.INIT_2C(256'hFFFFFFFFFEFFEFFFFFFFFFFFFFFFF7FEFFBFDFFA3FFFFFFFFF3F7FFFFEFFFF7F),
.INIT_2D(256'hFFFFFFFFFFFBADFFEFDFFF7B7FFFFFFDFFFFFFFFFFFFFFFFFFFD3FFFE3FFFFFF),
.INIT_2E(256'hFFFF7FFA7FBB767BFFBFFFFFFFEEFFEFFDBFFFFFFFFDFFFFFFFFFFFFDFFFFFFD),
.INIT_2F(256'hBB7FFFFFFFF74FFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBDDCCFED),
.INIT_30(256'hFEFFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFBFFFFAF77772BF63BFFFDDB7FD16AAD),
.INIT_31(256'hFFFFFFFFFFFFFFFEFFBFD2AEBF72F15AFCEED7EA7DE8DFC8B5B76FFFFEFDFFDF),
.INIT_32(256'hFFDFADBBFFFF5758AFBF74495DBFD6F3D98FFD6FFFFFABFBFFFFFFFFFFFFFFFF),
.INIT_33(256'hDCE6FFF27B42F9AFEB69632F3FFDFFEFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_34(256'h7CEF6EA4DFFF5FFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFEFFFFFADBF56D3CFC7B),
.INIT_35(256'h7FFFFFFFFFFDBFFFFFFFFFFFFFFFFFFFFFF7AD6FFEFFFE7FE7BF697969FA4FF1),
.INIT_36(256'hFFFFFFFFFFFFFFFFFFD91DFB43FD6C69AAFD9FD35DE4F3AEA13F9B4F88BBFDFF),
.INIT_37(256'hF6FDFFFEBCECB2FAEAFEBEF33DD4F49EF953DD4F6D6FFFFFFFFFFFFFFFFFDFFF),
.INIT_38(256'h9963EB3A12236E9B4AFB2236684FFFFFFDFFFFFFFBFFFDFFFFFFFFFFFFFFFFFF),
.INIT_39(256'hB7EAEFBD55BBFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFDAF466DB3ECDE4EF7),
.INIT_3A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7CECFBBEE1B7D6DD776DD6EFB4EFBDCB5),
.INIT_3B(256'hFFEFFFBFFFBF7B7FBA66DD59F19AB2765FF6F70128DCD396FC648DCDA7133FFF),
.INIT_3C(256'h7E5D965F7FFA25A6197CAEB90EEF9E97A6AEEEF9F7A6C2FBFDFFFFFFFFFFFFFF),
.INIT_3D(256'hAFA95F635D77303C3BB5D773B85CD1FFF7FFFFFFFFFFEFFFFFFFEFBBDBFA7FAE),
.INIT_3E(256'h54D2319F77BB4F3FFFFFFFFFFFFFFDFFFFEC979E64D7479133B3C9DDDB45E1CE),
.INIT_3F(256'hFFFFFFFFFFFFF7FFFFEFFC63AB6D9BDBEB7FADBACEF6FBA57876544A6319F7F3),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR(addra),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:1],\douta[0] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(\addra[14] ),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0
(\douta[3] ,
clka,
ena_array,
addra,
dina,
wea);
output [3:0]\douta[3] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [3:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [3:0]dina;
wire [3:0]\douta[3] ;
wire [0:0]ena_array;
wire [0:0]wea;
wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h5055500505505545404455350500450054605055750555065070030075033055),
.INIT_01(256'h0550755570304057505550745555407900554044553505004500542505045434),
.INIT_02(256'h4507553053055075070745564540775405550477050733505300064356657072),
.INIT_03(256'h5FF9575756550555565755555305505555055553705545505740035000705504),
.INIT_04(256'h605555559775597F95F57F5F77B759777D79FF977F7F5777FB77FF95F5F95757),
.INIT_05(256'h0055057035500555035705555073550555507007000707455005737075050750),
.INIT_06(256'h0540320545557053705005070577007900550357055550735505055555055035),
.INIT_07(256'h7037555353505555050005447073475555350534505550705405055745000555),
.INIT_08(256'h7977550503575550575453320234000746504505507037755430545050055437),
.INIT_09(256'h53020555579F5F977957F777F797DFF57777977F9797F9B77779777F597F7F7F),
.INIT_0A(256'h4505305070453403753040050057405440505535775573453570003050750565),
.INIT_0B(256'h9053555300500007005570523503306904537530400500574054300054403703),
.INIT_0C(256'h5550555050755600545553444455500750455555055005370005505507577555),
.INIT_0D(256'h7755754777070755577005055535555305055575557505543350670575553444),
.INIT_0E(256'h0070030735557559D7F775F779F399955F59BDF757F7F99BF77F7F77BF579797),
.INIT_0F(256'h5534555355050505405053545755455050452050300705000007055705003705),
.INIT_10(256'h5000500075555550544505555370507805354050535457554550005425505475),
.INIT_11(256'h7755075735002550370555554575457074556055770775507500555055030075),
.INIT_12(256'h5504557550457547550455534050555055540700575755672523570300505554),
.INIT_13(256'h55275033500535555579595FF5797FF777795775F77F79F77F95F77F57B7D7D7),
.INIT_14(256'h0500730355350030505500003005055903005557057055055704555003555070),
.INIT_15(256'h5500547547055340355700005005008900505055000030050559035300070555),
.INIT_16(256'h3056553075500073350530006435660554405570705070755790535004755505),
.INIT_17(256'h5775755055667050567503504750507556506755505055575053053350540006),
.INIT_18(256'h055005030500300005353572597537F79F57FF95B77F95F7F577FF79977F5F5F),
.INIT_19(256'h5307500555305043050050570505550504035352505053523573353003007550),
.INIT_1A(256'h0457507503003375035500455430709807730500505705055505545550703050),
.INIT_1B(256'h7540737063507555070540505574500570057705704055000720500005705707),
.INIT_1C(256'h7405554505007055047046300075057505075065767755750575555050550555),
.INIT_1D(256'h53004030505005355050050335755557557755F5979577399F959775BF959597),
.INIT_1E(256'h7570550300000550757077005300300355000555300705370435030545320303),
.INIT_1F(256'h0535350353450400735000505070007903307570770053003003053507350707),
.INIT_20(256'h0343044070505050555505550405507507503050057750030535073030740303),
.INIT_21(256'h0555070550453003053507303074030305353503534504007350005305353503),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:4],\douta[3] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(ena_array),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1
(\douta[1] ,
clka,
\addra[14] ,
addra,
dina,
wea);
output [0:0]\douta[1] ;
input clka;
input \addra[14] ;
input [13:0]addra;
input [0:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire \addra[14] ;
wire clka;
wire [0:0]dina;
wire [0:0]\douta[1] ;
wire [0:0]wea;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hB5DB5DB5C95D6EF67D27EDDC4FA4FA4FB6BB6BB6B92B92B9BBDBBDBB49F49F49),
.INIT_01(256'hFEDF9AFB3FDBFDBF59F59F59F7DF7DF75F35F35FB7FB7FB7F6EF6EF67D27D27D),
.INIT_02(256'h7D57D57DC79C79C78E78E78EFAAFAAFACD7CD7CDFEDFEDFECFACFACFBEFAD7CD),
.INIT_03(256'h6FF6FF6F76F76F769E39E39EABEABEABEABEABEA3CE3E39EABEB3C74157D57D5),
.INIT_04(256'hFDBFDBFDBDDBDDBDDBDDBDDBDFFDDBFDBDDBFB7737BB7BB7BB7BB7BBFBFFBFFB),
.INIT_05(256'h67D67D6756356356B76B76B42B3EB3EBACFACFAC6AC6AC6AD6ED6ED67D67D67D),
.INIT_06(256'hA76A76A638778778E5CE5CE54E54E54ED4ED4ED4EF0EF0EFBB5BB5BB59F59F59),
.INIT_07(256'hEF7EF7EFFEBFEBFEAFEAFEAFFAFFAFFA3B53B53BC3BC3BC32E72E72E72A72A72),
.INIT_08(256'hD67D67D6FF6FF6FFFABFABFABFEBFEBF7BF7BF7BF5FF5FF57F57F57A57FD7FD7),
.INIT_09(256'h9F59F59FDBFDBFDBEFBEFBEF3EB3EB3EB3EB3EB27B7FB7FB7DF7DF7D67D67D67),
.INIT_0A(256'h75C75C75D71D71D79D79D79A6B9EB9EB8EB8EB8E3AE3AE3AF3AF3AF33D73D73D),
.INIT_0B(256'h9D79D79A6BDEBDEBCEBCEBCE3EE3EE3EF3AF3AF3BD7BD7BDEBCEBCEB5CF5CF5C),
.INIT_0C(256'hFFF7F5FB9EB7CFE4AFD7E927BE2D4C4AEBCEBCEB5EF5EF5E75E75E75F71F71F7),
.INIT_0D(256'h54FBB6EFC7F761CDFF3EFFBDFFDBFF0FD8FCCD9DFAE9DFC77F5657F865DB2BDD),
.INIT_0E(256'hF9ED77F3FFD766BFBEAE47EF9EF69A3E9B6FFF727E7DD253FFC76DD2BFAEFDA9),
.INIT_0F(256'hE6DB6B78F6F3B9AFFFFDEBEA7EFD8F9A6EFDFF7DFDDF7DE48E7D67FB48A4CF4F),
.INIT_10(256'hAFD743F27D6FEFE7775C69F3BFEEFABF696B7A2FA881A4DEDFB7FFEBDF7FDFF7),
.INIT_11(256'hFFEEFFF0F67BE31EFD651CBFF57ED6D5F6F4CB2D7EE3F5F7DBDE3BD2EAF9CDDE),
.INIT_12(256'h1C6F5DD7E8FF3D5F3F1774FDCEBF8F4D677E6B71FF55FFFFC57FCF9A73F577CD),
.INIT_13(256'hF55DB2FEE35D63F791D2FEFFDFDEF7F7FFFBFFFA7ED1DF37FFF9FF84CEF5FFFD),
.INIT_14(256'hAAD9B6FBFFF7B4E3EE31E7F077F7FFCF7F2EFE7F51DAF535F6F3AFEFADFB8BF0),
.INIT_15(256'h5FFEBD326ABD361BDB8DCEBC06732D1D9FB3FBF7A9FF21F66EEF3BEBDDFF67FE),
.INIT_16(256'hF508FC3A09E1D6FAFE667297F7FFAD3A87D9DCF7B57ADCEEFFFA7D5FFBEF664F),
.INIT_17(256'h89D4E74FFBECC10AFF2FFFEDB7BCAFFD735D37FFFEE5FDB79FFB67E87CBEA9DF),
.INIT_18(256'hFF9A7FEFED7F67FF5DFDE371BFBFD6D9FF2FFFF2217FF853FE530005357AFEB7),
.INIT_19(256'hFBDEAEE070A4BA07DFF1DD42257FB40517E9118293DC3FE5C59883FFCE5CC1EF),
.INIT_1A(256'hF4A6FAB236FFD54035F5DAD73877778E8EEBD8FFFC903EECFFFAFFFDBD697FFF),
.INIT_1B(256'h0F9781D280FAA177319C7DDAFF97475FFFFF6DF1FF07FFFFFFBBFD1E3F4AC87D),
.INIT_1C(256'hAC4ABA69E4D519FF9FFFEFDBD39FFFFFFE9FF8FF37DF4C7FDFFDEFE2697FEA59),
.INIT_1D(256'h1FFF6FF7FDFFFFFFFFFFFFFF0ED3A05EFFDBE9A8183FE236E7FFF1E3C2E8343E),
.INIT_1E(256'hFEDDDEEC01836377FFDEBF500C9C166CA2DFDBE0177CF4217C2AFD96D8E2CBFA),
.INIT_1F(256'h976BE81A3AFE89FF67DFEEF05FC7DBFF13F7DB47041005DF1FFFBFFFDFDDFFFF),
.INIT_20(256'hE59EFC760EF8E6D85C9FA0E45AC9C6FA5DFF3FFFBF7BFFF07E67AB778CDF1DE6),
.INIT_21(256'hB2F1CF8889BEEC6F24FFC7FB8DAFFFE650399EA530E2E5FE19A86B620C3B2FFF),
.INIT_22(256'h087F65BD777F7FF4FE9A7D84E7FF8F77332ECFDA42FED7561FFF79DF9F5BF78C),
.INIT_23(256'hEDA4D1B1B39FEF3B5F3B7D3213FE9FD3E6F75FAF7F5F089AADA7BA074FF6B87F),
.INIT_24(256'hFD76DFC83D5FFF3B9BDE684E7DBCF5D497609CE91DFFB81F8188759FFC7E04F7),
.INIT_25(256'hFF3FABA7F7F386A57B55698F1BBD7BEF70EE97FFFF7578485E751DDDE7E4F856),
.INIT_26(256'hCEA875617AA2E6DFFDFD5FFBFBDFD7F1C8EC3679A9FE9F58FFE7F56A19FEF5E6),
.INIT_27(256'h2BFEFFEF5FE77E9C973ECBFC4F7F7FA7BE7BFD786F7F7AFBC95DC811FBD6AD18),
.INIT_28(256'h29976BEEDFAF5FCC1FFAECFA6FF5D5B4FEE69C3B1EACE17ABF76EDE47E39FAC0),
.INIT_29(256'h223F7F4A4FCB5BD77F924B454184118F89C70AFF28F7DF55C57FFF8FFFF6FF6A),
.INIT_2A(256'h395527AE3853FD9197AA6A939130D26A3EBCDFFFF7FFED7DB6DE7FF9F9FFAAFF),
.INIT_2B(256'hF68DB15D2EB6A0FF77FB93FD09EE9AFBDD4BFFF27EFF098FFDFB9FD27FD6B27F),
.INIT_2C(256'hEEEACBBFCAAEEE7F6FBFFFEF9D37A1E8F9BFD1E23FF0070D511755FFCAE7EA3F),
.INIT_2D(256'hFEFFDFBD5BE7BD7B4F431C724ED35FDC759031FFFFFBB919BF2D2EDD62A7826F),
.INIT_2E(256'h2CE97FD864420149AF9CB3A7FFAE74AC3D93C78FDEF15BF56EE1D145DE9BE73D),
.INIT_2F(256'h0037FC7EFFF74A15054399F62F98CA3F52C1413F97DE8D47577FC7FC49922394),
.INIT_30(256'hB8979E4FF95F05EFCCB5DDBBCBF5EF6EFBEFB6470F680C6B3870800232DB5A25),
.INIT_31(256'h5542EFFDB73DEF96B5B4E04040BF1230CA2D03024CA46C55ADA055F9DCFD259C),
.INIT_32(256'hFBDB6DA28E404901046DF00208304000045484449BFF22DB6B67F577DF4FABF5),
.INIT_33(256'h34D0E8125200892C2000D9082FFDB15FABAEED3DF19B114F9E27FFD7F7EF7DEF),
.INIT_34(256'h448400008FD64D3AED972FAB3F67BEAFCA976BEF5D3DAEBEFAF6420622208A89),
.INIT_35(256'h7E35BCFFF219BFBFB17FF2B7BFD8FA36B7D02C8EA14C0D513380003008000844),
.INIT_36(256'h2DDFFBEB57EFFCFDEFDD0012206208E08A2C1C423000B198008A920B0A33BC93),
.INIT_37(256'hC6CC00420A008AD2020C8E0211102018111111022109D57F03547DF71FFB06DF),
.INIT_38(256'h1902A11A1010489A104901041003C5BF148B9FD5F94DA93583A9F7FDFDFBBBDE),
.INIT_39(256'h2162A40440B001AA2B3E7BEFD6C7B7CF4ADEEDF8D8FABFD9B9226820073444AA),
.INIT_3A(256'h2795BE5DEDE74CDFEEFFDBC7E7F1FC8646482A461001010622C548920A404405),
.INIT_3B(256'h5FE7EFB1915A1245900009005192886E44724002204400022000044000031DD1),
.INIT_3C(256'h66481158000005A4281802001241960B20872419C1B0CAF52CB796DF5DF67DFF),
.INIT_3D(256'h420045425906202C0B1190620890011EFF5F62FFEFAD2F5F65E6E09D5D5384A0),
.INIT_3E(256'h40C0301400A05E0D4FFF7D77F7A5C9FA72C51216280349113296889489202001),
.INIT_3F(256'hF7FF0BBCFF5F82FFBDC0B4422B7A0050C0682021808601001810100023014303),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR(addra),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:1],\douta[1] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(\addra[14] ),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2
(\douta[2] ,
clka,
\addra[14] ,
addra,
dina,
wea);
output [0:0]\douta[2] ;
input clka;
input \addra[14] ;
input [13:0]addra;
input [0:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire \addra[14] ;
wire clka;
wire [0:0]dina;
wire [0:0]\douta[2] ;
wire [0:0]wea;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hB5DB5DB549556EB679276DD44F24F24FB6BB6BB6A92A92A9BADBADBA49E49E49),
.INIT_01(256'hFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB6EB6EB679279279),
.INIT_02(256'h5D55D55DD79D79D78F38F38FBABBABBAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_03(256'h7FF7FF7FF7FF7FF7CE3CE3CEAEEAEEAEEAAEAAEABCEAE3CEAEEB9C7415DD5DD5),
.INIT_04(256'hFDFFDFFDFFDFFDFFDFFDFFDFFFFFDFFDFFDFFBF73FFBFFBFFBFFBFFBFFFFFFFF),
.INIT_05(256'h4BD4BD4BD6BD6BD63F23F23433BB3BB3A97A97A97AD7AD7A47E47E4776776776),
.INIT_06(256'hE76E76E63C77C77CE5CE5CE5CE5CE5CEDCEDCEDCEF8EF8EFF91F91F99DD9DD9D),
.INIT_07(256'hDF7DF7DFFFBFFBFFAFBAFBAFBAFBAFBA3B73B73BE3BE3BE32E72E72E72E72E72),
.INIT_08(256'hDC7DC7DCEFCEFCEFEEBEEBEEBEEBEEBEFBEFBEFBFDFFDFFD7DD7DD7A57DD7DD7),
.INIT_09(256'h1F71F71FF3BF3BF3AF3AF3AF3AF3AF3AE3EE3EE27E77E77E75E75E75E75E75E7),
.INIT_0A(256'hEDDEDDED5ED5ED5ED7ED7ED27F3FF3FFBDBBDBBDABDABDABDAFDAFDA7FE7FE7F),
.INIT_0B(256'h9939939A2BDABDAB4AB4AB4A36E36E3673273273B57B57B5BF6BF6BFF9FF9FF9),
.INIT_0C(256'hFFFBFDBB0FFDCEB6FFF7FBBF3EBF6DDAC9CC9CC95ED5ED5E55A55A55B71B71B7),
.INIT_0D(256'h5EDD7FEFC3FFF3AFFBA7DFBDF7EBEF0FD8EED1BDEEEBEFCFEF56FFF8677BABDF),
.INIT_0E(256'hCDED77FBDFDB5EFFBFB767FB1FFE9A3E9BEFEE325EFFF75AAF6729D2FF26BDF9),
.INIT_0F(256'hEF7B6F7ABEF79DEFDFEFEB9A76FF9FDEAEFCE73DFD7F6DE5CE5DEFC4B775EFDF),
.INIT_10(256'h6BD9937A7DEAE96FF7D7FFE7B7F7FBBFF9FFFA105701B5FF5FBEAEEE9FD7FFF9),
.INIT_11(256'h7EE9FF1AEE2F765CCD650E000A82DF95F7E4D93D76EBF5F7F9DE92F6C9F9DDD6),
.INIT_12(256'h3E6F4CC017003DFFBF5776F5CEBFCF3DB7FF7BEBFF57FF7FD57FEFB23B5577F9),
.INIT_13(256'hD5EFFBBCFB656AF791F0F65EFF9BEFB3FEFB7BFA7DD28B1F29FFFFFC5FF4FBDF),
.INIT_14(256'h9B7DB3FFDEDFFF76F767F77016F29BCF79FFFFFFF3DAB1B7F7DB9A0052240FFA),
.INIT_15(256'h4FBEFC322EC735EAE2F7FFFFFF736D5DBFB02101170121FF0AE5BBCF7F7D624F),
.INIT_16(256'hFAF7FFFFFDA5F6FAF464066808000DFA7BDA6DF6FDDA9BFBFEDA6D4FBBFFDBDF),
.INIT_17(256'h89F0C4B04400013FFFFFF7FFB7B4FFFEF7593FFEF77FF6FFBEF7FEA877FFCFEF),
.INIT_18(256'hFFFA9FEDEF6FFFFFBDF5427D9EF7FBFBFB2DFFFA1FFF67FCEDEDFFFFFE5A7EA5),
.INIT_19(256'hFF76FCFFF7FB6FFFFFFFFFFA7BFFDFFFFCDFFF7D7E283F654D100180220C41EF),
.INIT_1A(256'h3F3FFFFA5FFFEEFFEF6F276AFFAB668E9AABD00084D03AFEFFFFFFFDBDFFFFFF),
.INIT_1B(256'hFB5AFE7D7F7FA156311C5D80020447DFFFFFFDB1F6BFFFFFFFEEF7FFCDFFFFFB),
.INIT_1C(256'h846A2A2804D119FFFFFEF2CB927FFFFFFFF80FFFF93BFFFDBFF7FFFA77FFF7B7),
.INIT_1D(256'hFFFFDDB6FFFFFFFFFFFFFFFEFFFDFFFFCFFFFFF87FFFFDC9FA9FFF1E3D28243E),
.INIT_1E(256'hFFFF7FFFFF7DFFDFFFFFFFF87F77FFD7FDB786DFEC09B425450B4C9659C2CAF5),
.INIT_1F(256'hFFFDFFFA774FFEA8D95EEEBFA3D7589E13D41B09040089FFFFFFF5CA7FA7FFFF),
.INIT_20(256'h3E745C4BF9A82558CC8220A45AC996FAFFFFDFBFFFDFFFFFF7FFFFDAFFFDEFFF),
.INIT_21(256'h92D9CD030022606FFFFFFE5EFFFFFFFBBFFEF7FFFFBF7ABFFFF7FEFA7BE5FF65),
.INIT_22(256'hFFFFFFF3ADFFFFFFADF7EF7BB97BFDFFFFFDFB3A3FAF7957F91B83B974129084),
.INIT_23(256'h73FFAF7FBBBF7FEFFFFDFFEA6EBBFB88BD9B55BB8057098A08973A164984A27A),
.INIT_24(256'hFFFDCAB87E9CEC336CEC6A5FD988F554874094E15E43021F7EFFFB79DFFDFFFE),
.INIT_25(256'hA9B2A3B4AE278AA52017498E395D10EF8FBB66FF55DF9FB7AFBAF3B94F446FFF),
.INIT_26(256'hCAB975617A0243DABAF3FB7BAFBD7F5E7FB7FFABA1BC9DEFFF7EBFF277739546),
.INIT_27(256'h292F6AD65D67EBF7F9D5F6F60F766F7BFFAF95C85BDCEAABBFCD49154094AC98),
.INIT_28(256'hDF7B954E5FAF763FFEF8AEF246B6D7B4B6E4BC3306A8E17C8122ED60461940C0),
.INIT_29(256'hFFDF6F4A4F6B1BD749B2EB45498401C17EC30AFD28DF8D45117FFEFF49E48ADF),
.INIT_2A(256'h31212A8A3053D4502B326A934138D26AAAAD2E59F75B7DF3FDBBDFA8F9FBB279),
.INIT_2B(256'h8889B05C2C2600D51C337D792DE59ABD67BDEE9A2E7F1F974FDA93D27DBFEE3F),
.INIT_2C(256'hD31FB8F6DAB7637ED27271EFD9A7A4CAFFBFD17A2AF3B1894D14156F8A8D4A2E),
.INIT_2D(256'h4E3C303D7FFFBDDF43431E724EDF5FDC51AB507FAF12A9184D2D2CC922A782EF),
.INIT_2E(256'hEDE97FD86FFBF76BAF883385002476EF7513C78DDCE151F095FEBFFB5A8BEF7D),
.INIT_2F(256'hFB77FC76A2854A50054191F62F980A3FBF3FFFFCEFDE851277EEC7FEFDDFBFFD),
.INIT_30(256'hB0979A4B785F056FB36E35AF7CC5EF7E8B2237EFFFFFAFDF33FFFDDA5FCF7BBD),
.INIT_31(256'hABBD6BBDBDBCBE86F53CFFEEFFFFF7FBFFEBDFCA7DEEF7DFBDBF7FFC6619219E),
.INIT_32(256'hA9DBED3FFDFF7FD9AFFFA44A5DBFD6F3DDFF7D6C8535229B4B43F477DF6763F5),
.INIT_33(256'h7AF757E27B4AF9AFEB7BFAAF2428B05E23AE6D3D7089154F73DABFD7F6EF5DEE),
.INIT_34(256'h7CEF6EB4CF064D98CD972FAABF679AAF75F349BDB934A6BE7A7EDBF76F3CF7FA),
.INIT_35(256'h2B17B8FFF211B6BA4EDCBEF7BEF9DF3696F7A9EDDF7FFF6FCFBF6B6869FB47E5),
.INIT_36(256'h360FED6B57A7BDD9AFDD1DFB6FFF6DE9AAFDDFB27DE5F63EA9BF9B5FEA11BC07),
.INIT_37(256'hD6F9FFFEB7ECBAF8EAFEFEF23DD4D59EF947DD4DEC7AD43E63557DFE1DBB06FF),
.INIT_38(256'h9B676B6A16272C0B4ABB627278DFC5BF8C8397BDF94D2D35C6BDD3BDBD5B935E),
.INIT_39(256'h16AEE3B9D5F3C1AA0B3E7BEF56C787CFD75EADF9D9FEBFFDBF642593EBFE5E7F),
.INIT_3A(256'h3715DE5DC1A54CDFEEBB5FCFEFF1FD97C9DF9BED1B7D6DD576DD2EFA6E3B9DB5),
.INIT_3B(256'hDBE7E8BFFFFF7B7E7B66D459FDDAFF7A5FB6F7120A9AD397DE64A9ADA75A7DD1),
.INIT_3C(256'h7A5D975F7FFA3D76397CAEB81CAF0D9E86AFCAF0F7B60E755CB53ABF5DF64D75),
.INIT_3D(256'hEFAB5E224571503070E45715B8CDD9FE7B176F6F6929235F67F7EF6FCFE9FFAE),
.INIT_3E(256'h5416C1CBF73B1D37CFEF3DDFE7A349DA7AEDD5DA6DD6CF9511A7CBCDFB67DFCF),
.INIT_3F(256'hF7FF6FF6BF4F827F3BEFFA61BBDFBBCBEB1FADBB4EF2FFF5727ED4C86C1CB7F6),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR(addra),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:1],\douta[2] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(\addra[14] ),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3
(\douta[3] ,
clka,
\addra[14] ,
addra,
dina,
wea);
output [0:0]\douta[3] ;
input clka;
input \addra[14] ;
input [13:0]addra;
input [0:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire \addra[14] ;
wire clka;
wire [0:0]dina;
wire [0:0]\douta[3] ;
wire [0:0]wea;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hFFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_01(256'h021002232042042040440440444444444404404484084084FFFFFFFFFFFFFFFF),
.INIT_02(256'hB7BB7BB7BB7BB7BBFBFFBFFB6FF6FF6F01101101021021020220220222221101),
.INIT_03(256'hC5CC5CC55E15E15EFFEFFEFFFDBFDBFDBDDBDDBDDBDDFEFFFDBFFFD4BFB7FB7F),
.INIT_04(256'h73173173857857856A56A56AC6AD31738578E627B0AF0AF0AD4AD4AD58D58D58),
.INIT_05(256'hFDAFDAFD2DD2DD2DD0DD0DD49F4DF4DF5FB5FB5FA5BA5BA5BA1BA1BA9BE9BE9B),
.INIT_06(256'h4DB4DB47A6DA6DA6DA2DA2DABFEBFEBF69B69B69B4DB4DB486E86E86FA6FA6FA),
.INIT_07(256'h36D36D3651651651F75F75F74D34D34D6DA6DA6D36D36D36D16D16D1FF5FF5FF),
.INIT_08(256'h3AA3AA3AB1EB1EB1D7DD7DD74D34D34DB69B69B68B28B28BBAFBAFBB69A69A69),
.INIT_09(256'hA8EA8EA87AC7AC7A55E55E5575575575D51D51D10F58F58FCABCABCAAEAAEAAE),
.INIT_0A(256'h96B96B96A92A92A9BA9BA9B909E09E0972D72D725525525537537537C13C13C1),
.INIT_0B(256'h67E67E61767F67F6FD6FD6FDEFDEFDEFCCFCCFCCFECFECFED4DD4DD44F04F04F),
.INIT_0C(256'h21759F6DF0D65D5928DA0D41CF51F22F3F33F33FB3FB3FB3EB7EB7EB7EF7EF7E),
.INIT_0D(256'hF326D2B8BC240D704E58E86A8D5F11F937D52F4BD71D54BC74BD654B2E957FED),
.INIT_0E(256'h73BEAB9532B4EFA5E56AFFACA8E575E375DCBBF979FEC8B77E9EFE7BECFBF3A6),
.INIT_0F(256'h34A5FDAFD54AFBB964D4B5612FFCF1B17BEBFFD66BCADF9AB3A315FFFFCE1125),
.INIT_10(256'hBF3E7EB11A1FBFB75DBFFFFBDA2934794EDAEDFFFFFF5ED0A6FBD5D3657D4A16),
.INIT_11(256'hCB7FFFFF35FAABE3B3BAF3FFFFFF602A4ADF7796DBD66FAE973B6F9D3FAE6A2F),
.INIT_12(256'hF595FF7FFFFFD3C5FDBB996B3554BCCB6E25DC5662FFFFE97AA350D955BFDBCE),
.INIT_13(256'h2A3966D7BFDFF5AEFECF2DF5D4FFFFDCA5DD9D6146FFFCF77E9FFFFFEA8F8DAD),
.INIT_14(256'hFF975EC4B5FFFFFBAAB91BBB7FFFFFF5DFFFFFFFFDBDDE6E48BFFFFFFFFFF22F),
.INIT_15(256'hF8DFFFF97FFFFFFF1FFFFFFFFFDEBFFBC56FFFFFFFFFFED0FFFF6578CAD7FFFF),
.INIT_16(256'hDFFFFFFFFFDF4DA53B9FFFFFFFFFFF05FFF5DE9FB36FFFFFFFFFFAF84FFFFFFC),
.INIT_17(256'hFFEFFFFFFFFFFECAFFEC99215EDFFFFFFFFFD625AFFFFFF2652FFFFB7FFFFFFF),
.INIT_18(256'hFFFF6E7AB9FFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFF3FFFFFFFFFFDABDF),
.INIT_19(256'hFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFEDDBF3FFFFFFFFFFFF1A),
.INIT_1A(256'hFFFFFFF97FFFFFFFFFFFFFFFFFFFDBFFFF7FBFFFFFFFEDC1FFFE44CACBFFFFFF),
.INIT_1B(256'hFFFFFFFFFFFFFFF9FFF3E7FFFFFFFA30FFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFE),
.INIT_1C(256'hFFFFFDFFFFFFF74AFFFFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFF),
.INIT_1D(256'hFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFEF),
.INIT_1E(256'hFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FCA),
.INIT_1F(256'hFFFFFFF97FFFFFFFFFFFFBFFFFFFEFEFEEFFEEFFFFFFFF2AFFFFFFFFFFFFFFFF),
.INIT_20(256'hFFFFFFFFFFFFFFF7FB7FFFFFFFFF7F85FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_21(256'h7FFE77FFFFFFFFBAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFF),
.INIT_22(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFF),
.INIT_23(256'hFFFFFFFFFD7BFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFFFFFFC7FFF7FFFFF5),
.INIT_24(256'hFFFFFFFB7FFFFFFFFFFFFFFFFFFFDFFFFDFF7B7EFFFFFFEAFFFFFFFFFFFFFFFF),
.INIT_25(256'hFFFFFFFFFFFF7FFFFFFFFF79E7FEFFB0FFFFFFFFFFFFFFFFFFFFFFFFFAFFFFFF),
.INIT_26(256'hBFFFAEDFDFFFFF35FFFFFFFFFFFFFFFFFFFFFFFFFEDBFFFFFFFFFFF97FFFFFFF),
.INIT_27(256'hFFFFFFFFFFFFFFFFFFFFFFFFFDEFFFFFFFFFFFFB7FFFFFFFFFFFFFEFFFFFFBF7),
.INIT_28(256'hFFFFFFFFFAFAFFFFFFFFFFF97FFFFB7FFFFFFFFFFFFFFFFFFFFF7F9FBFEFFF3F),
.INIT_29(256'hFFFFFDF97FFFFFEFFFFFFDFFFFFFFFFFFFFDF5AAFFFAFFFFFFFFFFFFFFFFFFFF),
.INIT_2A(256'hFFFFDFFDFFFF7FFFFFFFFF6DFFCFBF95FFFFFFFEFFFFFFFFFFFFFFFF8744DFFF),
.INIT_2B(256'hFFFF5FF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9ABFFFFFFFFFFF97FFFFFF6),
.INIT_2C(256'hFFFFFFFFFFFBFFFFFFFFFFFFB758FFFFFFFF7FF97FFFFFFFFFFFFED6FFFFFFFF),
.INIT_2D(256'hFFFFFFC280000000FDFDF7893120A027AEFFFFD2FFFFFFFFFFFBFB3EDF7E7F9A),
.INIT_2E(256'h121680231000001050F7CEFFFFFFFFFFFAFEFDF36FDFFFAFFFFFFFFFFFFCFED7),
.INIT_2F(256'h0008039BFFFFFFEFFFFE6E7DD16FFFD0FFFFFFFFFFF3FEFFFFFFF80000004000),
.INIT_30(256'hFF7DF7B6BFF7FBFAFFFFFFF7FFFF39F5FFFFC800000000000000000100000000),
.INIT_31(256'hFFFFFEDAFFFB7FFD7FFF00100000000000000021000000000000002FFFFFFFFB),
.INIT_32(256'h7FF40000000000000000000100000000000000037FFFFFFEFFFD9BC9AEFDDC7A),
.INIT_33(256'h8000000100000000000000001FFFFFEFFCFBD6EAAFF6FFBAFFFFF67CBF5BAB57),
.INIT_34(256'h0000000013FFFFE7BB69DAD5DABFEDF0FFFCFF6B47FFFFDBEFC0000000010000),
.INIT_35(256'hF7FED72E2DFE5F4FFFEFE5BEEF16ABFFFD800400008000000000000300000010),
.INIT_36(256'hFFF11BDFF8FF56E7720000000000000000000001000000000000000001FFF3FE),
.INIT_37(256'h20000000000100000000000100000000000000000007FBD5FEFEE32FE655FDD5),
.INIT_38(256'h00000001400002200000000002007FFAFBFD7CD25FF6FFCAFF773F7373EEEEE1),
.INIT_39(256'h8000080000083E55F7E38431A9397BFA39A7FA8EAE9171100000000000000000),
.INIT_3A(256'hFCEFB3EABF7EFF20D77DA030100E026000000000000000000000000100800000),
.INIT_3B(256'h34DC10000000000000000000000000000000000100000000000000000000027F),
.INIT_3C(256'h00002000000000000000000300000000000000000000000BEB6FD5D0BB5DFFCA),
.INIT_3D(256'h0000000100000000000000000000000385E99299B6DEFEAA9D68000000000040),
.INIT_3E(256'h00000000000000007A34D266997EBEB5AF100000000000000000000000000000),
.INIT_3F(256'h0891922970B17FC5D40000000000000000000000000000000000000300000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR(addra),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:1],\douta[3] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(\addra[14] ),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4
(\douta[11] ,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]\douta[11] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]\douta[11] ;
wire [0:0]ena_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h09880909880909008888000B09880909880909008888000B0988090988090900),
.INIT_01(256'h880988008809000B88880988880988008809000B88880988880988008809000B),
.INIT_02(256'h8809880B88090988090988098809880B88090988090988098809880B88090988),
.INIT_03(256'h8809888809888809000988008809888809888809000988008809888809888809),
.INIT_04(256'h09880909008888000B09880909880909008888000B0988090988090900888800),
.INIT_05(256'h09008888000B098809098809090088000B88880988880988008809000B880000),
.INIT_06(256'h0B88090988090988098809880B8809880988880988008809000B888809888809),
.INIT_07(256'h8809888809000988008809888809888809000988008809888809888809000988),
.INIT_08(256'h09008888000B09880909880909008888000B09880909880909008888000B0988),
.INIT_09(256'h000B88880988880988008809000B88880988880988008809000B888809888809),
.INIT_0A(256'h8855777755887777077777778855777755887777077777778855777755887777),
.INIT_0B(256'h5588557707887777555577075588557707887777555577075588557707887777),
.INIT_0C(256'h0788777755887707778855770788777755887707778855770788777755887707),
.INIT_0D(256'h5588550777555577778877775588550777555577778877775588550777555577),
.INIT_0E(256'h0055887777077777778855777755887777077777778855777755887777077777),
.INIT_0F(256'h777707777777885577775588777707777755557707558855770788777700FFFF),
.INIT_10(256'h7755887707778855770788777755885577075588557707887777555577075588),
.INIT_11(256'h0777555577778877775588550777555577778877775588550777555577778877),
.INIT_12(256'h7777077777778855777755887777077777778855777755887777077777778855),
.INIT_13(256'h7777555577075588557707887777555577075588557707887777555577075588),
.INIT_14(256'h770B8877000988098809000D770B8877000988098809000D770B887700098809),
.INIT_15(256'h000909098877000D090B8888000909098877000D090B8888000909098877000D),
.INIT_16(256'h8877090D09778888770909888877090D09778888770909888877090D09778888),
.INIT_17(256'h09770B88770009880977090009770B88770009880977090009770B8877000988),
.INIT_18(256'hFF000988098809000D770B8877000988098809000D770B887700098809880900),
.INIT_19(256'h88098809000D770B88770009880988000D090B88880009090988770010FF7070),
.INIT_1A(256'h0D09778888770909888877090D09770B8888000909098877000D090B88880009),
.INIT_1B(256'h88770009880977090009770B88770009880977090009770B8877000988097709),
.INIT_1C(256'h88098809000D770B8877000988098809000D770B8877000988098809000D770B),
.INIT_1D(256'h000D090B8888000909098877000D090B8888000909098877000D090B88880009),
.INIT_1E(256'h5588440009008855077707005588440009008855077707005588440009008855),
.INIT_1F(256'h0900775507000700888844070900775507000700888844070900775507000700),
.INIT_20(256'h0700770088554407000077880700770088554407000077880700770088554407),
.INIT_21(256'h8855880700097788550077078855880700097788550077078855880700097788),
.INIT_22(256'hFF00008855077707005588440009008855077707005588440009008855077707),
.INIT_23(256'h8855077707005588440009008855070700888844070900775507000700FFFFFF),
.INIT_24(256'h0088554407000077880700770088558844070900775507000700888844070900),
.INIT_25(256'h0700097788550077078855880700097788550077078855880700097788550077),
.INIT_26(256'h8855077707005588440009008855077707005588440009008855077707005588),
.INIT_27(256'h0700888844070900775507000700888844070900775507000700888844070900),
.INIT_28(256'h097777000B7707BB09880005097777000B7707BB09880005097777000B7707BB),
.INIT_29(256'h0B7709BB09770005777777090B7709BB09770005777777090B7709BB09770005),
.INIT_2A(256'h0977880577097709007709070977880577097709007709070977880577097709),
.INIT_2B(256'h77097709000B0907BB77880077097709000B0907BB77880077097709000B0907),
.INIT_2C(256'hFF007707BB09880005097777000B7707BB09880005097777000B7707BB098800),
.INIT_2D(256'hBB09770005777777090B7709BB09770005777777090B7709BB09770000FF7070),
.INIT_2E(256'h0577097709007709070977880577097709007709070977880577097709007709),
.INIT_2F(256'h09000B0907BB77880077097709000B0907BB77880077097709000B0907BB7788),
.INIT_30(256'h07BB09880005097777000B7707BB09880005097777000B7707BB098800050977),
.INIT_31(256'h0005777777090B7709BB09770005777777090B7709BB09770005777777090B77),
.INIT_32(256'h887700097700077777090B99887700097700077777090B998877000977000777),
.INIT_33(256'h7700997777770B99887700997700997777770B99887700997700997777770B99),
.INIT_34(256'h7777099988880099090099077777099988880099090099077777099988880099),
.INIT_35(256'h88887799097799077777090B88887799097799077777090B8888779909779907),
.INIT_36(256'hFF0000077777090B99887700097700077777090B99887700097700077777090B),
.INIT_37(256'h7777770B99887700997700997777770B99887700997700997777770B00FFFFFF),
.INIT_38(256'h9988880099090099077777099988880099090099077777099988880099090099),
.INIT_39(256'h99097799077777090B88887799097799077777090B8888779909779907777709),
.INIT_3A(256'h077777090B99887700097700077777090B99887700097700077777090B998877),
.INIT_3B(256'h0B99887700997700997777770B99887700997700997777770B99887700997700),
.INIT_3C(256'h770B77778809770977778800770B77778809770977778800770B777788097709),
.INIT_3D(256'h8809880977008800070B77778809880977008800070B77778809880977008800),
.INIT_3E(256'h7700770007777777770988777700770007777777770988777700770007777777),
.INIT_3F(256'h07770B77778888770900778807770B77778888770900778807770B7777888877),
.INIT_40(256'h008809770977778800770B77778809770977778800770B777788097709777788),
.INIT_41(256'h0977008800070B77778809880977008800070B7777880988097700880000FFFF),
.INIT_42(256'h0007777777770988777700770007777777770988777700770007777777770988),
.INIT_43(256'h77778888770900778807770B77778888770900778807770B7777888877090077),
.INIT_44(256'h770977778800770B77778809770977778800770B77778809770977778800770B),
.INIT_45(256'h8800070B77778809880977008800070B77778809880977008800070B77778809),
.INIT_46(256'h0077000B777777880D880B0B0077000B777777880D880B0B0077000B77777788),
.INIT_47(256'h777709880D770B0B99770077777709880D770B0B99770077777709880D770B0B),
.INIT_48(256'h0D77880B990000770B7709770D77880B990000770B7709770D77880B99000077),
.INIT_49(256'h990077770B7709778877880B990077770B7709778877880B990077770B770977),
.INIT_4A(256'h00777777880D880B0B0077000B777777880D880B0B0077000B777777880D880B),
.INIT_4B(256'h880D770B0B99770077777709880D770B0B99770077777709880D770B0B0077F8),
.INIT_4C(256'h0B990000770B7709770D77880B990000770B7709770D77880B990000770B7709),
.INIT_4D(256'h770B7709778877880B990077770B7709778877880B990077770B770977887788),
.INIT_4E(256'h77880D880B0B0077000B777777880D880B0B0077000B777777880D880B0B0077),
.INIT_4F(256'h0B0B99770077777709880D770B0B99770077777709880D770B0B997700777777),
.INIT_50(256'h99777777777755885577880B99777777777755885577880B9977777777775588),
.INIT_51(256'h77770B885599880B0777777777770B885599880B0777777777770B885599880B),
.INIT_52(256'h5599770B0799777777770B555599770B0799777777770B555599770B07997777),
.INIT_53(256'h0799777777770B55889977880799777777770B55889977880799777777770B55),
.INIT_54(256'h10777755885577880B99777777777755885577880B9977777777775588557788),
.INIT_55(256'h885599880B0777777777770B885599880B0777777777770B885599880B00BB99),
.INIT_56(256'h0B0799777777770B555599770B0799777777770B555599770B0799777777770B),
.INIT_57(256'h7777770B55889977880799777777770B55889977880799777777770B55889977),
.INIT_58(256'h55885577880B99777777777755885577880B99777777777755885577880B9977),
.INIT_59(256'h880B0777777777770B885599880B0777777777770B885599880B077777777777),
.INIT_5A(256'h880988880B88097709007777880988880B88097709007777880988880B880977),
.INIT_5B(256'h0B887777090977770B0988090B887777090977770B0988090B88777709097777),
.INIT_5C(256'h090900770B88880988887709090900770B88880988887709090900770B888809),
.INIT_5D(256'h0B880909880B7709770900770B880909880B7709770900770B880909880B7709),
.INIT_5E(256'h000B88097709007777880988880B88097709007777880988880B880977090077),
.INIT_5F(256'h77090977770B0988090B887777090977770B0988090B8877770909777700D7F8),
.INIT_60(256'h770B88880988887709090900770B88880988887709090900770B888809888877),
.INIT_61(256'h09880B7709770900770B880909880B7709770900770B880909880B7709770900),
.INIT_62(256'h097709007777880988880B88097709007777880988880B880977090077778809),
.INIT_63(256'h77770B0988090B887777090977770B0988090B887777090977770B0988090B88),
.INIT_64(256'h0B99777788008809550977770777550009887709777709775577099900098809),
.INIT_65(256'h7755885588D77777000055880977007777770755880905885509775555047788),
.INIT_66(256'h0B99090B777777998877770055880B7777880B990000770B770B770D09775509),
.INIT_67(256'h077788777707778877880088550B77880077778877000988770B887788997788),
.INIT_68(256'h0077880B990077770B7705887709778855058809000988880088907788885588),
.INIT_69(256'h5588000B7788077709770900990007095588777755007788078877770001F899),
.INIT_6A(256'h8800070B7777880977777709880955887788550B7700777700770909DD007777),
.INIT_6B(256'h77770988770909990000770B7700550977079955BB0B99007709550788770900),
.INIT_6C(256'h887777770B8877887788550B880988880777770B777777000999090900777788),
.INIT_6D(256'h77887777880B8877550977BB0B77775588000B77880777077709887788770977),
.INIT_6E(256'h8877999999BB777777770077558870075507775509095588070B770907770577),
.INIT_6F(256'h098809005507770977770B7777770B770B777700557788558877880988777777),
.INIT_70(256'h88778877008877070B0988090B448809000B8800777709880055885577090977),
.INIT_71(256'h770B000B008800770B77550909880007990B88098F0B997777885500990B8809),
.INIT_72(256'h00000B880077770977008888888877770088057799557755097709005509880B),
.INIT_73(256'h770999887709778877007709008877770077880B8877880B990B00880900D799),
.INIT_74(256'h0B0B997700777755888800775588770977090988779977099909887707770009),
.INIT_75(256'h0009887707887777779900550B778855098877090988008888770055880B7777),
.INIT_76(256'h77070B887707880788770988550B770799000B55770088098855887777880788),
.INIT_77(256'h07880B0B77550900887788098800097709778877097788880077070055097788),
.INIT_78(256'hDDBBDDDDBBDDDDDDBB7707550988990507775509777777885577090577887788),
.INIT_79(256'h885509097707000999770B777777098855777709550077008888BBBBBBDDBBBB),
.INIT_7A(256'h77888877880709000B880577887788770900770B88880588887707098F770955),
.INIT_7B(256'h550B880988778809008888778877996B88888FBBBB8F8888990B778877888F47),
.INIT_7C(256'h100700770B888805888888008888557700090977777777888855098804557709),
.INIT_7D(256'h77880B7777886B770000770B778895778877000977997788070B0B057700D799),
.INIT_7E(256'h880B078855887799778807770955000788050B00885509888855880988777700),
.INIT_7F(256'h77078809558877550B7777777709070009880009887777880977887700097799),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\douta[11] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5
(\douta[11] ,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]\douta[11] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]\douta[11] ;
wire [0:0]ena_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h770B09777788778855880B880B887788078855770077007777077788550B0B07),
.INIT_01(256'h0B7709047788887788090088777700BB000B770B7700770B880007097755000B),
.INIT_02(256'hBBDDBBDDBBDDDDDDBB9999999999998877097777098809558800550077077705),
.INIT_03(256'h5588775588990977778877770055880700000077880977099999BBDDBBBBBBBB),
.INIT_04(256'h880977880B778877777788550B77077777078888770977557709008800077700),
.INIT_05(256'h55887788098877880D7705880B887DDDDDFFFFDDFFDDDD888888880B99058888),
.INIT_06(256'h007707888877097755777799000B880B88778809000B0B880B77880955880088),
.INIT_07(256'h0B558809000B880877770988770B0B07550B9977090900770B778888550077F8),
.INIT_08(256'h77770B0988050B7700778877889999777788995588770977777709770B008809),
.INIT_09(256'h8877558877090B88777709888877889955090B770B09880B8807558899777709),
.INIT_0A(256'h098877000B778809888877055509887777880077098809880077887709888877),
.INIT_0B(256'h77007777097788558888770B098809097788097777990B88090B777777000977),
.INIT_0C(256'hBBBBBBBBDDBBDDBBDDBBBBBBBBBB889977880907550777550735997709770977),
.INIT_0D(256'h00770B0B7707990009078809097709078F99990B777777996B8FBBBBBBBBBBBB),
.INIT_0E(256'h7777880B55887709090B880B885588770B7788550955880B0977990707770B99),
.INIT_0F(256'h0B8807778877880B77888F8F88BBBBDDFFFFFFFFFFFFFFFFBBBB6B8877990D09),
.INIT_10(256'h000B7788550977880B070B0099889988998877889977888888005555880B0977),
.INIT_11(256'h770009779977090499778877777788887788550977770777880955880B00D799),
.INIT_12(256'h7788887707778877990099889988778888888888888888886B88887788777788),
.INIT_13(256'h550B885509880077557788077700777709887777880977775588770B55097777),
.INIT_14(256'h777709997788770977097788778877770055990988887777990B555588770900),
.INIT_15(256'h770988888888778809550988097788000977778809775509778800770B779900),
.INIT_16(256'hBBBBBBDDBBDDDDDDBBBBBBBBBBBBBBBB99997788777709007788550777007700),
.INIT_17(256'h99097788778805099977770977007788998899BB888899BB778899BB99BBBBBB),
.INIT_18(256'h0B88055588778855887707770588090B00770477880B778888770B7788885500),
.INIT_19(256'h330B880B000B0B778877778888DDDDFFFFFFFFFFFFFFFFFFFFDDDDDDDD889999),
.INIT_1A(256'h1000770477880B5588889988998F0D0B886B990B880B07B609990B8855888800),
.INIT_1B(256'h887788770700770B88880788880977880B777788000B7788448888077700BB99),
.INIT_1C(256'h888833007788770788BB8F8888BB8F7D8F888FBBDD8F8F88886B7788090B0777),
.INIT_1D(256'h00990900990909770088557709990B09777788770B8807090B880B887788770B),
.INIT_1E(256'h8807880D770988009988550B0B009988098800995509770B0077007709008877),
.INIT_1F(256'h77770B04097709775577770B880755887777007755098855880B6B0077000B99),
.INIT_20(256'hBBDDBBDDBBBBDDBBBBBB88BBBBDDBBBBBB999999775588777777007777097709),
.INIT_21(256'h778877770977075588770B88779988888899BBDD88BB88BBBBBBBB99BBBBBBBB),
.INIT_22(256'hDD88DD888F9955880077098800097709880B7700090B99775509007799887777),
.INIT_23(256'h09887700880B0B0077DD88DD888F88DDFFFFFFFFFFFFFFDDDDFFFFFFFFFFFF88),
.INIT_24(256'h000B0B88998888BB88888F888F6B880B880B6B8888BB8F888F88999977887788),
.INIT_25(256'h887788550B7788550955880B0955998877777777097788880B7788000901F899),
.INIT_26(256'h88770B007700770B888FBB8FDDFFFFFFFFDDFFFFDDFFDDDDBB88887D0955880B),
.INIT_27(256'h0F996B7D889988770B7755887777990077057788090B00550088777777777777),
.INIT_28(256'h0B885577887777770B88778877886B009988889999BB88BBBB8FBBBB888F8877),
.INIT_29(256'h8FBBBB99886B8F99888888090B880B88550988777709778877880B9988557777),
.INIT_2A(256'hBB99BBDDBBDDDD88BBBBBBBBBBBBBB8899998899999909778888078805770755),
.INIT_2B(256'h8809557777887788770988779999BBBBBBBB88BBBB99BB8FBBBBBBBB99BBBB88),
.INIT_2C(256'hDDDDDDDDDD88880D8F8877880999007709558899888809000977998800070988),
.INIT_2D(256'h777755BBBB9988BB8FDDDDDDBB88DDFFFFFFDDDDFFFFFFDDFFDDFFFFFFFFDDDD),
.INIT_2E(256'h00BB88998F77888F88DDBBBBBB88DD88999908888F88BBDDDDDDDDBB8899880B),
.INIT_2F(256'h0900090B00770477880B44888888889988DD8F888F8899BB8F990F888F00D799),
.INIT_30(256'h770B7777888F8F888F8FFFDD8FFFFFFFDDFFBBDDDDBBFFDDDD888F7788880744),
.INIT_31(256'h88888888880888BB88880B88009900990988880B007709770988090B00770777),
.INIT_32(256'h885588885507098855880B778899888F880B99888FBBDDDDFFFFFFDD8FBB8F7D),
.INIT_33(256'hBBDDDDDDDDBB8888888899887709550B0B88550B88880955007777880988880B),
.INIT_34(256'hBBBBBBBBDDBBBBBBBBBBBBBBBBBBBBBBBB996B99888899885555777777097709),
.INIT_35(256'h777788886B7D0B09997777999988BB9999BBBBBB997D8899BBDDDDBBDDBBBBBB),
.INIT_36(256'hDDDDDDDDFFDD9988880B77999977090077885577098877998877887777997799),
.INIT_37(256'h888877887DBBDDBBDDDDDDDDBBDDDDDDFFFFFFFFFFFFDDDDDDDDFFFFFFDDFFDD),
.INIT_38(256'h108F888FBB8FDDDDFFDDFFFFFFFFFFDD880D6B9988DDDDFFFFFFDDBB8F888F88),
.INIT_39(256'h779977777788770B777788070B7D8F8FDD8FFFDDDDFF8FBB88BB888F880099F8),
.INIT_3A(256'h007700770B8888DDBBFFFFDDDDFFDDFFFF8FFFFFBBFFDDBB88DD888855778877),
.INIT_3B(256'h7D888F888F7D888899889988880B99889999778855008877777788777788770B),
.INIT_3C(256'h7709770009888877000977886B888F99887D8F7D88FFFFFFFFFFFFFFFFFFDDBB),
.INIT_3D(256'hFFFFFFFFFFFFFFFFDDDD885500887777887777880B0777880777885577075588),
.INIT_3E(256'hBB88BBBBBBDDBBBBBBBBBB99BBBB9999BBBB9999999999770909550588558855),
.INIT_3F(256'h889999998899998888887D7799BB99998888BB998F88BBBBDDBBDDDDBBBBBBBB),
.INIT_40(256'hDDDDFFFFDDFFDDBB9988BB88889977990B778877007700098809776B8F880B88),
.INIT_41(256'h777788BB88FFBBDDDD8FDDBBDDDDBBFFDDDDDDDDDDDDDDDDDDDDDDDDDDFFDD8F),
.INIT_42(256'h1099BBDDDDDDDDFFDDFFFFFFFFFFFFFFBB88886BBBDDDDDDDDFFDDFFDDDDBBBB),
.INIT_43(256'h888F8888886B88888F9988998888BBFFFFFFFFFFFFFFFFFFFFFFFF88DD00D799),
.INIT_44(256'h888FBB888F8F8FBB8FDDFFFFBBFFFF8FFFFFDD8FDDBBFFDDFF88DD88888F7D88),
.INIT_45(256'hDDBBDD8F88888F8888880F886B8899880B880B99998F886B99880F887D778F88),
.INIT_46(256'h88778899887755888F88886B8888888F7D8888DDDDFFFFFFFFFFFFFFFFFFFFFF),
.INIT_47(256'hFFFFFFFFFFFFFFFFFFDDDD8F888F8809550B0B77888800777788000900770B77),
.INIT_48(256'hBBBBDD99BBBB888F99BB99BB888899996B88998F99999988B677070988778877),
.INIT_49(256'h0B889999997799886B999988BB0999090B9999999999BB8888BBBBBBBBBBBBBB),
.INIT_4A(256'hBBDDDDFFDDDDFFBBBBBBDDBB88BB999999098877888877886B88779999779988),
.INIT_4B(256'hDDDDDD8FDD88BBBB8F88BBDD8FDDDD8FDDDDDD8FDDDDDD88BBDDDDDDDDDDBBDD),
.INIT_4C(256'h00DD8FDDDDBBDDFFDDFFFFFFFFFFFFFFFFDDBB8FDDFFDDDDDDDDDDDDDDFFDDFF),
.INIT_4D(256'h888FDD888F888F8888888888DDDDDDFFFFFFDDFFFFFFDDFFDDFFDDDDDD00D799),
.INIT_4E(256'hDD8F8F8899DDDDDD88DD8FDDDDBBDDDDBBDD8FBBFFDD8FDDDDDDDDDDDD8F888F),
.INIT_4F(256'hFFFFFFFFFFDDFF8FBB887D8F6B888899887D8F7D888FBB8F8F888FDDDDDDDDDD),
.INIT_50(256'h88997777887709887D88887D8FDDDDFFDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFDD885577007777778807778888777700770977),
.INIT_52(256'h88BBBBBBBB88999988778F88998F999999998877880B77098808775577075509),
.INIT_53(256'h8899997D88BB8899776B889988998888887799886B999999BBBBBBBBBBBBBBBB),
.INIT_54(256'hDDDDFFFFFFDDDDDDDDBB88BBDDBB88889988770B9977886B8899999988888899),
.INIT_55(256'hDDDD8FBBDD8FDD88BB8F8FBBDD88DD88BBBBDDBBBBDD88DDBB8FDDBBDDBB88BB),
.INIT_56(256'h10DDBBFFDDFFFFDDFFFFFFFFFFFFFFFFFFFFDDBBDD8FDDBBDD88DDDDDDDDDDDD),
.INIT_57(256'h6BBB88FFDDFFDDDDBB998FDDDDFFFFDDFFFFFF8FFFDDFFDDFFDDFFFFDD00BB99),
.INIT_58(256'hDDDDBBBB888FBB88DD8FDDDD88DD88DD8F88DDDD88DDDDDDDD8FFFFFFFBB0D77),
.INIT_59(256'hFFFFFFFFFFFFFFFFFFDD88BB88DD8FBB8F888888BB88DD8FDDDDDDFFFFFFFFDD),
.INIT_5A(256'h778800880B8888BB778FDDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFF8F887D88887D88889988886B888899998F88),
.INIT_5C(256'hBBBBBBBBBBBB88BBBB9999BB9988BBBB998899998F7788770577098877777777),
.INIT_5D(256'h99998888998F9988BB9999887777999999886B7777888F8888BB99BBBB99BB99),
.INIT_5E(256'hBBDDDDDDDDDDDDDDBB8F8F88887D887D889988999999998899886B8F8F77770B),
.INIT_5F(256'hDDDDDDDD88BB888FBBDD998FDDBB88BB88DDDDDDDDDDDDBBBB88DDFFDDDDBBDD),
.INIT_60(256'h008FFFDDBBDDDDFFDDFFFFFFFFFFFFFFFFFFFFDDBBDDFFDDDDBBDD8FBBDDDDFF),
.INIT_61(256'h88BBDDFFFFFFFFFF8F8888FFBBFFDDFFFFFFFFDDFF8FFFFFFFFFFFDDDD00D7F8),
.INIT_62(256'hDDDD888FDDBBBB8FBBBBDD8F8FBB8F88DDFFDDDD8F8FDDDDDDFFFFFFFF8FBB88),
.INIT_63(256'hFFFFFFFFFFFFFFDDFFDDDD8F8FBBBBBBBBBBBBBB8FDDDDDDFFFFFFFFFFFFFFFF),
.INIT_64(256'h886B998899998FBBBBDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_65(256'hFFDDDDFFFFFFFFFFFFFFFFFFFFFFFFBB888888776B6B886B8888996B888F7700),
.INIT_66(256'hBBBBBB99998899998888998899BB99888F999988779999887788777700770077),
.INIT_67(256'h88996B99BB8899998F887D9988998899BB8F88BB889977998FBB8899889999BB),
.INIT_68(256'hBBBBDDDDDDDDBBDDBBBB888F88998F99998F88BB99888F998F99887788888899),
.INIT_69(256'hFFFFFFDDDDBB88BB88BBBB8888888F888F888F8FDD7DDD88BBBBBBDDDDDD8FBB),
.INIT_6A(256'h00DDDDFFFFDDDDDDDDDDFFFFFFFFFFFFFFFFFFDDDDDDBBDDDDDDBBBBDDBBBBDD),
.INIT_6B(256'h8F88BBBBFFFFFFFFFFFFDD8FFFDDFFFFFFFFFFDDFFDDDDFFFFDDFFDDFF01F899),
.INIT_6C(256'hDDDDDDDD8F888FDD888FDD88DDDDBBFF8FDD8FDDDDDDDDDDDDFFDDFFFFFFFFDD),
.INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8FFF8FFFFFFFFFFFFFFFFFFFFFFFFFBB),
.INIT_6E(256'h7788888F888FDD8FFFFF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6F(256'hDDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFDD88BB7D88886B88886B8888998888BB),
.INIT_70(256'hBB8899888899997D8888BB999999889977889999889988BB888877770B550B55),
.INIT_71(256'h9988BB6BBB888F7D9999BB99889988DDBB88BBBB8888996B8899998899888899),
.INIT_72(256'hDDDDDDBBDD88BBBB99BBBBBB88BB997D88BB888899889999999988998F7D9988),
.INIT_73(256'h8FDDFFDDDDDDBBDD88BBDD8FBB8F888888BB99BBBB7D88BB8F88BBDDDDDDDDDD),
.INIT_74(256'h10DDDDDDFFFFDDDDBBDDDD88BB88DDDDDDDDDDFFDD8888DDDD8FBBDDBB88DDDD),
.INIT_75(256'hFFFF8FFFFFFFFFFFFFFFDDFFFFFFFFDDFFDDFFFFFFFF8FFFDD8FDDFFDD0099F8),
.INIT_76(256'hDDDDDDDDDDDDDD8FBBDDDDDDDDDDBB8FDDFFFFDDDDDD8FFFDDFFBBFFDDFF8FFF),
.INIT_77(256'hFFFFFFFFFFFFFFDDFFFFDDFFFFFFDDFFBBFFDDFFFFFFFFDDFF8FFFDD8FFFDDDD),
.INIT_78(256'hBB88DDFFFFFFFFFFFFBBDDBBBBFFDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_79(256'hDDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFF8FDD888FBB886B8888886BBB88BB88BB),
.INIT_7A(256'h8F99999999889999999999BB999999997D9999997DBB9988D7770D7788778877),
.INIT_7B(256'h99999977998F887788886B889988BBBBBBBB8F778899887799BB999977BBBB8F),
.INIT_7C(256'hDDBBDDBBBBBB888F8F88997799888F88BB888F7788990BBB886BBB778888886B),
.INIT_7D(256'hDDFFBBDDDDBBBB8FBB889988888F88BB888F888F8F77888F88BB8888DDDDDDDD),
.INIT_7E(256'h10DDFFFFBBDD8FDDBB88BBBB8F888FDD88DDDDDDFFDDDDBB88BB8FBB8FBBBBBB),
.INIT_7F(256'h8FDDDD8FDDFFFFFFDDFFFFDDFFDDBBFFFFFFFFDDFFDDDDDDDDDDDDFFFF00D799),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\douta[11] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6
(\douta[11] ,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]\douta[11] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]\douta[11] ;
wire [0:0]ena_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h8FDDDDDD8F88DDDD8F8FDD88888FBB88DDDDDDBBFFFFDDFFFFFFFFDDDDFFFFDD),
.INIT_01(256'hDDFFFFFFBBFFFFDDDDFFFFDDDDFFFFFFFFDDFFDDFFDDFFFFDDFFBBFFDDBBFFBB),
.INIT_02(256'h8FDDFFFFFFFFFFFFDD8FBB8FFFDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFDDDDDDDD),
.INIT_03(256'hDDFFDDFFFFFFDDFFFFFFFFFFFFFFFFFFDDDDBB88888F888F8FBB888F88888888),
.INIT_04(256'h99889988888F88998888999988999988770B997799888F8F8877777777097709),
.INIT_05(256'h7D88996B88779999779999BBBBBB88BBBB99889999999999886B889999889999),
.INIT_06(256'hDDDDDDDD88BBBBDD88BB8FBB8899998FBBBB888F9988BB77BB88998877999999),
.INIT_07(256'hBBBBFFDDDD8FDDBBBBDDDD8FBB88BB8FBB88BB88888899998F88BBBBDDBBFFDD),
.INIT_08(256'h00DDDDDDFFBBDDDDDDDD8FBBBBDDBB8FDDDD8FDD8F8F888FBB8888BBBB88BB8F),
.INIT_09(256'hDDDDDDFFFFDDDDFFFFDD8FDDBBDDDDDDDDFFFFDDFFDDFFBBDD88FFDDDD0077F8),
.INIT_0A(256'hDDDD8888DDDD7DDD88BB88DDDDDD8FDDBB8888DDDDBBDDBB8FBBFFFFFFFFFFDD),
.INIT_0B(256'hDDBBDD88DDDDDDDDDDDDFFFFFFDDDDBBFFDDDDFFBBFF8FDDFFDDFFDDDDFFDD8F),
.INIT_0C(256'h88DDDDDDFFFFDD8F88DD88DD8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFDDDDBB8FDD),
.INIT_0D(256'hDDDDFFDDDDFFDDDDFFFFFFFFFFFFFFFFFF8FDDDDDD8888BBBB8FBB888FDD8FBB),
.INIT_0E(256'hBB999999BB9999BBBB998FBBBBBB8899BB888899BBBB99999977880988778877),
.INIT_0F(256'h77990B8899998F8F88886B887D999977778F999977886B88BB99998F0B997D77),
.INIT_10(256'hBBDDDD88BB8FBBBB99BB9988BB8F88BB88BBBB8899BBBBBB88999999BB888F99),
.INIT_11(256'hDDDDDD888FBBBB8FBBBBBB8888BB888877BBBBBBBB997D8888BB778F88BBBB88),
.INIT_12(256'h00BBDDDDDDDD88DD88BB88BB888F88DDBB88DD88DDBBBB8899889988998F88DD),
.INIT_13(256'hDDDD8FFFDDDDFF8FDDDD88DD8F88BBDDFFFFDDDD88BB888FBBBBDDFFFF00D799),
.INIT_14(256'h8FBB8FDD7DBBBB88BB888F8888BB88888FDDDDDD88FFBBFFDDFFFFFFDDFFFF8F),
.INIT_15(256'h8FBB88BBFF88BBDDFFDDDD8FBBDDFFDDDD8FFFBBFFFFDDFFBBDDDDDDDDBBDDDD),
.INIT_16(256'hDDBB8FBBDD8FBB88DD888FFFFFFF8FFFDDFF8FFFFFFFFFFFFFFFFFFFDDFFDDDD),
.INIT_17(256'hDDDDDDDDFFDDDDDDDDFFFFFFFFFFFFFFDD888FDDDDFFDDFFFFDD8F8FBBBBDD88),
.INIT_18(256'h9988999977BBBB888FBBBBBB9988BB99888F88BBBB997D9999888888770B770B),
.INIT_19(256'hBB990B9988BB996B8899BB7799888F88BB9977774799889999998F779988886B),
.INIT_1A(256'hDDBBBBBBBBBBBBBB8F888F88BB888F88998F8F8F8899997D88998FBB888F8899),
.INIT_1B(256'h88BB8FDDDD88BBDD88BBBB88DDBB888899889988BB88BB88888F887788BB8F88),
.INIT_1C(256'h00DDDDBBDDDD8FBB8FBB888F88BB88DD88DDDD888FBB8888886B996B7799BBBB),
.INIT_1D(256'hDDFFDDFFFFFFFFFFDDDDFFFF88DDBB8FDD888F8888887D88DDDD88BBDD00D7F8),
.INIT_1E(256'h888F88887D9977887799778888778888BB8888DD8F88888FDDDDFFBB8FDDFFFF),
.INIT_1F(256'hBB8F88DDBBBBDD888FDD88DDDDFFDDDDFFBBDDBBDDDDDDFFBBDD8888DDDDDD88),
.INIT_20(256'h888FBB8F888FDD7DDD888F8888FFBBDDDDDDDDDDDD8FDDDD8FFFFFFFDDFF88BB),
.INIT_21(256'hBBDDDDDDDDDDDDBBFFDDDDDD88DDDDDDDD8F888FDDBBDD88BBDDDD888FBBBB8F),
.INIT_22(256'h997D998F8F88DDBBBB88BBBBBBBB888FBB99BBBBBB997799098F997788778877),
.INIT_23(256'h889999BB9988778899886B9999999999778F99886B778F99778888996B999977),
.INIT_24(256'h7D88BB8F88BB8F888899BBBB88BB998F8888778899889988BB88998899889999),
.INIT_25(256'hBBDDDDBB88DDBBBB8F88DDBB888FBB8F9988889988997D999988997D888888DD),
.INIT_26(256'h00DD8FFF888FDDBBDDBBF8888F88BBBB8F8888BB888FBB6B999988886B998F88),
.INIT_27(256'hFFFFFFFFFFFFDDFFDD8FFFFFDD8FBBDD888F99BB8FBB88BB88BBDDDD8F01F899),
.INIT_28(256'hBB886B99777788770B886B9999889999BB8888BB88DDDDDDDD8FDDFFDDFFFFDD),
.INIT_29(256'hDDBBDDBB888F88DDDDBBFF88DDBBDDBBDDDDDDFFBBBBDD8888BBDD8F88BB9988),
.INIT_2A(256'hBB88BB88BB88BB88DD88BB88DD88DD8FDDBBBB888FDDDDDDDDBBDDDDBBDDDDDD),
.INIT_2B(256'hDDBBBBBBDDDDDDDD88BB88DD8FBB88DDBBDDDDBB998F88BB8F88888F88888F88),
.INIT_2C(256'h999977777799BB88BBDDBB88888F8F7799BBBB8FBB99BBBB8877880977777777),
.INIT_2D(256'h996B88BBBB8FBBBB99BB99888F887D8899886B998899598877998F99887777BB),
.INIT_2E(256'h88BB8FBBDD8F88BBBBBB886B997D8888778F99997D6B88998899888F99889988),
.INIT_2F(256'h8FBB88BB8FBBBB8FDDFF8F88BBBB88BB8899888FBB8F888888998877998FBBBB),
.INIT_30(256'h00DDDD88BBDDDD8FBB8F8888BBBB8FDD88BBBB888F8899886B886B9999888899),
.INIT_31(256'hFFFFFFFFFFFF8FFFBBFFFFDDDD8888BB88BB888F7788DD88DD8888DDBB00D799),
.INIT_32(256'h889988990B990977880B478888776B99888F8F888F88BB88DD88DDBBFFDDDDDD),
.INIT_33(256'hBB88DDDDFFDDDDDD88BB8FDDBB88DDDDDDDDFF88DD8F88DDDDBB8FBB888F7D88),
.INIT_34(256'h88BB88BB88DD888F88BB778F888FBB88BB8FDD8FDD888F88BBFFBB8FDDDDDDBB),
.INIT_35(256'h88BB888F88BBDDBB8F8F8888BBBBDD88DD88DD888FBB888FBB888F88888F8888),
.INIT_36(256'h9988778888F88899BB99BB8F999988F8BB88BB9999BB887D77770988770B770B),
.INIT_37(256'h8877999988BB888F8899887D8899997D8F778877998899779988779999998F88),
.INIT_38(256'hBB88BBBBBB99BBBB88BB99888F88BB8F889988998877990B7D9999887799998F),
.INIT_39(256'h88BBDDDD88DDDD88DD888FBB888F99886B888F998899997D8F99997799779988),
.INIT_3A(256'h10FFBBDD8FBB8F88DD88BB888F88BBBBDD8F8FBB8899888F886B880B8899888F),
.INIT_3B(256'hFFDDFFFFFFFFFFDDDDBBFFBB88DD8F888FBBBB88BB888F88DD8FBBBB880099F8),
.INIT_3C(256'h990B990988887788998888776B08880B998888BB88888F88BBDD8FDDDDBBFFFF),
.INIT_3D(256'hFFDDDD8FDDBBBB8FDDDDBB88BB8FBBDD888FDDDDBBDDFFBB888F8888BB887799),
.INIT_3E(256'h8F888F888F88BB88BB8F88998F888888DD8888BB88BB88DD88DDDD88BB8FDDDD),
.INIT_3F(256'h998F8F99888FBB88BBBB88BB888F88DDBB8F8FBB88BB8FBB8F88BBDDBB888FBB),
.INIT_40(256'h99D76BBB6B88888F9999BB778F999988BB88BBBBBB99BB997707999999999999),
.INIT_41(256'h8899BBBBBBBBBB8899BB886B99BB888F77888899888899886B777799990B9999),
.INIT_42(256'h998F99BBBB888F8F8899888F886B9999888888999999998899888888000D6B99),
.INIT_43(256'h88BB8888BB8888998888889999886B998F997D8888888F998F9988886B8F888F),
.INIT_44(256'h0088BBFFBB8888BB88BB88888F887DBB888F8F8899777D8F7799888899889999),
.INIT_45(256'hDDDDDD8FFFFFFFBBFF888F888899BB998FBB889988887D8F8F888F88BB0077F8),
.INIT_46(256'h6B88998888778877880988998877887709887D88BB8F88BBBBBB7DDD888FDDDD),
.INIT_47(256'hDDDDBBDD8FDDDD8FBBDDDD8FDDBB8888DDBBBBDDBBDDBB8FBB88BB8F888F8899),
.INIT_48(256'hBB8FBBBB88BBBB888F88886B9988BB8F88BBBBBB88BB88BBDD8FBBDD88DD88DD),
.INIT_49(256'hBBBB997D99BB9988998F88888F888F888F8888888F8F8FBB88DDDDDD8888888F),
.INIT_4A(256'h995988998899999988886B88777788778FBB99BB88886B889988990B99889988),
.INIT_4B(256'hBB7D77DD88DDDDBB88889999990B778899998F99779977098877887788770B77),
.INIT_4C(256'h9988998F7799998888999999998899998F998F0B998F9988887D8F99BBBBBB88),
.INIT_4D(256'h8F88BBBB88BBBB8F8F997D8899998899778877998F9977089988999999889988),
.INIT_4E(256'h008F8F998888888FBB887D8F8899888899BB99888F99888808888F7709888888),
.INIT_4F(256'hDDDD8FDDDDDD8FDDDDDDBB8F8F8888889988886B88887788998899998F00D799),
.INIT_50(256'h887707777709090077887707770B7777889977776B99888FBB88888F88BBBB8F),
.INIT_51(256'h88DD8888DD88BBDD88BBDD888FBB8FDDDD88BB8F88888F8888BB88BB8899996B),
.INIT_52(256'h888888888F88888FBB88BB88886B88886B888F778F888F88DD888888BBBBDD8F),
.INIT_53(256'h7D8F88BB88BB888F889988BB888899DDBBBBDDBB888888BBBB88BB8888BBBB77),
.INIT_54(256'h0B7799BB99999988999977777D99999988779988999988998F77779977997799),
.INIT_55(256'hBB99DDBBDDBB8888BB99887DBB99888F8F888899889988997799097709997788),
.INIT_56(256'h99998888BB8F99998F889988999988887788BB88BB88996BBB77998899998FBB),
.INIT_57(256'h99998888BB998F8899BB77BB990B998899997799770B88BB88990B99886B778F),
.INIT_58(256'h1088888F888FBB8888BB77887D888F7D887788BB7777888F996B888877888877),
.INIT_59(256'hBB88BBBB8F88DDFF8888BB88888F8FBB8F9999886B6B888888888F889900BB99),
.INIT_5A(256'h990B880B887777990B770077007788880999997D88777D888F998F77BB888F88),
.INIT_5B(256'hBB8FDDBBBB8FDD88DDBBDDDD88DDBB8F888F88BB888888BB8FBBBB887D990899),
.INIT_5C(256'h8F997D99887D8F88888F888FBB886B7D889999888899889988BB8F8F88DDBB88),
.INIT_5D(256'h99BBBB88DD8FBBBBBBBB8F88BB8F888FBBDDDD8FDDDDBB8FBB888F8F88BB8F8F),
.INIT_5E(256'h9999888F0F886B99BB9988BB99888899BB8F6B998F99999988886B886B886B88),
.INIT_5F(256'h88BBBBBBDDBBBB9988999999886B9988779977889999990B998899887788990B),
.INIT_60(256'h886B99998899888F88BB6B997D88BB88BB886B99889988998F9988BB888888BB),
.INIT_61(256'h998899BB777D99888F8F998899886B6B8F0B9988998899776B88770B77888877),
.INIT_62(256'h008F8FBB88BB8FBB88888F88999977777D997D77996B6B8877999999886B0900),
.INIT_63(256'h888F888888DDDD888F8F888F8F88888877888F88999999886B8888777D00D7F8),
.INIT_64(256'h88550988770B09885509770B09777777889988998F7D99BB8888BB998899778F),
.INIT_65(256'hDD88BBDDBBBB8FBBBB7D8888BBBB88BBBB888F88BBBBBB88888F889988888888),
.INIT_66(256'h8888997D8899888F8899887D0B7788776B88888FBB6B887D998888888F8888BB),
.INIT_67(256'h8888BBDDBBBB88DDBBBBBBDD88DD8FDD8FBBDDDD8899BBBB88DD8888BB8888BB),
.INIT_68(256'h990B778F8FF88899779988999988887777999999999988597D77779988778877),
.INIT_69(256'hBB77BBBB8888BB889999889988778F888F8F885988770B9977D7990B880B9977),
.INIT_6A(256'h886B88BB888F8F88BBBBBB88BB998FBB88998FBB8899998899999988889999BB),
.INIT_6B(256'h99770B77990B9977889977BB7D99777799776B889999990B0B88778877778877),
.INIT_6C(256'h0077099977777799777709770555777799770977D70777077777997777888F99),
.INIT_6D(256'h9988998FBB0B778899888F99999977889999998877887D998F7777779900D799),
.INIT_6E(256'h097755777755777777777D55556B777D770B776B77770B775577037777557777),
.INIT_6F(256'hBB88BBBB88888899BBBB8888888FBBBBBBBBDD8FBBBBBBBBBB99777777779977),
.INIT_70(256'hBB888F8F88BB88998899990B8809777788888899778888779977778877888F88),
.INIT_71(256'hDDBBBBDDBB88BBDD8F888FDDDDDDDDBBFFBBDD8FDDDDDDFFDDFFDDDDDDBBDD88),
.INIT_72(256'h7788997788886B998888770B99098F88990099886B996B8888778877990B990B),
.INIT_73(256'h997D8888BBDD8F77BB8F99889999887D88089999998877888899999977770B88),
.INIT_74(256'hBBBBBBBBBBBBBBBBBB99888FBB88BB8F9988888899887D99887D888F8F887D77),
.INIT_75(256'h7799770977D70777888F990B770B99990B9977770909887788990B9999886B88),
.INIT_76(256'h1077770955775555556B555555097705470555550955556B0977050977095577),
.INIT_77(256'h555577997777095577777799770909778F7777777777777777779977070099F8),
.INIT_78(256'h556B555507550B770755097755556B4705996B475555777D7705596B55070B55),
.INIT_79(256'h998F77889988888F77888FBB8F888FBB8F8F999999777777770777777777550B),
.INIT_7A(256'h88DDDDBBDD88888F8808098877778899880999990B880977990B997D990B88BB),
.INIT_7B(256'hDDBBDD88DDDD88DDBBBBDDDDDDDDDDFFDDFFDDDDDDDDDD88DDDD8888888FBBBB),
.INIT_7C(256'h999977997777778877999977889999990BBB9999889988999999778877777777),
.INIT_7D(256'h99999999998899889988998F99996B77779909770B9999777788888899887799),
.INIT_7E(256'h88BB88BBBBBB88BB88BBBBBB8F88BB888F888F8F889988999977997799BB99BB),
.INIT_7F(256'h05470555550955550955777799777777D707770777779999097777886B778899),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\douta[11] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7
(\douta[11] ,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]\douta[11] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]\douta[11] ;
wire [0:0]ena_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h1055037705557D5507470F336B746B770F77556B770977475509777405770977),
.INIT_01(256'h090F77073309550555077707559555354755350555550955555509055500D799),
.INIT_02(256'h475555596B777D4777777D556B595555740F5509776B5555557703556B55776B),
.INIT_03(256'h88BBBBBB8F8F8888BBBB8899BBBB88BBBB99777799077759556B550905777777),
.INIT_04(256'hBB887DDD88DDBBBB8888BBBB9908098877770809887777880988887777887799),
.INIT_05(256'h88BBDDDDBBBBDDDDBBDD88BBDDFFDDBBBBBBDD88BB8899888899880B77778888),
.INIT_06(256'h0B7788888899990B998899887788888899999999997799886B88889988778877),
.INIT_07(256'h889988886B99998F779999889988778888999988776B889999B60999776B8877),
.INIT_08(256'hBB8FDDBBBB8FDD8FBBBBBB8888BB8F8899998899990B998888998F8888777799),
.INIT_09(256'h770F77556B77097777097755470555550977556B5577057777778847880D99BB),
.INIT_0A(256'h000755597707095577557709596B477755776B053377550555770F6B556B746B),
.INIT_0B(256'h777755597D556B475555770B0703556B550509554755770755055577050077F8),
.INIT_0C(256'h556B5955505955556B5577076B6B776B550505770F476B5547596B7759095547),
.INIT_0D(256'h770D888899889988BB8F888F7D88999977776B5547775547056B558F55555509),
.INIT_0E(256'h88998888DD88BB887D9988008877090B770B887D8888000B0809990B9988778F),
.INIT_0F(256'hDDBBDDBBDDBBDD88DDBBDDDDDDDDBBDDBB888899880B8877880B778800770977),
.INIT_10(256'h8877997788888877998877996B8877000B7777990B99777D7788888899779977),
.INIT_11(256'h99886B9988998F8899886B99996B7788887777889977990B9988777799777788),
.INIT_12(256'h779999BBBBDDBB88BBBB8F88BB88BB88998F8F8F998F8899886B9988888F8877),
.INIT_13(256'h55550F55556B0F05356B476B557705053395550555770F550947050955070909),
.INIT_14(256'h1035070577550955330F77075950555505770F557D5555095555555500775505),
.INIT_15(256'h0599950B55070555556B4755777755076B35773307557755093307073300BB99),
.INIT_16(256'h77555555777D33555577595559555555090747556B55557747550F595509776B),
.INIT_17(256'h770B000B08990B8888888F8877097707556B470F7777777D330F770555740755),
.INIT_18(256'h887788880988880B778877098877880009770B7788770900778877097788880B),
.INIT_19(256'hBBDDDD88BBBB8FDDDDDDBBDDDDBB880B880B8888770088777700098809887777),
.INIT_1A(256'h6B7788779999990B8899990B77990BDD99999988997799889977099988778877),
.INIT_1B(256'h6B9988996B997777889988998877888F00887709778899779909880788779977),
.INIT_1C(256'h09777799BB88BBBBBBBB88BB88BB8FBB889988889999990B998899B6888888BB),
.INIT_1D(256'h5505770F557D555577550547550F74556B7D056B6B0F5533470F550F77555505),
.INIT_1E(256'h007D3577057707558F555577470F550F7755550547779977550F7D0977075055),
.INIT_1F(256'h99556B7D5933470B7777056B070555475507033533055505550555330F00D7F8),
.INIT_20(256'h0F557D0F55556B550D0B7D550555078F7755595535596B476B555059770F5533),
.INIT_21(256'h0B888877000988990B887777556B777755777755550B77355555055509776B55),
.INIT_22(256'h050B5507770B9988999988880B88090B880988990B88888F8809778800770899),
.INIT_23(256'hBB88DDDDBBDDBBDD8FDDDD88990B777799880B99888F0B88770B885588770B00),
.INIT_24(256'h7709778888778877997788999988888888996B77886B77998899880977777777),
.INIT_25(256'h88776B998877998F779999779977D7889999779988778877889977997799770B),
.INIT_26(256'h7705099977778888BBBB99BB998888998F888F998888998877990B77D7990B99),
.INIT_27(256'h0F775555054777990750550F057705557D3355095555550F5555057409050977),
.INIT_28(256'h00550509770999053305555555550574090509775305055555445555096B0F55),
.INIT_29(256'h55053533475507477D095555359505330955550B33094755095507335501F899),
.INIT_2A(256'h770555555555596B5577555977075555555555550747556B0907555505555907),
.INIT_2B(256'h88990B000988770B8877550709555555050F770F776609056B55557777775305),
.INIT_2C(256'h080988778888880B777705007709995588770B77880500770999008809880009),
.INIT_2D(256'hBBDDBBBBDDDDDDBBDD88BB7788880B0B880B8877057777090055888809880077),
.INIT_2E(256'h7777887709997799999999880B09F877778F77886B88880B77097777880B880B),
.INIT_2F(256'h8FBB886B776B887799990B8899880D7788997788770B9999777D8F7788888877),
.INIT_30(256'h0547740907096B8F998FBB88998FBB888899888877778F996B9999BB090D8877),
.INIT_31(256'h550F5907740977556B0F55557755770547099977050F7D350905774777550744),
.INIT_32(256'h00056B770533095555590507090577477755074409475533538F056B77055509),
.INIT_33(256'h075595090709770955557705777709550574090777770555053347550F00D799),
.INIT_34(256'h09556B0F474755555977075505596B050F55550F77550F476B77770F55777759),
.INIT_35(256'h770B88097777007777440977476B7777779909555559775555555507550F7759),
.INIT_36(256'h0988098809077777000B08990B888800770B77007708995588880B77770B0988),
.INIT_37(256'h099988DDBB88DDBBBBBB090B077777887777770B08550B880B00770988098888),
.INIT_38(256'h9909997777880B77776B77887709778899998F59990877998888558877887788),
.INIT_39(256'h997D77999999887799889988998899559988887777770988777788770D88000B),
.INIT_3A(256'h74050755055577030D55554777997D6B888F99889977996B990B77887788776B),
.INIT_3B(256'h05555577950977070F550F530774050755050947055509770905770F55555305),
.INIT_3C(256'h100B050755050947055509770905770F555553050705097455000B7707555509),
.INIT_3D(256'h0555550F0577770F55595505770755090747350577774409055959550F00D799),
.INIT_3E(256'h550F055953556B475559550B0555098F070735056B0977097D47557755553309),
.INIT_3F(256'h07770955097777097777555577530F5555550555555555555577550555557755),
.INIT_40(256'h770B0088077709880B8800778809887700090B770B0988070B88090707777709),
.INIT_41(256'h887799099977886B7709000D770D998877770B88990B8888770B888807770988),
.INIT_42(256'h77887788008F998899889999778899770B998899887D8F880999777709770977),
.INIT_43(256'h7799996B77778F99889909990B997788779999880B887777880B058855779977),
.INIT_44(256'h0955556B55778F9974550F7405557777778899999988998888998888887D8877),
.INIT_45(256'h09550F3235095577555333550709557709745577090F5532094755550F535599),
.INIT_46(256'h008F0F7709745577090F5532094755550F5355990755550933008F3377090755),
.INIT_47(256'h05770977770974440905550F77747755553377093309057707475533770077F8),
.INIT_48(256'h0555550F55336B6B55596B44597705557747094755775599035577556B054759),
.INIT_49(256'h7709776B775555770D356B770F05330F7733770F330509355509033509770559),
.INIT_4A(256'h8877097788090955880777007755770977098888777777887777558877050977),
.INIT_4B(256'h057709770B5577770B77997777888805880B8809007709770077777788090955),
.INIT_4C(256'h0B7799779947779907779999997777887799BBBB997788888888990988778877),
.INIT_4D(256'h99990B5977998888999988777777888F097777777709777777D7880977777788),
.INIT_4E(256'h747D7755775577050747777D9909555555559909999999777799070977997799),
.INIT_4F(256'h550F33590F05053305337D0955747D0907557709553335590577050555330905),
.INIT_50(256'h0055740907557709553335590577050555330905557D0F745500555509070F77),
.INIT_51(256'h095507050F557D0977770955050709770F5305777755950F770533770500D799),
.INIT_52(256'h09770777050F555509595555355509770905557705330F7755550B5959775359),
.INIT_53(256'h55770D0F553303743577094777555505500D535577777705557D550905775347),
.INIT_54(256'h0777770955777777777707070999097777777707777709557709995500777755),
.INIT_55(256'h8888770977888809770B8800000B77880B770977770577770777090955777777),
.INIT_56(256'h88770B990B0B0988770B889999880B7799889999888899997777097777777777),
.INIT_57(256'h0999887799887D776B9999779988098888550B88777788090900997788770977),
.INIT_58(256'h05230577095955557747775574777D530F740577777709777788998899099988),
.INIT_59(256'h555533355555470977055977090523775509740F55338F355533477755057755),
.INIT_5A(256'h100953775509740F55338F355533477755057755092355055500090577554474),
.INIT_5B(256'h7707775555073555053307770B9577775507550509050595077709740900BB99),
.INIT_5C(256'h0577057774740F7777470977590F7709447455056B7433470F0777556B330777),
.INIT_5D(256'h03743577050F55740959950F7705550735550B59335507330F35075555090705),
.INIT_5E(256'h7705557705555507556B55777755775509555577050977050977550555445533),
.INIT_5F(256'h55770988770B07778888778F9988777777777799073303337709777705555507),
.INIT_60(256'h997709888877998877887788090077099988BBBB888899880B8877770B770B77),
.INIT_61(256'h99770B5588778F097799887799880B000B995588550B7709880B558877777777),
.INIT_62(256'h777755050F5505774777476B7705550F533577776B7407093377770709B69988),
.INIT_63(256'h550F3377095905770777550F0577776B05555309553333775955050733770F53),
.INIT_64(256'h0077556B05555309553333775955050733770F5305770374550077056B050753),
.INIT_65(256'h77336B55770F09550F55550777550B770509050F55550707590F35050501F899),
.INIT_66(256'h095559555555055555555555550F5907770F334747770977337477740F770599),
.INIT_67(256'h09777D550553440977770F5577550B0555098F070735056B0977097D47550533),
.INIT_68(256'h55440F33076B5577594459033509336B6B55595555770555778F077735055509),
.INIT_69(256'h090777990900558807880059997777557707770B0535055503743533076B5577),
.INIT_6A(256'h0B778899770B0B770B09779988BB99779999888FBBBB88779977997788778877),
.INIT_6B(256'h0B777777B60B7788990B99770B77778899777709555588550B77770B88777788),
.INIT_6C(256'h057755557777770D6B550F530555777435590705740F77775505557777078809),
.INIT_6D(256'h557459053377533355470533090577033355770755595505770353550F473355),
.INIT_6E(256'h000709033355770755595505770353550F473355097755097709075503330977),
.INIT_6F(256'h556B05775555770555093309590F745509770955557705330F53550B7700D799),
.INIT_70(256'h77054755770F55770F556B0909557405555555474747740555590F095555556B),
.INIT_71(256'h990903777707330577775533096B445977055577470947557755990355770955),
.INIT_72(256'h0759770F6B55094759550F5509057753474477076B5959770555777D09470F77),
.INIT_73(256'h9077880777998809770755F805770B6B05470944770533555574097705534409),
.INIT_74(256'h8877770B09D7778877998899990B77770B77999988998F7788770B8877097709),
.INIT_75(256'h55000909007788777777880B77887777090B77887777097755880B7755888877),
.INIT_76(256'h7405050577050555530F7705550F550555550FB6077733050977555533770577),
.INIT_77(256'h094435550705090953530F557774057747473333093507550547095333535505),
.INIT_78(256'h1055777747473333093507550547095333535505770507775533550577474733),
.INIT_79(256'h09555907335574550933057747500507775577070905590974550F77550099F8),
.INIT_7A(256'h33550F0D5505550F44553555773307775505055905470577554705740F550959),
.INIT_7B(256'h7707550B0555555577330305075555355509770905557705330F7755550B556B),
.INIT_7C(256'h05997774770F777D4777336B77596B5955097435550F35555577093355775533),
.INIT_7D(256'h0B097788770B55777777550955555559775577075533470F0707550977073305),
.INIT_7E(256'h770B0088777777779977996B77777788770999998F9988990B88777777887788),
.INIT_7F(256'h770777770977777700777788770777009955550977558807075588770B775509),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\douta[11] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8
(DOADO,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]DOADO;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [7:0]DOADO;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [0:0]ena_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h55746B77550F05557D95775555550F6B550F770999500F777705553303070555),
.INIT_01(256'h33095505555577550F5555090555740547074747335553055505770F47550977),
.INIT_02(256'h100F590547074747335553055505770F475509770574230509550F4705473347),
.INIT_03(256'h7705350F77050555070F5307470B35770509555559097774595505054700D799),
.INIT_04(256'h0F5555550F74077709050F770333550905350977096B4733556B6B05770F7733),
.INIT_05(256'h47550F775505330955537755550977590F7709447455056B7433470F07770547),
.INIT_06(256'h55550F55555555337D0F55554759550F557D74090933590F5509440F55050F74),
.INIT_07(256'h9988000955770577056B55550F055505556B0577050555055533075505555555),
.INIT_08(256'h77777709008809777788778855777777880B7777888809558855880955775577),
.INIT_09(256'h6B77055555355555090777555509770009338855070055887707007755090777),
.INIT_0A(256'h05555577777709070707770755474755559909050753770777050B955507550F),
.INIT_0B(256'h0977055507050709553355776B05555509555507090505550555075505337705),
.INIT_0C(256'h00075555095555070905055505550755053377056B5555055505070555093355),
.INIT_0D(256'h0935740F5533093547055533070955334409550F09557707550577447700D799),
.INIT_0E(256'h055533550F593347550F055505770709054709550955057747050F7709555505),
.INIT_0F(256'h770F33775555553355335577555555550F5907770F3347477709773374770555),
.INIT_10(256'h476B550F47550F555509770D337D4755057433075547550F5507775533473377),
.INIT_11(256'h07097777550509550F0355775505550935445547553333330733357477090F77),
.INIT_12(256'h7707777799777788097709778899007777777709777777885509778877007700),
.INIT_13(256'h553309320905555555770900558809777709557788077707007709770D888855),
.INIT_14(256'h4755550F05555595777705950755473535337777770F530F059977050B956B55),
.INIT_15(256'h7455070553773555070F470503475533070553097407770577093507470F0547),
.INIT_16(256'h10740533070553097407770577093507470F0547035555090547740733070953),
.INIT_17(256'h5509553355055533090F550F097777070555055544093533335509353300BB99),
.INIT_18(256'h55774705555059050955550909553344770B7705550F55550F7D500777050555),
.INIT_19(256'h0505550F5505050F55090755056B0909557405555555474747740555590F0977),
.INIT_1A(256'h0F550D05555544595555075509555547033505556B7709550705550555474747),
.INIT_1B(256'h777755597755747D77770B077777595505777709090507333355330555555533),
.INIT_1C(256'h558805090B770077557788778809990B88777788778807770B88557709770977),
.INIT_1D(256'h0F77777777030907335555590755550977770077075500777709003300090955),
.INIT_1E(256'h05094755320F0509537709777705770F77095507073359770955097753075505),
.INIT_1F(256'h0535334705050533555577555505095547770577053305470577055547555509),
.INIT_20(256'h0005335547770577053305470577055547555509550905743305057755470705),
.INIT_21(256'h0577550955090977075505550555057705474705555505550533070F0500D7F8),
.INIT_22(256'h074755556B0F595507077707075505770705097705550577550509330F777705),
.INIT_23(256'h777D55059977597D555577093335557733077755050559054705775547050777),
.INIT_24(256'h55055574070709770577557755556B7733353335350777335577557705595547),
.INIT_25(256'h55550B4759557755557774550755477755590F7455550533470D550B5505050F),
.INIT_26(256'h07777790557777058807770077990077448809558877778855770B7777777777),
.INIT_27(256'h5505327705773353550977353355055555557709550999000055770977888877),
.INIT_28(256'h77530B0F055555777755077755550F5505770974550535477733550555557709),
.INIT_29(256'h0955090907530935050533050977530933095555090977095323090577050555),
.INIT_2A(256'h0009550933095555090977095323090577050555095305330977090709335555),
.INIT_2B(256'h35550B550574770574770933053374093305057709097709350977557701F899),
.INIT_2C(256'h5947470B55337709770955777709770555775509553355090947445505550955),
.INIT_2D(256'h3307556B55595555070505778F0F770333550905350977096B4733556B6B0955),
.INIT_2E(256'h556B550F6B7755555509550F59553507330755330F550333050905470977776B),
.INIT_2F(256'h557747557705550F55556B6B7709550F556B77057733550F7707057705777755),
.INIT_30(256'h09880577888809550B0477880955887700557777880077099977778855885588),
.INIT_31(256'h7755550977055553555933095309775577555505335507335509775533078877),
.INIT_32(256'h5574773305330533557755090553053333057733530555555553097707050577),
.INIT_33(256'h55330907057777550505530F0555745309550977550933077705770555050F55),
.INIT_34(256'h1077075309550977550933077705770555050F55057435050507770753090509),
.INIT_35(256'h09779507550977057733097733330705095555050B09475505745577070099F8),
.INIT_36(256'h77090F05777707057709740F555509550907300B057709770955777705770907),
.INIT_37(256'h7705470F773377776B33050907055505770709054709550955057747050F0905),
.INIT_38(256'h77057777550F6B55706B777D555577550F350705055505775509055509555555),
.INIT_39(256'h07749959555574550F557707770F330509747777746B5377097707550F350705),
.INIT_3A(256'h5533777755058855007709557707330999000955090777550000095509550977),
.INIT_3B(256'h05330F7774090307557755777735335505090577090555033355075555555507),
.INIT_3C(256'h5505070977550505330977440F555307557403550F3309554735333355337733),
.INIT_3D(256'h07550709555509530F0977090F55057707554409070777095533090F53090933),
.INIT_3E(256'h1033337707554409070777095533090F530909330F0533557744330577075544),
.INIT_3F(256'h0955333533055533053347050F7077097703550977770507550B07097700D799),
.INIT_40(256'h774455770309550977550777050977330F5533550944330F530F077409030F53),
.INIT_41(256'h773347330F7074097707550955770577055555550F5555550974095505097755),
.INIT_42(256'h0955333533055533053347050F70770977035509777705530955333533055533),
.INIT_43(256'h0905555509770F55550B7455330977330F5533550944330F530F077409030F53),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],DOADO}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bg_mid_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [14:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [14:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_mid_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "15" *) (* C_ADDRB_WIDTH = "15" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "5" *)
(* C_COUNT_36K_BRAM = "5" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 7.0707579999999997 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bg_mid.mem" *)
(* C_INIT_FILE_NAME = "bg_mid.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "18560" *) (* C_READ_DEPTH_B = "18560" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "18560" *) (* C_WRITE_DEPTH_B = "18560" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module bg_mid_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [14:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [14:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [14:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [14:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [14:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[14] = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[14] = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bg_mid_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module bg_mid_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [14:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [14:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_mid_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_32x32_dp_be.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ram_32x32_dp_be (
address_a,
address_b,
byteena_a,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [4:0] address_a;
input [4:0] address_b;
input [3:0] byteena_a;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena_a;
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1024"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 5 0 INPUT NODEFVAL "address_a[4..0]"
// Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL "address_b[4..0]"
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC "byteena_a[3..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address_a 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`define CYCLE_TIME 50
`include "StateTable.v"
module Cache_TestBench;
integer i, outfile, outfile2, counter;
parameter flush_cycle = 300;
reg clk, rst, start;
reg flag;
reg [26:0] address;
reg [23:0] tag;
reg [4:0] index;
wire [256-1:0] mem_cpu_data;
wire mem_cpu_ack;
wire [256-1:0] cpu_mem_data;
wire [32-1:0] cpu_mem_addr;
wire cpu_mem_enable;
wire cpu_mem_write;
always #(`CYCLE_TIME/2)
clk = ~clk;
CPU CPU(
.clk (clk),
.rst (rst),
.start (start),
// Interface to external memory.
.ext_mem_addr (cpu_mem_addr),
.ext_mem_data_i (mem_cpu_data),
.ext_mem_cs (cpu_mem_enable),
.ext_mem_we (cpu_mem_write),
.ext_mem_data_o (cpu_mem_data),
.ext_mem_ack (mem_cpu_ack)
);
Data_Memory Data_Memory
(
.clk_i (clk),
.rst_i (rst),
.addr_i (cpu_mem_addr),
.data_i (cpu_mem_data),
.enable_i (cpu_mem_enable),
.write_i (cpu_mem_write),
.ack_o (mem_cpu_ack),
.data_o (mem_cpu_data)
);
/*
// External memory, 16KB.
DRAM #(.data_width(256), .mem_size(2048), .delay(10)) Data_Memory (
.clk (clk),
// Interface to the CPU.
.addr_i (cpu_mem_addr),
.data_i (cpu_mem_data),
.cs (cpu_mem_enable),
.we (cpu_mem_write),
.ack (mem_cpu_ack),
.data_o (mem_cpu_data)
);
*/
initial begin
counter = 1;
// initialize data memory (16KB)
for(i=0; i<512; i=i+1) begin
Data_Memory.memory[i] = 256'b0;
end
// initialize cache memory (1KB)
for(i=0; i<32; i=i+1) begin
CPU.L1Cache.dcache_tag_sram.memory[i] = 24'b0;
CPU.L1Cache.dcache_data_sram.memory[i] = 256'b0;
end
// Load instructions into instruction memory
$readmemb(".\\dat\\cache_instruction.txt", CPU.InstrMem.memory);
// Open output file
outfile = $fopen(".\\dat\\output.txt") | 1;
outfile2 = $fopen(".\\dat\\cache.txt") | 1;
// Set Input n into data memory at 0x00
Data_Memory.memory[0] = 256'h5; // n = 5 for example
/*
clk = 0;
rst = 1;
start = 0;
#(`CYCLE_TIME/8)
rst = 0;
#(`CYCLE_TIME/8)
start = 1;
#(`CYCLE_TIME/8)
rst = 1;
*/
clk = 0;
rst = 0;
start = 0;
#(`CYCLE_TIME/4)
rst = 1;
start = 1;
end
always @ (posedge clk) begin
// Store cache to memory.
if(counter > flush_cycle)
$stop;
else if(counter == flush_cycle) begin
$fdisplay(outfile, "Flush Cache! \n");
for(i=0; i<32; i=i+1) begin
tag = CPU.L1Cache.dcache_tag_sram.memory[i];
index = i;
address = {tag[21:0], index};
Data_Memory.memory[address] = CPU.L1Cache.dcache_data_sram.memory[i];
end
end
$fdisplay(outfile, "cycle = %d, Start = %b", counter, start);
$fdisplay(outfile, "PC = %d", CPU.PC.addr_o);
// Dump the registers.
$fdisplay(outfile, "RegFiles");
$fdisplay(outfile, "R0(r0) = %h, R8 (t0) = %h, R16(s0) = %h, R24(t8) = %h", CPU.RegFiles.register[0], CPU.RegFiles.register[8] , CPU.RegFiles.register[16], CPU.RegFiles.register[24]);
$fdisplay(outfile, "R1(at) = %h, R9 (t1) = %h, R17(s1) = %h, R25(t9) = %h", CPU.RegFiles.register[1], CPU.RegFiles.register[9] , CPU.RegFiles.register[17], CPU.RegFiles.register[25]);
$fdisplay(outfile, "R2(v0) = %h, R10(t2) = %h, R18(s2) = %h, R26(k0) = %h", CPU.RegFiles.register[2], CPU.RegFiles.register[10], CPU.RegFiles.register[18], CPU.RegFiles.register[26]);
$fdisplay(outfile, "R3(v1) = %h, R11(t3) = %h, R19(s3) = %h, R27(k1) = %h", CPU.RegFiles.register[3], CPU.RegFiles.register[11], CPU.RegFiles.register[19], CPU.RegFiles.register[27]);
$fdisplay(outfile, "R4(a0) = %h, R12(t4) = %h, R20(s4) = %h, R28(gp) = %h", CPU.RegFiles.register[4], CPU.RegFiles.register[12], CPU.RegFiles.register[20], CPU.RegFiles.register[28]);
$fdisplay(outfile, "R5(a1) = %h, R13(t5) = %h, R21(s5) = %h, R29(sp) = %h", CPU.RegFiles.register[5], CPU.RegFiles.register[13], CPU.RegFiles.register[21], CPU.RegFiles.register[29]);
$fdisplay(outfile, "R6(a2) = %h, R14(t6) = %h, R22(s6) = %h, R30(s8) = %h", CPU.RegFiles.register[6], CPU.RegFiles.register[14], CPU.RegFiles.register[22], CPU.RegFiles.register[30]);
$fdisplay(outfile, "R7(a3) = %h, R15(t7) = %h, R23(s7) = %h, R31(ra) = %h", CPU.RegFiles.register[7], CPU.RegFiles.register[15], CPU.RegFiles.register[23], CPU.RegFiles.register[31]);
// Dump the data memory.
$fdisplay(outfile, "Data Memory: 0x0000 = %h", Data_Memory.memory[0]);
$fdisplay(outfile, "Data Memory: 0x0020 = %h", Data_Memory.memory[1]);
$fdisplay(outfile, "Data Memory: 0x0040 = %h", Data_Memory.memory[2]);
$fdisplay(outfile, "Data Memory: 0x0060 = %h", Data_Memory.memory[3]);
$fdisplay(outfile, "Data Memory: 0x0080 = %h", Data_Memory.memory[4]);
$fdisplay(outfile, "Data Memory: 0x00A0 = %h", Data_Memory.memory[5]);
$fdisplay(outfile, "Data Memory: 0x00C0 = %h", Data_Memory.memory[6]);
$fdisplay(outfile, "Data Memory: 0x00E0 = %h", Data_Memory.memory[7]);
$fdisplay(outfile, "Data Memory: 0x0400 = %h", Data_Memory.memory[32]);
$fdisplay(outfile, "\n");
// Print the status of data cache.
// print Data Cache Status
if(CPU.L1Cache.p1_stall_o && CPU.L1Cache.state==0) begin
if(CPU.L1Cache.sram_dirty) begin
if(CPU.L1Cache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h (Write Back!)", counter, CPU.L1Cache.p1_addr_i, CPU.L1Cache.p1_data_i);
else if(CPU.L1Cache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h (Write Back!)", counter, CPU.L1Cache.p1_addr_i, CPU.L1Cache.p1_data_o);
end
else begin
if(CPU.L1Cache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h", counter, CPU.L1Cache.p1_addr_i, CPU.L1Cache.p1_data_i);
else if(CPU.L1Cache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h", counter, CPU.L1Cache.p1_addr_i, CPU.L1Cache.p1_data_o);
end
flag = 1'b1;
end
else if(!CPU.L1Cache.p1_stall_o) begin
if(!flag) begin
if(CPU.L1Cache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Hit , Address: %h, Write Data: %h", counter, CPU.L1Cache.p1_addr_i, CPU.L1Cache.p1_data_i);
else if(CPU.L1Cache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Hit , Address: %h, Read Data : %h", counter, CPU.L1Cache.p1_addr_i, CPU.L1Cache.p1_data_o);
end
flag = 1'b0;
end
counter = counter+1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_8_V
`define SKY130_FD_SC_HDLL__CLKINV_8_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_8_V
|
module s349 (
B0,
A1,
B1,
A2,
A3,
blif_clk_net,
START,
B3,
A0,
blif_reset_net,
B2,
P7,
P5,
CNTVCON2,
P2,
P1,
CNTVCO2,
P0,
P6,
READY,
P3,
P4);
// Start PIs
input B0;
input A1;
input B1;
input A2;
input A3;
input blif_clk_net;
input START;
input B3;
input A0;
input blif_reset_net;
input B2;
// Start POs
output P7;
output P5;
output CNTVCON2;
output P2;
output P1;
output CNTVCO2;
output P0;
output P6;
output READY;
output P3;
output P4;
// Start wires
wire net_166;
wire net_107;
wire net_47;
wire net_179;
wire net_176;
wire net_159;
wire net_61;
wire net_137;
wire net_132;
wire net_54;
wire net_105;
wire net_62;
wire P3;
wire net_6;
wire net_129;
wire net_119;
wire net_98;
wire net_23;
wire P5;
wire net_117;
wire net_12;
wire B1;
wire net_151;
wire net_74;
wire net_53;
wire net_93;
wire net_168;
wire net_135;
wire net_130;
wire net_147;
wire net_127;
wire net_14;
wire P1;
wire net_113;
wire net_26;
wire net_76;
wire blif_clk_net;
wire net_101;
wire net_32;
wire net_111;
wire net_90;
wire net_40;
wire net_100;
wire net_85;
wire net_69;
wire net_124;
wire net_161;
wire net_141;
wire net_160;
wire net_83;
wire net_115;
wire B3;
wire net_4;
wire net_95;
wire net_17;
wire net_173;
wire net_78;
wire A1;
wire net_27;
wire net_164;
wire net_56;
wire net_87;
wire net_0;
wire net_155;
wire net_35;
wire net_16;
wire net_22;
wire net_181;
wire net_39;
wire net_157;
wire net_144;
wire net_102;
wire net_2;
wire net_59;
wire net_9;
wire net_42;
wire net_120;
wire A3;
wire net_109;
wire net_80;
wire net_65;
wire blif_reset_net;
wire net_50;
wire net_162;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire net_167;
wire net_136;
wire net_134;
wire net_19;
wire net_89;
wire net_45;
wire net_126;
wire B0;
wire net_34;
wire net_108;
wire net_178;
wire net_150;
wire net_63;
wire P2;
wire net_152;
wire net_116;
wire net_30;
wire net_175;
wire net_91;
wire net_106;
wire net_24;
wire net_55;
wire net_99;
wire net_46;
wire net_140;
wire net_118;
wire P7;
wire net_148;
wire net_104;
wire net_146;
wire net_72;
wire net_122;
wire net_25;
wire net_7;
wire net_70;
wire P4;
wire net_172;
wire net_5;
wire net_52;
wire net_165;
wire net_128;
wire P0;
wire net_138;
wire net_13;
wire P6;
wire net_94;
wire net_11;
wire CNTVCON2;
wire net_18;
wire net_123;
wire net_131;
wire net_114;
wire CNTVCO2;
wire net_170;
wire net_29;
wire net_68;
wire net_149;
wire net_142;
wire net_77;
wire net_20;
wire net_31;
wire net_36;
wire net_49;
wire net_158;
wire net_15;
wire net_41;
wire net_57;
wire A2;
wire net_71;
wire net_153;
wire START;
wire net_156;
wire net_3;
wire net_84;
wire net_174;
wire net_154;
wire net_112;
wire net_1;
wire net_92;
wire net_103;
wire net_139;
wire net_43;
wire net_10;
wire net_180;
wire net_28;
wire net_169;
wire net_21;
wire net_51;
wire net_171;
wire net_79;
wire net_143;
wire net_97;
wire net_88;
wire net_182;
wire net_145;
wire net_60;
wire net_81;
wire net_163;
wire net_58;
wire B2;
wire net_67;
wire net_82;
wire net_64;
wire net_37;
wire net_110;
wire net_121;
wire net_73;
wire net_33;
wire net_48;
wire net_177;
wire net_8;
wire net_75;
wire net_86;
wire net_133;
wire READY;
wire A0;
wire net_125;
// Start cells
CLKBUF_X2 inst_145 ( .A(net_133), .Z(net_134) );
INV_X4 inst_103 ( .ZN(net_64), .A(net_52) );
DFFR_X2 inst_125 ( .RN(net_102), .D(net_73), .QN(net_6), .CK(net_179) );
DFFR_X1 inst_138 ( .D(net_103), .RN(net_102), .QN(net_2), .CK(net_150) );
CLKBUF_X2 inst_159 ( .A(net_147), .Z(net_148) );
NOR2_X2 inst_15 ( .ZN(net_85), .A2(net_77), .A1(START) );
DFFR_X2 inst_134 ( .RN(net_102), .D(net_87), .QN(net_13), .CK(net_146) );
CLKBUF_X2 inst_179 ( .A(blif_clk_net), .Z(net_168) );
NAND3_X2 inst_24 ( .A2(net_100), .ZN(net_99), .A3(net_95), .A1(net_61) );
INV_X2 inst_114 ( .A(net_42), .ZN(P1) );
OR2_X2 inst_6 ( .A2(net_113), .ZN(net_90), .A1(net_89) );
DFFR_X2 inst_131 ( .RN(net_102), .D(net_86), .QN(net_9), .CK(net_159) );
INV_X4 inst_76 ( .A(net_128), .ZN(net_126) );
CLKBUF_X2 inst_180 ( .A(net_168), .Z(net_169) );
CLKBUF_X2 inst_160 ( .A(net_148), .Z(net_149) );
CLKBUF_X2 inst_150 ( .A(net_138), .Z(net_139) );
NAND2_X4 inst_33 ( .ZN(net_112), .A1(net_52), .A2(net_2) );
CLKBUF_X2 inst_172 ( .A(net_137), .Z(net_161) );
INV_X4 inst_83 ( .ZN(net_56), .A(net_3) );
NAND2_X2 inst_47 ( .ZN(net_39), .A1(net_38), .A2(READY) );
NAND3_X2 inst_19 ( .ZN(net_71), .A3(net_70), .A2(net_46), .A1(P5) );
INV_X1 inst_123 ( .ZN(net_102), .A(blif_reset_net) );
INV_X2 inst_121 ( .ZN(net_111), .A(net_65) );
OR2_X4 inst_2 ( .ZN(net_40), .A2(READY), .A1(B3) );
NOR3_X2 inst_8 ( .ZN(net_80), .A1(net_78), .A3(net_51), .A2(START) );
INV_X2 inst_118 ( .ZN(net_70), .A(net_68) );
INV_X4 inst_86 ( .ZN(net_100), .A(START) );
CLKBUF_X2 inst_153 ( .A(net_141), .Z(net_142) );
NAND3_X2 inst_20 ( .A3(net_117), .ZN(net_116), .A1(net_113), .A2(P6) );
NAND3_X2 inst_27 ( .A3(net_109), .A1(net_108), .ZN(net_103), .A2(net_100) );
NAND2_X4 inst_38 ( .A1(net_105), .ZN(net_94), .A2(net_89) );
INV_X4 inst_100 ( .ZN(net_45), .A(net_32) );
NAND2_X2 inst_52 ( .ZN(net_57), .A1(net_35), .A2(net_34) );
INV_X4 inst_90 ( .ZN(net_17), .A(net_2) );
AND2_X4 inst_140 ( .A1(net_121), .ZN(net_118), .A2(net_0) );
NAND2_X4 inst_40 ( .A1(net_104), .ZN(net_97), .A2(net_66) );
CLKBUF_X2 inst_162 ( .A(net_148), .Z(net_151) );
CLKBUF_X2 inst_167 ( .A(net_146), .Z(net_156) );
INV_X4 inst_93 ( .ZN(net_18), .A(net_16) );
INV_X4 inst_81 ( .ZN(net_24), .A(net_10) );
INV_X4 inst_95 ( .ZN(net_23), .A(net_18) );
XNOR2_X2 inst_1 ( .ZN(net_79), .A(net_78), .B(net_27) );
MUX2_X2 inst_72 ( .S(net_123), .Z(net_83), .A(net_60), .B(net_38) );
CLKBUF_X3 inst_139 ( .A(net_121), .Z(P0) );
CLKBUF_X2 inst_155 ( .A(net_143), .Z(net_144) );
NAND2_X2 inst_59 ( .A2(net_128), .ZN(net_109), .A1(net_20) );
DFFR_X2 inst_135 ( .RN(net_102), .D(net_96), .QN(net_0), .CK(net_142) );
NAND2_X2 inst_44 ( .A2(net_121), .ZN(net_53), .A1(net_33) );
NAND2_X2 inst_55 ( .ZN(net_60), .A1(net_44), .A2(net_43) );
CLKBUF_X2 inst_174 ( .A(net_162), .Z(net_163) );
INV_X2 inst_115 ( .ZN(net_19), .A(P5) );
NAND2_X4 inst_37 ( .A1(net_114), .A2(net_112), .ZN(net_105) );
CLKBUF_X2 inst_148 ( .A(net_136), .Z(net_137) );
CLKBUF_X2 inst_164 ( .A(net_152), .Z(net_153) );
CLKBUF_X2 inst_191 ( .A(net_154), .Z(net_180) );
OR2_X2 inst_5 ( .ZN(net_35), .A2(READY), .A1(B0) );
CLKBUF_X2 inst_157 ( .A(net_145), .Z(net_146) );
INV_X4 inst_84 ( .ZN(net_38), .A(net_12) );
NAND2_X2 inst_51 ( .ZN(net_66), .A1(net_56), .A2(net_53) );
CLKBUF_X2 inst_142 ( .A(net_130), .Z(net_131) );
INV_X4 inst_80 ( .ZN(net_16), .A(net_8) );
CLKBUF_X2 inst_173 ( .A(net_161), .Z(net_162) );
INV_X2 inst_105 ( .A(net_128), .ZN(net_127) );
MUX2_X2 inst_68 ( .S(net_122), .Z(net_72), .B(net_33), .A(A3) );
INV_X4 inst_78 ( .ZN(net_120), .A(P0) );
NAND2_X2 inst_42 ( .ZN(net_48), .A1(net_27), .A2(net_23) );
CLKBUF_X2 inst_175 ( .A(net_139), .Z(net_164) );
NAND2_X2 inst_53 ( .ZN(net_58), .A1(net_41), .A2(net_39) );
CLKBUF_X2 inst_177 ( .A(net_165), .Z(net_166) );
CLKBUF_X2 inst_183 ( .A(net_171), .Z(net_172) );
DFFR_X2 inst_133 ( .QN(net_121), .RN(net_102), .D(net_88), .CK(net_132) );
NAND3_X2 inst_26 ( .A2(net_125), .ZN(net_108), .A3(net_107), .A1(net_106) );
CLKBUF_X2 inst_151 ( .A(net_139), .Z(net_140) );
INV_X2 inst_112 ( .A(net_38), .ZN(P2) );
NAND2_X2 inst_64 ( .ZN(net_115), .A2(net_94), .A1(net_90) );
INV_X2 inst_107 ( .A(net_114), .ZN(net_113) );
NAND2_X2 inst_67 ( .A1(net_126), .ZN(net_98), .A2(net_97) );
CLKBUF_X2 inst_181 ( .A(net_169), .Z(net_170) );
DFFR_X2 inst_127 ( .RN(net_102), .D(net_80), .QN(net_8), .CK(net_172) );
MUX2_X2 inst_70 ( .S(net_122), .Z(net_74), .B(net_21), .A(A1) );
CLKBUF_X2 inst_186 ( .A(net_174), .Z(net_175) );
DFFR_X2 inst_129 ( .RN(net_102), .D(net_85), .QN(net_10), .CK(net_163) );
INV_X4 inst_92 ( .A(net_15), .ZN(P5) );
NAND2_X4 inst_29 ( .A1(net_118), .ZN(net_68), .A2(net_30) );
CLKBUF_X2 inst_189 ( .A(net_158), .Z(net_178) );
NAND3_X4 inst_17 ( .ZN(net_49), .A2(net_24), .A3(net_16), .A1(net_9) );
NOR2_X2 inst_11 ( .ZN(net_51), .A2(net_49), .A1(net_26) );
CLKBUF_X2 inst_146 ( .A(net_134), .Z(net_135) );
CLKBUF_X2 inst_188 ( .A(net_176), .Z(net_177) );
NOR2_X2 inst_14 ( .A1(net_129), .ZN(net_81), .A2(net_70) );
CLKBUF_X2 inst_187 ( .A(net_175), .Z(net_176) );
INV_X2 inst_122 ( .A(net_94), .ZN(net_92) );
NAND2_X4 inst_31 ( .ZN(net_128), .A2(net_122), .A1(net_49) );
NAND3_X2 inst_25 ( .ZN(net_101), .A2(net_100), .A3(net_98), .A1(net_63) );
DFFR_X2 inst_126 ( .RN(net_102), .D(net_75), .QN(net_4), .CK(net_177) );
CLKBUF_X2 inst_158 ( .A(net_138), .Z(net_147) );
CLKBUF_X2 inst_141 ( .A(blif_clk_net), .Z(net_130) );
NAND2_X2 inst_62 ( .A1(net_128), .ZN(net_82), .A2(net_57) );
INV_X2 inst_110 ( .A(net_56), .ZN(P7) );
MUX2_X2 inst_74 ( .S(net_124), .Z(net_87), .B(net_69), .A(net_59) );
NAND2_X2 inst_57 ( .A2(net_128), .ZN(net_62), .A1(net_54) );
NAND2_X4 inst_35 ( .ZN(net_89), .A1(net_64), .A2(net_17) );
INV_X4 inst_99 ( .A(net_49), .ZN(READY) );
NAND2_X2 inst_48 ( .ZN(net_43), .A1(net_42), .A2(READY) );
MUX2_X2 inst_69 ( .S(net_122), .Z(net_73), .B(net_28), .A(A2) );
NAND2_X2 inst_46 ( .ZN(net_37), .A1(net_36), .A2(READY) );
INV_X4 inst_82 ( .ZN(net_21), .A(net_5) );
DFFR_X2 inst_136 ( .RN(net_102), .D(net_99), .QN(net_1), .CK(net_140) );
NAND2_X4 inst_30 ( .A1(net_121), .ZN(net_29), .A2(net_28) );
INV_X4 inst_102 ( .ZN(net_46), .A(net_45) );
INV_X2 inst_108 ( .ZN(net_33), .A(net_7) );
CLKBUF_X2 inst_165 ( .A(net_153), .Z(net_154) );
NAND2_X4 inst_32 ( .ZN(net_129), .A1(net_45), .A2(net_15) );
NAND3_X2 inst_22 ( .A2(net_127), .A3(net_116), .A1(net_115), .ZN(net_95) );
CLKBUF_X2 inst_144 ( .A(net_131), .Z(net_133) );
NAND2_X4 inst_34 ( .ZN(net_119), .A2(net_68), .A1(net_47) );
NOR2_X2 inst_12 ( .ZN(net_78), .A1(net_25), .A2(READY) );
NAND2_X2 inst_56 ( .A2(net_128), .ZN(net_61), .A1(net_19) );
MUX2_X2 inst_71 ( .S(net_122), .Z(net_75), .B(net_30), .A(A0) );
NAND3_X2 inst_21 ( .A2(net_126), .ZN(net_93), .A3(net_91), .A1(net_71) );
INV_X4 inst_104 ( .ZN(net_67), .A(net_66) );
NAND2_X2 inst_60 ( .ZN(net_69), .A2(net_68), .A1(net_55) );
CLKBUF_X2 inst_169 ( .A(net_157), .Z(net_158) );
CLKBUF_X2 inst_168 ( .A(net_156), .Z(net_157) );
INV_X4 inst_97 ( .ZN(net_25), .A(net_23) );
CLKBUF_X2 inst_161 ( .A(net_149), .Z(net_150) );
DFFR_X2 inst_124 ( .RN(net_102), .D(net_72), .QN(net_7), .CK(net_182) );
NAND3_X2 inst_18 ( .ZN(net_122), .A2(net_18), .A3(net_10), .A1(net_9) );
NOR2_X2 inst_16 ( .ZN(net_86), .A2(net_79), .A1(START) );
INV_X4 inst_88 ( .ZN(net_15), .A(net_1) );
OR2_X4 inst_3 ( .ZN(net_41), .A2(READY), .A1(B2) );
CLKBUF_X2 inst_156 ( .A(net_144), .Z(net_145) );
NOR2_X2 inst_9 ( .A2(net_48), .A1(net_14), .ZN(CNTVCO2) );
INV_X2 inst_113 ( .A(net_36), .ZN(P3) );
CLKBUF_X2 inst_170 ( .A(net_158), .Z(net_159) );
NAND2_X2 inst_50 ( .ZN(net_55), .A1(net_54), .A2(net_31) );
DFFR_X2 inst_137 ( .RN(net_102), .D(net_101), .QN(net_3), .CK(net_137) );
NAND2_X4 inst_41 ( .A2(net_110), .ZN(net_106), .A1(net_97) );
DFFR_X2 inst_130 ( .RN(net_102), .D(net_83), .QN(net_11), .CK(net_160) );
INV_X4 inst_91 ( .A(net_24), .ZN(net_14) );
DFFR_X2 inst_132 ( .RN(net_102), .D(net_84), .QN(net_12), .CK(net_155) );
CLKBUF_X2 inst_143 ( .A(net_131), .Z(net_132) );
CLKBUF_X2 inst_176 ( .A(net_164), .Z(net_165) );
CLKBUF_X2 inst_152 ( .A(net_138), .Z(net_141) );
NAND2_X2 inst_58 ( .A2(net_128), .ZN(net_63), .A1(net_56) );
NAND2_X4 inst_36 ( .A2(net_129), .A1(net_119), .ZN(net_114) );
CLKBUF_X2 inst_147 ( .A(net_135), .Z(net_136) );
INV_X4 inst_87 ( .ZN(net_42), .A(net_11) );
NAND2_X2 inst_61 ( .A2(net_125), .ZN(net_76), .A1(net_42) );
NAND2_X2 inst_45 ( .A1(net_120), .ZN(net_34), .A2(READY) );
INV_X4 inst_96 ( .ZN(net_27), .A(net_9) );
INV_X4 inst_101 ( .ZN(net_52), .A(net_29) );
XNOR2_X2 inst_0 ( .ZN(net_77), .A(net_50), .B(net_24) );
CLKBUF_X2 inst_184 ( .A(net_142), .Z(net_173) );
NOR2_X2 inst_10 ( .ZN(net_50), .A1(net_48), .A2(READY) );
OR2_X4 inst_4 ( .ZN(net_44), .A2(READY), .A1(B1) );
NAND2_X2 inst_65 ( .ZN(net_110), .A2(net_94), .A1(net_67) );
CLKBUF_X2 inst_178 ( .A(net_166), .Z(net_167) );
INV_X4 inst_89 ( .ZN(net_54), .A(net_0) );
NAND2_X4 inst_28 ( .A2(net_121), .ZN(net_22), .A1(net_21) );
INV_X2 inst_111 ( .A(net_54), .ZN(P4) );
NAND2_X2 inst_66 ( .ZN(net_107), .A2(net_92), .A1(net_65) );
INV_X2 inst_117 ( .ZN(net_26), .A(net_25) );
INV_X4 inst_98 ( .ZN(net_32), .A(net_22) );
CLKBUF_X2 inst_190 ( .A(net_178), .Z(net_179) );
NAND2_X2 inst_63 ( .ZN(net_88), .A2(net_82), .A1(net_76) );
OR2_X2 inst_7 ( .A2(net_113), .ZN(net_91), .A1(net_81) );
CLKBUF_X2 inst_185 ( .A(net_173), .Z(net_174) );
CLKBUF_X2 inst_182 ( .A(net_170), .Z(net_171) );
NAND2_X2 inst_49 ( .ZN(net_47), .A1(net_32), .A2(net_1) );
INV_X2 inst_120 ( .ZN(net_117), .A(net_64) );
CLKBUF_X2 inst_154 ( .A(net_138), .Z(net_143) );
NOR2_X2 inst_13 ( .ZN(net_65), .A1(net_56), .A2(net_53) );
INV_X2 inst_119 ( .ZN(CNTVCON2), .A(CNTVCO2) );
INV_X8 inst_75 ( .A(net_128), .ZN(net_123) );
CLKBUF_X2 inst_192 ( .A(net_180), .Z(net_181) );
CLKBUF_X2 inst_166 ( .A(net_154), .Z(net_155) );
INV_X2 inst_116 ( .ZN(net_20), .A(P6) );
CLKBUF_X2 inst_163 ( .A(net_151), .Z(net_152) );
INV_X4 inst_85 ( .ZN(net_30), .A(net_4) );
NAND2_X2 inst_54 ( .ZN(net_59), .A1(net_40), .A2(net_37) );
INV_X4 inst_79 ( .ZN(net_36), .A(net_13) );
INV_X2 inst_109 ( .ZN(net_28), .A(net_6) );
INV_X2 inst_106 ( .A(net_128), .ZN(net_125) );
CLKBUF_X2 inst_193 ( .A(net_181), .Z(net_182) );
CLKBUF_X2 inst_149 ( .A(net_130), .Z(net_138) );
NAND2_X2 inst_43 ( .A2(net_121), .ZN(net_31), .A1(net_30) );
NAND2_X4 inst_39 ( .A2(net_111), .ZN(net_104), .A1(net_94) );
DFFR_X2 inst_128 ( .RN(net_102), .D(net_74), .QN(net_5), .CK(net_167) );
MUX2_X2 inst_73 ( .S(net_123), .Z(net_84), .A(net_58), .B(net_36) );
NAND3_X2 inst_23 ( .A2(net_100), .ZN(net_96), .A3(net_93), .A1(net_62) );
CLKBUF_X2 inst_171 ( .A(net_132), .Z(net_160) );
INV_X4 inst_77 ( .A(net_128), .ZN(net_124) );
INV_X4 inst_94 ( .A(net_17), .ZN(P6) );
endmodule
|
//`include "timescale.vh"
module spi (
input wire clk,
input wire resn,
input wire trig,
output wire done,
output reg [15:0] rdData,
input wire [15:0] wrData,
// SPI interface
output reg SCLK,
output reg SS,
output reg MOSI,
input wire MISO
);
reg [3:0] state;
reg [15:0] bitCount;
reg [15:0] clkCounter;
// Generate SPI clock
// ADC operates from 0.8 to 3.2 MHz
always @ (posedge clk) begin
clkCounter = clkCounter + 1;
if (clkCounter == 33) begin
SCLK <= !SCLK;
end
end
always @ (SCLK) begin
if (!resn) begin
SS <= 1;
MOSI <= 0;
state <= 0;
bitCount <= 0;
end else begin
case (state)
0: begin
// Idle
if (trig) begin
if (SCLK == 0) begin
// SS should be lowered on the first falling edge of SCLK
SS <= 0;
state <= 1;
bitCount <= 15;
end
end
end
1: begin
if (SCLK == 0) begin
// In order to avoid potential race conditions, the
// user should generate MOSI on the negative edges of SCLK.
MOSI <= wrData[bitCount];
bitCount <= bitCount - 1;
if (bitCount == 0) begin
state <= 2;
end
end else begin
// Capture data bits on the rising edge of SCLK.
rdData[bitCount] <= MISO;
end
end
2: begin
if (SCLK == 1) begin
// SS should be raised on the last rising edge of an operational frame.
SS <= 1;
MOSI <= 0;
state <= 0;
bitCount <= 0;
end
end
default: ;
endcase
end
end
assign done = SS;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O311A_PP_BLACKBOX_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_PP_BLACKBOX_V
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: hb_pll.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1.30 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module hb_pll (
inclk0,
pllena,
areset,
c0,
c1,
c2,
locked);
input inclk0;
input pllena;
input areset;
output c0;
output c1;
output c2;
output locked;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "33.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.000"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: PLL_TYPE STRING "FAST"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL hb_pll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hb_pll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hb_pll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hb_pll.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hb_pll_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hb_pll_bb.v TRUE FALSE
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:11:44 04/08/2014
// Design Name: fourbit_cpu
// Module Name: C:/Users/Jonathan/Documents/Xilinx/Projects/CPU/test_cpu.v
// Project Name: CPU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fourbit_cpu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_cpu;
// Inputs
reg clk;
reg clr;
reg [7:0] sw;
reg [1:0] btn;
// Outputs
wire [3:0] led;
wire decimal;
wire [3:0] enable;
wire [6:0] segs;
// Instantiate the Unit Under Test (UUT)
fourbit_cpu uut (
.clk(clk),
.clr(clr),
.sw(sw),
.btn(btn),
.led(led),
.decimal(decimal),
.enable(enable),
.segs(segs)
);
initial begin
$display("Simulation has Started..");
// Initialize Inputs
clk = 0;
clr = 0;
sw = 0;
btn = 0;
// Wait 100 ns for global reset to finish
#100;
clr = 1'b1;
#30;
clr = 1'b0;
// Test user mode.
// **************************************************************
// Test load
sw = 8'b00000100; // R[0] <- 4
btn = 2'b01;
#40;
btn = 2'b00;
#100;
sw = 8'b00010011; // R[1] <- 3
btn = 2'b01;
#40;
btn = 2'b00;
#100;
sw = 8'b00100010; // R[2] <- 2
btn = 2'b01;
#40;
btn = 2'b00;
#100;
sw = 8'b00110001; // R[3] <- 1
btn = 2'b01;
#40;
btn = 2'b00;
#100;
// **************************************************************
// Test store
// **************************************************************
sw = 8'b01000000; // LEDS <- R[0] = 4
btn = 2'b01;
#40;
btn = 2'b00;
#100;
// **************************************************************
// Test move
sw = 8'b10010000; // R[1] <- R[0] = 4
btn = 2'b01;
#40;
btn = 2'b00;
#100;
// Test ALU operations.
// **************************************************************
// add
sw = 8'b11111000; // R[3] <- R[3] + R[2] = 1 + 2
btn = 2'b01;
#40;
btn = 2'b00;
#120;
// sub
sw = 8'b11000101; // R[0] <- R[0] - R[1] = 4 - 4
btn = 2'b01;
#40;
btn = 2'b00;
#120;
// and
sw = 8'b11101110; // R[2] <- R[2] & R[3] = 10 & 11 = 2
btn = 2'b01;
#40;
btn = 2'b00;
#120;
// not
sw = 8'b11010011; // R[1] <- ~R[1] = ~(0100) = 1011 = 11
btn = 2'b01;
#40;
btn = 2'b00;
#120;
// **************************************************************
// Test run mode
// **************************************************************
clr = 1'b1;
#30;
clr = 1'b0;
btn = 2'b10;
#30;
btn = 2'b00;
// **************************************************************
$display("Simulation has Ended.");
end
always
#20 clk <= ~clk;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_PP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR3_FUNCTIONAL_PP_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: txfifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module txfifo_packet_composer #(
parameter DATA_WIDTH=64,
parameter LOCAL_FIFO_DEPTH=256
) (
clock,
aclr,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
localparam FIFO_ADDR_WIDTH=log2(LOCAL_FIFO_DEPTH);
input clock;
input aclr;
input [DATA_WIDTH-1:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [DATA_WIDTH-1:0] q;
output [FIFO_ADDR_WIDTH-1:0] usedw;
wire [FIFO_ADDR_WIDTH-1:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [DATA_WIDTH-1:0] sub_wire3;
wire sub_wire4;
wire [FIFO_ADDR_WIDTH-1:0] usedw = sub_wire0[FIFO_ADDR_WIDTH-1:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [DATA_WIDTH-1:0] q = sub_wire3[DATA_WIDTH-1:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.aclr (aclr),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = LOCAL_FIFO_DEPTH/2,
scfifo_component.intended_device_family = "Stratix IV",
scfifo_component.lpm_numwords = LOCAL_FIFO_DEPTH,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = DATA_WIDTH,
scfifo_component.lpm_widthu = FIFO_ADDR_WIDTH,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
|
`define INIT 5'd0
`define LOAD_INST_1 5'd1
`define LOAD_INST_2 5'd2
`define DEC_INST 5'd3
`define FETCH_OP1_1 5'd4
`define FETCH_OP1_2 5'd5
`define FETCH_OP2_1 5'd6
`define FETCH_OP2_2 5'd7
`define FETCH_OP3_1 5'd8
`define FETCH_OP3_2 5'd9
// never load Z
`define LOAD_OP2_1 5'd10
`define LOAD_OP2_2 5'd11
`define LOAD_OP3_1 5'd12
`define LOAD_OP3_2 5'd13
`define COMPUTE 5'd14
`define STORE_1 5'd15
`define STORE_2 5'd16
`define NEXT 5'd17
module CPU (
input clk,
input W_RST,
input W_CLK,
input wire [31:0] W_DATA_I,
input W_ACK,
output wire [31:0] W_DATA_O,
output wire [31:0] W_ADDR,
output wire W_WRITE
);
reg [4:0] state;
reg [31:0] PC;
reg [31:0] command;
reg [31:0] op1, op2, st_op;
reg signed [31:0] reg_a, reg_b;
wire [31:0] reg_c;
reg skip;
reg [31:0] f_op1, f_op2, f_op3, f_store;
reg [31:0] f_data_i;
reg f_enable;
reg f_write_enable;
wire f_ack;
wire [31:0] f_data_o;
reg [1:0] thread;
reg [31:0] addr;
reg alu_carry;
wire alu_ocarry;
wire [31:0] alu_summ, alu_sub, alu_ashiftl, alu_ashiftr;
wire [31:0] alu_lshiftl, alu_lshiftr;
wire [31:0] alu_mult_h;
wire [31:0] alu_mult_l;
wire [31:0] alu_zand, alu_zor, alu_zxor, alu_znot;
wire [31:0] alu_revers;
ALU alu_module(
reg_a,
reg_b,
alu_carry,
alu_summ,
alu_ocarry,
alu_mult_h,
alu_mult_l,
alu_zand,
alu_zor,
alu_zxor,
alu_znot,
alu_sub,
alu_ashiftl,
alu_ashiftr,
alu_lshiftl,
alu_lshiftr,
alu_revers
);
FETCH fetch_module(
clk,
f_enable,
f_write_enable,
addr,
f_data_i,
thread,
f_data_o,
f_ack,
W_CLK,
W_ACK,
W_DATA_I,
W_DATA_O,
W_ADDR,
W_WRITE);
initial
begin
thread <= 2'b0;
end
always @(posedge clk)
begin
case (state)
`INIT:
begin
// check interrupts
state <= `LOAD_INST_1;
end
`LOAD_INST_1:
begin
state <= `LOAD_INST_2;
//
addr <= PC;
f_enable <= 1'b1;
f_write_enable <= 1'b0;
end
`LOAD_INST_2:
if (f_ack)
begin
state <= `DEC_INST;
f_enable <= 1'b0;
command <= f_data_o;
end
`DEC_INST:
begin
if (skip)
begin
PC <= PC + 32'd4;
state <= `INIT;
end
else
if (f_op1)
state <= `FETCH_OP1_1;
else
state <= `COMPUTE;
end
`FETCH_OP1_1:
begin
f_enable <= 1'b1;
addr <= PC + 32'h1;
state <= `FETCH_OP1_2;
end
`FETCH_OP1_2:
if (f_ack)
begin
f_enable <= 1'b0;
st_op <= f_data_o;
if (f_op2)
state <= `FETCH_OP2_1;
else
state <= `LOAD_OP2_1;
end
`FETCH_OP2_1:
begin
f_enable <= 1'b1;
addr <= PC + 32'h2;
state <= `FETCH_OP2_2;
end
`FETCH_OP2_2:
if (f_ack)
begin
f_enable <= 1'b0;
op1 <= f_data_o;
if (f_op3)
state <= `FETCH_OP3_1;
else
state <= `LOAD_OP2_1;
end
`FETCH_OP3_1:
begin
f_enable <= 1'b1;
addr <= PC + 32'h3;
state <= `FETCH_OP3_2;
end
`FETCH_OP3_2:
if (f_ack)
begin
f_enable <= 1'b0;
op2 <= f_data_o;
state <= `LOAD_OP2_1;
end
`LOAD_OP2_1:
begin
addr <= op1;
f_enable <= 1'b1;
state <= `LOAD_OP2_2;
end
`LOAD_OP2_2:
if (f_ack)
begin
f_enable <= 1'b1;
reg_a <= f_data_o;
if (f_op3)
state <= `LOAD_OP3_1;
else
state <= `COMPUTE;
end
`LOAD_OP3_1:
begin
state <= `LOAD_OP3_2;
end
`LOAD_OP3_2:
if (f_ack)
begin
f_enable <= 1'b0;
reg_b <= f_data_o;
state <= `COMPUTE;
end
`COMPUTE:
begin
if (f_store)
state <= `STORE_1;
else
state <= `NEXT;
end
`STORE_1:
begin
f_enable <= 1'b1;
f_write_enable <= 1'b1;
f_data_i <= reg_c;
state <= `STORE_2;
end
`STORE_2:
if (f_ack)
begin
f_enable <= 1'b0;
f_write_enable <= 1'b0;
state <= `NEXT;
end
`NEXT:
begin
state <= `INIT;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4B_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NAND4B_PP_SYMBOL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4B_PP_SYMBOL_V
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// main top-level module
module main(
clk_fpga, // clocks
clk_24mhz, //
clksel0, // clock selection
clksel1, //
warmres_n, // warm reset
d, // Z80 data bus
a, // Z80 address bus
iorq_n, // Z80 control signals
mreq_n, //
rd_n, //
wr_n, //
m1_n, //
int_n, //
nmi_n, //
busrq_n, //
busak_n, //
z80res_n, //
mema14, // memory control
mema15, //
mema16, //
mema17, //
mema18, //
ram0cs_n, //
ram1cs_n, //
ram2cs_n, //
ram3cs_n, //
romcs_n, //
memoe_n, //
memwe_n, //
zxid, // zxbus signals
zxa, //
zxa14, //
zxa15, //
zxiorq_n, //
zxmreq_n, //
zxrd_n, //
zxwr_n, //
zxcsrom_n, //
zxblkiorq_n, //
zxblkrom_n, //
zxgenwait_n, //
zxbusin, //
zxbusena_n, //
dac_bitck, // audio-DAC signals
dac_lrck, //
dac_dat, //
sd_clk, // SD card interface
sd_cs, //
sd_do, //
sd_di, //
sd_wp, //
sd_det, //
ma_clk, // control interface of MP3 chip
ma_cs,
ma_do,
ma_di,
mp3_xreset, // data interface of MP3 chip
mp3_req, //
mp3_clk, //
mp3_dat, //
mp3_sync, //
led_diag // LED driver
);
// input-output description
input clk_fpga;
input clk_24mhz;
output clksel0;
output clksel1;
input warmres_n;
inout reg [7:0] d;
input [15:0] a;
input iorq_n;
input mreq_n;
input rd_n;
input wr_n;
input m1_n;
output int_n;
output nmi_n;
output busrq_n;
input busak_n;
output reg z80res_n;
output mema14;
output mema15;
output mema16;
output mema17;
output mema18;
output ram0cs_n;
output ram1cs_n;
output ram2cs_n;
output ram3cs_n;
output romcs_n;
output memoe_n;
output memwe_n;
inout [7:0] zxid;
input [7:0] zxa;
input zxa14;
input zxa15;
input zxiorq_n;
input zxmreq_n;
input zxrd_n;
input zxwr_n;
input zxcsrom_n;
output zxblkiorq_n;
output zxblkrom_n;
output zxgenwait_n;
output zxbusin;
output zxbusena_n;
output dac_bitck;
output dac_lrck;
output dac_dat;
output sd_clk;
output sd_cs;
output sd_do;
input sd_di;
input sd_wp;
input sd_det;
output ma_clk;
output ma_cs;
output ma_do;
input ma_di;
output mp3_xreset;
input mp3_req;
output mp3_clk;
output mp3_dat;
output mp3_sync;
output led_diag;
// global signals
wire internal_reset_n; // internal reset for everything
// zxbus-ports interconnection
wire rst_from_zx_n; // internal z80 reset
wire [7:0] command_zx2gs;
wire [7:0] data_zx2gs;
wire [7:0] data_gs2zx;
wire command_bit_2gs;
wire command_bit_2zx;
wire command_bit_wr;
wire data_bit_2gs;
wire data_bit_2zx;
wire data_bit_wr;
// ports-memmap interconnection
wire mode_ramro,mode_norom;
wire [6:0] mode_pg0,mode_pg1;
// ports databus
wire [7:0] ports_dout;
wire ports_busin;
// ports-sound interconnection
wire snd_wrtoggle;
wire snd_datnvol;
wire [2:0] snd_addr;
wire [7:0] snd_data;
wire mode_8chans;
wire mode_pan4ch;
// ports-SPIs interconnection
wire [7:0] md_din;
wire [7:0] mc_din;
wire [7:0] mc_dout;
wire [7:0] sd_din;
wire [7:0] sd_dout;
wire mc_start;
wire [1:0] mc_speed;
wire mc_rdy;
wire md_start;
wire md_halfspeed;
wire sd_start;
// LED related
wire led_toggle;
// CODE STARTS
// reset handling
resetter my_rst( .clk(clk_fpga),
.rst_in1_n( warmres_n ), .rst_in2_n( rst_from_zx_n ),
.rst_out_n( internal_reset_n ) );
always @* // reset for Z80
begin
if( internal_reset_n == 1'b0 )
z80res_n <= 1'b0;
else
z80res_n <= 1'bZ;
end
// control Z80 data bus
always @*
begin
if( (!m1_n) && (!iorq_n) )
begin
d <= 8'hFF;
end
else
begin
if( ports_busin==1'b1 ) // FPGA inputs on data bus
d <= 8'bZZZZZZZZ;
else // FPGA outputs
d <= ports_dout;
end
end
// control /BUSRQ
assign busrq_n = 1'b1;
// ZXBUS module
zxbus my_zxbus( .cpu_clock(clk_fpga),
.rst_n(internal_reset_n),
.rst_from_zx_n(rst_from_zx_n),
.nmi_n(nmi_n),
.zxid(zxid),
.zxa(zxa),
.zxa14(zxa14),
.zxa15(zxa15),
.zxiorq_n(zxiorq_n),
.zxmreq_n(zxmreq_n),
.zxrd_n(zxrd_n),
.zxwr_n(zxwr_n),
.zxblkiorq_n(zxblkiorq_n),
.zxblkrom_n(zxblkrom_n),
.zxcsrom_n(zxcsrom_n),
.zxgenwait_n(zxgenwait_n),
.zxbusin(zxbusin),
.zxbusena_n(zxbusena_n),
.command_reg_out(command_zx2gs),
.data_reg_out(data_zx2gs),
.data_reg_in(data_gs2zx),
.command_bit(command_bit_2gs),
.command_bit_in(command_bit_2zx),
.command_bit_wr(command_bit_wr),
.data_bit(data_bit_2gs),
.data_bit_in(data_bit_2zx),
.data_bit_wr(data_bit_wr),
.led_toggle(led_toggle) );
// MEMMAP module
memmap my_memmap( .a14(a[14]),
.a15(a[15]),
.mreq_n(mreq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.mema14(mema14),
.mema15(mema15),
.mema16(mema16),
.mema17(mema17),
.mema18(mema18),
.ram0cs_n(ram0cs_n),
.ram1cs_n(ram1cs_n),
.ram2cs_n(ram2cs_n),
.ram3cs_n(ram3cs_n),
.romcs_n(romcs_n),
.memoe_n(memoe_n),
.memwe_n(memwe_n),
.mode_ramro(mode_ramro),
.mode_norom(mode_norom),
.mode_pg0(mode_pg0),
.mode_pg1(mode_pg1) );
// PORTS module
ports my_ports( .dout(ports_dout),
.din(d),
.busin(ports_busin),
.a(a),
.iorq_n(iorq_n),
.mreq_n(mreq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.rst_n(internal_reset_n),
.cpu_clock(clk_fpga),
.clksel0(clksel0),
.clksel1(clksel1),
.snd_wrtoggle(snd_wrtoggle),
.snd_datnvol(snd_datnvol),
.snd_addr(snd_addr),
.snd_data(snd_data),
.mode_8chans(mode_8chans),
.mode_pan4ch(mode_pan4ch),
.command_port_input(command_zx2gs),
.command_bit_input(command_bit_2gs),
.command_bit_output(command_bit_2zx),
.command_bit_wr(command_bit_wr),
.data_port_input(data_zx2gs),
.data_port_output(data_gs2zx),
.data_bit_input(data_bit_2gs),
.data_bit_output(data_bit_2zx),
.data_bit_wr(data_bit_wr),
.mode_ramro(mode_ramro),
.mode_norom(mode_norom),
.mode_pg0(mode_pg0),
.mode_pg1(mode_pg1),
.md_din(md_din),
.md_start(md_start),
.md_dreq(mp3_req),
.md_halfspeed(md_halfspeed),
.mc_ncs(ma_cs),
.mc_xrst(mp3_xreset),
.mc_dout(mc_dout),
.mc_din(mc_din),
.mc_start(mc_start),
.mc_speed(mc_speed),
.mc_rdy(mc_rdy),
.sd_ncs(sd_cs),
.sd_wp(sd_wp),
.sd_det(sd_det),
.sd_din(sd_din),
.sd_dout(sd_dout),
.sd_start(sd_start),
.led(led_diag),
.led_toggle(led_toggle)
);
// SOUND_MAIN module
sound_main my_sound_main( .clock(clk_24mhz),
.mode_8chans(mode_8chans),
.mode_pan4ch(mode_pan4ch),
.in_wrtoggle(snd_wrtoggle),
.in_datnvol(snd_datnvol),
.in_wraddr(snd_addr),
.in_data(snd_data),
.dac_clock(dac_bitck),
.dac_leftright(dac_lrck),
.dac_data(dac_dat) );
// INTERRUPTS module
interrupts my_interrupts( .clk_24mhz(clk_24mhz),
.clk_z80(clk_fpga),
.m1_n(m1_n),
.iorq_n(iorq_n),
.int_n(int_n) );
// MP3, SDcard spi modules
spi2 spi_mp3_data( .clock(clk_fpga),
.sck(mp3_clk),
.sdo(mp3_dat),
.bsync(mp3_sync),
.din(md_din),
.start(md_start),
.speed( {1'b0,md_halfspeed} ),
.sdi(1'b0) );
spi2 spi_mp3_control( .clock(clk_fpga),
.sck(ma_clk),
.sdo(ma_do),
.sdi(ma_di),
.din(mc_din),
.dout(mc_dout),
.start(mc_start),
.rdy(mc_rdy),
.speed(mc_speed) );
spi2 spi_sd( .clock(clk_fpga),
.sck(sd_clk),
.sdo(sd_do),
.sdi(sd_di),
.din(sd_din),
.dout(sd_dout),
.start(sd_start),
.speed(2'b00) );
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_com.v
// Version : 1.8
//--
//--------------------------------------------------------------------------------
`include "board_common.v"
module pci_exp_usrapp_com ();
/* Local variables */
reg [31:0] rx_file_ptr;
reg [7:0] frame_store_rx[5119:0];
integer frame_store_rx_idx;
reg [31:0] tx_file_ptr;
reg [7:0] frame_store_tx[5119:0];
integer frame_store_tx_idx;
reg [31:0] log_file_ptr;
integer _frame_store_idx;
event rcvd_cpld, rcvd_memrd, rcvd_memwr;
event rcvd_cpl, rcvd_memrd64, rcvd_memwr64;
event rcvd_msg, rcvd_msgd, rcvd_cfgrd0;
event rcvd_cfgwr0, rcvd_cfgrd1, rcvd_cfgwr1;
event rcvd_iord, rcvd_iowr;
initial begin
frame_store_rx_idx = 0;
frame_store_tx_idx = 0;
rx_file_ptr = $fopen("rx.dat");
if (!rx_file_ptr) begin
$write("ERROR: Could not open rx.dat.\n");
$finish;
end
tx_file_ptr = $fopen("tx.dat");
if (!tx_file_ptr) begin
$write("ERROR: Could not open tx.dat.\n");
$finish;
end
end
/************************************************************
Task : TSK_PARSE_FRAME
Inputs : None
Outputs : None
Description : Parse frame data
*************************************************************/
task TSK_PARSE_FRAME;
input log_file;
reg [1:0] fmt;
reg [4:0] f_type;
reg [2:0] traffic_class;
reg td;
reg ep;
reg [1:0] attr;
reg [9:0] length;
reg payload;
reg [15:0] requester_id;
reg [15:0] completer_id;
reg [7:0] tag;
reg [7:0] byte_enables;
reg [7:0] message_code;
reg [31:0] address_low;
reg [31:0] address_high;
reg [9:0] register_address;
reg [2:0] completion_status;
reg [31:0] _log_file_ptr;
integer _frame_store_idx;
begin
if (log_file == `RX_LOG)
_log_file_ptr = rx_file_ptr;
else
_log_file_ptr = tx_file_ptr;
if (log_file == `RX_LOG) begin
_frame_store_idx = frame_store_rx_idx;
frame_store_rx_idx = 0;
end else begin
_frame_store_idx = frame_store_tx_idx;
frame_store_tx_idx = 0;
end
if (log_file == `RX_LOG) begin
$display("[%t] : TSK_PARSE_FRAME on Receive", $realtime);
end
else begin
$display("[%t] : TSK_PARSE_FRAME on Transmit", $realtime);
end
TSK_DECIPHER_FRAME (fmt, f_type, traffic_class, td, ep, attr, length, log_file);
// decode the packets received based on fmt and f_type
casex({fmt, f_type})
`PCI_EXP_MEM_READ32 : begin
$fdisplay(_log_file_ptr, "[%t] : Memory Read-32 Frame \n", $time);
payload = 0;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_memrd;
end
`PCI_EXP_IO_READ : begin
$fdisplay(_log_file_ptr, "[%t] : IO Read Frame \n", $time);
payload = 0;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_iord;
end
`PCI_EXP_CFG_READ0 : begin
$fdisplay(_log_file_ptr, "[%t] : Config Read Type 0 Frame \n", $time);
payload = 0;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_cfgrd0;
end
`PCI_EXP_COMPLETION_WO_DATA: begin
$fdisplay(_log_file_ptr, "[%t] : Completion Without Data Frame \n", $time);
payload = 0;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_cpl;
end
`PCI_EXP_MEM_READ64: begin
$fdisplay(_log_file_ptr, "[%t] : Memory Read-64 Frame \n", $time);
payload = 0;
TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_memrd64;
end
`PCI_EXP_MSG_NODATA: begin
$fdisplay(_log_file_ptr, "[%t] : Message With No Data Frame \n", $time);
payload = 0;
TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_msg;
end
`PCI_EXP_MEM_WRITE32: begin
$fdisplay(_log_file_ptr, "[%t] : Memory Write-32 Frame \n", $time);
payload = 1;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_memwr;
end
`PCI_EXP_IO_WRITE: begin
$fdisplay(_log_file_ptr, "[%t] : IO Write Frame \n", $time);
payload = 1;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_iowr;
end
`PCI_EXP_CFG_WRITE0: begin
$fdisplay(_log_file_ptr, "[%t] : Config Write Type 0 Frame \n", $time);
payload = 1;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_cfgwr0;
end
`PCI_EXP_COMPLETION_DATA: begin
$fdisplay(_log_file_ptr, "[%t] : Completion With Data Frame \n", $time);
payload = 1;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_cpld;
end
`PCI_EXP_MEM_WRITE64: begin
$fdisplay(_log_file_ptr, "[%t] : Memory Write-64 Frame \n", $time);
payload = 1;
TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_memwr64;
end
`PCI_EXP_MSG_DATA: begin
$fdisplay(_log_file_ptr, "[%t] : Message With Data Frame \n", $time);
payload = 1;
TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_msgd;
end
default: begin
$fdisplay(_log_file_ptr, "[%t] : Not a valid frame \n", $time);
$display(_log_file_ptr, "[%t] : Received an invalid frame \n", $time);
$finish(2);
end
endcase
end
endtask // TSK_PARSE_FRAME
/************************************************************
Task : TSK_DECIPHER_FRAME
Inputs : None
Outputs : fmt, f_type, traffic_class, td, ep, attr, length
Description : Deciphers frame
*************************************************************/
task TSK_DECIPHER_FRAME;
output [1:0] fmt;
output [4:0] f_type;
output [2:0] traffic_class;
output td;
output ep;
output [1:0] attr;
output [9:0] length;
input txrx;
begin
fmt = (txrx ? frame_store_tx[0] : frame_store_rx[0]) >> 5;
f_type = txrx ? frame_store_tx[0] : frame_store_rx[0];
traffic_class = (txrx ? frame_store_tx[1] : frame_store_rx[1]) >> 4;
td = (txrx ? frame_store_tx[2] : frame_store_rx[2]) >> 7;
ep = (txrx ? frame_store_tx[2] : frame_store_rx[2]) >> 6;
attr = (txrx ? frame_store_tx[2] : frame_store_rx[2]) >> 4;
length = (txrx ? frame_store_tx[2] : frame_store_rx[2]);
length = (length << 8) | (txrx ? frame_store_tx[3] : frame_store_rx[3]);
end
endtask // TSK_DECIPHER_FRAME
/************************************************************
Task : TSK_3DW
Inputs : fmt, f_type, traffic_class, td, ep, attr, length,
payload, _frame_store_idx
Outputs : None
Description : Gets variables and prints frame
*************************************************************/
task TSK_3DW;
input [1:0] fmt;
input [4:0] f_type;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [9:0] length;
input payload;
input [31:0] _frame_store_idx;
input [31:0] _log_file_ptr;
input txrx;
reg [15:0] requester_id;
reg [7:0] tag;
reg [7:0] byte_enables;
reg [31:0] address_low;
reg [15:0] completer_id;
reg [9:0] register_address;
reg [2:0] completion_status;
reg [31:0] dword_data; // this will be used to recontruct bytes of data and sent to tx_app
integer _i;
begin
$fdisplay(_log_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(_log_file_ptr, "\t TD: %h", td);
$fdisplay(_log_file_ptr, "\t EP: %h", ep);
$fdisplay(_log_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(_log_file_ptr, "\t Length: 0x%h", length);
casex({fmt, f_type})
`PCI_EXP_CFG_READ0,
`PCI_EXP_CFG_WRITE0: begin
requester_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
tag = txrx ? frame_store_tx[6] : frame_store_rx[6];
byte_enables = txrx ? frame_store_tx[7] : frame_store_rx[7];
completer_id = {txrx ? frame_store_tx[8] : frame_store_rx[8], txrx ? frame_store_tx[9] : frame_store_rx[9]};
register_address = txrx ? frame_store_tx[10] : frame_store_rx[10];
register_address = (register_address << 8) | (txrx ? frame_store_tx[11] : frame_store_rx[11]);
$fdisplay(_log_file_ptr, "\t Requester Id: 0x%h", requester_id);
$fdisplay(_log_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(_log_file_ptr, "\t Last and First Byte Enables: 0x%h", byte_enables);
$fdisplay(_log_file_ptr, "\t Completer Id: 0x%h", completer_id);
$fdisplay(_log_file_ptr, "\t Register Address: 0x%h \n", register_address);
if (payload == 1) begin
for (_i = 12; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
end
end
end
`PCI_EXP_COMPLETION_WO_DATA,
`PCI_EXP_COMPLETION_DATA: begin
completer_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
completion_status = txrx ? (frame_store_tx[6] >> 5) : (frame_store_rx[6] >> 5);
requester_id = txrx ? {frame_store_tx[8], frame_store_tx[9]} : {frame_store_rx[8], frame_store_rx[9]};
tag = txrx ? frame_store_tx[10] : frame_store_rx[10];
$fdisplay(_log_file_ptr, "\t Completer Id: 0x%h", completer_id);
$fdisplay(_log_file_ptr, "\t Completion Status: 0x%h", completion_status);
$fdisplay(_log_file_ptr, "\t Requester Id: 0x%h ", requester_id);
$fdisplay(_log_file_ptr, "\t Tag: 0x%h \n", tag);
if (payload == 1) begin
dword_data = 32'h0000_0000;
for (_i = 12; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
if (!txrx) begin // if we are called from rx
dword_data = dword_data >> 8; // build a dword to send to tx app
dword_data = dword_data | {frame_store_rx[_i], 24'h00_0000};
end
end
`TX_TASKS.TSK_SET_READ_DATA(4'hf,dword_data); // send the data to the tx_app
end
end
// memory reads, io reads, memory writes and io writes
default: begin
requester_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
tag = txrx ? frame_store_tx[6] : frame_store_rx[6];
byte_enables = txrx ? frame_store_tx[7] : frame_store_rx[7];
address_low = txrx ? frame_store_tx[8] : frame_store_rx[8];
address_low = (address_low << 8) | (txrx ? frame_store_tx[9] : frame_store_rx[9]);
address_low = (address_low << 8) | (txrx ? frame_store_tx[10] : frame_store_rx[10]);
address_low = (address_low << 8) | (txrx ? frame_store_tx[11] : frame_store_rx[11]);
$fdisplay(_log_file_ptr, "\t Requester Id: 0x%h", requester_id);
$fdisplay(_log_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(_log_file_ptr, "\t Last and First Byte Enables: 0x%h", byte_enables);
$fdisplay(_log_file_ptr, "\t Address Low: 0x%h \n", address_low);
if (payload == 1) begin
for (_i = 12; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", (txrx ? frame_store_tx[_i] : frame_store_rx[_i]));
end
end
end
endcase
end
endtask // TSK_3DW
/************************************************************
Task : TSK_4DW
Inputs : fmt, f_type, traffic_class, td, ep, attr, length
payload, _frame_store_idx
Outputs : None
Description : Gets variables and prints frame
*************************************************************/
task TSK_4DW;
input [1:0] fmt;
input [4:0] f_type;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [9:0] length;
input payload;
input [31:0] _frame_store_idx;
input [31:0] _log_file_ptr;
input txrx;
reg [15:0] requester_id;
reg [7:0] tag;
reg [7:0] byte_enables;
reg [7:0] message_code;
reg [31:0] address_high;
reg [31:0] address_low;
reg [2:0] msg_type;
integer _i;
begin
$fdisplay(_log_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(_log_file_ptr, "\t TD: %h", td);
$fdisplay(_log_file_ptr, "\t EP: %h", ep);
$fdisplay(_log_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(_log_file_ptr, "\t Length: 0x%h", length);
requester_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
tag = txrx ? frame_store_tx[6] : frame_store_rx[6];
byte_enables = txrx ? frame_store_tx[7] : frame_store_rx[7];
message_code = txrx ? frame_store_tx[7] : frame_store_rx[7];
address_high = txrx ? frame_store_tx[8] : frame_store_rx[8];
address_high = (address_high << 8) | (txrx ? frame_store_tx[9] : frame_store_rx[9]);
address_high = (address_high << 8) | (txrx ? frame_store_tx[10] : frame_store_rx[10]);
address_high = (address_high << 8) | (txrx ? frame_store_tx[11] : frame_store_rx[11]);
address_low = txrx ? frame_store_tx[12] : frame_store_rx[12];
address_low = (address_low << 8) | (txrx ? frame_store_tx[13] : frame_store_rx[13]);
address_low = (address_low << 8) | (txrx ? frame_store_tx[14] : frame_store_rx[14]);
address_low = (address_low << 8) | (txrx ? frame_store_tx[15] : frame_store_rx[15]);
$fdisplay(_log_file_ptr, "\t Requester Id: 0x%h", requester_id);
$fdisplay(_log_file_ptr, "\t Tag: 0x%h", tag);
casex({fmt, f_type})
`PCI_EXP_MEM_READ64,
`PCI_EXP_MEM_WRITE64: begin
$fdisplay(_log_file_ptr, "\t Last and First Byte Enables: 0x%h", byte_enables);
$fdisplay(_log_file_ptr, "\t Address High: 0x%h", address_high);
$fdisplay(_log_file_ptr, "\t Address Low: 0x%h \n", address_low);
if (payload == 1) begin
for (_i = 16; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
end
end
end
`PCI_EXP_MSG_NODATA,
`PCI_EXP_MSG_DATA: begin
msg_type = f_type;
$fdisplay(_log_file_ptr, "\t Message Type: 0x%h", msg_type);
$fdisplay(_log_file_ptr, "\t Message Code: 0x%h", message_code);
$fdisplay(_log_file_ptr, "\t Address High: 0x%h", address_high);
$fdisplay(_log_file_ptr, "\t Address Low: 0x%h \n", address_low);
if (payload == 1) begin
for (_i = 16; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
end
end
end
endcase
end
endtask // TSK_4DW
/************************************************************
Task : TSK_READ_DATA
Inputs : None
Outputs : None
Description : Consume clocks.
*************************************************************/
task TSK_READ_DATA;
input last;
input txrx;
input [63:0] trn_d;
input [3:0] trn_rem;
integer _i;
reg [7:0] _byte;
reg [63:0] _msk;
reg [3:0] _rem;
begin
_msk = 64'hff00000000000000;
_rem = last ? ((trn_rem == 8'h0F) ? 4 : 8) : 8;
for (_i = 0; _i < _rem; _i = _i + 1) begin
_byte = (trn_d & (_msk >> (_i * 8))) >> (((7) - _i) * 8);
if (txrx) begin
board.RP.com_usrapp.frame_store_tx[board.RP.com_usrapp.frame_store_tx_idx] = _byte;
board.RP.com_usrapp.frame_store_tx_idx = board.RP.com_usrapp.frame_store_tx_idx + 1;
end else begin
board.RP.com_usrapp.frame_store_rx[board.RP.com_usrapp.frame_store_rx_idx] = _byte;
board.RP.com_usrapp.frame_store_rx_idx = board.RP.com_usrapp.frame_store_rx_idx + 1;
end
end
end
endtask // TSK_READ_DATA
/************************************************************
Task : TSK_READ_DATA_128
Inputs : None
Outputs : None
Description : Consume clocks.
*************************************************************/
task TSK_READ_DATA_128;
input first;
input last;
input txrx;
input [127:0] trn_d;
input [1:0] trn_rem;
integer _i;
reg [7:0] _byte;
reg [127:0] _msk;
reg [4:0] _rem;
reg [3:0] _strt_pos;
begin
_msk = (first && trn_rem[1]) ? 128'h0000000000000000ff00000000000000 : 128'hff000000000000000000000000000000;
_rem = first ? (last ? ((trn_rem == 2'b01) ? 12 : 16) : 8) : (last ? (trn_rem[1] ? (trn_rem[0] ? 4 : 8) : (trn_rem[0] ? 12 : 16)) : 16);
_strt_pos = (first && trn_rem[1]) ? 4'd7 : 4'd15;
for (_i = 0; _i < _rem; _i = _i + 1) begin
_byte = (trn_d & (_msk >> (_i * 8))) >> (((_strt_pos) - _i) * 8);
if (txrx) begin
board.RP.com_usrapp.frame_store_tx[board.RP.com_usrapp.frame_store_tx_idx] = _byte;
board.RP.com_usrapp.frame_store_tx_idx = board.RP.com_usrapp.frame_store_tx_idx + 1;
end else begin
board.RP.com_usrapp.frame_store_rx[board.RP.com_usrapp.frame_store_rx_idx] = _byte;
board.RP.com_usrapp.frame_store_rx_idx = board.RP.com_usrapp.frame_store_rx_idx + 1;
end
end
end
endtask // TSK_READ_DATA_128
`include "pci_exp_expect_tasks.v"
endmodule // pci_exp_usrapp_com
|
`timescale 1ns / 1ps
module top
(
// Inouts
inout [63:0] ddr3_dq,
inout [7:0] ddr3_dqs_n,
inout [7:0] ddr3_dqs_p,
// Outputs
output [13:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output ddr3_ck_p,
output ddr3_ck_n,
output ddr3_cke,
output ddr3_cs_n,
output [7:0] ddr3_dm,
output ddr3_odt,
// Inputs
// Differential system clocks
input sys_clk_p,
input sys_clk_n,
//output tg_compare_error,
//output init_calib_complete,
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
// Wire declarations
(* MARK_DEBUG="true" *) wire app_rdy;
(* MARK_DEBUG="true" *) wire app_wdf_rdy;
(* MARK_DEBUG="true" *) wire [511:0] app_rd_data;
(* MARK_DEBUG="true" *) wire app_rd_data_valid;
(* MARK_DEBUG="true" *) wire [27:0] app_addr;
(* MARK_DEBUG="true" *) wire [2:0] app_cmd;
(* MARK_DEBUG="true" *) wire app_en;
(* MARK_DEBUG="true" *) wire [511:0] app_wdf_data;
(* MARK_DEBUG="true" *) wire app_wdf_end;
// (* MARK_DEBUG="true" *) wire [63:0] app_wdf_mask;
(* MARK_DEBUG="true" *) wire app_wdf_wren;
(* MARK_DEBUG="true" *) wire init_calib_complete;
(* MARK_DEBUG="true" *) wire rst;
reg [27:0] app_addr_a;
reg [2:0] app_cmd_a;
reg app_en_a;
reg [511:0] app_wdf_data_a;
reg app_wdf_end_a;
// reg [63:0] app_wdf_mask_a;
reg app_wdf_wren_a;
parameter START = 4'b0001;
parameter SWRITE = 4'b0010;
parameter SREAD = 4'b0100;
parameter SSTOP = 4'b1000;
(* MARK_DEBUG="true" *) reg[3:0] cstate;
always @(posedge clk or posedge sys_rst)
begin
if(sys_rst) cstate <= START;
else begin
case(cstate)
START:begin
if(init_calib_complete)
begin
if((app_wdf_rdy)&&(!app_rdy))
begin
app_en_a <= 1'b1; app_cmd_a <= 3'b000;
cstate <= SWRITE;
end
end
else cstate <= START;
end
SWRITE: begin
if((app_rdy)&&(app_wdf_rdy))
begin
app_wdf_wren_a <= 1'b1; app_wdf_end_a <= 1'b1;
app_addr_a <= 7'h0000000;
app_wdf_data_a <= 128'h508050ff;
cstate <= SREAD;
end
else if((!app_rdy) && (app_wdf_rdy))
begin
app_wdf_wren_a <= 1'b0; app_wdf_end_a <= 1'b0;
cstate <= SWRITE;
end
else
cstate <= START;
end
SREAD: begin
if(app_rdy )
begin
app_en_a <= 1'b1; app_cmd_a <= 3'b001;
app_addr_a <= 7'h0000f00;
cstate <= SSTOP;
end
else cstate <= SREAD;
end
SSTOP: cstate <= START;
default: cstate <= START;
endcase
end
end
assign app_addr = app_addr_a;
assign app_cmd = app_cmd_a;
assign app_en = app_en_a;
assign app_wdf = app_wdf_data_a;
assign app_wdf_end = app_wdf_end_a;
//assign app_wdf_mask = app_wdf_mask_a;
assign app_wdf_wren = app_wdf_wren_a;
assign rst = sys_rst;
//---------- mig instance
mig_7series_0 u_mig_7series_0 (
// Memory interface ports
.ddr3_addr (ddr3_addr), // output [13:0] ddr3_addr
.ddr3_ba (ddr3_ba), // output [2:0] ddr3_ba
.ddr3_cas_n (ddr3_cas_n), // output ddr3_cas_n
.ddr3_ck_n (ddr3_ck_n), // output [0:0] ddr3_ck_n
.ddr3_ck_p (ddr3_ck_p), // output [0:0] ddr3_ck_p
.ddr3_cke (ddr3_cke), // output [0:0] ddr3_cke
.ddr3_ras_n (ddr3_ras_n), // output ddr3_ras_n
.ddr3_reset_n (ddr3_reset_n), // output ddr3_reset_n
.ddr3_we_n (ddr3_we_n), // output ddr3_we_n
.ddr3_dq (ddr3_dq), // inout [63:0] ddr3_dq
.ddr3_dqs_n (ddr3_dqs_n), // inout [7:0] ddr3_dqs_n
.ddr3_dqs_p (ddr3_dqs_p), // inout [7:0] ddr3_dqs_p
.init_calib_complete (init_calib_complete), // output init_calib_complete
.ddr3_cs_n (ddr3_cs_n), // output [0:0] ddr3_cs_n
.ddr3_dm (ddr3_dm), // output [7:0] ddr3_dm
.ddr3_odt (ddr3_odt), // output [0:0] ddr3_odt
// Application interface ports
.app_addr (app_addr), // input [27:0] app_addr
.app_cmd (app_cmd), // input [2:0] app_cmd
.app_en (app_en), // input app_en
.app_wdf_data (app_wdf_data), // input [511:0] app_wdf_data
.app_wdf_end (app_wdf_end), // input app_wdf_end
.app_wdf_wren (app_wdf_wren), // input app_wdf_wren
.app_rd_data (app_rd_data), // output [511:0] app_rd_data
.app_rd_data_valid (app_rd_data_valid),//output
.app_rd_data_end (), // output app_rd_data_end
.app_rdy (app_rdy), // output app_rdy
.app_wdf_rdy (app_wdf_rdy), // output app_wdf_rdy
.app_sr_req (1'b0), // input app_sr_req
.app_ref_req (1'b0), // input app_ref_req
.app_zq_req (1'b0), // input app_zq_req
.app_sr_active (), // output app_sr_active
.app_ref_ack (), // output app_ref_ack
.app_zq_ack (), // output app_zq_ack
.ui_clk (clk), // output ui_clk
.ui_clk_sync_rst (), // output ui_clk_sync_rst
.app_wdf_mask (16'h0000000000000000), // input [63:0] app_wdf_mask
// System Clock Ports
.sys_clk_p (sys_clk_p), // input sys_clk_p
.sys_clk_n (sys_clk_n), // input sys_clk_n
.sys_rst (sys_rst) // input sys_rst
);
endmodule
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
//Date : Wed Mar 23 16:49:14 2016
//Host : WK116 running 64-bit major release (build 9200)
//Command : generate_target PmodJSTK.bd
//Design : PmodJSTK
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module PmodJSTK
(AXI_LITE_SPI_araddr,
AXI_LITE_SPI_arready,
AXI_LITE_SPI_arvalid,
AXI_LITE_SPI_awaddr,
AXI_LITE_SPI_awready,
AXI_LITE_SPI_awvalid,
AXI_LITE_SPI_bready,
AXI_LITE_SPI_bresp,
AXI_LITE_SPI_bvalid,
AXI_LITE_SPI_rdata,
AXI_LITE_SPI_rready,
AXI_LITE_SPI_rresp,
AXI_LITE_SPI_rvalid,
AXI_LITE_SPI_wdata,
AXI_LITE_SPI_wready,
AXI_LITE_SPI_wstrb,
AXI_LITE_SPI_wvalid,
Pmod_out_pin10_i,
Pmod_out_pin10_o,
Pmod_out_pin10_t,
Pmod_out_pin1_i,
Pmod_out_pin1_o,
Pmod_out_pin1_t,
Pmod_out_pin2_i,
Pmod_out_pin2_o,
Pmod_out_pin2_t,
Pmod_out_pin3_i,
Pmod_out_pin3_o,
Pmod_out_pin3_t,
Pmod_out_pin4_i,
Pmod_out_pin4_o,
Pmod_out_pin4_t,
Pmod_out_pin7_i,
Pmod_out_pin7_o,
Pmod_out_pin7_t,
Pmod_out_pin8_i,
Pmod_out_pin8_o,
Pmod_out_pin8_t,
Pmod_out_pin9_i,
Pmod_out_pin9_o,
Pmod_out_pin9_t,
ext_spi_clk,
s_axi_aclk,
s_axi_aresetn);
input [6:0]AXI_LITE_SPI_araddr;
output AXI_LITE_SPI_arready;
input AXI_LITE_SPI_arvalid;
input [6:0]AXI_LITE_SPI_awaddr;
output AXI_LITE_SPI_awready;
input AXI_LITE_SPI_awvalid;
input AXI_LITE_SPI_bready;
output [1:0]AXI_LITE_SPI_bresp;
output AXI_LITE_SPI_bvalid;
output [31:0]AXI_LITE_SPI_rdata;
input AXI_LITE_SPI_rready;
output [1:0]AXI_LITE_SPI_rresp;
output AXI_LITE_SPI_rvalid;
input [31:0]AXI_LITE_SPI_wdata;
output AXI_LITE_SPI_wready;
input [3:0]AXI_LITE_SPI_wstrb;
input AXI_LITE_SPI_wvalid;
input Pmod_out_pin10_i;
output Pmod_out_pin10_o;
output Pmod_out_pin10_t;
input Pmod_out_pin1_i;
output Pmod_out_pin1_o;
output Pmod_out_pin1_t;
input Pmod_out_pin2_i;
output Pmod_out_pin2_o;
output Pmod_out_pin2_t;
input Pmod_out_pin3_i;
output Pmod_out_pin3_o;
output Pmod_out_pin3_t;
input Pmod_out_pin4_i;
output Pmod_out_pin4_o;
output Pmod_out_pin4_t;
input Pmod_out_pin7_i;
output Pmod_out_pin7_o;
output Pmod_out_pin7_t;
input Pmod_out_pin8_i;
output Pmod_out_pin8_o;
output Pmod_out_pin8_t;
input Pmod_out_pin9_i;
output Pmod_out_pin9_o;
output Pmod_out_pin9_t;
input ext_spi_clk;
input s_axi_aclk;
input s_axi_aresetn;
wire [6:0]AXI_LITE_1_ARADDR;
wire AXI_LITE_1_ARREADY;
wire AXI_LITE_1_ARVALID;
wire [6:0]AXI_LITE_1_AWADDR;
wire AXI_LITE_1_AWREADY;
wire AXI_LITE_1_AWVALID;
wire AXI_LITE_1_BREADY;
wire [1:0]AXI_LITE_1_BRESP;
wire AXI_LITE_1_BVALID;
wire [31:0]AXI_LITE_1_RDATA;
wire AXI_LITE_1_RREADY;
wire [1:0]AXI_LITE_1_RRESP;
wire AXI_LITE_1_RVALID;
wire [31:0]AXI_LITE_1_WDATA;
wire AXI_LITE_1_WREADY;
wire [3:0]AXI_LITE_1_WSTRB;
wire AXI_LITE_1_WVALID;
wire axi_quad_spi_0_SPI_0_IO0_I;
wire axi_quad_spi_0_SPI_0_IO0_O;
wire axi_quad_spi_0_SPI_0_IO0_T;
wire axi_quad_spi_0_SPI_0_IO1_I;
wire axi_quad_spi_0_SPI_0_IO1_O;
wire axi_quad_spi_0_SPI_0_IO1_T;
wire axi_quad_spi_0_SPI_0_SCK_I;
wire axi_quad_spi_0_SPI_0_SCK_O;
wire axi_quad_spi_0_SPI_0_SCK_T;
wire axi_quad_spi_0_SPI_0_SS_I;
wire [0:0]axi_quad_spi_0_SPI_0_SS_O;
wire axi_quad_spi_0_SPI_0_SS_T;
wire ext_spi_clk_1;
wire pmod_bridge_0_Pmod_out_PIN10_I;
wire pmod_bridge_0_Pmod_out_PIN10_O;
wire pmod_bridge_0_Pmod_out_PIN10_T;
wire pmod_bridge_0_Pmod_out_PIN1_I;
wire pmod_bridge_0_Pmod_out_PIN1_O;
wire pmod_bridge_0_Pmod_out_PIN1_T;
wire pmod_bridge_0_Pmod_out_PIN2_I;
wire pmod_bridge_0_Pmod_out_PIN2_O;
wire pmod_bridge_0_Pmod_out_PIN2_T;
wire pmod_bridge_0_Pmod_out_PIN3_I;
wire pmod_bridge_0_Pmod_out_PIN3_O;
wire pmod_bridge_0_Pmod_out_PIN3_T;
wire pmod_bridge_0_Pmod_out_PIN4_I;
wire pmod_bridge_0_Pmod_out_PIN4_O;
wire pmod_bridge_0_Pmod_out_PIN4_T;
wire pmod_bridge_0_Pmod_out_PIN7_I;
wire pmod_bridge_0_Pmod_out_PIN7_O;
wire pmod_bridge_0_Pmod_out_PIN7_T;
wire pmod_bridge_0_Pmod_out_PIN8_I;
wire pmod_bridge_0_Pmod_out_PIN8_O;
wire pmod_bridge_0_Pmod_out_PIN8_T;
wire pmod_bridge_0_Pmod_out_PIN9_I;
wire pmod_bridge_0_Pmod_out_PIN9_O;
wire pmod_bridge_0_Pmod_out_PIN9_T;
wire s_axi_aclk_1;
wire s_axi_aresetn_1;
assign AXI_LITE_1_ARADDR = AXI_LITE_SPI_araddr[6:0];
assign AXI_LITE_1_ARVALID = AXI_LITE_SPI_arvalid;
assign AXI_LITE_1_AWADDR = AXI_LITE_SPI_awaddr[6:0];
assign AXI_LITE_1_AWVALID = AXI_LITE_SPI_awvalid;
assign AXI_LITE_1_BREADY = AXI_LITE_SPI_bready;
assign AXI_LITE_1_RREADY = AXI_LITE_SPI_rready;
assign AXI_LITE_1_WDATA = AXI_LITE_SPI_wdata[31:0];
assign AXI_LITE_1_WSTRB = AXI_LITE_SPI_wstrb[3:0];
assign AXI_LITE_1_WVALID = AXI_LITE_SPI_wvalid;
assign AXI_LITE_SPI_arready = AXI_LITE_1_ARREADY;
assign AXI_LITE_SPI_awready = AXI_LITE_1_AWREADY;
assign AXI_LITE_SPI_bresp[1:0] = AXI_LITE_1_BRESP;
assign AXI_LITE_SPI_bvalid = AXI_LITE_1_BVALID;
assign AXI_LITE_SPI_rdata[31:0] = AXI_LITE_1_RDATA;
assign AXI_LITE_SPI_rresp[1:0] = AXI_LITE_1_RRESP;
assign AXI_LITE_SPI_rvalid = AXI_LITE_1_RVALID;
assign AXI_LITE_SPI_wready = AXI_LITE_1_WREADY;
assign Pmod_out_pin10_o = pmod_bridge_0_Pmod_out_PIN10_O;
assign Pmod_out_pin10_t = pmod_bridge_0_Pmod_out_PIN10_T;
assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
assign ext_spi_clk_1 = ext_spi_clk;
assign pmod_bridge_0_Pmod_out_PIN10_I = Pmod_out_pin10_i;
assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
assign s_axi_aclk_1 = s_axi_aclk;
assign s_axi_aresetn_1 = s_axi_aresetn;
PmodJSTK_axi_quad_spi_0_0 axi_quad_spi_0
(.ext_spi_clk(ext_spi_clk_1),
.io0_i(axi_quad_spi_0_SPI_0_IO0_I),
.io0_o(axi_quad_spi_0_SPI_0_IO0_O),
.io0_t(axi_quad_spi_0_SPI_0_IO0_T),
.io1_i(axi_quad_spi_0_SPI_0_IO1_I),
.io1_o(axi_quad_spi_0_SPI_0_IO1_O),
.io1_t(axi_quad_spi_0_SPI_0_IO1_T),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(AXI_LITE_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(AXI_LITE_1_ARREADY),
.s_axi_arvalid(AXI_LITE_1_ARVALID),
.s_axi_awaddr(AXI_LITE_1_AWADDR),
.s_axi_awready(AXI_LITE_1_AWREADY),
.s_axi_awvalid(AXI_LITE_1_AWVALID),
.s_axi_bready(AXI_LITE_1_BREADY),
.s_axi_bresp(AXI_LITE_1_BRESP),
.s_axi_bvalid(AXI_LITE_1_BVALID),
.s_axi_rdata(AXI_LITE_1_RDATA),
.s_axi_rready(AXI_LITE_1_RREADY),
.s_axi_rresp(AXI_LITE_1_RRESP),
.s_axi_rvalid(AXI_LITE_1_RVALID),
.s_axi_wdata(AXI_LITE_1_WDATA),
.s_axi_wready(AXI_LITE_1_WREADY),
.s_axi_wstrb(AXI_LITE_1_WSTRB),
.s_axi_wvalid(AXI_LITE_1_WVALID),
.sck_i(axi_quad_spi_0_SPI_0_SCK_I),
.sck_o(axi_quad_spi_0_SPI_0_SCK_O),
.sck_t(axi_quad_spi_0_SPI_0_SCK_T),
.ss_i(axi_quad_spi_0_SPI_0_SS_I),
.ss_o(axi_quad_spi_0_SPI_0_SS_O),
.ss_t(axi_quad_spi_0_SPI_0_SS_T));
PmodJSTK_pmod_bridge_0_0 pmod_bridge_0
(.in0_I(axi_quad_spi_0_SPI_0_SS_I),
.in0_O(axi_quad_spi_0_SPI_0_SS_O),
.in0_T(axi_quad_spi_0_SPI_0_SS_T),
.in1_I(axi_quad_spi_0_SPI_0_IO0_I),
.in1_O(axi_quad_spi_0_SPI_0_IO0_O),
.in1_T(axi_quad_spi_0_SPI_0_IO0_T),
.in2_I(axi_quad_spi_0_SPI_0_IO1_I),
.in2_O(axi_quad_spi_0_SPI_0_IO1_O),
.in2_T(axi_quad_spi_0_SPI_0_IO1_T),
.in3_I(axi_quad_spi_0_SPI_0_SCK_I),
.in3_O(axi_quad_spi_0_SPI_0_SCK_O),
.in3_T(axi_quad_spi_0_SPI_0_SCK_T),
.out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
.out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
.out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
.out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
.out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
.out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
.out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
.out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
.out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
.out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
.out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
.out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
.out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
.out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
.out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
.out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
.out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
.out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
.out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
.out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
.out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
.out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
.out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
.out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__XOR2_BEHAVIORAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR2_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311AI_TB_V
`define SKY130_FD_SC_MS__O311AI_TB_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o311ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__o311ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311AI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBEC_P_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__PROBEC_P_PP_BLACKBOX_V
/**
* probec_p: Virtual current probe point.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__probec_p (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBEC_P_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O211AI_PP_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_PP_BLACKBOX_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.2 *
* *
* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
* direct drop-in replacement. It should be used in all new Xilinx *
* designs. The core supports RAM and ROM functions over a wide range of *
* widths and depths. Use this core to generate block memories with *
* symmetric or asymmetric read and write port widths, as well as cores *
* which can perform simultaneous write operations to separate *
* locations, and simultaneous read operations from the same location. *
* For more information on differences in interface and feature support *
* between this core and the Dual Port Block Memory and Single Port *
* Block Memory LogiCOREs, please consult the data sheet. *
*******************************************************************************/
// Synthesized Netlist Wrapper
// This file is provided to wrap around the synthesized netlist (if appropriate)
// Interfaces:
// CLK.ACLK
// AXI4 Interconnect Clock Input
// RST.ARESETN
// AXI4 Interconnect Reset Input
// AXI_SLAVE_S_AXI
// AXI_SLAVE
// AXILite_SLAVE_S_AXI
// AXILite_SLAVE
// BRAM_PORTA
// BRAM_PORTA
// BRAM_PORTB
// BRAM_PORTB
module ram_16x1k_sp (
clka,
ena,
wea,
addra,
dina,
douta
);
input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
// WARNING: This file provides a module declaration only, it does not support
// direct instantiation. Please use an instantiation template (VEO) to
// instantiate the IP within a design.
endmodule
|
`timescale 1ns / 1ps
module test_ip_minimal;
// Inputs
reg eth_tx_clk;
reg eth_tx_ack;
reg eth_rx_clk;
reg [7:0] eth_rx_data;
reg eth_rx_data_valid;
reg eth_rx_frame_good;
reg eth_rx_frame_bad;
reg [15: 0] udp_tx_pending_data; //max 1472 byte
reg [7:0] udp_tx;
// Outputs
wire [7:0] eth_tx_data;
wire eth_tx_data_en;
wire [7:0] udp_rx;
wire udp_rx_dv;
wire udp_tx_rden;
// Instantiate the Unit Under Test (UUT)
ip_minimal uut (
.eth_tx_clk(eth_tx_clk),
.eth_tx_data(eth_tx_data),
.eth_tx_data_en(eth_tx_data_en),
.eth_tx_ack(eth_tx_ack),
.eth_rx_clk(eth_rx_clk),
.eth_rx_data(eth_rx_data),
.eth_rx_data_valid(eth_rx_data_valid),
.eth_rx_frame_good(eth_rx_frame_good),
.eth_rx_frame_bad(eth_rx_frame_bad),
.udp_rx(udp_rx),
.udp_rx_dv(udp_rx_dv),
.udp_tx_pending_data(udp_tx_pending_data),
.udp_tx(udp_tx),
.udp_tx_rden(udp_tx_rden)
);
initial begin
// Initialize Inputs
eth_tx_clk = 0;
eth_tx_ack = 0;
eth_rx_clk = 0;
eth_rx_data = 0;
eth_rx_data_valid = 0;
eth_rx_frame_good = 0;
eth_rx_frame_bad = 0;
udp_tx_pending_data = 0;
udp_tx = 0;
forever begin
#4 eth_tx_clk<=~eth_tx_clk;
#1 eth_rx_clk<=~eth_rx_clk;
end
end
reg [1:0] finish_cond = 0;
initial forever #100 if (&finish_cond) $finish();
reg eth_tx_data_en_r=0;
reg [4:0] ask_delay=0;
always @(posedge eth_tx_clk) begin
eth_tx_data_en_r<=eth_tx_data_en;
ask_delay<={ask_delay[3:0],({eth_tx_data_en_r,eth_tx_data_en}==2'b01)};
eth_tx_ack<=ask_delay[4];
end
parameter arp_ack_len = 42;
reg [7:0] arp_ack [arp_ack_len-1:0] ;
initial $readmemh ("pkg_arp_ack.hex", arp_ack) ;
parameter udp_null_len = 42;
reg [7:0] udp_null [udp_null_len-1:0];
initial $readmemh ("pkg_udp_null.hex", udp_null) ;
parameter udp_len = 50;
reg [7:0] udp [udp_len-1:0];
initial $readmemh ("pkg_udp.hex", udp) ;
reg [4:0] send_state = 0;
reg [4:0] send_state_next = 0;
reg [31:0] w = 100;
reg [9:0] pkg_pos = 0;
reg need_answer = 0;
always @(posedge eth_rx_clk) case (send_state)
0: if (w) w<=w-1; else send_state<=10;
2: begin
w<=4;
send_state<=3;
pkg_pos<=0;
end
3: begin
if (w) w <= w - 1;
else begin
send_state<=4;
eth_rx_frame_good<=1;
end
end
4: begin
send_state<=need_answer?5:6;
eth_rx_frame_good<=0;
end
5: if (eth_tx_data_en) send_state<=6;
6: if (!eth_tx_data_en) send_state<=send_state_next;
// Send ARP request
10: begin
eth_rx_data_valid<=1;
if (pkg_pos!=arp_ack_len) begin
pkg_pos<=pkg_pos+1;
eth_rx_data<=arp_ack[pkg_pos];
end else begin
eth_rx_data_valid<=0;
send_state<=2;
send_state_next<=11;
need_answer<=1;
end
end
// Send null UDP packet
11: begin
eth_rx_data_valid<=1;
if (pkg_pos!=udp_null_len) begin
pkg_pos<=pkg_pos+1;
eth_rx_data<=udp_null[pkg_pos];
end else begin
eth_rx_data_valid<=0;
send_state<=2;
send_state_next<=12;
need_answer<=0;
end
end
// Send short UDP packet
12: begin
eth_rx_data_valid<=1;
if (pkg_pos!=udp_len) begin
pkg_pos<=pkg_pos+1;
eth_rx_data<=udp[pkg_pos];
end else begin
eth_rx_data_valid<=0;
send_state<=2;
send_state_next<=14;
need_answer<=0;
end
end
14: begin
w <= 10;
send_state <= 15;
end
15: begin
if (w) w <= w - 1;
else begin
finish_cond[0] = 1;
send_state <= 10;
end
end
endcase
// UDP TX
reg [4:0] state_udp = 0;
integer udp_wait;
integer udp_pkt_size = 5;
always @(posedge eth_tx_clk) case (state_udp)
0: if (send_state == 11) // ARP request finished
state_udp <= 1;
1: begin
udp_tx_pending_data <= udp_pkt_size;
if (udp_tx_rden) state_udp <= 2;
udp_tx <= 8'hBB;
end
2: begin
udp_tx_pending_data <= udp_tx_pending_data - 1;
if (udp_tx_pending_data == 2) udp_tx <= 8'hEE;
else udp_tx <= 8'h88;
if (!udp_tx_rden) begin
state_udp <= 3;
udp_wait <= 100;
end
end
3: begin
if (udp_wait) udp_wait <= udp_wait - 1;
else begin
state_udp <= 1;
udp_pkt_size = udp_pkt_size * 6 / 5;
if (udp_pkt_size > 9000) finish_cond[1] = 1;
end
end
endcase
// --- PCAP output
integer t = 0;
initial forever #1 t <= t + 1;
integer pcap;
initial begin
pcap = $fopen("test.pcap", "wb");
$fwrite(pcap, "%u", 192'hA1B2C3D4_00040002_00000000_00000000_FFFF0000_00000001);
end
// TX
reg [8:0] tx_packet [9100:0];
integer tx_packet_len = 0;
integer tx_packet_readpos;
reg [1:0] eth_tx_pkt = 0;
always @(posedge eth_tx_data_en) begin
eth_tx_pkt <= 1;
tx_packet_len <= 0;
end
always @(posedge eth_tx_ack) begin
eth_tx_pkt <= eth_tx_pkt + 1;
end
always @(posedge eth_tx_clk)
if (eth_tx_data_en && eth_tx_pkt==2) begin
tx_packet[tx_packet_len] <= eth_tx_data;
tx_packet_len <= tx_packet_len + 1;
end
always @(negedge eth_tx_data_en)
if (eth_tx_pkt==2) begin
eth_tx_pkt <= 0;
$fwrite(pcap, "%u", {t, 32'h0, tx_packet_len, tx_packet_len});
for (tx_packet_readpos = 0; tx_packet_readpos < tx_packet_len; tx_packet_readpos = tx_packet_readpos + 1)
$fwrite(pcap, "%c", tx_packet[tx_packet_readpos]);
end
// RX
reg [8:0] rx_packet [9100:0];
integer rx_packet_len = 0;
integer rx_packet_readpos;
always @(posedge eth_rx_data_valid) begin
rx_packet_len <= 0;
end
always @(posedge eth_rx_clk)
if (eth_rx_data_valid) begin
rx_packet[rx_packet_len] <= eth_rx_data;
rx_packet_len <= rx_packet_len + 1;
end
always @(negedge eth_rx_data_valid) begin
if (rx_packet_len) begin
$fwrite(pcap, "%u", {t, 32'h0, rx_packet_len, rx_packet_len});
for (rx_packet_readpos = 0; rx_packet_readpos < rx_packet_len; rx_packet_readpos = rx_packet_readpos + 1)
$fwrite(pcap, "%c", rx_packet[rx_packet_readpos]);
end
end
// ---
endmodule
|
(***
*** Semi Pre-Orders
***)
Require Export Coq.Program.Basics.
Require Export Coq.Setoids.Setoid.
Require Export Coq.Classes.Morphisms.
Require Export Coq.Arith.Arith_base.
Require Export Coq.Relations.Relations.
Require Export Coq.Classes.RelationClasses.
Section SemiPreOrder.
Context {A:Type}.
(* Semi-reflexivity: reflexivity on the field of the relation *)
Class SemiReflexive (R : relation A) :=
{
semi_reflexivity_l : forall (x y : A), R x y -> R x x;
semi_reflexivity_r : forall (x y : A), R x y -> R y y
}.
Theorem semi_reflexivity `{SemiReflexive} (x y : A) : R x y \/ R y x -> R x x.
intro hypR; destruct hypR.
+ apply (semi_reflexivity_l _ y); assumption.
+ apply (semi_reflexivity_r y); assumption.
Qed.
(* A Semi-PreOrder is a pre-order just on the field of the relation *)
Class SemiPreOrder (R : relation A) : Prop :=
{
SemiPreOrder_SemiReflexive :> SemiReflexive R | 2 ;
SemiPreOrder_Transitive :> Transitive R | 2
}.
(* A PreOrder is always a Semi-PreOrder *)
Global Instance PreOrder_SemiPreOrder {R} `{@PreOrder A R} : SemiPreOrder R.
destruct H; constructor; [ | assumption ].
constructor; intros x y H1; reflexivity.
Qed.
(* A PER is always a Semi-PreOrder *)
Global Instance PER_SemiPreOrder {R} `{@PER A R} : SemiPreOrder R.
destruct H; constructor; [ | assumption ].
constructor; intros x y H1; [ transitivity y | transitivity x ];
try assumption; symmetry; assumption.
Qed.
(* Symmetric intersection: the intersection of a relation and its converse *)
Definition inter_sym (R:relation A) : relation A :=
fun x y => R x y /\ R y x.
(* The symmetric intersection of any relation is symmetric *)
Global Instance inter_sym_Symmetric {R} : Symmetric (inter_sym R).
intros x y H; destruct H; split; assumption.
Qed.
(* The symmetric intersection of any semi-preorder is a PER *)
Global Instance inter_sym_PER `{SemiPreOrder} : PER (inter_sym R).
Proof.
constructor.
+ auto with typeclass_instances.
+ intros x y z Rxy Ryz; destruct Rxy; destruct Ryz;
split; transitivity y; assumption.
Qed.
End SemiPreOrder.
(***
*** So-Called Logical Relations
***)
(* A "logical relation" is just a distinguished semi-preorder on a type *)
Class LR_Op (A:Type) : Type := lr_leq : relation A.
(* To be valid, a logical relation must actually be a semi-preorder *)
Class LR A `{R:LR_Op A} : Prop :=
{ lr_SemiPreOrder :> @SemiPreOrder A lr_leq }.
Notation "x '<~' y" := (lr_leq x y) (at level 80, no associativity).
(* Helper notation for using the PER associated with a logical relation *)
Definition lr_eq `{LR_Op} : relation A := inter_sym lr_leq.
Notation "x '~~' y" := (lr_eq x y) (at level 80, no associativity).
Instance le_eq_SemiPreOrder `{LR} : SemiPreOrder lr_eq.
Proof. apply PER_SemiPreOrder. Qed.
(***
*** Some tactics and Proper instances for logical relations
***)
(* Tactic to apply semi-reflexivity to goals x <~ x if there is an assumption
with the form x <~ y or y <~ x *)
Ltac assumption_semi_refl :=
match goal with
| |- Proper lr_leq _ => unfold Proper; assumption_semi_refl
| |- Proper lr_eq _ => unfold Proper; assumption_semi_refl
| H : ?x <~ ?y |- ?x <~ ?x => apply (semi_reflexivity_l _ _ H)
| H : ?y <~ ?x |- ?x <~ ?x => apply (semi_reflexivity_r _ _ H)
| H : Proper lr_leq ?x |- ?x <~ ?x => apply H
| H : ?x ~~ ?y |- ?x <~ ?x => destruct H; assumption_semi_refl
| H : ?y ~~ ?x |- ?x <~ ?x => destruct H; assumption_semi_refl
| H : ?x ~~ ?y |- ?x ~~ ?x => apply (semi_reflexivity_l _ _ H)
| H : ?y ~~ ?x |- ?x ~~ ?x => apply (semi_reflexivity_r _ _ H)
| H : Proper lr_leq ?x |- ?x ~~ ?x => split; apply H
| H : Proper lr_eq ?x |- ?x ~~ ?x => apply H
(*
| |- ?f ?z <~ ?f ?z =>
apply semi_reflexivity_apply_Proper_leq; semi_reflexivity
| |- ?f ?z ~~ ?f ?z =>
apply semi_reflexivity_apply_Proper_eq; semi_reflexivity
| |- ?R ?f ?f =>
change (Proper R f); eauto with typeclass_instances
*)
end.
(* Tactic to apply transitivity to goals x <~ z if there is an assumption with
the form x <~ y or y <~ z *)
Ltac apply_transitivity :=
lazymatch goal with
| H : ?x <~ ?y |- ?x <~ ?z => apply (transitivity H); try assumption
| H : ?y <~ ?z |- ?x <~ ?z => apply (transitivity (y:=?y)); try assumption
end.
(* Rewrite using an lr_leq or lr_eq assumption *)
Ltac rewrite_assumption :=
match goal with
| H : ?x <~ ?y |- ?u <~ ?v => rewrite <- H
| H : ?x ~~ ?y |- ?u ~~ ?v => rewrite H
end.
(* FIXME HERE: not sure if these Proper instances are needed... *)
Instance lr_leq_Proper `{LR} : Proper (flip lr_leq ==> lr_leq ==> impl) lr_leq.
Proof.
intros x1 y1 R1 x2 y2 R2 R12. rewrite <- R1. rewrite <- R2. assumption.
Qed.
Instance lr_leq_Proper_flip `{LR} : Proper (lr_leq ==> flip lr_leq ==> flip impl) lr_leq.
Proof.
intros x1 y1 R1 x2 y2 R2 R12. rewrite R1. rewrite R2. assumption.
Qed.
Instance lr_leq_Proper_proj1 `{LR} x : Proper (lr_leq ==> impl) (lr_leq x).
Proof.
intros y1 y2 Ry. rewrite Ry. reflexivity.
Qed.
Instance lr_leq_Proper_proj1_flip `{LR} x :
Proper (lr_leq --> flip impl) (lr_leq x).
Proof.
intros y1 y2 Ry. rewrite Ry. reflexivity.
Qed.
Instance lr_eq_Proper `{LR} : Proper (lr_eq ==> lr_eq ==> iff) lr_eq.
Proof.
intros x1 y1 R1 x2 y2 R2; split; intro Rx.
+ rewrite <- R1. rewrite <- R2. assumption.
+ rewrite R1. rewrite R2. assumption.
Qed.
(* FIXME HERE: not sure if these subrelations are used... *)
(* lr_eq is a sub-relation of lr_leq *)
Instance subrelation_lr_eq_lr_leq `{LR} : subrelation lr_eq lr_leq.
Proof.
intros x y Rxy; destruct Rxy; assumption.
Qed.
(* lr_eq is a sub-relation of the inverse of lr_leq *)
Instance subrelation_lr_eq_flip_lr_leq `{LR} : subrelation lr_eq (flip lr_leq).
Proof.
intros x y Rxy; destruct Rxy; assumption.
Qed.
(* FIXME HERE: not sure if these Proper lemmas are used... *)
(* Any function that is Proper w.r.t. (lr_leq ==> lr_leq) also Proper
w.r.t. (lr_eq ==> lr_eq) *)
Instance Proper_lr_leq_lr_eq_unary {A B} `{LR A} `{LR B} (f:A -> B)
`{P:Proper _ (lr_leq ==> lr_leq) f} : Proper (lr_eq ==> lr_eq) f.
Proof.
intros x y Rxy; destruct Rxy; split; apply P; assumption.
Qed.
(* Similar to the above, but for binary functions *)
Instance Proper_lr_leq_lr_eq_binary {A B C} `{LR A} `{LR B} `{LR C}
(f:A -> B -> C)
`{P:Proper _ (lr_leq ==> lr_leq ==> lr_leq) f} :
Proper (lr_eq ==> lr_eq ==> lr_eq) f.
Proof.
intros x1 y1 Rxy1 x2 y2 Rxy2; destruct Rxy1; destruct Rxy2;
split; apply P; assumption.
Qed.
(* Similar to the above, but for trinary functions *)
Instance Proper_lr_leq_lr_eq_trinary {A B C D} `{LR A} `{LR B} `{LR C} `{LR D}
(f:A -> B -> C -> D)
`{P:Proper _ (lr_leq ==> lr_leq ==> lr_leq ==> lr_leq) f} :
Proper (lr_eq ==> lr_eq ==> lr_eq ==> lr_eq) f.
Proof.
intros x1 y1 Rxy1 x2 y2 Rxy2 x3 y3 Rxy3;
destruct Rxy1; destruct Rxy2; destruct Rxy3;
split; apply P; assumption.
Qed.
(***
*** The Logical Relation for Functions
***)
(* The LR for functions is the pointwise relation on all the outputs, restricted
so to only relate proper functions *)
Record LRFun {A B} `{LR_Op A} `{LR_Op B} (f g : A -> B) : Prop :=
{
LRFun_Proper_l : Proper (lr_leq ==> lr_leq) f;
LRFun_Proper_r : Proper (lr_leq ==> lr_leq) g;
apply_lr_leq : forall x y, x <~ y -> f x <~ g y
}.
(* Make LRFun itself an instance of LR_Op *)
Instance LR_Op_fun {A B} `{LR_Op A} `{LR_Op B} : LR_Op (A -> B) := LRFun.
(* LR instance for functions *)
Instance LR_fun {A B} `{LR A} `{LR B} : LR (A -> B).
Proof.
constructor; constructor.
{ constructor; intros f g Rfg; destruct Rfg as [ Pf Pg Rfg ]; constructor;
intros x y Rxy; first [ apply Pf | apply Pg | apply Rfg ]; assumption. }
{ intros f g h Rfg Rgh; destruct Rfg as [ Pf Pg Rfg ];
destruct Rgh as [ Pg' Ph Rgh ]; constructor; intros x y Rxy.
- apply Pf; assumption.
- apply Ph; assumption.
- transitivity (g x).
+ apply Rfg; assumption_semi_refl.
+ apply Rgh; assumption. }
Qed.
(* LRFun itself is Proper w.r.t. subrelations in the second argument *)
Instance LRFun_Proper_subrelation {A B} `{LR_Op A} :
Proper (subrelation ==> subrelation) (@LR_Op_fun A B _).
Proof.
intros R1 R2 subR f g Rfg; destruct Rfg as [Pf Pg Rfg].
split; intros x y Rxy; apply subR;
first [ apply Pf | apply Pg | apply Rfg ]; assumption.
Qed.
(* Elimination principle for proving ~~ from functions *)
Lemma apply_lr_eq {A B} `{LR_Op A} `{LR_Op B} (f g : A -> B) :
f ~~ g -> forall x y, x ~~ y -> f x ~~ g y.
intros Rfg x y Rxy; destruct Rfg as [ Rfg1 Rfg2 ]; destruct Rxy; split;
[ apply Rfg1 | apply Rfg2 ]; assumption.
Qed.
(***
*** The Logical Relation for Pairs
***)
(* The LR for pairs is just the pointwise relation on the components *)
Record LRPair {A B} `{LR_Op A} `{LR_Op B} (p1 p2 : A * B) : Prop :=
{ LRPair_fst : fst p1 <~ fst p2;
LRPair_snd : snd p1 <~ snd p2
}.
(* Make LRPair itself an instance of LR_Op *)
Instance LR_Op_pair {A B} `{LR_Op A} `{LR_Op B} : LR_Op (A * B) := LRPair.
(* Prove the LR instance for LRPair *)
Instance LR_pair {A B} `{LR A} `{LR B} : LR (A * B).
Proof.
constructor; constructor.
{ constructor; intros p1 p2 R12; destruct R12; split; assumption_semi_refl. }
{ intros p1 p2 p3 R12 R23; destruct R12; destruct R23; split;
[ transitivity (fst p2) | transitivity (snd p2) ]; assumption. }
Qed.
(* LRPair itself is Proper w.r.t. subrelations *)
Instance LRPair_Proper_subrelation {A B} :
Proper (subrelation ==> subrelation ==> subrelation) (@LR_Op_pair A B).
Proof.
intros R1 R2 subR S1 S2 subS p1 p2 Rp; destruct Rp.
split; first [ apply subR | apply subS ]; assumption.
Qed.
(* fst is a Proper morphism *)
Instance Proper_LRPair_fst {A B} `{LR_Op A} `{LR_Op B} :
Proper lr_leq (fst : (A*B) -> A).
Proof.
split; intros p1 p2 Rp; destruct Rp; assumption.
Qed.
(* snd is a Proper morphism *)
Instance Proper_LRPair_snd {A B} `{LR_Op A} `{LR_Op B} :
Proper lr_leq (snd : (A*B) -> B).
Proof.
split; intros p1 p2 Rp; destruct Rp; assumption.
Qed.
(* pair is a Proper morphism *)
Instance Proper_LRPair_pair {A B} `{LR A} `{LR B} :
Proper lr_leq (pair : A -> B -> A*B).
Proof.
split; intros x1 y1 Rxy1; split; intros x2 y2 Rxy2; split; unfold fst, snd;
try assumption; try assumption_semi_refl.
Qed.
(* Eta rule for pairs *)
Lemma LRPair_eta {A B} `{LR A} `{LR B} (p : A*B) : p <~ p -> (fst p, snd p) ~~ p.
intro Rp; destruct p; split; assumption.
Qed.
Hint Rewrite @LRPair_eta : LR.
(***
*** Automation (which uses the LRs for functions and pairs)
***)
(* Helper tactic for prove_lr: proves f <~ g by the Build_LRFun constructor *)
Ltac build_lr_fun :=
let x := fresh "x" in
let y := fresh "y" in
let Rxy := fresh "Rxy" in
apply Build_LRFun; intros x y Rxy.
(* Tactic to prove things like (f x y) <~ (f' x' y') and (f x y) ~~ (f' x' y')
by reducing them to f <~ f', x <~ x', and y <~ y' (or similar with ~~ in place
of <~). This is similar to (and the code is adapted from) the f_equiv tactic
in Coq.Classes.Morphisms, except that we do not use rewriting or reflexivity
because lr_leq and lr_eq are not necessarily reflexive. *)
Ltac prove_lr :=
(* autorewrite with LR; *)
repeat (simpl; rewrite_strat (topdown (hints LR)));
match goal with
| |- (?f _) <~ (?g _) => apply apply_lr_leq; [ change (f <~ g) | ]; prove_lr
| |- (?f _) ~~ (?g _) => apply apply_lr_eq; prove_lr
| |- (fun _ => _) <~ _ => build_lr_fun; prove_lr
| |- _ <~ (fun _ => _) => build_lr_fun; prove_lr
| |- (fun _ => _) ~~ _ => split; build_lr_fun; prove_lr
| |- _ ~~ (fun _ => _) => split; build_lr_fun; prove_lr
| |- ?f <~ ?g =>
first [ change (Proper lr_leq f);
solve [ assumption | auto with typeclass_instances ]
| change (f <~ f); assumption_semi_refl
| assumption ]
| |- ?f ~~ ?g =>
first [ change (Proper lr_eq f);
solve [ assumption | auto with typeclass_instances ]
| split; change (Proper lr_leq f);
solve [ auto with typeclass_instances ]
| change (f ~~ f); assumption_semi_refl
| assumption ]
| |- Proper lr_leq _ => unfold Proper; prove_lr
| |- _ => first [ assumption | auto with typeclass_instances ]
end.
(* To prove a function is Proper w.r.t. lr_leq, we only need to prove it is
Proper w.r.t. (lr_leq ==> lr_leq). Note that we do *not* make this an Instance,
since this is only for use in the lr_prove_proper tactic, below. *)
Lemma fun_Proper_lr_leq {A B} `{LR A} `{LR B} (f: A -> B) :
Proper (lr_leq ==> lr_leq) f -> Proper lr_leq f.
intro Rf; constructor; assumption.
Qed.
(* Helper lemma for the lr_prove_proper tactic *)
Lemma fun_Proper_lr_leq_adjoint {A B C} `{LR A} `{LR B} `{LR C} (f: A -> B -> C) :
Proper (lr_leq ==> lr_leq) (fun p => let (x,y) := p : A*B in f x y) ->
Proper (lr_leq ==> lr_leq) f.
intros Pf x1 y1 Rxy1; constructor; intros x2 y2 Rxy2;
(lazymatch goal with
| |- f ?x1 ?x2 <~ f ?y1 ?y2 => apply (Pf (x1,x2) (y1,y2))
end); split; prove_lr.
Qed.
(* Helper lemma for the lr_prove_proper tactic *)
Lemma fun_Proper_arrow_pair_commute {A B C D} `{LR A} `{LR B} `{LR C} RD
(f: A * (B * C) -> D) :
Proper (lr_leq ==> RD) (fun (p:(A * B) * C) =>
match p with ((x,y),z) => f (x,(y,z)) end) ->
Proper (lr_leq ==> RD) f.
intros Pf p1 p2 Rp; destruct p1 as [ x1 p1 ]; destruct p1 as [ y1 z1 ];
destruct p2 as [ x2 p2 ]; destruct p2 as [ y2 z2 ];
destruct Rp as [ Rx Rp ]; destruct Rp.
apply (Pf (x1, y1, z1) (x2, y2, z2)).
repeat split; unfold fst, snd in * |- *; assumption.
Qed.
(* Helper lemma for the lr_prove_proper tactic *)
Lemma fun_Proper_arrow_adjoint {A B C} `{LR A} `{LR B} RC (f: A * B -> C) :
Proper (lr_leq ==> (lr_leq ==> RC)) (fun x y => f (x,y)) ->
Proper (lr_leq ==> RC) f.
intros Pf p1 p2 Rp; destruct p1; destruct p2; destruct Rp; apply Pf;
unfold fst, snd in * |- *; assumption.
Qed.
(* Tactic to prove Proper lr_leq f from Proper (lr_leq ==> ... ==> lr_leq) f *)
Ltac prove_lr_proper :=
lazymatch goal with
| |- Proper lr_leq ?f =>
first [ solve [ auto with typeclass_instances ]
| progress (apply fun_Proper_lr_leq); prove_lr_proper
| unfold Proper; prove_lr ]
| |- Proper (lr_leq ==> _) ?f =>
first [ apply fun_Proper_lr_leq_adjoint; prove_lr_proper
| apply fun_Proper_arrow_pair_commute; prove_lr_proper
| apply fun_Proper_arrow_adjoint; prove_lr_proper
| repeat (intro; intros); prove_lr ]
| |- _ => idtac
end.
(***
*** The Discrete Logical Relation
***)
(* The discrete LR for a type A, making every element of A related to itself and
nothing else; this is the same as Liebniz equality *)
Definition LRDiscrete {A} : relation A := eq.
(* LRDiscrete is a valid LR. Note that we do not make this an Instance, since we
do not want Coq using this unless we tell it to. *)
Lemma LR_LRDiscrete {A} : @LR A LRDiscrete.
repeat constructor.
intros x y z Rxy Ryz; transitivity y; assumption.
Qed.
(* In the discrete LR, everything is related to itself. Again, we do not make
this an Instance, so that Coq doesn't use it unless we tell it to. *)
Lemma Proper_LRDiscrete_any {A} (a:A) : Proper (lr_leq (LR_Op:= LRDiscrete)) a.
reflexivity.
Qed.
(* The LR for the unit type is the discrete one *)
Instance LR_Op_unit : LR_Op unit := LRDiscrete.
Instance LR_unit : LR unit := LR_LRDiscrete.
Instance Proper_LR_unit_tt : Proper lr_leq tt := Proper_LRDiscrete_any tt.
(* The LR for bool is also the discrete one *)
Instance LR_Op_bool : LR_Op bool := LRDiscrete.
Instance LR_bool : LR bool := LR_LRDiscrete.
Instance Proper_LR_bool_any b : Proper lr_leq b := Proper_LRDiscrete_any b.
(* We want prove_lr, below, to always replace pattern-matches, including if,
with applications of an elimination combinator that we prove once and for all is
Proper. This is the version of that for bool. *)
Definition elimBool {A} (b:bool) (x y:A) := if b then x else y.
Instance Proper_elimBool `{LR} : Proper lr_leq elimBool.
Proof.
unfold elimBool; prove_lr_proper. rewrite H0; destruct y; assumption.
Qed.
Lemma rewrite_if_elimBool `{LR} (b:bool) x y :
Proper lr_leq x -> Proper lr_leq y ->
(if b then x else y) ~~ elimBool b x y.
intros Px Py; destruct b; unfold elimBool; assumption_semi_refl.
Qed.
Hint Rewrite @rewrite_if_elimBool : LR.
(***
*** The Logical Relation for Prop
***)
(* P1 <~ P2 is defined as P1 -> P2 *)
Instance LR_Op_Prop : LR_Op Prop := impl.
Instance LR_Prop : LR Prop.
Proof.
constructor; apply @PreOrder_SemiPreOrder; constructor;
auto with typeclass_instances.
Qed.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21AI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O21AI_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21ai (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21AI_BLACKBOX_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* IP ethernet frame transmitter (IP frame in, Ethernet frame out, 64 bit datapath)
*/
module ip_eth_tx_64
(
input wire clk,
input wire rst,
/*
* IP frame input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [63:0] s_ip_payload_axis_tdata,
input wire [7:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [63:0] m_eth_payload_axis_tdata,
output wire [7:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_payload_early_termination
);
/*
IP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
payload length octets
This module receives an IP frame with header fields in parallel along with the
payload in an AXI stream, combines the header with the payload, passes through
the Ethernet headers, and transmits the complete Ethernet payload on an AXI
interface.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_HEADER = 3'd1,
STATE_WRITE_HEADER_LAST = 3'd2,
STATE_WRITE_PAYLOAD = 3'd3,
STATE_WRITE_PAYLOAD_LAST = 3'd4,
STATE_WAIT_LAST = 3'd5;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_ip_hdr;
reg store_last_word;
reg [5:0] hdr_ptr_reg = 6'd0, hdr_ptr_next;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg flush_save;
reg transfer_in_save;
reg [19:0] hdr_sum_temp;
reg [19:0] hdr_sum_reg = 20'd0, hdr_sum_next;
reg [63:0] last_word_data_reg = 64'd0;
reg [7:0] last_word_keep_reg = 8'd0;
reg [5:0] ip_dscp_reg = 6'd0;
reg [1:0] ip_ecn_reg = 2'd0;
reg [15:0] ip_length_reg = 16'd0;
reg [15:0] ip_identification_reg = 16'd0;
reg [2:0] ip_flags_reg = 3'd0;
reg [12:0] ip_fragment_offset_reg = 13'd0;
reg [7:0] ip_ttl_reg = 8'd0;
reg [7:0] ip_protocol_reg = 8'd0;
reg [31:0] ip_source_ip_reg = 32'd0;
reg [31:0] ip_dest_ip_reg = 32'd0;
reg s_ip_hdr_ready_reg = 1'b0, s_ip_hdr_ready_next;
reg s_ip_payload_axis_tready_reg = 1'b0, s_ip_payload_axis_tready_next;
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg busy_reg = 1'b0;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
reg [63:0] save_ip_payload_axis_tdata_reg = 64'd0;
reg [7:0] save_ip_payload_axis_tkeep_reg = 8'd0;
reg save_ip_payload_axis_tlast_reg = 1'b0;
reg save_ip_payload_axis_tuser_reg = 1'b0;
reg [63:0] shift_ip_payload_axis_tdata;
reg [7:0] shift_ip_payload_axis_tkeep;
reg shift_ip_payload_axis_tvalid;
reg shift_ip_payload_axis_tlast;
reg shift_ip_payload_axis_tuser;
reg shift_ip_payload_s_tready;
reg shift_ip_payload_extra_cycle_reg = 1'b0;
// internal datapath
reg [63:0] m_eth_payload_axis_tdata_int;
reg [7:0] m_eth_payload_axis_tkeep_int;
reg m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_ip_hdr_ready = s_ip_hdr_ready_reg;
assign s_ip_payload_axis_tready = s_ip_payload_axis_tready_reg;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign busy = busy_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
function [7:0] count2keep;
input [3:0] k;
case (k)
4'd0: count2keep = 8'b00000000;
4'd1: count2keep = 8'b00000001;
4'd2: count2keep = 8'b00000011;
4'd3: count2keep = 8'b00000111;
4'd4: count2keep = 8'b00001111;
4'd5: count2keep = 8'b00011111;
4'd6: count2keep = 8'b00111111;
4'd7: count2keep = 8'b01111111;
4'd8: count2keep = 8'b11111111;
endcase
endfunction
always @* begin
shift_ip_payload_axis_tdata[31:0] = save_ip_payload_axis_tdata_reg[63:32];
shift_ip_payload_axis_tkeep[3:0] = save_ip_payload_axis_tkeep_reg[7:4];
if (shift_ip_payload_extra_cycle_reg) begin
shift_ip_payload_axis_tdata[63:32] = 32'd0;
shift_ip_payload_axis_tkeep[7:4] = 4'd0;
shift_ip_payload_axis_tvalid = 1'b1;
shift_ip_payload_axis_tlast = save_ip_payload_axis_tlast_reg;
shift_ip_payload_axis_tuser = save_ip_payload_axis_tuser_reg;
shift_ip_payload_s_tready = flush_save;
end else begin
shift_ip_payload_axis_tdata[63:32] = s_ip_payload_axis_tdata[31:0];
shift_ip_payload_axis_tkeep[7:4] = s_ip_payload_axis_tkeep[3:0];
shift_ip_payload_axis_tvalid = s_ip_payload_axis_tvalid;
shift_ip_payload_axis_tlast = (s_ip_payload_axis_tlast && (s_ip_payload_axis_tkeep[7:4] == 0));
shift_ip_payload_axis_tuser = (s_ip_payload_axis_tuser && (s_ip_payload_axis_tkeep[7:4] == 0));
shift_ip_payload_s_tready = !(s_ip_payload_axis_tlast && s_ip_payload_axis_tvalid && transfer_in_save) && !save_ip_payload_axis_tlast_reg;
end
end
always @* begin
state_next = STATE_IDLE;
s_ip_hdr_ready_next = 1'b0;
s_ip_payload_axis_tready_next = 1'b0;
store_ip_hdr = 1'b0;
store_last_word = 1'b0;
flush_save = 1'b0;
transfer_in_save = 1'b0;
hdr_ptr_next = hdr_ptr_reg;
word_count_next = word_count_reg;
hdr_sum_temp = 20'd0;
hdr_sum_next = hdr_sum_reg;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
error_payload_early_termination_next = 1'b0;
m_eth_payload_axis_tdata_int = 1'b0;
m_eth_payload_axis_tkeep_int = 1'b0;
m_eth_payload_axis_tvalid_int = 1'b0;
m_eth_payload_axis_tlast_int = 1'b0;
m_eth_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
hdr_ptr_next = 6'd0;
flush_save = 1'b1;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
if (s_ip_hdr_ready && s_ip_hdr_valid) begin
store_ip_hdr = 1'b1;
hdr_sum_next = {4'd4, 4'd5, s_ip_dscp, s_ip_ecn} +
s_ip_length +
s_ip_identification +
{s_ip_flags, s_ip_fragment_offset} +
{s_ip_ttl, s_ip_protocol} +
s_ip_source_ip[31:16] +
s_ip_source_ip[15: 0] +
s_ip_dest_ip[31:16] +
s_ip_dest_ip[15: 0];
s_ip_hdr_ready_next = 1'b0;
m_eth_hdr_valid_next = 1'b1;
if (m_eth_payload_axis_tready_int_reg) begin
m_eth_payload_axis_tvalid_int = 1'b1;
m_eth_payload_axis_tdata_int[ 7: 0] = {4'd4, 4'd5}; // ip_version, ip_ihl
m_eth_payload_axis_tdata_int[15: 8] = {s_ip_dscp, s_ip_ecn};
m_eth_payload_axis_tdata_int[23:16] = s_ip_length[15: 8];
m_eth_payload_axis_tdata_int[31:24] = s_ip_length[ 7: 0];
m_eth_payload_axis_tdata_int[39:32] = s_ip_identification[15: 8];
m_eth_payload_axis_tdata_int[47:40] = s_ip_identification[ 7: 0];
m_eth_payload_axis_tdata_int[55:48] = {s_ip_flags, s_ip_fragment_offset[12: 8]};
m_eth_payload_axis_tdata_int[63:56] = s_ip_fragment_offset[ 7: 0];
m_eth_payload_axis_tkeep_int = 8'hff;
hdr_ptr_next = 6'd8;
end
state_next = STATE_WRITE_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_HEADER: begin
// write header
word_count_next = ip_length_reg - 5*4 + 4;
if (m_eth_payload_axis_tready_int_reg) begin
hdr_ptr_next = hdr_ptr_reg + 6'd8;
m_eth_payload_axis_tvalid_int = 1'b1;
state_next = STATE_WRITE_HEADER;
case (hdr_ptr_reg)
6'h00: begin
m_eth_payload_axis_tdata_int[ 7: 0] = {4'd4, 4'd5}; // ip_version, ip_ihl
m_eth_payload_axis_tdata_int[15: 8] = {ip_dscp_reg, ip_ecn_reg};
m_eth_payload_axis_tdata_int[23:16] = ip_length_reg[15: 8];
m_eth_payload_axis_tdata_int[31:24] = ip_length_reg[ 7: 0];
m_eth_payload_axis_tdata_int[39:32] = ip_identification_reg[15: 8];
m_eth_payload_axis_tdata_int[47:40] = ip_identification_reg[ 7: 0];
m_eth_payload_axis_tdata_int[55:48] = {ip_flags_reg, ip_fragment_offset_reg[12: 8]};
m_eth_payload_axis_tdata_int[63:56] = ip_fragment_offset_reg[ 7: 0];
m_eth_payload_axis_tkeep_int = 8'hff;
end
6'h08: begin
hdr_sum_temp = hdr_sum_reg[15:0] + hdr_sum_reg[19:16];
hdr_sum_temp = hdr_sum_temp[15:0] + hdr_sum_temp[16];
m_eth_payload_axis_tdata_int[ 7: 0] = ip_ttl_reg;
m_eth_payload_axis_tdata_int[15: 8] = ip_protocol_reg;
m_eth_payload_axis_tdata_int[23:16] = ~hdr_sum_temp[15: 8];
m_eth_payload_axis_tdata_int[31:24] = ~hdr_sum_temp[ 7: 0];
m_eth_payload_axis_tdata_int[39:32] = ip_source_ip_reg[31:24];
m_eth_payload_axis_tdata_int[47:40] = ip_source_ip_reg[23:16];
m_eth_payload_axis_tdata_int[55:48] = ip_source_ip_reg[15: 8];
m_eth_payload_axis_tdata_int[63:56] = ip_source_ip_reg[ 7: 0];
m_eth_payload_axis_tkeep_int = 8'hff;
s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early;
state_next = STATE_WRITE_HEADER_LAST;
end
endcase
end else begin
state_next = STATE_WRITE_HEADER;
end
end
STATE_WRITE_HEADER_LAST: begin
// last header word requires first payload word; process accordingly
s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early && shift_ip_payload_s_tready;
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
m_eth_payload_axis_tvalid_int = 1'b1;
transfer_in_save = 1'b1;
m_eth_payload_axis_tdata_int[ 7: 0] = ip_dest_ip_reg[31:24];
m_eth_payload_axis_tdata_int[15: 8] = ip_dest_ip_reg[23:16];
m_eth_payload_axis_tdata_int[23:16] = ip_dest_ip_reg[15: 8];
m_eth_payload_axis_tdata_int[31:24] = ip_dest_ip_reg[ 7: 0];
m_eth_payload_axis_tdata_int[39:32] = shift_ip_payload_axis_tdata[39:32];
m_eth_payload_axis_tdata_int[47:40] = shift_ip_payload_axis_tdata[47:40];
m_eth_payload_axis_tdata_int[55:48] = shift_ip_payload_axis_tdata[55:48];
m_eth_payload_axis_tdata_int[63:56] = shift_ip_payload_axis_tdata[63:56];
m_eth_payload_axis_tkeep_int = {shift_ip_payload_axis_tkeep[7:4], 4'hF};
m_eth_payload_axis_tlast_int = shift_ip_payload_axis_tlast;
m_eth_payload_axis_tuser_int = shift_ip_payload_axis_tuser;
word_count_next = word_count_reg - 16'd8;
if (keep2count(m_eth_payload_axis_tkeep_int) >= word_count_reg) begin
// have entire payload
m_eth_payload_axis_tkeep_int = count2keep(word_count_reg);
if (shift_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
store_last_word = 1'b1;
s_ip_payload_axis_tready_next = shift_ip_payload_s_tready;
m_eth_payload_axis_tvalid_int = 1'b0;
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
if (shift_ip_payload_axis_tlast) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
s_ip_payload_axis_tready_next = shift_ip_payload_s_tready;
m_eth_payload_axis_tuser_int = 1'b1;
state_next = STATE_WAIT_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
end else begin
state_next = STATE_WRITE_HEADER_LAST;
end
end
STATE_WRITE_PAYLOAD: begin
// write payload
s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early && shift_ip_payload_s_tready;
m_eth_payload_axis_tdata_int = shift_ip_payload_axis_tdata;
m_eth_payload_axis_tkeep_int = shift_ip_payload_axis_tkeep;
m_eth_payload_axis_tvalid_int = shift_ip_payload_axis_tvalid;
m_eth_payload_axis_tlast_int = shift_ip_payload_axis_tlast;
m_eth_payload_axis_tuser_int = shift_ip_payload_axis_tuser;
store_last_word = 1'b1;
if (m_eth_payload_axis_tready_int_reg && shift_ip_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd8;
transfer_in_save = 1'b1;
if (word_count_reg <= 8) begin
// have entire payload
m_eth_payload_axis_tkeep_int = count2keep(word_count_reg);
if (shift_ip_payload_axis_tlast) begin
if (keep2count(shift_ip_payload_axis_tkeep) < word_count_reg[4:0]) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_eth_payload_axis_tuser_int = 1'b1;
end
s_ip_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
m_eth_payload_axis_tvalid_int = 1'b0;
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
if (shift_ip_payload_axis_tlast) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_eth_payload_axis_tuser_int = 1'b1;
s_ip_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
STATE_WRITE_PAYLOAD_LAST: begin
// read and discard until end of frame
s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early && shift_ip_payload_s_tready;
m_eth_payload_axis_tdata_int = last_word_data_reg;
m_eth_payload_axis_tkeep_int = last_word_keep_reg;
m_eth_payload_axis_tvalid_int = shift_ip_payload_axis_tvalid && shift_ip_payload_axis_tlast;
m_eth_payload_axis_tlast_int = shift_ip_payload_axis_tlast;
m_eth_payload_axis_tuser_int = shift_ip_payload_axis_tuser;
if (m_eth_payload_axis_tready_int_reg && shift_ip_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// read and discard until end of frame
s_ip_payload_axis_tready_next = shift_ip_payload_s_tready;
if (shift_ip_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_ip_hdr_ready_reg <= 1'b0;
s_ip_payload_axis_tready_reg <= 1'b0;
m_eth_hdr_valid_reg <= 1'b0;
save_ip_payload_axis_tlast_reg <= 1'b0;
shift_ip_payload_extra_cycle_reg <= 1'b0;
busy_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_ip_hdr_ready_reg <= s_ip_hdr_ready_next;
s_ip_payload_axis_tready_reg <= s_ip_payload_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
busy_reg <= state_next != STATE_IDLE;
error_payload_early_termination_reg <= error_payload_early_termination_next;
if (flush_save) begin
save_ip_payload_axis_tlast_reg <= 1'b0;
shift_ip_payload_extra_cycle_reg <= 1'b0;
end else if (transfer_in_save) begin
save_ip_payload_axis_tlast_reg <= s_ip_payload_axis_tlast;
shift_ip_payload_extra_cycle_reg <= s_ip_payload_axis_tlast && (s_ip_payload_axis_tkeep[7:4] != 0);
end
end
hdr_ptr_reg <= hdr_ptr_next;
word_count_reg <= word_count_next;
hdr_sum_reg <= hdr_sum_next;
// datapath
if (store_ip_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
ip_dscp_reg <= s_ip_dscp;
ip_ecn_reg <= s_ip_ecn;
ip_length_reg <= s_ip_length;
ip_identification_reg <= s_ip_identification;
ip_flags_reg <= s_ip_flags;
ip_fragment_offset_reg <= s_ip_fragment_offset;
ip_ttl_reg <= s_ip_ttl;
ip_protocol_reg <= s_ip_protocol;
ip_source_ip_reg <= s_ip_source_ip;
ip_dest_ip_reg <= s_ip_dest_ip;
end
if (store_last_word) begin
last_word_data_reg <= m_eth_payload_axis_tdata_int;
last_word_keep_reg <= m_eth_payload_axis_tkeep_int;
end
if (transfer_in_save) begin
save_ip_payload_axis_tdata_reg <= s_ip_payload_axis_tdata;
save_ip_payload_axis_tkeep_reg <= s_ip_payload_axis_tkeep;
save_ip_payload_axis_tuser_reg <= s_ip_payload_axis_tuser;
end
end
// output datapath logic
reg [63:0] m_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0;
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg m_eth_payload_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_eth_payload_axis_tkeep_reg = 8'd0;
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg temp_m_eth_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_eth_payload_int_to_output;
reg store_eth_payload_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready | (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg | !m_eth_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_eth_payload_int_to_output = 1'b0;
store_eth_payload_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if (m_eth_payload_axis_tready | !m_eth_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_eth_payload_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_eth_payload_axis_tvalid_reg <= 1'b0;
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
end
// datapath
if (store_eth_payload_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_eth_payload_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
end
endmodule
|
module ARM_ALU(input wire [31:0] A,B,input wire[4:0] OP,input wire [3:0] FLAGS,output wire [31:0] Out,output wire [3:0] FLAGS_OUT, input wire S,ALU_OUT);
parameter HIGHZ = 32'hzzzzzzzz;
reg [31:0] buffer,_A,_B;
reg [3:0] FLAGS_buff;
/*
STATUS REGISTER FLAGS
WE FETCH INSTRUCTIONS 8BITS AT A TIME 8BIT DATAPATH
31. Negatice, N = (ADD)&&(A[31]==B[31])&&(A[31]!=OUT[31]) || (SUB)
30. Zero, Z = OUT == 0
29. Carry, C = CARRY
28. Overflow, V = OVERFLOW
END
*/
always @(A or B or OP)
begin
FLAGS_buff=4'h0;
_A=A;
_B=B;
casez(OP)
//AND, Out = A & B
//TST, perform an AND but dont transfer it to a register
5'b00000,5'b01000:
begin
buffer <= A & B ;
end
//EOR Logical Exclusive OR, Out= A XOR B
//TEQ, perform an EOR but dont transfer it to a register
5'b00001,5'b01001:buffer <= A ^ B ;
//Sub Substract, Out = A - B
//CMP, perform an SUB but dont transfer it to a register
5'b00010,5'b01010:
begin
_B = ~B+1;
{FLAGS_buff[1],buffer} <= _A + _B ;
end
//RSB, OUT = B - A
5'b00011:
begin
_A = ~A+1;
{FLAGS_buff[1],buffer} <= _B + _A;
end
//ADD, OUT = A + B
//CMN, perform an ADD but dont transfer it to a register
5'b00100,5'b01011:
begin
{FLAGS_buff[1],buffer} <= A + B ;
end
//ADC, OUT = A + B + C
5'b00101:{FLAGS_buff[1],buffer} <= A + B + FLAGS[1];
//SBC, OUT = A-B-(~C)
5'b00110:
begin
_B = ~B+1;
{FLAGS_buff[1],buffer} <= _A + _B - !FLAGS[1];
end
//RSC, OUT = B-A-(~C)
5'b00111:
begin
_A = ~A+1;
{FLAGS_buff[1],buffer} <= B + _A - !FLAGS[1];
end
//ORR, OUT = A or B
5'b01100:buffer <= A | B;
//BIC, OUT = A or not(B)
5'b01110:
begin
buffer <= A & ~B;
//$display("A=%3h,B=%3h,!B=%3h, A & B! =%3h",A,B,~B,A & ~B);
end
//MVN Rd := NOT shifter_operand (no first operand)
5'b01111:
begin
buffer <= ~ B;
//$display("B=%3h,~B=%3h",B,~B);
end
//BYPASS B
5'b10000:buffer <= B;
//add 4 A
5'b10001:buffer <= A + 4;
//BYPASS A
5'b10010,5'b01101:buffer <= A;
endcase
end
always@(*)
begin
FLAGS_buff[3] = buffer[31];
FLAGS_buff[2] = buffer == 32'h0;
FLAGS_buff[0] = _A[31] == _B[31] && _A[31] != buffer[31];
end
assign FLAGS_OUT = S ? FLAGS_buff : FLAGS;
assign Out = ALU_OUT ? buffer : HIGHZ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_TB_V
`define SKY130_FD_SC_LP__DFXTP_TB_V
/**
* dfxtp: Delay flop, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfxtp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__dfxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_TB_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 3
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_SWandHW_standalone_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "design_SWandHW_standalone_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=32,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=6,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=1,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg400}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_SWandHW_standalone_processing_system7_0_0 (
SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *)
input wire SDIO0_WP;
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY" *)
output wire S_AXI_HP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY" *)
output wire S_AXI_HP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BVALID" *)
output wire S_AXI_HP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RLAST" *)
output wire S_AXI_HP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RVALID" *)
output wire S_AXI_HP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WREADY" *)
output wire S_AXI_HP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BRESP" *)
output wire [1 : 0] S_AXI_HP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RRESP" *)
output wire [1 : 0] S_AXI_HP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BID" *)
output wire [5 : 0] S_AXI_HP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RID" *)
output wire [5 : 0] S_AXI_HP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RDATA" *)
output wire [31 : 0] S_AXI_HP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RCOUNT" *)
output wire [7 : 0] S_AXI_HP0_RCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WCOUNT" *)
output wire [7 : 0] S_AXI_HP0_WCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RACOUNT" *)
output wire [2 : 0] S_AXI_HP0_RACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WACOUNT" *)
output wire [5 : 0] S_AXI_HP0_WACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK" *)
input wire S_AXI_HP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID" *)
input wire S_AXI_HP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWVALID" *)
input wire S_AXI_HP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BREADY" *)
input wire S_AXI_HP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RDISSUECAPEN" *)
input wire S_AXI_HP0_RDISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RREADY" *)
input wire S_AXI_HP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WLAST" *)
input wire S_AXI_HP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WRISSUECAPEN" *)
input wire S_AXI_HP0_WRISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WVALID" *)
input wire S_AXI_HP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARBURST" *)
input wire [1 : 0] S_AXI_HP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLOCK" *)
input wire [1 : 0] S_AXI_HP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARSIZE" *)
input wire [2 : 0] S_AXI_HP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWBURST" *)
input wire [1 : 0] S_AXI_HP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLOCK" *)
input wire [1 : 0] S_AXI_HP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWSIZE" *)
input wire [2 : 0] S_AXI_HP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARPROT" *)
input wire [2 : 0] S_AXI_HP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWPROT" *)
input wire [2 : 0] S_AXI_HP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARADDR" *)
input wire [31 : 0] S_AXI_HP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWADDR" *)
input wire [31 : 0] S_AXI_HP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARCACHE" *)
input wire [3 : 0] S_AXI_HP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLEN" *)
input wire [3 : 0] S_AXI_HP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARQOS" *)
input wire [3 : 0] S_AXI_HP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWCACHE" *)
input wire [3 : 0] S_AXI_HP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLEN" *)
input wire [3 : 0] S_AXI_HP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWQOS" *)
input wire [3 : 0] S_AXI_HP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARID" *)
input wire [5 : 0] S_AXI_HP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWID" *)
input wire [5 : 0] S_AXI_HP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID" *)
input wire [5 : 0] S_AXI_HP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *)
input wire [31 : 0] S_AXI_HP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *)
input wire [3 : 0] S_AXI_HP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
input wire [5 : 0] IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(32),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(6),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg400")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(SDIO0_WP),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT),
.S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT),
.S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT),
.S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(IRQ_F2P),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
// MBT 11/9/2014
//
// 1 read-port, 1 write-port ram
//
// reads are asynchronous; we allow reading and writing of same address
//
`define bsg_mem_1r1w_macro(words,bits) \
if (els_p == words && width_p == bits) \
begin: macro \
wire [els_p-1:0] wa_one_hot = (w_v_i << w_addr_i); \
wire [els_p-1:0] ra_one_hot = (r_v_i << r_addr_i); \
\
bsg_rp_tsmc_250_rf_w``words``_b``bits``_1r1w w``words``_b``bits \
( .clock_i(w_clk_i) \
,.data_i(w_data_i) \
,.write_sel_one_hot_i(wa_one_hot) \
,.read_sel_one_hot_i (ra_one_hot) \
,.data_o(r_data_o) \
); \
end
module bsg_mem_1r1w #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=$clog2(els_p)
, parameter harden_p=1)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [width_p-1:0] r_data_o
);
`bsg_mem_1r1w_macro(32,16)
else `bsg_mem_1r1w_macro(32,2)
else `bsg_mem_1r1w_macro(32,8)
else `bsg_mem_1r1w_macro(16,62)
else `bsg_mem_1r1w_macro(4,32)
else `bsg_mem_1r1w_macro(4,61)
else `bsg_mem_1r1w_macro(4,62)
else `bsg_mem_1r1w_macro(4,64)
else `bsg_mem_1r1w_macro(4,66)
else `bsg_mem_1r1w_macro(4,68)
else `bsg_mem_1r1w_macro(2,1)
else `bsg_mem_1r1w_macro(2,2)
else `bsg_mem_1r1w_macro(2,3)
else `bsg_mem_1r1w_macro(2,4)
else `bsg_mem_1r1w_macro(2,5)
else `bsg_mem_1r1w_macro(2,6)
else `bsg_mem_1r1w_macro(2,7)
else `bsg_mem_1r1w_macro(2,8)
else `bsg_mem_1r1w_macro(2,9)
else `bsg_mem_1r1w_macro(2,10)
else `bsg_mem_1r1w_macro(2,11)
else `bsg_mem_1r1w_macro(2,12)
else `bsg_mem_1r1w_macro(2,13)
else `bsg_mem_1r1w_macro(2,14)
else `bsg_mem_1r1w_macro(2,15)
else `bsg_mem_1r1w_macro(2,16)
else `bsg_mem_1r1w_macro(2,17)
else `bsg_mem_1r1w_macro(2,18)
else `bsg_mem_1r1w_macro(2,19)
else `bsg_mem_1r1w_macro(2,20)
else `bsg_mem_1r1w_macro(2,21)
else `bsg_mem_1r1w_macro(2,22)
else `bsg_mem_1r1w_macro(2,23)
else `bsg_mem_1r1w_macro(2,24)
else `bsg_mem_1r1w_macro(2,25)
else `bsg_mem_1r1w_macro(2,26)
else `bsg_mem_1r1w_macro(2,27)
else `bsg_mem_1r1w_macro(2,28)
else `bsg_mem_1r1w_macro(2,29)
else `bsg_mem_1r1w_macro(2,30)
else `bsg_mem_1r1w_macro(2,31)
else `bsg_mem_1r1w_macro(2,32)
else `bsg_mem_1r1w_macro(2,33)
else `bsg_mem_1r1w_macro(2,34)
else `bsg_mem_1r1w_macro(2,35)
else `bsg_mem_1r1w_macro(2,36)
else `bsg_mem_1r1w_macro(2,37)
else `bsg_mem_1r1w_macro(2,38)
else `bsg_mem_1r1w_macro(2,39)
else `bsg_mem_1r1w_macro(2,40)
else `bsg_mem_1r1w_macro(2,41)
else `bsg_mem_1r1w_macro(2,42)
else `bsg_mem_1r1w_macro(2,43)
else `bsg_mem_1r1w_macro(2,44)
else `bsg_mem_1r1w_macro(2,45)
else `bsg_mem_1r1w_macro(2,46)
else `bsg_mem_1r1w_macro(2,47)
else `bsg_mem_1r1w_macro(2,48)
else `bsg_mem_1r1w_macro(2,49)
else `bsg_mem_1r1w_macro(2,50)
else `bsg_mem_1r1w_macro(2,51)
else `bsg_mem_1r1w_macro(2,52)
else `bsg_mem_1r1w_macro(2,53)
else `bsg_mem_1r1w_macro(2,54)
else `bsg_mem_1r1w_macro(2,55)
else `bsg_mem_1r1w_macro(2,56)
else `bsg_mem_1r1w_macro(2,57)
else `bsg_mem_1r1w_macro(2,58)
else `bsg_mem_1r1w_macro(2,59)
else `bsg_mem_1r1w_macro(2,60)
else `bsg_mem_1r1w_macro(2,61)
else `bsg_mem_1r1w_macro(2,62)
else `bsg_mem_1r1w_macro(2,63)
else `bsg_mem_1r1w_macro(2,64)
else `bsg_mem_1r1w_macro(2,65)
else `bsg_mem_1r1w_macro(2,66)
else `bsg_mem_1r1w_macro(2,67)
else `bsg_mem_1r1w_macro(2,68)
else `bsg_mem_1r1w_macro(2,69)
else `bsg_mem_1r1w_macro(2,70)
else `bsg_mem_1r1w_macro(2,71)
else `bsg_mem_1r1w_macro(2,72)
else `bsg_mem_1r1w_macro(2,73)
else `bsg_mem_1r1w_macro(2,74)
else `bsg_mem_1r1w_macro(2,75)
else `bsg_mem_1r1w_macro(2,76)
else `bsg_mem_1r1w_macro(2,77)
else `bsg_mem_1r1w_macro(2,78)
else `bsg_mem_1r1w_macro(2,79)
else `bsg_mem_1r1w_macro(2,80)
else `bsg_mem_1r1w_macro(2,81)
else `bsg_mem_1r1w_macro(2,82)
else `bsg_mem_1r1w_macro(2,83)
else `bsg_mem_1r1w_macro(2,84)
else `bsg_mem_1r1w_macro(2,85)
else `bsg_mem_1r1w_macro(2,86)
else `bsg_mem_1r1w_macro(2,87)
else `bsg_mem_1r1w_macro(2,88)
else `bsg_mem_1r1w_macro(2,89)
else `bsg_mem_1r1w_macro(8,8)
else begin : notmacro
bsg_mem_1r1w_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.*);
end
// synopsys translate_off
initial
begin
if (width_p*els_p >= 64)
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d (%m), harden_p=%d"
,width_p,els_p,read_write_same_addr_p,harden_p);
end
always_ff @(posedge w_clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address %x",w_addr_i);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w)
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
// Date : Thu Jul 24 13:45:39 2014
// Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim
// D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_1_funcsim.v
// Design : blk_mem_gen_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.1" *) (* CHECK_LICENSE_TYPE = "blk_mem_gen_1,blk_mem_gen_v8_2,{}" *)
(* core_generation_info = "blk_mem_gen_1,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.528025 mW}" *)
(* NotValidForBitStream *)
module blk_mem_gen_1
(clka,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
input [0:0]wea;
input [11:0]addra;
input [7:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) input enb;
input [9:0]addrb;
output [31:0]doutb;
wire [11:0]addra;
wire [9:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [31:0]doutb;
wire enb;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [7:0]NLW_U0_douta_UNCONNECTED;
wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "12" *)
(* C_ADDRB_WIDTH = "10" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "1" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 5.528025 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "1" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "blk_mem_gen_1.mem" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "1" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "4096" *)
(* C_READ_DEPTH_B = "1024" *)
(* C_READ_WIDTH_A = "8" *)
(* C_READ_WIDTH_B = "32" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "4096" *)
(* C_WRITE_DEPTH_B = "1024" *)
(* C_WRITE_MODE_A = "READ_FIRST" *)
(* C_WRITE_MODE_B = "READ_FIRST" *)
(* C_WRITE_WIDTH_A = "8" *)
(* C_WRITE_WIDTH_B = "32" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
blk_mem_gen_1blk_mem_gen_v8_2__parameterized0 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(NLW_U0_douta_UNCONNECTED[7:0]),
.doutb(doutb),
.eccpipece(1'b0),
.ena(1'b0),
.enb(enb),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rstb(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module blk_mem_gen_1blk_mem_gen_generic_cstr
(doutb,
wea,
clka,
enb,
clkb,
addra,
addrb,
dina);
output [31:0]doutb;
input [0:0]wea;
input clka;
input enb;
input clkb;
input [11:0]addra;
input [9:0]addrb;
input [7:0]dina;
wire [11:0]addra;
wire [9:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [31:0]doutb;
wire enb;
wire [0:0]wea;
blk_mem_gen_1blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.enb(enb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_1blk_mem_gen_prim_width
(doutb,
wea,
clka,
enb,
clkb,
addra,
addrb,
dina);
output [31:0]doutb;
input [0:0]wea;
input clka;
input enb;
input clkb;
input [11:0]addra;
input [9:0]addrb;
input [7:0]dina;
wire [11:0]addra;
wire [9:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [31:0]doutb;
wire enb;
wire [0:0]wea;
blk_mem_gen_1blk_mem_gen_prim_wrapper \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.enb(enb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module blk_mem_gen_1blk_mem_gen_prim_wrapper
(doutb,
wea,
clka,
enb,
clkb,
addra,
addrb,
dina);
output [31:0]doutb;
input [0:0]wea;
input clka;
input enb;
input clkb;
input [11:0]addra;
input [9:0]addrb;
input [7:0]dina;
wire [11:0]addra;
wire [9:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [31:0]doutb;
wire enb;
wire \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire \n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO(doutb),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,\n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,\n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,\n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(wea),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module blk_mem_gen_1blk_mem_gen_top
(doutb,
wea,
clka,
enb,
clkb,
addra,
addrb,
dina);
output [31:0]doutb;
input [0:0]wea;
input clka;
input enb;
input clkb;
input [11:0]addra;
input [9:0]addrb;
input [7:0]dina;
wire [11:0]addra;
wire [9:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [31:0]doutb;
wire enb;
wire [0:0]wea;
blk_mem_gen_1blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.enb(enb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) (* C_FAMILY = "zynq" *) (* C_XDEVICEFAMILY = "zynq" *)
(* C_ELABORATION_DIR = "./" *) (* C_INTERFACE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_SLAVE_TYPE = "0" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *) (* C_HAS_AXI_ID = "0" *) (* C_AXI_ID_WIDTH = "4" *)
(* C_MEM_TYPE = "1" *) (* C_BYTE_SIZE = "9" *) (* C_ALGORITHM = "1" *)
(* C_PRIM_TYPE = "1" *) (* C_LOAD_INIT_FILE = "0" *) (* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INIT_FILE = "blk_mem_gen_1.mem" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_DEFAULT_DATA = "0" *)
(* C_HAS_RSTA = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RSTRAM_A = "0" *)
(* C_INITA_VAL = "0" *) (* C_HAS_ENA = "0" *) (* C_HAS_REGCEA = "0" *)
(* C_USE_BYTE_WEA = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WRITE_MODE_A = "READ_FIRST" *)
(* C_WRITE_WIDTH_A = "8" *) (* C_READ_WIDTH_A = "8" *) (* C_WRITE_DEPTH_A = "4096" *)
(* C_READ_DEPTH_A = "4096" *) (* C_ADDRA_WIDTH = "12" *) (* C_HAS_RSTB = "0" *)
(* C_RST_PRIORITY_B = "CE" *) (* C_RSTRAM_B = "0" *) (* C_INITB_VAL = "0" *)
(* C_HAS_ENB = "1" *) (* C_HAS_REGCEB = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_WEB_WIDTH = "1" *) (* C_WRITE_MODE_B = "READ_FIRST" *) (* C_WRITE_WIDTH_B = "32" *)
(* C_READ_WIDTH_B = "32" *) (* C_WRITE_DEPTH_B = "1024" *) (* C_READ_DEPTH_B = "1024" *)
(* C_ADDRB_WIDTH = "10" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_ECC = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_HAS_INJECTERR = "0" *)
(* C_SIM_COLLISION_CHECK = "ALL" *) (* C_COMMON_CLK = "1" *) (* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_EN_SLEEP_PIN = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_COUNT_36K_BRAM = "1" *)
(* C_COUNT_18K_BRAM = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 5.528025 mW" *) (* downgradeipidentifiedwarnings = "yes" *)
module blk_mem_gen_1blk_mem_gen_v8_2__parameterized0
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [11:0]addra;
input [7:0]dina;
output [7:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [9:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [9:0]rdaddrecc;
input sleep;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [7:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [9:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [11:0]addra;
wire [9:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [31:0]dinb;
wire [31:0]doutb;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [7:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign douta[7] = \<const0> ;
assign douta[6] = \<const0> ;
assign douta[5] = \<const0> ;
assign douta[4] = \<const0> ;
assign douta[3] = \<const0> ;
assign douta[2] = \<const0> ;
assign douta[1] = \<const0> ;
assign douta[0] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
blk_mem_gen_1blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.enb(enb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module blk_mem_gen_1blk_mem_gen_v8_2_synth
(doutb,
wea,
clka,
enb,
clkb,
addra,
addrb,
dina);
output [31:0]doutb;
input [0:0]wea;
input clka;
input enb;
input clkb;
input [11:0]addra;
input [9:0]addrb;
input [7:0]dina;
wire [11:0]addra;
wire [9:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [31:0]doutb;
wire enb;
wire [0:0]wea;
blk_mem_gen_1blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.enb(enb),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
(** * MoreCoq: More About Coq *)
Require Export Poly.
(** This chapter introduces several more Coq tactics that,
together, allow us to prove many more theorems about the
functional programs we are writing. *)
(* ###################################################### *)
(** * The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n;o] = [n;p] ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with
"[rewrite -> eq2. reflexivity.]" as we have
done several times above. But we can achieve the
same effect in a single step by using the
[apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q;o] = [r;p]) ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
intros. apply H. apply H0. Qed.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl. symmetry.apply H.Qed.
(* Here we cannot use [apply] directly *)
(** In this case we can use the [symmetry] tactic, which switches the
left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will perform simplification first. *)
apply H. Qed.
(** **** Exercise: 3 stars (apply_exercise1) *)
(** Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
(* FILL IN HERE *)
intros.
symmetry.
rewrite H.
apply rev_involutive.
Qed.
(** **** Exercise: 1 star, optional (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
(* FILL IN HERE *)
*)
(** [] *)
(* ###################################################### *)
(** * The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall (X:Type) (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c;d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: [apply trans_eq with [c,d]]. *)
(** **** Exercise: 3 stars, optional (apply_with_exercise) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
intros.
apply trans_eq with m.
apply H0. apply H. Qed.
(* ###################################################### *)
(** * The [inversion] tactic *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic called [inversion] that allows us to exploit
these principles in proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros.
inversion H.
reflexivity.Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n;m] = [o;o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
intros.
inversion H.
rewrite <- H2.
inversion H0.
reflexivity.
Qed.
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
intros.
inversion H0.
rewrite <- H2.
inversion H.
Qed.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication is an instance of a more general fact about
constructors and functions, which we will often find useful: *)
Theorem f_equal : forall (A B : Type) (f: A -> B) (x y: A),
x = y -> f x = f y.
Proof. intros A B f x y eq. rewrite eq. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (practice) *)
(** A couple more nontrivial but not-too-complicated proofs to work
together in class, or for you to work as exercises. *)
Theorem beq_nat_0_l : forall n,
beq_nat 0 n = true -> n = 0.
Proof.
intros.
destruct n.
reflexivity.
inversion H.
Qed.
Theorem beq_nat_0_r : forall n,
beq_nat n 0 = true -> n = 0.
Proof.
intros.
destruct n.
reflexivity.
inversion H.
Qed.
(* ###################################################### *)
(** * Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros.
simpl in H.
apply H.
Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros.
symmetry in H0.
apply H in H0.
rewrite H0.
reflexivity.
Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars (plus_n_n_injective) *)
(** Practice using "in" variants in this exercise. *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n. induction n as [| n'].
intros.
simpl in H.
symmetry in H.
destruct m.
reflexivity.
inversion H.
intros.
destruct m.
inversion H.
simpl in H.
inversion H.
rewrite <- plus_n_Sm in H1.
rewrite <- plus_n_Sm in H1.
inversion H1.
apply IHn' in H2.
rewrite H2.
reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** * Varying the Induction Hypothesis *)
(** Sometimes it is important to control the exact form of the
induction hypothesis when carrying out inductive proofs in Coq.
In particular, we need to be careful about which of the
assumptions we move (using [intros]) from the goal to the context
before invoking the [induction] tactic. For example, suppose
we want to show that the [double] function is injective -- i.e.,
that it always maps different arguments to different results:
Theorem double_injective: forall n m, double n = double m -> n = m.
The way we _start_ this proof is a little bit delicate: if we
begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'". apply f_equal.
(* Here we are stuck. The induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the goal is not provable. *)
Abort.
(** What went wrong? *)
(** The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context --
intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we know
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.) *)
(** To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for _every_ [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O".
(* The 0 case is trivial *)
inversion eq.
SCase "m = S m'".
apply f_equal.
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
apply IHn'. inversion eq. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** The proof of this theorem (left as an exercise) has to be treated similarly: *)
(** **** Exercise: 2 stars (beq_nat_true) *)
Theorem beq_nat_true : forall n m,
beq_nat n m = true -> n = m.
Proof.
intros n.
induction n.
intros.
destruct m.
Case "m = O". reflexivity.
Case "m = S m". apply beq_nat_0_l in H. symmetry. apply H.
intros.
destruct m.
Case "m = 0". apply beq_nat_0_r in H. apply H.
Case "m = S m". simpl in H. apply IHn in H. rewrite H. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (beq_nat_true_informal) *)
(** Give a careful informal proof of [beq_nat_true], being as explicit
as possible about quantifiers. *)
(* FILL IN HERE *)
(** [] *)
(** The strategy of doing fewer [intros] before an [induction] doesn't
always work directly; sometimes a little _rearrangement_ of
quantified variables is needed. Suppose, for example, that we
wanted to prove [double_injective] by induction on [m] instead of
[n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
(* Stuck again here, just like before. *)
Abort.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
apply IHm'. inversion eq. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [double n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** Here's another illustration of [inversion] and using an
appropriately general induction hypothesis. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
Case "l = []".
intros n eq. rewrite <- eq. reflexivity.
Case "l = v' :: l'".
intros n eq. simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. apply IHl'. inversion eq. reflexivity. Qed.
(** It might be tempting to start proving the above theorem
by introducing [n] and [eq] at the outset. However, this leads
to an induction hypothesis that is not strong enough. Compare
the above to the following (aborted) attempt: *)
Theorem length_snoc_bad : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l n eq. induction l as [| v' l'].
Case "l = []".
rewrite <- eq. reflexivity.
Case "l = v' :: l'".
simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. Abort. (* apply IHl'. *) (* The IH doesn't apply! *)
(** As in the double examples, the problem is that by
introducing [n] before doing induction on [l], the induction
hypothesis is specialized to one particular natural number, namely
[n]. In the induction case, however, we need to be able to use
the induction hypothesis on some other natural number [n'].
Retaining the more general form of the induction hypothesis thus
gives us more flexibility.
In general, a good rule of thumb is to make the induction hypothesis
as general as possible. *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index n l = None.
Proof.
intros n X l.
generalize dependent n.
induction l.
Case "l = []". intros.
simpl. reflexivity.
Case "l = x::l". intros.
destruct n.
inversion H.
simpl in H.
inversion H.
apply IHl in H1.
rewrite H.
simpl.
apply H1.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index n l = None].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_more) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
intros n X v l.
generalize dependent n.
induction l.
intros.
simpl.
simpl in H.
rewrite <- H.
reflexivity.
intros.
simpl.
destruct n.
inversion H.
inversion H.
rewrite H1.
apply IHl in H1.
rewrite H1.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
intros X l1.
induction l1.
intros.
simpl.
simpl in H.
apply H.
simpl.
intros.
destruct n.
inversion H.
inversion H.
apply IHl1 in H1.
rewrite H.
rewrite H1.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
intros X n l.
generalize dependent n.
induction l.
Case "l = []".
intros.
simpl.
inversion H.
simpl.
reflexivity.
Case "l = x :: l".
intros n.
destruct n.
SCase "n = 0".
simpl. intros.
inversion H.
SCase "n = S n".
intros.
inversion H.
apply IHl in H1.
rewrite <- plus_n_Sm.
simpl. Admitted. (* TODO *)
(** **** Exercise: 3 stars, optional (double_induction) *)
(** Prove the following principle of induction over two naturals. *)
Theorem double_induction: forall (P : nat -> nat -> Prop),
P 0 0 ->
(forall m, P m 0 -> P (S m) 0) ->
(forall n, P 0 n -> P 0 (S n)) ->
(forall m n, P m n -> P (S m) (S n)) ->
forall m n, P m n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false". destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity. Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases.
In general, the [destruct] tactic can be used to perform case
analysis of the results of arbitrary computations. If [e] is an
expression whose type is some inductively defined type [T], then,
for each constructor [c] of [T], [destruct e] generates a subgoal
in which all occurrences of [e] (in the goal and in the context)
are replaced by [c].
*)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (combine_split) *)
(** Complete the proof below *)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Sometimes, doing a [destruct] on a compound expression (a
non-variable) will erase information we need to complete a proof. *)
(** For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Abort.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep some
memory of this expression and how it was destructed, because we
need to be able to reason that since, in this branch of the case
analysis, [beq_nat n 3 = true], it must be that [n = 3], from
which it follows that [n] is odd.
What we would really like is to substitute away all existing
occurences of [beq_nat n 3], but at the same time add an equation
to the context that records which case we are in. The [eqn:]
qualifier allows us to introduce such an equation (with whatever
name we choose). *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3) eqn:Heqe3.
(* Now we have the same state as at the point where we got stuck
above, except that the context contains an extra equality
assumption, which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_true in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the body of the
function we are reasoning about, we can use [eqn:] again in the
same way, allow us to finish the proof. *)
destruct (beq_nat n 5) eqn:Heqe5.
SCase "e5 = true".
apply beq_nat_true in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (destruct_eqn_practice) *)
Theorem bool_fn_applied_thrice :
forall (f : bool -> bool) (b : bool),
f (f (f b)) = f b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics. We'll
introduce a few more as we go along through the coming lectures,
and later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [destruct... eqn:...]:
specify the name of an equation to be added to the context,
recording the result of the case analysis
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
- [generalize dependent x]:
move the variable [x] (and anything else that depends on it)
from the context back to an explicit hypothesis in the goal
formula
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (beq_nat_sym) *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (beq_nat_sym_informal) *)
(** Give an informal proof of this lemma that corresponds to your
formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (beq_nat_trans) *)
Theorem beq_nat_trans : forall n m p,
beq_nat n m = true ->
beq_nat m p = true ->
beq_nat n p = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (split_combine) *)
(** We have just proven that for all lists of pairs, [combine] is the
inverse of [split]. How would you formalize the statement that
[split] is the inverse of [combine]?
Complete the definition of [split_combine_statement] below with a
property that states that [split] is the inverse of
[combine]. Then, prove that the property holds. (Be sure to leave
your induction hypothesis general by not doing [intros] on more
things than necessary. Hint: what property do you need of [l1]
and [l2] for [split] [combine l1 l2 = (l1,l2)] to be true?) *)
Definition split_combine_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem split_combine : split_combine_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (override_permute) *)
Theorem override_permute : forall (X:Type) x1 x2 k1 k2 k3 (f : nat->X),
beq_nat k2 k1 = false ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (filter_exercise) *)
(** This one is a bit challenging. Pay attention to the form of your IH. *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (forall_exists_challenge) *)
(** Define two recursive [Fixpoints], [forallb] and [existsb]. The
first checks whether every element in a list satisfies a given
predicate:
forallb oddb [1;3;5;7;9] = true
forallb negb [false;false] = true
forallb evenb [0;2;4;5] = false
forallb (beq_nat 5) [] = true
The second checks whether there exists an element in the list that
satisfies a given predicate:
existsb (beq_nat 5) [0;2;3;6] = false
existsb (andb true) [true;true;false] = true
existsb oddb [1;0;0;0;0;3] = true
existsb evenb [] = false
Next, define a _nonrecursive_ version of [existsb] -- call it
[existsb'] -- using [forallb] and [negb].
Prove that [existsb'] and [existsb] have the same behavior.
*)
(* FILL IN HERE *)
(** [] *)
(* $Date: 2014-02-04 07:15:43 -0500 (Tue, 04 Feb 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_BLACKBOX_V
`define SKY130_FD_SC_HS__A22O_BLACKBOX_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a22o (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_MUX_4TO2_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_MUX_4TO2_SYMBOL_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_mux_4to2 (
//# {{data|Data Signals}}
input A0,
input A1,
input A2,
input A3,
output X ,
//# {{control|Control Signals}}
input S0,
input S1
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_MUX_4TO2_SYMBOL_V
|
// Author: Adam Nunez, [email protected]
// Copyright (C) 2015 Adam Nunez
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
`timescale 1ns/1ns
module KeyPadTestBench();
reg flag;
//Inputs to KeyPadInterpreter
reg Clock;
reg ResetButton;
reg KeyRead;
reg [3:0] RowDataIn;
//Outputs from KeyPadInterpreter
wire KeyReady;
wire [3:0] DataOut;
wire [3:0] ColDataOut;
wire [3:0] PressCount;
//Clock Setup
initial begin
Clock = 0;
end
always begin
#1 Clock = ~Clock;
end
//End Clock Setup
//Keypad Emulator,
// returns that "5" is pressed after flag goes high
always @(ColDataOut) begin
if(flag==1) begin
case(ColDataOut)
4'bzzz0: RowDataIn = 4'b1111;
4'bzz0z: RowDataIn = 4'b1111;
4'bz0zz: RowDataIn = 4'b1101;
4'b0zzz: RowDataIn = 4'b1111;
endcase
end
else begin
case(ColDataOut)
4'bzzz0: RowDataIn = 4'b1111;
4'bzz0z: RowDataIn = 4'b1111;
4'bz0zz: RowDataIn = 4'b1111;
4'b0zzz: RowDataIn = 4'b1111;
endcase
end
end
//End Keypad Emulator
//Actual Testing
initial begin
#0 flag = 0;
#0 ResetButton = 0;
#3 ResetButton = 1;
#10000000; //Wait a long time
flag = 1;
#10000000; //Wait a little more
if(DataOut == 4'b0110)
$display("CorrectKey");
else
$display("Wrong DataOut");
end
//End of Testing
//Module to be tested
KeyPadInterpreter test(Clock,ResetButton,KeyRead,RowDataIn,KeyReady,DataOut,ColDataOut,PressCount);
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4.1 (win64) Build 1149489 Thu Feb 19 16:23:09 MST 2015
//Date : Fri Apr 24 21:57:30 2015
//Host : xps15 running 64-bit major release (build 9200)
//Command : generate_target tutorial.bd
//Design : tutorial
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module m00_couplers_imp_1SEDA4W
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [8:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [8:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [8:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [8:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [8:0]m00_couplers_to_m00_couplers_ARADDR;
wire [0:0]m00_couplers_to_m00_couplers_ARREADY;
wire [0:0]m00_couplers_to_m00_couplers_ARVALID;
wire [8:0]m00_couplers_to_m00_couplers_AWADDR;
wire [0:0]m00_couplers_to_m00_couplers_AWREADY;
wire [0:0]m00_couplers_to_m00_couplers_AWVALID;
wire [0:0]m00_couplers_to_m00_couplers_BREADY;
wire [1:0]m00_couplers_to_m00_couplers_BRESP;
wire [0:0]m00_couplers_to_m00_couplers_BVALID;
wire [31:0]m00_couplers_to_m00_couplers_RDATA;
wire [0:0]m00_couplers_to_m00_couplers_RREADY;
wire [1:0]m00_couplers_to_m00_couplers_RRESP;
wire [0:0]m00_couplers_to_m00_couplers_RVALID;
wire [31:0]m00_couplers_to_m00_couplers_WDATA;
wire [0:0]m00_couplers_to_m00_couplers_WREADY;
wire [3:0]m00_couplers_to_m00_couplers_WSTRB;
wire [0:0]m00_couplers_to_m00_couplers_WVALID;
assign M_AXI_araddr[8:0] = m00_couplers_to_m00_couplers_ARADDR;
assign M_AXI_arvalid[0] = m00_couplers_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[8:0] = m00_couplers_to_m00_couplers_AWADDR;
assign M_AXI_awvalid[0] = m00_couplers_to_m00_couplers_AWVALID;
assign M_AXI_bready[0] = m00_couplers_to_m00_couplers_BREADY;
assign M_AXI_rready[0] = m00_couplers_to_m00_couplers_RREADY;
assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m00_couplers_to_m00_couplers_WSTRB;
assign M_AXI_wvalid[0] = m00_couplers_to_m00_couplers_WVALID;
assign S_AXI_arready[0] = m00_couplers_to_m00_couplers_ARREADY;
assign S_AXI_awready[0] = m00_couplers_to_m00_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP;
assign S_AXI_bvalid[0] = m00_couplers_to_m00_couplers_BVALID;
assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA;
assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP;
assign S_AXI_rvalid[0] = m00_couplers_to_m00_couplers_RVALID;
assign S_AXI_wready[0] = m00_couplers_to_m00_couplers_WREADY;
assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[8:0];
assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready[0];
assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid[0];
assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[8:0];
assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready[0];
assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid[0];
assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready[0];
assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid[0];
assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready[0];
assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid[0];
assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0];
assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready[0];
assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module m00_couplers_imp_MNAJMW
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wid,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arregion,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awregion,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [0:0]M_AXI_arid;
output [3:0]M_AXI_arlen;
output [1:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
output [3:0]M_AXI_arqos;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [0:0]M_AXI_awid;
output [3:0]M_AXI_awlen;
output [1:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
output [3:0]M_AXI_awqos;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
input [0:0]M_AXI_bid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [63:0]M_AXI_rdata;
input [0:0]M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [63:0]M_AXI_wdata;
output [0:0]M_AXI_wid;
output M_AXI_wlast;
input M_AXI_wready;
output [7:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [0:0]S_AXI_arid;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [3:0]S_AXI_arregion;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [0:0]S_AXI_awid;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [3:0]S_AXI_awregion;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [0:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [63:0]S_AXI_rdata;
output [0:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [63:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [7:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_m00_couplers_ARADDR;
wire [1:0]auto_pc_to_m00_couplers_ARBURST;
wire [3:0]auto_pc_to_m00_couplers_ARCACHE;
wire [0:0]auto_pc_to_m00_couplers_ARID;
wire [3:0]auto_pc_to_m00_couplers_ARLEN;
wire [1:0]auto_pc_to_m00_couplers_ARLOCK;
wire [2:0]auto_pc_to_m00_couplers_ARPROT;
wire [3:0]auto_pc_to_m00_couplers_ARQOS;
wire auto_pc_to_m00_couplers_ARREADY;
wire [2:0]auto_pc_to_m00_couplers_ARSIZE;
wire auto_pc_to_m00_couplers_ARVALID;
wire [31:0]auto_pc_to_m00_couplers_AWADDR;
wire [1:0]auto_pc_to_m00_couplers_AWBURST;
wire [3:0]auto_pc_to_m00_couplers_AWCACHE;
wire [0:0]auto_pc_to_m00_couplers_AWID;
wire [3:0]auto_pc_to_m00_couplers_AWLEN;
wire [1:0]auto_pc_to_m00_couplers_AWLOCK;
wire [2:0]auto_pc_to_m00_couplers_AWPROT;
wire [3:0]auto_pc_to_m00_couplers_AWQOS;
wire auto_pc_to_m00_couplers_AWREADY;
wire [2:0]auto_pc_to_m00_couplers_AWSIZE;
wire auto_pc_to_m00_couplers_AWVALID;
wire [0:0]auto_pc_to_m00_couplers_BID;
wire auto_pc_to_m00_couplers_BREADY;
wire [1:0]auto_pc_to_m00_couplers_BRESP;
wire auto_pc_to_m00_couplers_BVALID;
wire [63:0]auto_pc_to_m00_couplers_RDATA;
wire [0:0]auto_pc_to_m00_couplers_RID;
wire auto_pc_to_m00_couplers_RLAST;
wire auto_pc_to_m00_couplers_RREADY;
wire [1:0]auto_pc_to_m00_couplers_RRESP;
wire auto_pc_to_m00_couplers_RVALID;
wire [63:0]auto_pc_to_m00_couplers_WDATA;
wire [0:0]auto_pc_to_m00_couplers_WID;
wire auto_pc_to_m00_couplers_WLAST;
wire auto_pc_to_m00_couplers_WREADY;
wire [7:0]auto_pc_to_m00_couplers_WSTRB;
wire auto_pc_to_m00_couplers_WVALID;
wire [31:0]m00_couplers_to_auto_pc_ARADDR;
wire [1:0]m00_couplers_to_auto_pc_ARBURST;
wire [3:0]m00_couplers_to_auto_pc_ARCACHE;
wire [0:0]m00_couplers_to_auto_pc_ARID;
wire [7:0]m00_couplers_to_auto_pc_ARLEN;
wire [0:0]m00_couplers_to_auto_pc_ARLOCK;
wire [2:0]m00_couplers_to_auto_pc_ARPROT;
wire [3:0]m00_couplers_to_auto_pc_ARQOS;
wire m00_couplers_to_auto_pc_ARREADY;
wire [3:0]m00_couplers_to_auto_pc_ARREGION;
wire [2:0]m00_couplers_to_auto_pc_ARSIZE;
wire m00_couplers_to_auto_pc_ARVALID;
wire [31:0]m00_couplers_to_auto_pc_AWADDR;
wire [1:0]m00_couplers_to_auto_pc_AWBURST;
wire [3:0]m00_couplers_to_auto_pc_AWCACHE;
wire [0:0]m00_couplers_to_auto_pc_AWID;
wire [7:0]m00_couplers_to_auto_pc_AWLEN;
wire [0:0]m00_couplers_to_auto_pc_AWLOCK;
wire [2:0]m00_couplers_to_auto_pc_AWPROT;
wire [3:0]m00_couplers_to_auto_pc_AWQOS;
wire m00_couplers_to_auto_pc_AWREADY;
wire [3:0]m00_couplers_to_auto_pc_AWREGION;
wire [2:0]m00_couplers_to_auto_pc_AWSIZE;
wire m00_couplers_to_auto_pc_AWVALID;
wire [0:0]m00_couplers_to_auto_pc_BID;
wire m00_couplers_to_auto_pc_BREADY;
wire [1:0]m00_couplers_to_auto_pc_BRESP;
wire m00_couplers_to_auto_pc_BVALID;
wire [63:0]m00_couplers_to_auto_pc_RDATA;
wire [0:0]m00_couplers_to_auto_pc_RID;
wire m00_couplers_to_auto_pc_RLAST;
wire m00_couplers_to_auto_pc_RREADY;
wire [1:0]m00_couplers_to_auto_pc_RRESP;
wire m00_couplers_to_auto_pc_RVALID;
wire [63:0]m00_couplers_to_auto_pc_WDATA;
wire m00_couplers_to_auto_pc_WLAST;
wire m00_couplers_to_auto_pc_WREADY;
wire [7:0]m00_couplers_to_auto_pc_WSTRB;
wire m00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_m00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = auto_pc_to_m00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_m00_couplers_ARCACHE;
assign M_AXI_arid[0] = auto_pc_to_m00_couplers_ARID;
assign M_AXI_arlen[3:0] = auto_pc_to_m00_couplers_ARLEN;
assign M_AXI_arlock[1:0] = auto_pc_to_m00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_m00_couplers_ARPROT;
assign M_AXI_arqos[3:0] = auto_pc_to_m00_couplers_ARQOS;
assign M_AXI_arsize[2:0] = auto_pc_to_m00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_m00_couplers_AWADDR;
assign M_AXI_awburst[1:0] = auto_pc_to_m00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_m00_couplers_AWCACHE;
assign M_AXI_awid[0] = auto_pc_to_m00_couplers_AWID;
assign M_AXI_awlen[3:0] = auto_pc_to_m00_couplers_AWLEN;
assign M_AXI_awlock[1:0] = auto_pc_to_m00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_m00_couplers_AWPROT;
assign M_AXI_awqos[3:0] = auto_pc_to_m00_couplers_AWQOS;
assign M_AXI_awsize[2:0] = auto_pc_to_m00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_m00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_m00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_m00_couplers_RREADY;
assign M_AXI_wdata[63:0] = auto_pc_to_m00_couplers_WDATA;
assign M_AXI_wid[0] = auto_pc_to_m00_couplers_WID;
assign M_AXI_wlast = auto_pc_to_m00_couplers_WLAST;
assign M_AXI_wstrb[7:0] = auto_pc_to_m00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_m00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = m00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = m00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[0] = m00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = m00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = m00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[63:0] = m00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[0] = m00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = m00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = m00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = m00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = m00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_m00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_m00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_m00_couplers_BID = M_AXI_bid[0];
assign auto_pc_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_m00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_m00_couplers_RDATA = M_AXI_rdata[63:0];
assign auto_pc_to_m00_couplers_RID = M_AXI_rid[0];
assign auto_pc_to_m00_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_m00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_m00_couplers_WREADY = M_AXI_wready;
assign m00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign m00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign m00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign m00_couplers_to_auto_pc_ARID = S_AXI_arid[0];
assign m00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign m00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign m00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign m00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign m00_couplers_to_auto_pc_ARREGION = S_AXI_arregion[3:0];
assign m00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign m00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign m00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign m00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign m00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign m00_couplers_to_auto_pc_AWID = S_AXI_awid[0];
assign m00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign m00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign m00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign m00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign m00_couplers_to_auto_pc_AWREGION = S_AXI_awregion[3:0];
assign m00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign m00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign m00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign m00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign m00_couplers_to_auto_pc_WDATA = S_AXI_wdata[63:0];
assign m00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign m00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[7:0];
assign m00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
tutorial_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_m00_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_m00_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_m00_couplers_ARCACHE),
.m_axi_arid(auto_pc_to_m00_couplers_ARID),
.m_axi_arlen(auto_pc_to_m00_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_m00_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_m00_couplers_ARPROT),
.m_axi_arqos(auto_pc_to_m00_couplers_ARQOS),
.m_axi_arready(auto_pc_to_m00_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_m00_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_m00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_m00_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_m00_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_m00_couplers_AWCACHE),
.m_axi_awid(auto_pc_to_m00_couplers_AWID),
.m_axi_awlen(auto_pc_to_m00_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_m00_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_m00_couplers_AWPROT),
.m_axi_awqos(auto_pc_to_m00_couplers_AWQOS),
.m_axi_awready(auto_pc_to_m00_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_m00_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_m00_couplers_AWVALID),
.m_axi_bid(auto_pc_to_m00_couplers_BID),
.m_axi_bready(auto_pc_to_m00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_m00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_m00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_m00_couplers_RDATA),
.m_axi_rid(auto_pc_to_m00_couplers_RID),
.m_axi_rlast(auto_pc_to_m00_couplers_RLAST),
.m_axi_rready(auto_pc_to_m00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_m00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_m00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_m00_couplers_WDATA),
.m_axi_wid(auto_pc_to_m00_couplers_WID),
.m_axi_wlast(auto_pc_to_m00_couplers_WLAST),
.m_axi_wready(auto_pc_to_m00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_m00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_m00_couplers_WVALID),
.s_axi_araddr(m00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(m00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(m00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(m00_couplers_to_auto_pc_ARID),
.s_axi_arlen(m00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(m00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(m00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(m00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(m00_couplers_to_auto_pc_ARREADY),
.s_axi_arregion(m00_couplers_to_auto_pc_ARREGION),
.s_axi_arsize(m00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(m00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(m00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(m00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(m00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(m00_couplers_to_auto_pc_AWID),
.s_axi_awlen(m00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(m00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(m00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(m00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(m00_couplers_to_auto_pc_AWREADY),
.s_axi_awregion(m00_couplers_to_auto_pc_AWREGION),
.s_axi_awsize(m00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(m00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(m00_couplers_to_auto_pc_BID),
.s_axi_bready(m00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(m00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(m00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(m00_couplers_to_auto_pc_RDATA),
.s_axi_rid(m00_couplers_to_auto_pc_RID),
.s_axi_rlast(m00_couplers_to_auto_pc_RLAST),
.s_axi_rready(m00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(m00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(m00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(m00_couplers_to_auto_pc_WDATA),
.s_axi_wlast(m00_couplers_to_auto_pc_WLAST),
.s_axi_wready(m00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(m00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(m00_couplers_to_auto_pc_WVALID));
endmodule
module m01_couplers_imp_20VUK1
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [8:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [8:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [8:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [8:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [8:0]m01_couplers_to_m01_couplers_ARADDR;
wire [0:0]m01_couplers_to_m01_couplers_ARREADY;
wire [0:0]m01_couplers_to_m01_couplers_ARVALID;
wire [8:0]m01_couplers_to_m01_couplers_AWADDR;
wire [0:0]m01_couplers_to_m01_couplers_AWREADY;
wire [0:0]m01_couplers_to_m01_couplers_AWVALID;
wire [0:0]m01_couplers_to_m01_couplers_BREADY;
wire [1:0]m01_couplers_to_m01_couplers_BRESP;
wire [0:0]m01_couplers_to_m01_couplers_BVALID;
wire [31:0]m01_couplers_to_m01_couplers_RDATA;
wire [0:0]m01_couplers_to_m01_couplers_RREADY;
wire [1:0]m01_couplers_to_m01_couplers_RRESP;
wire [0:0]m01_couplers_to_m01_couplers_RVALID;
wire [31:0]m01_couplers_to_m01_couplers_WDATA;
wire [0:0]m01_couplers_to_m01_couplers_WREADY;
wire [3:0]m01_couplers_to_m01_couplers_WSTRB;
wire [0:0]m01_couplers_to_m01_couplers_WVALID;
assign M_AXI_araddr[8:0] = m01_couplers_to_m01_couplers_ARADDR;
assign M_AXI_arvalid[0] = m01_couplers_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[8:0] = m01_couplers_to_m01_couplers_AWADDR;
assign M_AXI_awvalid[0] = m01_couplers_to_m01_couplers_AWVALID;
assign M_AXI_bready[0] = m01_couplers_to_m01_couplers_BREADY;
assign M_AXI_rready[0] = m01_couplers_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = m01_couplers_to_m01_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m01_couplers_to_m01_couplers_WSTRB;
assign M_AXI_wvalid[0] = m01_couplers_to_m01_couplers_WVALID;
assign S_AXI_arready[0] = m01_couplers_to_m01_couplers_ARREADY;
assign S_AXI_awready[0] = m01_couplers_to_m01_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_m01_couplers_BRESP;
assign S_AXI_bvalid[0] = m01_couplers_to_m01_couplers_BVALID;
assign S_AXI_rdata[31:0] = m01_couplers_to_m01_couplers_RDATA;
assign S_AXI_rresp[1:0] = m01_couplers_to_m01_couplers_RRESP;
assign S_AXI_rvalid[0] = m01_couplers_to_m01_couplers_RVALID;
assign S_AXI_wready[0] = m01_couplers_to_m01_couplers_WREADY;
assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr[8:0];
assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready[0];
assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid[0];
assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr[8:0];
assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready[0];
assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid[0];
assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready[0];
assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid[0];
assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready[0];
assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid[0];
assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata[31:0];
assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready[0];
assign m01_couplers_to_m01_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module m02_couplers_imp_1TZBY8J
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [8:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [8:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [8:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [8:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [0:0]S_AXI_wvalid;
wire [8:0]m02_couplers_to_m02_couplers_ARADDR;
wire [0:0]m02_couplers_to_m02_couplers_ARREADY;
wire [0:0]m02_couplers_to_m02_couplers_ARVALID;
wire [8:0]m02_couplers_to_m02_couplers_AWADDR;
wire [0:0]m02_couplers_to_m02_couplers_AWREADY;
wire [0:0]m02_couplers_to_m02_couplers_AWVALID;
wire [0:0]m02_couplers_to_m02_couplers_BREADY;
wire [1:0]m02_couplers_to_m02_couplers_BRESP;
wire [0:0]m02_couplers_to_m02_couplers_BVALID;
wire [31:0]m02_couplers_to_m02_couplers_RDATA;
wire [0:0]m02_couplers_to_m02_couplers_RREADY;
wire [1:0]m02_couplers_to_m02_couplers_RRESP;
wire [0:0]m02_couplers_to_m02_couplers_RVALID;
wire [31:0]m02_couplers_to_m02_couplers_WDATA;
wire [0:0]m02_couplers_to_m02_couplers_WREADY;
wire [0:0]m02_couplers_to_m02_couplers_WVALID;
assign M_AXI_araddr[8:0] = m02_couplers_to_m02_couplers_ARADDR;
assign M_AXI_arvalid[0] = m02_couplers_to_m02_couplers_ARVALID;
assign M_AXI_awaddr[8:0] = m02_couplers_to_m02_couplers_AWADDR;
assign M_AXI_awvalid[0] = m02_couplers_to_m02_couplers_AWVALID;
assign M_AXI_bready[0] = m02_couplers_to_m02_couplers_BREADY;
assign M_AXI_rready[0] = m02_couplers_to_m02_couplers_RREADY;
assign M_AXI_wdata[31:0] = m02_couplers_to_m02_couplers_WDATA;
assign M_AXI_wvalid[0] = m02_couplers_to_m02_couplers_WVALID;
assign S_AXI_arready[0] = m02_couplers_to_m02_couplers_ARREADY;
assign S_AXI_awready[0] = m02_couplers_to_m02_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m02_couplers_to_m02_couplers_BRESP;
assign S_AXI_bvalid[0] = m02_couplers_to_m02_couplers_BVALID;
assign S_AXI_rdata[31:0] = m02_couplers_to_m02_couplers_RDATA;
assign S_AXI_rresp[1:0] = m02_couplers_to_m02_couplers_RRESP;
assign S_AXI_rvalid[0] = m02_couplers_to_m02_couplers_RVALID;
assign S_AXI_wready[0] = m02_couplers_to_m02_couplers_WREADY;
assign m02_couplers_to_m02_couplers_ARADDR = S_AXI_araddr[8:0];
assign m02_couplers_to_m02_couplers_ARREADY = M_AXI_arready[0];
assign m02_couplers_to_m02_couplers_ARVALID = S_AXI_arvalid[0];
assign m02_couplers_to_m02_couplers_AWADDR = S_AXI_awaddr[8:0];
assign m02_couplers_to_m02_couplers_AWREADY = M_AXI_awready[0];
assign m02_couplers_to_m02_couplers_AWVALID = S_AXI_awvalid[0];
assign m02_couplers_to_m02_couplers_BREADY = S_AXI_bready[0];
assign m02_couplers_to_m02_couplers_BRESP = M_AXI_bresp[1:0];
assign m02_couplers_to_m02_couplers_BVALID = M_AXI_bvalid[0];
assign m02_couplers_to_m02_couplers_RDATA = M_AXI_rdata[31:0];
assign m02_couplers_to_m02_couplers_RREADY = S_AXI_rready[0];
assign m02_couplers_to_m02_couplers_RRESP = M_AXI_rresp[1:0];
assign m02_couplers_to_m02_couplers_RVALID = M_AXI_rvalid[0];
assign m02_couplers_to_m02_couplers_WDATA = S_AXI_wdata[31:0];
assign m02_couplers_to_m02_couplers_WREADY = M_AXI_wready[0];
assign m02_couplers_to_m02_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module m03_couplers_imp_Q7ENM
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [8:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [8:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [8:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [8:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [8:0]m03_couplers_to_m03_couplers_ARADDR;
wire [0:0]m03_couplers_to_m03_couplers_ARREADY;
wire [0:0]m03_couplers_to_m03_couplers_ARVALID;
wire [8:0]m03_couplers_to_m03_couplers_AWADDR;
wire [0:0]m03_couplers_to_m03_couplers_AWREADY;
wire [0:0]m03_couplers_to_m03_couplers_AWVALID;
wire [0:0]m03_couplers_to_m03_couplers_BREADY;
wire [1:0]m03_couplers_to_m03_couplers_BRESP;
wire [0:0]m03_couplers_to_m03_couplers_BVALID;
wire [31:0]m03_couplers_to_m03_couplers_RDATA;
wire [0:0]m03_couplers_to_m03_couplers_RREADY;
wire [1:0]m03_couplers_to_m03_couplers_RRESP;
wire [0:0]m03_couplers_to_m03_couplers_RVALID;
wire [31:0]m03_couplers_to_m03_couplers_WDATA;
wire [0:0]m03_couplers_to_m03_couplers_WREADY;
wire [3:0]m03_couplers_to_m03_couplers_WSTRB;
wire [0:0]m03_couplers_to_m03_couplers_WVALID;
assign M_AXI_araddr[8:0] = m03_couplers_to_m03_couplers_ARADDR;
assign M_AXI_arvalid[0] = m03_couplers_to_m03_couplers_ARVALID;
assign M_AXI_awaddr[8:0] = m03_couplers_to_m03_couplers_AWADDR;
assign M_AXI_awvalid[0] = m03_couplers_to_m03_couplers_AWVALID;
assign M_AXI_bready[0] = m03_couplers_to_m03_couplers_BREADY;
assign M_AXI_rready[0] = m03_couplers_to_m03_couplers_RREADY;
assign M_AXI_wdata[31:0] = m03_couplers_to_m03_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m03_couplers_to_m03_couplers_WSTRB;
assign M_AXI_wvalid[0] = m03_couplers_to_m03_couplers_WVALID;
assign S_AXI_arready[0] = m03_couplers_to_m03_couplers_ARREADY;
assign S_AXI_awready[0] = m03_couplers_to_m03_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m03_couplers_to_m03_couplers_BRESP;
assign S_AXI_bvalid[0] = m03_couplers_to_m03_couplers_BVALID;
assign S_AXI_rdata[31:0] = m03_couplers_to_m03_couplers_RDATA;
assign S_AXI_rresp[1:0] = m03_couplers_to_m03_couplers_RRESP;
assign S_AXI_rvalid[0] = m03_couplers_to_m03_couplers_RVALID;
assign S_AXI_wready[0] = m03_couplers_to_m03_couplers_WREADY;
assign m03_couplers_to_m03_couplers_ARADDR = S_AXI_araddr[8:0];
assign m03_couplers_to_m03_couplers_ARREADY = M_AXI_arready[0];
assign m03_couplers_to_m03_couplers_ARVALID = S_AXI_arvalid[0];
assign m03_couplers_to_m03_couplers_AWADDR = S_AXI_awaddr[8:0];
assign m03_couplers_to_m03_couplers_AWREADY = M_AXI_awready[0];
assign m03_couplers_to_m03_couplers_AWVALID = S_AXI_awvalid[0];
assign m03_couplers_to_m03_couplers_BREADY = S_AXI_bready[0];
assign m03_couplers_to_m03_couplers_BRESP = M_AXI_bresp[1:0];
assign m03_couplers_to_m03_couplers_BVALID = M_AXI_bvalid[0];
assign m03_couplers_to_m03_couplers_RDATA = M_AXI_rdata[31:0];
assign m03_couplers_to_m03_couplers_RREADY = S_AXI_rready[0];
assign m03_couplers_to_m03_couplers_RRESP = M_AXI_rresp[1:0];
assign m03_couplers_to_m03_couplers_RVALID = M_AXI_rvalid[0];
assign m03_couplers_to_m03_couplers_WDATA = S_AXI_wdata[31:0];
assign m03_couplers_to_m03_couplers_WREADY = M_AXI_wready[0];
assign m03_couplers_to_m03_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m03_couplers_to_m03_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module s00_couplers_imp_1ASF99M
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arlen,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_rdata,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arlen,
S_AXI_arprot,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_rdata,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [7:0]M_AXI_arlen;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
input [63:0]M_AXI_rdata;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [7:0]S_AXI_arlen;
input [2:0]S_AXI_arprot;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
output [63:0]S_AXI_rdata;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
wire [31:0]s00_couplers_to_s00_couplers_ARADDR;
wire [1:0]s00_couplers_to_s00_couplers_ARBURST;
wire [3:0]s00_couplers_to_s00_couplers_ARCACHE;
wire [7:0]s00_couplers_to_s00_couplers_ARLEN;
wire [2:0]s00_couplers_to_s00_couplers_ARPROT;
wire s00_couplers_to_s00_couplers_ARREADY;
wire [2:0]s00_couplers_to_s00_couplers_ARSIZE;
wire s00_couplers_to_s00_couplers_ARVALID;
wire [63:0]s00_couplers_to_s00_couplers_RDATA;
wire s00_couplers_to_s00_couplers_RLAST;
wire s00_couplers_to_s00_couplers_RREADY;
wire [1:0]s00_couplers_to_s00_couplers_RRESP;
wire s00_couplers_to_s00_couplers_RVALID;
assign M_AXI_araddr[31:0] = s00_couplers_to_s00_couplers_ARADDR;
assign M_AXI_arburst[1:0] = s00_couplers_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = s00_couplers_to_s00_couplers_ARCACHE;
assign M_AXI_arlen[7:0] = s00_couplers_to_s00_couplers_ARLEN;
assign M_AXI_arprot[2:0] = s00_couplers_to_s00_couplers_ARPROT;
assign M_AXI_arsize[2:0] = s00_couplers_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = s00_couplers_to_s00_couplers_ARVALID;
assign M_AXI_rready = s00_couplers_to_s00_couplers_RREADY;
assign S_AXI_arready = s00_couplers_to_s00_couplers_ARREADY;
assign S_AXI_rdata[63:0] = s00_couplers_to_s00_couplers_RDATA;
assign S_AXI_rlast = s00_couplers_to_s00_couplers_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_s00_couplers_RRESP;
assign S_AXI_rvalid = s00_couplers_to_s00_couplers_RVALID;
assign s00_couplers_to_s00_couplers_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_s00_couplers_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_s00_couplers_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_s00_couplers_ARLEN = S_AXI_arlen[7:0];
assign s00_couplers_to_s00_couplers_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_s00_couplers_ARREADY = M_AXI_arready;
assign s00_couplers_to_s00_couplers_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_s00_couplers_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_s00_couplers_RDATA = M_AXI_rdata[63:0];
assign s00_couplers_to_s00_couplers_RLAST = M_AXI_rlast;
assign s00_couplers_to_s00_couplers_RREADY = S_AXI_rready;
assign s00_couplers_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign s00_couplers_to_s00_couplers_RVALID = M_AXI_rvalid;
endmodule
module s00_couplers_imp_4RCRTE
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
tutorial_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
module s00_couplers_imp_ADOUIZ
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [4:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [4:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[4:0] = auto_pc_to_s00_couplers_ARADDR[4:0];
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[4:0] = auto_pc_to_s00_couplers_AWADDR[4:0];
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
tutorial_auto_pc_2 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
module s01_couplers_imp_JYOW23
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arqos,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awqos,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output M_AXI_araddr;
output M_AXI_arburst;
output M_AXI_arcache;
output M_AXI_arid;
output M_AXI_arlen;
output M_AXI_arlock;
output M_AXI_arprot;
output M_AXI_arqos;
input M_AXI_arready;
output M_AXI_arsize;
output M_AXI_arvalid;
output M_AXI_awaddr;
output M_AXI_awburst;
output M_AXI_awcache;
output M_AXI_awid;
output M_AXI_awlen;
output M_AXI_awlock;
output M_AXI_awprot;
output M_AXI_awqos;
input M_AXI_awready;
output M_AXI_awsize;
output M_AXI_awvalid;
input M_AXI_bid;
output M_AXI_bready;
input M_AXI_bresp;
input M_AXI_bvalid;
input M_AXI_rdata;
input M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input M_AXI_rresp;
input M_AXI_rvalid;
output M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input S_AXI_araddr;
input S_AXI_arburst;
input S_AXI_arcache;
input S_AXI_arid;
input S_AXI_arlen;
input S_AXI_arlock;
input S_AXI_arprot;
input S_AXI_arqos;
output S_AXI_arready;
input S_AXI_arsize;
input S_AXI_arvalid;
input S_AXI_awaddr;
input S_AXI_awburst;
input S_AXI_awcache;
input S_AXI_awid;
input S_AXI_awlen;
input S_AXI_awlock;
input S_AXI_awprot;
input S_AXI_awqos;
output S_AXI_awready;
input S_AXI_awsize;
input S_AXI_awvalid;
output S_AXI_bid;
input S_AXI_bready;
output S_AXI_bresp;
output S_AXI_bvalid;
output S_AXI_rdata;
output S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output S_AXI_rresp;
output S_AXI_rvalid;
input S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input S_AXI_wstrb;
input S_AXI_wvalid;
wire s01_couplers_to_s01_couplers_ARADDR;
wire s01_couplers_to_s01_couplers_ARBURST;
wire s01_couplers_to_s01_couplers_ARCACHE;
wire s01_couplers_to_s01_couplers_ARID;
wire s01_couplers_to_s01_couplers_ARLEN;
wire s01_couplers_to_s01_couplers_ARLOCK;
wire s01_couplers_to_s01_couplers_ARPROT;
wire s01_couplers_to_s01_couplers_ARQOS;
wire s01_couplers_to_s01_couplers_ARREADY;
wire s01_couplers_to_s01_couplers_ARSIZE;
wire s01_couplers_to_s01_couplers_ARVALID;
wire s01_couplers_to_s01_couplers_AWADDR;
wire s01_couplers_to_s01_couplers_AWBURST;
wire s01_couplers_to_s01_couplers_AWCACHE;
wire s01_couplers_to_s01_couplers_AWID;
wire s01_couplers_to_s01_couplers_AWLEN;
wire s01_couplers_to_s01_couplers_AWLOCK;
wire s01_couplers_to_s01_couplers_AWPROT;
wire s01_couplers_to_s01_couplers_AWQOS;
wire s01_couplers_to_s01_couplers_AWREADY;
wire s01_couplers_to_s01_couplers_AWSIZE;
wire s01_couplers_to_s01_couplers_AWVALID;
wire s01_couplers_to_s01_couplers_BID;
wire s01_couplers_to_s01_couplers_BREADY;
wire s01_couplers_to_s01_couplers_BRESP;
wire s01_couplers_to_s01_couplers_BVALID;
wire s01_couplers_to_s01_couplers_RDATA;
wire s01_couplers_to_s01_couplers_RID;
wire s01_couplers_to_s01_couplers_RLAST;
wire s01_couplers_to_s01_couplers_RREADY;
wire s01_couplers_to_s01_couplers_RRESP;
wire s01_couplers_to_s01_couplers_RVALID;
wire s01_couplers_to_s01_couplers_WDATA;
wire s01_couplers_to_s01_couplers_WLAST;
wire s01_couplers_to_s01_couplers_WREADY;
wire s01_couplers_to_s01_couplers_WSTRB;
wire s01_couplers_to_s01_couplers_WVALID;
assign M_AXI_araddr = s01_couplers_to_s01_couplers_ARADDR;
assign M_AXI_arburst = s01_couplers_to_s01_couplers_ARBURST;
assign M_AXI_arcache = s01_couplers_to_s01_couplers_ARCACHE;
assign M_AXI_arid = s01_couplers_to_s01_couplers_ARID;
assign M_AXI_arlen = s01_couplers_to_s01_couplers_ARLEN;
assign M_AXI_arlock = s01_couplers_to_s01_couplers_ARLOCK;
assign M_AXI_arprot = s01_couplers_to_s01_couplers_ARPROT;
assign M_AXI_arqos = s01_couplers_to_s01_couplers_ARQOS;
assign M_AXI_arsize = s01_couplers_to_s01_couplers_ARSIZE;
assign M_AXI_arvalid = s01_couplers_to_s01_couplers_ARVALID;
assign M_AXI_awaddr = s01_couplers_to_s01_couplers_AWADDR;
assign M_AXI_awburst = s01_couplers_to_s01_couplers_AWBURST;
assign M_AXI_awcache = s01_couplers_to_s01_couplers_AWCACHE;
assign M_AXI_awid = s01_couplers_to_s01_couplers_AWID;
assign M_AXI_awlen = s01_couplers_to_s01_couplers_AWLEN;
assign M_AXI_awlock = s01_couplers_to_s01_couplers_AWLOCK;
assign M_AXI_awprot = s01_couplers_to_s01_couplers_AWPROT;
assign M_AXI_awqos = s01_couplers_to_s01_couplers_AWQOS;
assign M_AXI_awsize = s01_couplers_to_s01_couplers_AWSIZE;
assign M_AXI_awvalid = s01_couplers_to_s01_couplers_AWVALID;
assign M_AXI_bready = s01_couplers_to_s01_couplers_BREADY;
assign M_AXI_rready = s01_couplers_to_s01_couplers_RREADY;
assign M_AXI_wdata = s01_couplers_to_s01_couplers_WDATA;
assign M_AXI_wlast = s01_couplers_to_s01_couplers_WLAST;
assign M_AXI_wstrb = s01_couplers_to_s01_couplers_WSTRB;
assign M_AXI_wvalid = s01_couplers_to_s01_couplers_WVALID;
assign S_AXI_arready = s01_couplers_to_s01_couplers_ARREADY;
assign S_AXI_awready = s01_couplers_to_s01_couplers_AWREADY;
assign S_AXI_bid = s01_couplers_to_s01_couplers_BID;
assign S_AXI_bresp = s01_couplers_to_s01_couplers_BRESP;
assign S_AXI_bvalid = s01_couplers_to_s01_couplers_BVALID;
assign S_AXI_rdata = s01_couplers_to_s01_couplers_RDATA;
assign S_AXI_rid = s01_couplers_to_s01_couplers_RID;
assign S_AXI_rlast = s01_couplers_to_s01_couplers_RLAST;
assign S_AXI_rresp = s01_couplers_to_s01_couplers_RRESP;
assign S_AXI_rvalid = s01_couplers_to_s01_couplers_RVALID;
assign S_AXI_wready = s01_couplers_to_s01_couplers_WREADY;
assign s01_couplers_to_s01_couplers_ARADDR = S_AXI_araddr;
assign s01_couplers_to_s01_couplers_ARBURST = S_AXI_arburst;
assign s01_couplers_to_s01_couplers_ARCACHE = S_AXI_arcache;
assign s01_couplers_to_s01_couplers_ARID = S_AXI_arid;
assign s01_couplers_to_s01_couplers_ARLEN = S_AXI_arlen;
assign s01_couplers_to_s01_couplers_ARLOCK = S_AXI_arlock;
assign s01_couplers_to_s01_couplers_ARPROT = S_AXI_arprot;
assign s01_couplers_to_s01_couplers_ARQOS = S_AXI_arqos;
assign s01_couplers_to_s01_couplers_ARREADY = M_AXI_arready;
assign s01_couplers_to_s01_couplers_ARSIZE = S_AXI_arsize;
assign s01_couplers_to_s01_couplers_ARVALID = S_AXI_arvalid;
assign s01_couplers_to_s01_couplers_AWADDR = S_AXI_awaddr;
assign s01_couplers_to_s01_couplers_AWBURST = S_AXI_awburst;
assign s01_couplers_to_s01_couplers_AWCACHE = S_AXI_awcache;
assign s01_couplers_to_s01_couplers_AWID = S_AXI_awid;
assign s01_couplers_to_s01_couplers_AWLEN = S_AXI_awlen;
assign s01_couplers_to_s01_couplers_AWLOCK = S_AXI_awlock;
assign s01_couplers_to_s01_couplers_AWPROT = S_AXI_awprot;
assign s01_couplers_to_s01_couplers_AWQOS = S_AXI_awqos;
assign s01_couplers_to_s01_couplers_AWREADY = M_AXI_awready;
assign s01_couplers_to_s01_couplers_AWSIZE = S_AXI_awsize;
assign s01_couplers_to_s01_couplers_AWVALID = S_AXI_awvalid;
assign s01_couplers_to_s01_couplers_BID = M_AXI_bid;
assign s01_couplers_to_s01_couplers_BREADY = S_AXI_bready;
assign s01_couplers_to_s01_couplers_BRESP = M_AXI_bresp;
assign s01_couplers_to_s01_couplers_BVALID = M_AXI_bvalid;
assign s01_couplers_to_s01_couplers_RDATA = M_AXI_rdata;
assign s01_couplers_to_s01_couplers_RID = M_AXI_rid;
assign s01_couplers_to_s01_couplers_RLAST = M_AXI_rlast;
assign s01_couplers_to_s01_couplers_RREADY = S_AXI_rready;
assign s01_couplers_to_s01_couplers_RRESP = M_AXI_rresp;
assign s01_couplers_to_s01_couplers_RVALID = M_AXI_rvalid;
assign s01_couplers_to_s01_couplers_WDATA = S_AXI_wdata;
assign s01_couplers_to_s01_couplers_WLAST = S_AXI_wlast;
assign s01_couplers_to_s01_couplers_WREADY = M_AXI_wready;
assign s01_couplers_to_s01_couplers_WSTRB = S_AXI_wstrb;
assign s01_couplers_to_s01_couplers_WVALID = S_AXI_wvalid;
endmodule
module tutorial
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
hdmio_io_clk,
hdmio_io_data,
hdmio_io_de,
hdmio_io_hsync,
hdmio_io_spdif,
hdmio_io_vsync,
zed_hdmi_iic_scl_i,
zed_hdmi_iic_scl_o,
zed_hdmi_iic_scl_t,
zed_hdmi_iic_sda_i,
zed_hdmi_iic_sda_o,
zed_hdmi_iic_sda_t);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output hdmio_io_clk;
output [15:0]hdmio_io_data;
output hdmio_io_de;
output hdmio_io_hsync;
output hdmio_io_spdif;
output hdmio_io_vsync;
input zed_hdmi_iic_scl_i;
output zed_hdmi_iic_scl_o;
output zed_hdmi_iic_scl_t;
input zed_hdmi_iic_sda_i;
output zed_hdmi_iic_sda_o;
output zed_hdmi_iic_sda_t;
wire [0:0]ARESETN_1;
wire GND_1;
wire [0:0]S00_ARESETN_1;
wire VCC_1;
wire axi4s_clk_1;
wire axi4s_resetn_1;
wire hdmio_clk_1;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_CLK2;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP1_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP1_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP1_ARID;
wire [3:0]processing_system7_0_M_AXI_GP1_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP1_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP1_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP1_ARQOS;
wire processing_system7_0_M_AXI_GP1_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP1_ARSIZE;
wire processing_system7_0_M_AXI_GP1_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP1_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP1_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP1_AWID;
wire [3:0]processing_system7_0_M_AXI_GP1_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP1_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP1_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP1_AWQOS;
wire processing_system7_0_M_AXI_GP1_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP1_AWSIZE;
wire processing_system7_0_M_AXI_GP1_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP1_BID;
wire processing_system7_0_M_AXI_GP1_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP1_BRESP;
wire processing_system7_0_M_AXI_GP1_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP1_RID;
wire processing_system7_0_M_AXI_GP1_RLAST;
wire processing_system7_0_M_AXI_GP1_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP1_RRESP;
wire processing_system7_0_M_AXI_GP1_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP1_WID;
wire processing_system7_0_M_AXI_GP1_WLAST;
wire processing_system7_0_M_AXI_GP1_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP1_WSTRB;
wire processing_system7_0_M_AXI_GP1_WVALID;
wire [4:0]processing_system7_0_axi_periph_1_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_1_M00_AXI_ARREADY;
wire processing_system7_0_axi_periph_1_M00_AXI_ARVALID;
wire [4:0]processing_system7_0_axi_periph_1_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_1_M00_AXI_AWREADY;
wire processing_system7_0_axi_periph_1_M00_AXI_AWVALID;
wire processing_system7_0_axi_periph_1_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_1_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_1_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_1_M00_AXI_RDATA;
wire processing_system7_0_axi_periph_1_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_1_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_1_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_1_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_1_M00_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_1_M00_AXI_WSTRB;
wire processing_system7_0_axi_periph_1_M00_AXI_WVALID;
wire [8:0]processing_system7_0_axi_periph_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_M00_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_ARVALID;
wire [8:0]processing_system7_0_axi_periph_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_M00_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_M00_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M00_AXI_WSTRB;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_WVALID;
wire [8:0]processing_system7_0_axi_periph_M01_AXI_ARADDR;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_ARVALID;
wire [8:0]processing_system7_0_axi_periph_M01_AXI_AWADDR;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_BRESP;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_RRESP;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_WDATA;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M01_AXI_WSTRB;
wire [0:0]processing_system7_0_axi_periph_M01_AXI_WVALID;
wire [8:0]processing_system7_0_axi_periph_M02_AXI_ARADDR;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_ARVALID;
wire [8:0]processing_system7_0_axi_periph_M02_AXI_AWADDR;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_BRESP;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_RRESP;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_WDATA;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_WREADY;
wire [0:0]processing_system7_0_axi_periph_M02_AXI_WVALID;
wire [8:0]processing_system7_0_axi_periph_M03_AXI_ARADDR;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_ARVALID;
wire [8:0]processing_system7_0_axi_periph_M03_AXI_AWADDR;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M03_AXI_BRESP;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M03_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M03_AXI_RRESP;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M03_AXI_WDATA;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M03_AXI_WSTRB;
wire [0:0]processing_system7_0_axi_periph_M03_AXI_WVALID;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
wire [31:0]zed_hdmi_display_M00_AXI_ARADDR;
wire [1:0]zed_hdmi_display_M00_AXI_ARBURST;
wire [3:0]zed_hdmi_display_M00_AXI_ARCACHE;
wire [0:0]zed_hdmi_display_M00_AXI_ARID;
wire [3:0]zed_hdmi_display_M00_AXI_ARLEN;
wire [1:0]zed_hdmi_display_M00_AXI_ARLOCK;
wire [2:0]zed_hdmi_display_M00_AXI_ARPROT;
wire [3:0]zed_hdmi_display_M00_AXI_ARQOS;
wire zed_hdmi_display_M00_AXI_ARREADY;
wire [2:0]zed_hdmi_display_M00_AXI_ARSIZE;
wire zed_hdmi_display_M00_AXI_ARVALID;
wire [31:0]zed_hdmi_display_M00_AXI_AWADDR;
wire [1:0]zed_hdmi_display_M00_AXI_AWBURST;
wire [3:0]zed_hdmi_display_M00_AXI_AWCACHE;
wire [0:0]zed_hdmi_display_M00_AXI_AWID;
wire [3:0]zed_hdmi_display_M00_AXI_AWLEN;
wire [1:0]zed_hdmi_display_M00_AXI_AWLOCK;
wire [2:0]zed_hdmi_display_M00_AXI_AWPROT;
wire [3:0]zed_hdmi_display_M00_AXI_AWQOS;
wire zed_hdmi_display_M00_AXI_AWREADY;
wire [2:0]zed_hdmi_display_M00_AXI_AWSIZE;
wire zed_hdmi_display_M00_AXI_AWVALID;
wire [5:0]zed_hdmi_display_M00_AXI_BID;
wire zed_hdmi_display_M00_AXI_BREADY;
wire [1:0]zed_hdmi_display_M00_AXI_BRESP;
wire zed_hdmi_display_M00_AXI_BVALID;
wire [63:0]zed_hdmi_display_M00_AXI_RDATA;
wire [5:0]zed_hdmi_display_M00_AXI_RID;
wire zed_hdmi_display_M00_AXI_RLAST;
wire zed_hdmi_display_M00_AXI_RREADY;
wire [1:0]zed_hdmi_display_M00_AXI_RRESP;
wire zed_hdmi_display_M00_AXI_RVALID;
wire [63:0]zed_hdmi_display_M00_AXI_WDATA;
wire [0:0]zed_hdmi_display_M00_AXI_WID;
wire zed_hdmi_display_M00_AXI_WLAST;
wire zed_hdmi_display_M00_AXI_WREADY;
wire [7:0]zed_hdmi_display_M00_AXI_WSTRB;
wire zed_hdmi_display_M00_AXI_WVALID;
wire zed_hdmi_display_hdmio_io_CLK;
wire [15:0]zed_hdmi_display_hdmio_io_DATA;
wire zed_hdmi_display_hdmio_io_DE;
wire zed_hdmi_display_hdmio_io_HSYNC;
wire zed_hdmi_display_hdmio_io_SPDIF;
wire zed_hdmi_display_hdmio_io_VSYNC;
wire zed_hdmi_iic_0_IIC_SCL_I;
wire zed_hdmi_iic_0_IIC_SCL_O;
wire zed_hdmi_iic_0_IIC_SCL_T;
wire zed_hdmi_iic_0_IIC_SDA_I;
wire zed_hdmi_iic_0_IIC_SDA_O;
wire zed_hdmi_iic_0_IIC_SDA_T;
assign hdmio_io_clk = zed_hdmi_display_hdmio_io_CLK;
assign hdmio_io_data[15:0] = zed_hdmi_display_hdmio_io_DATA;
assign hdmio_io_de = zed_hdmi_display_hdmio_io_DE;
assign hdmio_io_hsync = zed_hdmi_display_hdmio_io_HSYNC;
assign hdmio_io_spdif = zed_hdmi_display_hdmio_io_SPDIF;
assign hdmio_io_vsync = zed_hdmi_display_hdmio_io_VSYNC;
assign zed_hdmi_iic_0_IIC_SCL_I = zed_hdmi_iic_scl_i;
assign zed_hdmi_iic_0_IIC_SDA_I = zed_hdmi_iic_sda_i;
assign zed_hdmi_iic_scl_o = zed_hdmi_iic_0_IIC_SCL_O;
assign zed_hdmi_iic_scl_t = zed_hdmi_iic_0_IIC_SCL_T;
assign zed_hdmi_iic_sda_o = zed_hdmi_iic_0_IIC_SDA_O;
assign zed_hdmi_iic_sda_t = zed_hdmi_iic_0_IIC_SDA_T;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
tutorial_clk_wiz_0_0 clk_wiz_0
(.clk_in1(processing_system7_0_FCLK_CLK2),
.clk_out1(hdmio_clk_1));
tutorial_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_CLK1(axi4s_clk_1),
.FCLK_CLK2(processing_system7_0_FCLK_CLK2),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.FCLK_RESET1_N(axi4s_resetn_1),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(axi4s_clk_1),
.M_AXI_GP1_ARADDR(processing_system7_0_M_AXI_GP1_ARADDR),
.M_AXI_GP1_ARBURST(processing_system7_0_M_AXI_GP1_ARBURST),
.M_AXI_GP1_ARCACHE(processing_system7_0_M_AXI_GP1_ARCACHE),
.M_AXI_GP1_ARID(processing_system7_0_M_AXI_GP1_ARID),
.M_AXI_GP1_ARLEN(processing_system7_0_M_AXI_GP1_ARLEN),
.M_AXI_GP1_ARLOCK(processing_system7_0_M_AXI_GP1_ARLOCK),
.M_AXI_GP1_ARPROT(processing_system7_0_M_AXI_GP1_ARPROT),
.M_AXI_GP1_ARQOS(processing_system7_0_M_AXI_GP1_ARQOS),
.M_AXI_GP1_ARREADY(processing_system7_0_M_AXI_GP1_ARREADY),
.M_AXI_GP1_ARSIZE(processing_system7_0_M_AXI_GP1_ARSIZE),
.M_AXI_GP1_ARVALID(processing_system7_0_M_AXI_GP1_ARVALID),
.M_AXI_GP1_AWADDR(processing_system7_0_M_AXI_GP1_AWADDR),
.M_AXI_GP1_AWBURST(processing_system7_0_M_AXI_GP1_AWBURST),
.M_AXI_GP1_AWCACHE(processing_system7_0_M_AXI_GP1_AWCACHE),
.M_AXI_GP1_AWID(processing_system7_0_M_AXI_GP1_AWID),
.M_AXI_GP1_AWLEN(processing_system7_0_M_AXI_GP1_AWLEN),
.M_AXI_GP1_AWLOCK(processing_system7_0_M_AXI_GP1_AWLOCK),
.M_AXI_GP1_AWPROT(processing_system7_0_M_AXI_GP1_AWPROT),
.M_AXI_GP1_AWQOS(processing_system7_0_M_AXI_GP1_AWQOS),
.M_AXI_GP1_AWREADY(processing_system7_0_M_AXI_GP1_AWREADY),
.M_AXI_GP1_AWSIZE(processing_system7_0_M_AXI_GP1_AWSIZE),
.M_AXI_GP1_AWVALID(processing_system7_0_M_AXI_GP1_AWVALID),
.M_AXI_GP1_BID(processing_system7_0_M_AXI_GP1_BID),
.M_AXI_GP1_BREADY(processing_system7_0_M_AXI_GP1_BREADY),
.M_AXI_GP1_BRESP(processing_system7_0_M_AXI_GP1_BRESP),
.M_AXI_GP1_BVALID(processing_system7_0_M_AXI_GP1_BVALID),
.M_AXI_GP1_RDATA(processing_system7_0_M_AXI_GP1_RDATA),
.M_AXI_GP1_RID(processing_system7_0_M_AXI_GP1_RID),
.M_AXI_GP1_RLAST(processing_system7_0_M_AXI_GP1_RLAST),
.M_AXI_GP1_RREADY(processing_system7_0_M_AXI_GP1_RREADY),
.M_AXI_GP1_RRESP(processing_system7_0_M_AXI_GP1_RRESP),
.M_AXI_GP1_RVALID(processing_system7_0_M_AXI_GP1_RVALID),
.M_AXI_GP1_WDATA(processing_system7_0_M_AXI_GP1_WDATA),
.M_AXI_GP1_WID(processing_system7_0_M_AXI_GP1_WID),
.M_AXI_GP1_WLAST(processing_system7_0_M_AXI_GP1_WLAST),
.M_AXI_GP1_WREADY(processing_system7_0_M_AXI_GP1_WREADY),
.M_AXI_GP1_WSTRB(processing_system7_0_M_AXI_GP1_WSTRB),
.M_AXI_GP1_WVALID(processing_system7_0_M_AXI_GP1_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.S_AXI_HP0_ACLK(axi4s_clk_1),
.S_AXI_HP0_ARADDR(zed_hdmi_display_M00_AXI_ARADDR),
.S_AXI_HP0_ARBURST(zed_hdmi_display_M00_AXI_ARBURST),
.S_AXI_HP0_ARCACHE(zed_hdmi_display_M00_AXI_ARCACHE),
.S_AXI_HP0_ARID(zed_hdmi_display_M00_AXI_ARID),
.S_AXI_HP0_ARLEN(zed_hdmi_display_M00_AXI_ARLEN),
.S_AXI_HP0_ARLOCK(zed_hdmi_display_M00_AXI_ARLOCK),
.S_AXI_HP0_ARPROT(zed_hdmi_display_M00_AXI_ARPROT),
.S_AXI_HP0_ARQOS(zed_hdmi_display_M00_AXI_ARQOS),
.S_AXI_HP0_ARREADY(zed_hdmi_display_M00_AXI_ARREADY),
.S_AXI_HP0_ARSIZE(zed_hdmi_display_M00_AXI_ARSIZE),
.S_AXI_HP0_ARVALID(zed_hdmi_display_M00_AXI_ARVALID),
.S_AXI_HP0_AWADDR(zed_hdmi_display_M00_AXI_AWADDR),
.S_AXI_HP0_AWBURST(zed_hdmi_display_M00_AXI_AWBURST),
.S_AXI_HP0_AWCACHE(zed_hdmi_display_M00_AXI_AWCACHE),
.S_AXI_HP0_AWID(zed_hdmi_display_M00_AXI_AWID),
.S_AXI_HP0_AWLEN(zed_hdmi_display_M00_AXI_AWLEN),
.S_AXI_HP0_AWLOCK(zed_hdmi_display_M00_AXI_AWLOCK),
.S_AXI_HP0_AWPROT(zed_hdmi_display_M00_AXI_AWPROT),
.S_AXI_HP0_AWQOS(zed_hdmi_display_M00_AXI_AWQOS),
.S_AXI_HP0_AWREADY(zed_hdmi_display_M00_AXI_AWREADY),
.S_AXI_HP0_AWSIZE(zed_hdmi_display_M00_AXI_AWSIZE),
.S_AXI_HP0_AWVALID(zed_hdmi_display_M00_AXI_AWVALID),
.S_AXI_HP0_BID(zed_hdmi_display_M00_AXI_BID),
.S_AXI_HP0_BREADY(zed_hdmi_display_M00_AXI_BREADY),
.S_AXI_HP0_BRESP(zed_hdmi_display_M00_AXI_BRESP),
.S_AXI_HP0_BVALID(zed_hdmi_display_M00_AXI_BVALID),
.S_AXI_HP0_RDATA(zed_hdmi_display_M00_AXI_RDATA),
.S_AXI_HP0_RDISSUECAP1_EN(GND_1),
.S_AXI_HP0_RID(zed_hdmi_display_M00_AXI_RID),
.S_AXI_HP0_RLAST(zed_hdmi_display_M00_AXI_RLAST),
.S_AXI_HP0_RREADY(zed_hdmi_display_M00_AXI_RREADY),
.S_AXI_HP0_RRESP(zed_hdmi_display_M00_AXI_RRESP),
.S_AXI_HP0_RVALID(zed_hdmi_display_M00_AXI_RVALID),
.S_AXI_HP0_WDATA(zed_hdmi_display_M00_AXI_WDATA),
.S_AXI_HP0_WID(zed_hdmi_display_M00_AXI_WID),
.S_AXI_HP0_WLAST(zed_hdmi_display_M00_AXI_WLAST),
.S_AXI_HP0_WREADY(zed_hdmi_display_M00_AXI_WREADY),
.S_AXI_HP0_WRISSUECAP1_EN(GND_1),
.S_AXI_HP0_WSTRB(zed_hdmi_display_M00_AXI_WSTRB),
.S_AXI_HP0_WVALID(zed_hdmi_display_M00_AXI_WVALID),
.USB0_VBUS_PWRFAULT(GND_1));
tutorial_processing_system7_0_axi_periph_0 processing_system7_0_axi_periph
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.M00_AXI_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.M00_AXI_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.M00_AXI_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.M00_AXI_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.M00_AXI_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.M00_AXI_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.M00_AXI_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.M00_AXI_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.M00_AXI_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.M00_AXI_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.M00_AXI_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.M00_AXI_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.M00_AXI_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.M00_AXI_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.M00_AXI_wstrb(processing_system7_0_axi_periph_M00_AXI_WSTRB),
.M00_AXI_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID),
.M01_ACLK(processing_system7_0_FCLK_CLK0),
.M01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M01_AXI_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.M01_AXI_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.M01_AXI_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.M01_AXI_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.M01_AXI_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.M01_AXI_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.M01_AXI_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.M01_AXI_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.M01_AXI_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.M01_AXI_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.M01_AXI_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.M01_AXI_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.M01_AXI_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.M01_AXI_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.M01_AXI_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.M01_AXI_wstrb(processing_system7_0_axi_periph_M01_AXI_WSTRB),
.M01_AXI_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.M02_ACLK(processing_system7_0_FCLK_CLK0),
.M02_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M02_AXI_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.M02_AXI_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.M02_AXI_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.M02_AXI_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.M02_AXI_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.M02_AXI_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.M02_AXI_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.M02_AXI_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.M02_AXI_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.M02_AXI_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.M02_AXI_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.M02_AXI_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.M02_AXI_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.M02_AXI_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.M02_AXI_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.M02_AXI_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.M03_ACLK(processing_system7_0_FCLK_CLK0),
.M03_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M03_AXI_araddr(processing_system7_0_axi_periph_M03_AXI_ARADDR),
.M03_AXI_arready(processing_system7_0_axi_periph_M03_AXI_ARREADY),
.M03_AXI_arvalid(processing_system7_0_axi_periph_M03_AXI_ARVALID),
.M03_AXI_awaddr(processing_system7_0_axi_periph_M03_AXI_AWADDR),
.M03_AXI_awready(processing_system7_0_axi_periph_M03_AXI_AWREADY),
.M03_AXI_awvalid(processing_system7_0_axi_periph_M03_AXI_AWVALID),
.M03_AXI_bready(processing_system7_0_axi_periph_M03_AXI_BREADY),
.M03_AXI_bresp(processing_system7_0_axi_periph_M03_AXI_BRESP),
.M03_AXI_bvalid(processing_system7_0_axi_periph_M03_AXI_BVALID),
.M03_AXI_rdata(processing_system7_0_axi_periph_M03_AXI_RDATA),
.M03_AXI_rready(processing_system7_0_axi_periph_M03_AXI_RREADY),
.M03_AXI_rresp(processing_system7_0_axi_periph_M03_AXI_RRESP),
.M03_AXI_rvalid(processing_system7_0_axi_periph_M03_AXI_RVALID),
.M03_AXI_wdata(processing_system7_0_axi_periph_M03_AXI_WDATA),
.M03_AXI_wready(processing_system7_0_axi_periph_M03_AXI_WREADY),
.M03_AXI_wstrb(processing_system7_0_axi_periph_M03_AXI_WSTRB),
.M03_AXI_wvalid(processing_system7_0_axi_periph_M03_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
tutorial_processing_system7_0_axi_periph_1_0 processing_system7_0_axi_periph_1
(.ACLK(axi4s_clk_1),
.ARESETN(ARESETN_1),
.M00_ACLK(axi4s_clk_1),
.M00_ARESETN(S00_ARESETN_1),
.M00_AXI_araddr(processing_system7_0_axi_periph_1_M00_AXI_ARADDR),
.M00_AXI_arready(processing_system7_0_axi_periph_1_M00_AXI_ARREADY),
.M00_AXI_arvalid(processing_system7_0_axi_periph_1_M00_AXI_ARVALID),
.M00_AXI_awaddr(processing_system7_0_axi_periph_1_M00_AXI_AWADDR),
.M00_AXI_awready(processing_system7_0_axi_periph_1_M00_AXI_AWREADY),
.M00_AXI_awvalid(processing_system7_0_axi_periph_1_M00_AXI_AWVALID),
.M00_AXI_bready(processing_system7_0_axi_periph_1_M00_AXI_BREADY),
.M00_AXI_bresp(processing_system7_0_axi_periph_1_M00_AXI_BRESP),
.M00_AXI_bvalid(processing_system7_0_axi_periph_1_M00_AXI_BVALID),
.M00_AXI_rdata(processing_system7_0_axi_periph_1_M00_AXI_RDATA),
.M00_AXI_rready(processing_system7_0_axi_periph_1_M00_AXI_RREADY),
.M00_AXI_rresp(processing_system7_0_axi_periph_1_M00_AXI_RRESP),
.M00_AXI_rvalid(processing_system7_0_axi_periph_1_M00_AXI_RVALID),
.M00_AXI_wdata(processing_system7_0_axi_periph_1_M00_AXI_WDATA),
.M00_AXI_wready(processing_system7_0_axi_periph_1_M00_AXI_WREADY),
.M00_AXI_wstrb(processing_system7_0_axi_periph_1_M00_AXI_WSTRB),
.M00_AXI_wvalid(processing_system7_0_axi_periph_1_M00_AXI_WVALID),
.S00_ACLK(axi4s_clk_1),
.S00_ARESETN(S00_ARESETN_1),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP1_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP1_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP1_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP1_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP1_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP1_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP1_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP1_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP1_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP1_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP1_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP1_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP1_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP1_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP1_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP1_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP1_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP1_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP1_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP1_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP1_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP1_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP1_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP1_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP1_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP1_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP1_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP1_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP1_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP1_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP1_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP1_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP1_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP1_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP1_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP1_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP1_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP1_WVALID));
tutorial_rst_processing_system7_0_100M_0 rst_processing_system7_0_76M
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_processing_system7_0_100M_interconnect_aresetn),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
zed_hdmi_display_imp_IWUBG8 zed_hdmi_display
(.M00_AXI_araddr(zed_hdmi_display_M00_AXI_ARADDR),
.M00_AXI_arburst(zed_hdmi_display_M00_AXI_ARBURST),
.M00_AXI_arcache(zed_hdmi_display_M00_AXI_ARCACHE),
.M00_AXI_arid(zed_hdmi_display_M00_AXI_ARID),
.M00_AXI_arlen(zed_hdmi_display_M00_AXI_ARLEN),
.M00_AXI_arlock(zed_hdmi_display_M00_AXI_ARLOCK),
.M00_AXI_arprot(zed_hdmi_display_M00_AXI_ARPROT),
.M00_AXI_arqos(zed_hdmi_display_M00_AXI_ARQOS),
.M00_AXI_arready(zed_hdmi_display_M00_AXI_ARREADY),
.M00_AXI_arsize(zed_hdmi_display_M00_AXI_ARSIZE),
.M00_AXI_arvalid(zed_hdmi_display_M00_AXI_ARVALID),
.M00_AXI_awaddr(zed_hdmi_display_M00_AXI_AWADDR),
.M00_AXI_awburst(zed_hdmi_display_M00_AXI_AWBURST),
.M00_AXI_awcache(zed_hdmi_display_M00_AXI_AWCACHE),
.M00_AXI_awid(zed_hdmi_display_M00_AXI_AWID),
.M00_AXI_awlen(zed_hdmi_display_M00_AXI_AWLEN),
.M00_AXI_awlock(zed_hdmi_display_M00_AXI_AWLOCK),
.M00_AXI_awprot(zed_hdmi_display_M00_AXI_AWPROT),
.M00_AXI_awqos(zed_hdmi_display_M00_AXI_AWQOS),
.M00_AXI_awready(zed_hdmi_display_M00_AXI_AWREADY),
.M00_AXI_awsize(zed_hdmi_display_M00_AXI_AWSIZE),
.M00_AXI_awvalid(zed_hdmi_display_M00_AXI_AWVALID),
.M00_AXI_bid(zed_hdmi_display_M00_AXI_BID[0]),
.M00_AXI_bready(zed_hdmi_display_M00_AXI_BREADY),
.M00_AXI_bresp(zed_hdmi_display_M00_AXI_BRESP),
.M00_AXI_bvalid(zed_hdmi_display_M00_AXI_BVALID),
.M00_AXI_rdata(zed_hdmi_display_M00_AXI_RDATA),
.M00_AXI_rid(zed_hdmi_display_M00_AXI_RID[0]),
.M00_AXI_rlast(zed_hdmi_display_M00_AXI_RLAST),
.M00_AXI_rready(zed_hdmi_display_M00_AXI_RREADY),
.M00_AXI_rresp(zed_hdmi_display_M00_AXI_RRESP),
.M00_AXI_rvalid(zed_hdmi_display_M00_AXI_RVALID),
.M00_AXI_wdata(zed_hdmi_display_M00_AXI_WDATA),
.M00_AXI_wid(zed_hdmi_display_M00_AXI_WID),
.M00_AXI_wlast(zed_hdmi_display_M00_AXI_WLAST),
.M00_AXI_wready(zed_hdmi_display_M00_AXI_WREADY),
.M00_AXI_wstrb(zed_hdmi_display_M00_AXI_WSTRB),
.M00_AXI_wvalid(zed_hdmi_display_M00_AXI_WVALID),
.S_AXI_CONTROL_BUS_araddr(processing_system7_0_axi_periph_1_M00_AXI_ARADDR),
.S_AXI_CONTROL_BUS_arready(processing_system7_0_axi_periph_1_M00_AXI_ARREADY),
.S_AXI_CONTROL_BUS_arvalid(processing_system7_0_axi_periph_1_M00_AXI_ARVALID),
.S_AXI_CONTROL_BUS_awaddr(processing_system7_0_axi_periph_1_M00_AXI_AWADDR),
.S_AXI_CONTROL_BUS_awready(processing_system7_0_axi_periph_1_M00_AXI_AWREADY),
.S_AXI_CONTROL_BUS_awvalid(processing_system7_0_axi_periph_1_M00_AXI_AWVALID),
.S_AXI_CONTROL_BUS_bready(processing_system7_0_axi_periph_1_M00_AXI_BREADY),
.S_AXI_CONTROL_BUS_bresp(processing_system7_0_axi_periph_1_M00_AXI_BRESP),
.S_AXI_CONTROL_BUS_bvalid(processing_system7_0_axi_periph_1_M00_AXI_BVALID),
.S_AXI_CONTROL_BUS_rdata(processing_system7_0_axi_periph_1_M00_AXI_RDATA),
.S_AXI_CONTROL_BUS_rready(processing_system7_0_axi_periph_1_M00_AXI_RREADY),
.S_AXI_CONTROL_BUS_rresp(processing_system7_0_axi_periph_1_M00_AXI_RRESP),
.S_AXI_CONTROL_BUS_rvalid(processing_system7_0_axi_periph_1_M00_AXI_RVALID),
.S_AXI_CONTROL_BUS_wdata(processing_system7_0_axi_periph_1_M00_AXI_WDATA),
.S_AXI_CONTROL_BUS_wready(processing_system7_0_axi_periph_1_M00_AXI_WREADY),
.S_AXI_CONTROL_BUS_wstrb(processing_system7_0_axi_periph_1_M00_AXI_WSTRB),
.S_AXI_CONTROL_BUS_wvalid(processing_system7_0_axi_periph_1_M00_AXI_WVALID),
.axi4lite_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.axi4lite_clk(processing_system7_0_FCLK_CLK0),
.axi4s_clk(axi4s_clk_1),
.axi4s_resetn(axi4s_resetn_1),
.ctrl_araddr(processing_system7_0_axi_periph_M03_AXI_ARADDR),
.ctrl_arready(processing_system7_0_axi_periph_M03_AXI_ARREADY),
.ctrl_arvalid(processing_system7_0_axi_periph_M03_AXI_ARVALID),
.ctrl_awaddr(processing_system7_0_axi_periph_M03_AXI_AWADDR),
.ctrl_awready(processing_system7_0_axi_periph_M03_AXI_AWREADY),
.ctrl_awvalid(processing_system7_0_axi_periph_M03_AXI_AWVALID),
.ctrl_bready(processing_system7_0_axi_periph_M03_AXI_BREADY),
.ctrl_bresp(processing_system7_0_axi_periph_M03_AXI_BRESP),
.ctrl_bvalid(processing_system7_0_axi_periph_M03_AXI_BVALID),
.ctrl_rdata(processing_system7_0_axi_periph_M03_AXI_RDATA),
.ctrl_rready(processing_system7_0_axi_periph_M03_AXI_RREADY),
.ctrl_rresp(processing_system7_0_axi_periph_M03_AXI_RRESP),
.ctrl_rvalid(processing_system7_0_axi_periph_M03_AXI_RVALID),
.ctrl_wdata(processing_system7_0_axi_periph_M03_AXI_WDATA),
.ctrl_wready(processing_system7_0_axi_periph_M03_AXI_WREADY),
.ctrl_wstrb(processing_system7_0_axi_periph_M03_AXI_WSTRB),
.ctrl_wvalid(processing_system7_0_axi_periph_M03_AXI_WVALID),
.hdmio_clk(hdmio_clk_1),
.hdmio_io_clk(zed_hdmi_display_hdmio_io_CLK),
.hdmio_io_data(zed_hdmi_display_hdmio_io_DATA),
.hdmio_io_de(zed_hdmi_display_hdmio_io_DE),
.hdmio_io_hsync(zed_hdmi_display_hdmio_io_HSYNC),
.hdmio_io_spdif(zed_hdmi_display_hdmio_io_SPDIF),
.hdmio_io_vsync(zed_hdmi_display_hdmio_io_VSYNC),
.interconnect_aresetn(ARESETN_1),
.peripheral_aresetn(S00_ARESETN_1),
.vdma_ctrl_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.vdma_ctrl_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.vdma_ctrl_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.vdma_ctrl_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.vdma_ctrl_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.vdma_ctrl_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.vdma_ctrl_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.vdma_ctrl_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.vdma_ctrl_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.vdma_ctrl_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.vdma_ctrl_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.vdma_ctrl_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.vdma_ctrl_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.vdma_ctrl_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.vdma_ctrl_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.vdma_ctrl_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.vtc_ctrl_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.vtc_ctrl_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.vtc_ctrl_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.vtc_ctrl_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.vtc_ctrl_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.vtc_ctrl_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.vtc_ctrl_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.vtc_ctrl_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.vtc_ctrl_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.vtc_ctrl_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.vtc_ctrl_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.vtc_ctrl_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.vtc_ctrl_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.vtc_ctrl_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.vtc_ctrl_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.vtc_ctrl_wstrb(processing_system7_0_axi_periph_M01_AXI_WSTRB),
.vtc_ctrl_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID));
tutorial_axi_iic_0_0 zed_hdmi_iic_0
(.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M00_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID),
.scl_i(zed_hdmi_iic_0_IIC_SCL_I),
.scl_o(zed_hdmi_iic_0_IIC_SCL_O),
.scl_t(zed_hdmi_iic_0_IIC_SCL_T),
.sda_i(zed_hdmi_iic_0_IIC_SDA_I),
.sda_o(zed_hdmi_iic_0_IIC_SDA_O),
.sda_t(zed_hdmi_iic_0_IIC_SDA_T));
endmodule
module tutorial_axi_mem_intercon_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arid,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awid,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rid,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wid,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arlen,
S00_AXI_arprot,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_rdata,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S01_ACLK,
S01_ARESETN,
S01_AXI_araddr,
S01_AXI_arburst,
S01_AXI_arcache,
S01_AXI_arid,
S01_AXI_arlen,
S01_AXI_arlock,
S01_AXI_arprot,
S01_AXI_arqos,
S01_AXI_arready,
S01_AXI_arsize,
S01_AXI_arvalid,
S01_AXI_awaddr,
S01_AXI_awburst,
S01_AXI_awcache,
S01_AXI_awid,
S01_AXI_awlen,
S01_AXI_awlock,
S01_AXI_awprot,
S01_AXI_awqos,
S01_AXI_awready,
S01_AXI_awsize,
S01_AXI_awvalid,
S01_AXI_bid,
S01_AXI_bready,
S01_AXI_bresp,
S01_AXI_bvalid,
S01_AXI_rdata,
S01_AXI_rid,
S01_AXI_rlast,
S01_AXI_rready,
S01_AXI_rresp,
S01_AXI_rvalid,
S01_AXI_wdata,
S01_AXI_wlast,
S01_AXI_wready,
S01_AXI_wstrb,
S01_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [31:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [0:0]M00_AXI_arid;
output [3:0]M00_AXI_arlen;
output [1:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
output [3:0]M00_AXI_arqos;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [0:0]M00_AXI_awid;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
input [0:0]M00_AXI_bid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [63:0]M00_AXI_rdata;
input [0:0]M00_AXI_rid;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [63:0]M00_AXI_wdata;
output [0:0]M00_AXI_wid;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [7:0]S00_AXI_arlen;
input [2:0]S00_AXI_arprot;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
output [63:0]S00_AXI_rdata;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input S01_ACLK;
input [0:0]S01_ARESETN;
input S01_AXI_araddr;
input S01_AXI_arburst;
input S01_AXI_arcache;
input S01_AXI_arid;
input S01_AXI_arlen;
input S01_AXI_arlock;
input S01_AXI_arprot;
input S01_AXI_arqos;
output S01_AXI_arready;
input S01_AXI_arsize;
input S01_AXI_arvalid;
input S01_AXI_awaddr;
input S01_AXI_awburst;
input S01_AXI_awcache;
input S01_AXI_awid;
input S01_AXI_awlen;
input S01_AXI_awlock;
input S01_AXI_awprot;
input S01_AXI_awqos;
output S01_AXI_awready;
input S01_AXI_awsize;
input S01_AXI_awvalid;
output S01_AXI_bid;
input S01_AXI_bready;
output S01_AXI_bresp;
output S01_AXI_bvalid;
output S01_AXI_rdata;
output S01_AXI_rid;
output S01_AXI_rlast;
input S01_AXI_rready;
output S01_AXI_rresp;
output S01_AXI_rvalid;
input S01_AXI_wdata;
input S01_AXI_wlast;
output S01_AXI_wready;
input S01_AXI_wstrb;
input S01_AXI_wvalid;
wire GND_1;
wire M00_ACLK_1;
wire [0:0]M00_ARESETN_1;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire S01_ACLK_1;
wire [0:0]S01_ARESETN_1;
wire VCC_1;
wire axi_mem_intercon_ACLK_net;
wire [0:0]axi_mem_intercon_ARESETN_net;
wire [31:0]axi_mem_intercon_to_s00_couplers_ARADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_ARBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_ARCACHE;
wire [7:0]axi_mem_intercon_to_s00_couplers_ARLEN;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARPROT;
wire axi_mem_intercon_to_s00_couplers_ARREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARSIZE;
wire axi_mem_intercon_to_s00_couplers_ARVALID;
wire [63:0]axi_mem_intercon_to_s00_couplers_RDATA;
wire axi_mem_intercon_to_s00_couplers_RLAST;
wire axi_mem_intercon_to_s00_couplers_RREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_RRESP;
wire axi_mem_intercon_to_s00_couplers_RVALID;
wire axi_mem_intercon_to_s01_couplers_ARADDR;
wire axi_mem_intercon_to_s01_couplers_ARBURST;
wire axi_mem_intercon_to_s01_couplers_ARCACHE;
wire axi_mem_intercon_to_s01_couplers_ARID;
wire axi_mem_intercon_to_s01_couplers_ARLEN;
wire axi_mem_intercon_to_s01_couplers_ARLOCK;
wire axi_mem_intercon_to_s01_couplers_ARPROT;
wire axi_mem_intercon_to_s01_couplers_ARQOS;
wire axi_mem_intercon_to_s01_couplers_ARREADY;
wire axi_mem_intercon_to_s01_couplers_ARSIZE;
wire axi_mem_intercon_to_s01_couplers_ARVALID;
wire axi_mem_intercon_to_s01_couplers_AWADDR;
wire axi_mem_intercon_to_s01_couplers_AWBURST;
wire axi_mem_intercon_to_s01_couplers_AWCACHE;
wire axi_mem_intercon_to_s01_couplers_AWID;
wire axi_mem_intercon_to_s01_couplers_AWLEN;
wire axi_mem_intercon_to_s01_couplers_AWLOCK;
wire axi_mem_intercon_to_s01_couplers_AWPROT;
wire axi_mem_intercon_to_s01_couplers_AWQOS;
wire axi_mem_intercon_to_s01_couplers_AWREADY;
wire axi_mem_intercon_to_s01_couplers_AWSIZE;
wire axi_mem_intercon_to_s01_couplers_AWVALID;
wire axi_mem_intercon_to_s01_couplers_BID;
wire axi_mem_intercon_to_s01_couplers_BREADY;
wire axi_mem_intercon_to_s01_couplers_BRESP;
wire axi_mem_intercon_to_s01_couplers_BVALID;
wire axi_mem_intercon_to_s01_couplers_RDATA;
wire axi_mem_intercon_to_s01_couplers_RID;
wire axi_mem_intercon_to_s01_couplers_RLAST;
wire axi_mem_intercon_to_s01_couplers_RREADY;
wire axi_mem_intercon_to_s01_couplers_RRESP;
wire axi_mem_intercon_to_s01_couplers_RVALID;
wire axi_mem_intercon_to_s01_couplers_WDATA;
wire axi_mem_intercon_to_s01_couplers_WLAST;
wire axi_mem_intercon_to_s01_couplers_WREADY;
wire axi_mem_intercon_to_s01_couplers_WSTRB;
wire axi_mem_intercon_to_s01_couplers_WVALID;
wire [31:0]m00_couplers_to_axi_mem_intercon_ARADDR;
wire [1:0]m00_couplers_to_axi_mem_intercon_ARBURST;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARCACHE;
wire [0:0]m00_couplers_to_axi_mem_intercon_ARID;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARLEN;
wire [1:0]m00_couplers_to_axi_mem_intercon_ARLOCK;
wire [2:0]m00_couplers_to_axi_mem_intercon_ARPROT;
wire [3:0]m00_couplers_to_axi_mem_intercon_ARQOS;
wire m00_couplers_to_axi_mem_intercon_ARREADY;
wire [2:0]m00_couplers_to_axi_mem_intercon_ARSIZE;
wire m00_couplers_to_axi_mem_intercon_ARVALID;
wire [31:0]m00_couplers_to_axi_mem_intercon_AWADDR;
wire [1:0]m00_couplers_to_axi_mem_intercon_AWBURST;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWCACHE;
wire [0:0]m00_couplers_to_axi_mem_intercon_AWID;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWLEN;
wire [1:0]m00_couplers_to_axi_mem_intercon_AWLOCK;
wire [2:0]m00_couplers_to_axi_mem_intercon_AWPROT;
wire [3:0]m00_couplers_to_axi_mem_intercon_AWQOS;
wire m00_couplers_to_axi_mem_intercon_AWREADY;
wire [2:0]m00_couplers_to_axi_mem_intercon_AWSIZE;
wire m00_couplers_to_axi_mem_intercon_AWVALID;
wire [0:0]m00_couplers_to_axi_mem_intercon_BID;
wire m00_couplers_to_axi_mem_intercon_BREADY;
wire [1:0]m00_couplers_to_axi_mem_intercon_BRESP;
wire m00_couplers_to_axi_mem_intercon_BVALID;
wire [63:0]m00_couplers_to_axi_mem_intercon_RDATA;
wire [0:0]m00_couplers_to_axi_mem_intercon_RID;
wire m00_couplers_to_axi_mem_intercon_RLAST;
wire m00_couplers_to_axi_mem_intercon_RREADY;
wire [1:0]m00_couplers_to_axi_mem_intercon_RRESP;
wire m00_couplers_to_axi_mem_intercon_RVALID;
wire [63:0]m00_couplers_to_axi_mem_intercon_WDATA;
wire [0:0]m00_couplers_to_axi_mem_intercon_WID;
wire m00_couplers_to_axi_mem_intercon_WLAST;
wire m00_couplers_to_axi_mem_intercon_WREADY;
wire [7:0]m00_couplers_to_axi_mem_intercon_WSTRB;
wire m00_couplers_to_axi_mem_intercon_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [1:0]s00_couplers_to_xbar_ARBURST;
wire [3:0]s00_couplers_to_xbar_ARCACHE;
wire [7:0]s00_couplers_to_xbar_ARLEN;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire [2:0]s00_couplers_to_xbar_ARSIZE;
wire s00_couplers_to_xbar_ARVALID;
wire [63:0]s00_couplers_to_xbar_RDATA;
wire [0:0]s00_couplers_to_xbar_RLAST;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire s01_couplers_to_xbar_ARADDR;
wire s01_couplers_to_xbar_ARBURST;
wire s01_couplers_to_xbar_ARCACHE;
wire s01_couplers_to_xbar_ARID;
wire s01_couplers_to_xbar_ARLEN;
wire s01_couplers_to_xbar_ARLOCK;
wire s01_couplers_to_xbar_ARPROT;
wire s01_couplers_to_xbar_ARQOS;
wire [1:1]s01_couplers_to_xbar_ARREADY;
wire s01_couplers_to_xbar_ARSIZE;
wire s01_couplers_to_xbar_ARVALID;
wire s01_couplers_to_xbar_AWADDR;
wire s01_couplers_to_xbar_AWBURST;
wire s01_couplers_to_xbar_AWCACHE;
wire s01_couplers_to_xbar_AWID;
wire s01_couplers_to_xbar_AWLEN;
wire s01_couplers_to_xbar_AWLOCK;
wire s01_couplers_to_xbar_AWPROT;
wire s01_couplers_to_xbar_AWQOS;
wire [1:1]s01_couplers_to_xbar_AWREADY;
wire s01_couplers_to_xbar_AWSIZE;
wire s01_couplers_to_xbar_AWVALID;
wire [1:1]s01_couplers_to_xbar_BID;
wire s01_couplers_to_xbar_BREADY;
wire [3:2]s01_couplers_to_xbar_BRESP;
wire [1:1]s01_couplers_to_xbar_BVALID;
wire [127:64]s01_couplers_to_xbar_RDATA;
wire [1:1]s01_couplers_to_xbar_RID;
wire [1:1]s01_couplers_to_xbar_RLAST;
wire s01_couplers_to_xbar_RREADY;
wire [3:2]s01_couplers_to_xbar_RRESP;
wire [1:1]s01_couplers_to_xbar_RVALID;
wire s01_couplers_to_xbar_WDATA;
wire s01_couplers_to_xbar_WLAST;
wire [1:1]s01_couplers_to_xbar_WREADY;
wire s01_couplers_to_xbar_WSTRB;
wire s01_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [1:0]xbar_to_m00_couplers_ARBURST;
wire [3:0]xbar_to_m00_couplers_ARCACHE;
wire [0:0]xbar_to_m00_couplers_ARID;
wire [7:0]xbar_to_m00_couplers_ARLEN;
wire [0:0]xbar_to_m00_couplers_ARLOCK;
wire [2:0]xbar_to_m00_couplers_ARPROT;
wire [3:0]xbar_to_m00_couplers_ARQOS;
wire xbar_to_m00_couplers_ARREADY;
wire [3:0]xbar_to_m00_couplers_ARREGION;
wire [2:0]xbar_to_m00_couplers_ARSIZE;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [1:0]xbar_to_m00_couplers_AWBURST;
wire [3:0]xbar_to_m00_couplers_AWCACHE;
wire [0:0]xbar_to_m00_couplers_AWID;
wire [7:0]xbar_to_m00_couplers_AWLEN;
wire [0:0]xbar_to_m00_couplers_AWLOCK;
wire [2:0]xbar_to_m00_couplers_AWPROT;
wire [3:0]xbar_to_m00_couplers_AWQOS;
wire xbar_to_m00_couplers_AWREADY;
wire [3:0]xbar_to_m00_couplers_AWREGION;
wire [2:0]xbar_to_m00_couplers_AWSIZE;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire xbar_to_m00_couplers_BVALID;
wire [63:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RID;
wire xbar_to_m00_couplers_RLAST;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire xbar_to_m00_couplers_RVALID;
wire [63:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WLAST;
wire xbar_to_m00_couplers_WREADY;
wire [7:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [1:0]NLW_xbar_s_axi_awready_UNCONNECTED;
wire [1:0]NLW_xbar_s_axi_bid_UNCONNECTED;
wire [3:0]NLW_xbar_s_axi_bresp_UNCONNECTED;
wire [1:0]NLW_xbar_s_axi_bvalid_UNCONNECTED;
wire [1:0]NLW_xbar_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_xbar_s_axi_wready_UNCONNECTED;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN[0];
assign M00_AXI_araddr[31:0] = m00_couplers_to_axi_mem_intercon_ARADDR;
assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_mem_intercon_ARBURST;
assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_mem_intercon_ARCACHE;
assign M00_AXI_arid[0] = m00_couplers_to_axi_mem_intercon_ARID;
assign M00_AXI_arlen[3:0] = m00_couplers_to_axi_mem_intercon_ARLEN;
assign M00_AXI_arlock[1:0] = m00_couplers_to_axi_mem_intercon_ARLOCK;
assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_mem_intercon_ARPROT;
assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_mem_intercon_ARQOS;
assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_mem_intercon_ARSIZE;
assign M00_AXI_arvalid = m00_couplers_to_axi_mem_intercon_ARVALID;
assign M00_AXI_awaddr[31:0] = m00_couplers_to_axi_mem_intercon_AWADDR;
assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_mem_intercon_AWBURST;
assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_mem_intercon_AWCACHE;
assign M00_AXI_awid[0] = m00_couplers_to_axi_mem_intercon_AWID;
assign M00_AXI_awlen[3:0] = m00_couplers_to_axi_mem_intercon_AWLEN;
assign M00_AXI_awlock[1:0] = m00_couplers_to_axi_mem_intercon_AWLOCK;
assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_mem_intercon_AWPROT;
assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_mem_intercon_AWQOS;
assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_mem_intercon_AWSIZE;
assign M00_AXI_awvalid = m00_couplers_to_axi_mem_intercon_AWVALID;
assign M00_AXI_bready = m00_couplers_to_axi_mem_intercon_BREADY;
assign M00_AXI_rready = m00_couplers_to_axi_mem_intercon_RREADY;
assign M00_AXI_wdata[63:0] = m00_couplers_to_axi_mem_intercon_WDATA;
assign M00_AXI_wid[0] = m00_couplers_to_axi_mem_intercon_WID;
assign M00_AXI_wlast = m00_couplers_to_axi_mem_intercon_WLAST;
assign M00_AXI_wstrb[7:0] = m00_couplers_to_axi_mem_intercon_WSTRB;
assign M00_AXI_wvalid = m00_couplers_to_axi_mem_intercon_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = axi_mem_intercon_to_s00_couplers_ARREADY;
assign S00_AXI_rdata[63:0] = axi_mem_intercon_to_s00_couplers_RDATA;
assign S00_AXI_rlast = axi_mem_intercon_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_mem_intercon_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_mem_intercon_to_s00_couplers_RVALID;
assign S01_ACLK_1 = S01_ACLK;
assign S01_ARESETN_1 = S01_ARESETN[0];
assign S01_AXI_arready = axi_mem_intercon_to_s01_couplers_ARREADY;
assign S01_AXI_awready = axi_mem_intercon_to_s01_couplers_AWREADY;
assign S01_AXI_bid = axi_mem_intercon_to_s01_couplers_BID;
assign S01_AXI_bresp = axi_mem_intercon_to_s01_couplers_BRESP;
assign S01_AXI_bvalid = axi_mem_intercon_to_s01_couplers_BVALID;
assign S01_AXI_rdata = axi_mem_intercon_to_s01_couplers_RDATA;
assign S01_AXI_rid = axi_mem_intercon_to_s01_couplers_RID;
assign S01_AXI_rlast = axi_mem_intercon_to_s01_couplers_RLAST;
assign S01_AXI_rresp = axi_mem_intercon_to_s01_couplers_RRESP;
assign S01_AXI_rvalid = axi_mem_intercon_to_s01_couplers_RVALID;
assign S01_AXI_wready = axi_mem_intercon_to_s01_couplers_WREADY;
assign axi_mem_intercon_ACLK_net = ACLK;
assign axi_mem_intercon_ARESETN_net = ARESETN[0];
assign axi_mem_intercon_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_mem_intercon_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_mem_intercon_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_mem_intercon_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];
assign axi_mem_intercon_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_mem_intercon_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_mem_intercon_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_mem_intercon_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_mem_intercon_to_s01_couplers_ARADDR = S01_AXI_araddr;
assign axi_mem_intercon_to_s01_couplers_ARBURST = S01_AXI_arburst;
assign axi_mem_intercon_to_s01_couplers_ARCACHE = S01_AXI_arcache;
assign axi_mem_intercon_to_s01_couplers_ARID = S01_AXI_arid;
assign axi_mem_intercon_to_s01_couplers_ARLEN = S01_AXI_arlen;
assign axi_mem_intercon_to_s01_couplers_ARLOCK = S01_AXI_arlock;
assign axi_mem_intercon_to_s01_couplers_ARPROT = S01_AXI_arprot;
assign axi_mem_intercon_to_s01_couplers_ARQOS = S01_AXI_arqos;
assign axi_mem_intercon_to_s01_couplers_ARSIZE = S01_AXI_arsize;
assign axi_mem_intercon_to_s01_couplers_ARVALID = S01_AXI_arvalid;
assign axi_mem_intercon_to_s01_couplers_AWADDR = S01_AXI_awaddr;
assign axi_mem_intercon_to_s01_couplers_AWBURST = S01_AXI_awburst;
assign axi_mem_intercon_to_s01_couplers_AWCACHE = S01_AXI_awcache;
assign axi_mem_intercon_to_s01_couplers_AWID = S01_AXI_awid;
assign axi_mem_intercon_to_s01_couplers_AWLEN = S01_AXI_awlen;
assign axi_mem_intercon_to_s01_couplers_AWLOCK = S01_AXI_awlock;
assign axi_mem_intercon_to_s01_couplers_AWPROT = S01_AXI_awprot;
assign axi_mem_intercon_to_s01_couplers_AWQOS = S01_AXI_awqos;
assign axi_mem_intercon_to_s01_couplers_AWSIZE = S01_AXI_awsize;
assign axi_mem_intercon_to_s01_couplers_AWVALID = S01_AXI_awvalid;
assign axi_mem_intercon_to_s01_couplers_BREADY = S01_AXI_bready;
assign axi_mem_intercon_to_s01_couplers_RREADY = S01_AXI_rready;
assign axi_mem_intercon_to_s01_couplers_WDATA = S01_AXI_wdata;
assign axi_mem_intercon_to_s01_couplers_WLAST = S01_AXI_wlast;
assign axi_mem_intercon_to_s01_couplers_WSTRB = S01_AXI_wstrb;
assign axi_mem_intercon_to_s01_couplers_WVALID = S01_AXI_wvalid;
assign m00_couplers_to_axi_mem_intercon_ARREADY = M00_AXI_arready;
assign m00_couplers_to_axi_mem_intercon_AWREADY = M00_AXI_awready;
assign m00_couplers_to_axi_mem_intercon_BID = M00_AXI_bid[0];
assign m00_couplers_to_axi_mem_intercon_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_axi_mem_intercon_BVALID = M00_AXI_bvalid;
assign m00_couplers_to_axi_mem_intercon_RDATA = M00_AXI_rdata[63:0];
assign m00_couplers_to_axi_mem_intercon_RID = M00_AXI_rid[0];
assign m00_couplers_to_axi_mem_intercon_RLAST = M00_AXI_rlast;
assign m00_couplers_to_axi_mem_intercon_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_axi_mem_intercon_RVALID = M00_AXI_rvalid;
assign m00_couplers_to_axi_mem_intercon_WREADY = M00_AXI_wready;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
m00_couplers_imp_MNAJMW m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_axi_mem_intercon_ARADDR),
.M_AXI_arburst(m00_couplers_to_axi_mem_intercon_ARBURST),
.M_AXI_arcache(m00_couplers_to_axi_mem_intercon_ARCACHE),
.M_AXI_arid(m00_couplers_to_axi_mem_intercon_ARID),
.M_AXI_arlen(m00_couplers_to_axi_mem_intercon_ARLEN),
.M_AXI_arlock(m00_couplers_to_axi_mem_intercon_ARLOCK),
.M_AXI_arprot(m00_couplers_to_axi_mem_intercon_ARPROT),
.M_AXI_arqos(m00_couplers_to_axi_mem_intercon_ARQOS),
.M_AXI_arready(m00_couplers_to_axi_mem_intercon_ARREADY),
.M_AXI_arsize(m00_couplers_to_axi_mem_intercon_ARSIZE),
.M_AXI_arvalid(m00_couplers_to_axi_mem_intercon_ARVALID),
.M_AXI_awaddr(m00_couplers_to_axi_mem_intercon_AWADDR),
.M_AXI_awburst(m00_couplers_to_axi_mem_intercon_AWBURST),
.M_AXI_awcache(m00_couplers_to_axi_mem_intercon_AWCACHE),
.M_AXI_awid(m00_couplers_to_axi_mem_intercon_AWID),
.M_AXI_awlen(m00_couplers_to_axi_mem_intercon_AWLEN),
.M_AXI_awlock(m00_couplers_to_axi_mem_intercon_AWLOCK),
.M_AXI_awprot(m00_couplers_to_axi_mem_intercon_AWPROT),
.M_AXI_awqos(m00_couplers_to_axi_mem_intercon_AWQOS),
.M_AXI_awready(m00_couplers_to_axi_mem_intercon_AWREADY),
.M_AXI_awsize(m00_couplers_to_axi_mem_intercon_AWSIZE),
.M_AXI_awvalid(m00_couplers_to_axi_mem_intercon_AWVALID),
.M_AXI_bid(m00_couplers_to_axi_mem_intercon_BID),
.M_AXI_bready(m00_couplers_to_axi_mem_intercon_BREADY),
.M_AXI_bresp(m00_couplers_to_axi_mem_intercon_BRESP),
.M_AXI_bvalid(m00_couplers_to_axi_mem_intercon_BVALID),
.M_AXI_rdata(m00_couplers_to_axi_mem_intercon_RDATA),
.M_AXI_rid(m00_couplers_to_axi_mem_intercon_RID),
.M_AXI_rlast(m00_couplers_to_axi_mem_intercon_RLAST),
.M_AXI_rready(m00_couplers_to_axi_mem_intercon_RREADY),
.M_AXI_rresp(m00_couplers_to_axi_mem_intercon_RRESP),
.M_AXI_rvalid(m00_couplers_to_axi_mem_intercon_RVALID),
.M_AXI_wdata(m00_couplers_to_axi_mem_intercon_WDATA),
.M_AXI_wid(m00_couplers_to_axi_mem_intercon_WID),
.M_AXI_wlast(m00_couplers_to_axi_mem_intercon_WLAST),
.M_AXI_wready(m00_couplers_to_axi_mem_intercon_WREADY),
.M_AXI_wstrb(m00_couplers_to_axi_mem_intercon_WSTRB),
.M_AXI_wvalid(m00_couplers_to_axi_mem_intercon_WVALID),
.S_ACLK(axi_mem_intercon_ACLK_net),
.S_ARESETN(axi_mem_intercon_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR),
.S_AXI_arburst(xbar_to_m00_couplers_ARBURST),
.S_AXI_arcache(xbar_to_m00_couplers_ARCACHE),
.S_AXI_arid(xbar_to_m00_couplers_ARID),
.S_AXI_arlen(xbar_to_m00_couplers_ARLEN),
.S_AXI_arlock(xbar_to_m00_couplers_ARLOCK),
.S_AXI_arprot(xbar_to_m00_couplers_ARPROT),
.S_AXI_arqos(xbar_to_m00_couplers_ARQOS),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arregion(xbar_to_m00_couplers_ARREGION),
.S_AXI_arsize(xbar_to_m00_couplers_ARSIZE),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR),
.S_AXI_awburst(xbar_to_m00_couplers_AWBURST),
.S_AXI_awcache(xbar_to_m00_couplers_AWCACHE),
.S_AXI_awid(xbar_to_m00_couplers_AWID),
.S_AXI_awlen(xbar_to_m00_couplers_AWLEN),
.S_AXI_awlock(xbar_to_m00_couplers_AWLOCK),
.S_AXI_awprot(xbar_to_m00_couplers_AWPROT),
.S_AXI_awqos(xbar_to_m00_couplers_AWQOS),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awregion(xbar_to_m00_couplers_AWREGION),
.S_AXI_awsize(xbar_to_m00_couplers_AWSIZE),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bid(xbar_to_m00_couplers_BID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rid(xbar_to_m00_couplers_RID),
.S_AXI_rlast(xbar_to_m00_couplers_RLAST),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wlast(xbar_to_m00_couplers_WLAST),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
s00_couplers_imp_1ASF99M s00_couplers
(.M_ACLK(axi_mem_intercon_ACLK_net),
.M_ARESETN(axi_mem_intercon_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s00_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s00_couplers_to_xbar_ARCACHE),
.M_AXI_arlen(s00_couplers_to_xbar_ARLEN),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s00_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rlast(s00_couplers_to_xbar_RLAST),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(axi_mem_intercon_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_mem_intercon_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_mem_intercon_to_s00_couplers_ARCACHE),
.S_AXI_arlen(axi_mem_intercon_to_s00_couplers_ARLEN),
.S_AXI_arprot(axi_mem_intercon_to_s00_couplers_ARPROT),
.S_AXI_arready(axi_mem_intercon_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_mem_intercon_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_mem_intercon_to_s00_couplers_ARVALID),
.S_AXI_rdata(axi_mem_intercon_to_s00_couplers_RDATA),
.S_AXI_rlast(axi_mem_intercon_to_s00_couplers_RLAST),
.S_AXI_rready(axi_mem_intercon_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_mem_intercon_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_mem_intercon_to_s00_couplers_RVALID));
s01_couplers_imp_JYOW23 s01_couplers
(.M_ACLK(axi_mem_intercon_ACLK_net),
.M_ARESETN(axi_mem_intercon_ARESETN_net),
.M_AXI_araddr(s01_couplers_to_xbar_ARADDR),
.M_AXI_arburst(s01_couplers_to_xbar_ARBURST),
.M_AXI_arcache(s01_couplers_to_xbar_ARCACHE),
.M_AXI_arid(s01_couplers_to_xbar_ARID),
.M_AXI_arlen(s01_couplers_to_xbar_ARLEN),
.M_AXI_arlock(s01_couplers_to_xbar_ARLOCK),
.M_AXI_arprot(s01_couplers_to_xbar_ARPROT),
.M_AXI_arqos(s01_couplers_to_xbar_ARQOS),
.M_AXI_arready(s01_couplers_to_xbar_ARREADY),
.M_AXI_arsize(s01_couplers_to_xbar_ARSIZE),
.M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),
.M_AXI_awburst(s01_couplers_to_xbar_AWBURST),
.M_AXI_awcache(s01_couplers_to_xbar_AWCACHE),
.M_AXI_awid(s01_couplers_to_xbar_AWID),
.M_AXI_awlen(s01_couplers_to_xbar_AWLEN),
.M_AXI_awlock(s01_couplers_to_xbar_AWLOCK),
.M_AXI_awprot(s01_couplers_to_xbar_AWPROT),
.M_AXI_awqos(s01_couplers_to_xbar_AWQOS),
.M_AXI_awready(s01_couplers_to_xbar_AWREADY),
.M_AXI_awsize(s01_couplers_to_xbar_AWSIZE),
.M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),
.M_AXI_bid(s01_couplers_to_xbar_BID),
.M_AXI_bready(s01_couplers_to_xbar_BREADY),
.M_AXI_bresp(s01_couplers_to_xbar_BRESP[2]),
.M_AXI_bvalid(s01_couplers_to_xbar_BVALID),
.M_AXI_rdata(s01_couplers_to_xbar_RDATA[64]),
.M_AXI_rid(s01_couplers_to_xbar_RID),
.M_AXI_rlast(s01_couplers_to_xbar_RLAST),
.M_AXI_rready(s01_couplers_to_xbar_RREADY),
.M_AXI_rresp(s01_couplers_to_xbar_RRESP[2]),
.M_AXI_rvalid(s01_couplers_to_xbar_RVALID),
.M_AXI_wdata(s01_couplers_to_xbar_WDATA),
.M_AXI_wlast(s01_couplers_to_xbar_WLAST),
.M_AXI_wready(s01_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s01_couplers_to_xbar_WVALID),
.S_ACLK(S01_ACLK_1),
.S_ARESETN(S01_ARESETN_1),
.S_AXI_araddr(axi_mem_intercon_to_s01_couplers_ARADDR),
.S_AXI_arburst(axi_mem_intercon_to_s01_couplers_ARBURST),
.S_AXI_arcache(axi_mem_intercon_to_s01_couplers_ARCACHE),
.S_AXI_arid(axi_mem_intercon_to_s01_couplers_ARID),
.S_AXI_arlen(axi_mem_intercon_to_s01_couplers_ARLEN),
.S_AXI_arlock(axi_mem_intercon_to_s01_couplers_ARLOCK),
.S_AXI_arprot(axi_mem_intercon_to_s01_couplers_ARPROT),
.S_AXI_arqos(axi_mem_intercon_to_s01_couplers_ARQOS),
.S_AXI_arready(axi_mem_intercon_to_s01_couplers_ARREADY),
.S_AXI_arsize(axi_mem_intercon_to_s01_couplers_ARSIZE),
.S_AXI_arvalid(axi_mem_intercon_to_s01_couplers_ARVALID),
.S_AXI_awaddr(axi_mem_intercon_to_s01_couplers_AWADDR),
.S_AXI_awburst(axi_mem_intercon_to_s01_couplers_AWBURST),
.S_AXI_awcache(axi_mem_intercon_to_s01_couplers_AWCACHE),
.S_AXI_awid(axi_mem_intercon_to_s01_couplers_AWID),
.S_AXI_awlen(axi_mem_intercon_to_s01_couplers_AWLEN),
.S_AXI_awlock(axi_mem_intercon_to_s01_couplers_AWLOCK),
.S_AXI_awprot(axi_mem_intercon_to_s01_couplers_AWPROT),
.S_AXI_awqos(axi_mem_intercon_to_s01_couplers_AWQOS),
.S_AXI_awready(axi_mem_intercon_to_s01_couplers_AWREADY),
.S_AXI_awsize(axi_mem_intercon_to_s01_couplers_AWSIZE),
.S_AXI_awvalid(axi_mem_intercon_to_s01_couplers_AWVALID),
.S_AXI_bid(axi_mem_intercon_to_s01_couplers_BID),
.S_AXI_bready(axi_mem_intercon_to_s01_couplers_BREADY),
.S_AXI_bresp(axi_mem_intercon_to_s01_couplers_BRESP),
.S_AXI_bvalid(axi_mem_intercon_to_s01_couplers_BVALID),
.S_AXI_rdata(axi_mem_intercon_to_s01_couplers_RDATA),
.S_AXI_rid(axi_mem_intercon_to_s01_couplers_RID),
.S_AXI_rlast(axi_mem_intercon_to_s01_couplers_RLAST),
.S_AXI_rready(axi_mem_intercon_to_s01_couplers_RREADY),
.S_AXI_rresp(axi_mem_intercon_to_s01_couplers_RRESP),
.S_AXI_rvalid(axi_mem_intercon_to_s01_couplers_RVALID),
.S_AXI_wdata(axi_mem_intercon_to_s01_couplers_WDATA),
.S_AXI_wlast(axi_mem_intercon_to_s01_couplers_WLAST),
.S_AXI_wready(axi_mem_intercon_to_s01_couplers_WREADY),
.S_AXI_wstrb(axi_mem_intercon_to_s01_couplers_WSTRB),
.S_AXI_wvalid(axi_mem_intercon_to_s01_couplers_WVALID));
tutorial_xbar_1 xbar
(.aclk(axi_mem_intercon_ACLK_net),
.aresetn(axi_mem_intercon_ARESETN_net),
.m_axi_araddr(xbar_to_m00_couplers_ARADDR),
.m_axi_arburst(xbar_to_m00_couplers_ARBURST),
.m_axi_arcache(xbar_to_m00_couplers_ARCACHE),
.m_axi_arid(xbar_to_m00_couplers_ARID),
.m_axi_arlen(xbar_to_m00_couplers_ARLEN),
.m_axi_arlock(xbar_to_m00_couplers_ARLOCK),
.m_axi_arprot(xbar_to_m00_couplers_ARPROT),
.m_axi_arqos(xbar_to_m00_couplers_ARQOS),
.m_axi_arready(xbar_to_m00_couplers_ARREADY),
.m_axi_arregion(xbar_to_m00_couplers_ARREGION),
.m_axi_arsize(xbar_to_m00_couplers_ARSIZE),
.m_axi_arvalid(xbar_to_m00_couplers_ARVALID),
.m_axi_awaddr(xbar_to_m00_couplers_AWADDR),
.m_axi_awburst(xbar_to_m00_couplers_AWBURST),
.m_axi_awcache(xbar_to_m00_couplers_AWCACHE),
.m_axi_awid(xbar_to_m00_couplers_AWID),
.m_axi_awlen(xbar_to_m00_couplers_AWLEN),
.m_axi_awlock(xbar_to_m00_couplers_AWLOCK),
.m_axi_awprot(xbar_to_m00_couplers_AWPROT),
.m_axi_awqos(xbar_to_m00_couplers_AWQOS),
.m_axi_awready(xbar_to_m00_couplers_AWREADY),
.m_axi_awregion(xbar_to_m00_couplers_AWREGION),
.m_axi_awsize(xbar_to_m00_couplers_AWSIZE),
.m_axi_awvalid(xbar_to_m00_couplers_AWVALID),
.m_axi_bid(xbar_to_m00_couplers_BID),
.m_axi_bready(xbar_to_m00_couplers_BREADY),
.m_axi_bresp(xbar_to_m00_couplers_BRESP),
.m_axi_bvalid(xbar_to_m00_couplers_BVALID),
.m_axi_rdata(xbar_to_m00_couplers_RDATA),
.m_axi_rid(xbar_to_m00_couplers_RID),
.m_axi_rlast(xbar_to_m00_couplers_RLAST),
.m_axi_rready(xbar_to_m00_couplers_RREADY),
.m_axi_rresp(xbar_to_m00_couplers_RRESP),
.m_axi_rvalid(xbar_to_m00_couplers_RVALID),
.m_axi_wdata(xbar_to_m00_couplers_WDATA),
.m_axi_wlast(xbar_to_m00_couplers_WLAST),
.m_axi_wready(xbar_to_m00_couplers_WREADY),
.m_axi_wstrb(xbar_to_m00_couplers_WSTRB),
.m_axi_wvalid(xbar_to_m00_couplers_WVALID),
.s_axi_araddr({s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),
.s_axi_arburst({s01_couplers_to_xbar_ARBURST,s01_couplers_to_xbar_ARBURST,s00_couplers_to_xbar_ARBURST}),
.s_axi_arcache({s01_couplers_to_xbar_ARCACHE,s01_couplers_to_xbar_ARCACHE,s01_couplers_to_xbar_ARCACHE,s01_couplers_to_xbar_ARCACHE,s00_couplers_to_xbar_ARCACHE}),
.s_axi_arid({s01_couplers_to_xbar_ARID,GND_1}),
.s_axi_arlen({s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s01_couplers_to_xbar_ARLEN,s00_couplers_to_xbar_ARLEN}),
.s_axi_arlock({s01_couplers_to_xbar_ARLOCK,GND_1}),
.s_axi_arprot({s01_couplers_to_xbar_ARPROT,s01_couplers_to_xbar_ARPROT,s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),
.s_axi_arqos({s01_couplers_to_xbar_ARQOS,s01_couplers_to_xbar_ARQOS,s01_couplers_to_xbar_ARQOS,s01_couplers_to_xbar_ARQOS,GND_1,GND_1,GND_1,GND_1}),
.s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),
.s_axi_arsize({s01_couplers_to_xbar_ARSIZE,s01_couplers_to_xbar_ARSIZE,s01_couplers_to_xbar_ARSIZE,s00_couplers_to_xbar_ARSIZE}),
.s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),
.s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,s01_couplers_to_xbar_AWADDR,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axi_awburst({s01_couplers_to_xbar_AWBURST,s01_couplers_to_xbar_AWBURST,GND_1,GND_1}),
.s_axi_awcache({s01_couplers_to_xbar_AWCACHE,s01_couplers_to_xbar_AWCACHE,s01_couplers_to_xbar_AWCACHE,s01_couplers_to_xbar_AWCACHE,GND_1,GND_1,GND_1,GND_1}),
.s_axi_awid({s01_couplers_to_xbar_AWID,GND_1}),
.s_axi_awlen({s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,s01_couplers_to_xbar_AWLEN,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axi_awlock({s01_couplers_to_xbar_AWLOCK,GND_1}),
.s_axi_awprot({s01_couplers_to_xbar_AWPROT,s01_couplers_to_xbar_AWPROT,s01_couplers_to_xbar_AWPROT,GND_1,GND_1,GND_1}),
.s_axi_awqos({s01_couplers_to_xbar_AWQOS,s01_couplers_to_xbar_AWQOS,s01_couplers_to_xbar_AWQOS,s01_couplers_to_xbar_AWQOS,GND_1,GND_1,GND_1,GND_1}),
.s_axi_awready({s01_couplers_to_xbar_AWREADY,NLW_xbar_s_axi_awready_UNCONNECTED[0]}),
.s_axi_awsize({s01_couplers_to_xbar_AWSIZE,s01_couplers_to_xbar_AWSIZE,s01_couplers_to_xbar_AWSIZE,GND_1,GND_1,GND_1}),
.s_axi_awvalid({s01_couplers_to_xbar_AWVALID,GND_1}),
.s_axi_bid({s01_couplers_to_xbar_BID,NLW_xbar_s_axi_bid_UNCONNECTED[0]}),
.s_axi_bready({s01_couplers_to_xbar_BREADY,GND_1}),
.s_axi_bresp({s01_couplers_to_xbar_BRESP,NLW_xbar_s_axi_bresp_UNCONNECTED[1:0]}),
.s_axi_bvalid({s01_couplers_to_xbar_BVALID,NLW_xbar_s_axi_bvalid_UNCONNECTED[0]}),
.s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),
.s_axi_rid({s01_couplers_to_xbar_RID,NLW_xbar_s_axi_rid_UNCONNECTED[0]}),
.s_axi_rlast({s01_couplers_to_xbar_RLAST,s00_couplers_to_xbar_RLAST}),
.s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),
.s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),
.s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),
.s_axi_wdata({s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,s01_couplers_to_xbar_WDATA,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.s_axi_wlast({s01_couplers_to_xbar_WLAST,VCC_1}),
.s_axi_wready({s01_couplers_to_xbar_WREADY,NLW_xbar_s_axi_wready_UNCONNECTED[0]}),
.s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,s01_couplers_to_xbar_WSTRB,VCC_1,VCC_1,VCC_1,VCC_1,VCC_1,VCC_1,VCC_1,VCC_1}),
.s_axi_wvalid({s01_couplers_to_xbar_WVALID,GND_1}));
endmodule
module tutorial_processing_system7_0_axi_periph_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arready,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awready,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
M02_ACLK,
M02_ARESETN,
M02_AXI_araddr,
M02_AXI_arready,
M02_AXI_arvalid,
M02_AXI_awaddr,
M02_AXI_awready,
M02_AXI_awvalid,
M02_AXI_bready,
M02_AXI_bresp,
M02_AXI_bvalid,
M02_AXI_rdata,
M02_AXI_rready,
M02_AXI_rresp,
M02_AXI_rvalid,
M02_AXI_wdata,
M02_AXI_wready,
M02_AXI_wvalid,
M03_ACLK,
M03_ARESETN,
M03_AXI_araddr,
M03_AXI_arready,
M03_AXI_arvalid,
M03_AXI_awaddr,
M03_AXI_awready,
M03_AXI_awvalid,
M03_AXI_bready,
M03_AXI_bresp,
M03_AXI_bvalid,
M03_AXI_rdata,
M03_AXI_rready,
M03_AXI_rresp,
M03_AXI_rvalid,
M03_AXI_wdata,
M03_AXI_wready,
M03_AXI_wstrb,
M03_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [8:0]M00_AXI_araddr;
input [0:0]M00_AXI_arready;
output [0:0]M00_AXI_arvalid;
output [8:0]M00_AXI_awaddr;
input [0:0]M00_AXI_awready;
output [0:0]M00_AXI_awvalid;
output [0:0]M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input [0:0]M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output [0:0]M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input [0:0]M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input [0:0]M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output [0:0]M00_AXI_wvalid;
input M01_ACLK;
input [0:0]M01_ARESETN;
output [8:0]M01_AXI_araddr;
input [0:0]M01_AXI_arready;
output [0:0]M01_AXI_arvalid;
output [8:0]M01_AXI_awaddr;
input [0:0]M01_AXI_awready;
output [0:0]M01_AXI_awvalid;
output [0:0]M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input [0:0]M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
output [0:0]M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input [0:0]M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
input [0:0]M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output [0:0]M01_AXI_wvalid;
input M02_ACLK;
input [0:0]M02_ARESETN;
output [8:0]M02_AXI_araddr;
input [0:0]M02_AXI_arready;
output [0:0]M02_AXI_arvalid;
output [8:0]M02_AXI_awaddr;
input [0:0]M02_AXI_awready;
output [0:0]M02_AXI_awvalid;
output [0:0]M02_AXI_bready;
input [1:0]M02_AXI_bresp;
input [0:0]M02_AXI_bvalid;
input [31:0]M02_AXI_rdata;
output [0:0]M02_AXI_rready;
input [1:0]M02_AXI_rresp;
input [0:0]M02_AXI_rvalid;
output [31:0]M02_AXI_wdata;
input [0:0]M02_AXI_wready;
output [0:0]M02_AXI_wvalid;
input M03_ACLK;
input [0:0]M03_ARESETN;
output [8:0]M03_AXI_araddr;
input [0:0]M03_AXI_arready;
output [0:0]M03_AXI_arvalid;
output [8:0]M03_AXI_awaddr;
input [0:0]M03_AXI_awready;
output [0:0]M03_AXI_awvalid;
output [0:0]M03_AXI_bready;
input [1:0]M03_AXI_bresp;
input [0:0]M03_AXI_bvalid;
input [31:0]M03_AXI_rdata;
output [0:0]M03_AXI_rready;
input [1:0]M03_AXI_rresp;
input [0:0]M03_AXI_rvalid;
output [31:0]M03_AXI_wdata;
input [0:0]M03_AXI_wready;
output [3:0]M03_AXI_wstrb;
output [0:0]M03_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire M00_ACLK_1;
wire [0:0]M00_ARESETN_1;
wire M01_ACLK_1;
wire [0:0]M01_ARESETN_1;
wire M02_ACLK_1;
wire [0:0]M02_ARESETN_1;
wire M03_ACLK_1;
wire [0:0]M03_ARESETN_1;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire [8:0]m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [8:0]m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m00_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [8:0]m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [8:0]m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m01_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire [0:0]m01_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [8:0]m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [8:0]m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [0:0]m02_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [8:0]m03_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [8:0]m03_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m03_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m03_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m03_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m03_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m03_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire [0:0]m03_couplers_to_processing_system7_0_axi_periph_WVALID;
wire processing_system7_0_axi_periph_ACLK_net;
wire [0:0]processing_system7_0_axi_periph_ARESETN_net;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_ARADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_ARID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_ARVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_AWADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_AWID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_AWVALID;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_BID;
wire processing_system7_0_axi_periph_to_s00_couplers_BREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_BRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_BVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_RDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_RID;
wire processing_system7_0_axi_periph_to_s00_couplers_RLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_RREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_RRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_RVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_WDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_WID;
wire processing_system7_0_axi_periph_to_s00_couplers_WLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_WREADY;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_WSTRB;
wire processing_system7_0_axi_periph_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [0:0]xbar_to_m00_couplers_ARREADY;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [0:0]xbar_to_m00_couplers_AWREADY;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire [0:0]xbar_to_m00_couplers_BVALID;
wire [31:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire [0:0]xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WREADY;
wire [3:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire [0:0]xbar_to_m01_couplers_ARREADY;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire [0:0]xbar_to_m01_couplers_AWREADY;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire [0:0]xbar_to_m01_couplers_BVALID;
wire [31:0]xbar_to_m01_couplers_RDATA;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire [0:0]xbar_to_m01_couplers_RVALID;
wire [63:32]xbar_to_m01_couplers_WDATA;
wire [0:0]xbar_to_m01_couplers_WREADY;
wire [7:4]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
wire [95:64]xbar_to_m02_couplers_ARADDR;
wire [0:0]xbar_to_m02_couplers_ARREADY;
wire [2:2]xbar_to_m02_couplers_ARVALID;
wire [95:64]xbar_to_m02_couplers_AWADDR;
wire [0:0]xbar_to_m02_couplers_AWREADY;
wire [2:2]xbar_to_m02_couplers_AWVALID;
wire [2:2]xbar_to_m02_couplers_BREADY;
wire [1:0]xbar_to_m02_couplers_BRESP;
wire [0:0]xbar_to_m02_couplers_BVALID;
wire [31:0]xbar_to_m02_couplers_RDATA;
wire [2:2]xbar_to_m02_couplers_RREADY;
wire [1:0]xbar_to_m02_couplers_RRESP;
wire [0:0]xbar_to_m02_couplers_RVALID;
wire [95:64]xbar_to_m02_couplers_WDATA;
wire [0:0]xbar_to_m02_couplers_WREADY;
wire [2:2]xbar_to_m02_couplers_WVALID;
wire [127:96]xbar_to_m03_couplers_ARADDR;
wire [0:0]xbar_to_m03_couplers_ARREADY;
wire [3:3]xbar_to_m03_couplers_ARVALID;
wire [127:96]xbar_to_m03_couplers_AWADDR;
wire [0:0]xbar_to_m03_couplers_AWREADY;
wire [3:3]xbar_to_m03_couplers_AWVALID;
wire [3:3]xbar_to_m03_couplers_BREADY;
wire [1:0]xbar_to_m03_couplers_BRESP;
wire [0:0]xbar_to_m03_couplers_BVALID;
wire [31:0]xbar_to_m03_couplers_RDATA;
wire [3:3]xbar_to_m03_couplers_RREADY;
wire [1:0]xbar_to_m03_couplers_RRESP;
wire [0:0]xbar_to_m03_couplers_RVALID;
wire [127:96]xbar_to_m03_couplers_WDATA;
wire [0:0]xbar_to_m03_couplers_WREADY;
wire [15:12]xbar_to_m03_couplers_WSTRB;
wire [3:3]xbar_to_m03_couplers_WVALID;
wire [15:0]NLW_xbar_m_axi_wstrb_UNCONNECTED;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN[0];
assign M00_AXI_araddr[8:0] = m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M00_AXI_arvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M00_AXI_awaddr[8:0] = m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M00_AXI_awvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M00_AXI_bready[0] = m00_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M00_AXI_rready[0] = m00_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M00_AXI_wdata[31:0] = m00_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M00_AXI_wstrb[3:0] = m00_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M00_AXI_wvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M01_ACLK_1 = M01_ACLK;
assign M01_ARESETN_1 = M01_ARESETN[0];
assign M01_AXI_araddr[8:0] = m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M01_AXI_arvalid[0] = m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M01_AXI_awaddr[8:0] = m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M01_AXI_awvalid[0] = m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M01_AXI_bready[0] = m01_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M01_AXI_rready[0] = m01_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M01_AXI_wvalid[0] = m01_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M02_ACLK_1 = M02_ACLK;
assign M02_ARESETN_1 = M02_ARESETN[0];
assign M02_AXI_araddr[8:0] = m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M02_AXI_arvalid[0] = m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M02_AXI_awaddr[8:0] = m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M02_AXI_awvalid[0] = m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M02_AXI_bready[0] = m02_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M02_AXI_rready[0] = m02_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M02_AXI_wdata[31:0] = m02_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M02_AXI_wvalid[0] = m02_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M03_ACLK_1 = M03_ACLK;
assign M03_ARESETN_1 = M03_ARESETN[0];
assign M03_AXI_araddr[8:0] = m03_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M03_AXI_arvalid[0] = m03_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M03_AXI_awaddr[8:0] = m03_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M03_AXI_awvalid[0] = m03_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M03_AXI_bready[0] = m03_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M03_AXI_rready[0] = m03_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M03_AXI_wdata[31:0] = m03_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M03_AXI_wstrb[3:0] = m03_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M03_AXI_wvalid[0] = m03_couplers_to_processing_system7_0_axi_periph_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
assign S00_AXI_awready = processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = processing_system7_0_axi_periph_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = processing_system7_0_axi_periph_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_RID;
assign S00_AXI_rlast = processing_system7_0_axi_periph_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = processing_system7_0_axi_periph_to_s00_couplers_RVALID;
assign S00_AXI_wready = processing_system7_0_axi_periph_to_s00_couplers_WREADY;
assign m00_couplers_to_processing_system7_0_axi_periph_ARREADY = M00_AXI_arready[0];
assign m00_couplers_to_processing_system7_0_axi_periph_AWREADY = M00_AXI_awready[0];
assign m00_couplers_to_processing_system7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_BVALID = M00_AXI_bvalid[0];
assign m00_couplers_to_processing_system7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RVALID = M00_AXI_rvalid[0];
assign m00_couplers_to_processing_system7_0_axi_periph_WREADY = M00_AXI_wready[0];
assign m01_couplers_to_processing_system7_0_axi_periph_ARREADY = M01_AXI_arready[0];
assign m01_couplers_to_processing_system7_0_axi_periph_AWREADY = M01_AXI_awready[0];
assign m01_couplers_to_processing_system7_0_axi_periph_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_BVALID = M01_AXI_bvalid[0];
assign m01_couplers_to_processing_system7_0_axi_periph_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RVALID = M01_AXI_rvalid[0];
assign m01_couplers_to_processing_system7_0_axi_periph_WREADY = M01_AXI_wready[0];
assign m02_couplers_to_processing_system7_0_axi_periph_ARREADY = M02_AXI_arready[0];
assign m02_couplers_to_processing_system7_0_axi_periph_AWREADY = M02_AXI_awready[0];
assign m02_couplers_to_processing_system7_0_axi_periph_BRESP = M02_AXI_bresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_BVALID = M02_AXI_bvalid[0];
assign m02_couplers_to_processing_system7_0_axi_periph_RDATA = M02_AXI_rdata[31:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RRESP = M02_AXI_rresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RVALID = M02_AXI_rvalid[0];
assign m02_couplers_to_processing_system7_0_axi_periph_WREADY = M02_AXI_wready[0];
assign m03_couplers_to_processing_system7_0_axi_periph_ARREADY = M03_AXI_arready[0];
assign m03_couplers_to_processing_system7_0_axi_periph_AWREADY = M03_AXI_awready[0];
assign m03_couplers_to_processing_system7_0_axi_periph_BRESP = M03_AXI_bresp[1:0];
assign m03_couplers_to_processing_system7_0_axi_periph_BVALID = M03_AXI_bvalid[0];
assign m03_couplers_to_processing_system7_0_axi_periph_RDATA = M03_AXI_rdata[31:0];
assign m03_couplers_to_processing_system7_0_axi_periph_RRESP = M03_AXI_rresp[1:0];
assign m03_couplers_to_processing_system7_0_axi_periph_RVALID = M03_AXI_rvalid[0];
assign m03_couplers_to_processing_system7_0_axi_periph_WREADY = M03_AXI_wready[0];
assign processing_system7_0_axi_periph_ACLK_net = ACLK;
assign processing_system7_0_axi_periph_ARESETN_net = ARESETN[0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
assign processing_system7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
assign processing_system7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
assign processing_system7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
m00_couplers_imp_1SEDA4W m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m00_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m00_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m00_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m00_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m00_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m00_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m00_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m00_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m00_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m00_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m00_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m00_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m00_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m00_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m00_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m00_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR[8:0]),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR[8:0]),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_20VUK1 m01_couplers
(.M_ACLK(M01_ACLK_1),
.M_ARESETN(M01_ARESETN_1),
.M_AXI_araddr(m01_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m01_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m01_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m01_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m01_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m01_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m01_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m01_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m01_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m01_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m01_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m01_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m01_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m01_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m01_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m01_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m01_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR[40:32]),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR[40:32]),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
m02_couplers_imp_1TZBY8J m02_couplers
(.M_ACLK(M02_ACLK_1),
.M_ARESETN(M02_ARESETN_1),
.M_AXI_araddr(m02_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m02_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m02_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m02_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m02_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m02_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m02_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m02_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m02_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m02_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m02_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m02_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m02_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m02_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m02_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wvalid(m02_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m02_couplers_ARADDR[72:64]),
.S_AXI_arready(xbar_to_m02_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m02_couplers_AWADDR[72:64]),
.S_AXI_awready(xbar_to_m02_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),
.S_AXI_bready(xbar_to_m02_couplers_BREADY),
.S_AXI_bresp(xbar_to_m02_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m02_couplers_BVALID),
.S_AXI_rdata(xbar_to_m02_couplers_RDATA),
.S_AXI_rready(xbar_to_m02_couplers_RREADY),
.S_AXI_rresp(xbar_to_m02_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m02_couplers_RVALID),
.S_AXI_wdata(xbar_to_m02_couplers_WDATA),
.S_AXI_wready(xbar_to_m02_couplers_WREADY),
.S_AXI_wvalid(xbar_to_m02_couplers_WVALID));
m03_couplers_imp_Q7ENM m03_couplers
(.M_ACLK(M03_ACLK_1),
.M_ARESETN(M03_ARESETN_1),
.M_AXI_araddr(m03_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m03_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m03_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m03_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m03_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m03_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m03_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m03_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m03_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m03_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m03_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m03_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m03_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m03_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m03_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m03_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m03_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m03_couplers_ARADDR[104:96]),
.S_AXI_arready(xbar_to_m03_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m03_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m03_couplers_AWADDR[104:96]),
.S_AXI_awready(xbar_to_m03_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m03_couplers_AWVALID),
.S_AXI_bready(xbar_to_m03_couplers_BREADY),
.S_AXI_bresp(xbar_to_m03_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m03_couplers_BVALID),
.S_AXI_rdata(xbar_to_m03_couplers_RDATA),
.S_AXI_rready(xbar_to_m03_couplers_RREADY),
.S_AXI_rresp(xbar_to_m03_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m03_couplers_RVALID),
.S_AXI_wdata(xbar_to_m03_couplers_WDATA),
.S_AXI_wready(xbar_to_m03_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m03_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m03_couplers_WVALID));
s00_couplers_imp_4RCRTE s00_couplers
(.M_ACLK(processing_system7_0_axi_periph_ACLK_net),
.M_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(processing_system7_0_axi_periph_to_s00_couplers_ARADDR),
.S_AXI_arburst(processing_system7_0_axi_periph_to_s00_couplers_ARBURST),
.S_AXI_arcache(processing_system7_0_axi_periph_to_s00_couplers_ARCACHE),
.S_AXI_arid(processing_system7_0_axi_periph_to_s00_couplers_ARID),
.S_AXI_arlen(processing_system7_0_axi_periph_to_s00_couplers_ARLEN),
.S_AXI_arlock(processing_system7_0_axi_periph_to_s00_couplers_ARLOCK),
.S_AXI_arprot(processing_system7_0_axi_periph_to_s00_couplers_ARPROT),
.S_AXI_arqos(processing_system7_0_axi_periph_to_s00_couplers_ARQOS),
.S_AXI_arready(processing_system7_0_axi_periph_to_s00_couplers_ARREADY),
.S_AXI_arsize(processing_system7_0_axi_periph_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(processing_system7_0_axi_periph_to_s00_couplers_ARVALID),
.S_AXI_awaddr(processing_system7_0_axi_periph_to_s00_couplers_AWADDR),
.S_AXI_awburst(processing_system7_0_axi_periph_to_s00_couplers_AWBURST),
.S_AXI_awcache(processing_system7_0_axi_periph_to_s00_couplers_AWCACHE),
.S_AXI_awid(processing_system7_0_axi_periph_to_s00_couplers_AWID),
.S_AXI_awlen(processing_system7_0_axi_periph_to_s00_couplers_AWLEN),
.S_AXI_awlock(processing_system7_0_axi_periph_to_s00_couplers_AWLOCK),
.S_AXI_awprot(processing_system7_0_axi_periph_to_s00_couplers_AWPROT),
.S_AXI_awqos(processing_system7_0_axi_periph_to_s00_couplers_AWQOS),
.S_AXI_awready(processing_system7_0_axi_periph_to_s00_couplers_AWREADY),
.S_AXI_awsize(processing_system7_0_axi_periph_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(processing_system7_0_axi_periph_to_s00_couplers_AWVALID),
.S_AXI_bid(processing_system7_0_axi_periph_to_s00_couplers_BID),
.S_AXI_bready(processing_system7_0_axi_periph_to_s00_couplers_BREADY),
.S_AXI_bresp(processing_system7_0_axi_periph_to_s00_couplers_BRESP),
.S_AXI_bvalid(processing_system7_0_axi_periph_to_s00_couplers_BVALID),
.S_AXI_rdata(processing_system7_0_axi_periph_to_s00_couplers_RDATA),
.S_AXI_rid(processing_system7_0_axi_periph_to_s00_couplers_RID),
.S_AXI_rlast(processing_system7_0_axi_periph_to_s00_couplers_RLAST),
.S_AXI_rready(processing_system7_0_axi_periph_to_s00_couplers_RREADY),
.S_AXI_rresp(processing_system7_0_axi_periph_to_s00_couplers_RRESP),
.S_AXI_rvalid(processing_system7_0_axi_periph_to_s00_couplers_RVALID),
.S_AXI_wdata(processing_system7_0_axi_periph_to_s00_couplers_WDATA),
.S_AXI_wid(processing_system7_0_axi_periph_to_s00_couplers_WID),
.S_AXI_wlast(processing_system7_0_axi_periph_to_s00_couplers_WLAST),
.S_AXI_wready(processing_system7_0_axi_periph_to_s00_couplers_WREADY),
.S_AXI_wstrb(processing_system7_0_axi_periph_to_s00_couplers_WSTRB),
.S_AXI_wvalid(processing_system7_0_axi_periph_to_s00_couplers_WVALID));
tutorial_xbar_0 xbar
(.aclk(processing_system7_0_axi_periph_ACLK_net),
.aresetn(processing_system7_0_axi_periph_ARESETN_net),
.m_axi_araddr({xbar_to_m03_couplers_ARADDR,xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arready({xbar_to_m03_couplers_ARREADY,xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arvalid({xbar_to_m03_couplers_ARVALID,xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m03_couplers_AWADDR,xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awready({xbar_to_m03_couplers_AWREADY,xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awvalid({xbar_to_m03_couplers_AWVALID,xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m03_couplers_BREADY,xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m03_couplers_BRESP,xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m03_couplers_BVALID,xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m03_couplers_RDATA,xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rready({xbar_to_m03_couplers_RREADY,xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m03_couplers_RRESP,xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m03_couplers_RVALID,xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m03_couplers_WDATA,xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wready({xbar_to_m03_couplers_WREADY,xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m03_couplers_WSTRB,NLW_xbar_m_axi_wstrb_UNCONNECTED[11:8],xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m03_couplers_WVALID,xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule
module tutorial_processing_system7_0_axi_periph_1_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [4:0]M00_AXI_araddr;
input M00_AXI_arready;
output M00_AXI_arvalid;
output [4:0]M00_AXI_awaddr;
input M00_AXI_awready;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire processing_system7_0_axi_periph_1_ACLK_net;
wire [0:0]processing_system7_0_axi_periph_1_ARESETN_net;
wire [31:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARID;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK;
wire [2:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS;
wire processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY;
wire [2:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE;
wire processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID;
wire [31:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWID;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK;
wire [2:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS;
wire processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY;
wire [2:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE;
wire processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_BID;
wire processing_system7_0_axi_periph_1_to_s00_couplers_BREADY;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_BRESP;
wire processing_system7_0_axi_periph_1_to_s00_couplers_BVALID;
wire [31:0]processing_system7_0_axi_periph_1_to_s00_couplers_RDATA;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_RID;
wire processing_system7_0_axi_periph_1_to_s00_couplers_RLAST;
wire processing_system7_0_axi_periph_1_to_s00_couplers_RREADY;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_RRESP;
wire processing_system7_0_axi_periph_1_to_s00_couplers_RVALID;
wire [31:0]processing_system7_0_axi_periph_1_to_s00_couplers_WDATA;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_WID;
wire processing_system7_0_axi_periph_1_to_s00_couplers_WLAST;
wire processing_system7_0_axi_periph_1_to_s00_couplers_WREADY;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB;
wire processing_system7_0_axi_periph_1_to_s00_couplers_WVALID;
wire [4:0]s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR;
wire s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY;
wire s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID;
wire [4:0]s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR;
wire s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY;
wire s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID;
wire s00_couplers_to_processing_system7_0_axi_periph_1_BREADY;
wire [1:0]s00_couplers_to_processing_system7_0_axi_periph_1_BRESP;
wire s00_couplers_to_processing_system7_0_axi_periph_1_BVALID;
wire [31:0]s00_couplers_to_processing_system7_0_axi_periph_1_RDATA;
wire s00_couplers_to_processing_system7_0_axi_periph_1_RREADY;
wire [1:0]s00_couplers_to_processing_system7_0_axi_periph_1_RRESP;
wire s00_couplers_to_processing_system7_0_axi_periph_1_RVALID;
wire [31:0]s00_couplers_to_processing_system7_0_axi_periph_1_WDATA;
wire s00_couplers_to_processing_system7_0_axi_periph_1_WREADY;
wire [3:0]s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB;
wire s00_couplers_to_processing_system7_0_axi_periph_1_WVALID;
assign M00_AXI_araddr[4:0] = s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR;
assign M00_AXI_arvalid = s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID;
assign M00_AXI_awaddr[4:0] = s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR;
assign M00_AXI_awvalid = s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID;
assign M00_AXI_bready = s00_couplers_to_processing_system7_0_axi_periph_1_BREADY;
assign M00_AXI_rready = s00_couplers_to_processing_system7_0_axi_periph_1_RREADY;
assign M00_AXI_wdata[31:0] = s00_couplers_to_processing_system7_0_axi_periph_1_WDATA;
assign M00_AXI_wstrb[3:0] = s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB;
assign M00_AXI_wvalid = s00_couplers_to_processing_system7_0_axi_periph_1_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY;
assign S00_AXI_awready = processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = processing_system7_0_axi_periph_1_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = processing_system7_0_axi_periph_1_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = processing_system7_0_axi_periph_1_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = processing_system7_0_axi_periph_1_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = processing_system7_0_axi_periph_1_to_s00_couplers_RID;
assign S00_AXI_rlast = processing_system7_0_axi_periph_1_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = processing_system7_0_axi_periph_1_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = processing_system7_0_axi_periph_1_to_s00_couplers_RVALID;
assign S00_AXI_wready = processing_system7_0_axi_periph_1_to_s00_couplers_WREADY;
assign processing_system7_0_axi_periph_1_ACLK_net = M00_ACLK;
assign processing_system7_0_axi_periph_1_ARESETN_net = M00_ARESETN[0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign processing_system7_0_axi_periph_1_to_s00_couplers_BREADY = S00_AXI_bready;
assign processing_system7_0_axi_periph_1_to_s00_couplers_RREADY = S00_AXI_rready;
assign processing_system7_0_axi_periph_1_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_WLAST = S00_AXI_wlast;
assign processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY = M00_AXI_arready;
assign s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY = M00_AXI_awready;
assign s00_couplers_to_processing_system7_0_axi_periph_1_BRESP = M00_AXI_bresp[1:0];
assign s00_couplers_to_processing_system7_0_axi_periph_1_BVALID = M00_AXI_bvalid;
assign s00_couplers_to_processing_system7_0_axi_periph_1_RDATA = M00_AXI_rdata[31:0];
assign s00_couplers_to_processing_system7_0_axi_periph_1_RRESP = M00_AXI_rresp[1:0];
assign s00_couplers_to_processing_system7_0_axi_periph_1_RVALID = M00_AXI_rvalid;
assign s00_couplers_to_processing_system7_0_axi_periph_1_WREADY = M00_AXI_wready;
s00_couplers_imp_ADOUIZ s00_couplers
(.M_ACLK(processing_system7_0_axi_periph_1_ACLK_net),
.M_ARESETN(processing_system7_0_axi_periph_1_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR),
.M_AXI_arready(s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY),
.M_AXI_arvalid(s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID),
.M_AXI_awaddr(s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR),
.M_AXI_awready(s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY),
.M_AXI_awvalid(s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID),
.M_AXI_bready(s00_couplers_to_processing_system7_0_axi_periph_1_BREADY),
.M_AXI_bresp(s00_couplers_to_processing_system7_0_axi_periph_1_BRESP),
.M_AXI_bvalid(s00_couplers_to_processing_system7_0_axi_periph_1_BVALID),
.M_AXI_rdata(s00_couplers_to_processing_system7_0_axi_periph_1_RDATA),
.M_AXI_rready(s00_couplers_to_processing_system7_0_axi_periph_1_RREADY),
.M_AXI_rresp(s00_couplers_to_processing_system7_0_axi_periph_1_RRESP),
.M_AXI_rvalid(s00_couplers_to_processing_system7_0_axi_periph_1_RVALID),
.M_AXI_wdata(s00_couplers_to_processing_system7_0_axi_periph_1_WDATA),
.M_AXI_wready(s00_couplers_to_processing_system7_0_axi_periph_1_WREADY),
.M_AXI_wstrb(s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB),
.M_AXI_wvalid(s00_couplers_to_processing_system7_0_axi_periph_1_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR),
.S_AXI_arburst(processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST),
.S_AXI_arcache(processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE),
.S_AXI_arid(processing_system7_0_axi_periph_1_to_s00_couplers_ARID),
.S_AXI_arlen(processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN),
.S_AXI_arlock(processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK),
.S_AXI_arprot(processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT),
.S_AXI_arqos(processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS),
.S_AXI_arready(processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY),
.S_AXI_arsize(processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID),
.S_AXI_awaddr(processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR),
.S_AXI_awburst(processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST),
.S_AXI_awcache(processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE),
.S_AXI_awid(processing_system7_0_axi_periph_1_to_s00_couplers_AWID),
.S_AXI_awlen(processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN),
.S_AXI_awlock(processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK),
.S_AXI_awprot(processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT),
.S_AXI_awqos(processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS),
.S_AXI_awready(processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY),
.S_AXI_awsize(processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID),
.S_AXI_bid(processing_system7_0_axi_periph_1_to_s00_couplers_BID),
.S_AXI_bready(processing_system7_0_axi_periph_1_to_s00_couplers_BREADY),
.S_AXI_bresp(processing_system7_0_axi_periph_1_to_s00_couplers_BRESP),
.S_AXI_bvalid(processing_system7_0_axi_periph_1_to_s00_couplers_BVALID),
.S_AXI_rdata(processing_system7_0_axi_periph_1_to_s00_couplers_RDATA),
.S_AXI_rid(processing_system7_0_axi_periph_1_to_s00_couplers_RID),
.S_AXI_rlast(processing_system7_0_axi_periph_1_to_s00_couplers_RLAST),
.S_AXI_rready(processing_system7_0_axi_periph_1_to_s00_couplers_RREADY),
.S_AXI_rresp(processing_system7_0_axi_periph_1_to_s00_couplers_RRESP),
.S_AXI_rvalid(processing_system7_0_axi_periph_1_to_s00_couplers_RVALID),
.S_AXI_wdata(processing_system7_0_axi_periph_1_to_s00_couplers_WDATA),
.S_AXI_wid(processing_system7_0_axi_periph_1_to_s00_couplers_WID),
.S_AXI_wlast(processing_system7_0_axi_periph_1_to_s00_couplers_WLAST),
.S_AXI_wready(processing_system7_0_axi_periph_1_to_s00_couplers_WREADY),
.S_AXI_wstrb(processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB),
.S_AXI_wvalid(processing_system7_0_axi_periph_1_to_s00_couplers_WVALID));
endmodule
module zed_hdmi_display_imp_IWUBG8
(M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arid,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arqos,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awid,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awqos,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rid,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wid,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S_AXI_CONTROL_BUS_araddr,
S_AXI_CONTROL_BUS_arready,
S_AXI_CONTROL_BUS_arvalid,
S_AXI_CONTROL_BUS_awaddr,
S_AXI_CONTROL_BUS_awready,
S_AXI_CONTROL_BUS_awvalid,
S_AXI_CONTROL_BUS_bready,
S_AXI_CONTROL_BUS_bresp,
S_AXI_CONTROL_BUS_bvalid,
S_AXI_CONTROL_BUS_rdata,
S_AXI_CONTROL_BUS_rready,
S_AXI_CONTROL_BUS_rresp,
S_AXI_CONTROL_BUS_rvalid,
S_AXI_CONTROL_BUS_wdata,
S_AXI_CONTROL_BUS_wready,
S_AXI_CONTROL_BUS_wstrb,
S_AXI_CONTROL_BUS_wvalid,
axi4lite_aresetn,
axi4lite_clk,
axi4s_clk,
axi4s_resetn,
ctrl_araddr,
ctrl_arready,
ctrl_arvalid,
ctrl_awaddr,
ctrl_awready,
ctrl_awvalid,
ctrl_bready,
ctrl_bresp,
ctrl_bvalid,
ctrl_rdata,
ctrl_rready,
ctrl_rresp,
ctrl_rvalid,
ctrl_wdata,
ctrl_wready,
ctrl_wstrb,
ctrl_wvalid,
hdmio_clk,
hdmio_io_clk,
hdmio_io_data,
hdmio_io_de,
hdmio_io_hsync,
hdmio_io_spdif,
hdmio_io_vsync,
interconnect_aresetn,
peripheral_aresetn,
vdma_ctrl_araddr,
vdma_ctrl_arready,
vdma_ctrl_arvalid,
vdma_ctrl_awaddr,
vdma_ctrl_awready,
vdma_ctrl_awvalid,
vdma_ctrl_bready,
vdma_ctrl_bresp,
vdma_ctrl_bvalid,
vdma_ctrl_rdata,
vdma_ctrl_rready,
vdma_ctrl_rresp,
vdma_ctrl_rvalid,
vdma_ctrl_wdata,
vdma_ctrl_wready,
vdma_ctrl_wvalid,
vtc_ctrl_araddr,
vtc_ctrl_arready,
vtc_ctrl_arvalid,
vtc_ctrl_awaddr,
vtc_ctrl_awready,
vtc_ctrl_awvalid,
vtc_ctrl_bready,
vtc_ctrl_bresp,
vtc_ctrl_bvalid,
vtc_ctrl_rdata,
vtc_ctrl_rready,
vtc_ctrl_rresp,
vtc_ctrl_rvalid,
vtc_ctrl_wdata,
vtc_ctrl_wready,
vtc_ctrl_wstrb,
vtc_ctrl_wvalid);
output [31:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [0:0]M00_AXI_arid;
output [3:0]M00_AXI_arlen;
output [1:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
output [3:0]M00_AXI_arqos;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [0:0]M00_AXI_awid;
output [3:0]M00_AXI_awlen;
output [1:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
output [3:0]M00_AXI_awqos;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
input [0:0]M00_AXI_bid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [63:0]M00_AXI_rdata;
input [0:0]M00_AXI_rid;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [63:0]M00_AXI_wdata;
output [0:0]M00_AXI_wid;
output M00_AXI_wlast;
input M00_AXI_wready;
output [7:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input [4:0]S_AXI_CONTROL_BUS_araddr;
output S_AXI_CONTROL_BUS_arready;
input S_AXI_CONTROL_BUS_arvalid;
input [4:0]S_AXI_CONTROL_BUS_awaddr;
output S_AXI_CONTROL_BUS_awready;
input S_AXI_CONTROL_BUS_awvalid;
input S_AXI_CONTROL_BUS_bready;
output [1:0]S_AXI_CONTROL_BUS_bresp;
output S_AXI_CONTROL_BUS_bvalid;
output [31:0]S_AXI_CONTROL_BUS_rdata;
input S_AXI_CONTROL_BUS_rready;
output [1:0]S_AXI_CONTROL_BUS_rresp;
output S_AXI_CONTROL_BUS_rvalid;
input [31:0]S_AXI_CONTROL_BUS_wdata;
output S_AXI_CONTROL_BUS_wready;
input [3:0]S_AXI_CONTROL_BUS_wstrb;
input S_AXI_CONTROL_BUS_wvalid;
input [0:0]axi4lite_aresetn;
input axi4lite_clk;
input axi4s_clk;
input [0:0]axi4s_resetn;
input [8:0]ctrl_araddr;
output [0:0]ctrl_arready;
input [0:0]ctrl_arvalid;
input [8:0]ctrl_awaddr;
output [0:0]ctrl_awready;
input [0:0]ctrl_awvalid;
input [0:0]ctrl_bready;
output [1:0]ctrl_bresp;
output [0:0]ctrl_bvalid;
output [31:0]ctrl_rdata;
input [0:0]ctrl_rready;
output [1:0]ctrl_rresp;
output [0:0]ctrl_rvalid;
input [31:0]ctrl_wdata;
output [0:0]ctrl_wready;
input [3:0]ctrl_wstrb;
input [0:0]ctrl_wvalid;
input hdmio_clk;
output hdmio_io_clk;
output [15:0]hdmio_io_data;
output hdmio_io_de;
output hdmio_io_hsync;
output hdmio_io_spdif;
output hdmio_io_vsync;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
input [8:0]vdma_ctrl_araddr;
output [0:0]vdma_ctrl_arready;
input [0:0]vdma_ctrl_arvalid;
input [8:0]vdma_ctrl_awaddr;
output [0:0]vdma_ctrl_awready;
input [0:0]vdma_ctrl_awvalid;
input [0:0]vdma_ctrl_bready;
output [1:0]vdma_ctrl_bresp;
output [0:0]vdma_ctrl_bvalid;
output [31:0]vdma_ctrl_rdata;
input [0:0]vdma_ctrl_rready;
output [1:0]vdma_ctrl_rresp;
output [0:0]vdma_ctrl_rvalid;
input [31:0]vdma_ctrl_wdata;
output [0:0]vdma_ctrl_wready;
input [0:0]vdma_ctrl_wvalid;
input [8:0]vtc_ctrl_araddr;
output [0:0]vtc_ctrl_arready;
input [0:0]vtc_ctrl_arvalid;
input [8:0]vtc_ctrl_awaddr;
output [0:0]vtc_ctrl_awready;
input [0:0]vtc_ctrl_awvalid;
input [0:0]vtc_ctrl_bready;
output [1:0]vtc_ctrl_bresp;
output [0:0]vtc_ctrl_bvalid;
output [31:0]vtc_ctrl_rdata;
input [0:0]vtc_ctrl_rready;
output [1:0]vtc_ctrl_rresp;
output [0:0]vtc_ctrl_rvalid;
input [31:0]vtc_ctrl_wdata;
output [0:0]vtc_ctrl_wready;
input [3:0]vtc_ctrl_wstrb;
input [0:0]vtc_ctrl_wvalid;
wire [8:0]Conn1_ARADDR;
wire Conn1_ARREADY;
wire [0:0]Conn1_ARVALID;
wire [8:0]Conn1_AWADDR;
wire Conn1_AWREADY;
wire [0:0]Conn1_AWVALID;
wire [0:0]Conn1_BREADY;
wire [1:0]Conn1_BRESP;
wire Conn1_BVALID;
wire [31:0]Conn1_RDATA;
wire [0:0]Conn1_RREADY;
wire [1:0]Conn1_RRESP;
wire Conn1_RVALID;
wire [31:0]Conn1_WDATA;
wire Conn1_WREADY;
wire [3:0]Conn1_WSTRB;
wire [0:0]Conn1_WVALID;
wire [31:0]Conn2_ARADDR;
wire [1:0]Conn2_ARBURST;
wire [3:0]Conn2_ARCACHE;
wire [0:0]Conn2_ARID;
wire [3:0]Conn2_ARLEN;
wire [1:0]Conn2_ARLOCK;
wire [2:0]Conn2_ARPROT;
wire [3:0]Conn2_ARQOS;
wire Conn2_ARREADY;
wire [2:0]Conn2_ARSIZE;
wire Conn2_ARVALID;
wire [31:0]Conn2_AWADDR;
wire [1:0]Conn2_AWBURST;
wire [3:0]Conn2_AWCACHE;
wire [0:0]Conn2_AWID;
wire [3:0]Conn2_AWLEN;
wire [1:0]Conn2_AWLOCK;
wire [2:0]Conn2_AWPROT;
wire [3:0]Conn2_AWQOS;
wire Conn2_AWREADY;
wire [2:0]Conn2_AWSIZE;
wire Conn2_AWVALID;
wire [0:0]Conn2_BID;
wire Conn2_BREADY;
wire [1:0]Conn2_BRESP;
wire Conn2_BVALID;
wire [63:0]Conn2_RDATA;
wire [0:0]Conn2_RID;
wire Conn2_RLAST;
wire Conn2_RREADY;
wire [1:0]Conn2_RRESP;
wire Conn2_RVALID;
wire [63:0]Conn2_WDATA;
wire [0:0]Conn2_WID;
wire Conn2_WLAST;
wire Conn2_WREADY;
wire [7:0]Conn2_WSTRB;
wire Conn2_WVALID;
wire [8:0]Conn3_ARADDR;
wire Conn3_ARREADY;
wire [0:0]Conn3_ARVALID;
wire [8:0]Conn3_AWADDR;
wire Conn3_AWREADY;
wire [0:0]Conn3_AWVALID;
wire [0:0]Conn3_BREADY;
wire [1:0]Conn3_BRESP;
wire Conn3_BVALID;
wire [31:0]Conn3_RDATA;
wire [0:0]Conn3_RREADY;
wire [1:0]Conn3_RRESP;
wire Conn3_RVALID;
wire [31:0]Conn3_WDATA;
wire Conn3_WREADY;
wire [0:0]Conn3_WVALID;
wire [8:0]Conn4_ARADDR;
wire Conn4_ARREADY;
wire [0:0]Conn4_ARVALID;
wire [8:0]Conn4_AWADDR;
wire Conn4_AWREADY;
wire [0:0]Conn4_AWVALID;
wire [0:0]Conn4_BREADY;
wire [1:0]Conn4_BRESP;
wire Conn4_BVALID;
wire [31:0]Conn4_RDATA;
wire [0:0]Conn4_RREADY;
wire [1:0]Conn4_RRESP;
wire Conn4_RVALID;
wire [31:0]Conn4_WDATA;
wire Conn4_WREADY;
wire [3:0]Conn4_WSTRB;
wire [0:0]Conn4_WVALID;
wire GND_2;
wire [4:0]S_AXI_CONTROL_BUS_1_ARADDR;
wire S_AXI_CONTROL_BUS_1_ARREADY;
wire S_AXI_CONTROL_BUS_1_ARVALID;
wire [4:0]S_AXI_CONTROL_BUS_1_AWADDR;
wire S_AXI_CONTROL_BUS_1_AWREADY;
wire S_AXI_CONTROL_BUS_1_AWVALID;
wire S_AXI_CONTROL_BUS_1_BREADY;
wire [1:0]S_AXI_CONTROL_BUS_1_BRESP;
wire S_AXI_CONTROL_BUS_1_BVALID;
wire [31:0]S_AXI_CONTROL_BUS_1_RDATA;
wire S_AXI_CONTROL_BUS_1_RREADY;
wire [1:0]S_AXI_CONTROL_BUS_1_RRESP;
wire S_AXI_CONTROL_BUS_1_RVALID;
wire [31:0]S_AXI_CONTROL_BUS_1_WDATA;
wire S_AXI_CONTROL_BUS_1_WREADY;
wire [3:0]S_AXI_CONTROL_BUS_1_WSTRB;
wire S_AXI_CONTROL_BUS_1_WVALID;
wire VCC_2;
wire [0:0]aresetn_1;
wire [31:0]axi_vdma_0_m_axi_mm2s_ARADDR;
wire [1:0]axi_vdma_0_m_axi_mm2s_ARBURST;
wire [3:0]axi_vdma_0_m_axi_mm2s_ARCACHE;
wire [7:0]axi_vdma_0_m_axi_mm2s_ARLEN;
wire [2:0]axi_vdma_0_m_axi_mm2s_ARPROT;
wire axi_vdma_0_m_axi_mm2s_ARREADY;
wire [2:0]axi_vdma_0_m_axi_mm2s_ARSIZE;
wire axi_vdma_0_m_axi_mm2s_ARVALID;
wire [63:0]axi_vdma_0_m_axi_mm2s_RDATA;
wire axi_vdma_0_m_axi_mm2s_RLAST;
wire axi_vdma_0_m_axi_mm2s_RREADY;
wire [1:0]axi_vdma_0_m_axi_mm2s_RRESP;
wire axi_vdma_0_m_axi_mm2s_RVALID;
wire clk_1;
wire [0:0]ext_reset_in_1;
wire [0:0]gnd_const;
(* MARK_DEBUG *) wire [23:0]pixelq_op_0_OUTPUT_STREAM_TDATA;
(* MARK_DEBUG *) wire [0:0]pixelq_op_0_OUTPUT_STREAM_TLAST;
(* MARK_DEBUG *) wire pixelq_op_0_OUTPUT_STREAM_TREADY;
(* MARK_DEBUG *) wire [0:0]pixelq_op_0_OUTPUT_STREAM_TUSER;
(* MARK_DEBUG *) wire pixelq_op_0_OUTPUT_STREAM_TVALID;
wire [0:0]proc_sys_reset_peripheral_aresetn;
wire processing_system7_0_fclk_clk1;
wire s_axi_aclk_1;
wire [0:0]s_axi_aresetn_1;
wire v_axi4s_vid_out_0_vid_io_out_ACTIVE_VIDEO;
wire [15:0]v_axi4s_vid_out_0_vid_io_out_DATA;
wire v_axi4s_vid_out_0_vid_io_out_HSYNC;
wire v_axi4s_vid_out_0_vid_io_out_VSYNC;
wire v_axi4s_vid_out_0_vtg_ce;
(* MARK_DEBUG *) wire [23:0]v_cfa_0_video_out_TDATA;
(* MARK_DEBUG *) wire v_cfa_0_video_out_TLAST;
(* MARK_DEBUG *) wire v_cfa_0_video_out_TREADY;
(* MARK_DEBUG *) wire v_cfa_0_video_out_TUSER;
(* MARK_DEBUG *) wire v_cfa_0_video_out_TVALID;
wire [15:0]v_cresample_0_video_out_TDATA;
wire v_cresample_0_video_out_TLAST;
wire v_cresample_0_video_out_TREADY;
wire v_cresample_0_video_out_TUSER;
wire v_cresample_0_video_out_TVALID;
wire [23:0]v_rgb2ycrcb_0_video_out_TDATA;
wire v_rgb2ycrcb_0_video_out_TLAST;
wire v_rgb2ycrcb_0_video_out_TREADY;
wire v_rgb2ycrcb_0_video_out_TUSER;
wire v_rgb2ycrcb_0_video_out_TVALID;
wire v_tc_0_vtiming_out_ACTIVE_VIDEO;
wire v_tc_0_vtiming_out_HBLANK;
wire v_tc_0_vtiming_out_HSYNC;
wire v_tc_0_vtiming_out_VBLANK;
wire v_tc_0_vtiming_out_VSYNC;
wire [7:0]v_tpg_0_video_out_TDATA;
wire v_tpg_0_video_out_TLAST;
wire v_tpg_0_video_out_TREADY;
wire v_tpg_0_video_out_TUSER;
wire v_tpg_0_video_out_TVALID;
wire [0:0]vcc_const;
wire zed_hdmi_out_0_io_hdmio_CLK;
wire [15:0]zed_hdmi_out_0_io_hdmio_DATA;
wire zed_hdmi_out_0_io_hdmio_DE;
wire zed_hdmi_out_0_io_hdmio_HSYNC;
wire zed_hdmi_out_0_io_hdmio_SPDIF;
wire zed_hdmi_out_0_io_hdmio_VSYNC;
assign Conn1_ARADDR = vtc_ctrl_araddr[8:0];
assign Conn1_ARVALID = vtc_ctrl_arvalid[0];
assign Conn1_AWADDR = vtc_ctrl_awaddr[8:0];
assign Conn1_AWVALID = vtc_ctrl_awvalid[0];
assign Conn1_BREADY = vtc_ctrl_bready[0];
assign Conn1_RREADY = vtc_ctrl_rready[0];
assign Conn1_WDATA = vtc_ctrl_wdata[31:0];
assign Conn1_WSTRB = vtc_ctrl_wstrb[3:0];
assign Conn1_WVALID = vtc_ctrl_wvalid[0];
assign Conn2_ARREADY = M00_AXI_arready;
assign Conn2_AWREADY = M00_AXI_awready;
assign Conn2_BID = M00_AXI_bid[0];
assign Conn2_BRESP = M00_AXI_bresp[1:0];
assign Conn2_BVALID = M00_AXI_bvalid;
assign Conn2_RDATA = M00_AXI_rdata[63:0];
assign Conn2_RID = M00_AXI_rid[0];
assign Conn2_RLAST = M00_AXI_rlast;
assign Conn2_RRESP = M00_AXI_rresp[1:0];
assign Conn2_RVALID = M00_AXI_rvalid;
assign Conn2_WREADY = M00_AXI_wready;
assign Conn3_ARADDR = vdma_ctrl_araddr[8:0];
assign Conn3_ARVALID = vdma_ctrl_arvalid[0];
assign Conn3_AWADDR = vdma_ctrl_awaddr[8:0];
assign Conn3_AWVALID = vdma_ctrl_awvalid[0];
assign Conn3_BREADY = vdma_ctrl_bready[0];
assign Conn3_RREADY = vdma_ctrl_rready[0];
assign Conn3_WDATA = vdma_ctrl_wdata[31:0];
assign Conn3_WVALID = vdma_ctrl_wvalid[0];
assign Conn4_ARADDR = ctrl_araddr[8:0];
assign Conn4_ARVALID = ctrl_arvalid[0];
assign Conn4_AWADDR = ctrl_awaddr[8:0];
assign Conn4_AWVALID = ctrl_awvalid[0];
assign Conn4_BREADY = ctrl_bready[0];
assign Conn4_RREADY = ctrl_rready[0];
assign Conn4_WDATA = ctrl_wdata[31:0];
assign Conn4_WSTRB = ctrl_wstrb[3:0];
assign Conn4_WVALID = ctrl_wvalid[0];
assign M00_AXI_araddr[31:0] = Conn2_ARADDR;
assign M00_AXI_arburst[1:0] = Conn2_ARBURST;
assign M00_AXI_arcache[3:0] = Conn2_ARCACHE;
assign M00_AXI_arid[0] = Conn2_ARID;
assign M00_AXI_arlen[3:0] = Conn2_ARLEN;
assign M00_AXI_arlock[1:0] = Conn2_ARLOCK;
assign M00_AXI_arprot[2:0] = Conn2_ARPROT;
assign M00_AXI_arqos[3:0] = Conn2_ARQOS;
assign M00_AXI_arsize[2:0] = Conn2_ARSIZE;
assign M00_AXI_arvalid = Conn2_ARVALID;
assign M00_AXI_awaddr[31:0] = Conn2_AWADDR;
assign M00_AXI_awburst[1:0] = Conn2_AWBURST;
assign M00_AXI_awcache[3:0] = Conn2_AWCACHE;
assign M00_AXI_awid[0] = Conn2_AWID;
assign M00_AXI_awlen[3:0] = Conn2_AWLEN;
assign M00_AXI_awlock[1:0] = Conn2_AWLOCK;
assign M00_AXI_awprot[2:0] = Conn2_AWPROT;
assign M00_AXI_awqos[3:0] = Conn2_AWQOS;
assign M00_AXI_awsize[2:0] = Conn2_AWSIZE;
assign M00_AXI_awvalid = Conn2_AWVALID;
assign M00_AXI_bready = Conn2_BREADY;
assign M00_AXI_rready = Conn2_RREADY;
assign M00_AXI_wdata[63:0] = Conn2_WDATA;
assign M00_AXI_wid[0] = Conn2_WID;
assign M00_AXI_wlast = Conn2_WLAST;
assign M00_AXI_wstrb[7:0] = Conn2_WSTRB;
assign M00_AXI_wvalid = Conn2_WVALID;
assign S_AXI_CONTROL_BUS_1_ARADDR = S_AXI_CONTROL_BUS_araddr[4:0];
assign S_AXI_CONTROL_BUS_1_ARVALID = S_AXI_CONTROL_BUS_arvalid;
assign S_AXI_CONTROL_BUS_1_AWADDR = S_AXI_CONTROL_BUS_awaddr[4:0];
assign S_AXI_CONTROL_BUS_1_AWVALID = S_AXI_CONTROL_BUS_awvalid;
assign S_AXI_CONTROL_BUS_1_BREADY = S_AXI_CONTROL_BUS_bready;
assign S_AXI_CONTROL_BUS_1_RREADY = S_AXI_CONTROL_BUS_rready;
assign S_AXI_CONTROL_BUS_1_WDATA = S_AXI_CONTROL_BUS_wdata[31:0];
assign S_AXI_CONTROL_BUS_1_WSTRB = S_AXI_CONTROL_BUS_wstrb[3:0];
assign S_AXI_CONTROL_BUS_1_WVALID = S_AXI_CONTROL_BUS_wvalid;
assign S_AXI_CONTROL_BUS_arready = S_AXI_CONTROL_BUS_1_ARREADY;
assign S_AXI_CONTROL_BUS_awready = S_AXI_CONTROL_BUS_1_AWREADY;
assign S_AXI_CONTROL_BUS_bresp[1:0] = S_AXI_CONTROL_BUS_1_BRESP;
assign S_AXI_CONTROL_BUS_bvalid = S_AXI_CONTROL_BUS_1_BVALID;
assign S_AXI_CONTROL_BUS_rdata[31:0] = S_AXI_CONTROL_BUS_1_RDATA;
assign S_AXI_CONTROL_BUS_rresp[1:0] = S_AXI_CONTROL_BUS_1_RRESP;
assign S_AXI_CONTROL_BUS_rvalid = S_AXI_CONTROL_BUS_1_RVALID;
assign S_AXI_CONTROL_BUS_wready = S_AXI_CONTROL_BUS_1_WREADY;
assign clk_1 = hdmio_clk;
assign ctrl_arready[0] = Conn4_ARREADY;
assign ctrl_awready[0] = Conn4_AWREADY;
assign ctrl_bresp[1:0] = Conn4_BRESP;
assign ctrl_bvalid[0] = Conn4_BVALID;
assign ctrl_rdata[31:0] = Conn4_RDATA;
assign ctrl_rresp[1:0] = Conn4_RRESP;
assign ctrl_rvalid[0] = Conn4_RVALID;
assign ctrl_wready[0] = Conn4_WREADY;
assign ext_reset_in_1 = axi4s_resetn[0];
assign hdmio_io_clk = zed_hdmi_out_0_io_hdmio_CLK;
assign hdmio_io_data[15:0] = zed_hdmi_out_0_io_hdmio_DATA;
assign hdmio_io_de = zed_hdmi_out_0_io_hdmio_DE;
assign hdmio_io_hsync = zed_hdmi_out_0_io_hdmio_HSYNC;
assign hdmio_io_spdif = zed_hdmi_out_0_io_hdmio_SPDIF;
assign hdmio_io_vsync = zed_hdmi_out_0_io_hdmio_VSYNC;
assign interconnect_aresetn[0] = aresetn_1;
assign peripheral_aresetn[0] = proc_sys_reset_peripheral_aresetn;
assign processing_system7_0_fclk_clk1 = axi4s_clk;
assign s_axi_aclk_1 = axi4lite_clk;
assign s_axi_aresetn_1 = axi4lite_aresetn[0];
assign vdma_ctrl_arready[0] = Conn3_ARREADY;
assign vdma_ctrl_awready[0] = Conn3_AWREADY;
assign vdma_ctrl_bresp[1:0] = Conn3_BRESP;
assign vdma_ctrl_bvalid[0] = Conn3_BVALID;
assign vdma_ctrl_rdata[31:0] = Conn3_RDATA;
assign vdma_ctrl_rresp[1:0] = Conn3_RRESP;
assign vdma_ctrl_rvalid[0] = Conn3_RVALID;
assign vdma_ctrl_wready[0] = Conn3_WREADY;
assign vtc_ctrl_arready[0] = Conn1_ARREADY;
assign vtc_ctrl_awready[0] = Conn1_AWREADY;
assign vtc_ctrl_bresp[1:0] = Conn1_BRESP;
assign vtc_ctrl_bvalid[0] = Conn1_BVALID;
assign vtc_ctrl_rdata[31:0] = Conn1_RDATA;
assign vtc_ctrl_rresp[1:0] = Conn1_RRESP;
assign vtc_ctrl_rvalid[0] = Conn1_RVALID;
assign vtc_ctrl_wready[0] = Conn1_WREADY;
GND GND_1
(.G(GND_2));
VCC VCC_1
(.P(VCC_2));
tutorial_axi_mem_intercon_0 axi_mem_intercon
(.ACLK(processing_system7_0_fclk_clk1),
.ARESETN(aresetn_1),
.M00_ACLK(processing_system7_0_fclk_clk1),
.M00_ARESETN(proc_sys_reset_peripheral_aresetn),
.M00_AXI_araddr(Conn2_ARADDR),
.M00_AXI_arburst(Conn2_ARBURST),
.M00_AXI_arcache(Conn2_ARCACHE),
.M00_AXI_arid(Conn2_ARID),
.M00_AXI_arlen(Conn2_ARLEN),
.M00_AXI_arlock(Conn2_ARLOCK),
.M00_AXI_arprot(Conn2_ARPROT),
.M00_AXI_arqos(Conn2_ARQOS),
.M00_AXI_arready(Conn2_ARREADY),
.M00_AXI_arsize(Conn2_ARSIZE),
.M00_AXI_arvalid(Conn2_ARVALID),
.M00_AXI_awaddr(Conn2_AWADDR),
.M00_AXI_awburst(Conn2_AWBURST),
.M00_AXI_awcache(Conn2_AWCACHE),
.M00_AXI_awid(Conn2_AWID),
.M00_AXI_awlen(Conn2_AWLEN),
.M00_AXI_awlock(Conn2_AWLOCK),
.M00_AXI_awprot(Conn2_AWPROT),
.M00_AXI_awqos(Conn2_AWQOS),
.M00_AXI_awready(Conn2_AWREADY),
.M00_AXI_awsize(Conn2_AWSIZE),
.M00_AXI_awvalid(Conn2_AWVALID),
.M00_AXI_bid(Conn2_BID),
.M00_AXI_bready(Conn2_BREADY),
.M00_AXI_bresp(Conn2_BRESP),
.M00_AXI_bvalid(Conn2_BVALID),
.M00_AXI_rdata(Conn2_RDATA),
.M00_AXI_rid(Conn2_RID),
.M00_AXI_rlast(Conn2_RLAST),
.M00_AXI_rready(Conn2_RREADY),
.M00_AXI_rresp(Conn2_RRESP),
.M00_AXI_rvalid(Conn2_RVALID),
.M00_AXI_wdata(Conn2_WDATA),
.M00_AXI_wid(Conn2_WID),
.M00_AXI_wlast(Conn2_WLAST),
.M00_AXI_wready(Conn2_WREADY),
.M00_AXI_wstrb(Conn2_WSTRB),
.M00_AXI_wvalid(Conn2_WVALID),
.S00_ACLK(processing_system7_0_fclk_clk1),
.S00_ARESETN(proc_sys_reset_peripheral_aresetn),
.S00_AXI_araddr(axi_vdma_0_m_axi_mm2s_ARADDR),
.S00_AXI_arburst(axi_vdma_0_m_axi_mm2s_ARBURST),
.S00_AXI_arcache(axi_vdma_0_m_axi_mm2s_ARCACHE),
.S00_AXI_arlen(axi_vdma_0_m_axi_mm2s_ARLEN),
.S00_AXI_arprot(axi_vdma_0_m_axi_mm2s_ARPROT),
.S00_AXI_arready(axi_vdma_0_m_axi_mm2s_ARREADY),
.S00_AXI_arsize(axi_vdma_0_m_axi_mm2s_ARSIZE),
.S00_AXI_arvalid(axi_vdma_0_m_axi_mm2s_ARVALID),
.S00_AXI_rdata(axi_vdma_0_m_axi_mm2s_RDATA),
.S00_AXI_rlast(axi_vdma_0_m_axi_mm2s_RLAST),
.S00_AXI_rready(axi_vdma_0_m_axi_mm2s_RREADY),
.S00_AXI_rresp(axi_vdma_0_m_axi_mm2s_RRESP),
.S00_AXI_rvalid(axi_vdma_0_m_axi_mm2s_RVALID),
.S01_ACLK(processing_system7_0_fclk_clk1),
.S01_ARESETN(proc_sys_reset_peripheral_aresetn),
.S01_AXI_araddr(GND_2),
.S01_AXI_arburst(GND_2),
.S01_AXI_arcache(GND_2),
.S01_AXI_arid(GND_2),
.S01_AXI_arlen(GND_2),
.S01_AXI_arlock(GND_2),
.S01_AXI_arprot(GND_2),
.S01_AXI_arqos(GND_2),
.S01_AXI_arsize(GND_2),
.S01_AXI_arvalid(GND_2),
.S01_AXI_awaddr(GND_2),
.S01_AXI_awburst(GND_2),
.S01_AXI_awcache(GND_2),
.S01_AXI_awid(GND_2),
.S01_AXI_awlen(GND_2),
.S01_AXI_awlock(GND_2),
.S01_AXI_awprot(GND_2),
.S01_AXI_awqos(GND_2),
.S01_AXI_awsize(GND_2),
.S01_AXI_awvalid(GND_2),
.S01_AXI_bready(GND_2),
.S01_AXI_rready(GND_2),
.S01_AXI_wdata(GND_2),
.S01_AXI_wlast(GND_2),
.S01_AXI_wstrb(GND_2),
.S01_AXI_wvalid(GND_2));
tutorial_axi_vdma_0_0 axi_vdma_0
(.axi_resetn(vcc_const),
.m_axi_mm2s_aclk(processing_system7_0_fclk_clk1),
.m_axi_mm2s_araddr(axi_vdma_0_m_axi_mm2s_ARADDR),
.m_axi_mm2s_arburst(axi_vdma_0_m_axi_mm2s_ARBURST),
.m_axi_mm2s_arcache(axi_vdma_0_m_axi_mm2s_ARCACHE),
.m_axi_mm2s_arlen(axi_vdma_0_m_axi_mm2s_ARLEN),
.m_axi_mm2s_arprot(axi_vdma_0_m_axi_mm2s_ARPROT),
.m_axi_mm2s_arready(axi_vdma_0_m_axi_mm2s_ARREADY),
.m_axi_mm2s_arsize(axi_vdma_0_m_axi_mm2s_ARSIZE),
.m_axi_mm2s_arvalid(axi_vdma_0_m_axi_mm2s_ARVALID),
.m_axi_mm2s_rdata(axi_vdma_0_m_axi_mm2s_RDATA),
.m_axi_mm2s_rlast(axi_vdma_0_m_axi_mm2s_RLAST),
.m_axi_mm2s_rready(axi_vdma_0_m_axi_mm2s_RREADY),
.m_axi_mm2s_rresp(axi_vdma_0_m_axi_mm2s_RRESP),
.m_axi_mm2s_rvalid(axi_vdma_0_m_axi_mm2s_RVALID),
.m_axis_mm2s_aclk(processing_system7_0_fclk_clk1),
.m_axis_mm2s_tready(GND_2),
.s_axi_lite_aclk(s_axi_aclk_1),
.s_axi_lite_araddr(Conn3_ARADDR),
.s_axi_lite_arready(Conn3_ARREADY),
.s_axi_lite_arvalid(Conn3_ARVALID),
.s_axi_lite_awaddr(Conn3_AWADDR),
.s_axi_lite_awready(Conn3_AWREADY),
.s_axi_lite_awvalid(Conn3_AWVALID),
.s_axi_lite_bready(Conn3_BREADY),
.s_axi_lite_bresp(Conn3_BRESP),
.s_axi_lite_bvalid(Conn3_BVALID),
.s_axi_lite_rdata(Conn3_RDATA),
.s_axi_lite_rready(Conn3_RREADY),
.s_axi_lite_rresp(Conn3_RRESP),
.s_axi_lite_rvalid(Conn3_RVALID),
.s_axi_lite_wdata(Conn3_WDATA),
.s_axi_lite_wready(Conn3_WREADY),
.s_axi_lite_wvalid(Conn3_WVALID));
tutorial_gnd_0 gnd
(.dout(gnd_const));
tutorial_pixelq_op_0_0 pixelq_op_0
(.INPUT_STREAM_TDATA(v_cfa_0_video_out_TDATA),
.INPUT_STREAM_TDEST(GND_2),
.INPUT_STREAM_TID(GND_2),
.INPUT_STREAM_TLAST(v_cfa_0_video_out_TLAST),
.INPUT_STREAM_TREADY(v_cfa_0_video_out_TREADY),
.INPUT_STREAM_TUSER(v_cfa_0_video_out_TUSER),
.INPUT_STREAM_TVALID(v_cfa_0_video_out_TVALID),
.OUTPUT_STREAM_TDATA(pixelq_op_0_OUTPUT_STREAM_TDATA),
.OUTPUT_STREAM_TLAST(pixelq_op_0_OUTPUT_STREAM_TLAST),
.OUTPUT_STREAM_TREADY(pixelq_op_0_OUTPUT_STREAM_TREADY),
.OUTPUT_STREAM_TUSER(pixelq_op_0_OUTPUT_STREAM_TUSER),
.OUTPUT_STREAM_TVALID(pixelq_op_0_OUTPUT_STREAM_TVALID),
.aclk(processing_system7_0_fclk_clk1),
.aresetn(vcc_const),
.s_axi_CONTROL_BUS_ARADDR(S_AXI_CONTROL_BUS_1_ARADDR),
.s_axi_CONTROL_BUS_ARREADY(S_AXI_CONTROL_BUS_1_ARREADY),
.s_axi_CONTROL_BUS_ARVALID(S_AXI_CONTROL_BUS_1_ARVALID),
.s_axi_CONTROL_BUS_AWADDR(S_AXI_CONTROL_BUS_1_AWADDR),
.s_axi_CONTROL_BUS_AWREADY(S_AXI_CONTROL_BUS_1_AWREADY),
.s_axi_CONTROL_BUS_AWVALID(S_AXI_CONTROL_BUS_1_AWVALID),
.s_axi_CONTROL_BUS_BREADY(S_AXI_CONTROL_BUS_1_BREADY),
.s_axi_CONTROL_BUS_BRESP(S_AXI_CONTROL_BUS_1_BRESP),
.s_axi_CONTROL_BUS_BVALID(S_AXI_CONTROL_BUS_1_BVALID),
.s_axi_CONTROL_BUS_RDATA(S_AXI_CONTROL_BUS_1_RDATA),
.s_axi_CONTROL_BUS_RREADY(S_AXI_CONTROL_BUS_1_RREADY),
.s_axi_CONTROL_BUS_RRESP(S_AXI_CONTROL_BUS_1_RRESP),
.s_axi_CONTROL_BUS_RVALID(S_AXI_CONTROL_BUS_1_RVALID),
.s_axi_CONTROL_BUS_WDATA(S_AXI_CONTROL_BUS_1_WDATA),
.s_axi_CONTROL_BUS_WREADY(S_AXI_CONTROL_BUS_1_WREADY),
.s_axi_CONTROL_BUS_WSTRB(S_AXI_CONTROL_BUS_1_WSTRB),
.s_axi_CONTROL_BUS_WVALID(S_AXI_CONTROL_BUS_1_WVALID));
tutorial_proc_sys_reset_0 proc_sys_reset
(.aux_reset_in(VCC_2),
.dcm_locked(VCC_2),
.ext_reset_in(ext_reset_in_1),
.interconnect_aresetn(aresetn_1),
.mb_debug_sys_rst(GND_2),
.peripheral_aresetn(proc_sys_reset_peripheral_aresetn),
.slowest_sync_clk(processing_system7_0_fclk_clk1));
tutorial_v_axi4s_vid_out_0_0 v_axi4s_vid_out_0
(.aclk(processing_system7_0_fclk_clk1),
.aclken(vcc_const),
.aresetn(vcc_const),
.fid(GND_2),
.rst(gnd_const),
.s_axis_video_tdata(v_cresample_0_video_out_TDATA),
.s_axis_video_tlast(v_cresample_0_video_out_TLAST),
.s_axis_video_tready(v_cresample_0_video_out_TREADY),
.s_axis_video_tuser(v_cresample_0_video_out_TUSER),
.s_axis_video_tvalid(v_cresample_0_video_out_TVALID),
.vid_active_video(v_axi4s_vid_out_0_vid_io_out_ACTIVE_VIDEO),
.vid_data(v_axi4s_vid_out_0_vid_io_out_DATA),
.vid_hsync(v_axi4s_vid_out_0_vid_io_out_HSYNC),
.vid_io_out_ce(vcc_const),
.vid_io_out_clk(clk_1),
.vid_vsync(v_axi4s_vid_out_0_vid_io_out_VSYNC),
.vtg_active_video(v_tc_0_vtiming_out_ACTIVE_VIDEO),
.vtg_ce(v_axi4s_vid_out_0_vtg_ce),
.vtg_field_id(GND_2),
.vtg_hblank(v_tc_0_vtiming_out_HBLANK),
.vtg_hsync(v_tc_0_vtiming_out_HSYNC),
.vtg_vblank(v_tc_0_vtiming_out_VBLANK),
.vtg_vsync(v_tc_0_vtiming_out_VSYNC));
tutorial_v_cfa_0_0 v_cfa_0
(.aclk(processing_system7_0_fclk_clk1),
.aclken(vcc_const),
.aresetn(vcc_const),
.m_axis_video_tdata(v_cfa_0_video_out_TDATA),
.m_axis_video_tlast(v_cfa_0_video_out_TLAST),
.m_axis_video_tready(v_cfa_0_video_out_TREADY),
.m_axis_video_tuser(v_cfa_0_video_out_TUSER),
.m_axis_video_tvalid(v_cfa_0_video_out_TVALID),
.s_axis_video_tdata(v_tpg_0_video_out_TDATA),
.s_axis_video_tlast(v_tpg_0_video_out_TLAST),
.s_axis_video_tready(v_tpg_0_video_out_TREADY),
.s_axis_video_tuser(v_tpg_0_video_out_TUSER),
.s_axis_video_tvalid(v_tpg_0_video_out_TVALID));
tutorial_v_cresample_0_0 v_cresample_0
(.aclk(processing_system7_0_fclk_clk1),
.aclken(vcc_const),
.aresetn(vcc_const),
.m_axis_video_tdata(v_cresample_0_video_out_TDATA),
.m_axis_video_tlast(v_cresample_0_video_out_TLAST),
.m_axis_video_tready(v_cresample_0_video_out_TREADY),
.m_axis_video_tuser(v_cresample_0_video_out_TUSER),
.m_axis_video_tvalid(v_cresample_0_video_out_TVALID),
.s_axis_video_tdata(v_rgb2ycrcb_0_video_out_TDATA),
.s_axis_video_tlast(v_rgb2ycrcb_0_video_out_TLAST),
.s_axis_video_tready(v_rgb2ycrcb_0_video_out_TREADY),
.s_axis_video_tuser(v_rgb2ycrcb_0_video_out_TUSER),
.s_axis_video_tvalid(v_rgb2ycrcb_0_video_out_TVALID));
tutorial_v_rgb2ycrcb_0_0 v_rgb2ycrcb_0
(.aclk(processing_system7_0_fclk_clk1),
.aclken(vcc_const),
.aresetn(vcc_const),
.m_axis_video_tdata(v_rgb2ycrcb_0_video_out_TDATA),
.m_axis_video_tlast(v_rgb2ycrcb_0_video_out_TLAST),
.m_axis_video_tready(v_rgb2ycrcb_0_video_out_TREADY),
.m_axis_video_tuser_sof(v_rgb2ycrcb_0_video_out_TUSER),
.m_axis_video_tvalid(v_rgb2ycrcb_0_video_out_TVALID),
.s_axis_video_tdata(pixelq_op_0_OUTPUT_STREAM_TDATA),
.s_axis_video_tlast(pixelq_op_0_OUTPUT_STREAM_TLAST),
.s_axis_video_tready(pixelq_op_0_OUTPUT_STREAM_TREADY),
.s_axis_video_tuser_sof(pixelq_op_0_OUTPUT_STREAM_TUSER),
.s_axis_video_tvalid(pixelq_op_0_OUTPUT_STREAM_TVALID));
tutorial_v_tc_0_0 v_tc_0
(.active_video_out(v_tc_0_vtiming_out_ACTIVE_VIDEO),
.clk(clk_1),
.clken(vcc_const),
.fsync_in(GND_2),
.gen_clken(v_axi4s_vid_out_0_vtg_ce),
.hblank_out(v_tc_0_vtiming_out_HBLANK),
.hsync_out(v_tc_0_vtiming_out_HSYNC),
.resetn(vcc_const),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_aclken(vcc_const),
.s_axi_araddr(Conn1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(Conn1_ARREADY),
.s_axi_arvalid(Conn1_ARVALID),
.s_axi_awaddr(Conn1_AWADDR),
.s_axi_awready(Conn1_AWREADY),
.s_axi_awvalid(Conn1_AWVALID),
.s_axi_bready(Conn1_BREADY),
.s_axi_bresp(Conn1_BRESP),
.s_axi_bvalid(Conn1_BVALID),
.s_axi_rdata(Conn1_RDATA),
.s_axi_rready(Conn1_RREADY),
.s_axi_rresp(Conn1_RRESP),
.s_axi_rvalid(Conn1_RVALID),
.s_axi_wdata(Conn1_WDATA),
.s_axi_wready(Conn1_WREADY),
.s_axi_wstrb(Conn1_WSTRB),
.s_axi_wvalid(Conn1_WVALID),
.vblank_out(v_tc_0_vtiming_out_VBLANK),
.vsync_out(v_tc_0_vtiming_out_VSYNC));
tutorial_v_tpg_0_0 v_tpg_0
(.aclk(processing_system7_0_fclk_clk1),
.aclken(vcc_const),
.aresetn(vcc_const),
.m_axis_video_tdata(v_tpg_0_video_out_TDATA),
.m_axis_video_tlast(v_tpg_0_video_out_TLAST),
.m_axis_video_tready(v_tpg_0_video_out_TREADY),
.m_axis_video_tuser(v_tpg_0_video_out_TUSER),
.m_axis_video_tvalid(v_tpg_0_video_out_TVALID),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_aclken(vcc_const),
.s_axi_araddr(Conn4_ARADDR),
.s_axi_aresetn(vcc_const),
.s_axi_arready(Conn4_ARREADY),
.s_axi_arvalid(Conn4_ARVALID),
.s_axi_awaddr(Conn4_AWADDR),
.s_axi_awready(Conn4_AWREADY),
.s_axi_awvalid(Conn4_AWVALID),
.s_axi_bready(Conn4_BREADY),
.s_axi_bresp(Conn4_BRESP),
.s_axi_bvalid(Conn4_BVALID),
.s_axi_rdata(Conn4_RDATA),
.s_axi_rready(Conn4_RREADY),
.s_axi_rresp(Conn4_RRESP),
.s_axi_rvalid(Conn4_RVALID),
.s_axi_wdata(Conn4_WDATA),
.s_axi_wready(Conn4_WREADY),
.s_axi_wstrb(Conn4_WSTRB),
.s_axi_wvalid(Conn4_WVALID));
tutorial_vcc_0 vcc
(.dout(vcc_const));
tutorial_zed_hdmi_out_0_0 zed_hdmi_out_0
(.audio_spdif(gnd_const),
.clk(clk_1),
.io_hdmio_clk(zed_hdmi_out_0_io_hdmio_CLK),
.io_hdmio_de(zed_hdmi_out_0_io_hdmio_DE),
.io_hdmio_hsync(zed_hdmi_out_0_io_hdmio_HSYNC),
.io_hdmio_spdif(zed_hdmi_out_0_io_hdmio_SPDIF),
.io_hdmio_video(zed_hdmi_out_0_io_hdmio_DATA),
.io_hdmio_vsync(zed_hdmi_out_0_io_hdmio_VSYNC),
.reset(gnd_const),
.video_data(v_axi4s_vid_out_0_vid_io_out_DATA),
.video_de(v_axi4s_vid_out_0_vid_io_out_ACTIVE_VIDEO),
.video_hsync(v_axi4s_vid_out_0_vid_io_out_HSYNC),
.video_vsync(v_axi4s_vid_out_0_vid_io_out_VSYNC));
endmodule
|
`default_nettype none
// ============================================================================
module error_counter #
(
parameter COUNT_WIDTH = 24,
parameter DELAY_TAPS = 32,
parameter TRIGGER_INTERVAL = 20,//100000000,
parameter HOLDOFF_TIME = 4,//10,
parameter MEASURE_TIME = 10//50000
)
(
input wire CLK,
input wire RST,
input wire I_STB,
input wire I_ERR,
output wire DLY_LD,
output wire [$clog2(DELAY_TAPS)-1:0] DLY_CNT,
output wire O_STB,
output wire [COUNT_WIDTH*DELAY_TAPS-1:0] O_DAT
);
// ============================================================================
// FSM
integer fsm;
localparam FSM_IDLE = 'h00;
localparam FSM_SETUP = 'h10;
localparam FSM_HOLDOFF = 'h20;
localparam FSM_PREPARE = 'h30;
localparam FSM_MEASURE = 'h40;
localparam FSM_STORE = 'h50;
localparam FSM_OUTPUT = 'h60;
// ============================================================================
// Counters
reg [32:0] ps_cnt;
reg [$clog2(DELAY_TAPS)-1:0] dly_cnt;
initial ps_cnt <= TRIGGER_INTERVAL - 1;
always @(posedge CLK)
case (fsm)
FSM_IDLE: ps_cnt <= ps_cnt - 1;
FSM_SETUP: ps_cnt <= HOLDOFF_TIME - 1;
FSM_HOLDOFF: ps_cnt <= ps_cnt - 1;
FSM_PREPARE: ps_cnt <= MEASURE_TIME - 1;
FSM_MEASURE: ps_cnt <= ps_cnt - 1;
FSM_OUTPUT: ps_cnt <= TRIGGER_INTERVAL - 1;
endcase
always @(posedge CLK)
case (fsm)
FSM_IDLE: dly_cnt <= 0;
FSM_STORE: dly_cnt <= dly_cnt + 1;
endcase
// ============================================================================
// IDELAY control
assign DLY_LD = (fsm == FSM_SETUP);
assign DLY_CNT = dly_cnt;
// ============================================================================
// Error counter and output shift register
reg [(COUNT_WIDTH*DELAY_TAPS)-1:0] o_dat_sr;
reg [COUNT_WIDTH-1:0] err_cnt;
always @(posedge CLK)
case (fsm)
FSM_PREPARE: err_cnt <= 0;
FSM_MEASURE: if(I_STB) err_cnt <= err_cnt + I_ERR;
endcase
always @(posedge CLK)
if (fsm == FSM_STORE)
o_dat_sr <= (o_dat_sr << COUNT_WIDTH) | err_cnt;
// ============================================================================
// Control FSM
always @(posedge CLK)
if (RST)
fsm <= FSM_IDLE;
else case (fsm)
FSM_IDLE: if (ps_cnt == 0) fsm <= FSM_SETUP;
FSM_SETUP: fsm <= FSM_HOLDOFF;
FSM_HOLDOFF: if (ps_cnt == 0) fsm <= FSM_PREPARE;
FSM_PREPARE: fsm <= FSM_MEASURE;
FSM_MEASURE: if (ps_cnt == 0) fsm <= FSM_STORE;
FSM_STORE: if (dly_cnt == (DELAY_TAPS-1))
fsm <= FSM_OUTPUT;
else
fsm <= FSM_SETUP;
FSM_OUTPUT: fsm <= FSM_IDLE;
endcase
// ============================================================================
// Output
assign O_STB = (fsm == FSM_OUTPUT);
assign O_DAT = o_dat_sr;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_1_V
`define SKY130_FD_SC_LP__XNOR2_1_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_1_V
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: rxuart.v
// {{{
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: Receive and decode inputs from a single UART line.
//
//
// To interface with this module, connect it to your system clock,
// pass it the 32 bit setup register (defined below) and the UART
// input. When data becomes available, the o_wr line will be asserted
// for one clock cycle. On parity or frame errors, the o_parity_err
// or o_frame_err lines will be asserted. Likewise, on a break
// condition, o_break will be asserted. These lines are self clearing.
//
// There is a synchronous reset line, logic high.
//
// Now for the setup register. The register is 32 bits, so that this
// UART may be set up over a 32-bit bus.
//
// i_setup[30] True if we are not using hardware flow control. This bit
// is ignored within this module, as any receive hardware flow
// control will need to be implemented elsewhere.
//
// i_setup[29:28] Indicates the number of data bits per word. This will
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
// for a six bit word, or 2'b11 for a five bit word.
//
// i_setup[27] Indicates whether or not to use one or two stop bits.
// Set this to one to expect two stop bits, zero for one.
//
// i_setup[26] Indicates whether or not a parity bit exists. Set this
// to 1'b1 to include parity.
//
// i_setup[25] Indicates whether or not the parity bit is fixed. Set
// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
// parity to be set based upon data. (Both assume the parity
// enable value is set.)
//
// i_setup[24] This bit is ignored if parity is not used. Otherwise,
// in the case of a fixed parity bit, this bit indicates whether
// mark (1'b1) or space (1'b0) parity is used. Likewise if the
// parity is not fixed, a 1'b1 selects even parity, and 1'b0
// selects odd.
//
// i_setup[23:0] Indicates the speed of the UART in terms of clocks.
// So, for example, if you have a 200 MHz clock and wish to
// run your UART at 9600 baud, you would take 200 MHz and divide
// by 9600 to set this value to 24'd20834. Likewise if you wished
// to run this serial port at 115200 baud from a 200 MHz clock,
// you would set the value to 24'd1736
//
// Thus, to set the UART for the common setting of an 8-bit word,
// one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
// would want to set the setup value to:
//
// 32'h0006c8 // For 115,200 baud, 8 bit, no parity
// 32'h005161 // For 9600 baud, 8 bit, no parity
//
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2015-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
// }}}
module rxuart #(
// {{{
// 8 data bits, no parity, (at least 1) stop bit
parameter [30:0] INITIAL_SETUP = 31'd868,
// States: (@ baud counter == 0)
// 0 First bit arrives
// ..7 Bits arrive
// 8 Stop bit (x1)
// 9 Stop bit (x2)
// c break condition
// d Waiting for the channel to go high
// e Waiting for the reset to complete
// f Idle state
localparam [3:0] RXU_BIT_ZERO = 4'h0,
RXU_BIT_ONE = 4'h1,
RXU_BIT_TWO = 4'h2,
RXU_BIT_THREE = 4'h3,
// RXU_BIT_FOUR = 4'h4, // UNUSED
// RXU_BIT_FIVE = 4'h5, // UNUSED
// RXU_BIT_SIX = 4'h6, // UNUSED
RXU_BIT_SEVEN = 4'h7,
RXU_PARITY = 4'h8,
RXU_STOP = 4'h9,
RXU_SECOND_STOP = 4'ha,
// Unused 4'hb
// Unused 4'hc
RXU_BREAK = 4'hd,
RXU_RESET_IDLE = 4'he,
RXU_IDLE = 4'hf
// }}}
) (
// {{{
input wire i_clk, i_reset,
/* verilator lint_off UNUSED */
input wire [30:0] i_setup,
/* verilator lint_on UNUSED */
input wire i_uart_rx,
output reg o_wr,
output reg [7:0] o_data,
output reg o_break,
output reg o_parity_err, o_frame_err,
output wire o_ck_uart
// }}}
);
// Signal declarations
// {{{
wire [27:0] clocks_per_baud, break_condition, half_baud;
wire [1:0] data_bits;
wire use_parity, parity_even, dblstop, fixd_parity;
reg [29:0] r_setup;
reg [3:0] state;
reg [27:0] baud_counter;
reg zero_baud_counter;
reg q_uart, qq_uart, ck_uart;
reg [27:0] chg_counter;
reg line_synch;
reg half_baud_time;
reg [7:0] data_reg;
reg calc_parity;
reg pre_wr;
assign clocks_per_baud = { 4'h0, r_setup[23:0] };
// assign hw_flow_control = !r_setup[30];
assign data_bits = r_setup[29:28];
assign dblstop = r_setup[27];
assign use_parity = r_setup[26];
assign fixd_parity = r_setup[25];
assign parity_even = r_setup[24];
assign break_condition = { r_setup[23:0], 4'h0 };
assign half_baud = { 5'h00, r_setup[23:1] }-28'h1;
// }}}
// ck_uart
// {{{
// Since this is an asynchronous receiver, we need to register our
// input a couple of clocks over to avoid any problems with
// metastability. We do that here, and then ignore all but the
// ck_uart wire.
initial q_uart = 1'b0;
initial qq_uart = 1'b0;
initial ck_uart = 1'b0;
always @(posedge i_clk)
begin
q_uart <= i_uart_rx;
qq_uart <= q_uart;
ck_uart <= qq_uart;
end
// }}}
// o_ck_uart
// {{{
// In case anyone else wants this clocked, stabilized value, we
// offer it on our output.
assign o_ck_uart = ck_uart;
// }}}
// chg_counter
// {{{
// Keep track of the number of clocks since the last change.
//
// This is used to determine if we are in either a break or an idle
// condition, as discussed further below.
initial chg_counter = 28'h00;
always @(posedge i_clk)
if (i_reset)
chg_counter <= 28'h00;
else if (qq_uart != ck_uart)
chg_counter <= 28'h00;
else if (chg_counter < break_condition)
chg_counter <= chg_counter + 1;
// }}}
// o_break
// {{{
// Are we in a break condition?
//
// A break condition exists if the line is held low for longer than
// a data word. Hence, we keep track of when the last change occurred.
// If it was more than break_condition clocks ago, and the current input
// value is a 0, then we're in a break--and nothing can be read until
// the line idles again.
initial o_break = 1'b0;
always @(posedge i_clk)
o_break <= ((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;
// }}}
// line_synch
// {{{
// Are we between characters?
//
// The opposite of a break condition is where the line is held high
// for more clocks than would be in a character. When this happens,
// we know we have synchronization--otherwise, we might be sampling
// from within a data word.
//
// This logic is used later to hold the RXUART in a reset condition
// until we know we are between data words. At that point, we should
// be able to hold on to our synchronization.
initial line_synch = 1'b0;
always @(posedge i_clk)
line_synch <= ((chg_counter >= break_condition)&&(ck_uart));
// }}}
// half_baud_time
// {{{
// Are we in the middle of a baud iterval? Specifically, are we
// in the middle of a start bit? Set this to high if so. We'll use
// this within our state machine to transition out of the IDLE
// state.
initial half_baud_time = 0;
always @(posedge i_clk)
half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);
// }}}
// r_setup
// {{{
// Allow our controlling processor to change our setup at any time
// outside of receiving/processing a character.
initial r_setup = INITIAL_SETUP[29:0];
always @(posedge i_clk)
if (state >= RXU_RESET_IDLE)
r_setup <= i_setup[29:0];
// }}}
// state -- the monster state machine
// {{{
// Our monster state machine. YIKES!
//
// Yeah, this may be more complicated than it needs to be. The basic
// progression is:
// RESET -> RESET_IDLE -> (when line is idle) -> IDLE
// IDLE -> bit 0 -> bit 1 -> bit_{ndatabits} ->
// (optional) PARITY -> STOP -> (optional) SECOND_STOP
// -> IDLE
// ANY -> (on break) BREAK -> IDLE
//
// There are 16 states, although all are not used. These are listed
// at the top of this file.
//
// Logic inputs (12): (I've tried to minimize this number)
// state (4)
// i_reset
// line_synch
// o_break
// ckuart
// half_baud_time
// zero_baud_counter
// use_parity
// dblstop
// Logic outputs (4):
// state
//
initial state = RXU_RESET_IDLE;
always @(posedge i_clk)
if (i_reset)
state <= RXU_RESET_IDLE;
else if (state == RXU_RESET_IDLE)
begin
// {{{
if (line_synch)
// Goto idle state from a reset
state <= RXU_IDLE;
else // Otherwise, stay in this condition 'til reset
state <= RXU_RESET_IDLE;
// }}}
end else if (o_break)
begin // We are in a break condition
state <= RXU_BREAK;
end else if (state == RXU_BREAK)
begin // Goto idle state following return ck_uart going high
// {{{
if (ck_uart)
state <= RXU_IDLE;
else
state <= RXU_BREAK;
// }}}
end else if (state == RXU_IDLE)
begin // Idle state, independent of baud counter
// {{{
if ((~ck_uart)&&(half_baud_time))
begin
// We are in the center of a valid start bit
case (data_bits)
2'b00: state <= RXU_BIT_ZERO;
2'b01: state <= RXU_BIT_ONE;
2'b10: state <= RXU_BIT_TWO;
2'b11: state <= RXU_BIT_THREE;
endcase
end else // Otherwise, just stay here in idle
state <= RXU_IDLE;
// }}}
end else if (zero_baud_counter)
begin
// {{{
if (state < RXU_BIT_SEVEN)
// Data arrives least significant bit first.
// By the time this is clocked in, it's what
// you'll have.
state <= state + 1;
else if (state == RXU_BIT_SEVEN)
state <= (use_parity) ? RXU_PARITY:RXU_STOP;
else if (state == RXU_PARITY)
state <= RXU_STOP;
else if (state == RXU_STOP)
begin // Stop (or parity) bit(s)
if (~ck_uart) // On frame error, wait 4 ch idle
state <= RXU_RESET_IDLE;
else if (dblstop)
state <= RXU_SECOND_STOP;
else
state <= RXU_IDLE;
end else // state must equal RX_SECOND_STOP
begin
if (~ck_uart) // On frame error, wait 4 ch idle
state <= RXU_RESET_IDLE;
else
state <= RXU_IDLE;
end
// }}}
end
// }}}
// data_reg -- Data bit capture logic.
// {{{
// This is drastically simplified from the state machine above, based
// upon: 1) it doesn't matter what it is until the end of a captured
// byte, and 2) the data register will flush itself of any invalid
// data in all other cases. Hence, let's keep it real simple.
// The only trick, though, is that if we have parity, then the data
// register needs to be held through that state without getting
// updated.
always @(posedge i_clk)
if ((zero_baud_counter)&&(state != RXU_PARITY))
data_reg <= { ck_uart, data_reg[7:1] };
// }}}
// calc_parity
// {{{
// Parity calculation logic
//
// As with the data capture logic, all that must be known about this
// bit is that it is the exclusive-OR of all bits prior. The first
// of those will follow idle, so we set ourselves to zero on idle.
// Then, as we walk through the states of a bit, all will adjust this
// value up until the parity bit, where the value will be read. Setting
// it then or after will be irrelevant, so ... this should be good
// and simplified. Note--we don't need to adjust this on reset either,
// since the reset state will lead to the idle state where we'll be
// reset before any transmission takes place.
always @(posedge i_clk)
if (state == RXU_IDLE)
calc_parity <= 0;
else if (zero_baud_counter)
calc_parity <= calc_parity ^ ck_uart;
// }}}
// o_parity_err -- Parity error logic
// {{{
// Set during the parity bit interval, read during the last stop bit
// interval, cleared on BREAK, RESET_IDLE, or IDLE states.
initial o_parity_err = 1'b0;
always @(posedge i_clk)
if ((zero_baud_counter)&&(state == RXU_PARITY))
begin
if (fixd_parity)
// Fixed parity bit--independent of any dat
// value.
o_parity_err <= (ck_uart ^ parity_even);
else if (parity_even)
// Parity even: The XOR of all bits including
// the parity bit must be zero.
o_parity_err <= (calc_parity != ck_uart);
else
// Parity odd: the parity bit must equal the
// XOR of all the data bits.
o_parity_err <= (calc_parity == ck_uart);
end else if (state >= RXU_BREAK)
o_parity_err <= 1'b0;
// }}}
// o_frame_err -- Frame error determination
// {{{
// For the purpose of this controller, a frame error is defined as a
// stop bit (or second stop bit, if so enabled) not being high midway
// through the stop baud interval. The frame error value is
// immediately read, so we can clear it under all other circumstances.
// Specifically, we want it clear in RXU_BREAK, RXU_RESET_IDLE, and
// most importantly in RXU_IDLE.
initial o_frame_err = 1'b0;
always @(posedge i_clk)
if ((zero_baud_counter)&&((state == RXU_STOP)
||(state == RXU_SECOND_STOP)))
o_frame_err <= (o_frame_err)||(~ck_uart);
else if ((zero_baud_counter)||(state >= RXU_BREAK))
o_frame_err <= 1'b0;
// }}}
// pre_wr, o_data
// {{{
// Our data bit logic doesn't need nearly the complexity of all that
// work above. Indeed, we only need to know if we are at the end of
// a stop bit, in which case we copy the data_reg into our output
// data register, o_data.
//
// We would also set o_wr to be true when this is the case, but ... we
// won't know if there is a frame error on the second stop bit for
// another baud interval yet. So, instead, we set up the logic so that
// we know on the next zero baud counter that we can write out. That's
// the purpose of pre_wr.
initial o_data = 8'h00;
initial pre_wr = 1'b0;
always @(posedge i_clk)
if (i_reset)
begin
pre_wr <= 1'b0;
o_data <= 8'h00;
end else if ((zero_baud_counter)&&(state == RXU_STOP))
begin
pre_wr <= 1'b1;
case (data_bits)
2'b00: o_data <= data_reg;
2'b01: o_data <= { 1'b0, data_reg[7:1] };
2'b10: o_data <= { 2'b0, data_reg[7:2] };
2'b11: o_data <= { 3'b0, data_reg[7:3] };
endcase
end else if ((zero_baud_counter)||(state == RXU_IDLE))
pre_wr <= 1'b0;
// }}}
// o_wr
// {{{
// Create an output strobe, true for one clock only, once we know
// all we need to know. o_data will be set on the last baud interval,
// o_parity_err on the last parity baud interval (if it existed,
// cleared otherwise, so ... we should be good to go here.)
initial o_wr = 1'b0;
always @(posedge i_clk)
if ((zero_baud_counter)||(state == RXU_IDLE))
o_wr <= (pre_wr)&&(!i_reset);
else
o_wr <= 1'b0;
// }}}
// The baud counter
// {{{
// This is used as a "clock divider" if you will, but the clock needs
// to be reset before any byte can be decoded. In all other respects,
// we set ourselves up for clocks_per_baud counts between baud
// intervals.
always @(posedge i_clk)
if (i_reset)
baud_counter <= clocks_per_baud-28'h01;
else if (zero_baud_counter)
baud_counter <= clocks_per_baud-28'h01;
else case(state)
RXU_RESET_IDLE:baud_counter <= clocks_per_baud-28'h01;
RXU_BREAK: baud_counter <= clocks_per_baud-28'h01;
RXU_IDLE: baud_counter <= clocks_per_baud-28'h01;
default: baud_counter <= baud_counter-28'h01;
endcase
// }}}
// zero_baud_counter
// {{{
// Rather than testing whether or not (baud_counter == 0) within our
// (already too complicated) state transition tables, we use
// zero_baud_counter to pre-charge that test on the clock
// before--cleaning up some otherwise difficult timing dependencies.
initial zero_baud_counter = 1'b0;
always @(posedge i_clk)
if (state == RXU_IDLE)
zero_baud_counter <= 1'b0;
else
zero_baud_counter <= (baud_counter == 28'h01);
// }}}
endmodule
|
`timescale 1ns / 1ns
//not a safe module (it pops a value in case of empty stack)
module Stack(input clk,rst,input[1:0] stackCntrl, input[11:0] pushValue, output[11:0] popValue);
reg[2:0] stackPntr;
reg[11:0] data[0:7];
//always@(stackCntrl , posedge rst) //??
always@(posedge clk , posedge rst) //??
if(~rst)
begin
#1;
if(stackCntrl==2'b01)//push
begin
data[stackPntr] = pushValue+1;
stackPntr = stackPntr+1;
end
else if(stackCntrl == 2'b10) //pop
begin
stackPntr = stackPntr-1;
end
end
else
stackPntr = 3'b000;
assign popValue = data[stackPntr];
endmodule
/*module StackTB();
initial begin
$dumpfile("StackTB.vcd");
$dumpvars;
#100 $finish;
end
reg clk,rst;
reg[1:0] stackCntrl;
reg[11:0] pushData;
wire[11:0] popData;
//integer i;
parameter delta = 5;
initial begin clk = 0; forever #delta clk = ~clk; end
Stack UUT(clk,rst,stackCntrl,pushData,popData);
initial begin
rst = 1'b1;
stackCntrl = 2'b01;
pushData = 12'd128;
rst = 1'b0;
#(delta) pushData=12'd100;
#(delta) pushData=12'd101;
#(delta) pushData=12'd102;
#(delta) pushData=12'd103;
stackCntrl = 2'b00;
#(2*delta) stackCntrl=2'b10;
#(5*delta) stackCntrl = 2'b00;
rst=1'b1;
#delta stackCntrl=2'b10;
end
endmodule*/
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:13:37 05/29/2015
// Design Name: subBytes
// Module Name: F:/Projects/Xilinx/Rijndael/test_subbytes.v
// Project Name: Rijndael
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: subBytes
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_subbytes;
// Inputs
reg [7:0] add;
reg invbytes;
// Outputs
wire [7:0] dout;
// Instantiate the Unit Under Test (UUT)
subBytes uut (
.dout(dout),
.add(add),
.invbytes(invbytes)
);
always begin
#20 add = add + 1;
end
initial begin
// Initialize Inputs
add = 0;
invbytes = 0;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DECAP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DECAP_BEHAVIORAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__decap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DECAP_BEHAVIORAL_V
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:05:16 EST 2014
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wmemiS0_SResp O 2 reg
// wmemiS0_SRespLast O 1 reg
// wmemiS0_SData O 128 reg
// wmemiS0_SCmdAccept O 1
// wmemiS0_SDataAccept O 1
// dram_addr O 13
// dram_ba O 3
// dram_ras_n O 1
// dram_cas_n O 1
// dram_we_n O 1
// dram_reset_n O 1
// dram_cs_n O 1
// dram_odt O 1
// dram_cke O 1
// dram_dm O 8
// dram_ck_p O 1
// dram_ck_n O 1
// isInReset O 1 reg
// isReset O 1
// isTrained O 1
// CLK_sys0_clk I 1 clock
// RST_N_sys0_rst I 1 unused
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wmemiS0_MCmd I 3
// wmemiS0_MAddr I 36
// wmemiS0_MBurstLength I 12
// wmemiS0_MData I 128
// wmemiS0_MDataByteEn I 16
// wmemiS0_MReqLast I 1
// wmemiS0_MDataValid I 1
// wmemiS0_MDataLast I 1
// wmemiS0_MReset_n I 1 reg
// dram_io_dq IO 64 inout
// dram_io_dqs_p IO 8 inout
// dram_io_dqs_n IO 8 inout
//
// Combinational paths from inputs to outputs:
// (wmemiS0_MCmd,
// wmemiS0_MAddr,
// wmemiS0_MBurstLength,
// wmemiS0_MReqLast) -> wmemiS0_SCmdAccept
// (wmemiS0_MData,
// wmemiS0_MDataByteEn,
// wmemiS0_MDataValid,
// wmemiS0_MDataLast) -> wmemiS0_SDataAccept
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkDramServer_v6(CLK_sys0_clk,
RST_N_sys0_rst,
wciS0_Clk,
wciS0_MReset_n,
dram_io_dq,
dram_io_dqs_p,
dram_io_dqs_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wmemiS0_MCmd,
wmemiS0_MReqLast,
wmemiS0_MAddr,
wmemiS0_MBurstLength,
wmemiS0_MDataValid,
wmemiS0_MDataLast,
wmemiS0_MData,
wmemiS0_MDataByteEn,
wmemiS0_SResp,
wmemiS0_SRespLast,
wmemiS0_SData,
wmemiS0_SCmdAccept,
wmemiS0_SDataAccept,
wmemiS0_MReset_n,
dram_addr,
dram_ba,
dram_ras_n,
dram_cas_n,
dram_we_n,
dram_reset_n,
dram_cs_n,
dram_odt,
dram_cke,
dram_dm,
dram_ck_p,
dram_ck_n,
isInReset,
isReset,
isTrained);
parameter [0 : 0] hasDebugLogic = 1'b0;
input CLK_sys0_clk;
input RST_N_sys0_rst;
input wciS0_Clk;
input wciS0_MReset_n;
inout [63 : 0] dram_io_dq;
inout [7 : 0] dram_io_dqs_p;
inout [7 : 0] dram_io_dqs_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wmemiS0_mCmd
input [2 : 0] wmemiS0_MCmd;
// action method wmemiS0_mReqLast
input wmemiS0_MReqLast;
// action method wmemiS0_mAddr
input [35 : 0] wmemiS0_MAddr;
// action method wmemiS0_mBurstLength
input [11 : 0] wmemiS0_MBurstLength;
// action method wmemiS0_mDataValid
input wmemiS0_MDataValid;
// action method wmemiS0_mDataLast
input wmemiS0_MDataLast;
// action method wmemiS0_mData
input [127 : 0] wmemiS0_MData;
// action method wmemiS0_mDataByteEn
input [15 : 0] wmemiS0_MDataByteEn;
// value method wmemiS0_sResp
output [1 : 0] wmemiS0_SResp;
// value method wmemiS0_sRespLast
output wmemiS0_SRespLast;
// value method wmemiS0_sData
output [127 : 0] wmemiS0_SData;
// value method wmemiS0_sCmdAccept
output wmemiS0_SCmdAccept;
// value method wmemiS0_sDataAccept
output wmemiS0_SDataAccept;
// action method wmemiS0_mReset_n
input wmemiS0_MReset_n;
// value method dram_addr
output [12 : 0] dram_addr;
// value method dram_ba
output [2 : 0] dram_ba;
// value method dram_ras_n
output dram_ras_n;
// value method dram_cas_n
output dram_cas_n;
// value method dram_we_n
output dram_we_n;
// value method dram_reset_n
output dram_reset_n;
// value method dram_cs_n
output dram_cs_n;
// value method dram_odt
output dram_odt;
// value method dram_cke
output dram_cke;
// value method dram_dm
output [7 : 0] dram_dm;
// value method dram_ck_p
output dram_ck_p;
// value method dram_ck_n
output dram_ck_n;
// value method isInReset
output isInReset;
// value method isReset
output isReset;
// value method isTrained
output isTrained;
// signals for module outputs
wire [127 : 0] wmemiS0_SData;
wire [31 : 0] wciS0_SData;
wire [12 : 0] dram_addr;
wire [7 : 0] dram_dm;
wire [2 : 0] dram_ba;
wire [1 : 0] wciS0_SFlag, wciS0_SResp, wmemiS0_SResp;
wire dram_cas_n,
dram_ck_n,
dram_ck_p,
dram_cke,
dram_cs_n,
dram_odt,
dram_ras_n,
dram_reset_n,
dram_we_n,
isInReset,
isReset,
isTrained,
wciS0_SThreadBusy,
wmemiS0_SCmdAccept,
wmemiS0_SDataAccept,
wmemiS0_SRespLast;
// inlined wires
wire [145 : 0] wmemi_wmemiDh_wget;
wire [130 : 0] wmemi_respF_x_wire_wget;
wire [127 : 0] wmemi_Es_mData_w_wget;
wire [71 : 0] wci_wslv_wciReq_wget;
wire [51 : 0] wmemi_wmemiReq_wget;
wire [35 : 0] wmemi_Es_mAddr_w_wget;
wire [33 : 0] wci_wslv_respF_x_wire_wget;
wire [31 : 0] wci_wci_Es_mAddr_w_wget, wci_wci_Es_mData_w_wget;
wire [15 : 0] wmemi_Es_mDataByteEn_w_wget;
wire [11 : 0] wmemi_Es_mBurstLength_w_wget;
wire [7 : 0] wmemiReadInFlight_acc_v1_wget, wmemiReadInFlight_acc_v2_wget;
wire [3 : 0] wci_wci_Es_mByteEn_w_wget;
wire [2 : 0] wci_wci_Es_mCmd_w_wget,
wci_wslv_wEdge_wget,
wmemi_Es_mCmd_w_wget;
wire memInReset_1_wget,
memInReset_1_whas,
memc_wdfEnd_wget,
memc_wdfEnd_whas,
memc_wdfWren_wget,
memc_wdfWren_whas,
wci_wci_Es_mAddrSpace_w_wget,
wci_wci_Es_mAddrSpace_w_whas,
wci_wci_Es_mAddr_w_whas,
wci_wci_Es_mByteEn_w_whas,
wci_wci_Es_mCmd_w_whas,
wci_wci_Es_mData_w_whas,
wci_wslv_ctlAckReg_1_wget,
wci_wslv_ctlAckReg_1_whas,
wci_wslv_reqF_r_clr_whas,
wci_wslv_reqF_r_deq_whas,
wci_wslv_reqF_r_enq_whas,
wci_wslv_respF_dequeueing_whas,
wci_wslv_respF_enqueueing_whas,
wci_wslv_respF_x_wire_whas,
wci_wslv_sFlagReg_1_wget,
wci_wslv_sFlagReg_1_whas,
wci_wslv_sThreadBusy_pw_whas,
wci_wslv_wEdge_whas,
wci_wslv_wciReq_whas,
wci_wslv_wci_cfrd_pw_whas,
wci_wslv_wci_cfwr_pw_whas,
wci_wslv_wci_ctrl_pw_whas,
wmemiReadInFlight_acc_v1_whas,
wmemiReadInFlight_acc_v2_whas,
wmemi_Es_mAddr_w_whas,
wmemi_Es_mBurstLength_w_whas,
wmemi_Es_mCmd_w_whas,
wmemi_Es_mDataByteEn_w_whas,
wmemi_Es_mDataLast_w_whas,
wmemi_Es_mDataValid_w_whas,
wmemi_Es_mData_w_whas,
wmemi_Es_mReqLast_w_whas,
wmemi_cmdAccept_w_wget,
wmemi_cmdAccept_w_whas,
wmemi_dhAccept_w_wget,
wmemi_dhAccept_w_whas,
wmemi_operateD_1_wget,
wmemi_operateD_1_whas,
wmemi_peerIsReady_1_wget,
wmemi_peerIsReady_1_whas,
wmemi_respF_dequeueing_whas,
wmemi_respF_enqueueing_whas,
wmemi_respF_x_wire_whas,
wmemi_wmemiDh_whas,
wmemi_wmemiReq_whas;
// register dbgCtrl
reg [31 : 0] dbgCtrl;
wire [31 : 0] dbgCtrl_D_IN;
wire dbgCtrl_EN;
// register dramCtrl
reg [31 : 0] dramCtrl;
wire [31 : 0] dramCtrl_D_IN;
wire dramCtrl_EN;
// register mReg
reg [15 : 0] mReg;
wire [15 : 0] mReg_D_IN;
wire mReg_EN;
// register memInReset
reg memInReset;
wire memInReset_D_IN, memInReset_EN;
// register memIsReset_isInReset
reg memIsReset_isInReset;
wire memIsReset_isInReset_D_IN, memIsReset_isInReset_EN;
// register memc_firstBeat
reg memc_firstBeat;
wire memc_firstBeat_D_IN, memc_firstBeat_EN;
// register memc_requestCount
reg [15 : 0] memc_requestCount;
wire [15 : 0] memc_requestCount_D_IN;
wire memc_requestCount_EN;
// register memc_responseCount
reg [15 : 0] memc_responseCount;
wire [15 : 0] memc_responseCount_D_IN;
wire memc_responseCount_EN;
// register memc_secondBeat
reg memc_secondBeat;
wire memc_secondBeat_D_IN, memc_secondBeat_EN;
// register pReg
reg [15 : 0] pReg;
wire [15 : 0] pReg_D_IN;
wire pReg_EN;
// register pioReadInFlight
reg pioReadInFlight;
wire pioReadInFlight_D_IN, pioReadInFlight_EN;
// register rdReg_0
reg [31 : 0] rdReg_0;
wire [31 : 0] rdReg_0_D_IN;
wire rdReg_0_EN;
// register rdReg_1
reg [31 : 0] rdReg_1;
wire [31 : 0] rdReg_1_D_IN;
wire rdReg_1_EN;
// register rdReg_2
reg [31 : 0] rdReg_2;
wire [31 : 0] rdReg_2_D_IN;
wire rdReg_2_EN;
// register rdReg_3
reg [31 : 0] rdReg_3;
wire [31 : 0] rdReg_3_D_IN;
wire rdReg_3_EN;
// register respCount
reg [7 : 0] respCount;
wire [7 : 0] respCount_D_IN;
wire respCount_EN;
// register splitReadInFlight
reg splitReadInFlight;
wire splitReadInFlight_D_IN, splitReadInFlight_EN;
// register uclkUpdateCnt
reg [31 : 0] uclkUpdateCnt;
wire [31 : 0] uclkUpdateCnt_D_IN;
wire uclkUpdateCnt_EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge_D_IN;
wire wci_wslv_cEdge_EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState_D_IN;
wire wci_wslv_cState_EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg_D_IN, wci_wslv_ctlAckReg_EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive_D_IN, wci_wslv_ctlOpActive_EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge_D_IN, wci_wslv_illegalEdge_EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset_D_IN, wci_wslv_isReset_isInReset_EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState_D_IN;
wire wci_wslv_nState_EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg_D_IN;
wire wci_wslv_reqF_countReg_EN;
// register wci_wslv_respF_cntr_r
reg [1 : 0] wci_wslv_respF_cntr_r;
wire [1 : 0] wci_wslv_respF_cntr_r_D_IN;
wire wci_wslv_respF_cntr_r_EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0_D_IN;
wire wci_wslv_respF_q_0_EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1_D_IN;
wire wci_wslv_respF_q_1_EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg_D_IN, wci_wslv_sFlagReg_EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d_D_IN, wci_wslv_sThreadBusy_d_EN;
// register wdReg_0
reg [31 : 0] wdReg_0;
wire [31 : 0] wdReg_0_D_IN;
wire wdReg_0_EN;
// register wdReg_1
reg [31 : 0] wdReg_1;
wire [31 : 0] wdReg_1_D_IN;
wire wdReg_1_EN;
// register wdReg_2
reg [31 : 0] wdReg_2;
wire [31 : 0] wdReg_2_D_IN;
wire wdReg_2_EN;
// register wdReg_3
reg [31 : 0] wdReg_3;
wire [31 : 0] wdReg_3_D_IN;
wire wdReg_3_EN;
// register wmemiRdReq
reg [31 : 0] wmemiRdReq;
wire [31 : 0] wmemiRdReq_D_IN;
wire wmemiRdReq_EN;
// register wmemiRdResp
reg [31 : 0] wmemiRdResp;
wire [31 : 0] wmemiRdResp_D_IN;
wire wmemiRdResp_EN;
// register wmemiReadInFlight_value
reg [7 : 0] wmemiReadInFlight_value;
wire [7 : 0] wmemiReadInFlight_value_D_IN;
wire wmemiReadInFlight_value_EN;
// register wmemiWrReq
reg [31 : 0] wmemiWrReq;
wire [31 : 0] wmemiWrReq_D_IN;
wire wmemiWrReq_EN;
// register wmemi_errorSticky
reg wmemi_errorSticky;
wire wmemi_errorSticky_D_IN, wmemi_errorSticky_EN;
// register wmemi_isReset_isInReset
reg wmemi_isReset_isInReset;
wire wmemi_isReset_isInReset_D_IN, wmemi_isReset_isInReset_EN;
// register wmemi_operateD
reg wmemi_operateD;
wire wmemi_operateD_D_IN, wmemi_operateD_EN;
// register wmemi_peerIsReady
reg wmemi_peerIsReady;
wire wmemi_peerIsReady_D_IN, wmemi_peerIsReady_EN;
// register wmemi_respF_cntr_r
reg [1 : 0] wmemi_respF_cntr_r;
wire [1 : 0] wmemi_respF_cntr_r_D_IN;
wire wmemi_respF_cntr_r_EN;
// register wmemi_respF_q_0
reg [130 : 0] wmemi_respF_q_0;
reg [130 : 0] wmemi_respF_q_0_D_IN;
wire wmemi_respF_q_0_EN;
// register wmemi_respF_q_1
reg [130 : 0] wmemi_respF_q_1;
reg [130 : 0] wmemi_respF_q_1_D_IN;
wire wmemi_respF_q_1_EN;
// register wmemi_statusR
reg [7 : 0] wmemi_statusR;
wire [7 : 0] wmemi_statusR_D_IN;
wire wmemi_statusR_EN;
// register wmemi_trafficSticky
reg wmemi_trafficSticky;
wire wmemi_trafficSticky_D_IN, wmemi_trafficSticky_EN;
// ports of submodule appFull
wire appFull_dD_OUT, appFull_sD_IN, appFull_sEN;
// ports of submodule dbg_cpt_first_edge_cnt
wire [39 : 0] dbg_cpt_first_edge_cnt_dD_OUT, dbg_cpt_first_edge_cnt_sD_IN;
wire dbg_cpt_first_edge_cnt_sEN, dbg_cpt_first_edge_cnt_sRDY;
// ports of submodule dbg_cpt_second_edge_cnt
wire [39 : 0] dbg_cpt_second_edge_cnt_dD_OUT, dbg_cpt_second_edge_cnt_sD_IN;
wire dbg_cpt_second_edge_cnt_sEN, dbg_cpt_second_edge_cnt_sRDY;
// ports of submodule dbg_cpt_tap_cnt
wire [39 : 0] dbg_cpt_tap_cnt_dD_OUT, dbg_cpt_tap_cnt_sD_IN;
wire dbg_cpt_tap_cnt_sEN, dbg_cpt_tap_cnt_sRDY;
// ports of submodule dbg_dq_tap_cnt
wire [39 : 0] dbg_dq_tap_cnt_dD_OUT, dbg_dq_tap_cnt_sD_IN;
wire dbg_dq_tap_cnt_sEN, dbg_dq_tap_cnt_sRDY;
// ports of submodule dbg_dqs_n_tap_cnt
wire [39 : 0] dbg_dqs_n_tap_cnt_dD_OUT, dbg_dqs_n_tap_cnt_sD_IN;
wire dbg_dqs_n_tap_cnt_sEN, dbg_dqs_n_tap_cnt_sRDY;
// ports of submodule dbg_dqs_p_tap_cnt
wire [39 : 0] dbg_dqs_p_tap_cnt_dD_OUT, dbg_dqs_p_tap_cnt_sD_IN;
wire dbg_dqs_p_tap_cnt_sEN, dbg_dqs_p_tap_cnt_sRDY;
// ports of submodule dbg_rd_active_dly
wire [4 : 0] dbg_rd_active_dly_dD_OUT, dbg_rd_active_dly_sD_IN;
wire dbg_rd_active_dly_sEN, dbg_rd_active_dly_sRDY;
// ports of submodule dbg_rd_bitslip_cnt
wire [23 : 0] dbg_rd_bitslip_cnt_dD_OUT, dbg_rd_bitslip_cnt_sD_IN;
wire dbg_rd_bitslip_cnt_sEN, dbg_rd_bitslip_cnt_sRDY;
// ports of submodule dbg_rd_clkdly_cnt
wire [15 : 0] dbg_rd_clkdly_cnt_dD_OUT, dbg_rd_clkdly_cnt_sD_IN;
wire dbg_rd_clkdly_cnt_sEN, dbg_rd_clkdly_cnt_sRDY;
// ports of submodule dbg_rddata
wire [31 : 0] dbg_rddata_dD_OUT, dbg_rddata_sD_IN;
wire dbg_rddata_sEN, dbg_rddata_sRDY;
// ports of submodule dbg_rdlvl_done
wire [1 : 0] dbg_rdlvl_done_dD_OUT, dbg_rdlvl_done_sD_IN;
wire dbg_rdlvl_done_sEN, dbg_rdlvl_done_sRDY;
// ports of submodule dbg_rdlvl_err
wire [1 : 0] dbg_rdlvl_err_dD_OUT, dbg_rdlvl_err_sD_IN;
wire dbg_rdlvl_err_sEN, dbg_rdlvl_err_sRDY;
// ports of submodule dbg_wl_dqs_inverted
wire [7 : 0] dbg_wl_dqs_inverted_dD_OUT, dbg_wl_dqs_inverted_sD_IN;
wire dbg_wl_dqs_inverted_sEN, dbg_wl_dqs_inverted_sRDY;
// ports of submodule dbg_wl_odelay_dq_tap_cnt
wire [39 : 0] dbg_wl_odelay_dq_tap_cnt_dD_OUT,
dbg_wl_odelay_dq_tap_cnt_sD_IN;
wire dbg_wl_odelay_dq_tap_cnt_sEN, dbg_wl_odelay_dq_tap_cnt_sRDY;
// ports of submodule dbg_wl_odelay_dqs_tap_cnt
wire [39 : 0] dbg_wl_odelay_dqs_tap_cnt_dD_OUT,
dbg_wl_odelay_dqs_tap_cnt_sD_IN;
wire dbg_wl_odelay_dqs_tap_cnt_sEN, dbg_wl_odelay_dqs_tap_cnt_sRDY;
// ports of submodule dbg_wr_calib_clk_delay
wire [15 : 0] dbg_wr_calib_clk_delay_dD_OUT, dbg_wr_calib_clk_delay_sD_IN;
wire dbg_wr_calib_clk_delay_sEN, dbg_wr_calib_clk_delay_sRDY;
// ports of submodule firBeat
wire firBeat_dD_OUT, firBeat_sD_IN, firBeat_sEN;
// ports of submodule initComplete
wire initComplete_dD_OUT, initComplete_sD_IN, initComplete_sEN;
// ports of submodule lreqF
reg [176 : 0] lreqF_sD_IN;
wire [176 : 0] lreqF_dD_OUT;
wire lreqF_dDEQ, lreqF_dEMPTY_N, lreqF_sENQ, lreqF_sFULL_N;
// ports of submodule lrespF
wire [127 : 0] lrespF_dD_OUT, lrespF_sD_IN;
wire lrespF_dDEQ, lrespF_dEMPTY_N, lrespF_sENQ, lrespF_sFULL_N;
// ports of submodule memIsResetCC
wire memIsResetCC_dD_OUT, memIsResetCC_sD_IN, memIsResetCC_sEN;
// ports of submodule memc_memc
wire [255 : 0] memc_memc_app_rd_data, memc_memc_app_wdf_data;
wire [63 : 0] memc_memc_ddr3_dq;
wire [39 : 0] memc_memc_dbg_cpt_first_edge_cnt,
memc_memc_dbg_cpt_second_edge_cnt,
memc_memc_dbg_cpt_tap_cnt,
memc_memc_dbg_dq_tap_cnt,
memc_memc_dbg_dqs_n_tap_cnt,
memc_memc_dbg_dqs_p_tap_cnt,
memc_memc_dbg_wl_odelay_dq_tap_cnt,
memc_memc_dbg_wl_odelay_dqs_tap_cnt;
wire [32 : 0] memc_memc_app_addr;
wire [31 : 0] memc_memc_app_wdf_mask, memc_memc_dbg_rddata;
wire [23 : 0] memc_memc_dbg_rd_bitslip_cnt;
wire [15 : 0] memc_memc_dbg_rd_clkdly_cnt, memc_memc_dbg_wr_calib_clk_delay;
wire [12 : 0] memc_memc_ddr3_addr;
wire [7 : 0] memc_memc_dbg_wl_dqs_inverted,
memc_memc_ddr3_dm,
memc_memc_ddr3_dqs_n,
memc_memc_ddr3_dqs_p;
wire [4 : 0] memc_memc_dbg_rd_active_dly;
wire [2 : 0] memc_memc_app_cmd,
memc_memc_dbg_inc_dec_sel,
memc_memc_ddr3_ba;
wire [1 : 0] memc_memc_dbg_rdlvl_done, memc_memc_dbg_rdlvl_err;
wire memc_memc_app_en,
memc_memc_app_rd_data_end,
memc_memc_app_rd_data_valid,
memc_memc_app_rdy,
memc_memc_app_wdf_end,
memc_memc_app_wdf_rdy,
memc_memc_app_wdf_wren,
memc_memc_dbg_dec_cpt,
memc_memc_dbg_dec_rd_dqs,
memc_memc_dbg_inc_cpt,
memc_memc_dbg_inc_rd_dqs,
memc_memc_dbg_ocb_mon_off,
memc_memc_dbg_pd_maintain_0_only,
memc_memc_dbg_pd_maintain_off,
memc_memc_dbg_pd_off,
memc_memc_ddr3_cas_n,
memc_memc_ddr3_ck_n,
memc_memc_ddr3_ck_p,
memc_memc_ddr3_cke,
memc_memc_ddr3_cs_n,
memc_memc_ddr3_odt,
memc_memc_ddr3_ras_n,
memc_memc_ddr3_reset_n,
memc_memc_ddr3_we_n,
memc_memc_phy_init_done,
memc_memc_tb_clk,
memc_memc_tb_rst_n;
// ports of submodule memc_rdpF
wire [1 : 0] memc_rdpF_D_IN, memc_rdpF_D_OUT;
wire memc_rdpF_CLR,
memc_rdpF_DEQ,
memc_rdpF_EMPTY_N,
memc_rdpF_ENQ,
memc_rdpF_FULL_N;
// ports of submodule memc_reqF
wire [176 : 0] memc_reqF_D_IN, memc_reqF_D_OUT;
wire memc_reqF_CLR,
memc_reqF_DEQ,
memc_reqF_EMPTY_N,
memc_reqF_ENQ,
memc_reqF_FULL_N;
// ports of submodule memc_respF
reg [127 : 0] memc_respF_D_IN;
wire [127 : 0] memc_respF_D_OUT;
wire memc_respF_CLR,
memc_respF_DEQ,
memc_respF_EMPTY_N,
memc_respF_ENQ,
memc_respF_FULL_N;
// ports of submodule memc_rst_stretch_n
wire memc_rst_stretch_n_OUT_RST;
// ports of submodule memc_rst_stretch_p
wire memc_rst_stretch_p_RESET_OUT;
// ports of submodule requestCount
wire [15 : 0] requestCount_dD_OUT, requestCount_sD_IN;
wire requestCount_sEN, requestCount_sRDY;
// ports of submodule responseCount
wire [15 : 0] responseCount_dD_OUT, responseCount_sD_IN;
wire responseCount_sEN, responseCount_sRDY;
// ports of submodule secBeat
wire secBeat_dD_OUT, secBeat_sD_IN, secBeat_sEN;
// ports of submodule splaF
wire [1 : 0] splaF_D_IN, splaF_D_OUT;
wire splaF_CLR, splaF_DEQ, splaF_EMPTY_N, splaF_ENQ, splaF_FULL_N;
// ports of submodule wci_uclkUpdateCnt
wire [31 : 0] wci_uclkUpdateCnt_dD_OUT, wci_uclkUpdateCnt_sD_IN;
wire wci_uclkUpdateCnt_sEN, wci_uclkUpdateCnt_sRDY;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF_D_IN, wci_wslv_reqF_D_OUT;
wire wci_wslv_reqF_CLR,
wci_wslv_reqF_DEQ,
wci_wslv_reqF_EMPTY_N,
wci_wslv_reqF_ENQ;
// ports of submodule wdfFull
wire wdfFull_dD_OUT, wdfFull_sD_IN, wdfFull_sEN;
// ports of submodule wmemi_dhF
wire [145 : 0] wmemi_dhF_D_IN, wmemi_dhF_D_OUT;
wire wmemi_dhF_CLR,
wmemi_dhF_DEQ,
wmemi_dhF_EMPTY_N,
wmemi_dhF_ENQ,
wmemi_dhF_FULL_N;
// ports of submodule wmemi_reqF
wire [51 : 0] wmemi_reqF_D_IN, wmemi_reqF_D_OUT;
wire wmemi_reqF_CLR,
wmemi_reqF_DEQ,
wmemi_reqF_EMPTY_N,
wmemi_reqF_ENQ,
wmemi_reqF_FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_advance_response,
WILL_FIRE_RL_memc_advance_readData,
WILL_FIRE_RL_memc_advance_request,
WILL_FIRE_RL_memc_advance_write0,
WILL_FIRE_RL_memc_advance_write1,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wmemi_respF_both,
WILL_FIRE_RL_wmemi_respF_decCtr,
WILL_FIRE_RL_wmemi_respF_incCtr;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2;
wire [176 : 0] MUX_lreqF_enq_1__VAL_1,
MUX_lreqF_enq_1__VAL_2,
MUX_lreqF_enq_1__VAL_3;
wire [130 : 0] MUX_wmemi_respF_q_0_write_1__VAL_1,
MUX_wmemi_respF_q_0_write_1__VAL_2,
MUX_wmemi_respF_q_1_write_1__VAL_1;
wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1,
MUX_wci_wslv_respF_q_1_write_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_3;
wire [7 : 0] MUX_wmemiReadInFlight_value_write_1__VAL_2;
wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2,
MUX_wmemi_respF_cntr_r_write_1__VAL_2;
wire MUX_lreqF_enq_1__PSEL_2,
MUX_lreqF_enq_1__SEL_2,
MUX_lreqF_enq_1__SEL_3,
MUX_memc_firstBeat_write_1__SEL_1,
MUX_memc_secondBeat_write_1__SEL_1,
MUX_rdReg_0_write_1__SEL_1,
MUX_rdReg_1_write_1__SEL_1,
MUX_rdReg_2_write_1__SEL_1,
MUX_rdReg_3_write_1__SEL_1,
MUX_splitReadInFlight_write_1__SEL_1,
MUX_splitReadInFlight_write_1__SEL_2,
MUX_wci_wslv_illegalEdge_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__VAL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_2,
MUX_wci_wslv_respF_q_1_write_1__SEL_1,
MUX_wci_wslv_respF_q_1_write_1__SEL_2,
MUX_wci_wslv_respF_x_wire_wset_1__SEL_2,
MUX_wmemi_respF_q_0_write_1__SEL_1,
MUX_wmemi_respF_q_0_write_1__SEL_2,
MUX_wmemi_respF_q_1_write_1__SEL_1,
MUX_wmemi_respF_q_1_write_1__SEL_2;
// remaining internal signals
reg [63 : 0] v__h19683, v__h3583, v__h3758, v__h3902;
reg [31 : 0] IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674,
g_data__h15477,
x__h5927,
x__h6148;
reg CASE_x385_0b0_memc_respFFULL_N_0b101_memc_res_ETC__q1;
wire [175 : 0] IF_wci_wslv_reqF_first__3_BIT_51_52_THEN_pReg__ETC___d503;
wire [127 : 0] x1_data__h16665, x1_data__h17674;
wire [31 : 0] dramStatus__h14103,
g_data__h19141,
myBE__h5964,
myBE__h5997,
rdat___1__h19204,
rdat___1__h19215,
rdat___1__h19226,
rdat___1__h19237,
rdat___1__h19248,
rdat___1__h19259,
rdat___1__h19270,
rdat___1__h19281,
rdat___1__h19292,
rdat___1__h19303,
rdat___1__h19314,
rdat___1__h19325,
rdat___1__h19336,
rdat___1__h19347,
rdat___1__h19358,
rdat___1__h19369,
rdat___1__h19376,
rdat___1__h19387,
rdat___1__h19398,
rdat___1__h19408,
rdat___1__h19418,
rdat___1__h19432,
rdat___1__h19446,
rdat___1__h19460,
rdat___1__h19474,
rdat___1__h19489,
rdat___1__h19504,
rdat___1__h19519,
rdat___1__h19534,
rdat___1__h19540,
rdat___1__h19546,
rdat___1__h19552,
x1_addr__h17672;
wire [15 : 0] x1_be__h17673, x__h19181;
wire [2 : 0] x__h6385;
wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27,
wmemi_respF_cntr_r_47_MINUS_1___d256;
wire IF_memc_memc_app_rd_data_end__09_CONCAT_memc_r_ETC___d225,
IF_wci_wslv_reqF_first__3_BIT_51_52_THEN_lreqF_ETC___d528,
IF_wmemi_reqF_first__84_BITS_51_TO_49_85_EQ_1__ETC___d393,
_dfoo1,
_dfoo3,
_dfoo5,
_dfoo7,
dbg_rd_active_dly_RDY_write__28_AND_dbg_dqs_p__ETC___d340,
dbg_rdlvl_err_RDY_write__22_AND_dbg_cpt_tap_cn_ETC___d346,
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349,
lrespF_RDY_first__19_AND_NOT_splitReadInFlight_ETC___d437,
lrespF_RDY_first__19_AND_NOT_wmemi_respF_cntr__ETC___d421,
wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d464,
wmemiReadInFlight_value_07_SLT_16___d390,
wmemi_operateD_74_AND_wmemi_peerIsReady_75_76__ETC___d283,
x1__h12825;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wmemiS0_sResp
assign wmemiS0_SResp = wmemi_respF_q_0[130:129] ;
// value method wmemiS0_sRespLast
assign wmemiS0_SRespLast = wmemi_respF_q_0[128] ;
// value method wmemiS0_sData
assign wmemiS0_SData = wmemi_respF_q_0[127:0] ;
// value method wmemiS0_sCmdAccept
assign wmemiS0_SCmdAccept = wmemi_cmdAccept_w_whas ;
// value method wmemiS0_sDataAccept
assign wmemiS0_SDataAccept = wmemi_dhAccept_w_whas ;
// value method dram_addr
assign dram_addr = memc_memc_ddr3_addr ;
// value method dram_ba
assign dram_ba = memc_memc_ddr3_ba ;
// value method dram_ras_n
assign dram_ras_n = memc_memc_ddr3_ras_n ;
// value method dram_cas_n
assign dram_cas_n = memc_memc_ddr3_cas_n ;
// value method dram_we_n
assign dram_we_n = memc_memc_ddr3_we_n ;
// value method dram_reset_n
assign dram_reset_n = memc_memc_ddr3_reset_n ;
// value method dram_cs_n
assign dram_cs_n = memc_memc_ddr3_cs_n ;
// value method dram_odt
assign dram_odt = memc_memc_ddr3_odt ;
// value method dram_cke
assign dram_cke = memc_memc_ddr3_cke ;
// value method dram_dm
assign dram_dm = memc_memc_ddr3_dm ;
// value method dram_ck_p
assign dram_ck_p = memc_memc_ddr3_ck_p ;
// value method dram_ck_n
assign dram_ck_n = memc_memc_ddr3_ck_n ;
// value method isInReset
assign isInReset = memInReset ;
// value method isReset
assign isReset = memIsResetCC_dD_OUT ;
// value method isTrained
assign isTrained = initComplete_dD_OUT ;
// submodule appFull
SyncBit #(.init(1'd0)) appFull(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(appFull_sD_IN),
.sEN(appFull_sEN),
.dD_OUT(appFull_dD_OUT));
// submodule dbg_cpt_first_edge_cnt
SyncRegister #(.width(32'd40),
.init(40'd0)) dbg_cpt_first_edge_cnt(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_cpt_first_edge_cnt_sD_IN),
.sEN(dbg_cpt_first_edge_cnt_sEN),
.dD_OUT(dbg_cpt_first_edge_cnt_dD_OUT),
.sRDY(dbg_cpt_first_edge_cnt_sRDY));
// submodule dbg_cpt_second_edge_cnt
SyncRegister #(.width(32'd40),
.init(40'd0)) dbg_cpt_second_edge_cnt(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_cpt_second_edge_cnt_sD_IN),
.sEN(dbg_cpt_second_edge_cnt_sEN),
.dD_OUT(dbg_cpt_second_edge_cnt_dD_OUT),
.sRDY(dbg_cpt_second_edge_cnt_sRDY));
// submodule dbg_cpt_tap_cnt
SyncRegister #(.width(32'd40),
.init(40'd0)) dbg_cpt_tap_cnt(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_cpt_tap_cnt_sD_IN),
.sEN(dbg_cpt_tap_cnt_sEN),
.dD_OUT(dbg_cpt_tap_cnt_dD_OUT),
.sRDY(dbg_cpt_tap_cnt_sRDY));
// submodule dbg_dq_tap_cnt
SyncRegister #(.width(32'd40),
.init(40'd0)) dbg_dq_tap_cnt(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_dq_tap_cnt_sD_IN),
.sEN(dbg_dq_tap_cnt_sEN),
.dD_OUT(dbg_dq_tap_cnt_dD_OUT),
.sRDY(dbg_dq_tap_cnt_sRDY));
// submodule dbg_dqs_n_tap_cnt
SyncRegister #(.width(32'd40),
.init(40'd0)) dbg_dqs_n_tap_cnt(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_dqs_n_tap_cnt_sD_IN),
.sEN(dbg_dqs_n_tap_cnt_sEN),
.dD_OUT(dbg_dqs_n_tap_cnt_dD_OUT),
.sRDY(dbg_dqs_n_tap_cnt_sRDY));
// submodule dbg_dqs_p_tap_cnt
SyncRegister #(.width(32'd40),
.init(40'd0)) dbg_dqs_p_tap_cnt(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_dqs_p_tap_cnt_sD_IN),
.sEN(dbg_dqs_p_tap_cnt_sEN),
.dD_OUT(dbg_dqs_p_tap_cnt_dD_OUT),
.sRDY(dbg_dqs_p_tap_cnt_sRDY));
// submodule dbg_rd_active_dly
SyncRegister #(.width(32'd5),
.init(5'd0)) dbg_rd_active_dly(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_rd_active_dly_sD_IN),
.sEN(dbg_rd_active_dly_sEN),
.dD_OUT(dbg_rd_active_dly_dD_OUT),
.sRDY(dbg_rd_active_dly_sRDY));
// submodule dbg_rd_bitslip_cnt
SyncRegister #(.width(32'd24),
.init(24'd0)) dbg_rd_bitslip_cnt(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_rd_bitslip_cnt_sD_IN),
.sEN(dbg_rd_bitslip_cnt_sEN),
.dD_OUT(dbg_rd_bitslip_cnt_dD_OUT),
.sRDY(dbg_rd_bitslip_cnt_sRDY));
// submodule dbg_rd_clkdly_cnt
SyncRegister #(.width(32'd16),
.init(16'd0)) dbg_rd_clkdly_cnt(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_rd_clkdly_cnt_sD_IN),
.sEN(dbg_rd_clkdly_cnt_sEN),
.dD_OUT(dbg_rd_clkdly_cnt_dD_OUT),
.sRDY(dbg_rd_clkdly_cnt_sRDY));
// submodule dbg_rddata
SyncRegister #(.width(32'd32),
.init(32'd0)) dbg_rddata(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_rddata_sD_IN),
.sEN(dbg_rddata_sEN),
.dD_OUT(dbg_rddata_dD_OUT),
.sRDY(dbg_rddata_sRDY));
// submodule dbg_rdlvl_done
SyncRegister #(.width(32'd2),
.init(2'd0)) dbg_rdlvl_done(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_rdlvl_done_sD_IN),
.sEN(dbg_rdlvl_done_sEN),
.dD_OUT(dbg_rdlvl_done_dD_OUT),
.sRDY(dbg_rdlvl_done_sRDY));
// submodule dbg_rdlvl_err
SyncRegister #(.width(32'd2),
.init(2'd0)) dbg_rdlvl_err(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_rdlvl_err_sD_IN),
.sEN(dbg_rdlvl_err_sEN),
.dD_OUT(dbg_rdlvl_err_dD_OUT),
.sRDY(dbg_rdlvl_err_sRDY));
// submodule dbg_wl_dqs_inverted
SyncRegister #(.width(32'd8),
.init(8'd0)) dbg_wl_dqs_inverted(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_wl_dqs_inverted_sD_IN),
.sEN(dbg_wl_dqs_inverted_sEN),
.dD_OUT(dbg_wl_dqs_inverted_dD_OUT),
.sRDY(dbg_wl_dqs_inverted_sRDY));
// submodule dbg_wl_odelay_dq_tap_cnt
SyncRegister #(.width(32'd40),
.init(40'd0)) dbg_wl_odelay_dq_tap_cnt(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_wl_odelay_dq_tap_cnt_sD_IN),
.sEN(dbg_wl_odelay_dq_tap_cnt_sEN),
.dD_OUT(dbg_wl_odelay_dq_tap_cnt_dD_OUT),
.sRDY(dbg_wl_odelay_dq_tap_cnt_sRDY));
// submodule dbg_wl_odelay_dqs_tap_cnt
SyncRegister #(.width(32'd40),
.init(40'd0)) dbg_wl_odelay_dqs_tap_cnt(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_wl_odelay_dqs_tap_cnt_sD_IN),
.sEN(dbg_wl_odelay_dqs_tap_cnt_sEN),
.dD_OUT(dbg_wl_odelay_dqs_tap_cnt_dD_OUT),
.sRDY(dbg_wl_odelay_dqs_tap_cnt_sRDY));
// submodule dbg_wr_calib_clk_delay
SyncRegister #(.width(32'd16),
.init(16'd0)) dbg_wr_calib_clk_delay(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(dbg_wr_calib_clk_delay_sD_IN),
.sEN(dbg_wr_calib_clk_delay_sEN),
.dD_OUT(dbg_wr_calib_clk_delay_dD_OUT),
.sRDY(dbg_wr_calib_clk_delay_sRDY));
// submodule firBeat
SyncBit #(.init(1'd0)) firBeat(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(firBeat_sD_IN),
.sEN(firBeat_sEN),
.dD_OUT(firBeat_dD_OUT));
// submodule initComplete
SyncBit #(.init(1'd0)) initComplete(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(initComplete_sD_IN),
.sEN(initComplete_sEN),
.dD_OUT(initComplete_dD_OUT));
// submodule lreqF
SyncFIFO #(.dataWidth(32'd177),
.depth(32'd2),
.indxWidth(32'd1)) lreqF(.sCLK(wciS0_Clk),
.dCLK(memc_memc_tb_clk),
.sRST(wciS0_MReset_n),
.sD_IN(lreqF_sD_IN),
.sENQ(lreqF_sENQ),
.dDEQ(lreqF_dDEQ),
.dD_OUT(lreqF_dD_OUT),
.sFULL_N(lreqF_sFULL_N),
.dEMPTY_N(lreqF_dEMPTY_N));
// submodule lrespF
SyncFIFO #(.dataWidth(32'd128),
.depth(32'd2),
.indxWidth(32'd1)) lrespF(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(lrespF_sD_IN),
.sENQ(lrespF_sENQ),
.dDEQ(lrespF_dDEQ),
.dD_OUT(lrespF_dD_OUT),
.sFULL_N(lrespF_sFULL_N),
.dEMPTY_N(lrespF_dEMPTY_N));
// submodule memIsResetCC
SyncBit #(.init(1'd0)) memIsResetCC(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(memIsResetCC_sD_IN),
.sEN(memIsResetCC_sEN),
.dD_OUT(memIsResetCC_dD_OUT));
// submodule memc_memc
v6_mig37 memc_memc(.sys_rst(memc_rst_stretch_p_RESET_OUT),
.clk_ref(CLK_sys0_clk),
.clk_sys(CLK_sys0_clk),
.app_addr(memc_memc_app_addr),
.app_cmd(memc_memc_app_cmd),
.app_wdf_data(memc_memc_app_wdf_data),
.app_wdf_end(memc_memc_app_wdf_end),
.app_wdf_mask(memc_memc_app_wdf_mask),
.dbg_dec_cpt(memc_memc_dbg_dec_cpt),
.dbg_dec_rd_dqs(memc_memc_dbg_dec_rd_dqs),
.dbg_inc_cpt(memc_memc_dbg_inc_cpt),
.dbg_inc_dec_sel(memc_memc_dbg_inc_dec_sel),
.dbg_inc_rd_dqs(memc_memc_dbg_inc_rd_dqs),
.dbg_ocb_mon_off(memc_memc_dbg_ocb_mon_off),
.dbg_pd_maintain_0_only(memc_memc_dbg_pd_maintain_0_only),
.dbg_pd_maintain_off(memc_memc_dbg_pd_maintain_off),
.dbg_pd_off(memc_memc_dbg_pd_off),
.app_en(memc_memc_app_en),
.app_wdf_wren(memc_memc_app_wdf_wren),
.ddr3_addr(memc_memc_ddr3_addr),
.ddr3_ba(memc_memc_ddr3_ba),
.ddr3_ras_n(memc_memc_ddr3_ras_n),
.ddr3_cas_n(memc_memc_ddr3_cas_n),
.ddr3_we_n(memc_memc_ddr3_we_n),
.ddr3_reset_n(memc_memc_ddr3_reset_n),
.ddr3_cs_n(memc_memc_ddr3_cs_n),
.ddr3_odt(memc_memc_ddr3_odt),
.ddr3_cke(memc_memc_ddr3_cke),
.ddr3_dm(memc_memc_ddr3_dm),
.ddr3_ck_p(memc_memc_ddr3_ck_p),
.ddr3_ck_n(memc_memc_ddr3_ck_n),
.app_rdy(memc_memc_app_rdy),
.app_wdf_rdy(memc_memc_app_wdf_rdy),
.app_rd_data(memc_memc_app_rd_data),
.app_rd_data_end(memc_memc_app_rd_data_end),
.app_rd_data_valid(memc_memc_app_rd_data_valid),
.phy_init_done(memc_memc_phy_init_done),
.dbg_wl_dqs_inverted(memc_memc_dbg_wl_dqs_inverted),
.dbg_wr_calib_clk_delay(memc_memc_dbg_wr_calib_clk_delay),
.dbg_wl_odelay_dqs_tap_cnt(memc_memc_dbg_wl_odelay_dqs_tap_cnt),
.dbg_wl_odelay_dq_tap_cnt(memc_memc_dbg_wl_odelay_dq_tap_cnt),
.dbg_rdlvl_done(memc_memc_dbg_rdlvl_done),
.dbg_rdlvl_err(memc_memc_dbg_rdlvl_err),
.dbg_cpt_tap_cnt(memc_memc_dbg_cpt_tap_cnt),
.dbg_cpt_first_edge_cnt(memc_memc_dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt(memc_memc_dbg_cpt_second_edge_cnt),
.dbg_rd_bitslip_cnt(memc_memc_dbg_rd_bitslip_cnt),
.dbg_rd_clkdly_cnt(memc_memc_dbg_rd_clkdly_cnt),
.dbg_rd_active_dly(memc_memc_dbg_rd_active_dly),
.dbg_dqs_p_tap_cnt(memc_memc_dbg_dqs_p_tap_cnt),
.dbg_dqs_n_tap_cnt(memc_memc_dbg_dqs_n_tap_cnt),
.dbg_dq_tap_cnt(memc_memc_dbg_dq_tap_cnt),
.dbg_rddata(memc_memc_dbg_rddata),
.tb_clk(memc_memc_tb_clk),
.tb_rst_n(memc_memc_tb_rst_n),
.ddr3_dq(dram_io_dq),
.ddr3_dqs_p(dram_io_dqs_p),
.ddr3_dqs_n(dram_io_dqs_n));
// submodule memc_rdpF
arSRLFIFOD #(.width(32'd2),
.l2depth(32'd4)) memc_rdpF(.CLK(memc_memc_tb_clk),
.RST_N(memc_memc_tb_rst_n),
.D_IN(memc_rdpF_D_IN),
.DEQ(memc_rdpF_DEQ),
.ENQ(memc_rdpF_ENQ),
.CLR(memc_rdpF_CLR),
.D_OUT(memc_rdpF_D_OUT),
.EMPTY_N(memc_rdpF_EMPTY_N),
.FULL_N(memc_rdpF_FULL_N));
// submodule memc_reqF
FIFO2 #(.width(32'd177),
.guarded(32'd1)) memc_reqF(.RST(memc_memc_tb_rst_n),
.CLK(memc_memc_tb_clk),
.D_IN(memc_reqF_D_IN),
.ENQ(memc_reqF_ENQ),
.DEQ(memc_reqF_DEQ),
.CLR(memc_reqF_CLR),
.D_OUT(memc_reqF_D_OUT),
.FULL_N(memc_reqF_FULL_N),
.EMPTY_N(memc_reqF_EMPTY_N));
// submodule memc_respF
arSRLFIFOD #(.width(32'd128),
.l2depth(32'd4)) memc_respF(.CLK(memc_memc_tb_clk),
.RST_N(memc_memc_tb_rst_n),
.D_IN(memc_respF_D_IN),
.DEQ(memc_respF_DEQ),
.ENQ(memc_respF_ENQ),
.CLR(memc_respF_CLR),
.D_OUT(memc_respF_D_OUT),
.EMPTY_N(memc_respF_EMPTY_N),
.FULL_N(memc_respF_FULL_N));
// submodule memc_rst_stretch_n
SyncResetA #(.RSTDELAY(32'd15)) memc_rst_stretch_n(.CLK(CLK_sys0_clk),
.IN_RST(wciS0_MReset_n),
.OUT_RST(memc_rst_stretch_n_OUT_RST));
// submodule memc_rst_stretch_p
ResetInverter memc_rst_stretch_p(.RESET_IN(memc_rst_stretch_n_OUT_RST),
.RESET_OUT(memc_rst_stretch_p_RESET_OUT));
// submodule requestCount
SyncRegister #(.width(32'd16),
.init(16'd0)) requestCount(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(requestCount_sD_IN),
.sEN(requestCount_sEN),
.dD_OUT(requestCount_dD_OUT),
.sRDY(requestCount_sRDY));
// submodule responseCount
SyncRegister #(.width(32'd16),
.init(16'd0)) responseCount(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(responseCount_sD_IN),
.sEN(responseCount_sEN),
.dD_OUT(responseCount_dD_OUT),
.sRDY(responseCount_sRDY));
// submodule secBeat
SyncBit #(.init(1'd0)) secBeat(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(secBeat_sD_IN),
.sEN(secBeat_sEN),
.dD_OUT(secBeat_dD_OUT));
// submodule splaF
arSRLFIFOD #(.width(32'd2), .l2depth(32'd4)) splaF(.CLK(wciS0_Clk),
.RST_N(wciS0_MReset_n),
.D_IN(splaF_D_IN),
.DEQ(splaF_DEQ),
.ENQ(splaF_ENQ),
.CLR(splaF_CLR),
.D_OUT(splaF_D_OUT),
.EMPTY_N(splaF_EMPTY_N),
.FULL_N(splaF_FULL_N));
// submodule wci_uclkUpdateCnt
SyncRegister #(.width(32'd32),
.init(32'd0)) wci_uclkUpdateCnt(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(wci_uclkUpdateCnt_sD_IN),
.sEN(wci_uclkUpdateCnt_sEN),
.dD_OUT(wci_uclkUpdateCnt_dD_OUT),
.sRDY(wci_uclkUpdateCnt_sRDY));
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF_D_IN),
.ENQ(wci_wslv_reqF_ENQ),
.DEQ(wci_wslv_reqF_DEQ),
.CLR(wci_wslv_reqF_CLR),
.D_OUT(wci_wslv_reqF_D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF_EMPTY_N));
// submodule wdfFull
SyncBit #(.init(1'd0)) wdfFull(.sCLK(memc_memc_tb_clk),
.dCLK(wciS0_Clk),
.sRST(memc_memc_tb_rst_n),
.sD_IN(wdfFull_sD_IN),
.sEN(wdfFull_sEN),
.dD_OUT(wdfFull_dD_OUT));
// submodule wmemi_dhF
FIFO2 #(.width(32'd146), .guarded(32'd1)) wmemi_dhF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wmemi_dhF_D_IN),
.ENQ(wmemi_dhF_ENQ),
.DEQ(wmemi_dhF_DEQ),
.CLR(wmemi_dhF_CLR),
.D_OUT(wmemi_dhF_D_OUT),
.FULL_N(wmemi_dhF_FULL_N),
.EMPTY_N(wmemi_dhF_EMPTY_N));
// submodule wmemi_reqF
FIFO2 #(.width(32'd52), .guarded(32'd1)) wmemi_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wmemi_reqF_D_IN),
.ENQ(wmemi_reqF_ENQ),
.DEQ(wmemi_reqF_DEQ),
.CLR(wmemi_reqF_CLR),
.D_OUT(wmemi_reqF_D_OUT),
.FULL_N(wmemi_reqF_FULL_N),
.EMPTY_N(wmemi_reqF_EMPTY_N));
// rule RL_advance_response
assign WILL_FIRE_RL_advance_response =
lrespF_dEMPTY_N &&
lrespF_RDY_first__19_AND_NOT_splitReadInFlight_ETC___d437 &&
!wci_wslv_wci_cfwr_pw_whas &&
wmemiReadInFlight_value == 8'd0 &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_wslv_respF_cntr_r != 2'd2 &&
wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d464 &&
wci_wslv_wci_cfwr_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_wslv_reqF_EMPTY_N &&
IF_wci_wslv_reqF_first__3_BIT_51_52_THEN_lreqF_ETC___d528 &&
wci_wslv_wci_cfrd_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd0 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd3 ;
// rule RL_memc_advance_readData
assign WILL_FIRE_RL_memc_advance_readData =
memc_rdpF_EMPTY_N &&
IF_memc_memc_app_rd_data_end__09_CONCAT_memc_r_ETC___d225 &&
memc_memc_phy_init_done &&
memc_memc_app_rd_data_valid ;
// rule RL_memc_advance_request
assign WILL_FIRE_RL_memc_advance_request =
memc_reqF_EMPTY_N &&
(x1__h12825 || !memc_reqF_D_OUT[176] || memc_rdpF_FULL_N) &&
memc_memc_phy_init_done &&
!memc_firstBeat &&
!memc_secondBeat ;
// rule RL_memc_advance_write0
assign WILL_FIRE_RL_memc_advance_write0 =
memc_reqF_EMPTY_N && memc_memc_phy_init_done && memc_firstBeat &&
!memc_secondBeat ;
// rule RL_memc_advance_write1
assign WILL_FIRE_RL_memc_advance_write1 =
memc_reqF_EMPTY_N && memc_memc_phy_init_done &&
!memc_firstBeat &&
memc_secondBeat ;
// rule RL_wmemi_respF_incCtr
assign WILL_FIRE_RL_wmemi_respF_incCtr =
wmemi_respF_enqueueing_whas && wmemi_respF_enqueueing_whas &&
!(wmemi_respF_cntr_r != 2'd0) ;
// rule RL_wmemi_respF_decCtr
assign WILL_FIRE_RL_wmemi_respF_decCtr =
wmemi_respF_cntr_r != 2'd0 && !wmemi_respF_enqueueing_whas ;
// rule RL_wmemi_respF_both
assign WILL_FIRE_RL_wmemi_respF_both =
wmemi_respF_enqueueing_whas && wmemi_respF_cntr_r != 2'd0 &&
wmemi_respF_enqueueing_whas ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd1 ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_enqueueing_whas &&
!(wci_wslv_respF_cntr_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_cntr_r != 2'd0 &&
!wci_wslv_respF_enqueueing_whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_cntr_r != 2'd0 &&
wci_wslv_respF_enqueueing_whas ;
// inputs to muxes for submodule ports
assign MUX_lreqF_enq_1__PSEL_2 =
wmemi_operateD && wmemi_peerIsReady && wmemi_reqF_EMPTY_N &&
IF_wmemi_reqF_first__84_BITS_51_TO_49_85_EQ_1__ETC___d393 &&
!wci_wslv_wci_cfwr_pw_whas &&
!wci_wslv_wci_cfrd_pw_whas ;
assign MUX_lreqF_enq_1__SEL_2 =
MUX_lreqF_enq_1__PSEL_2 &&
(wmemi_reqF_D_OUT[51:49] == 3'd1 ||
wmemiReadInFlight_value_07_SLT_16___d390) ;
assign MUX_lreqF_enq_1__SEL_3 =
WILL_FIRE_RL_wci_cfwr &&
(wci_wslv_reqF_D_OUT[51] ||
wci_wslv_reqF_D_OUT[39:32] == 8'h54 ||
wci_wslv_reqF_D_OUT[39:32] == 8'h58) ;
assign MUX_memc_firstBeat_write_1__SEL_1 =
WILL_FIRE_RL_memc_advance_write0 && memc_memc_app_wdf_rdy ;
assign MUX_memc_secondBeat_write_1__SEL_1 =
WILL_FIRE_RL_memc_advance_write1 && memc_memc_app_wdf_rdy ;
assign MUX_rdReg_0_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h80 ;
assign MUX_rdReg_1_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h84 ;
assign MUX_rdReg_2_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h88 ;
assign MUX_rdReg_3_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h8C ;
assign MUX_splitReadInFlight_write_1__SEL_1 =
WILL_FIRE_RL_advance_response && splitReadInFlight ;
assign MUX_splitReadInFlight_write_1__SEL_2 =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[51] ;
assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ;
assign MUX_wci_wslv_respF_x_wire_wset_1__SEL_2 =
WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF_D_OUT[51] ;
assign MUX_wmemi_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wmemi_respF_both && _dfoo7 ;
assign MUX_wmemi_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd0 ;
assign MUX_wmemi_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wmemi_respF_both && _dfoo5 ;
assign MUX_wmemi_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd1 ;
assign MUX_lreqF_enq_1__VAL_1 =
{ 1'd1,
x1_addr__h17672,
144'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_lreqF_enq_1__VAL_2 =
{ wmemi_reqF_D_OUT[51:49] != 3'd1,
(wmemi_reqF_D_OUT[51:49] == 3'd1) ?
{ wmemi_reqF_D_OUT[43:12],
wmemi_dhF_D_OUT[15:0],
wmemi_dhF_D_OUT[143:16] } :
{ wmemi_reqF_D_OUT[43:0],
132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } } ;
assign MUX_lreqF_enq_1__VAL_3 =
{ !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] != 8'h54,
IF_wci_wslv_reqF_first__3_BIT_51_52_THEN_pReg__ETC___d503 } ;
assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 =
wci_wslv_reqF_D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 =
wci_wslv_respF_cntr_r + 2'd1 ;
assign MUX_wci_wslv_respF_q_0_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd1) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
wci_wslv_respF_q_1 ;
always@(MUX_splitReadInFlight_write_1__SEL_1 or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 or
MUX_wci_wslv_respF_x_wire_wset_1__SEL_2 or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_3 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
MUX_splitReadInFlight_write_1__SEL_1:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1;
MUX_wci_wslv_respF_x_wire_wset_1__SEL_2:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_3;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_1_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd2) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 = { 2'd1, g_data__h15477 } ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, g_data__h19141 } ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_3 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wmemiReadInFlight_value_write_1__VAL_2 =
wmemiReadInFlight_value +
(wmemiReadInFlight_acc_v1_whas ? 8'd1 : 8'd0) +
(wmemi_respF_enqueueing_whas ? 8'd255 : 8'd0) ;
assign MUX_wmemi_respF_cntr_r_write_1__VAL_2 = wmemi_respF_cntr_r + 2'd1 ;
assign MUX_wmemi_respF_q_0_write_1__VAL_1 =
(wmemi_respF_cntr_r == 2'd1) ?
MUX_wmemi_respF_q_0_write_1__VAL_2 :
wmemi_respF_q_1 ;
assign MUX_wmemi_respF_q_0_write_1__VAL_2 = { 3'd3, lrespF_dD_OUT } ;
assign MUX_wmemi_respF_q_1_write_1__VAL_1 =
(wmemi_respF_cntr_r == 2'd2) ?
MUX_wmemi_respF_q_0_write_1__VAL_2 :
131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
// inlined wires
assign wci_wslv_wciReq_wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq_whas = 1'd1 ;
assign wci_wslv_respF_x_wire_wget = MUX_wci_wslv_respF_q_0_write_1__VAL_2 ;
assign wci_wslv_respF_x_wire_whas =
WILL_FIRE_RL_advance_response && splitReadInFlight ||
WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF_D_OUT[51] ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge_wget = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_wEdge_whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1_wget = 1'b0 ;
assign wci_wslv_sFlagReg_1_whas = 1'b0 ;
assign wci_wslv_ctlAckReg_1_wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1_whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w_whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w_whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w_wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w_whas = 1'd1 ;
assign wci_wci_Es_mAddr_w_wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w_whas = 1'd1 ;
assign wci_wci_Es_mData_w_wget = wciS0_MData ;
assign wci_wci_Es_mData_w_whas = 1'd1 ;
assign memc_wdfWren_wget = 1'd1 ;
assign memc_wdfWren_whas =
WILL_FIRE_RL_memc_advance_write1 ||
WILL_FIRE_RL_memc_advance_write0 ;
assign memc_wdfEnd_wget = 1'd1 ;
assign memc_wdfEnd_whas = WILL_FIRE_RL_memc_advance_write1 ;
assign wmemi_wmemiReq_wget =
{ wmemiS0_MCmd,
wmemiS0_MReqLast,
wmemiS0_MAddr,
wmemiS0_MBurstLength } ;
assign wmemi_wmemiReq_whas = 1'd1 ;
assign wmemi_wmemiDh_wget =
{ wmemiS0_MDataValid,
wmemiS0_MDataLast,
wmemiS0_MData,
wmemiS0_MDataByteEn } ;
assign wmemi_wmemiDh_whas = 1'd1 ;
assign wmemi_cmdAccept_w_wget = 1'd1 ;
assign wmemi_cmdAccept_w_whas =
wmemi_reqF_FULL_N &&
wmemi_operateD_74_AND_wmemi_peerIsReady_75_76__ETC___d283 ;
assign wmemi_dhAccept_w_wget = 1'd1 ;
assign wmemi_dhAccept_w_whas =
wmemi_dhF_FULL_N && wmemi_operateD && wmemi_peerIsReady &&
wmemi_wmemiDh_wget[145] &&
wmemi_dhF_FULL_N ;
assign wmemi_respF_x_wire_wget = MUX_wmemi_respF_q_0_write_1__VAL_2 ;
assign wmemi_respF_x_wire_whas = wmemi_respF_enqueueing_whas ;
assign wmemi_operateD_1_wget = 1'd1 ;
assign wmemi_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wmemi_peerIsReady_1_wget = 1'd1 ;
assign wmemi_peerIsReady_1_whas = wmemiS0_MReset_n ;
assign memInReset_1_wget = 1'd0 ;
assign memInReset_1_whas = 1'd1 ;
assign wmemiReadInFlight_acc_v1_wget = 8'd1 ;
assign wmemiReadInFlight_acc_v1_whas =
MUX_lreqF_enq_1__PSEL_2 && wmemi_reqF_D_OUT[51:49] != 3'd1 &&
wmemiReadInFlight_value_07_SLT_16___d390 ;
assign wmemiReadInFlight_acc_v2_wget = 8'd255 ;
assign wmemiReadInFlight_acc_v2_whas = wmemi_respF_enqueueing_whas ;
assign wmemi_Es_mCmd_w_wget = wmemiS0_MCmd ;
assign wmemi_Es_mCmd_w_whas = 1'd1 ;
assign wmemi_Es_mAddr_w_wget = wmemiS0_MAddr ;
assign wmemi_Es_mAddr_w_whas = 1'd1 ;
assign wmemi_Es_mBurstLength_w_wget = wmemiS0_MBurstLength ;
assign wmemi_Es_mBurstLength_w_whas = 1'd1 ;
assign wmemi_Es_mData_w_wget = wmemiS0_MData ;
assign wmemi_Es_mData_w_whas = 1'd1 ;
assign wmemi_Es_mDataByteEn_w_wget = wmemiS0_MDataByteEn ;
assign wmemi_Es_mDataByteEn_w_whas = 1'd1 ;
assign wci_wslv_reqF_r_enq_whas = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr_whas = 1'b0 ;
assign wci_wslv_respF_enqueueing_whas =
WILL_FIRE_RL_advance_response && splitReadInFlight ||
WILL_FIRE_RL_wci_cfrd && !wci_wslv_reqF_D_OUT[51] ||
WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing_whas = wci_wslv_respF_cntr_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw_whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw_whas =
wci_wslv_reqF_EMPTY_N && !wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wmemi_respF_enqueueing_whas =
lrespF_dEMPTY_N &&
lrespF_RDY_first__19_AND_NOT_wmemi_respF_cntr__ETC___d421 &&
(wmemiReadInFlight_value ^ 8'h80) > 8'd128 ;
assign wmemi_respF_dequeueing_whas = wmemi_respF_cntr_r != 2'd0 ;
assign wmemi_Es_mReqLast_w_whas = wmemiS0_MReqLast ;
assign wmemi_Es_mDataValid_w_whas = wmemiS0_MDataValid ;
assign wmemi_Es_mDataLast_w_whas = wmemiS0_MDataLast ;
// register dbgCtrl
assign dbgCtrl_D_IN = 32'h0 ;
assign dbgCtrl_EN = 1'b0 ;
// register dramCtrl
assign dramCtrl_D_IN = wci_wslv_reqF_D_OUT[31:0] ;
assign dramCtrl_EN =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h04 ;
// register mReg
assign mReg_D_IN = wci_wslv_reqF_D_OUT[15:0] ;
assign mReg_EN =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h5C ;
// register memInReset
assign memInReset_D_IN = 1'b0 ;
assign memInReset_EN = 1'd1 ;
// register memIsReset_isInReset
assign memIsReset_isInReset_D_IN = 1'd0 ;
assign memIsReset_isInReset_EN = memIsReset_isInReset ;
// register memc_firstBeat
assign memc_firstBeat_D_IN = !MUX_memc_firstBeat_write_1__SEL_1 ;
assign memc_firstBeat_EN =
WILL_FIRE_RL_memc_advance_write0 && memc_memc_app_wdf_rdy ||
WILL_FIRE_RL_memc_advance_request && memc_memc_app_rdy &&
!memc_reqF_D_OUT[176] ;
// register memc_requestCount
assign memc_requestCount_D_IN = memc_requestCount + 16'd1 ;
assign memc_requestCount_EN =
WILL_FIRE_RL_memc_advance_request && memc_memc_app_rdy ;
// register memc_responseCount
assign memc_responseCount_D_IN = memc_responseCount + 16'd1 ;
assign memc_responseCount_EN = WILL_FIRE_RL_memc_advance_readData ;
// register memc_secondBeat
assign memc_secondBeat_D_IN = !MUX_memc_secondBeat_write_1__SEL_1 ;
assign memc_secondBeat_EN =
WILL_FIRE_RL_memc_advance_write1 && memc_memc_app_wdf_rdy ||
WILL_FIRE_RL_memc_advance_write0 && memc_memc_app_wdf_rdy ;
// register pReg
assign pReg_D_IN = wci_wslv_reqF_D_OUT[15:0] ;
assign pReg_EN =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h50 ;
// register pioReadInFlight
assign pioReadInFlight_D_IN = 1'b0 ;
assign pioReadInFlight_EN = 1'b0 ;
// register rdReg_0
assign rdReg_0_D_IN =
MUX_rdReg_0_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
lrespF_dD_OUT[31:0] ;
assign rdReg_0_EN =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h80 ||
WILL_FIRE_RL_advance_response ;
// register rdReg_1
assign rdReg_1_D_IN =
MUX_rdReg_1_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
lrespF_dD_OUT[63:32] ;
assign rdReg_1_EN =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h84 ||
WILL_FIRE_RL_advance_response ;
// register rdReg_2
assign rdReg_2_D_IN =
MUX_rdReg_2_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
lrespF_dD_OUT[95:64] ;
assign rdReg_2_EN =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h88 ||
WILL_FIRE_RL_advance_response ;
// register rdReg_3
assign rdReg_3_D_IN =
MUX_rdReg_3_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
lrespF_dD_OUT[127:96] ;
assign rdReg_3_EN =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h8C ||
WILL_FIRE_RL_advance_response ;
// register respCount
assign respCount_D_IN = respCount + 8'd1 ;
assign respCount_EN = WILL_FIRE_RL_advance_response ;
// register splitReadInFlight
assign splitReadInFlight_D_IN = !MUX_splitReadInFlight_write_1__SEL_1 ;
assign splitReadInFlight_EN =
WILL_FIRE_RL_advance_response && splitReadInFlight ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[51] ;
// register uclkUpdateCnt
assign uclkUpdateCnt_D_IN = uclkUpdateCnt + 32'd1 ;
assign uclkUpdateCnt_EN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_cEdge_EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState_D_IN = wci_wslv_nState ;
assign wci_wslv_cState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg_D_IN = wci_wslv_ctlAckReg_1_whas ;
assign wci_wslv_ctlAckReg_EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive_D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge_D_IN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge_write_1__VAL_1 ;
assign wci_wslv_illegalEdge_EN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset_EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF_D_OUT)
begin
case (wci_wslv_reqF_D_OUT[36:34])
3'd0: wci_wslv_nState_D_IN = 3'd1;
3'd1: wci_wslv_nState_D_IN = 3'd2;
3'd2: wci_wslv_nState_D_IN = 3'd3;
default: wci_wslv_nState_D_IN = 3'd0;
endcase
end
assign wci_wslv_nState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg_D_IN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg_EN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq_whas ;
// register wci_wslv_respF_cntr_r
assign wci_wslv_respF_cntr_r_D_IN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ?
wci_wslv_respF_cntr_r_8_MINUS_1___d27 :
MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 ;
assign wci_wslv_respF_cntr_r_EN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ||
WILL_FIRE_RL_wci_wslv_respF_incCtr ;
// register wci_wslv_respF_q_0
always@(MUX_wci_wslv_respF_q_0_write_1__SEL_1 or
MUX_wci_wslv_respF_q_0_write_1__VAL_1 or
MUX_wci_wslv_respF_q_0_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_0_write_1__SEL_1:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_1;
MUX_wci_wslv_respF_q_0_write_1__SEL_2:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0_D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(MUX_wci_wslv_respF_q_1_write_1__SEL_1 or
MUX_wci_wslv_respF_q_1_write_1__VAL_1 or
MUX_wci_wslv_respF_q_1_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_1_write_1__SEL_1:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_1_write_1__VAL_1;
MUX_wci_wslv_respF_q_1_write_1__SEL_2:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1_D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg_D_IN = 1'b0 ;
assign wci_wslv_sFlagReg_EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d_D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d_EN = 1'd1 ;
// register wdReg_0
assign wdReg_0_D_IN = wci_wslv_reqF_D_OUT[31:0] ;
assign wdReg_0_EN =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h60 ;
// register wdReg_1
assign wdReg_1_D_IN = wci_wslv_reqF_D_OUT[31:0] ;
assign wdReg_1_EN =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h64 ;
// register wdReg_2
assign wdReg_2_D_IN = wci_wslv_reqF_D_OUT[31:0] ;
assign wdReg_2_EN =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h68 ;
// register wdReg_3
assign wdReg_3_D_IN = wci_wslv_reqF_D_OUT[31:0] ;
assign wdReg_3_EN =
WILL_FIRE_RL_wci_cfwr && !wci_wslv_reqF_D_OUT[51] &&
wci_wslv_reqF_D_OUT[39:32] == 8'h6C ;
// register wmemiRdReq
assign wmemiRdReq_D_IN = wmemiRdReq + 32'd1 ;
assign wmemiRdReq_EN =
MUX_lreqF_enq_1__PSEL_2 && wmemi_reqF_D_OUT[51:49] != 3'd1 &&
wmemiReadInFlight_value_07_SLT_16___d390 ;
// register wmemiRdResp
assign wmemiRdResp_D_IN = wmemiRdResp + 32'd1 ;
assign wmemiRdResp_EN =
lrespF_dEMPTY_N &&
lrespF_RDY_first__19_AND_NOT_wmemi_respF_cntr__ETC___d421 &&
(wmemiReadInFlight_value ^ 8'h80) > 8'd128 ;
// register wmemiReadInFlight_value
assign wmemiReadInFlight_value_D_IN =
WILL_FIRE_RL_wci_ctrl_IsO ?
8'd0 :
MUX_wmemiReadInFlight_value_write_1__VAL_2 ;
assign wmemiReadInFlight_value_EN = 1'b1 ;
// register wmemiWrReq
assign wmemiWrReq_D_IN = wmemiWrReq + 32'd1 ;
assign wmemiWrReq_EN =
MUX_lreqF_enq_1__PSEL_2 && wmemi_reqF_D_OUT[51:49] == 3'd1 ;
// register wmemi_errorSticky
assign wmemi_errorSticky_D_IN = 1'b0 ;
assign wmemi_errorSticky_EN = 1'b0 ;
// register wmemi_isReset_isInReset
assign wmemi_isReset_isInReset_D_IN = 1'd0 ;
assign wmemi_isReset_isInReset_EN = wmemi_isReset_isInReset ;
// register wmemi_operateD
assign wmemi_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wmemi_operateD_EN = 1'd1 ;
// register wmemi_peerIsReady
assign wmemi_peerIsReady_D_IN = wmemiS0_MReset_n ;
assign wmemi_peerIsReady_EN = 1'd1 ;
// register wmemi_respF_cntr_r
assign wmemi_respF_cntr_r_D_IN =
WILL_FIRE_RL_wmemi_respF_decCtr ?
wmemi_respF_cntr_r_47_MINUS_1___d256 :
MUX_wmemi_respF_cntr_r_write_1__VAL_2 ;
assign wmemi_respF_cntr_r_EN =
WILL_FIRE_RL_wmemi_respF_decCtr ||
WILL_FIRE_RL_wmemi_respF_incCtr ;
// register wmemi_respF_q_0
always@(MUX_wmemi_respF_q_0_write_1__SEL_1 or
MUX_wmemi_respF_q_0_write_1__VAL_1 or
MUX_wmemi_respF_q_0_write_1__SEL_2 or
MUX_wmemi_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wmemi_respF_decCtr or wmemi_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wmemi_respF_q_0_write_1__SEL_1:
wmemi_respF_q_0_D_IN = MUX_wmemi_respF_q_0_write_1__VAL_1;
MUX_wmemi_respF_q_0_write_1__SEL_2:
wmemi_respF_q_0_D_IN = MUX_wmemi_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wmemi_respF_decCtr: wmemi_respF_q_0_D_IN = wmemi_respF_q_1;
default: wmemi_respF_q_0_D_IN =
131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_respF_q_0_EN =
WILL_FIRE_RL_wmemi_respF_both && _dfoo7 ||
WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wmemi_respF_decCtr ;
// register wmemi_respF_q_1
always@(MUX_wmemi_respF_q_1_write_1__SEL_1 or
MUX_wmemi_respF_q_1_write_1__VAL_1 or
MUX_wmemi_respF_q_1_write_1__SEL_2 or
MUX_wmemi_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wmemi_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wmemi_respF_q_1_write_1__SEL_1:
wmemi_respF_q_1_D_IN = MUX_wmemi_respF_q_1_write_1__VAL_1;
MUX_wmemi_respF_q_1_write_1__SEL_2:
wmemi_respF_q_1_D_IN = MUX_wmemi_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wmemi_respF_decCtr:
wmemi_respF_q_1_D_IN = 131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
default: wmemi_respF_q_1_D_IN =
131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmemi_respF_q_1_EN =
WILL_FIRE_RL_wmemi_respF_both && _dfoo5 ||
WILL_FIRE_RL_wmemi_respF_incCtr && wmemi_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wmemi_respF_decCtr ;
// register wmemi_statusR
assign wmemi_statusR_D_IN =
{ wmemi_isReset_isInReset,
!wmemi_peerIsReady,
!wmemi_operateD,
wmemi_errorSticky,
3'd0,
wmemi_trafficSticky } ;
assign wmemi_statusR_EN = 1'd1 ;
// register wmemi_trafficSticky
assign wmemi_trafficSticky_D_IN = 1'd1 ;
assign wmemi_trafficSticky_EN =
wmemi_reqF_FULL_N &&
wmemi_operateD_74_AND_wmemi_peerIsReady_75_76__ETC___d283 ;
// submodule appFull
assign appFull_sD_IN = x1__h12825 ;
assign appFull_sEN = 1'd1 ;
// submodule dbg_cpt_first_edge_cnt
assign dbg_cpt_first_edge_cnt_sD_IN = memc_memc_dbg_cpt_first_edge_cnt ;
assign dbg_cpt_first_edge_cnt_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_cpt_second_edge_cnt
assign dbg_cpt_second_edge_cnt_sD_IN = memc_memc_dbg_cpt_second_edge_cnt ;
assign dbg_cpt_second_edge_cnt_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_cpt_tap_cnt
assign dbg_cpt_tap_cnt_sD_IN = memc_memc_dbg_cpt_tap_cnt ;
assign dbg_cpt_tap_cnt_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_dq_tap_cnt
assign dbg_dq_tap_cnt_sD_IN = memc_memc_dbg_dq_tap_cnt ;
assign dbg_dq_tap_cnt_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_dqs_n_tap_cnt
assign dbg_dqs_n_tap_cnt_sD_IN = memc_memc_dbg_dqs_n_tap_cnt ;
assign dbg_dqs_n_tap_cnt_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_dqs_p_tap_cnt
assign dbg_dqs_p_tap_cnt_sD_IN = memc_memc_dbg_dqs_p_tap_cnt ;
assign dbg_dqs_p_tap_cnt_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_rd_active_dly
assign dbg_rd_active_dly_sD_IN = memc_memc_dbg_rd_active_dly ;
assign dbg_rd_active_dly_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_rd_bitslip_cnt
assign dbg_rd_bitslip_cnt_sD_IN = memc_memc_dbg_rd_bitslip_cnt ;
assign dbg_rd_bitslip_cnt_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_rd_clkdly_cnt
assign dbg_rd_clkdly_cnt_sD_IN = memc_memc_dbg_rd_clkdly_cnt ;
assign dbg_rd_clkdly_cnt_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_rddata
assign dbg_rddata_sD_IN = memc_memc_dbg_rddata ;
assign dbg_rddata_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_rdlvl_done
assign dbg_rdlvl_done_sD_IN = memc_memc_dbg_rdlvl_done ;
assign dbg_rdlvl_done_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_rdlvl_err
assign dbg_rdlvl_err_sD_IN = memc_memc_dbg_rdlvl_err ;
assign dbg_rdlvl_err_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_wl_dqs_inverted
assign dbg_wl_dqs_inverted_sD_IN = memc_memc_dbg_wl_dqs_inverted ;
assign dbg_wl_dqs_inverted_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_wl_odelay_dq_tap_cnt
assign dbg_wl_odelay_dq_tap_cnt_sD_IN = memc_memc_dbg_wl_odelay_dq_tap_cnt ;
assign dbg_wl_odelay_dq_tap_cnt_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_wl_odelay_dqs_tap_cnt
assign dbg_wl_odelay_dqs_tap_cnt_sD_IN =
memc_memc_dbg_wl_odelay_dqs_tap_cnt ;
assign dbg_wl_odelay_dqs_tap_cnt_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule dbg_wr_calib_clk_delay
assign dbg_wr_calib_clk_delay_sD_IN = memc_memc_dbg_wr_calib_clk_delay ;
assign dbg_wr_calib_clk_delay_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule firBeat
assign firBeat_sD_IN = memc_firstBeat ;
assign firBeat_sEN = 1'd1 ;
// submodule initComplete
assign initComplete_sD_IN = memc_memc_phy_init_done ;
assign initComplete_sEN = 1'd1 ;
// submodule lreqF
always@(MUX_splitReadInFlight_write_1__SEL_2 or
MUX_lreqF_enq_1__VAL_1 or
MUX_lreqF_enq_1__SEL_2 or
MUX_lreqF_enq_1__VAL_2 or
MUX_lreqF_enq_1__SEL_3 or MUX_lreqF_enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_splitReadInFlight_write_1__SEL_2:
lreqF_sD_IN = MUX_lreqF_enq_1__VAL_1;
MUX_lreqF_enq_1__SEL_2: lreqF_sD_IN = MUX_lreqF_enq_1__VAL_2;
MUX_lreqF_enq_1__SEL_3: lreqF_sD_IN = MUX_lreqF_enq_1__VAL_3;
default: lreqF_sD_IN =
177'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign lreqF_sENQ =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF_D_OUT[51] ||
MUX_lreqF_enq_1__PSEL_2 &&
(wmemi_reqF_D_OUT[51:49] == 3'd1 ||
wmemiReadInFlight_value_07_SLT_16___d390) ||
WILL_FIRE_RL_wci_cfwr &&
(wci_wslv_reqF_D_OUT[51] ||
wci_wslv_reqF_D_OUT[39:32] == 8'h54 ||
wci_wslv_reqF_D_OUT[39:32] == 8'h58) ;
assign lreqF_dDEQ = lreqF_dEMPTY_N && memc_reqF_FULL_N ;
// submodule lrespF
assign lrespF_sD_IN = memc_respF_D_OUT ;
assign lrespF_sENQ = lrespF_sFULL_N && memc_respF_EMPTY_N ;
assign lrespF_dDEQ =
lrespF_dEMPTY_N &&
lrespF_RDY_first__19_AND_NOT_wmemi_respF_cntr__ETC___d421 &&
(wmemiReadInFlight_value ^ 8'h80) > 8'd128 ||
WILL_FIRE_RL_advance_response ;
// submodule memIsResetCC
assign memIsResetCC_sD_IN = memIsReset_isInReset ;
assign memIsResetCC_sEN = 1'd1 ;
// submodule memc_memc
assign memc_memc_app_addr = { 3'd0, memc_reqF_D_OUT[175:146] } ;
assign memc_memc_app_cmd = memc_reqF_D_OUT[176] ? 3'b001 : 3'b0 ;
assign memc_memc_app_wdf_data = {2{memc_reqF_D_OUT[127:0]}} ;
assign memc_memc_app_wdf_end = WILL_FIRE_RL_memc_advance_write1 ;
assign memc_memc_app_wdf_mask =
WILL_FIRE_RL_memc_advance_write0 ? ~x__h5927 : ~x__h6148 ;
assign memc_memc_dbg_dec_cpt = 1'd0 ;
assign memc_memc_dbg_dec_rd_dqs = 1'd0 ;
assign memc_memc_dbg_inc_cpt = 1'd0 ;
assign memc_memc_dbg_inc_dec_sel = 3'd0 ;
assign memc_memc_dbg_inc_rd_dqs = 1'd0 ;
assign memc_memc_dbg_ocb_mon_off = 1'd0 ;
assign memc_memc_dbg_pd_maintain_0_only = 1'd0 ;
assign memc_memc_dbg_pd_maintain_off = 1'd0 ;
assign memc_memc_dbg_pd_off = 1'd0 ;
assign memc_memc_app_en = WILL_FIRE_RL_memc_advance_request ;
assign memc_memc_app_wdf_wren = memc_wdfWren_whas ;
// submodule memc_rdpF
assign memc_rdpF_D_IN = memc_reqF_D_OUT[149:148] ;
assign memc_rdpF_DEQ =
WILL_FIRE_RL_memc_advance_readData && memc_memc_app_rd_data_end ;
assign memc_rdpF_ENQ =
WILL_FIRE_RL_memc_advance_request && memc_memc_app_rdy &&
memc_reqF_D_OUT[176] ;
assign memc_rdpF_CLR = 1'b0 ;
// submodule memc_reqF
assign memc_reqF_D_IN = lreqF_dD_OUT ;
assign memc_reqF_ENQ = lreqF_dEMPTY_N && memc_reqF_FULL_N ;
assign memc_reqF_DEQ =
WILL_FIRE_RL_memc_advance_write1 && memc_memc_app_wdf_rdy ||
WILL_FIRE_RL_memc_advance_request && memc_memc_app_rdy &&
memc_reqF_D_OUT[176] ;
assign memc_reqF_CLR = 1'b0 ;
// submodule memc_respF
always@(x__h6385 or memc_memc_app_rd_data)
begin
case (x__h6385)
3'b0, 3'b110: memc_respF_D_IN = memc_memc_app_rd_data[127:0];
3'b101: memc_respF_D_IN = memc_memc_app_rd_data[255:128];
default: memc_respF_D_IN = memc_memc_app_rd_data[255:128];
endcase
end
assign memc_respF_DEQ = lrespF_sFULL_N && memc_respF_EMPTY_N ;
assign memc_respF_ENQ =
WILL_FIRE_RL_memc_advance_readData &&
(x__h6385 == 3'b0 || x__h6385 == 3'b101 || x__h6385 == 3'b110 ||
x__h6385 == 3'b011) ;
assign memc_respF_CLR = 1'b0 ;
// submodule requestCount
assign requestCount_sD_IN = memc_requestCount ;
assign requestCount_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule responseCount
assign responseCount_sD_IN = memc_responseCount ;
assign responseCount_sEN =
dbg_wl_dqs_inverted_sRDY && dbg_wr_calib_clk_delay_sRDY &&
dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 ;
// submodule secBeat
assign secBeat_sD_IN = memc_secondBeat ;
assign secBeat_sEN = 1'd1 ;
// submodule splaF
assign splaF_D_IN = wci_wslv_reqF_D_OUT[35:34] ;
assign splaF_DEQ = MUX_splitReadInFlight_write_1__SEL_1 ;
assign splaF_ENQ = MUX_splitReadInFlight_write_1__SEL_2 ;
assign splaF_CLR = 1'b0 ;
// submodule wci_uclkUpdateCnt
assign wci_uclkUpdateCnt_sD_IN = uclkUpdateCnt ;
assign wci_uclkUpdateCnt_sEN = wci_uclkUpdateCnt_sRDY ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF_D_IN = wci_wslv_wciReq_wget ;
assign wci_wslv_reqF_ENQ = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_DEQ = wci_wslv_reqF_r_deq_whas ;
assign wci_wslv_reqF_CLR = 1'b0 ;
// submodule wdfFull
assign wdfFull_sD_IN = !memc_memc_app_wdf_rdy ;
assign wdfFull_sEN = 1'd1 ;
// submodule wmemi_dhF
assign wmemi_dhF_D_IN = wmemi_wmemiDh_wget ;
assign wmemi_dhF_ENQ = wmemi_dhAccept_w_whas ;
assign wmemi_dhF_DEQ =
MUX_lreqF_enq_1__PSEL_2 && wmemi_reqF_D_OUT[51:49] == 3'd1 ;
assign wmemi_dhF_CLR = 1'b0 ;
// submodule wmemi_reqF
assign wmemi_reqF_D_IN = wmemi_wmemiReq_wget ;
assign wmemi_reqF_ENQ = wmemi_cmdAccept_w_whas ;
assign wmemi_reqF_DEQ = MUX_lreqF_enq_1__PSEL_2 ;
assign wmemi_reqF_CLR = 1'b0 ;
// remaining internal signals
assign IF_memc_memc_app_rd_data_end__09_CONCAT_memc_r_ETC___d225 =
CASE_x385_0b0_memc_respFFULL_N_0b101_memc_res_ETC__q1 &&
(!memc_memc_app_rd_data_end || memc_rdpF_EMPTY_N) ;
assign IF_wci_wslv_reqF_first__3_BIT_51_52_THEN_lreqF_ETC___d528 =
wci_wslv_reqF_D_OUT[51] ?
lreqF_sFULL_N && splaF_FULL_N :
wci_wslv_respF_cntr_r != 2'd2 ;
assign IF_wci_wslv_reqF_first__3_BIT_51_52_THEN_pReg__ETC___d503 =
wci_wslv_reqF_D_OUT[51] ?
{ x1_addr__h17672, x1_be__h17673, x1_data__h17674 } :
{ wci_wslv_reqF_D_OUT[31:0], mReg, x1_data__h16665 } ;
assign IF_wmemi_reqF_first__84_BITS_51_TO_49_85_EQ_1__ETC___d393 =
(wmemi_reqF_D_OUT[51:49] == 3'd1) ?
lreqF_sFULL_N && wmemi_dhF_EMPTY_N :
!wmemiReadInFlight_value_07_SLT_16___d390 || lreqF_sFULL_N ;
assign _dfoo1 =
wci_wslv_respF_cntr_r != 2'd2 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ;
assign _dfoo3 =
wci_wslv_respF_cntr_r != 2'd1 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ;
assign _dfoo5 =
wmemi_respF_cntr_r != 2'd2 ||
wmemi_respF_cntr_r_47_MINUS_1___d256 == 2'd1 ;
assign _dfoo7 =
wmemi_respF_cntr_r != 2'd1 ||
wmemi_respF_cntr_r_47_MINUS_1___d256 == 2'd0 ;
assign dbg_rd_active_dly_RDY_write__28_AND_dbg_dqs_p__ETC___d340 =
dbg_rd_active_dly_sRDY && dbg_dqs_p_tap_cnt_sRDY &&
dbg_dqs_n_tap_cnt_sRDY &&
dbg_dq_tap_cnt_sRDY &&
dbg_rddata_sRDY &&
requestCount_sRDY &&
responseCount_sRDY ;
assign dbg_rdlvl_err_RDY_write__22_AND_dbg_cpt_tap_cn_ETC___d346 =
dbg_rdlvl_err_sRDY && dbg_cpt_tap_cnt_sRDY &&
dbg_cpt_first_edge_cnt_sRDY &&
dbg_cpt_second_edge_cnt_sRDY &&
dbg_rd_bitslip_cnt_sRDY &&
dbg_rd_clkdly_cnt_sRDY &&
dbg_rd_active_dly_RDY_write__28_AND_dbg_dqs_p__ETC___d340 ;
assign dbg_wl_odelay_dqs_tap_cnt_RDY_write__19_AND_db_ETC___d349 =
dbg_wl_odelay_dqs_tap_cnt_sRDY &&
dbg_wl_odelay_dq_tap_cnt_sRDY &&
dbg_rdlvl_done_sRDY &&
dbg_rdlvl_err_RDY_write__22_AND_dbg_cpt_tap_cn_ETC___d346 ;
assign dramStatus__h14103 = { 16'd0, x__h19181 } ;
assign g_data__h19141 =
wci_wslv_reqF_D_OUT[51] ?
32'd0 :
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 ;
assign lrespF_RDY_first__19_AND_NOT_splitReadInFlight_ETC___d437 =
lrespF_dEMPTY_N &&
(!splitReadInFlight ||
splaF_EMPTY_N && wci_wslv_respF_cntr_r != 2'd2) ;
assign lrespF_RDY_first__19_AND_NOT_wmemi_respF_cntr__ETC___d421 =
lrespF_dEMPTY_N && wmemi_respF_cntr_r != 2'd2 &&
wmemi_operateD &&
wmemi_peerIsReady ;
assign myBE__h5964 = { 16'h0, memc_reqF_D_OUT[143:128] } ;
assign myBE__h5997 = { memc_reqF_D_OUT[143:128], 16'h0 } ;
assign rdat___1__h19204 =
hasDebugLogic ? { 24'd0, dbg_wl_dqs_inverted_dD_OUT } : 32'd0 ;
assign rdat___1__h19215 =
hasDebugLogic ?
{ 16'd0, dbg_wr_calib_clk_delay_dD_OUT } :
32'd0 ;
assign rdat___1__h19226 =
hasDebugLogic ? dbg_wl_odelay_dqs_tap_cnt_dD_OUT[31:0] : 32'd0 ;
assign rdat___1__h19237 =
hasDebugLogic ? dbg_wl_odelay_dq_tap_cnt_dD_OUT[31:0] : 32'd0 ;
assign rdat___1__h19248 =
hasDebugLogic ? { 30'd0, dbg_rdlvl_done_dD_OUT } : 32'd0 ;
assign rdat___1__h19259 =
hasDebugLogic ? { 30'd0, dbg_rdlvl_err_dD_OUT } : 32'd0 ;
assign rdat___1__h19270 =
hasDebugLogic ? dbg_cpt_tap_cnt_dD_OUT[31:0] : 32'd0 ;
assign rdat___1__h19281 =
hasDebugLogic ? dbg_cpt_first_edge_cnt_dD_OUT[31:0] : 32'd0 ;
assign rdat___1__h19292 =
hasDebugLogic ? dbg_cpt_second_edge_cnt_dD_OUT[31:0] : 32'd0 ;
assign rdat___1__h19303 =
hasDebugLogic ? { 8'd0, dbg_rd_bitslip_cnt_dD_OUT } : 32'd0 ;
assign rdat___1__h19314 =
hasDebugLogic ? { 16'd0, dbg_rd_clkdly_cnt_dD_OUT } : 32'd0 ;
assign rdat___1__h19325 =
hasDebugLogic ? { 27'd0, dbg_rd_active_dly_dD_OUT } : 32'd0 ;
assign rdat___1__h19336 =
hasDebugLogic ? dbg_dqs_p_tap_cnt_dD_OUT[31:0] : 32'd0 ;
assign rdat___1__h19347 =
hasDebugLogic ? dbg_dqs_n_tap_cnt_dD_OUT[31:0] : 32'd0 ;
assign rdat___1__h19358 =
hasDebugLogic ? dbg_dq_tap_cnt_dD_OUT[31:0] : 32'd0 ;
assign rdat___1__h19369 = hasDebugLogic ? dbg_rddata_dD_OUT : 32'd0 ;
assign rdat___1__h19376 =
hasDebugLogic ? { 16'd0, requestCount_dD_OUT } : 32'd0 ;
assign rdat___1__h19387 =
hasDebugLogic ? { 16'd0, responseCount_dD_OUT } : 32'd0 ;
assign rdat___1__h19398 = hasDebugLogic ? { 16'd0, pReg } : 32'd0 ;
assign rdat___1__h19408 = hasDebugLogic ? { 16'd0, mReg } : 32'd0 ;
assign rdat___1__h19418 = hasDebugLogic ? wdReg_0 : 32'd0 ;
assign rdat___1__h19432 = hasDebugLogic ? wdReg_1 : 32'd0 ;
assign rdat___1__h19446 = hasDebugLogic ? wdReg_2 : 32'd0 ;
assign rdat___1__h19460 = hasDebugLogic ? wdReg_3 : 32'd0 ;
assign rdat___1__h19474 = hasDebugLogic ? rdReg_0 : 32'd0 ;
assign rdat___1__h19489 = hasDebugLogic ? rdReg_1 : 32'd0 ;
assign rdat___1__h19504 = hasDebugLogic ? rdReg_2 : 32'd0 ;
assign rdat___1__h19519 = hasDebugLogic ? rdReg_3 : 32'd0 ;
assign rdat___1__h19534 = hasDebugLogic ? wmemiWrReq : 32'd0 ;
assign rdat___1__h19540 = hasDebugLogic ? wmemiRdReq : 32'd0 ;
assign rdat___1__h19546 = hasDebugLogic ? wmemiRdResp : 32'd0 ;
assign rdat___1__h19552 = hasDebugLogic ? wci_uclkUpdateCnt_dD_OUT : 32'd0 ;
assign wci_wslv_reqF_i_notEmpty__2_AND_IF_wci_wslv_re_ETC___d464 =
wci_wslv_reqF_EMPTY_N &&
(wci_wslv_reqF_D_OUT[51] ?
lreqF_sFULL_N :
((wci_wslv_reqF_D_OUT[39:32] == 8'h54) ?
lreqF_sFULL_N :
wci_wslv_reqF_D_OUT[39:32] != 8'h58 || lreqF_sFULL_N)) ;
assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 =
wci_wslv_respF_cntr_r - 2'd1 ;
assign wmemiReadInFlight_value_07_SLT_16___d390 =
(wmemiReadInFlight_value ^ 8'h80) < 8'd144 ;
assign wmemi_operateD_74_AND_wmemi_peerIsReady_75_76__ETC___d283 =
wmemi_operateD && wmemi_peerIsReady &&
wmemi_wmemiReq_wget[51:49] != 3'd0 &&
wmemi_reqF_FULL_N ;
assign wmemi_respF_cntr_r_47_MINUS_1___d256 = wmemi_respF_cntr_r - 2'd1 ;
assign x1__h12825 = !memc_memc_app_rdy ;
assign x1_addr__h17672 = { pReg[12:0], wci_wslv_reqF_D_OUT[50:36], 4'd0 } ;
assign x1_be__h17673 =
{ (wci_wslv_reqF_D_OUT[35:34] == 2'd3) ? 4'hF : 4'h0,
(wci_wslv_reqF_D_OUT[35:34] == 2'd2) ? 4'hF : 4'h0,
(wci_wslv_reqF_D_OUT[35:34] == 2'd1) ? 4'hF : 4'h0,
(wci_wslv_reqF_D_OUT[35:34] == 2'd0) ? 4'hF : 4'h0 } ;
assign x1_data__h16665 = { wdReg_3, wdReg_2, wdReg_1, wdReg_0 } ;
assign x1_data__h17674 = {4{wci_wslv_reqF_D_OUT[31:0]}} ;
assign x__h19181 =
{ respCount,
2'b0,
memIsResetCC_dD_OUT,
appFull_dD_OUT,
wdfFull_dD_OUT,
secBeat_dD_OUT,
firBeat_dD_OUT,
initComplete_dD_OUT } ;
assign x__h6385 = { memc_memc_app_rd_data_end, memc_rdpF_D_OUT } ;
always@(splaF_D_OUT or lrespF_dD_OUT)
begin
case (splaF_D_OUT)
2'd0: g_data__h15477 = lrespF_dD_OUT[31:0];
2'd1: g_data__h15477 = lrespF_dD_OUT[63:32];
2'd2: g_data__h15477 = lrespF_dD_OUT[95:64];
2'd3: g_data__h15477 = lrespF_dD_OUT[127:96];
endcase
end
always@(memc_reqF_D_OUT or myBE__h5964 or myBE__h5997)
begin
case (memc_reqF_D_OUT[149:148])
2'b0: x__h5927 = myBE__h5964;
2'b01: x__h5927 = myBE__h5997;
default: x__h5927 = 32'd0;
endcase
end
always@(memc_reqF_D_OUT or myBE__h5964 or myBE__h5997)
begin
case (memc_reqF_D_OUT[149:148])
2'b10: x__h6148 = myBE__h5964;
2'b11: x__h6148 = myBE__h5997;
default: x__h6148 = 32'd0;
endcase
end
always@(x__h6385 or memc_respF_FULL_N)
begin
case (x__h6385)
3'b0, 3'b101, 3'b110:
CASE_x385_0b0_memc_respFFULL_N_0b101_memc_res_ETC__q1 =
memc_respF_FULL_N;
default: CASE_x385_0b0_memc_respFFULL_N_0b101_memc_res_ETC__q1 =
x__h6385 != 3'b011 || memc_respF_FULL_N;
endcase
end
always@(wci_wslv_reqF_D_OUT or
dramStatus__h14103 or
dramCtrl or
rdat___1__h19204 or
rdat___1__h19215 or
rdat___1__h19226 or
rdat___1__h19237 or
rdat___1__h19248 or
rdat___1__h19259 or
rdat___1__h19270 or
rdat___1__h19281 or
rdat___1__h19292 or
rdat___1__h19303 or
rdat___1__h19314 or
rdat___1__h19325 or
rdat___1__h19336 or
rdat___1__h19347 or
rdat___1__h19358 or
rdat___1__h19369 or
rdat___1__h19376 or
rdat___1__h19387 or
rdat___1__h19398 or
rdat___1__h19408 or
rdat___1__h19418 or
rdat___1__h19432 or
rdat___1__h19446 or
rdat___1__h19460 or
rdat___1__h19474 or
rdat___1__h19489 or
rdat___1__h19504 or
rdat___1__h19519 or
rdat___1__h19534 or
rdat___1__h19540 or rdat___1__h19546 or rdat___1__h19552)
begin
case (wci_wslv_reqF_D_OUT[39:32])
8'h0:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
dramStatus__h14103;
8'h04:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
dramCtrl;
8'h08:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19204;
8'h0C:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19215;
8'h10:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19226;
8'h14:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19237;
8'h18:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19248;
8'h1C:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19259;
8'h20:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19270;
8'h24:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19281;
8'h28:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19292;
8'h2C:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19303;
8'h30:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19314;
8'h34:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19325;
8'h38:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19336;
8'h3C:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19347;
8'h40:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19358;
8'h44:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19369;
8'h48:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19376;
8'h4C:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19387;
8'h50:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19398;
8'h5C:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19408;
8'h60:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19418;
8'h64:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19432;
8'h68:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19446;
8'h6C:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19460;
8'h80:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19474;
8'h84:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19489;
8'h88:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19504;
8'h8C:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19519;
8'h90:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19534;
8'h94:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19540;
8'h98:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19546;
8'h9C:
IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
rdat___1__h19552;
default: IF_wci_wslv_reqF_first__3_BITS_39_TO_32_53_EQ__ETC___d674 =
32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
dramCtrl <= `BSV_ASSIGNMENT_DELAY 32'd0;
mReg <= `BSV_ASSIGNMENT_DELAY 16'd0;
memInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
pReg <= `BSV_ASSIGNMENT_DELAY 16'd0;
pioReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
rdReg_0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
rdReg_1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
rdReg_2 <= `BSV_ASSIGNMENT_DELAY 32'd0;
rdReg_3 <= `BSV_ASSIGNMENT_DELAY 32'd0;
respCount <= `BSV_ASSIGNMENT_DELAY 8'd0;
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wdReg_0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wdReg_1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wdReg_2 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wdReg_3 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemiRdReq <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemiRdResp <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemiReadInFlight_value <= `BSV_ASSIGNMENT_DELAY 8'd0;
wmemiWrReq <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmemi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmemi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmemi_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmemi_respF_q_0 <= `BSV_ASSIGNMENT_DELAY
131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_respF_q_1 <= `BSV_ASSIGNMENT_DELAY
131'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (dramCtrl_EN) dramCtrl <= `BSV_ASSIGNMENT_DELAY dramCtrl_D_IN;
if (mReg_EN) mReg <= `BSV_ASSIGNMENT_DELAY mReg_D_IN;
if (memInReset_EN)
memInReset <= `BSV_ASSIGNMENT_DELAY memInReset_D_IN;
if (pReg_EN) pReg <= `BSV_ASSIGNMENT_DELAY pReg_D_IN;
if (pioReadInFlight_EN)
pioReadInFlight <= `BSV_ASSIGNMENT_DELAY pioReadInFlight_D_IN;
if (rdReg_0_EN) rdReg_0 <= `BSV_ASSIGNMENT_DELAY rdReg_0_D_IN;
if (rdReg_1_EN) rdReg_1 <= `BSV_ASSIGNMENT_DELAY rdReg_1_D_IN;
if (rdReg_2_EN) rdReg_2 <= `BSV_ASSIGNMENT_DELAY rdReg_2_D_IN;
if (rdReg_3_EN) rdReg_3 <= `BSV_ASSIGNMENT_DELAY rdReg_3_D_IN;
if (respCount_EN) respCount <= `BSV_ASSIGNMENT_DELAY respCount_D_IN;
if (splitReadInFlight_EN)
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY splitReadInFlight_D_IN;
if (wci_wslv_cEdge_EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge_D_IN;
if (wci_wslv_cState_EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState_D_IN;
if (wci_wslv_ctlAckReg_EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg_D_IN;
if (wci_wslv_ctlOpActive_EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive_D_IN;
if (wci_wslv_illegalEdge_EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge_D_IN;
if (wci_wslv_nState_EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState_D_IN;
if (wci_wslv_reqF_countReg_EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg_D_IN;
if (wci_wslv_respF_cntr_r_EN)
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY
wci_wslv_respF_cntr_r_D_IN;
if (wci_wslv_respF_q_0_EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0_D_IN;
if (wci_wslv_respF_q_1_EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1_D_IN;
if (wci_wslv_sFlagReg_EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg_D_IN;
if (wci_wslv_sThreadBusy_d_EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d_D_IN;
if (wdReg_0_EN) wdReg_0 <= `BSV_ASSIGNMENT_DELAY wdReg_0_D_IN;
if (wdReg_1_EN) wdReg_1 <= `BSV_ASSIGNMENT_DELAY wdReg_1_D_IN;
if (wdReg_2_EN) wdReg_2 <= `BSV_ASSIGNMENT_DELAY wdReg_2_D_IN;
if (wdReg_3_EN) wdReg_3 <= `BSV_ASSIGNMENT_DELAY wdReg_3_D_IN;
if (wmemiRdReq_EN)
wmemiRdReq <= `BSV_ASSIGNMENT_DELAY wmemiRdReq_D_IN;
if (wmemiRdResp_EN)
wmemiRdResp <= `BSV_ASSIGNMENT_DELAY wmemiRdResp_D_IN;
if (wmemiReadInFlight_value_EN)
wmemiReadInFlight_value <= `BSV_ASSIGNMENT_DELAY
wmemiReadInFlight_value_D_IN;
if (wmemiWrReq_EN)
wmemiWrReq <= `BSV_ASSIGNMENT_DELAY wmemiWrReq_D_IN;
if (wmemi_errorSticky_EN)
wmemi_errorSticky <= `BSV_ASSIGNMENT_DELAY wmemi_errorSticky_D_IN;
if (wmemi_operateD_EN)
wmemi_operateD <= `BSV_ASSIGNMENT_DELAY wmemi_operateD_D_IN;
if (wmemi_peerIsReady_EN)
wmemi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmemi_peerIsReady_D_IN;
if (wmemi_respF_cntr_r_EN)
wmemi_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmemi_respF_cntr_r_D_IN;
if (wmemi_respF_q_0_EN)
wmemi_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wmemi_respF_q_0_D_IN;
if (wmemi_respF_q_1_EN)
wmemi_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wmemi_respF_q_1_D_IN;
if (wmemi_trafficSticky_EN)
wmemi_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wmemi_trafficSticky_D_IN;
end
if (wmemi_statusR_EN)
wmemi_statusR <= `BSV_ASSIGNMENT_DELAY wmemi_statusR_D_IN;
end
always@(posedge memc_memc_tb_clk)
begin
if (memc_memc_tb_rst_n == `BSV_RESET_VALUE)
begin
dbgCtrl <= `BSV_ASSIGNMENT_DELAY 32'd0;
memc_firstBeat <= `BSV_ASSIGNMENT_DELAY 1'd0;
memc_requestCount <= `BSV_ASSIGNMENT_DELAY 16'd0;
memc_responseCount <= `BSV_ASSIGNMENT_DELAY 16'd0;
memc_secondBeat <= `BSV_ASSIGNMENT_DELAY 1'd0;
uclkUpdateCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
end
else
begin
if (dbgCtrl_EN) dbgCtrl <= `BSV_ASSIGNMENT_DELAY dbgCtrl_D_IN;
if (memc_firstBeat_EN)
memc_firstBeat <= `BSV_ASSIGNMENT_DELAY memc_firstBeat_D_IN;
if (memc_requestCount_EN)
memc_requestCount <= `BSV_ASSIGNMENT_DELAY memc_requestCount_D_IN;
if (memc_responseCount_EN)
memc_responseCount <= `BSV_ASSIGNMENT_DELAY memc_responseCount_D_IN;
if (memc_secondBeat_EN)
memc_secondBeat <= `BSV_ASSIGNMENT_DELAY memc_secondBeat_D_IN;
if (uclkUpdateCnt_EN)
uclkUpdateCnt <= `BSV_ASSIGNMENT_DELAY uclkUpdateCnt_D_IN;
end
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmemi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_wslv_isReset_isInReset_EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset_D_IN;
if (wmemi_isReset_isInReset_EN)
wmemi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wmemi_isReset_isInReset_D_IN;
end
always@(posedge memc_memc_tb_clk or `BSV_RESET_EDGE memc_memc_tb_rst_n)
if (memc_memc_tb_rst_n == `BSV_RESET_VALUE)
begin
memIsReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (memIsReset_isInReset_EN)
memIsReset_isInReset <= `BSV_ASSIGNMENT_DELAY
memIsReset_isInReset_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
dbgCtrl = 32'hAAAAAAAA;
dramCtrl = 32'hAAAAAAAA;
mReg = 16'hAAAA;
memInReset = 1'h0;
memIsReset_isInReset = 1'h0;
memc_firstBeat = 1'h0;
memc_requestCount = 16'hAAAA;
memc_responseCount = 16'hAAAA;
memc_secondBeat = 1'h0;
pReg = 16'hAAAA;
pioReadInFlight = 1'h0;
rdReg_0 = 32'hAAAAAAAA;
rdReg_1 = 32'hAAAAAAAA;
rdReg_2 = 32'hAAAAAAAA;
rdReg_3 = 32'hAAAAAAAA;
respCount = 8'hAA;
splitReadInFlight = 1'h0;
uclkUpdateCnt = 32'hAAAAAAAA;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_cntr_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wdReg_0 = 32'hAAAAAAAA;
wdReg_1 = 32'hAAAAAAAA;
wdReg_2 = 32'hAAAAAAAA;
wdReg_3 = 32'hAAAAAAAA;
wmemiRdReq = 32'hAAAAAAAA;
wmemiRdResp = 32'hAAAAAAAA;
wmemiReadInFlight_value = 8'hAA;
wmemiWrReq = 32'hAAAAAAAA;
wmemi_errorSticky = 1'h0;
wmemi_isReset_isInReset = 1'h0;
wmemi_operateD = 1'h0;
wmemi_peerIsReady = 1'h0;
wmemi_respF_cntr_r = 2'h2;
wmemi_respF_q_0 = 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_respF_q_1 = 131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmemi_statusR = 8'hAA;
wmemi_trafficSticky = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3583 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3583,
wci_wslv_reqF_D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
begin
v__h19683 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
$display("[%0d]: %m: Starting DramWorker dramCtrl:%0x",
v__h19683,
dramCtrl);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_advance_response && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 90: (R0001)\n Mutually exclusive rules (from the ME sets [RL_advance_response] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_advance_response && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 90: (R0001)\n Mutually exclusive rules (from the ME sets [RL_advance_response] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_advance_response && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 90: (R0001)\n Mutually exclusive rules (from the ME sets [RL_advance_response] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_advance_response)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_advance_response] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_advance_response)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_advance_response] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/DramServer_v6.bsv\", line 208, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h3902 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h3902,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3758 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3758,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
end
// synopsys translate_on
endmodule // mkDramServer_v6
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This optional block is used for two purposes:
1) Relay response information back to the host typically in ST->MM mode.
This information is 'actual bytes transferred', 'error', and 'early termination'.
2) Relay response and interrupt information back to a prefetching master block
that will write the contents back to memory. Interrupt information is also passed
since the interrupt needs to occur when the prefetching master block overwrites
the descriptor in main memory and not when the event occurs. The host needs to read
the interrupt condition out of memory so it could potentially get out of sync if
the interrupt information wasn't buffered and delayed.
This block has three response port options: MM slave, ST source, and disabled.
When you don't need access to response information (MM->MM or MM->ST) or interrupts in
the case of a prefetching descriptor master then you can safely disable the port.
By disabling the port you will not consume any logic resources or on-chip memory blocks.
When the source port is enabled bit 52 of the data stream represents the "descriptor full"
condition. The descriptor prefetching master can use this signal to perform pipelined reads
without having to worry about flow control (since there is room for an entire descriptor to be
written). This is benefical as apposed to performing descriptor reads, buffering the data, then
writting it out to the descriptor buffer block.
Version 1.0
1.0 - If you attempt to use the wrong response port type you will be issued a warning
but allowed to generate. This is because in some cases you may not need the typical
behavior. For example if you perform MM->MM transfers with some streaming IP between
the read and write masters you still might need access to error bits. Likewise
if you don't enable the streaming sink port while using a descriptor pre-fetching block
you may not care if you get interrupted early and want to use the CSR block for interrupts
instead.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
/*
* In The Name Of God
* ========================================
* [] File Name : cache.v
*
* [] Creation Date : 04-03-2015
*
* [] Last Modified : Wed 01 Apr 2015 09:12:09 AM IRDT
*
* [] Created By : Parham Alvani ([email protected])
* =======================================
*/
module cache (enable, index, word, comp,
write, tag_in, data_in, valid_in,
rst, hit, dirty, tag_out,
data_out, valid, ack);
parameter N = 15;
reg [0:3] counter;
input enable;
input [0:3] index;
input [0:1] word;
input comp;
input write;
input [0:4] tag_in;
input [0:15] data_in;
input valid_in;
input rst;
output reg hit;
output reg dirty;
output reg [0:4] tag_out;
output reg [0:15] data_out;
output reg valid;
output reg ack;
reg set_en [0:N];
reg [0:1] set_word [0:N];
reg set_cmp [0:N];
reg set_wr [0:N];
reg [0:4] set_tag_in [0:N];
reg [0:15] set_in [0:N];
reg set_valid_in [0:N];
reg set_rst [0:N];
wire set_hit [0:N];
wire set_dirty_out [0:N];
wire [0:4] set_tag_out [0:N];
wire [0:15] set_out [0:N];
wire set_valid_out [0:N];
wire set_ack [0:N];
generate
genvar i;
for (i = 0; i < N; i = i + 1) begin
set set_ins(set_en[i], set_word[i], set_cmp[i], set_wr[i], set_rst[i],
set_tag_in[i], set_in[i], set_valid_in[i], set_hit[i], set_dirty_out[i],
set_tag_out[i], set_out[i], set_valid_out[i], set_ack[i]);
end
endgenerate
always @ (enable) begin
ack = 1'b0;
if (enable) begin
if (rst) begin
for (counter = 0; counter < N; counter = counter + 1) begin
set_en[counter] = 1'b1;
set_rst[counter] = 1'b1;
wait (set_ack[counter]) begin
set_en[counter] = 1'b0;
set_rst[counter] = 1'b0;
end
end
ack = 1'b1;
end else begin
set_word[index] = word;
set_cmp[index] = comp;
set_wr[index] = write;
set_tag_in[index] = tag_in;
set_in[index] = data_in;
set_valid_in[index] = valid_in;
set_en[index] = 1'b1;
wait (set_ack[index]) begin
hit = set_hit[index];
dirty = set_dirty_out[index];
tag_out = set_tag_out[index];
valid = set_valid_out[index];
data_out = set_out[index];
end
ack = 1'b1;
end
end else begin
set_en[index] = 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTN_BLACKBOX_V
`define SKY130_FD_SC_LS__DLRTN_BLACKBOX_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTN_BLACKBOX_V
|
`default_nettype none
module romtest2 (
input wire sysclk,
input wire clk,
input wire rst,
output wire d0,
output wire d1,
output wire d2,
output wire d3,
output wire d4,
output wire d5,
output wire d6,
output wire d7
);
wire [7:0] dout;
reg [3:0] addr;
//-- Instanciar la memoria rom
rom16x8
ROM (
.clk(sysclk),
.addr(addr),
.data(dout)
);
//-- Configure the pull-up resistors for clk and rst inputs
wire clk_in, clk2;
wire rst_in, rst2;
wire sw;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin (
.PACKAGE_PIN(clk),
.D_IN_0(clk2)
);
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin2 (
.PACKAGE_PIN(rst),
.D_IN_0(rst2)
);
//-- rst_in and clk_in are the signals from the switches, with
//-- standar logic (1 pressed, 0 not presssed)
assign rst_in = ~rst2;
assign sw = ~clk2;
debounce deb1 (
.clk(sysclk),
.sw_in(sw),
.sw_out(clk_in)
);
//-- Counter for incrementing the address
always @(posedge clk_in or posedge rst_in) begin
if (rst_in==1'b1)
addr <= 4'b0;
else
addr <= addr + 1;
end
assign {d7,d6,d5,d4,d3,d2,d1,d0} = dout;
endmodule
module rom16x8 (input clk,
input wire [3:0] addr,
output reg [7:0] data);
//-- Name of the file with the rom contents
parameter ROMFILE = "rom2.list";
//-- Memoria
reg [7:0] rom [0:15];
always @(negedge clk) begin
data <= rom[addr];
end
//-- ROM2: Secuencia
initial begin
$readmemh(ROMFILE, rom);
end
endmodule
module debounce(input wire clk,
input wire sw_in,
output wire sw_out);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam STABLE_0 = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam STABLE_1 = 2; //-- Button is pressed and stable
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = STABLE_0;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
STABLE_0: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 1;
if (timer_trig)
next_state = STABLE_1;
end
STABLE_1: begin
timer_ena = 0;
out = 1;
if (sw_in == 0)
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = STABLE_0;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debounce
//-- Prescaler N bits
module prescaler(input wire clk_in,
input wire ena,
output wire clk_out);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge(clk_in)) begin
if (!ena)
count <= 0;
else
count <= count + 1;
end
endmodule /// prescaler
|
parameter DW = 16;
parameter AW = 8;
module pllclk (input ext_clock, output pll_clock, input nrst, output lock);
wire dummy_out;
wire bypass, lock1;
assign bypass = 1'b0;
// DIVR=0 DIVF=71 DIVQ=3 freq=12/1*72/8 = 108 MHz
SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"), .PLLOUT_SELECT("GENCLK"),
.DIVR(4'd0), .DIVF(7'b1000111), .DIVQ(3'b011),
.FILTER_RANGE(3'b001)
) mypll1 (.REFERENCECLK(ext_clock),
.PLLOUTGLOBAL(pll_clock), .PLLOUTCORE(dummy_out), .LOCK(lock1),
.RESETB(nrst), .BYPASS(bypass));
endmodule
module dff #(parameter W=1)
(input wire[W-1:0] D, input clk, output reg[W-1:0] Q);
always @(posedge clk)
Q <= D;
endmodule // dff
module synchroniser #(parameter W=1)
(input wire[W-1:0] D, input clk, output wire[W-1:0] Q);
wire[W-1:0] M;
dff #(W) first_reg(D, clk, M);
dff #(W) last_reg(M, clk, Q);
endmodule
module clocked_bus_slave #(parameter ADRW=1, DATW=1)
(input aNE, aNOE, aNWE,
input wire [ADRW-1:0] aAn, input wire[DATW-1:0] aDn,
input clk,
output wire[ADRW-1:0] r_adr, output wire[ADRW-1:0] w_adr,
output reg do_read, input wire[DATW-1:0] read_data,
output reg do_write, output reg[DATW-1:0] w_data,
output io_output, output wire[DATW-1:0] io_data);
wire sNE, sNOE, sNWE;
reg[ADRW-1:0] sAn_r;
reg[ADRW-1:0] sAn_w;
reg[DATW-1:0] rDn;
reg[DATW-1:0] wDn;
wire[ADRW-1:0] next_sAn_r;
wire[ADRW-1:0] next_sAn_w;
wire[DATW-1:0] next_rDn;
wire[DATW-1:0] next_wDn;
wire next_do_write, next_do_read;
// States for one-hot state machine.
reg st_idle=1, st_write=0, st_read1=0, st_read2=0;
wire next_st_idle, next_st_write, next_st_read1, next_st_read2;
synchroniser sync_NE(aNE, clk, sNE);
synchroniser sync_NOE(aNOE, clk, sNOE);
synchroniser sync_NWE(aNWE, clk, sNWE);
always @(posedge clk) begin
st_idle <= next_st_idle;
st_write <= next_st_write;
st_read1 <= next_st_read1;
st_read2 <= next_st_read2;
do_write <= next_do_write;
do_read <= next_do_read;
sAn_r <= next_sAn_r;
sAn_w <= next_sAn_w;
wDn <= next_wDn;
rDn <= next_rDn;
end
/* Latch the address on the falling edge of NOE (read) or NWE (write).
We can use the external address unsynchronised, as it will be stable
when NOE/NWE toggles.
*/
assign next_sAn_r = st_idle & ~sNE & ~sNOE ? aAn : sAn_r;
assign next_sAn_w = st_idle & ~sNE & ~sNWE ? aAn : sAn_w;
/* Incoming write. */
/* Latch the write data on the falling edge of NWE. NWE is synchronised,
so the synchronisation delay is enough to ensure that the async external
data signal is stable at this point.
*/
assign next_wDn = st_idle & ~sNE & ~sNWE ? aDn : wDn;
// Trigger a register write when NWE goes low.
assign next_do_write = st_idle & ~sNE & ~sNWE;
assign next_st_write = (st_idle | st_write) & (~sNE & ~sNWE);
/* Incoming read. */
assign next_do_read = st_idle & ~sNE & ~sNOE;
/* Wait one cycle for register read data to become available. */
assign next_st_read1 = st_idle & ~sNE & ~sNOE;
/* Put read data on the bus while NOE is asserted. */
assign next_st_read2 = (st_read1 | st_read2) & ~sNE & ~sNOE;
assign next_st_idle = ((st_read1 | st_read2) & (sNOE | sNE)) |
(st_write & (sNWE | sNE)) |
(st_idle & (sNE | (sNOE & sNWE)));
/* Latch register read data one cycle after asserting do_read. */
assign next_rDn = st_read1 ? read_data : rDn;
/* Output data during read after latching read data. */
assign io_output = st_read2 & next_st_read2;
assign io_data = rDn;
assign r_adr = sAn_r;
assign w_adr = sAn_w;
assign w_data = wDn;
endmodule // clocked_bus_slave
module top (
/* FSMC */
input crystal_clk,
input STM32_PIN,
input aNE, aNOE, aNWE,
input [AW-1:0] aA,
inout [DW-1:0] aD,
//output [7:0] LED,
input uart_tx_in, output uart_tx_out,
/* VGA */
output [2:0] red, green, blue,
output hsync, vsync
);
wire clk;
wire nrst, lock;
wire [7:0] pulse_counter;
wire[DW-1:0] aDn_output;
wire[DW-1:0] aDn_input;
wire io_d_output;
wire do_write;
wire[AW-1:0] r_adr;
wire[AW-1:0] w_adr;
wire[DW-1:0] w_data;
wire do_read;
wire[DW-1:0] register_data;
wire chk_err;
wire[7:0] err_count;
/* Type 101001 is output with tristate/enable and simple input. */
SB_IO #(.PIN_TYPE(6'b1010_01), .PULLUP(1'b0))
io_Dn[DW-1:0](.PACKAGE_PIN(aD),
.OUTPUT_ENABLE(io_d_output),
.D_OUT_0(aDn_output),
.D_IN_0(aDn_input)
);
assign nrst = 1'b1;
pllclk my_pll(crystal_clk, clk, nrst, lock);
clocked_bus_slave #(.ADRW(AW), .DATW(DW))
my_bus_slave(aNE, aNOE, aNWE,
aA, aDn_input,
clk, r_adr, w_adr,
do_read, register_data,
do_write, w_data,
io_d_output, aDn_output);
/* The clocked_bus_slave asserts do_read once per read transaction on the
external bus (synchronous on clk). This can be used to have side effects
on read (eg. clear "data ready" on read of data register). However, in
this particular case we have no such side effects, so can just decode
the read data continously (clocked_bus_slave latches the read value).
*/
always @(*) begin
case (r_adr)
default: register_data <= 0;
endcase // case (r_adr)
end
reg [15:0] chadr;
reg [7:0] chdata;
reg chbuf_w;
reg chadr_inc;
always @(posedge clk) begin
if (do_write) begin
case (w_adr)
8'h00: begin
// Write charbuf address
chadr <= w_data;
end
8'h02: begin
// Write charbuf data
chdata <= w_data[7:0];
chbuf_w <= 1'b1;
end
8'h03: begin
// Write charbuf data with auto-increment of address
chdata <= w_data[7:0];
chbuf_w <= 1'b1;
chadr_inc <= 1'b1;
end
endcase
end else begin
if (chbuf_w == 1'b1) begin
chbuf_w <= 1'b0;
end
if (chadr_inc == 1'b1) begin
chadr <= chadr + 1;
chadr_inc <= 1'b0;
end
end
end // always @ (posedge_clk)
/* For debugging, proxy an UART Tx signal to the FTDI chip. */
assign uart_tx_out = uart_tx_in;
/* vga stuff */
wire vga_clk = clk;
wire [11:0] x, y;
wire fb_enable, fb_reset;
wire i_hsync, i_vsync;
wire [11:0] pixel_count, line_count;
vga_blank blank(vga_clk, pixel_count, line_count, i_hsync, i_vsync, fb_reset, fb_enable);
vga_adr_trans #(.FB_X_MAX(1280), .FB_Y_MAX(1024)) trans(vga_clk, pixel_count, line_count, fb_reset, fb_enable, x, y);
wire [7:0] w_col, w_row;
wire [7:0] buf_out;
assign w_col = w_adr;
char_buf buffer(vga_clk, chbuf_w, y[10:4], x[10:3], chadr[13:0], chdata, buf_out);
wire [7:0] pixels;
font_rom rom(vga_clk, y[3:0], buf_out, pixels);
reg pixel;
reg [2:0] ascii_x;
always @(posedge vga_clk) begin
pixel <= pixels[ascii_x];
ascii_x <= ~(x[2:0]-1);
end
// Buffer output lines.
always @(posedge vga_clk) begin
red <= ~fb_enable ? 0 : (pixel ? 'b11 : 0);
green <= ~fb_enable ? 0 : (pixel ? 'b11 : 0);
blue <= 0;
hsync <= i_hsync;
vsync <= i_vsync;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NOR2B_PP_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2B_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4BB_BLACKBOX_V
`define SKY130_FD_SC_HD__OR4BB_BLACKBOX_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4BB_BLACKBOX_V
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
`define M 503 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 (1008-1)
module test_tiny;
// Inputs
reg clk;
reg reset;
reg sel;
reg [5:0] addr;
reg w;
reg [`WIDTH_D0:0] data;
// Outputs
wire [`WIDTH_D0:0] out;
wire done;
// Instantiate the Unit Under Test (UUT)
tiny uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.data(data),
.out(out),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1; // keep FSM silent
// init x, y
write(3, 1006'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
write(5, 1006'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
write(6, 1006'h0412500224298894260864922a0084a98a0454681a18164a08268062495a596469659050406960a191646a024a0aa26688240682059585a258a89664946584924a9a8a1a8145400889899a6a2601184a2596419a04161969169128281805669a9509145852901691690a8506a9145224850109a150110629229564901a00);
write(7, 1006'h161181618265a480158208a088a01aa89a424001019a90912969511008944a806119a1429520105654089861546a912295590518a90842962660a665899405681aa510844840524240145a0295855920091640a66a5a044568510469454a18a06218922914510004a25409a81a5800456055996128a965624116289904aa);
/* read back. uncomment me if error happens */
/* read(3);
$display("xp = %h", out);
read(5);
$display("yp = %h", out);
read(6);
$display("xq = %h", out);
read(7);
$display("yq = %h", out);*/
reset = 0;
sel = 0; w = 0;
@(posedge done);
@(negedge clk);
read(9);
check(1006'h2965a664a44a85426524a19821aa12a42605258540a056525248149a96061560451a6a95861496a8140985a8902955951552696a425948159a2141a0aaa5840442851218546a49a2a2496658644656a9a6162a5098a025645151aa668902aaa102a0805900488980545120462896204252584282868449488a00884995a9);
read(10);
check(1006'h244151402864a58144a0509a26121148024224a299a4062a248944801589895a04a8a681a4245492a5aa5958901a142120515582941220529512012554699982594528256086220a55641a5a212511aa50a0a4a198200560a628994925551249659028459a8a24688191044a08529064119949a112564a52082068858890);
read(11);
check(1006'h180645a168488aa651260a226a124a66080299922a8595404428610808262992a22682905a55625665824505a609882a88422a886296551a6221a29a16aa11141a12280942aa84094946860205964a26669684569054810a914124a086212a5a5821440119015a98844101854a9951141981221169224a1599a11914a504);
read(12);
check(1006'h18a6911a415584242209a6a52629464160400a0a45554552866a9a20a8520a551856814024118140a144a151604449609aa24085a609a2a0851285445a96602a2461212641204a591a66a5604211004882191912920862a9860a861a88a005516611622a44880a48690412292244615156004952521664a84a5961510225);
read(13);
check(1006'h250869062a008a1882940945a20441680111009595094282260a95488aaa4588262641912aa64a29a8526408451940619612014212441090209588888a004002462206a8294a158809258852650a15226a99808952201191614814166198a52a8151454968a288295994286919811691aa21048661a5288402182a558215);
read(14);
check(1006'h016641111896469064656661124a160226a89485469954a6a5406aa28590655a018922965688045984585a61888165085289a61a051258a59459210842108082566966664250991442a2941521806608610a52182256042680a4881900605a8459260a9824295244629865a6a62a18958a66955152404814065588150894);
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task write;
input [6:0] adr;
input [`WIDTH_D0:0] dat;
begin
sel = 1;
w = 1;
addr = adr;
data = dat;
#(`P);
end
endtask
task read;
input [6:0] adr;
begin
sel = 1;
w = 0;
addr = adr;
#(`P);
end
endtask
task check;
input [`WIDTH_D0:0] wish;
begin
if (out !== wish)
begin $display("Error! %h %h", out, wish); end
end
endtask
endmodule
|
/* Module: vga640x480
Description: Generates VGA signals for 640x480 resolution
using a 25 MHz pixel clock. Once Vertical and
Horizontal sync signals are in between front
and back porch, VIDON is enabled
to display data. */
module vga640x480(
CLK,
CLR,
HSYNC,
VSYNC,
HC,
VC,
VIDON
);
// |--------------------|
// | Port Declarations |
// | -------------------|
input CLK; // Clock
input CLR; // Clear
output HSYNC; // Horizontal Sync
output VSYNC; // Vertical Sync
output [9:0] HC; // Horizontal Counter
output [9:0] VC; // Vertical Counter
output VIDON; // When active, data may be displayed
// |------------------------|
// | Parameters (Constants) |
// | -----------------------|
localparam hpixels = 800 /*10'b1100100000*/, // Pixels in horizontal line = 800
vlines = 521 /*10'b1000001001*/, // Horizontal lines = 521
hbp = 144 /*10'b1100010000*/, // Horizontal Back Porch = 144 (128+16)
hfp = 784 /*10'b1100010000*/, // Horizontal Front Porch = 784 (128+16+640)
vbp = 31 /*10'b0000011111*/, // Vertical Back Porch = 31 (2+29)
vfp = 511 /*10'b0111111111*/; // Vertical Front Porch = 511 (2+29+480)
reg [9:0] HCS, VCS; // Horizontal and Vertical counters
reg VSenable; // Enable for Vertical counter
assign HC = HCS;
assign VC = VCS;
assign HSYNC = (HCS < 128) ? 1'b0 : 1'b1; // HS Pulse is low for HCS from 0-127
assign VSYNC = (VCS < 2) ? 1'b0 : 1'b1; // VS Pulse is low for VCS from 0-1
assign VIDON = (((HCS < hfp) && (HCS >= hbp)) && ((VCS < vfp) && (VCS >= vbp))) ? 1 : 0;
// Counter for the horizontal sync signal
always @ (posedge CLK)
begin
if(CLR == 1'b1)
HCS <= 10'b0000000000;
else if(CLK == 1'b1)
begin
if(HCS < (hpixels - 1'b1) )
begin
HCS <= HCS + 1'b1;
VSenable <= 1'b0; // Leave VSenable off
end
else
begin
// Counter reached end of the pixel count
HCS <= 10'b0000000000; // Reset counter, then,
VSenable <= 1'b1; // Enable vertical counter
end
end
end
// Counter for the vertical sync signal
always @ (posedge CLK)
begin
if(CLR == 1'b1)
VCS <= 10'b0000000000;
else if(CLK == 1'b1 && VSenable == 1'b1)
begin
// Increment when enabled
if( VCS < (vlines - 1'b1) )
begin
VCS <= VCS + 1'b1; // Increment vertical counter
end
else
begin
VCS <= 10'b0000000000;
end
end
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 7
(* X_CORE_INFO = "axi_protocol_converter_v2_1_7_axi_protocol_converter,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_auto_pc_1,axi_protocol_converter_v2_1_7_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "zc702_auto_pc_1,axi_protocol_converter_v2_1_7_axi_protocol_converter,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=1,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [0 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [0 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [0 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [0 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *)
output wire [0 : 0] m_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [3 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_7_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(1),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S4S_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DLYMETAL6S4S_FUNCTIONAL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__dlymetal6s4s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S4S_FUNCTIONAL_V
|
//-----------------------------------------------------------------------------
// system_axi_interconnect_1_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "axi_interconnect_v1_06_a" *)
module system_axi_interconnect_1_wrapper
(
INTERCONNECT_ACLK,
INTERCONNECT_ARESETN,
S_AXI_ARESET_OUT_N,
M_AXI_ARESET_OUT_N,
IRQ,
S_AXI_ACLK,
S_AXI_AWID,
S_AXI_AWADDR,
S_AXI_AWLEN,
S_AXI_AWSIZE,
S_AXI_AWBURST,
S_AXI_AWLOCK,
S_AXI_AWCACHE,
S_AXI_AWPROT,
S_AXI_AWQOS,
S_AXI_AWUSER,
S_AXI_AWVALID,
S_AXI_AWREADY,
S_AXI_WID,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WLAST,
S_AXI_WUSER,
S_AXI_WVALID,
S_AXI_WREADY,
S_AXI_BID,
S_AXI_BRESP,
S_AXI_BUSER,
S_AXI_BVALID,
S_AXI_BREADY,
S_AXI_ARID,
S_AXI_ARADDR,
S_AXI_ARLEN,
S_AXI_ARSIZE,
S_AXI_ARBURST,
S_AXI_ARLOCK,
S_AXI_ARCACHE,
S_AXI_ARPROT,
S_AXI_ARQOS,
S_AXI_ARUSER,
S_AXI_ARVALID,
S_AXI_ARREADY,
S_AXI_RID,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RLAST,
S_AXI_RUSER,
S_AXI_RVALID,
S_AXI_RREADY,
M_AXI_ACLK,
M_AXI_AWID,
M_AXI_AWADDR,
M_AXI_AWLEN,
M_AXI_AWSIZE,
M_AXI_AWBURST,
M_AXI_AWLOCK,
M_AXI_AWCACHE,
M_AXI_AWPROT,
M_AXI_AWREGION,
M_AXI_AWQOS,
M_AXI_AWUSER,
M_AXI_AWVALID,
M_AXI_AWREADY,
M_AXI_WID,
M_AXI_WDATA,
M_AXI_WSTRB,
M_AXI_WLAST,
M_AXI_WUSER,
M_AXI_WVALID,
M_AXI_WREADY,
M_AXI_BID,
M_AXI_BRESP,
M_AXI_BUSER,
M_AXI_BVALID,
M_AXI_BREADY,
M_AXI_ARID,
M_AXI_ARADDR,
M_AXI_ARLEN,
M_AXI_ARSIZE,
M_AXI_ARBURST,
M_AXI_ARLOCK,
M_AXI_ARCACHE,
M_AXI_ARPROT,
M_AXI_ARREGION,
M_AXI_ARQOS,
M_AXI_ARUSER,
M_AXI_ARVALID,
M_AXI_ARREADY,
M_AXI_RID,
M_AXI_RDATA,
M_AXI_RRESP,
M_AXI_RLAST,
M_AXI_RUSER,
M_AXI_RVALID,
M_AXI_RREADY,
S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA,
S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY,
INTERCONNECT_ARESET_OUT_N,
DEBUG_AW_TRANS_SEQ,
DEBUG_AW_ARB_GRANT,
DEBUG_AR_TRANS_SEQ,
DEBUG_AR_ARB_GRANT,
DEBUG_AW_TRANS_QUAL,
DEBUG_AW_ACCEPT_CNT,
DEBUG_AW_ACTIVE_THREAD,
DEBUG_AW_ACTIVE_TARGET,
DEBUG_AW_ACTIVE_REGION,
DEBUG_AW_ERROR,
DEBUG_AW_TARGET,
DEBUG_AR_TRANS_QUAL,
DEBUG_AR_ACCEPT_CNT,
DEBUG_AR_ACTIVE_THREAD,
DEBUG_AR_ACTIVE_TARGET,
DEBUG_AR_ACTIVE_REGION,
DEBUG_AR_ERROR,
DEBUG_AR_TARGET,
DEBUG_B_TRANS_SEQ,
DEBUG_R_BEAT_CNT,
DEBUG_R_TRANS_SEQ,
DEBUG_AW_ISSUING_CNT,
DEBUG_AR_ISSUING_CNT,
DEBUG_W_BEAT_CNT,
DEBUG_W_TRANS_SEQ,
DEBUG_BID_TARGET,
DEBUG_BID_ERROR,
DEBUG_RID_TARGET,
DEBUG_RID_ERROR,
DEBUG_SR_SC_ARADDR,
DEBUG_SR_SC_ARADDRCONTROL,
DEBUG_SR_SC_AWADDR,
DEBUG_SR_SC_AWADDRCONTROL,
DEBUG_SR_SC_BRESP,
DEBUG_SR_SC_RDATA,
DEBUG_SR_SC_RDATACONTROL,
DEBUG_SR_SC_WDATA,
DEBUG_SR_SC_WDATACONTROL,
DEBUG_SC_SF_ARADDR,
DEBUG_SC_SF_ARADDRCONTROL,
DEBUG_SC_SF_AWADDR,
DEBUG_SC_SF_AWADDRCONTROL,
DEBUG_SC_SF_BRESP,
DEBUG_SC_SF_RDATA,
DEBUG_SC_SF_RDATACONTROL,
DEBUG_SC_SF_WDATA,
DEBUG_SC_SF_WDATACONTROL,
DEBUG_SF_CB_ARADDR,
DEBUG_SF_CB_ARADDRCONTROL,
DEBUG_SF_CB_AWADDR,
DEBUG_SF_CB_AWADDRCONTROL,
DEBUG_SF_CB_BRESP,
DEBUG_SF_CB_RDATA,
DEBUG_SF_CB_RDATACONTROL,
DEBUG_SF_CB_WDATA,
DEBUG_SF_CB_WDATACONTROL,
DEBUG_CB_MF_ARADDR,
DEBUG_CB_MF_ARADDRCONTROL,
DEBUG_CB_MF_AWADDR,
DEBUG_CB_MF_AWADDRCONTROL,
DEBUG_CB_MF_BRESP,
DEBUG_CB_MF_RDATA,
DEBUG_CB_MF_RDATACONTROL,
DEBUG_CB_MF_WDATA,
DEBUG_CB_MF_WDATACONTROL,
DEBUG_MF_MC_ARADDR,
DEBUG_MF_MC_ARADDRCONTROL,
DEBUG_MF_MC_AWADDR,
DEBUG_MF_MC_AWADDRCONTROL,
DEBUG_MF_MC_BRESP,
DEBUG_MF_MC_RDATA,
DEBUG_MF_MC_RDATACONTROL,
DEBUG_MF_MC_WDATA,
DEBUG_MF_MC_WDATACONTROL,
DEBUG_MC_MP_ARADDR,
DEBUG_MC_MP_ARADDRCONTROL,
DEBUG_MC_MP_AWADDR,
DEBUG_MC_MP_AWADDRCONTROL,
DEBUG_MC_MP_BRESP,
DEBUG_MC_MP_RDATA,
DEBUG_MC_MP_RDATACONTROL,
DEBUG_MC_MP_WDATA,
DEBUG_MC_MP_WDATACONTROL,
DEBUG_MP_MR_ARADDR,
DEBUG_MP_MR_ARADDRCONTROL,
DEBUG_MP_MR_AWADDR,
DEBUG_MP_MR_AWADDRCONTROL,
DEBUG_MP_MR_BRESP,
DEBUG_MP_MR_RDATA,
DEBUG_MP_MR_RDATACONTROL,
DEBUG_MP_MR_WDATA,
DEBUG_MP_MR_WDATACONTROL
);
input INTERCONNECT_ACLK;
input INTERCONNECT_ARESETN;
output [0:0] S_AXI_ARESET_OUT_N;
output [0:0] M_AXI_ARESET_OUT_N;
output IRQ;
input [0:0] S_AXI_ACLK;
input [0:0] S_AXI_AWID;
input [31:0] S_AXI_AWADDR;
input [7:0] S_AXI_AWLEN;
input [2:0] S_AXI_AWSIZE;
input [1:0] S_AXI_AWBURST;
input [1:0] S_AXI_AWLOCK;
input [3:0] S_AXI_AWCACHE;
input [2:0] S_AXI_AWPROT;
input [3:0] S_AXI_AWQOS;
input [0:0] S_AXI_AWUSER;
input [0:0] S_AXI_AWVALID;
output [0:0] S_AXI_AWREADY;
input [0:0] S_AXI_WID;
input [31:0] S_AXI_WDATA;
input [3:0] S_AXI_WSTRB;
input [0:0] S_AXI_WLAST;
input [0:0] S_AXI_WUSER;
input [0:0] S_AXI_WVALID;
output [0:0] S_AXI_WREADY;
output [0:0] S_AXI_BID;
output [1:0] S_AXI_BRESP;
output [0:0] S_AXI_BUSER;
output [0:0] S_AXI_BVALID;
input [0:0] S_AXI_BREADY;
input [0:0] S_AXI_ARID;
input [31:0] S_AXI_ARADDR;
input [7:0] S_AXI_ARLEN;
input [2:0] S_AXI_ARSIZE;
input [1:0] S_AXI_ARBURST;
input [1:0] S_AXI_ARLOCK;
input [3:0] S_AXI_ARCACHE;
input [2:0] S_AXI_ARPROT;
input [3:0] S_AXI_ARQOS;
input [0:0] S_AXI_ARUSER;
input [0:0] S_AXI_ARVALID;
output [0:0] S_AXI_ARREADY;
output [0:0] S_AXI_RID;
output [31:0] S_AXI_RDATA;
output [1:0] S_AXI_RRESP;
output [0:0] S_AXI_RLAST;
output [0:0] S_AXI_RUSER;
output [0:0] S_AXI_RVALID;
input [0:0] S_AXI_RREADY;
input [0:0] M_AXI_ACLK;
output [0:0] M_AXI_AWID;
output [31:0] M_AXI_AWADDR;
output [7:0] M_AXI_AWLEN;
output [2:0] M_AXI_AWSIZE;
output [1:0] M_AXI_AWBURST;
output [1:0] M_AXI_AWLOCK;
output [3:0] M_AXI_AWCACHE;
output [2:0] M_AXI_AWPROT;
output [3:0] M_AXI_AWREGION;
output [3:0] M_AXI_AWQOS;
output [0:0] M_AXI_AWUSER;
output [0:0] M_AXI_AWVALID;
input [0:0] M_AXI_AWREADY;
output [0:0] M_AXI_WID;
output [31:0] M_AXI_WDATA;
output [3:0] M_AXI_WSTRB;
output [0:0] M_AXI_WLAST;
output [0:0] M_AXI_WUSER;
output [0:0] M_AXI_WVALID;
input [0:0] M_AXI_WREADY;
input [0:0] M_AXI_BID;
input [1:0] M_AXI_BRESP;
input [0:0] M_AXI_BUSER;
input [0:0] M_AXI_BVALID;
output [0:0] M_AXI_BREADY;
output [0:0] M_AXI_ARID;
output [31:0] M_AXI_ARADDR;
output [7:0] M_AXI_ARLEN;
output [2:0] M_AXI_ARSIZE;
output [1:0] M_AXI_ARBURST;
output [1:0] M_AXI_ARLOCK;
output [3:0] M_AXI_ARCACHE;
output [2:0] M_AXI_ARPROT;
output [3:0] M_AXI_ARREGION;
output [3:0] M_AXI_ARQOS;
output [0:0] M_AXI_ARUSER;
output [0:0] M_AXI_ARVALID;
input [0:0] M_AXI_ARREADY;
input [0:0] M_AXI_RID;
input [31:0] M_AXI_RDATA;
input [1:0] M_AXI_RRESP;
input [0:0] M_AXI_RLAST;
input [0:0] M_AXI_RUSER;
input [0:0] M_AXI_RVALID;
output [0:0] M_AXI_RREADY;
input [31:0] S_AXI_CTRL_AWADDR;
input S_AXI_CTRL_AWVALID;
output S_AXI_CTRL_AWREADY;
input [31:0] S_AXI_CTRL_WDATA;
input S_AXI_CTRL_WVALID;
output S_AXI_CTRL_WREADY;
output [1:0] S_AXI_CTRL_BRESP;
output S_AXI_CTRL_BVALID;
input S_AXI_CTRL_BREADY;
input [31:0] S_AXI_CTRL_ARADDR;
input S_AXI_CTRL_ARVALID;
output S_AXI_CTRL_ARREADY;
output [31:0] S_AXI_CTRL_RDATA;
output [1:0] S_AXI_CTRL_RRESP;
output S_AXI_CTRL_RVALID;
input S_AXI_CTRL_RREADY;
output INTERCONNECT_ARESET_OUT_N;
output [7:0] DEBUG_AW_TRANS_SEQ;
output [7:0] DEBUG_AW_ARB_GRANT;
output [7:0] DEBUG_AR_TRANS_SEQ;
output [7:0] DEBUG_AR_ARB_GRANT;
output [0:0] DEBUG_AW_TRANS_QUAL;
output [7:0] DEBUG_AW_ACCEPT_CNT;
output [15:0] DEBUG_AW_ACTIVE_THREAD;
output [7:0] DEBUG_AW_ACTIVE_TARGET;
output [7:0] DEBUG_AW_ACTIVE_REGION;
output [7:0] DEBUG_AW_ERROR;
output [7:0] DEBUG_AW_TARGET;
output [0:0] DEBUG_AR_TRANS_QUAL;
output [7:0] DEBUG_AR_ACCEPT_CNT;
output [15:0] DEBUG_AR_ACTIVE_THREAD;
output [7:0] DEBUG_AR_ACTIVE_TARGET;
output [7:0] DEBUG_AR_ACTIVE_REGION;
output [7:0] DEBUG_AR_ERROR;
output [7:0] DEBUG_AR_TARGET;
output [7:0] DEBUG_B_TRANS_SEQ;
output [7:0] DEBUG_R_BEAT_CNT;
output [7:0] DEBUG_R_TRANS_SEQ;
output [7:0] DEBUG_AW_ISSUING_CNT;
output [7:0] DEBUG_AR_ISSUING_CNT;
output [7:0] DEBUG_W_BEAT_CNT;
output [7:0] DEBUG_W_TRANS_SEQ;
output [7:0] DEBUG_BID_TARGET;
output DEBUG_BID_ERROR;
output [7:0] DEBUG_RID_TARGET;
output DEBUG_RID_ERROR;
output [31:0] DEBUG_SR_SC_ARADDR;
output [23:0] DEBUG_SR_SC_ARADDRCONTROL;
output [31:0] DEBUG_SR_SC_AWADDR;
output [23:0] DEBUG_SR_SC_AWADDRCONTROL;
output [4:0] DEBUG_SR_SC_BRESP;
output [31:0] DEBUG_SR_SC_RDATA;
output [5:0] DEBUG_SR_SC_RDATACONTROL;
output [31:0] DEBUG_SR_SC_WDATA;
output [6:0] DEBUG_SR_SC_WDATACONTROL;
output [31:0] DEBUG_SC_SF_ARADDR;
output [23:0] DEBUG_SC_SF_ARADDRCONTROL;
output [31:0] DEBUG_SC_SF_AWADDR;
output [23:0] DEBUG_SC_SF_AWADDRCONTROL;
output [4:0] DEBUG_SC_SF_BRESP;
output [31:0] DEBUG_SC_SF_RDATA;
output [5:0] DEBUG_SC_SF_RDATACONTROL;
output [31:0] DEBUG_SC_SF_WDATA;
output [6:0] DEBUG_SC_SF_WDATACONTROL;
output [31:0] DEBUG_SF_CB_ARADDR;
output [23:0] DEBUG_SF_CB_ARADDRCONTROL;
output [31:0] DEBUG_SF_CB_AWADDR;
output [23:0] DEBUG_SF_CB_AWADDRCONTROL;
output [4:0] DEBUG_SF_CB_BRESP;
output [31:0] DEBUG_SF_CB_RDATA;
output [5:0] DEBUG_SF_CB_RDATACONTROL;
output [31:0] DEBUG_SF_CB_WDATA;
output [6:0] DEBUG_SF_CB_WDATACONTROL;
output [31:0] DEBUG_CB_MF_ARADDR;
output [23:0] DEBUG_CB_MF_ARADDRCONTROL;
output [31:0] DEBUG_CB_MF_AWADDR;
output [23:0] DEBUG_CB_MF_AWADDRCONTROL;
output [4:0] DEBUG_CB_MF_BRESP;
output [31:0] DEBUG_CB_MF_RDATA;
output [5:0] DEBUG_CB_MF_RDATACONTROL;
output [31:0] DEBUG_CB_MF_WDATA;
output [6:0] DEBUG_CB_MF_WDATACONTROL;
output [31:0] DEBUG_MF_MC_ARADDR;
output [23:0] DEBUG_MF_MC_ARADDRCONTROL;
output [31:0] DEBUG_MF_MC_AWADDR;
output [23:0] DEBUG_MF_MC_AWADDRCONTROL;
output [4:0] DEBUG_MF_MC_BRESP;
output [31:0] DEBUG_MF_MC_RDATA;
output [5:0] DEBUG_MF_MC_RDATACONTROL;
output [31:0] DEBUG_MF_MC_WDATA;
output [6:0] DEBUG_MF_MC_WDATACONTROL;
output [31:0] DEBUG_MC_MP_ARADDR;
output [23:0] DEBUG_MC_MP_ARADDRCONTROL;
output [31:0] DEBUG_MC_MP_AWADDR;
output [23:0] DEBUG_MC_MP_AWADDRCONTROL;
output [4:0] DEBUG_MC_MP_BRESP;
output [31:0] DEBUG_MC_MP_RDATA;
output [5:0] DEBUG_MC_MP_RDATACONTROL;
output [31:0] DEBUG_MC_MP_WDATA;
output [6:0] DEBUG_MC_MP_WDATACONTROL;
output [31:0] DEBUG_MP_MR_ARADDR;
output [23:0] DEBUG_MP_MR_ARADDRCONTROL;
output [31:0] DEBUG_MP_MR_AWADDR;
output [23:0] DEBUG_MP_MR_AWADDRCONTROL;
output [4:0] DEBUG_MP_MR_BRESP;
output [31:0] DEBUG_MP_MR_RDATA;
output [5:0] DEBUG_MP_MR_RDATACONTROL;
output [31:0] DEBUG_MP_MR_WDATA;
output [6:0] DEBUG_MP_MR_WDATACONTROL;
axi_interconnect
#(
.C_BASEFAMILY ( "zynq" ),
.C_NUM_SLAVE_SLOTS ( 1 ),
.C_NUM_MASTER_SLOTS ( 1 ),
.C_AXI_ID_WIDTH ( 1 ),
.C_AXI_ADDR_WIDTH ( 32 ),
.C_AXI_DATA_MAX_WIDTH ( 32 ),
.C_S_AXI_DATA_WIDTH ( 512'h00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 ),
.C_M_AXI_DATA_WIDTH ( 512'h00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 ),
.C_INTERCONNECT_DATA_WIDTH ( 32 ),
.C_S_AXI_PROTOCOL ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ),
.C_M_AXI_PROTOCOL ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ),
.C_M_AXI_BASE_ADDR ( 16384'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000000000000 ),
.C_M_AXI_HIGH_ADDR ( 16384'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001fffffff ),
.C_S_AXI_BASE_ID ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_THREAD_ID_WIDTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_IS_INTERCONNECT ( 16'b0000000000000000 ),
.C_S_AXI_ACLK_RATIO ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100 ),
.C_S_AXI_IS_ACLK_ASYNC ( 16'b0000000000000000 ),
.C_M_AXI_ACLK_RATIO ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100 ),
.C_M_AXI_IS_ACLK_ASYNC ( 16'b0000000000000000 ),
.C_INTERCONNECT_ACLK_RATIO ( 100000000 ),
.C_S_AXI_SUPPORTS_WRITE ( 16'b1111111111111111 ),
.C_S_AXI_SUPPORTS_READ ( 16'b1111111111111111 ),
.C_M_AXI_SUPPORTS_WRITE ( 16'b1111111111111111 ),
.C_M_AXI_SUPPORTS_READ ( 16'b1111111111111111 ),
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ),
.C_AXI_AWUSER_WIDTH ( 1 ),
.C_AXI_ARUSER_WIDTH ( 1 ),
.C_AXI_WUSER_WIDTH ( 1 ),
.C_AXI_RUSER_WIDTH ( 1 ),
.C_AXI_BUSER_WIDTH ( 1 ),
.C_AXI_CONNECTIVITY ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ),
.C_S_AXI_SINGLE_THREAD ( 16'b0000000000000000 ),
.C_M_AXI_SUPPORTS_REORDERING ( 16'b1111111111111111 ),
.C_S_AXI_SUPPORTS_NARROW_BURST ( 16'b1111111111111111 ),
.C_M_AXI_SUPPORTS_NARROW_BURST ( 16'b1111111111111111 ),
.C_S_AXI_WRITE_ACCEPTANCE ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ),
.C_S_AXI_READ_ACCEPTANCE ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ),
.C_M_AXI_WRITE_ISSUING ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008 ),
.C_M_AXI_READ_ISSUING ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008 ),
.C_S_AXI_ARB_PRIORITY ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_SECURE ( 16'b0000000000000000 ),
.C_S_AXI_WRITE_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_WRITE_FIFO_TYPE ( 16'b1111111111111111 ),
.C_S_AXI_WRITE_FIFO_DELAY ( 16'b0000000000000000 ),
.C_S_AXI_READ_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_READ_FIFO_TYPE ( 16'b1111111111111111 ),
.C_S_AXI_READ_FIFO_DELAY ( 16'b0000000000000000 ),
.C_M_AXI_WRITE_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_WRITE_FIFO_TYPE ( 16'b1111111111111111 ),
.C_M_AXI_WRITE_FIFO_DELAY ( 16'b0000000000000000 ),
.C_M_AXI_READ_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_READ_FIFO_TYPE ( 16'b1111111111111111 ),
.C_M_AXI_READ_FIFO_DELAY ( 16'b0000000000000000 ),
.C_S_AXI_AW_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_AR_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_W_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_R_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_B_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_AW_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_AR_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_W_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_R_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_B_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_INTERCONNECT_R_REGISTER ( 0 ),
.C_INTERCONNECT_CONNECTIVITY_MODE ( 1 ),
.C_USE_CTRL_PORT ( 0 ),
.C_USE_INTERRUPT ( 1 ),
.C_RANGE_CHECK ( 0 ),
.C_S_AXI_CTRL_ADDR_WIDTH ( 32 ),
.C_S_AXI_CTRL_DATA_WIDTH ( 32 ),
.C_DEBUG ( 0 ),
.C_S_AXI_DEBUG_SLOT ( 0 ),
.C_M_AXI_DEBUG_SLOT ( 0 ),
.C_MAX_DEBUG_THREADS ( 1 )
)
axi_interconnect_1 (
.INTERCONNECT_ACLK ( INTERCONNECT_ACLK ),
.INTERCONNECT_ARESETN ( INTERCONNECT_ARESETN ),
.S_AXI_ARESET_OUT_N ( S_AXI_ARESET_OUT_N ),
.M_AXI_ARESET_OUT_N ( M_AXI_ARESET_OUT_N ),
.IRQ ( IRQ ),
.S_AXI_ACLK ( S_AXI_ACLK ),
.S_AXI_AWID ( S_AXI_AWID ),
.S_AXI_AWADDR ( S_AXI_AWADDR ),
.S_AXI_AWLEN ( S_AXI_AWLEN ),
.S_AXI_AWSIZE ( S_AXI_AWSIZE ),
.S_AXI_AWBURST ( S_AXI_AWBURST ),
.S_AXI_AWLOCK ( S_AXI_AWLOCK ),
.S_AXI_AWCACHE ( S_AXI_AWCACHE ),
.S_AXI_AWPROT ( S_AXI_AWPROT ),
.S_AXI_AWQOS ( S_AXI_AWQOS ),
.S_AXI_AWUSER ( S_AXI_AWUSER ),
.S_AXI_AWVALID ( S_AXI_AWVALID ),
.S_AXI_AWREADY ( S_AXI_AWREADY ),
.S_AXI_WID ( S_AXI_WID ),
.S_AXI_WDATA ( S_AXI_WDATA ),
.S_AXI_WSTRB ( S_AXI_WSTRB ),
.S_AXI_WLAST ( S_AXI_WLAST ),
.S_AXI_WUSER ( S_AXI_WUSER ),
.S_AXI_WVALID ( S_AXI_WVALID ),
.S_AXI_WREADY ( S_AXI_WREADY ),
.S_AXI_BID ( S_AXI_BID ),
.S_AXI_BRESP ( S_AXI_BRESP ),
.S_AXI_BUSER ( S_AXI_BUSER ),
.S_AXI_BVALID ( S_AXI_BVALID ),
.S_AXI_BREADY ( S_AXI_BREADY ),
.S_AXI_ARID ( S_AXI_ARID ),
.S_AXI_ARADDR ( S_AXI_ARADDR ),
.S_AXI_ARLEN ( S_AXI_ARLEN ),
.S_AXI_ARSIZE ( S_AXI_ARSIZE ),
.S_AXI_ARBURST ( S_AXI_ARBURST ),
.S_AXI_ARLOCK ( S_AXI_ARLOCK ),
.S_AXI_ARCACHE ( S_AXI_ARCACHE ),
.S_AXI_ARPROT ( S_AXI_ARPROT ),
.S_AXI_ARQOS ( S_AXI_ARQOS ),
.S_AXI_ARUSER ( S_AXI_ARUSER ),
.S_AXI_ARVALID ( S_AXI_ARVALID ),
.S_AXI_ARREADY ( S_AXI_ARREADY ),
.S_AXI_RID ( S_AXI_RID ),
.S_AXI_RDATA ( S_AXI_RDATA ),
.S_AXI_RRESP ( S_AXI_RRESP ),
.S_AXI_RLAST ( S_AXI_RLAST ),
.S_AXI_RUSER ( S_AXI_RUSER ),
.S_AXI_RVALID ( S_AXI_RVALID ),
.S_AXI_RREADY ( S_AXI_RREADY ),
.M_AXI_ACLK ( M_AXI_ACLK ),
.M_AXI_AWID ( M_AXI_AWID ),
.M_AXI_AWADDR ( M_AXI_AWADDR ),
.M_AXI_AWLEN ( M_AXI_AWLEN ),
.M_AXI_AWSIZE ( M_AXI_AWSIZE ),
.M_AXI_AWBURST ( M_AXI_AWBURST ),
.M_AXI_AWLOCK ( M_AXI_AWLOCK ),
.M_AXI_AWCACHE ( M_AXI_AWCACHE ),
.M_AXI_AWPROT ( M_AXI_AWPROT ),
.M_AXI_AWREGION ( M_AXI_AWREGION ),
.M_AXI_AWQOS ( M_AXI_AWQOS ),
.M_AXI_AWUSER ( M_AXI_AWUSER ),
.M_AXI_AWVALID ( M_AXI_AWVALID ),
.M_AXI_AWREADY ( M_AXI_AWREADY ),
.M_AXI_WID ( M_AXI_WID ),
.M_AXI_WDATA ( M_AXI_WDATA ),
.M_AXI_WSTRB ( M_AXI_WSTRB ),
.M_AXI_WLAST ( M_AXI_WLAST ),
.M_AXI_WUSER ( M_AXI_WUSER ),
.M_AXI_WVALID ( M_AXI_WVALID ),
.M_AXI_WREADY ( M_AXI_WREADY ),
.M_AXI_BID ( M_AXI_BID ),
.M_AXI_BRESP ( M_AXI_BRESP ),
.M_AXI_BUSER ( M_AXI_BUSER ),
.M_AXI_BVALID ( M_AXI_BVALID ),
.M_AXI_BREADY ( M_AXI_BREADY ),
.M_AXI_ARID ( M_AXI_ARID ),
.M_AXI_ARADDR ( M_AXI_ARADDR ),
.M_AXI_ARLEN ( M_AXI_ARLEN ),
.M_AXI_ARSIZE ( M_AXI_ARSIZE ),
.M_AXI_ARBURST ( M_AXI_ARBURST ),
.M_AXI_ARLOCK ( M_AXI_ARLOCK ),
.M_AXI_ARCACHE ( M_AXI_ARCACHE ),
.M_AXI_ARPROT ( M_AXI_ARPROT ),
.M_AXI_ARREGION ( M_AXI_ARREGION ),
.M_AXI_ARQOS ( M_AXI_ARQOS ),
.M_AXI_ARUSER ( M_AXI_ARUSER ),
.M_AXI_ARVALID ( M_AXI_ARVALID ),
.M_AXI_ARREADY ( M_AXI_ARREADY ),
.M_AXI_RID ( M_AXI_RID ),
.M_AXI_RDATA ( M_AXI_RDATA ),
.M_AXI_RRESP ( M_AXI_RRESP ),
.M_AXI_RLAST ( M_AXI_RLAST ),
.M_AXI_RUSER ( M_AXI_RUSER ),
.M_AXI_RVALID ( M_AXI_RVALID ),
.M_AXI_RREADY ( M_AXI_RREADY ),
.S_AXI_CTRL_AWADDR ( S_AXI_CTRL_AWADDR ),
.S_AXI_CTRL_AWVALID ( S_AXI_CTRL_AWVALID ),
.S_AXI_CTRL_AWREADY ( S_AXI_CTRL_AWREADY ),
.S_AXI_CTRL_WDATA ( S_AXI_CTRL_WDATA ),
.S_AXI_CTRL_WVALID ( S_AXI_CTRL_WVALID ),
.S_AXI_CTRL_WREADY ( S_AXI_CTRL_WREADY ),
.S_AXI_CTRL_BRESP ( S_AXI_CTRL_BRESP ),
.S_AXI_CTRL_BVALID ( S_AXI_CTRL_BVALID ),
.S_AXI_CTRL_BREADY ( S_AXI_CTRL_BREADY ),
.S_AXI_CTRL_ARADDR ( S_AXI_CTRL_ARADDR ),
.S_AXI_CTRL_ARVALID ( S_AXI_CTRL_ARVALID ),
.S_AXI_CTRL_ARREADY ( S_AXI_CTRL_ARREADY ),
.S_AXI_CTRL_RDATA ( S_AXI_CTRL_RDATA ),
.S_AXI_CTRL_RRESP ( S_AXI_CTRL_RRESP ),
.S_AXI_CTRL_RVALID ( S_AXI_CTRL_RVALID ),
.S_AXI_CTRL_RREADY ( S_AXI_CTRL_RREADY ),
.INTERCONNECT_ARESET_OUT_N ( INTERCONNECT_ARESET_OUT_N ),
.DEBUG_AW_TRANS_SEQ ( DEBUG_AW_TRANS_SEQ ),
.DEBUG_AW_ARB_GRANT ( DEBUG_AW_ARB_GRANT ),
.DEBUG_AR_TRANS_SEQ ( DEBUG_AR_TRANS_SEQ ),
.DEBUG_AR_ARB_GRANT ( DEBUG_AR_ARB_GRANT ),
.DEBUG_AW_TRANS_QUAL ( DEBUG_AW_TRANS_QUAL ),
.DEBUG_AW_ACCEPT_CNT ( DEBUG_AW_ACCEPT_CNT ),
.DEBUG_AW_ACTIVE_THREAD ( DEBUG_AW_ACTIVE_THREAD ),
.DEBUG_AW_ACTIVE_TARGET ( DEBUG_AW_ACTIVE_TARGET ),
.DEBUG_AW_ACTIVE_REGION ( DEBUG_AW_ACTIVE_REGION ),
.DEBUG_AW_ERROR ( DEBUG_AW_ERROR ),
.DEBUG_AW_TARGET ( DEBUG_AW_TARGET ),
.DEBUG_AR_TRANS_QUAL ( DEBUG_AR_TRANS_QUAL ),
.DEBUG_AR_ACCEPT_CNT ( DEBUG_AR_ACCEPT_CNT ),
.DEBUG_AR_ACTIVE_THREAD ( DEBUG_AR_ACTIVE_THREAD ),
.DEBUG_AR_ACTIVE_TARGET ( DEBUG_AR_ACTIVE_TARGET ),
.DEBUG_AR_ACTIVE_REGION ( DEBUG_AR_ACTIVE_REGION ),
.DEBUG_AR_ERROR ( DEBUG_AR_ERROR ),
.DEBUG_AR_TARGET ( DEBUG_AR_TARGET ),
.DEBUG_B_TRANS_SEQ ( DEBUG_B_TRANS_SEQ ),
.DEBUG_R_BEAT_CNT ( DEBUG_R_BEAT_CNT ),
.DEBUG_R_TRANS_SEQ ( DEBUG_R_TRANS_SEQ ),
.DEBUG_AW_ISSUING_CNT ( DEBUG_AW_ISSUING_CNT ),
.DEBUG_AR_ISSUING_CNT ( DEBUG_AR_ISSUING_CNT ),
.DEBUG_W_BEAT_CNT ( DEBUG_W_BEAT_CNT ),
.DEBUG_W_TRANS_SEQ ( DEBUG_W_TRANS_SEQ ),
.DEBUG_BID_TARGET ( DEBUG_BID_TARGET ),
.DEBUG_BID_ERROR ( DEBUG_BID_ERROR ),
.DEBUG_RID_TARGET ( DEBUG_RID_TARGET ),
.DEBUG_RID_ERROR ( DEBUG_RID_ERROR ),
.DEBUG_SR_SC_ARADDR ( DEBUG_SR_SC_ARADDR ),
.DEBUG_SR_SC_ARADDRCONTROL ( DEBUG_SR_SC_ARADDRCONTROL ),
.DEBUG_SR_SC_AWADDR ( DEBUG_SR_SC_AWADDR ),
.DEBUG_SR_SC_AWADDRCONTROL ( DEBUG_SR_SC_AWADDRCONTROL ),
.DEBUG_SR_SC_BRESP ( DEBUG_SR_SC_BRESP ),
.DEBUG_SR_SC_RDATA ( DEBUG_SR_SC_RDATA ),
.DEBUG_SR_SC_RDATACONTROL ( DEBUG_SR_SC_RDATACONTROL ),
.DEBUG_SR_SC_WDATA ( DEBUG_SR_SC_WDATA ),
.DEBUG_SR_SC_WDATACONTROL ( DEBUG_SR_SC_WDATACONTROL ),
.DEBUG_SC_SF_ARADDR ( DEBUG_SC_SF_ARADDR ),
.DEBUG_SC_SF_ARADDRCONTROL ( DEBUG_SC_SF_ARADDRCONTROL ),
.DEBUG_SC_SF_AWADDR ( DEBUG_SC_SF_AWADDR ),
.DEBUG_SC_SF_AWADDRCONTROL ( DEBUG_SC_SF_AWADDRCONTROL ),
.DEBUG_SC_SF_BRESP ( DEBUG_SC_SF_BRESP ),
.DEBUG_SC_SF_RDATA ( DEBUG_SC_SF_RDATA ),
.DEBUG_SC_SF_RDATACONTROL ( DEBUG_SC_SF_RDATACONTROL ),
.DEBUG_SC_SF_WDATA ( DEBUG_SC_SF_WDATA ),
.DEBUG_SC_SF_WDATACONTROL ( DEBUG_SC_SF_WDATACONTROL ),
.DEBUG_SF_CB_ARADDR ( DEBUG_SF_CB_ARADDR ),
.DEBUG_SF_CB_ARADDRCONTROL ( DEBUG_SF_CB_ARADDRCONTROL ),
.DEBUG_SF_CB_AWADDR ( DEBUG_SF_CB_AWADDR ),
.DEBUG_SF_CB_AWADDRCONTROL ( DEBUG_SF_CB_AWADDRCONTROL ),
.DEBUG_SF_CB_BRESP ( DEBUG_SF_CB_BRESP ),
.DEBUG_SF_CB_RDATA ( DEBUG_SF_CB_RDATA ),
.DEBUG_SF_CB_RDATACONTROL ( DEBUG_SF_CB_RDATACONTROL ),
.DEBUG_SF_CB_WDATA ( DEBUG_SF_CB_WDATA ),
.DEBUG_SF_CB_WDATACONTROL ( DEBUG_SF_CB_WDATACONTROL ),
.DEBUG_CB_MF_ARADDR ( DEBUG_CB_MF_ARADDR ),
.DEBUG_CB_MF_ARADDRCONTROL ( DEBUG_CB_MF_ARADDRCONTROL ),
.DEBUG_CB_MF_AWADDR ( DEBUG_CB_MF_AWADDR ),
.DEBUG_CB_MF_AWADDRCONTROL ( DEBUG_CB_MF_AWADDRCONTROL ),
.DEBUG_CB_MF_BRESP ( DEBUG_CB_MF_BRESP ),
.DEBUG_CB_MF_RDATA ( DEBUG_CB_MF_RDATA ),
.DEBUG_CB_MF_RDATACONTROL ( DEBUG_CB_MF_RDATACONTROL ),
.DEBUG_CB_MF_WDATA ( DEBUG_CB_MF_WDATA ),
.DEBUG_CB_MF_WDATACONTROL ( DEBUG_CB_MF_WDATACONTROL ),
.DEBUG_MF_MC_ARADDR ( DEBUG_MF_MC_ARADDR ),
.DEBUG_MF_MC_ARADDRCONTROL ( DEBUG_MF_MC_ARADDRCONTROL ),
.DEBUG_MF_MC_AWADDR ( DEBUG_MF_MC_AWADDR ),
.DEBUG_MF_MC_AWADDRCONTROL ( DEBUG_MF_MC_AWADDRCONTROL ),
.DEBUG_MF_MC_BRESP ( DEBUG_MF_MC_BRESP ),
.DEBUG_MF_MC_RDATA ( DEBUG_MF_MC_RDATA ),
.DEBUG_MF_MC_RDATACONTROL ( DEBUG_MF_MC_RDATACONTROL ),
.DEBUG_MF_MC_WDATA ( DEBUG_MF_MC_WDATA ),
.DEBUG_MF_MC_WDATACONTROL ( DEBUG_MF_MC_WDATACONTROL ),
.DEBUG_MC_MP_ARADDR ( DEBUG_MC_MP_ARADDR ),
.DEBUG_MC_MP_ARADDRCONTROL ( DEBUG_MC_MP_ARADDRCONTROL ),
.DEBUG_MC_MP_AWADDR ( DEBUG_MC_MP_AWADDR ),
.DEBUG_MC_MP_AWADDRCONTROL ( DEBUG_MC_MP_AWADDRCONTROL ),
.DEBUG_MC_MP_BRESP ( DEBUG_MC_MP_BRESP ),
.DEBUG_MC_MP_RDATA ( DEBUG_MC_MP_RDATA ),
.DEBUG_MC_MP_RDATACONTROL ( DEBUG_MC_MP_RDATACONTROL ),
.DEBUG_MC_MP_WDATA ( DEBUG_MC_MP_WDATA ),
.DEBUG_MC_MP_WDATACONTROL ( DEBUG_MC_MP_WDATACONTROL ),
.DEBUG_MP_MR_ARADDR ( DEBUG_MP_MR_ARADDR ),
.DEBUG_MP_MR_ARADDRCONTROL ( DEBUG_MP_MR_ARADDRCONTROL ),
.DEBUG_MP_MR_AWADDR ( DEBUG_MP_MR_AWADDR ),
.DEBUG_MP_MR_AWADDRCONTROL ( DEBUG_MP_MR_AWADDRCONTROL ),
.DEBUG_MP_MR_BRESP ( DEBUG_MP_MR_BRESP ),
.DEBUG_MP_MR_RDATA ( DEBUG_MP_MR_RDATA ),
.DEBUG_MP_MR_RDATACONTROL ( DEBUG_MP_MR_RDATACONTROL ),
.DEBUG_MP_MR_WDATA ( DEBUG_MP_MR_WDATA ),
.DEBUG_MP_MR_WDATACONTROL ( DEBUG_MP_MR_WDATACONTROL )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXTP_SYMBOL_V
`define SKY130_FD_SC_HS__SEDFXTP_SYMBOL_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sedfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DE ,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXTP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGSBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SREGSBP_FUNCTIONAL_PP_V
/**
* sregsbp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sregsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire set ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (set , ASYNC );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, set, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGSBP_FUNCTIONAL_PP_V
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 5
*/
// Testbench for behavioral model for the circular FIFO
// Import the modules that will be tested for in this testbench
`include "fifo.v"
// IMPORTANT: To run this, try: ncverilog -f fifo.f +gui
module tb_fifo();
/**
* Depth = number of rows for the register file
*
* The construct base**exponent is not synthesizable for our
* tool and technology library set up. It should be with the latest
* version of Verilog, Verilog 2005
*/
parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
// Width of the register file
parameter WIDTH = 8;
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the FIFO queue
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// data_out & emp & full_cb output signals
wire [7:0] d_out;
wire empty_cb,full_cb;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// push, pop, reset, & clk
reg push_cb,pop_cb,rst,clock;
// data_in
reg [WIDTH-1:0] d_in;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of SIPO() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
FIFO fifo_cb (
// instance_name(signal name),
// Signal name can be the same as the instance name
d_out,empty_cb,full_cb,d_in,push_cb,pop_cb,rst,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
rst=1'd1; // Reset
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd45;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd231;
// Push 8...
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd230;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd37;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd174;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd235;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd39;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd201;
// Pop 8...
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
// Try push and pull
/*
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd18;
*/
// Push 3 in
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd18;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
/*
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd74;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd138;
// Pop 3 out
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
*/
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
`default_nettype none
module execute_forwarding_register(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Writeback - General Register
input wire iWB_GR_VALID,
input wire [31:0] iWB_GR_DATA,
input wire [4:0] iWB_GR_DEST,
input wire iWB_GR_DEST_SYSREG,
//Writeback - Stack Point Register
input wire iWB_SPR_VALID,
input wire [31:0] iWB_SPR_DATA,
//Writeback[AUTO] - Stack Point Register
input wire iWB_AUTO_SPR_VALID,
input wire [31:0] iWB_AUTO_SPR_DATA,
//Current - Stack Point Register
input wire [31:0] iCUUR_SPR_DATA,
//Writeback - FRCR
input wire iWB_FRCR_VALID,
input wire [63:0] iWB_FRCR_DATA,
//Current - FRCR
input wire [63:0] iCUUR_FRCR_DATA,
//Fowerding Register Output
output wire oFDR_GR_VALID,
output wire [31:0] oFDR_GR_DATA,
output wire [4:0] oFDR_GR_DEST,
output wire oFDR_GR_DEST_SYSREG,
//Fowerding Register Output
output wire oFDR_SPR_VALID,
output wire [31:0] oFDR_SPR_DATA,
//Forwerding Register Output
output wire oFDR_FRCR_VALID,
output wire [63:0] oFDR_FRCR_DATA
);
//Fowarding General Register
reg b_ex_history_valid;
reg [31:0] b_ex_history_data;
reg [4:0] b_ex_history_destination;
reg b_ex_history_destination_sysreg;
//reg [31:0] b_ex_history_pc;
//Fowarding Stack Point Register
reg b_fwdng_spr_valid;
reg [31:0] b_fwdng_spr;
//FRCR
reg b_fwdng_frcr_valid;
reg [63:0] b_fwdng_frcr;
/************************************************************************
Fowarding Register
************************************************************************/
//General Register
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_ex_history_valid <= 1'h0;
b_ex_history_data <= 32'h0;
b_ex_history_destination <= 5'h0;
b_ex_history_destination_sysreg <= 1'h0;
//b_ex_history_pc <= 32'h0;
end
else if(iRESET_SYNC)begin
b_ex_history_valid <= 1'h0;
b_ex_history_data <= 32'h0;
b_ex_history_destination <= 5'h0;
b_ex_history_destination_sysreg <= 1'h0;
//b_ex_history_pc <= 32'h0;
end
else begin
if(iWB_GR_VALID)begin
b_ex_history_valid <= iWB_GR_VALID;
b_ex_history_data <= iWB_GR_DATA;
b_ex_history_destination <= iWB_GR_DEST;
b_ex_history_destination_sysreg <= iWB_GR_DEST_SYSREG;
//b_ex_history_pc <= iWB_PCR - 32'h00000004;
end
end
end
//Stack Point Register
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_fwdng_spr_valid <= 1'h0;
b_fwdng_spr <= 32'h0;
end
else if(iRESET_SYNC)begin
b_fwdng_spr_valid <= 1'h0;
b_fwdng_spr <= 32'h0;
end
else begin
if(iWB_SPR_VALID)begin
b_fwdng_spr_valid <= iWB_SPR_VALID;
b_fwdng_spr <= iWB_SPR_DATA;
end
else if(iWB_AUTO_SPR_VALID)begin
b_fwdng_spr_valid <= iWB_SPR_VALID;
b_fwdng_spr <= iWB_AUTO_SPR_DATA;
end
else begin
b_fwdng_spr_valid <= 1'b1;
b_fwdng_spr <= iCUUR_SPR_DATA;
end
end
end
//FRCR
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_fwdng_frcr_valid <= 1'h0;
b_fwdng_frcr <= 64'h0;
end
else if(iRESET_SYNC)begin
b_fwdng_frcr_valid <= 1'h0;
b_fwdng_frcr <= 64'h0;
end
else begin
if(iWB_FRCR_VALID)begin
b_fwdng_frcr_valid <= iWB_FRCR_VALID;
b_fwdng_frcr <= iWB_FRCR_DATA;
end
else begin
b_fwdng_frcr_valid <= 1'h1;
b_fwdng_frcr <= iCUUR_FRCR_DATA;
end
end
end
/************************************************************************
Assign
************************************************************************/
//GR Out
assign oFDR_GR_VALID = b_ex_history_valid;
assign oFDR_GR_DATA = b_ex_history_data;
assign oFDR_GR_DEST = b_ex_history_destination;
assign oFDR_GR_DEST_SYSREG = b_ex_history_destination_sysreg;
//SPR Out
assign oFDR_SPR_VALID = b_fwdng_spr_valid;
assign oFDR_SPR_DATA = b_fwdng_spr;
//FRCR Out
assign oFDR_FRCR_VALID = b_fwdng_frcr_valid;
assign oFDR_FRCR_DATA = b_fwdng_frcr;
endmodule
`default_nettype wire
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 08:26:59 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_rgb888_to_rgb565_0_0 -prefix
// system_rgb888_to_rgb565_0_0_ system_rgb888_to_rgb565_0_0_sim_netlist.v
// Design : system_rgb888_to_rgb565_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "rgb888_to_rgb565,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_rgb888_to_rgb565_0_0
(rgb_888,
rgb_565);
input [23:0]rgb_888;
output [15:0]rgb_565;
wire [23:0]rgb_888;
assign rgb_565[15:11] = rgb_888[23:19];
assign rgb_565[10:5] = rgb_888[15:10];
assign rgb_565[4:0] = rgb_888[7:3];
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.6
// \ \ Application : MIG
// / / Filename : memc_ui_top_std.v
// /___/ /\ Date Last Modified : $Date: 2011/06/10 13:17:56 $
// \ \ / \ Date Created : Fri Oct 08 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM & DDR3 SDRAM
// Purpose :
// Top level memory interface block. Instantiates a clock and
// reset generator, the memory controller, the phy and the
// user interface blocks.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
(* X_CORE_INFO = "mig_7series_v1_2_ddr3_7Series, Coregen 13.2" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v1_2,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Foundation_ISE, LEVEL=CONTROLLER, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, AXI_ENABLE=0, CLK_PERIOD=2500, PHY_RATIO=4, CLKIN_PERIOD=2500, VCCAUX_IO=1.8V, MEMORY_TYPE=SODIMM, MEMORY_PART=mt8jtf12864hz-1g6, DQ_WIDTH=64, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=60, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, INPUT_CLK_TYPE=DIFFERENTIAL}" *)
module memc_ui_top_std #
(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter ECC_TEST = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ORDERING = "NORM",
parameter IBUF_LPWR_MODE = "OFF",
parameter IODELAY_HP_MODE = "ON",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter OUTPUT_DRV = "HIGH",
parameter REG_CTRL = "OFF",
parameter RTT_NOM = "60",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter WRLVL = "OFF",
parameter DEBUG_PORT = "OFF",
parameter CAL_WIDTH = "HALF",
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter ADDR_WIDTH = 32,
parameter APP_MASK_WIDTH = 8,
parameter APP_DATA_WIDTH = 64,
parameter BYTE_LANES_B0 = 4'hF,
parameter BYTE_LANES_B1 = 4'hF,
parameter BYTE_LANES_B2 = 4'hF,
parameter BYTE_LANES_B3 = 4'hF,
parameter BYTE_LANES_B4 = 4'hF,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'h0,
parameter DATA_CTL_B4 = 4'h0,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter SLOT_0_CONFIG = 8'b0000_0001,
parameter SLOT_1_CONFIG = 8'b0000_0000,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter CALIB_ROW_ADD = 16'h0000, // Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1 // Support ODT output
)
(
// Clock and reset ports
input clk,
input clk_ref,
input mem_refclk ,
input freq_refclk ,
input pll_lock,
input sync_pulse ,
input rst,
// memory interface ports
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [RANKS-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
// user interface ports
input [ADDR_WIDTH-1:0] app_addr,
input [2:0] app_cmd,
input app_en,
input app_hi_pri,
input [APP_DATA_WIDTH-1:0] app_wdf_data,
input app_wdf_end,
input [APP_MASK_WIDTH-1:0] app_wdf_mask,
input app_wdf_wren,
input app_correct_en_i,
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc,
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err,
output [APP_DATA_WIDTH-1:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
// debug logic ports
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
output [255:0] dbg_calib_top,
output [5*DQS_WIDTH-1:0] dbg_cpt_first_edge_cnt,
output [5*DQS_WIDTH-1:0] dbg_cpt_second_edge_cnt,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [4*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [4:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output init_calib_complete
);
wire correct_en;
wire [2*nCK_PER_CLK-1:0] raw_not_ecc;
wire [2*nCK_PER_CLK-1:0] ecc_single;
wire [2*nCK_PER_CLK-1:0] ecc_multiple;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
wire wr_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire rd_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
wire accept;
wire accept_ns;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
wire rd_data_end;
wire use_addr;
wire size;
wire [ROW_WIDTH-1:0] row;
wire [RANK_WIDTH-1:0] rank;
wire hi_priority;
wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
wire [COL_WIDTH-1:0] col;
wire [2:0] cmd;
wire [BANK_WIDTH-1:0] bank;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
wire [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
mem_intfc #
(
.TCQ (TCQ),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.IODELAY_GRP (IODELAY_GRP),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT)
)
mem_intfc0
(
.clk (clk),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.rst (rst),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs (ddr_dqs),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck (ddr_ck),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_we_n (ddr_we_n),
.slot_0_present (SLOT_0_CONFIG),
.slot_1_present (SLOT_1_CONFIG),
.correct_en (correct_en),
.bank (bank),
.cmd (cmd),
.col (col),
.data_buf_addr (data_buf_addr),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.rank (rank),
.raw_not_ecc (raw_not_ecc),
.row (row),
.hi_priority (hi_priority),
.size (size),
.use_addr (use_addr),
.accept (accept),
.accept_ns (accept_ns),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.bank_mach_next (bank_mach_next),
.init_calib_complete (init_calib_complete),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start)
);
ui_top #
(
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER)
)
u_ui_top
(
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.use_addr (use_addr),
.size (size),
.row (row),
.raw_not_ecc (raw_not_ecc),
.rank (rank),
.hi_priority (hi_priority),
.data_buf_addr (data_buf_addr),
.col (col),
.cmd (cmd),
.bank (bank),
.app_wdf_rdy (app_wdf_rdy),
.app_rdy (app_rdy),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data),
.app_ecc_multiple_err (app_ecc_multiple_err),
.correct_en (correct_en),
.wr_data_offset (wr_data_offset),
.wr_data_en (wr_data_en),
.wr_data_addr (wr_data_addr),
.rst (rst),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.clk (clk),
.app_wdf_wren (app_wdf_wren),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_wdf_data (app_wdf_data),
.app_sz (1'b1),
.app_raw_not_ecc (app_raw_not_ecc),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.app_cmd (app_cmd),
.app_addr (app_addr),
.accept_ns (accept_ns),
.accept (accept),
.app_correct_en (app_correct_en_i)
);
endmodule
|
// ====================================================================
// Bashkiria-2M FPGA REPLICA
//
// Copyright (C) 2010 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Bashkiria-2M home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580vv55.v
//
// Parallel interface k580vv55 design file of Bashkiria-2M replica.
//
// Warning: This realization is not fully operational.
module k580vv55
(
input reset,
input clk_sys,
input [1:0] addr,
input we_n,
input [7:0] idata,
output reg[7:0] odata,
input [7:0] ipa,
output [7:0] opa,
input [7:0] ipb,
output [7:0] opb,
input [7:0] ipc,
output [7:0] opc
);
reg [7:0] mode;
reg [7:0] opa_r;
reg [7:0] opb_r;
reg [7:0] opc_r;
assign opa = mode[4] ? 8'hFF : opa_r;
assign opb = mode[1] ? 8'hFF : opb_r;
assign opc ={mode[3] ? 4'hF : opc_r[7:4], mode[0] ? 4'hF : opc_r[3:0]};
always @* begin
case(addr)
0: odata = mode[4] ? ipa : opa_r;
1: odata = mode[1] ? ipb : opb_r;
2: odata ={mode[3] ? ipc[7:4] : opc_r[7:4], mode[0] ? ipc[3:0] : opc_r[3:0]};
3: odata = 0;
endcase
end
always @(posedge clk_sys, posedge reset) begin
reg old_we;
if (reset) begin
{opa_r,opb_r,opc_r,mode} <= {8'h00,8'h00,8'h00,8'hFF};
end else begin
old_we <= we_n;
if(old_we & ~we_n) begin
case(addr)
0: opa_r <= idata;
1: opb_r <= idata;
2: opc_r <= idata;
default: begin
if (~idata[7]) opc_r[idata[3:1]] <= idata[0];
else {opa_r,opb_r,opc_r,mode} <= {8'h00,8'h00,8'h00,idata};
end
endcase
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlygate4sd1 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_FUNCTIONAL_V
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module HazardDetect(clk, reset, EX_MemRead, EX_Rt, EX_Rs, ID_Rt, ID_Rs, MuxCtl, PCWrite);
input EX_MemRead, clk, reset;
input [4:0] EX_Rt, ID_Rt, ID_Rs, EX_Rs;
output MuxCtl, PCWrite;
reg MuxCtl, PCWrite;
//set wires and registers
always @(clk or EX_Rs or EX_Rt or ID_Rs or ID_Rt )
begin
if(((EX_Rt == ID_Rt) && (EX_Rt != 0)) || ((EX_Rs == ID_Rs) && (EX_Rs != 0)))
begin
assign MuxCtl = 1;
assign PCWrite = 1;
end
else
begin
assign MuxCtl = 0;
assign PCWrite = 0;
end
end
initial begin
assign MuxCtl = 0;
assign PCWrite = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DIODE_PP_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_PP_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Drawing Engine Top Level Miscelaneos module
// File : de_top_misc.v
// Author : Frank Bruno
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module contains functionality which used to be instantiated at the
// top level
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module de_top_misc
(// inputs
input de_clk,
input sys_locked,
input hb_clk,
input hb_rstn,
input [1:0] ps_2,
input pc_mc_rdy,
input busy_hb,
input mw_de_fip,
input [4:0] dr_style_2,
input dx_blt_actv_2,
input load_actvn,
input line_actv_2,
input wb_clip_ind,
input clip,
input deb,
input cmd_trig_comb,
input line_actv_1,
input blt_actv_1,
input [23:0] de_key_2,
input cmdcpyclr,
input pc_empty,
input pal_busy,
output reg mw_fip,
output ca_busy,
output ps8_2,
output ps16_2,
output ps565_2,
output ps32_2,
output de_pad8_2,
output [1:0] stpl_2,
output reg de_rstn,
output reg de_clint_tog,
output reg dx_clp,
output reg dx_deb,
output [31:0] kcol_2,
output de_trnsp_2,
output reg de_ddint_tog,
output [3:0] probe_misc
);
wire wb_clip_rstn;
wire clip_ddd;
reg mw_fip_dd, de_busy_sync;
reg ca_busyi;
reg tmp_rstn;
reg clip_disab;
reg wb_clip;
reg clip_d, clip_dd;
reg deb_clr_hold;
reg deb_clr_q0,deb_clr_q1,deb_clr_q2;
reg deb_last;
reg de_clint;
reg pal_clr_q0;
reg pal_clr_q1;
reg pal_clr_q2;
reg pal_clr;
assign probe_misc = {ca_busyi, busy_hb, de_busy_sync, pc_mc_rdy};
// Syncronizers.
always @ (posedge de_clk) begin
de_busy_sync <= busy_hb;
mw_fip_dd <= mw_de_fip;
mw_fip <= mw_fip_dd;
end
always @ (posedge de_clk or negedge de_rstn) begin
if(!de_rstn) ca_busyi <= 1'b0;
else ca_busyi <= ~pc_empty | ((busy_hb & de_busy_sync) |
(~pc_mc_rdy & ca_busyi));
end
assign ca_busy = (ca_busyi | busy_hb);
// create the pixel size bits
assign ps8_2 = (ps_2==2'b00);
assign ps16_2 = (ps_2==2'b01) | (ps_2==2'b11);
assign ps565_2 = (ps_2==2'b11);
assign ps32_2 = (ps_2==2'b10);
// 8 bit padding for linear
assign de_pad8_2 = dr_style_2[3] & dr_style_2[2];
// transparent enable bit
assign de_trnsp_2 = (dr_style_2[1] & ~dr_style_2[0] & ~(dx_blt_actv_2)) |
(dr_style_2[1] & ~dr_style_2[0] &
(dr_style_2[3] | dr_style_2[2]));
// stipple packed enable bit
assign stpl_2[1] = dr_style_2[3] & ~line_actv_2;
// stipple planar enable bit
assign stpl_2[0] = ~dr_style_2[3] & dr_style_2[2] & ~line_actv_2;
// syncronize the drawing engine reset.
always @ (posedge de_clk) begin
tmp_rstn <= (sys_locked & hb_rstn);
de_rstn <= tmp_rstn;
end //
//
always @ (posedge de_clk or negedge de_rstn) begin
if (!de_rstn) clip_disab <= 1'b0;
else if (!load_actvn) clip_disab <= 1'b0;
else if (clip_ddd) clip_disab <= 1'b1;
end //
// grab the wb clip pulse.
always @ (posedge de_clk or negedge de_rstn) begin
if (!de_rstn) wb_clip <= 1'b0;
else if (clip_ddd) wb_clip <= 1'b0; // checkme ???? ~
else if (wb_clip_ind) wb_clip <= 1'b1;
end //
always @ (posedge de_clk) begin
clip_d <= ((clip & line_actv_2) | wb_clip);
clip_dd <= clip_d;
de_clint <= (clip_ddd & ~clip_disab);
end //
always @ (posedge de_clk or negedge de_rstn) begin
if(!de_rstn) de_clint_tog <= 1'b0;
else if(de_clint) de_clint_tog <= ~de_clint_tog;
end //
assign clip_ddd = clip_d & ~clip_dd;
always @ (posedge de_clk or negedge de_rstn) begin
if(!de_rstn) de_ddint_tog <= 1'b0;
else if(cmdcpyclr) de_ddint_tog <= ~de_ddint_tog;
end //
always @ (posedge de_clk or negedge de_rstn) begin
if (!de_rstn) dx_clp <= 1'b0;
else if (!load_actvn) dx_clp <= 1'b0;
else if (de_clint) dx_clp <= 1'b1;
end //
// Detect DEB going away
always @(posedge de_clk or negedge hb_rstn) begin
if (!hb_rstn) begin
deb_last <= 1'b0;
deb_clr_hold <= 1'b0;
end else begin
deb_last <= deb;
deb_clr_hold <= (deb_last & ~deb) ^ deb_clr_hold; // Selectable inverter
end
end
always @ (posedge hb_clk) begin
pal_clr_q0 <= pal_busy;
pal_clr_q1 <= pal_clr_q0;
pal_clr_q2 <= pal_clr_q1;
pal_clr <= (pal_clr_q2 & ~pal_clr_q1);
end //
always @ (posedge hb_clk) begin
deb_clr_q0 <= deb_clr_hold;
deb_clr_q1 <= deb_clr_q0;
deb_clr_q2 <= deb_clr_q1;
end //
wire busy_and_not_noop;
assign busy_and_not_noop = (busy_hb && (line_actv_1 || blt_actv_1));
always @(posedge hb_clk or negedge hb_rstn) begin
if (!hb_rstn) dx_deb <= 1'b0;
// else if (cmd_trig_comb && (line_actv_1 || blt_actv_1)) dx_deb <= 1'b1;
else if (cmd_trig_comb) dx_deb <= 1'b1;
else if ((deb_clr_q2 ^ deb_clr_q1) && !busy_and_not_noop) dx_deb <= 1'b0;
else if (pal_clr) dx_deb <= 1'b0;
end //
assign kcol_2 = (ps8_2) ?
{de_key_2[7:0],de_key_2[7:0],de_key_2[7:0],de_key_2[7:0]} :
(ps16_2) ? {de_key_2[15:0],de_key_2[15:0]} : {8'h0,de_key_2};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR2_1_V
`define SKY130_FD_SC_HD__XNOR2_1_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xnor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR2_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_2_V
`define SKY130_FD_SC_LS__O2111AI_2_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2111ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111ai_2 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21O_2_V
`define SKY130_FD_SC_LS__A21O_2_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21o_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21o_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21O_2_V
|
module test(I1,I2,I3,I4,enter,win,lose,reset,equal,bigger,smaller,nums);//,a1,a2,a3,a4,b1,b2,b3,b4,numa,numb,suc);
input I1, I2, I3, I4, enter,reset;
reg[0:6] a1,a2,a3,a4,suc,b1,b2,b3,b4;
reg[0:3] numa,numb;
output reg win,lose;
output reg equal,bigger,smaller;
reg runa,runb;
reg [0:3] turn;
output reg [0:3] nums;
initial begin
nums = 0;
win = 0;
suc = 0;
runa = 1;
runb = 0;
lose = 0;
equal = 0;
bigger = 0;
smaller = 0;
a1 = 0;
a2 = 0;
a3 = 0;
a4 = 0;
b1 = 0;
b2 = 0;
b3 = 0;
b4 = 0;
numa = 0;
numb = 0;
turn = 0;
end
always @(posedge I1 or posedge I2 or posedge I3 or posedge I4 or posedge enter or posedge reset) begin
if(I1) begin
nums = 0;
nums[0] = 1;
if(runa) begin
a1[numa] = 1;
numa = numa + 1;
end
if(runb) begin
b1[numb] = 1;
numb=numb + 1;
end
end
else if(I2) begin
nums = 0;
nums[1] = 1;
if(runa) begin
a2[numa] = 1;
numa=numa+1;
end
if(runb) begin
b2[numb] = 1;
numb=numb+1;
end
end
else if(I3) begin
nums = 0;
nums[2] = 1;
if(runa) begin
a3[numa] = 1;
numa=numa+1;
end
if(runb) begin
b3[numb] = 1;
numb=numb+1;
end
end
else if(I4) begin
nums = 0;
nums[3] = 1;
if(runa) begin
a4[numa] = 1;
numa=numa+1;
end
if(runb) begin
b4[numb] = 1;
numb=numb+1;
end
end
else if(enter) begin
if(numa >=4) begin
runa = 0;
runb = 1;
end
else if(numa < 4) begin
a1 = 0;
a2 = 0;
a3 = 0;
a4 = 0;
numa = 0;
end
if(numb >=4) begin
suc = (a1~^b1)&(a2~^b2)&(a3~^b3)&(a4~^b4);
win = suc[0]&suc[1]&suc[2]&suc[3]&suc[4]&suc[5]&suc[6];
if(!win && turn <3) begin
turn=turn+1;
b1=0;
b2=0;
b3=0;
b4=0;
end
if(numb > numa) begin
smaller = 1;
bigger = 0;
equal = 0;
end
if(numb == numa) begin
smaller = 0;
bigger = 0;
equal = 1;
end
if(numb < numa) begin
smaller = 0;
bigger = 1;
equal = 0;
end
numb = 0;
end
if(!win && turn >= 3)
lose = 1;
end
else if(reset) begin
win = 0;
suc = 0;
runa = 1;
runb = 0;
lose = 0;
equal = 0;
bigger = 0;
smaller = 0;
nums = 0;
a1 = 0;
a2 = 0;
a3 = 0;
a4 = 0;
b1 = 0;
b2 = 0;
b3 = 0;
b4 = 0;
numa = 0;
numb = 0;
turn = 0;
end
else begin
if(numa == 7) begin
runa = 0;
runb = 1;
end
if(numb == 7)
runb = 0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21OI_SYMBOL_V
`define SKY130_FD_SC_HDLL__A21OI_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21OI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DECAP_6_V
`define SKY130_FD_SC_HDLL__DECAP_6_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 6 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__decap_6 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__decap_6 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DECAP_6_V
|
// Single-Port BRAM with Byte-wide Write Enable
// Read-First mode
// Single-process description
// Compact description of the write with a generate-for
// statement
// Column width and number of columns easily configurable
//
// bytewrite_ram_32bits.v
//
// `timescale 1ns/1ps
module bytewrite_ram_32bits (clk, we, addr, din, dout);
parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;
parameter filename = "code.hex";
localparam COL_WIDTH = 8;
localparam NB_COL = 4;
input clk;
input [NB_COL-1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [NB_COL*COL_WIDTH-1:0] din;
output [NB_COL*COL_WIDTH-1:0] dout;
reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
integer _i;
wire [ADDR_WIDTH-1:0] addr_dly;
reg [NB_COL*COL_WIDTH-1:0] dout_int;
initial begin
`ifndef NO_RAM_INIT
$readmemh(filename,RAM);
`endif
// #10;
// // Just for debugging readmemh in case it does not work as expected
// for(_i=0;_i<6;_i=_i+1) begin
// $display("idx : %d data : %x",_i,RAM[_i]);
// end
// $display("======================");
end
always @(posedge clk)
begin
dout_int <= RAM[addr];
// $display("%t -D- reading code rom : addr %x ",$realtime,addr);
end
// assign #60 dout = dout_int;
assign dout = dout_int;
// Remove the original generate statement to ease Xilinx memory bitstream patching
always @(posedge clk) begin
if (we[0]) begin
// $display("-I Write to address %x , data %x (%t)",addr,din,$realtime);
RAM[addr][(0+1)*COL_WIDTH-1:0*COL_WIDTH] <= din[(0+1)*COL_WIDTH-1:0*COL_WIDTH];
end
end
always @(posedge clk) begin
if (we[1])
RAM[addr][(1+1)*COL_WIDTH-1:1*COL_WIDTH] <= din[(1+1)*COL_WIDTH-1:1*COL_WIDTH];
end
always @(posedge clk) begin
if (we[2])
RAM[addr][(2+1)*COL_WIDTH-1:2*COL_WIDTH] <= din[(2+1)*COL_WIDTH-1:2*COL_WIDTH];
end
always @(posedge clk) begin
if (we[3])
RAM[addr][(3+1)*COL_WIDTH-1:3*COL_WIDTH] <= din[(3+1)*COL_WIDTH-1:3*COL_WIDTH];
end
endmodule
|
/// date: 2016/2/24
/// engineer: ZhaiShaoMIn
/// module name: fsm_download_flit(from IN_local fifos)
/// fsm for controlling datapath from IN_local to the regs
/// used to process rep msgs and req msgs.
module FSM_download_flit(
//input
req_flit,
req_rdy,
rep_flit,
rep_rdy,
clk,
rst,
cache_rst,
//output
en_deq_req,
en_deq_rep,
rf_rdy_for_cache_out,
head_flit,
addrHI_flit,
addrLO_flit,
data1HI_flit,
data1LO_flit,
data2HI_flit,
data2LO_flit,
data3HI_flit,
data3LO_flit,
data4HI_flit,
data4LO_flit
);
//input
input [17:0] req_flit; // with ctrl (2 bits)
input req_rdy;
input [17:0] rep_flit; // with ctrl (2 bits)
input rep_rdy;
input clk;
input rst;
input cache_rst;
//output
output en_deq_req;
output en_deq_rep;
output rf_rdy_for_cache_out;
output [15:0] head_flit;
output [15:0] addrHI_flit;
output [15:0] addrLO_flit;
output [15:0] data1HI_flit;
output [15:0] data1LO_flit;
output [15:0] data2HI_flit;
output [15:0] data2LO_flit;
output [15:0] data3HI_flit;
output [15:0] data3LO_flit;
output [15:0] data4HI_flit;
output [15:0] data4LO_flit;
//wires for interconnection
wire [1:0] ctrl_rep;
wire [1:0] ctrl_req;
assign ctrl_rep=rep_flit[17:16];
assign ctrl_req=req_flit[17:16];
//arbitration
wire tCbusy;
wire req_cacheORhome;
wire rep_cacheORhome;
assign req_cacheORhome=req_flit[13];
assign rep_cacheORhome=rep_flit[13];
//fake regs
reg deq_rep_on;
reg deq_req_on;
always@(tCbusy or rep_rdy or req_rdy or req_cacheORhome or rep_cacheORhome or ctrl)
begin
if(~tCbusy&&rep_rdy&&~rep_cacheORhome&&(ctrl_rep==2'b01))
begin
deq_rep_on=1;
deq_req_on=0;
end
else if(~tCbusy&&req_rdy&&~req_cacheORhome&&(ctrl_req==2'b01))
begin
deq_rep_on=0;
deq_req_on=1;
end
else
begin
deq_rep_on=0;
deq_req_on=0;
end
//defult: signals
deq_req_on=0;
deq_rep_on=0;
end
//parameters
parameter idle=3'b000;
parameter load_req=3'b001;
parameter load_rep=3'b101;
parameter wait_req=3'b010;
parameter wait_rep=3'b110;
//FSM
reg [2:0] rstate;
reg [2:0] nstate;
reg en_deq_req;
reg en_deq_rep;
reg en_load;
reg en_cnt;
reg rst_cnt;
reg en_read_all;
reg C_busy;
// generate flit to flit registers
wire [17:0] temp_flit;
wire [15:0] flit;
wire [1:0] ctrl;
assign temp_flit=en_deq_rep?rep_flit:req_flit;
assign ctrl=temp_flit[17:16];
assign flit=temp_flit[15:0];
always@(deq_rep_on or deq_req_on or rep_rdy or req_rdy or ctrl )
begin
//defult value for all signals !//
/*no state change by default*/
nstate=rstate;
en_deq_req=1'b0;
en_deq_rep=1'b0;
en_load=1'b0;
en_cnt=1'b0;
rst_cnt=1'b0;
en_read_all=1'b0;
case(rstate)
idle:
begin
if(deq_rep_on|deq_req_on)
begin
C_busy=1;
rst_cnt=1;
if(deq_rep_on)
nstate=load_rep;
else
nstate=load_req;
end
end
load_req:
begin
if(req_rdy==1'b0)
begin
nstate=wait_req;
end
else if(ctrl!=2'b11)
begin
en_deq_req=1'b1;
en_cnt=1'b1;
en_load=1'b1;
end
else if(ctrl==2'b11)
begin
nstate=idle;
en_read_all=1'b1;
end
end
wait_req:
begin
if(req_rdy==1'b1)
begin
if(ctrl==2'b11)
begin
nstate=idle;
en_read_all=1'b1;
end
else
begin
nstate=load_req;
end
en_deq_req=1'b1;
en_load=1'b1;
en_cnt=1'b1;
end
end
load_rep:
begin
if(rep_rdy==1'b0)
begin
nstate=wait_rep;
end
else if(ctrl!=2'b11)
begin
en_deq_rep=1'b1;
en_cnt=1'b1;
en_load=1'b1;
end
else if(ctrl==2'b11)
begin
nstate=idle;
en_load=1'b1;
en_deq_rep=1'b1;
en_read_all=1'b1;
end
end
wait_rep:
begin
if(rep_rdy==1'b1)
begin
if(ctrl==2'b11)
begin
nstate=idle;
en_read_all=1'b1;
end
else
begin
nstate=load_rep;
end
en_deq_rep=1'b1;
en_cnt=1'b1;
en_load=1'b1;
end
end
endcase
end
//counter for write address to flit regs
reg [3:0] cnt;
always@(posedge clk)
begin
if(rst_cnt|rst)
cnt<=4'b0000;
else if(en_cnt)
cnt<=cnt+1'b1;
else
cnt<=cnt;
end
//wire [3:0] cnt_sel;
//assign cnt_sel=cnt;
//Cache_busy register
reg Cbusy;
always@(posedge clk)
begin
if(rst==1'b0|cache_rst==1'b1)
Cbusy<=1'b0;
else if(C_busy==1'b1)
Cbusy<=1'b1;
else
Cbusy<=Cbusy;
end
assign tCbusy=Cbusy;
// reg indicate flit regs are ready!
reg rf_rdy_for_cache;
always@(posedge clk)
begin
if(rst==1'b0|cache_rst==1'b1)
rf_rdy_for_cache<=1'b0;
else if(C_busy==1'b1)
rf_rdy_for_cache<=1'b1;
else
rf_rdy_for_cache<=rf_rdy_for_cache;
end
wire rf_rdy_for_cache_out; //IN_local flit regs busy output!
assign rf_rdy_for_cache_out=rf_rdy_for_cache;
//FSM reg
always @(posedge clk)
begin
if (rst)
rstate <= idle; //reset to idle state
else
rstate <= nstate;
end
// instance of flit regfile
SP_rf_LUT_RAM #(11,16,4) flit_regs (
.clk(clk),
.we(en_load),
.wa(cnt),
.di(flit),
.re(en_read_all),
// .flit_rdy(flit_rdy_out),
.do0(head_flit),
.do1(addrHI_flit),
.do2(addrLO_flit),
.do3(data1HI_flit),
.do4(data1LO_flit),
.do5(data2HI_flit),
.do6(data2LO_flit),
.do7(data3HI_flit),
.do8(data3LO_flit),
.do9(data4HI_flit),
.do10(data4LO_flit)
);
endmodule
|
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY CONFIGURATION REGISTER
########################################################################
-------------------------------------------------------------
ESYSRESET ***Elink reset***
[0] 0 - elink active
1 - elink in reset
-------------------------------------------------------------
ESYSCFGTX ***Elink transmitter configuration***
[0] 0 - link TX disable
1 - link TX enable
[1] 0 - normal pass through transaction mode
1 - mmu mode
[3:2] 00 - normal mode
01 - gpio mode
10 - reserved
11 - reserved
[7:4] Transmit control mode for eMesh
[11:8] 0000 - No division, full speed
0001 - Divide by 2
Others - Reserved
-------------------------------------------------------------
ESYSCFGRX ***Elink receiver configuration***
[0] 0 - link RX disable
1 - link RX enable
[1] 0 - normal transaction mode
1 - mmu mode
[3:2] 00 - normal mode
01 - GPIO mode (drive rd wait pins from registers)
10 - loopback mode (loops TX-->RX)
11 - reserved
[4] 0 - set monitor to count traffic
1 - set monitor to count congestion
-------------------------------------------------------------
ESYSCFGCLK ***Epiphany clock frequency setting***
[3:0] Output divider
0000 - Clock turned off
0001 - CLKIN/64
0010 - CLKIN/32
0011 - CLKIN/16
0100 - CLKIN/8
0101 - CLKIN/4
0110 - CLKIN/2
0111 - CLKIN/1 (full speed)
1XXX - RESERVED
[7:4] PLL settings (TBD)
-------------------------------------------------------------
ESYSCOREID ***CORE ID***
[5:0] Column ID-->default at powerup/reset
[11:6] Row ID
-------------------------------------------------------------
ESYSVERSION ***Version number (read only)***
[7:0] Revision #, incremented in each change (match git?)
[15:8] Type (features included in FPGA load, same board)
[23:16] Board platform #
[31:24] Generation # (needed??)
-------------------------------------------------------------
ESYSDATAIN ***Data on elink input pins
[7:0] rx_data[7:0]
[8] tx_frame
[9] tx_wait_rd
[10] tx_wait_wr
-------------------------------------------------------------
ESYSDATAOUT ***Data on eLink output pins
[7:0] tx_data[7:0]
[8] tx_frame
[9] rx_wait_rd
[10] rx_wait_wr
########################################################################
*/
// These are WORD addresses
`define E_REG_SYSRESET 10'h010
`define E_REG_SYSCFGTX 10'h011
`define E_REG_SYSCFGRX 10'h012
`define E_REG_SYSCFGCLK 10'h013
`define E_REG_SYSCOREID 10'h014
`define E_REG_SYSVERSION 10'h015
`define E_REG_SYSDATAIN 10'h016
`define E_REG_SYSDATAOUT 10'h017
module ecfg (/*AUTOARG*/
// Outputs
mi_dout, ecfg_sw_reset, ecfg_reset, ecfg_tx_enable,
ecfg_tx_mmu_mode, ecfg_tx_gpio_mode, ecfg_tx_ctrl_mode,
ecfg_tx_clkdiv, ecfg_rx_enable, ecfg_rx_mmu_mode,
ecfg_rx_gpio_mode, ecfg_rx_loopback_mode, ecfg_cclk_en,
ecfg_cclk_div, ecfg_cclk_pllcfg, ecfg_coreid, ecfg_dataout,
// Inputs
mi_clk, mi_rst, mi_en, mi_we, mi_addr, mi_din, hw_reset,
ecfg_datain
);
//Register file parameters
/***************************/
/* COMPILE TIME PARAMETERS */
/***************************/
parameter E_VERSION = 32'h00_00_00_00; // FPGA gen:plat:type:rev
parameter IDW = 12; // Elink ID (row,column coordinate)
parameter RFAW = 12; // Register file address width
// NB: The BRAM interface seems to provide BYTE addresses!
parameter DEF_COREID = 12'h808; // Reset value for ecfg_coreid
/*****************************/
/*SIMPLE MEMORY INTERFACE */
/*****************************/
input mi_clk;
input mi_rst; // Not used
input mi_en;
input mi_we; // Single WE, must write full words!
input [RFAW-1:0] mi_addr;
input [31:0] mi_din;
output [31:0] mi_dout;
input hw_reset;
/*****************************/
/*ELINK CONTROL SIGNALS */
/*****************************/
//RESET
output ecfg_sw_reset;
output ecfg_reset;
//tx
output ecfg_tx_enable; //enable signal for TX
output ecfg_tx_mmu_mode; //enables MMU on transnmit path
output ecfg_tx_gpio_mode; //forces TX output pins to constants
output [3:0] ecfg_tx_ctrl_mode; //value for emesh ctrlmode tag
output [3:0] ecfg_tx_clkdiv; //transmit clock divider
//rx
output ecfg_rx_enable; //enable signal for rx
output ecfg_rx_mmu_mode; //enables MMU on rx path
output ecfg_rx_gpio_mode; //forces rx wait pins to constants
output ecfg_rx_loopback_mode; //loops back tx to rx receiver (after serdes)
//cclk
output ecfg_cclk_en; //cclk enable
output [3:0] ecfg_cclk_div; //cclk divider setting
output [3:0] ecfg_cclk_pllcfg; //pll configuration
//coreid
output [11:0] ecfg_coreid; //core-id of fpga elink
//gpio
input [10:0] ecfg_datain; // data from elink inputs
output [10:0] ecfg_dataout; //data for elink outputs {rd_wait,wr_wait,frame,data[7:0]}
/*------------------------BODY CODE---------------------------------------*/
//registers
reg [11:0] ecfg_cfgtx_reg;
reg [4:0] ecfg_cfgrx_reg;
reg [7:0] ecfg_cfgclk_reg;
reg [11:0] ecfg_coreid_reg;
reg ecfg_reset_reg;
reg [11:0] ecfg_datain_reg;
reg [11:0] ecfg_dataout_reg;
reg [31:0] mi_dout;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_reset_match;
wire ecfg_cfgtx_match;
wire ecfg_cfgrx_match;
wire ecfg_cfgclk_match;
wire ecfg_coreid_match;
wire ecfg_datain_match;
wire ecfg_dataout_match;
wire ecfg_match;
wire ecfg_regmux;
wire [31:0] ecfg_reg_mux;
wire ecfg_cfgtx_write;
wire ecfg_cfgrx_write;
wire ecfg_cfgclk_write;
wire ecfg_coreid_write;
wire ecfg_dataout_write;
wire ecfg_rx_monitor_mode;
wire ecfg_reset_write;
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//address match signals
assign ecfg_reset_match = mi_addr[RFAW-1:2]==`E_REG_SYSRESET;
assign ecfg_cfgtx_match = mi_addr[RFAW-1:2]==`E_REG_SYSCFGTX;
assign ecfg_cfgrx_match = mi_addr[RFAW-1:2]==`E_REG_SYSCFGRX;
assign ecfg_cfgclk_match = mi_addr[RFAW-1:2]==`E_REG_SYSCFGCLK;
assign ecfg_coreid_match = mi_addr[RFAW-1:2]==`E_REG_SYSCOREID;
assign ecfg_version_match = mi_addr[RFAW-1:2]==`E_REG_SYSVERSION;
assign ecfg_datain_match = mi_addr[RFAW-1:2]==`E_REG_SYSDATAIN;
assign ecfg_dataout_match = mi_addr[RFAW-1:2]==`E_REG_SYSDATAOUT;
assign ecfg_match = ecfg_reset_match |
ecfg_cfgtx_match |
ecfg_cfgrx_match |
ecfg_cfgclk_match |
ecfg_coreid_match |
ecfg_version_match |
ecfg_datain_match |
ecfg_dataout_match;
//Write enables
assign ecfg_reset_write = ecfg_reset_match & ecfg_write;
assign ecfg_cfgtx_write = ecfg_cfgtx_match & ecfg_write;
assign ecfg_cfgrx_write = ecfg_cfgrx_match & ecfg_write;
assign ecfg_cfgclk_write = ecfg_cfgclk_match & ecfg_write;
assign ecfg_coreid_write = ecfg_coreid_match & ecfg_write;
assign ecfg_dataout_write = ecfg_dataout_match & ecfg_write;
//###########################
//# ESYSCFGTX
//###########################
always @ (posedge mi_clk)
if(hw_reset)
ecfg_cfgtx_reg[11:0] <= 12'b0;
else if (ecfg_cfgtx_write)
ecfg_cfgtx_reg[11:0] <= mi_din[11:0];
assign ecfg_tx_enable = ecfg_cfgtx_reg[0];
assign ecfg_tx_mmu_mode = ecfg_cfgtx_reg[1];
assign ecfg_tx_gpio_mode = ecfg_cfgtx_reg[3:2]==2'b01;
assign ecfg_tx_ctrl_mode[3:0] = ecfg_cfgtx_reg[7:4];
assign ecfg_tx_clkdiv[3:0] = ecfg_cfgtx_reg[11:8];
//###########################
//# ESYSCFGRX
//###########################
always @ (posedge mi_clk)
if(hw_reset)
ecfg_cfgrx_reg[4:0] <= 5'b0;
else if (ecfg_cfgrx_write)
ecfg_cfgrx_reg[4:0] <= mi_din[4:0];
assign ecfg_rx_enable = ecfg_cfgrx_reg[0];
assign ecfg_rx_mmu_mode = ecfg_cfgrx_reg[1];
assign ecfg_rx_gpio_mode = ecfg_cfgrx_reg[3:2]==2'b01;
assign ecfg_rx_loopback_mode = ecfg_cfgrx_reg[3:2]==2'b10;
assign ecfg_rx_monitor_mode = ecfg_cfgrx_reg[4];
//###########################
//# ESYSCFGCLK
//###########################
always @ (posedge mi_clk)
if(hw_reset)
ecfg_cfgclk_reg[7:0] <= 8'b0;
else if (ecfg_cfgclk_write)
ecfg_cfgclk_reg[7:0] <= mi_din[7:0];
assign ecfg_cclk_en = ~(ecfg_cfgclk_reg[3:0]==4'b0000);
assign ecfg_cclk_div[3:0] = ecfg_cfgclk_reg[3:0];
assign ecfg_cclk_pllcfg[3:0] = ecfg_cfgclk_reg[7:4];
//###########################
//# ESYSCOREID
//###########################
always @ (posedge mi_clk)
if(hw_reset)
ecfg_coreid_reg[IDW-1:0] <= DEF_COREID;
else if (ecfg_coreid_write)
ecfg_coreid_reg[IDW-1:0] <= mi_din[IDW-1:0];
assign ecfg_coreid[IDW-1:0] = ecfg_coreid_reg[IDW-1:0];
//###########################
//# ESYSDATAIN
//###########################
always @ (posedge mi_clk)
ecfg_datain_reg <= ecfg_datain;
//###########################
//# ESYSDATAOUT
//###########################
always @ (posedge mi_clk)
if(hw_reset)
ecfg_dataout_reg <= 'd0;
else if (ecfg_dataout_write)
ecfg_dataout_reg <= mi_din[10:0];
assign ecfg_dataout[10:0] = ecfg_dataout_reg[10:0];
//###########################
//# ESYSRESET
//###########################
always @ (posedge mi_clk)
if(hw_reset)
ecfg_reset_reg <= 1'b0;
else if (ecfg_reset_write)
ecfg_reset_reg <= mi_din[0];
assign ecfg_sw_reset = ecfg_reset_reg;
assign ecfg_reset = ecfg_sw_reset | hw_reset;
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge mi_clk)
if(ecfg_read)
case(mi_addr[RFAW-1:2])
`E_REG_SYSRESET: mi_dout <= {31'b0, ecfg_reset_reg};
`E_REG_SYSCFGTX: mi_dout <= {20'b0, ecfg_cfgtx_reg[11:0]};
`E_REG_SYSCFGRX: mi_dout <= {27'b0, ecfg_cfgrx_reg[4:0]};
`E_REG_SYSCFGCLK: mi_dout <= {24'b0, ecfg_cfgclk_reg[7:0]};
`E_REG_SYSCOREID: mi_dout <= {{(32-IDW){1'b0}}, ecfg_coreid_reg[IDW-1:0]};
`E_REG_SYSVERSION: mi_dout <= E_VERSION;
`E_REG_SYSDATAIN: mi_dout <= {20'b0, ecfg_datain_reg[11:0]};
`E_REG_SYSDATAOUT: mi_dout <= {20'b0, ecfg_dataout_reg[11:0]};
default: mi_dout <= 32'd0;
endcase
endmodule // para_config
|
/* This module manages the control of the bridge. It includes the
* checking of flow control credits and any necessary reset logic.
*/
module bridge_control (
// Inputs to modules
input Ctrl_CLK, // Clock that all things are synchronous to
input Ctrl_RST, // Reset signal from the core block to the bridge
input Ctrl_Link_Up, // Signals Link up of core block with PCIe partner
input [7:0] Ctrl_fc_ph, // Posted Header
input [11:0] Ctrl_fc_pd, // Posted Data
input [7:0] Ctrl_fc_nph, // Non-posted Header
input [11:0] Ctrl_fc_npd, // Non-posted Data
input [7:0] Ctrl_fc_cplh, // Completion Header
input [11:0] Ctrl_fc_cpld, // Completion Data
// Outputs of module
output reg [2:0] Ctrl_fc_sel, // Selection of desired flow control type
output Ctrl_Bridge_RST,// Signals to Bridge that a reset is needed
output [5:0] Ctrl_Tx_FC // Signals for Flow Credits to transmit bridge module
);
// Set reset value for system
// Ctrl_RST (user_reset_out is active high, so it is asserted when
// a reset is required. Therefore, we will use active low for all
// module resets so the reset in the control module will just be
// inverted. Also reset will be connected to the user_lnk_up signal.
assign Ctrl_Bridge_RST = ~Ctrl_RST & Ctrl_Link_Up;
// Set up all of the buffer values for processing packets
// Control should signal that it is not ok to transmit a given packet
// type once less than one maximum size packet can fit.
always begin
if (Ctrl_fc_ph [7:5] == 0) Ctrl_Tx_FC[0] <= 0;
else Ctrl_Tx_FC[0] <= 1;
if (Ctrl_fc_ph[11:10] == 0) Ctrl_Tx_FC[1] <= 0;
else Ctrl_Tx_FC[1] <= 1;
if (Ctrl_fc_nph[7:5] == 0) Ctrl_Tx_FC[2] <= 0;
else Ctrl_Tx_FC[2] <= 1;
if (Ctrl_fc_npd[11:10] == 0) Ctrl_Tx_FC[3] <= 0;
else Ctrl_Tx_FC[3] <= 1;
if (Ctrl_fc_cplh[7:5] == 0) Ctrl_Tx_FC[4] <= 0;
else Ctrl_Tx_FC[4] <= 1;
if (Ctrl_fc_cpld[11:10] == 0) Ctrl_Tx_FC[5] <= 0;
else Ctrl_Tx_FC[5] <= 1;
end
// Initialize Flow Credit Select register
initial begin
Ctrl_fc_sel = 3'b100; // Set to request Tx available buffer space
end
end module
|
`timescale 1ns / 1ps
//----------------------------------------------------------
//Copyright (c) 2016, Xilinx, Inc.
//All rights reserved.
//
//Redistribution and use in source and binary forms, with or without modification,
//are permitted provided that the following conditions are met:
//
//1. Redistributions of source code must retain the above copyright notice,
//this list of conditions and the following disclaimer.
//
//2. Redistributions in binary form must reproduce the above copyright notice,
//this list of conditions and the following disclaimer in the documentation
//and/or other materials provided with the distribution.
//
//3. Neither the name of the copyright holder nor the names of its contributors
//may be used to endorse or promote products derived from this software
//without specific prior written permission.
//
//THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
//ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
//THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
//INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
//PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
//HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
//OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
//EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//----------------------------------------------------------
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.08.2013 15:05:03
// Design Name:
// Module Name: vc709_10g_interface
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vc709_10g_interface(
// 200MHz reference clock input
input clk_ref_p,
input clk_ref_n,
input reset,
input aresetn,
//-SI5324 I2C programming interface
inout i2c_clk,
inout i2c_data,
output i2c_mux_rst_n,
output si5324_rst_n,
// 156.25 MHz clock in
input xphy_refclk_p,
input xphy_refclk_n,
output xphy0_txp,
output xphy0_txn,
input xphy0_rxp,
input xphy0_rxn,
output xphy1_txp,
output xphy1_txn,
input xphy1_rxp,
input xphy1_rxn,
output xphy2_txp,
output xphy2_txn,
input xphy2_rxp,
input xphy2_rxn,
output xphy3_txp,
output xphy3_txn,
input xphy3_rxp,
input xphy3_rxn,
output[63:0] axis_i_0_tdata,
output axis_i_0_tvalid,
output axis_i_0_tlast,
output axis_i_0_tuser,
output[7:0] axis_i_0_tkeep,
input axis_i_0_tready,
input[63:0] axis_o_0_tdata,
input axis_o_0_tvalid,
input axis_o_0_tlast,
input axis_o_0_tuser,
input[7:0] axis_o_0_tkeep,
output axis_o_0_tready,
/*
output[63:0] axis_i_1_tdata,
output axis_i_1_tvalid,
output axis_i_1_tlast,
output axis_i_1_tuser,
output[7:0] axis_i_1_tkeep,
input axis_i_1_tready,
input[63:0] axis_o_1_tdata,
input axis_o_1_tvalid,
input axis_o_1_tlast,
input axis_o_1_tuser,
input[7:0] axis_o_1_tkeep,
output axis_o_1_tready,
*/
output[3:0] sfp_tx_disable,
output clk156_out,
output clk_ref_200_out,
output network_reset_done,
output [7:0] led
);
wire clk_ref_200;
wire clk_ref_200_i;
wire[7:0] core0_status;
wire[7:0] core1_status;
wire[7:0] core2_status;
wire[7:0] core3_status;
// Shared clk signals
wire gt_txclk322;
wire gt_txusrclk;
wire gt_txusrclk2;
wire gt_qplllock;
wire gt_gpllrefclklost;
wire gt_gplloutrefclk;
wire gt_gplllock_txusrclk2;
wire gttxreset_txusrclk2;
wire gt_txuserrdy;
wire tx_fault;
wire core_reset;
wire gt0_tx_resetdone;
wire gt1_tx_resetdone;
wire gt2_tx_resetdone;
wire gt3_tx_resetdone;
wire areset_clk_156_25_bufh;
wire areset_clk_156_25;
wire mmcm_locked_clk156;
wire reset_counter_done;
wire gttxreset;
wire gtrxreset;
wire clk156_25;
wire dclk_i;
wire xphyrefclk_i;
assign network_reset_done = ~core_reset;
/*wire[63:0] axis_i_0_tdata;
wire axis_i_0_tvalid;
wire axis_i_0_tlast;
wire axis_i_0_tuser;
wire[7:0] axis_i_0_tkeep;
wire axis_i_0_tready;
wire[63:0] axis_o_0_tdata;
wire axis_o_0_tvalid;
wire axis_o_0_tlast;
//wire axis_o_0_tuser;
wire[7:0] axis_o_0_tkeep;
wire axis_o_0_tready;*/
wire[63:0] axis_i_1_tdata;
wire axis_i_1_tvalid;
wire axis_i_1_tlast;
wire axis_i_1_tuser;
wire[7:0] axis_i_1_tkeep;
wire axis_i_1_tready;
wire[63:0] axis_o_1_tdata;
wire axis_o_1_tvalid;
wire axis_o_1_tlast;
//wire axis_o_1_tuser;
wire[7:0] axis_o_1_tkeep;
wire axis_o_1_tready;
/**/
wire[63:0] axis_i_2_tdata;
wire axis_i_2_tvalid;
wire axis_i_2_tlast;
wire axis_i_2_tuser;
wire[7:0] axis_i_2_tkeep;
wire axis_i_2_tready;
wire[63:0] axis_o_2_tdata;
wire axis_o_2_tvalid;
wire axis_o_2_tlast;
//wire axis_o_2_tuser;
wire[7:0] axis_o_2_tkeep;
wire axis_o_2_tready;
wire[63:0] axis_i_3_tdata;
wire axis_i_3_tvalid;
wire axis_i_3_tlast;
wire axis_i_3_tuser;
wire[7:0] axis_i_3_tkeep;
wire axis_i_3_tready;
wire[63:0] axis_o_3_tdata;
wire axis_o_3_tvalid;
wire axis_o_3_tlast;
//wire axis_o_3_tuser;
wire[7:0] axis_o_3_tkeep;
wire axis_o_3_tready;
assign clk156_out = clk156_25;
assign clk_ref_200_out = clk_ref_200;
/*
* Clocks
*/
// 200mhz ref clk
IBUFGDS #(
.DIFF_TERM ("TRUE"),
.IBUF_LOW_PWR ("FALSE")
) diff_clk_200 (
.I (clk_ref_p ),
.IB (clk_ref_n ),
.O (clk_ref_200_i )
);
BUFG u_bufg_clk_ref
(
.O (clk_ref_200),
.I (clk_ref_200_i)
);
// 50mhz clk
wire clk50;
reg [1:0] clk_divide = 2'b00;
always @(posedge clk_ref_200)
clk_divide <= clk_divide + 1'b1;
BUFG buffer_clk50 (
.I (clk_divide[1]),
.O (clk50 )
);
//-SI 5324 programming
clock_control cc_inst (
.i2c_clk (i2c_clk ),
.i2c_data (i2c_data ),
.i2c_mux_rst_n (i2c_mux_rst_n ),
.si5324_rst_n (si5324_rst_n ),
.rst (reset ),
.clk50 (clk50 )
);
/*
* Network modules
*/
wire[7:0] tx_ifg_delay;
wire signal_detect;
//wire tx_fault;
assign tx_ifg_delay = 8'h00;
assign signal_detect = 1'b1;
//assign tx_fault = 1'b0;
network_module network_inst_0
(
.clk156 (clk156_25),
.reset(reset),
.aresetn(aresetn),
.dclk (dclk_i),
.txusrclk (gt_txusrclk),
.txusrclk2 (gt_txusrclk2),
.txclk322 (gt_txclk322),
.areset_refclk_bufh (areset_clk_156_25_bufh),
.areset_clk156 (areset_clk_156_25),
.mmcm_locked_clk156 (mmcm_locked_clk156),
.gttxreset_txusrclk2 (gttxreset_txusrclk2),
.gttxreset (gttxreset),
.gtrxreset (gtrxreset),
.txuserrdy (gt_txuserrdy),
.qplllock (gt_qplllock),
.qplloutclk (gt_qplloutclk),
.qplloutrefclk (gt_qplloutrefclk),
.reset_counter_done (reset_counter_done),
.tx_resetdone (gt0_tx_resetdone),
.txp(xphy0_txp),
.txn(xphy0_txn),
.rxp(xphy0_rxp),
.rxn(xphy0_rxn),
.tx_axis_tdata(axis_o_0_tdata),
.tx_axis_tvalid(axis_o_0_tvalid),
.tx_axis_tlast(axis_o_0_tlast),
.tx_axis_tuser(1'b0),
.tx_axis_tkeep(axis_o_0_tkeep),
.tx_axis_tready(axis_o_0_tready),
.rx_axis_tdata(axis_i_0_tdata),
.rx_axis_tvalid(axis_i_0_tvalid),
.rx_axis_tuser(axis_i_0_tuser),
.rx_axis_tlast(axis_i_0_tlast),
.rx_axis_tkeep(axis_i_0_tkeep),
.rx_axis_tready(axis_i_0_tready),
.core_reset(core_reset),
.tx_fault(tx_fault),
.signal_detect(signal_detect),
.tx_ifg_delay(tx_ifg_delay),
.tx_disable(),
.core_status(core0_status)
);
//assign axis_o_0_tdata = axis_i_0_tdata;
///assign axis_o_0_tvalid = axis_i_0_tvalid;
//assign axis_o_0_tkeep = axis_i_0_tkeep;
//assign axis_o_0_tlast = axis_i_0_tlast;
//assign axis_o_0_tuser <= ;
//assign axis_i_0_tready = axis_o_0_tready;
/*
network_module network_inst_1
(
.clk156 (clk156_25),
.reset(reset),
.dclk (dclk_i),
.txusrclk (gt_txusrclk),
.txusrclk2 (gt_txusrclk2),
.txclk322 (gt_txclk322),
.areset_refclk_bufh (areset_clk_156_25_bufh),
.areset_clk156 (areset_clk_156_25),
.mmcm_locked_clk156 (mmcm_locked_clk156),
.gttxreset_txusrclk2 (gttxreset_txusrclk2),
.gttxreset (gttxreset),
.gtrxreset (gtrxreset),
.txuserrdy (gt_txuserrdy),
.qplllock (gt_qplllock),
.qplloutclk (gt_qplloutclk),
.qplloutrefclk (gt_qplloutrefclk),
.reset_counter_done (reset_counter_done),
.tx_resetdone (gt1_tx_resetdone),
.txp(xphy1_txp),
.txn(xphy1_txn),
.rxp(xphy1_rxp),
.rxn(xphy1_rxn),
.tx_axis_tdata(axis_o_1_tdata),
.tx_axis_tvalid(axis_o_1_tvalid),
.tx_axis_tlast(axis_o_1_tlast),
.tx_axis_tuser(1'b0),
.tx_axis_tkeep(axis_o_1_tkeep),
.tx_axis_tready(axis_o_1_tready),
.rx_axis_tdata(axis_i_1_tdata),
.rx_axis_tvalid(axis_i_1_tvalid),
.rx_axis_tuser(axis_i_1_tuser),
.rx_axis_tlast(axis_i_1_tlast),
.rx_axis_tkeep(axis_i_1_tkeep),
.rx_axis_tready(axis_i_1_tready),
.core_reset(core_reset),
.tx_fault(tx_fault),
.signal_detect(signal_detect),
.tx_ifg_delay(tx_ifg_delay),
.tx_disable(),
.core_status(core1_status)
);
assign axis_o_1_tdata = axis_i_1_tdata;
assign axis_o_1_tvalid = axis_i_1_tvalid;
assign axis_o_1_tkeep = axis_i_1_tkeep;
assign axis_o_1_tlast = axis_i_1_tlast;
//assign axis_o_0_tuser <= ;
assign axis_i_1_tready = axis_o_1_tready;
/*
network_module network_inst_2
(
.clk156 (clk156_25),
.reset(reset),
.dclk (dclk_i),
.txusrclk (gt_txusrclk),
.txusrclk2 (gt_txusrclk2),
.txclk322 (),
.areset_refclk_bufh (areset_clk_156_25_bufh),
.areset_clk156 (areset_clk_156_25),
.mmcm_locked_clk156 (mmcm_locked_clk156),
.gttxreset_txusrclk2 (gttxreset_txusrclk2),
.gttxreset (gttxreset),
.gtrxreset (gtrxreset),
.txuserrdy (gt_txuserrdy),
.qplllock (gt_qplllock),
.qplloutclk (gt_qplloutclk),
.qplloutrefclk (gt_qplloutrefclk),
.reset_counter_done (reset_counter_done),
.tx_resetdone (gt2_tx_resetdone),
.txp(xphy2_txp),
.txn(xphy2_txn),
.rxp(xphy2_rxp),
.rxn(xphy2_rxn),
.tx_axis_tdata(axis_o_2_tdata),
.tx_axis_tvalid(axis_o_2_tvalid),
.tx_axis_tlast(axis_o_2_tlast),
.tx_axis_tuser(1'b0),
.tx_axis_tkeep(axis_o_2_tkeep),
.tx_axis_tready(axis_o_2_tready),
.rx_axis_tdata(axis_i_2_tdata),
.rx_axis_tvalid(axis_i_2_tvalid),
.rx_axis_tuser(axis_i_2_tuser),
.rx_axis_tlast(axis_i_2_tlast),
.rx_axis_tkeep(axis_i_2_tkeep),
.rx_axis_tready(axis_i_2_tready),
.core_reset(core_reset),
.tx_fault(tx_fault),
.signal_detect(signal_detect),
.tx_ifg_delay(tx_ifg_delay),
.tx_disable(),
.core_status(core2_status)
);
network_module network_inst_3
(
.clk156 (clk156_25),
.reset(reset),
.dclk (dclk_i),
.txusrclk (gt_txusrclk),
.txusrclk2 (gt_txusrclk2),
.txclk322 (),
.areset_refclk_bufh (areset_clk_156_25_bufh),
.areset_clk156 (areset_clk_156_25),
.mmcm_locked_clk156 (mmcm_locked_clk156),
.gttxreset_txusrclk2 (gttxreset_txusrclk2),
.gttxreset (gttxreset),
.gtrxreset (gtrxreset),
.txuserrdy (gt_txuserrdy),
.qplllock (gt_qplllock),
.qplloutclk (gt_qplloutclk),
.qplloutrefclk (gt_qplloutrefclk),
.reset_counter_done (reset_counter_done),
.tx_resetdone (gt3_tx_resetdone),
.txp(xphy3_txp),
.txn(xphy3_txn),
.rxp(xphy3_rxp),
.rxn(xphy3_rxn),
.tx_axis_tdata(axis_o_3_tdata),
.tx_axis_tvalid(axis_o_3_tvalid),
.tx_axis_tlast(axis_o_3_tlast),
.tx_axis_tuser(1'b0),
.tx_axis_tkeep(axis_o_3_tkeep),
.tx_axis_tready(axis_o_3_tready),
.rx_axis_tdata(axis_i_3_tdata),
.rx_axis_tvalid(axis_i_3_tvalid),
.rx_axis_tuser(axis_i_3_tuser),
.rx_axis_tlast(axis_i_3_tlast),
.rx_axis_tkeep(axis_i_3_tkeep),
.rx_axis_tready(axis_i_3_tready),
.core_reset(core_reset),
.tx_fault(tx_fault),
.signal_detect(signal_detect),
.tx_ifg_delay(tx_ifg_delay),
.tx_disable(),
.core_status(core3_status)
);
//switch btw 2 & 3
assign axis_o_2_tdata = axis_i_2_tdata;
assign axis_o_2_tvalid = axis_i_2_tvalid;
assign axis_o_2_tkeep = axis_i_2_tkeep;
assign axis_o_2_tlast = axis_i_2_tlast;
//assign axis_o_0_tuser <= ;
assign axis_i_2_tready = axis_o_2_tready;
assign axis_o_3_tdata = axis_i_3_tdata;
assign axis_o_3_tvalid = axis_i_3_tvalid;
assign axis_o_3_tkeep = axis_i_3_tkeep;
assign axis_o_3_tlast = axis_i_3_tlast;
//assign axis_o_0_tuser <= ;
assign axis_i_3_tready = axis_o_3_tready;
*/
//wire xphyrefclk_i;
IBUFDS_GTE2 xgphy_refclk_ibuf (
.I (xphy_refclk_p),
.IB (xphy_refclk_n),
.O (xphyrefclk_i ),
.CEB (1'b0 ),
.ODIV2 ( )
);
assign gt1_tx_resetdone = 1'b1;
assign gt2_tx_resetdone = 1'b1;
assign gt3_tx_resetdone = 1'b1;
xgbaser_gt_same_quad_wrapper #(
.WRAPPER_SIM_GTRESET_SPEEDUP ("TRUE" )
) xgbaser_gt_wrapper_inst (
.gt_txclk322 (gt_txclk322),
.gt_txusrclk (gt_txusrclk),
.gt_txusrclk2 (gt_txusrclk2),
.qplllock (gt_qplllock),
.qpllrefclklost (gt_qpllrefclklost),
.qplloutclk (gt_qplloutclk),
.qplloutrefclk (gt_qplloutrefclk),
.qplllock_txusrclk2 (gt_qplllock_txusrclk2), //not used
.gttxreset_txusrclk2 (gttxreset_txusrclk2),
.txuserrdy (gt_txuserrdy),
.tx_fault (tx_fault),
.core_reset (core_reset),
.gt0_tx_resetdone (gt0_tx_resetdone),
.gt1_tx_resetdone (gt1_tx_resetdone),
.gt2_tx_resetdone (gt2_tx_resetdone),
.gt3_tx_resetdone (gt3_tx_resetdone),
.areset_clk_156_25_bufh (areset_clk_156_25_bufh),
.areset_clk_156_25 (areset_clk_156_25),
.mmcm_locked_clk156 (mmcm_locked_clk156),
.reset_counter_done (reset_counter_done),
.gttxreset (gttxreset),
.gtrxreset (gtrxreset),
.clk156 (clk156_25 ),
.areset (reset),
.dclk (dclk_i ),
.gt_refclk (xphyrefclk_i )
);
assign sfp_tx_disable = 4'b0000;
localparam LED_CTR_WIDTH = 26;
reg [LED_CTR_WIDTH-1:0] l1_ctr;
reg [LED_CTR_WIDTH-1:0] l2_ctr;
always @(posedge clk156_25)
begin
l1_ctr <= l1_ctr + {{(LED_CTR_WIDTH-1){1'b0}}, 1'b1};
end
/*always @(posedge gt_txclk322)
begin
l2_ctr <= l2_ctr + {{(LED_CTR_WIDTH-1){1'b0}}, 1'b1};
end
always @(posedge user_clk2)
begin
l3_ctr <= l3_ctr + {{(LED_CTR_WIDTH-1){1'b0}}, 1'b1};
end
*/
assign led[0] = l1_ctr[LED_CTR_WIDTH-1];
assign led[1] = l2_ctr[LED_CTR_WIDTH-1];
assign led[2] = reset;
assign led[3] = core_reset;
assign led[4] = core0_status[0];
assign led[5] = core1_status[0];
assign led[6] = core2_status[0];
assign led[7] = core3_status[0];
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2011 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(*i $Id: NZDomain.v 13323 2010-07-24 15:57:30Z herbelin $ i*)
Require Export NumPrelude NZAxioms.
Require Import NZBase NZOrder NZAddOrder Plus Minus.
(** In this file, we investigate the shape of domains satisfying
the [NZDomainSig] interface. In particular, we define a
translation from Peano numbers [nat] into NZ.
*)
(** First, a section about iterating a function. *)
Section Iter.
Variable A : Type.
Fixpoint iter (f:A->A)(n:nat) : A -> A := fun a =>
match n with
| O => a
| S n => f (iter f n a)
end.
Infix "^" := iter.
Lemma iter_alt : forall f n m, (f^(Datatypes.S n)) m = (f^n) (f m).
Proof.
induction n; simpl; auto.
intros; rewrite <- IHn; auto.
Qed.
Lemma iter_plus : forall f n n' m, (f^(n+n')) m = (f^n) ((f^n') m).
Proof.
induction n; simpl; auto.
intros; rewrite IHn; auto.
Qed.
Lemma iter_plus_bis : forall f n n' m, (f^(n+n')) m = (f^n') ((f^n) m).
Proof.
induction n; simpl; auto.
intros. rewrite <- iter_alt, IHn; auto.
Qed.
Global Instance iter_wd (R:relation A) : Proper ((R==>R)==>eq==>R==>R) iter.
Proof.
intros f f' Hf n n' Hn; subst n'. induction n; simpl; red; auto.
Qed.
End Iter.
Implicit Arguments iter [A].
Local Infix "^" := iter.
Module NZDomainProp (Import NZ:NZDomainSig').
(** * Relationship between points thanks to [succ] and [pred]. *)
(** We prove that any points in NZ have a common descendant by [succ] *)
Definition common_descendant n m := exists k, exists l, (S^k) n == (S^l) m.
Instance common_descendant_wd : Proper (eq==>eq==>iff) common_descendant.
Proof.
unfold common_descendant. intros n n' Hn m m' Hm.
setoid_rewrite Hn. setoid_rewrite Hm. auto with *.
Qed.
Instance common_descendant_equiv : Equivalence common_descendant.
Proof.
split; red.
intros x. exists O; exists O. simpl; auto with *.
intros x y (p & q & H); exists q; exists p; auto with *.
intros x y z (p & q & Hpq) (r & s & Hrs).
exists (r+p)%nat. exists (q+s)%nat.
rewrite !iter_plus. rewrite Hpq, <-Hrs, <-iter_plus, <- iter_plus_bis.
auto with *.
Qed.
Lemma common_descendant_with_0 : forall n, common_descendant n 0.
Proof.
apply bi_induction.
intros n n' Hn. rewrite Hn; auto with *.
reflexivity.
split; intros (p & q & H).
exists p; exists (Datatypes.S q). rewrite <- iter_alt; simpl.
apply succ_wd; auto.
exists (Datatypes.S p); exists q. rewrite iter_alt; auto.
Qed.
Lemma common_descendant_always : forall n m, common_descendant n m.
Proof.
intros. transitivity 0; [|symmetry]; apply common_descendant_with_0.
Qed.
(** Thanks to [succ] being injective, we can then deduce that for any two
points, one is an iterated successor of the other. *)
Lemma itersucc_or_itersucc : forall n m, exists k, n == (S^k) m \/ m == (S^k) n.
Proof.
intros n m. destruct (common_descendant_always n m) as (k & l & H).
revert l H. induction k.
simpl. intros; exists l; left; auto with *.
intros. destruct l.
simpl in *. exists (Datatypes.S k); right; auto with *.
simpl in *. apply pred_wd in H; rewrite !pred_succ in H. eauto.
Qed.
(** Generalized version of [pred_succ] when iterating *)
Lemma succ_swap_pred : forall k n m, n == (S^k) m -> m == (P^k) n.
Proof.
induction k.
simpl; auto with *.
simpl; intros. apply pred_wd in H. rewrite pred_succ in H. apply IHk in H; auto.
rewrite <- iter_alt in H; auto.
Qed.
(** From a given point, all others are iterated successors
or iterated predecessors. *)
Lemma itersucc_or_iterpred : forall n m, exists k, n == (S^k) m \/ n == (P^k) m.
Proof.
intros n m. destruct (itersucc_or_itersucc n m) as (k,[H|H]).
exists k; left; auto.
exists k; right. apply succ_swap_pred; auto.
Qed.
(** In particular, all points are either iterated successors of [0]
or iterated predecessors of [0] (or both). *)
Lemma itersucc0_or_iterpred0 :
forall n, exists p:nat, n == (S^p) 0 \/ n == (P^p) 0.
Proof.
intros n. exact (itersucc_or_iterpred n 0).
Qed.
(** * Study of initial point w.r.t. [succ] (if any). *)
Definition initial n := forall m, n ~= S m.
Lemma initial_alt : forall n, initial n <-> S (P n) ~= n.
Proof.
split. intros Bn EQ. symmetry in EQ. destruct (Bn _ EQ).
intros NEQ m EQ. apply NEQ. rewrite EQ, pred_succ; auto with *.
Qed.
Lemma initial_alt2 : forall n, initial n <-> ~exists m, n == S m.
Proof. firstorder. Qed.
(** First case: let's assume such an initial point exists
(i.e. [S] isn't surjective)... *)
Section InitialExists.
Hypothesis init : t.
Hypothesis Initial : initial init.
(** ... then we have unicity of this initial point. *)
Lemma initial_unique : forall m, initial m -> m == init.
Proof.
intros m Im. destruct (itersucc_or_itersucc init m) as (p,[H|H]).
destruct p. now simpl in *. destruct (Initial _ H).
destruct p. now simpl in *. destruct (Im _ H).
Qed.
(** ... then all other points are descendant of it. *)
Lemma initial_ancestor : forall m, exists p, m == (S^p) init.
Proof.
intros m. destruct (itersucc_or_itersucc init m) as (p,[H|H]).
destruct p; simpl in *; auto. exists O; auto with *. destruct (Initial _ H).
exists p; auto.
Qed.
(** NB : We would like to have [pred n == n] for the initial element,
but nothing forces that. For instance we can have -3 as initial point,
and P(-3) = 2. A bit odd indeed, but legal according to [NZDomainSig].
We can hence have [n == (P^k) m] without [exists k', m == (S^k') n].
*)
(** We need decidability of [eq] (or classical reasoning) for this: *)
Section SuccPred.
Hypothesis eq_decidable : forall n m, n==m \/ n~=m.
Lemma succ_pred_approx : forall n, ~initial n -> S (P n) == n.
Proof.
intros n NB. rewrite initial_alt in NB.
destruct (eq_decidable (S (P n)) n); auto.
elim NB; auto.
Qed.
End SuccPred.
End InitialExists.
(** Second case : let's suppose now [S] surjective, i.e. no initial point. *)
Section InitialDontExists.
Hypothesis succ_onto : forall n, exists m, n == S m.
Lemma succ_onto_gives_succ_pred : forall n, S (P n) == n.
Proof.
intros n. destruct (succ_onto n) as (m,H). rewrite H, pred_succ; auto with *.
Qed.
Lemma succ_onto_pred_injective : forall n m, P n == P m -> n == m.
Proof.
intros n m. intros H; apply succ_wd in H.
rewrite !succ_onto_gives_succ_pred in H; auto.
Qed.
End InitialDontExists.
(** To summarize:
S is always injective, P is always surjective (thanks to [pred_succ]).
I) If S is not surjective, we have an initial point, which is unique.
This bottom is below zero: we have N shifted (or not) to the left.
P cannot be injective: P init = P (S (P init)).
(P init) can be arbitrary.
II) If S is surjective, we have [forall n, S (P n) = n], S and P are
bijective and reciprocal.
IIa) if [exists k<>O, 0 == S^k 0], then we have a cyclic structure Z/nZ
IIb) otherwise, we have Z
*)
(** * An alternative induction principle using [S] and [P]. *)
(** It is weaker than [bi_induction]. For instance it cannot prove that
we can go from one point by many [S] _or_ many [P], but only by many
[S] mixed with many [P]. Think of a model with two copies of N:
0, 1=S 0, 2=S 1, ...
0', 1'=S 0', 2'=S 1', ...
and P 0 = 0' and P 0' = 0.
*)
Lemma bi_induction_pred :
forall A : t -> Prop, Proper (eq==>iff) A ->
A 0 -> (forall n, A n -> A (S n)) -> (forall n, A n -> A (P n)) ->
forall n, A n.
Proof.
intros. apply bi_induction; auto.
clear n. intros n; split; auto.
intros G; apply H2 in G. rewrite pred_succ in G; auto.
Qed.
Lemma central_induction_pred :
forall A : t -> Prop, Proper (eq==>iff) A -> forall n0,
A n0 -> (forall n, A n -> A (S n)) -> (forall n, A n -> A (P n)) ->
forall n, A n.
Proof.
intros.
assert (A 0).
destruct (itersucc_or_iterpred 0 n0) as (k,[Hk|Hk]); rewrite Hk; clear Hk.
clear H2. induction k; simpl in *; auto.
clear H1. induction k; simpl in *; auto.
apply bi_induction_pred; auto.
Qed.
End NZDomainProp.
(** We now focus on the translation from [nat] into [NZ].
First, relationship with [0], [succ], [pred].
*)
Module NZOfNat (Import NZ:NZDomainSig').
Definition ofnat (n : nat) : t := (S^n) 0.
Notation "[ n ]" := (ofnat n) (at level 7) : ofnat.
Local Open Scope ofnat.
Lemma ofnat_zero : [O] == 0.
Proof.
reflexivity.
Qed.
Lemma ofnat_succ : forall n, [Datatypes.S n] == succ [n].
Proof.
now unfold ofnat.
Qed.
Lemma ofnat_pred : forall n, n<>O -> [Peano.pred n] == P [n].
Proof.
unfold ofnat. destruct n. destruct 1; auto.
intros _. simpl. symmetry. apply pred_succ.
Qed.
(** Since [P 0] can be anything in NZ (either [-1], [0], or even other
numbers, we cannot state previous lemma for [n=O]. *)
End NZOfNat.
(** If we require in addition a strict order on NZ, we can prove that
[ofnat] is injective, and hence that NZ is infinite
(i.e. we ban Z/nZ models) *)
Module NZOfNatOrd (Import NZ:NZOrdSig').
Include NZOfNat NZ.
Include NZOrderPropFunct NZ.
Local Open Scope ofnat.
Theorem ofnat_S_gt_0 :
forall n : nat, 0 < [Datatypes.S n].
Proof.
unfold ofnat.
intros n; induction n as [| n IH]; simpl in *.
apply lt_0_1.
apply lt_trans with 1. apply lt_0_1. now rewrite <- succ_lt_mono.
Qed.
Theorem ofnat_S_neq_0 :
forall n : nat, 0 ~= [Datatypes.S n].
Proof.
intros. apply lt_neq, ofnat_S_gt_0.
Qed.
Lemma ofnat_injective : forall n m, [n]==[m] -> n = m.
Proof.
induction n as [|n IH]; destruct m; auto.
intros H; elim (ofnat_S_neq_0 _ H).
intros H; symmetry in H; elim (ofnat_S_neq_0 _ H).
intros. f_equal. apply IH. now rewrite <- succ_inj_wd.
Qed.
Lemma ofnat_eq : forall n m, [n]==[m] <-> n = m.
Proof.
split. apply ofnat_injective. intros; now subst.
Qed.
(* In addition, we can prove that [ofnat] preserves order. *)
Lemma ofnat_lt : forall n m : nat, [n]<[m] <-> (n<m)%nat.
Proof.
induction n as [|n IH]; destruct m; repeat rewrite ofnat_zero; split.
intro H; elim (lt_irrefl _ H).
inversion 1.
auto with arith.
intros; apply ofnat_S_gt_0.
intro H; elim (lt_asymm _ _ H); apply ofnat_S_gt_0.
inversion 1.
rewrite !ofnat_succ, <- succ_lt_mono, IH; auto with arith.
rewrite !ofnat_succ, <- succ_lt_mono, IH; auto with arith.
Qed.
Lemma ofnat_le : forall n m : nat, [n]<=[m] <-> (n<=m)%nat.
Proof.
intros. rewrite lt_eq_cases, ofnat_lt, ofnat_eq.
split.
destruct 1; subst; auto with arith.
apply Lt.le_lt_or_eq.
Qed.
End NZOfNatOrd.
(** For basic operations, we can prove correspondance with
their counterpart in [nat]. *)
Module NZOfNatOps (Import NZ:NZAxiomsSig').
Include NZOfNat NZ.
Local Open Scope ofnat.
Lemma ofnat_add_l : forall n m, [n]+m == (S^n) m.
Proof.
induction n; intros.
apply add_0_l.
rewrite ofnat_succ, add_succ_l. simpl; apply succ_wd; auto.
Qed.
Lemma ofnat_add : forall n m, [n+m] == [n]+[m].
Proof.
intros. rewrite ofnat_add_l.
induction n; simpl. reflexivity.
rewrite ofnat_succ. now apply succ_wd.
Qed.
Lemma ofnat_mul : forall n m, [n*m] == [n]*[m].
Proof.
induction n; simpl; intros.
symmetry. apply mul_0_l.
rewrite plus_comm.
rewrite ofnat_succ, ofnat_add, mul_succ_l.
now apply add_wd.
Qed.
Lemma ofnat_sub_r : forall n m, n-[m] == (P^m) n.
Proof.
induction m; simpl; intros.
rewrite ofnat_zero. apply sub_0_r.
rewrite ofnat_succ, sub_succ_r. now apply pred_wd.
Qed.
Lemma ofnat_sub : forall n m, m<=n -> [n-m] == [n]-[m].
Proof.
intros n m H. rewrite ofnat_sub_r.
revert n H. induction m. intros.
rewrite <- minus_n_O. now simpl.
intros.
destruct n.
inversion H.
rewrite iter_alt.
simpl.
rewrite ofnat_succ, pred_succ; auto with arith.
Qed.
End NZOfNatOps.
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's 32x32 multiply for ASIC ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// 32x32 multiply for ASIC ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_amultp2_32x32.v,v $
// Revision 1.2 2003/04/07 01:23:31 lampret
// Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/12/04 05:02:35 lampret
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
`ifdef OR1200_ASIC_MULTP2_32X32
module PP_LOW ( ONEPOS, ONENEG, TWONEG, INA, INB, PPBIT );
input ONEPOS;
input ONENEG;
input TWONEG;
input INA;
input INB;
output PPBIT;
assign PPBIT = (ONEPOS & INA) | (ONENEG & INB) | TWONEG;
endmodule
module PP_MIDDLE ( ONEPOS, ONENEG, TWOPOS, TWONEG, INA, INB, INC, IND, PPBIT );
input ONEPOS;
input ONENEG;
input TWOPOS;
input TWONEG;
input INA;
input INB;
input INC;
input IND;
output PPBIT;
assign PPBIT = ~ (( ~ (INA & TWOPOS)) & ( ~ (INB & TWONEG)) & ( ~ (INC & ONEPOS)) & ( ~ (IND & ONENEG)));
endmodule
module PP_HIGH ( ONEPOS, ONENEG, TWOPOS, TWONEG, INA, INB, PPBIT );
input ONEPOS;
input ONENEG;
input TWOPOS;
input TWONEG;
input INA;
input INB;
output PPBIT;
assign PPBIT = ~ ((INA & ONEPOS) | (INB & ONENEG) | (INA & TWOPOS) | (INB & TWONEG));
endmodule
module R_GATE ( INA, INB, INC, PPBIT );
input INA;
input INB;
input INC;
output PPBIT;
assign PPBIT = ( ~ (INA & INB)) & INC;
endmodule
module DECODER ( INA, INB, INC, TWOPOS, TWONEG, ONEPOS, ONENEG );
input INA;
input INB;
input INC;
output TWOPOS;
output TWONEG;
output ONEPOS;
output ONENEG;
assign TWOPOS = ~ ( ~ (INA & INB & ( ~ INC)));
assign TWONEG = ~ ( ~ (( ~ INA) & ( ~ INB) & INC));
assign ONEPOS = (( ~ INA) & INB & ( ~ INC)) | (( ~ INC) & ( ~ INB) & INA);
assign ONENEG = (INA & ( ~ INB) & INC) | (INC & INB & ( ~ INA));
endmodule
module BOOTHCODER_33_32 ( OPA, OPB, SUMMAND );
input [0:32] OPA;
input [0:31] OPB;
output [0:575] SUMMAND;
wire [0:32] INV_MULTIPLICAND;
wire [0:63] INT_MULTIPLIER;
wire LOGIC_ONE, LOGIC_ZERO;
assign LOGIC_ONE = 1;
assign LOGIC_ZERO = 0;
DECODER DEC_0 (.INA (LOGIC_ZERO) , .INB (OPB[0]) , .INC (OPB[1]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) );
assign INV_MULTIPLICAND[0] = ~ OPA[0];
PP_LOW PPL_0 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[0]) );
R_GATE RGATE_0 (.INA (LOGIC_ZERO) , .INB (OPB[0]) , .INC (OPB[1]) , .PPBIT (SUMMAND[1]) );
assign INV_MULTIPLICAND[1] = ~ OPA[1];
PP_MIDDLE PPM_0 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[2]) );
assign INV_MULTIPLICAND[2] = ~ OPA[2];
PP_MIDDLE PPM_1 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[3]) );
assign INV_MULTIPLICAND[3] = ~ OPA[3];
PP_MIDDLE PPM_2 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[6]) );
assign INV_MULTIPLICAND[4] = ~ OPA[4];
PP_MIDDLE PPM_3 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[8]) );
assign INV_MULTIPLICAND[5] = ~ OPA[5];
PP_MIDDLE PPM_4 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[12]) );
assign INV_MULTIPLICAND[6] = ~ OPA[6];
PP_MIDDLE PPM_5 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[15]) );
assign INV_MULTIPLICAND[7] = ~ OPA[7];
PP_MIDDLE PPM_6 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[20]) );
assign INV_MULTIPLICAND[8] = ~ OPA[8];
PP_MIDDLE PPM_7 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[24]) );
assign INV_MULTIPLICAND[9] = ~ OPA[9];
PP_MIDDLE PPM_8 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[30]) );
assign INV_MULTIPLICAND[10] = ~ OPA[10];
PP_MIDDLE PPM_9 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[35]) );
assign INV_MULTIPLICAND[11] = ~ OPA[11];
PP_MIDDLE PPM_10 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[42]) );
assign INV_MULTIPLICAND[12] = ~ OPA[12];
PP_MIDDLE PPM_11 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[48]) );
assign INV_MULTIPLICAND[13] = ~ OPA[13];
PP_MIDDLE PPM_12 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[56]) );
assign INV_MULTIPLICAND[14] = ~ OPA[14];
PP_MIDDLE PPM_13 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[63]) );
assign INV_MULTIPLICAND[15] = ~ OPA[15];
PP_MIDDLE PPM_14 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[72]) );
assign INV_MULTIPLICAND[16] = ~ OPA[16];
PP_MIDDLE PPM_15 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[80]) );
assign INV_MULTIPLICAND[17] = ~ OPA[17];
PP_MIDDLE PPM_16 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[90]) );
assign INV_MULTIPLICAND[18] = ~ OPA[18];
PP_MIDDLE PPM_17 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[99]) );
assign INV_MULTIPLICAND[19] = ~ OPA[19];
PP_MIDDLE PPM_18 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[110]) );
assign INV_MULTIPLICAND[20] = ~ OPA[20];
PP_MIDDLE PPM_19 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[120]) );
assign INV_MULTIPLICAND[21] = ~ OPA[21];
PP_MIDDLE PPM_20 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[132]) );
assign INV_MULTIPLICAND[22] = ~ OPA[22];
PP_MIDDLE PPM_21 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[143]) );
assign INV_MULTIPLICAND[23] = ~ OPA[23];
PP_MIDDLE PPM_22 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[156]) );
assign INV_MULTIPLICAND[24] = ~ OPA[24];
PP_MIDDLE PPM_23 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[168]) );
assign INV_MULTIPLICAND[25] = ~ OPA[25];
PP_MIDDLE PPM_24 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[182]) );
assign INV_MULTIPLICAND[26] = ~ OPA[26];
PP_MIDDLE PPM_25 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[195]) );
assign INV_MULTIPLICAND[27] = ~ OPA[27];
PP_MIDDLE PPM_26 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[210]) );
assign INV_MULTIPLICAND[28] = ~ OPA[28];
PP_MIDDLE PPM_27 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[224]) );
assign INV_MULTIPLICAND[29] = ~ OPA[29];
PP_MIDDLE PPM_28 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[240]) );
assign INV_MULTIPLICAND[30] = ~ OPA[30];
PP_MIDDLE PPM_29 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[255]) );
assign INV_MULTIPLICAND[31] = ~ OPA[31];
PP_MIDDLE PPM_30 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[272]) );
assign INV_MULTIPLICAND[32] = ~ OPA[32];
PP_MIDDLE PPM_31 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[288]) );
PP_HIGH PPH_0 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[304]) );
assign SUMMAND[305] = 1;
DECODER DEC_1 (.INA (OPB[1]) , .INB (OPB[2]) , .INC (OPB[3]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) );
PP_LOW PPL_1 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[4]) );
R_GATE RGATE_1 (.INA (OPB[1]) , .INB (OPB[2]) , .INC (OPB[3]) , .PPBIT (SUMMAND[5]) );
PP_MIDDLE PPM_32 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[7]) );
PP_MIDDLE PPM_33 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[9]) );
PP_MIDDLE PPM_34 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[13]) );
PP_MIDDLE PPM_35 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[16]) );
PP_MIDDLE PPM_36 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[21]) );
PP_MIDDLE PPM_37 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[25]) );
PP_MIDDLE PPM_38 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[31]) );
PP_MIDDLE PPM_39 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[36]) );
PP_MIDDLE PPM_40 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[43]) );
PP_MIDDLE PPM_41 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[49]) );
PP_MIDDLE PPM_42 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[57]) );
PP_MIDDLE PPM_43 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[64]) );
PP_MIDDLE PPM_44 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[73]) );
PP_MIDDLE PPM_45 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[81]) );
PP_MIDDLE PPM_46 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[91]) );
PP_MIDDLE PPM_47 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[100]) );
PP_MIDDLE PPM_48 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[111]) );
PP_MIDDLE PPM_49 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[121]) );
PP_MIDDLE PPM_50 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[133]) );
PP_MIDDLE PPM_51 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[144]) );
PP_MIDDLE PPM_52 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[157]) );
PP_MIDDLE PPM_53 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[169]) );
PP_MIDDLE PPM_54 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[183]) );
PP_MIDDLE PPM_55 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[196]) );
PP_MIDDLE PPM_56 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[211]) );
PP_MIDDLE PPM_57 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[225]) );
PP_MIDDLE PPM_58 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[241]) );
PP_MIDDLE PPM_59 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[256]) );
PP_MIDDLE PPM_60 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[273]) );
PP_MIDDLE PPM_61 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[289]) );
PP_MIDDLE PPM_62 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[306]) );
PP_MIDDLE PPM_63 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[321]) );
assign SUMMAND[322] = LOGIC_ONE;
PP_HIGH PPH_1 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[337]) );
DECODER DEC_2 (.INA (OPB[3]) , .INB (OPB[4]) , .INC (OPB[5]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) );
PP_LOW PPL_2 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[10]) );
R_GATE RGATE_2 (.INA (OPB[3]) , .INB (OPB[4]) , .INC (OPB[5]) , .PPBIT (SUMMAND[11]) );
PP_MIDDLE PPM_64 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[14]) );
PP_MIDDLE PPM_65 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[17]) );
PP_MIDDLE PPM_66 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[22]) );
PP_MIDDLE PPM_67 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[26]) );
PP_MIDDLE PPM_68 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[32]) );
PP_MIDDLE PPM_69 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[37]) );
PP_MIDDLE PPM_70 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[44]) );
PP_MIDDLE PPM_71 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[50]) );
PP_MIDDLE PPM_72 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[58]) );
PP_MIDDLE PPM_73 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[65]) );
PP_MIDDLE PPM_74 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[74]) );
PP_MIDDLE PPM_75 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[82]) );
PP_MIDDLE PPM_76 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[92]) );
PP_MIDDLE PPM_77 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[101]) );
PP_MIDDLE PPM_78 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[112]) );
PP_MIDDLE PPM_79 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[122]) );
PP_MIDDLE PPM_80 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[134]) );
PP_MIDDLE PPM_81 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[145]) );
PP_MIDDLE PPM_82 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[158]) );
PP_MIDDLE PPM_83 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[170]) );
PP_MIDDLE PPM_84 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[184]) );
PP_MIDDLE PPM_85 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[197]) );
PP_MIDDLE PPM_86 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[212]) );
PP_MIDDLE PPM_87 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[226]) );
PP_MIDDLE PPM_88 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[242]) );
PP_MIDDLE PPM_89 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[257]) );
PP_MIDDLE PPM_90 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[274]) );
PP_MIDDLE PPM_91 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[290]) );
PP_MIDDLE PPM_92 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[307]) );
PP_MIDDLE PPM_93 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[323]) );
PP_MIDDLE PPM_94 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[338]) );
PP_MIDDLE PPM_95 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[352]) );
assign SUMMAND[353] = LOGIC_ONE;
PP_HIGH PPH_2 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[367]) );
DECODER DEC_3 (.INA (OPB[5]) , .INB (OPB[6]) , .INC (OPB[7]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) );
PP_LOW PPL_3 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[18]) );
R_GATE RGATE_3 (.INA (OPB[5]) , .INB (OPB[6]) , .INC (OPB[7]) , .PPBIT (SUMMAND[19]) );
PP_MIDDLE PPM_96 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[23]) );
PP_MIDDLE PPM_97 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[27]) );
PP_MIDDLE PPM_98 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[33]) );
PP_MIDDLE PPM_99 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[38]) );
PP_MIDDLE PPM_100 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[45]) );
PP_MIDDLE PPM_101 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[51]) );
PP_MIDDLE PPM_102 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[59]) );
PP_MIDDLE PPM_103 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[66]) );
PP_MIDDLE PPM_104 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[75]) );
PP_MIDDLE PPM_105 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[83]) );
PP_MIDDLE PPM_106 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[93]) );
PP_MIDDLE PPM_107 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[102]) );
PP_MIDDLE PPM_108 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[113]) );
PP_MIDDLE PPM_109 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[123]) );
PP_MIDDLE PPM_110 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[135]) );
PP_MIDDLE PPM_111 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[146]) );
PP_MIDDLE PPM_112 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[159]) );
PP_MIDDLE PPM_113 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[171]) );
PP_MIDDLE PPM_114 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[185]) );
PP_MIDDLE PPM_115 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[198]) );
PP_MIDDLE PPM_116 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[213]) );
PP_MIDDLE PPM_117 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[227]) );
PP_MIDDLE PPM_118 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[243]) );
PP_MIDDLE PPM_119 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[258]) );
PP_MIDDLE PPM_120 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[275]) );
PP_MIDDLE PPM_121 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[291]) );
PP_MIDDLE PPM_122 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[308]) );
PP_MIDDLE PPM_123 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[324]) );
PP_MIDDLE PPM_124 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[339]) );
PP_MIDDLE PPM_125 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[354]) );
PP_MIDDLE PPM_126 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[368]) );
PP_MIDDLE PPM_127 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[381]) );
assign SUMMAND[382] = LOGIC_ONE;
PP_HIGH PPH_3 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[395]) );
DECODER DEC_4 (.INA (OPB[7]) , .INB (OPB[8]) , .INC (OPB[9]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) );
PP_LOW PPL_4 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[28]) );
R_GATE RGATE_4 (.INA (OPB[7]) , .INB (OPB[8]) , .INC (OPB[9]) , .PPBIT (SUMMAND[29]) );
PP_MIDDLE PPM_128 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[34]) );
PP_MIDDLE PPM_129 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[39]) );
PP_MIDDLE PPM_130 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[46]) );
PP_MIDDLE PPM_131 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[52]) );
PP_MIDDLE PPM_132 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[60]) );
PP_MIDDLE PPM_133 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[67]) );
PP_MIDDLE PPM_134 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[76]) );
PP_MIDDLE PPM_135 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[84]) );
PP_MIDDLE PPM_136 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[94]) );
PP_MIDDLE PPM_137 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[103]) );
PP_MIDDLE PPM_138 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[114]) );
PP_MIDDLE PPM_139 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[124]) );
PP_MIDDLE PPM_140 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[136]) );
PP_MIDDLE PPM_141 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[147]) );
PP_MIDDLE PPM_142 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[160]) );
PP_MIDDLE PPM_143 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[172]) );
PP_MIDDLE PPM_144 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[186]) );
PP_MIDDLE PPM_145 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[199]) );
PP_MIDDLE PPM_146 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[214]) );
PP_MIDDLE PPM_147 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[228]) );
PP_MIDDLE PPM_148 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[244]) );
PP_MIDDLE PPM_149 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[259]) );
PP_MIDDLE PPM_150 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[276]) );
PP_MIDDLE PPM_151 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[292]) );
PP_MIDDLE PPM_152 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[309]) );
PP_MIDDLE PPM_153 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[325]) );
PP_MIDDLE PPM_154 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[340]) );
PP_MIDDLE PPM_155 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[355]) );
PP_MIDDLE PPM_156 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[369]) );
PP_MIDDLE PPM_157 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[383]) );
PP_MIDDLE PPM_158 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[396]) );
PP_MIDDLE PPM_159 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[408]) );
assign SUMMAND[409] = LOGIC_ONE;
PP_HIGH PPH_4 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[421]) );
DECODER DEC_5 (.INA (OPB[9]) , .INB (OPB[10]) , .INC (OPB[11]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) );
PP_LOW PPL_5 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[40]) );
R_GATE RGATE_5 (.INA (OPB[9]) , .INB (OPB[10]) , .INC (OPB[11]) , .PPBIT (SUMMAND[41]) );
PP_MIDDLE PPM_160 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[47]) );
PP_MIDDLE PPM_161 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[53]) );
PP_MIDDLE PPM_162 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[61]) );
PP_MIDDLE PPM_163 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[68]) );
PP_MIDDLE PPM_164 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[77]) );
PP_MIDDLE PPM_165 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[85]) );
PP_MIDDLE PPM_166 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[95]) );
PP_MIDDLE PPM_167 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[104]) );
PP_MIDDLE PPM_168 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[115]) );
PP_MIDDLE PPM_169 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[125]) );
PP_MIDDLE PPM_170 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[137]) );
PP_MIDDLE PPM_171 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[148]) );
PP_MIDDLE PPM_172 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[161]) );
PP_MIDDLE PPM_173 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[173]) );
PP_MIDDLE PPM_174 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[187]) );
PP_MIDDLE PPM_175 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[200]) );
PP_MIDDLE PPM_176 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[215]) );
PP_MIDDLE PPM_177 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[229]) );
PP_MIDDLE PPM_178 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[245]) );
PP_MIDDLE PPM_179 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[260]) );
PP_MIDDLE PPM_180 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[277]) );
PP_MIDDLE PPM_181 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[293]) );
PP_MIDDLE PPM_182 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[310]) );
PP_MIDDLE PPM_183 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[326]) );
PP_MIDDLE PPM_184 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[341]) );
PP_MIDDLE PPM_185 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[356]) );
PP_MIDDLE PPM_186 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[370]) );
PP_MIDDLE PPM_187 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[384]) );
PP_MIDDLE PPM_188 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[397]) );
PP_MIDDLE PPM_189 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[410]) );
PP_MIDDLE PPM_190 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[422]) );
PP_MIDDLE PPM_191 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[433]) );
assign SUMMAND[434] = LOGIC_ONE;
PP_HIGH PPH_5 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[445]) );
DECODER DEC_6 (.INA (OPB[11]) , .INB (OPB[12]) , .INC (OPB[13]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) );
PP_LOW PPL_6 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[54]) );
R_GATE RGATE_6 (.INA (OPB[11]) , .INB (OPB[12]) , .INC (OPB[13]) , .PPBIT (SUMMAND[55]) );
PP_MIDDLE PPM_192 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[62]) );
PP_MIDDLE PPM_193 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[69]) );
PP_MIDDLE PPM_194 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[78]) );
PP_MIDDLE PPM_195 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[86]) );
PP_MIDDLE PPM_196 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[96]) );
PP_MIDDLE PPM_197 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[105]) );
PP_MIDDLE PPM_198 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[116]) );
PP_MIDDLE PPM_199 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[126]) );
PP_MIDDLE PPM_200 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[138]) );
PP_MIDDLE PPM_201 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[149]) );
PP_MIDDLE PPM_202 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[162]) );
PP_MIDDLE PPM_203 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[174]) );
PP_MIDDLE PPM_204 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[188]) );
PP_MIDDLE PPM_205 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[201]) );
PP_MIDDLE PPM_206 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[216]) );
PP_MIDDLE PPM_207 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[230]) );
PP_MIDDLE PPM_208 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[246]) );
PP_MIDDLE PPM_209 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[261]) );
PP_MIDDLE PPM_210 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[278]) );
PP_MIDDLE PPM_211 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[294]) );
PP_MIDDLE PPM_212 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[311]) );
PP_MIDDLE PPM_213 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[327]) );
PP_MIDDLE PPM_214 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[342]) );
PP_MIDDLE PPM_215 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[357]) );
PP_MIDDLE PPM_216 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[371]) );
PP_MIDDLE PPM_217 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[385]) );
PP_MIDDLE PPM_218 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[398]) );
PP_MIDDLE PPM_219 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[411]) );
PP_MIDDLE PPM_220 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[423]) );
PP_MIDDLE PPM_221 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[435]) );
PP_MIDDLE PPM_222 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[446]) );
PP_MIDDLE PPM_223 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[456]) );
assign SUMMAND[457] = LOGIC_ONE;
PP_HIGH PPH_6 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[467]) );
DECODER DEC_7 (.INA (OPB[13]) , .INB (OPB[14]) , .INC (OPB[15]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) );
PP_LOW PPL_7 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[70]) );
R_GATE RGATE_7 (.INA (OPB[13]) , .INB (OPB[14]) , .INC (OPB[15]) , .PPBIT (SUMMAND[71]) );
PP_MIDDLE PPM_224 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[79]) );
PP_MIDDLE PPM_225 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[87]) );
PP_MIDDLE PPM_226 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[97]) );
PP_MIDDLE PPM_227 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[106]) );
PP_MIDDLE PPM_228 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[117]) );
PP_MIDDLE PPM_229 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[127]) );
PP_MIDDLE PPM_230 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[139]) );
PP_MIDDLE PPM_231 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[150]) );
PP_MIDDLE PPM_232 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[163]) );
PP_MIDDLE PPM_233 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[175]) );
PP_MIDDLE PPM_234 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[189]) );
PP_MIDDLE PPM_235 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[202]) );
PP_MIDDLE PPM_236 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[217]) );
PP_MIDDLE PPM_237 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[231]) );
PP_MIDDLE PPM_238 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[247]) );
PP_MIDDLE PPM_239 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[262]) );
PP_MIDDLE PPM_240 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[279]) );
PP_MIDDLE PPM_241 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[295]) );
PP_MIDDLE PPM_242 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[312]) );
PP_MIDDLE PPM_243 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[328]) );
PP_MIDDLE PPM_244 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[343]) );
PP_MIDDLE PPM_245 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[358]) );
PP_MIDDLE PPM_246 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[372]) );
PP_MIDDLE PPM_247 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[386]) );
PP_MIDDLE PPM_248 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[399]) );
PP_MIDDLE PPM_249 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[412]) );
PP_MIDDLE PPM_250 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[424]) );
PP_MIDDLE PPM_251 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[436]) );
PP_MIDDLE PPM_252 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[447]) );
PP_MIDDLE PPM_253 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[458]) );
PP_MIDDLE PPM_254 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[468]) );
PP_MIDDLE PPM_255 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[477]) );
assign SUMMAND[478] = LOGIC_ONE;
PP_HIGH PPH_7 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[487]) );
DECODER DEC_8 (.INA (OPB[15]) , .INB (OPB[16]) , .INC (OPB[17]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) );
PP_LOW PPL_8 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[88]) );
R_GATE RGATE_8 (.INA (OPB[15]) , .INB (OPB[16]) , .INC (OPB[17]) , .PPBIT (SUMMAND[89]) );
PP_MIDDLE PPM_256 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[98]) );
PP_MIDDLE PPM_257 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[107]) );
PP_MIDDLE PPM_258 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[118]) );
PP_MIDDLE PPM_259 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[128]) );
PP_MIDDLE PPM_260 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[140]) );
PP_MIDDLE PPM_261 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[151]) );
PP_MIDDLE PPM_262 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[164]) );
PP_MIDDLE PPM_263 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[176]) );
PP_MIDDLE PPM_264 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[190]) );
PP_MIDDLE PPM_265 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[203]) );
PP_MIDDLE PPM_266 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[218]) );
PP_MIDDLE PPM_267 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[232]) );
PP_MIDDLE PPM_268 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[248]) );
PP_MIDDLE PPM_269 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[263]) );
PP_MIDDLE PPM_270 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[280]) );
PP_MIDDLE PPM_271 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[296]) );
PP_MIDDLE PPM_272 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[313]) );
PP_MIDDLE PPM_273 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[329]) );
PP_MIDDLE PPM_274 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[344]) );
PP_MIDDLE PPM_275 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[359]) );
PP_MIDDLE PPM_276 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[373]) );
PP_MIDDLE PPM_277 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[387]) );
PP_MIDDLE PPM_278 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[400]) );
PP_MIDDLE PPM_279 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[413]) );
PP_MIDDLE PPM_280 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[425]) );
PP_MIDDLE PPM_281 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[437]) );
PP_MIDDLE PPM_282 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[448]) );
PP_MIDDLE PPM_283 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[459]) );
PP_MIDDLE PPM_284 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[469]) );
PP_MIDDLE PPM_285 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[479]) );
PP_MIDDLE PPM_286 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[488]) );
PP_MIDDLE PPM_287 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[496]) );
assign SUMMAND[497] = LOGIC_ONE;
PP_HIGH PPH_8 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[505]) );
DECODER DEC_9 (.INA (OPB[17]) , .INB (OPB[18]) , .INC (OPB[19]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) );
PP_LOW PPL_9 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[108]) );
R_GATE RGATE_9 (.INA (OPB[17]) , .INB (OPB[18]) , .INC (OPB[19]) , .PPBIT (SUMMAND[109]) );
PP_MIDDLE PPM_288 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[119]) );
PP_MIDDLE PPM_289 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[129]) );
PP_MIDDLE PPM_290 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[141]) );
PP_MIDDLE PPM_291 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[152]) );
PP_MIDDLE PPM_292 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[165]) );
PP_MIDDLE PPM_293 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[177]) );
PP_MIDDLE PPM_294 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[191]) );
PP_MIDDLE PPM_295 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[204]) );
PP_MIDDLE PPM_296 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[219]) );
PP_MIDDLE PPM_297 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[233]) );
PP_MIDDLE PPM_298 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[249]) );
PP_MIDDLE PPM_299 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[264]) );
PP_MIDDLE PPM_300 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[281]) );
PP_MIDDLE PPM_301 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[297]) );
PP_MIDDLE PPM_302 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[314]) );
PP_MIDDLE PPM_303 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[330]) );
PP_MIDDLE PPM_304 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[345]) );
PP_MIDDLE PPM_305 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[360]) );
PP_MIDDLE PPM_306 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[374]) );
PP_MIDDLE PPM_307 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[388]) );
PP_MIDDLE PPM_308 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[401]) );
PP_MIDDLE PPM_309 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[414]) );
PP_MIDDLE PPM_310 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[426]) );
PP_MIDDLE PPM_311 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[438]) );
PP_MIDDLE PPM_312 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[449]) );
PP_MIDDLE PPM_313 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[460]) );
PP_MIDDLE PPM_314 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[470]) );
PP_MIDDLE PPM_315 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[480]) );
PP_MIDDLE PPM_316 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[489]) );
PP_MIDDLE PPM_317 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[498]) );
PP_MIDDLE PPM_318 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[506]) );
PP_MIDDLE PPM_319 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[513]) );
assign SUMMAND[514] = LOGIC_ONE;
PP_HIGH PPH_9 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[521]) );
DECODER DEC_10 (.INA (OPB[19]) , .INB (OPB[20]) , .INC (OPB[21]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) );
PP_LOW PPL_10 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[130]) );
R_GATE RGATE_10 (.INA (OPB[19]) , .INB (OPB[20]) , .INC (OPB[21]) , .PPBIT (SUMMAND[131]) );
PP_MIDDLE PPM_320 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[142]) );
PP_MIDDLE PPM_321 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[153]) );
PP_MIDDLE PPM_322 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[166]) );
PP_MIDDLE PPM_323 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[178]) );
PP_MIDDLE PPM_324 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[192]) );
PP_MIDDLE PPM_325 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[205]) );
PP_MIDDLE PPM_326 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[220]) );
PP_MIDDLE PPM_327 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[234]) );
PP_MIDDLE PPM_328 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[250]) );
PP_MIDDLE PPM_329 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[265]) );
PP_MIDDLE PPM_330 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[282]) );
PP_MIDDLE PPM_331 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[298]) );
PP_MIDDLE PPM_332 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[315]) );
PP_MIDDLE PPM_333 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[331]) );
PP_MIDDLE PPM_334 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[346]) );
PP_MIDDLE PPM_335 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[361]) );
PP_MIDDLE PPM_336 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[375]) );
PP_MIDDLE PPM_337 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[389]) );
PP_MIDDLE PPM_338 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[402]) );
PP_MIDDLE PPM_339 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[415]) );
PP_MIDDLE PPM_340 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[427]) );
PP_MIDDLE PPM_341 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[439]) );
PP_MIDDLE PPM_342 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[450]) );
PP_MIDDLE PPM_343 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[461]) );
PP_MIDDLE PPM_344 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[471]) );
PP_MIDDLE PPM_345 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[481]) );
PP_MIDDLE PPM_346 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[490]) );
PP_MIDDLE PPM_347 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[499]) );
PP_MIDDLE PPM_348 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[507]) );
PP_MIDDLE PPM_349 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[515]) );
PP_MIDDLE PPM_350 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[522]) );
PP_MIDDLE PPM_351 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[528]) );
assign SUMMAND[529] = LOGIC_ONE;
PP_HIGH PPH_10 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[535]) );
DECODER DEC_11 (.INA (OPB[21]) , .INB (OPB[22]) , .INC (OPB[23]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) );
PP_LOW PPL_11 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[154]) );
R_GATE RGATE_11 (.INA (OPB[21]) , .INB (OPB[22]) , .INC (OPB[23]) , .PPBIT (SUMMAND[155]) );
PP_MIDDLE PPM_352 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[167]) );
PP_MIDDLE PPM_353 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[179]) );
PP_MIDDLE PPM_354 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[193]) );
PP_MIDDLE PPM_355 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[206]) );
PP_MIDDLE PPM_356 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[221]) );
PP_MIDDLE PPM_357 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[235]) );
PP_MIDDLE PPM_358 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[251]) );
PP_MIDDLE PPM_359 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[266]) );
PP_MIDDLE PPM_360 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[283]) );
PP_MIDDLE PPM_361 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[299]) );
PP_MIDDLE PPM_362 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[316]) );
PP_MIDDLE PPM_363 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[332]) );
PP_MIDDLE PPM_364 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[347]) );
PP_MIDDLE PPM_365 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[362]) );
PP_MIDDLE PPM_366 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[376]) );
PP_MIDDLE PPM_367 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[390]) );
PP_MIDDLE PPM_368 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[403]) );
PP_MIDDLE PPM_369 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[416]) );
PP_MIDDLE PPM_370 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[428]) );
PP_MIDDLE PPM_371 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[440]) );
PP_MIDDLE PPM_372 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[451]) );
PP_MIDDLE PPM_373 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[462]) );
PP_MIDDLE PPM_374 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[472]) );
PP_MIDDLE PPM_375 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[482]) );
PP_MIDDLE PPM_376 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[491]) );
PP_MIDDLE PPM_377 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[500]) );
PP_MIDDLE PPM_378 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[508]) );
PP_MIDDLE PPM_379 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[516]) );
PP_MIDDLE PPM_380 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[523]) );
PP_MIDDLE PPM_381 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[530]) );
PP_MIDDLE PPM_382 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[536]) );
PP_MIDDLE PPM_383 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[541]) );
assign SUMMAND[542] = LOGIC_ONE;
PP_HIGH PPH_11 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[547]) );
DECODER DEC_12 (.INA (OPB[23]) , .INB (OPB[24]) , .INC (OPB[25]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) );
PP_LOW PPL_12 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[180]) );
R_GATE RGATE_12 (.INA (OPB[23]) , .INB (OPB[24]) , .INC (OPB[25]) , .PPBIT (SUMMAND[181]) );
PP_MIDDLE PPM_384 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[194]) );
PP_MIDDLE PPM_385 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[207]) );
PP_MIDDLE PPM_386 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[222]) );
PP_MIDDLE PPM_387 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[236]) );
PP_MIDDLE PPM_388 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[252]) );
PP_MIDDLE PPM_389 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[267]) );
PP_MIDDLE PPM_390 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[284]) );
PP_MIDDLE PPM_391 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[300]) );
PP_MIDDLE PPM_392 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[317]) );
PP_MIDDLE PPM_393 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[333]) );
PP_MIDDLE PPM_394 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[348]) );
PP_MIDDLE PPM_395 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[363]) );
PP_MIDDLE PPM_396 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[377]) );
PP_MIDDLE PPM_397 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[391]) );
PP_MIDDLE PPM_398 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[404]) );
PP_MIDDLE PPM_399 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[417]) );
PP_MIDDLE PPM_400 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[429]) );
PP_MIDDLE PPM_401 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[441]) );
PP_MIDDLE PPM_402 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[452]) );
PP_MIDDLE PPM_403 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[463]) );
PP_MIDDLE PPM_404 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[473]) );
PP_MIDDLE PPM_405 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[483]) );
PP_MIDDLE PPM_406 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[492]) );
PP_MIDDLE PPM_407 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[501]) );
PP_MIDDLE PPM_408 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[509]) );
PP_MIDDLE PPM_409 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[517]) );
PP_MIDDLE PPM_410 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[524]) );
PP_MIDDLE PPM_411 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[531]) );
PP_MIDDLE PPM_412 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[537]) );
PP_MIDDLE PPM_413 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[543]) );
PP_MIDDLE PPM_414 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[548]) );
PP_MIDDLE PPM_415 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[552]) );
assign SUMMAND[553] = LOGIC_ONE;
PP_HIGH PPH_12 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[557]) );
DECODER DEC_13 (.INA (OPB[25]) , .INB (OPB[26]) , .INC (OPB[27]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) );
PP_LOW PPL_13 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[208]) );
R_GATE RGATE_13 (.INA (OPB[25]) , .INB (OPB[26]) , .INC (OPB[27]) , .PPBIT (SUMMAND[209]) );
PP_MIDDLE PPM_416 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[223]) );
PP_MIDDLE PPM_417 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[237]) );
PP_MIDDLE PPM_418 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[253]) );
PP_MIDDLE PPM_419 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[268]) );
PP_MIDDLE PPM_420 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[285]) );
PP_MIDDLE PPM_421 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[301]) );
PP_MIDDLE PPM_422 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[318]) );
PP_MIDDLE PPM_423 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[334]) );
PP_MIDDLE PPM_424 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[349]) );
PP_MIDDLE PPM_425 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[364]) );
PP_MIDDLE PPM_426 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[378]) );
PP_MIDDLE PPM_427 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[392]) );
PP_MIDDLE PPM_428 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[405]) );
PP_MIDDLE PPM_429 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[418]) );
PP_MIDDLE PPM_430 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[430]) );
PP_MIDDLE PPM_431 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[442]) );
PP_MIDDLE PPM_432 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[453]) );
PP_MIDDLE PPM_433 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[464]) );
PP_MIDDLE PPM_434 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[474]) );
PP_MIDDLE PPM_435 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[484]) );
PP_MIDDLE PPM_436 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[493]) );
PP_MIDDLE PPM_437 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[502]) );
PP_MIDDLE PPM_438 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[510]) );
PP_MIDDLE PPM_439 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[518]) );
PP_MIDDLE PPM_440 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[525]) );
PP_MIDDLE PPM_441 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[532]) );
PP_MIDDLE PPM_442 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[538]) );
PP_MIDDLE PPM_443 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[544]) );
PP_MIDDLE PPM_444 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[549]) );
PP_MIDDLE PPM_445 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[554]) );
PP_MIDDLE PPM_446 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[558]) );
PP_MIDDLE PPM_447 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[561]) );
assign SUMMAND[562] = LOGIC_ONE;
PP_HIGH PPH_13 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[565]) );
DECODER DEC_14 (.INA (OPB[27]) , .INB (OPB[28]) , .INC (OPB[29]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) );
PP_LOW PPL_14 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[238]) );
R_GATE RGATE_14 (.INA (OPB[27]) , .INB (OPB[28]) , .INC (OPB[29]) , .PPBIT (SUMMAND[239]) );
PP_MIDDLE PPM_448 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[254]) );
PP_MIDDLE PPM_449 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[269]) );
PP_MIDDLE PPM_450 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[286]) );
PP_MIDDLE PPM_451 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[302]) );
PP_MIDDLE PPM_452 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[319]) );
PP_MIDDLE PPM_453 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[335]) );
PP_MIDDLE PPM_454 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[350]) );
PP_MIDDLE PPM_455 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[365]) );
PP_MIDDLE PPM_456 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[379]) );
PP_MIDDLE PPM_457 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[393]) );
PP_MIDDLE PPM_458 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[406]) );
PP_MIDDLE PPM_459 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[419]) );
PP_MIDDLE PPM_460 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[431]) );
PP_MIDDLE PPM_461 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[443]) );
PP_MIDDLE PPM_462 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[454]) );
PP_MIDDLE PPM_463 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[465]) );
PP_MIDDLE PPM_464 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[475]) );
PP_MIDDLE PPM_465 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[485]) );
PP_MIDDLE PPM_466 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[494]) );
PP_MIDDLE PPM_467 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[503]) );
PP_MIDDLE PPM_468 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[511]) );
PP_MIDDLE PPM_469 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[519]) );
PP_MIDDLE PPM_470 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[526]) );
PP_MIDDLE PPM_471 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[533]) );
PP_MIDDLE PPM_472 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[539]) );
PP_MIDDLE PPM_473 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[545]) );
PP_MIDDLE PPM_474 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[550]) );
PP_MIDDLE PPM_475 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[555]) );
PP_MIDDLE PPM_476 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[559]) );
PP_MIDDLE PPM_477 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[563]) );
PP_MIDDLE PPM_478 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[566]) );
PP_MIDDLE PPM_479 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[568]) );
assign SUMMAND[569] = LOGIC_ONE;
PP_HIGH PPH_14 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[571]) );
DECODER DEC_15 (.INA (OPB[29]) , .INB (OPB[30]) , .INC (OPB[31]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) );
PP_LOW PPL_15 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[270]) );
R_GATE RGATE_15 (.INA (OPB[29]) , .INB (OPB[30]) , .INC (OPB[31]) , .PPBIT (SUMMAND[271]) );
PP_MIDDLE PPM_480 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[287]) );
PP_MIDDLE PPM_481 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[303]) );
PP_MIDDLE PPM_482 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[320]) );
PP_MIDDLE PPM_483 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[336]) );
PP_MIDDLE PPM_484 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[351]) );
PP_MIDDLE PPM_485 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[366]) );
PP_MIDDLE PPM_486 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[380]) );
PP_MIDDLE PPM_487 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[394]) );
PP_MIDDLE PPM_488 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[407]) );
PP_MIDDLE PPM_489 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[420]) );
PP_MIDDLE PPM_490 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[432]) );
PP_MIDDLE PPM_491 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[444]) );
PP_MIDDLE PPM_492 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[455]) );
PP_MIDDLE PPM_493 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[466]) );
PP_MIDDLE PPM_494 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[476]) );
PP_MIDDLE PPM_495 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[486]) );
PP_MIDDLE PPM_496 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[495]) );
PP_MIDDLE PPM_497 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[504]) );
PP_MIDDLE PPM_498 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[512]) );
PP_MIDDLE PPM_499 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[520]) );
PP_MIDDLE PPM_500 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[527]) );
PP_MIDDLE PPM_501 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[534]) );
PP_MIDDLE PPM_502 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[540]) );
PP_MIDDLE PPM_503 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[546]) );
PP_MIDDLE PPM_504 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[551]) );
PP_MIDDLE PPM_505 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[556]) );
PP_MIDDLE PPM_506 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[560]) );
PP_MIDDLE PPM_507 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[564]) );
PP_MIDDLE PPM_508 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[567]) );
PP_MIDDLE PPM_509 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[570]) );
PP_MIDDLE PPM_510 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[572]) );
PP_MIDDLE PPM_511 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[573]) );
assign SUMMAND[574] = LOGIC_ONE;
PP_HIGH PPH_15 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[575]) );
endmodule
module FULL_ADDER ( DATA_A, DATA_B, DATA_C, SAVE, CARRY );
input DATA_A;
input DATA_B;
input DATA_C;
output SAVE;
output CARRY;
wire TMP;
assign TMP = DATA_A ^ DATA_B;
assign SAVE = TMP ^ DATA_C;
assign CARRY = ~ (( ~ (TMP & DATA_C)) & ( ~ (DATA_A & DATA_B)));
endmodule
module HALF_ADDER ( DATA_A, DATA_B, SAVE, CARRY );
input DATA_A;
input DATA_B;
output SAVE;
output CARRY;
assign SAVE = DATA_A ^ DATA_B;
assign CARRY = DATA_A & DATA_B;
endmodule
module FLIPFLOP ( DIN, RST, CLK, DOUT );
input DIN;
input RST;
input CLK;
output DOUT;
reg DOUT_reg;
always @ ( posedge RST or posedge CLK ) begin
if (RST)
DOUT_reg <= 1'b0;
else
DOUT_reg <= #1 DIN;
end
assign DOUT = DOUT_reg;
endmodule
module WALLACE_33_32 ( SUMMAND, RST, CLK, CARRY, SUM );
input [0:575] SUMMAND;
input RST;
input CLK;
output [0:62] CARRY;
output [0:63] SUM;
wire [0:7] LATCHED_PP;
wire [0:523] INT_CARRY;
wire [0:669] INT_SUM;
HALF_ADDER HA_0 (.DATA_A (SUMMAND[0]) , .DATA_B (SUMMAND[1]) , .SAVE (INT_SUM[0]) , .CARRY (INT_CARRY[0]) );
FLIPFLOP LA_0 (.DIN (INT_SUM[0]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[0]) );
FLIPFLOP LA_1 (.DIN (INT_CARRY[0]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[0]) );
assign INT_SUM[1] = SUMMAND[2];
assign CARRY[1] = 0;
FLIPFLOP LA_2 (.DIN (INT_SUM[1]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[1]) );
FULL_ADDER FA_0 (.DATA_A (SUMMAND[3]) , .DATA_B (SUMMAND[4]) , .DATA_C (SUMMAND[5]) , .SAVE (INT_SUM[2]) , .CARRY (INT_CARRY[1]) );
FLIPFLOP LA_3 (.DIN (INT_SUM[2]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[2]) );
FLIPFLOP LA_4 (.DIN (INT_CARRY[1]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[2]) );
HALF_ADDER HA_1 (.DATA_A (SUMMAND[6]) , .DATA_B (SUMMAND[7]) , .SAVE (INT_SUM[3]) , .CARRY (INT_CARRY[2]) );
FLIPFLOP LA_5 (.DIN (INT_SUM[3]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[3]) );
FLIPFLOP LA_6 (.DIN (INT_CARRY[2]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[3]) );
FULL_ADDER FA_1 (.DATA_A (SUMMAND[8]) , .DATA_B (SUMMAND[9]) , .DATA_C (SUMMAND[10]) , .SAVE (INT_SUM[4]) , .CARRY (INT_CARRY[4]) );
assign INT_SUM[5] = SUMMAND[11];
HALF_ADDER HA_2 (.DATA_A (INT_SUM[4]) , .DATA_B (INT_SUM[5]) , .SAVE (INT_SUM[6]) , .CARRY (INT_CARRY[3]) );
FLIPFLOP LA_7 (.DIN (INT_SUM[6]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[4]) );
FLIPFLOP LA_8 (.DIN (INT_CARRY[3]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[4]) );
FULL_ADDER FA_2 (.DATA_A (SUMMAND[12]) , .DATA_B (SUMMAND[13]) , .DATA_C (SUMMAND[14]) , .SAVE (INT_SUM[7]) , .CARRY (INT_CARRY[6]) );
HALF_ADDER HA_3 (.DATA_A (INT_SUM[7]) , .DATA_B (INT_CARRY[4]) , .SAVE (INT_SUM[8]) , .CARRY (INT_CARRY[5]) );
FLIPFLOP LA_9 (.DIN (INT_SUM[8]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[5]) );
FLIPFLOP LA_10 (.DIN (INT_CARRY[5]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[5]) );
FULL_ADDER FA_3 (.DATA_A (SUMMAND[15]) , .DATA_B (SUMMAND[16]) , .DATA_C (SUMMAND[17]) , .SAVE (INT_SUM[9]) , .CARRY (INT_CARRY[8]) );
HALF_ADDER HA_4 (.DATA_A (SUMMAND[18]) , .DATA_B (SUMMAND[19]) , .SAVE (INT_SUM[10]) , .CARRY (INT_CARRY[9]) );
FULL_ADDER FA_4 (.DATA_A (INT_SUM[9]) , .DATA_B (INT_SUM[10]) , .DATA_C (INT_CARRY[6]) , .SAVE (INT_SUM[11]) , .CARRY (INT_CARRY[7]) );
FLIPFLOP LA_11 (.DIN (INT_SUM[11]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[6]) );
FLIPFLOP LA_12 (.DIN (INT_CARRY[7]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[6]) );
FULL_ADDER FA_5 (.DATA_A (SUMMAND[20]) , .DATA_B (SUMMAND[21]) , .DATA_C (SUMMAND[22]) , .SAVE (INT_SUM[12]) , .CARRY (INT_CARRY[11]) );
assign INT_SUM[13] = SUMMAND[23];
FULL_ADDER FA_6 (.DATA_A (INT_SUM[12]) , .DATA_B (INT_SUM[13]) , .DATA_C (INT_CARRY[8]) , .SAVE (INT_SUM[14]) , .CARRY (INT_CARRY[12]) );
assign INT_SUM[15] = INT_CARRY[9];
HALF_ADDER HA_5 (.DATA_A (INT_SUM[14]) , .DATA_B (INT_SUM[15]) , .SAVE (INT_SUM[16]) , .CARRY (INT_CARRY[10]) );
FLIPFLOP LA_13 (.DIN (INT_SUM[16]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[7]) );
FLIPFLOP LA_14 (.DIN (INT_CARRY[10]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[7]) );
FULL_ADDER FA_7 (.DATA_A (SUMMAND[24]) , .DATA_B (SUMMAND[25]) , .DATA_C (SUMMAND[26]) , .SAVE (INT_SUM[17]) , .CARRY (INT_CARRY[14]) );
FULL_ADDER FA_8 (.DATA_A (SUMMAND[27]) , .DATA_B (SUMMAND[28]) , .DATA_C (SUMMAND[29]) , .SAVE (INT_SUM[18]) , .CARRY (INT_CARRY[15]) );
FULL_ADDER FA_9 (.DATA_A (INT_SUM[17]) , .DATA_B (INT_SUM[18]) , .DATA_C (INT_CARRY[11]) , .SAVE (INT_SUM[19]) , .CARRY (INT_CARRY[16]) );
HALF_ADDER HA_6 (.DATA_A (INT_SUM[19]) , .DATA_B (INT_CARRY[12]) , .SAVE (INT_SUM[20]) , .CARRY (INT_CARRY[13]) );
FLIPFLOP LA_15 (.DIN (INT_SUM[20]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[8]) );
FLIPFLOP LA_16 (.DIN (INT_CARRY[13]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[8]) );
FULL_ADDER FA_10 (.DATA_A (SUMMAND[30]) , .DATA_B (SUMMAND[31]) , .DATA_C (SUMMAND[32]) , .SAVE (INT_SUM[21]) , .CARRY (INT_CARRY[18]) );
HALF_ADDER HA_7 (.DATA_A (SUMMAND[33]) , .DATA_B (SUMMAND[34]) , .SAVE (INT_SUM[22]) , .CARRY (INT_CARRY[19]) );
FULL_ADDER FA_11 (.DATA_A (INT_SUM[21]) , .DATA_B (INT_SUM[22]) , .DATA_C (INT_CARRY[14]) , .SAVE (INT_SUM[23]) , .CARRY (INT_CARRY[20]) );
assign INT_SUM[24] = INT_CARRY[15];
FULL_ADDER FA_12 (.DATA_A (INT_SUM[23]) , .DATA_B (INT_SUM[24]) , .DATA_C (INT_CARRY[16]) , .SAVE (INT_SUM[25]) , .CARRY (INT_CARRY[17]) );
FLIPFLOP LA_17 (.DIN (INT_SUM[25]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[9]) );
FLIPFLOP LA_18 (.DIN (INT_CARRY[17]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[9]) );
FULL_ADDER FA_13 (.DATA_A (SUMMAND[35]) , .DATA_B (SUMMAND[36]) , .DATA_C (SUMMAND[37]) , .SAVE (INT_SUM[26]) , .CARRY (INT_CARRY[22]) );
FULL_ADDER FA_14 (.DATA_A (SUMMAND[38]) , .DATA_B (SUMMAND[39]) , .DATA_C (SUMMAND[40]) , .SAVE (INT_SUM[27]) , .CARRY (INT_CARRY[23]) );
assign INT_SUM[28] = SUMMAND[41];
FULL_ADDER FA_15 (.DATA_A (INT_SUM[26]) , .DATA_B (INT_SUM[27]) , .DATA_C (INT_SUM[28]) , .SAVE (INT_SUM[29]) , .CARRY (INT_CARRY[24]) );
HALF_ADDER HA_8 (.DATA_A (INT_CARRY[18]) , .DATA_B (INT_CARRY[19]) , .SAVE (INT_SUM[30]) , .CARRY (INT_CARRY[25]) );
FULL_ADDER FA_16 (.DATA_A (INT_SUM[29]) , .DATA_B (INT_SUM[30]) , .DATA_C (INT_CARRY[20]) , .SAVE (INT_SUM[31]) , .CARRY (INT_CARRY[21]) );
FLIPFLOP LA_19 (.DIN (INT_SUM[31]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[10]) );
FLIPFLOP LA_20 (.DIN (INT_CARRY[21]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[10]) );
FULL_ADDER FA_17 (.DATA_A (SUMMAND[42]) , .DATA_B (SUMMAND[43]) , .DATA_C (SUMMAND[44]) , .SAVE (INT_SUM[32]) , .CARRY (INT_CARRY[27]) );
FULL_ADDER FA_18 (.DATA_A (SUMMAND[45]) , .DATA_B (SUMMAND[46]) , .DATA_C (SUMMAND[47]) , .SAVE (INT_SUM[33]) , .CARRY (INT_CARRY[28]) );
FULL_ADDER FA_19 (.DATA_A (INT_SUM[32]) , .DATA_B (INT_SUM[33]) , .DATA_C (INT_CARRY[22]) , .SAVE (INT_SUM[34]) , .CARRY (INT_CARRY[29]) );
assign INT_SUM[35] = INT_CARRY[23];
FULL_ADDER FA_20 (.DATA_A (INT_SUM[34]) , .DATA_B (INT_SUM[35]) , .DATA_C (INT_CARRY[24]) , .SAVE (INT_SUM[36]) , .CARRY (INT_CARRY[30]) );
assign INT_SUM[37] = INT_CARRY[25];
HALF_ADDER HA_9 (.DATA_A (INT_SUM[36]) , .DATA_B (INT_SUM[37]) , .SAVE (INT_SUM[38]) , .CARRY (INT_CARRY[26]) );
FLIPFLOP LA_21 (.DIN (INT_SUM[38]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[11]) );
FLIPFLOP LA_22 (.DIN (INT_CARRY[26]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[11]) );
FULL_ADDER FA_21 (.DATA_A (SUMMAND[48]) , .DATA_B (SUMMAND[49]) , .DATA_C (SUMMAND[50]) , .SAVE (INT_SUM[39]) , .CARRY (INT_CARRY[32]) );
FULL_ADDER FA_22 (.DATA_A (SUMMAND[51]) , .DATA_B (SUMMAND[52]) , .DATA_C (SUMMAND[53]) , .SAVE (INT_SUM[40]) , .CARRY (INT_CARRY[33]) );
assign INT_SUM[41] = SUMMAND[54];
assign INT_SUM[42] = SUMMAND[55];
FULL_ADDER FA_23 (.DATA_A (INT_SUM[39]) , .DATA_B (INT_SUM[40]) , .DATA_C (INT_SUM[41]) , .SAVE (INT_SUM[43]) , .CARRY (INT_CARRY[34]) );
FULL_ADDER FA_24 (.DATA_A (INT_SUM[42]) , .DATA_B (INT_CARRY[27]) , .DATA_C (INT_CARRY[28]) , .SAVE (INT_SUM[44]) , .CARRY (INT_CARRY[35]) );
FULL_ADDER FA_25 (.DATA_A (INT_SUM[43]) , .DATA_B (INT_SUM[44]) , .DATA_C (INT_CARRY[29]) , .SAVE (INT_SUM[45]) , .CARRY (INT_CARRY[36]) );
HALF_ADDER HA_10 (.DATA_A (INT_SUM[45]) , .DATA_B (INT_CARRY[30]) , .SAVE (INT_SUM[46]) , .CARRY (INT_CARRY[31]) );
FLIPFLOP LA_23 (.DIN (INT_SUM[46]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[12]) );
FLIPFLOP LA_24 (.DIN (INT_CARRY[31]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[12]) );
FULL_ADDER FA_26 (.DATA_A (SUMMAND[56]) , .DATA_B (SUMMAND[57]) , .DATA_C (SUMMAND[58]) , .SAVE (INT_SUM[47]) , .CARRY (INT_CARRY[38]) );
FULL_ADDER FA_27 (.DATA_A (SUMMAND[59]) , .DATA_B (SUMMAND[60]) , .DATA_C (SUMMAND[61]) , .SAVE (INT_SUM[48]) , .CARRY (INT_CARRY[39]) );
assign INT_SUM[49] = SUMMAND[62];
FULL_ADDER FA_28 (.DATA_A (INT_SUM[47]) , .DATA_B (INT_SUM[48]) , .DATA_C (INT_SUM[49]) , .SAVE (INT_SUM[50]) , .CARRY (INT_CARRY[40]) );
HALF_ADDER HA_11 (.DATA_A (INT_CARRY[32]) , .DATA_B (INT_CARRY[33]) , .SAVE (INT_SUM[51]) , .CARRY (INT_CARRY[41]) );
FULL_ADDER FA_29 (.DATA_A (INT_SUM[50]) , .DATA_B (INT_SUM[51]) , .DATA_C (INT_CARRY[34]) , .SAVE (INT_SUM[52]) , .CARRY (INT_CARRY[42]) );
assign INT_SUM[53] = INT_CARRY[35];
FULL_ADDER FA_30 (.DATA_A (INT_SUM[52]) , .DATA_B (INT_SUM[53]) , .DATA_C (INT_CARRY[36]) , .SAVE (INT_SUM[54]) , .CARRY (INT_CARRY[37]) );
FLIPFLOP LA_25 (.DIN (INT_SUM[54]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[13]) );
FLIPFLOP LA_26 (.DIN (INT_CARRY[37]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[13]) );
FULL_ADDER FA_31 (.DATA_A (SUMMAND[63]) , .DATA_B (SUMMAND[64]) , .DATA_C (SUMMAND[65]) , .SAVE (INT_SUM[55]) , .CARRY (INT_CARRY[44]) );
FULL_ADDER FA_32 (.DATA_A (SUMMAND[66]) , .DATA_B (SUMMAND[67]) , .DATA_C (SUMMAND[68]) , .SAVE (INT_SUM[56]) , .CARRY (INT_CARRY[45]) );
FULL_ADDER FA_33 (.DATA_A (SUMMAND[69]) , .DATA_B (SUMMAND[70]) , .DATA_C (SUMMAND[71]) , .SAVE (INT_SUM[57]) , .CARRY (INT_CARRY[46]) );
FULL_ADDER FA_34 (.DATA_A (INT_SUM[55]) , .DATA_B (INT_SUM[56]) , .DATA_C (INT_SUM[57]) , .SAVE (INT_SUM[58]) , .CARRY (INT_CARRY[47]) );
HALF_ADDER HA_12 (.DATA_A (INT_CARRY[38]) , .DATA_B (INT_CARRY[39]) , .SAVE (INT_SUM[59]) , .CARRY (INT_CARRY[48]) );
FULL_ADDER FA_35 (.DATA_A (INT_SUM[58]) , .DATA_B (INT_SUM[59]) , .DATA_C (INT_CARRY[40]) , .SAVE (INT_SUM[60]) , .CARRY (INT_CARRY[49]) );
assign INT_SUM[61] = INT_CARRY[41];
FULL_ADDER FA_36 (.DATA_A (INT_SUM[60]) , .DATA_B (INT_SUM[61]) , .DATA_C (INT_CARRY[42]) , .SAVE (INT_SUM[62]) , .CARRY (INT_CARRY[43]) );
FLIPFLOP LA_27 (.DIN (INT_SUM[62]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[14]) );
FLIPFLOP LA_28 (.DIN (INT_CARRY[43]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[14]) );
FULL_ADDER FA_37 (.DATA_A (SUMMAND[72]) , .DATA_B (SUMMAND[73]) , .DATA_C (SUMMAND[74]) , .SAVE (INT_SUM[63]) , .CARRY (INT_CARRY[51]) );
FULL_ADDER FA_38 (.DATA_A (SUMMAND[75]) , .DATA_B (SUMMAND[76]) , .DATA_C (SUMMAND[77]) , .SAVE (INT_SUM[64]) , .CARRY (INT_CARRY[52]) );
HALF_ADDER HA_13 (.DATA_A (SUMMAND[78]) , .DATA_B (SUMMAND[79]) , .SAVE (INT_SUM[65]) , .CARRY (INT_CARRY[53]) );
FULL_ADDER FA_39 (.DATA_A (INT_SUM[63]) , .DATA_B (INT_SUM[64]) , .DATA_C (INT_SUM[65]) , .SAVE (INT_SUM[66]) , .CARRY (INT_CARRY[54]) );
FULL_ADDER FA_40 (.DATA_A (INT_CARRY[44]) , .DATA_B (INT_CARRY[45]) , .DATA_C (INT_CARRY[46]) , .SAVE (INT_SUM[67]) , .CARRY (INT_CARRY[55]) );
FULL_ADDER FA_41 (.DATA_A (INT_SUM[66]) , .DATA_B (INT_SUM[67]) , .DATA_C (INT_CARRY[47]) , .SAVE (INT_SUM[68]) , .CARRY (INT_CARRY[56]) );
assign INT_SUM[69] = INT_CARRY[48];
FULL_ADDER FA_42 (.DATA_A (INT_SUM[68]) , .DATA_B (INT_SUM[69]) , .DATA_C (INT_CARRY[49]) , .SAVE (INT_SUM[70]) , .CARRY (INT_CARRY[50]) );
FLIPFLOP LA_29 (.DIN (INT_SUM[70]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[15]) );
FLIPFLOP LA_30 (.DIN (INT_CARRY[50]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[15]) );
FULL_ADDER FA_43 (.DATA_A (SUMMAND[80]) , .DATA_B (SUMMAND[81]) , .DATA_C (SUMMAND[82]) , .SAVE (INT_SUM[71]) , .CARRY (INT_CARRY[58]) );
FULL_ADDER FA_44 (.DATA_A (SUMMAND[83]) , .DATA_B (SUMMAND[84]) , .DATA_C (SUMMAND[85]) , .SAVE (INT_SUM[72]) , .CARRY (INT_CARRY[59]) );
FULL_ADDER FA_45 (.DATA_A (SUMMAND[86]) , .DATA_B (SUMMAND[87]) , .DATA_C (SUMMAND[88]) , .SAVE (INT_SUM[73]) , .CARRY (INT_CARRY[60]) );
assign INT_SUM[74] = SUMMAND[89];
FULL_ADDER FA_46 (.DATA_A (INT_SUM[71]) , .DATA_B (INT_SUM[72]) , .DATA_C (INT_SUM[73]) , .SAVE (INT_SUM[75]) , .CARRY (INT_CARRY[61]) );
FULL_ADDER FA_47 (.DATA_A (INT_SUM[74]) , .DATA_B (INT_CARRY[51]) , .DATA_C (INT_CARRY[52]) , .SAVE (INT_SUM[76]) , .CARRY (INT_CARRY[62]) );
assign INT_SUM[77] = INT_CARRY[53];
FULL_ADDER FA_48 (.DATA_A (INT_SUM[75]) , .DATA_B (INT_SUM[76]) , .DATA_C (INT_SUM[77]) , .SAVE (INT_SUM[78]) , .CARRY (INT_CARRY[63]) );
HALF_ADDER HA_14 (.DATA_A (INT_CARRY[54]) , .DATA_B (INT_CARRY[55]) , .SAVE (INT_SUM[79]) , .CARRY (INT_CARRY[64]) );
FULL_ADDER FA_49 (.DATA_A (INT_SUM[78]) , .DATA_B (INT_SUM[79]) , .DATA_C (INT_CARRY[56]) , .SAVE (INT_SUM[80]) , .CARRY (INT_CARRY[57]) );
FLIPFLOP LA_31 (.DIN (INT_SUM[80]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[16]) );
FLIPFLOP LA_32 (.DIN (INT_CARRY[57]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[16]) );
FULL_ADDER FA_50 (.DATA_A (SUMMAND[90]) , .DATA_B (SUMMAND[91]) , .DATA_C (SUMMAND[92]) , .SAVE (INT_SUM[81]) , .CARRY (INT_CARRY[65]) );
FULL_ADDER FA_51 (.DATA_A (SUMMAND[93]) , .DATA_B (SUMMAND[94]) , .DATA_C (SUMMAND[95]) , .SAVE (INT_SUM[82]) , .CARRY (INT_CARRY[66]) );
FULL_ADDER FA_52 (.DATA_A (SUMMAND[96]) , .DATA_B (SUMMAND[97]) , .DATA_C (SUMMAND[98]) , .SAVE (INT_SUM[83]) , .CARRY (INT_CARRY[67]) );
FULL_ADDER FA_53 (.DATA_A (INT_SUM[81]) , .DATA_B (INT_SUM[82]) , .DATA_C (INT_SUM[83]) , .SAVE (INT_SUM[84]) , .CARRY (INT_CARRY[68]) );
FULL_ADDER FA_54 (.DATA_A (INT_CARRY[58]) , .DATA_B (INT_CARRY[59]) , .DATA_C (INT_CARRY[60]) , .SAVE (INT_SUM[85]) , .CARRY (INT_CARRY[69]) );
FULL_ADDER FA_55 (.DATA_A (INT_SUM[84]) , .DATA_B (INT_SUM[85]) , .DATA_C (INT_CARRY[61]) , .SAVE (INT_SUM[86]) , .CARRY (INT_CARRY[70]) );
assign INT_SUM[87] = INT_CARRY[62];
FULL_ADDER FA_56 (.DATA_A (INT_SUM[86]) , .DATA_B (INT_SUM[87]) , .DATA_C (INT_CARRY[63]) , .SAVE (INT_SUM[88]) , .CARRY (INT_CARRY[71]) );
assign INT_SUM[90] = INT_CARRY[64];
FLIPFLOP LA_33 (.DIN (INT_SUM[88]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[89]) );
FLIPFLOP LA_34 (.DIN (INT_SUM[90]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[91]) );
HALF_ADDER HA_15 (.DATA_A (INT_SUM[89]) , .DATA_B (INT_SUM[91]) , .SAVE (SUM[17]) , .CARRY (CARRY[17]) );
FULL_ADDER FA_57 (.DATA_A (SUMMAND[99]) , .DATA_B (SUMMAND[100]) , .DATA_C (SUMMAND[101]) , .SAVE (INT_SUM[92]) , .CARRY (INT_CARRY[73]) );
FULL_ADDER FA_58 (.DATA_A (SUMMAND[102]) , .DATA_B (SUMMAND[103]) , .DATA_C (SUMMAND[104]) , .SAVE (INT_SUM[93]) , .CARRY (INT_CARRY[74]) );
FULL_ADDER FA_59 (.DATA_A (SUMMAND[105]) , .DATA_B (SUMMAND[106]) , .DATA_C (SUMMAND[107]) , .SAVE (INT_SUM[94]) , .CARRY (INT_CARRY[75]) );
assign INT_SUM[95] = SUMMAND[108];
assign INT_SUM[96] = SUMMAND[109];
FULL_ADDER FA_60 (.DATA_A (INT_SUM[92]) , .DATA_B (INT_SUM[93]) , .DATA_C (INT_SUM[94]) , .SAVE (INT_SUM[97]) , .CARRY (INT_CARRY[76]) );
FULL_ADDER FA_61 (.DATA_A (INT_SUM[95]) , .DATA_B (INT_SUM[96]) , .DATA_C (INT_CARRY[65]) , .SAVE (INT_SUM[98]) , .CARRY (INT_CARRY[77]) );
assign INT_SUM[99] = INT_CARRY[66];
assign INT_SUM[100] = INT_CARRY[67];
FULL_ADDER FA_62 (.DATA_A (INT_SUM[97]) , .DATA_B (INT_SUM[98]) , .DATA_C (INT_SUM[99]) , .SAVE (INT_SUM[101]) , .CARRY (INT_CARRY[78]) );
FULL_ADDER FA_63 (.DATA_A (INT_SUM[100]) , .DATA_B (INT_CARRY[68]) , .DATA_C (INT_CARRY[69]) , .SAVE (INT_SUM[102]) , .CARRY (INT_CARRY[79]) );
FULL_ADDER FA_64 (.DATA_A (INT_SUM[101]) , .DATA_B (INT_SUM[102]) , .DATA_C (INT_CARRY[70]) , .SAVE (INT_SUM[103]) , .CARRY (INT_CARRY[80]) );
FLIPFLOP LA_35 (.DIN (INT_SUM[103]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[104]) );
FLIPFLOP LA_36 (.DIN (INT_CARRY[71]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[72]) );
HALF_ADDER HA_16 (.DATA_A (INT_SUM[104]) , .DATA_B (INT_CARRY[72]) , .SAVE (SUM[18]) , .CARRY (CARRY[18]) );
FULL_ADDER FA_65 (.DATA_A (SUMMAND[110]) , .DATA_B (SUMMAND[111]) , .DATA_C (SUMMAND[112]) , .SAVE (INT_SUM[105]) , .CARRY (INT_CARRY[82]) );
FULL_ADDER FA_66 (.DATA_A (SUMMAND[113]) , .DATA_B (SUMMAND[114]) , .DATA_C (SUMMAND[115]) , .SAVE (INT_SUM[106]) , .CARRY (INT_CARRY[83]) );
FULL_ADDER FA_67 (.DATA_A (SUMMAND[116]) , .DATA_B (SUMMAND[117]) , .DATA_C (SUMMAND[118]) , .SAVE (INT_SUM[107]) , .CARRY (INT_CARRY[84]) );
assign INT_SUM[108] = SUMMAND[119];
FULL_ADDER FA_68 (.DATA_A (INT_SUM[105]) , .DATA_B (INT_SUM[106]) , .DATA_C (INT_SUM[107]) , .SAVE (INT_SUM[109]) , .CARRY (INT_CARRY[85]) );
FULL_ADDER FA_69 (.DATA_A (INT_SUM[108]) , .DATA_B (INT_CARRY[73]) , .DATA_C (INT_CARRY[74]) , .SAVE (INT_SUM[110]) , .CARRY (INT_CARRY[86]) );
assign INT_SUM[111] = INT_CARRY[75];
FULL_ADDER FA_70 (.DATA_A (INT_SUM[109]) , .DATA_B (INT_SUM[110]) , .DATA_C (INT_SUM[111]) , .SAVE (INT_SUM[112]) , .CARRY (INT_CARRY[87]) );
HALF_ADDER HA_17 (.DATA_A (INT_CARRY[76]) , .DATA_B (INT_CARRY[77]) , .SAVE (INT_SUM[113]) , .CARRY (INT_CARRY[88]) );
FULL_ADDER FA_71 (.DATA_A (INT_SUM[112]) , .DATA_B (INT_SUM[113]) , .DATA_C (INT_CARRY[78]) , .SAVE (INT_SUM[114]) , .CARRY (INT_CARRY[89]) );
assign INT_SUM[116] = INT_CARRY[79];
FLIPFLOP LA_37 (.DIN (INT_SUM[114]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[115]) );
FLIPFLOP LA_38 (.DIN (INT_SUM[116]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[117]) );
FLIPFLOP LA_39 (.DIN (INT_CARRY[80]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[81]) );
FULL_ADDER FA_72 (.DATA_A (INT_SUM[115]) , .DATA_B (INT_SUM[117]) , .DATA_C (INT_CARRY[81]) , .SAVE (SUM[19]) , .CARRY (CARRY[19]) );
FULL_ADDER FA_73 (.DATA_A (SUMMAND[120]) , .DATA_B (SUMMAND[121]) , .DATA_C (SUMMAND[122]) , .SAVE (INT_SUM[118]) , .CARRY (INT_CARRY[91]) );
FULL_ADDER FA_74 (.DATA_A (SUMMAND[123]) , .DATA_B (SUMMAND[124]) , .DATA_C (SUMMAND[125]) , .SAVE (INT_SUM[119]) , .CARRY (INT_CARRY[92]) );
FULL_ADDER FA_75 (.DATA_A (SUMMAND[126]) , .DATA_B (SUMMAND[127]) , .DATA_C (SUMMAND[128]) , .SAVE (INT_SUM[120]) , .CARRY (INT_CARRY[93]) );
FULL_ADDER FA_76 (.DATA_A (SUMMAND[129]) , .DATA_B (SUMMAND[130]) , .DATA_C (SUMMAND[131]) , .SAVE (INT_SUM[121]) , .CARRY (INT_CARRY[94]) );
FULL_ADDER FA_77 (.DATA_A (INT_SUM[118]) , .DATA_B (INT_SUM[119]) , .DATA_C (INT_SUM[120]) , .SAVE (INT_SUM[122]) , .CARRY (INT_CARRY[95]) );
FULL_ADDER FA_78 (.DATA_A (INT_SUM[121]) , .DATA_B (INT_CARRY[82]) , .DATA_C (INT_CARRY[83]) , .SAVE (INT_SUM[123]) , .CARRY (INT_CARRY[96]) );
assign INT_SUM[124] = INT_CARRY[84];
FULL_ADDER FA_79 (.DATA_A (INT_SUM[122]) , .DATA_B (INT_SUM[123]) , .DATA_C (INT_SUM[124]) , .SAVE (INT_SUM[125]) , .CARRY (INT_CARRY[97]) );
HALF_ADDER HA_18 (.DATA_A (INT_CARRY[85]) , .DATA_B (INT_CARRY[86]) , .SAVE (INT_SUM[126]) , .CARRY (INT_CARRY[98]) );
FULL_ADDER FA_80 (.DATA_A (INT_SUM[125]) , .DATA_B (INT_SUM[126]) , .DATA_C (INT_CARRY[87]) , .SAVE (INT_SUM[127]) , .CARRY (INT_CARRY[99]) );
assign INT_SUM[129] = INT_CARRY[88];
FLIPFLOP LA_40 (.DIN (INT_SUM[127]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[128]) );
FLIPFLOP LA_41 (.DIN (INT_SUM[129]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[130]) );
FLIPFLOP LA_42 (.DIN (INT_CARRY[89]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[90]) );
FULL_ADDER FA_81 (.DATA_A (INT_SUM[128]) , .DATA_B (INT_SUM[130]) , .DATA_C (INT_CARRY[90]) , .SAVE (SUM[20]) , .CARRY (CARRY[20]) );
FULL_ADDER FA_82 (.DATA_A (SUMMAND[132]) , .DATA_B (SUMMAND[133]) , .DATA_C (SUMMAND[134]) , .SAVE (INT_SUM[131]) , .CARRY (INT_CARRY[101]) );
FULL_ADDER FA_83 (.DATA_A (SUMMAND[135]) , .DATA_B (SUMMAND[136]) , .DATA_C (SUMMAND[137]) , .SAVE (INT_SUM[132]) , .CARRY (INT_CARRY[102]) );
FULL_ADDER FA_84 (.DATA_A (SUMMAND[138]) , .DATA_B (SUMMAND[139]) , .DATA_C (SUMMAND[140]) , .SAVE (INT_SUM[133]) , .CARRY (INT_CARRY[103]) );
assign INT_SUM[134] = SUMMAND[141];
assign INT_SUM[135] = SUMMAND[142];
FULL_ADDER FA_85 (.DATA_A (INT_SUM[131]) , .DATA_B (INT_SUM[132]) , .DATA_C (INT_SUM[133]) , .SAVE (INT_SUM[136]) , .CARRY (INT_CARRY[104]) );
FULL_ADDER FA_86 (.DATA_A (INT_SUM[134]) , .DATA_B (INT_SUM[135]) , .DATA_C (INT_CARRY[91]) , .SAVE (INT_SUM[137]) , .CARRY (INT_CARRY[105]) );
FULL_ADDER FA_87 (.DATA_A (INT_CARRY[92]) , .DATA_B (INT_CARRY[93]) , .DATA_C (INT_CARRY[94]) , .SAVE (INT_SUM[138]) , .CARRY (INT_CARRY[106]) );
FULL_ADDER FA_88 (.DATA_A (INT_SUM[136]) , .DATA_B (INT_SUM[137]) , .DATA_C (INT_SUM[138]) , .SAVE (INT_SUM[139]) , .CARRY (INT_CARRY[107]) );
HALF_ADDER HA_19 (.DATA_A (INT_CARRY[95]) , .DATA_B (INT_CARRY[96]) , .SAVE (INT_SUM[140]) , .CARRY (INT_CARRY[108]) );
FULL_ADDER FA_89 (.DATA_A (INT_SUM[139]) , .DATA_B (INT_SUM[140]) , .DATA_C (INT_CARRY[97]) , .SAVE (INT_SUM[141]) , .CARRY (INT_CARRY[109]) );
assign INT_SUM[143] = INT_CARRY[98];
FLIPFLOP LA_43 (.DIN (INT_SUM[141]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[142]) );
FLIPFLOP LA_44 (.DIN (INT_SUM[143]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[144]) );
FLIPFLOP LA_45 (.DIN (INT_CARRY[99]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[100]) );
FULL_ADDER FA_90 (.DATA_A (INT_SUM[142]) , .DATA_B (INT_SUM[144]) , .DATA_C (INT_CARRY[100]) , .SAVE (SUM[21]) , .CARRY (CARRY[21]) );
FULL_ADDER FA_91 (.DATA_A (SUMMAND[143]) , .DATA_B (SUMMAND[144]) , .DATA_C (SUMMAND[145]) , .SAVE (INT_SUM[145]) , .CARRY (INT_CARRY[111]) );
FULL_ADDER FA_92 (.DATA_A (SUMMAND[146]) , .DATA_B (SUMMAND[147]) , .DATA_C (SUMMAND[148]) , .SAVE (INT_SUM[146]) , .CARRY (INT_CARRY[112]) );
FULL_ADDER FA_93 (.DATA_A (SUMMAND[149]) , .DATA_B (SUMMAND[150]) , .DATA_C (SUMMAND[151]) , .SAVE (INT_SUM[147]) , .CARRY (INT_CARRY[113]) );
FULL_ADDER FA_94 (.DATA_A (SUMMAND[152]) , .DATA_B (SUMMAND[153]) , .DATA_C (SUMMAND[154]) , .SAVE (INT_SUM[148]) , .CARRY (INT_CARRY[114]) );
assign INT_SUM[149] = SUMMAND[155];
FULL_ADDER FA_95 (.DATA_A (INT_SUM[145]) , .DATA_B (INT_SUM[146]) , .DATA_C (INT_SUM[147]) , .SAVE (INT_SUM[150]) , .CARRY (INT_CARRY[115]) );
FULL_ADDER FA_96 (.DATA_A (INT_SUM[148]) , .DATA_B (INT_SUM[149]) , .DATA_C (INT_CARRY[101]) , .SAVE (INT_SUM[151]) , .CARRY (INT_CARRY[116]) );
HALF_ADDER HA_20 (.DATA_A (INT_CARRY[102]) , .DATA_B (INT_CARRY[103]) , .SAVE (INT_SUM[152]) , .CARRY (INT_CARRY[117]) );
FULL_ADDER FA_97 (.DATA_A (INT_SUM[150]) , .DATA_B (INT_SUM[151]) , .DATA_C (INT_SUM[152]) , .SAVE (INT_SUM[153]) , .CARRY (INT_CARRY[118]) );
FULL_ADDER FA_98 (.DATA_A (INT_CARRY[104]) , .DATA_B (INT_CARRY[105]) , .DATA_C (INT_CARRY[106]) , .SAVE (INT_SUM[154]) , .CARRY (INT_CARRY[119]) );
FULL_ADDER FA_99 (.DATA_A (INT_SUM[153]) , .DATA_B (INT_SUM[154]) , .DATA_C (INT_CARRY[107]) , .SAVE (INT_SUM[155]) , .CARRY (INT_CARRY[120]) );
assign INT_SUM[157] = INT_CARRY[108];
FLIPFLOP LA_46 (.DIN (INT_SUM[155]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[156]) );
FLIPFLOP LA_47 (.DIN (INT_SUM[157]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[158]) );
FLIPFLOP LA_48 (.DIN (INT_CARRY[109]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[110]) );
FULL_ADDER FA_100 (.DATA_A (INT_SUM[156]) , .DATA_B (INT_SUM[158]) , .DATA_C (INT_CARRY[110]) , .SAVE (SUM[22]) , .CARRY (CARRY[22]) );
FULL_ADDER FA_101 (.DATA_A (SUMMAND[156]) , .DATA_B (SUMMAND[157]) , .DATA_C (SUMMAND[158]) , .SAVE (INT_SUM[159]) , .CARRY (INT_CARRY[122]) );
FULL_ADDER FA_102 (.DATA_A (SUMMAND[159]) , .DATA_B (SUMMAND[160]) , .DATA_C (SUMMAND[161]) , .SAVE (INT_SUM[160]) , .CARRY (INT_CARRY[123]) );
FULL_ADDER FA_103 (.DATA_A (SUMMAND[162]) , .DATA_B (SUMMAND[163]) , .DATA_C (SUMMAND[164]) , .SAVE (INT_SUM[161]) , .CARRY (INT_CARRY[124]) );
FULL_ADDER FA_104 (.DATA_A (SUMMAND[165]) , .DATA_B (SUMMAND[166]) , .DATA_C (SUMMAND[167]) , .SAVE (INT_SUM[162]) , .CARRY (INT_CARRY[125]) );
FULL_ADDER FA_105 (.DATA_A (INT_SUM[159]) , .DATA_B (INT_SUM[160]) , .DATA_C (INT_SUM[161]) , .SAVE (INT_SUM[163]) , .CARRY (INT_CARRY[126]) );
FULL_ADDER FA_106 (.DATA_A (INT_SUM[162]) , .DATA_B (INT_CARRY[111]) , .DATA_C (INT_CARRY[112]) , .SAVE (INT_SUM[164]) , .CARRY (INT_CARRY[127]) );
HALF_ADDER HA_21 (.DATA_A (INT_CARRY[113]) , .DATA_B (INT_CARRY[114]) , .SAVE (INT_SUM[165]) , .CARRY (INT_CARRY[128]) );
FULL_ADDER FA_107 (.DATA_A (INT_SUM[163]) , .DATA_B (INT_SUM[164]) , .DATA_C (INT_SUM[165]) , .SAVE (INT_SUM[166]) , .CARRY (INT_CARRY[129]) );
FULL_ADDER FA_108 (.DATA_A (INT_CARRY[115]) , .DATA_B (INT_CARRY[116]) , .DATA_C (INT_CARRY[117]) , .SAVE (INT_SUM[167]) , .CARRY (INT_CARRY[130]) );
FULL_ADDER FA_109 (.DATA_A (INT_SUM[166]) , .DATA_B (INT_SUM[167]) , .DATA_C (INT_CARRY[118]) , .SAVE (INT_SUM[168]) , .CARRY (INT_CARRY[131]) );
assign INT_SUM[170] = INT_CARRY[119];
FLIPFLOP LA_49 (.DIN (INT_SUM[168]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[169]) );
FLIPFLOP LA_50 (.DIN (INT_SUM[170]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[171]) );
FLIPFLOP LA_51 (.DIN (INT_CARRY[120]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[121]) );
FULL_ADDER FA_110 (.DATA_A (INT_SUM[169]) , .DATA_B (INT_SUM[171]) , .DATA_C (INT_CARRY[121]) , .SAVE (SUM[23]) , .CARRY (CARRY[23]) );
FULL_ADDER FA_111 (.DATA_A (SUMMAND[168]) , .DATA_B (SUMMAND[169]) , .DATA_C (SUMMAND[170]) , .SAVE (INT_SUM[172]) , .CARRY (INT_CARRY[133]) );
FULL_ADDER FA_112 (.DATA_A (SUMMAND[171]) , .DATA_B (SUMMAND[172]) , .DATA_C (SUMMAND[173]) , .SAVE (INT_SUM[173]) , .CARRY (INT_CARRY[134]) );
FULL_ADDER FA_113 (.DATA_A (SUMMAND[174]) , .DATA_B (SUMMAND[175]) , .DATA_C (SUMMAND[176]) , .SAVE (INT_SUM[174]) , .CARRY (INT_CARRY[135]) );
FULL_ADDER FA_114 (.DATA_A (SUMMAND[177]) , .DATA_B (SUMMAND[178]) , .DATA_C (SUMMAND[179]) , .SAVE (INT_SUM[175]) , .CARRY (INT_CARRY[136]) );
HALF_ADDER HA_22 (.DATA_A (SUMMAND[180]) , .DATA_B (SUMMAND[181]) , .SAVE (INT_SUM[176]) , .CARRY (INT_CARRY[137]) );
FULL_ADDER FA_115 (.DATA_A (INT_SUM[172]) , .DATA_B (INT_SUM[173]) , .DATA_C (INT_SUM[174]) , .SAVE (INT_SUM[177]) , .CARRY (INT_CARRY[138]) );
FULL_ADDER FA_116 (.DATA_A (INT_SUM[175]) , .DATA_B (INT_SUM[176]) , .DATA_C (INT_CARRY[122]) , .SAVE (INT_SUM[178]) , .CARRY (INT_CARRY[139]) );
FULL_ADDER FA_117 (.DATA_A (INT_CARRY[123]) , .DATA_B (INT_CARRY[124]) , .DATA_C (INT_CARRY[125]) , .SAVE (INT_SUM[179]) , .CARRY (INT_CARRY[140]) );
FULL_ADDER FA_118 (.DATA_A (INT_SUM[177]) , .DATA_B (INT_SUM[178]) , .DATA_C (INT_SUM[179]) , .SAVE (INT_SUM[180]) , .CARRY (INT_CARRY[141]) );
FULL_ADDER FA_119 (.DATA_A (INT_CARRY[126]) , .DATA_B (INT_CARRY[127]) , .DATA_C (INT_CARRY[128]) , .SAVE (INT_SUM[181]) , .CARRY (INT_CARRY[142]) );
FULL_ADDER FA_120 (.DATA_A (INT_SUM[180]) , .DATA_B (INT_SUM[181]) , .DATA_C (INT_CARRY[129]) , .SAVE (INT_SUM[182]) , .CARRY (INT_CARRY[143]) );
assign INT_SUM[184] = INT_CARRY[130];
FLIPFLOP LA_52 (.DIN (INT_SUM[182]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[183]) );
FLIPFLOP LA_53 (.DIN (INT_SUM[184]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[185]) );
FLIPFLOP LA_54 (.DIN (INT_CARRY[131]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[132]) );
FULL_ADDER FA_121 (.DATA_A (INT_SUM[183]) , .DATA_B (INT_SUM[185]) , .DATA_C (INT_CARRY[132]) , .SAVE (SUM[24]) , .CARRY (CARRY[24]) );
FULL_ADDER FA_122 (.DATA_A (SUMMAND[182]) , .DATA_B (SUMMAND[183]) , .DATA_C (SUMMAND[184]) , .SAVE (INT_SUM[186]) , .CARRY (INT_CARRY[145]) );
FULL_ADDER FA_123 (.DATA_A (SUMMAND[185]) , .DATA_B (SUMMAND[186]) , .DATA_C (SUMMAND[187]) , .SAVE (INT_SUM[187]) , .CARRY (INT_CARRY[146]) );
FULL_ADDER FA_124 (.DATA_A (SUMMAND[188]) , .DATA_B (SUMMAND[189]) , .DATA_C (SUMMAND[190]) , .SAVE (INT_SUM[188]) , .CARRY (INT_CARRY[147]) );
FULL_ADDER FA_125 (.DATA_A (SUMMAND[191]) , .DATA_B (SUMMAND[192]) , .DATA_C (SUMMAND[193]) , .SAVE (INT_SUM[189]) , .CARRY (INT_CARRY[148]) );
assign INT_SUM[190] = SUMMAND[194];
FULL_ADDER FA_126 (.DATA_A (INT_SUM[186]) , .DATA_B (INT_SUM[187]) , .DATA_C (INT_SUM[188]) , .SAVE (INT_SUM[191]) , .CARRY (INT_CARRY[149]) );
FULL_ADDER FA_127 (.DATA_A (INT_SUM[189]) , .DATA_B (INT_SUM[190]) , .DATA_C (INT_CARRY[133]) , .SAVE (INT_SUM[192]) , .CARRY (INT_CARRY[150]) );
FULL_ADDER FA_128 (.DATA_A (INT_CARRY[134]) , .DATA_B (INT_CARRY[135]) , .DATA_C (INT_CARRY[136]) , .SAVE (INT_SUM[193]) , .CARRY (INT_CARRY[151]) );
assign INT_SUM[194] = INT_CARRY[137];
FULL_ADDER FA_129 (.DATA_A (INT_SUM[191]) , .DATA_B (INT_SUM[192]) , .DATA_C (INT_SUM[193]) , .SAVE (INT_SUM[195]) , .CARRY (INT_CARRY[152]) );
FULL_ADDER FA_130 (.DATA_A (INT_SUM[194]) , .DATA_B (INT_CARRY[138]) , .DATA_C (INT_CARRY[139]) , .SAVE (INT_SUM[196]) , .CARRY (INT_CARRY[153]) );
assign INT_SUM[197] = INT_CARRY[140];
FULL_ADDER FA_131 (.DATA_A (INT_SUM[195]) , .DATA_B (INT_SUM[196]) , .DATA_C (INT_SUM[197]) , .SAVE (INT_SUM[198]) , .CARRY (INT_CARRY[154]) );
HALF_ADDER HA_23 (.DATA_A (INT_CARRY[141]) , .DATA_B (INT_CARRY[142]) , .SAVE (INT_SUM[200]) , .CARRY (INT_CARRY[156]) );
FLIPFLOP LA_55 (.DIN (INT_SUM[198]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[199]) );
FLIPFLOP LA_56 (.DIN (INT_SUM[200]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[201]) );
FLIPFLOP LA_57 (.DIN (INT_CARRY[143]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[144]) );
FULL_ADDER FA_132 (.DATA_A (INT_SUM[199]) , .DATA_B (INT_SUM[201]) , .DATA_C (INT_CARRY[144]) , .SAVE (SUM[25]) , .CARRY (CARRY[25]) );
FULL_ADDER FA_133 (.DATA_A (SUMMAND[195]) , .DATA_B (SUMMAND[196]) , .DATA_C (SUMMAND[197]) , .SAVE (INT_SUM[202]) , .CARRY (INT_CARRY[158]) );
FULL_ADDER FA_134 (.DATA_A (SUMMAND[198]) , .DATA_B (SUMMAND[199]) , .DATA_C (SUMMAND[200]) , .SAVE (INT_SUM[203]) , .CARRY (INT_CARRY[159]) );
FULL_ADDER FA_135 (.DATA_A (SUMMAND[201]) , .DATA_B (SUMMAND[202]) , .DATA_C (SUMMAND[203]) , .SAVE (INT_SUM[204]) , .CARRY (INT_CARRY[160]) );
FULL_ADDER FA_136 (.DATA_A (SUMMAND[204]) , .DATA_B (SUMMAND[205]) , .DATA_C (SUMMAND[206]) , .SAVE (INT_SUM[205]) , .CARRY (INT_CARRY[161]) );
FULL_ADDER FA_137 (.DATA_A (SUMMAND[207]) , .DATA_B (SUMMAND[208]) , .DATA_C (SUMMAND[209]) , .SAVE (INT_SUM[206]) , .CARRY (INT_CARRY[162]) );
FULL_ADDER FA_138 (.DATA_A (INT_SUM[202]) , .DATA_B (INT_SUM[203]) , .DATA_C (INT_SUM[204]) , .SAVE (INT_SUM[207]) , .CARRY (INT_CARRY[163]) );
FULL_ADDER FA_139 (.DATA_A (INT_SUM[205]) , .DATA_B (INT_SUM[206]) , .DATA_C (INT_CARRY[145]) , .SAVE (INT_SUM[208]) , .CARRY (INT_CARRY[164]) );
FULL_ADDER FA_140 (.DATA_A (INT_CARRY[146]) , .DATA_B (INT_CARRY[147]) , .DATA_C (INT_CARRY[148]) , .SAVE (INT_SUM[209]) , .CARRY (INT_CARRY[165]) );
FULL_ADDER FA_141 (.DATA_A (INT_SUM[207]) , .DATA_B (INT_SUM[208]) , .DATA_C (INT_SUM[209]) , .SAVE (INT_SUM[210]) , .CARRY (INT_CARRY[166]) );
FULL_ADDER FA_142 (.DATA_A (INT_CARRY[149]) , .DATA_B (INT_CARRY[150]) , .DATA_C (INT_CARRY[151]) , .SAVE (INT_SUM[211]) , .CARRY (INT_CARRY[167]) );
FULL_ADDER FA_143 (.DATA_A (INT_SUM[210]) , .DATA_B (INT_SUM[211]) , .DATA_C (INT_CARRY[152]) , .SAVE (INT_SUM[212]) , .CARRY (INT_CARRY[168]) );
assign INT_SUM[214] = INT_CARRY[153];
FLIPFLOP LA_58 (.DIN (INT_SUM[212]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[213]) );
FLIPFLOP LA_59 (.DIN (INT_SUM[214]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[215]) );
FLIPFLOP LA_60 (.DIN (INT_CARRY[154]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[155]) );
FULL_ADDER FA_144 (.DATA_A (INT_SUM[213]) , .DATA_B (INT_SUM[215]) , .DATA_C (INT_CARRY[155]) , .SAVE (INT_SUM[216]) , .CARRY (INT_CARRY[170]) );
FLIPFLOP LA_61 (.DIN (INT_CARRY[156]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[157]) );
assign INT_SUM[217] = INT_CARRY[157];
HALF_ADDER HA_24 (.DATA_A (INT_SUM[216]) , .DATA_B (INT_SUM[217]) , .SAVE (SUM[26]) , .CARRY (CARRY[26]) );
FULL_ADDER FA_145 (.DATA_A (SUMMAND[210]) , .DATA_B (SUMMAND[211]) , .DATA_C (SUMMAND[212]) , .SAVE (INT_SUM[218]) , .CARRY (INT_CARRY[171]) );
FULL_ADDER FA_146 (.DATA_A (SUMMAND[213]) , .DATA_B (SUMMAND[214]) , .DATA_C (SUMMAND[215]) , .SAVE (INT_SUM[219]) , .CARRY (INT_CARRY[172]) );
FULL_ADDER FA_147 (.DATA_A (SUMMAND[216]) , .DATA_B (SUMMAND[217]) , .DATA_C (SUMMAND[218]) , .SAVE (INT_SUM[220]) , .CARRY (INT_CARRY[173]) );
FULL_ADDER FA_148 (.DATA_A (SUMMAND[219]) , .DATA_B (SUMMAND[220]) , .DATA_C (SUMMAND[221]) , .SAVE (INT_SUM[221]) , .CARRY (INT_CARRY[174]) );
HALF_ADDER HA_25 (.DATA_A (SUMMAND[222]) , .DATA_B (SUMMAND[223]) , .SAVE (INT_SUM[222]) , .CARRY (INT_CARRY[175]) );
FULL_ADDER FA_149 (.DATA_A (INT_SUM[218]) , .DATA_B (INT_SUM[219]) , .DATA_C (INT_SUM[220]) , .SAVE (INT_SUM[223]) , .CARRY (INT_CARRY[176]) );
FULL_ADDER FA_150 (.DATA_A (INT_SUM[221]) , .DATA_B (INT_SUM[222]) , .DATA_C (INT_CARRY[158]) , .SAVE (INT_SUM[224]) , .CARRY (INT_CARRY[177]) );
FULL_ADDER FA_151 (.DATA_A (INT_CARRY[159]) , .DATA_B (INT_CARRY[160]) , .DATA_C (INT_CARRY[161]) , .SAVE (INT_SUM[225]) , .CARRY (INT_CARRY[178]) );
assign INT_SUM[226] = INT_CARRY[162];
FULL_ADDER FA_152 (.DATA_A (INT_SUM[223]) , .DATA_B (INT_SUM[224]) , .DATA_C (INT_SUM[225]) , .SAVE (INT_SUM[227]) , .CARRY (INT_CARRY[179]) );
FULL_ADDER FA_153 (.DATA_A (INT_SUM[226]) , .DATA_B (INT_CARRY[163]) , .DATA_C (INT_CARRY[164]) , .SAVE (INT_SUM[228]) , .CARRY (INT_CARRY[180]) );
assign INT_SUM[229] = INT_CARRY[165];
FULL_ADDER FA_154 (.DATA_A (INT_SUM[227]) , .DATA_B (INT_SUM[228]) , .DATA_C (INT_SUM[229]) , .SAVE (INT_SUM[230]) , .CARRY (INT_CARRY[181]) );
assign INT_SUM[232] = INT_CARRY[166];
assign INT_SUM[234] = INT_CARRY[167];
FLIPFLOP LA_62 (.DIN (INT_SUM[230]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[231]) );
FLIPFLOP LA_63 (.DIN (INT_SUM[232]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[233]) );
FLIPFLOP LA_64 (.DIN (INT_SUM[234]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[235]) );
FULL_ADDER FA_155 (.DATA_A (INT_SUM[231]) , .DATA_B (INT_SUM[233]) , .DATA_C (INT_SUM[235]) , .SAVE (INT_SUM[236]) , .CARRY (INT_CARRY[183]) );
FLIPFLOP LA_65 (.DIN (INT_CARRY[168]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[169]) );
assign INT_SUM[237] = INT_CARRY[169];
FULL_ADDER FA_156 (.DATA_A (INT_SUM[236]) , .DATA_B (INT_SUM[237]) , .DATA_C (INT_CARRY[170]) , .SAVE (SUM[27]) , .CARRY (CARRY[27]) );
FULL_ADDER FA_157 (.DATA_A (SUMMAND[224]) , .DATA_B (SUMMAND[225]) , .DATA_C (SUMMAND[226]) , .SAVE (INT_SUM[238]) , .CARRY (INT_CARRY[184]) );
FULL_ADDER FA_158 (.DATA_A (SUMMAND[227]) , .DATA_B (SUMMAND[228]) , .DATA_C (SUMMAND[229]) , .SAVE (INT_SUM[239]) , .CARRY (INT_CARRY[185]) );
FULL_ADDER FA_159 (.DATA_A (SUMMAND[230]) , .DATA_B (SUMMAND[231]) , .DATA_C (SUMMAND[232]) , .SAVE (INT_SUM[240]) , .CARRY (INT_CARRY[186]) );
FULL_ADDER FA_160 (.DATA_A (SUMMAND[233]) , .DATA_B (SUMMAND[234]) , .DATA_C (SUMMAND[235]) , .SAVE (INT_SUM[241]) , .CARRY (INT_CARRY[187]) );
FULL_ADDER FA_161 (.DATA_A (SUMMAND[236]) , .DATA_B (SUMMAND[237]) , .DATA_C (SUMMAND[238]) , .SAVE (INT_SUM[242]) , .CARRY (INT_CARRY[188]) );
assign INT_SUM[243] = SUMMAND[239];
FULL_ADDER FA_162 (.DATA_A (INT_SUM[238]) , .DATA_B (INT_SUM[239]) , .DATA_C (INT_SUM[240]) , .SAVE (INT_SUM[244]) , .CARRY (INT_CARRY[189]) );
FULL_ADDER FA_163 (.DATA_A (INT_SUM[241]) , .DATA_B (INT_SUM[242]) , .DATA_C (INT_SUM[243]) , .SAVE (INT_SUM[245]) , .CARRY (INT_CARRY[190]) );
FULL_ADDER FA_164 (.DATA_A (INT_CARRY[171]) , .DATA_B (INT_CARRY[172]) , .DATA_C (INT_CARRY[173]) , .SAVE (INT_SUM[246]) , .CARRY (INT_CARRY[191]) );
assign INT_SUM[247] = INT_CARRY[174];
assign INT_SUM[248] = INT_CARRY[175];
FULL_ADDER FA_165 (.DATA_A (INT_SUM[244]) , .DATA_B (INT_SUM[245]) , .DATA_C (INT_SUM[246]) , .SAVE (INT_SUM[249]) , .CARRY (INT_CARRY[192]) );
FULL_ADDER FA_166 (.DATA_A (INT_SUM[247]) , .DATA_B (INT_SUM[248]) , .DATA_C (INT_CARRY[176]) , .SAVE (INT_SUM[250]) , .CARRY (INT_CARRY[193]) );
assign INT_SUM[251] = INT_CARRY[177];
assign INT_SUM[252] = INT_CARRY[178];
FULL_ADDER FA_167 (.DATA_A (INT_SUM[249]) , .DATA_B (INT_SUM[250]) , .DATA_C (INT_SUM[251]) , .SAVE (INT_SUM[253]) , .CARRY (INT_CARRY[194]) );
FULL_ADDER FA_168 (.DATA_A (INT_SUM[252]) , .DATA_B (INT_CARRY[179]) , .DATA_C (INT_CARRY[180]) , .SAVE (INT_SUM[255]) , .CARRY (INT_CARRY[196]) );
FLIPFLOP LA_66 (.DIN (INT_SUM[253]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[254]) );
FLIPFLOP LA_67 (.DIN (INT_SUM[255]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[256]) );
FLIPFLOP LA_68 (.DIN (INT_CARRY[181]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[182]) );
FULL_ADDER FA_169 (.DATA_A (INT_SUM[254]) , .DATA_B (INT_SUM[256]) , .DATA_C (INT_CARRY[182]) , .SAVE (INT_SUM[257]) , .CARRY (INT_CARRY[198]) );
HALF_ADDER HA_26 (.DATA_A (INT_SUM[257]) , .DATA_B (INT_CARRY[183]) , .SAVE (SUM[28]) , .CARRY (CARRY[28]) );
FULL_ADDER FA_170 (.DATA_A (SUMMAND[240]) , .DATA_B (SUMMAND[241]) , .DATA_C (SUMMAND[242]) , .SAVE (INT_SUM[258]) , .CARRY (INT_CARRY[199]) );
FULL_ADDER FA_171 (.DATA_A (SUMMAND[243]) , .DATA_B (SUMMAND[244]) , .DATA_C (SUMMAND[245]) , .SAVE (INT_SUM[259]) , .CARRY (INT_CARRY[200]) );
FULL_ADDER FA_172 (.DATA_A (SUMMAND[246]) , .DATA_B (SUMMAND[247]) , .DATA_C (SUMMAND[248]) , .SAVE (INT_SUM[260]) , .CARRY (INT_CARRY[201]) );
FULL_ADDER FA_173 (.DATA_A (SUMMAND[249]) , .DATA_B (SUMMAND[250]) , .DATA_C (SUMMAND[251]) , .SAVE (INT_SUM[261]) , .CARRY (INT_CARRY[202]) );
FULL_ADDER FA_174 (.DATA_A (SUMMAND[252]) , .DATA_B (SUMMAND[253]) , .DATA_C (SUMMAND[254]) , .SAVE (INT_SUM[262]) , .CARRY (INT_CARRY[203]) );
FULL_ADDER FA_175 (.DATA_A (INT_SUM[258]) , .DATA_B (INT_SUM[259]) , .DATA_C (INT_SUM[260]) , .SAVE (INT_SUM[263]) , .CARRY (INT_CARRY[204]) );
FULL_ADDER FA_176 (.DATA_A (INT_SUM[261]) , .DATA_B (INT_SUM[262]) , .DATA_C (INT_CARRY[184]) , .SAVE (INT_SUM[264]) , .CARRY (INT_CARRY[205]) );
FULL_ADDER FA_177 (.DATA_A (INT_CARRY[185]) , .DATA_B (INT_CARRY[186]) , .DATA_C (INT_CARRY[187]) , .SAVE (INT_SUM[265]) , .CARRY (INT_CARRY[206]) );
assign INT_SUM[266] = INT_CARRY[188];
FULL_ADDER FA_178 (.DATA_A (INT_SUM[263]) , .DATA_B (INT_SUM[264]) , .DATA_C (INT_SUM[265]) , .SAVE (INT_SUM[267]) , .CARRY (INT_CARRY[207]) );
FULL_ADDER FA_179 (.DATA_A (INT_SUM[266]) , .DATA_B (INT_CARRY[189]) , .DATA_C (INT_CARRY[190]) , .SAVE (INT_SUM[268]) , .CARRY (INT_CARRY[208]) );
assign INT_SUM[269] = INT_CARRY[191];
FULL_ADDER FA_180 (.DATA_A (INT_SUM[267]) , .DATA_B (INT_SUM[268]) , .DATA_C (INT_SUM[269]) , .SAVE (INT_SUM[270]) , .CARRY (INT_CARRY[209]) );
HALF_ADDER HA_27 (.DATA_A (INT_CARRY[192]) , .DATA_B (INT_CARRY[193]) , .SAVE (INT_SUM[272]) , .CARRY (INT_CARRY[211]) );
FLIPFLOP LA_69 (.DIN (INT_SUM[270]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[271]) );
FLIPFLOP LA_70 (.DIN (INT_SUM[272]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[273]) );
FLIPFLOP LA_71 (.DIN (INT_CARRY[194]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[195]) );
FULL_ADDER FA_181 (.DATA_A (INT_SUM[271]) , .DATA_B (INT_SUM[273]) , .DATA_C (INT_CARRY[195]) , .SAVE (INT_SUM[274]) , .CARRY (INT_CARRY[213]) );
FLIPFLOP LA_72 (.DIN (INT_CARRY[196]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[197]) );
assign INT_SUM[275] = INT_CARRY[197];
FULL_ADDER FA_182 (.DATA_A (INT_SUM[274]) , .DATA_B (INT_SUM[275]) , .DATA_C (INT_CARRY[198]) , .SAVE (SUM[29]) , .CARRY (CARRY[29]) );
FULL_ADDER FA_183 (.DATA_A (SUMMAND[255]) , .DATA_B (SUMMAND[256]) , .DATA_C (SUMMAND[257]) , .SAVE (INT_SUM[276]) , .CARRY (INT_CARRY[214]) );
FULL_ADDER FA_184 (.DATA_A (SUMMAND[258]) , .DATA_B (SUMMAND[259]) , .DATA_C (SUMMAND[260]) , .SAVE (INT_SUM[277]) , .CARRY (INT_CARRY[215]) );
FULL_ADDER FA_185 (.DATA_A (SUMMAND[261]) , .DATA_B (SUMMAND[262]) , .DATA_C (SUMMAND[263]) , .SAVE (INT_SUM[278]) , .CARRY (INT_CARRY[216]) );
FULL_ADDER FA_186 (.DATA_A (SUMMAND[264]) , .DATA_B (SUMMAND[265]) , .DATA_C (SUMMAND[266]) , .SAVE (INT_SUM[279]) , .CARRY (INT_CARRY[217]) );
FULL_ADDER FA_187 (.DATA_A (SUMMAND[267]) , .DATA_B (SUMMAND[268]) , .DATA_C (SUMMAND[269]) , .SAVE (INT_SUM[280]) , .CARRY (INT_CARRY[218]) );
assign INT_SUM[281] = SUMMAND[270];
assign INT_SUM[282] = SUMMAND[271];
FULL_ADDER FA_188 (.DATA_A (INT_SUM[276]) , .DATA_B (INT_SUM[277]) , .DATA_C (INT_SUM[278]) , .SAVE (INT_SUM[283]) , .CARRY (INT_CARRY[219]) );
FULL_ADDER FA_189 (.DATA_A (INT_SUM[279]) , .DATA_B (INT_SUM[280]) , .DATA_C (INT_SUM[281]) , .SAVE (INT_SUM[284]) , .CARRY (INT_CARRY[220]) );
FULL_ADDER FA_190 (.DATA_A (INT_SUM[282]) , .DATA_B (INT_CARRY[199]) , .DATA_C (INT_CARRY[200]) , .SAVE (INT_SUM[285]) , .CARRY (INT_CARRY[221]) );
FULL_ADDER FA_191 (.DATA_A (INT_CARRY[201]) , .DATA_B (INT_CARRY[202]) , .DATA_C (INT_CARRY[203]) , .SAVE (INT_SUM[286]) , .CARRY (INT_CARRY[222]) );
FULL_ADDER FA_192 (.DATA_A (INT_SUM[283]) , .DATA_B (INT_SUM[284]) , .DATA_C (INT_SUM[285]) , .SAVE (INT_SUM[287]) , .CARRY (INT_CARRY[223]) );
FULL_ADDER FA_193 (.DATA_A (INT_SUM[286]) , .DATA_B (INT_CARRY[204]) , .DATA_C (INT_CARRY[205]) , .SAVE (INT_SUM[288]) , .CARRY (INT_CARRY[224]) );
assign INT_SUM[289] = INT_CARRY[206];
FULL_ADDER FA_194 (.DATA_A (INT_SUM[287]) , .DATA_B (INT_SUM[288]) , .DATA_C (INT_SUM[289]) , .SAVE (INT_SUM[290]) , .CARRY (INT_CARRY[225]) );
HALF_ADDER HA_28 (.DATA_A (INT_CARRY[207]) , .DATA_B (INT_CARRY[208]) , .SAVE (INT_SUM[292]) , .CARRY (INT_CARRY[227]) );
FLIPFLOP LA_73 (.DIN (INT_SUM[290]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[291]) );
FLIPFLOP LA_74 (.DIN (INT_SUM[292]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[293]) );
FLIPFLOP LA_75 (.DIN (INT_CARRY[209]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[210]) );
FULL_ADDER FA_195 (.DATA_A (INT_SUM[291]) , .DATA_B (INT_SUM[293]) , .DATA_C (INT_CARRY[210]) , .SAVE (INT_SUM[294]) , .CARRY (INT_CARRY[229]) );
FLIPFLOP LA_76 (.DIN (INT_CARRY[211]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[212]) );
assign INT_SUM[295] = INT_CARRY[212];
FULL_ADDER FA_196 (.DATA_A (INT_SUM[294]) , .DATA_B (INT_SUM[295]) , .DATA_C (INT_CARRY[213]) , .SAVE (SUM[30]) , .CARRY (CARRY[30]) );
FULL_ADDER FA_197 (.DATA_A (SUMMAND[272]) , .DATA_B (SUMMAND[273]) , .DATA_C (SUMMAND[274]) , .SAVE (INT_SUM[296]) , .CARRY (INT_CARRY[230]) );
FULL_ADDER FA_198 (.DATA_A (SUMMAND[275]) , .DATA_B (SUMMAND[276]) , .DATA_C (SUMMAND[277]) , .SAVE (INT_SUM[297]) , .CARRY (INT_CARRY[231]) );
FULL_ADDER FA_199 (.DATA_A (SUMMAND[278]) , .DATA_B (SUMMAND[279]) , .DATA_C (SUMMAND[280]) , .SAVE (INT_SUM[298]) , .CARRY (INT_CARRY[232]) );
FULL_ADDER FA_200 (.DATA_A (SUMMAND[281]) , .DATA_B (SUMMAND[282]) , .DATA_C (SUMMAND[283]) , .SAVE (INT_SUM[299]) , .CARRY (INT_CARRY[233]) );
FULL_ADDER FA_201 (.DATA_A (SUMMAND[284]) , .DATA_B (SUMMAND[285]) , .DATA_C (SUMMAND[286]) , .SAVE (INT_SUM[300]) , .CARRY (INT_CARRY[234]) );
assign INT_SUM[301] = SUMMAND[287];
FULL_ADDER FA_202 (.DATA_A (INT_SUM[296]) , .DATA_B (INT_SUM[297]) , .DATA_C (INT_SUM[298]) , .SAVE (INT_SUM[302]) , .CARRY (INT_CARRY[235]) );
FULL_ADDER FA_203 (.DATA_A (INT_SUM[299]) , .DATA_B (INT_SUM[300]) , .DATA_C (INT_SUM[301]) , .SAVE (INT_SUM[303]) , .CARRY (INT_CARRY[236]) );
FULL_ADDER FA_204 (.DATA_A (INT_CARRY[214]) , .DATA_B (INT_CARRY[215]) , .DATA_C (INT_CARRY[216]) , .SAVE (INT_SUM[304]) , .CARRY (INT_CARRY[237]) );
assign INT_SUM[305] = INT_CARRY[217];
assign INT_SUM[306] = INT_CARRY[218];
FULL_ADDER FA_205 (.DATA_A (INT_SUM[302]) , .DATA_B (INT_SUM[303]) , .DATA_C (INT_SUM[304]) , .SAVE (INT_SUM[307]) , .CARRY (INT_CARRY[238]) );
FULL_ADDER FA_206 (.DATA_A (INT_SUM[305]) , .DATA_B (INT_SUM[306]) , .DATA_C (INT_CARRY[219]) , .SAVE (INT_SUM[308]) , .CARRY (INT_CARRY[239]) );
FULL_ADDER FA_207 (.DATA_A (INT_CARRY[220]) , .DATA_B (INT_CARRY[221]) , .DATA_C (INT_CARRY[222]) , .SAVE (INT_SUM[309]) , .CARRY (INT_CARRY[240]) );
FULL_ADDER FA_208 (.DATA_A (INT_SUM[307]) , .DATA_B (INT_SUM[308]) , .DATA_C (INT_SUM[309]) , .SAVE (INT_SUM[310]) , .CARRY (INT_CARRY[241]) );
HALF_ADDER HA_29 (.DATA_A (INT_CARRY[223]) , .DATA_B (INT_CARRY[224]) , .SAVE (INT_SUM[312]) , .CARRY (INT_CARRY[243]) );
FLIPFLOP LA_77 (.DIN (INT_SUM[310]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[311]) );
FLIPFLOP LA_78 (.DIN (INT_SUM[312]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[313]) );
FLIPFLOP LA_79 (.DIN (INT_CARRY[225]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[226]) );
FULL_ADDER FA_209 (.DATA_A (INT_SUM[311]) , .DATA_B (INT_SUM[313]) , .DATA_C (INT_CARRY[226]) , .SAVE (INT_SUM[314]) , .CARRY (INT_CARRY[245]) );
FLIPFLOP LA_80 (.DIN (INT_CARRY[227]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[228]) );
assign INT_SUM[315] = INT_CARRY[228];
FULL_ADDER FA_210 (.DATA_A (INT_SUM[314]) , .DATA_B (INT_SUM[315]) , .DATA_C (INT_CARRY[229]) , .SAVE (SUM[31]) , .CARRY (CARRY[31]) );
FULL_ADDER FA_211 (.DATA_A (SUMMAND[288]) , .DATA_B (SUMMAND[289]) , .DATA_C (SUMMAND[290]) , .SAVE (INT_SUM[316]) , .CARRY (INT_CARRY[246]) );
FULL_ADDER FA_212 (.DATA_A (SUMMAND[291]) , .DATA_B (SUMMAND[292]) , .DATA_C (SUMMAND[293]) , .SAVE (INT_SUM[317]) , .CARRY (INT_CARRY[247]) );
FULL_ADDER FA_213 (.DATA_A (SUMMAND[294]) , .DATA_B (SUMMAND[295]) , .DATA_C (SUMMAND[296]) , .SAVE (INT_SUM[318]) , .CARRY (INT_CARRY[248]) );
FULL_ADDER FA_214 (.DATA_A (SUMMAND[297]) , .DATA_B (SUMMAND[298]) , .DATA_C (SUMMAND[299]) , .SAVE (INT_SUM[319]) , .CARRY (INT_CARRY[249]) );
FULL_ADDER FA_215 (.DATA_A (SUMMAND[300]) , .DATA_B (SUMMAND[301]) , .DATA_C (SUMMAND[302]) , .SAVE (INT_SUM[320]) , .CARRY (INT_CARRY[250]) );
assign INT_SUM[321] = SUMMAND[303];
FULL_ADDER FA_216 (.DATA_A (INT_SUM[316]) , .DATA_B (INT_SUM[317]) , .DATA_C (INT_SUM[318]) , .SAVE (INT_SUM[322]) , .CARRY (INT_CARRY[251]) );
FULL_ADDER FA_217 (.DATA_A (INT_SUM[319]) , .DATA_B (INT_SUM[320]) , .DATA_C (INT_SUM[321]) , .SAVE (INT_SUM[323]) , .CARRY (INT_CARRY[252]) );
FULL_ADDER FA_218 (.DATA_A (INT_CARRY[230]) , .DATA_B (INT_CARRY[231]) , .DATA_C (INT_CARRY[232]) , .SAVE (INT_SUM[324]) , .CARRY (INT_CARRY[253]) );
HALF_ADDER HA_30 (.DATA_A (INT_CARRY[233]) , .DATA_B (INT_CARRY[234]) , .SAVE (INT_SUM[325]) , .CARRY (INT_CARRY[254]) );
FULL_ADDER FA_219 (.DATA_A (INT_SUM[322]) , .DATA_B (INT_SUM[323]) , .DATA_C (INT_SUM[324]) , .SAVE (INT_SUM[326]) , .CARRY (INT_CARRY[255]) );
FULL_ADDER FA_220 (.DATA_A (INT_SUM[325]) , .DATA_B (INT_CARRY[235]) , .DATA_C (INT_CARRY[236]) , .SAVE (INT_SUM[327]) , .CARRY (INT_CARRY[256]) );
assign INT_SUM[328] = INT_CARRY[237];
FULL_ADDER FA_221 (.DATA_A (INT_SUM[326]) , .DATA_B (INT_SUM[327]) , .DATA_C (INT_SUM[328]) , .SAVE (INT_SUM[329]) , .CARRY (INT_CARRY[257]) );
FULL_ADDER FA_222 (.DATA_A (INT_CARRY[238]) , .DATA_B (INT_CARRY[239]) , .DATA_C (INT_CARRY[240]) , .SAVE (INT_SUM[331]) , .CARRY (INT_CARRY[259]) );
FLIPFLOP LA_81 (.DIN (INT_SUM[329]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[330]) );
FLIPFLOP LA_82 (.DIN (INT_SUM[331]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[332]) );
FLIPFLOP LA_83 (.DIN (INT_CARRY[241]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[242]) );
FULL_ADDER FA_223 (.DATA_A (INT_SUM[330]) , .DATA_B (INT_SUM[332]) , .DATA_C (INT_CARRY[242]) , .SAVE (INT_SUM[333]) , .CARRY (INT_CARRY[261]) );
FLIPFLOP LA_84 (.DIN (INT_CARRY[243]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[244]) );
assign INT_SUM[334] = INT_CARRY[244];
FULL_ADDER FA_224 (.DATA_A (INT_SUM[333]) , .DATA_B (INT_SUM[334]) , .DATA_C (INT_CARRY[245]) , .SAVE (SUM[32]) , .CARRY (CARRY[32]) );
FULL_ADDER FA_225 (.DATA_A (SUMMAND[304]) , .DATA_B (SUMMAND[305]) , .DATA_C (SUMMAND[306]) , .SAVE (INT_SUM[335]) , .CARRY (INT_CARRY[262]) );
FULL_ADDER FA_226 (.DATA_A (SUMMAND[307]) , .DATA_B (SUMMAND[308]) , .DATA_C (SUMMAND[309]) , .SAVE (INT_SUM[336]) , .CARRY (INT_CARRY[263]) );
FULL_ADDER FA_227 (.DATA_A (SUMMAND[310]) , .DATA_B (SUMMAND[311]) , .DATA_C (SUMMAND[312]) , .SAVE (INT_SUM[337]) , .CARRY (INT_CARRY[264]) );
FULL_ADDER FA_228 (.DATA_A (SUMMAND[313]) , .DATA_B (SUMMAND[314]) , .DATA_C (SUMMAND[315]) , .SAVE (INT_SUM[338]) , .CARRY (INT_CARRY[265]) );
FULL_ADDER FA_229 (.DATA_A (SUMMAND[316]) , .DATA_B (SUMMAND[317]) , .DATA_C (SUMMAND[318]) , .SAVE (INT_SUM[339]) , .CARRY (INT_CARRY[266]) );
assign INT_SUM[340] = SUMMAND[319];
assign INT_SUM[341] = SUMMAND[320];
FULL_ADDER FA_230 (.DATA_A (INT_SUM[335]) , .DATA_B (INT_SUM[336]) , .DATA_C (INT_SUM[337]) , .SAVE (INT_SUM[342]) , .CARRY (INT_CARRY[267]) );
FULL_ADDER FA_231 (.DATA_A (INT_SUM[338]) , .DATA_B (INT_SUM[339]) , .DATA_C (INT_SUM[340]) , .SAVE (INT_SUM[343]) , .CARRY (INT_CARRY[268]) );
FULL_ADDER FA_232 (.DATA_A (INT_SUM[341]) , .DATA_B (INT_CARRY[246]) , .DATA_C (INT_CARRY[247]) , .SAVE (INT_SUM[344]) , .CARRY (INT_CARRY[269]) );
FULL_ADDER FA_233 (.DATA_A (INT_CARRY[248]) , .DATA_B (INT_CARRY[249]) , .DATA_C (INT_CARRY[250]) , .SAVE (INT_SUM[345]) , .CARRY (INT_CARRY[270]) );
FULL_ADDER FA_234 (.DATA_A (INT_SUM[342]) , .DATA_B (INT_SUM[343]) , .DATA_C (INT_SUM[344]) , .SAVE (INT_SUM[346]) , .CARRY (INT_CARRY[271]) );
FULL_ADDER FA_235 (.DATA_A (INT_SUM[345]) , .DATA_B (INT_CARRY[251]) , .DATA_C (INT_CARRY[252]) , .SAVE (INT_SUM[347]) , .CARRY (INT_CARRY[272]) );
assign INT_SUM[348] = INT_CARRY[253];
assign INT_SUM[349] = INT_CARRY[254];
FULL_ADDER FA_236 (.DATA_A (INT_SUM[346]) , .DATA_B (INT_SUM[347]) , .DATA_C (INT_SUM[348]) , .SAVE (INT_SUM[350]) , .CARRY (INT_CARRY[273]) );
FULL_ADDER FA_237 (.DATA_A (INT_SUM[349]) , .DATA_B (INT_CARRY[255]) , .DATA_C (INT_CARRY[256]) , .SAVE (INT_SUM[352]) , .CARRY (INT_CARRY[275]) );
FLIPFLOP LA_85 (.DIN (INT_SUM[350]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[351]) );
FLIPFLOP LA_86 (.DIN (INT_SUM[352]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[353]) );
FLIPFLOP LA_87 (.DIN (INT_CARRY[257]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[258]) );
FULL_ADDER FA_238 (.DATA_A (INT_SUM[351]) , .DATA_B (INT_SUM[353]) , .DATA_C (INT_CARRY[258]) , .SAVE (INT_SUM[354]) , .CARRY (INT_CARRY[277]) );
FLIPFLOP LA_88 (.DIN (INT_CARRY[259]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[260]) );
assign INT_SUM[355] = INT_CARRY[260];
FULL_ADDER FA_239 (.DATA_A (INT_SUM[354]) , .DATA_B (INT_SUM[355]) , .DATA_C (INT_CARRY[261]) , .SAVE (SUM[33]) , .CARRY (CARRY[33]) );
FULL_ADDER FA_240 (.DATA_A (SUMMAND[321]) , .DATA_B (SUMMAND[322]) , .DATA_C (SUMMAND[323]) , .SAVE (INT_SUM[356]) , .CARRY (INT_CARRY[278]) );
FULL_ADDER FA_241 (.DATA_A (SUMMAND[324]) , .DATA_B (SUMMAND[325]) , .DATA_C (SUMMAND[326]) , .SAVE (INT_SUM[357]) , .CARRY (INT_CARRY[279]) );
FULL_ADDER FA_242 (.DATA_A (SUMMAND[327]) , .DATA_B (SUMMAND[328]) , .DATA_C (SUMMAND[329]) , .SAVE (INT_SUM[358]) , .CARRY (INT_CARRY[280]) );
FULL_ADDER FA_243 (.DATA_A (SUMMAND[330]) , .DATA_B (SUMMAND[331]) , .DATA_C (SUMMAND[332]) , .SAVE (INT_SUM[359]) , .CARRY (INT_CARRY[281]) );
FULL_ADDER FA_244 (.DATA_A (SUMMAND[333]) , .DATA_B (SUMMAND[334]) , .DATA_C (SUMMAND[335]) , .SAVE (INT_SUM[360]) , .CARRY (INT_CARRY[282]) );
assign INT_SUM[361] = SUMMAND[336];
FULL_ADDER FA_245 (.DATA_A (INT_SUM[356]) , .DATA_B (INT_SUM[357]) , .DATA_C (INT_SUM[358]) , .SAVE (INT_SUM[362]) , .CARRY (INT_CARRY[283]) );
FULL_ADDER FA_246 (.DATA_A (INT_SUM[359]) , .DATA_B (INT_SUM[360]) , .DATA_C (INT_SUM[361]) , .SAVE (INT_SUM[363]) , .CARRY (INT_CARRY[284]) );
FULL_ADDER FA_247 (.DATA_A (INT_CARRY[262]) , .DATA_B (INT_CARRY[263]) , .DATA_C (INT_CARRY[264]) , .SAVE (INT_SUM[364]) , .CARRY (INT_CARRY[285]) );
assign INT_SUM[365] = INT_CARRY[265];
assign INT_SUM[366] = INT_CARRY[266];
FULL_ADDER FA_248 (.DATA_A (INT_SUM[362]) , .DATA_B (INT_SUM[363]) , .DATA_C (INT_SUM[364]) , .SAVE (INT_SUM[367]) , .CARRY (INT_CARRY[286]) );
FULL_ADDER FA_249 (.DATA_A (INT_SUM[365]) , .DATA_B (INT_SUM[366]) , .DATA_C (INT_CARRY[267]) , .SAVE (INT_SUM[368]) , .CARRY (INT_CARRY[287]) );
FULL_ADDER FA_250 (.DATA_A (INT_CARRY[268]) , .DATA_B (INT_CARRY[269]) , .DATA_C (INT_CARRY[270]) , .SAVE (INT_SUM[369]) , .CARRY (INT_CARRY[288]) );
FULL_ADDER FA_251 (.DATA_A (INT_SUM[367]) , .DATA_B (INT_SUM[368]) , .DATA_C (INT_SUM[369]) , .SAVE (INT_SUM[370]) , .CARRY (INT_CARRY[289]) );
HALF_ADDER HA_31 (.DATA_A (INT_CARRY[271]) , .DATA_B (INT_CARRY[272]) , .SAVE (INT_SUM[372]) , .CARRY (INT_CARRY[291]) );
FLIPFLOP LA_89 (.DIN (INT_SUM[370]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[371]) );
FLIPFLOP LA_90 (.DIN (INT_SUM[372]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[373]) );
FLIPFLOP LA_91 (.DIN (INT_CARRY[273]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[274]) );
FULL_ADDER FA_252 (.DATA_A (INT_SUM[371]) , .DATA_B (INT_SUM[373]) , .DATA_C (INT_CARRY[274]) , .SAVE (INT_SUM[374]) , .CARRY (INT_CARRY[293]) );
FLIPFLOP LA_92 (.DIN (INT_CARRY[275]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[276]) );
assign INT_SUM[375] = INT_CARRY[276];
FULL_ADDER FA_253 (.DATA_A (INT_SUM[374]) , .DATA_B (INT_SUM[375]) , .DATA_C (INT_CARRY[277]) , .SAVE (SUM[34]) , .CARRY (CARRY[34]) );
FULL_ADDER FA_254 (.DATA_A (SUMMAND[337]) , .DATA_B (SUMMAND[338]) , .DATA_C (SUMMAND[339]) , .SAVE (INT_SUM[376]) , .CARRY (INT_CARRY[294]) );
FULL_ADDER FA_255 (.DATA_A (SUMMAND[340]) , .DATA_B (SUMMAND[341]) , .DATA_C (SUMMAND[342]) , .SAVE (INT_SUM[377]) , .CARRY (INT_CARRY[295]) );
FULL_ADDER FA_256 (.DATA_A (SUMMAND[343]) , .DATA_B (SUMMAND[344]) , .DATA_C (SUMMAND[345]) , .SAVE (INT_SUM[378]) , .CARRY (INT_CARRY[296]) );
FULL_ADDER FA_257 (.DATA_A (SUMMAND[346]) , .DATA_B (SUMMAND[347]) , .DATA_C (SUMMAND[348]) , .SAVE (INT_SUM[379]) , .CARRY (INT_CARRY[297]) );
FULL_ADDER FA_258 (.DATA_A (SUMMAND[349]) , .DATA_B (SUMMAND[350]) , .DATA_C (SUMMAND[351]) , .SAVE (INT_SUM[380]) , .CARRY (INT_CARRY[298]) );
FULL_ADDER FA_259 (.DATA_A (INT_SUM[376]) , .DATA_B (INT_SUM[377]) , .DATA_C (INT_SUM[378]) , .SAVE (INT_SUM[381]) , .CARRY (INT_CARRY[299]) );
FULL_ADDER FA_260 (.DATA_A (INT_SUM[379]) , .DATA_B (INT_SUM[380]) , .DATA_C (INT_CARRY[278]) , .SAVE (INT_SUM[382]) , .CARRY (INT_CARRY[300]) );
FULL_ADDER FA_261 (.DATA_A (INT_CARRY[279]) , .DATA_B (INT_CARRY[280]) , .DATA_C (INT_CARRY[281]) , .SAVE (INT_SUM[383]) , .CARRY (INT_CARRY[301]) );
assign INT_SUM[384] = INT_CARRY[282];
FULL_ADDER FA_262 (.DATA_A (INT_SUM[381]) , .DATA_B (INT_SUM[382]) , .DATA_C (INT_SUM[383]) , .SAVE (INT_SUM[385]) , .CARRY (INT_CARRY[302]) );
FULL_ADDER FA_263 (.DATA_A (INT_SUM[384]) , .DATA_B (INT_CARRY[283]) , .DATA_C (INT_CARRY[284]) , .SAVE (INT_SUM[386]) , .CARRY (INT_CARRY[303]) );
assign INT_SUM[387] = INT_CARRY[285];
FULL_ADDER FA_264 (.DATA_A (INT_SUM[385]) , .DATA_B (INT_SUM[386]) , .DATA_C (INT_SUM[387]) , .SAVE (INT_SUM[388]) , .CARRY (INT_CARRY[304]) );
FULL_ADDER FA_265 (.DATA_A (INT_CARRY[286]) , .DATA_B (INT_CARRY[287]) , .DATA_C (INT_CARRY[288]) , .SAVE (INT_SUM[390]) , .CARRY (INT_CARRY[306]) );
FLIPFLOP LA_93 (.DIN (INT_SUM[388]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[389]) );
FLIPFLOP LA_94 (.DIN (INT_SUM[390]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[391]) );
FLIPFLOP LA_95 (.DIN (INT_CARRY[289]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[290]) );
FULL_ADDER FA_266 (.DATA_A (INT_SUM[389]) , .DATA_B (INT_SUM[391]) , .DATA_C (INT_CARRY[290]) , .SAVE (INT_SUM[392]) , .CARRY (INT_CARRY[308]) );
FLIPFLOP LA_96 (.DIN (INT_CARRY[291]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[292]) );
assign INT_SUM[393] = INT_CARRY[292];
FULL_ADDER FA_267 (.DATA_A (INT_SUM[392]) , .DATA_B (INT_SUM[393]) , .DATA_C (INT_CARRY[293]) , .SAVE (SUM[35]) , .CARRY (CARRY[35]) );
FULL_ADDER FA_268 (.DATA_A (SUMMAND[352]) , .DATA_B (SUMMAND[353]) , .DATA_C (SUMMAND[354]) , .SAVE (INT_SUM[394]) , .CARRY (INT_CARRY[309]) );
FULL_ADDER FA_269 (.DATA_A (SUMMAND[355]) , .DATA_B (SUMMAND[356]) , .DATA_C (SUMMAND[357]) , .SAVE (INT_SUM[395]) , .CARRY (INT_CARRY[310]) );
FULL_ADDER FA_270 (.DATA_A (SUMMAND[358]) , .DATA_B (SUMMAND[359]) , .DATA_C (SUMMAND[360]) , .SAVE (INT_SUM[396]) , .CARRY (INT_CARRY[311]) );
FULL_ADDER FA_271 (.DATA_A (SUMMAND[361]) , .DATA_B (SUMMAND[362]) , .DATA_C (SUMMAND[363]) , .SAVE (INT_SUM[397]) , .CARRY (INT_CARRY[312]) );
FULL_ADDER FA_272 (.DATA_A (SUMMAND[364]) , .DATA_B (SUMMAND[365]) , .DATA_C (SUMMAND[366]) , .SAVE (INT_SUM[398]) , .CARRY (INT_CARRY[313]) );
FULL_ADDER FA_273 (.DATA_A (INT_SUM[394]) , .DATA_B (INT_SUM[395]) , .DATA_C (INT_SUM[396]) , .SAVE (INT_SUM[399]) , .CARRY (INT_CARRY[314]) );
FULL_ADDER FA_274 (.DATA_A (INT_SUM[397]) , .DATA_B (INT_SUM[398]) , .DATA_C (INT_CARRY[294]) , .SAVE (INT_SUM[400]) , .CARRY (INT_CARRY[315]) );
FULL_ADDER FA_275 (.DATA_A (INT_CARRY[295]) , .DATA_B (INT_CARRY[296]) , .DATA_C (INT_CARRY[297]) , .SAVE (INT_SUM[401]) , .CARRY (INT_CARRY[316]) );
assign INT_SUM[402] = INT_CARRY[298];
FULL_ADDER FA_276 (.DATA_A (INT_SUM[399]) , .DATA_B (INT_SUM[400]) , .DATA_C (INT_SUM[401]) , .SAVE (INT_SUM[403]) , .CARRY (INT_CARRY[317]) );
FULL_ADDER FA_277 (.DATA_A (INT_SUM[402]) , .DATA_B (INT_CARRY[299]) , .DATA_C (INT_CARRY[300]) , .SAVE (INT_SUM[404]) , .CARRY (INT_CARRY[318]) );
assign INT_SUM[405] = INT_CARRY[301];
FULL_ADDER FA_278 (.DATA_A (INT_SUM[403]) , .DATA_B (INT_SUM[404]) , .DATA_C (INT_SUM[405]) , .SAVE (INT_SUM[406]) , .CARRY (INT_CARRY[319]) );
HALF_ADDER HA_32 (.DATA_A (INT_CARRY[302]) , .DATA_B (INT_CARRY[303]) , .SAVE (INT_SUM[408]) , .CARRY (INT_CARRY[321]) );
FLIPFLOP LA_97 (.DIN (INT_SUM[406]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[407]) );
FLIPFLOP LA_98 (.DIN (INT_SUM[408]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[409]) );
FLIPFLOP LA_99 (.DIN (INT_CARRY[304]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[305]) );
FULL_ADDER FA_279 (.DATA_A (INT_SUM[407]) , .DATA_B (INT_SUM[409]) , .DATA_C (INT_CARRY[305]) , .SAVE (INT_SUM[410]) , .CARRY (INT_CARRY[323]) );
FLIPFLOP LA_100 (.DIN (INT_CARRY[306]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[307]) );
assign INT_SUM[411] = INT_CARRY[307];
FULL_ADDER FA_280 (.DATA_A (INT_SUM[410]) , .DATA_B (INT_SUM[411]) , .DATA_C (INT_CARRY[308]) , .SAVE (SUM[36]) , .CARRY (CARRY[36]) );
FULL_ADDER FA_281 (.DATA_A (SUMMAND[367]) , .DATA_B (SUMMAND[368]) , .DATA_C (SUMMAND[369]) , .SAVE (INT_SUM[412]) , .CARRY (INT_CARRY[324]) );
FULL_ADDER FA_282 (.DATA_A (SUMMAND[370]) , .DATA_B (SUMMAND[371]) , .DATA_C (SUMMAND[372]) , .SAVE (INT_SUM[413]) , .CARRY (INT_CARRY[325]) );
FULL_ADDER FA_283 (.DATA_A (SUMMAND[373]) , .DATA_B (SUMMAND[374]) , .DATA_C (SUMMAND[375]) , .SAVE (INT_SUM[414]) , .CARRY (INT_CARRY[326]) );
FULL_ADDER FA_284 (.DATA_A (SUMMAND[376]) , .DATA_B (SUMMAND[377]) , .DATA_C (SUMMAND[378]) , .SAVE (INT_SUM[415]) , .CARRY (INT_CARRY[327]) );
HALF_ADDER HA_33 (.DATA_A (SUMMAND[379]) , .DATA_B (SUMMAND[380]) , .SAVE (INT_SUM[416]) , .CARRY (INT_CARRY[328]) );
FULL_ADDER FA_285 (.DATA_A (INT_SUM[412]) , .DATA_B (INT_SUM[413]) , .DATA_C (INT_SUM[414]) , .SAVE (INT_SUM[417]) , .CARRY (INT_CARRY[329]) );
FULL_ADDER FA_286 (.DATA_A (INT_SUM[415]) , .DATA_B (INT_SUM[416]) , .DATA_C (INT_CARRY[309]) , .SAVE (INT_SUM[418]) , .CARRY (INT_CARRY[330]) );
FULL_ADDER FA_287 (.DATA_A (INT_CARRY[310]) , .DATA_B (INT_CARRY[311]) , .DATA_C (INT_CARRY[312]) , .SAVE (INT_SUM[419]) , .CARRY (INT_CARRY[331]) );
assign INT_SUM[420] = INT_CARRY[313];
FULL_ADDER FA_288 (.DATA_A (INT_SUM[417]) , .DATA_B (INT_SUM[418]) , .DATA_C (INT_SUM[419]) , .SAVE (INT_SUM[421]) , .CARRY (INT_CARRY[332]) );
FULL_ADDER FA_289 (.DATA_A (INT_SUM[420]) , .DATA_B (INT_CARRY[314]) , .DATA_C (INT_CARRY[315]) , .SAVE (INT_SUM[422]) , .CARRY (INT_CARRY[333]) );
assign INT_SUM[423] = INT_CARRY[316];
FULL_ADDER FA_290 (.DATA_A (INT_SUM[421]) , .DATA_B (INT_SUM[422]) , .DATA_C (INT_SUM[423]) , .SAVE (INT_SUM[424]) , .CARRY (INT_CARRY[334]) );
HALF_ADDER HA_34 (.DATA_A (INT_CARRY[317]) , .DATA_B (INT_CARRY[318]) , .SAVE (INT_SUM[426]) , .CARRY (INT_CARRY[336]) );
FLIPFLOP LA_101 (.DIN (INT_SUM[424]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[425]) );
FLIPFLOP LA_102 (.DIN (INT_SUM[426]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[427]) );
FLIPFLOP LA_103 (.DIN (INT_CARRY[319]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[320]) );
FULL_ADDER FA_291 (.DATA_A (INT_SUM[425]) , .DATA_B (INT_SUM[427]) , .DATA_C (INT_CARRY[320]) , .SAVE (INT_SUM[428]) , .CARRY (INT_CARRY[338]) );
FLIPFLOP LA_104 (.DIN (INT_CARRY[321]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[322]) );
assign INT_SUM[429] = INT_CARRY[322];
FULL_ADDER FA_292 (.DATA_A (INT_SUM[428]) , .DATA_B (INT_SUM[429]) , .DATA_C (INT_CARRY[323]) , .SAVE (SUM[37]) , .CARRY (CARRY[37]) );
FULL_ADDER FA_293 (.DATA_A (SUMMAND[381]) , .DATA_B (SUMMAND[382]) , .DATA_C (SUMMAND[383]) , .SAVE (INT_SUM[430]) , .CARRY (INT_CARRY[339]) );
FULL_ADDER FA_294 (.DATA_A (SUMMAND[384]) , .DATA_B (SUMMAND[385]) , .DATA_C (SUMMAND[386]) , .SAVE (INT_SUM[431]) , .CARRY (INT_CARRY[340]) );
FULL_ADDER FA_295 (.DATA_A (SUMMAND[387]) , .DATA_B (SUMMAND[388]) , .DATA_C (SUMMAND[389]) , .SAVE (INT_SUM[432]) , .CARRY (INT_CARRY[341]) );
FULL_ADDER FA_296 (.DATA_A (SUMMAND[390]) , .DATA_B (SUMMAND[391]) , .DATA_C (SUMMAND[392]) , .SAVE (INT_SUM[433]) , .CARRY (INT_CARRY[342]) );
HALF_ADDER HA_35 (.DATA_A (SUMMAND[393]) , .DATA_B (SUMMAND[394]) , .SAVE (INT_SUM[434]) , .CARRY (INT_CARRY[343]) );
FULL_ADDER FA_297 (.DATA_A (INT_SUM[430]) , .DATA_B (INT_SUM[431]) , .DATA_C (INT_SUM[432]) , .SAVE (INT_SUM[435]) , .CARRY (INT_CARRY[344]) );
FULL_ADDER FA_298 (.DATA_A (INT_SUM[433]) , .DATA_B (INT_SUM[434]) , .DATA_C (INT_CARRY[324]) , .SAVE (INT_SUM[436]) , .CARRY (INT_CARRY[345]) );
FULL_ADDER FA_299 (.DATA_A (INT_CARRY[325]) , .DATA_B (INT_CARRY[326]) , .DATA_C (INT_CARRY[327]) , .SAVE (INT_SUM[437]) , .CARRY (INT_CARRY[346]) );
assign INT_SUM[438] = INT_CARRY[328];
FULL_ADDER FA_300 (.DATA_A (INT_SUM[435]) , .DATA_B (INT_SUM[436]) , .DATA_C (INT_SUM[437]) , .SAVE (INT_SUM[439]) , .CARRY (INT_CARRY[347]) );
FULL_ADDER FA_301 (.DATA_A (INT_SUM[438]) , .DATA_B (INT_CARRY[329]) , .DATA_C (INT_CARRY[330]) , .SAVE (INT_SUM[440]) , .CARRY (INT_CARRY[348]) );
assign INT_SUM[441] = INT_CARRY[331];
FULL_ADDER FA_302 (.DATA_A (INT_SUM[439]) , .DATA_B (INT_SUM[440]) , .DATA_C (INT_SUM[441]) , .SAVE (INT_SUM[442]) , .CARRY (INT_CARRY[349]) );
HALF_ADDER HA_36 (.DATA_A (INT_CARRY[332]) , .DATA_B (INT_CARRY[333]) , .SAVE (INT_SUM[444]) , .CARRY (INT_CARRY[351]) );
FLIPFLOP LA_105 (.DIN (INT_SUM[442]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[443]) );
FLIPFLOP LA_106 (.DIN (INT_SUM[444]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[445]) );
FLIPFLOP LA_107 (.DIN (INT_CARRY[334]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[335]) );
FULL_ADDER FA_303 (.DATA_A (INT_SUM[443]) , .DATA_B (INT_SUM[445]) , .DATA_C (INT_CARRY[335]) , .SAVE (INT_SUM[446]) , .CARRY (INT_CARRY[353]) );
FLIPFLOP LA_108 (.DIN (INT_CARRY[336]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[337]) );
assign INT_SUM[447] = INT_CARRY[337];
FULL_ADDER FA_304 (.DATA_A (INT_SUM[446]) , .DATA_B (INT_SUM[447]) , .DATA_C (INT_CARRY[338]) , .SAVE (SUM[38]) , .CARRY (CARRY[38]) );
FULL_ADDER FA_305 (.DATA_A (SUMMAND[395]) , .DATA_B (SUMMAND[396]) , .DATA_C (SUMMAND[397]) , .SAVE (INT_SUM[448]) , .CARRY (INT_CARRY[354]) );
FULL_ADDER FA_306 (.DATA_A (SUMMAND[398]) , .DATA_B (SUMMAND[399]) , .DATA_C (SUMMAND[400]) , .SAVE (INT_SUM[449]) , .CARRY (INT_CARRY[355]) );
FULL_ADDER FA_307 (.DATA_A (SUMMAND[401]) , .DATA_B (SUMMAND[402]) , .DATA_C (SUMMAND[403]) , .SAVE (INT_SUM[450]) , .CARRY (INT_CARRY[356]) );
FULL_ADDER FA_308 (.DATA_A (SUMMAND[404]) , .DATA_B (SUMMAND[405]) , .DATA_C (SUMMAND[406]) , .SAVE (INT_SUM[451]) , .CARRY (INT_CARRY[357]) );
assign INT_SUM[452] = SUMMAND[407];
FULL_ADDER FA_309 (.DATA_A (INT_SUM[448]) , .DATA_B (INT_SUM[449]) , .DATA_C (INT_SUM[450]) , .SAVE (INT_SUM[453]) , .CARRY (INT_CARRY[358]) );
FULL_ADDER FA_310 (.DATA_A (INT_SUM[451]) , .DATA_B (INT_SUM[452]) , .DATA_C (INT_CARRY[339]) , .SAVE (INT_SUM[454]) , .CARRY (INT_CARRY[359]) );
FULL_ADDER FA_311 (.DATA_A (INT_CARRY[340]) , .DATA_B (INT_CARRY[341]) , .DATA_C (INT_CARRY[342]) , .SAVE (INT_SUM[455]) , .CARRY (INT_CARRY[360]) );
assign INT_SUM[456] = INT_CARRY[343];
FULL_ADDER FA_312 (.DATA_A (INT_SUM[453]) , .DATA_B (INT_SUM[454]) , .DATA_C (INT_SUM[455]) , .SAVE (INT_SUM[457]) , .CARRY (INT_CARRY[361]) );
FULL_ADDER FA_313 (.DATA_A (INT_SUM[456]) , .DATA_B (INT_CARRY[344]) , .DATA_C (INT_CARRY[345]) , .SAVE (INT_SUM[458]) , .CARRY (INT_CARRY[362]) );
assign INT_SUM[459] = INT_CARRY[346];
FULL_ADDER FA_314 (.DATA_A (INT_SUM[457]) , .DATA_B (INT_SUM[458]) , .DATA_C (INT_SUM[459]) , .SAVE (INT_SUM[460]) , .CARRY (INT_CARRY[363]) );
HALF_ADDER HA_37 (.DATA_A (INT_CARRY[347]) , .DATA_B (INT_CARRY[348]) , .SAVE (INT_SUM[462]) , .CARRY (INT_CARRY[365]) );
FLIPFLOP LA_109 (.DIN (INT_SUM[460]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[461]) );
FLIPFLOP LA_110 (.DIN (INT_SUM[462]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[463]) );
FLIPFLOP LA_111 (.DIN (INT_CARRY[349]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[350]) );
FULL_ADDER FA_315 (.DATA_A (INT_SUM[461]) , .DATA_B (INT_SUM[463]) , .DATA_C (INT_CARRY[350]) , .SAVE (INT_SUM[464]) , .CARRY (INT_CARRY[367]) );
FLIPFLOP LA_112 (.DIN (INT_CARRY[351]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[352]) );
assign INT_SUM[465] = INT_CARRY[352];
FULL_ADDER FA_316 (.DATA_A (INT_SUM[464]) , .DATA_B (INT_SUM[465]) , .DATA_C (INT_CARRY[353]) , .SAVE (SUM[39]) , .CARRY (CARRY[39]) );
FULL_ADDER FA_317 (.DATA_A (SUMMAND[408]) , .DATA_B (SUMMAND[409]) , .DATA_C (SUMMAND[410]) , .SAVE (INT_SUM[466]) , .CARRY (INT_CARRY[368]) );
FULL_ADDER FA_318 (.DATA_A (SUMMAND[411]) , .DATA_B (SUMMAND[412]) , .DATA_C (SUMMAND[413]) , .SAVE (INT_SUM[467]) , .CARRY (INT_CARRY[369]) );
FULL_ADDER FA_319 (.DATA_A (SUMMAND[414]) , .DATA_B (SUMMAND[415]) , .DATA_C (SUMMAND[416]) , .SAVE (INT_SUM[468]) , .CARRY (INT_CARRY[370]) );
FULL_ADDER FA_320 (.DATA_A (SUMMAND[417]) , .DATA_B (SUMMAND[418]) , .DATA_C (SUMMAND[419]) , .SAVE (INT_SUM[469]) , .CARRY (INT_CARRY[371]) );
FULL_ADDER FA_321 (.DATA_A (SUMMAND[420]) , .DATA_B (INT_CARRY[354]) , .DATA_C (INT_CARRY[355]) , .SAVE (INT_SUM[470]) , .CARRY (INT_CARRY[372]) );
assign INT_SUM[471] = INT_CARRY[356];
assign INT_SUM[472] = INT_CARRY[357];
FULL_ADDER FA_322 (.DATA_A (INT_SUM[466]) , .DATA_B (INT_SUM[467]) , .DATA_C (INT_SUM[468]) , .SAVE (INT_SUM[473]) , .CARRY (INT_CARRY[373]) );
FULL_ADDER FA_323 (.DATA_A (INT_SUM[469]) , .DATA_B (INT_SUM[470]) , .DATA_C (INT_SUM[471]) , .SAVE (INT_SUM[474]) , .CARRY (INT_CARRY[374]) );
FULL_ADDER FA_324 (.DATA_A (INT_SUM[472]) , .DATA_B (INT_CARRY[358]) , .DATA_C (INT_CARRY[359]) , .SAVE (INT_SUM[475]) , .CARRY (INT_CARRY[375]) );
assign INT_SUM[476] = INT_CARRY[360];
FULL_ADDER FA_325 (.DATA_A (INT_SUM[473]) , .DATA_B (INT_SUM[474]) , .DATA_C (INT_SUM[475]) , .SAVE (INT_SUM[477]) , .CARRY (INT_CARRY[376]) );
FULL_ADDER FA_326 (.DATA_A (INT_SUM[476]) , .DATA_B (INT_CARRY[361]) , .DATA_C (INT_CARRY[362]) , .SAVE (INT_SUM[479]) , .CARRY (INT_CARRY[378]) );
FLIPFLOP LA_113 (.DIN (INT_SUM[477]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[478]) );
FLIPFLOP LA_114 (.DIN (INT_SUM[479]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[480]) );
FLIPFLOP LA_115 (.DIN (INT_CARRY[363]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[364]) );
FULL_ADDER FA_327 (.DATA_A (INT_SUM[478]) , .DATA_B (INT_SUM[480]) , .DATA_C (INT_CARRY[364]) , .SAVE (INT_SUM[481]) , .CARRY (INT_CARRY[380]) );
FLIPFLOP LA_116 (.DIN (INT_CARRY[365]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[366]) );
assign INT_SUM[482] = INT_CARRY[366];
FULL_ADDER FA_328 (.DATA_A (INT_SUM[481]) , .DATA_B (INT_SUM[482]) , .DATA_C (INT_CARRY[367]) , .SAVE (SUM[40]) , .CARRY (CARRY[40]) );
FULL_ADDER FA_329 (.DATA_A (SUMMAND[421]) , .DATA_B (SUMMAND[422]) , .DATA_C (SUMMAND[423]) , .SAVE (INT_SUM[483]) , .CARRY (INT_CARRY[381]) );
FULL_ADDER FA_330 (.DATA_A (SUMMAND[424]) , .DATA_B (SUMMAND[425]) , .DATA_C (SUMMAND[426]) , .SAVE (INT_SUM[484]) , .CARRY (INT_CARRY[382]) );
FULL_ADDER FA_331 (.DATA_A (SUMMAND[427]) , .DATA_B (SUMMAND[428]) , .DATA_C (SUMMAND[429]) , .SAVE (INT_SUM[485]) , .CARRY (INT_CARRY[383]) );
FULL_ADDER FA_332 (.DATA_A (SUMMAND[430]) , .DATA_B (SUMMAND[431]) , .DATA_C (SUMMAND[432]) , .SAVE (INT_SUM[486]) , .CARRY (INT_CARRY[384]) );
FULL_ADDER FA_333 (.DATA_A (INT_SUM[483]) , .DATA_B (INT_SUM[484]) , .DATA_C (INT_SUM[485]) , .SAVE (INT_SUM[487]) , .CARRY (INT_CARRY[385]) );
FULL_ADDER FA_334 (.DATA_A (INT_SUM[486]) , .DATA_B (INT_CARRY[368]) , .DATA_C (INT_CARRY[369]) , .SAVE (INT_SUM[488]) , .CARRY (INT_CARRY[386]) );
FULL_ADDER FA_335 (.DATA_A (INT_CARRY[370]) , .DATA_B (INT_CARRY[371]) , .DATA_C (INT_CARRY[372]) , .SAVE (INT_SUM[489]) , .CARRY (INT_CARRY[387]) );
FULL_ADDER FA_336 (.DATA_A (INT_SUM[487]) , .DATA_B (INT_SUM[488]) , .DATA_C (INT_SUM[489]) , .SAVE (INT_SUM[490]) , .CARRY (INT_CARRY[388]) );
FULL_ADDER FA_337 (.DATA_A (INT_CARRY[373]) , .DATA_B (INT_CARRY[374]) , .DATA_C (INT_CARRY[375]) , .SAVE (INT_SUM[492]) , .CARRY (INT_CARRY[390]) );
FLIPFLOP LA_117 (.DIN (INT_SUM[490]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[491]) );
FLIPFLOP LA_118 (.DIN (INT_SUM[492]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[493]) );
FLIPFLOP LA_119 (.DIN (INT_CARRY[376]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[377]) );
FULL_ADDER FA_338 (.DATA_A (INT_SUM[491]) , .DATA_B (INT_SUM[493]) , .DATA_C (INT_CARRY[377]) , .SAVE (INT_SUM[494]) , .CARRY (INT_CARRY[392]) );
FLIPFLOP LA_120 (.DIN (INT_CARRY[378]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[379]) );
assign INT_SUM[495] = INT_CARRY[379];
FULL_ADDER FA_339 (.DATA_A (INT_SUM[494]) , .DATA_B (INT_SUM[495]) , .DATA_C (INT_CARRY[380]) , .SAVE (SUM[41]) , .CARRY (CARRY[41]) );
FULL_ADDER FA_340 (.DATA_A (SUMMAND[433]) , .DATA_B (SUMMAND[434]) , .DATA_C (SUMMAND[435]) , .SAVE (INT_SUM[496]) , .CARRY (INT_CARRY[393]) );
FULL_ADDER FA_341 (.DATA_A (SUMMAND[436]) , .DATA_B (SUMMAND[437]) , .DATA_C (SUMMAND[438]) , .SAVE (INT_SUM[497]) , .CARRY (INT_CARRY[394]) );
FULL_ADDER FA_342 (.DATA_A (SUMMAND[439]) , .DATA_B (SUMMAND[440]) , .DATA_C (SUMMAND[441]) , .SAVE (INT_SUM[498]) , .CARRY (INT_CARRY[395]) );
FULL_ADDER FA_343 (.DATA_A (SUMMAND[442]) , .DATA_B (SUMMAND[443]) , .DATA_C (SUMMAND[444]) , .SAVE (INT_SUM[499]) , .CARRY (INT_CARRY[396]) );
FULL_ADDER FA_344 (.DATA_A (INT_SUM[496]) , .DATA_B (INT_SUM[497]) , .DATA_C (INT_SUM[498]) , .SAVE (INT_SUM[500]) , .CARRY (INT_CARRY[397]) );
FULL_ADDER FA_345 (.DATA_A (INT_SUM[499]) , .DATA_B (INT_CARRY[381]) , .DATA_C (INT_CARRY[382]) , .SAVE (INT_SUM[501]) , .CARRY (INT_CARRY[398]) );
HALF_ADDER HA_38 (.DATA_A (INT_CARRY[383]) , .DATA_B (INT_CARRY[384]) , .SAVE (INT_SUM[502]) , .CARRY (INT_CARRY[399]) );
FULL_ADDER FA_346 (.DATA_A (INT_SUM[500]) , .DATA_B (INT_SUM[501]) , .DATA_C (INT_SUM[502]) , .SAVE (INT_SUM[503]) , .CARRY (INT_CARRY[400]) );
FULL_ADDER FA_347 (.DATA_A (INT_CARRY[385]) , .DATA_B (INT_CARRY[386]) , .DATA_C (INT_CARRY[387]) , .SAVE (INT_SUM[505]) , .CARRY (INT_CARRY[402]) );
FLIPFLOP LA_121 (.DIN (INT_SUM[503]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[504]) );
FLIPFLOP LA_122 (.DIN (INT_SUM[505]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[506]) );
FLIPFLOP LA_123 (.DIN (INT_CARRY[388]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[389]) );
FULL_ADDER FA_348 (.DATA_A (INT_SUM[504]) , .DATA_B (INT_SUM[506]) , .DATA_C (INT_CARRY[389]) , .SAVE (INT_SUM[507]) , .CARRY (INT_CARRY[404]) );
FLIPFLOP LA_124 (.DIN (INT_CARRY[390]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[391]) );
assign INT_SUM[508] = INT_CARRY[391];
FULL_ADDER FA_349 (.DATA_A (INT_SUM[507]) , .DATA_B (INT_SUM[508]) , .DATA_C (INT_CARRY[392]) , .SAVE (SUM[42]) , .CARRY (CARRY[42]) );
FULL_ADDER FA_350 (.DATA_A (SUMMAND[445]) , .DATA_B (SUMMAND[446]) , .DATA_C (SUMMAND[447]) , .SAVE (INT_SUM[509]) , .CARRY (INT_CARRY[405]) );
FULL_ADDER FA_351 (.DATA_A (SUMMAND[448]) , .DATA_B (SUMMAND[449]) , .DATA_C (SUMMAND[450]) , .SAVE (INT_SUM[510]) , .CARRY (INT_CARRY[406]) );
FULL_ADDER FA_352 (.DATA_A (SUMMAND[451]) , .DATA_B (SUMMAND[452]) , .DATA_C (SUMMAND[453]) , .SAVE (INT_SUM[511]) , .CARRY (INT_CARRY[407]) );
assign INT_SUM[512] = SUMMAND[454];
assign INT_SUM[513] = SUMMAND[455];
FULL_ADDER FA_353 (.DATA_A (INT_SUM[509]) , .DATA_B (INT_SUM[510]) , .DATA_C (INT_SUM[511]) , .SAVE (INT_SUM[514]) , .CARRY (INT_CARRY[408]) );
FULL_ADDER FA_354 (.DATA_A (INT_SUM[512]) , .DATA_B (INT_SUM[513]) , .DATA_C (INT_CARRY[393]) , .SAVE (INT_SUM[515]) , .CARRY (INT_CARRY[409]) );
FULL_ADDER FA_355 (.DATA_A (INT_CARRY[394]) , .DATA_B (INT_CARRY[395]) , .DATA_C (INT_CARRY[396]) , .SAVE (INT_SUM[516]) , .CARRY (INT_CARRY[410]) );
FULL_ADDER FA_356 (.DATA_A (INT_SUM[514]) , .DATA_B (INT_SUM[515]) , .DATA_C (INT_SUM[516]) , .SAVE (INT_SUM[517]) , .CARRY (INT_CARRY[411]) );
FULL_ADDER FA_357 (.DATA_A (INT_CARRY[397]) , .DATA_B (INT_CARRY[398]) , .DATA_C (INT_CARRY[399]) , .SAVE (INT_SUM[519]) , .CARRY (INT_CARRY[413]) );
FLIPFLOP LA_125 (.DIN (INT_SUM[517]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[518]) );
FLIPFLOP LA_126 (.DIN (INT_SUM[519]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[520]) );
FLIPFLOP LA_127 (.DIN (INT_CARRY[400]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[401]) );
FULL_ADDER FA_358 (.DATA_A (INT_SUM[518]) , .DATA_B (INT_SUM[520]) , .DATA_C (INT_CARRY[401]) , .SAVE (INT_SUM[521]) , .CARRY (INT_CARRY[415]) );
FLIPFLOP LA_128 (.DIN (INT_CARRY[402]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[403]) );
assign INT_SUM[522] = INT_CARRY[403];
FULL_ADDER FA_359 (.DATA_A (INT_SUM[521]) , .DATA_B (INT_SUM[522]) , .DATA_C (INT_CARRY[404]) , .SAVE (SUM[43]) , .CARRY (CARRY[43]) );
FULL_ADDER FA_360 (.DATA_A (SUMMAND[456]) , .DATA_B (SUMMAND[457]) , .DATA_C (SUMMAND[458]) , .SAVE (INT_SUM[523]) , .CARRY (INT_CARRY[416]) );
FULL_ADDER FA_361 (.DATA_A (SUMMAND[459]) , .DATA_B (SUMMAND[460]) , .DATA_C (SUMMAND[461]) , .SAVE (INT_SUM[524]) , .CARRY (INT_CARRY[417]) );
FULL_ADDER FA_362 (.DATA_A (SUMMAND[462]) , .DATA_B (SUMMAND[463]) , .DATA_C (SUMMAND[464]) , .SAVE (INT_SUM[525]) , .CARRY (INT_CARRY[418]) );
HALF_ADDER HA_39 (.DATA_A (SUMMAND[465]) , .DATA_B (SUMMAND[466]) , .SAVE (INT_SUM[526]) , .CARRY (INT_CARRY[419]) );
FULL_ADDER FA_363 (.DATA_A (INT_SUM[523]) , .DATA_B (INT_SUM[524]) , .DATA_C (INT_SUM[525]) , .SAVE (INT_SUM[527]) , .CARRY (INT_CARRY[420]) );
FULL_ADDER FA_364 (.DATA_A (INT_SUM[526]) , .DATA_B (INT_CARRY[405]) , .DATA_C (INT_CARRY[406]) , .SAVE (INT_SUM[528]) , .CARRY (INT_CARRY[421]) );
assign INT_SUM[529] = INT_CARRY[407];
FULL_ADDER FA_365 (.DATA_A (INT_SUM[527]) , .DATA_B (INT_SUM[528]) , .DATA_C (INT_SUM[529]) , .SAVE (INT_SUM[530]) , .CARRY (INT_CARRY[422]) );
FULL_ADDER FA_366 (.DATA_A (INT_CARRY[408]) , .DATA_B (INT_CARRY[409]) , .DATA_C (INT_CARRY[410]) , .SAVE (INT_SUM[532]) , .CARRY (INT_CARRY[424]) );
FLIPFLOP LA_129 (.DIN (INT_SUM[530]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[531]) );
FLIPFLOP LA_130 (.DIN (INT_SUM[532]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[533]) );
FLIPFLOP LA_131 (.DIN (INT_CARRY[411]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[412]) );
FULL_ADDER FA_367 (.DATA_A (INT_SUM[531]) , .DATA_B (INT_SUM[533]) , .DATA_C (INT_CARRY[412]) , .SAVE (INT_SUM[534]) , .CARRY (INT_CARRY[426]) );
FLIPFLOP LA_132 (.DIN (INT_CARRY[413]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[414]) );
assign INT_SUM[535] = INT_CARRY[414];
FULL_ADDER FA_368 (.DATA_A (INT_SUM[534]) , .DATA_B (INT_SUM[535]) , .DATA_C (INT_CARRY[415]) , .SAVE (SUM[44]) , .CARRY (CARRY[44]) );
FULL_ADDER FA_369 (.DATA_A (SUMMAND[467]) , .DATA_B (SUMMAND[468]) , .DATA_C (SUMMAND[469]) , .SAVE (INT_SUM[536]) , .CARRY (INT_CARRY[427]) );
FULL_ADDER FA_370 (.DATA_A (SUMMAND[470]) , .DATA_B (SUMMAND[471]) , .DATA_C (SUMMAND[472]) , .SAVE (INT_SUM[537]) , .CARRY (INT_CARRY[428]) );
FULL_ADDER FA_371 (.DATA_A (SUMMAND[473]) , .DATA_B (SUMMAND[474]) , .DATA_C (SUMMAND[475]) , .SAVE (INT_SUM[538]) , .CARRY (INT_CARRY[429]) );
assign INT_SUM[539] = SUMMAND[476];
FULL_ADDER FA_372 (.DATA_A (INT_SUM[536]) , .DATA_B (INT_SUM[537]) , .DATA_C (INT_SUM[538]) , .SAVE (INT_SUM[540]) , .CARRY (INT_CARRY[430]) );
FULL_ADDER FA_373 (.DATA_A (INT_SUM[539]) , .DATA_B (INT_CARRY[416]) , .DATA_C (INT_CARRY[417]) , .SAVE (INT_SUM[541]) , .CARRY (INT_CARRY[431]) );
assign INT_SUM[542] = INT_CARRY[418];
assign INT_SUM[543] = INT_CARRY[419];
FULL_ADDER FA_374 (.DATA_A (INT_SUM[540]) , .DATA_B (INT_SUM[541]) , .DATA_C (INT_SUM[542]) , .SAVE (INT_SUM[544]) , .CARRY (INT_CARRY[432]) );
FULL_ADDER FA_375 (.DATA_A (INT_SUM[543]) , .DATA_B (INT_CARRY[420]) , .DATA_C (INT_CARRY[421]) , .SAVE (INT_SUM[546]) , .CARRY (INT_CARRY[434]) );
FLIPFLOP LA_133 (.DIN (INT_SUM[544]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[545]) );
FLIPFLOP LA_134 (.DIN (INT_SUM[546]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[547]) );
FLIPFLOP LA_135 (.DIN (INT_CARRY[422]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[423]) );
FULL_ADDER FA_376 (.DATA_A (INT_SUM[545]) , .DATA_B (INT_SUM[547]) , .DATA_C (INT_CARRY[423]) , .SAVE (INT_SUM[548]) , .CARRY (INT_CARRY[436]) );
FLIPFLOP LA_136 (.DIN (INT_CARRY[424]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[425]) );
assign INT_SUM[549] = INT_CARRY[425];
FULL_ADDER FA_377 (.DATA_A (INT_SUM[548]) , .DATA_B (INT_SUM[549]) , .DATA_C (INT_CARRY[426]) , .SAVE (SUM[45]) , .CARRY (CARRY[45]) );
FULL_ADDER FA_378 (.DATA_A (SUMMAND[477]) , .DATA_B (SUMMAND[478]) , .DATA_C (SUMMAND[479]) , .SAVE (INT_SUM[550]) , .CARRY (INT_CARRY[437]) );
FULL_ADDER FA_379 (.DATA_A (SUMMAND[480]) , .DATA_B (SUMMAND[481]) , .DATA_C (SUMMAND[482]) , .SAVE (INT_SUM[551]) , .CARRY (INT_CARRY[438]) );
FULL_ADDER FA_380 (.DATA_A (SUMMAND[483]) , .DATA_B (SUMMAND[484]) , .DATA_C (SUMMAND[485]) , .SAVE (INT_SUM[552]) , .CARRY (INT_CARRY[439]) );
assign INT_SUM[553] = SUMMAND[486];
FULL_ADDER FA_381 (.DATA_A (INT_SUM[550]) , .DATA_B (INT_SUM[551]) , .DATA_C (INT_SUM[552]) , .SAVE (INT_SUM[554]) , .CARRY (INT_CARRY[440]) );
FULL_ADDER FA_382 (.DATA_A (INT_SUM[553]) , .DATA_B (INT_CARRY[427]) , .DATA_C (INT_CARRY[428]) , .SAVE (INT_SUM[555]) , .CARRY (INT_CARRY[441]) );
assign INT_SUM[556] = INT_CARRY[429];
FULL_ADDER FA_383 (.DATA_A (INT_SUM[554]) , .DATA_B (INT_SUM[555]) , .DATA_C (INT_SUM[556]) , .SAVE (INT_SUM[557]) , .CARRY (INT_CARRY[442]) );
HALF_ADDER HA_40 (.DATA_A (INT_CARRY[430]) , .DATA_B (INT_CARRY[431]) , .SAVE (INT_SUM[559]) , .CARRY (INT_CARRY[444]) );
FLIPFLOP LA_137 (.DIN (INT_SUM[557]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[558]) );
FLIPFLOP LA_138 (.DIN (INT_SUM[559]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[560]) );
FLIPFLOP LA_139 (.DIN (INT_CARRY[432]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[433]) );
FULL_ADDER FA_384 (.DATA_A (INT_SUM[558]) , .DATA_B (INT_SUM[560]) , .DATA_C (INT_CARRY[433]) , .SAVE (INT_SUM[561]) , .CARRY (INT_CARRY[446]) );
FLIPFLOP LA_140 (.DIN (INT_CARRY[434]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[435]) );
assign INT_SUM[562] = INT_CARRY[435];
FULL_ADDER FA_385 (.DATA_A (INT_SUM[561]) , .DATA_B (INT_SUM[562]) , .DATA_C (INT_CARRY[436]) , .SAVE (SUM[46]) , .CARRY (CARRY[46]) );
FULL_ADDER FA_386 (.DATA_A (SUMMAND[487]) , .DATA_B (SUMMAND[488]) , .DATA_C (SUMMAND[489]) , .SAVE (INT_SUM[563]) , .CARRY (INT_CARRY[447]) );
FULL_ADDER FA_387 (.DATA_A (SUMMAND[490]) , .DATA_B (SUMMAND[491]) , .DATA_C (SUMMAND[492]) , .SAVE (INT_SUM[564]) , .CARRY (INT_CARRY[448]) );
FULL_ADDER FA_388 (.DATA_A (SUMMAND[493]) , .DATA_B (SUMMAND[494]) , .DATA_C (SUMMAND[495]) , .SAVE (INT_SUM[565]) , .CARRY (INT_CARRY[449]) );
FULL_ADDER FA_389 (.DATA_A (INT_SUM[563]) , .DATA_B (INT_SUM[564]) , .DATA_C (INT_SUM[565]) , .SAVE (INT_SUM[566]) , .CARRY (INT_CARRY[450]) );
FULL_ADDER FA_390 (.DATA_A (INT_CARRY[437]) , .DATA_B (INT_CARRY[438]) , .DATA_C (INT_CARRY[439]) , .SAVE (INT_SUM[567]) , .CARRY (INT_CARRY[451]) );
FULL_ADDER FA_391 (.DATA_A (INT_SUM[566]) , .DATA_B (INT_SUM[567]) , .DATA_C (INT_CARRY[440]) , .SAVE (INT_SUM[568]) , .CARRY (INT_CARRY[452]) );
assign INT_SUM[570] = INT_CARRY[441];
FLIPFLOP LA_141 (.DIN (INT_SUM[568]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[569]) );
FLIPFLOP LA_142 (.DIN (INT_SUM[570]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[571]) );
FLIPFLOP LA_143 (.DIN (INT_CARRY[442]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[443]) );
FULL_ADDER FA_392 (.DATA_A (INT_SUM[569]) , .DATA_B (INT_SUM[571]) , .DATA_C (INT_CARRY[443]) , .SAVE (INT_SUM[572]) , .CARRY (INT_CARRY[454]) );
FLIPFLOP LA_144 (.DIN (INT_CARRY[444]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[445]) );
assign INT_SUM[573] = INT_CARRY[445];
FULL_ADDER FA_393 (.DATA_A (INT_SUM[572]) , .DATA_B (INT_SUM[573]) , .DATA_C (INT_CARRY[446]) , .SAVE (SUM[47]) , .CARRY (CARRY[47]) );
FULL_ADDER FA_394 (.DATA_A (SUMMAND[496]) , .DATA_B (SUMMAND[497]) , .DATA_C (SUMMAND[498]) , .SAVE (INT_SUM[574]) , .CARRY (INT_CARRY[455]) );
FULL_ADDER FA_395 (.DATA_A (SUMMAND[499]) , .DATA_B (SUMMAND[500]) , .DATA_C (SUMMAND[501]) , .SAVE (INT_SUM[575]) , .CARRY (INT_CARRY[456]) );
FULL_ADDER FA_396 (.DATA_A (SUMMAND[502]) , .DATA_B (SUMMAND[503]) , .DATA_C (SUMMAND[504]) , .SAVE (INT_SUM[576]) , .CARRY (INT_CARRY[457]) );
FULL_ADDER FA_397 (.DATA_A (INT_SUM[574]) , .DATA_B (INT_SUM[575]) , .DATA_C (INT_SUM[576]) , .SAVE (INT_SUM[577]) , .CARRY (INT_CARRY[458]) );
FULL_ADDER FA_398 (.DATA_A (INT_CARRY[447]) , .DATA_B (INT_CARRY[448]) , .DATA_C (INT_CARRY[449]) , .SAVE (INT_SUM[578]) , .CARRY (INT_CARRY[459]) );
FULL_ADDER FA_399 (.DATA_A (INT_SUM[577]) , .DATA_B (INT_SUM[578]) , .DATA_C (INT_CARRY[450]) , .SAVE (INT_SUM[579]) , .CARRY (INT_CARRY[460]) );
assign INT_SUM[581] = INT_CARRY[451];
FLIPFLOP LA_145 (.DIN (INT_SUM[579]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[580]) );
FLIPFLOP LA_146 (.DIN (INT_SUM[581]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[582]) );
FLIPFLOP LA_147 (.DIN (INT_CARRY[452]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[453]) );
FULL_ADDER FA_400 (.DATA_A (INT_SUM[580]) , .DATA_B (INT_SUM[582]) , .DATA_C (INT_CARRY[453]) , .SAVE (INT_SUM[583]) , .CARRY (INT_CARRY[462]) );
HALF_ADDER HA_41 (.DATA_A (INT_SUM[583]) , .DATA_B (INT_CARRY[454]) , .SAVE (SUM[48]) , .CARRY (CARRY[48]) );
FULL_ADDER FA_401 (.DATA_A (SUMMAND[505]) , .DATA_B (SUMMAND[506]) , .DATA_C (SUMMAND[507]) , .SAVE (INT_SUM[584]) , .CARRY (INT_CARRY[463]) );
FULL_ADDER FA_402 (.DATA_A (SUMMAND[508]) , .DATA_B (SUMMAND[509]) , .DATA_C (SUMMAND[510]) , .SAVE (INT_SUM[585]) , .CARRY (INT_CARRY[464]) );
FULL_ADDER FA_403 (.DATA_A (SUMMAND[511]) , .DATA_B (SUMMAND[512]) , .DATA_C (INT_CARRY[455]) , .SAVE (INT_SUM[586]) , .CARRY (INT_CARRY[465]) );
HALF_ADDER HA_42 (.DATA_A (INT_CARRY[456]) , .DATA_B (INT_CARRY[457]) , .SAVE (INT_SUM[587]) , .CARRY (INT_CARRY[466]) );
FULL_ADDER FA_404 (.DATA_A (INT_SUM[584]) , .DATA_B (INT_SUM[585]) , .DATA_C (INT_SUM[586]) , .SAVE (INT_SUM[588]) , .CARRY (INT_CARRY[467]) );
FULL_ADDER FA_405 (.DATA_A (INT_SUM[587]) , .DATA_B (INT_CARRY[458]) , .DATA_C (INT_CARRY[459]) , .SAVE (INT_SUM[590]) , .CARRY (INT_CARRY[469]) );
FLIPFLOP LA_148 (.DIN (INT_SUM[588]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[589]) );
FLIPFLOP LA_149 (.DIN (INT_SUM[590]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[591]) );
FLIPFLOP LA_150 (.DIN (INT_CARRY[460]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[461]) );
FULL_ADDER FA_406 (.DATA_A (INT_SUM[589]) , .DATA_B (INT_SUM[591]) , .DATA_C (INT_CARRY[461]) , .SAVE (INT_SUM[592]) , .CARRY (INT_CARRY[471]) );
HALF_ADDER HA_43 (.DATA_A (INT_SUM[592]) , .DATA_B (INT_CARRY[462]) , .SAVE (SUM[49]) , .CARRY (CARRY[49]) );
FULL_ADDER FA_407 (.DATA_A (SUMMAND[513]) , .DATA_B (SUMMAND[514]) , .DATA_C (SUMMAND[515]) , .SAVE (INT_SUM[593]) , .CARRY (INT_CARRY[472]) );
FULL_ADDER FA_408 (.DATA_A (SUMMAND[516]) , .DATA_B (SUMMAND[517]) , .DATA_C (SUMMAND[518]) , .SAVE (INT_SUM[594]) , .CARRY (INT_CARRY[473]) );
assign INT_SUM[595] = SUMMAND[519];
assign INT_SUM[596] = SUMMAND[520];
FULL_ADDER FA_409 (.DATA_A (INT_SUM[593]) , .DATA_B (INT_SUM[594]) , .DATA_C (INT_SUM[595]) , .SAVE (INT_SUM[597]) , .CARRY (INT_CARRY[474]) );
assign INT_SUM[598] = INT_SUM[596];
FULL_ADDER FA_410 (.DATA_A (INT_SUM[597]) , .DATA_B (INT_SUM[598]) , .DATA_C (INT_CARRY[463]) , .SAVE (INT_SUM[599]) , .CARRY (INT_CARRY[475]) );
FULL_ADDER FA_411 (.DATA_A (INT_CARRY[464]) , .DATA_B (INT_CARRY[465]) , .DATA_C (INT_CARRY[466]) , .SAVE (INT_SUM[601]) , .CARRY (INT_CARRY[477]) );
FLIPFLOP LA_151 (.DIN (INT_SUM[599]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[600]) );
FLIPFLOP LA_152 (.DIN (INT_SUM[601]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[602]) );
FLIPFLOP LA_153 (.DIN (INT_CARRY[467]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[468]) );
FULL_ADDER FA_412 (.DATA_A (INT_SUM[600]) , .DATA_B (INT_SUM[602]) , .DATA_C (INT_CARRY[468]) , .SAVE (INT_SUM[603]) , .CARRY (INT_CARRY[479]) );
FLIPFLOP LA_154 (.DIN (INT_CARRY[469]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[470]) );
assign INT_SUM[604] = INT_CARRY[470];
FULL_ADDER FA_413 (.DATA_A (INT_SUM[603]) , .DATA_B (INT_SUM[604]) , .DATA_C (INT_CARRY[471]) , .SAVE (SUM[50]) , .CARRY (CARRY[50]) );
FULL_ADDER FA_414 (.DATA_A (SUMMAND[521]) , .DATA_B (SUMMAND[522]) , .DATA_C (SUMMAND[523]) , .SAVE (INT_SUM[605]) , .CARRY (INT_CARRY[480]) );
FULL_ADDER FA_415 (.DATA_A (SUMMAND[524]) , .DATA_B (SUMMAND[525]) , .DATA_C (SUMMAND[526]) , .SAVE (INT_SUM[606]) , .CARRY (INT_CARRY[481]) );
FULL_ADDER FA_416 (.DATA_A (SUMMAND[527]) , .DATA_B (INT_CARRY[472]) , .DATA_C (INT_CARRY[473]) , .SAVE (INT_SUM[607]) , .CARRY (INT_CARRY[482]) );
FULL_ADDER FA_417 (.DATA_A (INT_SUM[605]) , .DATA_B (INT_SUM[606]) , .DATA_C (INT_SUM[607]) , .SAVE (INT_SUM[608]) , .CARRY (INT_CARRY[483]) );
assign INT_SUM[610] = INT_CARRY[474];
FLIPFLOP LA_155 (.DIN (INT_SUM[608]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[609]) );
FLIPFLOP LA_156 (.DIN (INT_SUM[610]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[611]) );
FLIPFLOP LA_157 (.DIN (INT_CARRY[475]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[476]) );
FULL_ADDER FA_418 (.DATA_A (INT_SUM[609]) , .DATA_B (INT_SUM[611]) , .DATA_C (INT_CARRY[476]) , .SAVE (INT_SUM[612]) , .CARRY (INT_CARRY[485]) );
FLIPFLOP LA_158 (.DIN (INT_CARRY[477]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[478]) );
assign INT_SUM[613] = INT_CARRY[478];
FULL_ADDER FA_419 (.DATA_A (INT_SUM[612]) , .DATA_B (INT_SUM[613]) , .DATA_C (INT_CARRY[479]) , .SAVE (SUM[51]) , .CARRY (CARRY[51]) );
FULL_ADDER FA_420 (.DATA_A (SUMMAND[528]) , .DATA_B (SUMMAND[529]) , .DATA_C (SUMMAND[530]) , .SAVE (INT_SUM[614]) , .CARRY (INT_CARRY[486]) );
FULL_ADDER FA_421 (.DATA_A (SUMMAND[531]) , .DATA_B (SUMMAND[532]) , .DATA_C (SUMMAND[533]) , .SAVE (INT_SUM[615]) , .CARRY (INT_CARRY[487]) );
assign INT_SUM[616] = SUMMAND[534];
FULL_ADDER FA_422 (.DATA_A (INT_SUM[614]) , .DATA_B (INT_SUM[615]) , .DATA_C (INT_SUM[616]) , .SAVE (INT_SUM[617]) , .CARRY (INT_CARRY[488]) );
FULL_ADDER FA_423 (.DATA_A (INT_CARRY[480]) , .DATA_B (INT_CARRY[481]) , .DATA_C (INT_CARRY[482]) , .SAVE (INT_SUM[619]) , .CARRY (INT_CARRY[490]) );
FLIPFLOP LA_159 (.DIN (INT_SUM[617]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[618]) );
FLIPFLOP LA_160 (.DIN (INT_SUM[619]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[620]) );
FLIPFLOP LA_161 (.DIN (INT_CARRY[483]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[484]) );
FULL_ADDER FA_424 (.DATA_A (INT_SUM[618]) , .DATA_B (INT_SUM[620]) , .DATA_C (INT_CARRY[484]) , .SAVE (INT_SUM[621]) , .CARRY (INT_CARRY[492]) );
HALF_ADDER HA_44 (.DATA_A (INT_SUM[621]) , .DATA_B (INT_CARRY[485]) , .SAVE (SUM[52]) , .CARRY (CARRY[52]) );
FULL_ADDER FA_425 (.DATA_A (SUMMAND[535]) , .DATA_B (SUMMAND[536]) , .DATA_C (SUMMAND[537]) , .SAVE (INT_SUM[622]) , .CARRY (INT_CARRY[493]) );
FULL_ADDER FA_426 (.DATA_A (SUMMAND[538]) , .DATA_B (SUMMAND[539]) , .DATA_C (SUMMAND[540]) , .SAVE (INT_SUM[623]) , .CARRY (INT_CARRY[494]) );
FULL_ADDER FA_427 (.DATA_A (INT_SUM[622]) , .DATA_B (INT_SUM[623]) , .DATA_C (INT_CARRY[486]) , .SAVE (INT_SUM[624]) , .CARRY (INT_CARRY[495]) );
assign INT_SUM[626] = INT_CARRY[487];
FLIPFLOP LA_162 (.DIN (INT_SUM[624]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[625]) );
FLIPFLOP LA_163 (.DIN (INT_SUM[626]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[627]) );
FLIPFLOP LA_164 (.DIN (INT_CARRY[488]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[489]) );
FULL_ADDER FA_428 (.DATA_A (INT_SUM[625]) , .DATA_B (INT_SUM[627]) , .DATA_C (INT_CARRY[489]) , .SAVE (INT_SUM[628]) , .CARRY (INT_CARRY[497]) );
FLIPFLOP LA_165 (.DIN (INT_CARRY[490]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[491]) );
assign INT_SUM[629] = INT_CARRY[491];
FULL_ADDER FA_429 (.DATA_A (INT_SUM[628]) , .DATA_B (INT_SUM[629]) , .DATA_C (INT_CARRY[492]) , .SAVE (SUM[53]) , .CARRY (CARRY[53]) );
FULL_ADDER FA_430 (.DATA_A (SUMMAND[541]) , .DATA_B (SUMMAND[542]) , .DATA_C (SUMMAND[543]) , .SAVE (INT_SUM[630]) , .CARRY (INT_CARRY[498]) );
FULL_ADDER FA_431 (.DATA_A (SUMMAND[544]) , .DATA_B (SUMMAND[545]) , .DATA_C (SUMMAND[546]) , .SAVE (INT_SUM[631]) , .CARRY (INT_CARRY[499]) );
FULL_ADDER FA_432 (.DATA_A (INT_SUM[630]) , .DATA_B (INT_SUM[631]) , .DATA_C (INT_CARRY[493]) , .SAVE (INT_SUM[632]) , .CARRY (INT_CARRY[500]) );
assign INT_SUM[634] = INT_CARRY[494];
FLIPFLOP LA_166 (.DIN (INT_SUM[632]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[633]) );
FLIPFLOP LA_167 (.DIN (INT_SUM[634]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[635]) );
FLIPFLOP LA_168 (.DIN (INT_CARRY[495]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[496]) );
FULL_ADDER FA_433 (.DATA_A (INT_SUM[633]) , .DATA_B (INT_SUM[635]) , .DATA_C (INT_CARRY[496]) , .SAVE (INT_SUM[636]) , .CARRY (INT_CARRY[502]) );
HALF_ADDER HA_45 (.DATA_A (INT_SUM[636]) , .DATA_B (INT_CARRY[497]) , .SAVE (SUM[54]) , .CARRY (CARRY[54]) );
FULL_ADDER FA_434 (.DATA_A (SUMMAND[547]) , .DATA_B (SUMMAND[548]) , .DATA_C (SUMMAND[549]) , .SAVE (INT_SUM[637]) , .CARRY (INT_CARRY[503]) );
HALF_ADDER HA_46 (.DATA_A (SUMMAND[550]) , .DATA_B (SUMMAND[551]) , .SAVE (INT_SUM[638]) , .CARRY (INT_CARRY[504]) );
FULL_ADDER FA_435 (.DATA_A (INT_SUM[637]) , .DATA_B (INT_SUM[638]) , .DATA_C (INT_CARRY[498]) , .SAVE (INT_SUM[639]) , .CARRY (INT_CARRY[505]) );
assign INT_SUM[641] = INT_CARRY[499];
FLIPFLOP LA_169 (.DIN (INT_SUM[639]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[640]) );
FLIPFLOP LA_170 (.DIN (INT_SUM[641]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[642]) );
FLIPFLOP LA_171 (.DIN (INT_CARRY[500]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[501]) );
FULL_ADDER FA_436 (.DATA_A (INT_SUM[640]) , .DATA_B (INT_SUM[642]) , .DATA_C (INT_CARRY[501]) , .SAVE (INT_SUM[643]) , .CARRY (INT_CARRY[507]) );
HALF_ADDER HA_47 (.DATA_A (INT_SUM[643]) , .DATA_B (INT_CARRY[502]) , .SAVE (SUM[55]) , .CARRY (CARRY[55]) );
FULL_ADDER FA_437 (.DATA_A (SUMMAND[552]) , .DATA_B (SUMMAND[553]) , .DATA_C (SUMMAND[554]) , .SAVE (INT_SUM[644]) , .CARRY (INT_CARRY[508]) );
HALF_ADDER HA_48 (.DATA_A (SUMMAND[555]) , .DATA_B (SUMMAND[556]) , .SAVE (INT_SUM[645]) , .CARRY (INT_CARRY[509]) );
FULL_ADDER FA_438 (.DATA_A (INT_SUM[644]) , .DATA_B (INT_SUM[645]) , .DATA_C (INT_CARRY[503]) , .SAVE (INT_SUM[646]) , .CARRY (INT_CARRY[510]) );
assign INT_SUM[648] = INT_CARRY[504];
FLIPFLOP LA_172 (.DIN (INT_SUM[646]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[647]) );
FLIPFLOP LA_173 (.DIN (INT_SUM[648]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[649]) );
FLIPFLOP LA_174 (.DIN (INT_CARRY[505]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[506]) );
FULL_ADDER FA_439 (.DATA_A (INT_SUM[647]) , .DATA_B (INT_SUM[649]) , .DATA_C (INT_CARRY[506]) , .SAVE (INT_SUM[650]) , .CARRY (INT_CARRY[512]) );
HALF_ADDER HA_49 (.DATA_A (INT_SUM[650]) , .DATA_B (INT_CARRY[507]) , .SAVE (SUM[56]) , .CARRY (CARRY[56]) );
FULL_ADDER FA_440 (.DATA_A (SUMMAND[557]) , .DATA_B (SUMMAND[558]) , .DATA_C (SUMMAND[559]) , .SAVE (INT_SUM[651]) , .CARRY (INT_CARRY[513]) );
FULL_ADDER FA_441 (.DATA_A (SUMMAND[560]) , .DATA_B (INT_CARRY[508]) , .DATA_C (INT_CARRY[509]) , .SAVE (INT_SUM[653]) , .CARRY (INT_CARRY[515]) );
FLIPFLOP LA_175 (.DIN (INT_SUM[651]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[652]) );
FLIPFLOP LA_176 (.DIN (INT_SUM[653]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[654]) );
FLIPFLOP LA_177 (.DIN (INT_CARRY[510]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[511]) );
FULL_ADDER FA_442 (.DATA_A (INT_SUM[652]) , .DATA_B (INT_SUM[654]) , .DATA_C (INT_CARRY[511]) , .SAVE (INT_SUM[655]) , .CARRY (INT_CARRY[517]) );
HALF_ADDER HA_50 (.DATA_A (INT_SUM[655]) , .DATA_B (INT_CARRY[512]) , .SAVE (SUM[57]) , .CARRY (CARRY[57]) );
FULL_ADDER FA_443 (.DATA_A (SUMMAND[561]) , .DATA_B (SUMMAND[562]) , .DATA_C (SUMMAND[563]) , .SAVE (INT_SUM[656]) , .CARRY (INT_CARRY[518]) );
assign INT_SUM[658] = SUMMAND[564];
FLIPFLOP LA_178 (.DIN (INT_SUM[656]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[657]) );
FLIPFLOP LA_179 (.DIN (INT_SUM[658]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[659]) );
FLIPFLOP LA_180 (.DIN (INT_CARRY[513]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[514]) );
FULL_ADDER FA_444 (.DATA_A (INT_SUM[657]) , .DATA_B (INT_SUM[659]) , .DATA_C (INT_CARRY[514]) , .SAVE (INT_SUM[660]) , .CARRY (INT_CARRY[520]) );
FLIPFLOP LA_181 (.DIN (INT_CARRY[515]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[516]) );
assign INT_SUM[661] = INT_CARRY[516];
FULL_ADDER FA_445 (.DATA_A (INT_SUM[660]) , .DATA_B (INT_SUM[661]) , .DATA_C (INT_CARRY[517]) , .SAVE (SUM[58]) , .CARRY (CARRY[58]) );
FULL_ADDER FA_446 (.DATA_A (SUMMAND[565]) , .DATA_B (SUMMAND[566]) , .DATA_C (SUMMAND[567]) , .SAVE (INT_SUM[662]) , .CARRY (INT_CARRY[521]) );
FLIPFLOP LA_182 (.DIN (INT_SUM[662]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[663]) );
assign INT_SUM[664] = INT_SUM[663];
FLIPFLOP LA_183 (.DIN (INT_CARRY[518]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[519]) );
assign INT_SUM[665] = INT_CARRY[519];
FULL_ADDER FA_447 (.DATA_A (INT_SUM[664]) , .DATA_B (INT_SUM[665]) , .DATA_C (INT_CARRY[520]) , .SAVE (SUM[59]) , .CARRY (CARRY[59]) );
FLIPFLOP LA_184 (.DIN (SUMMAND[568]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[0]) );
FLIPFLOP LA_185 (.DIN (SUMMAND[569]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[1]) );
FLIPFLOP LA_186 (.DIN (SUMMAND[570]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[2]) );
FULL_ADDER FA_448 (.DATA_A (LATCHED_PP[0]) , .DATA_B (LATCHED_PP[1]) , .DATA_C (LATCHED_PP[2]) , .SAVE (INT_SUM[666]) , .CARRY (INT_CARRY[523]) );
FLIPFLOP LA_187 (.DIN (INT_CARRY[521]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[522]) );
assign INT_SUM[667] = INT_CARRY[522];
HALF_ADDER HA_51 (.DATA_A (INT_SUM[666]) , .DATA_B (INT_SUM[667]) , .SAVE (SUM[60]) , .CARRY (CARRY[60]) );
FLIPFLOP LA_188 (.DIN (SUMMAND[571]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[3]) );
assign INT_SUM[668] = LATCHED_PP[3];
FLIPFLOP LA_189 (.DIN (SUMMAND[572]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[4]) );
assign INT_SUM[669] = LATCHED_PP[4];
FULL_ADDER FA_449 (.DATA_A (INT_SUM[668]) , .DATA_B (INT_SUM[669]) , .DATA_C (INT_CARRY[523]) , .SAVE (SUM[61]) , .CARRY (CARRY[61]) );
FLIPFLOP LA_190 (.DIN (SUMMAND[573]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[5]) );
FLIPFLOP LA_191 (.DIN (SUMMAND[574]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[6]) );
HALF_ADDER HA_52 (.DATA_A (LATCHED_PP[5]) , .DATA_B (LATCHED_PP[6]) , .SAVE (SUM[62]) , .CARRY (CARRY[62]) );
FLIPFLOP LA_192 (.DIN (SUMMAND[575]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[7]) );
assign SUM[63] = LATCHED_PP[7];
endmodule
module INVBLOCK ( GIN, PHI, GOUT );
input GIN;
input PHI;
output GOUT;
assign GOUT = ~ GIN;
endmodule
module XXOR1 ( A, B, GIN, PHI, SUM );
input A;
input B;
input GIN;
input PHI;
output SUM;
assign SUM = ( ~ (A ^ B)) ^ GIN;
endmodule
module BLOCK0 ( A, B, PHI, POUT, GOUT );
input A;
input B;
input PHI;
output POUT;
output GOUT;
assign POUT = ~ (A | B);
assign GOUT = ~ (A & B);
endmodule
module BLOCK1 ( PIN1, PIN2, GIN1, GIN2, PHI, POUT, GOUT );
input PIN1;
input PIN2;
input GIN1;
input GIN2;
input PHI;
output POUT;
output GOUT;
assign POUT = ~ (PIN1 | PIN2);
assign GOUT = ~ (GIN2 & (PIN2 | GIN1));
endmodule
module BLOCK2 ( PIN1, PIN2, GIN1, GIN2, PHI, POUT, GOUT );
input PIN1;
input PIN2;
input GIN1;
input GIN2;
input PHI;
output POUT;
output GOUT;
assign POUT = ~ (PIN1 & PIN2);
assign GOUT = ~ (GIN2 | (PIN2 & GIN1));
endmodule
module BLOCK1A ( PIN2, GIN1, GIN2, PHI, GOUT );
input PIN2;
input GIN1;
input GIN2;
input PHI;
output GOUT;
assign GOUT = ~ (GIN2 & (PIN2 | GIN1));
endmodule
module BLOCK2A ( PIN2, GIN1, GIN2, PHI, GOUT );
input PIN2;
input GIN1;
input GIN2;
input PHI;
output GOUT;
assign GOUT = ~ (GIN2 | (PIN2 & GIN1));
endmodule
module PRESTAGE_64 ( A, B, CIN, PHI, POUT, GOUT );
input [0:63] A;
input [0:63] B;
input CIN;
input PHI;
output [0:63] POUT;
output [0:64] GOUT;
BLOCK0 U10 (A[0] , B[0] , PHI , POUT[0] , GOUT[1] );
BLOCK0 U11 (A[1] , B[1] , PHI , POUT[1] , GOUT[2] );
BLOCK0 U12 (A[2] , B[2] , PHI , POUT[2] , GOUT[3] );
BLOCK0 U13 (A[3] , B[3] , PHI , POUT[3] , GOUT[4] );
BLOCK0 U14 (A[4] , B[4] , PHI , POUT[4] , GOUT[5] );
BLOCK0 U15 (A[5] , B[5] , PHI , POUT[5] , GOUT[6] );
BLOCK0 U16 (A[6] , B[6] , PHI , POUT[6] , GOUT[7] );
BLOCK0 U17 (A[7] , B[7] , PHI , POUT[7] , GOUT[8] );
BLOCK0 U18 (A[8] , B[8] , PHI , POUT[8] , GOUT[9] );
BLOCK0 U19 (A[9] , B[9] , PHI , POUT[9] , GOUT[10] );
BLOCK0 U110 (A[10] , B[10] , PHI , POUT[10] , GOUT[11] );
BLOCK0 U111 (A[11] , B[11] , PHI , POUT[11] , GOUT[12] );
BLOCK0 U112 (A[12] , B[12] , PHI , POUT[12] , GOUT[13] );
BLOCK0 U113 (A[13] , B[13] , PHI , POUT[13] , GOUT[14] );
BLOCK0 U114 (A[14] , B[14] , PHI , POUT[14] , GOUT[15] );
BLOCK0 U115 (A[15] , B[15] , PHI , POUT[15] , GOUT[16] );
BLOCK0 U116 (A[16] , B[16] , PHI , POUT[16] , GOUT[17] );
BLOCK0 U117 (A[17] , B[17] , PHI , POUT[17] , GOUT[18] );
BLOCK0 U118 (A[18] , B[18] , PHI , POUT[18] , GOUT[19] );
BLOCK0 U119 (A[19] , B[19] , PHI , POUT[19] , GOUT[20] );
BLOCK0 U120 (A[20] , B[20] , PHI , POUT[20] , GOUT[21] );
BLOCK0 U121 (A[21] , B[21] , PHI , POUT[21] , GOUT[22] );
BLOCK0 U122 (A[22] , B[22] , PHI , POUT[22] , GOUT[23] );
BLOCK0 U123 (A[23] , B[23] , PHI , POUT[23] , GOUT[24] );
BLOCK0 U124 (A[24] , B[24] , PHI , POUT[24] , GOUT[25] );
BLOCK0 U125 (A[25] , B[25] , PHI , POUT[25] , GOUT[26] );
BLOCK0 U126 (A[26] , B[26] , PHI , POUT[26] , GOUT[27] );
BLOCK0 U127 (A[27] , B[27] , PHI , POUT[27] , GOUT[28] );
BLOCK0 U128 (A[28] , B[28] , PHI , POUT[28] , GOUT[29] );
BLOCK0 U129 (A[29] , B[29] , PHI , POUT[29] , GOUT[30] );
BLOCK0 U130 (A[30] , B[30] , PHI , POUT[30] , GOUT[31] );
BLOCK0 U131 (A[31] , B[31] , PHI , POUT[31] , GOUT[32] );
BLOCK0 U132 (A[32] , B[32] , PHI , POUT[32] , GOUT[33] );
BLOCK0 U133 (A[33] , B[33] , PHI , POUT[33] , GOUT[34] );
BLOCK0 U134 (A[34] , B[34] , PHI , POUT[34] , GOUT[35] );
BLOCK0 U135 (A[35] , B[35] , PHI , POUT[35] , GOUT[36] );
BLOCK0 U136 (A[36] , B[36] , PHI , POUT[36] , GOUT[37] );
BLOCK0 U137 (A[37] , B[37] , PHI , POUT[37] , GOUT[38] );
BLOCK0 U138 (A[38] , B[38] , PHI , POUT[38] , GOUT[39] );
BLOCK0 U139 (A[39] , B[39] , PHI , POUT[39] , GOUT[40] );
BLOCK0 U140 (A[40] , B[40] , PHI , POUT[40] , GOUT[41] );
BLOCK0 U141 (A[41] , B[41] , PHI , POUT[41] , GOUT[42] );
BLOCK0 U142 (A[42] , B[42] , PHI , POUT[42] , GOUT[43] );
BLOCK0 U143 (A[43] , B[43] , PHI , POUT[43] , GOUT[44] );
BLOCK0 U144 (A[44] , B[44] , PHI , POUT[44] , GOUT[45] );
BLOCK0 U145 (A[45] , B[45] , PHI , POUT[45] , GOUT[46] );
BLOCK0 U146 (A[46] , B[46] , PHI , POUT[46] , GOUT[47] );
BLOCK0 U147 (A[47] , B[47] , PHI , POUT[47] , GOUT[48] );
BLOCK0 U148 (A[48] , B[48] , PHI , POUT[48] , GOUT[49] );
BLOCK0 U149 (A[49] , B[49] , PHI , POUT[49] , GOUT[50] );
BLOCK0 U150 (A[50] , B[50] , PHI , POUT[50] , GOUT[51] );
BLOCK0 U151 (A[51] , B[51] , PHI , POUT[51] , GOUT[52] );
BLOCK0 U152 (A[52] , B[52] , PHI , POUT[52] , GOUT[53] );
BLOCK0 U153 (A[53] , B[53] , PHI , POUT[53] , GOUT[54] );
BLOCK0 U154 (A[54] , B[54] , PHI , POUT[54] , GOUT[55] );
BLOCK0 U155 (A[55] , B[55] , PHI , POUT[55] , GOUT[56] );
BLOCK0 U156 (A[56] , B[56] , PHI , POUT[56] , GOUT[57] );
BLOCK0 U157 (A[57] , B[57] , PHI , POUT[57] , GOUT[58] );
BLOCK0 U158 (A[58] , B[58] , PHI , POUT[58] , GOUT[59] );
BLOCK0 U159 (A[59] , B[59] , PHI , POUT[59] , GOUT[60] );
BLOCK0 U160 (A[60] , B[60] , PHI , POUT[60] , GOUT[61] );
BLOCK0 U161 (A[61] , B[61] , PHI , POUT[61] , GOUT[62] );
BLOCK0 U162 (A[62] , B[62] , PHI , POUT[62] , GOUT[63] );
BLOCK0 U163 (A[63] , B[63] , PHI , POUT[63] , GOUT[64] );
INVBLOCK U2 (CIN , PHI , GOUT[0] );
endmodule
module DBLC_0_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:63] PIN;
input [0:64] GIN;
input PHI;
output [0:62] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
BLOCK1A U21 (PIN[0] , GIN[0] , GIN[1] , PHI , GOUT[1] );
BLOCK1 U32 (PIN[0] , PIN[1] , GIN[1] , GIN[2] , PHI , POUT[0] , GOUT[2] );
BLOCK1 U33 (PIN[1] , PIN[2] , GIN[2] , GIN[3] , PHI , POUT[1] , GOUT[3] );
BLOCK1 U34 (PIN[2] , PIN[3] , GIN[3] , GIN[4] , PHI , POUT[2] , GOUT[4] );
BLOCK1 U35 (PIN[3] , PIN[4] , GIN[4] , GIN[5] , PHI , POUT[3] , GOUT[5] );
BLOCK1 U36 (PIN[4] , PIN[5] , GIN[5] , GIN[6] , PHI , POUT[4] , GOUT[6] );
BLOCK1 U37 (PIN[5] , PIN[6] , GIN[6] , GIN[7] , PHI , POUT[5] , GOUT[7] );
BLOCK1 U38 (PIN[6] , PIN[7] , GIN[7] , GIN[8] , PHI , POUT[6] , GOUT[8] );
BLOCK1 U39 (PIN[7] , PIN[8] , GIN[8] , GIN[9] , PHI , POUT[7] , GOUT[9] );
BLOCK1 U310 (PIN[8] , PIN[9] , GIN[9] , GIN[10] , PHI , POUT[8] , GOUT[10] );
BLOCK1 U311 (PIN[9] , PIN[10] , GIN[10] , GIN[11] , PHI , POUT[9] , GOUT[11] );
BLOCK1 U312 (PIN[10] , PIN[11] , GIN[11] , GIN[12] , PHI , POUT[10] , GOUT[12] );
BLOCK1 U313 (PIN[11] , PIN[12] , GIN[12] , GIN[13] , PHI , POUT[11] , GOUT[13] );
BLOCK1 U314 (PIN[12] , PIN[13] , GIN[13] , GIN[14] , PHI , POUT[12] , GOUT[14] );
BLOCK1 U315 (PIN[13] , PIN[14] , GIN[14] , GIN[15] , PHI , POUT[13] , GOUT[15] );
BLOCK1 U316 (PIN[14] , PIN[15] , GIN[15] , GIN[16] , PHI , POUT[14] , GOUT[16] );
BLOCK1 U317 (PIN[15] , PIN[16] , GIN[16] , GIN[17] , PHI , POUT[15] , GOUT[17] );
BLOCK1 U318 (PIN[16] , PIN[17] , GIN[17] , GIN[18] , PHI , POUT[16] , GOUT[18] );
BLOCK1 U319 (PIN[17] , PIN[18] , GIN[18] , GIN[19] , PHI , POUT[17] , GOUT[19] );
BLOCK1 U320 (PIN[18] , PIN[19] , GIN[19] , GIN[20] , PHI , POUT[18] , GOUT[20] );
BLOCK1 U321 (PIN[19] , PIN[20] , GIN[20] , GIN[21] , PHI , POUT[19] , GOUT[21] );
BLOCK1 U322 (PIN[20] , PIN[21] , GIN[21] , GIN[22] , PHI , POUT[20] , GOUT[22] );
BLOCK1 U323 (PIN[21] , PIN[22] , GIN[22] , GIN[23] , PHI , POUT[21] , GOUT[23] );
BLOCK1 U324 (PIN[22] , PIN[23] , GIN[23] , GIN[24] , PHI , POUT[22] , GOUT[24] );
BLOCK1 U325 (PIN[23] , PIN[24] , GIN[24] , GIN[25] , PHI , POUT[23] , GOUT[25] );
BLOCK1 U326 (PIN[24] , PIN[25] , GIN[25] , GIN[26] , PHI , POUT[24] , GOUT[26] );
BLOCK1 U327 (PIN[25] , PIN[26] , GIN[26] , GIN[27] , PHI , POUT[25] , GOUT[27] );
BLOCK1 U328 (PIN[26] , PIN[27] , GIN[27] , GIN[28] , PHI , POUT[26] , GOUT[28] );
BLOCK1 U329 (PIN[27] , PIN[28] , GIN[28] , GIN[29] , PHI , POUT[27] , GOUT[29] );
BLOCK1 U330 (PIN[28] , PIN[29] , GIN[29] , GIN[30] , PHI , POUT[28] , GOUT[30] );
BLOCK1 U331 (PIN[29] , PIN[30] , GIN[30] , GIN[31] , PHI , POUT[29] , GOUT[31] );
BLOCK1 U332 (PIN[30] , PIN[31] , GIN[31] , GIN[32] , PHI , POUT[30] , GOUT[32] );
BLOCK1 U333 (PIN[31] , PIN[32] , GIN[32] , GIN[33] , PHI , POUT[31] , GOUT[33] );
BLOCK1 U334 (PIN[32] , PIN[33] , GIN[33] , GIN[34] , PHI , POUT[32] , GOUT[34] );
BLOCK1 U335 (PIN[33] , PIN[34] , GIN[34] , GIN[35] , PHI , POUT[33] , GOUT[35] );
BLOCK1 U336 (PIN[34] , PIN[35] , GIN[35] , GIN[36] , PHI , POUT[34] , GOUT[36] );
BLOCK1 U337 (PIN[35] , PIN[36] , GIN[36] , GIN[37] , PHI , POUT[35] , GOUT[37] );
BLOCK1 U338 (PIN[36] , PIN[37] , GIN[37] , GIN[38] , PHI , POUT[36] , GOUT[38] );
BLOCK1 U339 (PIN[37] , PIN[38] , GIN[38] , GIN[39] , PHI , POUT[37] , GOUT[39] );
BLOCK1 U340 (PIN[38] , PIN[39] , GIN[39] , GIN[40] , PHI , POUT[38] , GOUT[40] );
BLOCK1 U341 (PIN[39] , PIN[40] , GIN[40] , GIN[41] , PHI , POUT[39] , GOUT[41] );
BLOCK1 U342 (PIN[40] , PIN[41] , GIN[41] , GIN[42] , PHI , POUT[40] , GOUT[42] );
BLOCK1 U343 (PIN[41] , PIN[42] , GIN[42] , GIN[43] , PHI , POUT[41] , GOUT[43] );
BLOCK1 U344 (PIN[42] , PIN[43] , GIN[43] , GIN[44] , PHI , POUT[42] , GOUT[44] );
BLOCK1 U345 (PIN[43] , PIN[44] , GIN[44] , GIN[45] , PHI , POUT[43] , GOUT[45] );
BLOCK1 U346 (PIN[44] , PIN[45] , GIN[45] , GIN[46] , PHI , POUT[44] , GOUT[46] );
BLOCK1 U347 (PIN[45] , PIN[46] , GIN[46] , GIN[47] , PHI , POUT[45] , GOUT[47] );
BLOCK1 U348 (PIN[46] , PIN[47] , GIN[47] , GIN[48] , PHI , POUT[46] , GOUT[48] );
BLOCK1 U349 (PIN[47] , PIN[48] , GIN[48] , GIN[49] , PHI , POUT[47] , GOUT[49] );
BLOCK1 U350 (PIN[48] , PIN[49] , GIN[49] , GIN[50] , PHI , POUT[48] , GOUT[50] );
BLOCK1 U351 (PIN[49] , PIN[50] , GIN[50] , GIN[51] , PHI , POUT[49] , GOUT[51] );
BLOCK1 U352 (PIN[50] , PIN[51] , GIN[51] , GIN[52] , PHI , POUT[50] , GOUT[52] );
BLOCK1 U353 (PIN[51] , PIN[52] , GIN[52] , GIN[53] , PHI , POUT[51] , GOUT[53] );
BLOCK1 U354 (PIN[52] , PIN[53] , GIN[53] , GIN[54] , PHI , POUT[52] , GOUT[54] );
BLOCK1 U355 (PIN[53] , PIN[54] , GIN[54] , GIN[55] , PHI , POUT[53] , GOUT[55] );
BLOCK1 U356 (PIN[54] , PIN[55] , GIN[55] , GIN[56] , PHI , POUT[54] , GOUT[56] );
BLOCK1 U357 (PIN[55] , PIN[56] , GIN[56] , GIN[57] , PHI , POUT[55] , GOUT[57] );
BLOCK1 U358 (PIN[56] , PIN[57] , GIN[57] , GIN[58] , PHI , POUT[56] , GOUT[58] );
BLOCK1 U359 (PIN[57] , PIN[58] , GIN[58] , GIN[59] , PHI , POUT[57] , GOUT[59] );
BLOCK1 U360 (PIN[58] , PIN[59] , GIN[59] , GIN[60] , PHI , POUT[58] , GOUT[60] );
BLOCK1 U361 (PIN[59] , PIN[60] , GIN[60] , GIN[61] , PHI , POUT[59] , GOUT[61] );
BLOCK1 U362 (PIN[60] , PIN[61] , GIN[61] , GIN[62] , PHI , POUT[60] , GOUT[62] );
BLOCK1 U363 (PIN[61] , PIN[62] , GIN[62] , GIN[63] , PHI , POUT[61] , GOUT[63] );
BLOCK1 U364 (PIN[62] , PIN[63] , GIN[63] , GIN[64] , PHI , POUT[62] , GOUT[64] );
endmodule
module DBLC_1_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:62] PIN;
input [0:64] GIN;
input PHI;
output [0:60] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
BLOCK2A U22 (PIN[0] , GIN[0] , GIN[2] , PHI , GOUT[2] );
BLOCK2A U23 (PIN[1] , GIN[1] , GIN[3] , PHI , GOUT[3] );
BLOCK2 U34 (PIN[0] , PIN[2] , GIN[2] , GIN[4] , PHI , POUT[0] , GOUT[4] );
BLOCK2 U35 (PIN[1] , PIN[3] , GIN[3] , GIN[5] , PHI , POUT[1] , GOUT[5] );
BLOCK2 U36 (PIN[2] , PIN[4] , GIN[4] , GIN[6] , PHI , POUT[2] , GOUT[6] );
BLOCK2 U37 (PIN[3] , PIN[5] , GIN[5] , GIN[7] , PHI , POUT[3] , GOUT[7] );
BLOCK2 U38 (PIN[4] , PIN[6] , GIN[6] , GIN[8] , PHI , POUT[4] , GOUT[8] );
BLOCK2 U39 (PIN[5] , PIN[7] , GIN[7] , GIN[9] , PHI , POUT[5] , GOUT[9] );
BLOCK2 U310 (PIN[6] , PIN[8] , GIN[8] , GIN[10] , PHI , POUT[6] , GOUT[10] );
BLOCK2 U311 (PIN[7] , PIN[9] , GIN[9] , GIN[11] , PHI , POUT[7] , GOUT[11] );
BLOCK2 U312 (PIN[8] , PIN[10] , GIN[10] , GIN[12] , PHI , POUT[8] , GOUT[12] );
BLOCK2 U313 (PIN[9] , PIN[11] , GIN[11] , GIN[13] , PHI , POUT[9] , GOUT[13] );
BLOCK2 U314 (PIN[10] , PIN[12] , GIN[12] , GIN[14] , PHI , POUT[10] , GOUT[14] );
BLOCK2 U315 (PIN[11] , PIN[13] , GIN[13] , GIN[15] , PHI , POUT[11] , GOUT[15] );
BLOCK2 U316 (PIN[12] , PIN[14] , GIN[14] , GIN[16] , PHI , POUT[12] , GOUT[16] );
BLOCK2 U317 (PIN[13] , PIN[15] , GIN[15] , GIN[17] , PHI , POUT[13] , GOUT[17] );
BLOCK2 U318 (PIN[14] , PIN[16] , GIN[16] , GIN[18] , PHI , POUT[14] , GOUT[18] );
BLOCK2 U319 (PIN[15] , PIN[17] , GIN[17] , GIN[19] , PHI , POUT[15] , GOUT[19] );
BLOCK2 U320 (PIN[16] , PIN[18] , GIN[18] , GIN[20] , PHI , POUT[16] , GOUT[20] );
BLOCK2 U321 (PIN[17] , PIN[19] , GIN[19] , GIN[21] , PHI , POUT[17] , GOUT[21] );
BLOCK2 U322 (PIN[18] , PIN[20] , GIN[20] , GIN[22] , PHI , POUT[18] , GOUT[22] );
BLOCK2 U323 (PIN[19] , PIN[21] , GIN[21] , GIN[23] , PHI , POUT[19] , GOUT[23] );
BLOCK2 U324 (PIN[20] , PIN[22] , GIN[22] , GIN[24] , PHI , POUT[20] , GOUT[24] );
BLOCK2 U325 (PIN[21] , PIN[23] , GIN[23] , GIN[25] , PHI , POUT[21] , GOUT[25] );
BLOCK2 U326 (PIN[22] , PIN[24] , GIN[24] , GIN[26] , PHI , POUT[22] , GOUT[26] );
BLOCK2 U327 (PIN[23] , PIN[25] , GIN[25] , GIN[27] , PHI , POUT[23] , GOUT[27] );
BLOCK2 U328 (PIN[24] , PIN[26] , GIN[26] , GIN[28] , PHI , POUT[24] , GOUT[28] );
BLOCK2 U329 (PIN[25] , PIN[27] , GIN[27] , GIN[29] , PHI , POUT[25] , GOUT[29] );
BLOCK2 U330 (PIN[26] , PIN[28] , GIN[28] , GIN[30] , PHI , POUT[26] , GOUT[30] );
BLOCK2 U331 (PIN[27] , PIN[29] , GIN[29] , GIN[31] , PHI , POUT[27] , GOUT[31] );
BLOCK2 U332 (PIN[28] , PIN[30] , GIN[30] , GIN[32] , PHI , POUT[28] , GOUT[32] );
BLOCK2 U333 (PIN[29] , PIN[31] , GIN[31] , GIN[33] , PHI , POUT[29] , GOUT[33] );
BLOCK2 U334 (PIN[30] , PIN[32] , GIN[32] , GIN[34] , PHI , POUT[30] , GOUT[34] );
BLOCK2 U335 (PIN[31] , PIN[33] , GIN[33] , GIN[35] , PHI , POUT[31] , GOUT[35] );
BLOCK2 U336 (PIN[32] , PIN[34] , GIN[34] , GIN[36] , PHI , POUT[32] , GOUT[36] );
BLOCK2 U337 (PIN[33] , PIN[35] , GIN[35] , GIN[37] , PHI , POUT[33] , GOUT[37] );
BLOCK2 U338 (PIN[34] , PIN[36] , GIN[36] , GIN[38] , PHI , POUT[34] , GOUT[38] );
BLOCK2 U339 (PIN[35] , PIN[37] , GIN[37] , GIN[39] , PHI , POUT[35] , GOUT[39] );
BLOCK2 U340 (PIN[36] , PIN[38] , GIN[38] , GIN[40] , PHI , POUT[36] , GOUT[40] );
BLOCK2 U341 (PIN[37] , PIN[39] , GIN[39] , GIN[41] , PHI , POUT[37] , GOUT[41] );
BLOCK2 U342 (PIN[38] , PIN[40] , GIN[40] , GIN[42] , PHI , POUT[38] , GOUT[42] );
BLOCK2 U343 (PIN[39] , PIN[41] , GIN[41] , GIN[43] , PHI , POUT[39] , GOUT[43] );
BLOCK2 U344 (PIN[40] , PIN[42] , GIN[42] , GIN[44] , PHI , POUT[40] , GOUT[44] );
BLOCK2 U345 (PIN[41] , PIN[43] , GIN[43] , GIN[45] , PHI , POUT[41] , GOUT[45] );
BLOCK2 U346 (PIN[42] , PIN[44] , GIN[44] , GIN[46] , PHI , POUT[42] , GOUT[46] );
BLOCK2 U347 (PIN[43] , PIN[45] , GIN[45] , GIN[47] , PHI , POUT[43] , GOUT[47] );
BLOCK2 U348 (PIN[44] , PIN[46] , GIN[46] , GIN[48] , PHI , POUT[44] , GOUT[48] );
BLOCK2 U349 (PIN[45] , PIN[47] , GIN[47] , GIN[49] , PHI , POUT[45] , GOUT[49] );
BLOCK2 U350 (PIN[46] , PIN[48] , GIN[48] , GIN[50] , PHI , POUT[46] , GOUT[50] );
BLOCK2 U351 (PIN[47] , PIN[49] , GIN[49] , GIN[51] , PHI , POUT[47] , GOUT[51] );
BLOCK2 U352 (PIN[48] , PIN[50] , GIN[50] , GIN[52] , PHI , POUT[48] , GOUT[52] );
BLOCK2 U353 (PIN[49] , PIN[51] , GIN[51] , GIN[53] , PHI , POUT[49] , GOUT[53] );
BLOCK2 U354 (PIN[50] , PIN[52] , GIN[52] , GIN[54] , PHI , POUT[50] , GOUT[54] );
BLOCK2 U355 (PIN[51] , PIN[53] , GIN[53] , GIN[55] , PHI , POUT[51] , GOUT[55] );
BLOCK2 U356 (PIN[52] , PIN[54] , GIN[54] , GIN[56] , PHI , POUT[52] , GOUT[56] );
BLOCK2 U357 (PIN[53] , PIN[55] , GIN[55] , GIN[57] , PHI , POUT[53] , GOUT[57] );
BLOCK2 U358 (PIN[54] , PIN[56] , GIN[56] , GIN[58] , PHI , POUT[54] , GOUT[58] );
BLOCK2 U359 (PIN[55] , PIN[57] , GIN[57] , GIN[59] , PHI , POUT[55] , GOUT[59] );
BLOCK2 U360 (PIN[56] , PIN[58] , GIN[58] , GIN[60] , PHI , POUT[56] , GOUT[60] );
BLOCK2 U361 (PIN[57] , PIN[59] , GIN[59] , GIN[61] , PHI , POUT[57] , GOUT[61] );
BLOCK2 U362 (PIN[58] , PIN[60] , GIN[60] , GIN[62] , PHI , POUT[58] , GOUT[62] );
BLOCK2 U363 (PIN[59] , PIN[61] , GIN[61] , GIN[63] , PHI , POUT[59] , GOUT[63] );
BLOCK2 U364 (PIN[60] , PIN[62] , GIN[62] , GIN[64] , PHI , POUT[60] , GOUT[64] );
endmodule
module DBLC_2_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:60] PIN;
input [0:64] GIN;
input PHI;
output [0:56] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
BLOCK1A U24 (PIN[0] , GIN[0] , GIN[4] , PHI , GOUT[4] );
BLOCK1A U25 (PIN[1] , GIN[1] , GIN[5] , PHI , GOUT[5] );
BLOCK1A U26 (PIN[2] , GIN[2] , GIN[6] , PHI , GOUT[6] );
BLOCK1A U27 (PIN[3] , GIN[3] , GIN[7] , PHI , GOUT[7] );
BLOCK1 U38 (PIN[0] , PIN[4] , GIN[4] , GIN[8] , PHI , POUT[0] , GOUT[8] );
BLOCK1 U39 (PIN[1] , PIN[5] , GIN[5] , GIN[9] , PHI , POUT[1] , GOUT[9] );
BLOCK1 U310 (PIN[2] , PIN[6] , GIN[6] , GIN[10] , PHI , POUT[2] , GOUT[10] );
BLOCK1 U311 (PIN[3] , PIN[7] , GIN[7] , GIN[11] , PHI , POUT[3] , GOUT[11] );
BLOCK1 U312 (PIN[4] , PIN[8] , GIN[8] , GIN[12] , PHI , POUT[4] , GOUT[12] );
BLOCK1 U313 (PIN[5] , PIN[9] , GIN[9] , GIN[13] , PHI , POUT[5] , GOUT[13] );
BLOCK1 U314 (PIN[6] , PIN[10] , GIN[10] , GIN[14] , PHI , POUT[6] , GOUT[14] );
BLOCK1 U315 (PIN[7] , PIN[11] , GIN[11] , GIN[15] , PHI , POUT[7] , GOUT[15] );
BLOCK1 U316 (PIN[8] , PIN[12] , GIN[12] , GIN[16] , PHI , POUT[8] , GOUT[16] );
BLOCK1 U317 (PIN[9] , PIN[13] , GIN[13] , GIN[17] , PHI , POUT[9] , GOUT[17] );
BLOCK1 U318 (PIN[10] , PIN[14] , GIN[14] , GIN[18] , PHI , POUT[10] , GOUT[18] );
BLOCK1 U319 (PIN[11] , PIN[15] , GIN[15] , GIN[19] , PHI , POUT[11] , GOUT[19] );
BLOCK1 U320 (PIN[12] , PIN[16] , GIN[16] , GIN[20] , PHI , POUT[12] , GOUT[20] );
BLOCK1 U321 (PIN[13] , PIN[17] , GIN[17] , GIN[21] , PHI , POUT[13] , GOUT[21] );
BLOCK1 U322 (PIN[14] , PIN[18] , GIN[18] , GIN[22] , PHI , POUT[14] , GOUT[22] );
BLOCK1 U323 (PIN[15] , PIN[19] , GIN[19] , GIN[23] , PHI , POUT[15] , GOUT[23] );
BLOCK1 U324 (PIN[16] , PIN[20] , GIN[20] , GIN[24] , PHI , POUT[16] , GOUT[24] );
BLOCK1 U325 (PIN[17] , PIN[21] , GIN[21] , GIN[25] , PHI , POUT[17] , GOUT[25] );
BLOCK1 U326 (PIN[18] , PIN[22] , GIN[22] , GIN[26] , PHI , POUT[18] , GOUT[26] );
BLOCK1 U327 (PIN[19] , PIN[23] , GIN[23] , GIN[27] , PHI , POUT[19] , GOUT[27] );
BLOCK1 U328 (PIN[20] , PIN[24] , GIN[24] , GIN[28] , PHI , POUT[20] , GOUT[28] );
BLOCK1 U329 (PIN[21] , PIN[25] , GIN[25] , GIN[29] , PHI , POUT[21] , GOUT[29] );
BLOCK1 U330 (PIN[22] , PIN[26] , GIN[26] , GIN[30] , PHI , POUT[22] , GOUT[30] );
BLOCK1 U331 (PIN[23] , PIN[27] , GIN[27] , GIN[31] , PHI , POUT[23] , GOUT[31] );
BLOCK1 U332 (PIN[24] , PIN[28] , GIN[28] , GIN[32] , PHI , POUT[24] , GOUT[32] );
BLOCK1 U333 (PIN[25] , PIN[29] , GIN[29] , GIN[33] , PHI , POUT[25] , GOUT[33] );
BLOCK1 U334 (PIN[26] , PIN[30] , GIN[30] , GIN[34] , PHI , POUT[26] , GOUT[34] );
BLOCK1 U335 (PIN[27] , PIN[31] , GIN[31] , GIN[35] , PHI , POUT[27] , GOUT[35] );
BLOCK1 U336 (PIN[28] , PIN[32] , GIN[32] , GIN[36] , PHI , POUT[28] , GOUT[36] );
BLOCK1 U337 (PIN[29] , PIN[33] , GIN[33] , GIN[37] , PHI , POUT[29] , GOUT[37] );
BLOCK1 U338 (PIN[30] , PIN[34] , GIN[34] , GIN[38] , PHI , POUT[30] , GOUT[38] );
BLOCK1 U339 (PIN[31] , PIN[35] , GIN[35] , GIN[39] , PHI , POUT[31] , GOUT[39] );
BLOCK1 U340 (PIN[32] , PIN[36] , GIN[36] , GIN[40] , PHI , POUT[32] , GOUT[40] );
BLOCK1 U341 (PIN[33] , PIN[37] , GIN[37] , GIN[41] , PHI , POUT[33] , GOUT[41] );
BLOCK1 U342 (PIN[34] , PIN[38] , GIN[38] , GIN[42] , PHI , POUT[34] , GOUT[42] );
BLOCK1 U343 (PIN[35] , PIN[39] , GIN[39] , GIN[43] , PHI , POUT[35] , GOUT[43] );
BLOCK1 U344 (PIN[36] , PIN[40] , GIN[40] , GIN[44] , PHI , POUT[36] , GOUT[44] );
BLOCK1 U345 (PIN[37] , PIN[41] , GIN[41] , GIN[45] , PHI , POUT[37] , GOUT[45] );
BLOCK1 U346 (PIN[38] , PIN[42] , GIN[42] , GIN[46] , PHI , POUT[38] , GOUT[46] );
BLOCK1 U347 (PIN[39] , PIN[43] , GIN[43] , GIN[47] , PHI , POUT[39] , GOUT[47] );
BLOCK1 U348 (PIN[40] , PIN[44] , GIN[44] , GIN[48] , PHI , POUT[40] , GOUT[48] );
BLOCK1 U349 (PIN[41] , PIN[45] , GIN[45] , GIN[49] , PHI , POUT[41] , GOUT[49] );
BLOCK1 U350 (PIN[42] , PIN[46] , GIN[46] , GIN[50] , PHI , POUT[42] , GOUT[50] );
BLOCK1 U351 (PIN[43] , PIN[47] , GIN[47] , GIN[51] , PHI , POUT[43] , GOUT[51] );
BLOCK1 U352 (PIN[44] , PIN[48] , GIN[48] , GIN[52] , PHI , POUT[44] , GOUT[52] );
BLOCK1 U353 (PIN[45] , PIN[49] , GIN[49] , GIN[53] , PHI , POUT[45] , GOUT[53] );
BLOCK1 U354 (PIN[46] , PIN[50] , GIN[50] , GIN[54] , PHI , POUT[46] , GOUT[54] );
BLOCK1 U355 (PIN[47] , PIN[51] , GIN[51] , GIN[55] , PHI , POUT[47] , GOUT[55] );
BLOCK1 U356 (PIN[48] , PIN[52] , GIN[52] , GIN[56] , PHI , POUT[48] , GOUT[56] );
BLOCK1 U357 (PIN[49] , PIN[53] , GIN[53] , GIN[57] , PHI , POUT[49] , GOUT[57] );
BLOCK1 U358 (PIN[50] , PIN[54] , GIN[54] , GIN[58] , PHI , POUT[50] , GOUT[58] );
BLOCK1 U359 (PIN[51] , PIN[55] , GIN[55] , GIN[59] , PHI , POUT[51] , GOUT[59] );
BLOCK1 U360 (PIN[52] , PIN[56] , GIN[56] , GIN[60] , PHI , POUT[52] , GOUT[60] );
BLOCK1 U361 (PIN[53] , PIN[57] , GIN[57] , GIN[61] , PHI , POUT[53] , GOUT[61] );
BLOCK1 U362 (PIN[54] , PIN[58] , GIN[58] , GIN[62] , PHI , POUT[54] , GOUT[62] );
BLOCK1 U363 (PIN[55] , PIN[59] , GIN[59] , GIN[63] , PHI , POUT[55] , GOUT[63] );
BLOCK1 U364 (PIN[56] , PIN[60] , GIN[60] , GIN[64] , PHI , POUT[56] , GOUT[64] );
endmodule
module DBLC_3_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:56] PIN;
input [0:64] GIN;
input PHI;
output [0:48] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
INVBLOCK U14 (GIN[4] , PHI , GOUT[4] );
INVBLOCK U15 (GIN[5] , PHI , GOUT[5] );
INVBLOCK U16 (GIN[6] , PHI , GOUT[6] );
INVBLOCK U17 (GIN[7] , PHI , GOUT[7] );
BLOCK2A U28 (PIN[0] , GIN[0] , GIN[8] , PHI , GOUT[8] );
BLOCK2A U29 (PIN[1] , GIN[1] , GIN[9] , PHI , GOUT[9] );
BLOCK2A U210 (PIN[2] , GIN[2] , GIN[10] , PHI , GOUT[10] );
BLOCK2A U211 (PIN[3] , GIN[3] , GIN[11] , PHI , GOUT[11] );
BLOCK2A U212 (PIN[4] , GIN[4] , GIN[12] , PHI , GOUT[12] );
BLOCK2A U213 (PIN[5] , GIN[5] , GIN[13] , PHI , GOUT[13] );
BLOCK2A U214 (PIN[6] , GIN[6] , GIN[14] , PHI , GOUT[14] );
BLOCK2A U215 (PIN[7] , GIN[7] , GIN[15] , PHI , GOUT[15] );
BLOCK2 U316 (PIN[0] , PIN[8] , GIN[8] , GIN[16] , PHI , POUT[0] , GOUT[16] );
BLOCK2 U317 (PIN[1] , PIN[9] , GIN[9] , GIN[17] , PHI , POUT[1] , GOUT[17] );
BLOCK2 U318 (PIN[2] , PIN[10] , GIN[10] , GIN[18] , PHI , POUT[2] , GOUT[18] );
BLOCK2 U319 (PIN[3] , PIN[11] , GIN[11] , GIN[19] , PHI , POUT[3] , GOUT[19] );
BLOCK2 U320 (PIN[4] , PIN[12] , GIN[12] , GIN[20] , PHI , POUT[4] , GOUT[20] );
BLOCK2 U321 (PIN[5] , PIN[13] , GIN[13] , GIN[21] , PHI , POUT[5] , GOUT[21] );
BLOCK2 U322 (PIN[6] , PIN[14] , GIN[14] , GIN[22] , PHI , POUT[6] , GOUT[22] );
BLOCK2 U323 (PIN[7] , PIN[15] , GIN[15] , GIN[23] , PHI , POUT[7] , GOUT[23] );
BLOCK2 U324 (PIN[8] , PIN[16] , GIN[16] , GIN[24] , PHI , POUT[8] , GOUT[24] );
BLOCK2 U325 (PIN[9] , PIN[17] , GIN[17] , GIN[25] , PHI , POUT[9] , GOUT[25] );
BLOCK2 U326 (PIN[10] , PIN[18] , GIN[18] , GIN[26] , PHI , POUT[10] , GOUT[26] );
BLOCK2 U327 (PIN[11] , PIN[19] , GIN[19] , GIN[27] , PHI , POUT[11] , GOUT[27] );
BLOCK2 U328 (PIN[12] , PIN[20] , GIN[20] , GIN[28] , PHI , POUT[12] , GOUT[28] );
BLOCK2 U329 (PIN[13] , PIN[21] , GIN[21] , GIN[29] , PHI , POUT[13] , GOUT[29] );
BLOCK2 U330 (PIN[14] , PIN[22] , GIN[22] , GIN[30] , PHI , POUT[14] , GOUT[30] );
BLOCK2 U331 (PIN[15] , PIN[23] , GIN[23] , GIN[31] , PHI , POUT[15] , GOUT[31] );
BLOCK2 U332 (PIN[16] , PIN[24] , GIN[24] , GIN[32] , PHI , POUT[16] , GOUT[32] );
BLOCK2 U333 (PIN[17] , PIN[25] , GIN[25] , GIN[33] , PHI , POUT[17] , GOUT[33] );
BLOCK2 U334 (PIN[18] , PIN[26] , GIN[26] , GIN[34] , PHI , POUT[18] , GOUT[34] );
BLOCK2 U335 (PIN[19] , PIN[27] , GIN[27] , GIN[35] , PHI , POUT[19] , GOUT[35] );
BLOCK2 U336 (PIN[20] , PIN[28] , GIN[28] , GIN[36] , PHI , POUT[20] , GOUT[36] );
BLOCK2 U337 (PIN[21] , PIN[29] , GIN[29] , GIN[37] , PHI , POUT[21] , GOUT[37] );
BLOCK2 U338 (PIN[22] , PIN[30] , GIN[30] , GIN[38] , PHI , POUT[22] , GOUT[38] );
BLOCK2 U339 (PIN[23] , PIN[31] , GIN[31] , GIN[39] , PHI , POUT[23] , GOUT[39] );
BLOCK2 U340 (PIN[24] , PIN[32] , GIN[32] , GIN[40] , PHI , POUT[24] , GOUT[40] );
BLOCK2 U341 (PIN[25] , PIN[33] , GIN[33] , GIN[41] , PHI , POUT[25] , GOUT[41] );
BLOCK2 U342 (PIN[26] , PIN[34] , GIN[34] , GIN[42] , PHI , POUT[26] , GOUT[42] );
BLOCK2 U343 (PIN[27] , PIN[35] , GIN[35] , GIN[43] , PHI , POUT[27] , GOUT[43] );
BLOCK2 U344 (PIN[28] , PIN[36] , GIN[36] , GIN[44] , PHI , POUT[28] , GOUT[44] );
BLOCK2 U345 (PIN[29] , PIN[37] , GIN[37] , GIN[45] , PHI , POUT[29] , GOUT[45] );
BLOCK2 U346 (PIN[30] , PIN[38] , GIN[38] , GIN[46] , PHI , POUT[30] , GOUT[46] );
BLOCK2 U347 (PIN[31] , PIN[39] , GIN[39] , GIN[47] , PHI , POUT[31] , GOUT[47] );
BLOCK2 U348 (PIN[32] , PIN[40] , GIN[40] , GIN[48] , PHI , POUT[32] , GOUT[48] );
BLOCK2 U349 (PIN[33] , PIN[41] , GIN[41] , GIN[49] , PHI , POUT[33] , GOUT[49] );
BLOCK2 U350 (PIN[34] , PIN[42] , GIN[42] , GIN[50] , PHI , POUT[34] , GOUT[50] );
BLOCK2 U351 (PIN[35] , PIN[43] , GIN[43] , GIN[51] , PHI , POUT[35] , GOUT[51] );
BLOCK2 U352 (PIN[36] , PIN[44] , GIN[44] , GIN[52] , PHI , POUT[36] , GOUT[52] );
BLOCK2 U353 (PIN[37] , PIN[45] , GIN[45] , GIN[53] , PHI , POUT[37] , GOUT[53] );
BLOCK2 U354 (PIN[38] , PIN[46] , GIN[46] , GIN[54] , PHI , POUT[38] , GOUT[54] );
BLOCK2 U355 (PIN[39] , PIN[47] , GIN[47] , GIN[55] , PHI , POUT[39] , GOUT[55] );
BLOCK2 U356 (PIN[40] , PIN[48] , GIN[48] , GIN[56] , PHI , POUT[40] , GOUT[56] );
BLOCK2 U357 (PIN[41] , PIN[49] , GIN[49] , GIN[57] , PHI , POUT[41] , GOUT[57] );
BLOCK2 U358 (PIN[42] , PIN[50] , GIN[50] , GIN[58] , PHI , POUT[42] , GOUT[58] );
BLOCK2 U359 (PIN[43] , PIN[51] , GIN[51] , GIN[59] , PHI , POUT[43] , GOUT[59] );
BLOCK2 U360 (PIN[44] , PIN[52] , GIN[52] , GIN[60] , PHI , POUT[44] , GOUT[60] );
BLOCK2 U361 (PIN[45] , PIN[53] , GIN[53] , GIN[61] , PHI , POUT[45] , GOUT[61] );
BLOCK2 U362 (PIN[46] , PIN[54] , GIN[54] , GIN[62] , PHI , POUT[46] , GOUT[62] );
BLOCK2 U363 (PIN[47] , PIN[55] , GIN[55] , GIN[63] , PHI , POUT[47] , GOUT[63] );
BLOCK2 U364 (PIN[48] , PIN[56] , GIN[56] , GIN[64] , PHI , POUT[48] , GOUT[64] );
endmodule
module DBLC_4_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:48] PIN;
input [0:64] GIN;
input PHI;
output [0:32] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
INVBLOCK U14 (GIN[4] , PHI , GOUT[4] );
INVBLOCK U15 (GIN[5] , PHI , GOUT[5] );
INVBLOCK U16 (GIN[6] , PHI , GOUT[6] );
INVBLOCK U17 (GIN[7] , PHI , GOUT[7] );
INVBLOCK U18 (GIN[8] , PHI , GOUT[8] );
INVBLOCK U19 (GIN[9] , PHI , GOUT[9] );
INVBLOCK U110 (GIN[10] , PHI , GOUT[10] );
INVBLOCK U111 (GIN[11] , PHI , GOUT[11] );
INVBLOCK U112 (GIN[12] , PHI , GOUT[12] );
INVBLOCK U113 (GIN[13] , PHI , GOUT[13] );
INVBLOCK U114 (GIN[14] , PHI , GOUT[14] );
INVBLOCK U115 (GIN[15] , PHI , GOUT[15] );
BLOCK1A U216 (PIN[0] , GIN[0] , GIN[16] , PHI , GOUT[16] );
BLOCK1A U217 (PIN[1] , GIN[1] , GIN[17] , PHI , GOUT[17] );
BLOCK1A U218 (PIN[2] , GIN[2] , GIN[18] , PHI , GOUT[18] );
BLOCK1A U219 (PIN[3] , GIN[3] , GIN[19] , PHI , GOUT[19] );
BLOCK1A U220 (PIN[4] , GIN[4] , GIN[20] , PHI , GOUT[20] );
BLOCK1A U221 (PIN[5] , GIN[5] , GIN[21] , PHI , GOUT[21] );
BLOCK1A U222 (PIN[6] , GIN[6] , GIN[22] , PHI , GOUT[22] );
BLOCK1A U223 (PIN[7] , GIN[7] , GIN[23] , PHI , GOUT[23] );
BLOCK1A U224 (PIN[8] , GIN[8] , GIN[24] , PHI , GOUT[24] );
BLOCK1A U225 (PIN[9] , GIN[9] , GIN[25] , PHI , GOUT[25] );
BLOCK1A U226 (PIN[10] , GIN[10] , GIN[26] , PHI , GOUT[26] );
BLOCK1A U227 (PIN[11] , GIN[11] , GIN[27] , PHI , GOUT[27] );
BLOCK1A U228 (PIN[12] , GIN[12] , GIN[28] , PHI , GOUT[28] );
BLOCK1A U229 (PIN[13] , GIN[13] , GIN[29] , PHI , GOUT[29] );
BLOCK1A U230 (PIN[14] , GIN[14] , GIN[30] , PHI , GOUT[30] );
BLOCK1A U231 (PIN[15] , GIN[15] , GIN[31] , PHI , GOUT[31] );
BLOCK1 U332 (PIN[0] , PIN[16] , GIN[16] , GIN[32] , PHI , POUT[0] , GOUT[32] );
BLOCK1 U333 (PIN[1] , PIN[17] , GIN[17] , GIN[33] , PHI , POUT[1] , GOUT[33] );
BLOCK1 U334 (PIN[2] , PIN[18] , GIN[18] , GIN[34] , PHI , POUT[2] , GOUT[34] );
BLOCK1 U335 (PIN[3] , PIN[19] , GIN[19] , GIN[35] , PHI , POUT[3] , GOUT[35] );
BLOCK1 U336 (PIN[4] , PIN[20] , GIN[20] , GIN[36] , PHI , POUT[4] , GOUT[36] );
BLOCK1 U337 (PIN[5] , PIN[21] , GIN[21] , GIN[37] , PHI , POUT[5] , GOUT[37] );
BLOCK1 U338 (PIN[6] , PIN[22] , GIN[22] , GIN[38] , PHI , POUT[6] , GOUT[38] );
BLOCK1 U339 (PIN[7] , PIN[23] , GIN[23] , GIN[39] , PHI , POUT[7] , GOUT[39] );
BLOCK1 U340 (PIN[8] , PIN[24] , GIN[24] , GIN[40] , PHI , POUT[8] , GOUT[40] );
BLOCK1 U341 (PIN[9] , PIN[25] , GIN[25] , GIN[41] , PHI , POUT[9] , GOUT[41] );
BLOCK1 U342 (PIN[10] , PIN[26] , GIN[26] , GIN[42] , PHI , POUT[10] , GOUT[42] );
BLOCK1 U343 (PIN[11] , PIN[27] , GIN[27] , GIN[43] , PHI , POUT[11] , GOUT[43] );
BLOCK1 U344 (PIN[12] , PIN[28] , GIN[28] , GIN[44] , PHI , POUT[12] , GOUT[44] );
BLOCK1 U345 (PIN[13] , PIN[29] , GIN[29] , GIN[45] , PHI , POUT[13] , GOUT[45] );
BLOCK1 U346 (PIN[14] , PIN[30] , GIN[30] , GIN[46] , PHI , POUT[14] , GOUT[46] );
BLOCK1 U347 (PIN[15] , PIN[31] , GIN[31] , GIN[47] , PHI , POUT[15] , GOUT[47] );
BLOCK1 U348 (PIN[16] , PIN[32] , GIN[32] , GIN[48] , PHI , POUT[16] , GOUT[48] );
BLOCK1 U349 (PIN[17] , PIN[33] , GIN[33] , GIN[49] , PHI , POUT[17] , GOUT[49] );
BLOCK1 U350 (PIN[18] , PIN[34] , GIN[34] , GIN[50] , PHI , POUT[18] , GOUT[50] );
BLOCK1 U351 (PIN[19] , PIN[35] , GIN[35] , GIN[51] , PHI , POUT[19] , GOUT[51] );
BLOCK1 U352 (PIN[20] , PIN[36] , GIN[36] , GIN[52] , PHI , POUT[20] , GOUT[52] );
BLOCK1 U353 (PIN[21] , PIN[37] , GIN[37] , GIN[53] , PHI , POUT[21] , GOUT[53] );
BLOCK1 U354 (PIN[22] , PIN[38] , GIN[38] , GIN[54] , PHI , POUT[22] , GOUT[54] );
BLOCK1 U355 (PIN[23] , PIN[39] , GIN[39] , GIN[55] , PHI , POUT[23] , GOUT[55] );
BLOCK1 U356 (PIN[24] , PIN[40] , GIN[40] , GIN[56] , PHI , POUT[24] , GOUT[56] );
BLOCK1 U357 (PIN[25] , PIN[41] , GIN[41] , GIN[57] , PHI , POUT[25] , GOUT[57] );
BLOCK1 U358 (PIN[26] , PIN[42] , GIN[42] , GIN[58] , PHI , POUT[26] , GOUT[58] );
BLOCK1 U359 (PIN[27] , PIN[43] , GIN[43] , GIN[59] , PHI , POUT[27] , GOUT[59] );
BLOCK1 U360 (PIN[28] , PIN[44] , GIN[44] , GIN[60] , PHI , POUT[28] , GOUT[60] );
BLOCK1 U361 (PIN[29] , PIN[45] , GIN[45] , GIN[61] , PHI , POUT[29] , GOUT[61] );
BLOCK1 U362 (PIN[30] , PIN[46] , GIN[46] , GIN[62] , PHI , POUT[30] , GOUT[62] );
BLOCK1 U363 (PIN[31] , PIN[47] , GIN[47] , GIN[63] , PHI , POUT[31] , GOUT[63] );
BLOCK1 U364 (PIN[32] , PIN[48] , GIN[48] , GIN[64] , PHI , POUT[32] , GOUT[64] );
endmodule
module DBLC_5_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:32] PIN;
input [0:64] GIN;
input PHI;
output [0:0] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
INVBLOCK U14 (GIN[4] , PHI , GOUT[4] );
INVBLOCK U15 (GIN[5] , PHI , GOUT[5] );
INVBLOCK U16 (GIN[6] , PHI , GOUT[6] );
INVBLOCK U17 (GIN[7] , PHI , GOUT[7] );
INVBLOCK U18 (GIN[8] , PHI , GOUT[8] );
INVBLOCK U19 (GIN[9] , PHI , GOUT[9] );
INVBLOCK U110 (GIN[10] , PHI , GOUT[10] );
INVBLOCK U111 (GIN[11] , PHI , GOUT[11] );
INVBLOCK U112 (GIN[12] , PHI , GOUT[12] );
INVBLOCK U113 (GIN[13] , PHI , GOUT[13] );
INVBLOCK U114 (GIN[14] , PHI , GOUT[14] );
INVBLOCK U115 (GIN[15] , PHI , GOUT[15] );
INVBLOCK U116 (GIN[16] , PHI , GOUT[16] );
INVBLOCK U117 (GIN[17] , PHI , GOUT[17] );
INVBLOCK U118 (GIN[18] , PHI , GOUT[18] );
INVBLOCK U119 (GIN[19] , PHI , GOUT[19] );
INVBLOCK U120 (GIN[20] , PHI , GOUT[20] );
INVBLOCK U121 (GIN[21] , PHI , GOUT[21] );
INVBLOCK U122 (GIN[22] , PHI , GOUT[22] );
INVBLOCK U123 (GIN[23] , PHI , GOUT[23] );
INVBLOCK U124 (GIN[24] , PHI , GOUT[24] );
INVBLOCK U125 (GIN[25] , PHI , GOUT[25] );
INVBLOCK U126 (GIN[26] , PHI , GOUT[26] );
INVBLOCK U127 (GIN[27] , PHI , GOUT[27] );
INVBLOCK U128 (GIN[28] , PHI , GOUT[28] );
INVBLOCK U129 (GIN[29] , PHI , GOUT[29] );
INVBLOCK U130 (GIN[30] , PHI , GOUT[30] );
INVBLOCK U131 (GIN[31] , PHI , GOUT[31] );
BLOCK2A U232 (PIN[0] , GIN[0] , GIN[32] , PHI , GOUT[32] );
BLOCK2A U233 (PIN[1] , GIN[1] , GIN[33] , PHI , GOUT[33] );
BLOCK2A U234 (PIN[2] , GIN[2] , GIN[34] , PHI , GOUT[34] );
BLOCK2A U235 (PIN[3] , GIN[3] , GIN[35] , PHI , GOUT[35] );
BLOCK2A U236 (PIN[4] , GIN[4] , GIN[36] , PHI , GOUT[36] );
BLOCK2A U237 (PIN[5] , GIN[5] , GIN[37] , PHI , GOUT[37] );
BLOCK2A U238 (PIN[6] , GIN[6] , GIN[38] , PHI , GOUT[38] );
BLOCK2A U239 (PIN[7] , GIN[7] , GIN[39] , PHI , GOUT[39] );
BLOCK2A U240 (PIN[8] , GIN[8] , GIN[40] , PHI , GOUT[40] );
BLOCK2A U241 (PIN[9] , GIN[9] , GIN[41] , PHI , GOUT[41] );
BLOCK2A U242 (PIN[10] , GIN[10] , GIN[42] , PHI , GOUT[42] );
BLOCK2A U243 (PIN[11] , GIN[11] , GIN[43] , PHI , GOUT[43] );
BLOCK2A U244 (PIN[12] , GIN[12] , GIN[44] , PHI , GOUT[44] );
BLOCK2A U245 (PIN[13] , GIN[13] , GIN[45] , PHI , GOUT[45] );
BLOCK2A U246 (PIN[14] , GIN[14] , GIN[46] , PHI , GOUT[46] );
BLOCK2A U247 (PIN[15] , GIN[15] , GIN[47] , PHI , GOUT[47] );
BLOCK2A U248 (PIN[16] , GIN[16] , GIN[48] , PHI , GOUT[48] );
BLOCK2A U249 (PIN[17] , GIN[17] , GIN[49] , PHI , GOUT[49] );
BLOCK2A U250 (PIN[18] , GIN[18] , GIN[50] , PHI , GOUT[50] );
BLOCK2A U251 (PIN[19] , GIN[19] , GIN[51] , PHI , GOUT[51] );
BLOCK2A U252 (PIN[20] , GIN[20] , GIN[52] , PHI , GOUT[52] );
BLOCK2A U253 (PIN[21] , GIN[21] , GIN[53] , PHI , GOUT[53] );
BLOCK2A U254 (PIN[22] , GIN[22] , GIN[54] , PHI , GOUT[54] );
BLOCK2A U255 (PIN[23] , GIN[23] , GIN[55] , PHI , GOUT[55] );
BLOCK2A U256 (PIN[24] , GIN[24] , GIN[56] , PHI , GOUT[56] );
BLOCK2A U257 (PIN[25] , GIN[25] , GIN[57] , PHI , GOUT[57] );
BLOCK2A U258 (PIN[26] , GIN[26] , GIN[58] , PHI , GOUT[58] );
BLOCK2A U259 (PIN[27] , GIN[27] , GIN[59] , PHI , GOUT[59] );
BLOCK2A U260 (PIN[28] , GIN[28] , GIN[60] , PHI , GOUT[60] );
BLOCK2A U261 (PIN[29] , GIN[29] , GIN[61] , PHI , GOUT[61] );
BLOCK2A U262 (PIN[30] , GIN[30] , GIN[62] , PHI , GOUT[62] );
BLOCK2A U263 (PIN[31] , GIN[31] , GIN[63] , PHI , GOUT[63] );
BLOCK2 U364 (PIN[0] , PIN[32] , GIN[32] , GIN[64] , PHI , POUT[0] , GOUT[64] );
endmodule
module XORSTAGE_64 ( A, B, PBIT, PHI, CARRY, SUM, COUT );
input [0:63] A;
input [0:63] B;
input PBIT;
input PHI;
input [0:64] CARRY;
output [0:63] SUM;
output COUT;
XXOR1 U20 (A[0] , B[0] , CARRY[0] , PHI , SUM[0] );
XXOR1 U21 (A[1] , B[1] , CARRY[1] , PHI , SUM[1] );
XXOR1 U22 (A[2] , B[2] , CARRY[2] , PHI , SUM[2] );
XXOR1 U23 (A[3] , B[3] , CARRY[3] , PHI , SUM[3] );
XXOR1 U24 (A[4] , B[4] , CARRY[4] , PHI , SUM[4] );
XXOR1 U25 (A[5] , B[5] , CARRY[5] , PHI , SUM[5] );
XXOR1 U26 (A[6] , B[6] , CARRY[6] , PHI , SUM[6] );
XXOR1 U27 (A[7] , B[7] , CARRY[7] , PHI , SUM[7] );
XXOR1 U28 (A[8] , B[8] , CARRY[8] , PHI , SUM[8] );
XXOR1 U29 (A[9] , B[9] , CARRY[9] , PHI , SUM[9] );
XXOR1 U210 (A[10] , B[10] , CARRY[10] , PHI , SUM[10] );
XXOR1 U211 (A[11] , B[11] , CARRY[11] , PHI , SUM[11] );
XXOR1 U212 (A[12] , B[12] , CARRY[12] , PHI , SUM[12] );
XXOR1 U213 (A[13] , B[13] , CARRY[13] , PHI , SUM[13] );
XXOR1 U214 (A[14] , B[14] , CARRY[14] , PHI , SUM[14] );
XXOR1 U215 (A[15] , B[15] , CARRY[15] , PHI , SUM[15] );
XXOR1 U216 (A[16] , B[16] , CARRY[16] , PHI , SUM[16] );
XXOR1 U217 (A[17] , B[17] , CARRY[17] , PHI , SUM[17] );
XXOR1 U218 (A[18] , B[18] , CARRY[18] , PHI , SUM[18] );
XXOR1 U219 (A[19] , B[19] , CARRY[19] , PHI , SUM[19] );
XXOR1 U220 (A[20] , B[20] , CARRY[20] , PHI , SUM[20] );
XXOR1 U221 (A[21] , B[21] , CARRY[21] , PHI , SUM[21] );
XXOR1 U222 (A[22] , B[22] , CARRY[22] , PHI , SUM[22] );
XXOR1 U223 (A[23] , B[23] , CARRY[23] , PHI , SUM[23] );
XXOR1 U224 (A[24] , B[24] , CARRY[24] , PHI , SUM[24] );
XXOR1 U225 (A[25] , B[25] , CARRY[25] , PHI , SUM[25] );
XXOR1 U226 (A[26] , B[26] , CARRY[26] , PHI , SUM[26] );
XXOR1 U227 (A[27] , B[27] , CARRY[27] , PHI , SUM[27] );
XXOR1 U228 (A[28] , B[28] , CARRY[28] , PHI , SUM[28] );
XXOR1 U229 (A[29] , B[29] , CARRY[29] , PHI , SUM[29] );
XXOR1 U230 (A[30] , B[30] , CARRY[30] , PHI , SUM[30] );
XXOR1 U231 (A[31] , B[31] , CARRY[31] , PHI , SUM[31] );
XXOR1 U232 (A[32] , B[32] , CARRY[32] , PHI , SUM[32] );
XXOR1 U233 (A[33] , B[33] , CARRY[33] , PHI , SUM[33] );
XXOR1 U234 (A[34] , B[34] , CARRY[34] , PHI , SUM[34] );
XXOR1 U235 (A[35] , B[35] , CARRY[35] , PHI , SUM[35] );
XXOR1 U236 (A[36] , B[36] , CARRY[36] , PHI , SUM[36] );
XXOR1 U237 (A[37] , B[37] , CARRY[37] , PHI , SUM[37] );
XXOR1 U238 (A[38] , B[38] , CARRY[38] , PHI , SUM[38] );
XXOR1 U239 (A[39] , B[39] , CARRY[39] , PHI , SUM[39] );
XXOR1 U240 (A[40] , B[40] , CARRY[40] , PHI , SUM[40] );
XXOR1 U241 (A[41] , B[41] , CARRY[41] , PHI , SUM[41] );
XXOR1 U242 (A[42] , B[42] , CARRY[42] , PHI , SUM[42] );
XXOR1 U243 (A[43] , B[43] , CARRY[43] , PHI , SUM[43] );
XXOR1 U244 (A[44] , B[44] , CARRY[44] , PHI , SUM[44] );
XXOR1 U245 (A[45] , B[45] , CARRY[45] , PHI , SUM[45] );
XXOR1 U246 (A[46] , B[46] , CARRY[46] , PHI , SUM[46] );
XXOR1 U247 (A[47] , B[47] , CARRY[47] , PHI , SUM[47] );
XXOR1 U248 (A[48] , B[48] , CARRY[48] , PHI , SUM[48] );
XXOR1 U249 (A[49] , B[49] , CARRY[49] , PHI , SUM[49] );
XXOR1 U250 (A[50] , B[50] , CARRY[50] , PHI , SUM[50] );
XXOR1 U251 (A[51] , B[51] , CARRY[51] , PHI , SUM[51] );
XXOR1 U252 (A[52] , B[52] , CARRY[52] , PHI , SUM[52] );
XXOR1 U253 (A[53] , B[53] , CARRY[53] , PHI , SUM[53] );
XXOR1 U254 (A[54] , B[54] , CARRY[54] , PHI , SUM[54] );
XXOR1 U255 (A[55] , B[55] , CARRY[55] , PHI , SUM[55] );
XXOR1 U256 (A[56] , B[56] , CARRY[56] , PHI , SUM[56] );
XXOR1 U257 (A[57] , B[57] , CARRY[57] , PHI , SUM[57] );
XXOR1 U258 (A[58] , B[58] , CARRY[58] , PHI , SUM[58] );
XXOR1 U259 (A[59] , B[59] , CARRY[59] , PHI , SUM[59] );
XXOR1 U260 (A[60] , B[60] , CARRY[60] , PHI , SUM[60] );
XXOR1 U261 (A[61] , B[61] , CARRY[61] , PHI , SUM[61] );
XXOR1 U262 (A[62] , B[62] , CARRY[62] , PHI , SUM[62] );
XXOR1 U263 (A[63] , B[63] , CARRY[63] , PHI , SUM[63] );
BLOCK1A U1 (PBIT , CARRY[0] , CARRY[64] , PHI , COUT );
endmodule
module DBLCTREE_64 ( PIN, GIN, PHI, GOUT, POUT );
input [0:63] PIN;
input [0:64] GIN;
input PHI;
output [0:64] GOUT;
output [0:0] POUT;
wire [0:62] INTPROP_0;
wire [0:64] INTGEN_0;
wire [0:60] INTPROP_1;
wire [0:64] INTGEN_1;
wire [0:56] INTPROP_2;
wire [0:64] INTGEN_2;
wire [0:48] INTPROP_3;
wire [0:64] INTGEN_3;
wire [0:32] INTPROP_4;
wire [0:64] INTGEN_4;
DBLC_0_64 U_0 (.PIN(PIN) , .GIN(GIN) , .PHI(PHI) , .POUT(INTPROP_0) , .GOUT(INTGEN_0) );
DBLC_1_64 U_1 (.PIN(INTPROP_0) , .GIN(INTGEN_0) , .PHI(PHI) , .POUT(INTPROP_1) , .GOUT(INTGEN_1) );
DBLC_2_64 U_2 (.PIN(INTPROP_1) , .GIN(INTGEN_1) , .PHI(PHI) , .POUT(INTPROP_2) , .GOUT(INTGEN_2) );
DBLC_3_64 U_3 (.PIN(INTPROP_2) , .GIN(INTGEN_2) , .PHI(PHI) , .POUT(INTPROP_3) , .GOUT(INTGEN_3) );
DBLC_4_64 U_4 (.PIN(INTPROP_3) , .GIN(INTGEN_3) , .PHI(PHI) , .POUT(INTPROP_4) , .GOUT(INTGEN_4) );
DBLC_5_64 U_5 (.PIN(INTPROP_4) , .GIN(INTGEN_4) , .PHI(PHI) , .POUT(POUT) , .GOUT(GOUT) );
endmodule
module DBLCADDER_64_64 ( OPA, OPB, CIN, PHI, SUM, COUT );
input [0:63] OPA;
input [0:63] OPB;
input CIN;
input PHI;
output [0:63] SUM;
output COUT;
wire [0:63] INTPROP;
wire [0:64] INTGEN;
wire [0:0] PBIT;
wire [0:64] CARRY;
PRESTAGE_64 U1 (OPA , OPB , CIN , PHI , INTPROP , INTGEN );
DBLCTREE_64 U2 (INTPROP , INTGEN , PHI , CARRY , PBIT );
XORSTAGE_64 U3 (OPA[0:63] , OPB[0:63] , PBIT[0] , PHI , CARRY[0:64] , SUM , COUT );
endmodule
module MULTIPLIER_33_32 ( MULTIPLICAND, MULTIPLIER, RST, CLK, PHI, RESULT );
input [0:32] MULTIPLICAND;
input [0:31] MULTIPLIER;
input RST;
input CLK;
input PHI;
output [0:63] RESULT;
wire [0:575] PPBIT;
wire [0:64] INT_CARRY;
wire [0:63] INT_SUM;
wire LOGIC_ZERO;
wire [0:63] ARESULT;
reg [0:63] RESULT;
assign LOGIC_ZERO = 0;
BOOTHCODER_33_32 B (.OPA(MULTIPLICAND[0:32]) , .OPB(MULTIPLIER[0:31]) , .SUMMAND(PPBIT[0:575]) );
WALLACE_33_32 W (.SUMMAND(PPBIT[0:575]) , .RST(RST), .CLK (CLK) , .CARRY(INT_CARRY[1:63]) , .SUM(INT_SUM[0:63]) );
assign INT_CARRY[0] = LOGIC_ZERO;
DBLCADDER_64_64 D (.OPA(INT_SUM[0:63]) , .OPB(INT_CARRY[0:63]) , .CIN (LOGIC_ZERO) , .PHI (PHI) , .SUM(ARESULT[0:63]), .COUT() );
always @(posedge CLK or posedge RST)
if (RST)
RESULT <= #1 64'h0000_0000_0000_0000;
else
RESULT <= ARESULT;
endmodule
// 32x32 multiplier, no input/output registers
// Registers inside Wallace trees every 8 full adder levels,
// with first pipeline after level 4
module or1200_amultp2_32x32 ( X, Y, RST, CLK, P );
input [31:0] X;
input [31:0] Y;
input RST;
input CLK;
output [63:0] P;
wire [0:32] A;
wire [0:31] B;
wire [0:63] Q;
assign A[0] = X[0];
assign A[1] = X[1];
assign A[2] = X[2];
assign A[3] = X[3];
assign A[4] = X[4];
assign A[5] = X[5];
assign A[6] = X[6];
assign A[7] = X[7];
assign A[8] = X[8];
assign A[9] = X[9];
assign A[10] = X[10];
assign A[11] = X[11];
assign A[12] = X[12];
assign A[13] = X[13];
assign A[14] = X[14];
assign A[15] = X[15];
assign A[16] = X[16];
assign A[17] = X[17];
assign A[18] = X[18];
assign A[19] = X[19];
assign A[20] = X[20];
assign A[21] = X[21];
assign A[22] = X[22];
assign A[23] = X[23];
assign A[24] = X[24];
assign A[25] = X[25];
assign A[26] = X[26];
assign A[27] = X[27];
assign A[28] = X[28];
assign A[29] = X[29];
assign A[30] = X[30];
assign A[31] = X[31];
assign A[32] = X[31];
assign B[0] = Y[0];
assign B[1] = Y[1];
assign B[2] = Y[2];
assign B[3] = Y[3];
assign B[4] = Y[4];
assign B[5] = Y[5];
assign B[6] = Y[6];
assign B[7] = Y[7];
assign B[8] = Y[8];
assign B[9] = Y[9];
assign B[10] = Y[10];
assign B[11] = Y[11];
assign B[12] = Y[12];
assign B[13] = Y[13];
assign B[14] = Y[14];
assign B[15] = Y[15];
assign B[16] = Y[16];
assign B[17] = Y[17];
assign B[18] = Y[18];
assign B[19] = Y[19];
assign B[20] = Y[20];
assign B[21] = Y[21];
assign B[22] = Y[22];
assign B[23] = Y[23];
assign B[24] = Y[24];
assign B[25] = Y[25];
assign B[26] = Y[26];
assign B[27] = Y[27];
assign B[28] = Y[28];
assign B[29] = Y[29];
assign B[30] = Y[30];
assign B[31] = Y[31];
assign P[0] = Q[0];
assign P[1] = Q[1];
assign P[2] = Q[2];
assign P[3] = Q[3];
assign P[4] = Q[4];
assign P[5] = Q[5];
assign P[6] = Q[6];
assign P[7] = Q[7];
assign P[8] = Q[8];
assign P[9] = Q[9];
assign P[10] = Q[10];
assign P[11] = Q[11];
assign P[12] = Q[12];
assign P[13] = Q[13];
assign P[14] = Q[14];
assign P[15] = Q[15];
assign P[16] = Q[16];
assign P[17] = Q[17];
assign P[18] = Q[18];
assign P[19] = Q[19];
assign P[20] = Q[20];
assign P[21] = Q[21];
assign P[22] = Q[22];
assign P[23] = Q[23];
assign P[24] = Q[24];
assign P[25] = Q[25];
assign P[26] = Q[26];
assign P[27] = Q[27];
assign P[28] = Q[28];
assign P[29] = Q[29];
assign P[30] = Q[30];
assign P[31] = Q[31];
assign P[32] = Q[32];
assign P[33] = Q[33];
assign P[34] = Q[34];
assign P[35] = Q[35];
assign P[36] = Q[36];
assign P[37] = Q[37];
assign P[38] = Q[38];
assign P[39] = Q[39];
assign P[40] = Q[40];
assign P[41] = Q[41];
assign P[42] = Q[42];
assign P[43] = Q[43];
assign P[44] = Q[44];
assign P[45] = Q[45];
assign P[46] = Q[46];
assign P[47] = Q[47];
assign P[48] = Q[48];
assign P[49] = Q[49];
assign P[50] = Q[50];
assign P[51] = Q[51];
assign P[52] = Q[52];
assign P[53] = Q[53];
assign P[54] = Q[54];
assign P[55] = Q[55];
assign P[56] = Q[56];
assign P[57] = Q[57];
assign P[58] = Q[58];
assign P[59] = Q[59];
assign P[60] = Q[60];
assign P[61] = Q[61];
assign P[62] = Q[62];
assign P[63] = Q[63];
MULTIPLIER_33_32 U1 (.MULTIPLICAND(A) , .MULTIPLIER(B) , .RST(RST), .CLK(CLK) , .PHI(1'b0) , .RESULT(Q) );
endmodule
`endif
|
module bsg_black_parrot (
bsg_tag_clk_i,
bsg_tag_clk_o,
bsg_tag_data_i,
bsg_tag_data_o,
bsg_tag_en_i,
ci2_0_o,
ci2_1_o,
ci2_2_o,
ci2_3_o,
ci2_4_o,
ci2_5_o,
ci2_6_o,
ci2_7_o,
ci2_8_o,
ci2_clk_o,
ci2_tkn_i,
ci2_v_o,
ci_0_i,
ci_1_i,
ci_2_i,
ci_3_i,
ci_4_i,
ci_5_i,
ci_6_i,
ci_7_i,
ci_8_i,
ci_clk_i,
ci_tkn_o,
ci_v_i,
clk_A_i,
clk_B_i,
clk_C_i,
clk_async_reset_i,
clk_o,
co2_0_o,
co2_1_o,
co2_2_o,
co2_3_o,
co2_4_o,
co2_5_o,
co2_6_o,
co2_7_o,
co2_8_o,
co2_clk_o,
co2_tkn_i,
co2_v_o,
co_0_i,
co_1_i,
co_2_i,
co_3_i,
co_4_i,
co_5_i,
co_6_i,
co_7_i,
co_8_i,
co_clk_i,
co_tkn_o,
co_v_i,
core_async_reset_i,
ddr_addr_0_o,
ddr_addr_10_o,
ddr_addr_11_o,
ddr_addr_12_o,
ddr_addr_13_o,
ddr_addr_14_o,
ddr_addr_15_o,
ddr_addr_1_o,
ddr_addr_2_o,
ddr_addr_3_o,
ddr_addr_4_o,
ddr_addr_5_o,
ddr_addr_6_o,
ddr_addr_7_o,
ddr_addr_8_o,
ddr_addr_9_o,
ddr_ba_0_o,
ddr_ba_1_o,
ddr_ba_2_o,
ddr_cas_n_o,
ddr_ck_n_o,
ddr_ck_p_o,
ddr_cke_o,
ddr_cs_n_o,
ddr_dm_0_o,
ddr_dm_1_o,
ddr_dm_2_o,
ddr_dm_3_o,
ddr_dq_0_o,
ddr_dq_10_o,
ddr_dq_11_o,
ddr_dq_12_o,
ddr_dq_13_o,
ddr_dq_14_o,
ddr_dq_15_o,
ddr_dq_16_o,
ddr_dq_17_o,
ddr_dq_18_o,
ddr_dq_19_o,
ddr_dq_1_o,
ddr_dq_20_o,
ddr_dq_21_o,
ddr_dq_22_o,
ddr_dq_23_o,
ddr_dq_24_o,
ddr_dq_25_o,
ddr_dq_26_o,
ddr_dq_27_o,
ddr_dq_28_o,
ddr_dq_29_o,
ddr_dq_2_o,
ddr_dq_30_o,
ddr_dq_31_o,
ddr_dq_3_o,
ddr_dq_4_o,
ddr_dq_5_o,
ddr_dq_6_o,
ddr_dq_7_o,
ddr_dq_8_o,
ddr_dq_9_o,
ddr_dqs_n_0_o,
ddr_dqs_n_1_o,
ddr_dqs_n_2_o,
ddr_dqs_n_3_o,
ddr_dqs_p_0_o,
ddr_dqs_p_1_o,
ddr_dqs_p_2_o,
ddr_dqs_p_3_o,
ddr_dq_0_i,
ddr_dq_10_i,
ddr_dq_11_i,
ddr_dq_12_i,
ddr_dq_13_i,
ddr_dq_14_i,
ddr_dq_15_i,
ddr_dq_16_i,
ddr_dq_17_i,
ddr_dq_18_i,
ddr_dq_19_i,
ddr_dq_1_i,
ddr_dq_20_i,
ddr_dq_21_i,
ddr_dq_22_i,
ddr_dq_23_i,
ddr_dq_24_i,
ddr_dq_25_i,
ddr_dq_26_i,
ddr_dq_27_i,
ddr_dq_28_i,
ddr_dq_29_i,
ddr_dq_2_i,
ddr_dq_30_i,
ddr_dq_31_i,
ddr_dq_3_i,
ddr_dq_4_i,
ddr_dq_5_i,
ddr_dq_6_i,
ddr_dq_7_i,
ddr_dq_8_i,
ddr_dq_9_i,
ddr_dqs_n_0_i,
ddr_dqs_n_1_i,
ddr_dqs_n_2_i,
ddr_dqs_n_3_i,
ddr_dqs_p_0_i,
ddr_dqs_p_1_i,
ddr_dqs_p_2_i,
ddr_dqs_p_3_i,
ddr_dq_0_sel,
ddr_dq_10_sel,
ddr_dq_11_sel,
ddr_dq_12_sel,
ddr_dq_13_sel,
ddr_dq_14_sel,
ddr_dq_15_sel,
ddr_dq_16_sel,
ddr_dq_17_sel,
ddr_dq_18_sel,
ddr_dq_19_sel,
ddr_dq_1_sel,
ddr_dq_20_sel,
ddr_dq_21_sel,
ddr_dq_22_sel,
ddr_dq_23_sel,
ddr_dq_24_sel,
ddr_dq_25_sel,
ddr_dq_26_sel,
ddr_dq_27_sel,
ddr_dq_28_sel,
ddr_dq_29_sel,
ddr_dq_2_sel,
ddr_dq_30_sel,
ddr_dq_31_sel,
ddr_dq_3_sel,
ddr_dq_4_sel,
ddr_dq_5_sel,
ddr_dq_6_sel,
ddr_dq_7_sel,
ddr_dq_8_sel,
ddr_dq_9_sel,
ddr_dqs_n_0_sel,
ddr_dqs_n_1_sel,
ddr_dqs_n_2_sel,
ddr_dqs_n_3_sel,
ddr_dqs_p_0_sel,
ddr_dqs_p_1_sel,
ddr_dqs_p_2_sel,
ddr_dqs_p_3_sel,
ddr_odt_o,
ddr_ras_n_o,
ddr_reset_n_o,
ddr_we_n_o,
misc_o,
sel_0_i,
sel_1_i,
sel_2_i
) ;
input bsg_tag_clk_i ;
output bsg_tag_clk_o ;
input bsg_tag_data_i ;
output bsg_tag_data_o ;
input bsg_tag_en_i ;
output ci2_0_o ;
output ci2_1_o ;
output ci2_2_o ;
output ci2_3_o ;
output ci2_4_o ;
output ci2_5_o ;
output ci2_6_o ;
output ci2_7_o ;
output ci2_8_o ;
output ci2_clk_o ;
input ci2_tkn_i ;
output ci2_v_o ;
input ci_0_i ;
input ci_1_i ;
input ci_2_i ;
input ci_3_i ;
input ci_4_i ;
input ci_5_i ;
input ci_6_i ;
input ci_7_i ;
input ci_8_i ;
input ci_clk_i ;
output ci_tkn_o ;
input ci_v_i ;
input clk_A_i ;
input clk_B_i ;
input clk_C_i ;
input clk_async_reset_i ;
output clk_o ;
output co2_0_o ;
output co2_1_o ;
output co2_2_o ;
output co2_3_o ;
output co2_4_o ;
output co2_5_o ;
output co2_6_o ;
output co2_7_o ;
output co2_8_o ;
output co2_clk_o ;
input co2_tkn_i ;
output co2_v_o ;
input co_0_i ;
input co_1_i ;
input co_2_i ;
input co_3_i ;
input co_4_i ;
input co_5_i ;
input co_6_i ;
input co_7_i ;
input co_8_i ;
input co_clk_i ;
output co_tkn_o ;
input co_v_i ;
input core_async_reset_i ;
output ddr_addr_0_o ;
output ddr_addr_10_o ;
output ddr_addr_11_o ;
output ddr_addr_12_o ;
output ddr_addr_13_o ;
output ddr_addr_14_o ;
output ddr_addr_15_o ;
output ddr_addr_1_o ;
output ddr_addr_2_o ;
output ddr_addr_3_o ;
output ddr_addr_4_o ;
output ddr_addr_5_o ;
output ddr_addr_6_o ;
output ddr_addr_7_o ;
output ddr_addr_8_o ;
output ddr_addr_9_o ;
output ddr_ba_0_o ;
output ddr_ba_1_o ;
output ddr_ba_2_o ;
output ddr_cas_n_o ;
output ddr_ck_n_o ;
output ddr_ck_p_o ;
output ddr_cke_o ;
output ddr_cs_n_o ;
output ddr_dm_0_o ;
output ddr_dm_1_o ;
output ddr_dm_2_o ;
output ddr_dm_3_o ;
output ddr_dq_0_o ;
output ddr_dq_10_o ;
output ddr_dq_11_o ;
output ddr_dq_12_o ;
output ddr_dq_13_o ;
output ddr_dq_14_o ;
output ddr_dq_15_o ;
output ddr_dq_16_o ;
output ddr_dq_17_o ;
output ddr_dq_18_o ;
output ddr_dq_19_o ;
output ddr_dq_1_o ;
output ddr_dq_20_o ;
output ddr_dq_21_o ;
output ddr_dq_22_o ;
output ddr_dq_23_o ;
output ddr_dq_24_o ;
output ddr_dq_25_o ;
output ddr_dq_26_o ;
output ddr_dq_27_o ;
output ddr_dq_28_o ;
output ddr_dq_29_o ;
output ddr_dq_2_o ;
output ddr_dq_30_o ;
output ddr_dq_31_o ;
output ddr_dq_3_o ;
output ddr_dq_4_o ;
output ddr_dq_5_o ;
output ddr_dq_6_o ;
output ddr_dq_7_o ;
output ddr_dq_8_o ;
output ddr_dq_9_o ;
output ddr_dqs_n_0_o ;
output ddr_dqs_n_1_o ;
output ddr_dqs_n_2_o ;
output ddr_dqs_n_3_o ;
output ddr_dqs_p_0_o ;
output ddr_dqs_p_1_o ;
output ddr_dqs_p_2_o ;
output ddr_dqs_p_3_o ;
input ddr_dq_0_i ;
input ddr_dq_10_i ;
input ddr_dq_11_i ;
input ddr_dq_12_i ;
input ddr_dq_13_i ;
input ddr_dq_14_i ;
input ddr_dq_15_i ;
input ddr_dq_16_i ;
input ddr_dq_17_i ;
input ddr_dq_18_i ;
input ddr_dq_19_i ;
input ddr_dq_1_i ;
input ddr_dq_20_i ;
input ddr_dq_21_i ;
input ddr_dq_22_i ;
input ddr_dq_23_i ;
input ddr_dq_24_i ;
input ddr_dq_25_i ;
input ddr_dq_26_i ;
input ddr_dq_27_i ;
input ddr_dq_28_i ;
input ddr_dq_29_i ;
input ddr_dq_2_i ;
input ddr_dq_30_i ;
input ddr_dq_31_i ;
input ddr_dq_3_i ;
input ddr_dq_4_i ;
input ddr_dq_5_i ;
input ddr_dq_6_i ;
input ddr_dq_7_i ;
input ddr_dq_8_i ;
input ddr_dq_9_i ;
input ddr_dqs_n_0_i ;
input ddr_dqs_n_1_i ;
input ddr_dqs_n_2_i ;
input ddr_dqs_n_3_i ;
input ddr_dqs_p_0_i ;
input ddr_dqs_p_1_i ;
input ddr_dqs_p_2_i ;
input ddr_dqs_p_3_i ;
output ddr_dq_0_sel ;
output ddr_dq_10_sel ;
output ddr_dq_11_sel ;
output ddr_dq_12_sel ;
output ddr_dq_13_sel ;
output ddr_dq_14_sel ;
output ddr_dq_15_sel ;
output ddr_dq_16_sel ;
output ddr_dq_17_sel ;
output ddr_dq_18_sel ;
output ddr_dq_19_sel ;
output ddr_dq_1_sel ;
output ddr_dq_20_sel ;
output ddr_dq_21_sel ;
output ddr_dq_22_sel ;
output ddr_dq_23_sel ;
output ddr_dq_24_sel ;
output ddr_dq_25_sel ;
output ddr_dq_26_sel ;
output ddr_dq_27_sel ;
output ddr_dq_28_sel ;
output ddr_dq_29_sel ;
output ddr_dq_2_sel ;
output ddr_dq_30_sel ;
output ddr_dq_31_sel ;
output ddr_dq_3_sel ;
output ddr_dq_4_sel ;
output ddr_dq_5_sel ;
output ddr_dq_6_sel ;
output ddr_dq_7_sel ;
output ddr_dq_8_sel ;
output ddr_dq_9_sel ;
output ddr_dqs_n_0_sel ;
output ddr_dqs_n_1_sel ;
output ddr_dqs_n_2_sel ;
output ddr_dqs_n_3_sel ;
output ddr_dqs_p_0_sel ;
output ddr_dqs_p_1_sel ;
output ddr_dqs_p_2_sel ;
output ddr_dqs_p_3_sel ;
output ddr_odt_o ;
output ddr_ras_n_o ;
output ddr_reset_n_o ;
output ddr_we_n_o ;
output misc_o ;
input sel_0_i ;
input sel_1_i ;
input sel_2_i ;
endmodule
module soc_bsg_black_parrot (
p_bsg_tag_clk_i,
p_bsg_tag_clk_o,
p_bsg_tag_data_i,
p_bsg_tag_data_o,
p_bsg_tag_en_i,
p_ci2_0_o,
p_ci2_1_o,
p_ci2_2_o,
p_ci2_3_o,
p_ci2_4_o,
p_ci2_5_o,
p_ci2_6_o,
p_ci2_7_o,
p_ci2_8_o,
p_ci2_clk_o,
p_ci2_tkn_i,
p_ci2_v_o,
p_ci_0_i,
p_ci_1_i,
p_ci_2_i,
p_ci_3_i,
p_ci_4_i,
p_ci_5_i,
p_ci_6_i,
p_ci_7_i,
p_ci_8_i,
p_ci_clk_i,
p_ci_tkn_o,
p_ci_v_i,
p_clk_A_i,
p_clk_B_i,
p_clk_C_i,
p_clk_async_reset_i,
p_clk_o,
p_co2_0_o,
p_co2_1_o,
p_co2_2_o,
p_co2_3_o,
p_co2_4_o,
p_co2_5_o,
p_co2_6_o,
p_co2_7_o,
p_co2_8_o,
p_co2_clk_o,
p_co2_tkn_i,
p_co2_v_o,
p_co_0_i,
p_co_1_i,
p_co_2_i,
p_co_3_i,
p_co_4_i,
p_co_5_i,
p_co_6_i,
p_co_7_i,
p_co_8_i,
p_co_clk_i,
p_co_tkn_o,
p_co_v_i,
p_core_async_reset_i,
p_ddr_addr_0_o,
p_ddr_addr_10_o,
p_ddr_addr_11_o,
p_ddr_addr_12_o,
p_ddr_addr_13_o,
p_ddr_addr_14_o,
p_ddr_addr_15_o,
p_ddr_addr_1_o,
p_ddr_addr_2_o,
p_ddr_addr_3_o,
p_ddr_addr_4_o,
p_ddr_addr_5_o,
p_ddr_addr_6_o,
p_ddr_addr_7_o,
p_ddr_addr_8_o,
p_ddr_addr_9_o,
p_ddr_ba_0_o,
p_ddr_ba_1_o,
p_ddr_ba_2_o,
p_ddr_cas_n_o,
p_ddr_ck_n_o,
p_ddr_ck_p_o,
p_ddr_cke_o,
p_ddr_cs_n_o,
p_ddr_dm_0_o,
p_ddr_dm_1_o,
p_ddr_dm_2_o,
p_ddr_dm_3_o,
p_ddr_dq_0_io,
p_ddr_dq_10_io,
p_ddr_dq_11_io,
p_ddr_dq_12_io,
p_ddr_dq_13_io,
p_ddr_dq_14_io,
p_ddr_dq_15_io,
p_ddr_dq_16_io,
p_ddr_dq_17_io,
p_ddr_dq_18_io,
p_ddr_dq_19_io,
p_ddr_dq_1_io,
p_ddr_dq_20_io,
p_ddr_dq_21_io,
p_ddr_dq_22_io,
p_ddr_dq_23_io,
p_ddr_dq_24_io,
p_ddr_dq_25_io,
p_ddr_dq_26_io,
p_ddr_dq_27_io,
p_ddr_dq_28_io,
p_ddr_dq_29_io,
p_ddr_dq_2_io,
p_ddr_dq_30_io,
p_ddr_dq_31_io,
p_ddr_dq_3_io,
p_ddr_dq_4_io,
p_ddr_dq_5_io,
p_ddr_dq_6_io,
p_ddr_dq_7_io,
p_ddr_dq_8_io,
p_ddr_dq_9_io,
p_ddr_dqs_n_0_io,
p_ddr_dqs_n_1_io,
p_ddr_dqs_n_2_io,
p_ddr_dqs_n_3_io,
p_ddr_dqs_p_0_io,
p_ddr_dqs_p_1_io,
p_ddr_dqs_p_2_io,
p_ddr_dqs_p_3_io,
p_ddr_odt_o,
p_ddr_ras_n_o,
p_ddr_reset_n_o,
p_ddr_we_n_o,
p_misc_o,
p_sel_0_i,
p_sel_1_i,
p_sel_2_i
) ;
input p_bsg_tag_clk_i ;
output p_bsg_tag_clk_o ;
input p_bsg_tag_data_i ;
output p_bsg_tag_data_o ;
input p_bsg_tag_en_i ;
output p_ci2_0_o ;
output p_ci2_1_o ;
output p_ci2_2_o ;
output p_ci2_3_o ;
output p_ci2_4_o ;
output p_ci2_5_o ;
output p_ci2_6_o ;
output p_ci2_7_o ;
output p_ci2_8_o ;
output p_ci2_clk_o ;
input p_ci2_tkn_i ;
output p_ci2_v_o ;
input p_ci_0_i ;
input p_ci_1_i ;
input p_ci_2_i ;
input p_ci_3_i ;
input p_ci_4_i ;
input p_ci_5_i ;
input p_ci_6_i ;
input p_ci_7_i ;
input p_ci_8_i ;
input p_ci_clk_i ;
output p_ci_tkn_o ;
input p_ci_v_i ;
input p_clk_A_i ;
input p_clk_B_i ;
input p_clk_C_i ;
input p_clk_async_reset_i ;
output p_clk_o ;
output p_co2_0_o ;
output p_co2_1_o ;
output p_co2_2_o ;
output p_co2_3_o ;
output p_co2_4_o ;
output p_co2_5_o ;
output p_co2_6_o ;
output p_co2_7_o ;
output p_co2_8_o ;
output p_co2_clk_o ;
input p_co2_tkn_i ;
output p_co2_v_o ;
input p_co_0_i ;
input p_co_1_i ;
input p_co_2_i ;
input p_co_3_i ;
input p_co_4_i ;
input p_co_5_i ;
input p_co_6_i ;
input p_co_7_i ;
input p_co_8_i ;
input p_co_clk_i ;
output p_co_tkn_o ;
input p_co_v_i ;
input p_core_async_reset_i ;
output p_ddr_addr_0_o ;
output p_ddr_addr_10_o ;
output p_ddr_addr_11_o ;
output p_ddr_addr_12_o ;
output p_ddr_addr_13_o ;
output p_ddr_addr_14_o ;
output p_ddr_addr_15_o ;
output p_ddr_addr_1_o ;
output p_ddr_addr_2_o ;
output p_ddr_addr_3_o ;
output p_ddr_addr_4_o ;
output p_ddr_addr_5_o ;
output p_ddr_addr_6_o ;
output p_ddr_addr_7_o ;
output p_ddr_addr_8_o ;
output p_ddr_addr_9_o ;
output p_ddr_ba_0_o ;
output p_ddr_ba_1_o ;
output p_ddr_ba_2_o ;
output p_ddr_cas_n_o ;
output p_ddr_ck_n_o ;
output p_ddr_ck_p_o ;
output p_ddr_cke_o ;
output p_ddr_cs_n_o ;
output p_ddr_dm_0_o ;
output p_ddr_dm_1_o ;
output p_ddr_dm_2_o ;
output p_ddr_dm_3_o ;
inout p_ddr_dq_0_io ;
inout p_ddr_dq_10_io ;
inout p_ddr_dq_11_io ;
inout p_ddr_dq_12_io ;
inout p_ddr_dq_13_io ;
inout p_ddr_dq_14_io ;
inout p_ddr_dq_15_io ;
inout p_ddr_dq_16_io ;
inout p_ddr_dq_17_io ;
inout p_ddr_dq_18_io ;
inout p_ddr_dq_19_io ;
inout p_ddr_dq_1_io ;
inout p_ddr_dq_20_io ;
inout p_ddr_dq_21_io ;
inout p_ddr_dq_22_io ;
inout p_ddr_dq_23_io ;
inout p_ddr_dq_24_io ;
inout p_ddr_dq_25_io ;
inout p_ddr_dq_26_io ;
inout p_ddr_dq_27_io ;
inout p_ddr_dq_28_io ;
inout p_ddr_dq_29_io ;
inout p_ddr_dq_2_io ;
inout p_ddr_dq_30_io ;
inout p_ddr_dq_31_io ;
inout p_ddr_dq_3_io ;
inout p_ddr_dq_4_io ;
inout p_ddr_dq_5_io ;
inout p_ddr_dq_6_io ;
inout p_ddr_dq_7_io ;
inout p_ddr_dq_8_io ;
inout p_ddr_dq_9_io ;
inout p_ddr_dqs_n_0_io ;
inout p_ddr_dqs_n_1_io ;
inout p_ddr_dqs_n_2_io ;
inout p_ddr_dqs_n_3_io ;
inout p_ddr_dqs_p_0_io ;
inout p_ddr_dqs_p_1_io ;
inout p_ddr_dqs_p_2_io ;
inout p_ddr_dqs_p_3_io ;
output p_ddr_odt_o ;
output p_ddr_ras_n_o ;
output p_ddr_reset_n_o ;
output p_ddr_we_n_o ;
output p_misc_o ;
input p_sel_0_i ;
input p_sel_1_i ;
input p_sel_2_i ;
bsg_black_parrot u_design (
.bsg_tag_clk_i(core_bsg_tag_clk_i),
.bsg_tag_clk_o(core_bsg_tag_clk_o),
.bsg_tag_data_i(core_bsg_tag_data_i),
.bsg_tag_data_o(core_bsg_tag_data_o),
.bsg_tag_en_i(core_bsg_tag_en_i),
.ci2_0_o(core_ci2_0_o),
.ci2_1_o(core_ci2_1_o),
.ci2_2_o(core_ci2_2_o),
.ci2_3_o(core_ci2_3_o),
.ci2_4_o(core_ci2_4_o),
.ci2_5_o(core_ci2_5_o),
.ci2_6_o(core_ci2_6_o),
.ci2_7_o(core_ci2_7_o),
.ci2_8_o(core_ci2_8_o),
.ci2_clk_o(core_ci2_clk_o),
.ci2_tkn_i(core_ci2_tkn_i),
.ci2_v_o(core_ci2_v_o),
.ci_0_i(core_ci_0_i),
.ci_1_i(core_ci_1_i),
.ci_2_i(core_ci_2_i),
.ci_3_i(core_ci_3_i),
.ci_4_i(core_ci_4_i),
.ci_5_i(core_ci_5_i),
.ci_6_i(core_ci_6_i),
.ci_7_i(core_ci_7_i),
.ci_8_i(core_ci_8_i),
.ci_clk_i(core_ci_clk_i),
.ci_tkn_o(core_ci_tkn_o),
.ci_v_i(core_ci_v_i),
.clk_A_i(core_clk_A_i),
.clk_B_i(core_clk_B_i),
.clk_C_i(core_clk_C_i),
.clk_async_reset_i(core_clk_async_reset_i),
.clk_o(core_clk_o),
.co2_0_o(core_co2_0_o),
.co2_1_o(core_co2_1_o),
.co2_2_o(core_co2_2_o),
.co2_3_o(core_co2_3_o),
.co2_4_o(core_co2_4_o),
.co2_5_o(core_co2_5_o),
.co2_6_o(core_co2_6_o),
.co2_7_o(core_co2_7_o),
.co2_8_o(core_co2_8_o),
.co2_clk_o(core_co2_clk_o),
.co2_tkn_i(core_co2_tkn_i),
.co2_v_o(core_co2_v_o),
.co_0_i(core_co_0_i),
.co_1_i(core_co_1_i),
.co_2_i(core_co_2_i),
.co_3_i(core_co_3_i),
.co_4_i(core_co_4_i),
.co_5_i(core_co_5_i),
.co_6_i(core_co_6_i),
.co_7_i(core_co_7_i),
.co_8_i(core_co_8_i),
.co_clk_i(core_co_clk_i),
.co_tkn_o(core_co_tkn_o),
.co_v_i(core_co_v_i),
.core_async_reset_i(core_core_async_reset_i),
.ddr_addr_0_o(core_ddr_addr_0_o),
.ddr_addr_10_o(core_ddr_addr_10_o),
.ddr_addr_11_o(core_ddr_addr_11_o),
.ddr_addr_12_o(core_ddr_addr_12_o),
.ddr_addr_13_o(core_ddr_addr_13_o),
.ddr_addr_14_o(core_ddr_addr_14_o),
.ddr_addr_15_o(core_ddr_addr_15_o),
.ddr_addr_1_o(core_ddr_addr_1_o),
.ddr_addr_2_o(core_ddr_addr_2_o),
.ddr_addr_3_o(core_ddr_addr_3_o),
.ddr_addr_4_o(core_ddr_addr_4_o),
.ddr_addr_5_o(core_ddr_addr_5_o),
.ddr_addr_6_o(core_ddr_addr_6_o),
.ddr_addr_7_o(core_ddr_addr_7_o),
.ddr_addr_8_o(core_ddr_addr_8_o),
.ddr_addr_9_o(core_ddr_addr_9_o),
.ddr_ba_0_o(core_ddr_ba_0_o),
.ddr_ba_1_o(core_ddr_ba_1_o),
.ddr_ba_2_o(core_ddr_ba_2_o),
.ddr_cas_n_o(core_ddr_cas_n_o),
.ddr_ck_n_o(core_ddr_ck_n_o),
.ddr_ck_p_o(core_ddr_ck_p_o),
.ddr_cke_o(core_ddr_cke_o),
.ddr_cs_n_o(core_ddr_cs_n_o),
.ddr_dm_0_o(core_ddr_dm_0_o),
.ddr_dm_1_o(core_ddr_dm_1_o),
.ddr_dm_2_o(core_ddr_dm_2_o),
.ddr_dm_3_o(core_ddr_dm_3_o),
.ddr_dq_0_o(core_ddr_dq_0_o),
.ddr_dq_10_o(core_ddr_dq_10_o),
.ddr_dq_11_o(core_ddr_dq_11_o),
.ddr_dq_12_o(core_ddr_dq_12_o),
.ddr_dq_13_o(core_ddr_dq_13_o),
.ddr_dq_14_o(core_ddr_dq_14_o),
.ddr_dq_15_o(core_ddr_dq_15_o),
.ddr_dq_16_o(core_ddr_dq_16_o),
.ddr_dq_17_o(core_ddr_dq_17_o),
.ddr_dq_18_o(core_ddr_dq_18_o),
.ddr_dq_19_o(core_ddr_dq_19_o),
.ddr_dq_1_o(core_ddr_dq_1_o),
.ddr_dq_20_o(core_ddr_dq_20_o),
.ddr_dq_21_o(core_ddr_dq_21_o),
.ddr_dq_22_o(core_ddr_dq_22_o),
.ddr_dq_23_o(core_ddr_dq_23_o),
.ddr_dq_24_o(core_ddr_dq_24_o),
.ddr_dq_25_o(core_ddr_dq_25_o),
.ddr_dq_26_o(core_ddr_dq_26_o),
.ddr_dq_27_o(core_ddr_dq_27_o),
.ddr_dq_28_o(core_ddr_dq_28_o),
.ddr_dq_29_o(core_ddr_dq_29_o),
.ddr_dq_2_o(core_ddr_dq_2_o),
.ddr_dq_30_o(core_ddr_dq_30_o),
.ddr_dq_31_o(core_ddr_dq_31_o),
.ddr_dq_3_o(core_ddr_dq_3_o),
.ddr_dq_4_o(core_ddr_dq_4_o),
.ddr_dq_5_o(core_ddr_dq_5_o),
.ddr_dq_6_o(core_ddr_dq_6_o),
.ddr_dq_7_o(core_ddr_dq_7_o),
.ddr_dq_8_o(core_ddr_dq_8_o),
.ddr_dq_9_o(core_ddr_dq_9_o),
.ddr_dqs_n_0_o(core_ddr_dqs_n_0_o),
.ddr_dqs_n_1_o(core_ddr_dqs_n_1_o),
.ddr_dqs_n_2_o(core_ddr_dqs_n_2_o),
.ddr_dqs_n_3_o(core_ddr_dqs_n_3_o),
.ddr_dqs_p_0_o(core_ddr_dqs_p_0_o),
.ddr_dqs_p_1_o(core_ddr_dqs_p_1_o),
.ddr_dqs_p_2_o(core_ddr_dqs_p_2_o),
.ddr_dqs_p_3_o(core_ddr_dqs_p_3_o),
.ddr_dq_0_i(core_ddr_dq_0_i),
.ddr_dq_10_i(core_ddr_dq_10_i),
.ddr_dq_11_i(core_ddr_dq_11_i),
.ddr_dq_12_i(core_ddr_dq_12_i),
.ddr_dq_13_i(core_ddr_dq_13_i),
.ddr_dq_14_i(core_ddr_dq_14_i),
.ddr_dq_15_i(core_ddr_dq_15_i),
.ddr_dq_16_i(core_ddr_dq_16_i),
.ddr_dq_17_i(core_ddr_dq_17_i),
.ddr_dq_18_i(core_ddr_dq_18_i),
.ddr_dq_19_i(core_ddr_dq_19_i),
.ddr_dq_1_i(core_ddr_dq_1_i),
.ddr_dq_20_i(core_ddr_dq_20_i),
.ddr_dq_21_i(core_ddr_dq_21_i),
.ddr_dq_22_i(core_ddr_dq_22_i),
.ddr_dq_23_i(core_ddr_dq_23_i),
.ddr_dq_24_i(core_ddr_dq_24_i),
.ddr_dq_25_i(core_ddr_dq_25_i),
.ddr_dq_26_i(core_ddr_dq_26_i),
.ddr_dq_27_i(core_ddr_dq_27_i),
.ddr_dq_28_i(core_ddr_dq_28_i),
.ddr_dq_29_i(core_ddr_dq_29_i),
.ddr_dq_2_i(core_ddr_dq_2_i),
.ddr_dq_30_i(core_ddr_dq_30_i),
.ddr_dq_31_i(core_ddr_dq_31_i),
.ddr_dq_3_i(core_ddr_dq_3_i),
.ddr_dq_4_i(core_ddr_dq_4_i),
.ddr_dq_5_i(core_ddr_dq_5_i),
.ddr_dq_6_i(core_ddr_dq_6_i),
.ddr_dq_7_i(core_ddr_dq_7_i),
.ddr_dq_8_i(core_ddr_dq_8_i),
.ddr_dq_9_i(core_ddr_dq_9_i),
.ddr_dqs_n_0_i(core_ddr_dqs_n_0_i),
.ddr_dqs_n_1_i(core_ddr_dqs_n_1_i),
.ddr_dqs_n_2_i(core_ddr_dqs_n_2_i),
.ddr_dqs_n_3_i(core_ddr_dqs_n_3_i),
.ddr_dqs_p_0_i(core_ddr_dqs_p_0_i),
.ddr_dqs_p_1_i(core_ddr_dqs_p_1_i),
.ddr_dqs_p_2_i(core_ddr_dqs_p_2_i),
.ddr_dqs_p_3_i(core_ddr_dqs_p_3_i),
.ddr_dq_0_sel(core_ddr_dq_0_sel),
.ddr_dq_10_sel(core_ddr_dq_10_sel),
.ddr_dq_11_sel(core_ddr_dq_11_sel),
.ddr_dq_12_sel(core_ddr_dq_12_sel),
.ddr_dq_13_sel(core_ddr_dq_13_sel),
.ddr_dq_14_sel(core_ddr_dq_14_sel),
.ddr_dq_15_sel(core_ddr_dq_15_sel),
.ddr_dq_16_sel(core_ddr_dq_16_sel),
.ddr_dq_17_sel(core_ddr_dq_17_sel),
.ddr_dq_18_sel(core_ddr_dq_18_sel),
.ddr_dq_19_sel(core_ddr_dq_19_sel),
.ddr_dq_1_sel(core_ddr_dq_1_sel),
.ddr_dq_20_sel(core_ddr_dq_20_sel),
.ddr_dq_21_sel(core_ddr_dq_21_sel),
.ddr_dq_22_sel(core_ddr_dq_22_sel),
.ddr_dq_23_sel(core_ddr_dq_23_sel),
.ddr_dq_24_sel(core_ddr_dq_24_sel),
.ddr_dq_25_sel(core_ddr_dq_25_sel),
.ddr_dq_26_sel(core_ddr_dq_26_sel),
.ddr_dq_27_sel(core_ddr_dq_27_sel),
.ddr_dq_28_sel(core_ddr_dq_28_sel),
.ddr_dq_29_sel(core_ddr_dq_29_sel),
.ddr_dq_2_sel(core_ddr_dq_2_sel),
.ddr_dq_30_sel(core_ddr_dq_30_sel),
.ddr_dq_31_sel(core_ddr_dq_31_sel),
.ddr_dq_3_sel(core_ddr_dq_3_sel),
.ddr_dq_4_sel(core_ddr_dq_4_sel),
.ddr_dq_5_sel(core_ddr_dq_5_sel),
.ddr_dq_6_sel(core_ddr_dq_6_sel),
.ddr_dq_7_sel(core_ddr_dq_7_sel),
.ddr_dq_8_sel(core_ddr_dq_8_sel),
.ddr_dq_9_sel(core_ddr_dq_9_sel),
.ddr_dqs_n_0_sel(core_ddr_dqs_n_0_sel),
.ddr_dqs_n_1_sel(core_ddr_dqs_n_1_sel),
.ddr_dqs_n_2_sel(core_ddr_dqs_n_2_sel),
.ddr_dqs_n_3_sel(core_ddr_dqs_n_3_sel),
.ddr_dqs_p_0_sel(core_ddr_dqs_p_0_sel),
.ddr_dqs_p_1_sel(core_ddr_dqs_p_1_sel),
.ddr_dqs_p_2_sel(core_ddr_dqs_p_2_sel),
.ddr_dqs_p_3_sel(core_ddr_dqs_p_3_sel),
.ddr_odt_o(core_ddr_odt_o),
.ddr_ras_n_o(core_ddr_ras_n_o),
.ddr_reset_n_o(core_ddr_reset_n_o),
.ddr_we_n_o(core_ddr_we_n_o),
.misc_o(core_misc_o),
.sel_0_i(core_sel_0_i),
.sel_1_i(core_sel_1_i),
.sel_2_i(core_sel_2_i)
) ;
PADCELL_SIG_V u_ci2_0_o (.PAD(p_ci2_0_o), .A(core_ci2_0_o)) ;
PADCELL_SIG_V u_ci2_1_o (.PAD(p_ci2_1_o), .A(core_ci2_1_o)) ;
PADCELL_SIG_V u_ci2_2_o (.PAD(p_ci2_2_o), .A(core_ci2_2_o)) ;
PADCELL_SIG_V u_ci2_3_o (.PAD(p_ci2_3_o), .A(core_ci2_3_o)) ;
PADCELL_SIG_V u_ci2_4_o (.PAD(p_ci2_4_o), .A(core_ci2_4_o)) ;
PADCELL_SIG_V u_ci2_5_o (.PAD(p_ci2_5_o), .A(core_ci2_5_o)) ;
PADCELL_SIG_V u_ci2_6_o (.PAD(p_ci2_6_o), .A(core_ci2_6_o)) ;
PADCELL_SIG_V u_ci2_7_o (.PAD(p_ci2_7_o), .A(core_ci2_7_o)) ;
PADCELL_SIG_V u_ci2_8_o (.PAD(p_ci2_8_o), .A(core_ci2_8_o)) ;
PADCELL_SIG_V u_ci2_clk_o (.PAD(p_ci2_clk_o), .A(core_ci2_clk_o)) ;
PADCELL_SIG_V u_ci2_tkn_i (.PAD(p_ci2_tkn_i), .Y(core_ci2_tkn_i)) ;
PADCELL_SIG_V u_ci2_v_o (.PAD(p_ci2_v_o), .A(core_ci2_v_o)) ;
PADCELL_SIG_V u_clk_A_i (.PAD(p_clk_A_i), .Y(core_clk_A_i)) ;
PADCELL_SIG_V u_clk_B_i (.PAD(p_clk_B_i), .Y(core_clk_B_i)) ;
PADCELL_SIG_V u_clk_C_i (.PAD(p_clk_C_i), .Y(core_clk_C_i)) ;
PADCELL_SIG_V u_clk_async_reset_i (.PAD(p_clk_async_reset_i), .Y(core_clk_async_reset_i)) ;
PADCELL_SIG_V u_clk_o (.PAD(p_clk_o), .A(core_clk_o)) ;
PADCELL_SIG_V u_co_0_i (.PAD(p_co_0_i), .Y(core_co_0_i)) ;
PADCELL_SIG_V u_co_1_i (.PAD(p_co_1_i), .Y(core_co_1_i)) ;
PADCELL_SIG_V u_co_2_i (.PAD(p_co_2_i), .Y(core_co_2_i)) ;
PADCELL_SIG_V u_co_3_i (.PAD(p_co_3_i), .Y(core_co_3_i)) ;
PADCELL_SIG_V u_co_4_i (.PAD(p_co_4_i), .Y(core_co_4_i)) ;
PADCELL_SIG_V u_co_5_i (.PAD(p_co_5_i), .Y(core_co_5_i)) ;
PADCELL_SIG_V u_co_6_i (.PAD(p_co_6_i), .Y(core_co_6_i)) ;
PADCELL_SIG_V u_co_7_i (.PAD(p_co_7_i), .Y(core_co_7_i)) ;
PADCELL_SIG_V u_co_8_i (.PAD(p_co_8_i), .Y(core_co_8_i)) ;
PADCELL_SIG_V u_co_clk_i (.PAD(p_co_clk_i), .Y(core_co_clk_i)) ;
PADCELL_SIG_V u_co_tkn_o (.PAD(p_co_tkn_o), .A(core_co_tkn_o)) ;
PADCELL_SIG_V u_co_v_i (.PAD(p_co_v_i), .Y(core_co_v_i)) ;
PADCELL_SIG_V u_core_async_reset_i (.PAD(p_core_async_reset_i), .Y(core_core_async_reset_i)) ;
PADCELL_SIG_V u_ddr_addr_0_o (.PAD(p_ddr_addr_0_o), .A(core_ddr_addr_0_o)) ;
PADCELL_SIG_V u_ddr_addr_10_o (.PAD(p_ddr_addr_10_o), .A(core_ddr_addr_10_o)) ;
PADCELL_SIG_V u_ddr_addr_11_o (.PAD(p_ddr_addr_11_o), .A(core_ddr_addr_11_o)) ;
PADCELL_SIG_V u_ddr_addr_12_o (.PAD(p_ddr_addr_12_o), .A(core_ddr_addr_12_o)) ;
PADCELL_SIG_V u_ddr_addr_13_o (.PAD(p_ddr_addr_13_o), .A(core_ddr_addr_13_o)) ;
PADCELL_SIG_V u_ddr_addr_14_o (.PAD(p_ddr_addr_14_o), .A(core_ddr_addr_14_o)) ;
PADCELL_SIG_V u_ddr_addr_15_o (.PAD(p_ddr_addr_15_o), .A(core_ddr_addr_15_o)) ;
PADCELL_SIG_V u_ddr_addr_1_o (.PAD(p_ddr_addr_1_o), .A(core_ddr_addr_1_o)) ;
PADCELL_SIG_V u_ddr_addr_2_o (.PAD(p_ddr_addr_2_o), .A(core_ddr_addr_2_o)) ;
PADCELL_SIG_V u_ddr_addr_3_o (.PAD(p_ddr_addr_3_o), .A(core_ddr_addr_3_o)) ;
PADCELL_SIG_V u_ddr_addr_4_o (.PAD(p_ddr_addr_4_o), .A(core_ddr_addr_4_o)) ;
PADCELL_SIG_V u_ddr_addr_5_o (.PAD(p_ddr_addr_5_o), .A(core_ddr_addr_5_o)) ;
PADCELL_SIG_V u_ddr_addr_6_o (.PAD(p_ddr_addr_6_o), .A(core_ddr_addr_6_o)) ;
PADCELL_SIG_V u_ddr_addr_7_o (.PAD(p_ddr_addr_7_o), .A(core_ddr_addr_7_o)) ;
PADCELL_SIG_V u_ddr_addr_8_o (.PAD(p_ddr_addr_8_o), .A(core_ddr_addr_8_o)) ;
PADCELL_SIG_V u_ddr_addr_9_o (.PAD(p_ddr_addr_9_o), .A(core_ddr_addr_9_o)) ;
PADCELL_SIG_V u_ddr_ba_0_o (.PAD(p_ddr_ba_0_o), .A(core_ddr_ba_0_o)) ;
PADCELL_SIG_V u_ddr_ba_1_o (.PAD(p_ddr_ba_1_o), .A(core_ddr_ba_1_o)) ;
PADCELL_SIG_V u_ddr_ba_2_o (.PAD(p_ddr_ba_2_o), .A(core_ddr_ba_2_o)) ;
PADCELL_SIG_V u_ddr_cas_n_o (.PAD(p_ddr_cas_n_o), .A(core_ddr_cas_n_o)) ;
PADCELL_SIG_V u_ddr_ck_n_o (.PAD(p_ddr_ck_n_o), .A(core_ddr_ck_n_o)) ;
PADCELL_SIG_V u_ddr_ck_p_o (.PAD(p_ddr_ck_p_o), .A(core_ddr_ck_p_o)) ;
PADCELL_SIG_V u_ddr_cke_o (.PAD(p_ddr_cke_o), .A(core_ddr_cke_o)) ;
PADCELL_SIG_V u_ddr_cs_n_o (.PAD(p_ddr_cs_n_o), .A(core_ddr_cs_n_o)) ;
PADCELL_SIG_V u_ddr_dm_1_o (.PAD(p_ddr_dm_1_o), .A(core_ddr_dm_1_o)) ;
PADCELL_SIG_V u_ddr_dm_2_o (.PAD(p_ddr_dm_2_o), .A(core_ddr_dm_2_o)) ;
PADCELL_SIG_V u_ddr_dqs_n_1_io (.PAD(p_ddr_dqs_n_1_io), .A(core_ddr_dqs_n_1_o), .Y(core_ddr_dqs_n_1_i), .OE(core_ddr_dqs_n_1_sel), .PU(core_ddr_dqs_n_1_sel)) ;
PADCELL_SIG_V u_ddr_dqs_n_2_io (.PAD(p_ddr_dqs_n_2_io), .A(core_ddr_dqs_n_2_o), .Y(core_ddr_dqs_n_2_i), .OE(core_ddr_dqs_n_2_sel), .PU(core_ddr_dqs_n_2_sel)) ;
PADCELL_SIG_V u_ddr_dqs_p_1_io (.PAD(p_ddr_dqs_p_1_io), .A(core_ddr_dqs_p_1_o), .Y(core_ddr_dqs_p_1_i), .OE(core_ddr_dqs_p_1_sel), .PU(core_ddr_dqs_p_1_sel)) ;
PADCELL_SIG_V u_ddr_dqs_p_2_io (.PAD(p_ddr_dqs_p_2_io), .A(core_ddr_dqs_p_2_o), .Y(core_ddr_dqs_p_2_i), .OE(core_ddr_dqs_p_2_sel), .PU(core_ddr_dqs_p_2_sel)) ;
PADCELL_SIG_V u_ddr_odt_o (.PAD(p_ddr_odt_o), .A(core_ddr_odt_o)) ;
PADCELL_SIG_V u_ddr_ras_n_o (.PAD(p_ddr_ras_n_o), .A(core_ddr_ras_n_o)) ;
PADCELL_SIG_V u_ddr_reset_n_o (.PAD(p_ddr_reset_n_o), .A(core_ddr_reset_n_o)) ;
PADCELL_SIG_V u_ddr_we_n_o (.PAD(p_ddr_we_n_o), .A(core_ddr_we_n_o)) ;
PADCELL_SIG_V u_misc_o (.PAD(p_misc_o), .A(core_misc_o)) ;
PADCELL_SIG_V u_sel_0_i (.PAD(p_sel_0_i), .Y(core_sel_0_i)) ;
PADCELL_SIG_V u_sel_1_i (.PAD(p_sel_1_i), .Y(core_sel_1_i)) ;
PADCELL_SIG_V u_sel_2_i (.PAD(p_sel_2_i), .Y(core_sel_2_i)) ;
PADCELL_SIG_H u_bsg_tag_clk_i (.PAD(p_bsg_tag_clk_i), .Y(core_bsg_tag_clk_i)) ;
PADCELL_SIG_H u_bsg_tag_clk_o (.PAD(p_bsg_tag_clk_o), .A(core_bsg_tag_clk_o)) ;
PADCELL_SIG_H u_bsg_tag_data_i (.PAD(p_bsg_tag_data_i), .Y(core_bsg_tag_data_i)) ;
PADCELL_SIG_H u_bsg_tag_data_o (.PAD(p_bsg_tag_data_o), .A(core_bsg_tag_data_o)) ;
PADCELL_SIG_H u_bsg_tag_en_i (.PAD(p_bsg_tag_en_i), .Y(core_bsg_tag_en_i)) ;
PADCELL_SIG_H u_ci_0_i (.PAD(p_ci_0_i), .Y(core_ci_0_i)) ;
PADCELL_SIG_H u_ci_1_i (.PAD(p_ci_1_i), .Y(core_ci_1_i)) ;
PADCELL_SIG_H u_ci_2_i (.PAD(p_ci_2_i), .Y(core_ci_2_i)) ;
PADCELL_SIG_H u_ci_3_i (.PAD(p_ci_3_i), .Y(core_ci_3_i)) ;
PADCELL_SIG_H u_ci_4_i (.PAD(p_ci_4_i), .Y(core_ci_4_i)) ;
PADCELL_SIG_H u_ci_5_i (.PAD(p_ci_5_i), .Y(core_ci_5_i)) ;
PADCELL_SIG_H u_ci_6_i (.PAD(p_ci_6_i), .Y(core_ci_6_i)) ;
PADCELL_SIG_H u_ci_7_i (.PAD(p_ci_7_i), .Y(core_ci_7_i)) ;
PADCELL_SIG_H u_ci_8_i (.PAD(p_ci_8_i), .Y(core_ci_8_i)) ;
PADCELL_SIG_H u_ci_clk_i (.PAD(p_ci_clk_i), .Y(core_ci_clk_i)) ;
PADCELL_SIG_H u_ci_tkn_o (.PAD(p_ci_tkn_o), .A(core_ci_tkn_o)) ;
PADCELL_SIG_H u_ci_v_i (.PAD(p_ci_v_i), .Y(core_ci_v_i)) ;
PADCELL_SIG_H u_co2_0_o (.PAD(p_co2_0_o), .A(core_co2_0_o)) ;
PADCELL_SIG_H u_co2_1_o (.PAD(p_co2_1_o), .A(core_co2_1_o)) ;
PADCELL_SIG_H u_co2_2_o (.PAD(p_co2_2_o), .A(core_co2_2_o)) ;
PADCELL_SIG_H u_co2_3_o (.PAD(p_co2_3_o), .A(core_co2_3_o)) ;
PADCELL_SIG_H u_co2_4_o (.PAD(p_co2_4_o), .A(core_co2_4_o)) ;
PADCELL_SIG_H u_co2_5_o (.PAD(p_co2_5_o), .A(core_co2_5_o)) ;
PADCELL_SIG_H u_co2_6_o (.PAD(p_co2_6_o), .A(core_co2_6_o)) ;
PADCELL_SIG_H u_co2_7_o (.PAD(p_co2_7_o), .A(core_co2_7_o)) ;
PADCELL_SIG_H u_co2_8_o (.PAD(p_co2_8_o), .A(core_co2_8_o)) ;
PADCELL_SIG_H u_co2_clk_o (.PAD(p_co2_clk_o), .A(core_co2_clk_o)) ;
PADCELL_SIG_H u_co2_tkn_i (.PAD(p_co2_tkn_i), .Y(core_co2_tkn_i)) ;
PADCELL_SIG_H u_co2_v_o (.PAD(p_co2_v_o), .A(core_co2_v_o)) ;
PADCELL_SIG_H u_ddr_dm_0_o (.PAD(p_ddr_dm_0_o), .A(core_ddr_dm_0_o)) ;
PADCELL_SIG_H u_ddr_dm_3_o (.PAD(p_ddr_dm_3_o), .A(core_ddr_dm_3_o)) ;
PADCELL_SIG_H u_ddr_dq_0_io (.PAD(p_ddr_dq_0_io), .A(core_ddr_dq_0_o), .Y(core_ddr_dq_0_i), .OE(core_ddr_dq_0_sel), .PU(core_ddr_dq_0_sel)) ;
PADCELL_SIG_H u_ddr_dq_10_io (.PAD(p_ddr_dq_10_io), .A(core_ddr_dq_10_o), .Y(core_ddr_dq_10_i), .OE(core_ddr_dq_10_sel), .PU(core_ddr_dq_10_sel)) ;
PADCELL_SIG_H u_ddr_dq_11_io (.PAD(p_ddr_dq_11_io), .A(core_ddr_dq_11_o), .Y(core_ddr_dq_11_i), .OE(core_ddr_dq_11_sel), .PU(core_ddr_dq_11_sel)) ;
PADCELL_SIG_H u_ddr_dq_12_io (.PAD(p_ddr_dq_12_io), .A(core_ddr_dq_12_o), .Y(core_ddr_dq_12_i), .OE(core_ddr_dq_12_sel), .PU(core_ddr_dq_12_sel)) ;
PADCELL_SIG_H u_ddr_dq_13_io (.PAD(p_ddr_dq_13_io), .A(core_ddr_dq_13_o), .Y(core_ddr_dq_13_i), .OE(core_ddr_dq_13_sel), .PU(core_ddr_dq_13_sel)) ;
PADCELL_SIG_H u_ddr_dq_14_io (.PAD(p_ddr_dq_14_io), .A(core_ddr_dq_14_o), .Y(core_ddr_dq_14_i), .OE(core_ddr_dq_14_sel), .PU(core_ddr_dq_14_sel)) ;
PADCELL_SIG_H u_ddr_dq_15_io (.PAD(p_ddr_dq_15_io), .A(core_ddr_dq_15_o), .Y(core_ddr_dq_15_i), .OE(core_ddr_dq_15_sel), .PU(core_ddr_dq_15_sel)) ;
PADCELL_SIG_H u_ddr_dq_16_io (.PAD(p_ddr_dq_16_io), .A(core_ddr_dq_16_o), .Y(core_ddr_dq_16_i), .OE(core_ddr_dq_16_sel), .PU(core_ddr_dq_16_sel)) ;
PADCELL_SIG_H u_ddr_dq_17_io (.PAD(p_ddr_dq_17_io), .A(core_ddr_dq_17_o), .Y(core_ddr_dq_17_i), .OE(core_ddr_dq_17_sel), .PU(core_ddr_dq_17_sel)) ;
PADCELL_SIG_H u_ddr_dq_18_io (.PAD(p_ddr_dq_18_io), .A(core_ddr_dq_18_o), .Y(core_ddr_dq_18_i), .OE(core_ddr_dq_18_sel), .PU(core_ddr_dq_18_sel)) ;
PADCELL_SIG_H u_ddr_dq_19_io (.PAD(p_ddr_dq_19_io), .A(core_ddr_dq_19_o), .Y(core_ddr_dq_19_i), .OE(core_ddr_dq_19_sel), .PU(core_ddr_dq_19_sel)) ;
PADCELL_SIG_H u_ddr_dq_1_io (.PAD(p_ddr_dq_1_io), .A(core_ddr_dq_1_o), .Y(core_ddr_dq_1_i), .OE(core_ddr_dq_1_sel), .PU(core_ddr_dq_1_sel)) ;
PADCELL_SIG_H u_ddr_dq_20_io (.PAD(p_ddr_dq_20_io), .A(core_ddr_dq_20_o), .Y(core_ddr_dq_20_i), .OE(core_ddr_dq_20_sel), .PU(core_ddr_dq_20_sel)) ;
PADCELL_SIG_H u_ddr_dq_21_io (.PAD(p_ddr_dq_21_io), .A(core_ddr_dq_21_o), .Y(core_ddr_dq_21_i), .OE(core_ddr_dq_21_sel), .PU(core_ddr_dq_21_sel)) ;
PADCELL_SIG_H u_ddr_dq_22_io (.PAD(p_ddr_dq_22_io), .A(core_ddr_dq_22_o), .Y(core_ddr_dq_22_i), .OE(core_ddr_dq_22_sel), .PU(core_ddr_dq_22_sel)) ;
PADCELL_SIG_H u_ddr_dq_23_io (.PAD(p_ddr_dq_23_io), .A(core_ddr_dq_23_o), .Y(core_ddr_dq_23_i), .OE(core_ddr_dq_23_sel), .PU(core_ddr_dq_23_sel)) ;
PADCELL_SIG_H u_ddr_dq_24_io (.PAD(p_ddr_dq_24_io), .A(core_ddr_dq_24_o), .Y(core_ddr_dq_24_i), .OE(core_ddr_dq_24_sel), .PU(core_ddr_dq_24_sel)) ;
PADCELL_SIG_H u_ddr_dq_25_io (.PAD(p_ddr_dq_25_io), .A(core_ddr_dq_25_o), .Y(core_ddr_dq_25_i), .OE(core_ddr_dq_25_sel), .PU(core_ddr_dq_25_sel)) ;
PADCELL_SIG_H u_ddr_dq_26_io (.PAD(p_ddr_dq_26_io), .A(core_ddr_dq_26_o), .Y(core_ddr_dq_26_i), .OE(core_ddr_dq_26_sel), .PU(core_ddr_dq_26_sel)) ;
PADCELL_SIG_H u_ddr_dq_27_io (.PAD(p_ddr_dq_27_io), .A(core_ddr_dq_27_o), .Y(core_ddr_dq_27_i), .OE(core_ddr_dq_27_sel), .PU(core_ddr_dq_27_sel)) ;
PADCELL_SIG_H u_ddr_dq_28_io (.PAD(p_ddr_dq_28_io), .A(core_ddr_dq_28_o), .Y(core_ddr_dq_28_i), .OE(core_ddr_dq_28_sel), .PU(core_ddr_dq_28_sel)) ;
PADCELL_SIG_H u_ddr_dq_29_io (.PAD(p_ddr_dq_29_io), .A(core_ddr_dq_29_o), .Y(core_ddr_dq_29_i), .OE(core_ddr_dq_29_sel), .PU(core_ddr_dq_29_sel)) ;
PADCELL_SIG_H u_ddr_dq_2_io (.PAD(p_ddr_dq_2_io), .A(core_ddr_dq_2_o), .Y(core_ddr_dq_2_i), .OE(core_ddr_dq_2_sel), .PU(core_ddr_dq_2_sel)) ;
PADCELL_SIG_H u_ddr_dq_30_io (.PAD(p_ddr_dq_30_io), .A(core_ddr_dq_30_o), .Y(core_ddr_dq_30_i), .OE(core_ddr_dq_30_sel), .PU(core_ddr_dq_30_sel)) ;
PADCELL_SIG_H u_ddr_dq_31_io (.PAD(p_ddr_dq_31_io), .A(core_ddr_dq_31_o), .Y(core_ddr_dq_31_i), .OE(core_ddr_dq_31_sel), .PU(core_ddr_dq_31_sel)) ;
PADCELL_SIG_H u_ddr_dq_3_io (.PAD(p_ddr_dq_3_io), .A(core_ddr_dq_3_o), .Y(core_ddr_dq_3_i), .OE(core_ddr_dq_3_sel), .PU(core_ddr_dq_3_sel)) ;
PADCELL_SIG_H u_ddr_dq_4_io (.PAD(p_ddr_dq_4_io), .A(core_ddr_dq_4_o), .Y(core_ddr_dq_4_i), .OE(core_ddr_dq_4_sel), .PU(core_ddr_dq_4_sel)) ;
PADCELL_SIG_H u_ddr_dq_5_io (.PAD(p_ddr_dq_5_io), .A(core_ddr_dq_5_o), .Y(core_ddr_dq_5_i), .OE(core_ddr_dq_5_sel), .PU(core_ddr_dq_5_sel)) ;
PADCELL_SIG_H u_ddr_dq_6_io (.PAD(p_ddr_dq_6_io), .A(core_ddr_dq_6_o), .Y(core_ddr_dq_6_i), .OE(core_ddr_dq_6_sel), .PU(core_ddr_dq_6_sel)) ;
PADCELL_SIG_H u_ddr_dq_7_io (.PAD(p_ddr_dq_7_io), .A(core_ddr_dq_7_o), .Y(core_ddr_dq_7_i), .OE(core_ddr_dq_7_sel), .PU(core_ddr_dq_7_sel)) ;
PADCELL_SIG_H u_ddr_dq_8_io (.PAD(p_ddr_dq_8_io), .A(core_ddr_dq_8_o), .Y(core_ddr_dq_8_i), .OE(core_ddr_dq_8_sel), .PU(core_ddr_dq_8_sel)) ;
PADCELL_SIG_H u_ddr_dq_9_io (.PAD(p_ddr_dq_9_io), .A(core_ddr_dq_9_o), .Y(core_ddr_dq_9_i), .OE(core_ddr_dq_9_sel), .PU(core_ddr_dq_9_sel)) ;
PADCELL_SIG_H u_ddr_dqs_n_0_io (.PAD(p_ddr_dqs_n_0_io), .A(core_ddr_dqs_n_0_o), .Y(core_ddr_dqs_n_0_i), .OE(core_ddr_dqs_n_0_sel), .PU(core_ddr_dqs_n_0_sel)) ;
PADCELL_SIG_H u_ddr_dqs_n_3_io (.PAD(p_ddr_dqs_n_3_io), .A(core_ddr_dqs_n_3_o), .Y(core_ddr_dqs_n_3_i), .OE(core_ddr_dqs_n_3_sel), .PU(core_ddr_dqs_n_3_sel)) ;
PADCELL_SIG_H u_ddr_dqs_p_0_io (.PAD(p_ddr_dqs_p_0_io), .A(core_ddr_dqs_p_0_o), .Y(core_ddr_dqs_p_0_i), .OE(core_ddr_dqs_p_0_sel), .PU(core_ddr_dqs_p_0_sel)) ;
PADCELL_SIG_H u_ddr_dqs_p_3_io (.PAD(p_ddr_dqs_p_3_io), .A(core_ddr_dqs_p_3_o), .Y(core_ddr_dqs_p_3_i), .OE(core_ddr_dqs_p_3_sel), .PU(core_ddr_dqs_p_3_sel)) ;
// PADCELL_VDDIO_V u_v18_0 ();
PADCELL_VDDIO_V u_v18_1 ();
PADCELL_VDDIO_V u_v18_2 ();
PADCELL_VDDIO_V u_v18_3 ();
PADCELL_VDDIO_V u_v18_4 ();
PADCELL_VDDIO_V u_v18_5 ();
PADCELL_VDDIO_V u_v18_6 ();
PADCELL_VDDIO_V u_v18_7 ();
PADCELL_VDDIO_V u_v18_8 ();
PADCELL_VDDIO_V u_v18_17 ();
PADCELL_VDDIO_V u_v18_18 ();
PADCELL_VDDIO_V u_v18_19 ();
PADCELL_VDDIO_V u_v18_20 ();
PADCELL_VDDIO_V u_v18_21 ();
PADCELL_VDDIO_V u_v18_22 ();
PADCELL_VDDIO_V u_v18_23 ();
PADCELL_VDDIO_V u_v18_24 ();
// PADCELL_VDD_V u_vdd_0 ();
PADCELL_VDD_V u_vdd_1 ();
PADCELL_VDD_V u_vdd_2 ();
PADCELL_VDD_V u_vdd_3 ();
PADCELL_VDD_V u_vdd_4 ();
PADCELL_VDD_V u_vdd_5 ();
PADCELL_VDD_V u_vdd_6 ();
PADCELL_VDD_V u_vdd_7 ();
PADCELL_VDD_V u_vdd_pll ();
PADCELL_VDD_V u_vdd_17 ();
PADCELL_VDD_V u_vdd_18 ();
PADCELL_VDD_V u_vdd_19 ();
PADCELL_VDD_V u_vdd_20 ();
PADCELL_VDD_V u_vdd_21 ();
PADCELL_VDD_V u_vdd_22 ();
PADCELL_VDD_V u_vdd_23 ();
PADCELL_VDD_V u_vdd_24 ();
PADCELL_VSS_V u_vss_0 ();
PADCELL_VSS_V u_vss_1 ();
PADCELL_VSS_V u_vss_2 ();
PADCELL_VSS_V u_vss_3 ();
PADCELL_VSS_V u_vss_4 ();
PADCELL_VSS_V u_vss_5 ();
PADCELL_VSS_V u_vss_6 ();
PADCELL_VSS_V u_vss_7 ();
PADCELL_VSS_V u_vss_pll ();
PADCELL_VSS_V u_vss_17 ();
PADCELL_VSS_V u_vss_18 ();
PADCELL_VSS_V u_vss_19 ();
PADCELL_VSS_V u_vss_20 ();
PADCELL_VSS_V u_vss_21 ();
PADCELL_VSS_V u_vss_22 ();
PADCELL_VSS_V u_vss_23 ();
PADCELL_VSS_V u_vss_24 ();
PADCELL_VSSIO_V u_vzz_0 ();
PADCELL_VSSIO_V u_vzz_1 ();
PADCELL_VSSIO_V u_vzz_2 ();
PADCELL_VSSIO_V u_vzz_3 ();
PADCELL_VSSIO_V u_vzz_4 ();
PADCELL_VSSIO_V u_vzz_5 ();
PADCELL_VSSIO_V u_vzz_6 ();
PADCELL_VSSIO_V u_vzz_7 ();
PADCELL_VSSIO_V u_vzz_8 ();
PADCELL_VSSIO_V u_vzz_17 ();
PADCELL_VSSIO_V u_vzz_18 ();
PADCELL_VSSIO_V u_vzz_19 ();
PADCELL_VSSIO_V u_vzz_20 ();
PADCELL_VSSIO_V u_vzz_21 ();
PADCELL_VSSIO_V u_vzz_22 ();
PADCELL_VSSIO_V u_vzz_23 ();
PADCELL_VSSIO_V u_vzz_24 ();
PADCELL_VDDIO_H u_v18_25 ();
PADCELL_VDDIO_H u_v18_26 ();
PADCELL_VDDIO_H u_v18_27 ();
PADCELL_VDDIO_H u_v18_28 ();
PADCELL_VDDIO_H u_v18_29 ();
PADCELL_VDDIO_H u_v18_30 ();
PADCELL_VDDIO_H u_v18_31 ();
PADCELL_VDDIO_H u_v18_32 ();
PADCELL_VDDIO_H u_v18_9 ();
PADCELL_VDDIO_H u_v18_10 ();
PADCELL_VDDIO_H u_v18_11 ();
PADCELL_VDDIO_H u_v18_12 ();
PADCELL_VDDIO_H u_v18_13 ();
PADCELL_VDDIO_H u_v18_14 ();
PADCELL_VDDIO_H u_v18_15 ();
PADCELL_VDDIO_H u_v18_16 ();
PADCELL_VDD_H u_vdd_25 ();
PADCELL_VDD_H u_vdd_26 ();
PADCELL_VDD_H u_vdd_27 ();
PADCELL_VDD_H u_vdd_28 ();
PADCELL_VDD_H u_vdd_29 ();
PADCELL_VDD_H u_vdd_30 ();
PADCELL_VDD_H u_vdd_31 ();
PADCELL_VDD_H u_vdd_32 ();
PADCELL_VDD_H u_vdd_8 ();
PADCELL_VDD_H u_vdd_9 ();
PADCELL_VDD_H u_vdd_10 ();
PADCELL_VDD_H u_vdd_11 ();
PADCELL_VDD_H u_vdd_12 ();
PADCELL_VDD_H u_vdd_13 ();
PADCELL_VDD_H u_vdd_14 ();
PADCELL_VDD_H u_vdd_15 ();
PADCELL_VDD_H u_vdd_16 ();
PADCELL_VSS_H u_vss_25 ();
PADCELL_VSS_H u_vss_26 ();
PADCELL_VSS_H u_vss_27 ();
PADCELL_VSS_H u_vss_28 ();
PADCELL_VSS_H u_vss_29 ();
PADCELL_VSS_H u_vss_30 ();
PADCELL_VSS_H u_vss_31 ();
PADCELL_VSS_H u_vss_32 ();
PADCELL_VSS_H u_vss_8 ();
PADCELL_VSS_H u_vss_9 ();
PADCELL_VSS_H u_vss_10 ();
PADCELL_VSS_H u_vss_11 ();
PADCELL_VSS_H u_vss_12 ();
PADCELL_VSS_H u_vss_13 ();
PADCELL_VSS_H u_vss_14 ();
PADCELL_VSS_H u_vss_15 ();
PADCELL_VSS_H u_vss_16 ();
PADCELL_VSSIO_H u_vzz_25 ();
PADCELL_VSSIO_H u_vzz_26 ();
PADCELL_VSSIO_H u_vzz_27 ();
PADCELL_VSSIO_H u_vzz_28 ();
PADCELL_VSSIO_H u_vzz_29 ();
PADCELL_VSSIO_H u_vzz_30 ();
PADCELL_VSSIO_H u_vzz_31 ();
PADCELL_VSSIO_H u_vzz_32 ();
PADCELL_VSSIO_H u_vzz_9 ();
PADCELL_VSSIO_H u_vzz_10 ();
PADCELL_VSSIO_H u_vzz_11 ();
PADCELL_VSSIO_H u_vzz_12 ();
PADCELL_VSSIO_H u_vzz_13 ();
PADCELL_VSSIO_H u_vzz_14 ();
PADCELL_VSSIO_H u_vzz_15 ();
PADCELL_VSSIO_H u_vzz_16 ();
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninja_life.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ninja_life (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/ninja_life.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/ninja_life.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* File: pippo_alu.v
* Project: pippo
* Designer: fang@ali
* Mainteiner: fang@ali
* Checker:
* Assigner:
* Description:
Ò»£¬¹¦ÄÜÃèÊö
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b£©ALU²¿¼þ³ýµÃµ½»ù±¾½á¹û¸üÐÂÄ¿±ê¼Ä´æÆ÷Í⣬¸ù¾ÝÖ¸ÁîÀàÐÍ£¬»¹½«¸üÐÂCRºÍXER¼Ä´æÆ÷¡£·ÖΪÒÔÏÂËÄÖÖÇé¿ö£º
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2£¬[o]¸ñʽµÄËãÊõºÍÂß¼ÔËËãÖ¸Áѻ·ÒÆλָÁ±íʾ½«¸ù¾ÝÔËËã½á¹û¸üÐÂXER[SO, OV]
3£¬´øCarryingµÄÖ¸Á±íʾ½«¸ù¾ÝÔËËã½á¹û¸üÐÂXER[CA]
* Task:
* [TBO]ʹÓüĴæÆ÷µÄena£¬ÒÔ½µµÍ¹¦ºÄ
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module pippo_alu(
clk, rst,
alu_uops, bus_a, bus_b,
sh_mb_me,
result
);
parameter width = `OPERAND_WIDTH;
//
input clk;
input rst;
input [`ALUUOPS_WIDTH-1:0] alu_uops;
input [width-1:0] bus_a;
input [width-1:0] bus_b;
input reg_zero;
input [14:0] sh_mb_me;
output [width-1:0] result;
// global wires in module
wire [width-1:0] bus_a;
wire [width-1:0] bus_b;
//
// Logic
//
wire [`ALUOP_WIDTH-1:0] alu_op;
assign alu_op = alu_uops[`ALUOP_WIDTH-1:0];
//
// barrel shifter
//
wire [5:0] shrot_cnt;
wire shift_arith;
wire shift_left;
wire shift_mode_32b
// shrot operands
assign shrot_cnt = alu_op[`ALUOP_SHTEN_BIT] ? bus_b[5:0] : 6'b0;
// control signals
assign shift_mode_32b = alu_op[`ALUOP_M32B_BIT];
assign shift_left = alu_op[`ALUOP_LFT_BIT];
assign shift_arith = alu_op[`ALUOP_AGM_BIT];
// shifted result
wire [width-1:0] shrot_result;
pippo_barrel pippo_barrel (
.shift_in(bus_a),
.shift_cnt(shrot_cnt),
.shift_left(shift_left),
.shift_arith(shift_arith),
.shift_mode_32b(shift_mode_32b),
.shrot_out(shrot_result)
);
//
// multiplier for 32x32
//
//wire [63:0] mul_out, mul_out_a;
//reg [31:0] mul_result;
//wire [31:0] bus_a_u;
//wire [31:0] bus_b_u;
//wire [31:0] opa;
//wire [31:0] opb;
//assign tag_unsigned = (alu_op == `ALUOP_MULHWU);
//assign mul_sign = bus_a[31] ^ bus_b[31];
//assign bus_a_u = bus_a[31] ? (~bus_a + 32'd1) : bus_a;
//assign bus_b_u = bus_b[31] ? (~bus_b + 32'd1) : bus_b;
//assign opa = tag_unsigned ? bus_a : {1'b0, bus_a_u[30:0]};
//assign opb = tag_unsigned ? bus_b : {1'b0, bus_b_u[30:0]};
// unsigned multiplier
//pippo_mul32x32 pippo_mul32x32 (
// .clk(clk),
// .rst(rst),
// .opa(opa),
// .opb(opb),
// .result(mul_out_a)
//);
// adjust the sign bit of result
// 1, if unsigned instruction, nothing to do
// 2, if positive mulitply negative, transfer the absolute result to negative value
// Notes: it doesn't matter for the last case: actually it's a 31*31 multiplication
//assign mul_out = tag_unsigned ? mul_out_a[63:0] : (mul_sign ? (~mul_out_a + 1'd1): {1'b0, mul_out_a[62:0]});
//assign mul_out = tag_unsigned ? mul_out_a[63:0] : (mul_sign ? (~mul_out_a + 1'd1): mul_out_a[63:0]);
//always @(alu_op or mul_out or mul_sign) begin
// mul_result=32'd0;
// casex (alu_op) // synopsys parallel_case
// `ALUOP_MULHWU: begin
// mul_result = mul_out[63:32];
// end
// `ALUOP_MULHW: begin
// mul_result = mul_out[31:0];
// end
// `ALUOP_MULLI: begin
// mul_result = mul_out[31:0];
// end
// `ALUOP_MULLW: begin
// mul_result = mul_out[31:0];
// end
// default: begin
// mul_result = mul_out[31:0];
// end
// endcase
//end
//
// hardware divider
//
//`ifdef pippo_DIV_IMPLEMENTED
//module pippo_div64x32 (
// clk(),
// ena(),
// z(),
// d(),
// q(),
// s(),
// ovf(),
// div0()
//);
//`endif
//
// ALU
//
reg [width-1:0] result;
wire [width-1:0] cmp_a, cmp_b;
assign cmp_a = {bus_a[width-1] ^ alu_uops[`ALUOP_SCMP_BIT], bus_a[width-2:0]};
assign cmp_b = {bus_b[width-1] ^ alu_uops[`ALUOP_SCMP_BIT], bus_b[width-2:0]};
always @(alu_op or bus_a or bus_b or cmp_a or cmp_b or shrot_result ) begin
result = 64'd0;
casex (alu_op) // synopsys parallel_case
// arithmetic
`ALUOP_ADD : begin
result = bus_a + bus_b;
end
`ALUOP_SUB : begin
result = bus_b - bus_a;
end
// logic
`ALUOP_AND : begin
result = bus_a & bus_b;
end
`ALUOP_OR : begin
result = bus_a | bus_b;
end
`ALUOP_XOR : begin
result = bus_a ^ bus_b;
end
`ALUOP_SLT, `ALUOP_SLTU: begin
result = (cmp_a < cmp_b);
end
// barrel shifter
`ALUOP_SLL, `ALUOP_SRL, `ALUOP_SRA,
`ALUOP_SLLW, `ALUOP_SRLW, `ALUOP_SRAW: begin
result = shrot_result;
end
// multiplier
// `ifdef pippo_MULT_IMPLEMENTED
// `ALUOP_MULHWU, `ALUOP_MULHW, `ALUOP_MULLI, `ALUOP_MULLW: begin
// result = mul_result;
// end
// `endif
endcase
end
//
// Simulation check for bad ALU behavior
//
`ifdef pippo_WARNINGS
// synopsys translate_off
always @(result) begin
if (result === 32'bx)
$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_REFGEN_NEW_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_REFGEN_NEW_PP_SYMBOL_V
/**
* top_refgen_new: The REFGEN block (sky130_fd_io__top_refgen) is used
* to provide the input trip point (VINREF) for the
* differential input buffer in SIO and also
* the output buffer regulated output level (VOUTREF).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_refgen_new (
//# {{data|Data Signals}}
input DFT_REFGEN ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input ENABLE_H ,
input ENABLE_VDDA_H,
input HLD_H_N ,
input IBUF_SEL ,
//# {{power|Power}}
input [2:0] VOH_SEL ,
input [1:0] VREF_SEL ,
input VREG_EN ,
input VTRIP_SEL ,
inout VSWITCH ,
inout REFLEAK_BIAS ,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
output VINREF ,
inout VINREF_DFT ,
input VOHREF ,
output VOUTREF ,
inout VOUTREF_DFT ,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_REFGEN_NEW_PP_SYMBOL_V
|
// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.1.0.96
// Netlist written on Wed May 07 14:52:57 2014
//
// Verilog Description of module section3_schematic
//
module section3_schematic (A, B, C, D, LED, SegA, SegB, SegC,
SegD, SegE, SegF, SegG) /* synthesis syn_module_defined=1 */ ; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(3[8:26])
input A; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(5[8:9])
input B; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(6[8:9])
input C; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(7[8:9])
input D; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(8[8:9])
output LED; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(9[8:11])
output SegA; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(10[8:12])
output SegB; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(11[8:12])
output SegC; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(12[8:12])
output SegD; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(13[8:12])
output SegE; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(14[8:12])
output SegF; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(15[8:12])
output SegG; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(16[8:12])
wire A_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(5[8:9])
wire B_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(6[8:9])
wire C_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(7[8:9])
wire D_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(8[8:9])
wire LED_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(9[8:11])
wire SegA_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(10[8:12])
wire SegB_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(11[8:12])
wire SegC_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(12[8:12])
wire SegD_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(13[8:12])
wire SegE_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(14[8:12])
wire SegF_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(15[8:12])
wire SegG_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(16[8:12])
wire N_44; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(17[6:10])
wire N_45; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(18[6:10])
wire N_46; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(19[6:10])
wire N_42; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(20[6:10])
wire N_43; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(21[6:10])
wire N_35; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(22[6:10])
wire N_39; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(23[6:10])
wire N_28; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(24[6:10])
wire N_29; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(25[6:10])
wire N_30; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(26[6:10])
wire N_16; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(27[6:10])
wire N_17; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(28[6:10])
wire N_18; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(29[6:10])
wire N_19; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(30[6:10])
wire N_20; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(31[6:10])
wire N_21; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(32[6:10])
wire N_22; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(33[6:10])
wire N_23; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(34[6:10])
wire N_24; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(35[6:10])
wire N_25; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(36[6:10])
wire N_26; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(37[6:10])
wire N_1; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(38[6:9])
wire N_2; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(39[6:9])
wire N_3; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(40[6:9])
wire N_8; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(41[6:9])
wire N_9; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(42[6:9])
wire N_10; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(43[6:10])
wire N_11; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(44[6:10])
wire N_12; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(45[6:10])
wire N_13; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(46[6:10])
wire N_14; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(47[6:10])
wire N_15; // c:/lscc/diamond/3.1_x64/bin/nt64/lab3_7segdisplaydriver/section3/section3_schematic.v(48[6:10])
wire GND_net, VCC_net;
IB A_pad (.I(A), .O(A_c));
OR3 I24 (.A(N_22), .B(N_20), .C(N_21), .Z(SegE_c)) /* synthesis syn_instantiated=1 */ ;
OR3 I18 (.A(N_3), .B(N_1), .C(N_2), .Z(SegC_c)) /* synthesis syn_instantiated=1 */ ;
AND3 I33 (.A(N_45), .B(N_42), .C(N_44), .Z(N_28)) /* synthesis syn_instantiated=1 */ ;
AND3 I25 (.A(N_45), .B(N_42), .C(N_46), .Z(N_18)) /* synthesis syn_instantiated=1 */ ;
AND3 I26 (.A(N_45), .B(N_46), .C(N_35), .Z(N_17)) /* synthesis syn_instantiated=1 */ ;
AND3 I27 (.A(N_45), .B(N_42), .C(N_35), .Z(N_16)) /* synthesis syn_instantiated=1 */ ;
AND3 I28 (.A(N_42), .B(N_44), .C(N_35), .Z(N_20)) /* synthesis syn_instantiated=1 */ ;
AND3 I29 (.A(N_45), .B(N_43), .C(N_44), .Z(N_22)) /* synthesis syn_instantiated=1 */ ;
AND3 I19 (.A(N_43), .B(N_46), .C(N_35), .Z(N_25)) /* synthesis syn_instantiated=1 */ ;
AND3 I5 (.A(N_43), .B(N_46), .C(LED_c), .Z(N_10)) /* synthesis syn_instantiated=1 */ ;
AND3 I4 (.A(N_39), .B(N_43), .C(LED_c), .Z(N_11)) /* synthesis syn_instantiated=1 */ ;
AND3 I3 (.A(N_39), .B(N_46), .C(N_35), .Z(N_15)) /* synthesis syn_instantiated=1 */ ;
AND3 I2 (.A(N_39), .B(N_43), .C(LED_c), .Z(N_1)) /* synthesis syn_instantiated=1 */ ;
AND3 I1 (.A(N_39), .B(N_43), .C(N_46), .Z(N_2)) /* synthesis syn_instantiated=1 */ ;
OR4 I30 (.A(N_19), .B(N_16), .C(N_17), .D(N_18), .Z(SegF_c)) /* synthesis syn_instantiated=1 */ ;
OR4 I31 (.A(N_26), .B(N_23), .C(N_24), .D(N_25), .Z(SegD_c)) /* synthesis syn_instantiated=1 */ ;
OR4 I7 (.A(N_12), .B(N_8), .C(N_9), .D(N_13), .Z(SegA_c)) /* synthesis syn_instantiated=1 */ ;
OR4 I6 (.A(N_14), .B(N_10), .C(N_11), .D(N_15), .Z(SegB_c)) /* synthesis syn_instantiated=1 */ ;
AND4 I35 (.A(N_45), .B(N_43), .C(N_46), .D(N_35), .Z(N_29)) /* synthesis syn_instantiated=1 */ ;
AND4 I34 (.A(N_39), .B(N_43), .C(N_44), .D(LED_c), .Z(N_30)) /* synthesis syn_instantiated=1 */ ;
AND4 I32 (.A(N_39), .B(N_43), .C(N_44), .D(N_35), .Z(N_19)) /* synthesis syn_instantiated=1 */ ;
AND4 I22 (.A(N_45), .B(N_43), .C(N_44), .D(LED_c), .Z(N_26)) /* synthesis syn_instantiated=1 */ ;
AND4 I20 (.A(N_39), .B(N_42), .C(N_46), .D(LED_c), .Z(N_24)) /* synthesis syn_instantiated=1 */ ;
AND4 I21 (.A(N_45), .B(N_42), .C(N_44), .D(N_35), .Z(N_23)) /* synthesis syn_instantiated=1 */ ;
AND4 I13 (.A(N_45), .B(N_42), .C(N_44), .D(N_35), .Z(N_12)) /* synthesis syn_instantiated=1 */ ;
AND4 I12 (.A(N_45), .B(N_43), .C(N_44), .D(LED_c), .Z(N_8)) /* synthesis syn_instantiated=1 */ ;
AND4 I11 (.A(N_39), .B(N_43), .C(N_44), .D(N_35), .Z(N_9)) /* synthesis syn_instantiated=1 */ ;
AND4 I10 (.A(N_39), .B(N_42), .C(N_46), .D(N_35), .Z(N_13)) /* synthesis syn_instantiated=1 */ ;
AND4 I9 (.A(N_45), .B(N_43), .C(N_44), .D(N_35), .Z(N_14)) /* synthesis syn_instantiated=1 */ ;
AND4 I8 (.A(N_45), .B(N_42), .C(N_46), .D(LED_c), .Z(N_3)) /* synthesis syn_instantiated=1 */ ;
INV I15 (.A(N_46), .Z(N_44));
OB SegG_pad (.I(SegG_c), .O(SegG));
OB SegF_pad (.I(SegF_c), .O(SegF));
OB SegE_pad (.I(SegE_c), .O(SegE));
OB SegD_pad (.I(SegD_c), .O(SegD));
OB SegC_pad (.I(SegC_c), .O(SegC));
OB SegB_pad (.I(SegB_c), .O(SegB));
OB SegA_pad (.I(SegA_c), .O(SegA));
OB LED_pad (.I(LED_c), .O(LED));
VLO i29 (.Z(GND_net));
AND2 I23 (.A(N_45), .B(N_35), .Z(N_21)) /* synthesis syn_instantiated=1 */ ;
OR3 I36 (.A(N_29), .B(N_30), .C(N_28), .Z(SegG_c)) /* synthesis syn_instantiated=1 */ ;
INV I16 (.A(N_43), .Z(N_42));
INV I37 (.A(D_c), .Z(N_35));
INV I38 (.A(C_c), .Z(N_46));
INV I39 (.A(B_c), .Z(N_43));
INV I40 (.A(A_c), .Z(N_39));
INV I17 (.A(N_39), .Z(N_45));
INV I14 (.A(N_35), .Z(LED_c));
IB B_pad (.I(B), .O(B_c));
IB C_pad (.I(C), .O(C_c));
IB D_pad (.I(D), .O(D_c));
GSR GSR_INST (.GSR(VCC_net));
PUR PUR_INST (.PUR(VCC_net));
defparam PUR_INST.RST_PULSE = 1;
VHI i30 (.Z(VCC_net));
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box.
//
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